1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(true),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 static cl::opt<int> ReciprocalEstimateRefinementSteps(
75 "x86-recip-refinement-steps", cl::init(1),
76 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
77 "result of the hardware reciprocal estimate instruction."),
80 // Forward declarations.
81 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
84 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
85 SelectionDAG &DAG, SDLoc dl,
86 unsigned vectorWidth) {
87 assert((vectorWidth == 128 || vectorWidth == 256) &&
88 "Unsupported vector width");
89 EVT VT = Vec.getValueType();
90 EVT ElVT = VT.getVectorElementType();
91 unsigned Factor = VT.getSizeInBits()/vectorWidth;
92 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
93 VT.getVectorNumElements()/Factor);
95 // Extract from UNDEF is UNDEF.
96 if (Vec.getOpcode() == ISD::UNDEF)
97 return DAG.getUNDEF(ResultVT);
99 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
100 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
102 // This is the index of the first element of the vectorWidth-bit chunk
104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
107 // If the input is a buildvector just emit a smaller one.
108 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
109 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
110 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
113 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
114 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
117 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
118 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
119 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
120 /// instructions or a simple subregister reference. Idx is an index in the
121 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
122 /// lowering EXTRACT_VECTOR_ELT operations easier.
123 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
124 SelectionDAG &DAG, SDLoc dl) {
125 assert((Vec.getValueType().is256BitVector() ||
126 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
127 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
130 /// Generate a DAG to grab 256-bits from a 512-bit vector.
131 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
132 SelectionDAG &DAG, SDLoc dl) {
133 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
134 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
137 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
138 unsigned IdxVal, SelectionDAG &DAG,
139 SDLoc dl, unsigned vectorWidth) {
140 assert((vectorWidth == 128 || vectorWidth == 256) &&
141 "Unsupported vector width");
142 // Inserting UNDEF is Result
143 if (Vec.getOpcode() == ISD::UNDEF)
145 EVT VT = Vec.getValueType();
146 EVT ElVT = VT.getVectorElementType();
147 EVT ResultVT = Result.getValueType();
149 // Insert the relevant vectorWidth bits.
150 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
152 // This is the index of the first element of the vectorWidth-bit chunk
154 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
157 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
158 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
161 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
162 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
163 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
164 /// simple superregister reference. Idx is an index in the 128 bits
165 /// we want. It need not be aligned to a 128-bit boundary. That makes
166 /// lowering INSERT_VECTOR_ELT operations easier.
167 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
168 SelectionDAG &DAG,SDLoc dl) {
169 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
170 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
173 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
174 SelectionDAG &DAG, SDLoc dl) {
175 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
176 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
179 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
180 /// instructions. This is used because creating CONCAT_VECTOR nodes of
181 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
182 /// large BUILD_VECTORS.
183 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
184 unsigned NumElems, SelectionDAG &DAG,
186 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
187 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
190 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
191 unsigned NumElems, SelectionDAG &DAG,
193 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
194 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
197 // FIXME: This should stop caching the target machine as soon as
198 // we can remove resetOperationActions et al.
199 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
200 : TargetLowering(TM) {
201 Subtarget = &TM.getSubtarget<X86Subtarget>();
202 X86ScalarSSEf64 = Subtarget->hasSSE2();
203 X86ScalarSSEf32 = Subtarget->hasSSE1();
204 TD = getDataLayout();
206 resetOperationActions();
209 void X86TargetLowering::resetOperationActions() {
210 const TargetMachine &TM = getTargetMachine();
211 static bool FirstTimeThrough = true;
213 // If none of the target options have changed, then we don't need to reset the
214 // operation actions.
215 if (!FirstTimeThrough && TO == TM.Options) return;
217 if (!FirstTimeThrough) {
218 // Reinitialize the actions.
220 FirstTimeThrough = false;
225 // Set up the TargetLowering object.
226 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
228 // X86 is weird. It always uses i8 for shift amounts and setcc results.
229 setBooleanContents(ZeroOrOneBooleanContent);
230 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
231 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
233 // For 64-bit, since we have so many registers, use the ILP scheduler.
234 // For 32-bit, use the register pressure specific scheduling.
235 // For Atom, always use ILP scheduling.
236 if (Subtarget->isAtom())
237 setSchedulingPreference(Sched::ILP);
238 else if (Subtarget->is64Bit())
239 setSchedulingPreference(Sched::ILP);
241 setSchedulingPreference(Sched::RegPressure);
242 const X86RegisterInfo *RegInfo =
243 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
244 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
246 // Bypass expensive divides on Atom when compiling with O2.
247 if (TM.getOptLevel() >= CodeGenOpt::Default) {
248 if (Subtarget->hasSlowDivide32())
249 addBypassSlowDiv(32, 8);
250 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
251 addBypassSlowDiv(64, 16);
254 if (Subtarget->isTargetKnownWindowsMSVC()) {
255 // Setup Windows compiler runtime calls.
256 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
257 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
258 setLibcallName(RTLIB::SREM_I64, "_allrem");
259 setLibcallName(RTLIB::UREM_I64, "_aullrem");
260 setLibcallName(RTLIB::MUL_I64, "_allmul");
261 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
262 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
263 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
264 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
265 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
267 // The _ftol2 runtime function has an unusual calling conv, which
268 // is modeled by a special pseudo-instruction.
269 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
270 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
271 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
272 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
275 if (Subtarget->isTargetDarwin()) {
276 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
277 setUseUnderscoreSetJmp(false);
278 setUseUnderscoreLongJmp(false);
279 } else if (Subtarget->isTargetWindowsGNU()) {
280 // MS runtime is weird: it exports _setjmp, but longjmp!
281 setUseUnderscoreSetJmp(true);
282 setUseUnderscoreLongJmp(false);
284 setUseUnderscoreSetJmp(true);
285 setUseUnderscoreLongJmp(true);
288 // Set up the register classes.
289 addRegisterClass(MVT::i8, &X86::GR8RegClass);
290 addRegisterClass(MVT::i16, &X86::GR16RegClass);
291 addRegisterClass(MVT::i32, &X86::GR32RegClass);
292 if (Subtarget->is64Bit())
293 addRegisterClass(MVT::i64, &X86::GR64RegClass);
295 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
297 // We don't accept any truncstore of integer registers.
298 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
299 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
300 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
301 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
302 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
303 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
305 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
307 // SETOEQ and SETUNE require checking two conditions.
308 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
309 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
310 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
311 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
312 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
313 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
315 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
317 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
318 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
319 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
321 if (Subtarget->is64Bit()) {
322 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
323 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
324 } else if (!TM.Options.UseSoftFloat) {
325 // We have an algorithm for SSE2->double, and we turn this into a
326 // 64-bit FILD followed by conditional FADD for other targets.
327 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
328 // We have an algorithm for SSE2, and we turn this into a 64-bit
329 // FILD for other targets.
330 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
333 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
335 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
336 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
338 if (!TM.Options.UseSoftFloat) {
339 // SSE has no i16 to fp conversion, only i32
340 if (X86ScalarSSEf32) {
341 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
342 // f32 and f64 cases are Legal, f80 case is not
343 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
345 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
346 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
349 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
350 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
353 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
354 // are Legal, f80 is custom lowered.
355 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
356 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
358 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
360 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
361 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
363 if (X86ScalarSSEf32) {
364 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
365 // f32 and f64 cases are Legal, f80 case is not
366 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
368 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
369 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
372 // Handle FP_TO_UINT by promoting the destination to a larger signed
374 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
375 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
376 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
378 if (Subtarget->is64Bit()) {
379 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
380 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
381 } else if (!TM.Options.UseSoftFloat) {
382 // Since AVX is a superset of SSE3, only check for SSE here.
383 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
384 // Expand FP_TO_UINT into a select.
385 // FIXME: We would like to use a Custom expander here eventually to do
386 // the optimal thing for SSE vs. the default expansion in the legalizer.
387 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
389 // With SSE3 we can use fisttpll to convert to a signed i64; without
390 // SSE, we're stuck with a fistpll.
391 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
394 if (isTargetFTOL()) {
395 // Use the _ftol2 runtime function, which has a pseudo-instruction
396 // to handle its weird calling convention.
397 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
400 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
401 if (!X86ScalarSSEf64) {
402 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
403 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
404 if (Subtarget->is64Bit()) {
405 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
406 // Without SSE, i64->f64 goes through memory.
407 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
411 // Scalar integer divide and remainder are lowered to use operations that
412 // produce two results, to match the available instructions. This exposes
413 // the two-result form to trivial CSE, which is able to combine x/y and x%y
414 // into a single instruction.
416 // Scalar integer multiply-high is also lowered to use two-result
417 // operations, to match the available instructions. However, plain multiply
418 // (low) operations are left as Legal, as there are single-result
419 // instructions for this in x86. Using the two-result multiply instructions
420 // when both high and low results are needed must be arranged by dagcombine.
421 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
423 setOperationAction(ISD::MULHS, VT, Expand);
424 setOperationAction(ISD::MULHU, VT, Expand);
425 setOperationAction(ISD::SDIV, VT, Expand);
426 setOperationAction(ISD::UDIV, VT, Expand);
427 setOperationAction(ISD::SREM, VT, Expand);
428 setOperationAction(ISD::UREM, VT, Expand);
430 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
431 setOperationAction(ISD::ADDC, VT, Custom);
432 setOperationAction(ISD::ADDE, VT, Custom);
433 setOperationAction(ISD::SUBC, VT, Custom);
434 setOperationAction(ISD::SUBE, VT, Custom);
437 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
438 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
439 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
440 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
441 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
442 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
443 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
444 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
445 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
446 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
447 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
448 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
449 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
450 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
451 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
452 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
453 if (Subtarget->is64Bit())
454 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
455 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
456 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
457 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
458 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
459 setOperationAction(ISD::FREM , MVT::f32 , Expand);
460 setOperationAction(ISD::FREM , MVT::f64 , Expand);
461 setOperationAction(ISD::FREM , MVT::f80 , Expand);
462 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
464 // Promote the i8 variants and force them on up to i32 which has a shorter
466 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
467 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
468 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
469 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
470 if (Subtarget->hasBMI()) {
471 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
472 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
473 if (Subtarget->is64Bit())
474 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
476 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
477 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
478 if (Subtarget->is64Bit())
479 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
482 if (Subtarget->hasLZCNT()) {
483 // When promoting the i8 variants, force them to i32 for a shorter
485 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
486 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
487 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
488 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
489 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
490 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
491 if (Subtarget->is64Bit())
492 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
494 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
495 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
496 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
497 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
498 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
499 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
500 if (Subtarget->is64Bit()) {
501 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
502 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
506 // Special handling for half-precision floating point conversions.
507 // If we don't have F16C support, then lower half float conversions
508 // into library calls.
509 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
510 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
511 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
514 // There's never any support for operations beyond MVT::f32.
515 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
516 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
517 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
518 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
520 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
521 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
522 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
523 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
525 if (Subtarget->hasPOPCNT()) {
526 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
528 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
529 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
530 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
531 if (Subtarget->is64Bit())
532 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
535 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
537 if (!Subtarget->hasMOVBE())
538 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
540 // These should be promoted to a larger select which is supported.
541 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
542 // X86 wants to expand cmov itself.
543 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
544 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
545 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
546 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
547 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
548 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
549 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
550 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
551 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
552 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
553 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
554 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
555 if (Subtarget->is64Bit()) {
556 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
557 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
559 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
560 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
561 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
562 // support continuation, user-level threading, and etc.. As a result, no
563 // other SjLj exception interfaces are implemented and please don't build
564 // your own exception handling based on them.
565 // LLVM/Clang supports zero-cost DWARF exception handling.
566 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
567 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
570 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
571 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
572 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
573 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
574 if (Subtarget->is64Bit())
575 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
576 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
577 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
578 if (Subtarget->is64Bit()) {
579 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
580 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
581 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
582 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
583 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
585 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
586 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
587 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
588 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
589 if (Subtarget->is64Bit()) {
590 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
591 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
592 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
595 if (Subtarget->hasSSE1())
596 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
598 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
600 // Expand certain atomics
601 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
603 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
604 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
605 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
608 if (Subtarget->hasCmpxchg16b()) {
609 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
612 // FIXME - use subtarget debug flags
613 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
614 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
615 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
618 if (Subtarget->is64Bit()) {
619 setExceptionPointerRegister(X86::RAX);
620 setExceptionSelectorRegister(X86::RDX);
622 setExceptionPointerRegister(X86::EAX);
623 setExceptionSelectorRegister(X86::EDX);
625 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
626 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
628 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
629 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
631 setOperationAction(ISD::TRAP, MVT::Other, Legal);
632 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
634 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
635 setOperationAction(ISD::VASTART , MVT::Other, Custom);
636 setOperationAction(ISD::VAEND , MVT::Other, Expand);
637 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
638 // TargetInfo::X86_64ABIBuiltinVaList
639 setOperationAction(ISD::VAARG , MVT::Other, Custom);
640 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
642 // TargetInfo::CharPtrBuiltinVaList
643 setOperationAction(ISD::VAARG , MVT::Other, Expand);
644 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
647 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
648 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
650 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
652 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
653 // f32 and f64 use SSE.
654 // Set up the FP register classes.
655 addRegisterClass(MVT::f32, &X86::FR32RegClass);
656 addRegisterClass(MVT::f64, &X86::FR64RegClass);
658 // Use ANDPD to simulate FABS.
659 setOperationAction(ISD::FABS , MVT::f64, Custom);
660 setOperationAction(ISD::FABS , MVT::f32, Custom);
662 // Use XORP to simulate FNEG.
663 setOperationAction(ISD::FNEG , MVT::f64, Custom);
664 setOperationAction(ISD::FNEG , MVT::f32, Custom);
666 // Use ANDPD and ORPD to simulate FCOPYSIGN.
667 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
668 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
670 // Lower this to FGETSIGNx86 plus an AND.
671 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
672 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
674 // We don't support sin/cos/fmod
675 setOperationAction(ISD::FSIN , MVT::f64, Expand);
676 setOperationAction(ISD::FCOS , MVT::f64, Expand);
677 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
678 setOperationAction(ISD::FSIN , MVT::f32, Expand);
679 setOperationAction(ISD::FCOS , MVT::f32, Expand);
680 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
682 // Expand FP immediates into loads from the stack, except for the special
684 addLegalFPImmediate(APFloat(+0.0)); // xorpd
685 addLegalFPImmediate(APFloat(+0.0f)); // xorps
686 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
687 // Use SSE for f32, x87 for f64.
688 // Set up the FP register classes.
689 addRegisterClass(MVT::f32, &X86::FR32RegClass);
690 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
692 // Use ANDPS to simulate FABS.
693 setOperationAction(ISD::FABS , MVT::f32, Custom);
695 // Use XORP to simulate FNEG.
696 setOperationAction(ISD::FNEG , MVT::f32, Custom);
698 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
700 // Use ANDPS and ORPS to simulate FCOPYSIGN.
701 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
702 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
704 // We don't support sin/cos/fmod
705 setOperationAction(ISD::FSIN , MVT::f32, Expand);
706 setOperationAction(ISD::FCOS , MVT::f32, Expand);
707 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
709 // Special cases we handle for FP constants.
710 addLegalFPImmediate(APFloat(+0.0f)); // xorps
711 addLegalFPImmediate(APFloat(+0.0)); // FLD0
712 addLegalFPImmediate(APFloat(+1.0)); // FLD1
713 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
714 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
716 if (!TM.Options.UnsafeFPMath) {
717 setOperationAction(ISD::FSIN , MVT::f64, Expand);
718 setOperationAction(ISD::FCOS , MVT::f64, Expand);
719 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
721 } else if (!TM.Options.UseSoftFloat) {
722 // f32 and f64 in x87.
723 // Set up the FP register classes.
724 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
725 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
727 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
728 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
729 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
730 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
732 if (!TM.Options.UnsafeFPMath) {
733 setOperationAction(ISD::FSIN , MVT::f64, Expand);
734 setOperationAction(ISD::FSIN , MVT::f32, Expand);
735 setOperationAction(ISD::FCOS , MVT::f64, Expand);
736 setOperationAction(ISD::FCOS , MVT::f32, Expand);
737 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
738 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
740 addLegalFPImmediate(APFloat(+0.0)); // FLD0
741 addLegalFPImmediate(APFloat(+1.0)); // FLD1
742 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
743 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
744 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
745 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
746 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
747 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
750 // We don't support FMA.
751 setOperationAction(ISD::FMA, MVT::f64, Expand);
752 setOperationAction(ISD::FMA, MVT::f32, Expand);
754 // Long double always uses X87.
755 if (!TM.Options.UseSoftFloat) {
756 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
757 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
758 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
760 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
761 addLegalFPImmediate(TmpFlt); // FLD0
763 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
766 APFloat TmpFlt2(+1.0);
767 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
769 addLegalFPImmediate(TmpFlt2); // FLD1
770 TmpFlt2.changeSign();
771 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
774 if (!TM.Options.UnsafeFPMath) {
775 setOperationAction(ISD::FSIN , MVT::f80, Expand);
776 setOperationAction(ISD::FCOS , MVT::f80, Expand);
777 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
780 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
781 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
782 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
783 setOperationAction(ISD::FRINT, MVT::f80, Expand);
784 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
785 setOperationAction(ISD::FMA, MVT::f80, Expand);
788 // Always use a library call for pow.
789 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
790 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
791 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
793 setOperationAction(ISD::FLOG, MVT::f80, Expand);
794 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
795 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
796 setOperationAction(ISD::FEXP, MVT::f80, Expand);
797 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
798 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
799 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
801 // First set operation action for all vector types to either promote
802 // (for widening) or expand (for scalarization). Then we will selectively
803 // turn on ones that can be effectively codegen'd.
804 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
805 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
806 MVT VT = (MVT::SimpleValueType)i;
807 setOperationAction(ISD::ADD , VT, Expand);
808 setOperationAction(ISD::SUB , VT, Expand);
809 setOperationAction(ISD::FADD, VT, Expand);
810 setOperationAction(ISD::FNEG, VT, Expand);
811 setOperationAction(ISD::FSUB, VT, Expand);
812 setOperationAction(ISD::MUL , VT, Expand);
813 setOperationAction(ISD::FMUL, VT, Expand);
814 setOperationAction(ISD::SDIV, VT, Expand);
815 setOperationAction(ISD::UDIV, VT, Expand);
816 setOperationAction(ISD::FDIV, VT, Expand);
817 setOperationAction(ISD::SREM, VT, Expand);
818 setOperationAction(ISD::UREM, VT, Expand);
819 setOperationAction(ISD::LOAD, VT, Expand);
820 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
821 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
822 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
823 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
824 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
825 setOperationAction(ISD::FABS, VT, Expand);
826 setOperationAction(ISD::FSIN, VT, Expand);
827 setOperationAction(ISD::FSINCOS, VT, Expand);
828 setOperationAction(ISD::FCOS, VT, Expand);
829 setOperationAction(ISD::FSINCOS, VT, Expand);
830 setOperationAction(ISD::FREM, VT, Expand);
831 setOperationAction(ISD::FMA, VT, Expand);
832 setOperationAction(ISD::FPOWI, VT, Expand);
833 setOperationAction(ISD::FSQRT, VT, Expand);
834 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
835 setOperationAction(ISD::FFLOOR, VT, Expand);
836 setOperationAction(ISD::FCEIL, VT, Expand);
837 setOperationAction(ISD::FTRUNC, VT, Expand);
838 setOperationAction(ISD::FRINT, VT, Expand);
839 setOperationAction(ISD::FNEARBYINT, VT, Expand);
840 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
841 setOperationAction(ISD::MULHS, VT, Expand);
842 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
843 setOperationAction(ISD::MULHU, VT, Expand);
844 setOperationAction(ISD::SDIVREM, VT, Expand);
845 setOperationAction(ISD::UDIVREM, VT, Expand);
846 setOperationAction(ISD::FPOW, VT, Expand);
847 setOperationAction(ISD::CTPOP, VT, Expand);
848 setOperationAction(ISD::CTTZ, VT, Expand);
849 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
850 setOperationAction(ISD::CTLZ, VT, Expand);
851 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
852 setOperationAction(ISD::SHL, VT, Expand);
853 setOperationAction(ISD::SRA, VT, Expand);
854 setOperationAction(ISD::SRL, VT, Expand);
855 setOperationAction(ISD::ROTL, VT, Expand);
856 setOperationAction(ISD::ROTR, VT, Expand);
857 setOperationAction(ISD::BSWAP, VT, Expand);
858 setOperationAction(ISD::SETCC, VT, Expand);
859 setOperationAction(ISD::FLOG, VT, Expand);
860 setOperationAction(ISD::FLOG2, VT, Expand);
861 setOperationAction(ISD::FLOG10, VT, Expand);
862 setOperationAction(ISD::FEXP, VT, Expand);
863 setOperationAction(ISD::FEXP2, VT, Expand);
864 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
865 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
866 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
867 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
868 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
869 setOperationAction(ISD::TRUNCATE, VT, Expand);
870 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
871 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
872 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
873 setOperationAction(ISD::VSELECT, VT, Expand);
874 setOperationAction(ISD::SELECT_CC, VT, Expand);
875 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
876 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
877 setTruncStoreAction(VT,
878 (MVT::SimpleValueType)InnerVT, Expand);
879 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
880 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
882 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
883 // we have to deal with them whether we ask for Expansion or not. Setting
884 // Expand causes its own optimisation problems though, so leave them legal.
885 if (VT.getVectorElementType() == MVT::i1)
886 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
889 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
890 // with -msoft-float, disable use of MMX as well.
891 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
892 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
893 // No operations on x86mmx supported, everything uses intrinsics.
896 // MMX-sized vectors (other than x86mmx) are expected to be expanded
897 // into smaller operations.
898 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
899 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
900 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
901 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
902 setOperationAction(ISD::AND, MVT::v8i8, Expand);
903 setOperationAction(ISD::AND, MVT::v4i16, Expand);
904 setOperationAction(ISD::AND, MVT::v2i32, Expand);
905 setOperationAction(ISD::AND, MVT::v1i64, Expand);
906 setOperationAction(ISD::OR, MVT::v8i8, Expand);
907 setOperationAction(ISD::OR, MVT::v4i16, Expand);
908 setOperationAction(ISD::OR, MVT::v2i32, Expand);
909 setOperationAction(ISD::OR, MVT::v1i64, Expand);
910 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
911 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
912 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
913 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
914 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
915 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
916 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
917 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
918 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
919 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
920 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
921 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
922 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
923 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
924 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
925 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
926 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
928 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
929 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
931 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
932 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
933 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
934 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
935 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
936 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
937 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
938 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
939 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
940 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
941 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
942 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
943 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
946 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
947 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
949 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
950 // registers cannot be used even for integer operations.
951 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
952 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
953 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
954 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
956 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
957 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
958 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
959 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
960 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
961 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
962 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
963 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
964 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
965 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
966 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
967 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
968 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
969 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
970 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
971 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
972 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
973 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
974 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
975 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
976 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
977 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
979 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
980 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
981 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
982 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
984 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
985 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
986 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
987 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
988 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
990 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
991 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
992 MVT VT = (MVT::SimpleValueType)i;
993 // Do not attempt to custom lower non-power-of-2 vectors
994 if (!isPowerOf2_32(VT.getVectorNumElements()))
996 // Do not attempt to custom lower non-128-bit vectors
997 if (!VT.is128BitVector())
999 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1000 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1001 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1004 // We support custom legalizing of sext and anyext loads for specific
1005 // memory vector types which we can load as a scalar (or sequence of
1006 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1007 // loads these must work with a single scalar load.
1008 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1009 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1010 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1011 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1012 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1013 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1014 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1015 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1016 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1018 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1019 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1020 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1021 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1022 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1023 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1025 if (Subtarget->is64Bit()) {
1026 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1027 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1030 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1031 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1032 MVT VT = (MVT::SimpleValueType)i;
1034 // Do not attempt to promote non-128-bit vectors
1035 if (!VT.is128BitVector())
1038 setOperationAction(ISD::AND, VT, Promote);
1039 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1040 setOperationAction(ISD::OR, VT, Promote);
1041 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1042 setOperationAction(ISD::XOR, VT, Promote);
1043 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1044 setOperationAction(ISD::LOAD, VT, Promote);
1045 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1046 setOperationAction(ISD::SELECT, VT, Promote);
1047 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1050 // Custom lower v2i64 and v2f64 selects.
1051 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1052 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1053 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1054 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1056 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1057 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1059 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1060 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1061 // As there is no 64-bit GPR available, we need build a special custom
1062 // sequence to convert from v2i32 to v2f32.
1063 if (!Subtarget->is64Bit())
1064 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1066 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1067 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1069 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1071 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1072 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1073 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1076 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1077 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1078 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1079 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1080 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1081 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1082 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1083 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1084 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1085 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1086 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1088 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1089 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1090 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1091 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1092 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1093 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1094 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1095 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1096 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1097 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1099 // FIXME: Do we need to handle scalar-to-vector here?
1100 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1102 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1103 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1104 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1105 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1106 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1107 // There is no BLENDI for byte vectors. We don't need to custom lower
1108 // some vselects for now.
1109 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1111 // SSE41 brings specific instructions for doing vector sign extend even in
1112 // cases where we don't have SRA.
1113 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1114 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1115 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1117 // i8 and i16 vectors are custom because the source register and source
1118 // source memory operand types are not the same width. f32 vectors are
1119 // custom since the immediate controlling the insert encodes additional
1121 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1122 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1123 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1124 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1126 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1127 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1128 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1129 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1131 // FIXME: these should be Legal, but that's only for the case where
1132 // the index is constant. For now custom expand to deal with that.
1133 if (Subtarget->is64Bit()) {
1134 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1135 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1139 if (Subtarget->hasSSE2()) {
1140 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1141 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1143 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1144 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1146 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1147 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1149 // In the customized shift lowering, the legal cases in AVX2 will be
1151 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1152 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1154 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1155 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1157 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1160 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1161 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1162 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1163 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1164 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1165 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1166 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1168 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1169 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1170 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1172 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1173 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1174 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1175 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1176 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1177 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1178 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1179 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1180 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1181 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1182 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1183 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1185 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1186 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1187 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1188 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1189 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1190 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1191 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1192 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1193 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1194 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1195 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1196 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1198 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1199 // even though v8i16 is a legal type.
1200 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1201 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1202 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1204 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1205 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1206 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1208 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1209 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1211 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1213 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1214 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1216 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1217 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1219 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1220 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1222 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1223 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1224 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1225 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1227 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1228 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1229 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1231 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1232 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1233 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1234 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1236 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1237 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1238 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1239 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1240 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1241 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1242 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1243 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1244 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1245 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1246 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1247 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1249 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1250 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1251 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1252 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1253 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1254 setOperationAction(ISD::FMA, MVT::f32, Legal);
1255 setOperationAction(ISD::FMA, MVT::f64, Legal);
1258 if (Subtarget->hasInt256()) {
1259 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1260 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1261 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1262 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1264 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1265 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1266 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1267 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1269 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1270 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1271 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1272 // Don't lower v32i8 because there is no 128-bit byte mul
1274 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1275 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1276 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1277 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1279 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1280 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1282 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1283 // when we have a 256bit-wide blend with immediate.
1284 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1286 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1287 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1288 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1289 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1291 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1292 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1293 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1294 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1296 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1297 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1298 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1299 // Don't lower v32i8 because there is no 128-bit byte mul
1302 // In the customized shift lowering, the legal cases in AVX2 will be
1304 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1305 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1307 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1308 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1310 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1312 // Custom lower several nodes for 256-bit types.
1313 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1314 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1315 MVT VT = (MVT::SimpleValueType)i;
1317 // Extract subvector is special because the value type
1318 // (result) is 128-bit but the source is 256-bit wide.
1319 if (VT.is128BitVector()) {
1320 if (VT.getScalarSizeInBits() >= 32) {
1321 setOperationAction(ISD::MLOAD, VT, Custom);
1322 setOperationAction(ISD::MSTORE, VT, Custom);
1324 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1326 // Do not attempt to custom lower other non-256-bit vectors
1327 if (!VT.is256BitVector())
1330 if (VT.getScalarSizeInBits() >= 32) {
1331 setOperationAction(ISD::MLOAD, VT, Legal);
1332 setOperationAction(ISD::MSTORE, VT, Legal);
1334 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1335 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1336 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1337 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1338 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1339 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1340 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1343 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1344 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1345 MVT VT = (MVT::SimpleValueType)i;
1347 // Do not attempt to promote non-256-bit vectors
1348 if (!VT.is256BitVector())
1351 setOperationAction(ISD::AND, VT, Promote);
1352 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1353 setOperationAction(ISD::OR, VT, Promote);
1354 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1355 setOperationAction(ISD::XOR, VT, Promote);
1356 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1357 setOperationAction(ISD::LOAD, VT, Promote);
1358 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1359 setOperationAction(ISD::SELECT, VT, Promote);
1360 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1364 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1365 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1366 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1367 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1368 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1370 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1371 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1372 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1374 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1375 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1376 setOperationAction(ISD::XOR, MVT::i1, Legal);
1377 setOperationAction(ISD::OR, MVT::i1, Legal);
1378 setOperationAction(ISD::AND, MVT::i1, Legal);
1379 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1380 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1381 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1382 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1386 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1387 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1388 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1389 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1393 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1394 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1395 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1399 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1400 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1402 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1403 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1404 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1405 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1406 if (Subtarget->is64Bit()) {
1407 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1408 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1409 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1410 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1412 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1413 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1416 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1418 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1419 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1420 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1421 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1422 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1423 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1424 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1425 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1427 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1430 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1431 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1432 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1433 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1434 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1437 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1438 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1439 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1444 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1445 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1446 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1448 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1449 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1451 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1453 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1454 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1455 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1456 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1457 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1458 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1459 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1460 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1461 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1463 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1464 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1466 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1467 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1469 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1471 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1472 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1474 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1477 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1478 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1480 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1481 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1482 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1483 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1484 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1485 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1487 if (Subtarget->hasCDI()) {
1488 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1489 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1492 // Custom lower several nodes.
1493 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1494 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1495 MVT VT = (MVT::SimpleValueType)i;
1497 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1498 // Extract subvector is special because the value type
1499 // (result) is 256/128-bit but the source is 512-bit wide.
1500 if (VT.is128BitVector() || VT.is256BitVector()) {
1501 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1502 if ( EltSize >= 32) {
1503 setOperationAction(ISD::MLOAD, VT, Legal);
1504 setOperationAction(ISD::MSTORE, VT, Legal);
1507 if (VT.getVectorElementType() == MVT::i1)
1508 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1510 // Do not attempt to custom lower other non-512-bit vectors
1511 if (!VT.is512BitVector())
1514 if ( EltSize >= 32) {
1515 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1516 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1517 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1518 setOperationAction(ISD::VSELECT, VT, Legal);
1519 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1520 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1521 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1522 setOperationAction(ISD::MLOAD, VT, Legal);
1523 setOperationAction(ISD::MSTORE, VT, Legal);
1526 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1527 MVT VT = (MVT::SimpleValueType)i;
1529 // Do not attempt to promote non-256-bit vectors.
1530 if (!VT.is512BitVector())
1533 setOperationAction(ISD::SELECT, VT, Promote);
1534 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1538 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1539 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1540 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1542 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1543 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1545 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1546 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1547 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1548 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1550 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1551 const MVT VT = (MVT::SimpleValueType)i;
1553 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1555 // Do not attempt to promote non-256-bit vectors.
1556 if (!VT.is512BitVector())
1560 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1561 setOperationAction(ISD::VSELECT, VT, Legal);
1566 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1567 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1568 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1570 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1571 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1572 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1574 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1575 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1576 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1577 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1578 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1579 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1582 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1583 // of this type with custom code.
1584 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1585 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1586 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1590 // We want to custom lower some of our intrinsics.
1591 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1592 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1593 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1594 if (!Subtarget->is64Bit())
1595 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1597 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1598 // handle type legalization for these operations here.
1600 // FIXME: We really should do custom legalization for addition and
1601 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1602 // than generic legalization for 64-bit multiplication-with-overflow, though.
1603 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1604 // Add/Sub/Mul with overflow operations are custom lowered.
1606 setOperationAction(ISD::SADDO, VT, Custom);
1607 setOperationAction(ISD::UADDO, VT, Custom);
1608 setOperationAction(ISD::SSUBO, VT, Custom);
1609 setOperationAction(ISD::USUBO, VT, Custom);
1610 setOperationAction(ISD::SMULO, VT, Custom);
1611 setOperationAction(ISD::UMULO, VT, Custom);
1615 if (!Subtarget->is64Bit()) {
1616 // These libcalls are not available in 32-bit.
1617 setLibcallName(RTLIB::SHL_I128, nullptr);
1618 setLibcallName(RTLIB::SRL_I128, nullptr);
1619 setLibcallName(RTLIB::SRA_I128, nullptr);
1622 // Combine sin / cos into one node or libcall if possible.
1623 if (Subtarget->hasSinCos()) {
1624 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1625 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1626 if (Subtarget->isTargetDarwin()) {
1627 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1628 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1629 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1630 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1634 if (Subtarget->isTargetWin64()) {
1635 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1636 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1637 setOperationAction(ISD::SREM, MVT::i128, Custom);
1638 setOperationAction(ISD::UREM, MVT::i128, Custom);
1639 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1640 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1643 // We have target-specific dag combine patterns for the following nodes:
1644 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1645 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1646 setTargetDAGCombine(ISD::VSELECT);
1647 setTargetDAGCombine(ISD::SELECT);
1648 setTargetDAGCombine(ISD::SHL);
1649 setTargetDAGCombine(ISD::SRA);
1650 setTargetDAGCombine(ISD::SRL);
1651 setTargetDAGCombine(ISD::OR);
1652 setTargetDAGCombine(ISD::AND);
1653 setTargetDAGCombine(ISD::ADD);
1654 setTargetDAGCombine(ISD::FADD);
1655 setTargetDAGCombine(ISD::FSUB);
1656 setTargetDAGCombine(ISD::FMA);
1657 setTargetDAGCombine(ISD::SUB);
1658 setTargetDAGCombine(ISD::LOAD);
1659 setTargetDAGCombine(ISD::STORE);
1660 setTargetDAGCombine(ISD::ZERO_EXTEND);
1661 setTargetDAGCombine(ISD::ANY_EXTEND);
1662 setTargetDAGCombine(ISD::SIGN_EXTEND);
1663 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1664 setTargetDAGCombine(ISD::TRUNCATE);
1665 setTargetDAGCombine(ISD::SINT_TO_FP);
1666 setTargetDAGCombine(ISD::SETCC);
1667 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1668 setTargetDAGCombine(ISD::BUILD_VECTOR);
1669 if (Subtarget->is64Bit())
1670 setTargetDAGCombine(ISD::MUL);
1671 setTargetDAGCombine(ISD::XOR);
1673 computeRegisterProperties();
1675 // On Darwin, -Os means optimize for size without hurting performance,
1676 // do not reduce the limit.
1677 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1678 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1679 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1680 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1681 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1682 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1683 setPrefLoopAlignment(4); // 2^4 bytes.
1685 // Predictable cmov don't hurt on atom because it's in-order.
1686 PredictableSelectIsExpensive = !Subtarget->isAtom();
1688 setPrefFunctionAlignment(4); // 2^4 bytes.
1690 verifyIntrinsicTables();
1693 // This has so far only been implemented for 64-bit MachO.
1694 bool X86TargetLowering::useLoadStackGuardNode() const {
1695 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1698 TargetLoweringBase::LegalizeTypeAction
1699 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1700 if (ExperimentalVectorWideningLegalization &&
1701 VT.getVectorNumElements() != 1 &&
1702 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1703 return TypeWidenVector;
1705 return TargetLoweringBase::getPreferredVectorAction(VT);
1708 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1710 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1712 const unsigned NumElts = VT.getVectorNumElements();
1713 const EVT EltVT = VT.getVectorElementType();
1714 if (VT.is512BitVector()) {
1715 if (Subtarget->hasAVX512())
1716 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1717 EltVT == MVT::f32 || EltVT == MVT::f64)
1719 case 8: return MVT::v8i1;
1720 case 16: return MVT::v16i1;
1722 if (Subtarget->hasBWI())
1723 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1725 case 32: return MVT::v32i1;
1726 case 64: return MVT::v64i1;
1730 if (VT.is256BitVector() || VT.is128BitVector()) {
1731 if (Subtarget->hasVLX())
1732 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1733 EltVT == MVT::f32 || EltVT == MVT::f64)
1735 case 2: return MVT::v2i1;
1736 case 4: return MVT::v4i1;
1737 case 8: return MVT::v8i1;
1739 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1740 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1742 case 8: return MVT::v8i1;
1743 case 16: return MVT::v16i1;
1744 case 32: return MVT::v32i1;
1748 return VT.changeVectorElementTypeToInteger();
1751 /// Helper for getByValTypeAlignment to determine
1752 /// the desired ByVal argument alignment.
1753 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1756 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1757 if (VTy->getBitWidth() == 128)
1759 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1760 unsigned EltAlign = 0;
1761 getMaxByValAlign(ATy->getElementType(), EltAlign);
1762 if (EltAlign > MaxAlign)
1763 MaxAlign = EltAlign;
1764 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1765 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1766 unsigned EltAlign = 0;
1767 getMaxByValAlign(STy->getElementType(i), EltAlign);
1768 if (EltAlign > MaxAlign)
1769 MaxAlign = EltAlign;
1776 /// Return the desired alignment for ByVal aggregate
1777 /// function arguments in the caller parameter area. For X86, aggregates
1778 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1779 /// are at 4-byte boundaries.
1780 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1781 if (Subtarget->is64Bit()) {
1782 // Max of 8 and alignment of type.
1783 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1790 if (Subtarget->hasSSE1())
1791 getMaxByValAlign(Ty, Align);
1795 /// Returns the target specific optimal type for load
1796 /// and store operations as a result of memset, memcpy, and memmove
1797 /// lowering. If DstAlign is zero that means it's safe to destination
1798 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1799 /// means there isn't a need to check it against alignment requirement,
1800 /// probably because the source does not need to be loaded. If 'IsMemset' is
1801 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1802 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1803 /// source is constant so it does not need to be loaded.
1804 /// It returns EVT::Other if the type should be determined using generic
1805 /// target-independent logic.
1807 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1808 unsigned DstAlign, unsigned SrcAlign,
1809 bool IsMemset, bool ZeroMemset,
1811 MachineFunction &MF) const {
1812 const Function *F = MF.getFunction();
1813 if ((!IsMemset || ZeroMemset) &&
1814 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1815 Attribute::NoImplicitFloat)) {
1817 (Subtarget->isUnalignedMemAccessFast() ||
1818 ((DstAlign == 0 || DstAlign >= 16) &&
1819 (SrcAlign == 0 || SrcAlign >= 16)))) {
1821 if (Subtarget->hasInt256())
1823 if (Subtarget->hasFp256())
1826 if (Subtarget->hasSSE2())
1828 if (Subtarget->hasSSE1())
1830 } else if (!MemcpyStrSrc && Size >= 8 &&
1831 !Subtarget->is64Bit() &&
1832 Subtarget->hasSSE2()) {
1833 // Do not use f64 to lower memcpy if source is string constant. It's
1834 // better to use i32 to avoid the loads.
1838 if (Subtarget->is64Bit() && Size >= 8)
1843 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1845 return X86ScalarSSEf32;
1846 else if (VT == MVT::f64)
1847 return X86ScalarSSEf64;
1852 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1857 *Fast = Subtarget->isUnalignedMemAccessFast();
1861 /// Return the entry encoding for a jump table in the
1862 /// current function. The returned value is a member of the
1863 /// MachineJumpTableInfo::JTEntryKind enum.
1864 unsigned X86TargetLowering::getJumpTableEncoding() const {
1865 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1867 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1868 Subtarget->isPICStyleGOT())
1869 return MachineJumpTableInfo::EK_Custom32;
1871 // Otherwise, use the normal jump table encoding heuristics.
1872 return TargetLowering::getJumpTableEncoding();
1876 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1877 const MachineBasicBlock *MBB,
1878 unsigned uid,MCContext &Ctx) const{
1879 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1880 Subtarget->isPICStyleGOT());
1881 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1883 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1884 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1887 /// Returns relocation base for the given PIC jumptable.
1888 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1889 SelectionDAG &DAG) const {
1890 if (!Subtarget->is64Bit())
1891 // This doesn't have SDLoc associated with it, but is not really the
1892 // same as a Register.
1893 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1897 /// This returns the relocation base for the given PIC jumptable,
1898 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
1899 const MCExpr *X86TargetLowering::
1900 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1901 MCContext &Ctx) const {
1902 // X86-64 uses RIP relative addressing based on the jump table label.
1903 if (Subtarget->isPICStyleRIPRel())
1904 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1906 // Otherwise, the reference is relative to the PIC base.
1907 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1910 // FIXME: Why this routine is here? Move to RegInfo!
1911 std::pair<const TargetRegisterClass*, uint8_t>
1912 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1913 const TargetRegisterClass *RRC = nullptr;
1915 switch (VT.SimpleTy) {
1917 return TargetLowering::findRepresentativeClass(VT);
1918 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1919 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1922 RRC = &X86::VR64RegClass;
1924 case MVT::f32: case MVT::f64:
1925 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1926 case MVT::v4f32: case MVT::v2f64:
1927 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1929 RRC = &X86::VR128RegClass;
1932 return std::make_pair(RRC, Cost);
1935 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1936 unsigned &Offset) const {
1937 if (!Subtarget->isTargetLinux())
1940 if (Subtarget->is64Bit()) {
1941 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1943 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1955 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1956 unsigned DestAS) const {
1957 assert(SrcAS != DestAS && "Expected different address spaces!");
1959 return SrcAS < 256 && DestAS < 256;
1962 //===----------------------------------------------------------------------===//
1963 // Return Value Calling Convention Implementation
1964 //===----------------------------------------------------------------------===//
1966 #include "X86GenCallingConv.inc"
1969 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1970 MachineFunction &MF, bool isVarArg,
1971 const SmallVectorImpl<ISD::OutputArg> &Outs,
1972 LLVMContext &Context) const {
1973 SmallVector<CCValAssign, 16> RVLocs;
1974 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1975 return CCInfo.CheckReturn(Outs, RetCC_X86);
1978 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1979 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1984 X86TargetLowering::LowerReturn(SDValue Chain,
1985 CallingConv::ID CallConv, bool isVarArg,
1986 const SmallVectorImpl<ISD::OutputArg> &Outs,
1987 const SmallVectorImpl<SDValue> &OutVals,
1988 SDLoc dl, SelectionDAG &DAG) const {
1989 MachineFunction &MF = DAG.getMachineFunction();
1990 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1992 SmallVector<CCValAssign, 16> RVLocs;
1993 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1994 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1997 SmallVector<SDValue, 6> RetOps;
1998 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1999 // Operand #1 = Bytes To Pop
2000 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
2003 // Copy the result values into the output registers.
2004 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2005 CCValAssign &VA = RVLocs[i];
2006 assert(VA.isRegLoc() && "Can only return in registers!");
2007 SDValue ValToCopy = OutVals[i];
2008 EVT ValVT = ValToCopy.getValueType();
2010 // Promote values to the appropriate types.
2011 if (VA.getLocInfo() == CCValAssign::SExt)
2012 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2013 else if (VA.getLocInfo() == CCValAssign::ZExt)
2014 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2015 else if (VA.getLocInfo() == CCValAssign::AExt)
2016 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2017 else if (VA.getLocInfo() == CCValAssign::BCvt)
2018 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2020 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2021 "Unexpected FP-extend for return value.");
2023 // If this is x86-64, and we disabled SSE, we can't return FP values,
2024 // or SSE or MMX vectors.
2025 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2026 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2027 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2028 report_fatal_error("SSE register return with SSE disabled");
2030 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2031 // llvm-gcc has never done it right and no one has noticed, so this
2032 // should be OK for now.
2033 if (ValVT == MVT::f64 &&
2034 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2035 report_fatal_error("SSE2 register return with SSE2 disabled");
2037 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2038 // the RET instruction and handled by the FP Stackifier.
2039 if (VA.getLocReg() == X86::FP0 ||
2040 VA.getLocReg() == X86::FP1) {
2041 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2042 // change the value to the FP stack register class.
2043 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2044 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2045 RetOps.push_back(ValToCopy);
2046 // Don't emit a copytoreg.
2050 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2051 // which is returned in RAX / RDX.
2052 if (Subtarget->is64Bit()) {
2053 if (ValVT == MVT::x86mmx) {
2054 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2055 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2056 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2058 // If we don't have SSE2 available, convert to v4f32 so the generated
2059 // register is legal.
2060 if (!Subtarget->hasSSE2())
2061 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2066 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2067 Flag = Chain.getValue(1);
2068 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2071 // The x86-64 ABIs require that for returning structs by value we copy
2072 // the sret argument into %rax/%eax (depending on ABI) for the return.
2073 // Win32 requires us to put the sret argument to %eax as well.
2074 // We saved the argument into a virtual register in the entry block,
2075 // so now we copy the value out and into %rax/%eax.
2076 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2077 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2078 MachineFunction &MF = DAG.getMachineFunction();
2079 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2080 unsigned Reg = FuncInfo->getSRetReturnReg();
2082 "SRetReturnReg should have been set in LowerFormalArguments().");
2083 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2086 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2087 X86::RAX : X86::EAX;
2088 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2089 Flag = Chain.getValue(1);
2091 // RAX/EAX now acts like a return value.
2092 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2095 RetOps[0] = Chain; // Update chain.
2097 // Add the flag if we have it.
2099 RetOps.push_back(Flag);
2101 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2104 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2105 if (N->getNumValues() != 1)
2107 if (!N->hasNUsesOfValue(1, 0))
2110 SDValue TCChain = Chain;
2111 SDNode *Copy = *N->use_begin();
2112 if (Copy->getOpcode() == ISD::CopyToReg) {
2113 // If the copy has a glue operand, we conservatively assume it isn't safe to
2114 // perform a tail call.
2115 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2117 TCChain = Copy->getOperand(0);
2118 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2121 bool HasRet = false;
2122 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2124 if (UI->getOpcode() != X86ISD::RET_FLAG)
2126 // If we are returning more than one value, we can definitely
2127 // not make a tail call see PR19530
2128 if (UI->getNumOperands() > 4)
2130 if (UI->getNumOperands() == 4 &&
2131 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2144 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2145 ISD::NodeType ExtendKind) const {
2147 // TODO: Is this also valid on 32-bit?
2148 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2149 ReturnMVT = MVT::i8;
2151 ReturnMVT = MVT::i32;
2153 EVT MinVT = getRegisterType(Context, ReturnMVT);
2154 return VT.bitsLT(MinVT) ? MinVT : VT;
2157 /// Lower the result values of a call into the
2158 /// appropriate copies out of appropriate physical registers.
2161 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2162 CallingConv::ID CallConv, bool isVarArg,
2163 const SmallVectorImpl<ISD::InputArg> &Ins,
2164 SDLoc dl, SelectionDAG &DAG,
2165 SmallVectorImpl<SDValue> &InVals) const {
2167 // Assign locations to each value returned by this call.
2168 SmallVector<CCValAssign, 16> RVLocs;
2169 bool Is64Bit = Subtarget->is64Bit();
2170 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2172 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2174 // Copy all of the result registers out of their specified physreg.
2175 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2176 CCValAssign &VA = RVLocs[i];
2177 EVT CopyVT = VA.getValVT();
2179 // If this is x86-64, and we disabled SSE, we can't return FP values
2180 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2181 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2182 report_fatal_error("SSE register return with SSE disabled");
2185 // If we prefer to use the value in xmm registers, copy it out as f80 and
2186 // use a truncate to move it from fp stack reg to xmm reg.
2187 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2188 isScalarFPTypeInSSEReg(VA.getValVT()))
2191 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2192 CopyVT, InFlag).getValue(1);
2193 SDValue Val = Chain.getValue(0);
2195 if (CopyVT != VA.getValVT())
2196 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2197 // This truncation won't change the value.
2198 DAG.getIntPtrConstant(1));
2200 InFlag = Chain.getValue(2);
2201 InVals.push_back(Val);
2207 //===----------------------------------------------------------------------===//
2208 // C & StdCall & Fast Calling Convention implementation
2209 //===----------------------------------------------------------------------===//
2210 // StdCall calling convention seems to be standard for many Windows' API
2211 // routines and around. It differs from C calling convention just a little:
2212 // callee should clean up the stack, not caller. Symbols should be also
2213 // decorated in some fancy way :) It doesn't support any vector arguments.
2214 // For info on fast calling convention see Fast Calling Convention (tail call)
2215 // implementation LowerX86_32FastCCCallTo.
2217 /// CallIsStructReturn - Determines whether a call uses struct return
2219 enum StructReturnType {
2224 static StructReturnType
2225 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2227 return NotStructReturn;
2229 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2230 if (!Flags.isSRet())
2231 return NotStructReturn;
2232 if (Flags.isInReg())
2233 return RegStructReturn;
2234 return StackStructReturn;
2237 /// Determines whether a function uses struct return semantics.
2238 static StructReturnType
2239 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2241 return NotStructReturn;
2243 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2244 if (!Flags.isSRet())
2245 return NotStructReturn;
2246 if (Flags.isInReg())
2247 return RegStructReturn;
2248 return StackStructReturn;
2251 /// Make a copy of an aggregate at address specified by "Src" to address
2252 /// "Dst" with size and alignment information specified by the specific
2253 /// parameter attribute. The copy will be passed as a byval function parameter.
2255 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2256 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2258 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2260 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2261 /*isVolatile*/false, /*AlwaysInline=*/true,
2262 MachinePointerInfo(), MachinePointerInfo());
2265 /// Return true if the calling convention is one that
2266 /// supports tail call optimization.
2267 static bool IsTailCallConvention(CallingConv::ID CC) {
2268 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2269 CC == CallingConv::HiPE);
2272 /// \brief Return true if the calling convention is a C calling convention.
2273 static bool IsCCallConvention(CallingConv::ID CC) {
2274 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2275 CC == CallingConv::X86_64_SysV);
2278 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2279 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2283 CallingConv::ID CalleeCC = CS.getCallingConv();
2284 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2290 /// Return true if the function is being made into
2291 /// a tailcall target by changing its ABI.
2292 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2293 bool GuaranteedTailCallOpt) {
2294 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2298 X86TargetLowering::LowerMemArgument(SDValue Chain,
2299 CallingConv::ID CallConv,
2300 const SmallVectorImpl<ISD::InputArg> &Ins,
2301 SDLoc dl, SelectionDAG &DAG,
2302 const CCValAssign &VA,
2303 MachineFrameInfo *MFI,
2305 // Create the nodes corresponding to a load from this parameter slot.
2306 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2307 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2308 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2309 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2312 // If value is passed by pointer we have address passed instead of the value
2314 if (VA.getLocInfo() == CCValAssign::Indirect)
2315 ValVT = VA.getLocVT();
2317 ValVT = VA.getValVT();
2319 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2320 // changed with more analysis.
2321 // In case of tail call optimization mark all arguments mutable. Since they
2322 // could be overwritten by lowering of arguments in case of a tail call.
2323 if (Flags.isByVal()) {
2324 unsigned Bytes = Flags.getByValSize();
2325 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2326 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2327 return DAG.getFrameIndex(FI, getPointerTy());
2329 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2330 VA.getLocMemOffset(), isImmutable);
2331 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2332 return DAG.getLoad(ValVT, dl, Chain, FIN,
2333 MachinePointerInfo::getFixedStack(FI),
2334 false, false, false, 0);
2338 // FIXME: Get this from tablegen.
2339 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2340 const X86Subtarget *Subtarget) {
2341 assert(Subtarget->is64Bit());
2343 if (Subtarget->isCallingConvWin64(CallConv)) {
2344 static const MCPhysReg GPR64ArgRegsWin64[] = {
2345 X86::RCX, X86::RDX, X86::R8, X86::R9
2347 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2350 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2351 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2353 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2356 // FIXME: Get this from tablegen.
2357 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2358 CallingConv::ID CallConv,
2359 const X86Subtarget *Subtarget) {
2360 assert(Subtarget->is64Bit());
2361 if (Subtarget->isCallingConvWin64(CallConv)) {
2362 // The XMM registers which might contain var arg parameters are shadowed
2363 // in their paired GPR. So we only need to save the GPR to their home
2365 // TODO: __vectorcall will change this.
2369 const Function *Fn = MF.getFunction();
2370 bool NoImplicitFloatOps = Fn->getAttributes().
2371 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2372 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2373 "SSE register cannot be used when SSE is disabled!");
2374 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2375 !Subtarget->hasSSE1())
2376 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2380 static const MCPhysReg XMMArgRegs64Bit[] = {
2381 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2382 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2384 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2388 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2389 CallingConv::ID CallConv,
2391 const SmallVectorImpl<ISD::InputArg> &Ins,
2394 SmallVectorImpl<SDValue> &InVals)
2396 MachineFunction &MF = DAG.getMachineFunction();
2397 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2399 const Function* Fn = MF.getFunction();
2400 if (Fn->hasExternalLinkage() &&
2401 Subtarget->isTargetCygMing() &&
2402 Fn->getName() == "main")
2403 FuncInfo->setForceFramePointer(true);
2405 MachineFrameInfo *MFI = MF.getFrameInfo();
2406 bool Is64Bit = Subtarget->is64Bit();
2407 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2409 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2410 "Var args not supported with calling convention fastcc, ghc or hipe");
2412 // Assign locations to all of the incoming arguments.
2413 SmallVector<CCValAssign, 16> ArgLocs;
2414 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2416 // Allocate shadow area for Win64
2418 CCInfo.AllocateStack(32, 8);
2420 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2422 unsigned LastVal = ~0U;
2424 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2425 CCValAssign &VA = ArgLocs[i];
2426 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2428 assert(VA.getValNo() != LastVal &&
2429 "Don't support value assigned to multiple locs yet");
2431 LastVal = VA.getValNo();
2433 if (VA.isRegLoc()) {
2434 EVT RegVT = VA.getLocVT();
2435 const TargetRegisterClass *RC;
2436 if (RegVT == MVT::i32)
2437 RC = &X86::GR32RegClass;
2438 else if (Is64Bit && RegVT == MVT::i64)
2439 RC = &X86::GR64RegClass;
2440 else if (RegVT == MVT::f32)
2441 RC = &X86::FR32RegClass;
2442 else if (RegVT == MVT::f64)
2443 RC = &X86::FR64RegClass;
2444 else if (RegVT.is512BitVector())
2445 RC = &X86::VR512RegClass;
2446 else if (RegVT.is256BitVector())
2447 RC = &X86::VR256RegClass;
2448 else if (RegVT.is128BitVector())
2449 RC = &X86::VR128RegClass;
2450 else if (RegVT == MVT::x86mmx)
2451 RC = &X86::VR64RegClass;
2452 else if (RegVT == MVT::i1)
2453 RC = &X86::VK1RegClass;
2454 else if (RegVT == MVT::v8i1)
2455 RC = &X86::VK8RegClass;
2456 else if (RegVT == MVT::v16i1)
2457 RC = &X86::VK16RegClass;
2458 else if (RegVT == MVT::v32i1)
2459 RC = &X86::VK32RegClass;
2460 else if (RegVT == MVT::v64i1)
2461 RC = &X86::VK64RegClass;
2463 llvm_unreachable("Unknown argument type!");
2465 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2466 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2468 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2469 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2471 if (VA.getLocInfo() == CCValAssign::SExt)
2472 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2473 DAG.getValueType(VA.getValVT()));
2474 else if (VA.getLocInfo() == CCValAssign::ZExt)
2475 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2476 DAG.getValueType(VA.getValVT()));
2477 else if (VA.getLocInfo() == CCValAssign::BCvt)
2478 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2480 if (VA.isExtInLoc()) {
2481 // Handle MMX values passed in XMM regs.
2482 if (RegVT.isVector())
2483 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2485 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2488 assert(VA.isMemLoc());
2489 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2492 // If value is passed via pointer - do a load.
2493 if (VA.getLocInfo() == CCValAssign::Indirect)
2494 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2495 MachinePointerInfo(), false, false, false, 0);
2497 InVals.push_back(ArgValue);
2500 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2501 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2502 // The x86-64 ABIs require that for returning structs by value we copy
2503 // the sret argument into %rax/%eax (depending on ABI) for the return.
2504 // Win32 requires us to put the sret argument to %eax as well.
2505 // Save the argument into a virtual register so that we can access it
2506 // from the return points.
2507 if (Ins[i].Flags.isSRet()) {
2508 unsigned Reg = FuncInfo->getSRetReturnReg();
2510 MVT PtrTy = getPointerTy();
2511 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2512 FuncInfo->setSRetReturnReg(Reg);
2514 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2515 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2521 unsigned StackSize = CCInfo.getNextStackOffset();
2522 // Align stack specially for tail calls.
2523 if (FuncIsMadeTailCallSafe(CallConv,
2524 MF.getTarget().Options.GuaranteedTailCallOpt))
2525 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2527 // If the function takes variable number of arguments, make a frame index for
2528 // the start of the first vararg value... for expansion of llvm.va_start. We
2529 // can skip this if there are no va_start calls.
2530 if (MFI->hasVAStart() &&
2531 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2532 CallConv != CallingConv::X86_ThisCall))) {
2533 FuncInfo->setVarArgsFrameIndex(
2534 MFI->CreateFixedObject(1, StackSize, true));
2537 // 64-bit calling conventions support varargs and register parameters, so we
2538 // have to do extra work to spill them in the prologue or forward them to
2540 if (Is64Bit && isVarArg &&
2541 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2542 // Find the first unallocated argument registers.
2543 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2544 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2545 unsigned NumIntRegs =
2546 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2547 unsigned NumXMMRegs =
2548 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2549 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2550 "SSE register cannot be used when SSE is disabled!");
2552 // Gather all the live in physical registers.
2553 SmallVector<SDValue, 6> LiveGPRs;
2554 SmallVector<SDValue, 8> LiveXMMRegs;
2556 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2557 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2559 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2561 if (!ArgXMMs.empty()) {
2562 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2563 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2564 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2565 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2566 LiveXMMRegs.push_back(
2567 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2571 // Store them to the va_list returned by va_start.
2572 if (MFI->hasVAStart()) {
2574 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2575 // Get to the caller-allocated home save location. Add 8 to account
2576 // for the return address.
2577 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2578 FuncInfo->setRegSaveFrameIndex(
2579 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2580 // Fixup to set vararg frame on shadow area (4 x i64).
2582 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2584 // For X86-64, if there are vararg parameters that are passed via
2585 // registers, then we must store them to their spots on the stack so
2586 // they may be loaded by deferencing the result of va_next.
2587 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2588 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2589 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2590 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2593 // Store the integer parameter registers.
2594 SmallVector<SDValue, 8> MemOps;
2595 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2597 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2598 for (SDValue Val : LiveGPRs) {
2599 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2600 DAG.getIntPtrConstant(Offset));
2602 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2603 MachinePointerInfo::getFixedStack(
2604 FuncInfo->getRegSaveFrameIndex(), Offset),
2606 MemOps.push_back(Store);
2610 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2611 // Now store the XMM (fp + vector) parameter registers.
2612 SmallVector<SDValue, 12> SaveXMMOps;
2613 SaveXMMOps.push_back(Chain);
2614 SaveXMMOps.push_back(ALVal);
2615 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2616 FuncInfo->getRegSaveFrameIndex()));
2617 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2618 FuncInfo->getVarArgsFPOffset()));
2619 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2621 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2622 MVT::Other, SaveXMMOps));
2625 if (!MemOps.empty())
2626 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2628 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2629 // to the liveout set on a musttail call.
2630 assert(MFI->hasMustTailInVarArgFunc());
2631 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2632 typedef X86MachineFunctionInfo::Forward Forward;
2634 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2636 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2637 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2638 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2641 if (!ArgXMMs.empty()) {
2643 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2644 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2645 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2647 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2649 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2650 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2652 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2658 // Some CCs need callee pop.
2659 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2660 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2661 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2663 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2664 // If this is an sret function, the return should pop the hidden pointer.
2665 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2666 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2667 argsAreStructReturn(Ins) == StackStructReturn)
2668 FuncInfo->setBytesToPopOnReturn(4);
2672 // RegSaveFrameIndex is X86-64 only.
2673 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2674 if (CallConv == CallingConv::X86_FastCall ||
2675 CallConv == CallingConv::X86_ThisCall)
2676 // fastcc functions can't have varargs.
2677 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2680 FuncInfo->setArgumentStackSize(StackSize);
2686 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2687 SDValue StackPtr, SDValue Arg,
2688 SDLoc dl, SelectionDAG &DAG,
2689 const CCValAssign &VA,
2690 ISD::ArgFlagsTy Flags) const {
2691 unsigned LocMemOffset = VA.getLocMemOffset();
2692 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2693 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2694 if (Flags.isByVal())
2695 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2697 return DAG.getStore(Chain, dl, Arg, PtrOff,
2698 MachinePointerInfo::getStack(LocMemOffset),
2702 /// Emit a load of return address if tail call
2703 /// optimization is performed and it is required.
2705 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2706 SDValue &OutRetAddr, SDValue Chain,
2707 bool IsTailCall, bool Is64Bit,
2708 int FPDiff, SDLoc dl) const {
2709 // Adjust the Return address stack slot.
2710 EVT VT = getPointerTy();
2711 OutRetAddr = getReturnAddressFrameIndex(DAG);
2713 // Load the "old" Return address.
2714 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2715 false, false, false, 0);
2716 return SDValue(OutRetAddr.getNode(), 1);
2719 /// Emit a store of the return address if tail call
2720 /// optimization is performed and it is required (FPDiff!=0).
2721 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2722 SDValue Chain, SDValue RetAddrFrIdx,
2723 EVT PtrVT, unsigned SlotSize,
2724 int FPDiff, SDLoc dl) {
2725 // Store the return address to the appropriate stack slot.
2726 if (!FPDiff) return Chain;
2727 // Calculate the new stack slot for the return address.
2728 int NewReturnAddrFI =
2729 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2731 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2732 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2733 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2739 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2740 SmallVectorImpl<SDValue> &InVals) const {
2741 SelectionDAG &DAG = CLI.DAG;
2743 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2744 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2745 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2746 SDValue Chain = CLI.Chain;
2747 SDValue Callee = CLI.Callee;
2748 CallingConv::ID CallConv = CLI.CallConv;
2749 bool &isTailCall = CLI.IsTailCall;
2750 bool isVarArg = CLI.IsVarArg;
2752 MachineFunction &MF = DAG.getMachineFunction();
2753 bool Is64Bit = Subtarget->is64Bit();
2754 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2755 StructReturnType SR = callIsStructReturn(Outs);
2756 bool IsSibcall = false;
2757 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2759 if (MF.getTarget().Options.DisableTailCalls)
2762 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2764 // Force this to be a tail call. The verifier rules are enough to ensure
2765 // that we can lower this successfully without moving the return address
2768 } else if (isTailCall) {
2769 // Check if it's really possible to do a tail call.
2770 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2771 isVarArg, SR != NotStructReturn,
2772 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2773 Outs, OutVals, Ins, DAG);
2775 // Sibcalls are automatically detected tailcalls which do not require
2777 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2784 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2785 "Var args not supported with calling convention fastcc, ghc or hipe");
2787 // Analyze operands of the call, assigning locations to each operand.
2788 SmallVector<CCValAssign, 16> ArgLocs;
2789 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2791 // Allocate shadow area for Win64
2793 CCInfo.AllocateStack(32, 8);
2795 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2797 // Get a count of how many bytes are to be pushed on the stack.
2798 unsigned NumBytes = CCInfo.getNextStackOffset();
2800 // This is a sibcall. The memory operands are available in caller's
2801 // own caller's stack.
2803 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2804 IsTailCallConvention(CallConv))
2805 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2808 if (isTailCall && !IsSibcall && !IsMustTail) {
2809 // Lower arguments at fp - stackoffset + fpdiff.
2810 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2812 FPDiff = NumBytesCallerPushed - NumBytes;
2814 // Set the delta of movement of the returnaddr stackslot.
2815 // But only set if delta is greater than previous delta.
2816 if (FPDiff < X86Info->getTCReturnAddrDelta())
2817 X86Info->setTCReturnAddrDelta(FPDiff);
2820 unsigned NumBytesToPush = NumBytes;
2821 unsigned NumBytesToPop = NumBytes;
2823 // If we have an inalloca argument, all stack space has already been allocated
2824 // for us and be right at the top of the stack. We don't support multiple
2825 // arguments passed in memory when using inalloca.
2826 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2828 if (!ArgLocs.back().isMemLoc())
2829 report_fatal_error("cannot use inalloca attribute on a register "
2831 if (ArgLocs.back().getLocMemOffset() != 0)
2832 report_fatal_error("any parameter with the inalloca attribute must be "
2833 "the only memory argument");
2837 Chain = DAG.getCALLSEQ_START(
2838 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2840 SDValue RetAddrFrIdx;
2841 // Load return address for tail calls.
2842 if (isTailCall && FPDiff)
2843 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2844 Is64Bit, FPDiff, dl);
2846 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2847 SmallVector<SDValue, 8> MemOpChains;
2850 // Walk the register/memloc assignments, inserting copies/loads. In the case
2851 // of tail call optimization arguments are handle later.
2852 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2853 DAG.getSubtarget().getRegisterInfo());
2854 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2855 // Skip inalloca arguments, they have already been written.
2856 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2857 if (Flags.isInAlloca())
2860 CCValAssign &VA = ArgLocs[i];
2861 EVT RegVT = VA.getLocVT();
2862 SDValue Arg = OutVals[i];
2863 bool isByVal = Flags.isByVal();
2865 // Promote the value if needed.
2866 switch (VA.getLocInfo()) {
2867 default: llvm_unreachable("Unknown loc info!");
2868 case CCValAssign::Full: break;
2869 case CCValAssign::SExt:
2870 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2872 case CCValAssign::ZExt:
2873 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2875 case CCValAssign::AExt:
2876 if (RegVT.is128BitVector()) {
2877 // Special case: passing MMX values in XMM registers.
2878 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2879 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2880 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2882 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2884 case CCValAssign::BCvt:
2885 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2887 case CCValAssign::Indirect: {
2888 // Store the argument.
2889 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2890 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2891 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2892 MachinePointerInfo::getFixedStack(FI),
2899 if (VA.isRegLoc()) {
2900 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2901 if (isVarArg && IsWin64) {
2902 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2903 // shadow reg if callee is a varargs function.
2904 unsigned ShadowReg = 0;
2905 switch (VA.getLocReg()) {
2906 case X86::XMM0: ShadowReg = X86::RCX; break;
2907 case X86::XMM1: ShadowReg = X86::RDX; break;
2908 case X86::XMM2: ShadowReg = X86::R8; break;
2909 case X86::XMM3: ShadowReg = X86::R9; break;
2912 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2914 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2915 assert(VA.isMemLoc());
2916 if (!StackPtr.getNode())
2917 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2919 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2920 dl, DAG, VA, Flags));
2924 if (!MemOpChains.empty())
2925 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2927 if (Subtarget->isPICStyleGOT()) {
2928 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2931 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2932 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2934 // If we are tail calling and generating PIC/GOT style code load the
2935 // address of the callee into ECX. The value in ecx is used as target of
2936 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2937 // for tail calls on PIC/GOT architectures. Normally we would just put the
2938 // address of GOT into ebx and then call target@PLT. But for tail calls
2939 // ebx would be restored (since ebx is callee saved) before jumping to the
2942 // Note: The actual moving to ECX is done further down.
2943 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2944 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2945 !G->getGlobal()->hasProtectedVisibility())
2946 Callee = LowerGlobalAddress(Callee, DAG);
2947 else if (isa<ExternalSymbolSDNode>(Callee))
2948 Callee = LowerExternalSymbol(Callee, DAG);
2952 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2953 // From AMD64 ABI document:
2954 // For calls that may call functions that use varargs or stdargs
2955 // (prototype-less calls or calls to functions containing ellipsis (...) in
2956 // the declaration) %al is used as hidden argument to specify the number
2957 // of SSE registers used. The contents of %al do not need to match exactly
2958 // the number of registers, but must be an ubound on the number of SSE
2959 // registers used and is in the range 0 - 8 inclusive.
2961 // Count the number of XMM registers allocated.
2962 static const MCPhysReg XMMArgRegs[] = {
2963 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2964 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2966 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2967 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2968 && "SSE registers cannot be used when SSE is disabled");
2970 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2971 DAG.getConstant(NumXMMRegs, MVT::i8)));
2974 if (Is64Bit && isVarArg && IsMustTail) {
2975 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2976 for (const auto &F : Forwards) {
2977 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2978 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2982 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2983 // don't need this because the eligibility check rejects calls that require
2984 // shuffling arguments passed in memory.
2985 if (!IsSibcall && isTailCall) {
2986 // Force all the incoming stack arguments to be loaded from the stack
2987 // before any new outgoing arguments are stored to the stack, because the
2988 // outgoing stack slots may alias the incoming argument stack slots, and
2989 // the alias isn't otherwise explicit. This is slightly more conservative
2990 // than necessary, because it means that each store effectively depends
2991 // on every argument instead of just those arguments it would clobber.
2992 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2994 SmallVector<SDValue, 8> MemOpChains2;
2997 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2998 CCValAssign &VA = ArgLocs[i];
3001 assert(VA.isMemLoc());
3002 SDValue Arg = OutVals[i];
3003 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3004 // Skip inalloca arguments. They don't require any work.
3005 if (Flags.isInAlloca())
3007 // Create frame index.
3008 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3009 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3010 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3011 FIN = DAG.getFrameIndex(FI, getPointerTy());
3013 if (Flags.isByVal()) {
3014 // Copy relative to framepointer.
3015 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3016 if (!StackPtr.getNode())
3017 StackPtr = DAG.getCopyFromReg(Chain, dl,
3018 RegInfo->getStackRegister(),
3020 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3022 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3026 // Store relative to framepointer.
3027 MemOpChains2.push_back(
3028 DAG.getStore(ArgChain, dl, Arg, FIN,
3029 MachinePointerInfo::getFixedStack(FI),
3034 if (!MemOpChains2.empty())
3035 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3037 // Store the return address to the appropriate stack slot.
3038 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3039 getPointerTy(), RegInfo->getSlotSize(),
3043 // Build a sequence of copy-to-reg nodes chained together with token chain
3044 // and flag operands which copy the outgoing args into registers.
3046 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3047 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3048 RegsToPass[i].second, InFlag);
3049 InFlag = Chain.getValue(1);
3052 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3053 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3054 // In the 64-bit large code model, we have to make all calls
3055 // through a register, since the call instruction's 32-bit
3056 // pc-relative offset may not be large enough to hold the whole
3058 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3059 // If the callee is a GlobalAddress node (quite common, every direct call
3060 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3063 // We should use extra load for direct calls to dllimported functions in
3065 const GlobalValue *GV = G->getGlobal();
3066 if (!GV->hasDLLImportStorageClass()) {
3067 unsigned char OpFlags = 0;
3068 bool ExtraLoad = false;
3069 unsigned WrapperKind = ISD::DELETED_NODE;
3071 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3072 // external symbols most go through the PLT in PIC mode. If the symbol
3073 // has hidden or protected visibility, or if it is static or local, then
3074 // we don't need to use the PLT - we can directly call it.
3075 if (Subtarget->isTargetELF() &&
3076 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3077 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3078 OpFlags = X86II::MO_PLT;
3079 } else if (Subtarget->isPICStyleStubAny() &&
3080 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3081 (!Subtarget->getTargetTriple().isMacOSX() ||
3082 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3083 // PC-relative references to external symbols should go through $stub,
3084 // unless we're building with the leopard linker or later, which
3085 // automatically synthesizes these stubs.
3086 OpFlags = X86II::MO_DARWIN_STUB;
3087 } else if (Subtarget->isPICStyleRIPRel() &&
3088 isa<Function>(GV) &&
3089 cast<Function>(GV)->getAttributes().
3090 hasAttribute(AttributeSet::FunctionIndex,
3091 Attribute::NonLazyBind)) {
3092 // If the function is marked as non-lazy, generate an indirect call
3093 // which loads from the GOT directly. This avoids runtime overhead
3094 // at the cost of eager binding (and one extra byte of encoding).
3095 OpFlags = X86II::MO_GOTPCREL;
3096 WrapperKind = X86ISD::WrapperRIP;
3100 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3101 G->getOffset(), OpFlags);
3103 // Add a wrapper if needed.
3104 if (WrapperKind != ISD::DELETED_NODE)
3105 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3106 // Add extra indirection if needed.
3108 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3109 MachinePointerInfo::getGOT(),
3110 false, false, false, 0);
3112 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3113 unsigned char OpFlags = 0;
3115 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3116 // external symbols should go through the PLT.
3117 if (Subtarget->isTargetELF() &&
3118 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3119 OpFlags = X86II::MO_PLT;
3120 } else if (Subtarget->isPICStyleStubAny() &&
3121 (!Subtarget->getTargetTriple().isMacOSX() ||
3122 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3123 // PC-relative references to external symbols should go through $stub,
3124 // unless we're building with the leopard linker or later, which
3125 // automatically synthesizes these stubs.
3126 OpFlags = X86II::MO_DARWIN_STUB;
3129 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3131 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3132 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3133 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3136 // Returns a chain & a flag for retval copy to use.
3137 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3138 SmallVector<SDValue, 8> Ops;
3140 if (!IsSibcall && isTailCall) {
3141 Chain = DAG.getCALLSEQ_END(Chain,
3142 DAG.getIntPtrConstant(NumBytesToPop, true),
3143 DAG.getIntPtrConstant(0, true), InFlag, dl);
3144 InFlag = Chain.getValue(1);
3147 Ops.push_back(Chain);
3148 Ops.push_back(Callee);
3151 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3153 // Add argument registers to the end of the list so that they are known live
3155 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3156 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3157 RegsToPass[i].second.getValueType()));
3159 // Add a register mask operand representing the call-preserved registers.
3160 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3161 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3162 assert(Mask && "Missing call preserved mask for calling convention");
3163 Ops.push_back(DAG.getRegisterMask(Mask));
3165 if (InFlag.getNode())
3166 Ops.push_back(InFlag);
3170 //// If this is the first return lowered for this function, add the regs
3171 //// to the liveout set for the function.
3172 // This isn't right, although it's probably harmless on x86; liveouts
3173 // should be computed from returns not tail calls. Consider a void
3174 // function making a tail call to a function returning int.
3175 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3178 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3179 InFlag = Chain.getValue(1);
3181 // Create the CALLSEQ_END node.
3182 unsigned NumBytesForCalleeToPop;
3183 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3184 DAG.getTarget().Options.GuaranteedTailCallOpt))
3185 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3186 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3187 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3188 SR == StackStructReturn)
3189 // If this is a call to a struct-return function, the callee
3190 // pops the hidden struct pointer, so we have to push it back.
3191 // This is common for Darwin/X86, Linux & Mingw32 targets.
3192 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3193 NumBytesForCalleeToPop = 4;
3195 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3197 // Returns a flag for retval copy to use.
3199 Chain = DAG.getCALLSEQ_END(Chain,
3200 DAG.getIntPtrConstant(NumBytesToPop, true),
3201 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3204 InFlag = Chain.getValue(1);
3207 // Handle result values, copying them out of physregs into vregs that we
3209 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3210 Ins, dl, DAG, InVals);
3213 //===----------------------------------------------------------------------===//
3214 // Fast Calling Convention (tail call) implementation
3215 //===----------------------------------------------------------------------===//
3217 // Like std call, callee cleans arguments, convention except that ECX is
3218 // reserved for storing the tail called function address. Only 2 registers are
3219 // free for argument passing (inreg). Tail call optimization is performed
3221 // * tailcallopt is enabled
3222 // * caller/callee are fastcc
3223 // On X86_64 architecture with GOT-style position independent code only local
3224 // (within module) calls are supported at the moment.
3225 // To keep the stack aligned according to platform abi the function
3226 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3227 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3228 // If a tail called function callee has more arguments than the caller the
3229 // caller needs to make sure that there is room to move the RETADDR to. This is
3230 // achieved by reserving an area the size of the argument delta right after the
3231 // original RETADDR, but before the saved framepointer or the spilled registers
3232 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3244 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3245 /// for a 16 byte align requirement.
3247 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3248 SelectionDAG& DAG) const {
3249 MachineFunction &MF = DAG.getMachineFunction();
3250 const TargetMachine &TM = MF.getTarget();
3251 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3252 TM.getSubtargetImpl()->getRegisterInfo());
3253 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3254 unsigned StackAlignment = TFI.getStackAlignment();
3255 uint64_t AlignMask = StackAlignment - 1;
3256 int64_t Offset = StackSize;
3257 unsigned SlotSize = RegInfo->getSlotSize();
3258 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3259 // Number smaller than 12 so just add the difference.
3260 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3262 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3263 Offset = ((~AlignMask) & Offset) + StackAlignment +
3264 (StackAlignment-SlotSize);
3269 /// MatchingStackOffset - Return true if the given stack call argument is
3270 /// already available in the same position (relatively) of the caller's
3271 /// incoming argument stack.
3273 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3274 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3275 const X86InstrInfo *TII) {
3276 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3278 if (Arg.getOpcode() == ISD::CopyFromReg) {
3279 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3280 if (!TargetRegisterInfo::isVirtualRegister(VR))
3282 MachineInstr *Def = MRI->getVRegDef(VR);
3285 if (!Flags.isByVal()) {
3286 if (!TII->isLoadFromStackSlot(Def, FI))
3289 unsigned Opcode = Def->getOpcode();
3290 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3291 Def->getOperand(1).isFI()) {
3292 FI = Def->getOperand(1).getIndex();
3293 Bytes = Flags.getByValSize();
3297 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3298 if (Flags.isByVal())
3299 // ByVal argument is passed in as a pointer but it's now being
3300 // dereferenced. e.g.
3301 // define @foo(%struct.X* %A) {
3302 // tail call @bar(%struct.X* byval %A)
3305 SDValue Ptr = Ld->getBasePtr();
3306 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3309 FI = FINode->getIndex();
3310 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3311 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3312 FI = FINode->getIndex();
3313 Bytes = Flags.getByValSize();
3317 assert(FI != INT_MAX);
3318 if (!MFI->isFixedObjectIndex(FI))
3320 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3323 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3324 /// for tail call optimization. Targets which want to do tail call
3325 /// optimization should implement this function.
3327 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3328 CallingConv::ID CalleeCC,
3330 bool isCalleeStructRet,
3331 bool isCallerStructRet,
3333 const SmallVectorImpl<ISD::OutputArg> &Outs,
3334 const SmallVectorImpl<SDValue> &OutVals,
3335 const SmallVectorImpl<ISD::InputArg> &Ins,
3336 SelectionDAG &DAG) const {
3337 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3340 // If -tailcallopt is specified, make fastcc functions tail-callable.
3341 const MachineFunction &MF = DAG.getMachineFunction();
3342 const Function *CallerF = MF.getFunction();
3344 // If the function return type is x86_fp80 and the callee return type is not,
3345 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3346 // perform a tailcall optimization here.
3347 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3350 CallingConv::ID CallerCC = CallerF->getCallingConv();
3351 bool CCMatch = CallerCC == CalleeCC;
3352 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3353 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3355 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3356 if (IsTailCallConvention(CalleeCC) && CCMatch)
3361 // Look for obvious safe cases to perform tail call optimization that do not
3362 // require ABI changes. This is what gcc calls sibcall.
3364 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3365 // emit a special epilogue.
3366 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3367 DAG.getSubtarget().getRegisterInfo());
3368 if (RegInfo->needsStackRealignment(MF))
3371 // Also avoid sibcall optimization if either caller or callee uses struct
3372 // return semantics.
3373 if (isCalleeStructRet || isCallerStructRet)
3376 // An stdcall/thiscall caller is expected to clean up its arguments; the
3377 // callee isn't going to do that.
3378 // FIXME: this is more restrictive than needed. We could produce a tailcall
3379 // when the stack adjustment matches. For example, with a thiscall that takes
3380 // only one argument.
3381 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3382 CallerCC == CallingConv::X86_ThisCall))
3385 // Do not sibcall optimize vararg calls unless all arguments are passed via
3387 if (isVarArg && !Outs.empty()) {
3389 // Optimizing for varargs on Win64 is unlikely to be safe without
3390 // additional testing.
3391 if (IsCalleeWin64 || IsCallerWin64)
3394 SmallVector<CCValAssign, 16> ArgLocs;
3395 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3398 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3399 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3400 if (!ArgLocs[i].isRegLoc())
3404 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3405 // stack. Therefore, if it's not used by the call it is not safe to optimize
3406 // this into a sibcall.
3407 bool Unused = false;
3408 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3415 SmallVector<CCValAssign, 16> RVLocs;
3416 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3418 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3419 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3420 CCValAssign &VA = RVLocs[i];
3421 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3426 // If the calling conventions do not match, then we'd better make sure the
3427 // results are returned in the same way as what the caller expects.
3429 SmallVector<CCValAssign, 16> RVLocs1;
3430 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3432 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3434 SmallVector<CCValAssign, 16> RVLocs2;
3435 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3437 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3439 if (RVLocs1.size() != RVLocs2.size())
3441 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3442 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3444 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3446 if (RVLocs1[i].isRegLoc()) {
3447 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3450 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3456 // If the callee takes no arguments then go on to check the results of the
3458 if (!Outs.empty()) {
3459 // Check if stack adjustment is needed. For now, do not do this if any
3460 // argument is passed on the stack.
3461 SmallVector<CCValAssign, 16> ArgLocs;
3462 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3465 // Allocate shadow area for Win64
3467 CCInfo.AllocateStack(32, 8);
3469 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3470 if (CCInfo.getNextStackOffset()) {
3471 MachineFunction &MF = DAG.getMachineFunction();
3472 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3475 // Check if the arguments are already laid out in the right way as
3476 // the caller's fixed stack objects.
3477 MachineFrameInfo *MFI = MF.getFrameInfo();
3478 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3479 const X86InstrInfo *TII =
3480 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3481 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3482 CCValAssign &VA = ArgLocs[i];
3483 SDValue Arg = OutVals[i];
3484 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3485 if (VA.getLocInfo() == CCValAssign::Indirect)
3487 if (!VA.isRegLoc()) {
3488 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3495 // If the tailcall address may be in a register, then make sure it's
3496 // possible to register allocate for it. In 32-bit, the call address can
3497 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3498 // callee-saved registers are restored. These happen to be the same
3499 // registers used to pass 'inreg' arguments so watch out for those.
3500 if (!Subtarget->is64Bit() &&
3501 ((!isa<GlobalAddressSDNode>(Callee) &&
3502 !isa<ExternalSymbolSDNode>(Callee)) ||
3503 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3504 unsigned NumInRegs = 0;
3505 // In PIC we need an extra register to formulate the address computation
3507 unsigned MaxInRegs =
3508 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3510 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3511 CCValAssign &VA = ArgLocs[i];
3514 unsigned Reg = VA.getLocReg();
3517 case X86::EAX: case X86::EDX: case X86::ECX:
3518 if (++NumInRegs == MaxInRegs)
3530 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3531 const TargetLibraryInfo *libInfo) const {
3532 return X86::createFastISel(funcInfo, libInfo);
3535 //===----------------------------------------------------------------------===//
3536 // Other Lowering Hooks
3537 //===----------------------------------------------------------------------===//
3539 static bool MayFoldLoad(SDValue Op) {
3540 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3543 static bool MayFoldIntoStore(SDValue Op) {
3544 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3547 static bool isTargetShuffle(unsigned Opcode) {
3549 default: return false;
3550 case X86ISD::BLENDI:
3551 case X86ISD::PSHUFB:
3552 case X86ISD::PSHUFD:
3553 case X86ISD::PSHUFHW:
3554 case X86ISD::PSHUFLW:
3556 case X86ISD::PALIGNR:
3557 case X86ISD::MOVLHPS:
3558 case X86ISD::MOVLHPD:
3559 case X86ISD::MOVHLPS:
3560 case X86ISD::MOVLPS:
3561 case X86ISD::MOVLPD:
3562 case X86ISD::MOVSHDUP:
3563 case X86ISD::MOVSLDUP:
3564 case X86ISD::MOVDDUP:
3567 case X86ISD::UNPCKL:
3568 case X86ISD::UNPCKH:
3569 case X86ISD::VPERMILPI:
3570 case X86ISD::VPERM2X128:
3571 case X86ISD::VPERMI:
3576 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3577 SDValue V1, SelectionDAG &DAG) {
3579 default: llvm_unreachable("Unknown x86 shuffle node");
3580 case X86ISD::MOVSHDUP:
3581 case X86ISD::MOVSLDUP:
3582 case X86ISD::MOVDDUP:
3583 return DAG.getNode(Opc, dl, VT, V1);
3587 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3588 SDValue V1, unsigned TargetMask,
3589 SelectionDAG &DAG) {
3591 default: llvm_unreachable("Unknown x86 shuffle node");
3592 case X86ISD::PSHUFD:
3593 case X86ISD::PSHUFHW:
3594 case X86ISD::PSHUFLW:
3595 case X86ISD::VPERMILPI:
3596 case X86ISD::VPERMI:
3597 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3601 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3602 SDValue V1, SDValue V2, unsigned TargetMask,
3603 SelectionDAG &DAG) {
3605 default: llvm_unreachable("Unknown x86 shuffle node");
3606 case X86ISD::PALIGNR:
3607 case X86ISD::VALIGN:
3609 case X86ISD::VPERM2X128:
3610 return DAG.getNode(Opc, dl, VT, V1, V2,
3611 DAG.getConstant(TargetMask, MVT::i8));
3615 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3616 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3618 default: llvm_unreachable("Unknown x86 shuffle node");
3619 case X86ISD::MOVLHPS:
3620 case X86ISD::MOVLHPD:
3621 case X86ISD::MOVHLPS:
3622 case X86ISD::MOVLPS:
3623 case X86ISD::MOVLPD:
3626 case X86ISD::UNPCKL:
3627 case X86ISD::UNPCKH:
3628 return DAG.getNode(Opc, dl, VT, V1, V2);
3632 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3633 MachineFunction &MF = DAG.getMachineFunction();
3634 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3635 DAG.getSubtarget().getRegisterInfo());
3636 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3637 int ReturnAddrIndex = FuncInfo->getRAIndex();
3639 if (ReturnAddrIndex == 0) {
3640 // Set up a frame object for the return address.
3641 unsigned SlotSize = RegInfo->getSlotSize();
3642 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3645 FuncInfo->setRAIndex(ReturnAddrIndex);
3648 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3651 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3652 bool hasSymbolicDisplacement) {
3653 // Offset should fit into 32 bit immediate field.
3654 if (!isInt<32>(Offset))
3657 // If we don't have a symbolic displacement - we don't have any extra
3659 if (!hasSymbolicDisplacement)
3662 // FIXME: Some tweaks might be needed for medium code model.
3663 if (M != CodeModel::Small && M != CodeModel::Kernel)
3666 // For small code model we assume that latest object is 16MB before end of 31
3667 // bits boundary. We may also accept pretty large negative constants knowing
3668 // that all objects are in the positive half of address space.
3669 if (M == CodeModel::Small && Offset < 16*1024*1024)
3672 // For kernel code model we know that all object resist in the negative half
3673 // of 32bits address space. We may not accept negative offsets, since they may
3674 // be just off and we may accept pretty large positive ones.
3675 if (M == CodeModel::Kernel && Offset >= 0)
3681 /// isCalleePop - Determines whether the callee is required to pop its
3682 /// own arguments. Callee pop is necessary to support tail calls.
3683 bool X86::isCalleePop(CallingConv::ID CallingConv,
3684 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3685 switch (CallingConv) {
3688 case CallingConv::X86_StdCall:
3689 case CallingConv::X86_FastCall:
3690 case CallingConv::X86_ThisCall:
3692 case CallingConv::Fast:
3693 case CallingConv::GHC:
3694 case CallingConv::HiPE:
3701 /// \brief Return true if the condition is an unsigned comparison operation.
3702 static bool isX86CCUnsigned(unsigned X86CC) {
3704 default: llvm_unreachable("Invalid integer condition!");
3705 case X86::COND_E: return true;
3706 case X86::COND_G: return false;
3707 case X86::COND_GE: return false;
3708 case X86::COND_L: return false;
3709 case X86::COND_LE: return false;
3710 case X86::COND_NE: return true;
3711 case X86::COND_B: return true;
3712 case X86::COND_A: return true;
3713 case X86::COND_BE: return true;
3714 case X86::COND_AE: return true;
3716 llvm_unreachable("covered switch fell through?!");
3719 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3720 /// specific condition code, returning the condition code and the LHS/RHS of the
3721 /// comparison to make.
3722 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3723 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3725 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3726 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3727 // X > -1 -> X == 0, jump !sign.
3728 RHS = DAG.getConstant(0, RHS.getValueType());
3729 return X86::COND_NS;
3731 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3732 // X < 0 -> X == 0, jump on sign.
3735 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3737 RHS = DAG.getConstant(0, RHS.getValueType());
3738 return X86::COND_LE;
3742 switch (SetCCOpcode) {
3743 default: llvm_unreachable("Invalid integer condition!");
3744 case ISD::SETEQ: return X86::COND_E;
3745 case ISD::SETGT: return X86::COND_G;
3746 case ISD::SETGE: return X86::COND_GE;
3747 case ISD::SETLT: return X86::COND_L;
3748 case ISD::SETLE: return X86::COND_LE;
3749 case ISD::SETNE: return X86::COND_NE;
3750 case ISD::SETULT: return X86::COND_B;
3751 case ISD::SETUGT: return X86::COND_A;
3752 case ISD::SETULE: return X86::COND_BE;
3753 case ISD::SETUGE: return X86::COND_AE;
3757 // First determine if it is required or is profitable to flip the operands.
3759 // If LHS is a foldable load, but RHS is not, flip the condition.
3760 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3761 !ISD::isNON_EXTLoad(RHS.getNode())) {
3762 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3763 std::swap(LHS, RHS);
3766 switch (SetCCOpcode) {
3772 std::swap(LHS, RHS);
3776 // On a floating point condition, the flags are set as follows:
3778 // 0 | 0 | 0 | X > Y
3779 // 0 | 0 | 1 | X < Y
3780 // 1 | 0 | 0 | X == Y
3781 // 1 | 1 | 1 | unordered
3782 switch (SetCCOpcode) {
3783 default: llvm_unreachable("Condcode should be pre-legalized away");
3785 case ISD::SETEQ: return X86::COND_E;
3786 case ISD::SETOLT: // flipped
3788 case ISD::SETGT: return X86::COND_A;
3789 case ISD::SETOLE: // flipped
3791 case ISD::SETGE: return X86::COND_AE;
3792 case ISD::SETUGT: // flipped
3794 case ISD::SETLT: return X86::COND_B;
3795 case ISD::SETUGE: // flipped
3797 case ISD::SETLE: return X86::COND_BE;
3799 case ISD::SETNE: return X86::COND_NE;
3800 case ISD::SETUO: return X86::COND_P;
3801 case ISD::SETO: return X86::COND_NP;
3803 case ISD::SETUNE: return X86::COND_INVALID;
3807 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3808 /// code. Current x86 isa includes the following FP cmov instructions:
3809 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3810 static bool hasFPCMov(unsigned X86CC) {
3826 /// isFPImmLegal - Returns true if the target can instruction select the
3827 /// specified FP immediate natively. If false, the legalizer will
3828 /// materialize the FP immediate as a load from a constant pool.
3829 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3830 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3831 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3837 /// \brief Returns true if it is beneficial to convert a load of a constant
3838 /// to just the constant itself.
3839 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3841 assert(Ty->isIntegerTy());
3843 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3844 if (BitSize == 0 || BitSize > 64)
3849 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3850 /// the specified range (L, H].
3851 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3852 return (Val < 0) || (Val >= Low && Val < Hi);
3855 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3856 /// specified value.
3857 static bool isUndefOrEqual(int Val, int CmpVal) {
3858 return (Val < 0 || Val == CmpVal);
3861 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3862 /// from position Pos and ending in Pos+Size, falls within the specified
3863 /// sequential range (L, L+Pos]. or is undef.
3864 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3865 unsigned Pos, unsigned Size, int Low) {
3866 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3867 if (!isUndefOrEqual(Mask[i], Low))
3872 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3873 /// is suitable for input to PSHUFD. That is, it doesn't reference the other
3874 /// operand - by default will match for first operand.
3875 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT,
3876 bool TestSecondOperand = false) {
3877 if (VT != MVT::v4f32 && VT != MVT::v4i32 &&
3878 VT != MVT::v2f64 && VT != MVT::v2i64)
3881 unsigned NumElems = VT.getVectorNumElements();
3882 unsigned Lo = TestSecondOperand ? NumElems : 0;
3883 unsigned Hi = Lo + NumElems;
3885 for (unsigned i = 0; i < NumElems; ++i)
3886 if (!isUndefOrInRange(Mask[i], (int)Lo, (int)Hi))
3892 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3893 /// is suitable for input to PSHUFHW.
3894 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3895 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3898 // Lower quadword copied in order or undef.
3899 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3902 // Upper quadword shuffled.
3903 for (unsigned i = 4; i != 8; ++i)
3904 if (!isUndefOrInRange(Mask[i], 4, 8))
3907 if (VT == MVT::v16i16) {
3908 // Lower quadword copied in order or undef.
3909 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3912 // Upper quadword shuffled.
3913 for (unsigned i = 12; i != 16; ++i)
3914 if (!isUndefOrInRange(Mask[i], 12, 16))
3921 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3922 /// is suitable for input to PSHUFLW.
3923 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3924 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3927 // Upper quadword copied in order.
3928 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3931 // Lower quadword shuffled.
3932 for (unsigned i = 0; i != 4; ++i)
3933 if (!isUndefOrInRange(Mask[i], 0, 4))
3936 if (VT == MVT::v16i16) {
3937 // Upper quadword copied in order.
3938 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3941 // Lower quadword shuffled.
3942 for (unsigned i = 8; i != 12; ++i)
3943 if (!isUndefOrInRange(Mask[i], 8, 12))
3950 /// \brief Return true if the mask specifies a shuffle of elements that is
3951 /// suitable for input to intralane (palignr) or interlane (valign) vector
3953 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3954 unsigned NumElts = VT.getVectorNumElements();
3955 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3956 unsigned NumLaneElts = NumElts/NumLanes;
3958 // Do not handle 64-bit element shuffles with palignr.
3959 if (NumLaneElts == 2)
3962 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3964 for (i = 0; i != NumLaneElts; ++i) {
3969 // Lane is all undef, go to next lane
3970 if (i == NumLaneElts)
3973 int Start = Mask[i+l];
3975 // Make sure its in this lane in one of the sources
3976 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3977 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3980 // If not lane 0, then we must match lane 0
3981 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3984 // Correct second source to be contiguous with first source
3985 if (Start >= (int)NumElts)
3986 Start -= NumElts - NumLaneElts;
3988 // Make sure we're shifting in the right direction.
3989 if (Start <= (int)(i+l))
3994 // Check the rest of the elements to see if they are consecutive.
3995 for (++i; i != NumLaneElts; ++i) {
3996 int Idx = Mask[i+l];
3998 // Make sure its in this lane
3999 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
4000 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
4003 // If not lane 0, then we must match lane 0
4004 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
4007 if (Idx >= (int)NumElts)
4008 Idx -= NumElts - NumLaneElts;
4010 if (!isUndefOrEqual(Idx, Start+i))
4019 /// \brief Return true if the node specifies a shuffle of elements that is
4020 /// suitable for input to PALIGNR.
4021 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4022 const X86Subtarget *Subtarget) {
4023 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4024 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4025 VT.is512BitVector())
4026 // FIXME: Add AVX512BW.
4029 return isAlignrMask(Mask, VT, false);
4032 /// \brief Return true if the node specifies a shuffle of elements that is
4033 /// suitable for input to VALIGN.
4034 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4035 const X86Subtarget *Subtarget) {
4036 // FIXME: Add AVX512VL.
4037 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4039 return isAlignrMask(Mask, VT, true);
4042 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4043 /// the two vector operands have swapped position.
4044 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4045 unsigned NumElems) {
4046 for (unsigned i = 0; i != NumElems; ++i) {
4050 else if (idx < (int)NumElems)
4051 Mask[i] = idx + NumElems;
4053 Mask[i] = idx - NumElems;
4057 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4058 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4059 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4060 /// reverse of what x86 shuffles want.
4061 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4063 unsigned NumElems = VT.getVectorNumElements();
4064 unsigned NumLanes = VT.getSizeInBits()/128;
4065 unsigned NumLaneElems = NumElems/NumLanes;
4067 if (NumLaneElems != 2 && NumLaneElems != 4)
4070 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4071 bool symetricMaskRequired =
4072 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4074 // VSHUFPSY divides the resulting vector into 4 chunks.
4075 // The sources are also splitted into 4 chunks, and each destination
4076 // chunk must come from a different source chunk.
4078 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4079 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4081 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4082 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4084 // VSHUFPDY divides the resulting vector into 4 chunks.
4085 // The sources are also splitted into 4 chunks, and each destination
4086 // chunk must come from a different source chunk.
4088 // SRC1 => X3 X2 X1 X0
4089 // SRC2 => Y3 Y2 Y1 Y0
4091 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4093 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4094 unsigned HalfLaneElems = NumLaneElems/2;
4095 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4096 for (unsigned i = 0; i != NumLaneElems; ++i) {
4097 int Idx = Mask[i+l];
4098 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4099 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4101 // For VSHUFPSY, the mask of the second half must be the same as the
4102 // first but with the appropriate offsets. This works in the same way as
4103 // VPERMILPS works with masks.
4104 if (!symetricMaskRequired || Idx < 0)
4106 if (MaskVal[i] < 0) {
4107 MaskVal[i] = Idx - l;
4110 if ((signed)(Idx - l) != MaskVal[i])
4118 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4119 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4120 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4121 if (!VT.is128BitVector())
4124 unsigned NumElems = VT.getVectorNumElements();
4129 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4130 return isUndefOrEqual(Mask[0], 6) &&
4131 isUndefOrEqual(Mask[1], 7) &&
4132 isUndefOrEqual(Mask[2], 2) &&
4133 isUndefOrEqual(Mask[3], 3);
4136 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4137 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4139 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4140 if (!VT.is128BitVector())
4143 unsigned NumElems = VT.getVectorNumElements();
4148 return isUndefOrEqual(Mask[0], 2) &&
4149 isUndefOrEqual(Mask[1], 3) &&
4150 isUndefOrEqual(Mask[2], 2) &&
4151 isUndefOrEqual(Mask[3], 3);
4154 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4155 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4156 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4157 if (!VT.is128BitVector())
4160 unsigned NumElems = VT.getVectorNumElements();
4162 if (NumElems != 2 && NumElems != 4)
4165 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4166 if (!isUndefOrEqual(Mask[i], i + NumElems))
4169 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4170 if (!isUndefOrEqual(Mask[i], i))
4176 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4177 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4178 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4179 if (!VT.is128BitVector())
4182 unsigned NumElems = VT.getVectorNumElements();
4184 if (NumElems != 2 && NumElems != 4)
4187 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4188 if (!isUndefOrEqual(Mask[i], i))
4191 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4192 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4198 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4199 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4200 /// i. e: If all but one element come from the same vector.
4201 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4202 // TODO: Deal with AVX's VINSERTPS
4203 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4206 unsigned CorrectPosV1 = 0;
4207 unsigned CorrectPosV2 = 0;
4208 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4209 if (Mask[i] == -1) {
4217 else if (Mask[i] == i + 4)
4221 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4222 // We have 3 elements (undefs count as elements from any vector) from one
4223 // vector, and one from another.
4230 // Some special combinations that can be optimized.
4233 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4234 SelectionDAG &DAG) {
4235 MVT VT = SVOp->getSimpleValueType(0);
4238 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4241 ArrayRef<int> Mask = SVOp->getMask();
4243 // These are the special masks that may be optimized.
4244 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4245 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4246 bool MatchEvenMask = true;
4247 bool MatchOddMask = true;
4248 for (int i=0; i<8; ++i) {
4249 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4250 MatchEvenMask = false;
4251 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4252 MatchOddMask = false;
4255 if (!MatchEvenMask && !MatchOddMask)
4258 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4260 SDValue Op0 = SVOp->getOperand(0);
4261 SDValue Op1 = SVOp->getOperand(1);
4263 if (MatchEvenMask) {
4264 // Shift the second operand right to 32 bits.
4265 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4266 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4268 // Shift the first operand left to 32 bits.
4269 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4270 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4272 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4273 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4276 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4277 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4278 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4279 bool HasInt256, bool V2IsSplat = false) {
4281 assert(VT.getSizeInBits() >= 128 &&
4282 "Unsupported vector type for unpckl");
4284 unsigned NumElts = VT.getVectorNumElements();
4285 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4286 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4289 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4290 "Unsupported vector type for unpckh");
4292 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4293 unsigned NumLanes = VT.getSizeInBits()/128;
4294 unsigned NumLaneElts = NumElts/NumLanes;
4296 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4297 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4298 int BitI = Mask[l+i];
4299 int BitI1 = Mask[l+i+1];
4300 if (!isUndefOrEqual(BitI, j))
4303 if (!isUndefOrEqual(BitI1, NumElts))
4306 if (!isUndefOrEqual(BitI1, j + NumElts))
4315 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4316 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4317 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4318 bool HasInt256, bool V2IsSplat = false) {
4319 assert(VT.getSizeInBits() >= 128 &&
4320 "Unsupported vector type for unpckh");
4322 unsigned NumElts = VT.getVectorNumElements();
4323 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4324 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4327 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4328 "Unsupported vector type for unpckh");
4330 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4331 unsigned NumLanes = VT.getSizeInBits()/128;
4332 unsigned NumLaneElts = NumElts/NumLanes;
4334 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4335 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4336 int BitI = Mask[l+i];
4337 int BitI1 = Mask[l+i+1];
4338 if (!isUndefOrEqual(BitI, j))
4341 if (isUndefOrEqual(BitI1, NumElts))
4344 if (!isUndefOrEqual(BitI1, j+NumElts))
4352 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4353 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4355 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4356 unsigned NumElts = VT.getVectorNumElements();
4357 bool Is256BitVec = VT.is256BitVector();
4359 if (VT.is512BitVector())
4361 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4362 "Unsupported vector type for unpckh");
4364 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4365 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4368 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4369 // FIXME: Need a better way to get rid of this, there's no latency difference
4370 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4371 // the former later. We should also remove the "_undef" special mask.
4372 if (NumElts == 4 && Is256BitVec)
4375 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4376 // independently on 128-bit lanes.
4377 unsigned NumLanes = VT.getSizeInBits()/128;
4378 unsigned NumLaneElts = NumElts/NumLanes;
4380 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4381 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4382 int BitI = Mask[l+i];
4383 int BitI1 = Mask[l+i+1];
4385 if (!isUndefOrEqual(BitI, j))
4387 if (!isUndefOrEqual(BitI1, j))
4395 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4396 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4398 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4399 unsigned NumElts = VT.getVectorNumElements();
4401 if (VT.is512BitVector())
4404 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4405 "Unsupported vector type for unpckh");
4407 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4408 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4411 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4412 // independently on 128-bit lanes.
4413 unsigned NumLanes = VT.getSizeInBits()/128;
4414 unsigned NumLaneElts = NumElts/NumLanes;
4416 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4417 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4418 int BitI = Mask[l+i];
4419 int BitI1 = Mask[l+i+1];
4420 if (!isUndefOrEqual(BitI, j))
4422 if (!isUndefOrEqual(BitI1, j))
4429 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4430 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4431 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4432 if (!VT.is512BitVector())
4435 unsigned NumElts = VT.getVectorNumElements();
4436 unsigned HalfSize = NumElts/2;
4437 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4438 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4443 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4444 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4452 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4453 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4454 /// MOVSD, and MOVD, i.e. setting the lowest element.
4455 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4456 if (VT.getVectorElementType().getSizeInBits() < 32)
4458 if (!VT.is128BitVector())
4461 unsigned NumElts = VT.getVectorNumElements();
4463 if (!isUndefOrEqual(Mask[0], NumElts))
4466 for (unsigned i = 1; i != NumElts; ++i)
4467 if (!isUndefOrEqual(Mask[i], i))
4473 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4474 /// as permutations between 128-bit chunks or halves. As an example: this
4476 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4477 /// The first half comes from the second half of V1 and the second half from the
4478 /// the second half of V2.
4479 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4480 if (!HasFp256 || !VT.is256BitVector())
4483 // The shuffle result is divided into half A and half B. In total the two
4484 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4485 // B must come from C, D, E or F.
4486 unsigned HalfSize = VT.getVectorNumElements()/2;
4487 bool MatchA = false, MatchB = false;
4489 // Check if A comes from one of C, D, E, F.
4490 for (unsigned Half = 0; Half != 4; ++Half) {
4491 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4497 // Check if B comes from one of C, D, E, F.
4498 for (unsigned Half = 0; Half != 4; ++Half) {
4499 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4505 return MatchA && MatchB;
4508 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4509 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4510 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4511 MVT VT = SVOp->getSimpleValueType(0);
4513 unsigned HalfSize = VT.getVectorNumElements()/2;
4515 unsigned FstHalf = 0, SndHalf = 0;
4516 for (unsigned i = 0; i < HalfSize; ++i) {
4517 if (SVOp->getMaskElt(i) > 0) {
4518 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4522 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4523 if (SVOp->getMaskElt(i) > 0) {
4524 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4529 return (FstHalf | (SndHalf << 4));
4532 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4533 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4534 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4538 unsigned NumElts = VT.getVectorNumElements();
4540 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4541 for (unsigned i = 0; i != NumElts; ++i) {
4544 Imm8 |= Mask[i] << (i*2);
4549 unsigned LaneSize = 4;
4550 SmallVector<int, 4> MaskVal(LaneSize, -1);
4552 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4553 for (unsigned i = 0; i != LaneSize; ++i) {
4554 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4558 if (MaskVal[i] < 0) {
4559 MaskVal[i] = Mask[i+l] - l;
4560 Imm8 |= MaskVal[i] << (i*2);
4563 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4570 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4571 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4572 /// Note that VPERMIL mask matching is different depending whether theunderlying
4573 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4574 /// to the same elements of the low, but to the higher half of the source.
4575 /// In VPERMILPD the two lanes could be shuffled independently of each other
4576 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4577 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4578 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4579 if (VT.getSizeInBits() < 256 || EltSize < 32)
4581 bool symetricMaskRequired = (EltSize == 32);
4582 unsigned NumElts = VT.getVectorNumElements();
4584 unsigned NumLanes = VT.getSizeInBits()/128;
4585 unsigned LaneSize = NumElts/NumLanes;
4586 // 2 or 4 elements in one lane
4588 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4589 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4590 for (unsigned i = 0; i != LaneSize; ++i) {
4591 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4593 if (symetricMaskRequired) {
4594 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4595 ExpectedMaskVal[i] = Mask[i+l] - l;
4598 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4606 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4607 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4608 /// element of vector 2 and the other elements to come from vector 1 in order.
4609 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4610 bool V2IsSplat = false, bool V2IsUndef = false) {
4611 if (!VT.is128BitVector())
4614 unsigned NumOps = VT.getVectorNumElements();
4615 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4618 if (!isUndefOrEqual(Mask[0], 0))
4621 for (unsigned i = 1; i != NumOps; ++i)
4622 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4623 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4624 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4630 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4631 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4632 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4633 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4634 const X86Subtarget *Subtarget) {
4635 if (!Subtarget->hasSSE3())
4638 unsigned NumElems = VT.getVectorNumElements();
4640 if ((VT.is128BitVector() && NumElems != 4) ||
4641 (VT.is256BitVector() && NumElems != 8) ||
4642 (VT.is512BitVector() && NumElems != 16))
4645 // "i+1" is the value the indexed mask element must have
4646 for (unsigned i = 0; i != NumElems; i += 2)
4647 if (!isUndefOrEqual(Mask[i], i+1) ||
4648 !isUndefOrEqual(Mask[i+1], i+1))
4654 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4655 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4656 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4657 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4658 const X86Subtarget *Subtarget) {
4659 if (!Subtarget->hasSSE3())
4662 unsigned NumElems = VT.getVectorNumElements();
4664 if ((VT.is128BitVector() && NumElems != 4) ||
4665 (VT.is256BitVector() && NumElems != 8) ||
4666 (VT.is512BitVector() && NumElems != 16))
4669 // "i" is the value the indexed mask element must have
4670 for (unsigned i = 0; i != NumElems; i += 2)
4671 if (!isUndefOrEqual(Mask[i], i) ||
4672 !isUndefOrEqual(Mask[i+1], i))
4678 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4679 /// specifies a shuffle of elements that is suitable for input to 256-bit
4680 /// version of MOVDDUP.
4681 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4682 if (!HasFp256 || !VT.is256BitVector())
4685 unsigned NumElts = VT.getVectorNumElements();
4689 for (unsigned i = 0; i != NumElts/2; ++i)
4690 if (!isUndefOrEqual(Mask[i], 0))
4692 for (unsigned i = NumElts/2; i != NumElts; ++i)
4693 if (!isUndefOrEqual(Mask[i], NumElts/2))
4698 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4699 /// specifies a shuffle of elements that is suitable for input to 128-bit
4700 /// version of MOVDDUP.
4701 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4702 if (!VT.is128BitVector())
4705 unsigned e = VT.getVectorNumElements() / 2;
4706 for (unsigned i = 0; i != e; ++i)
4707 if (!isUndefOrEqual(Mask[i], i))
4709 for (unsigned i = 0; i != e; ++i)
4710 if (!isUndefOrEqual(Mask[e+i], i))
4715 /// isVEXTRACTIndex - Return true if the specified
4716 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4717 /// suitable for instruction that extract 128 or 256 bit vectors
4718 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4719 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4720 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4723 // The index should be aligned on a vecWidth-bit boundary.
4725 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4727 MVT VT = N->getSimpleValueType(0);
4728 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4729 bool Result = (Index * ElSize) % vecWidth == 0;
4734 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4735 /// operand specifies a subvector insert that is suitable for input to
4736 /// insertion of 128 or 256-bit subvectors
4737 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4738 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4739 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4741 // The index should be aligned on a vecWidth-bit boundary.
4743 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4745 MVT VT = N->getSimpleValueType(0);
4746 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4747 bool Result = (Index * ElSize) % vecWidth == 0;
4752 bool X86::isVINSERT128Index(SDNode *N) {
4753 return isVINSERTIndex(N, 128);
4756 bool X86::isVINSERT256Index(SDNode *N) {
4757 return isVINSERTIndex(N, 256);
4760 bool X86::isVEXTRACT128Index(SDNode *N) {
4761 return isVEXTRACTIndex(N, 128);
4764 bool X86::isVEXTRACT256Index(SDNode *N) {
4765 return isVEXTRACTIndex(N, 256);
4768 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4769 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4770 /// Handles 128-bit and 256-bit.
4771 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4772 MVT VT = N->getSimpleValueType(0);
4774 assert((VT.getSizeInBits() >= 128) &&
4775 "Unsupported vector type for PSHUF/SHUFP");
4777 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4778 // independently on 128-bit lanes.
4779 unsigned NumElts = VT.getVectorNumElements();
4780 unsigned NumLanes = VT.getSizeInBits()/128;
4781 unsigned NumLaneElts = NumElts/NumLanes;
4783 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4784 "Only supports 2, 4 or 8 elements per lane");
4786 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4788 for (unsigned i = 0; i != NumElts; ++i) {
4789 int Elt = N->getMaskElt(i);
4790 if (Elt < 0) continue;
4791 Elt &= NumLaneElts - 1;
4792 unsigned ShAmt = (i << Shift) % 8;
4793 Mask |= Elt << ShAmt;
4799 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4800 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4801 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4802 MVT VT = N->getSimpleValueType(0);
4804 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4805 "Unsupported vector type for PSHUFHW");
4807 unsigned NumElts = VT.getVectorNumElements();
4810 for (unsigned l = 0; l != NumElts; l += 8) {
4811 // 8 nodes per lane, but we only care about the last 4.
4812 for (unsigned i = 0; i < 4; ++i) {
4813 int Elt = N->getMaskElt(l+i+4);
4814 if (Elt < 0) continue;
4815 Elt &= 0x3; // only 2-bits.
4816 Mask |= Elt << (i * 2);
4823 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4824 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4825 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4826 MVT VT = N->getSimpleValueType(0);
4828 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4829 "Unsupported vector type for PSHUFHW");
4831 unsigned NumElts = VT.getVectorNumElements();
4834 for (unsigned l = 0; l != NumElts; l += 8) {
4835 // 8 nodes per lane, but we only care about the first 4.
4836 for (unsigned i = 0; i < 4; ++i) {
4837 int Elt = N->getMaskElt(l+i);
4838 if (Elt < 0) continue;
4839 Elt &= 0x3; // only 2-bits
4840 Mask |= Elt << (i * 2);
4847 /// \brief Return the appropriate immediate to shuffle the specified
4848 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4849 /// VALIGN (if Interlane is true) instructions.
4850 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4852 MVT VT = SVOp->getSimpleValueType(0);
4853 unsigned EltSize = InterLane ? 1 :
4854 VT.getVectorElementType().getSizeInBits() >> 3;
4856 unsigned NumElts = VT.getVectorNumElements();
4857 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4858 unsigned NumLaneElts = NumElts/NumLanes;
4862 for (i = 0; i != NumElts; ++i) {
4863 Val = SVOp->getMaskElt(i);
4867 if (Val >= (int)NumElts)
4868 Val -= NumElts - NumLaneElts;
4870 assert(Val - i > 0 && "PALIGNR imm should be positive");
4871 return (Val - i) * EltSize;
4874 /// \brief Return the appropriate immediate to shuffle the specified
4875 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4876 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4877 return getShuffleAlignrImmediate(SVOp, false);
4880 /// \brief Return the appropriate immediate to shuffle the specified
4881 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4882 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4883 return getShuffleAlignrImmediate(SVOp, true);
4887 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4888 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4889 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4890 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4893 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4895 MVT VecVT = N->getOperand(0).getSimpleValueType();
4896 MVT ElVT = VecVT.getVectorElementType();
4898 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4899 return Index / NumElemsPerChunk;
4902 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4903 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4904 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4905 llvm_unreachable("Illegal insert subvector for VINSERT");
4908 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4910 MVT VecVT = N->getSimpleValueType(0);
4911 MVT ElVT = VecVT.getVectorElementType();
4913 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4914 return Index / NumElemsPerChunk;
4917 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4918 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4919 /// and VINSERTI128 instructions.
4920 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4921 return getExtractVEXTRACTImmediate(N, 128);
4924 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4925 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4926 /// and VINSERTI64x4 instructions.
4927 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4928 return getExtractVEXTRACTImmediate(N, 256);
4931 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4932 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4933 /// and VINSERTI128 instructions.
4934 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4935 return getInsertVINSERTImmediate(N, 128);
4938 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4939 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4940 /// and VINSERTI64x4 instructions.
4941 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4942 return getInsertVINSERTImmediate(N, 256);
4945 /// isZero - Returns true if Elt is a constant integer zero
4946 static bool isZero(SDValue V) {
4947 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4948 return C && C->isNullValue();
4951 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4953 bool X86::isZeroNode(SDValue Elt) {
4956 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4957 return CFP->getValueAPF().isPosZero();
4961 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4962 /// match movhlps. The lower half elements should come from upper half of
4963 /// V1 (and in order), and the upper half elements should come from the upper
4964 /// half of V2 (and in order).
4965 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4966 if (!VT.is128BitVector())
4968 if (VT.getVectorNumElements() != 4)
4970 for (unsigned i = 0, e = 2; i != e; ++i)
4971 if (!isUndefOrEqual(Mask[i], i+2))
4973 for (unsigned i = 2; i != 4; ++i)
4974 if (!isUndefOrEqual(Mask[i], i+4))
4979 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4980 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4982 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4983 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4985 N = N->getOperand(0).getNode();
4986 if (!ISD::isNON_EXTLoad(N))
4989 *LD = cast<LoadSDNode>(N);
4993 // Test whether the given value is a vector value which will be legalized
4995 static bool WillBeConstantPoolLoad(SDNode *N) {
4996 if (N->getOpcode() != ISD::BUILD_VECTOR)
4999 // Check for any non-constant elements.
5000 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
5001 switch (N->getOperand(i).getNode()->getOpcode()) {
5003 case ISD::ConstantFP:
5010 // Vectors of all-zeros and all-ones are materialized with special
5011 // instructions rather than being loaded.
5012 return !ISD::isBuildVectorAllZeros(N) &&
5013 !ISD::isBuildVectorAllOnes(N);
5016 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5017 /// match movlp{s|d}. The lower half elements should come from lower half of
5018 /// V1 (and in order), and the upper half elements should come from the upper
5019 /// half of V2 (and in order). And since V1 will become the source of the
5020 /// MOVLP, it must be either a vector load or a scalar load to vector.
5021 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5022 ArrayRef<int> Mask, MVT VT) {
5023 if (!VT.is128BitVector())
5026 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5028 // Is V2 is a vector load, don't do this transformation. We will try to use
5029 // load folding shufps op.
5030 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5033 unsigned NumElems = VT.getVectorNumElements();
5035 if (NumElems != 2 && NumElems != 4)
5037 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5038 if (!isUndefOrEqual(Mask[i], i))
5040 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5041 if (!isUndefOrEqual(Mask[i], i+NumElems))
5046 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5047 /// to an zero vector.
5048 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5049 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5050 SDValue V1 = N->getOperand(0);
5051 SDValue V2 = N->getOperand(1);
5052 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5053 for (unsigned i = 0; i != NumElems; ++i) {
5054 int Idx = N->getMaskElt(i);
5055 if (Idx >= (int)NumElems) {
5056 unsigned Opc = V2.getOpcode();
5057 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5059 if (Opc != ISD::BUILD_VECTOR ||
5060 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5062 } else if (Idx >= 0) {
5063 unsigned Opc = V1.getOpcode();
5064 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5066 if (Opc != ISD::BUILD_VECTOR ||
5067 !X86::isZeroNode(V1.getOperand(Idx)))
5074 /// getZeroVector - Returns a vector of specified type with all zero elements.
5076 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5077 SelectionDAG &DAG, SDLoc dl) {
5078 assert(VT.isVector() && "Expected a vector type");
5080 // Always build SSE zero vectors as <4 x i32> bitcasted
5081 // to their dest type. This ensures they get CSE'd.
5083 if (VT.is128BitVector()) { // SSE
5084 if (Subtarget->hasSSE2()) { // SSE2
5085 SDValue Cst = DAG.getConstant(0, MVT::i32);
5086 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5088 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5089 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5091 } else if (VT.is256BitVector()) { // AVX
5092 if (Subtarget->hasInt256()) { // AVX2
5093 SDValue Cst = DAG.getConstant(0, MVT::i32);
5094 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5095 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5097 // 256-bit logic and arithmetic instructions in AVX are all
5098 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5099 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5100 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5101 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5103 } else if (VT.is512BitVector()) { // AVX-512
5104 SDValue Cst = DAG.getConstant(0, MVT::i32);
5105 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5106 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5107 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5108 } else if (VT.getScalarType() == MVT::i1) {
5109 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5110 SDValue Cst = DAG.getConstant(0, MVT::i1);
5111 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5112 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5114 llvm_unreachable("Unexpected vector type");
5116 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5119 /// getOnesVector - Returns a vector of specified type with all bits set.
5120 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5121 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5122 /// Then bitcast to their original type, ensuring they get CSE'd.
5123 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5125 assert(VT.isVector() && "Expected a vector type");
5127 SDValue Cst = DAG.getConstant(~0U, MVT::i32);
5129 if (VT.is256BitVector()) {
5130 if (HasInt256) { // AVX2
5131 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5132 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5134 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5135 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5137 } else if (VT.is128BitVector()) {
5138 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5140 llvm_unreachable("Unexpected vector type");
5142 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5145 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5146 /// that point to V2 points to its first element.
5147 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5148 for (unsigned i = 0; i != NumElems; ++i) {
5149 if (Mask[i] > (int)NumElems) {
5155 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5156 /// operation of specified width.
5157 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5159 unsigned NumElems = VT.getVectorNumElements();
5160 SmallVector<int, 8> Mask;
5161 Mask.push_back(NumElems);
5162 for (unsigned i = 1; i != NumElems; ++i)
5164 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5167 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5168 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5170 unsigned NumElems = VT.getVectorNumElements();
5171 SmallVector<int, 8> Mask;
5172 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5174 Mask.push_back(i + NumElems);
5176 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5179 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5180 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5182 unsigned NumElems = VT.getVectorNumElements();
5183 SmallVector<int, 8> Mask;
5184 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5185 Mask.push_back(i + Half);
5186 Mask.push_back(i + NumElems + Half);
5188 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5191 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5192 // a generic shuffle instruction because the target has no such instructions.
5193 // Generate shuffles which repeat i16 and i8 several times until they can be
5194 // represented by v4f32 and then be manipulated by target suported shuffles.
5195 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5196 MVT VT = V.getSimpleValueType();
5197 int NumElems = VT.getVectorNumElements();
5200 while (NumElems > 4) {
5201 if (EltNo < NumElems/2) {
5202 V = getUnpackl(DAG, dl, VT, V, V);
5204 V = getUnpackh(DAG, dl, VT, V, V);
5205 EltNo -= NumElems/2;
5212 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5213 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5214 MVT VT = V.getSimpleValueType();
5217 if (VT.is128BitVector()) {
5218 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5219 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5220 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5222 } else if (VT.is256BitVector()) {
5223 // To use VPERMILPS to splat scalars, the second half of indicies must
5224 // refer to the higher part, which is a duplication of the lower one,
5225 // because VPERMILPS can only handle in-lane permutations.
5226 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5227 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5229 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5230 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5233 llvm_unreachable("Vector size not supported");
5235 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5238 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5239 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5240 MVT SrcVT = SV->getSimpleValueType(0);
5241 SDValue V1 = SV->getOperand(0);
5244 int EltNo = SV->getSplatIndex();
5245 int NumElems = SrcVT.getVectorNumElements();
5246 bool Is256BitVec = SrcVT.is256BitVector();
5248 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5249 "Unknown how to promote splat for type");
5251 // Extract the 128-bit part containing the splat element and update
5252 // the splat element index when it refers to the higher register.
5254 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5255 if (EltNo >= NumElems/2)
5256 EltNo -= NumElems/2;
5259 // All i16 and i8 vector types can't be used directly by a generic shuffle
5260 // instruction because the target has no such instruction. Generate shuffles
5261 // which repeat i16 and i8 several times until they fit in i32, and then can
5262 // be manipulated by target suported shuffles.
5263 MVT EltVT = SrcVT.getVectorElementType();
5264 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5265 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5267 // Recreate the 256-bit vector and place the same 128-bit vector
5268 // into the low and high part. This is necessary because we want
5269 // to use VPERM* to shuffle the vectors
5271 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5274 return getLegalSplat(DAG, V1, EltNo);
5277 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5278 /// vector of zero or undef vector. This produces a shuffle where the low
5279 /// element of V2 is swizzled into the zero/undef vector, landing at element
5280 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5281 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5283 const X86Subtarget *Subtarget,
5284 SelectionDAG &DAG) {
5285 MVT VT = V2.getSimpleValueType();
5287 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5288 unsigned NumElems = VT.getVectorNumElements();
5289 SmallVector<int, 16> MaskVec;
5290 for (unsigned i = 0; i != NumElems; ++i)
5291 // If this is the insertion idx, put the low elt of V2 here.
5292 MaskVec.push_back(i == Idx ? NumElems : i);
5293 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5296 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5297 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5298 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5299 /// shuffles which use a single input multiple times, and in those cases it will
5300 /// adjust the mask to only have indices within that single input.
5301 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5302 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5303 unsigned NumElems = VT.getVectorNumElements();
5307 bool IsFakeUnary = false;
5308 switch(N->getOpcode()) {
5309 case X86ISD::BLENDI:
5310 ImmN = N->getOperand(N->getNumOperands()-1);
5311 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5314 ImmN = N->getOperand(N->getNumOperands()-1);
5315 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5316 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5318 case X86ISD::UNPCKH:
5319 DecodeUNPCKHMask(VT, Mask);
5320 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5322 case X86ISD::UNPCKL:
5323 DecodeUNPCKLMask(VT, Mask);
5324 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5326 case X86ISD::MOVHLPS:
5327 DecodeMOVHLPSMask(NumElems, Mask);
5328 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5330 case X86ISD::MOVLHPS:
5331 DecodeMOVLHPSMask(NumElems, Mask);
5332 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5334 case X86ISD::PALIGNR:
5335 ImmN = N->getOperand(N->getNumOperands()-1);
5336 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5338 case X86ISD::PSHUFD:
5339 case X86ISD::VPERMILPI:
5340 ImmN = N->getOperand(N->getNumOperands()-1);
5341 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5344 case X86ISD::PSHUFHW:
5345 ImmN = N->getOperand(N->getNumOperands()-1);
5346 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5349 case X86ISD::PSHUFLW:
5350 ImmN = N->getOperand(N->getNumOperands()-1);
5351 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5354 case X86ISD::PSHUFB: {
5356 SDValue MaskNode = N->getOperand(1);
5357 while (MaskNode->getOpcode() == ISD::BITCAST)
5358 MaskNode = MaskNode->getOperand(0);
5360 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5361 // If we have a build-vector, then things are easy.
5362 EVT VT = MaskNode.getValueType();
5363 assert(VT.isVector() &&
5364 "Can't produce a non-vector with a build_vector!");
5365 if (!VT.isInteger())
5368 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5370 SmallVector<uint64_t, 32> RawMask;
5371 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5372 SDValue Op = MaskNode->getOperand(i);
5373 if (Op->getOpcode() == ISD::UNDEF) {
5374 RawMask.push_back((uint64_t)SM_SentinelUndef);
5377 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5380 APInt MaskElement = CN->getAPIntValue();
5382 // We now have to decode the element which could be any integer size and
5383 // extract each byte of it.
5384 for (int j = 0; j < NumBytesPerElement; ++j) {
5385 // Note that this is x86 and so always little endian: the low byte is
5386 // the first byte of the mask.
5387 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5388 MaskElement = MaskElement.lshr(8);
5391 DecodePSHUFBMask(RawMask, Mask);
5395 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5399 SDValue Ptr = MaskLoad->getBasePtr();
5400 if (Ptr->getOpcode() == X86ISD::Wrapper)
5401 Ptr = Ptr->getOperand(0);
5403 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5404 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5407 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5408 // FIXME: Support AVX-512 here.
5409 Type *Ty = C->getType();
5410 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5411 Ty->getVectorNumElements() != 32))
5414 DecodePSHUFBMask(C, Mask);
5420 case X86ISD::VPERMI:
5421 ImmN = N->getOperand(N->getNumOperands()-1);
5422 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5426 case X86ISD::MOVSD: {
5427 // The index 0 always comes from the first element of the second source,
5428 // this is why MOVSS and MOVSD are used in the first place. The other
5429 // elements come from the other positions of the first source vector
5430 Mask.push_back(NumElems);
5431 for (unsigned i = 1; i != NumElems; ++i) {
5436 case X86ISD::VPERM2X128:
5437 ImmN = N->getOperand(N->getNumOperands()-1);
5438 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5439 if (Mask.empty()) return false;
5441 case X86ISD::MOVSLDUP:
5442 DecodeMOVSLDUPMask(VT, Mask);
5444 case X86ISD::MOVSHDUP:
5445 DecodeMOVSHDUPMask(VT, Mask);
5447 case X86ISD::MOVDDUP:
5448 case X86ISD::MOVLHPD:
5449 case X86ISD::MOVLPD:
5450 case X86ISD::MOVLPS:
5451 // Not yet implemented
5453 default: llvm_unreachable("unknown target shuffle node");
5456 // If we have a fake unary shuffle, the shuffle mask is spread across two
5457 // inputs that are actually the same node. Re-map the mask to always point
5458 // into the first input.
5461 if (M >= (int)Mask.size())
5467 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5468 /// element of the result of the vector shuffle.
5469 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5472 return SDValue(); // Limit search depth.
5474 SDValue V = SDValue(N, 0);
5475 EVT VT = V.getValueType();
5476 unsigned Opcode = V.getOpcode();
5478 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5479 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5480 int Elt = SV->getMaskElt(Index);
5483 return DAG.getUNDEF(VT.getVectorElementType());
5485 unsigned NumElems = VT.getVectorNumElements();
5486 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5487 : SV->getOperand(1);
5488 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5491 // Recurse into target specific vector shuffles to find scalars.
5492 if (isTargetShuffle(Opcode)) {
5493 MVT ShufVT = V.getSimpleValueType();
5494 unsigned NumElems = ShufVT.getVectorNumElements();
5495 SmallVector<int, 16> ShuffleMask;
5498 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5501 int Elt = ShuffleMask[Index];
5503 return DAG.getUNDEF(ShufVT.getVectorElementType());
5505 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5507 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5511 // Actual nodes that may contain scalar elements
5512 if (Opcode == ISD::BITCAST) {
5513 V = V.getOperand(0);
5514 EVT SrcVT = V.getValueType();
5515 unsigned NumElems = VT.getVectorNumElements();
5517 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5521 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5522 return (Index == 0) ? V.getOperand(0)
5523 : DAG.getUNDEF(VT.getVectorElementType());
5525 if (V.getOpcode() == ISD::BUILD_VECTOR)
5526 return V.getOperand(Index);
5531 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5532 /// shuffle operation which come from a consecutively from a zero. The
5533 /// search can start in two different directions, from left or right.
5534 /// We count undefs as zeros until PreferredNum is reached.
5535 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5536 unsigned NumElems, bool ZerosFromLeft,
5538 unsigned PreferredNum = -1U) {
5539 unsigned NumZeros = 0;
5540 for (unsigned i = 0; i != NumElems; ++i) {
5541 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5542 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5546 if (X86::isZeroNode(Elt))
5548 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5549 NumZeros = std::min(NumZeros + 1, PreferredNum);
5557 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5558 /// correspond consecutively to elements from one of the vector operands,
5559 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5561 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5562 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5563 unsigned NumElems, unsigned &OpNum) {
5564 bool SeenV1 = false;
5565 bool SeenV2 = false;
5567 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5568 int Idx = SVOp->getMaskElt(i);
5569 // Ignore undef indicies
5573 if (Idx < (int)NumElems)
5578 // Only accept consecutive elements from the same vector
5579 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5583 OpNum = SeenV1 ? 0 : 1;
5587 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5588 /// logical left shift of a vector.
5589 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5590 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5592 SVOp->getSimpleValueType(0).getVectorNumElements();
5593 unsigned NumZeros = getNumOfConsecutiveZeros(
5594 SVOp, NumElems, false /* check zeros from right */, DAG,
5595 SVOp->getMaskElt(0));
5601 // Considering the elements in the mask that are not consecutive zeros,
5602 // check if they consecutively come from only one of the source vectors.
5604 // V1 = {X, A, B, C} 0
5606 // vector_shuffle V1, V2 <1, 2, 3, X>
5608 if (!isShuffleMaskConsecutive(SVOp,
5609 0, // Mask Start Index
5610 NumElems-NumZeros, // Mask End Index(exclusive)
5611 NumZeros, // Where to start looking in the src vector
5612 NumElems, // Number of elements in vector
5613 OpSrc)) // Which source operand ?
5618 ShVal = SVOp->getOperand(OpSrc);
5622 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5623 /// logical left shift of a vector.
5624 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5625 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5627 SVOp->getSimpleValueType(0).getVectorNumElements();
5628 unsigned NumZeros = getNumOfConsecutiveZeros(
5629 SVOp, NumElems, true /* check zeros from left */, DAG,
5630 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5636 // Considering the elements in the mask that are not consecutive zeros,
5637 // check if they consecutively come from only one of the source vectors.
5639 // 0 { A, B, X, X } = V2
5641 // vector_shuffle V1, V2 <X, X, 4, 5>
5643 if (!isShuffleMaskConsecutive(SVOp,
5644 NumZeros, // Mask Start Index
5645 NumElems, // Mask End Index(exclusive)
5646 0, // Where to start looking in the src vector
5647 NumElems, // Number of elements in vector
5648 OpSrc)) // Which source operand ?
5653 ShVal = SVOp->getOperand(OpSrc);
5657 /// isVectorShift - Returns true if the shuffle can be implemented as a
5658 /// logical left or right shift of a vector.
5659 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5660 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5661 // Although the logic below support any bitwidth size, there are no
5662 // shift instructions which handle more than 128-bit vectors.
5663 if (!SVOp->getSimpleValueType(0).is128BitVector())
5666 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5667 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5673 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5675 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5676 unsigned NumNonZero, unsigned NumZero,
5678 const X86Subtarget* Subtarget,
5679 const TargetLowering &TLI) {
5686 for (unsigned i = 0; i < 16; ++i) {
5687 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5688 if (ThisIsNonZero && First) {
5690 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5692 V = DAG.getUNDEF(MVT::v8i16);
5697 SDValue ThisElt, LastElt;
5698 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5699 if (LastIsNonZero) {
5700 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5701 MVT::i16, Op.getOperand(i-1));
5703 if (ThisIsNonZero) {
5704 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5705 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5706 ThisElt, DAG.getConstant(8, MVT::i8));
5708 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5712 if (ThisElt.getNode())
5713 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5714 DAG.getIntPtrConstant(i/2));
5718 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5721 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5723 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5724 unsigned NumNonZero, unsigned NumZero,
5726 const X86Subtarget* Subtarget,
5727 const TargetLowering &TLI) {
5734 for (unsigned i = 0; i < 8; ++i) {
5735 bool isNonZero = (NonZeros & (1 << i)) != 0;
5739 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5741 V = DAG.getUNDEF(MVT::v8i16);
5744 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5745 MVT::v8i16, V, Op.getOperand(i),
5746 DAG.getIntPtrConstant(i));
5753 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5754 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5755 const X86Subtarget *Subtarget,
5756 const TargetLowering &TLI) {
5757 // Find all zeroable elements.
5759 for (int i=0; i < 4; ++i) {
5760 SDValue Elt = Op->getOperand(i);
5761 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5763 assert(std::count_if(&Zeroable[0], &Zeroable[4],
5764 [](bool M) { return !M; }) > 1 &&
5765 "We expect at least two non-zero elements!");
5767 // We only know how to deal with build_vector nodes where elements are either
5768 // zeroable or extract_vector_elt with constant index.
5769 SDValue FirstNonZero;
5770 unsigned FirstNonZeroIdx;
5771 for (unsigned i=0; i < 4; ++i) {
5774 SDValue Elt = Op->getOperand(i);
5775 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5776 !isa<ConstantSDNode>(Elt.getOperand(1)))
5778 // Make sure that this node is extracting from a 128-bit vector.
5779 MVT VT = Elt.getOperand(0).getSimpleValueType();
5780 if (!VT.is128BitVector())
5782 if (!FirstNonZero.getNode()) {
5784 FirstNonZeroIdx = i;
5788 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5789 SDValue V1 = FirstNonZero.getOperand(0);
5790 MVT VT = V1.getSimpleValueType();
5792 // See if this build_vector can be lowered as a blend with zero.
5794 unsigned EltMaskIdx, EltIdx;
5796 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5797 if (Zeroable[EltIdx]) {
5798 // The zero vector will be on the right hand side.
5799 Mask[EltIdx] = EltIdx+4;
5803 Elt = Op->getOperand(EltIdx);
5804 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5805 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5806 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5808 Mask[EltIdx] = EltIdx;
5812 // Let the shuffle legalizer deal with blend operations.
5813 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5814 if (V1.getSimpleValueType() != VT)
5815 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5816 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5819 // See if we can lower this build_vector to a INSERTPS.
5820 if (!Subtarget->hasSSE41())
5823 SDValue V2 = Elt.getOperand(0);
5824 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5827 bool CanFold = true;
5828 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5832 SDValue Current = Op->getOperand(i);
5833 SDValue SrcVector = Current->getOperand(0);
5836 CanFold = SrcVector == V1 &&
5837 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5843 assert(V1.getNode() && "Expected at least two non-zero elements!");
5844 if (V1.getSimpleValueType() != MVT::v4f32)
5845 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5846 if (V2.getSimpleValueType() != MVT::v4f32)
5847 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5849 // Ok, we can emit an INSERTPS instruction.
5851 for (int i = 0; i < 4; ++i)
5855 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5856 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5857 SDValue Result = DAG.getNode(X86ISD::INSERTPS, SDLoc(Op), MVT::v4f32, V1, V2,
5858 DAG.getIntPtrConstant(InsertPSMask));
5859 return DAG.getNode(ISD::BITCAST, SDLoc(Op), VT, Result);
5862 /// getVShift - Return a vector logical shift node.
5864 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5865 unsigned NumBits, SelectionDAG &DAG,
5866 const TargetLowering &TLI, SDLoc dl) {
5867 assert(VT.is128BitVector() && "Unknown type for VShift");
5868 EVT ShVT = MVT::v2i64;
5869 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5870 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5871 return DAG.getNode(ISD::BITCAST, dl, VT,
5872 DAG.getNode(Opc, dl, ShVT, SrcOp,
5873 DAG.getConstant(NumBits,
5874 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5878 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5880 // Check if the scalar load can be widened into a vector load. And if
5881 // the address is "base + cst" see if the cst can be "absorbed" into
5882 // the shuffle mask.
5883 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5884 SDValue Ptr = LD->getBasePtr();
5885 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5887 EVT PVT = LD->getValueType(0);
5888 if (PVT != MVT::i32 && PVT != MVT::f32)
5893 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5894 FI = FINode->getIndex();
5896 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5897 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5898 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5899 Offset = Ptr.getConstantOperandVal(1);
5900 Ptr = Ptr.getOperand(0);
5905 // FIXME: 256-bit vector instructions don't require a strict alignment,
5906 // improve this code to support it better.
5907 unsigned RequiredAlign = VT.getSizeInBits()/8;
5908 SDValue Chain = LD->getChain();
5909 // Make sure the stack object alignment is at least 16 or 32.
5910 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5911 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5912 if (MFI->isFixedObjectIndex(FI)) {
5913 // Can't change the alignment. FIXME: It's possible to compute
5914 // the exact stack offset and reference FI + adjust offset instead.
5915 // If someone *really* cares about this. That's the way to implement it.
5918 MFI->setObjectAlignment(FI, RequiredAlign);
5922 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5923 // Ptr + (Offset & ~15).
5926 if ((Offset % RequiredAlign) & 3)
5928 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5930 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5931 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5933 int EltNo = (Offset - StartOffset) >> 2;
5934 unsigned NumElems = VT.getVectorNumElements();
5936 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5937 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5938 LD->getPointerInfo().getWithOffset(StartOffset),
5939 false, false, false, 0);
5941 SmallVector<int, 8> Mask;
5942 for (unsigned i = 0; i != NumElems; ++i)
5943 Mask.push_back(EltNo);
5945 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5951 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5952 /// vector of type 'VT', see if the elements can be replaced by a single large
5953 /// load which has the same value as a build_vector whose operands are 'elts'.
5955 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5957 /// FIXME: we'd also like to handle the case where the last elements are zero
5958 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5959 /// There's even a handy isZeroNode for that purpose.
5960 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5961 SDLoc &DL, SelectionDAG &DAG,
5962 bool isAfterLegalize) {
5963 EVT EltVT = VT.getVectorElementType();
5964 unsigned NumElems = Elts.size();
5966 LoadSDNode *LDBase = nullptr;
5967 unsigned LastLoadedElt = -1U;
5969 // For each element in the initializer, see if we've found a load or an undef.
5970 // If we don't find an initial load element, or later load elements are
5971 // non-consecutive, bail out.
5972 for (unsigned i = 0; i < NumElems; ++i) {
5973 SDValue Elt = Elts[i];
5975 if (!Elt.getNode() ||
5976 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5979 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5981 LDBase = cast<LoadSDNode>(Elt.getNode());
5985 if (Elt.getOpcode() == ISD::UNDEF)
5988 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5989 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5994 // If we have found an entire vector of loads and undefs, then return a large
5995 // load of the entire vector width starting at the base pointer. If we found
5996 // consecutive loads for the low half, generate a vzext_load node.
5997 if (LastLoadedElt == NumElems - 1) {
5999 if (isAfterLegalize &&
6000 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
6003 SDValue NewLd = SDValue();
6005 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
6006 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
6007 LDBase->getPointerInfo(),
6008 LDBase->isVolatile(), LDBase->isNonTemporal(),
6009 LDBase->isInvariant(), 0);
6010 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
6011 LDBase->getPointerInfo(),
6012 LDBase->isVolatile(), LDBase->isNonTemporal(),
6013 LDBase->isInvariant(), LDBase->getAlignment());
6015 if (LDBase->hasAnyUseOfValue(1)) {
6016 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6018 SDValue(NewLd.getNode(), 1));
6019 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6020 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6021 SDValue(NewLd.getNode(), 1));
6027 //TODO: The code below fires only for for loading the low v2i32 / v2f32
6028 //of a v4i32 / v4f32. It's probably worth generalizing.
6029 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
6030 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
6031 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
6032 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
6034 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
6035 LDBase->getPointerInfo(),
6036 LDBase->getAlignment(),
6037 false/*isVolatile*/, true/*ReadMem*/,
6040 // Make sure the newly-created LOAD is in the same position as LDBase in
6041 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
6042 // update uses of LDBase's output chain to use the TokenFactor.
6043 if (LDBase->hasAnyUseOfValue(1)) {
6044 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6045 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
6046 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6047 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6048 SDValue(ResNode.getNode(), 1));
6051 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6056 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6057 /// to generate a splat value for the following cases:
6058 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6059 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6060 /// a scalar load, or a constant.
6061 /// The VBROADCAST node is returned when a pattern is found,
6062 /// or SDValue() otherwise.
6063 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6064 SelectionDAG &DAG) {
6065 // VBROADCAST requires AVX.
6066 // TODO: Splats could be generated for non-AVX CPUs using SSE
6067 // instructions, but there's less potential gain for only 128-bit vectors.
6068 if (!Subtarget->hasAVX())
6071 MVT VT = Op.getSimpleValueType();
6074 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6075 "Unsupported vector type for broadcast.");
6080 switch (Op.getOpcode()) {
6082 // Unknown pattern found.
6085 case ISD::BUILD_VECTOR: {
6086 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6087 BitVector UndefElements;
6088 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6090 // We need a splat of a single value to use broadcast, and it doesn't
6091 // make any sense if the value is only in one element of the vector.
6092 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6096 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6097 Ld.getOpcode() == ISD::ConstantFP);
6099 // Make sure that all of the users of a non-constant load are from the
6100 // BUILD_VECTOR node.
6101 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6106 case ISD::VECTOR_SHUFFLE: {
6107 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6109 // Shuffles must have a splat mask where the first element is
6111 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6114 SDValue Sc = Op.getOperand(0);
6115 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6116 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6118 if (!Subtarget->hasInt256())
6121 // Use the register form of the broadcast instruction available on AVX2.
6122 if (VT.getSizeInBits() >= 256)
6123 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6124 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6127 Ld = Sc.getOperand(0);
6128 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6129 Ld.getOpcode() == ISD::ConstantFP);
6131 // The scalar_to_vector node and the suspected
6132 // load node must have exactly one user.
6133 // Constants may have multiple users.
6135 // AVX-512 has register version of the broadcast
6136 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6137 Ld.getValueType().getSizeInBits() >= 32;
6138 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6145 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6146 bool IsGE256 = (VT.getSizeInBits() >= 256);
6148 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6149 // instruction to save 8 or more bytes of constant pool data.
6150 // TODO: If multiple splats are generated to load the same constant,
6151 // it may be detrimental to overall size. There needs to be a way to detect
6152 // that condition to know if this is truly a size win.
6153 const Function *F = DAG.getMachineFunction().getFunction();
6154 bool OptForSize = F->getAttributes().
6155 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6157 // Handle broadcasting a single constant scalar from the constant pool
6159 // On Sandybridge (no AVX2), it is still better to load a constant vector
6160 // from the constant pool and not to broadcast it from a scalar.
6161 // But override that restriction when optimizing for size.
6162 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6163 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6164 EVT CVT = Ld.getValueType();
6165 assert(!CVT.isVector() && "Must not broadcast a vector type");
6167 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6168 // For size optimization, also splat v2f64 and v2i64, and for size opt
6169 // with AVX2, also splat i8 and i16.
6170 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6171 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6172 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6173 const Constant *C = nullptr;
6174 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6175 C = CI->getConstantIntValue();
6176 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6177 C = CF->getConstantFPValue();
6179 assert(C && "Invalid constant type");
6181 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6182 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6183 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6184 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6185 MachinePointerInfo::getConstantPool(),
6186 false, false, false, Alignment);
6188 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6192 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6194 // Handle AVX2 in-register broadcasts.
6195 if (!IsLoad && Subtarget->hasInt256() &&
6196 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6197 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6199 // The scalar source must be a normal load.
6203 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6204 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6206 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6207 // double since there is no vbroadcastsd xmm
6208 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6209 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6210 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6213 // Unsupported broadcast.
6217 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6218 /// underlying vector and index.
6220 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6222 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6224 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6225 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6228 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6230 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6232 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6233 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6236 // In this case the vector is the extract_subvector expression and the index
6237 // is 2, as specified by the shuffle.
6238 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6239 SDValue ShuffleVec = SVOp->getOperand(0);
6240 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6241 assert(ShuffleVecVT.getVectorElementType() ==
6242 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6244 int ShuffleIdx = SVOp->getMaskElt(Idx);
6245 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6246 ExtractedFromVec = ShuffleVec;
6252 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6253 MVT VT = Op.getSimpleValueType();
6255 // Skip if insert_vec_elt is not supported.
6256 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6257 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6261 unsigned NumElems = Op.getNumOperands();
6265 SmallVector<unsigned, 4> InsertIndices;
6266 SmallVector<int, 8> Mask(NumElems, -1);
6268 for (unsigned i = 0; i != NumElems; ++i) {
6269 unsigned Opc = Op.getOperand(i).getOpcode();
6271 if (Opc == ISD::UNDEF)
6274 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6275 // Quit if more than 1 elements need inserting.
6276 if (InsertIndices.size() > 1)
6279 InsertIndices.push_back(i);
6283 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6284 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6285 // Quit if non-constant index.
6286 if (!isa<ConstantSDNode>(ExtIdx))
6288 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6290 // Quit if extracted from vector of different type.
6291 if (ExtractedFromVec.getValueType() != VT)
6294 if (!VecIn1.getNode())
6295 VecIn1 = ExtractedFromVec;
6296 else if (VecIn1 != ExtractedFromVec) {
6297 if (!VecIn2.getNode())
6298 VecIn2 = ExtractedFromVec;
6299 else if (VecIn2 != ExtractedFromVec)
6300 // Quit if more than 2 vectors to shuffle
6304 if (ExtractedFromVec == VecIn1)
6306 else if (ExtractedFromVec == VecIn2)
6307 Mask[i] = Idx + NumElems;
6310 if (!VecIn1.getNode())
6313 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6314 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6315 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6316 unsigned Idx = InsertIndices[i];
6317 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6318 DAG.getIntPtrConstant(Idx));
6324 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6326 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6328 MVT VT = Op.getSimpleValueType();
6329 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6330 "Unexpected type in LowerBUILD_VECTORvXi1!");
6333 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6334 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6335 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6336 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6339 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6340 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6341 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6342 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6345 bool AllContants = true;
6346 uint64_t Immediate = 0;
6347 int NonConstIdx = -1;
6348 bool IsSplat = true;
6349 unsigned NumNonConsts = 0;
6350 unsigned NumConsts = 0;
6351 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6352 SDValue In = Op.getOperand(idx);
6353 if (In.getOpcode() == ISD::UNDEF)
6355 if (!isa<ConstantSDNode>(In)) {
6356 AllContants = false;
6361 if (cast<ConstantSDNode>(In)->getZExtValue())
6362 Immediate |= (1ULL << idx);
6364 if (In != Op.getOperand(0))
6369 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6370 DAG.getConstant(Immediate, MVT::i16));
6371 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6372 DAG.getIntPtrConstant(0));
6375 if (NumNonConsts == 1 && NonConstIdx != 0) {
6378 SDValue VecAsImm = DAG.getConstant(Immediate,
6379 MVT::getIntegerVT(VT.getSizeInBits()));
6380 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6383 DstVec = DAG.getUNDEF(VT);
6384 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6385 Op.getOperand(NonConstIdx),
6386 DAG.getIntPtrConstant(NonConstIdx));
6388 if (!IsSplat && (NonConstIdx != 0))
6389 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6390 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6393 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6394 DAG.getConstant(-1, SelectVT),
6395 DAG.getConstant(0, SelectVT));
6397 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6398 DAG.getConstant((Immediate | 1), SelectVT),
6399 DAG.getConstant(Immediate, SelectVT));
6400 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6403 /// \brief Return true if \p N implements a horizontal binop and return the
6404 /// operands for the horizontal binop into V0 and V1.
6406 /// This is a helper function of PerformBUILD_VECTORCombine.
6407 /// This function checks that the build_vector \p N in input implements a
6408 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6409 /// operation to match.
6410 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6411 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6412 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6415 /// This function only analyzes elements of \p N whose indices are
6416 /// in range [BaseIdx, LastIdx).
6417 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6419 unsigned BaseIdx, unsigned LastIdx,
6420 SDValue &V0, SDValue &V1) {
6421 EVT VT = N->getValueType(0);
6423 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6424 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6425 "Invalid Vector in input!");
6427 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6428 bool CanFold = true;
6429 unsigned ExpectedVExtractIdx = BaseIdx;
6430 unsigned NumElts = LastIdx - BaseIdx;
6431 V0 = DAG.getUNDEF(VT);
6432 V1 = DAG.getUNDEF(VT);
6434 // Check if N implements a horizontal binop.
6435 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6436 SDValue Op = N->getOperand(i + BaseIdx);
6439 if (Op->getOpcode() == ISD::UNDEF) {
6440 // Update the expected vector extract index.
6441 if (i * 2 == NumElts)
6442 ExpectedVExtractIdx = BaseIdx;
6443 ExpectedVExtractIdx += 2;
6447 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6452 SDValue Op0 = Op.getOperand(0);
6453 SDValue Op1 = Op.getOperand(1);
6455 // Try to match the following pattern:
6456 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6457 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6458 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6459 Op0.getOperand(0) == Op1.getOperand(0) &&
6460 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6461 isa<ConstantSDNode>(Op1.getOperand(1)));
6465 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6466 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6468 if (i * 2 < NumElts) {
6469 if (V0.getOpcode() == ISD::UNDEF)
6470 V0 = Op0.getOperand(0);
6472 if (V1.getOpcode() == ISD::UNDEF)
6473 V1 = Op0.getOperand(0);
6474 if (i * 2 == NumElts)
6475 ExpectedVExtractIdx = BaseIdx;
6478 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6479 if (I0 == ExpectedVExtractIdx)
6480 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6481 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6482 // Try to match the following dag sequence:
6483 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6484 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6488 ExpectedVExtractIdx += 2;
6494 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6495 /// a concat_vector.
6497 /// This is a helper function of PerformBUILD_VECTORCombine.
6498 /// This function expects two 256-bit vectors called V0 and V1.
6499 /// At first, each vector is split into two separate 128-bit vectors.
6500 /// Then, the resulting 128-bit vectors are used to implement two
6501 /// horizontal binary operations.
6503 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6505 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6506 /// the two new horizontal binop.
6507 /// When Mode is set, the first horizontal binop dag node would take as input
6508 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6509 /// horizontal binop dag node would take as input the lower 128-bit of V1
6510 /// and the upper 128-bit of V1.
6512 /// HADD V0_LO, V0_HI
6513 /// HADD V1_LO, V1_HI
6515 /// Otherwise, the first horizontal binop dag node takes as input the lower
6516 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6517 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6519 /// HADD V0_LO, V1_LO
6520 /// HADD V0_HI, V1_HI
6522 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6523 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6524 /// the upper 128-bits of the result.
6525 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6526 SDLoc DL, SelectionDAG &DAG,
6527 unsigned X86Opcode, bool Mode,
6528 bool isUndefLO, bool isUndefHI) {
6529 EVT VT = V0.getValueType();
6530 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6531 "Invalid nodes in input!");
6533 unsigned NumElts = VT.getVectorNumElements();
6534 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6535 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6536 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6537 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6538 EVT NewVT = V0_LO.getValueType();
6540 SDValue LO = DAG.getUNDEF(NewVT);
6541 SDValue HI = DAG.getUNDEF(NewVT);
6544 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6545 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6546 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6547 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6548 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6550 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6551 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6552 V1_LO->getOpcode() != ISD::UNDEF))
6553 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6555 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6556 V1_HI->getOpcode() != ISD::UNDEF))
6557 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6560 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6563 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6564 /// sequence of 'vadd + vsub + blendi'.
6565 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6566 const X86Subtarget *Subtarget) {
6568 EVT VT = BV->getValueType(0);
6569 unsigned NumElts = VT.getVectorNumElements();
6570 SDValue InVec0 = DAG.getUNDEF(VT);
6571 SDValue InVec1 = DAG.getUNDEF(VT);
6573 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6574 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6576 // Odd-numbered elements in the input build vector are obtained from
6577 // adding two integer/float elements.
6578 // Even-numbered elements in the input build vector are obtained from
6579 // subtracting two integer/float elements.
6580 unsigned ExpectedOpcode = ISD::FSUB;
6581 unsigned NextExpectedOpcode = ISD::FADD;
6582 bool AddFound = false;
6583 bool SubFound = false;
6585 for (unsigned i = 0, e = NumElts; i != e; i++) {
6586 SDValue Op = BV->getOperand(i);
6588 // Skip 'undef' values.
6589 unsigned Opcode = Op.getOpcode();
6590 if (Opcode == ISD::UNDEF) {
6591 std::swap(ExpectedOpcode, NextExpectedOpcode);
6595 // Early exit if we found an unexpected opcode.
6596 if (Opcode != ExpectedOpcode)
6599 SDValue Op0 = Op.getOperand(0);
6600 SDValue Op1 = Op.getOperand(1);
6602 // Try to match the following pattern:
6603 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6604 // Early exit if we cannot match that sequence.
6605 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6606 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6607 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6608 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6609 Op0.getOperand(1) != Op1.getOperand(1))
6612 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6616 // We found a valid add/sub node. Update the information accordingly.
6622 // Update InVec0 and InVec1.
6623 if (InVec0.getOpcode() == ISD::UNDEF)
6624 InVec0 = Op0.getOperand(0);
6625 if (InVec1.getOpcode() == ISD::UNDEF)
6626 InVec1 = Op1.getOperand(0);
6628 // Make sure that operands in input to each add/sub node always
6629 // come from a same pair of vectors.
6630 if (InVec0 != Op0.getOperand(0)) {
6631 if (ExpectedOpcode == ISD::FSUB)
6634 // FADD is commutable. Try to commute the operands
6635 // and then test again.
6636 std::swap(Op0, Op1);
6637 if (InVec0 != Op0.getOperand(0))
6641 if (InVec1 != Op1.getOperand(0))
6644 // Update the pair of expected opcodes.
6645 std::swap(ExpectedOpcode, NextExpectedOpcode);
6648 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6649 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6650 InVec1.getOpcode() != ISD::UNDEF)
6651 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6656 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6657 const X86Subtarget *Subtarget) {
6659 EVT VT = N->getValueType(0);
6660 unsigned NumElts = VT.getVectorNumElements();
6661 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6662 SDValue InVec0, InVec1;
6664 // Try to match an ADDSUB.
6665 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6666 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6667 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6668 if (Value.getNode())
6672 // Try to match horizontal ADD/SUB.
6673 unsigned NumUndefsLO = 0;
6674 unsigned NumUndefsHI = 0;
6675 unsigned Half = NumElts/2;
6677 // Count the number of UNDEF operands in the build_vector in input.
6678 for (unsigned i = 0, e = Half; i != e; ++i)
6679 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6682 for (unsigned i = Half, e = NumElts; i != e; ++i)
6683 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6686 // Early exit if this is either a build_vector of all UNDEFs or all the
6687 // operands but one are UNDEF.
6688 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6691 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6692 // Try to match an SSE3 float HADD/HSUB.
6693 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6694 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6696 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6697 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6698 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6699 // Try to match an SSSE3 integer HADD/HSUB.
6700 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6701 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6703 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6704 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6707 if (!Subtarget->hasAVX())
6710 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6711 // Try to match an AVX horizontal add/sub of packed single/double
6712 // precision floating point values from 256-bit vectors.
6713 SDValue InVec2, InVec3;
6714 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6715 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6716 ((InVec0.getOpcode() == ISD::UNDEF ||
6717 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6718 ((InVec1.getOpcode() == ISD::UNDEF ||
6719 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6720 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6722 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6723 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6724 ((InVec0.getOpcode() == ISD::UNDEF ||
6725 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6726 ((InVec1.getOpcode() == ISD::UNDEF ||
6727 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6728 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6729 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6730 // Try to match an AVX2 horizontal add/sub of signed integers.
6731 SDValue InVec2, InVec3;
6733 bool CanFold = true;
6735 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6736 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6737 ((InVec0.getOpcode() == ISD::UNDEF ||
6738 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6739 ((InVec1.getOpcode() == ISD::UNDEF ||
6740 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6741 X86Opcode = X86ISD::HADD;
6742 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6743 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6744 ((InVec0.getOpcode() == ISD::UNDEF ||
6745 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6746 ((InVec1.getOpcode() == ISD::UNDEF ||
6747 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6748 X86Opcode = X86ISD::HSUB;
6753 // Fold this build_vector into a single horizontal add/sub.
6754 // Do this only if the target has AVX2.
6755 if (Subtarget->hasAVX2())
6756 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6758 // Do not try to expand this build_vector into a pair of horizontal
6759 // add/sub if we can emit a pair of scalar add/sub.
6760 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6763 // Convert this build_vector into a pair of horizontal binop followed by
6765 bool isUndefLO = NumUndefsLO == Half;
6766 bool isUndefHI = NumUndefsHI == Half;
6767 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6768 isUndefLO, isUndefHI);
6772 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6773 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6775 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6776 X86Opcode = X86ISD::HADD;
6777 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6778 X86Opcode = X86ISD::HSUB;
6779 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6780 X86Opcode = X86ISD::FHADD;
6781 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6782 X86Opcode = X86ISD::FHSUB;
6786 // Don't try to expand this build_vector into a pair of horizontal add/sub
6787 // if we can simply emit a pair of scalar add/sub.
6788 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6791 // Convert this build_vector into two horizontal add/sub followed by
6793 bool isUndefLO = NumUndefsLO == Half;
6794 bool isUndefHI = NumUndefsHI == Half;
6795 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6796 isUndefLO, isUndefHI);
6803 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6806 MVT VT = Op.getSimpleValueType();
6807 MVT ExtVT = VT.getVectorElementType();
6808 unsigned NumElems = Op.getNumOperands();
6810 // Generate vectors for predicate vectors.
6811 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6812 return LowerBUILD_VECTORvXi1(Op, DAG);
6814 // Vectors containing all zeros can be matched by pxor and xorps later
6815 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6816 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6817 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6818 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6821 return getZeroVector(VT, Subtarget, DAG, dl);
6824 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6825 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6826 // vpcmpeqd on 256-bit vectors.
6827 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6828 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6831 if (!VT.is512BitVector())
6832 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6835 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6836 if (Broadcast.getNode())
6839 unsigned EVTBits = ExtVT.getSizeInBits();
6841 unsigned NumZero = 0;
6842 unsigned NumNonZero = 0;
6843 unsigned NonZeros = 0;
6844 bool IsAllConstants = true;
6845 SmallSet<SDValue, 8> Values;
6846 for (unsigned i = 0; i < NumElems; ++i) {
6847 SDValue Elt = Op.getOperand(i);
6848 if (Elt.getOpcode() == ISD::UNDEF)
6851 if (Elt.getOpcode() != ISD::Constant &&
6852 Elt.getOpcode() != ISD::ConstantFP)
6853 IsAllConstants = false;
6854 if (X86::isZeroNode(Elt))
6857 NonZeros |= (1 << i);
6862 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6863 if (NumNonZero == 0)
6864 return DAG.getUNDEF(VT);
6866 // Special case for single non-zero, non-undef, element.
6867 if (NumNonZero == 1) {
6868 unsigned Idx = countTrailingZeros(NonZeros);
6869 SDValue Item = Op.getOperand(Idx);
6871 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6872 // the value are obviously zero, truncate the value to i32 and do the
6873 // insertion that way. Only do this if the value is non-constant or if the
6874 // value is a constant being inserted into element 0. It is cheaper to do
6875 // a constant pool load than it is to do a movd + shuffle.
6876 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6877 (!IsAllConstants || Idx == 0)) {
6878 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6880 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6881 EVT VecVT = MVT::v4i32;
6882 unsigned VecElts = 4;
6884 // Truncate the value (which may itself be a constant) to i32, and
6885 // convert it to a vector with movd (S2V+shuffle to zero extend).
6886 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6887 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6889 // If using the new shuffle lowering, just directly insert this.
6890 if (ExperimentalVectorShuffleLowering)
6892 ISD::BITCAST, dl, VT,
6893 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6895 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6897 // Now we have our 32-bit value zero extended in the low element of
6898 // a vector. If Idx != 0, swizzle it into place.
6900 SmallVector<int, 4> Mask;
6901 Mask.push_back(Idx);
6902 for (unsigned i = 1; i != VecElts; ++i)
6904 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6907 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6911 // If we have a constant or non-constant insertion into the low element of
6912 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6913 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6914 // depending on what the source datatype is.
6917 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6919 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6920 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6921 if (VT.is256BitVector() || VT.is512BitVector()) {
6922 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6923 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6924 Item, DAG.getIntPtrConstant(0));
6926 assert(VT.is128BitVector() && "Expected an SSE value type!");
6927 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6928 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6929 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6932 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6933 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6934 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6935 if (VT.is256BitVector()) {
6936 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6937 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6939 assert(VT.is128BitVector() && "Expected an SSE value type!");
6940 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6942 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6946 // Is it a vector logical left shift?
6947 if (NumElems == 2 && Idx == 1 &&
6948 X86::isZeroNode(Op.getOperand(0)) &&
6949 !X86::isZeroNode(Op.getOperand(1))) {
6950 unsigned NumBits = VT.getSizeInBits();
6951 return getVShift(true, VT,
6952 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6953 VT, Op.getOperand(1)),
6954 NumBits/2, DAG, *this, dl);
6957 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6960 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6961 // is a non-constant being inserted into an element other than the low one,
6962 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6963 // movd/movss) to move this into the low element, then shuffle it into
6965 if (EVTBits == 32) {
6966 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6968 // If using the new shuffle lowering, just directly insert this.
6969 if (ExperimentalVectorShuffleLowering)
6970 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6972 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6973 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6974 SmallVector<int, 8> MaskVec;
6975 for (unsigned i = 0; i != NumElems; ++i)
6976 MaskVec.push_back(i == Idx ? 0 : 1);
6977 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6981 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6982 if (Values.size() == 1) {
6983 if (EVTBits == 32) {
6984 // Instead of a shuffle like this:
6985 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6986 // Check if it's possible to issue this instead.
6987 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6988 unsigned Idx = countTrailingZeros(NonZeros);
6989 SDValue Item = Op.getOperand(Idx);
6990 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6991 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6996 // A vector full of immediates; various special cases are already
6997 // handled, so this is best done with a single constant-pool load.
7001 // For AVX-length vectors, see if we can use a vector load to get all of the
7002 // elements, otherwise build the individual 128-bit pieces and use
7003 // shuffles to put them in place.
7004 if (VT.is256BitVector() || VT.is512BitVector()) {
7005 SmallVector<SDValue, 64> V;
7006 for (unsigned i = 0; i != NumElems; ++i)
7007 V.push_back(Op.getOperand(i));
7009 // Check for a build vector of consecutive loads.
7010 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
7013 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
7015 // Build both the lower and upper subvector.
7016 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7017 makeArrayRef(&V[0], NumElems/2));
7018 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7019 makeArrayRef(&V[NumElems / 2], NumElems/2));
7021 // Recreate the wider vector with the lower and upper part.
7022 if (VT.is256BitVector())
7023 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7024 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7027 // Let legalizer expand 2-wide build_vectors.
7028 if (EVTBits == 64) {
7029 if (NumNonZero == 1) {
7030 // One half is zero or undef.
7031 unsigned Idx = countTrailingZeros(NonZeros);
7032 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
7033 Op.getOperand(Idx));
7034 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
7039 // If element VT is < 32 bits, convert it to inserts into a zero vector.
7040 if (EVTBits == 8 && NumElems == 16) {
7041 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
7043 if (V.getNode()) return V;
7046 if (EVTBits == 16 && NumElems == 8) {
7047 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
7049 if (V.getNode()) return V;
7052 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
7053 if (EVTBits == 32 && NumElems == 4) {
7054 SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this);
7059 // If element VT is == 32 bits, turn it into a number of shuffles.
7060 SmallVector<SDValue, 8> V(NumElems);
7061 if (NumElems == 4 && NumZero > 0) {
7062 for (unsigned i = 0; i < 4; ++i) {
7063 bool isZero = !(NonZeros & (1 << i));
7065 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7067 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7070 for (unsigned i = 0; i < 2; ++i) {
7071 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7074 V[i] = V[i*2]; // Must be a zero vector.
7077 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7080 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7083 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7088 bool Reverse1 = (NonZeros & 0x3) == 2;
7089 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7093 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7094 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7096 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7099 if (Values.size() > 1 && VT.is128BitVector()) {
7100 // Check for a build vector of consecutive loads.
7101 for (unsigned i = 0; i < NumElems; ++i)
7102 V[i] = Op.getOperand(i);
7104 // Check for elements which are consecutive loads.
7105 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7109 // Check for a build vector from mostly shuffle plus few inserting.
7110 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7114 // For SSE 4.1, use insertps to put the high elements into the low element.
7115 if (getSubtarget()->hasSSE41()) {
7117 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7118 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7120 Result = DAG.getUNDEF(VT);
7122 for (unsigned i = 1; i < NumElems; ++i) {
7123 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7124 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7125 Op.getOperand(i), DAG.getIntPtrConstant(i));
7130 // Otherwise, expand into a number of unpckl*, start by extending each of
7131 // our (non-undef) elements to the full vector width with the element in the
7132 // bottom slot of the vector (which generates no code for SSE).
7133 for (unsigned i = 0; i < NumElems; ++i) {
7134 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7135 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7137 V[i] = DAG.getUNDEF(VT);
7140 // Next, we iteratively mix elements, e.g. for v4f32:
7141 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7142 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7143 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7144 unsigned EltStride = NumElems >> 1;
7145 while (EltStride != 0) {
7146 for (unsigned i = 0; i < EltStride; ++i) {
7147 // If V[i+EltStride] is undef and this is the first round of mixing,
7148 // then it is safe to just drop this shuffle: V[i] is already in the
7149 // right place, the one element (since it's the first round) being
7150 // inserted as undef can be dropped. This isn't safe for successive
7151 // rounds because they will permute elements within both vectors.
7152 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7153 EltStride == NumElems/2)
7156 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7165 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7166 // to create 256-bit vectors from two other 128-bit ones.
7167 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7169 MVT ResVT = Op.getSimpleValueType();
7171 assert((ResVT.is256BitVector() ||
7172 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7174 SDValue V1 = Op.getOperand(0);
7175 SDValue V2 = Op.getOperand(1);
7176 unsigned NumElems = ResVT.getVectorNumElements();
7177 if(ResVT.is256BitVector())
7178 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7180 if (Op.getNumOperands() == 4) {
7181 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7182 ResVT.getVectorNumElements()/2);
7183 SDValue V3 = Op.getOperand(2);
7184 SDValue V4 = Op.getOperand(3);
7185 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7186 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7188 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7191 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7192 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7193 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7194 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7195 Op.getNumOperands() == 4)));
7197 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7198 // from two other 128-bit ones.
7200 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7201 return LowerAVXCONCAT_VECTORS(Op, DAG);
7205 //===----------------------------------------------------------------------===//
7206 // Vector shuffle lowering
7208 // This is an experimental code path for lowering vector shuffles on x86. It is
7209 // designed to handle arbitrary vector shuffles and blends, gracefully
7210 // degrading performance as necessary. It works hard to recognize idiomatic
7211 // shuffles and lower them to optimal instruction patterns without leaving
7212 // a framework that allows reasonably efficient handling of all vector shuffle
7214 //===----------------------------------------------------------------------===//
7216 /// \brief Tiny helper function to identify a no-op mask.
7218 /// This is a somewhat boring predicate function. It checks whether the mask
7219 /// array input, which is assumed to be a single-input shuffle mask of the kind
7220 /// used by the X86 shuffle instructions (not a fully general
7221 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7222 /// in-place shuffle are 'no-op's.
7223 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7224 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7225 if (Mask[i] != -1 && Mask[i] != i)
7230 /// \brief Helper function to classify a mask as a single-input mask.
7232 /// This isn't a generic single-input test because in the vector shuffle
7233 /// lowering we canonicalize single inputs to be the first input operand. This
7234 /// means we can more quickly test for a single input by only checking whether
7235 /// an input from the second operand exists. We also assume that the size of
7236 /// mask corresponds to the size of the input vectors which isn't true in the
7237 /// fully general case.
7238 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7240 if (M >= (int)Mask.size())
7245 /// \brief Test whether there are elements crossing 128-bit lanes in this
7248 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7249 /// and we routinely test for these.
7250 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7251 int LaneSize = 128 / VT.getScalarSizeInBits();
7252 int Size = Mask.size();
7253 for (int i = 0; i < Size; ++i)
7254 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7259 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7261 /// This checks a shuffle mask to see if it is performing the same
7262 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7263 /// that it is also not lane-crossing. It may however involve a blend from the
7264 /// same lane of a second vector.
7266 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7267 /// non-trivial to compute in the face of undef lanes. The representation is
7268 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7269 /// entries from both V1 and V2 inputs to the wider mask.
7271 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7272 SmallVectorImpl<int> &RepeatedMask) {
7273 int LaneSize = 128 / VT.getScalarSizeInBits();
7274 RepeatedMask.resize(LaneSize, -1);
7275 int Size = Mask.size();
7276 for (int i = 0; i < Size; ++i) {
7279 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7280 // This entry crosses lanes, so there is no way to model this shuffle.
7283 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7284 if (RepeatedMask[i % LaneSize] == -1)
7285 // This is the first non-undef entry in this slot of a 128-bit lane.
7286 RepeatedMask[i % LaneSize] =
7287 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7288 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7289 // Found a mismatch with the repeated mask.
7295 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7296 // 2013 will allow us to use it as a non-type template parameter.
7299 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7301 /// See its documentation for details.
7302 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7303 if (Mask.size() != Args.size())
7305 for (int i = 0, e = Mask.size(); i < e; ++i) {
7306 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7307 if (Mask[i] != -1 && Mask[i] != *Args[i])
7315 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7318 /// This is a fast way to test a shuffle mask against a fixed pattern:
7320 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7322 /// It returns true if the mask is exactly as wide as the argument list, and
7323 /// each element of the mask is either -1 (signifying undef) or the value given
7324 /// in the argument.
7325 static const VariadicFunction1<
7326 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7328 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7330 /// This helper function produces an 8-bit shuffle immediate corresponding to
7331 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7332 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7335 /// NB: We rely heavily on "undef" masks preserving the input lane.
7336 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7337 SelectionDAG &DAG) {
7338 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7339 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7340 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7341 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7342 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7345 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7346 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7347 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7348 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7349 return DAG.getConstant(Imm, MVT::i8);
7352 /// \brief Try to emit a blend instruction for a shuffle.
7354 /// This doesn't do any checks for the availability of instructions for blending
7355 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7356 /// be matched in the backend with the type given. What it does check for is
7357 /// that the shuffle mask is in fact a blend.
7358 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7359 SDValue V2, ArrayRef<int> Mask,
7360 const X86Subtarget *Subtarget,
7361 SelectionDAG &DAG) {
7363 unsigned BlendMask = 0;
7364 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7365 if (Mask[i] >= Size) {
7366 if (Mask[i] != i + Size)
7367 return SDValue(); // Shuffled V2 input!
7368 BlendMask |= 1u << i;
7371 if (Mask[i] >= 0 && Mask[i] != i)
7372 return SDValue(); // Shuffled V1 input!
7374 switch (VT.SimpleTy) {
7379 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7380 DAG.getConstant(BlendMask, MVT::i8));
7384 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7388 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7389 // that instruction.
7390 if (Subtarget->hasAVX2()) {
7391 // Scale the blend by the number of 32-bit dwords per element.
7392 int Scale = VT.getScalarSizeInBits() / 32;
7394 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7395 if (Mask[i] >= Size)
7396 for (int j = 0; j < Scale; ++j)
7397 BlendMask |= 1u << (i * Scale + j);
7399 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7400 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7401 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7402 return DAG.getNode(ISD::BITCAST, DL, VT,
7403 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7404 DAG.getConstant(BlendMask, MVT::i8)));
7408 // For integer shuffles we need to expand the mask and cast the inputs to
7409 // v8i16s prior to blending.
7410 int Scale = 8 / VT.getVectorNumElements();
7412 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7413 if (Mask[i] >= Size)
7414 for (int j = 0; j < Scale; ++j)
7415 BlendMask |= 1u << (i * Scale + j);
7417 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7418 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7419 return DAG.getNode(ISD::BITCAST, DL, VT,
7420 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7421 DAG.getConstant(BlendMask, MVT::i8)));
7425 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7426 SmallVector<int, 8> RepeatedMask;
7427 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7428 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7429 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7431 for (int i = 0; i < 8; ++i)
7432 if (RepeatedMask[i] >= 16)
7433 BlendMask |= 1u << i;
7434 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7435 DAG.getConstant(BlendMask, MVT::i8));
7440 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7441 // Scale the blend by the number of bytes per element.
7442 int Scale = VT.getScalarSizeInBits() / 8;
7443 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7445 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7446 // mix of LLVM's code generator and the x86 backend. We tell the code
7447 // generator that boolean values in the elements of an x86 vector register
7448 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7449 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7450 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7451 // of the element (the remaining are ignored) and 0 in that high bit would
7452 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7453 // the LLVM model for boolean values in vector elements gets the relevant
7454 // bit set, it is set backwards and over constrained relative to x86's
7456 SDValue VSELECTMask[32];
7457 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7458 for (int j = 0; j < Scale; ++j)
7459 VSELECTMask[Scale * i + j] =
7460 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7461 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7463 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7464 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7466 ISD::BITCAST, DL, VT,
7467 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7468 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7473 llvm_unreachable("Not a supported integer vector type!");
7477 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7478 /// unblended shuffles followed by an unshuffled blend.
7480 /// This matches the extremely common pattern for handling combined
7481 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7483 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7487 SelectionDAG &DAG) {
7488 // Shuffle the input elements into the desired positions in V1 and V2 and
7489 // blend them together.
7490 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7491 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7492 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7493 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7494 if (Mask[i] >= 0 && Mask[i] < Size) {
7495 V1Mask[i] = Mask[i];
7497 } else if (Mask[i] >= Size) {
7498 V2Mask[i] = Mask[i] - Size;
7499 BlendMask[i] = i + Size;
7502 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7503 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7504 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7507 /// \brief Try to lower a vector shuffle as a byte rotation.
7509 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7510 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7511 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7512 /// try to generically lower a vector shuffle through such an pattern. It
7513 /// does not check for the profitability of lowering either as PALIGNR or
7514 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7515 /// This matches shuffle vectors that look like:
7517 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7519 /// Essentially it concatenates V1 and V2, shifts right by some number of
7520 /// elements, and takes the low elements as the result. Note that while this is
7521 /// specified as a *right shift* because x86 is little-endian, it is a *left
7522 /// rotate* of the vector lanes.
7524 /// Note that this only handles 128-bit vector widths currently.
7525 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7528 const X86Subtarget *Subtarget,
7529 SelectionDAG &DAG) {
7530 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7532 // We need to detect various ways of spelling a rotation:
7533 // [11, 12, 13, 14, 15, 0, 1, 2]
7534 // [-1, 12, 13, 14, -1, -1, 1, -1]
7535 // [-1, -1, -1, -1, -1, -1, 1, 2]
7536 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7537 // [-1, 4, 5, 6, -1, -1, 9, -1]
7538 // [-1, 4, 5, 6, -1, -1, -1, -1]
7541 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7544 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7546 // Based on the mod-Size value of this mask element determine where
7547 // a rotated vector would have started.
7548 int StartIdx = i - (Mask[i] % Size);
7550 // The identity rotation isn't interesting, stop.
7553 // If we found the tail of a vector the rotation must be the missing
7554 // front. If we found the head of a vector, it must be how much of the head.
7555 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7558 Rotation = CandidateRotation;
7559 else if (Rotation != CandidateRotation)
7560 // The rotations don't match, so we can't match this mask.
7563 // Compute which value this mask is pointing at.
7564 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7566 // Compute which of the two target values this index should be assigned to.
7567 // This reflects whether the high elements are remaining or the low elements
7569 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7571 // Either set up this value if we've not encountered it before, or check
7572 // that it remains consistent.
7575 else if (TargetV != MaskV)
7576 // This may be a rotation, but it pulls from the inputs in some
7577 // unsupported interleaving.
7581 // Check that we successfully analyzed the mask, and normalize the results.
7582 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7583 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7589 assert(VT.getSizeInBits() == 128 &&
7590 "Rotate-based lowering only supports 128-bit lowering!");
7591 assert(Mask.size() <= 16 &&
7592 "Can shuffle at most 16 bytes in a 128-bit vector!");
7594 // The actual rotate instruction rotates bytes, so we need to scale the
7595 // rotation based on how many bytes are in the vector.
7596 int Scale = 16 / Mask.size();
7598 // SSSE3 targets can use the palignr instruction
7599 if (Subtarget->hasSSSE3()) {
7600 // Cast the inputs to v16i8 to match PALIGNR.
7601 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7602 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7604 return DAG.getNode(ISD::BITCAST, DL, VT,
7605 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7606 DAG.getConstant(Rotation * Scale, MVT::i8)));
7609 // Default SSE2 implementation
7610 int LoByteShift = 16 - Rotation * Scale;
7611 int HiByteShift = Rotation * Scale;
7613 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7614 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
7615 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
7617 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7618 DAG.getConstant(8 * LoByteShift, MVT::i8));
7619 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7620 DAG.getConstant(8 * HiByteShift, MVT::i8));
7621 return DAG.getNode(ISD::BITCAST, DL, VT,
7622 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7625 /// \brief Compute whether each element of a shuffle is zeroable.
7627 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7628 /// Either it is an undef element in the shuffle mask, the element of the input
7629 /// referenced is undef, or the element of the input referenced is known to be
7630 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7631 /// as many lanes with this technique as possible to simplify the remaining
7633 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7634 SDValue V1, SDValue V2) {
7635 SmallBitVector Zeroable(Mask.size(), false);
7637 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7638 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7640 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7642 // Handle the easy cases.
7643 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7648 // If this is an index into a build_vector node, dig out the input value and
7650 SDValue V = M < Size ? V1 : V2;
7651 if (V.getOpcode() != ISD::BUILD_VECTOR)
7654 SDValue Input = V.getOperand(M % Size);
7655 // The UNDEF opcode check really should be dead code here, but not quite
7656 // worth asserting on (it isn't invalid, just unexpected).
7657 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7664 /// \brief Try to lower a vector shuffle as a byte shift (shifts in zeros).
7666 /// Attempts to match a shuffle mask against the PSRLDQ and PSLLDQ SSE2
7667 /// byte-shift instructions. The mask must consist of a shifted sequential
7668 /// shuffle from one of the input vectors and zeroable elements for the
7669 /// remaining 'shifted in' elements.
7671 /// Note that this only handles 128-bit vector widths currently.
7672 static SDValue lowerVectorShuffleAsByteShift(SDLoc DL, MVT VT, SDValue V1,
7673 SDValue V2, ArrayRef<int> Mask,
7674 SelectionDAG &DAG) {
7675 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7677 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7679 int Size = Mask.size();
7680 int Scale = 16 / Size;
7682 auto isSequential = [](int Base, int StartIndex, int EndIndex, int MaskOffset,
7683 ArrayRef<int> Mask) {
7684 for (int i = StartIndex; i < EndIndex; i++) {
7687 if (i + Base != Mask[i] - MaskOffset)
7693 for (int Shift = 1; Shift < Size; Shift++) {
7694 int ByteShift = Shift * Scale;
7696 // PSRLDQ : (little-endian) right byte shift
7697 // [ 5, 6, 7, zz, zz, zz, zz, zz]
7698 // [ -1, 5, 6, 7, zz, zz, zz, zz]
7699 // [ 1, 2, -1, -1, -1, -1, zz, zz]
7700 bool ZeroableRight = true;
7701 for (int i = Size - Shift; i < Size; i++) {
7702 ZeroableRight &= Zeroable[i];
7705 if (ZeroableRight) {
7706 bool ValidShiftRight1 = isSequential(Shift, 0, Size - Shift, 0, Mask);
7707 bool ValidShiftRight2 = isSequential(Shift, 0, Size - Shift, Size, Mask);
7709 if (ValidShiftRight1 || ValidShiftRight2) {
7710 // Cast the inputs to v2i64 to match PSRLDQ.
7711 SDValue &TargetV = ValidShiftRight1 ? V1 : V2;
7712 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7713 SDValue Shifted = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, V,
7714 DAG.getConstant(ByteShift * 8, MVT::i8));
7715 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7719 // PSLLDQ : (little-endian) left byte shift
7720 // [ zz, 0, 1, 2, 3, 4, 5, 6]
7721 // [ zz, zz, -1, -1, 2, 3, 4, -1]
7722 // [ zz, zz, zz, zz, zz, zz, -1, 1]
7723 bool ZeroableLeft = true;
7724 for (int i = 0; i < Shift; i++) {
7725 ZeroableLeft &= Zeroable[i];
7729 bool ValidShiftLeft1 = isSequential(-Shift, Shift, Size, 0, Mask);
7730 bool ValidShiftLeft2 = isSequential(-Shift, Shift, Size, Size, Mask);
7732 if (ValidShiftLeft1 || ValidShiftLeft2) {
7733 // Cast the inputs to v2i64 to match PSLLDQ.
7734 SDValue &TargetV = ValidShiftLeft1 ? V1 : V2;
7735 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7736 SDValue Shifted = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, V,
7737 DAG.getConstant(ByteShift * 8, MVT::i8));
7738 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7746 /// \brief Lower a vector shuffle as a zero or any extension.
7748 /// Given a specific number of elements, element bit width, and extension
7749 /// stride, produce either a zero or any extension based on the available
7750 /// features of the subtarget.
7751 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7752 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7753 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7754 assert(Scale > 1 && "Need a scale to extend.");
7755 int EltBits = VT.getSizeInBits() / NumElements;
7756 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7757 "Only 8, 16, and 32 bit elements can be extended.");
7758 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7760 // Found a valid zext mask! Try various lowering strategies based on the
7761 // input type and available ISA extensions.
7762 if (Subtarget->hasSSE41()) {
7763 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7764 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7765 NumElements / Scale);
7766 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7767 return DAG.getNode(ISD::BITCAST, DL, VT,
7768 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7771 // For any extends we can cheat for larger element sizes and use shuffle
7772 // instructions that can fold with a load and/or copy.
7773 if (AnyExt && EltBits == 32) {
7774 int PSHUFDMask[4] = {0, -1, 1, -1};
7776 ISD::BITCAST, DL, VT,
7777 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7778 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7779 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7781 if (AnyExt && EltBits == 16 && Scale > 2) {
7782 int PSHUFDMask[4] = {0, -1, 0, -1};
7783 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7784 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7785 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7786 int PSHUFHWMask[4] = {1, -1, -1, -1};
7788 ISD::BITCAST, DL, VT,
7789 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7790 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7791 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7794 // If this would require more than 2 unpack instructions to expand, use
7795 // pshufb when available. We can only use more than 2 unpack instructions
7796 // when zero extending i8 elements which also makes it easier to use pshufb.
7797 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7798 assert(NumElements == 16 && "Unexpected byte vector width!");
7799 SDValue PSHUFBMask[16];
7800 for (int i = 0; i < 16; ++i)
7802 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7803 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7804 return DAG.getNode(ISD::BITCAST, DL, VT,
7805 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7806 DAG.getNode(ISD::BUILD_VECTOR, DL,
7807 MVT::v16i8, PSHUFBMask)));
7810 // Otherwise emit a sequence of unpacks.
7812 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7813 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7814 : getZeroVector(InputVT, Subtarget, DAG, DL);
7815 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7816 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7820 } while (Scale > 1);
7821 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7824 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7826 /// This routine will try to do everything in its power to cleverly lower
7827 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7828 /// check for the profitability of this lowering, it tries to aggressively
7829 /// match this pattern. It will use all of the micro-architectural details it
7830 /// can to emit an efficient lowering. It handles both blends with all-zero
7831 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7832 /// masking out later).
7834 /// The reason we have dedicated lowering for zext-style shuffles is that they
7835 /// are both incredibly common and often quite performance sensitive.
7836 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7837 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7838 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7839 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7841 int Bits = VT.getSizeInBits();
7842 int NumElements = Mask.size();
7844 // Define a helper function to check a particular ext-scale and lower to it if
7846 auto Lower = [&](int Scale) -> SDValue {
7849 for (int i = 0; i < NumElements; ++i) {
7851 continue; // Valid anywhere but doesn't tell us anything.
7852 if (i % Scale != 0) {
7853 // Each of the extend elements needs to be zeroable.
7857 // We no lorger are in the anyext case.
7862 // Each of the base elements needs to be consecutive indices into the
7863 // same input vector.
7864 SDValue V = Mask[i] < NumElements ? V1 : V2;
7867 else if (InputV != V)
7868 return SDValue(); // Flip-flopping inputs.
7870 if (Mask[i] % NumElements != i / Scale)
7871 return SDValue(); // Non-consecutive strided elemenst.
7874 // If we fail to find an input, we have a zero-shuffle which should always
7875 // have already been handled.
7876 // FIXME: Maybe handle this here in case during blending we end up with one?
7880 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7881 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7884 // The widest scale possible for extending is to a 64-bit integer.
7885 assert(Bits % 64 == 0 &&
7886 "The number of bits in a vector must be divisible by 64 on x86!");
7887 int NumExtElements = Bits / 64;
7889 // Each iteration, try extending the elements half as much, but into twice as
7891 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7892 assert(NumElements % NumExtElements == 0 &&
7893 "The input vector size must be divisble by the extended size.");
7894 if (SDValue V = Lower(NumElements / NumExtElements))
7898 // No viable ext lowering found.
7902 /// \brief Try to get a scalar value for a specific element of a vector.
7904 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7905 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7906 SelectionDAG &DAG) {
7907 MVT VT = V.getSimpleValueType();
7908 MVT EltVT = VT.getVectorElementType();
7909 while (V.getOpcode() == ISD::BITCAST)
7910 V = V.getOperand(0);
7911 // If the bitcasts shift the element size, we can't extract an equivalent
7913 MVT NewVT = V.getSimpleValueType();
7914 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7917 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7918 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
7919 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
7924 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7926 /// This is particularly important because the set of instructions varies
7927 /// significantly based on whether the operand is a load or not.
7928 static bool isShuffleFoldableLoad(SDValue V) {
7929 while (V.getOpcode() == ISD::BITCAST)
7930 V = V.getOperand(0);
7932 return ISD::isNON_EXTLoad(V.getNode());
7935 /// \brief Try to lower insertion of a single element into a zero vector.
7937 /// This is a common pattern that we have especially efficient patterns to lower
7938 /// across all subtarget feature sets.
7939 static SDValue lowerVectorShuffleAsElementInsertion(
7940 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7941 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7942 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7944 MVT EltVT = VT.getVectorElementType();
7946 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7947 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7949 bool IsV1Zeroable = true;
7950 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7951 if (i != V2Index && !Zeroable[i]) {
7952 IsV1Zeroable = false;
7956 // Check for a single input from a SCALAR_TO_VECTOR node.
7957 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7958 // all the smarts here sunk into that routine. However, the current
7959 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7960 // vector shuffle lowering is dead.
7961 if (SDValue V2S = getScalarValueForVectorElement(
7962 V2, Mask[V2Index] - Mask.size(), DAG)) {
7963 // We need to zext the scalar if it is smaller than an i32.
7964 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7965 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7966 // Using zext to expand a narrow element won't work for non-zero
7971 // Zero-extend directly to i32.
7973 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7975 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7976 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7977 EltVT == MVT::i16) {
7978 // Either not inserting from the low element of the input or the input
7979 // element size is too small to use VZEXT_MOVL to clear the high bits.
7983 if (!IsV1Zeroable) {
7984 // If V1 can't be treated as a zero vector we have fewer options to lower
7985 // this. We can't support integer vectors or non-zero targets cheaply, and
7986 // the V1 elements can't be permuted in any way.
7987 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7988 if (!VT.isFloatingPoint() || V2Index != 0)
7990 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7991 V1Mask[V2Index] = -1;
7992 if (!isNoopShuffleMask(V1Mask))
7994 // This is essentially a special case blend operation, but if we have
7995 // general purpose blend operations, they are always faster. Bail and let
7996 // the rest of the lowering handle these as blends.
7997 if (Subtarget->hasSSE41())
8000 // Otherwise, use MOVSD or MOVSS.
8001 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
8002 "Only two types of floating point element types to handle!");
8003 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
8007 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
8009 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8012 // If we have 4 or fewer lanes we can cheaply shuffle the element into
8013 // the desired position. Otherwise it is more efficient to do a vector
8014 // shift left. We know that we can do a vector shift left because all
8015 // the inputs are zero.
8016 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
8017 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
8018 V2Shuffle[V2Index] = 0;
8019 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
8021 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
8023 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
8025 V2Index * EltVT.getSizeInBits(),
8026 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
8027 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8033 /// \brief Try to lower broadcast of a single element.
8035 /// For convenience, this code also bundles all of the subtarget feature set
8036 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8037 /// a convenient way to factor it out.
8038 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
8040 const X86Subtarget *Subtarget,
8041 SelectionDAG &DAG) {
8042 if (!Subtarget->hasAVX())
8044 if (VT.isInteger() && !Subtarget->hasAVX2())
8047 // Check that the mask is a broadcast.
8048 int BroadcastIdx = -1;
8050 if (M >= 0 && BroadcastIdx == -1)
8052 else if (M >= 0 && M != BroadcastIdx)
8055 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8056 "a sorted mask where the broadcast "
8059 // Go up the chain of (vector) values to try and find a scalar load that
8060 // we can combine with the broadcast.
8062 switch (V.getOpcode()) {
8063 case ISD::CONCAT_VECTORS: {
8064 int OperandSize = Mask.size() / V.getNumOperands();
8065 V = V.getOperand(BroadcastIdx / OperandSize);
8066 BroadcastIdx %= OperandSize;
8070 case ISD::INSERT_SUBVECTOR: {
8071 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8072 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8076 int BeginIdx = (int)ConstantIdx->getZExtValue();
8078 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
8079 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8080 BroadcastIdx -= BeginIdx;
8091 // Check if this is a broadcast of a scalar. We special case lowering
8092 // for scalars so that we can more effectively fold with loads.
8093 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8094 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8095 V = V.getOperand(BroadcastIdx);
8097 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
8099 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8101 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8102 // We can't broadcast from a vector register w/o AVX2, and we can only
8103 // broadcast from the zero-element of a vector register.
8107 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8110 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8112 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8113 /// support for floating point shuffles but not integer shuffles. These
8114 /// instructions will incur a domain crossing penalty on some chips though so
8115 /// it is better to avoid lowering through this for integer vectors where
8117 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8118 const X86Subtarget *Subtarget,
8119 SelectionDAG &DAG) {
8121 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8122 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8123 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8124 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8125 ArrayRef<int> Mask = SVOp->getMask();
8126 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8128 if (isSingleInputShuffleMask(Mask)) {
8129 // Straight shuffle of a single input vector. Simulate this by using the
8130 // single input as both of the "inputs" to this instruction..
8131 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8133 if (Subtarget->hasAVX()) {
8134 // If we have AVX, we can use VPERMILPS which will allow folding a load
8135 // into the shuffle.
8136 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8137 DAG.getConstant(SHUFPDMask, MVT::i8));
8140 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
8141 DAG.getConstant(SHUFPDMask, MVT::i8));
8143 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8144 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8146 // Use dedicated unpack instructions for masks that match their pattern.
8147 if (isShuffleEquivalent(Mask, 0, 2))
8148 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8149 if (isShuffleEquivalent(Mask, 1, 3))
8150 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8152 // If we have a single input, insert that into V1 if we can do so cheaply.
8153 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8154 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8155 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
8157 // Try inverting the insertion since for v2 masks it is easy to do and we
8158 // can't reliably sort the mask one way or the other.
8159 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8160 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8161 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8162 MVT::v2f64, DL, V2, V1, InverseMask, Subtarget, DAG))
8166 // Try to use one of the special instruction patterns to handle two common
8167 // blend patterns if a zero-blend above didn't work.
8168 if (isShuffleEquivalent(Mask, 0, 3) || isShuffleEquivalent(Mask, 1, 3))
8169 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8170 // We can either use a special instruction to load over the low double or
8171 // to move just the low double.
8173 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8175 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8177 if (Subtarget->hasSSE41())
8178 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8182 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8183 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
8184 DAG.getConstant(SHUFPDMask, MVT::i8));
8187 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8189 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8190 /// the integer unit to minimize domain crossing penalties. However, for blends
8191 /// it falls back to the floating point shuffle operation with appropriate bit
8193 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8194 const X86Subtarget *Subtarget,
8195 SelectionDAG &DAG) {
8197 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8198 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8199 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8200 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8201 ArrayRef<int> Mask = SVOp->getMask();
8202 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8204 if (isSingleInputShuffleMask(Mask)) {
8205 // Check for being able to broadcast a single element.
8206 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
8207 Mask, Subtarget, DAG))
8210 // Straight shuffle of a single input vector. For everything from SSE2
8211 // onward this has a single fast instruction with no scary immediates.
8212 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8213 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
8214 int WidenedMask[4] = {
8215 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8216 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8218 ISD::BITCAST, DL, MVT::v2i64,
8219 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
8220 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
8223 // Try to use byte shift instructions.
8224 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8225 DL, MVT::v2i64, V1, V2, Mask, DAG))
8228 // If we have a single input from V2 insert that into V1 if we can do so
8230 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8231 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8232 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
8234 // Try inverting the insertion since for v2 masks it is easy to do and we
8235 // can't reliably sort the mask one way or the other.
8236 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8237 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8238 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8239 MVT::v2i64, DL, V2, V1, InverseMask, Subtarget, DAG))
8243 // Use dedicated unpack instructions for masks that match their pattern.
8244 if (isShuffleEquivalent(Mask, 0, 2))
8245 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8246 if (isShuffleEquivalent(Mask, 1, 3))
8247 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8249 if (Subtarget->hasSSE41())
8250 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8254 // Try to use byte rotation instructions.
8255 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8256 if (Subtarget->hasSSSE3())
8257 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8258 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8261 // We implement this with SHUFPD which is pretty lame because it will likely
8262 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8263 // However, all the alternatives are still more cycles and newer chips don't
8264 // have this problem. It would be really nice if x86 had better shuffles here.
8265 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
8266 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
8267 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
8268 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8271 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8273 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8274 /// It makes no assumptions about whether this is the *best* lowering, it simply
8276 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8277 ArrayRef<int> Mask, SDValue V1,
8278 SDValue V2, SelectionDAG &DAG) {
8279 SDValue LowV = V1, HighV = V2;
8280 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8283 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8285 if (NumV2Elements == 1) {
8287 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8290 // Compute the index adjacent to V2Index and in the same half by toggling
8292 int V2AdjIndex = V2Index ^ 1;
8294 if (Mask[V2AdjIndex] == -1) {
8295 // Handles all the cases where we have a single V2 element and an undef.
8296 // This will only ever happen in the high lanes because we commute the
8297 // vector otherwise.
8299 std::swap(LowV, HighV);
8300 NewMask[V2Index] -= 4;
8302 // Handle the case where the V2 element ends up adjacent to a V1 element.
8303 // To make this work, blend them together as the first step.
8304 int V1Index = V2AdjIndex;
8305 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8306 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8307 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8309 // Now proceed to reconstruct the final blend as we have the necessary
8310 // high or low half formed.
8317 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8318 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8320 } else if (NumV2Elements == 2) {
8321 if (Mask[0] < 4 && Mask[1] < 4) {
8322 // Handle the easy case where we have V1 in the low lanes and V2 in the
8326 } else if (Mask[2] < 4 && Mask[3] < 4) {
8327 // We also handle the reversed case because this utility may get called
8328 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8329 // arrange things in the right direction.
8335 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8336 // trying to place elements directly, just blend them and set up the final
8337 // shuffle to place them.
8339 // The first two blend mask elements are for V1, the second two are for
8341 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8342 Mask[2] < 4 ? Mask[2] : Mask[3],
8343 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8344 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8345 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8346 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8348 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8351 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8352 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8353 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8354 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8357 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8358 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8361 /// \brief Lower 4-lane 32-bit floating point shuffles.
8363 /// Uses instructions exclusively from the floating point unit to minimize
8364 /// domain crossing penalties, as these are sufficient to implement all v4f32
8366 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8367 const X86Subtarget *Subtarget,
8368 SelectionDAG &DAG) {
8370 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8371 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8372 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8373 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8374 ArrayRef<int> Mask = SVOp->getMask();
8375 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8378 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8380 if (NumV2Elements == 0) {
8381 // Check for being able to broadcast a single element.
8382 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8383 Mask, Subtarget, DAG))
8386 if (Subtarget->hasAVX()) {
8387 // If we have AVX, we can use VPERMILPS which will allow folding a load
8388 // into the shuffle.
8389 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8390 getV4X86ShuffleImm8ForMask(Mask, DAG));
8393 // Otherwise, use a straight shuffle of a single input vector. We pass the
8394 // input vector to both operands to simulate this with a SHUFPS.
8395 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8396 getV4X86ShuffleImm8ForMask(Mask, DAG));
8399 // Use dedicated unpack instructions for masks that match their pattern.
8400 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8401 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8402 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8403 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8405 // There are special ways we can lower some single-element blends. However, we
8406 // have custom ways we can lower more complex single-element blends below that
8407 // we defer to if both this and BLENDPS fail to match, so restrict this to
8408 // when the V2 input is targeting element 0 of the mask -- that is the fast
8410 if (NumV2Elements == 1 && Mask[0] >= 4)
8411 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8412 Mask, Subtarget, DAG))
8415 if (Subtarget->hasSSE41())
8416 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8420 // Check for whether we can use INSERTPS to perform the blend. We only use
8421 // INSERTPS when the V1 elements are already in the correct locations
8422 // because otherwise we can just always use two SHUFPS instructions which
8423 // are much smaller to encode than a SHUFPS and an INSERTPS.
8424 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8426 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8429 // When using INSERTPS we can zero any lane of the destination. Collect
8430 // the zero inputs into a mask and drop them from the lanes of V1 which
8431 // actually need to be present as inputs to the INSERTPS.
8432 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8434 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8435 bool InsertNeedsShuffle = false;
8437 for (int i = 0; i < 4; ++i)
8441 } else if (Mask[i] != i) {
8442 InsertNeedsShuffle = true;
8447 // We don't want to use INSERTPS or other insertion techniques if it will
8448 // require shuffling anyways.
8449 if (!InsertNeedsShuffle) {
8450 // If all of V1 is zeroable, replace it with undef.
8451 if ((ZMask | 1 << V2Index) == 0xF)
8452 V1 = DAG.getUNDEF(MVT::v4f32);
8454 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8455 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8457 // Insert the V2 element into the desired position.
8458 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8459 DAG.getConstant(InsertPSMask, MVT::i8));
8463 // Otherwise fall back to a SHUFPS lowering strategy.
8464 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8467 /// \brief Lower 4-lane i32 vector shuffles.
8469 /// We try to handle these with integer-domain shuffles where we can, but for
8470 /// blends we use the floating point domain blend instructions.
8471 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8472 const X86Subtarget *Subtarget,
8473 SelectionDAG &DAG) {
8475 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8476 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8477 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8478 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8479 ArrayRef<int> Mask = SVOp->getMask();
8480 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8482 // Whenever we can lower this as a zext, that instruction is strictly faster
8483 // than any alternative. It also allows us to fold memory operands into the
8484 // shuffle in many cases.
8485 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8486 Mask, Subtarget, DAG))
8490 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8492 if (NumV2Elements == 0) {
8493 // Check for being able to broadcast a single element.
8494 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8495 Mask, Subtarget, DAG))
8498 // Straight shuffle of a single input vector. For everything from SSE2
8499 // onward this has a single fast instruction with no scary immediates.
8500 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8501 // but we aren't actually going to use the UNPCK instruction because doing
8502 // so prevents folding a load into this instruction or making a copy.
8503 const int UnpackLoMask[] = {0, 0, 1, 1};
8504 const int UnpackHiMask[] = {2, 2, 3, 3};
8505 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8506 Mask = UnpackLoMask;
8507 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8508 Mask = UnpackHiMask;
8510 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8511 getV4X86ShuffleImm8ForMask(Mask, DAG));
8514 // Try to use byte shift instructions.
8515 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8516 DL, MVT::v4i32, V1, V2, Mask, DAG))
8519 // There are special ways we can lower some single-element blends.
8520 if (NumV2Elements == 1)
8521 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8522 Mask, Subtarget, DAG))
8525 // Use dedicated unpack instructions for masks that match their pattern.
8526 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8527 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8528 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8529 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8531 if (Subtarget->hasSSE41())
8532 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8536 // Try to use byte rotation instructions.
8537 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8538 if (Subtarget->hasSSSE3())
8539 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8540 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8543 // We implement this with SHUFPS because it can blend from two vectors.
8544 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8545 // up the inputs, bypassing domain shift penalties that we would encur if we
8546 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8548 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8549 DAG.getVectorShuffle(
8551 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8552 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8555 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8556 /// shuffle lowering, and the most complex part.
8558 /// The lowering strategy is to try to form pairs of input lanes which are
8559 /// targeted at the same half of the final vector, and then use a dword shuffle
8560 /// to place them onto the right half, and finally unpack the paired lanes into
8561 /// their final position.
8563 /// The exact breakdown of how to form these dword pairs and align them on the
8564 /// correct sides is really tricky. See the comments within the function for
8565 /// more of the details.
8566 static SDValue lowerV8I16SingleInputVectorShuffle(
8567 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8568 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8569 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8570 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8571 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8573 SmallVector<int, 4> LoInputs;
8574 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8575 [](int M) { return M >= 0; });
8576 std::sort(LoInputs.begin(), LoInputs.end());
8577 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8578 SmallVector<int, 4> HiInputs;
8579 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8580 [](int M) { return M >= 0; });
8581 std::sort(HiInputs.begin(), HiInputs.end());
8582 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8584 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8585 int NumHToL = LoInputs.size() - NumLToL;
8587 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8588 int NumHToH = HiInputs.size() - NumLToH;
8589 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8590 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8591 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8592 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8594 // Check for being able to broadcast a single element.
8595 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8596 Mask, Subtarget, DAG))
8599 // Try to use byte shift instructions.
8600 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8601 DL, MVT::v8i16, V, V, Mask, DAG))
8604 // Use dedicated unpack instructions for masks that match their pattern.
8605 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8606 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8607 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8608 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8610 // Try to use byte rotation instructions.
8611 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8612 DL, MVT::v8i16, V, V, Mask, Subtarget, DAG))
8615 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8616 // such inputs we can swap two of the dwords across the half mark and end up
8617 // with <=2 inputs to each half in each half. Once there, we can fall through
8618 // to the generic code below. For example:
8620 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8621 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8623 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8624 // and an existing 2-into-2 on the other half. In this case we may have to
8625 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8626 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8627 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8628 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8629 // half than the one we target for fixing) will be fixed when we re-enter this
8630 // path. We will also combine away any sequence of PSHUFD instructions that
8631 // result into a single instruction. Here is an example of the tricky case:
8633 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8634 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8636 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8638 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8639 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8641 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8642 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8644 // The result is fine to be handled by the generic logic.
8645 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8646 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8647 int AOffset, int BOffset) {
8648 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8649 "Must call this with A having 3 or 1 inputs from the A half.");
8650 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8651 "Must call this with B having 1 or 3 inputs from the B half.");
8652 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8653 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8655 // Compute the index of dword with only one word among the three inputs in
8656 // a half by taking the sum of the half with three inputs and subtracting
8657 // the sum of the actual three inputs. The difference is the remaining
8660 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8661 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8662 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8663 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8664 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8665 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8666 int TripleNonInputIdx =
8667 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8668 TripleDWord = TripleNonInputIdx / 2;
8670 // We use xor with one to compute the adjacent DWord to whichever one the
8672 OneInputDWord = (OneInput / 2) ^ 1;
8674 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8675 // and BToA inputs. If there is also such a problem with the BToB and AToB
8676 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8677 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8678 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8679 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8680 // Compute how many inputs will be flipped by swapping these DWords. We
8682 // to balance this to ensure we don't form a 3-1 shuffle in the other
8684 int NumFlippedAToBInputs =
8685 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8686 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8687 int NumFlippedBToBInputs =
8688 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8689 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8690 if ((NumFlippedAToBInputs == 1 &&
8691 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8692 (NumFlippedBToBInputs == 1 &&
8693 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8694 // We choose whether to fix the A half or B half based on whether that
8695 // half has zero flipped inputs. At zero, we may not be able to fix it
8696 // with that half. We also bias towards fixing the B half because that
8697 // will more commonly be the high half, and we have to bias one way.
8698 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8699 ArrayRef<int> Inputs) {
8700 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8701 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8702 PinnedIdx ^ 1) != Inputs.end();
8703 // Determine whether the free index is in the flipped dword or the
8704 // unflipped dword based on where the pinned index is. We use this bit
8705 // in an xor to conditionally select the adjacent dword.
8706 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8707 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8708 FixFreeIdx) != Inputs.end();
8709 if (IsFixIdxInput == IsFixFreeIdxInput)
8711 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8712 FixFreeIdx) != Inputs.end();
8713 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8714 "We need to be changing the number of flipped inputs!");
8715 int PSHUFHalfMask[] = {0, 1, 2, 3};
8716 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8717 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8719 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8722 if (M != -1 && M == FixIdx)
8724 else if (M != -1 && M == FixFreeIdx)
8727 if (NumFlippedBToBInputs != 0) {
8729 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8730 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8732 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8734 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8735 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8740 int PSHUFDMask[] = {0, 1, 2, 3};
8741 PSHUFDMask[ADWord] = BDWord;
8742 PSHUFDMask[BDWord] = ADWord;
8743 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8744 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8745 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8746 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8748 // Adjust the mask to match the new locations of A and B.
8750 if (M != -1 && M/2 == ADWord)
8751 M = 2 * BDWord + M % 2;
8752 else if (M != -1 && M/2 == BDWord)
8753 M = 2 * ADWord + M % 2;
8755 // Recurse back into this routine to re-compute state now that this isn't
8756 // a 3 and 1 problem.
8757 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8760 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8761 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8762 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8763 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8765 // At this point there are at most two inputs to the low and high halves from
8766 // each half. That means the inputs can always be grouped into dwords and
8767 // those dwords can then be moved to the correct half with a dword shuffle.
8768 // We use at most one low and one high word shuffle to collect these paired
8769 // inputs into dwords, and finally a dword shuffle to place them.
8770 int PSHUFLMask[4] = {-1, -1, -1, -1};
8771 int PSHUFHMask[4] = {-1, -1, -1, -1};
8772 int PSHUFDMask[4] = {-1, -1, -1, -1};
8774 // First fix the masks for all the inputs that are staying in their
8775 // original halves. This will then dictate the targets of the cross-half
8777 auto fixInPlaceInputs =
8778 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8779 MutableArrayRef<int> SourceHalfMask,
8780 MutableArrayRef<int> HalfMask, int HalfOffset) {
8781 if (InPlaceInputs.empty())
8783 if (InPlaceInputs.size() == 1) {
8784 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8785 InPlaceInputs[0] - HalfOffset;
8786 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8789 if (IncomingInputs.empty()) {
8790 // Just fix all of the in place inputs.
8791 for (int Input : InPlaceInputs) {
8792 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8793 PSHUFDMask[Input / 2] = Input / 2;
8798 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8799 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8800 InPlaceInputs[0] - HalfOffset;
8801 // Put the second input next to the first so that they are packed into
8802 // a dword. We find the adjacent index by toggling the low bit.
8803 int AdjIndex = InPlaceInputs[0] ^ 1;
8804 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8805 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8806 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8808 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8809 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8811 // Now gather the cross-half inputs and place them into a free dword of
8812 // their target half.
8813 // FIXME: This operation could almost certainly be simplified dramatically to
8814 // look more like the 3-1 fixing operation.
8815 auto moveInputsToRightHalf = [&PSHUFDMask](
8816 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8817 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8818 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8820 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8821 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8823 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8825 int LowWord = Word & ~1;
8826 int HighWord = Word | 1;
8827 return isWordClobbered(SourceHalfMask, LowWord) ||
8828 isWordClobbered(SourceHalfMask, HighWord);
8831 if (IncomingInputs.empty())
8834 if (ExistingInputs.empty()) {
8835 // Map any dwords with inputs from them into the right half.
8836 for (int Input : IncomingInputs) {
8837 // If the source half mask maps over the inputs, turn those into
8838 // swaps and use the swapped lane.
8839 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8840 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8841 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8842 Input - SourceOffset;
8843 // We have to swap the uses in our half mask in one sweep.
8844 for (int &M : HalfMask)
8845 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8847 else if (M == Input)
8848 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8850 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8851 Input - SourceOffset &&
8852 "Previous placement doesn't match!");
8854 // Note that this correctly re-maps both when we do a swap and when
8855 // we observe the other side of the swap above. We rely on that to
8856 // avoid swapping the members of the input list directly.
8857 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8860 // Map the input's dword into the correct half.
8861 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8862 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8864 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8866 "Previous placement doesn't match!");
8869 // And just directly shift any other-half mask elements to be same-half
8870 // as we will have mirrored the dword containing the element into the
8871 // same position within that half.
8872 for (int &M : HalfMask)
8873 if (M >= SourceOffset && M < SourceOffset + 4) {
8874 M = M - SourceOffset + DestOffset;
8875 assert(M >= 0 && "This should never wrap below zero!");
8880 // Ensure we have the input in a viable dword of its current half. This
8881 // is particularly tricky because the original position may be clobbered
8882 // by inputs being moved and *staying* in that half.
8883 if (IncomingInputs.size() == 1) {
8884 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8885 int InputFixed = std::find(std::begin(SourceHalfMask),
8886 std::end(SourceHalfMask), -1) -
8887 std::begin(SourceHalfMask) + SourceOffset;
8888 SourceHalfMask[InputFixed - SourceOffset] =
8889 IncomingInputs[0] - SourceOffset;
8890 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8892 IncomingInputs[0] = InputFixed;
8894 } else if (IncomingInputs.size() == 2) {
8895 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8896 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8897 // We have two non-adjacent or clobbered inputs we need to extract from
8898 // the source half. To do this, we need to map them into some adjacent
8899 // dword slot in the source mask.
8900 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8901 IncomingInputs[1] - SourceOffset};
8903 // If there is a free slot in the source half mask adjacent to one of
8904 // the inputs, place the other input in it. We use (Index XOR 1) to
8905 // compute an adjacent index.
8906 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8907 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8908 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8909 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8910 InputsFixed[1] = InputsFixed[0] ^ 1;
8911 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8912 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8913 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8914 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8915 InputsFixed[0] = InputsFixed[1] ^ 1;
8916 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8917 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8918 // The two inputs are in the same DWord but it is clobbered and the
8919 // adjacent DWord isn't used at all. Move both inputs to the free
8921 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8922 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8923 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8924 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8926 // The only way we hit this point is if there is no clobbering
8927 // (because there are no off-half inputs to this half) and there is no
8928 // free slot adjacent to one of the inputs. In this case, we have to
8929 // swap an input with a non-input.
8930 for (int i = 0; i < 4; ++i)
8931 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8932 "We can't handle any clobbers here!");
8933 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8934 "Cannot have adjacent inputs here!");
8936 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8937 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8939 // We also have to update the final source mask in this case because
8940 // it may need to undo the above swap.
8941 for (int &M : FinalSourceHalfMask)
8942 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8943 M = InputsFixed[1] + SourceOffset;
8944 else if (M == InputsFixed[1] + SourceOffset)
8945 M = (InputsFixed[0] ^ 1) + SourceOffset;
8947 InputsFixed[1] = InputsFixed[0] ^ 1;
8950 // Point everything at the fixed inputs.
8951 for (int &M : HalfMask)
8952 if (M == IncomingInputs[0])
8953 M = InputsFixed[0] + SourceOffset;
8954 else if (M == IncomingInputs[1])
8955 M = InputsFixed[1] + SourceOffset;
8957 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8958 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8961 llvm_unreachable("Unhandled input size!");
8964 // Now hoist the DWord down to the right half.
8965 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8966 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8967 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8968 for (int &M : HalfMask)
8969 for (int Input : IncomingInputs)
8971 M = FreeDWord * 2 + Input % 2;
8973 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8974 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8975 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8976 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8978 // Now enact all the shuffles we've computed to move the inputs into their
8980 if (!isNoopShuffleMask(PSHUFLMask))
8981 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8982 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8983 if (!isNoopShuffleMask(PSHUFHMask))
8984 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8985 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8986 if (!isNoopShuffleMask(PSHUFDMask))
8987 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8988 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8989 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8990 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8992 // At this point, each half should contain all its inputs, and we can then
8993 // just shuffle them into their final position.
8994 assert(std::count_if(LoMask.begin(), LoMask.end(),
8995 [](int M) { return M >= 4; }) == 0 &&
8996 "Failed to lift all the high half inputs to the low mask!");
8997 assert(std::count_if(HiMask.begin(), HiMask.end(),
8998 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8999 "Failed to lift all the low half inputs to the high mask!");
9001 // Do a half shuffle for the low mask.
9002 if (!isNoopShuffleMask(LoMask))
9003 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
9004 getV4X86ShuffleImm8ForMask(LoMask, DAG));
9006 // Do a half shuffle with the high mask after shifting its values down.
9007 for (int &M : HiMask)
9010 if (!isNoopShuffleMask(HiMask))
9011 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
9012 getV4X86ShuffleImm8ForMask(HiMask, DAG));
9017 /// \brief Detect whether the mask pattern should be lowered through
9020 /// This essentially tests whether viewing the mask as an interleaving of two
9021 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
9022 /// lowering it through interleaving is a significantly better strategy.
9023 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
9024 int NumEvenInputs[2] = {0, 0};
9025 int NumOddInputs[2] = {0, 0};
9026 int NumLoInputs[2] = {0, 0};
9027 int NumHiInputs[2] = {0, 0};
9028 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
9032 int InputIdx = Mask[i] >= Size;
9035 ++NumLoInputs[InputIdx];
9037 ++NumHiInputs[InputIdx];
9040 ++NumEvenInputs[InputIdx];
9042 ++NumOddInputs[InputIdx];
9045 // The minimum number of cross-input results for both the interleaved and
9046 // split cases. If interleaving results in fewer cross-input results, return
9048 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
9049 NumEvenInputs[0] + NumOddInputs[1]);
9050 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
9051 NumLoInputs[0] + NumHiInputs[1]);
9052 return InterleavedCrosses < SplitCrosses;
9055 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
9057 /// This strategy only works when the inputs from each vector fit into a single
9058 /// half of that vector, and generally there are not so many inputs as to leave
9059 /// the in-place shuffles required highly constrained (and thus expensive). It
9060 /// shifts all the inputs into a single side of both input vectors and then
9061 /// uses an unpack to interleave these inputs in a single vector. At that
9062 /// point, we will fall back on the generic single input shuffle lowering.
9063 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
9065 MutableArrayRef<int> Mask,
9066 const X86Subtarget *Subtarget,
9067 SelectionDAG &DAG) {
9068 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9069 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9070 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
9071 for (int i = 0; i < 8; ++i)
9072 if (Mask[i] >= 0 && Mask[i] < 4)
9073 LoV1Inputs.push_back(i);
9074 else if (Mask[i] >= 4 && Mask[i] < 8)
9075 HiV1Inputs.push_back(i);
9076 else if (Mask[i] >= 8 && Mask[i] < 12)
9077 LoV2Inputs.push_back(i);
9078 else if (Mask[i] >= 12)
9079 HiV2Inputs.push_back(i);
9081 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
9082 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
9085 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
9086 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
9087 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
9089 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
9090 HiV1Inputs.size() + HiV2Inputs.size();
9092 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
9093 ArrayRef<int> HiInputs, bool MoveToLo,
9095 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
9096 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
9097 if (BadInputs.empty())
9100 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9101 int MoveOffset = MoveToLo ? 0 : 4;
9103 if (GoodInputs.empty()) {
9104 for (int BadInput : BadInputs) {
9105 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
9106 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
9109 if (GoodInputs.size() == 2) {
9110 // If the low inputs are spread across two dwords, pack them into
9112 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
9113 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
9114 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
9115 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
9117 // Otherwise pin the good inputs.
9118 for (int GoodInput : GoodInputs)
9119 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
9122 if (BadInputs.size() == 2) {
9123 // If we have two bad inputs then there may be either one or two good
9124 // inputs fixed in place. Find a fixed input, and then find the *other*
9125 // two adjacent indices by using modular arithmetic.
9127 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
9128 [](int M) { return M >= 0; }) -
9129 std::begin(MoveMask);
9131 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
9132 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
9133 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
9134 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9135 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
9136 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9137 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
9139 assert(BadInputs.size() == 1 && "All sizes handled");
9140 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
9141 std::end(MoveMask), -1) -
9142 std::begin(MoveMask);
9143 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9144 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9148 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
9151 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
9153 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
9156 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
9157 // cross-half traffic in the final shuffle.
9159 // Munge the mask to be a single-input mask after the unpack merges the
9163 M = 2 * (M % 4) + (M / 8);
9165 return DAG.getVectorShuffle(
9166 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
9167 DL, MVT::v8i16, V1, V2),
9168 DAG.getUNDEF(MVT::v8i16), Mask);
9171 /// \brief Generic lowering of 8-lane i16 shuffles.
9173 /// This handles both single-input shuffles and combined shuffle/blends with
9174 /// two inputs. The single input shuffles are immediately delegated to
9175 /// a dedicated lowering routine.
9177 /// The blends are lowered in one of three fundamental ways. If there are few
9178 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9179 /// of the input is significantly cheaper when lowered as an interleaving of
9180 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9181 /// halves of the inputs separately (making them have relatively few inputs)
9182 /// and then concatenate them.
9183 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9184 const X86Subtarget *Subtarget,
9185 SelectionDAG &DAG) {
9187 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9188 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9189 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9190 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9191 ArrayRef<int> OrigMask = SVOp->getMask();
9192 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9193 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9194 MutableArrayRef<int> Mask(MaskStorage);
9196 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9198 // Whenever we can lower this as a zext, that instruction is strictly faster
9199 // than any alternative.
9200 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9201 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9204 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9205 auto isV2 = [](int M) { return M >= 8; };
9207 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
9208 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9210 if (NumV2Inputs == 0)
9211 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
9213 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
9214 "to be V1-input shuffles.");
9216 // Try to use byte shift instructions.
9217 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9218 DL, MVT::v8i16, V1, V2, Mask, DAG))
9221 // There are special ways we can lower some single-element blends.
9222 if (NumV2Inputs == 1)
9223 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
9224 Mask, Subtarget, DAG))
9227 // Use dedicated unpack instructions for masks that match their pattern.
9228 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 2, 10, 3, 11))
9229 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9230 if (isShuffleEquivalent(Mask, 4, 12, 5, 13, 6, 14, 7, 15))
9231 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9233 if (Subtarget->hasSSE41())
9234 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9238 // Try to use byte rotation instructions.
9239 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9240 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9243 if (NumV1Inputs + NumV2Inputs <= 4)
9244 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
9246 // Check whether an interleaving lowering is likely to be more efficient.
9247 // This isn't perfect but it is a strong heuristic that tends to work well on
9248 // the kinds of shuffles that show up in practice.
9250 // FIXME: Handle 1x, 2x, and 4x interleaving.
9251 if (shouldLowerAsInterleaving(Mask)) {
9252 // FIXME: Figure out whether we should pack these into the low or high
9255 int EMask[8], OMask[8];
9256 for (int i = 0; i < 4; ++i) {
9257 EMask[i] = Mask[2*i];
9258 OMask[i] = Mask[2*i + 1];
9263 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
9264 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
9266 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
9269 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9270 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9272 for (int i = 0; i < 4; ++i) {
9273 LoBlendMask[i] = Mask[i];
9274 HiBlendMask[i] = Mask[i + 4];
9277 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9278 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9279 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
9280 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
9282 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9283 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
9286 /// \brief Check whether a compaction lowering can be done by dropping even
9287 /// elements and compute how many times even elements must be dropped.
9289 /// This handles shuffles which take every Nth element where N is a power of
9290 /// two. Example shuffle masks:
9292 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9293 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9294 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9295 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9296 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9297 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9299 /// Any of these lanes can of course be undef.
9301 /// This routine only supports N <= 3.
9302 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9305 /// \returns N above, or the number of times even elements must be dropped if
9306 /// there is such a number. Otherwise returns zero.
9307 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9308 // Figure out whether we're looping over two inputs or just one.
9309 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9311 // The modulus for the shuffle vector entries is based on whether this is
9312 // a single input or not.
9313 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9314 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9315 "We should only be called with masks with a power-of-2 size!");
9317 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9319 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9320 // and 2^3 simultaneously. This is because we may have ambiguity with
9321 // partially undef inputs.
9322 bool ViableForN[3] = {true, true, true};
9324 for (int i = 0, e = Mask.size(); i < e; ++i) {
9325 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9330 bool IsAnyViable = false;
9331 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9332 if (ViableForN[j]) {
9335 // The shuffle mask must be equal to (i * 2^N) % M.
9336 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9339 ViableForN[j] = false;
9341 // Early exit if we exhaust the possible powers of two.
9346 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9350 // Return 0 as there is no viable power of two.
9354 /// \brief Generic lowering of v16i8 shuffles.
9356 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9357 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9358 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9359 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9361 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9362 const X86Subtarget *Subtarget,
9363 SelectionDAG &DAG) {
9365 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9366 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9367 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9368 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9369 ArrayRef<int> OrigMask = SVOp->getMask();
9370 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9372 // Try to use byte shift instructions.
9373 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9374 DL, MVT::v16i8, V1, V2, OrigMask, DAG))
9377 // Try to use byte rotation instructions.
9378 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9379 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9382 // Try to use a zext lowering.
9383 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9384 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9387 int MaskStorage[16] = {
9388 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9389 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9390 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9391 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9392 MutableArrayRef<int> Mask(MaskStorage);
9393 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9394 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9397 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9399 // For single-input shuffles, there are some nicer lowering tricks we can use.
9400 if (NumV2Elements == 0) {
9401 // Check for being able to broadcast a single element.
9402 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9403 Mask, Subtarget, DAG))
9406 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9407 // Notably, this handles splat and partial-splat shuffles more efficiently.
9408 // However, it only makes sense if the pre-duplication shuffle simplifies
9409 // things significantly. Currently, this means we need to be able to
9410 // express the pre-duplication shuffle as an i16 shuffle.
9412 // FIXME: We should check for other patterns which can be widened into an
9413 // i16 shuffle as well.
9414 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9415 for (int i = 0; i < 16; i += 2)
9416 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9421 auto tryToWidenViaDuplication = [&]() -> SDValue {
9422 if (!canWidenViaDuplication(Mask))
9424 SmallVector<int, 4> LoInputs;
9425 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9426 [](int M) { return M >= 0 && M < 8; });
9427 std::sort(LoInputs.begin(), LoInputs.end());
9428 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9430 SmallVector<int, 4> HiInputs;
9431 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9432 [](int M) { return M >= 8; });
9433 std::sort(HiInputs.begin(), HiInputs.end());
9434 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9437 bool TargetLo = LoInputs.size() >= HiInputs.size();
9438 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9439 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9441 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9442 SmallDenseMap<int, int, 8> LaneMap;
9443 for (int I : InPlaceInputs) {
9444 PreDupI16Shuffle[I/2] = I/2;
9447 int j = TargetLo ? 0 : 4, je = j + 4;
9448 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9449 // Check if j is already a shuffle of this input. This happens when
9450 // there are two adjacent bytes after we move the low one.
9451 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9452 // If we haven't yet mapped the input, search for a slot into which
9454 while (j < je && PreDupI16Shuffle[j] != -1)
9458 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9461 // Map this input with the i16 shuffle.
9462 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9465 // Update the lane map based on the mapping we ended up with.
9466 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9469 ISD::BITCAST, DL, MVT::v16i8,
9470 DAG.getVectorShuffle(MVT::v8i16, DL,
9471 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9472 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9474 // Unpack the bytes to form the i16s that will be shuffled into place.
9475 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9476 MVT::v16i8, V1, V1);
9478 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9479 for (int i = 0; i < 16; ++i)
9480 if (Mask[i] != -1) {
9481 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9482 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9483 if (PostDupI16Shuffle[i / 2] == -1)
9484 PostDupI16Shuffle[i / 2] = MappedMask;
9486 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9487 "Conflicting entrties in the original shuffle!");
9490 ISD::BITCAST, DL, MVT::v16i8,
9491 DAG.getVectorShuffle(MVT::v8i16, DL,
9492 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9493 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9495 if (SDValue V = tryToWidenViaDuplication())
9499 // Check whether an interleaving lowering is likely to be more efficient.
9500 // This isn't perfect but it is a strong heuristic that tends to work well on
9501 // the kinds of shuffles that show up in practice.
9503 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9504 if (shouldLowerAsInterleaving(Mask)) {
9505 int NumLoHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9506 return (M >= 0 && M < 8) || (M >= 16 && M < 24);
9508 int NumHiHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9509 return (M >= 8 && M < 16) || M >= 24;
9511 int EMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9512 -1, -1, -1, -1, -1, -1, -1, -1};
9513 int OMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9514 -1, -1, -1, -1, -1, -1, -1, -1};
9515 bool UnpackLo = NumLoHalf >= NumHiHalf;
9516 MutableArrayRef<int> TargetEMask(UnpackLo ? EMask : EMask + 8, 8);
9517 MutableArrayRef<int> TargetOMask(UnpackLo ? OMask : OMask + 8, 8);
9518 for (int i = 0; i < 8; ++i) {
9519 TargetEMask[i] = Mask[2 * i];
9520 TargetOMask[i] = Mask[2 * i + 1];
9523 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9524 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9526 return DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9527 MVT::v16i8, Evens, Odds);
9530 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9531 // with PSHUFB. It is important to do this before we attempt to generate any
9532 // blends but after all of the single-input lowerings. If the single input
9533 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9534 // want to preserve that and we can DAG combine any longer sequences into
9535 // a PSHUFB in the end. But once we start blending from multiple inputs,
9536 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9537 // and there are *very* few patterns that would actually be faster than the
9538 // PSHUFB approach because of its ability to zero lanes.
9540 // FIXME: The only exceptions to the above are blends which are exact
9541 // interleavings with direct instructions supporting them. We currently don't
9542 // handle those well here.
9543 if (Subtarget->hasSSSE3()) {
9546 for (int i = 0; i < 16; ++i)
9547 if (Mask[i] == -1) {
9548 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9550 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9552 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9554 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9555 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9556 if (isSingleInputShuffleMask(Mask))
9557 return V1; // Single inputs are easy.
9559 // Otherwise, blend the two.
9560 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9561 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9562 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9565 // There are special ways we can lower some single-element blends.
9566 if (NumV2Elements == 1)
9567 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9568 Mask, Subtarget, DAG))
9571 // Check whether a compaction lowering can be done. This handles shuffles
9572 // which take every Nth element for some even N. See the helper function for
9575 // We special case these as they can be particularly efficiently handled with
9576 // the PACKUSB instruction on x86 and they show up in common patterns of
9577 // rearranging bytes to truncate wide elements.
9578 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9579 // NumEvenDrops is the power of two stride of the elements. Another way of
9580 // thinking about it is that we need to drop the even elements this many
9581 // times to get the original input.
9582 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9584 // First we need to zero all the dropped bytes.
9585 assert(NumEvenDrops <= 3 &&
9586 "No support for dropping even elements more than 3 times.");
9587 // We use the mask type to pick which bytes are preserved based on how many
9588 // elements are dropped.
9589 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9590 SDValue ByteClearMask =
9591 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9592 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9593 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9595 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9597 // Now pack things back together.
9598 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9599 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9600 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9601 for (int i = 1; i < NumEvenDrops; ++i) {
9602 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9603 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9609 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9610 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9611 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9612 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9614 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9615 MutableArrayRef<int> V1HalfBlendMask,
9616 MutableArrayRef<int> V2HalfBlendMask) {
9617 for (int i = 0; i < 8; ++i)
9618 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9619 V1HalfBlendMask[i] = HalfMask[i];
9621 } else if (HalfMask[i] >= 16) {
9622 V2HalfBlendMask[i] = HalfMask[i] - 16;
9623 HalfMask[i] = i + 8;
9626 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9627 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9629 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9631 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9632 MutableArrayRef<int> HiBlendMask) {
9634 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9635 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9637 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9638 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9639 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9640 [](int M) { return M >= 0 && M % 2 == 1; })) {
9641 // Use a mask to drop the high bytes.
9642 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9643 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9644 DAG.getConstant(0x00FF, MVT::v8i16));
9646 // This will be a single vector shuffle instead of a blend so nuke V2.
9647 V2 = DAG.getUNDEF(MVT::v8i16);
9649 // Squash the masks to point directly into V1.
9650 for (int &M : LoBlendMask)
9653 for (int &M : HiBlendMask)
9657 // Otherwise just unpack the low half of V into V1 and the high half into
9658 // V2 so that we can blend them as i16s.
9659 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9660 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9661 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9662 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9665 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9666 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9667 return std::make_pair(BlendedLo, BlendedHi);
9669 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9670 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9671 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9673 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9674 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9676 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9679 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9681 /// This routine breaks down the specific type of 128-bit shuffle and
9682 /// dispatches to the lowering routines accordingly.
9683 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9684 MVT VT, const X86Subtarget *Subtarget,
9685 SelectionDAG &DAG) {
9686 switch (VT.SimpleTy) {
9688 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9690 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9692 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9694 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9696 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9698 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9701 llvm_unreachable("Unimplemented!");
9705 /// \brief Helper function to test whether a shuffle mask could be
9706 /// simplified by widening the elements being shuffled.
9708 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9709 /// leaves it in an unspecified state.
9711 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9712 /// shuffle masks. The latter have the special property of a '-2' representing
9713 /// a zero-ed lane of a vector.
9714 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9715 SmallVectorImpl<int> &WidenedMask) {
9716 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9717 // If both elements are undef, its trivial.
9718 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9719 WidenedMask.push_back(SM_SentinelUndef);
9723 // Check for an undef mask and a mask value properly aligned to fit with
9724 // a pair of values. If we find such a case, use the non-undef mask's value.
9725 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9726 WidenedMask.push_back(Mask[i + 1] / 2);
9729 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9730 WidenedMask.push_back(Mask[i] / 2);
9734 // When zeroing, we need to spread the zeroing across both lanes to widen.
9735 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9736 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9737 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9738 WidenedMask.push_back(SM_SentinelZero);
9744 // Finally check if the two mask values are adjacent and aligned with
9746 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9747 WidenedMask.push_back(Mask[i] / 2);
9751 // Otherwise we can't safely widen the elements used in this shuffle.
9754 assert(WidenedMask.size() == Mask.size() / 2 &&
9755 "Incorrect size of mask after widening the elements!");
9760 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9762 /// This routine just extracts two subvectors, shuffles them independently, and
9763 /// then concatenates them back together. This should work effectively with all
9764 /// AVX vector shuffle types.
9765 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9766 SDValue V2, ArrayRef<int> Mask,
9767 SelectionDAG &DAG) {
9768 assert(VT.getSizeInBits() >= 256 &&
9769 "Only for 256-bit or wider vector shuffles!");
9770 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9771 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9773 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9774 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9776 int NumElements = VT.getVectorNumElements();
9777 int SplitNumElements = NumElements / 2;
9778 MVT ScalarVT = VT.getScalarType();
9779 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9781 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9782 DAG.getIntPtrConstant(0));
9783 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9784 DAG.getIntPtrConstant(SplitNumElements));
9785 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9786 DAG.getIntPtrConstant(0));
9787 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9788 DAG.getIntPtrConstant(SplitNumElements));
9790 // Now create two 4-way blends of these half-width vectors.
9791 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9792 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9793 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9794 for (int i = 0; i < SplitNumElements; ++i) {
9795 int M = HalfMask[i];
9796 if (M >= NumElements) {
9797 if (M >= NumElements + SplitNumElements)
9801 V2BlendMask.push_back(M - NumElements);
9802 V1BlendMask.push_back(-1);
9803 BlendMask.push_back(SplitNumElements + i);
9804 } else if (M >= 0) {
9805 if (M >= SplitNumElements)
9809 V2BlendMask.push_back(-1);
9810 V1BlendMask.push_back(M);
9811 BlendMask.push_back(i);
9813 V2BlendMask.push_back(-1);
9814 V1BlendMask.push_back(-1);
9815 BlendMask.push_back(-1);
9819 // Because the lowering happens after all combining takes place, we need to
9820 // manually combine these blend masks as much as possible so that we create
9821 // a minimal number of high-level vector shuffle nodes.
9823 // First try just blending the halves of V1 or V2.
9824 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9825 return DAG.getUNDEF(SplitVT);
9826 if (!UseLoV2 && !UseHiV2)
9827 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9828 if (!UseLoV1 && !UseHiV1)
9829 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9831 SDValue V1Blend, V2Blend;
9832 if (UseLoV1 && UseHiV1) {
9834 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9836 // We only use half of V1 so map the usage down into the final blend mask.
9837 V1Blend = UseLoV1 ? LoV1 : HiV1;
9838 for (int i = 0; i < SplitNumElements; ++i)
9839 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9840 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9842 if (UseLoV2 && UseHiV2) {
9844 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9846 // We only use half of V2 so map the usage down into the final blend mask.
9847 V2Blend = UseLoV2 ? LoV2 : HiV2;
9848 for (int i = 0; i < SplitNumElements; ++i)
9849 if (BlendMask[i] >= SplitNumElements)
9850 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9852 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9854 SDValue Lo = HalfBlend(LoMask);
9855 SDValue Hi = HalfBlend(HiMask);
9856 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9859 /// \brief Either split a vector in halves or decompose the shuffles and the
9862 /// This is provided as a good fallback for many lowerings of non-single-input
9863 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9864 /// between splitting the shuffle into 128-bit components and stitching those
9865 /// back together vs. extracting the single-input shuffles and blending those
9867 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9868 SDValue V2, ArrayRef<int> Mask,
9869 SelectionDAG &DAG) {
9870 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9871 "lower single-input shuffles as it "
9872 "could then recurse on itself.");
9873 int Size = Mask.size();
9875 // If this can be modeled as a broadcast of two elements followed by a blend,
9876 // prefer that lowering. This is especially important because broadcasts can
9877 // often fold with memory operands.
9878 auto DoBothBroadcast = [&] {
9879 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9882 if (V2BroadcastIdx == -1)
9883 V2BroadcastIdx = M - Size;
9884 else if (M - Size != V2BroadcastIdx)
9886 } else if (M >= 0) {
9887 if (V1BroadcastIdx == -1)
9889 else if (M != V1BroadcastIdx)
9894 if (DoBothBroadcast())
9895 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9898 // If the inputs all stem from a single 128-bit lane of each input, then we
9899 // split them rather than blending because the split will decompose to
9900 // unusually few instructions.
9901 int LaneCount = VT.getSizeInBits() / 128;
9902 int LaneSize = Size / LaneCount;
9903 SmallBitVector LaneInputs[2];
9904 LaneInputs[0].resize(LaneCount, false);
9905 LaneInputs[1].resize(LaneCount, false);
9906 for (int i = 0; i < Size; ++i)
9908 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9909 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9910 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9912 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9913 // that the decomposed single-input shuffles don't end up here.
9914 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9917 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9918 /// a permutation and blend of those lanes.
9920 /// This essentially blends the out-of-lane inputs to each lane into the lane
9921 /// from a permuted copy of the vector. This lowering strategy results in four
9922 /// instructions in the worst case for a single-input cross lane shuffle which
9923 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9924 /// of. Special cases for each particular shuffle pattern should be handled
9925 /// prior to trying this lowering.
9926 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9927 SDValue V1, SDValue V2,
9929 SelectionDAG &DAG) {
9930 // FIXME: This should probably be generalized for 512-bit vectors as well.
9931 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9932 int LaneSize = Mask.size() / 2;
9934 // If there are only inputs from one 128-bit lane, splitting will in fact be
9935 // less expensive. The flags track wether the given lane contains an element
9936 // that crosses to another lane.
9937 bool LaneCrossing[2] = {false, false};
9938 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9939 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9940 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9941 if (!LaneCrossing[0] || !LaneCrossing[1])
9942 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9944 if (isSingleInputShuffleMask(Mask)) {
9945 SmallVector<int, 32> FlippedBlendMask;
9946 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9947 FlippedBlendMask.push_back(
9948 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9950 : Mask[i] % LaneSize +
9951 (i / LaneSize) * LaneSize + Size));
9953 // Flip the vector, and blend the results which should now be in-lane. The
9954 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9955 // 5 for the high source. The value 3 selects the high half of source 2 and
9956 // the value 2 selects the low half of source 2. We only use source 2 to
9957 // allow folding it into a memory operand.
9958 unsigned PERMMask = 3 | 2 << 4;
9959 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9960 V1, DAG.getConstant(PERMMask, MVT::i8));
9961 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9964 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9965 // will be handled by the above logic and a blend of the results, much like
9966 // other patterns in AVX.
9967 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9970 /// \brief Handle lowering 2-lane 128-bit shuffles.
9971 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9972 SDValue V2, ArrayRef<int> Mask,
9973 const X86Subtarget *Subtarget,
9974 SelectionDAG &DAG) {
9975 // Blends are faster and handle all the non-lane-crossing cases.
9976 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9980 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9981 VT.getVectorNumElements() / 2);
9982 // Check for patterns which can be matched with a single insert of a 128-bit
9984 if (isShuffleEquivalent(Mask, 0, 1, 0, 1) ||
9985 isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
9986 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9987 DAG.getIntPtrConstant(0));
9988 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9989 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
9990 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9992 if (isShuffleEquivalent(Mask, 0, 1, 6, 7)) {
9993 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9994 DAG.getIntPtrConstant(0));
9995 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
9996 DAG.getIntPtrConstant(2));
9997 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10000 // Otherwise form a 128-bit permutation.
10001 // FIXME: Detect zero-vector inputs and use the VPERM2X128 to zero that half.
10002 unsigned PermMask = Mask[0] / 2 | (Mask[2] / 2) << 4;
10003 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
10004 DAG.getConstant(PermMask, MVT::i8));
10007 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10008 /// shuffling each lane.
10010 /// This will only succeed when the result of fixing the 128-bit lanes results
10011 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10012 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10013 /// the lane crosses early and then use simpler shuffles within each lane.
10015 /// FIXME: It might be worthwhile at some point to support this without
10016 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10017 /// in x86 only floating point has interesting non-repeating shuffles, and even
10018 /// those are still *marginally* more expensive.
10019 static SDValue lowerVectorShuffleByMerging128BitLanes(
10020 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10021 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10022 assert(!isSingleInputShuffleMask(Mask) &&
10023 "This is only useful with multiple inputs.");
10025 int Size = Mask.size();
10026 int LaneSize = 128 / VT.getScalarSizeInBits();
10027 int NumLanes = Size / LaneSize;
10028 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10030 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10031 // check whether the in-128-bit lane shuffles share a repeating pattern.
10032 SmallVector<int, 4> Lanes;
10033 Lanes.resize(NumLanes, -1);
10034 SmallVector<int, 4> InLaneMask;
10035 InLaneMask.resize(LaneSize, -1);
10036 for (int i = 0; i < Size; ++i) {
10040 int j = i / LaneSize;
10042 if (Lanes[j] < 0) {
10043 // First entry we've seen for this lane.
10044 Lanes[j] = Mask[i] / LaneSize;
10045 } else if (Lanes[j] != Mask[i] / LaneSize) {
10046 // This doesn't match the lane selected previously!
10050 // Check that within each lane we have a consistent shuffle mask.
10051 int k = i % LaneSize;
10052 if (InLaneMask[k] < 0) {
10053 InLaneMask[k] = Mask[i] % LaneSize;
10054 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10055 // This doesn't fit a repeating in-lane mask.
10060 // First shuffle the lanes into place.
10061 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10062 VT.getSizeInBits() / 64);
10063 SmallVector<int, 8> LaneMask;
10064 LaneMask.resize(NumLanes * 2, -1);
10065 for (int i = 0; i < NumLanes; ++i)
10066 if (Lanes[i] >= 0) {
10067 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10068 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10071 V1 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V1);
10072 V2 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V2);
10073 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10075 // Cast it back to the type we actually want.
10076 LaneShuffle = DAG.getNode(ISD::BITCAST, DL, VT, LaneShuffle);
10078 // Now do a simple shuffle that isn't lane crossing.
10079 SmallVector<int, 8> NewMask;
10080 NewMask.resize(Size, -1);
10081 for (int i = 0; i < Size; ++i)
10083 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10084 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10085 "Must not introduce lane crosses at this point!");
10087 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10090 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10093 /// This returns true if the elements from a particular input are already in the
10094 /// slot required by the given mask and require no permutation.
10095 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10096 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10097 int Size = Mask.size();
10098 for (int i = 0; i < Size; ++i)
10099 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10105 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10107 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10108 /// isn't available.
10109 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10110 const X86Subtarget *Subtarget,
10111 SelectionDAG &DAG) {
10113 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10114 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10115 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10116 ArrayRef<int> Mask = SVOp->getMask();
10117 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10119 SmallVector<int, 4> WidenedMask;
10120 if (canWidenShuffleElements(Mask, WidenedMask))
10121 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10124 if (isSingleInputShuffleMask(Mask)) {
10125 // Check for being able to broadcast a single element.
10126 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
10127 Mask, Subtarget, DAG))
10130 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10131 // Non-half-crossing single input shuffles can be lowerid with an
10132 // interleaved permutation.
10133 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10134 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10135 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10136 DAG.getConstant(VPERMILPMask, MVT::i8));
10139 // With AVX2 we have direct support for this permutation.
10140 if (Subtarget->hasAVX2())
10141 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10142 getV4X86ShuffleImm8ForMask(Mask, DAG));
10144 // Otherwise, fall back.
10145 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10149 // X86 has dedicated unpack instructions that can handle specific blend
10150 // operations: UNPCKH and UNPCKL.
10151 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10152 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10153 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10154 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10156 // If we have a single input to the zero element, insert that into V1 if we
10157 // can do so cheaply.
10158 int NumV2Elements =
10159 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
10160 if (NumV2Elements == 1 && Mask[0] >= 4)
10161 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10162 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
10165 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10169 // Check if the blend happens to exactly fit that of SHUFPD.
10170 if ((Mask[0] == -1 || Mask[0] < 2) &&
10171 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
10172 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
10173 (Mask[3] == -1 || Mask[3] >= 6)) {
10174 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
10175 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
10176 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
10177 DAG.getConstant(SHUFPDMask, MVT::i8));
10179 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
10180 (Mask[1] == -1 || Mask[1] < 2) &&
10181 (Mask[2] == -1 || Mask[2] >= 6) &&
10182 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
10183 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
10184 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
10185 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
10186 DAG.getConstant(SHUFPDMask, MVT::i8));
10189 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10190 // shuffle. However, if we have AVX2 and either inputs are already in place,
10191 // we will be able to shuffle even across lanes the other input in a single
10192 // instruction so skip this pattern.
10193 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10194 isShuffleMaskInputInPlace(1, Mask))))
10195 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10196 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10199 // If we have AVX2 then we always want to lower with a blend because an v4 we
10200 // can fully permute the elements.
10201 if (Subtarget->hasAVX2())
10202 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10205 // Otherwise fall back on generic lowering.
10206 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10209 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10211 /// This routine is only called when we have AVX2 and thus a reasonable
10212 /// instruction set for v4i64 shuffling..
10213 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10214 const X86Subtarget *Subtarget,
10215 SelectionDAG &DAG) {
10217 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10218 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10219 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10220 ArrayRef<int> Mask = SVOp->getMask();
10221 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10222 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10224 SmallVector<int, 4> WidenedMask;
10225 if (canWidenShuffleElements(Mask, WidenedMask))
10226 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10229 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10233 // Check for being able to broadcast a single element.
10234 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
10235 Mask, Subtarget, DAG))
10238 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10239 // use lower latency instructions that will operate on both 128-bit lanes.
10240 SmallVector<int, 2> RepeatedMask;
10241 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10242 if (isSingleInputShuffleMask(Mask)) {
10243 int PSHUFDMask[] = {-1, -1, -1, -1};
10244 for (int i = 0; i < 2; ++i)
10245 if (RepeatedMask[i] >= 0) {
10246 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10247 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10249 return DAG.getNode(
10250 ISD::BITCAST, DL, MVT::v4i64,
10251 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10252 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
10253 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
10256 // Use dedicated unpack instructions for masks that match their pattern.
10257 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10258 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10259 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10260 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10263 // AVX2 provides a direct instruction for permuting a single input across
10265 if (isSingleInputShuffleMask(Mask))
10266 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10267 getV4X86ShuffleImm8ForMask(Mask, DAG));
10269 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10270 // shuffle. However, if we have AVX2 and either inputs are already in place,
10271 // we will be able to shuffle even across lanes the other input in a single
10272 // instruction so skip this pattern.
10273 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10274 isShuffleMaskInputInPlace(1, Mask))))
10275 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10276 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10279 // Otherwise fall back on generic blend lowering.
10280 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10284 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10286 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10287 /// isn't available.
10288 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10289 const X86Subtarget *Subtarget,
10290 SelectionDAG &DAG) {
10292 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10293 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10294 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10295 ArrayRef<int> Mask = SVOp->getMask();
10296 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10298 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10302 // Check for being able to broadcast a single element.
10303 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
10304 Mask, Subtarget, DAG))
10307 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10308 // options to efficiently lower the shuffle.
10309 SmallVector<int, 4> RepeatedMask;
10310 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10311 assert(RepeatedMask.size() == 4 &&
10312 "Repeated masks must be half the mask width!");
10313 if (isSingleInputShuffleMask(Mask))
10314 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10315 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10317 // Use dedicated unpack instructions for masks that match their pattern.
10318 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10319 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10320 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10321 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10323 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10324 // have already handled any direct blends. We also need to squash the
10325 // repeated mask into a simulated v4f32 mask.
10326 for (int i = 0; i < 4; ++i)
10327 if (RepeatedMask[i] >= 8)
10328 RepeatedMask[i] -= 4;
10329 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10332 // If we have a single input shuffle with different shuffle patterns in the
10333 // two 128-bit lanes use the variable mask to VPERMILPS.
10334 if (isSingleInputShuffleMask(Mask)) {
10335 SDValue VPermMask[8];
10336 for (int i = 0; i < 8; ++i)
10337 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10338 : DAG.getConstant(Mask[i], MVT::i32);
10339 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10340 return DAG.getNode(
10341 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10342 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10344 if (Subtarget->hasAVX2())
10345 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
10346 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
10347 DAG.getNode(ISD::BUILD_VECTOR, DL,
10348 MVT::v8i32, VPermMask)),
10351 // Otherwise, fall back.
10352 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10356 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10358 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10359 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10362 // If we have AVX2 then we always want to lower with a blend because at v8 we
10363 // can fully permute the elements.
10364 if (Subtarget->hasAVX2())
10365 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10368 // Otherwise fall back on generic lowering.
10369 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10372 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10374 /// This routine is only called when we have AVX2 and thus a reasonable
10375 /// instruction set for v8i32 shuffling..
10376 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10377 const X86Subtarget *Subtarget,
10378 SelectionDAG &DAG) {
10380 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10381 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10382 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10383 ArrayRef<int> Mask = SVOp->getMask();
10384 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10385 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10387 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10391 // Check for being able to broadcast a single element.
10392 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
10393 Mask, Subtarget, DAG))
10396 // If the shuffle mask is repeated in each 128-bit lane we can use more
10397 // efficient instructions that mirror the shuffles across the two 128-bit
10399 SmallVector<int, 4> RepeatedMask;
10400 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10401 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10402 if (isSingleInputShuffleMask(Mask))
10403 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10404 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10406 // Use dedicated unpack instructions for masks that match their pattern.
10407 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10408 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10409 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10410 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10413 // If the shuffle patterns aren't repeated but it is a single input, directly
10414 // generate a cross-lane VPERMD instruction.
10415 if (isSingleInputShuffleMask(Mask)) {
10416 SDValue VPermMask[8];
10417 for (int i = 0; i < 8; ++i)
10418 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10419 : DAG.getConstant(Mask[i], MVT::i32);
10420 return DAG.getNode(
10421 X86ISD::VPERMV, DL, MVT::v8i32,
10422 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10425 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10427 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10428 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10431 // Otherwise fall back on generic blend lowering.
10432 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10436 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10438 /// This routine is only called when we have AVX2 and thus a reasonable
10439 /// instruction set for v16i16 shuffling..
10440 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10441 const X86Subtarget *Subtarget,
10442 SelectionDAG &DAG) {
10444 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10445 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10446 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10447 ArrayRef<int> Mask = SVOp->getMask();
10448 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10449 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10451 // Check for being able to broadcast a single element.
10452 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
10453 Mask, Subtarget, DAG))
10456 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10460 // Use dedicated unpack instructions for masks that match their pattern.
10461 if (isShuffleEquivalent(Mask,
10462 // First 128-bit lane:
10463 0, 16, 1, 17, 2, 18, 3, 19,
10464 // Second 128-bit lane:
10465 8, 24, 9, 25, 10, 26, 11, 27))
10466 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10467 if (isShuffleEquivalent(Mask,
10468 // First 128-bit lane:
10469 4, 20, 5, 21, 6, 22, 7, 23,
10470 // Second 128-bit lane:
10471 12, 28, 13, 29, 14, 30, 15, 31))
10472 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10474 if (isSingleInputShuffleMask(Mask)) {
10475 // There are no generalized cross-lane shuffle operations available on i16
10477 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10478 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10481 SDValue PSHUFBMask[32];
10482 for (int i = 0; i < 16; ++i) {
10483 if (Mask[i] == -1) {
10484 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10488 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10489 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10490 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
10491 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
10493 return DAG.getNode(
10494 ISD::BITCAST, DL, MVT::v16i16,
10496 X86ISD::PSHUFB, DL, MVT::v32i8,
10497 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
10498 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
10501 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10503 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10504 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10507 // Otherwise fall back on generic lowering.
10508 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10511 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10513 /// This routine is only called when we have AVX2 and thus a reasonable
10514 /// instruction set for v32i8 shuffling..
10515 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10516 const X86Subtarget *Subtarget,
10517 SelectionDAG &DAG) {
10519 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10520 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10521 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10522 ArrayRef<int> Mask = SVOp->getMask();
10523 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10524 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10526 // Check for being able to broadcast a single element.
10527 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
10528 Mask, Subtarget, DAG))
10531 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10535 // Use dedicated unpack instructions for masks that match their pattern.
10536 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10538 if (isShuffleEquivalent(
10540 // First 128-bit lane:
10541 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10542 // Second 128-bit lane:
10543 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
10544 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10545 if (isShuffleEquivalent(
10547 // First 128-bit lane:
10548 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10549 // Second 128-bit lane:
10550 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
10551 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10553 if (isSingleInputShuffleMask(Mask)) {
10554 // There are no generalized cross-lane shuffle operations available on i8
10556 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10557 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10560 SDValue PSHUFBMask[32];
10561 for (int i = 0; i < 32; ++i)
10564 ? DAG.getUNDEF(MVT::i8)
10565 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
10567 return DAG.getNode(
10568 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10569 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10572 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10574 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10575 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10578 // Otherwise fall back on generic lowering.
10579 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10582 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10584 /// This routine either breaks down the specific type of a 256-bit x86 vector
10585 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10586 /// together based on the available instructions.
10587 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10588 MVT VT, const X86Subtarget *Subtarget,
10589 SelectionDAG &DAG) {
10591 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10592 ArrayRef<int> Mask = SVOp->getMask();
10594 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10595 // check for those subtargets here and avoid much of the subtarget querying in
10596 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10597 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10598 // floating point types there eventually, just immediately cast everything to
10599 // a float and operate entirely in that domain.
10600 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10601 int ElementBits = VT.getScalarSizeInBits();
10602 if (ElementBits < 32)
10603 // No floating point type available, decompose into 128-bit vectors.
10604 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10606 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10607 VT.getVectorNumElements());
10608 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10609 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10610 return DAG.getNode(ISD::BITCAST, DL, VT,
10611 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10614 switch (VT.SimpleTy) {
10616 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10618 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10620 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10622 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10624 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10626 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10629 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10633 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10634 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10635 const X86Subtarget *Subtarget,
10636 SelectionDAG &DAG) {
10638 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10639 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10640 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10641 ArrayRef<int> Mask = SVOp->getMask();
10642 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10644 // FIXME: Implement direct support for this type!
10645 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10648 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10649 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10650 const X86Subtarget *Subtarget,
10651 SelectionDAG &DAG) {
10653 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10654 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10655 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10656 ArrayRef<int> Mask = SVOp->getMask();
10657 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10659 // FIXME: Implement direct support for this type!
10660 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10663 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10664 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10665 const X86Subtarget *Subtarget,
10666 SelectionDAG &DAG) {
10668 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10669 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10670 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10671 ArrayRef<int> Mask = SVOp->getMask();
10672 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10674 // FIXME: Implement direct support for this type!
10675 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10678 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10679 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10680 const X86Subtarget *Subtarget,
10681 SelectionDAG &DAG) {
10683 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10684 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10685 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10686 ArrayRef<int> Mask = SVOp->getMask();
10687 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10689 // FIXME: Implement direct support for this type!
10690 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10693 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10694 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10695 const X86Subtarget *Subtarget,
10696 SelectionDAG &DAG) {
10698 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10699 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10700 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10701 ArrayRef<int> Mask = SVOp->getMask();
10702 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10703 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10705 // FIXME: Implement direct support for this type!
10706 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10709 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10710 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10711 const X86Subtarget *Subtarget,
10712 SelectionDAG &DAG) {
10714 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10715 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10716 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10717 ArrayRef<int> Mask = SVOp->getMask();
10718 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10719 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10721 // FIXME: Implement direct support for this type!
10722 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10725 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10727 /// This routine either breaks down the specific type of a 512-bit x86 vector
10728 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10729 /// together based on the available instructions.
10730 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10731 MVT VT, const X86Subtarget *Subtarget,
10732 SelectionDAG &DAG) {
10734 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10735 ArrayRef<int> Mask = SVOp->getMask();
10736 assert(Subtarget->hasAVX512() &&
10737 "Cannot lower 512-bit vectors w/ basic ISA!");
10739 // Check for being able to broadcast a single element.
10740 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(VT.SimpleTy, DL, V1,
10741 Mask, Subtarget, DAG))
10744 // Dispatch to each element type for lowering. If we don't have supprot for
10745 // specific element type shuffles at 512 bits, immediately split them and
10746 // lower them. Each lowering routine of a given type is allowed to assume that
10747 // the requisite ISA extensions for that element type are available.
10748 switch (VT.SimpleTy) {
10750 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10752 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10754 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10756 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10758 if (Subtarget->hasBWI())
10759 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10762 if (Subtarget->hasBWI())
10763 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10767 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10770 // Otherwise fall back on splitting.
10771 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10774 /// \brief Top-level lowering for x86 vector shuffles.
10776 /// This handles decomposition, canonicalization, and lowering of all x86
10777 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10778 /// above in helper routines. The canonicalization attempts to widen shuffles
10779 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10780 /// s.t. only one of the two inputs needs to be tested, etc.
10781 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10782 SelectionDAG &DAG) {
10783 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10784 ArrayRef<int> Mask = SVOp->getMask();
10785 SDValue V1 = Op.getOperand(0);
10786 SDValue V2 = Op.getOperand(1);
10787 MVT VT = Op.getSimpleValueType();
10788 int NumElements = VT.getVectorNumElements();
10791 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10793 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10794 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10795 if (V1IsUndef && V2IsUndef)
10796 return DAG.getUNDEF(VT);
10798 // When we create a shuffle node we put the UNDEF node to second operand,
10799 // but in some cases the first operand may be transformed to UNDEF.
10800 // In this case we should just commute the node.
10802 return DAG.getCommutedVectorShuffle(*SVOp);
10804 // Check for non-undef masks pointing at an undef vector and make the masks
10805 // undef as well. This makes it easier to match the shuffle based solely on
10809 if (M >= NumElements) {
10810 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10811 for (int &M : NewMask)
10812 if (M >= NumElements)
10814 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10817 // Try to collapse shuffles into using a vector type with fewer elements but
10818 // wider element types. We cap this to not form integers or floating point
10819 // elements wider than 64 bits, but it might be interesting to form i128
10820 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10821 SmallVector<int, 16> WidenedMask;
10822 if (VT.getScalarSizeInBits() < 64 &&
10823 canWidenShuffleElements(Mask, WidenedMask)) {
10824 MVT NewEltVT = VT.isFloatingPoint()
10825 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10826 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10827 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10828 // Make sure that the new vector type is legal. For example, v2f64 isn't
10830 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10831 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10832 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10833 return DAG.getNode(ISD::BITCAST, dl, VT,
10834 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10838 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10839 for (int M : SVOp->getMask())
10841 ++NumUndefElements;
10842 else if (M < NumElements)
10847 // Commute the shuffle as needed such that more elements come from V1 than
10848 // V2. This allows us to match the shuffle pattern strictly on how many
10849 // elements come from V1 without handling the symmetric cases.
10850 if (NumV2Elements > NumV1Elements)
10851 return DAG.getCommutedVectorShuffle(*SVOp);
10853 // When the number of V1 and V2 elements are the same, try to minimize the
10854 // number of uses of V2 in the low half of the vector. When that is tied,
10855 // ensure that the sum of indices for V1 is equal to or lower than the sum
10856 // indices for V2. When those are equal, try to ensure that the number of odd
10857 // indices for V1 is lower than the number of odd indices for V2.
10858 if (NumV1Elements == NumV2Elements) {
10859 int LowV1Elements = 0, LowV2Elements = 0;
10860 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10861 if (M >= NumElements)
10865 if (LowV2Elements > LowV1Elements) {
10866 return DAG.getCommutedVectorShuffle(*SVOp);
10867 } else if (LowV2Elements == LowV1Elements) {
10868 int SumV1Indices = 0, SumV2Indices = 0;
10869 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10870 if (SVOp->getMask()[i] >= NumElements)
10872 else if (SVOp->getMask()[i] >= 0)
10874 if (SumV2Indices < SumV1Indices) {
10875 return DAG.getCommutedVectorShuffle(*SVOp);
10876 } else if (SumV2Indices == SumV1Indices) {
10877 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10878 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10879 if (SVOp->getMask()[i] >= NumElements)
10880 NumV2OddIndices += i % 2;
10881 else if (SVOp->getMask()[i] >= 0)
10882 NumV1OddIndices += i % 2;
10883 if (NumV2OddIndices < NumV1OddIndices)
10884 return DAG.getCommutedVectorShuffle(*SVOp);
10889 // For each vector width, delegate to a specialized lowering routine.
10890 if (VT.getSizeInBits() == 128)
10891 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10893 if (VT.getSizeInBits() == 256)
10894 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10896 // Force AVX-512 vectors to be scalarized for now.
10897 // FIXME: Implement AVX-512 support!
10898 if (VT.getSizeInBits() == 512)
10899 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10901 llvm_unreachable("Unimplemented!");
10905 //===----------------------------------------------------------------------===//
10906 // Legacy vector shuffle lowering
10908 // This code is the legacy code handling vector shuffles until the above
10909 // replaces its functionality and performance.
10910 //===----------------------------------------------------------------------===//
10912 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10913 bool hasInt256, unsigned *MaskOut = nullptr) {
10914 MVT EltVT = VT.getVectorElementType();
10916 // There is no blend with immediate in AVX-512.
10917 if (VT.is512BitVector())
10920 if (!hasSSE41 || EltVT == MVT::i8)
10922 if (!hasInt256 && VT == MVT::v16i16)
10925 unsigned MaskValue = 0;
10926 unsigned NumElems = VT.getVectorNumElements();
10927 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10928 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10929 unsigned NumElemsInLane = NumElems / NumLanes;
10931 // Blend for v16i16 should be symetric for the both lanes.
10932 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10934 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10935 int EltIdx = MaskVals[i];
10937 if ((EltIdx < 0 || EltIdx == (int)i) &&
10938 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10941 if (((unsigned)EltIdx == (i + NumElems)) &&
10942 (SndLaneEltIdx < 0 ||
10943 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10944 MaskValue |= (1 << i);
10950 *MaskOut = MaskValue;
10954 // Try to lower a shuffle node into a simple blend instruction.
10955 // This function assumes isBlendMask returns true for this
10956 // SuffleVectorSDNode
10957 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
10958 unsigned MaskValue,
10959 const X86Subtarget *Subtarget,
10960 SelectionDAG &DAG) {
10961 MVT VT = SVOp->getSimpleValueType(0);
10962 MVT EltVT = VT.getVectorElementType();
10963 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
10964 Subtarget->hasInt256() && "Trying to lower a "
10965 "VECTOR_SHUFFLE to a Blend but "
10966 "with the wrong mask"));
10967 SDValue V1 = SVOp->getOperand(0);
10968 SDValue V2 = SVOp->getOperand(1);
10970 unsigned NumElems = VT.getVectorNumElements();
10972 // Convert i32 vectors to floating point if it is not AVX2.
10973 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10975 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10976 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10978 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
10979 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
10982 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
10983 DAG.getConstant(MaskValue, MVT::i32));
10984 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10987 /// In vector type \p VT, return true if the element at index \p InputIdx
10988 /// falls on a different 128-bit lane than \p OutputIdx.
10989 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
10990 unsigned OutputIdx) {
10991 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
10992 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
10995 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
10996 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
10997 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
10998 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
11000 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
11001 SelectionDAG &DAG) {
11002 MVT VT = V1.getSimpleValueType();
11003 assert(VT.is128BitVector() || VT.is256BitVector());
11005 MVT EltVT = VT.getVectorElementType();
11006 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
11007 unsigned NumElts = VT.getVectorNumElements();
11009 SmallVector<SDValue, 32> PshufbMask;
11010 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
11011 int InputIdx = MaskVals[OutputIdx];
11012 unsigned InputByteIdx;
11014 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
11015 InputByteIdx = 0x80;
11017 // Cross lane is not allowed.
11018 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
11020 InputByteIdx = InputIdx * EltSizeInBytes;
11021 // Index is an byte offset within the 128-bit lane.
11022 InputByteIdx &= 0xf;
11025 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
11026 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
11027 if (InputByteIdx != 0x80)
11032 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
11034 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
11035 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
11036 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
11039 // v8i16 shuffles - Prefer shuffles in the following order:
11040 // 1. [all] pshuflw, pshufhw, optional move
11041 // 2. [ssse3] 1 x pshufb
11042 // 3. [ssse3] 2 x pshufb + 1 x por
11043 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
11045 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
11046 SelectionDAG &DAG) {
11047 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11048 SDValue V1 = SVOp->getOperand(0);
11049 SDValue V2 = SVOp->getOperand(1);
11051 SmallVector<int, 8> MaskVals;
11053 // Determine if more than 1 of the words in each of the low and high quadwords
11054 // of the result come from the same quadword of one of the two inputs. Undef
11055 // mask values count as coming from any quadword, for better codegen.
11057 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
11058 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
11059 unsigned LoQuad[] = { 0, 0, 0, 0 };
11060 unsigned HiQuad[] = { 0, 0, 0, 0 };
11061 // Indices of quads used.
11062 std::bitset<4> InputQuads;
11063 for (unsigned i = 0; i < 8; ++i) {
11064 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
11065 int EltIdx = SVOp->getMaskElt(i);
11066 MaskVals.push_back(EltIdx);
11074 ++Quad[EltIdx / 4];
11075 InputQuads.set(EltIdx / 4);
11078 int BestLoQuad = -1;
11079 unsigned MaxQuad = 1;
11080 for (unsigned i = 0; i < 4; ++i) {
11081 if (LoQuad[i] > MaxQuad) {
11083 MaxQuad = LoQuad[i];
11087 int BestHiQuad = -1;
11089 for (unsigned i = 0; i < 4; ++i) {
11090 if (HiQuad[i] > MaxQuad) {
11092 MaxQuad = HiQuad[i];
11096 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
11097 // of the two input vectors, shuffle them into one input vector so only a
11098 // single pshufb instruction is necessary. If there are more than 2 input
11099 // quads, disable the next transformation since it does not help SSSE3.
11100 bool V1Used = InputQuads[0] || InputQuads[1];
11101 bool V2Used = InputQuads[2] || InputQuads[3];
11102 if (Subtarget->hasSSSE3()) {
11103 if (InputQuads.count() == 2 && V1Used && V2Used) {
11104 BestLoQuad = InputQuads[0] ? 0 : 1;
11105 BestHiQuad = InputQuads[2] ? 2 : 3;
11107 if (InputQuads.count() > 2) {
11113 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
11114 // the shuffle mask. If a quad is scored as -1, that means that it contains
11115 // words from all 4 input quadwords.
11117 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
11119 BestLoQuad < 0 ? 0 : BestLoQuad,
11120 BestHiQuad < 0 ? 1 : BestHiQuad
11122 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
11123 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
11124 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
11125 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
11127 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
11128 // source words for the shuffle, to aid later transformations.
11129 bool AllWordsInNewV = true;
11130 bool InOrder[2] = { true, true };
11131 for (unsigned i = 0; i != 8; ++i) {
11132 int idx = MaskVals[i];
11134 InOrder[i/4] = false;
11135 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
11137 AllWordsInNewV = false;
11141 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
11142 if (AllWordsInNewV) {
11143 for (int i = 0; i != 8; ++i) {
11144 int idx = MaskVals[i];
11147 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
11148 if ((idx != i) && idx < 4)
11150 if ((idx != i) && idx > 3)
11159 // If we've eliminated the use of V2, and the new mask is a pshuflw or
11160 // pshufhw, that's as cheap as it gets. Return the new shuffle.
11161 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
11162 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
11163 unsigned TargetMask = 0;
11164 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
11165 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
11166 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11167 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
11168 getShufflePSHUFLWImmediate(SVOp);
11169 V1 = NewV.getOperand(0);
11170 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
11174 // Promote splats to a larger type which usually leads to more efficient code.
11175 // FIXME: Is this true if pshufb is available?
11176 if (SVOp->isSplat())
11177 return PromoteSplat(SVOp, DAG);
11179 // If we have SSSE3, and all words of the result are from 1 input vector,
11180 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
11181 // is present, fall back to case 4.
11182 if (Subtarget->hasSSSE3()) {
11183 SmallVector<SDValue,16> pshufbMask;
11185 // If we have elements from both input vectors, set the high bit of the
11186 // shuffle mask element to zero out elements that come from V2 in the V1
11187 // mask, and elements that come from V1 in the V2 mask, so that the two
11188 // results can be OR'd together.
11189 bool TwoInputs = V1Used && V2Used;
11190 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
11192 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11194 // Calculate the shuffle mask for the second input, shuffle it, and
11195 // OR it with the first shuffled input.
11196 CommuteVectorShuffleMask(MaskVals, 8);
11197 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
11198 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11199 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11202 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
11203 // and update MaskVals with new element order.
11204 std::bitset<8> InOrder;
11205 if (BestLoQuad >= 0) {
11206 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
11207 for (int i = 0; i != 4; ++i) {
11208 int idx = MaskVals[i];
11211 } else if ((idx / 4) == BestLoQuad) {
11212 MaskV[i] = idx & 3;
11216 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11219 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11220 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11221 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
11222 NewV.getOperand(0),
11223 getShufflePSHUFLWImmediate(SVOp), DAG);
11227 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
11228 // and update MaskVals with the new element order.
11229 if (BestHiQuad >= 0) {
11230 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
11231 for (unsigned i = 4; i != 8; ++i) {
11232 int idx = MaskVals[i];
11235 } else if ((idx / 4) == BestHiQuad) {
11236 MaskV[i] = (idx & 3) + 4;
11240 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11243 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11244 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11245 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
11246 NewV.getOperand(0),
11247 getShufflePSHUFHWImmediate(SVOp), DAG);
11251 // In case BestHi & BestLo were both -1, which means each quadword has a word
11252 // from each of the four input quadwords, calculate the InOrder bitvector now
11253 // before falling through to the insert/extract cleanup.
11254 if (BestLoQuad == -1 && BestHiQuad == -1) {
11256 for (int i = 0; i != 8; ++i)
11257 if (MaskVals[i] < 0 || MaskVals[i] == i)
11261 // The other elements are put in the right place using pextrw and pinsrw.
11262 for (unsigned i = 0; i != 8; ++i) {
11265 int EltIdx = MaskVals[i];
11268 SDValue ExtOp = (EltIdx < 8) ?
11269 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
11270 DAG.getIntPtrConstant(EltIdx)) :
11271 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
11272 DAG.getIntPtrConstant(EltIdx - 8));
11273 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
11274 DAG.getIntPtrConstant(i));
11279 /// \brief v16i16 shuffles
11281 /// FIXME: We only support generation of a single pshufb currently. We can
11282 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
11283 /// well (e.g 2 x pshufb + 1 x por).
11285 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
11286 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11287 SDValue V1 = SVOp->getOperand(0);
11288 SDValue V2 = SVOp->getOperand(1);
11291 if (V2.getOpcode() != ISD::UNDEF)
11294 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11295 return getPSHUFB(MaskVals, V1, dl, DAG);
11298 // v16i8 shuffles - Prefer shuffles in the following order:
11299 // 1. [ssse3] 1 x pshufb
11300 // 2. [ssse3] 2 x pshufb + 1 x por
11301 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
11302 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
11303 const X86Subtarget* Subtarget,
11304 SelectionDAG &DAG) {
11305 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11306 SDValue V1 = SVOp->getOperand(0);
11307 SDValue V2 = SVOp->getOperand(1);
11309 ArrayRef<int> MaskVals = SVOp->getMask();
11311 // Promote splats to a larger type which usually leads to more efficient code.
11312 // FIXME: Is this true if pshufb is available?
11313 if (SVOp->isSplat())
11314 return PromoteSplat(SVOp, DAG);
11316 // If we have SSSE3, case 1 is generated when all result bytes come from
11317 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
11318 // present, fall back to case 3.
11320 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
11321 if (Subtarget->hasSSSE3()) {
11322 SmallVector<SDValue,16> pshufbMask;
11324 // If all result elements are from one input vector, then only translate
11325 // undef mask values to 0x80 (zero out result) in the pshufb mask.
11327 // Otherwise, we have elements from both input vectors, and must zero out
11328 // elements that come from V2 in the first mask, and V1 in the second mask
11329 // so that we can OR them together.
11330 for (unsigned i = 0; i != 16; ++i) {
11331 int EltIdx = MaskVals[i];
11332 if (EltIdx < 0 || EltIdx >= 16)
11334 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11336 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
11337 DAG.getNode(ISD::BUILD_VECTOR, dl,
11338 MVT::v16i8, pshufbMask));
11340 // As PSHUFB will zero elements with negative indices, it's safe to ignore
11341 // the 2nd operand if it's undefined or zero.
11342 if (V2.getOpcode() == ISD::UNDEF ||
11343 ISD::isBuildVectorAllZeros(V2.getNode()))
11346 // Calculate the shuffle mask for the second input, shuffle it, and
11347 // OR it with the first shuffled input.
11348 pshufbMask.clear();
11349 for (unsigned i = 0; i != 16; ++i) {
11350 int EltIdx = MaskVals[i];
11351 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
11352 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11354 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
11355 DAG.getNode(ISD::BUILD_VECTOR, dl,
11356 MVT::v16i8, pshufbMask));
11357 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11360 // No SSSE3 - Calculate in place words and then fix all out of place words
11361 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
11362 // the 16 different words that comprise the two doublequadword input vectors.
11363 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11364 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
11366 for (int i = 0; i != 8; ++i) {
11367 int Elt0 = MaskVals[i*2];
11368 int Elt1 = MaskVals[i*2+1];
11370 // This word of the result is all undef, skip it.
11371 if (Elt0 < 0 && Elt1 < 0)
11374 // This word of the result is already in the correct place, skip it.
11375 if ((Elt0 == i*2) && (Elt1 == i*2+1))
11378 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
11379 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
11382 // If Elt0 and Elt1 are defined, are consecutive, and can be load
11383 // using a single extract together, load it and store it.
11384 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
11385 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11386 DAG.getIntPtrConstant(Elt1 / 2));
11387 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11388 DAG.getIntPtrConstant(i));
11392 // If Elt1 is defined, extract it from the appropriate source. If the
11393 // source byte is not also odd, shift the extracted word left 8 bits
11394 // otherwise clear the bottom 8 bits if we need to do an or.
11396 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11397 DAG.getIntPtrConstant(Elt1 / 2));
11398 if ((Elt1 & 1) == 0)
11399 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
11401 TLI.getShiftAmountTy(InsElt.getValueType())));
11402 else if (Elt0 >= 0)
11403 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
11404 DAG.getConstant(0xFF00, MVT::i16));
11406 // If Elt0 is defined, extract it from the appropriate source. If the
11407 // source byte is not also even, shift the extracted word right 8 bits. If
11408 // Elt1 was also defined, OR the extracted values together before
11409 // inserting them in the result.
11411 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
11412 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
11413 if ((Elt0 & 1) != 0)
11414 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
11416 TLI.getShiftAmountTy(InsElt0.getValueType())));
11417 else if (Elt1 >= 0)
11418 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
11419 DAG.getConstant(0x00FF, MVT::i16));
11420 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
11423 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11424 DAG.getIntPtrConstant(i));
11426 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
11429 // v32i8 shuffles - Translate to VPSHUFB if possible.
11431 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
11432 const X86Subtarget *Subtarget,
11433 SelectionDAG &DAG) {
11434 MVT VT = SVOp->getSimpleValueType(0);
11435 SDValue V1 = SVOp->getOperand(0);
11436 SDValue V2 = SVOp->getOperand(1);
11438 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11440 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11441 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
11442 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
11444 // VPSHUFB may be generated if
11445 // (1) one of input vector is undefined or zeroinitializer.
11446 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
11447 // And (2) the mask indexes don't cross the 128-bit lane.
11448 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
11449 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
11452 if (V1IsAllZero && !V2IsAllZero) {
11453 CommuteVectorShuffleMask(MaskVals, 32);
11456 return getPSHUFB(MaskVals, V1, dl, DAG);
11459 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
11460 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
11461 /// done when every pair / quad of shuffle mask elements point to elements in
11462 /// the right sequence. e.g.
11463 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
11465 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
11466 SelectionDAG &DAG) {
11467 MVT VT = SVOp->getSimpleValueType(0);
11469 unsigned NumElems = VT.getVectorNumElements();
11472 switch (VT.SimpleTy) {
11473 default: llvm_unreachable("Unexpected!");
11476 return SDValue(SVOp, 0);
11477 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
11478 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
11479 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
11480 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
11481 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
11482 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
11485 SmallVector<int, 8> MaskVec;
11486 for (unsigned i = 0; i != NumElems; i += Scale) {
11488 for (unsigned j = 0; j != Scale; ++j) {
11489 int EltIdx = SVOp->getMaskElt(i+j);
11493 StartIdx = (EltIdx / Scale);
11494 if (EltIdx != (int)(StartIdx*Scale + j))
11497 MaskVec.push_back(StartIdx);
11500 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
11501 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
11502 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
11505 /// getVZextMovL - Return a zero-extending vector move low node.
11507 static SDValue getVZextMovL(MVT VT, MVT OpVT,
11508 SDValue SrcOp, SelectionDAG &DAG,
11509 const X86Subtarget *Subtarget, SDLoc dl) {
11510 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
11511 LoadSDNode *LD = nullptr;
11512 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
11513 LD = dyn_cast<LoadSDNode>(SrcOp);
11515 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
11517 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
11518 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
11519 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
11520 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
11521 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
11523 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
11524 return DAG.getNode(ISD::BITCAST, dl, VT,
11525 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11526 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11528 SrcOp.getOperand(0)
11534 return DAG.getNode(ISD::BITCAST, dl, VT,
11535 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11536 DAG.getNode(ISD::BITCAST, dl,
11540 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
11541 /// which could not be matched by any known target speficic shuffle
11543 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11545 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
11546 if (NewOp.getNode())
11549 MVT VT = SVOp->getSimpleValueType(0);
11551 unsigned NumElems = VT.getVectorNumElements();
11552 unsigned NumLaneElems = NumElems / 2;
11555 MVT EltVT = VT.getVectorElementType();
11556 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
11559 SmallVector<int, 16> Mask;
11560 for (unsigned l = 0; l < 2; ++l) {
11561 // Build a shuffle mask for the output, discovering on the fly which
11562 // input vectors to use as shuffle operands (recorded in InputUsed).
11563 // If building a suitable shuffle vector proves too hard, then bail
11564 // out with UseBuildVector set.
11565 bool UseBuildVector = false;
11566 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
11567 unsigned LaneStart = l * NumLaneElems;
11568 for (unsigned i = 0; i != NumLaneElems; ++i) {
11569 // The mask element. This indexes into the input.
11570 int Idx = SVOp->getMaskElt(i+LaneStart);
11572 // the mask element does not index into any input vector.
11573 Mask.push_back(-1);
11577 // The input vector this mask element indexes into.
11578 int Input = Idx / NumLaneElems;
11580 // Turn the index into an offset from the start of the input vector.
11581 Idx -= Input * NumLaneElems;
11583 // Find or create a shuffle vector operand to hold this input.
11585 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
11586 if (InputUsed[OpNo] == Input)
11587 // This input vector is already an operand.
11589 if (InputUsed[OpNo] < 0) {
11590 // Create a new operand for this input vector.
11591 InputUsed[OpNo] = Input;
11596 if (OpNo >= array_lengthof(InputUsed)) {
11597 // More than two input vectors used! Give up on trying to create a
11598 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
11599 UseBuildVector = true;
11603 // Add the mask index for the new shuffle vector.
11604 Mask.push_back(Idx + OpNo * NumLaneElems);
11607 if (UseBuildVector) {
11608 SmallVector<SDValue, 16> SVOps;
11609 for (unsigned i = 0; i != NumLaneElems; ++i) {
11610 // The mask element. This indexes into the input.
11611 int Idx = SVOp->getMaskElt(i+LaneStart);
11613 SVOps.push_back(DAG.getUNDEF(EltVT));
11617 // The input vector this mask element indexes into.
11618 int Input = Idx / NumElems;
11620 // Turn the index into an offset from the start of the input vector.
11621 Idx -= Input * NumElems;
11623 // Extract the vector element by hand.
11624 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11625 SVOp->getOperand(Input),
11626 DAG.getIntPtrConstant(Idx)));
11629 // Construct the output using a BUILD_VECTOR.
11630 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11631 } else if (InputUsed[0] < 0) {
11632 // No input vectors were used! The result is undefined.
11633 Output[l] = DAG.getUNDEF(NVT);
11635 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11636 (InputUsed[0] % 2) * NumLaneElems,
11638 // If only one input was used, use an undefined vector for the other.
11639 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11640 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11641 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11642 // At least one input vector was used. Create a new shuffle vector.
11643 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11649 // Concatenate the result back
11650 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11653 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11654 /// 4 elements, and match them with several different shuffle types.
11656 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11657 SDValue V1 = SVOp->getOperand(0);
11658 SDValue V2 = SVOp->getOperand(1);
11660 MVT VT = SVOp->getSimpleValueType(0);
11662 assert(VT.is128BitVector() && "Unsupported vector size");
11664 std::pair<int, int> Locs[4];
11665 int Mask1[] = { -1, -1, -1, -1 };
11666 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11668 unsigned NumHi = 0;
11669 unsigned NumLo = 0;
11670 for (unsigned i = 0; i != 4; ++i) {
11671 int Idx = PermMask[i];
11673 Locs[i] = std::make_pair(-1, -1);
11675 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11677 Locs[i] = std::make_pair(0, NumLo);
11678 Mask1[NumLo] = Idx;
11681 Locs[i] = std::make_pair(1, NumHi);
11683 Mask1[2+NumHi] = Idx;
11689 if (NumLo <= 2 && NumHi <= 2) {
11690 // If no more than two elements come from either vector. This can be
11691 // implemented with two shuffles. First shuffle gather the elements.
11692 // The second shuffle, which takes the first shuffle as both of its
11693 // vector operands, put the elements into the right order.
11694 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11696 int Mask2[] = { -1, -1, -1, -1 };
11698 for (unsigned i = 0; i != 4; ++i)
11699 if (Locs[i].first != -1) {
11700 unsigned Idx = (i < 2) ? 0 : 4;
11701 Idx += Locs[i].first * 2 + Locs[i].second;
11705 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11708 if (NumLo == 3 || NumHi == 3) {
11709 // Otherwise, we must have three elements from one vector, call it X, and
11710 // one element from the other, call it Y. First, use a shufps to build an
11711 // intermediate vector with the one element from Y and the element from X
11712 // that will be in the same half in the final destination (the indexes don't
11713 // matter). Then, use a shufps to build the final vector, taking the half
11714 // containing the element from Y from the intermediate, and the other half
11717 // Normalize it so the 3 elements come from V1.
11718 CommuteVectorShuffleMask(PermMask, 4);
11722 // Find the element from V2.
11724 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11725 int Val = PermMask[HiIndex];
11732 Mask1[0] = PermMask[HiIndex];
11734 Mask1[2] = PermMask[HiIndex^1];
11736 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11738 if (HiIndex >= 2) {
11739 Mask1[0] = PermMask[0];
11740 Mask1[1] = PermMask[1];
11741 Mask1[2] = HiIndex & 1 ? 6 : 4;
11742 Mask1[3] = HiIndex & 1 ? 4 : 6;
11743 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11746 Mask1[0] = HiIndex & 1 ? 2 : 0;
11747 Mask1[1] = HiIndex & 1 ? 0 : 2;
11748 Mask1[2] = PermMask[2];
11749 Mask1[3] = PermMask[3];
11754 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11757 // Break it into (shuffle shuffle_hi, shuffle_lo).
11758 int LoMask[] = { -1, -1, -1, -1 };
11759 int HiMask[] = { -1, -1, -1, -1 };
11761 int *MaskPtr = LoMask;
11762 unsigned MaskIdx = 0;
11763 unsigned LoIdx = 0;
11764 unsigned HiIdx = 2;
11765 for (unsigned i = 0; i != 4; ++i) {
11772 int Idx = PermMask[i];
11774 Locs[i] = std::make_pair(-1, -1);
11775 } else if (Idx < 4) {
11776 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11777 MaskPtr[LoIdx] = Idx;
11780 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11781 MaskPtr[HiIdx] = Idx;
11786 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11787 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11788 int MaskOps[] = { -1, -1, -1, -1 };
11789 for (unsigned i = 0; i != 4; ++i)
11790 if (Locs[i].first != -1)
11791 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11792 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11795 static bool MayFoldVectorLoad(SDValue V) {
11796 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11797 V = V.getOperand(0);
11799 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11800 V = V.getOperand(0);
11801 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11802 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11803 // BUILD_VECTOR (load), undef
11804 V = V.getOperand(0);
11806 return MayFoldLoad(V);
11810 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11811 MVT VT = Op.getSimpleValueType();
11813 // Canonizalize to v2f64.
11814 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11815 return DAG.getNode(ISD::BITCAST, dl, VT,
11816 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11821 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11823 SDValue V1 = Op.getOperand(0);
11824 SDValue V2 = Op.getOperand(1);
11825 MVT VT = Op.getSimpleValueType();
11827 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11829 if (HasSSE2 && VT == MVT::v2f64)
11830 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11832 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11833 return DAG.getNode(ISD::BITCAST, dl, VT,
11834 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11835 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11836 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11840 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11841 SDValue V1 = Op.getOperand(0);
11842 SDValue V2 = Op.getOperand(1);
11843 MVT VT = Op.getSimpleValueType();
11845 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11846 "unsupported shuffle type");
11848 if (V2.getOpcode() == ISD::UNDEF)
11852 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11856 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11857 SDValue V1 = Op.getOperand(0);
11858 SDValue V2 = Op.getOperand(1);
11859 MVT VT = Op.getSimpleValueType();
11860 unsigned NumElems = VT.getVectorNumElements();
11862 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11863 // operand of these instructions is only memory, so check if there's a
11864 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11866 bool CanFoldLoad = false;
11868 // Trivial case, when V2 comes from a load.
11869 if (MayFoldVectorLoad(V2))
11870 CanFoldLoad = true;
11872 // When V1 is a load, it can be folded later into a store in isel, example:
11873 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11875 // (MOVLPSmr addr:$src1, VR128:$src2)
11876 // So, recognize this potential and also use MOVLPS or MOVLPD
11877 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11878 CanFoldLoad = true;
11880 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11882 if (HasSSE2 && NumElems == 2)
11883 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11886 // If we don't care about the second element, proceed to use movss.
11887 if (SVOp->getMaskElt(1) != -1)
11888 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11891 // movl and movlp will both match v2i64, but v2i64 is never matched by
11892 // movl earlier because we make it strict to avoid messing with the movlp load
11893 // folding logic (see the code above getMOVLP call). Match it here then,
11894 // this is horrible, but will stay like this until we move all shuffle
11895 // matching to x86 specific nodes. Note that for the 1st condition all
11896 // types are matched with movsd.
11898 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11899 // as to remove this logic from here, as much as possible
11900 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11901 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11902 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11905 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11907 // Invert the operand order and use SHUFPS to match it.
11908 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11909 getShuffleSHUFImmediate(SVOp), DAG);
11912 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11913 SelectionDAG &DAG) {
11915 MVT VT = Load->getSimpleValueType(0);
11916 MVT EVT = VT.getVectorElementType();
11917 SDValue Addr = Load->getOperand(1);
11918 SDValue NewAddr = DAG.getNode(
11919 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11920 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11923 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11924 DAG.getMachineFunction().getMachineMemOperand(
11925 Load->getMemOperand(), 0, EVT.getStoreSize()));
11929 // It is only safe to call this function if isINSERTPSMask is true for
11930 // this shufflevector mask.
11931 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11932 SelectionDAG &DAG) {
11933 // Generate an insertps instruction when inserting an f32 from memory onto a
11934 // v4f32 or when copying a member from one v4f32 to another.
11935 // We also use it for transferring i32 from one register to another,
11936 // since it simply copies the same bits.
11937 // If we're transferring an i32 from memory to a specific element in a
11938 // register, we output a generic DAG that will match the PINSRD
11940 MVT VT = SVOp->getSimpleValueType(0);
11941 MVT EVT = VT.getVectorElementType();
11942 SDValue V1 = SVOp->getOperand(0);
11943 SDValue V2 = SVOp->getOperand(1);
11944 auto Mask = SVOp->getMask();
11945 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11946 "unsupported vector type for insertps/pinsrd");
11948 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11949 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11950 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11954 unsigned DestIndex;
11958 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
11961 // If we have 1 element from each vector, we have to check if we're
11962 // changing V1's element's place. If so, we're done. Otherwise, we
11963 // should assume we're changing V2's element's place and behave
11965 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
11966 assert(DestIndex <= INT32_MAX && "truncated destination index");
11967 if (FromV1 == FromV2 &&
11968 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
11972 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11975 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
11976 "More than one element from V1 and from V2, or no elements from one "
11977 "of the vectors. This case should not have returned true from "
11982 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11985 // Get an index into the source vector in the range [0,4) (the mask is
11986 // in the range [0,8) because it can address V1 and V2)
11987 unsigned SrcIndex = Mask[DestIndex] % 4;
11988 if (MayFoldLoad(From)) {
11989 // Trivial case, when From comes from a load and is only used by the
11990 // shuffle. Make it use insertps from the vector that we need from that
11993 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
11994 if (!NewLoad.getNode())
11997 if (EVT == MVT::f32) {
11998 // Create this as a scalar to vector to match the instruction pattern.
11999 SDValue LoadScalarToVector =
12000 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
12001 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
12002 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
12004 } else { // EVT == MVT::i32
12005 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
12006 // instruction, to match the PINSRD instruction, which loads an i32 to a
12007 // certain vector element.
12008 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
12009 DAG.getConstant(DestIndex, MVT::i32));
12013 // Vector-element-to-vector
12014 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
12015 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
12018 // Reduce a vector shuffle to zext.
12019 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
12020 SelectionDAG &DAG) {
12021 // PMOVZX is only available from SSE41.
12022 if (!Subtarget->hasSSE41())
12025 MVT VT = Op.getSimpleValueType();
12027 // Only AVX2 support 256-bit vector integer extending.
12028 if (!Subtarget->hasInt256() && VT.is256BitVector())
12031 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12033 SDValue V1 = Op.getOperand(0);
12034 SDValue V2 = Op.getOperand(1);
12035 unsigned NumElems = VT.getVectorNumElements();
12037 // Extending is an unary operation and the element type of the source vector
12038 // won't be equal to or larger than i64.
12039 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
12040 VT.getVectorElementType() == MVT::i64)
12043 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
12044 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
12045 while ((1U << Shift) < NumElems) {
12046 if (SVOp->getMaskElt(1U << Shift) == 1)
12049 // The maximal ratio is 8, i.e. from i8 to i64.
12054 // Check the shuffle mask.
12055 unsigned Mask = (1U << Shift) - 1;
12056 for (unsigned i = 0; i != NumElems; ++i) {
12057 int EltIdx = SVOp->getMaskElt(i);
12058 if ((i & Mask) != 0 && EltIdx != -1)
12060 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
12064 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
12065 MVT NeVT = MVT::getIntegerVT(NBits);
12066 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
12068 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
12071 return DAG.getNode(ISD::BITCAST, DL, VT,
12072 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
12075 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
12076 SelectionDAG &DAG) {
12077 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12078 MVT VT = Op.getSimpleValueType();
12080 SDValue V1 = Op.getOperand(0);
12081 SDValue V2 = Op.getOperand(1);
12083 if (isZeroShuffle(SVOp))
12084 return getZeroVector(VT, Subtarget, DAG, dl);
12086 // Handle splat operations
12087 if (SVOp->isSplat()) {
12088 // Use vbroadcast whenever the splat comes from a foldable load
12089 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
12090 if (Broadcast.getNode())
12094 // Check integer expanding shuffles.
12095 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
12096 if (NewOp.getNode())
12099 // If the shuffle can be profitably rewritten as a narrower shuffle, then
12101 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
12102 VT == MVT::v32i8) {
12103 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12104 if (NewOp.getNode())
12105 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
12106 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
12107 // FIXME: Figure out a cleaner way to do this.
12108 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
12109 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12110 if (NewOp.getNode()) {
12111 MVT NewVT = NewOp.getSimpleValueType();
12112 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
12113 NewVT, true, false))
12114 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
12117 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
12118 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12119 if (NewOp.getNode()) {
12120 MVT NewVT = NewOp.getSimpleValueType();
12121 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
12122 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
12131 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
12132 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12133 SDValue V1 = Op.getOperand(0);
12134 SDValue V2 = Op.getOperand(1);
12135 MVT VT = Op.getSimpleValueType();
12137 unsigned NumElems = VT.getVectorNumElements();
12138 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
12139 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
12140 bool V1IsSplat = false;
12141 bool V2IsSplat = false;
12142 bool HasSSE2 = Subtarget->hasSSE2();
12143 bool HasFp256 = Subtarget->hasFp256();
12144 bool HasInt256 = Subtarget->hasInt256();
12145 MachineFunction &MF = DAG.getMachineFunction();
12146 bool OptForSize = MF.getFunction()->getAttributes().
12147 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
12149 // Check if we should use the experimental vector shuffle lowering. If so,
12150 // delegate completely to that code path.
12151 if (ExperimentalVectorShuffleLowering)
12152 return lowerVectorShuffle(Op, Subtarget, DAG);
12154 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
12156 if (V1IsUndef && V2IsUndef)
12157 return DAG.getUNDEF(VT);
12159 // When we create a shuffle node we put the UNDEF node to second operand,
12160 // but in some cases the first operand may be transformed to UNDEF.
12161 // In this case we should just commute the node.
12163 return DAG.getCommutedVectorShuffle(*SVOp);
12165 // Vector shuffle lowering takes 3 steps:
12167 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
12168 // narrowing and commutation of operands should be handled.
12169 // 2) Matching of shuffles with known shuffle masks to x86 target specific
12171 // 3) Rewriting of unmatched masks into new generic shuffle operations,
12172 // so the shuffle can be broken into other shuffles and the legalizer can
12173 // try the lowering again.
12175 // The general idea is that no vector_shuffle operation should be left to
12176 // be matched during isel, all of them must be converted to a target specific
12179 // Normalize the input vectors. Here splats, zeroed vectors, profitable
12180 // narrowing and commutation of operands should be handled. The actual code
12181 // doesn't include all of those, work in progress...
12182 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
12183 if (NewOp.getNode())
12186 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
12188 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
12189 // unpckh_undef). Only use pshufd if speed is more important than size.
12190 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12191 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12192 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12193 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12195 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
12196 V2IsUndef && MayFoldVectorLoad(V1))
12197 return getMOVDDup(Op, dl, V1, DAG);
12199 if (isMOVHLPS_v_undef_Mask(M, VT))
12200 return getMOVHighToLow(Op, dl, DAG);
12202 // Use to match splats
12203 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
12204 (VT == MVT::v2f64 || VT == MVT::v2i64))
12205 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12207 if (isPSHUFDMask(M, VT)) {
12208 // The actual implementation will match the mask in the if above and then
12209 // during isel it can match several different instructions, not only pshufd
12210 // as its name says, sad but true, emulate the behavior for now...
12211 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
12212 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
12214 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
12216 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
12217 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
12219 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
12220 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
12223 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
12227 if (isPALIGNRMask(M, VT, Subtarget))
12228 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
12229 getShufflePALIGNRImmediate(SVOp),
12232 if (isVALIGNMask(M, VT, Subtarget))
12233 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
12234 getShuffleVALIGNImmediate(SVOp),
12237 // Check if this can be converted into a logical shift.
12238 bool isLeft = false;
12239 unsigned ShAmt = 0;
12241 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
12242 if (isShift && ShVal.hasOneUse()) {
12243 // If the shifted value has multiple uses, it may be cheaper to use
12244 // v_set0 + movlhps or movhlps, etc.
12245 MVT EltVT = VT.getVectorElementType();
12246 ShAmt *= EltVT.getSizeInBits();
12247 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12250 if (isMOVLMask(M, VT)) {
12251 if (ISD::isBuildVectorAllZeros(V1.getNode()))
12252 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
12253 if (!isMOVLPMask(M, VT)) {
12254 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
12255 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
12257 if (VT == MVT::v4i32 || VT == MVT::v4f32)
12258 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
12262 // FIXME: fold these into legal mask.
12263 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
12264 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
12266 if (isMOVHLPSMask(M, VT))
12267 return getMOVHighToLow(Op, dl, DAG);
12269 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
12270 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
12272 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
12273 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
12275 if (isMOVLPMask(M, VT))
12276 return getMOVLP(Op, dl, DAG, HasSSE2);
12278 if (ShouldXformToMOVHLPS(M, VT) ||
12279 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
12280 return DAG.getCommutedVectorShuffle(*SVOp);
12283 // No better options. Use a vshldq / vsrldq.
12284 MVT EltVT = VT.getVectorElementType();
12285 ShAmt *= EltVT.getSizeInBits();
12286 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12289 bool Commuted = false;
12290 // FIXME: This should also accept a bitcast of a splat? Be careful, not
12291 // 1,1,1,1 -> v8i16 though.
12292 BitVector UndefElements;
12293 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
12294 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12296 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
12297 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12300 // Canonicalize the splat or undef, if present, to be on the RHS.
12301 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
12302 CommuteVectorShuffleMask(M, NumElems);
12304 std::swap(V1IsSplat, V2IsSplat);
12308 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
12309 // Shuffling low element of v1 into undef, just return v1.
12312 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
12313 // the instruction selector will not match, so get a canonical MOVL with
12314 // swapped operands to undo the commute.
12315 return getMOVL(DAG, dl, VT, V2, V1);
12318 if (isUNPCKLMask(M, VT, HasInt256))
12319 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12321 if (isUNPCKHMask(M, VT, HasInt256))
12322 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12325 // Normalize mask so all entries that point to V2 points to its first
12326 // element then try to match unpck{h|l} again. If match, return a
12327 // new vector_shuffle with the corrected mask.p
12328 SmallVector<int, 8> NewMask(M.begin(), M.end());
12329 NormalizeMask(NewMask, NumElems);
12330 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
12331 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12332 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
12333 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12337 // Commute is back and try unpck* again.
12338 // FIXME: this seems wrong.
12339 CommuteVectorShuffleMask(M, NumElems);
12341 std::swap(V1IsSplat, V2IsSplat);
12343 if (isUNPCKLMask(M, VT, HasInt256))
12344 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12346 if (isUNPCKHMask(M, VT, HasInt256))
12347 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12350 // Normalize the node to match x86 shuffle ops if needed
12351 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
12352 return DAG.getCommutedVectorShuffle(*SVOp);
12354 // The checks below are all present in isShuffleMaskLegal, but they are
12355 // inlined here right now to enable us to directly emit target specific
12356 // nodes, and remove one by one until they don't return Op anymore.
12358 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
12359 SVOp->getSplatIndex() == 0 && V2IsUndef) {
12360 if (VT == MVT::v2f64 || VT == MVT::v2i64)
12361 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12364 if (isPSHUFHWMask(M, VT, HasInt256))
12365 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
12366 getShufflePSHUFHWImmediate(SVOp),
12369 if (isPSHUFLWMask(M, VT, HasInt256))
12370 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
12371 getShufflePSHUFLWImmediate(SVOp),
12374 unsigned MaskValue;
12375 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
12377 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
12379 if (isSHUFPMask(M, VT))
12380 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
12381 getShuffleSHUFImmediate(SVOp), DAG);
12383 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12384 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12385 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12386 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12388 //===--------------------------------------------------------------------===//
12389 // Generate target specific nodes for 128 or 256-bit shuffles only
12390 // supported in the AVX instruction set.
12393 // Handle VMOVDDUPY permutations
12394 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
12395 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
12397 // Handle VPERMILPS/D* permutations
12398 if (isVPERMILPMask(M, VT)) {
12399 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
12400 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
12401 getShuffleSHUFImmediate(SVOp), DAG);
12402 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
12403 getShuffleSHUFImmediate(SVOp), DAG);
12407 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
12408 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
12409 Idx*(NumElems/2), DAG, dl);
12411 // Handle VPERM2F128/VPERM2I128 permutations
12412 if (isVPERM2X128Mask(M, VT, HasFp256))
12413 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
12414 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
12416 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
12417 return getINSERTPS(SVOp, dl, DAG);
12420 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
12421 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
12423 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
12424 VT.is512BitVector()) {
12425 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
12426 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
12427 SmallVector<SDValue, 16> permclMask;
12428 for (unsigned i = 0; i != NumElems; ++i) {
12429 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
12432 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
12434 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
12435 return DAG.getNode(X86ISD::VPERMV, dl, VT,
12436 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
12437 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
12438 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
12441 //===--------------------------------------------------------------------===//
12442 // Since no target specific shuffle was selected for this generic one,
12443 // lower it into other known shuffles. FIXME: this isn't true yet, but
12444 // this is the plan.
12447 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
12448 if (VT == MVT::v8i16) {
12449 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
12450 if (NewOp.getNode())
12454 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
12455 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
12456 if (NewOp.getNode())
12460 if (VT == MVT::v16i8) {
12461 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
12462 if (NewOp.getNode())
12466 if (VT == MVT::v32i8) {
12467 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
12468 if (NewOp.getNode())
12472 // Handle all 128-bit wide vectors with 4 elements, and match them with
12473 // several different shuffle types.
12474 if (NumElems == 4 && VT.is128BitVector())
12475 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
12477 // Handle general 256-bit shuffles
12478 if (VT.is256BitVector())
12479 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
12484 // This function assumes its argument is a BUILD_VECTOR of constants or
12485 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
12487 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
12488 unsigned &MaskValue) {
12490 unsigned NumElems = BuildVector->getNumOperands();
12491 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
12492 unsigned NumLanes = (NumElems - 1) / 8 + 1;
12493 unsigned NumElemsInLane = NumElems / NumLanes;
12495 // Blend for v16i16 should be symetric for the both lanes.
12496 for (unsigned i = 0; i < NumElemsInLane; ++i) {
12497 SDValue EltCond = BuildVector->getOperand(i);
12498 SDValue SndLaneEltCond =
12499 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
12501 int Lane1Cond = -1, Lane2Cond = -1;
12502 if (isa<ConstantSDNode>(EltCond))
12503 Lane1Cond = !isZero(EltCond);
12504 if (isa<ConstantSDNode>(SndLaneEltCond))
12505 Lane2Cond = !isZero(SndLaneEltCond);
12507 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
12508 // Lane1Cond != 0, means we want the first argument.
12509 // Lane1Cond == 0, means we want the second argument.
12510 // The encoding of this argument is 0 for the first argument, 1
12511 // for the second. Therefore, invert the condition.
12512 MaskValue |= !Lane1Cond << i;
12513 else if (Lane1Cond < 0)
12514 MaskValue |= !Lane2Cond << i;
12521 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
12523 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
12524 SelectionDAG &DAG) {
12525 SDValue Cond = Op.getOperand(0);
12526 SDValue LHS = Op.getOperand(1);
12527 SDValue RHS = Op.getOperand(2);
12529 MVT VT = Op.getSimpleValueType();
12530 MVT EltVT = VT.getVectorElementType();
12531 unsigned NumElems = VT.getVectorNumElements();
12533 // There is no blend with immediate in AVX-512.
12534 if (VT.is512BitVector())
12537 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
12539 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
12542 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
12545 // Check the mask for BLEND and build the value.
12546 unsigned MaskValue = 0;
12547 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
12550 // Convert i32 vectors to floating point if it is not AVX2.
12551 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
12553 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
12554 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
12556 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
12557 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
12560 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
12561 DAG.getConstant(MaskValue, MVT::i32));
12562 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
12565 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
12566 // A vselect where all conditions and data are constants can be optimized into
12567 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
12568 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
12569 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
12570 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
12573 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
12574 if (BlendOp.getNode())
12577 // Some types for vselect were previously set to Expand, not Legal or
12578 // Custom. Return an empty SDValue so we fall-through to Expand, after
12579 // the Custom lowering phase.
12580 MVT VT = Op.getSimpleValueType();
12581 switch (VT.SimpleTy) {
12586 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12591 // We couldn't create a "Blend with immediate" node.
12592 // This node should still be legal, but we'll have to emit a blendv*
12597 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12598 MVT VT = Op.getSimpleValueType();
12601 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12604 if (VT.getSizeInBits() == 8) {
12605 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12606 Op.getOperand(0), Op.getOperand(1));
12607 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12608 DAG.getValueType(VT));
12609 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12612 if (VT.getSizeInBits() == 16) {
12613 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12614 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12616 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12617 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12618 DAG.getNode(ISD::BITCAST, dl,
12621 Op.getOperand(1)));
12622 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12623 Op.getOperand(0), Op.getOperand(1));
12624 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12625 DAG.getValueType(VT));
12626 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12629 if (VT == MVT::f32) {
12630 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12631 // the result back to FR32 register. It's only worth matching if the
12632 // result has a single use which is a store or a bitcast to i32. And in
12633 // the case of a store, it's not worth it if the index is a constant 0,
12634 // because a MOVSSmr can be used instead, which is smaller and faster.
12635 if (!Op.hasOneUse())
12637 SDNode *User = *Op.getNode()->use_begin();
12638 if ((User->getOpcode() != ISD::STORE ||
12639 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12640 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12641 (User->getOpcode() != ISD::BITCAST ||
12642 User->getValueType(0) != MVT::i32))
12644 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12645 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12648 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12651 if (VT == MVT::i32 || VT == MVT::i64) {
12652 // ExtractPS/pextrq works with constant index.
12653 if (isa<ConstantSDNode>(Op.getOperand(1)))
12659 /// Extract one bit from mask vector, like v16i1 or v8i1.
12660 /// AVX-512 feature.
12662 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12663 SDValue Vec = Op.getOperand(0);
12665 MVT VecVT = Vec.getSimpleValueType();
12666 SDValue Idx = Op.getOperand(1);
12667 MVT EltVT = Op.getSimpleValueType();
12669 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12671 // variable index can't be handled in mask registers,
12672 // extend vector to VR512
12673 if (!isa<ConstantSDNode>(Idx)) {
12674 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12675 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12676 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12677 ExtVT.getVectorElementType(), Ext, Idx);
12678 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12681 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12682 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12683 unsigned MaxSift = rc->getSize()*8 - 1;
12684 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12685 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12686 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12687 DAG.getConstant(MaxSift, MVT::i8));
12688 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12689 DAG.getIntPtrConstant(0));
12693 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12694 SelectionDAG &DAG) const {
12696 SDValue Vec = Op.getOperand(0);
12697 MVT VecVT = Vec.getSimpleValueType();
12698 SDValue Idx = Op.getOperand(1);
12700 if (Op.getSimpleValueType() == MVT::i1)
12701 return ExtractBitFromMaskVector(Op, DAG);
12703 if (!isa<ConstantSDNode>(Idx)) {
12704 if (VecVT.is512BitVector() ||
12705 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12706 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12709 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12710 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12711 MaskEltVT.getSizeInBits());
12713 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12714 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12715 getZeroVector(MaskVT, Subtarget, DAG, dl),
12716 Idx, DAG.getConstant(0, getPointerTy()));
12717 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12718 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12719 Perm, DAG.getConstant(0, getPointerTy()));
12724 // If this is a 256-bit vector result, first extract the 128-bit vector and
12725 // then extract the element from the 128-bit vector.
12726 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12728 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12729 // Get the 128-bit vector.
12730 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12731 MVT EltVT = VecVT.getVectorElementType();
12733 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12735 //if (IdxVal >= NumElems/2)
12736 // IdxVal -= NumElems/2;
12737 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12738 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12739 DAG.getConstant(IdxVal, MVT::i32));
12742 assert(VecVT.is128BitVector() && "Unexpected vector length");
12744 if (Subtarget->hasSSE41()) {
12745 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12750 MVT VT = Op.getSimpleValueType();
12751 // TODO: handle v16i8.
12752 if (VT.getSizeInBits() == 16) {
12753 SDValue Vec = Op.getOperand(0);
12754 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12756 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12757 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12758 DAG.getNode(ISD::BITCAST, dl,
12760 Op.getOperand(1)));
12761 // Transform it so it match pextrw which produces a 32-bit result.
12762 MVT EltVT = MVT::i32;
12763 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12764 Op.getOperand(0), Op.getOperand(1));
12765 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12766 DAG.getValueType(VT));
12767 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12770 if (VT.getSizeInBits() == 32) {
12771 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12775 // SHUFPS the element to the lowest double word, then movss.
12776 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12777 MVT VVT = Op.getOperand(0).getSimpleValueType();
12778 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12779 DAG.getUNDEF(VVT), Mask);
12780 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12781 DAG.getIntPtrConstant(0));
12784 if (VT.getSizeInBits() == 64) {
12785 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12786 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12787 // to match extract_elt for f64.
12788 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12792 // UNPCKHPD the element to the lowest double word, then movsd.
12793 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12794 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12795 int Mask[2] = { 1, -1 };
12796 MVT VVT = Op.getOperand(0).getSimpleValueType();
12797 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12798 DAG.getUNDEF(VVT), Mask);
12799 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12800 DAG.getIntPtrConstant(0));
12806 /// Insert one bit to mask vector, like v16i1 or v8i1.
12807 /// AVX-512 feature.
12809 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12811 SDValue Vec = Op.getOperand(0);
12812 SDValue Elt = Op.getOperand(1);
12813 SDValue Idx = Op.getOperand(2);
12814 MVT VecVT = Vec.getSimpleValueType();
12816 if (!isa<ConstantSDNode>(Idx)) {
12817 // Non constant index. Extend source and destination,
12818 // insert element and then truncate the result.
12819 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12820 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12821 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12822 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12823 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12824 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12827 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12828 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12829 if (Vec.getOpcode() == ISD::UNDEF)
12830 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12831 DAG.getConstant(IdxVal, MVT::i8));
12832 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12833 unsigned MaxSift = rc->getSize()*8 - 1;
12834 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12835 DAG.getConstant(MaxSift, MVT::i8));
12836 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12837 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12838 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12841 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12842 SelectionDAG &DAG) const {
12843 MVT VT = Op.getSimpleValueType();
12844 MVT EltVT = VT.getVectorElementType();
12846 if (EltVT == MVT::i1)
12847 return InsertBitToMaskVector(Op, DAG);
12850 SDValue N0 = Op.getOperand(0);
12851 SDValue N1 = Op.getOperand(1);
12852 SDValue N2 = Op.getOperand(2);
12853 if (!isa<ConstantSDNode>(N2))
12855 auto *N2C = cast<ConstantSDNode>(N2);
12856 unsigned IdxVal = N2C->getZExtValue();
12858 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12859 // into that, and then insert the subvector back into the result.
12860 if (VT.is256BitVector() || VT.is512BitVector()) {
12861 // Get the desired 128-bit vector half.
12862 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12864 // Insert the element into the desired half.
12865 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12866 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12868 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12869 DAG.getConstant(IdxIn128, MVT::i32));
12871 // Insert the changed part back to the 256-bit vector
12872 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12874 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12876 if (Subtarget->hasSSE41()) {
12877 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12879 if (VT == MVT::v8i16) {
12880 Opc = X86ISD::PINSRW;
12882 assert(VT == MVT::v16i8);
12883 Opc = X86ISD::PINSRB;
12886 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12888 if (N1.getValueType() != MVT::i32)
12889 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12890 if (N2.getValueType() != MVT::i32)
12891 N2 = DAG.getIntPtrConstant(IdxVal);
12892 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12895 if (EltVT == MVT::f32) {
12896 // Bits [7:6] of the constant are the source select. This will always be
12897 // zero here. The DAG Combiner may combine an extract_elt index into
12899 // bits. For example (insert (extract, 3), 2) could be matched by
12901 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12902 // Bits [5:4] of the constant are the destination select. This is the
12903 // value of the incoming immediate.
12904 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12905 // combine either bitwise AND or insert of float 0.0 to set these bits.
12906 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12907 // Create this as a scalar to vector..
12908 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12909 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12912 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12913 // PINSR* works with constant index.
12918 if (EltVT == MVT::i8)
12921 if (EltVT.getSizeInBits() == 16) {
12922 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12923 // as its second argument.
12924 if (N1.getValueType() != MVT::i32)
12925 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12926 if (N2.getValueType() != MVT::i32)
12927 N2 = DAG.getIntPtrConstant(IdxVal);
12928 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12933 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12935 MVT OpVT = Op.getSimpleValueType();
12937 // If this is a 256-bit vector result, first insert into a 128-bit
12938 // vector and then insert into the 256-bit vector.
12939 if (!OpVT.is128BitVector()) {
12940 // Insert into a 128-bit vector.
12941 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12942 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12943 OpVT.getVectorNumElements() / SizeFactor);
12945 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12947 // Insert the 128-bit vector.
12948 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12951 if (OpVT == MVT::v1i64 &&
12952 Op.getOperand(0).getValueType() == MVT::i64)
12953 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12955 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12956 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12957 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12958 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12961 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12962 // a simple subregister reference or explicit instructions to grab
12963 // upper bits of a vector.
12964 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12965 SelectionDAG &DAG) {
12967 SDValue In = Op.getOperand(0);
12968 SDValue Idx = Op.getOperand(1);
12969 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12970 MVT ResVT = Op.getSimpleValueType();
12971 MVT InVT = In.getSimpleValueType();
12973 if (Subtarget->hasFp256()) {
12974 if (ResVT.is128BitVector() &&
12975 (InVT.is256BitVector() || InVT.is512BitVector()) &&
12976 isa<ConstantSDNode>(Idx)) {
12977 return Extract128BitVector(In, IdxVal, DAG, dl);
12979 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
12980 isa<ConstantSDNode>(Idx)) {
12981 return Extract256BitVector(In, IdxVal, DAG, dl);
12987 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12988 // simple superregister reference or explicit instructions to insert
12989 // the upper bits of a vector.
12990 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12991 SelectionDAG &DAG) {
12992 if (Subtarget->hasFp256()) {
12993 SDLoc dl(Op.getNode());
12994 SDValue Vec = Op.getNode()->getOperand(0);
12995 SDValue SubVec = Op.getNode()->getOperand(1);
12996 SDValue Idx = Op.getNode()->getOperand(2);
12998 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
12999 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
13000 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
13001 isa<ConstantSDNode>(Idx)) {
13002 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13003 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
13006 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
13007 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
13008 isa<ConstantSDNode>(Idx)) {
13009 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13010 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
13016 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
13017 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
13018 // one of the above mentioned nodes. It has to be wrapped because otherwise
13019 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
13020 // be used to form addressing mode. These wrapped nodes will be selected
13023 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
13024 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
13026 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13027 // global base reg.
13028 unsigned char OpFlag = 0;
13029 unsigned WrapperKind = X86ISD::Wrapper;
13030 CodeModel::Model M = DAG.getTarget().getCodeModel();
13032 if (Subtarget->isPICStyleRIPRel() &&
13033 (M == CodeModel::Small || M == CodeModel::Kernel))
13034 WrapperKind = X86ISD::WrapperRIP;
13035 else if (Subtarget->isPICStyleGOT())
13036 OpFlag = X86II::MO_GOTOFF;
13037 else if (Subtarget->isPICStyleStubPIC())
13038 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13040 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
13041 CP->getAlignment(),
13042 CP->getOffset(), OpFlag);
13044 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13045 // With PIC, the address is actually $g + Offset.
13047 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13048 DAG.getNode(X86ISD::GlobalBaseReg,
13049 SDLoc(), getPointerTy()),
13056 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
13057 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
13059 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13060 // global base reg.
13061 unsigned char OpFlag = 0;
13062 unsigned WrapperKind = X86ISD::Wrapper;
13063 CodeModel::Model M = DAG.getTarget().getCodeModel();
13065 if (Subtarget->isPICStyleRIPRel() &&
13066 (M == CodeModel::Small || M == CodeModel::Kernel))
13067 WrapperKind = X86ISD::WrapperRIP;
13068 else if (Subtarget->isPICStyleGOT())
13069 OpFlag = X86II::MO_GOTOFF;
13070 else if (Subtarget->isPICStyleStubPIC())
13071 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13073 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
13076 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13078 // With PIC, the address is actually $g + Offset.
13080 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13081 DAG.getNode(X86ISD::GlobalBaseReg,
13082 SDLoc(), getPointerTy()),
13089 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
13090 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
13092 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13093 // global base reg.
13094 unsigned char OpFlag = 0;
13095 unsigned WrapperKind = X86ISD::Wrapper;
13096 CodeModel::Model M = DAG.getTarget().getCodeModel();
13098 if (Subtarget->isPICStyleRIPRel() &&
13099 (M == CodeModel::Small || M == CodeModel::Kernel)) {
13100 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
13101 OpFlag = X86II::MO_GOTPCREL;
13102 WrapperKind = X86ISD::WrapperRIP;
13103 } else if (Subtarget->isPICStyleGOT()) {
13104 OpFlag = X86II::MO_GOT;
13105 } else if (Subtarget->isPICStyleStubPIC()) {
13106 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
13107 } else if (Subtarget->isPICStyleStubNoDynamic()) {
13108 OpFlag = X86II::MO_DARWIN_NONLAZY;
13111 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
13114 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13116 // With PIC, the address is actually $g + Offset.
13117 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
13118 !Subtarget->is64Bit()) {
13119 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13120 DAG.getNode(X86ISD::GlobalBaseReg,
13121 SDLoc(), getPointerTy()),
13125 // For symbols that require a load from a stub to get the address, emit the
13127 if (isGlobalStubReference(OpFlag))
13128 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
13129 MachinePointerInfo::getGOT(), false, false, false, 0);
13135 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
13136 // Create the TargetBlockAddressAddress node.
13137 unsigned char OpFlags =
13138 Subtarget->ClassifyBlockAddressReference();
13139 CodeModel::Model M = DAG.getTarget().getCodeModel();
13140 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
13141 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
13143 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
13146 if (Subtarget->isPICStyleRIPRel() &&
13147 (M == CodeModel::Small || M == CodeModel::Kernel))
13148 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13150 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13152 // With PIC, the address is actually $g + Offset.
13153 if (isGlobalRelativeToPICBase(OpFlags)) {
13154 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13155 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13163 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
13164 int64_t Offset, SelectionDAG &DAG) const {
13165 // Create the TargetGlobalAddress node, folding in the constant
13166 // offset if it is legal.
13167 unsigned char OpFlags =
13168 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
13169 CodeModel::Model M = DAG.getTarget().getCodeModel();
13171 if (OpFlags == X86II::MO_NO_FLAG &&
13172 X86::isOffsetSuitableForCodeModel(Offset, M)) {
13173 // A direct static reference to a global.
13174 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
13177 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
13180 if (Subtarget->isPICStyleRIPRel() &&
13181 (M == CodeModel::Small || M == CodeModel::Kernel))
13182 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13184 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13186 // With PIC, the address is actually $g + Offset.
13187 if (isGlobalRelativeToPICBase(OpFlags)) {
13188 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13189 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13193 // For globals that require a load from a stub to get the address, emit the
13195 if (isGlobalStubReference(OpFlags))
13196 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
13197 MachinePointerInfo::getGOT(), false, false, false, 0);
13199 // If there was a non-zero offset that we didn't fold, create an explicit
13200 // addition for it.
13202 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
13203 DAG.getConstant(Offset, getPointerTy()));
13209 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
13210 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
13211 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
13212 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
13216 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
13217 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
13218 unsigned char OperandFlags, bool LocalDynamic = false) {
13219 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13220 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13222 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13223 GA->getValueType(0),
13227 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
13231 SDValue Ops[] = { Chain, TGA, *InFlag };
13232 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13234 SDValue Ops[] = { Chain, TGA };
13235 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13238 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
13239 MFI->setAdjustsStack(true);
13240 MFI->setHasCalls(true);
13242 SDValue Flag = Chain.getValue(1);
13243 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
13246 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
13248 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13251 SDLoc dl(GA); // ? function entry point might be better
13252 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13253 DAG.getNode(X86ISD::GlobalBaseReg,
13254 SDLoc(), PtrVT), InFlag);
13255 InFlag = Chain.getValue(1);
13257 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
13260 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
13262 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13264 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
13265 X86::RAX, X86II::MO_TLSGD);
13268 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
13274 // Get the start address of the TLS block for this module.
13275 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
13276 .getInfo<X86MachineFunctionInfo>();
13277 MFI->incNumLocalDynamicTLSAccesses();
13281 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
13282 X86II::MO_TLSLD, /*LocalDynamic=*/true);
13285 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13286 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
13287 InFlag = Chain.getValue(1);
13288 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
13289 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
13292 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
13296 unsigned char OperandFlags = X86II::MO_DTPOFF;
13297 unsigned WrapperKind = X86ISD::Wrapper;
13298 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13299 GA->getValueType(0),
13300 GA->getOffset(), OperandFlags);
13301 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13303 // Add x@dtpoff with the base.
13304 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
13307 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
13308 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13309 const EVT PtrVT, TLSModel::Model model,
13310 bool is64Bit, bool isPIC) {
13313 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
13314 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
13315 is64Bit ? 257 : 256));
13317 SDValue ThreadPointer =
13318 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
13319 MachinePointerInfo(Ptr), false, false, false, 0);
13321 unsigned char OperandFlags = 0;
13322 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
13324 unsigned WrapperKind = X86ISD::Wrapper;
13325 if (model == TLSModel::LocalExec) {
13326 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
13327 } else if (model == TLSModel::InitialExec) {
13329 OperandFlags = X86II::MO_GOTTPOFF;
13330 WrapperKind = X86ISD::WrapperRIP;
13332 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
13335 llvm_unreachable("Unexpected model");
13338 // emit "addl x@ntpoff,%eax" (local exec)
13339 // or "addl x@indntpoff,%eax" (initial exec)
13340 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
13342 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
13343 GA->getOffset(), OperandFlags);
13344 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13346 if (model == TLSModel::InitialExec) {
13347 if (isPIC && !is64Bit) {
13348 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
13349 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
13353 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
13354 MachinePointerInfo::getGOT(), false, false, false, 0);
13357 // The address of the thread local variable is the add of the thread
13358 // pointer with the offset of the variable.
13359 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
13363 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
13365 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
13366 const GlobalValue *GV = GA->getGlobal();
13368 if (Subtarget->isTargetELF()) {
13369 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
13372 case TLSModel::GeneralDynamic:
13373 if (Subtarget->is64Bit())
13374 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
13375 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
13376 case TLSModel::LocalDynamic:
13377 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
13378 Subtarget->is64Bit());
13379 case TLSModel::InitialExec:
13380 case TLSModel::LocalExec:
13381 return LowerToTLSExecModel(
13382 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
13383 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
13385 llvm_unreachable("Unknown TLS model.");
13388 if (Subtarget->isTargetDarwin()) {
13389 // Darwin only has one model of TLS. Lower to that.
13390 unsigned char OpFlag = 0;
13391 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
13392 X86ISD::WrapperRIP : X86ISD::Wrapper;
13394 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13395 // global base reg.
13396 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
13397 !Subtarget->is64Bit();
13399 OpFlag = X86II::MO_TLVP_PIC_BASE;
13401 OpFlag = X86II::MO_TLVP;
13403 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
13404 GA->getValueType(0),
13405 GA->getOffset(), OpFlag);
13406 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13408 // With PIC32, the address is actually $g + Offset.
13410 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13411 DAG.getNode(X86ISD::GlobalBaseReg,
13412 SDLoc(), getPointerTy()),
13415 // Lowering the machine isd will make sure everything is in the right
13417 SDValue Chain = DAG.getEntryNode();
13418 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13419 SDValue Args[] = { Chain, Offset };
13420 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
13422 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
13423 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13424 MFI->setAdjustsStack(true);
13426 // And our return value (tls address) is in the standard call return value
13428 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
13429 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
13430 Chain.getValue(1));
13433 if (Subtarget->isTargetKnownWindowsMSVC() ||
13434 Subtarget->isTargetWindowsGNU()) {
13435 // Just use the implicit TLS architecture
13436 // Need to generate someting similar to:
13437 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
13439 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
13440 // mov rcx, qword [rdx+rcx*8]
13441 // mov eax, .tls$:tlsvar
13442 // [rax+rcx] contains the address
13443 // Windows 64bit: gs:0x58
13444 // Windows 32bit: fs:__tls_array
13447 SDValue Chain = DAG.getEntryNode();
13449 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
13450 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
13451 // use its literal value of 0x2C.
13452 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
13453 ? Type::getInt8PtrTy(*DAG.getContext(),
13455 : Type::getInt32PtrTy(*DAG.getContext(),
13459 Subtarget->is64Bit()
13460 ? DAG.getIntPtrConstant(0x58)
13461 : (Subtarget->isTargetWindowsGNU()
13462 ? DAG.getIntPtrConstant(0x2C)
13463 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
13465 SDValue ThreadPointer =
13466 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
13467 MachinePointerInfo(Ptr), false, false, false, 0);
13469 // Load the _tls_index variable
13470 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
13471 if (Subtarget->is64Bit())
13472 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
13473 IDX, MachinePointerInfo(), MVT::i32,
13474 false, false, false, 0);
13476 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
13477 false, false, false, 0);
13479 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
13481 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
13483 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
13484 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
13485 false, false, false, 0);
13487 // Get the offset of start of .tls section
13488 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13489 GA->getValueType(0),
13490 GA->getOffset(), X86II::MO_SECREL);
13491 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
13493 // The address of the thread local variable is the add of the thread
13494 // pointer with the offset of the variable.
13495 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
13498 llvm_unreachable("TLS not implemented for this target.");
13501 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
13502 /// and take a 2 x i32 value to shift plus a shift amount.
13503 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
13504 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
13505 MVT VT = Op.getSimpleValueType();
13506 unsigned VTBits = VT.getSizeInBits();
13508 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
13509 SDValue ShOpLo = Op.getOperand(0);
13510 SDValue ShOpHi = Op.getOperand(1);
13511 SDValue ShAmt = Op.getOperand(2);
13512 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
13513 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
13515 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13516 DAG.getConstant(VTBits - 1, MVT::i8));
13517 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
13518 DAG.getConstant(VTBits - 1, MVT::i8))
13519 : DAG.getConstant(0, VT);
13521 SDValue Tmp2, Tmp3;
13522 if (Op.getOpcode() == ISD::SHL_PARTS) {
13523 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
13524 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
13526 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
13527 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
13530 // If the shift amount is larger or equal than the width of a part we can't
13531 // rely on the results of shld/shrd. Insert a test and select the appropriate
13532 // values for large shift amounts.
13533 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13534 DAG.getConstant(VTBits, MVT::i8));
13535 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13536 AndNode, DAG.getConstant(0, MVT::i8));
13539 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13540 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13541 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13543 if (Op.getOpcode() == ISD::SHL_PARTS) {
13544 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13545 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13547 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13548 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13551 SDValue Ops[2] = { Lo, Hi };
13552 return DAG.getMergeValues(Ops, dl);
13555 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
13556 SelectionDAG &DAG) const {
13557 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13560 if (SrcVT.isVector()) {
13561 if (SrcVT.getVectorElementType() == MVT::i1) {
13562 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
13563 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13564 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
13565 Op.getOperand(0)));
13570 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
13571 "Unknown SINT_TO_FP to lower!");
13573 // These are really Legal; return the operand so the caller accepts it as
13575 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
13577 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
13578 Subtarget->is64Bit()) {
13582 unsigned Size = SrcVT.getSizeInBits()/8;
13583 MachineFunction &MF = DAG.getMachineFunction();
13584 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
13585 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13586 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13588 MachinePointerInfo::getFixedStack(SSFI),
13590 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13593 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13595 SelectionDAG &DAG) const {
13599 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13601 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13603 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13605 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13607 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13608 MachineMemOperand *MMO;
13610 int SSFI = FI->getIndex();
13612 DAG.getMachineFunction()
13613 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13614 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13616 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13617 StackSlot = StackSlot.getOperand(1);
13619 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13620 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13622 Tys, Ops, SrcVT, MMO);
13625 Chain = Result.getValue(1);
13626 SDValue InFlag = Result.getValue(2);
13628 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13629 // shouldn't be necessary except that RFP cannot be live across
13630 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13631 MachineFunction &MF = DAG.getMachineFunction();
13632 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13633 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13634 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13635 Tys = DAG.getVTList(MVT::Other);
13637 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13639 MachineMemOperand *MMO =
13640 DAG.getMachineFunction()
13641 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13642 MachineMemOperand::MOStore, SSFISize, SSFISize);
13644 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13645 Ops, Op.getValueType(), MMO);
13646 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13647 MachinePointerInfo::getFixedStack(SSFI),
13648 false, false, false, 0);
13654 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13655 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13656 SelectionDAG &DAG) const {
13657 // This algorithm is not obvious. Here it is what we're trying to output:
13660 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13661 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13663 haddpd %xmm0, %xmm0
13665 pshufd $0x4e, %xmm0, %xmm1
13671 LLVMContext *Context = DAG.getContext();
13673 // Build some magic constants.
13674 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13675 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13676 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13678 SmallVector<Constant*,2> CV1;
13680 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13681 APInt(64, 0x4330000000000000ULL))));
13683 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13684 APInt(64, 0x4530000000000000ULL))));
13685 Constant *C1 = ConstantVector::get(CV1);
13686 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13688 // Load the 64-bit value into an XMM register.
13689 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13691 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13692 MachinePointerInfo::getConstantPool(),
13693 false, false, false, 16);
13694 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13695 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13698 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13699 MachinePointerInfo::getConstantPool(),
13700 false, false, false, 16);
13701 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13702 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13705 if (Subtarget->hasSSE3()) {
13706 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13707 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13709 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13710 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13712 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13713 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13717 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13718 DAG.getIntPtrConstant(0));
13721 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13722 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13723 SelectionDAG &DAG) const {
13725 // FP constant to bias correct the final result.
13726 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13729 // Load the 32-bit value into an XMM register.
13730 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13733 // Zero out the upper parts of the register.
13734 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13736 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13737 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13738 DAG.getIntPtrConstant(0));
13740 // Or the load with the bias.
13741 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13742 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13743 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13744 MVT::v2f64, Load)),
13745 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13746 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13747 MVT::v2f64, Bias)));
13748 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13749 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13750 DAG.getIntPtrConstant(0));
13752 // Subtract the bias.
13753 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13755 // Handle final rounding.
13756 EVT DestVT = Op.getValueType();
13758 if (DestVT.bitsLT(MVT::f64))
13759 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13760 DAG.getIntPtrConstant(0));
13761 if (DestVT.bitsGT(MVT::f64))
13762 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13764 // Handle final rounding.
13768 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
13769 const X86Subtarget &Subtarget) {
13770 // The algorithm is the following:
13771 // #ifdef __SSE4_1__
13772 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13773 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13774 // (uint4) 0x53000000, 0xaa);
13776 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13777 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13779 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13780 // return (float4) lo + fhi;
13783 SDValue V = Op->getOperand(0);
13784 EVT VecIntVT = V.getValueType();
13785 bool Is128 = VecIntVT == MVT::v4i32;
13786 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
13787 // If we convert to something else than the supported type, e.g., to v4f64,
13789 if (VecFloatVT != Op->getValueType(0))
13792 unsigned NumElts = VecIntVT.getVectorNumElements();
13793 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
13794 "Unsupported custom type");
13795 assert(NumElts <= 8 && "The size of the constant array must be fixed");
13797 // In the #idef/#else code, we have in common:
13798 // - The vector of constants:
13804 // Create the splat vector for 0x4b000000.
13805 SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);
13806 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
13807 CstLow, CstLow, CstLow, CstLow};
13808 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13809 makeArrayRef(&CstLowArray[0], NumElts));
13810 // Create the splat vector for 0x53000000.
13811 SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);
13812 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
13813 CstHigh, CstHigh, CstHigh, CstHigh};
13814 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13815 makeArrayRef(&CstHighArray[0], NumElts));
13817 // Create the right shift.
13818 SDValue CstShift = DAG.getConstant(16, MVT::i32);
13819 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
13820 CstShift, CstShift, CstShift, CstShift};
13821 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13822 makeArrayRef(&CstShiftArray[0], NumElts));
13823 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
13826 if (Subtarget.hasSSE41()) {
13827 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
13828 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13829 SDValue VecCstLowBitcast =
13830 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
13831 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
13832 // Low will be bitcasted right away, so do not bother bitcasting back to its
13834 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
13835 VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));
13836 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13837 // (uint4) 0x53000000, 0xaa);
13838 SDValue VecCstHighBitcast =
13839 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
13840 SDValue VecShiftBitcast =
13841 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
13842 // High will be bitcasted right away, so do not bother bitcasting back to
13843 // its original type.
13844 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
13845 VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32));
13847 SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);
13848 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
13849 CstMask, CstMask, CstMask);
13850 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13851 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
13852 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
13854 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13855 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
13858 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
13859 SDValue CstFAdd = DAG.getConstantFP(
13860 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);
13861 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
13862 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
13863 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
13864 makeArrayRef(&CstFAddArray[0], NumElts));
13866 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13867 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
13869 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
13870 // return (float4) lo + fhi;
13871 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
13872 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
13875 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13876 SelectionDAG &DAG) const {
13877 SDValue N0 = Op.getOperand(0);
13878 MVT SVT = N0.getSimpleValueType();
13881 switch (SVT.SimpleTy) {
13883 llvm_unreachable("Custom UINT_TO_FP is not supported!");
13888 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13889 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13890 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13894 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
13896 llvm_unreachable(nullptr);
13899 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13900 SelectionDAG &DAG) const {
13901 SDValue N0 = Op.getOperand(0);
13904 if (Op.getValueType().isVector())
13905 return lowerUINT_TO_FP_vec(Op, DAG);
13907 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13908 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13909 // the optimization here.
13910 if (DAG.SignBitIsZero(N0))
13911 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13913 MVT SrcVT = N0.getSimpleValueType();
13914 MVT DstVT = Op.getSimpleValueType();
13915 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13916 return LowerUINT_TO_FP_i64(Op, DAG);
13917 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13918 return LowerUINT_TO_FP_i32(Op, DAG);
13919 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13922 // Make a 64-bit buffer, and use it to build an FILD.
13923 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13924 if (SrcVT == MVT::i32) {
13925 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13926 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13927 getPointerTy(), StackSlot, WordOff);
13928 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13929 StackSlot, MachinePointerInfo(),
13931 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13932 OffsetSlot, MachinePointerInfo(),
13934 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13938 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13939 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13940 StackSlot, MachinePointerInfo(),
13942 // For i64 source, we need to add the appropriate power of 2 if the input
13943 // was negative. This is the same as the optimization in
13944 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13945 // we must be careful to do the computation in x87 extended precision, not
13946 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13947 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13948 MachineMemOperand *MMO =
13949 DAG.getMachineFunction()
13950 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13951 MachineMemOperand::MOLoad, 8, 8);
13953 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13954 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13955 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13958 APInt FF(32, 0x5F800000ULL);
13960 // Check whether the sign bit is set.
13961 SDValue SignSet = DAG.getSetCC(dl,
13962 getSetCCResultType(*DAG.getContext(), MVT::i64),
13963 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
13966 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
13967 SDValue FudgePtr = DAG.getConstantPool(
13968 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
13971 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
13972 SDValue Zero = DAG.getIntPtrConstant(0);
13973 SDValue Four = DAG.getIntPtrConstant(4);
13974 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
13976 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
13978 // Load the value out, extending it from f32 to f80.
13979 // FIXME: Avoid the extend by constructing the right constant pool?
13980 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
13981 FudgePtr, MachinePointerInfo::getConstantPool(),
13982 MVT::f32, false, false, false, 4);
13983 // Extend everything to 80 bits to force it to be done on x87.
13984 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
13985 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
13988 std::pair<SDValue,SDValue>
13989 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
13990 bool IsSigned, bool IsReplace) const {
13993 EVT DstTy = Op.getValueType();
13995 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
13996 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
14000 assert(DstTy.getSimpleVT() <= MVT::i64 &&
14001 DstTy.getSimpleVT() >= MVT::i16 &&
14002 "Unknown FP_TO_INT to lower!");
14004 // These are really Legal.
14005 if (DstTy == MVT::i32 &&
14006 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
14007 return std::make_pair(SDValue(), SDValue());
14008 if (Subtarget->is64Bit() &&
14009 DstTy == MVT::i64 &&
14010 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
14011 return std::make_pair(SDValue(), SDValue());
14013 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
14014 // stack slot, or into the FTOL runtime function.
14015 MachineFunction &MF = DAG.getMachineFunction();
14016 unsigned MemSize = DstTy.getSizeInBits()/8;
14017 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14018 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14021 if (!IsSigned && isIntegerTypeFTOL(DstTy))
14022 Opc = X86ISD::WIN_FTOL;
14024 switch (DstTy.getSimpleVT().SimpleTy) {
14025 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
14026 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
14027 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
14028 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
14031 SDValue Chain = DAG.getEntryNode();
14032 SDValue Value = Op.getOperand(0);
14033 EVT TheVT = Op.getOperand(0).getValueType();
14034 // FIXME This causes a redundant load/store if the SSE-class value is already
14035 // in memory, such as if it is on the callstack.
14036 if (isScalarFPTypeInSSEReg(TheVT)) {
14037 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
14038 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
14039 MachinePointerInfo::getFixedStack(SSFI),
14041 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
14043 Chain, StackSlot, DAG.getValueType(TheVT)
14046 MachineMemOperand *MMO =
14047 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14048 MachineMemOperand::MOLoad, MemSize, MemSize);
14049 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
14050 Chain = Value.getValue(1);
14051 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14052 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14055 MachineMemOperand *MMO =
14056 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14057 MachineMemOperand::MOStore, MemSize, MemSize);
14059 if (Opc != X86ISD::WIN_FTOL) {
14060 // Build the FP_TO_INT*_IN_MEM
14061 SDValue Ops[] = { Chain, Value, StackSlot };
14062 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
14064 return std::make_pair(FIST, StackSlot);
14066 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
14067 DAG.getVTList(MVT::Other, MVT::Glue),
14069 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
14070 MVT::i32, ftol.getValue(1));
14071 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
14072 MVT::i32, eax.getValue(2));
14073 SDValue Ops[] = { eax, edx };
14074 SDValue pair = IsReplace
14075 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
14076 : DAG.getMergeValues(Ops, DL);
14077 return std::make_pair(pair, SDValue());
14081 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
14082 const X86Subtarget *Subtarget) {
14083 MVT VT = Op->getSimpleValueType(0);
14084 SDValue In = Op->getOperand(0);
14085 MVT InVT = In.getSimpleValueType();
14088 // Optimize vectors in AVX mode:
14091 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14092 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14093 // Concat upper and lower parts.
14096 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14097 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14098 // Concat upper and lower parts.
14101 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
14102 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
14103 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
14106 if (Subtarget->hasInt256())
14107 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
14109 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
14110 SDValue Undef = DAG.getUNDEF(InVT);
14111 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
14112 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14113 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14115 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
14116 VT.getVectorNumElements()/2);
14118 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14119 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14121 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14124 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
14125 SelectionDAG &DAG) {
14126 MVT VT = Op->getSimpleValueType(0);
14127 SDValue In = Op->getOperand(0);
14128 MVT InVT = In.getSimpleValueType();
14130 unsigned int NumElts = VT.getVectorNumElements();
14131 if (NumElts != 8 && NumElts != 16)
14134 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14135 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
14137 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
14138 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14139 // Now we have only mask extension
14140 assert(InVT.getVectorElementType() == MVT::i1);
14141 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
14142 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14143 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14144 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14145 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14146 MachinePointerInfo::getConstantPool(),
14147 false, false, false, Alignment);
14149 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
14150 if (VT.is512BitVector())
14152 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
14155 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14156 SelectionDAG &DAG) {
14157 if (Subtarget->hasFp256()) {
14158 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14166 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14167 SelectionDAG &DAG) {
14169 MVT VT = Op.getSimpleValueType();
14170 SDValue In = Op.getOperand(0);
14171 MVT SVT = In.getSimpleValueType();
14173 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
14174 return LowerZERO_EXTEND_AVX512(Op, DAG);
14176 if (Subtarget->hasFp256()) {
14177 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14182 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
14183 VT.getVectorNumElements() != SVT.getVectorNumElements());
14187 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
14189 MVT VT = Op.getSimpleValueType();
14190 SDValue In = Op.getOperand(0);
14191 MVT InVT = In.getSimpleValueType();
14193 if (VT == MVT::i1) {
14194 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
14195 "Invalid scalar TRUNCATE operation");
14196 if (InVT.getSizeInBits() >= 32)
14198 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
14199 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
14201 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
14202 "Invalid TRUNCATE operation");
14204 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
14205 if (VT.getVectorElementType().getSizeInBits() >=8)
14206 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
14208 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14209 unsigned NumElts = InVT.getVectorNumElements();
14210 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
14211 if (InVT.getSizeInBits() < 512) {
14212 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
14213 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
14217 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
14218 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14219 SDValue CP = DAG.getConstantPool(C, getPointerTy());
14220 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14221 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14222 MachinePointerInfo::getConstantPool(),
14223 false, false, false, Alignment);
14224 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
14225 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
14226 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
14229 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
14230 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
14231 if (Subtarget->hasInt256()) {
14232 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
14233 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
14234 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
14236 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
14237 DAG.getIntPtrConstant(0));
14240 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14241 DAG.getIntPtrConstant(0));
14242 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14243 DAG.getIntPtrConstant(2));
14244 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14245 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14246 static const int ShufMask[] = {0, 2, 4, 6};
14247 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
14250 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
14251 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
14252 if (Subtarget->hasInt256()) {
14253 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
14255 SmallVector<SDValue,32> pshufbMask;
14256 for (unsigned i = 0; i < 2; ++i) {
14257 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
14258 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
14259 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
14260 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
14261 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
14262 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
14263 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
14264 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
14265 for (unsigned j = 0; j < 8; ++j)
14266 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
14268 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
14269 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
14270 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
14272 static const int ShufMask[] = {0, 2, -1, -1};
14273 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
14275 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14276 DAG.getIntPtrConstant(0));
14277 return DAG.getNode(ISD::BITCAST, DL, VT, In);
14280 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14281 DAG.getIntPtrConstant(0));
14283 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14284 DAG.getIntPtrConstant(4));
14286 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
14287 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
14289 // The PSHUFB mask:
14290 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
14291 -1, -1, -1, -1, -1, -1, -1, -1};
14293 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
14294 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
14295 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
14297 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14298 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14300 // The MOVLHPS Mask:
14301 static const int ShufMask2[] = {0, 1, 4, 5};
14302 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
14303 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
14306 // Handle truncation of V256 to V128 using shuffles.
14307 if (!VT.is128BitVector() || !InVT.is256BitVector())
14310 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
14312 unsigned NumElems = VT.getVectorNumElements();
14313 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
14315 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
14316 // Prepare truncation shuffle mask
14317 for (unsigned i = 0; i != NumElems; ++i)
14318 MaskVec[i] = i * 2;
14319 SDValue V = DAG.getVectorShuffle(NVT, DL,
14320 DAG.getNode(ISD::BITCAST, DL, NVT, In),
14321 DAG.getUNDEF(NVT), &MaskVec[0]);
14322 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
14323 DAG.getIntPtrConstant(0));
14326 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
14327 SelectionDAG &DAG) const {
14328 assert(!Op.getSimpleValueType().isVector());
14330 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14331 /*IsSigned=*/ true, /*IsReplace=*/ false);
14332 SDValue FIST = Vals.first, StackSlot = Vals.second;
14333 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
14334 if (!FIST.getNode()) return Op;
14336 if (StackSlot.getNode())
14337 // Load the result.
14338 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14339 FIST, StackSlot, MachinePointerInfo(),
14340 false, false, false, 0);
14342 // The node is the result.
14346 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
14347 SelectionDAG &DAG) const {
14348 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14349 /*IsSigned=*/ false, /*IsReplace=*/ false);
14350 SDValue FIST = Vals.first, StackSlot = Vals.second;
14351 assert(FIST.getNode() && "Unexpected failure");
14353 if (StackSlot.getNode())
14354 // Load the result.
14355 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14356 FIST, StackSlot, MachinePointerInfo(),
14357 false, false, false, 0);
14359 // The node is the result.
14363 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
14365 MVT VT = Op.getSimpleValueType();
14366 SDValue In = Op.getOperand(0);
14367 MVT SVT = In.getSimpleValueType();
14369 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
14371 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
14372 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
14373 In, DAG.getUNDEF(SVT)));
14376 /// The only differences between FABS and FNEG are the mask and the logic op.
14377 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
14378 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
14379 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
14380 "Wrong opcode for lowering FABS or FNEG.");
14382 bool IsFABS = (Op.getOpcode() == ISD::FABS);
14384 // If this is a FABS and it has an FNEG user, bail out to fold the combination
14385 // into an FNABS. We'll lower the FABS after that if it is still in use.
14387 for (SDNode *User : Op->uses())
14388 if (User->getOpcode() == ISD::FNEG)
14391 SDValue Op0 = Op.getOperand(0);
14392 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
14395 MVT VT = Op.getSimpleValueType();
14396 // Assume scalar op for initialization; update for vector if needed.
14397 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
14398 // generate a 16-byte vector constant and logic op even for the scalar case.
14399 // Using a 16-byte mask allows folding the load of the mask with
14400 // the logic op, so it can save (~4 bytes) on code size.
14402 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
14403 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
14404 // decide if we should generate a 16-byte constant mask when we only need 4 or
14405 // 8 bytes for the scalar case.
14406 if (VT.isVector()) {
14407 EltVT = VT.getVectorElementType();
14408 NumElts = VT.getVectorNumElements();
14411 unsigned EltBits = EltVT.getSizeInBits();
14412 LLVMContext *Context = DAG.getContext();
14413 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
14415 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
14416 Constant *C = ConstantInt::get(*Context, MaskElt);
14417 C = ConstantVector::getSplat(NumElts, C);
14418 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14419 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
14420 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
14421 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14422 MachinePointerInfo::getConstantPool(),
14423 false, false, false, Alignment);
14425 if (VT.isVector()) {
14426 // For a vector, cast operands to a vector type, perform the logic op,
14427 // and cast the result back to the original value type.
14428 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
14429 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
14430 SDValue Operand = IsFNABS ?
14431 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
14432 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
14433 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
14434 return DAG.getNode(ISD::BITCAST, dl, VT,
14435 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
14438 // If not vector, then scalar.
14439 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
14440 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
14441 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
14444 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
14445 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14446 LLVMContext *Context = DAG.getContext();
14447 SDValue Op0 = Op.getOperand(0);
14448 SDValue Op1 = Op.getOperand(1);
14450 MVT VT = Op.getSimpleValueType();
14451 MVT SrcVT = Op1.getSimpleValueType();
14453 // If second operand is smaller, extend it first.
14454 if (SrcVT.bitsLT(VT)) {
14455 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
14458 // And if it is bigger, shrink it first.
14459 if (SrcVT.bitsGT(VT)) {
14460 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
14464 // At this point the operands and the result should have the same
14465 // type, and that won't be f80 since that is not custom lowered.
14467 const fltSemantics &Sem =
14468 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
14469 const unsigned SizeInBits = VT.getSizeInBits();
14471 SmallVector<Constant *, 4> CV(
14472 VT == MVT::f64 ? 2 : 4,
14473 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
14475 // First, clear all bits but the sign bit from the second operand (sign).
14476 CV[0] = ConstantFP::get(*Context,
14477 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
14478 Constant *C = ConstantVector::get(CV);
14479 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14480 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
14481 MachinePointerInfo::getConstantPool(),
14482 false, false, false, 16);
14483 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
14485 // Next, clear the sign bit from the first operand (magnitude).
14486 CV[0] = ConstantFP::get(
14487 *Context, APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
14488 C = ConstantVector::get(CV);
14489 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14490 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14491 MachinePointerInfo::getConstantPool(),
14492 false, false, false, 16);
14493 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
14495 // OR the magnitude value with the sign bit.
14496 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
14499 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
14500 SDValue N0 = Op.getOperand(0);
14502 MVT VT = Op.getSimpleValueType();
14504 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
14505 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
14506 DAG.getConstant(1, VT));
14507 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
14510 // Check whether an OR'd tree is PTEST-able.
14511 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
14512 SelectionDAG &DAG) {
14513 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
14515 if (!Subtarget->hasSSE41())
14518 if (!Op->hasOneUse())
14521 SDNode *N = Op.getNode();
14524 SmallVector<SDValue, 8> Opnds;
14525 DenseMap<SDValue, unsigned> VecInMap;
14526 SmallVector<SDValue, 8> VecIns;
14527 EVT VT = MVT::Other;
14529 // Recognize a special case where a vector is casted into wide integer to
14531 Opnds.push_back(N->getOperand(0));
14532 Opnds.push_back(N->getOperand(1));
14534 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
14535 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
14536 // BFS traverse all OR'd operands.
14537 if (I->getOpcode() == ISD::OR) {
14538 Opnds.push_back(I->getOperand(0));
14539 Opnds.push_back(I->getOperand(1));
14540 // Re-evaluate the number of nodes to be traversed.
14541 e += 2; // 2 more nodes (LHS and RHS) are pushed.
14545 // Quit if a non-EXTRACT_VECTOR_ELT
14546 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14549 // Quit if without a constant index.
14550 SDValue Idx = I->getOperand(1);
14551 if (!isa<ConstantSDNode>(Idx))
14554 SDValue ExtractedFromVec = I->getOperand(0);
14555 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
14556 if (M == VecInMap.end()) {
14557 VT = ExtractedFromVec.getValueType();
14558 // Quit if not 128/256-bit vector.
14559 if (!VT.is128BitVector() && !VT.is256BitVector())
14561 // Quit if not the same type.
14562 if (VecInMap.begin() != VecInMap.end() &&
14563 VT != VecInMap.begin()->first.getValueType())
14565 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
14566 VecIns.push_back(ExtractedFromVec);
14568 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
14571 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14572 "Not extracted from 128-/256-bit vector.");
14574 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
14576 for (DenseMap<SDValue, unsigned>::const_iterator
14577 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
14578 // Quit if not all elements are used.
14579 if (I->second != FullMask)
14583 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
14585 // Cast all vectors into TestVT for PTEST.
14586 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
14587 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
14589 // If more than one full vectors are evaluated, OR them first before PTEST.
14590 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
14591 // Each iteration will OR 2 nodes and append the result until there is only
14592 // 1 node left, i.e. the final OR'd value of all vectors.
14593 SDValue LHS = VecIns[Slot];
14594 SDValue RHS = VecIns[Slot + 1];
14595 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
14598 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
14599 VecIns.back(), VecIns.back());
14602 /// \brief return true if \c Op has a use that doesn't just read flags.
14603 static bool hasNonFlagsUse(SDValue Op) {
14604 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
14606 SDNode *User = *UI;
14607 unsigned UOpNo = UI.getOperandNo();
14608 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
14609 // Look pass truncate.
14610 UOpNo = User->use_begin().getOperandNo();
14611 User = *User->use_begin();
14614 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
14615 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
14621 /// Emit nodes that will be selected as "test Op0,Op0", or something
14623 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
14624 SelectionDAG &DAG) const {
14625 if (Op.getValueType() == MVT::i1)
14626 // KORTEST instruction should be selected
14627 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14628 DAG.getConstant(0, Op.getValueType()));
14630 // CF and OF aren't always set the way we want. Determine which
14631 // of these we need.
14632 bool NeedCF = false;
14633 bool NeedOF = false;
14636 case X86::COND_A: case X86::COND_AE:
14637 case X86::COND_B: case X86::COND_BE:
14640 case X86::COND_G: case X86::COND_GE:
14641 case X86::COND_L: case X86::COND_LE:
14642 case X86::COND_O: case X86::COND_NO: {
14643 // Check if we really need to set the
14644 // Overflow flag. If NoSignedWrap is present
14645 // that is not actually needed.
14646 switch (Op->getOpcode()) {
14651 const BinaryWithFlagsSDNode *BinNode =
14652 cast<BinaryWithFlagsSDNode>(Op.getNode());
14653 if (BinNode->hasNoSignedWrap())
14663 // See if we can use the EFLAGS value from the operand instead of
14664 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
14665 // we prove that the arithmetic won't overflow, we can't use OF or CF.
14666 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
14667 // Emit a CMP with 0, which is the TEST pattern.
14668 //if (Op.getValueType() == MVT::i1)
14669 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
14670 // DAG.getConstant(0, MVT::i1));
14671 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14672 DAG.getConstant(0, Op.getValueType()));
14674 unsigned Opcode = 0;
14675 unsigned NumOperands = 0;
14677 // Truncate operations may prevent the merge of the SETCC instruction
14678 // and the arithmetic instruction before it. Attempt to truncate the operands
14679 // of the arithmetic instruction and use a reduced bit-width instruction.
14680 bool NeedTruncation = false;
14681 SDValue ArithOp = Op;
14682 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
14683 SDValue Arith = Op->getOperand(0);
14684 // Both the trunc and the arithmetic op need to have one user each.
14685 if (Arith->hasOneUse())
14686 switch (Arith.getOpcode()) {
14693 NeedTruncation = true;
14699 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14700 // which may be the result of a CAST. We use the variable 'Op', which is the
14701 // non-casted variable when we check for possible users.
14702 switch (ArithOp.getOpcode()) {
14704 // Due to an isel shortcoming, be conservative if this add is likely to be
14705 // selected as part of a load-modify-store instruction. When the root node
14706 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14707 // uses of other nodes in the match, such as the ADD in this case. This
14708 // leads to the ADD being left around and reselected, with the result being
14709 // two adds in the output. Alas, even if none our users are stores, that
14710 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14711 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14712 // climbing the DAG back to the root, and it doesn't seem to be worth the
14714 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14715 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14716 if (UI->getOpcode() != ISD::CopyToReg &&
14717 UI->getOpcode() != ISD::SETCC &&
14718 UI->getOpcode() != ISD::STORE)
14721 if (ConstantSDNode *C =
14722 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14723 // An add of one will be selected as an INC.
14724 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14725 Opcode = X86ISD::INC;
14730 // An add of negative one (subtract of one) will be selected as a DEC.
14731 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14732 Opcode = X86ISD::DEC;
14738 // Otherwise use a regular EFLAGS-setting add.
14739 Opcode = X86ISD::ADD;
14744 // If we have a constant logical shift that's only used in a comparison
14745 // against zero turn it into an equivalent AND. This allows turning it into
14746 // a TEST instruction later.
14747 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14748 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14749 EVT VT = Op.getValueType();
14750 unsigned BitWidth = VT.getSizeInBits();
14751 unsigned ShAmt = Op->getConstantOperandVal(1);
14752 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14754 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14755 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14756 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14757 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14759 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14760 DAG.getConstant(Mask, VT));
14761 DAG.ReplaceAllUsesWith(Op, New);
14767 // If the primary and result isn't used, don't bother using X86ISD::AND,
14768 // because a TEST instruction will be better.
14769 if (!hasNonFlagsUse(Op))
14775 // Due to the ISEL shortcoming noted above, be conservative if this op is
14776 // likely to be selected as part of a load-modify-store instruction.
14777 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14778 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14779 if (UI->getOpcode() == ISD::STORE)
14782 // Otherwise use a regular EFLAGS-setting instruction.
14783 switch (ArithOp.getOpcode()) {
14784 default: llvm_unreachable("unexpected operator!");
14785 case ISD::SUB: Opcode = X86ISD::SUB; break;
14786 case ISD::XOR: Opcode = X86ISD::XOR; break;
14787 case ISD::AND: Opcode = X86ISD::AND; break;
14789 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14790 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14791 if (EFLAGS.getNode())
14794 Opcode = X86ISD::OR;
14808 return SDValue(Op.getNode(), 1);
14814 // If we found that truncation is beneficial, perform the truncation and
14816 if (NeedTruncation) {
14817 EVT VT = Op.getValueType();
14818 SDValue WideVal = Op->getOperand(0);
14819 EVT WideVT = WideVal.getValueType();
14820 unsigned ConvertedOp = 0;
14821 // Use a target machine opcode to prevent further DAGCombine
14822 // optimizations that may separate the arithmetic operations
14823 // from the setcc node.
14824 switch (WideVal.getOpcode()) {
14826 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14827 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14828 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14829 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14830 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14834 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14835 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14836 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14837 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14838 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14844 // Emit a CMP with 0, which is the TEST pattern.
14845 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14846 DAG.getConstant(0, Op.getValueType()));
14848 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14849 SmallVector<SDValue, 4> Ops;
14850 for (unsigned i = 0; i != NumOperands; ++i)
14851 Ops.push_back(Op.getOperand(i));
14853 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14854 DAG.ReplaceAllUsesWith(Op, New);
14855 return SDValue(New.getNode(), 1);
14858 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14860 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14861 SDLoc dl, SelectionDAG &DAG) const {
14862 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14863 if (C->getAPIntValue() == 0)
14864 return EmitTest(Op0, X86CC, dl, DAG);
14866 if (Op0.getValueType() == MVT::i1)
14867 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14870 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14871 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14872 // Do the comparison at i32 if it's smaller, besides the Atom case.
14873 // This avoids subregister aliasing issues. Keep the smaller reference
14874 // if we're optimizing for size, however, as that'll allow better folding
14875 // of memory operations.
14876 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14877 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14878 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14879 !Subtarget->isAtom()) {
14880 unsigned ExtendOp =
14881 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14882 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14883 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14885 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14886 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14887 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14889 return SDValue(Sub.getNode(), 1);
14891 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14894 /// Convert a comparison if required by the subtarget.
14895 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14896 SelectionDAG &DAG) const {
14897 // If the subtarget does not support the FUCOMI instruction, floating-point
14898 // comparisons have to be converted.
14899 if (Subtarget->hasCMov() ||
14900 Cmp.getOpcode() != X86ISD::CMP ||
14901 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14902 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14905 // The instruction selector will select an FUCOM instruction instead of
14906 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14907 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14908 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14910 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14911 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14912 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14913 DAG.getConstant(8, MVT::i8));
14914 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14915 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14918 /// The minimum architected relative accuracy is 2^-12. We need one
14919 /// Newton-Raphson step to have a good float result (24 bits of precision).
14920 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
14921 DAGCombinerInfo &DCI,
14922 unsigned &RefinementSteps,
14923 bool &UseOneConstNR) const {
14924 // FIXME: We should use instruction latency models to calculate the cost of
14925 // each potential sequence, but this is very hard to do reliably because
14926 // at least Intel's Core* chips have variable timing based on the number of
14927 // significant digits in the divisor and/or sqrt operand.
14928 if (!Subtarget->useSqrtEst())
14931 EVT VT = Op.getValueType();
14933 // SSE1 has rsqrtss and rsqrtps.
14934 // TODO: Add support for AVX512 (v16f32).
14935 // It is likely not profitable to do this for f64 because a double-precision
14936 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
14937 // instructions: convert to single, rsqrtss, convert back to double, refine
14938 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
14939 // along with FMA, this could be a throughput win.
14940 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14941 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14942 RefinementSteps = 1;
14943 UseOneConstNR = false;
14944 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
14949 /// The minimum architected relative accuracy is 2^-12. We need one
14950 /// Newton-Raphson step to have a good float result (24 bits of precision).
14951 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
14952 DAGCombinerInfo &DCI,
14953 unsigned &RefinementSteps) const {
14954 // FIXME: We should use instruction latency models to calculate the cost of
14955 // each potential sequence, but this is very hard to do reliably because
14956 // at least Intel's Core* chips have variable timing based on the number of
14957 // significant digits in the divisor.
14958 if (!Subtarget->useReciprocalEst())
14961 EVT VT = Op.getValueType();
14963 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
14964 // TODO: Add support for AVX512 (v16f32).
14965 // It is likely not profitable to do this for f64 because a double-precision
14966 // reciprocal estimate with refinement on x86 prior to FMA requires
14967 // 15 instructions: convert to single, rcpss, convert back to double, refine
14968 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
14969 // along with FMA, this could be a throughput win.
14970 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14971 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14972 RefinementSteps = ReciprocalEstimateRefinementSteps;
14973 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
14978 static bool isAllOnes(SDValue V) {
14979 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
14980 return C && C->isAllOnesValue();
14983 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14984 /// if it's possible.
14985 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14986 SDLoc dl, SelectionDAG &DAG) const {
14987 SDValue Op0 = And.getOperand(0);
14988 SDValue Op1 = And.getOperand(1);
14989 if (Op0.getOpcode() == ISD::TRUNCATE)
14990 Op0 = Op0.getOperand(0);
14991 if (Op1.getOpcode() == ISD::TRUNCATE)
14992 Op1 = Op1.getOperand(0);
14995 if (Op1.getOpcode() == ISD::SHL)
14996 std::swap(Op0, Op1);
14997 if (Op0.getOpcode() == ISD::SHL) {
14998 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
14999 if (And00C->getZExtValue() == 1) {
15000 // If we looked past a truncate, check that it's only truncating away
15002 unsigned BitWidth = Op0.getValueSizeInBits();
15003 unsigned AndBitWidth = And.getValueSizeInBits();
15004 if (BitWidth > AndBitWidth) {
15006 DAG.computeKnownBits(Op0, Zeros, Ones);
15007 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
15011 RHS = Op0.getOperand(1);
15013 } else if (Op1.getOpcode() == ISD::Constant) {
15014 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
15015 uint64_t AndRHSVal = AndRHS->getZExtValue();
15016 SDValue AndLHS = Op0;
15018 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
15019 LHS = AndLHS.getOperand(0);
15020 RHS = AndLHS.getOperand(1);
15023 // Use BT if the immediate can't be encoded in a TEST instruction.
15024 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
15026 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
15030 if (LHS.getNode()) {
15031 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
15032 // instruction. Since the shift amount is in-range-or-undefined, we know
15033 // that doing a bittest on the i32 value is ok. We extend to i32 because
15034 // the encoding for the i16 version is larger than the i32 version.
15035 // Also promote i16 to i32 for performance / code size reason.
15036 if (LHS.getValueType() == MVT::i8 ||
15037 LHS.getValueType() == MVT::i16)
15038 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
15040 // If the operand types disagree, extend the shift amount to match. Since
15041 // BT ignores high bits (like shifts) we can use anyextend.
15042 if (LHS.getValueType() != RHS.getValueType())
15043 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
15045 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
15046 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
15047 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15048 DAG.getConstant(Cond, MVT::i8), BT);
15054 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
15056 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
15061 // SSE Condition code mapping:
15070 switch (SetCCOpcode) {
15071 default: llvm_unreachable("Unexpected SETCC condition");
15073 case ISD::SETEQ: SSECC = 0; break;
15075 case ISD::SETGT: Swap = true; // Fallthrough
15077 case ISD::SETOLT: SSECC = 1; break;
15079 case ISD::SETGE: Swap = true; // Fallthrough
15081 case ISD::SETOLE: SSECC = 2; break;
15082 case ISD::SETUO: SSECC = 3; break;
15084 case ISD::SETNE: SSECC = 4; break;
15085 case ISD::SETULE: Swap = true; // Fallthrough
15086 case ISD::SETUGE: SSECC = 5; break;
15087 case ISD::SETULT: Swap = true; // Fallthrough
15088 case ISD::SETUGT: SSECC = 6; break;
15089 case ISD::SETO: SSECC = 7; break;
15091 case ISD::SETONE: SSECC = 8; break;
15094 std::swap(Op0, Op1);
15099 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
15100 // ones, and then concatenate the result back.
15101 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
15102 MVT VT = Op.getSimpleValueType();
15104 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
15105 "Unsupported value type for operation");
15107 unsigned NumElems = VT.getVectorNumElements();
15109 SDValue CC = Op.getOperand(2);
15111 // Extract the LHS vectors
15112 SDValue LHS = Op.getOperand(0);
15113 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15114 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15116 // Extract the RHS vectors
15117 SDValue RHS = Op.getOperand(1);
15118 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15119 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15121 // Issue the operation on the smaller types and concatenate the result back
15122 MVT EltVT = VT.getVectorElementType();
15123 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15124 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15125 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
15126 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
15129 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
15130 const X86Subtarget *Subtarget) {
15131 SDValue Op0 = Op.getOperand(0);
15132 SDValue Op1 = Op.getOperand(1);
15133 SDValue CC = Op.getOperand(2);
15134 MVT VT = Op.getSimpleValueType();
15137 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
15138 Op.getValueType().getScalarType() == MVT::i1 &&
15139 "Cannot set masked compare for this operation");
15141 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15143 bool Unsigned = false;
15146 switch (SetCCOpcode) {
15147 default: llvm_unreachable("Unexpected SETCC condition");
15148 case ISD::SETNE: SSECC = 4; break;
15149 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
15150 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
15151 case ISD::SETLT: Swap = true; //fall-through
15152 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
15153 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
15154 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
15155 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
15156 case ISD::SETULE: Unsigned = true; //fall-through
15157 case ISD::SETLE: SSECC = 2; break;
15161 std::swap(Op0, Op1);
15163 return DAG.getNode(Opc, dl, VT, Op0, Op1);
15164 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
15165 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15166 DAG.getConstant(SSECC, MVT::i8));
15169 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
15170 /// operand \p Op1. If non-trivial (for example because it's not constant)
15171 /// return an empty value.
15172 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
15174 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
15178 MVT VT = Op1.getSimpleValueType();
15179 MVT EVT = VT.getVectorElementType();
15180 unsigned n = VT.getVectorNumElements();
15181 SmallVector<SDValue, 8> ULTOp1;
15183 for (unsigned i = 0; i < n; ++i) {
15184 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
15185 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
15188 // Avoid underflow.
15189 APInt Val = Elt->getAPIntValue();
15193 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
15196 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
15199 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
15200 SelectionDAG &DAG) {
15201 SDValue Op0 = Op.getOperand(0);
15202 SDValue Op1 = Op.getOperand(1);
15203 SDValue CC = Op.getOperand(2);
15204 MVT VT = Op.getSimpleValueType();
15205 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15206 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
15211 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
15212 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
15215 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
15216 unsigned Opc = X86ISD::CMPP;
15217 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
15218 assert(VT.getVectorNumElements() <= 16);
15219 Opc = X86ISD::CMPM;
15221 // In the two special cases we can't handle, emit two comparisons.
15224 unsigned CombineOpc;
15225 if (SetCCOpcode == ISD::SETUEQ) {
15226 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
15228 assert(SetCCOpcode == ISD::SETONE);
15229 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
15232 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15233 DAG.getConstant(CC0, MVT::i8));
15234 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15235 DAG.getConstant(CC1, MVT::i8));
15236 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
15238 // Handle all other FP comparisons here.
15239 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15240 DAG.getConstant(SSECC, MVT::i8));
15243 // Break 256-bit integer vector compare into smaller ones.
15244 if (VT.is256BitVector() && !Subtarget->hasInt256())
15245 return Lower256IntVSETCC(Op, DAG);
15247 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
15248 EVT OpVT = Op1.getValueType();
15249 if (Subtarget->hasAVX512()) {
15250 if (Op1.getValueType().is512BitVector() ||
15251 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
15252 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
15253 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
15255 // In AVX-512 architecture setcc returns mask with i1 elements,
15256 // But there is no compare instruction for i8 and i16 elements in KNL.
15257 // We are not talking about 512-bit operands in this case, these
15258 // types are illegal.
15260 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
15261 OpVT.getVectorElementType().getSizeInBits() >= 8))
15262 return DAG.getNode(ISD::TRUNCATE, dl, VT,
15263 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
15266 // We are handling one of the integer comparisons here. Since SSE only has
15267 // GT and EQ comparisons for integer, swapping operands and multiple
15268 // operations may be required for some comparisons.
15270 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
15271 bool Subus = false;
15273 switch (SetCCOpcode) {
15274 default: llvm_unreachable("Unexpected SETCC condition");
15275 case ISD::SETNE: Invert = true;
15276 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
15277 case ISD::SETLT: Swap = true;
15278 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
15279 case ISD::SETGE: Swap = true;
15280 case ISD::SETLE: Opc = X86ISD::PCMPGT;
15281 Invert = true; break;
15282 case ISD::SETULT: Swap = true;
15283 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
15284 FlipSigns = true; break;
15285 case ISD::SETUGE: Swap = true;
15286 case ISD::SETULE: Opc = X86ISD::PCMPGT;
15287 FlipSigns = true; Invert = true; break;
15290 // Special case: Use min/max operations for SETULE/SETUGE
15291 MVT VET = VT.getVectorElementType();
15293 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
15294 || (Subtarget->hasSSE2() && (VET == MVT::i8));
15297 switch (SetCCOpcode) {
15299 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
15300 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
15303 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
15306 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
15307 if (!MinMax && hasSubus) {
15308 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
15310 // t = psubus Op0, Op1
15311 // pcmpeq t, <0..0>
15312 switch (SetCCOpcode) {
15314 case ISD::SETULT: {
15315 // If the comparison is against a constant we can turn this into a
15316 // setule. With psubus, setule does not require a swap. This is
15317 // beneficial because the constant in the register is no longer
15318 // destructed as the destination so it can be hoisted out of a loop.
15319 // Only do this pre-AVX since vpcmp* is no longer destructive.
15320 if (Subtarget->hasAVX())
15322 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
15323 if (ULEOp1.getNode()) {
15325 Subus = true; Invert = false; Swap = false;
15329 // Psubus is better than flip-sign because it requires no inversion.
15330 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
15331 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
15335 Opc = X86ISD::SUBUS;
15341 std::swap(Op0, Op1);
15343 // Check that the operation in question is available (most are plain SSE2,
15344 // but PCMPGTQ and PCMPEQQ have different requirements).
15345 if (VT == MVT::v2i64) {
15346 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
15347 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
15349 // First cast everything to the right type.
15350 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15351 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15353 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15354 // bits of the inputs before performing those operations. The lower
15355 // compare is always unsigned.
15358 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
15360 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
15361 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
15362 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
15363 Sign, Zero, Sign, Zero);
15365 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
15366 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
15368 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
15369 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
15370 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
15372 // Create masks for only the low parts/high parts of the 64 bit integers.
15373 static const int MaskHi[] = { 1, 1, 3, 3 };
15374 static const int MaskLo[] = { 0, 0, 2, 2 };
15375 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
15376 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
15377 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
15379 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
15380 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
15383 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15385 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15388 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
15389 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
15390 // pcmpeqd + pshufd + pand.
15391 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
15393 // First cast everything to the right type.
15394 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15395 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15398 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
15400 // Make sure the lower and upper halves are both all-ones.
15401 static const int Mask[] = { 1, 0, 3, 2 };
15402 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
15403 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
15406 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15408 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15412 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15413 // bits of the inputs before performing those operations.
15415 EVT EltVT = VT.getVectorElementType();
15416 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
15417 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
15418 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
15421 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
15423 // If the logical-not of the result is required, perform that now.
15425 Result = DAG.getNOT(dl, Result, VT);
15428 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
15431 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
15432 getZeroVector(VT, Subtarget, DAG, dl));
15437 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
15439 MVT VT = Op.getSimpleValueType();
15441 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
15443 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
15444 && "SetCC type must be 8-bit or 1-bit integer");
15445 SDValue Op0 = Op.getOperand(0);
15446 SDValue Op1 = Op.getOperand(1);
15448 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
15450 // Optimize to BT if possible.
15451 // Lower (X & (1 << N)) == 0 to BT(X, N).
15452 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
15453 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
15454 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
15455 Op1.getOpcode() == ISD::Constant &&
15456 cast<ConstantSDNode>(Op1)->isNullValue() &&
15457 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15458 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
15459 if (NewSetCC.getNode()) {
15461 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
15466 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
15468 if (Op1.getOpcode() == ISD::Constant &&
15469 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
15470 cast<ConstantSDNode>(Op1)->isNullValue()) &&
15471 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15473 // If the input is a setcc, then reuse the input setcc or use a new one with
15474 // the inverted condition.
15475 if (Op0.getOpcode() == X86ISD::SETCC) {
15476 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
15477 bool Invert = (CC == ISD::SETNE) ^
15478 cast<ConstantSDNode>(Op1)->isNullValue();
15482 CCode = X86::GetOppositeBranchCondition(CCode);
15483 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15484 DAG.getConstant(CCode, MVT::i8),
15485 Op0.getOperand(1));
15487 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15491 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
15492 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
15493 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15495 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
15496 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
15499 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
15500 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
15501 if (X86CC == X86::COND_INVALID)
15504 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
15505 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
15506 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15507 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
15509 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15513 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
15514 static bool isX86LogicalCmp(SDValue Op) {
15515 unsigned Opc = Op.getNode()->getOpcode();
15516 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
15517 Opc == X86ISD::SAHF)
15519 if (Op.getResNo() == 1 &&
15520 (Opc == X86ISD::ADD ||
15521 Opc == X86ISD::SUB ||
15522 Opc == X86ISD::ADC ||
15523 Opc == X86ISD::SBB ||
15524 Opc == X86ISD::SMUL ||
15525 Opc == X86ISD::UMUL ||
15526 Opc == X86ISD::INC ||
15527 Opc == X86ISD::DEC ||
15528 Opc == X86ISD::OR ||
15529 Opc == X86ISD::XOR ||
15530 Opc == X86ISD::AND))
15533 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
15539 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
15540 if (V.getOpcode() != ISD::TRUNCATE)
15543 SDValue VOp0 = V.getOperand(0);
15544 unsigned InBits = VOp0.getValueSizeInBits();
15545 unsigned Bits = V.getValueSizeInBits();
15546 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
15549 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
15550 bool addTest = true;
15551 SDValue Cond = Op.getOperand(0);
15552 SDValue Op1 = Op.getOperand(1);
15553 SDValue Op2 = Op.getOperand(2);
15555 EVT VT = Op1.getValueType();
15558 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
15559 // are available. Otherwise fp cmovs get lowered into a less efficient branch
15560 // sequence later on.
15561 if (Cond.getOpcode() == ISD::SETCC &&
15562 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
15563 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
15564 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
15565 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
15566 int SSECC = translateX86FSETCC(
15567 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
15570 if (Subtarget->hasAVX512()) {
15571 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
15572 DAG.getConstant(SSECC, MVT::i8));
15573 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
15575 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
15576 DAG.getConstant(SSECC, MVT::i8));
15577 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
15578 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
15579 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
15583 if (Cond.getOpcode() == ISD::SETCC) {
15584 SDValue NewCond = LowerSETCC(Cond, DAG);
15585 if (NewCond.getNode())
15589 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
15590 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
15591 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
15592 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
15593 if (Cond.getOpcode() == X86ISD::SETCC &&
15594 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
15595 isZero(Cond.getOperand(1).getOperand(1))) {
15596 SDValue Cmp = Cond.getOperand(1);
15598 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
15600 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
15601 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
15602 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
15604 SDValue CmpOp0 = Cmp.getOperand(0);
15605 // Apply further optimizations for special cases
15606 // (select (x != 0), -1, 0) -> neg & sbb
15607 // (select (x == 0), 0, -1) -> neg & sbb
15608 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
15609 if (YC->isNullValue() &&
15610 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
15611 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
15612 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
15613 DAG.getConstant(0, CmpOp0.getValueType()),
15615 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15616 DAG.getConstant(X86::COND_B, MVT::i8),
15617 SDValue(Neg.getNode(), 1));
15621 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
15622 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
15623 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15625 SDValue Res = // Res = 0 or -1.
15626 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15627 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
15629 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
15630 Res = DAG.getNOT(DL, Res, Res.getValueType());
15632 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
15633 if (!N2C || !N2C->isNullValue())
15634 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
15639 // Look past (and (setcc_carry (cmp ...)), 1).
15640 if (Cond.getOpcode() == ISD::AND &&
15641 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15642 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15643 if (C && C->getAPIntValue() == 1)
15644 Cond = Cond.getOperand(0);
15647 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15648 // setting operand in place of the X86ISD::SETCC.
15649 unsigned CondOpcode = Cond.getOpcode();
15650 if (CondOpcode == X86ISD::SETCC ||
15651 CondOpcode == X86ISD::SETCC_CARRY) {
15652 CC = Cond.getOperand(0);
15654 SDValue Cmp = Cond.getOperand(1);
15655 unsigned Opc = Cmp.getOpcode();
15656 MVT VT = Op.getSimpleValueType();
15658 bool IllegalFPCMov = false;
15659 if (VT.isFloatingPoint() && !VT.isVector() &&
15660 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15661 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15663 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15664 Opc == X86ISD::BT) { // FIXME
15668 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15669 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15670 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15671 Cond.getOperand(0).getValueType() != MVT::i8)) {
15672 SDValue LHS = Cond.getOperand(0);
15673 SDValue RHS = Cond.getOperand(1);
15674 unsigned X86Opcode;
15677 switch (CondOpcode) {
15678 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15679 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15680 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15681 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15682 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15683 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15684 default: llvm_unreachable("unexpected overflowing operator");
15686 if (CondOpcode == ISD::UMULO)
15687 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15690 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15692 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15694 if (CondOpcode == ISD::UMULO)
15695 Cond = X86Op.getValue(2);
15697 Cond = X86Op.getValue(1);
15699 CC = DAG.getConstant(X86Cond, MVT::i8);
15704 // Look pass the truncate if the high bits are known zero.
15705 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15706 Cond = Cond.getOperand(0);
15708 // We know the result of AND is compared against zero. Try to match
15710 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15711 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
15712 if (NewSetCC.getNode()) {
15713 CC = NewSetCC.getOperand(0);
15714 Cond = NewSetCC.getOperand(1);
15721 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15722 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15725 // a < b ? -1 : 0 -> RES = ~setcc_carry
15726 // a < b ? 0 : -1 -> RES = setcc_carry
15727 // a >= b ? -1 : 0 -> RES = setcc_carry
15728 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15729 if (Cond.getOpcode() == X86ISD::SUB) {
15730 Cond = ConvertCmpIfNecessary(Cond, DAG);
15731 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15733 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15734 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
15735 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15736 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
15737 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
15738 return DAG.getNOT(DL, Res, Res.getValueType());
15743 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15744 // widen the cmov and push the truncate through. This avoids introducing a new
15745 // branch during isel and doesn't add any extensions.
15746 if (Op.getValueType() == MVT::i8 &&
15747 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15748 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15749 if (T1.getValueType() == T2.getValueType() &&
15750 // Blacklist CopyFromReg to avoid partial register stalls.
15751 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15752 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15753 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15754 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15758 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15759 // condition is true.
15760 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15761 SDValue Ops[] = { Op2, Op1, CC, Cond };
15762 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15765 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
15766 SelectionDAG &DAG) {
15767 MVT VT = Op->getSimpleValueType(0);
15768 SDValue In = Op->getOperand(0);
15769 MVT InVT = In.getSimpleValueType();
15770 MVT VTElt = VT.getVectorElementType();
15771 MVT InVTElt = InVT.getVectorElementType();
15775 if ((InVTElt == MVT::i1) &&
15776 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15777 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15779 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15780 VTElt.getSizeInBits() <= 16)) ||
15782 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15783 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15785 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15786 VTElt.getSizeInBits() >= 32))))
15787 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15789 unsigned int NumElts = VT.getVectorNumElements();
15791 if (NumElts != 8 && NumElts != 16)
15794 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15795 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15796 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15797 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15800 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15801 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15803 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15804 Constant *C = ConstantInt::get(*DAG.getContext(),
15805 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15807 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15808 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15809 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15810 MachinePointerInfo::getConstantPool(),
15811 false, false, false, Alignment);
15812 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15813 if (VT.is512BitVector())
15815 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15818 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15819 SelectionDAG &DAG) {
15820 MVT VT = Op->getSimpleValueType(0);
15821 SDValue In = Op->getOperand(0);
15822 MVT InVT = In.getSimpleValueType();
15825 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15826 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15828 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15829 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15830 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15833 if (Subtarget->hasInt256())
15834 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15836 // Optimize vectors in AVX mode
15837 // Sign extend v8i16 to v8i32 and
15840 // Divide input vector into two parts
15841 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15842 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15843 // concat the vectors to original VT
15845 unsigned NumElems = InVT.getVectorNumElements();
15846 SDValue Undef = DAG.getUNDEF(InVT);
15848 SmallVector<int,8> ShufMask1(NumElems, -1);
15849 for (unsigned i = 0; i != NumElems/2; ++i)
15852 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15854 SmallVector<int,8> ShufMask2(NumElems, -1);
15855 for (unsigned i = 0; i != NumElems/2; ++i)
15856 ShufMask2[i] = i + NumElems/2;
15858 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15860 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15861 VT.getVectorNumElements()/2);
15863 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15864 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15866 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15869 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15870 // may emit an illegal shuffle but the expansion is still better than scalar
15871 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15872 // we'll emit a shuffle and a arithmetic shift.
15873 // TODO: It is possible to support ZExt by zeroing the undef values during
15874 // the shuffle phase or after the shuffle.
15875 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15876 SelectionDAG &DAG) {
15877 MVT RegVT = Op.getSimpleValueType();
15878 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15879 assert(RegVT.isInteger() &&
15880 "We only custom lower integer vector sext loads.");
15882 // Nothing useful we can do without SSE2 shuffles.
15883 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15885 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15887 EVT MemVT = Ld->getMemoryVT();
15888 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15889 unsigned RegSz = RegVT.getSizeInBits();
15891 ISD::LoadExtType Ext = Ld->getExtensionType();
15893 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15894 && "Only anyext and sext are currently implemented.");
15895 assert(MemVT != RegVT && "Cannot extend to the same type");
15896 assert(MemVT.isVector() && "Must load a vector from memory");
15898 unsigned NumElems = RegVT.getVectorNumElements();
15899 unsigned MemSz = MemVT.getSizeInBits();
15900 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15902 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15903 // The only way in which we have a legal 256-bit vector result but not the
15904 // integer 256-bit operations needed to directly lower a sextload is if we
15905 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15906 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15907 // correctly legalized. We do this late to allow the canonical form of
15908 // sextload to persist throughout the rest of the DAG combiner -- it wants
15909 // to fold together any extensions it can, and so will fuse a sign_extend
15910 // of an sextload into a sextload targeting a wider value.
15912 if (MemSz == 128) {
15913 // Just switch this to a normal load.
15914 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15915 "it must be a legal 128-bit vector "
15917 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15918 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15919 Ld->isInvariant(), Ld->getAlignment());
15921 assert(MemSz < 128 &&
15922 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15923 // Do an sext load to a 128-bit vector type. We want to use the same
15924 // number of elements, but elements half as wide. This will end up being
15925 // recursively lowered by this routine, but will succeed as we definitely
15926 // have all the necessary features if we're using AVX1.
15928 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15929 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15931 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15932 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15933 Ld->isNonTemporal(), Ld->isInvariant(),
15934 Ld->getAlignment());
15937 // Replace chain users with the new chain.
15938 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15939 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15941 // Finally, do a normal sign-extend to the desired register.
15942 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15945 // All sizes must be a power of two.
15946 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15947 "Non-power-of-two elements are not custom lowered!");
15949 // Attempt to load the original value using scalar loads.
15950 // Find the largest scalar type that divides the total loaded size.
15951 MVT SclrLoadTy = MVT::i8;
15952 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15953 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15954 MVT Tp = (MVT::SimpleValueType)tp;
15955 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15960 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15961 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15963 SclrLoadTy = MVT::f64;
15965 // Calculate the number of scalar loads that we need to perform
15966 // in order to load our vector from memory.
15967 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15969 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15970 "Can only lower sext loads with a single scalar load!");
15972 unsigned loadRegZize = RegSz;
15973 if (Ext == ISD::SEXTLOAD && RegSz == 256)
15976 // Represent our vector as a sequence of elements which are the
15977 // largest scalar that we can load.
15978 EVT LoadUnitVecVT = EVT::getVectorVT(
15979 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15981 // Represent the data using the same element type that is stored in
15982 // memory. In practice, we ''widen'' MemVT.
15984 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15985 loadRegZize / MemVT.getScalarType().getSizeInBits());
15987 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15988 "Invalid vector type");
15990 // We can't shuffle using an illegal type.
15991 assert(TLI.isTypeLegal(WideVecVT) &&
15992 "We only lower types that form legal widened vector types");
15994 SmallVector<SDValue, 8> Chains;
15995 SDValue Ptr = Ld->getBasePtr();
15996 SDValue Increment =
15997 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
15998 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
16000 for (unsigned i = 0; i < NumLoads; ++i) {
16001 // Perform a single load.
16002 SDValue ScalarLoad =
16003 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
16004 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
16005 Ld->getAlignment());
16006 Chains.push_back(ScalarLoad.getValue(1));
16007 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
16008 // another round of DAGCombining.
16010 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
16012 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
16013 ScalarLoad, DAG.getIntPtrConstant(i));
16015 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16018 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
16020 // Bitcast the loaded value to a vector of the original element type, in
16021 // the size of the target vector type.
16022 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
16023 unsigned SizeRatio = RegSz / MemSz;
16025 if (Ext == ISD::SEXTLOAD) {
16026 // If we have SSE4.1, we can directly emit a VSEXT node.
16027 if (Subtarget->hasSSE41()) {
16028 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
16029 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16033 // Otherwise we'll shuffle the small elements in the high bits of the
16034 // larger type and perform an arithmetic shift. If the shift is not legal
16035 // it's better to scalarize.
16036 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
16037 "We can't implement a sext load without an arithmetic right shift!");
16039 // Redistribute the loaded elements into the different locations.
16040 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16041 for (unsigned i = 0; i != NumElems; ++i)
16042 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
16044 SDValue Shuff = DAG.getVectorShuffle(
16045 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16047 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16049 // Build the arithmetic shift.
16050 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
16051 MemVT.getVectorElementType().getSizeInBits();
16053 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
16055 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16059 // Redistribute the loaded elements into the different locations.
16060 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16061 for (unsigned i = 0; i != NumElems; ++i)
16062 ShuffleVec[i * SizeRatio] = i;
16064 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
16065 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16067 // Bitcast to the requested type.
16068 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16069 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16073 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
16074 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
16075 // from the AND / OR.
16076 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
16077 Opc = Op.getOpcode();
16078 if (Opc != ISD::OR && Opc != ISD::AND)
16080 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16081 Op.getOperand(0).hasOneUse() &&
16082 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
16083 Op.getOperand(1).hasOneUse());
16086 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
16087 // 1 and that the SETCC node has a single use.
16088 static bool isXor1OfSetCC(SDValue Op) {
16089 if (Op.getOpcode() != ISD::XOR)
16091 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
16092 if (N1C && N1C->getAPIntValue() == 1) {
16093 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16094 Op.getOperand(0).hasOneUse();
16099 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
16100 bool addTest = true;
16101 SDValue Chain = Op.getOperand(0);
16102 SDValue Cond = Op.getOperand(1);
16103 SDValue Dest = Op.getOperand(2);
16106 bool Inverted = false;
16108 if (Cond.getOpcode() == ISD::SETCC) {
16109 // Check for setcc([su]{add,sub,mul}o == 0).
16110 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
16111 isa<ConstantSDNode>(Cond.getOperand(1)) &&
16112 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
16113 Cond.getOperand(0).getResNo() == 1 &&
16114 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
16115 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
16116 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
16117 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
16118 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
16119 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
16121 Cond = Cond.getOperand(0);
16123 SDValue NewCond = LowerSETCC(Cond, DAG);
16124 if (NewCond.getNode())
16129 // FIXME: LowerXALUO doesn't handle these!!
16130 else if (Cond.getOpcode() == X86ISD::ADD ||
16131 Cond.getOpcode() == X86ISD::SUB ||
16132 Cond.getOpcode() == X86ISD::SMUL ||
16133 Cond.getOpcode() == X86ISD::UMUL)
16134 Cond = LowerXALUO(Cond, DAG);
16137 // Look pass (and (setcc_carry (cmp ...)), 1).
16138 if (Cond.getOpcode() == ISD::AND &&
16139 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
16140 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
16141 if (C && C->getAPIntValue() == 1)
16142 Cond = Cond.getOperand(0);
16145 // If condition flag is set by a X86ISD::CMP, then use it as the condition
16146 // setting operand in place of the X86ISD::SETCC.
16147 unsigned CondOpcode = Cond.getOpcode();
16148 if (CondOpcode == X86ISD::SETCC ||
16149 CondOpcode == X86ISD::SETCC_CARRY) {
16150 CC = Cond.getOperand(0);
16152 SDValue Cmp = Cond.getOperand(1);
16153 unsigned Opc = Cmp.getOpcode();
16154 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
16155 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
16159 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
16163 // These can only come from an arithmetic instruction with overflow,
16164 // e.g. SADDO, UADDO.
16165 Cond = Cond.getNode()->getOperand(1);
16171 CondOpcode = Cond.getOpcode();
16172 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
16173 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
16174 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
16175 Cond.getOperand(0).getValueType() != MVT::i8)) {
16176 SDValue LHS = Cond.getOperand(0);
16177 SDValue RHS = Cond.getOperand(1);
16178 unsigned X86Opcode;
16181 // Keep this in sync with LowerXALUO, otherwise we might create redundant
16182 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
16184 switch (CondOpcode) {
16185 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
16187 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16189 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
16192 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
16193 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
16195 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16197 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
16200 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
16201 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
16202 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
16203 default: llvm_unreachable("unexpected overflowing operator");
16206 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
16207 if (CondOpcode == ISD::UMULO)
16208 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
16211 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
16213 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
16215 if (CondOpcode == ISD::UMULO)
16216 Cond = X86Op.getValue(2);
16218 Cond = X86Op.getValue(1);
16220 CC = DAG.getConstant(X86Cond, MVT::i8);
16224 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
16225 SDValue Cmp = Cond.getOperand(0).getOperand(1);
16226 if (CondOpc == ISD::OR) {
16227 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
16228 // two branches instead of an explicit OR instruction with a
16230 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16231 isX86LogicalCmp(Cmp)) {
16232 CC = Cond.getOperand(0).getOperand(0);
16233 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16234 Chain, Dest, CC, Cmp);
16235 CC = Cond.getOperand(1).getOperand(0);
16239 } else { // ISD::AND
16240 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
16241 // two branches instead of an explicit AND instruction with a
16242 // separate test. However, we only do this if this block doesn't
16243 // have a fall-through edge, because this requires an explicit
16244 // jmp when the condition is false.
16245 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16246 isX86LogicalCmp(Cmp) &&
16247 Op.getNode()->hasOneUse()) {
16248 X86::CondCode CCode =
16249 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16250 CCode = X86::GetOppositeBranchCondition(CCode);
16251 CC = DAG.getConstant(CCode, MVT::i8);
16252 SDNode *User = *Op.getNode()->use_begin();
16253 // Look for an unconditional branch following this conditional branch.
16254 // We need this because we need to reverse the successors in order
16255 // to implement FCMP_OEQ.
16256 if (User->getOpcode() == ISD::BR) {
16257 SDValue FalseBB = User->getOperand(1);
16259 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16260 assert(NewBR == User);
16264 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16265 Chain, Dest, CC, Cmp);
16266 X86::CondCode CCode =
16267 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
16268 CCode = X86::GetOppositeBranchCondition(CCode);
16269 CC = DAG.getConstant(CCode, MVT::i8);
16275 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
16276 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
16277 // It should be transformed during dag combiner except when the condition
16278 // is set by a arithmetics with overflow node.
16279 X86::CondCode CCode =
16280 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16281 CCode = X86::GetOppositeBranchCondition(CCode);
16282 CC = DAG.getConstant(CCode, MVT::i8);
16283 Cond = Cond.getOperand(0).getOperand(1);
16285 } else if (Cond.getOpcode() == ISD::SETCC &&
16286 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
16287 // For FCMP_OEQ, we can emit
16288 // two branches instead of an explicit AND instruction with a
16289 // separate test. However, we only do this if this block doesn't
16290 // have a fall-through edge, because this requires an explicit
16291 // jmp when the condition is false.
16292 if (Op.getNode()->hasOneUse()) {
16293 SDNode *User = *Op.getNode()->use_begin();
16294 // Look for an unconditional branch following this conditional branch.
16295 // We need this because we need to reverse the successors in order
16296 // to implement FCMP_OEQ.
16297 if (User->getOpcode() == ISD::BR) {
16298 SDValue FalseBB = User->getOperand(1);
16300 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16301 assert(NewBR == User);
16305 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16306 Cond.getOperand(0), Cond.getOperand(1));
16307 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16308 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16309 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16310 Chain, Dest, CC, Cmp);
16311 CC = DAG.getConstant(X86::COND_P, MVT::i8);
16316 } else if (Cond.getOpcode() == ISD::SETCC &&
16317 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
16318 // For FCMP_UNE, we can emit
16319 // two branches instead of an explicit AND instruction with a
16320 // separate test. However, we only do this if this block doesn't
16321 // have a fall-through edge, because this requires an explicit
16322 // jmp when the condition is false.
16323 if (Op.getNode()->hasOneUse()) {
16324 SDNode *User = *Op.getNode()->use_begin();
16325 // Look for an unconditional branch following this conditional branch.
16326 // We need this because we need to reverse the successors in order
16327 // to implement FCMP_UNE.
16328 if (User->getOpcode() == ISD::BR) {
16329 SDValue FalseBB = User->getOperand(1);
16331 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16332 assert(NewBR == User);
16335 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16336 Cond.getOperand(0), Cond.getOperand(1));
16337 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16338 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16339 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16340 Chain, Dest, CC, Cmp);
16341 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
16351 // Look pass the truncate if the high bits are known zero.
16352 if (isTruncWithZeroHighBitsInput(Cond, DAG))
16353 Cond = Cond.getOperand(0);
16355 // We know the result of AND is compared against zero. Try to match
16357 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
16358 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
16359 if (NewSetCC.getNode()) {
16360 CC = NewSetCC.getOperand(0);
16361 Cond = NewSetCC.getOperand(1);
16368 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
16369 CC = DAG.getConstant(X86Cond, MVT::i8);
16370 Cond = EmitTest(Cond, X86Cond, dl, DAG);
16372 Cond = ConvertCmpIfNecessary(Cond, DAG);
16373 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16374 Chain, Dest, CC, Cond);
16377 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
16378 // Calls to _alloca are needed to probe the stack when allocating more than 4k
16379 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
16380 // that the guard pages used by the OS virtual memory manager are allocated in
16381 // correct sequence.
16383 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
16384 SelectionDAG &DAG) const {
16385 MachineFunction &MF = DAG.getMachineFunction();
16386 bool SplitStack = MF.shouldSplitStack();
16387 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
16392 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16393 SDNode* Node = Op.getNode();
16395 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
16396 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
16397 " not tell us which reg is the stack pointer!");
16398 EVT VT = Node->getValueType(0);
16399 SDValue Tmp1 = SDValue(Node, 0);
16400 SDValue Tmp2 = SDValue(Node, 1);
16401 SDValue Tmp3 = Node->getOperand(2);
16402 SDValue Chain = Tmp1.getOperand(0);
16404 // Chain the dynamic stack allocation so that it doesn't modify the stack
16405 // pointer when other instructions are using the stack.
16406 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
16409 SDValue Size = Tmp2.getOperand(1);
16410 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
16411 Chain = SP.getValue(1);
16412 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
16413 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
16414 unsigned StackAlign = TFI.getStackAlignment();
16415 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
16416 if (Align > StackAlign)
16417 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
16418 DAG.getConstant(-(uint64_t)Align, VT));
16419 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
16421 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
16422 DAG.getIntPtrConstant(0, true), SDValue(),
16425 SDValue Ops[2] = { Tmp1, Tmp2 };
16426 return DAG.getMergeValues(Ops, dl);
16430 SDValue Chain = Op.getOperand(0);
16431 SDValue Size = Op.getOperand(1);
16432 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
16433 EVT VT = Op.getNode()->getValueType(0);
16435 bool Is64Bit = Subtarget->is64Bit();
16436 EVT SPTy = getPointerTy();
16439 MachineRegisterInfo &MRI = MF.getRegInfo();
16442 // The 64 bit implementation of segmented stacks needs to clobber both r10
16443 // r11. This makes it impossible to use it along with nested parameters.
16444 const Function *F = MF.getFunction();
16446 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
16448 if (I->hasNestAttr())
16449 report_fatal_error("Cannot use segmented stacks with functions that "
16450 "have nested arguments.");
16453 const TargetRegisterClass *AddrRegClass =
16454 getRegClassFor(getPointerTy());
16455 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
16456 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
16457 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
16458 DAG.getRegister(Vreg, SPTy));
16459 SDValue Ops1[2] = { Value, Chain };
16460 return DAG.getMergeValues(Ops1, dl);
16463 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
16465 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
16466 Flag = Chain.getValue(1);
16467 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
16469 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
16471 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16472 DAG.getSubtarget().getRegisterInfo());
16473 unsigned SPReg = RegInfo->getStackRegister();
16474 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
16475 Chain = SP.getValue(1);
16478 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
16479 DAG.getConstant(-(uint64_t)Align, VT));
16480 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
16483 SDValue Ops1[2] = { SP, Chain };
16484 return DAG.getMergeValues(Ops1, dl);
16488 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
16489 MachineFunction &MF = DAG.getMachineFunction();
16490 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16492 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16495 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
16496 // vastart just stores the address of the VarArgsFrameIndex slot into the
16497 // memory location argument.
16498 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16500 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
16501 MachinePointerInfo(SV), false, false, 0);
16505 // gp_offset (0 - 6 * 8)
16506 // fp_offset (48 - 48 + 8 * 16)
16507 // overflow_arg_area (point to parameters coming in memory).
16509 SmallVector<SDValue, 8> MemOps;
16510 SDValue FIN = Op.getOperand(1);
16512 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
16513 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
16515 FIN, MachinePointerInfo(SV), false, false, 0);
16516 MemOps.push_back(Store);
16519 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16520 FIN, DAG.getIntPtrConstant(4));
16521 Store = DAG.getStore(Op.getOperand(0), DL,
16522 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
16524 FIN, MachinePointerInfo(SV, 4), false, false, 0);
16525 MemOps.push_back(Store);
16527 // Store ptr to overflow_arg_area
16528 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16529 FIN, DAG.getIntPtrConstant(4));
16530 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16532 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
16533 MachinePointerInfo(SV, 8),
16535 MemOps.push_back(Store);
16537 // Store ptr to reg_save_area.
16538 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16539 FIN, DAG.getIntPtrConstant(8));
16540 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
16542 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
16543 MachinePointerInfo(SV, 16), false, false, 0);
16544 MemOps.push_back(Store);
16545 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
16548 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
16549 assert(Subtarget->is64Bit() &&
16550 "LowerVAARG only handles 64-bit va_arg!");
16551 assert((Subtarget->isTargetLinux() ||
16552 Subtarget->isTargetDarwin()) &&
16553 "Unhandled target in LowerVAARG");
16554 assert(Op.getNode()->getNumOperands() == 4);
16555 SDValue Chain = Op.getOperand(0);
16556 SDValue SrcPtr = Op.getOperand(1);
16557 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16558 unsigned Align = Op.getConstantOperandVal(3);
16561 EVT ArgVT = Op.getNode()->getValueType(0);
16562 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16563 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
16566 // Decide which area this value should be read from.
16567 // TODO: Implement the AMD64 ABI in its entirety. This simple
16568 // selection mechanism works only for the basic types.
16569 if (ArgVT == MVT::f80) {
16570 llvm_unreachable("va_arg for f80 not yet implemented");
16571 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
16572 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
16573 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
16574 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
16576 llvm_unreachable("Unhandled argument type in LowerVAARG");
16579 if (ArgMode == 2) {
16580 // Sanity Check: Make sure using fp_offset makes sense.
16581 assert(!DAG.getTarget().Options.UseSoftFloat &&
16582 !(DAG.getMachineFunction()
16583 .getFunction()->getAttributes()
16584 .hasAttribute(AttributeSet::FunctionIndex,
16585 Attribute::NoImplicitFloat)) &&
16586 Subtarget->hasSSE1());
16589 // Insert VAARG_64 node into the DAG
16590 // VAARG_64 returns two values: Variable Argument Address, Chain
16591 SmallVector<SDValue, 11> InstOps;
16592 InstOps.push_back(Chain);
16593 InstOps.push_back(SrcPtr);
16594 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
16595 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
16596 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
16597 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
16598 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
16599 VTs, InstOps, MVT::i64,
16600 MachinePointerInfo(SV),
16602 /*Volatile=*/false,
16604 /*WriteMem=*/true);
16605 Chain = VAARG.getValue(1);
16607 // Load the next argument and return it
16608 return DAG.getLoad(ArgVT, dl,
16611 MachinePointerInfo(),
16612 false, false, false, 0);
16615 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
16616 SelectionDAG &DAG) {
16617 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
16618 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
16619 SDValue Chain = Op.getOperand(0);
16620 SDValue DstPtr = Op.getOperand(1);
16621 SDValue SrcPtr = Op.getOperand(2);
16622 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
16623 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16626 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
16627 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
16629 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
16632 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
16633 // amount is a constant. Takes immediate version of shift as input.
16634 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16635 SDValue SrcOp, uint64_t ShiftAmt,
16636 SelectionDAG &DAG) {
16637 MVT ElementType = VT.getVectorElementType();
16639 // Fold this packed shift into its first operand if ShiftAmt is 0.
16643 // Check for ShiftAmt >= element width
16644 if (ShiftAmt >= ElementType.getSizeInBits()) {
16645 if (Opc == X86ISD::VSRAI)
16646 ShiftAmt = ElementType.getSizeInBits() - 1;
16648 return DAG.getConstant(0, VT);
16651 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16652 && "Unknown target vector shift-by-constant node");
16654 // Fold this packed vector shift into a build vector if SrcOp is a
16655 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16656 if (VT == SrcOp.getSimpleValueType() &&
16657 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16658 SmallVector<SDValue, 8> Elts;
16659 unsigned NumElts = SrcOp->getNumOperands();
16660 ConstantSDNode *ND;
16663 default: llvm_unreachable(nullptr);
16664 case X86ISD::VSHLI:
16665 for (unsigned i=0; i!=NumElts; ++i) {
16666 SDValue CurrentOp = SrcOp->getOperand(i);
16667 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16668 Elts.push_back(CurrentOp);
16671 ND = cast<ConstantSDNode>(CurrentOp);
16672 const APInt &C = ND->getAPIntValue();
16673 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
16676 case X86ISD::VSRLI:
16677 for (unsigned i=0; i!=NumElts; ++i) {
16678 SDValue CurrentOp = SrcOp->getOperand(i);
16679 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16680 Elts.push_back(CurrentOp);
16683 ND = cast<ConstantSDNode>(CurrentOp);
16684 const APInt &C = ND->getAPIntValue();
16685 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
16688 case X86ISD::VSRAI:
16689 for (unsigned i=0; i!=NumElts; ++i) {
16690 SDValue CurrentOp = SrcOp->getOperand(i);
16691 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16692 Elts.push_back(CurrentOp);
16695 ND = cast<ConstantSDNode>(CurrentOp);
16696 const APInt &C = ND->getAPIntValue();
16697 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
16702 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16705 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
16708 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16709 // may or may not be a constant. Takes immediate version of shift as input.
16710 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16711 SDValue SrcOp, SDValue ShAmt,
16712 SelectionDAG &DAG) {
16713 MVT SVT = ShAmt.getSimpleValueType();
16714 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
16716 // Catch shift-by-constant.
16717 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16718 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16719 CShAmt->getZExtValue(), DAG);
16721 // Change opcode to non-immediate version
16723 default: llvm_unreachable("Unknown target vector shift node");
16724 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16725 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16726 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16729 const X86Subtarget &Subtarget =
16730 DAG.getTarget().getSubtarget<X86Subtarget>();
16731 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
16732 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
16733 // Let the shuffle legalizer expand this shift amount node.
16734 SDValue Op0 = ShAmt.getOperand(0);
16735 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
16736 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
16738 // Need to build a vector containing shift amount.
16739 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
16740 SmallVector<SDValue, 4> ShOps;
16741 ShOps.push_back(ShAmt);
16742 if (SVT == MVT::i32) {
16743 ShOps.push_back(DAG.getConstant(0, SVT));
16744 ShOps.push_back(DAG.getUNDEF(SVT));
16746 ShOps.push_back(DAG.getUNDEF(SVT));
16748 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
16749 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
16752 // The return type has to be a 128-bit type with the same element
16753 // type as the input type.
16754 MVT EltVT = VT.getVectorElementType();
16755 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16757 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
16758 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16761 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16762 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16763 /// necessary casting for \p Mask when lowering masking intrinsics.
16764 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16765 SDValue PreservedSrc,
16766 const X86Subtarget *Subtarget,
16767 SelectionDAG &DAG) {
16768 EVT VT = Op.getValueType();
16769 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16770 MVT::i1, VT.getVectorNumElements());
16771 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16772 Mask.getValueType().getSizeInBits());
16775 assert(MaskVT.isSimple() && "invalid mask type");
16777 if (isAllOnes(Mask))
16780 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16781 // are extracted by EXTRACT_SUBVECTOR.
16782 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16783 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16784 DAG.getIntPtrConstant(0));
16786 switch (Op.getOpcode()) {
16788 case X86ISD::PCMPEQM:
16789 case X86ISD::PCMPGTM:
16791 case X86ISD::CMPMU:
16792 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16794 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16795 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16796 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
16799 /// \brief Creates an SDNode for a predicated scalar operation.
16800 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
16801 /// The mask is comming as MVT::i8 and it should be truncated
16802 /// to MVT::i1 while lowering masking intrinsics.
16803 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
16804 /// "X86select" instead of "vselect". We just can't create the "vselect" node for
16805 /// a scalar instruction.
16806 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
16807 SDValue PreservedSrc,
16808 const X86Subtarget *Subtarget,
16809 SelectionDAG &DAG) {
16810 if (isAllOnes(Mask))
16813 EVT VT = Op.getValueType();
16815 // The mask should be of type MVT::i1
16816 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
16818 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16819 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16820 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
16823 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
16825 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16826 case Intrinsic::x86_fma_vfmadd_ps:
16827 case Intrinsic::x86_fma_vfmadd_pd:
16828 case Intrinsic::x86_fma_vfmadd_ps_256:
16829 case Intrinsic::x86_fma_vfmadd_pd_256:
16830 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16831 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16832 return X86ISD::FMADD;
16833 case Intrinsic::x86_fma_vfmsub_ps:
16834 case Intrinsic::x86_fma_vfmsub_pd:
16835 case Intrinsic::x86_fma_vfmsub_ps_256:
16836 case Intrinsic::x86_fma_vfmsub_pd_256:
16837 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16838 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16839 return X86ISD::FMSUB;
16840 case Intrinsic::x86_fma_vfnmadd_ps:
16841 case Intrinsic::x86_fma_vfnmadd_pd:
16842 case Intrinsic::x86_fma_vfnmadd_ps_256:
16843 case Intrinsic::x86_fma_vfnmadd_pd_256:
16844 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16845 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16846 return X86ISD::FNMADD;
16847 case Intrinsic::x86_fma_vfnmsub_ps:
16848 case Intrinsic::x86_fma_vfnmsub_pd:
16849 case Intrinsic::x86_fma_vfnmsub_ps_256:
16850 case Intrinsic::x86_fma_vfnmsub_pd_256:
16851 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16852 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16853 return X86ISD::FNMSUB;
16854 case Intrinsic::x86_fma_vfmaddsub_ps:
16855 case Intrinsic::x86_fma_vfmaddsub_pd:
16856 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16857 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16858 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16859 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16860 return X86ISD::FMADDSUB;
16861 case Intrinsic::x86_fma_vfmsubadd_ps:
16862 case Intrinsic::x86_fma_vfmsubadd_pd:
16863 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16864 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16865 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16866 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16867 return X86ISD::FMSUBADD;
16871 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16872 SelectionDAG &DAG) {
16874 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16875 EVT VT = Op.getValueType();
16876 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16878 switch(IntrData->Type) {
16879 case INTR_TYPE_1OP:
16880 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16881 case INTR_TYPE_2OP:
16882 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16884 case INTR_TYPE_3OP:
16885 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16886 Op.getOperand(2), Op.getOperand(3));
16887 case INTR_TYPE_1OP_MASK_RM: {
16888 SDValue Src = Op.getOperand(1);
16889 SDValue Src0 = Op.getOperand(2);
16890 SDValue Mask = Op.getOperand(3);
16891 SDValue RoundingMode = Op.getOperand(4);
16892 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16894 Mask, Src0, Subtarget, DAG);
16896 case INTR_TYPE_SCALAR_MASK_RM: {
16897 SDValue Src1 = Op.getOperand(1);
16898 SDValue Src2 = Op.getOperand(2);
16899 SDValue Src0 = Op.getOperand(3);
16900 SDValue Mask = Op.getOperand(4);
16901 SDValue RoundingMode = Op.getOperand(5);
16902 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16904 Mask, Src0, Subtarget, DAG);
16906 case INTR_TYPE_2OP_MASK: {
16907 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Op.getOperand(1),
16909 Op.getOperand(4), Op.getOperand(3), Subtarget, DAG);
16912 case CMP_MASK_CC: {
16913 // Comparison intrinsics with masks.
16914 // Example of transformation:
16915 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16916 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16918 // (v8i1 (insert_subvector undef,
16919 // (v2i1 (and (PCMPEQM %a, %b),
16920 // (extract_subvector
16921 // (v8i1 (bitcast %mask)), 0))), 0))))
16922 EVT VT = Op.getOperand(1).getValueType();
16923 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16924 VT.getVectorNumElements());
16925 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16926 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16927 Mask.getValueType().getSizeInBits());
16929 if (IntrData->Type == CMP_MASK_CC) {
16930 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16931 Op.getOperand(2), Op.getOperand(3));
16933 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16934 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16937 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16938 DAG.getTargetConstant(0, MaskVT),
16940 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16941 DAG.getUNDEF(BitcastVT), CmpMask,
16942 DAG.getIntPtrConstant(0));
16943 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
16945 case COMI: { // Comparison intrinsics
16946 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16947 SDValue LHS = Op.getOperand(1);
16948 SDValue RHS = Op.getOperand(2);
16949 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
16950 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16951 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16952 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16953 DAG.getConstant(X86CC, MVT::i8), Cond);
16954 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16957 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16958 Op.getOperand(1), Op.getOperand(2), DAG);
16960 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
16961 Op.getSimpleValueType(),
16963 Op.getOperand(2), DAG),
16964 Op.getOperand(4), Op.getOperand(3), Subtarget,
16966 case COMPRESS_EXPAND_IN_REG: {
16967 SDValue Mask = Op.getOperand(3);
16968 SDValue DataToCompress = Op.getOperand(1);
16969 SDValue PassThru = Op.getOperand(2);
16970 if (isAllOnes(Mask)) // return data as is
16971 return Op.getOperand(1);
16972 EVT VT = Op.getValueType();
16973 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16974 VT.getVectorNumElements());
16975 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16976 Mask.getValueType().getSizeInBits());
16978 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16979 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16980 DAG.getIntPtrConstant(0));
16982 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToCompress,
16991 default: return SDValue(); // Don't custom lower most intrinsics.
16993 case Intrinsic::x86_avx512_mask_valign_q_512:
16994 case Intrinsic::x86_avx512_mask_valign_d_512:
16995 // Vector source operands are swapped.
16996 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
16997 Op.getValueType(), Op.getOperand(2),
17000 Op.getOperand(5), Op.getOperand(4),
17003 // ptest and testp intrinsics. The intrinsic these come from are designed to
17004 // return an integer value, not just an instruction so lower it to the ptest
17005 // or testp pattern and a setcc for the result.
17006 case Intrinsic::x86_sse41_ptestz:
17007 case Intrinsic::x86_sse41_ptestc:
17008 case Intrinsic::x86_sse41_ptestnzc:
17009 case Intrinsic::x86_avx_ptestz_256:
17010 case Intrinsic::x86_avx_ptestc_256:
17011 case Intrinsic::x86_avx_ptestnzc_256:
17012 case Intrinsic::x86_avx_vtestz_ps:
17013 case Intrinsic::x86_avx_vtestc_ps:
17014 case Intrinsic::x86_avx_vtestnzc_ps:
17015 case Intrinsic::x86_avx_vtestz_pd:
17016 case Intrinsic::x86_avx_vtestc_pd:
17017 case Intrinsic::x86_avx_vtestnzc_pd:
17018 case Intrinsic::x86_avx_vtestz_ps_256:
17019 case Intrinsic::x86_avx_vtestc_ps_256:
17020 case Intrinsic::x86_avx_vtestnzc_ps_256:
17021 case Intrinsic::x86_avx_vtestz_pd_256:
17022 case Intrinsic::x86_avx_vtestc_pd_256:
17023 case Intrinsic::x86_avx_vtestnzc_pd_256: {
17024 bool IsTestPacked = false;
17027 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
17028 case Intrinsic::x86_avx_vtestz_ps:
17029 case Intrinsic::x86_avx_vtestz_pd:
17030 case Intrinsic::x86_avx_vtestz_ps_256:
17031 case Intrinsic::x86_avx_vtestz_pd_256:
17032 IsTestPacked = true; // Fallthrough
17033 case Intrinsic::x86_sse41_ptestz:
17034 case Intrinsic::x86_avx_ptestz_256:
17036 X86CC = X86::COND_E;
17038 case Intrinsic::x86_avx_vtestc_ps:
17039 case Intrinsic::x86_avx_vtestc_pd:
17040 case Intrinsic::x86_avx_vtestc_ps_256:
17041 case Intrinsic::x86_avx_vtestc_pd_256:
17042 IsTestPacked = true; // Fallthrough
17043 case Intrinsic::x86_sse41_ptestc:
17044 case Intrinsic::x86_avx_ptestc_256:
17046 X86CC = X86::COND_B;
17048 case Intrinsic::x86_avx_vtestnzc_ps:
17049 case Intrinsic::x86_avx_vtestnzc_pd:
17050 case Intrinsic::x86_avx_vtestnzc_ps_256:
17051 case Intrinsic::x86_avx_vtestnzc_pd_256:
17052 IsTestPacked = true; // Fallthrough
17053 case Intrinsic::x86_sse41_ptestnzc:
17054 case Intrinsic::x86_avx_ptestnzc_256:
17056 X86CC = X86::COND_A;
17060 SDValue LHS = Op.getOperand(1);
17061 SDValue RHS = Op.getOperand(2);
17062 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
17063 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
17064 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17065 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
17066 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17068 case Intrinsic::x86_avx512_kortestz_w:
17069 case Intrinsic::x86_avx512_kortestc_w: {
17070 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
17071 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
17072 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
17073 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17074 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
17075 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
17076 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17079 case Intrinsic::x86_sse42_pcmpistria128:
17080 case Intrinsic::x86_sse42_pcmpestria128:
17081 case Intrinsic::x86_sse42_pcmpistric128:
17082 case Intrinsic::x86_sse42_pcmpestric128:
17083 case Intrinsic::x86_sse42_pcmpistrio128:
17084 case Intrinsic::x86_sse42_pcmpestrio128:
17085 case Intrinsic::x86_sse42_pcmpistris128:
17086 case Intrinsic::x86_sse42_pcmpestris128:
17087 case Intrinsic::x86_sse42_pcmpistriz128:
17088 case Intrinsic::x86_sse42_pcmpestriz128: {
17092 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
17093 case Intrinsic::x86_sse42_pcmpistria128:
17094 Opcode = X86ISD::PCMPISTRI;
17095 X86CC = X86::COND_A;
17097 case Intrinsic::x86_sse42_pcmpestria128:
17098 Opcode = X86ISD::PCMPESTRI;
17099 X86CC = X86::COND_A;
17101 case Intrinsic::x86_sse42_pcmpistric128:
17102 Opcode = X86ISD::PCMPISTRI;
17103 X86CC = X86::COND_B;
17105 case Intrinsic::x86_sse42_pcmpestric128:
17106 Opcode = X86ISD::PCMPESTRI;
17107 X86CC = X86::COND_B;
17109 case Intrinsic::x86_sse42_pcmpistrio128:
17110 Opcode = X86ISD::PCMPISTRI;
17111 X86CC = X86::COND_O;
17113 case Intrinsic::x86_sse42_pcmpestrio128:
17114 Opcode = X86ISD::PCMPESTRI;
17115 X86CC = X86::COND_O;
17117 case Intrinsic::x86_sse42_pcmpistris128:
17118 Opcode = X86ISD::PCMPISTRI;
17119 X86CC = X86::COND_S;
17121 case Intrinsic::x86_sse42_pcmpestris128:
17122 Opcode = X86ISD::PCMPESTRI;
17123 X86CC = X86::COND_S;
17125 case Intrinsic::x86_sse42_pcmpistriz128:
17126 Opcode = X86ISD::PCMPISTRI;
17127 X86CC = X86::COND_E;
17129 case Intrinsic::x86_sse42_pcmpestriz128:
17130 Opcode = X86ISD::PCMPESTRI;
17131 X86CC = X86::COND_E;
17134 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17135 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17136 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
17137 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17138 DAG.getConstant(X86CC, MVT::i8),
17139 SDValue(PCMP.getNode(), 1));
17140 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17143 case Intrinsic::x86_sse42_pcmpistri128:
17144 case Intrinsic::x86_sse42_pcmpestri128: {
17146 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
17147 Opcode = X86ISD::PCMPISTRI;
17149 Opcode = X86ISD::PCMPESTRI;
17151 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17152 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17153 return DAG.getNode(Opcode, dl, VTs, NewOps);
17156 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
17157 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
17158 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
17159 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
17160 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
17161 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
17162 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
17163 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
17164 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
17165 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
17166 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
17167 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
17168 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
17169 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
17170 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
17171 dl, Op.getValueType(),
17175 Op.getOperand(4), Op.getOperand(1),
17181 case Intrinsic::x86_fma_vfmadd_ps:
17182 case Intrinsic::x86_fma_vfmadd_pd:
17183 case Intrinsic::x86_fma_vfmsub_ps:
17184 case Intrinsic::x86_fma_vfmsub_pd:
17185 case Intrinsic::x86_fma_vfnmadd_ps:
17186 case Intrinsic::x86_fma_vfnmadd_pd:
17187 case Intrinsic::x86_fma_vfnmsub_ps:
17188 case Intrinsic::x86_fma_vfnmsub_pd:
17189 case Intrinsic::x86_fma_vfmaddsub_ps:
17190 case Intrinsic::x86_fma_vfmaddsub_pd:
17191 case Intrinsic::x86_fma_vfmsubadd_ps:
17192 case Intrinsic::x86_fma_vfmsubadd_pd:
17193 case Intrinsic::x86_fma_vfmadd_ps_256:
17194 case Intrinsic::x86_fma_vfmadd_pd_256:
17195 case Intrinsic::x86_fma_vfmsub_ps_256:
17196 case Intrinsic::x86_fma_vfmsub_pd_256:
17197 case Intrinsic::x86_fma_vfnmadd_ps_256:
17198 case Intrinsic::x86_fma_vfnmadd_pd_256:
17199 case Intrinsic::x86_fma_vfnmsub_ps_256:
17200 case Intrinsic::x86_fma_vfnmsub_pd_256:
17201 case Intrinsic::x86_fma_vfmaddsub_ps_256:
17202 case Intrinsic::x86_fma_vfmaddsub_pd_256:
17203 case Intrinsic::x86_fma_vfmsubadd_ps_256:
17204 case Intrinsic::x86_fma_vfmsubadd_pd_256:
17205 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
17206 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
17210 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17211 SDValue Src, SDValue Mask, SDValue Base,
17212 SDValue Index, SDValue ScaleOp, SDValue Chain,
17213 const X86Subtarget * Subtarget) {
17215 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17216 assert(C && "Invalid scale type");
17217 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17218 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17219 Index.getSimpleValueType().getVectorNumElements());
17221 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17223 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17225 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17226 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
17227 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17228 SDValue Segment = DAG.getRegister(0, MVT::i32);
17229 if (Src.getOpcode() == ISD::UNDEF)
17230 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
17231 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17232 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17233 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
17234 return DAG.getMergeValues(RetOps, dl);
17237 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17238 SDValue Src, SDValue Mask, SDValue Base,
17239 SDValue Index, SDValue ScaleOp, SDValue Chain) {
17241 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17242 assert(C && "Invalid scale type");
17243 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17244 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17245 SDValue Segment = DAG.getRegister(0, MVT::i32);
17246 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17247 Index.getSimpleValueType().getVectorNumElements());
17249 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17251 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17253 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17254 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
17255 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
17256 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17257 return SDValue(Res, 1);
17260 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17261 SDValue Mask, SDValue Base, SDValue Index,
17262 SDValue ScaleOp, SDValue Chain) {
17264 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17265 assert(C && "Invalid scale type");
17266 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17267 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17268 SDValue Segment = DAG.getRegister(0, MVT::i32);
17270 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
17272 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17274 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17276 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17277 //SDVTList VTs = DAG.getVTList(MVT::Other);
17278 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17279 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
17280 return SDValue(Res, 0);
17283 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
17284 // read performance monitor counters (x86_rdpmc).
17285 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
17286 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17287 SmallVectorImpl<SDValue> &Results) {
17288 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17289 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17292 // The ECX register is used to select the index of the performance counter
17294 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
17296 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
17298 // Reads the content of a 64-bit performance counter and returns it in the
17299 // registers EDX:EAX.
17300 if (Subtarget->is64Bit()) {
17301 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17302 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17305 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17306 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17309 Chain = HI.getValue(1);
17311 if (Subtarget->is64Bit()) {
17312 // The EAX register is loaded with the low-order 32 bits. The EDX register
17313 // is loaded with the supported high-order bits of the counter.
17314 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17315 DAG.getConstant(32, MVT::i8));
17316 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17317 Results.push_back(Chain);
17321 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17322 SDValue Ops[] = { LO, HI };
17323 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17324 Results.push_back(Pair);
17325 Results.push_back(Chain);
17328 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
17329 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
17330 // also used to custom lower READCYCLECOUNTER nodes.
17331 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
17332 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17333 SmallVectorImpl<SDValue> &Results) {
17334 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17335 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
17338 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
17339 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
17340 // and the EAX register is loaded with the low-order 32 bits.
17341 if (Subtarget->is64Bit()) {
17342 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17343 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17346 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17347 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17350 SDValue Chain = HI.getValue(1);
17352 if (Opcode == X86ISD::RDTSCP_DAG) {
17353 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17355 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
17356 // the ECX register. Add 'ecx' explicitly to the chain.
17357 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
17359 // Explicitly store the content of ECX at the location passed in input
17360 // to the 'rdtscp' intrinsic.
17361 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
17362 MachinePointerInfo(), false, false, 0);
17365 if (Subtarget->is64Bit()) {
17366 // The EDX register is loaded with the high-order 32 bits of the MSR, and
17367 // the EAX register is loaded with the low-order 32 bits.
17368 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17369 DAG.getConstant(32, MVT::i8));
17370 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17371 Results.push_back(Chain);
17375 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17376 SDValue Ops[] = { LO, HI };
17377 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17378 Results.push_back(Pair);
17379 Results.push_back(Chain);
17382 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17383 SelectionDAG &DAG) {
17384 SmallVector<SDValue, 2> Results;
17386 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17388 return DAG.getMergeValues(Results, DL);
17392 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17393 SelectionDAG &DAG) {
17394 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17396 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17401 switch(IntrData->Type) {
17403 llvm_unreachable("Unknown Intrinsic Type");
17407 // Emit the node with the right value type.
17408 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17409 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17411 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17412 // Otherwise return the value from Rand, which is always 0, casted to i32.
17413 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17414 DAG.getConstant(1, Op->getValueType(1)),
17415 DAG.getConstant(X86::COND_B, MVT::i32),
17416 SDValue(Result.getNode(), 1) };
17417 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17418 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17421 // Return { result, isValid, chain }.
17422 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17423 SDValue(Result.getNode(), 2));
17426 //gather(v1, mask, index, base, scale);
17427 SDValue Chain = Op.getOperand(0);
17428 SDValue Src = Op.getOperand(2);
17429 SDValue Base = Op.getOperand(3);
17430 SDValue Index = Op.getOperand(4);
17431 SDValue Mask = Op.getOperand(5);
17432 SDValue Scale = Op.getOperand(6);
17433 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
17437 //scatter(base, mask, index, v1, scale);
17438 SDValue Chain = Op.getOperand(0);
17439 SDValue Base = Op.getOperand(2);
17440 SDValue Mask = Op.getOperand(3);
17441 SDValue Index = Op.getOperand(4);
17442 SDValue Src = Op.getOperand(5);
17443 SDValue Scale = Op.getOperand(6);
17444 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
17447 SDValue Hint = Op.getOperand(6);
17449 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
17450 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
17451 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
17452 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17453 SDValue Chain = Op.getOperand(0);
17454 SDValue Mask = Op.getOperand(2);
17455 SDValue Index = Op.getOperand(3);
17456 SDValue Base = Op.getOperand(4);
17457 SDValue Scale = Op.getOperand(5);
17458 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17460 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17462 SmallVector<SDValue, 2> Results;
17463 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
17464 return DAG.getMergeValues(Results, dl);
17466 // Read Performance Monitoring Counters.
17468 SmallVector<SDValue, 2> Results;
17469 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17470 return DAG.getMergeValues(Results, dl);
17472 // XTEST intrinsics.
17474 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17475 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17476 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17477 DAG.getConstant(X86::COND_NE, MVT::i8),
17479 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17480 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17481 Ret, SDValue(InTrans.getNode(), 1));
17485 SmallVector<SDValue, 2> Results;
17486 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17487 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17488 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17489 DAG.getConstant(-1, MVT::i8));
17490 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17491 Op.getOperand(4), GenCF.getValue(1));
17492 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17493 Op.getOperand(5), MachinePointerInfo(),
17495 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17496 DAG.getConstant(X86::COND_B, MVT::i8),
17498 Results.push_back(SetCC);
17499 Results.push_back(Store);
17500 return DAG.getMergeValues(Results, dl);
17502 case COMPRESS_TO_MEM: {
17504 SDValue Mask = Op.getOperand(4);
17505 SDValue DataToCompress = Op.getOperand(3);
17506 SDValue Addr = Op.getOperand(2);
17507 SDValue Chain = Op.getOperand(0);
17509 if (isAllOnes(Mask)) // return just a store
17510 return DAG.getStore(Chain, dl, DataToCompress, Addr,
17511 MachinePointerInfo(), false, false, 0);
17513 EVT VT = DataToCompress.getValueType();
17514 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17515 VT.getVectorNumElements());
17516 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17517 Mask.getValueType().getSizeInBits());
17518 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17519 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17520 DAG.getIntPtrConstant(0));
17522 SDValue Compressed = DAG.getNode(IntrData->Opc0, dl, VT, VMask,
17523 DataToCompress, DAG.getUNDEF(VT));
17524 return DAG.getStore(Chain, dl, Compressed, Addr,
17525 MachinePointerInfo(), false, false, 0);
17527 case EXPAND_FROM_MEM: {
17529 SDValue Mask = Op.getOperand(4);
17530 SDValue PathThru = Op.getOperand(3);
17531 SDValue Addr = Op.getOperand(2);
17532 SDValue Chain = Op.getOperand(0);
17533 EVT VT = Op.getValueType();
17535 if (isAllOnes(Mask)) // return just a load
17536 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
17538 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17539 VT.getVectorNumElements());
17540 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17541 Mask.getValueType().getSizeInBits());
17542 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17543 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17544 DAG.getIntPtrConstant(0));
17546 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
17547 false, false, false, 0);
17549 SmallVector<SDValue, 2> Results;
17550 Results.push_back(DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToExpand,
17552 Results.push_back(Chain);
17553 return DAG.getMergeValues(Results, dl);
17558 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17559 SelectionDAG &DAG) const {
17560 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17561 MFI->setReturnAddressIsTaken(true);
17563 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17566 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17568 EVT PtrVT = getPointerTy();
17571 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17572 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17573 DAG.getSubtarget().getRegisterInfo());
17574 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
17575 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17576 DAG.getNode(ISD::ADD, dl, PtrVT,
17577 FrameAddr, Offset),
17578 MachinePointerInfo(), false, false, false, 0);
17581 // Just load the return address.
17582 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17583 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17584 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17587 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17588 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17589 MFI->setFrameAddressIsTaken(true);
17591 EVT VT = Op.getValueType();
17592 SDLoc dl(Op); // FIXME probably not meaningful
17593 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17594 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17595 DAG.getSubtarget().getRegisterInfo());
17596 unsigned FrameReg = RegInfo->getPtrSizedFrameRegister(
17597 DAG.getMachineFunction());
17598 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17599 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17600 "Invalid Frame Register!");
17601 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17603 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17604 MachinePointerInfo(),
17605 false, false, false, 0);
17609 // FIXME? Maybe this could be a TableGen attribute on some registers and
17610 // this table could be generated automatically from RegInfo.
17611 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
17613 unsigned Reg = StringSwitch<unsigned>(RegName)
17614 .Case("esp", X86::ESP)
17615 .Case("rsp", X86::RSP)
17619 report_fatal_error("Invalid register name global variable");
17622 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17623 SelectionDAG &DAG) const {
17624 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17625 DAG.getSubtarget().getRegisterInfo());
17626 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
17629 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17630 SDValue Chain = Op.getOperand(0);
17631 SDValue Offset = Op.getOperand(1);
17632 SDValue Handler = Op.getOperand(2);
17635 EVT PtrVT = getPointerTy();
17636 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17637 DAG.getSubtarget().getRegisterInfo());
17638 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17639 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17640 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17641 "Invalid Frame Register!");
17642 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17643 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17645 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17646 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
17647 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17648 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17650 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17652 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17653 DAG.getRegister(StoreAddrReg, PtrVT));
17656 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17657 SelectionDAG &DAG) const {
17659 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17660 DAG.getVTList(MVT::i32, MVT::Other),
17661 Op.getOperand(0), Op.getOperand(1));
17664 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17665 SelectionDAG &DAG) const {
17667 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17668 Op.getOperand(0), Op.getOperand(1));
17671 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17672 return Op.getOperand(0);
17675 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17676 SelectionDAG &DAG) const {
17677 SDValue Root = Op.getOperand(0);
17678 SDValue Trmp = Op.getOperand(1); // trampoline
17679 SDValue FPtr = Op.getOperand(2); // nested function
17680 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17683 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17684 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
17686 if (Subtarget->is64Bit()) {
17687 SDValue OutChains[6];
17689 // Large code-model.
17690 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17691 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17693 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17694 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17696 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17698 // Load the pointer to the nested function into R11.
17699 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17700 SDValue Addr = Trmp;
17701 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17702 Addr, MachinePointerInfo(TrmpAddr),
17705 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17706 DAG.getConstant(2, MVT::i64));
17707 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17708 MachinePointerInfo(TrmpAddr, 2),
17711 // Load the 'nest' parameter value into R10.
17712 // R10 is specified in X86CallingConv.td
17713 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17714 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17715 DAG.getConstant(10, MVT::i64));
17716 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17717 Addr, MachinePointerInfo(TrmpAddr, 10),
17720 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17721 DAG.getConstant(12, MVT::i64));
17722 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17723 MachinePointerInfo(TrmpAddr, 12),
17726 // Jump to the nested function.
17727 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17728 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17729 DAG.getConstant(20, MVT::i64));
17730 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17731 Addr, MachinePointerInfo(TrmpAddr, 20),
17734 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17735 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17736 DAG.getConstant(22, MVT::i64));
17737 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
17738 MachinePointerInfo(TrmpAddr, 22),
17741 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17743 const Function *Func =
17744 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17745 CallingConv::ID CC = Func->getCallingConv();
17750 llvm_unreachable("Unsupported calling convention");
17751 case CallingConv::C:
17752 case CallingConv::X86_StdCall: {
17753 // Pass 'nest' parameter in ECX.
17754 // Must be kept in sync with X86CallingConv.td
17755 NestReg = X86::ECX;
17757 // Check that ECX wasn't needed by an 'inreg' parameter.
17758 FunctionType *FTy = Func->getFunctionType();
17759 const AttributeSet &Attrs = Func->getAttributes();
17761 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17762 unsigned InRegCount = 0;
17765 for (FunctionType::param_iterator I = FTy->param_begin(),
17766 E = FTy->param_end(); I != E; ++I, ++Idx)
17767 if (Attrs.hasAttribute(Idx, Attribute::InReg))
17768 // FIXME: should only count parameters that are lowered to integers.
17769 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
17771 if (InRegCount > 2) {
17772 report_fatal_error("Nest register in use - reduce number of inreg"
17778 case CallingConv::X86_FastCall:
17779 case CallingConv::X86_ThisCall:
17780 case CallingConv::Fast:
17781 // Pass 'nest' parameter in EAX.
17782 // Must be kept in sync with X86CallingConv.td
17783 NestReg = X86::EAX;
17787 SDValue OutChains[4];
17788 SDValue Addr, Disp;
17790 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17791 DAG.getConstant(10, MVT::i32));
17792 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17794 // This is storing the opcode for MOV32ri.
17795 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17796 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17797 OutChains[0] = DAG.getStore(Root, dl,
17798 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
17799 Trmp, MachinePointerInfo(TrmpAddr),
17802 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17803 DAG.getConstant(1, MVT::i32));
17804 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17805 MachinePointerInfo(TrmpAddr, 1),
17808 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17809 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17810 DAG.getConstant(5, MVT::i32));
17811 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17812 MachinePointerInfo(TrmpAddr, 5),
17815 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17816 DAG.getConstant(6, MVT::i32));
17817 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17818 MachinePointerInfo(TrmpAddr, 6),
17821 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17825 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17826 SelectionDAG &DAG) const {
17828 The rounding mode is in bits 11:10 of FPSR, and has the following
17830 00 Round to nearest
17835 FLT_ROUNDS, on the other hand, expects the following:
17842 To perform the conversion, we do:
17843 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17846 MachineFunction &MF = DAG.getMachineFunction();
17847 const TargetMachine &TM = MF.getTarget();
17848 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17849 unsigned StackAlignment = TFI.getStackAlignment();
17850 MVT VT = Op.getSimpleValueType();
17853 // Save FP Control Word to stack slot
17854 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17855 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
17857 MachineMemOperand *MMO =
17858 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
17859 MachineMemOperand::MOStore, 2, 2);
17861 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17862 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17863 DAG.getVTList(MVT::Other),
17864 Ops, MVT::i16, MMO);
17866 // Load FP Control Word from stack slot
17867 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17868 MachinePointerInfo(), false, false, false, 0);
17870 // Transform as necessary
17872 DAG.getNode(ISD::SRL, DL, MVT::i16,
17873 DAG.getNode(ISD::AND, DL, MVT::i16,
17874 CWD, DAG.getConstant(0x800, MVT::i16)),
17875 DAG.getConstant(11, MVT::i8));
17877 DAG.getNode(ISD::SRL, DL, MVT::i16,
17878 DAG.getNode(ISD::AND, DL, MVT::i16,
17879 CWD, DAG.getConstant(0x400, MVT::i16)),
17880 DAG.getConstant(9, MVT::i8));
17883 DAG.getNode(ISD::AND, DL, MVT::i16,
17884 DAG.getNode(ISD::ADD, DL, MVT::i16,
17885 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17886 DAG.getConstant(1, MVT::i16)),
17887 DAG.getConstant(3, MVT::i16));
17889 return DAG.getNode((VT.getSizeInBits() < 16 ?
17890 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17893 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17894 MVT VT = Op.getSimpleValueType();
17896 unsigned NumBits = VT.getSizeInBits();
17899 Op = Op.getOperand(0);
17900 if (VT == MVT::i8) {
17901 // Zero extend to i32 since there is not an i8 bsr.
17903 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17906 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17907 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17908 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17910 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17913 DAG.getConstant(NumBits+NumBits-1, OpVT),
17914 DAG.getConstant(X86::COND_E, MVT::i8),
17917 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17919 // Finally xor with NumBits-1.
17920 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17923 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17927 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17928 MVT VT = Op.getSimpleValueType();
17930 unsigned NumBits = VT.getSizeInBits();
17933 Op = Op.getOperand(0);
17934 if (VT == MVT::i8) {
17935 // Zero extend to i32 since there is not an i8 bsr.
17937 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17940 // Issue a bsr (scan bits in reverse).
17941 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17942 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17944 // And xor with NumBits-1.
17945 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17948 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17952 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17953 MVT VT = Op.getSimpleValueType();
17954 unsigned NumBits = VT.getSizeInBits();
17956 Op = Op.getOperand(0);
17958 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17959 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17960 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
17962 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17965 DAG.getConstant(NumBits, VT),
17966 DAG.getConstant(X86::COND_E, MVT::i8),
17969 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17972 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17973 // ones, and then concatenate the result back.
17974 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17975 MVT VT = Op.getSimpleValueType();
17977 assert(VT.is256BitVector() && VT.isInteger() &&
17978 "Unsupported value type for operation");
17980 unsigned NumElems = VT.getVectorNumElements();
17983 // Extract the LHS vectors
17984 SDValue LHS = Op.getOperand(0);
17985 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17986 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17988 // Extract the RHS vectors
17989 SDValue RHS = Op.getOperand(1);
17990 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17991 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17993 MVT EltVT = VT.getVectorElementType();
17994 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17996 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17997 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17998 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
18001 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
18002 assert(Op.getSimpleValueType().is256BitVector() &&
18003 Op.getSimpleValueType().isInteger() &&
18004 "Only handle AVX 256-bit vector integer operation");
18005 return Lower256IntArith(Op, DAG);
18008 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
18009 assert(Op.getSimpleValueType().is256BitVector() &&
18010 Op.getSimpleValueType().isInteger() &&
18011 "Only handle AVX 256-bit vector integer operation");
18012 return Lower256IntArith(Op, DAG);
18015 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
18016 SelectionDAG &DAG) {
18018 MVT VT = Op.getSimpleValueType();
18020 // Decompose 256-bit ops into smaller 128-bit ops.
18021 if (VT.is256BitVector() && !Subtarget->hasInt256())
18022 return Lower256IntArith(Op, DAG);
18024 SDValue A = Op.getOperand(0);
18025 SDValue B = Op.getOperand(1);
18027 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
18028 if (VT == MVT::v4i32) {
18029 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
18030 "Should not custom lower when pmuldq is available!");
18032 // Extract the odd parts.
18033 static const int UnpackMask[] = { 1, -1, 3, -1 };
18034 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
18035 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
18037 // Multiply the even parts.
18038 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
18039 // Now multiply odd parts.
18040 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
18042 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
18043 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
18045 // Merge the two vectors back together with a shuffle. This expands into 2
18047 static const int ShufMask[] = { 0, 4, 2, 6 };
18048 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
18051 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
18052 "Only know how to lower V2I64/V4I64/V8I64 multiply");
18054 // Ahi = psrlqi(a, 32);
18055 // Bhi = psrlqi(b, 32);
18057 // AloBlo = pmuludq(a, b);
18058 // AloBhi = pmuludq(a, Bhi);
18059 // AhiBlo = pmuludq(Ahi, b);
18061 // AloBhi = psllqi(AloBhi, 32);
18062 // AhiBlo = psllqi(AhiBlo, 32);
18063 // return AloBlo + AloBhi + AhiBlo;
18065 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
18066 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
18068 // Bit cast to 32-bit vectors for MULUDQ
18069 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
18070 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
18071 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
18072 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
18073 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
18074 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
18076 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
18077 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
18078 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
18080 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
18081 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
18083 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
18084 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
18087 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
18088 assert(Subtarget->isTargetWin64() && "Unexpected target");
18089 EVT VT = Op.getValueType();
18090 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
18091 "Unexpected return type for lowering");
18095 switch (Op->getOpcode()) {
18096 default: llvm_unreachable("Unexpected request for libcall!");
18097 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
18098 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
18099 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
18100 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
18101 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
18102 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
18106 SDValue InChain = DAG.getEntryNode();
18108 TargetLowering::ArgListTy Args;
18109 TargetLowering::ArgListEntry Entry;
18110 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
18111 EVT ArgVT = Op->getOperand(i).getValueType();
18112 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
18113 "Unexpected argument type for lowering");
18114 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
18115 Entry.Node = StackPtr;
18116 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
18118 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18119 Entry.Ty = PointerType::get(ArgTy,0);
18120 Entry.isSExt = false;
18121 Entry.isZExt = false;
18122 Args.push_back(Entry);
18125 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
18128 TargetLowering::CallLoweringInfo CLI(DAG);
18129 CLI.setDebugLoc(dl).setChain(InChain)
18130 .setCallee(getLibcallCallingConv(LC),
18131 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
18132 Callee, std::move(Args), 0)
18133 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
18135 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
18136 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
18139 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
18140 SelectionDAG &DAG) {
18141 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
18142 EVT VT = Op0.getValueType();
18145 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
18146 (VT == MVT::v8i32 && Subtarget->hasInt256()));
18148 // PMULxD operations multiply each even value (starting at 0) of LHS with
18149 // the related value of RHS and produce a widen result.
18150 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18151 // => <2 x i64> <ae|cg>
18153 // In other word, to have all the results, we need to perform two PMULxD:
18154 // 1. one with the even values.
18155 // 2. one with the odd values.
18156 // To achieve #2, with need to place the odd values at an even position.
18158 // Place the odd value at an even position (basically, shift all values 1
18159 // step to the left):
18160 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18161 // <a|b|c|d> => <b|undef|d|undef>
18162 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18163 // <e|f|g|h> => <f|undef|h|undef>
18164 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18166 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18168 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18169 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18171 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18172 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18173 // => <2 x i64> <ae|cg>
18174 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
18175 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18176 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18177 // => <2 x i64> <bf|dh>
18178 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
18179 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18181 // Shuffle it back into the right order.
18182 SDValue Highs, Lows;
18183 if (VT == MVT::v8i32) {
18184 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18185 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18186 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18187 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18189 const int HighMask[] = {1, 5, 3, 7};
18190 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18191 const int LowMask[] = {0, 4, 2, 6};
18192 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18195 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18196 // unsigned multiply.
18197 if (IsSigned && !Subtarget->hasSSE41()) {
18199 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
18200 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18201 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18202 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18203 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18205 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18206 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18209 // The first result of MUL_LOHI is actually the low value, followed by the
18211 SDValue Ops[] = {Lows, Highs};
18212 return DAG.getMergeValues(Ops, dl);
18215 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18216 const X86Subtarget *Subtarget) {
18217 MVT VT = Op.getSimpleValueType();
18219 SDValue R = Op.getOperand(0);
18220 SDValue Amt = Op.getOperand(1);
18222 // Optimize shl/srl/sra with constant shift amount.
18223 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18224 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18225 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18227 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
18228 (Subtarget->hasInt256() &&
18229 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18230 (Subtarget->hasAVX512() &&
18231 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18232 if (Op.getOpcode() == ISD::SHL)
18233 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18235 if (Op.getOpcode() == ISD::SRL)
18236 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18238 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
18239 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18243 if (VT == MVT::v16i8) {
18244 if (Op.getOpcode() == ISD::SHL) {
18245 // Make a large shift.
18246 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18247 MVT::v8i16, R, ShiftAmt,
18249 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18250 // Zero out the rightmost bits.
18251 SmallVector<SDValue, 16> V(16,
18252 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18254 return DAG.getNode(ISD::AND, dl, VT, SHL,
18255 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18257 if (Op.getOpcode() == ISD::SRL) {
18258 // Make a large shift.
18259 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18260 MVT::v8i16, R, ShiftAmt,
18262 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18263 // Zero out the leftmost bits.
18264 SmallVector<SDValue, 16> V(16,
18265 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18267 return DAG.getNode(ISD::AND, dl, VT, SRL,
18268 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18270 if (Op.getOpcode() == ISD::SRA) {
18271 if (ShiftAmt == 7) {
18272 // R s>> 7 === R s< 0
18273 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18274 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18277 // R s>> a === ((R u>> a) ^ m) - m
18278 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18279 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
18281 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18282 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18283 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18286 llvm_unreachable("Unknown shift opcode.");
18289 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
18290 if (Op.getOpcode() == ISD::SHL) {
18291 // Make a large shift.
18292 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18293 MVT::v16i16, R, ShiftAmt,
18295 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18296 // Zero out the rightmost bits.
18297 SmallVector<SDValue, 32> V(32,
18298 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18300 return DAG.getNode(ISD::AND, dl, VT, SHL,
18301 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18303 if (Op.getOpcode() == ISD::SRL) {
18304 // Make a large shift.
18305 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18306 MVT::v16i16, R, ShiftAmt,
18308 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18309 // Zero out the leftmost bits.
18310 SmallVector<SDValue, 32> V(32,
18311 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18313 return DAG.getNode(ISD::AND, dl, VT, SRL,
18314 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18316 if (Op.getOpcode() == ISD::SRA) {
18317 if (ShiftAmt == 7) {
18318 // R s>> 7 === R s< 0
18319 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18320 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18323 // R s>> a === ((R u>> a) ^ m) - m
18324 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18325 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
18327 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18328 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18329 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18332 llvm_unreachable("Unknown shift opcode.");
18337 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18338 if (!Subtarget->is64Bit() &&
18339 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18340 Amt.getOpcode() == ISD::BITCAST &&
18341 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18342 Amt = Amt.getOperand(0);
18343 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18344 VT.getVectorNumElements();
18345 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18346 uint64_t ShiftAmt = 0;
18347 for (unsigned i = 0; i != Ratio; ++i) {
18348 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
18352 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18354 // Check remaining shift amounts.
18355 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18356 uint64_t ShAmt = 0;
18357 for (unsigned j = 0; j != Ratio; ++j) {
18358 ConstantSDNode *C =
18359 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18363 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18365 if (ShAmt != ShiftAmt)
18368 switch (Op.getOpcode()) {
18370 llvm_unreachable("Unknown shift opcode!");
18372 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18375 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18378 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18386 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18387 const X86Subtarget* Subtarget) {
18388 MVT VT = Op.getSimpleValueType();
18390 SDValue R = Op.getOperand(0);
18391 SDValue Amt = Op.getOperand(1);
18393 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
18394 VT == MVT::v4i32 || VT == MVT::v8i16 ||
18395 (Subtarget->hasInt256() &&
18396 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
18397 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18398 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18400 EVT EltVT = VT.getVectorElementType();
18402 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18403 // Check if this build_vector node is doing a splat.
18404 // If so, then set BaseShAmt equal to the splat value.
18405 BaseShAmt = BV->getSplatValue();
18406 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18407 BaseShAmt = SDValue();
18409 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18410 Amt = Amt.getOperand(0);
18412 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18413 if (SVN && SVN->isSplat()) {
18414 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18415 SDValue InVec = Amt.getOperand(0);
18416 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18417 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
18418 "Unexpected shuffle index found!");
18419 BaseShAmt = InVec.getOperand(SplatIdx);
18420 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18421 if (ConstantSDNode *C =
18422 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18423 if (C->getZExtValue() == SplatIdx)
18424 BaseShAmt = InVec.getOperand(1);
18429 // Avoid introducing an extract element from a shuffle.
18430 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18431 DAG.getIntPtrConstant(SplatIdx));
18435 if (BaseShAmt.getNode()) {
18436 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18437 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18438 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18439 else if (EltVT.bitsLT(MVT::i32))
18440 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18442 switch (Op.getOpcode()) {
18444 llvm_unreachable("Unknown shift opcode!");
18446 switch (VT.SimpleTy) {
18447 default: return SDValue();
18456 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
18459 switch (VT.SimpleTy) {
18460 default: return SDValue();
18467 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
18470 switch (VT.SimpleTy) {
18471 default: return SDValue();
18480 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
18486 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18487 if (!Subtarget->is64Bit() &&
18488 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
18489 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
18490 Amt.getOpcode() == ISD::BITCAST &&
18491 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18492 Amt = Amt.getOperand(0);
18493 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18494 VT.getVectorNumElements();
18495 std::vector<SDValue> Vals(Ratio);
18496 for (unsigned i = 0; i != Ratio; ++i)
18497 Vals[i] = Amt.getOperand(i);
18498 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18499 for (unsigned j = 0; j != Ratio; ++j)
18500 if (Vals[j] != Amt.getOperand(i + j))
18503 switch (Op.getOpcode()) {
18505 llvm_unreachable("Unknown shift opcode!");
18507 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
18509 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
18511 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
18518 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18519 SelectionDAG &DAG) {
18520 MVT VT = Op.getSimpleValueType();
18522 SDValue R = Op.getOperand(0);
18523 SDValue Amt = Op.getOperand(1);
18526 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18527 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18529 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
18533 V = LowerScalarVariableShift(Op, DAG, Subtarget);
18537 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
18539 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
18540 if (Subtarget->hasInt256()) {
18541 if (Op.getOpcode() == ISD::SRL &&
18542 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18543 VT == MVT::v4i64 || VT == MVT::v8i32))
18545 if (Op.getOpcode() == ISD::SHL &&
18546 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18547 VT == MVT::v4i64 || VT == MVT::v8i32))
18549 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
18553 // If possible, lower this packed shift into a vector multiply instead of
18554 // expanding it into a sequence of scalar shifts.
18555 // Do this only if the vector shift count is a constant build_vector.
18556 if (Op.getOpcode() == ISD::SHL &&
18557 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18558 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18559 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18560 SmallVector<SDValue, 8> Elts;
18561 EVT SVT = VT.getScalarType();
18562 unsigned SVTBits = SVT.getSizeInBits();
18563 const APInt &One = APInt(SVTBits, 1);
18564 unsigned NumElems = VT.getVectorNumElements();
18566 for (unsigned i=0; i !=NumElems; ++i) {
18567 SDValue Op = Amt->getOperand(i);
18568 if (Op->getOpcode() == ISD::UNDEF) {
18569 Elts.push_back(Op);
18573 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18574 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18575 uint64_t ShAmt = C.getZExtValue();
18576 if (ShAmt >= SVTBits) {
18577 Elts.push_back(DAG.getUNDEF(SVT));
18580 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
18582 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18583 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18586 // Lower SHL with variable shift amount.
18587 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18588 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
18590 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
18591 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
18592 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18593 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18596 // If possible, lower this shift as a sequence of two shifts by
18597 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18599 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18601 // Could be rewritten as:
18602 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18604 // The advantage is that the two shifts from the example would be
18605 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18606 // the vector shift into four scalar shifts plus four pairs of vector
18608 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18609 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18610 unsigned TargetOpcode = X86ISD::MOVSS;
18611 bool CanBeSimplified;
18612 // The splat value for the first packed shift (the 'X' from the example).
18613 SDValue Amt1 = Amt->getOperand(0);
18614 // The splat value for the second packed shift (the 'Y' from the example).
18615 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18616 Amt->getOperand(2);
18618 // See if it is possible to replace this node with a sequence of
18619 // two shifts followed by a MOVSS/MOVSD
18620 if (VT == MVT::v4i32) {
18621 // Check if it is legal to use a MOVSS.
18622 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18623 Amt2 == Amt->getOperand(3);
18624 if (!CanBeSimplified) {
18625 // Otherwise, check if we can still simplify this node using a MOVSD.
18626 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18627 Amt->getOperand(2) == Amt->getOperand(3);
18628 TargetOpcode = X86ISD::MOVSD;
18629 Amt2 = Amt->getOperand(2);
18632 // Do similar checks for the case where the machine value type
18634 CanBeSimplified = Amt1 == Amt->getOperand(1);
18635 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18636 CanBeSimplified = Amt2 == Amt->getOperand(i);
18638 if (!CanBeSimplified) {
18639 TargetOpcode = X86ISD::MOVSD;
18640 CanBeSimplified = true;
18641 Amt2 = Amt->getOperand(4);
18642 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18643 CanBeSimplified = Amt1 == Amt->getOperand(i);
18644 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18645 CanBeSimplified = Amt2 == Amt->getOperand(j);
18649 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18650 isa<ConstantSDNode>(Amt2)) {
18651 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18652 EVT CastVT = MVT::v4i32;
18654 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
18655 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18657 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
18658 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18659 if (TargetOpcode == X86ISD::MOVSD)
18660 CastVT = MVT::v2i64;
18661 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
18662 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
18663 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18665 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
18669 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
18670 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
18673 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
18674 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
18676 // Turn 'a' into a mask suitable for VSELECT
18677 SDValue VSelM = DAG.getConstant(0x80, VT);
18678 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18679 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18681 SDValue CM1 = DAG.getConstant(0x0f, VT);
18682 SDValue CM2 = DAG.getConstant(0x3f, VT);
18684 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
18685 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
18686 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
18687 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18688 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18691 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18692 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18693 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18695 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
18696 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
18697 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
18698 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18699 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18702 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18703 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18704 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18706 // return VSELECT(r, r+r, a);
18707 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
18708 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
18712 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18713 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18714 // solution better.
18715 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18716 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
18718 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18719 R = DAG.getNode(ExtOpc, dl, NewVT, R);
18720 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
18721 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18722 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
18725 // Decompose 256-bit shifts into smaller 128-bit shifts.
18726 if (VT.is256BitVector()) {
18727 unsigned NumElems = VT.getVectorNumElements();
18728 MVT EltVT = VT.getVectorElementType();
18729 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18731 // Extract the two vectors
18732 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18733 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18735 // Recreate the shift amount vectors
18736 SDValue Amt1, Amt2;
18737 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18738 // Constant shift amount
18739 SmallVector<SDValue, 4> Amt1Csts;
18740 SmallVector<SDValue, 4> Amt2Csts;
18741 for (unsigned i = 0; i != NumElems/2; ++i)
18742 Amt1Csts.push_back(Amt->getOperand(i));
18743 for (unsigned i = NumElems/2; i != NumElems; ++i)
18744 Amt2Csts.push_back(Amt->getOperand(i));
18746 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18747 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18749 // Variable shift amount
18750 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18751 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18754 // Issue new vector shifts for the smaller types
18755 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18756 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18758 // Concatenate the result back
18759 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18765 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18766 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18767 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18768 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18769 // has only one use.
18770 SDNode *N = Op.getNode();
18771 SDValue LHS = N->getOperand(0);
18772 SDValue RHS = N->getOperand(1);
18773 unsigned BaseOp = 0;
18776 switch (Op.getOpcode()) {
18777 default: llvm_unreachable("Unknown ovf instruction!");
18779 // A subtract of one will be selected as a INC. Note that INC doesn't
18780 // set CF, so we can't do this for UADDO.
18781 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18783 BaseOp = X86ISD::INC;
18784 Cond = X86::COND_O;
18787 BaseOp = X86ISD::ADD;
18788 Cond = X86::COND_O;
18791 BaseOp = X86ISD::ADD;
18792 Cond = X86::COND_B;
18795 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18796 // set CF, so we can't do this for USUBO.
18797 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18799 BaseOp = X86ISD::DEC;
18800 Cond = X86::COND_O;
18803 BaseOp = X86ISD::SUB;
18804 Cond = X86::COND_O;
18807 BaseOp = X86ISD::SUB;
18808 Cond = X86::COND_B;
18811 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18812 Cond = X86::COND_O;
18814 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18815 if (N->getValueType(0) == MVT::i8) {
18816 BaseOp = X86ISD::UMUL8;
18817 Cond = X86::COND_O;
18820 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18822 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18825 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18826 DAG.getConstant(X86::COND_O, MVT::i32),
18827 SDValue(Sum.getNode(), 2));
18829 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18833 // Also sets EFLAGS.
18834 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18835 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18838 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18839 DAG.getConstant(Cond, MVT::i32),
18840 SDValue(Sum.getNode(), 1));
18842 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18845 // Sign extension of the low part of vector elements. This may be used either
18846 // when sign extend instructions are not available or if the vector element
18847 // sizes already match the sign-extended size. If the vector elements are in
18848 // their pre-extended size and sign extend instructions are available, that will
18849 // be handled by LowerSIGN_EXTEND.
18850 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18851 SelectionDAG &DAG) const {
18853 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18854 MVT VT = Op.getSimpleValueType();
18856 if (!Subtarget->hasSSE2() || !VT.isVector())
18859 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
18860 ExtraVT.getScalarType().getSizeInBits();
18862 switch (VT.SimpleTy) {
18863 default: return SDValue();
18866 if (!Subtarget->hasFp256())
18868 if (!Subtarget->hasInt256()) {
18869 // needs to be split
18870 unsigned NumElems = VT.getVectorNumElements();
18872 // Extract the LHS vectors
18873 SDValue LHS = Op.getOperand(0);
18874 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18875 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18877 MVT EltVT = VT.getVectorElementType();
18878 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18880 EVT ExtraEltVT = ExtraVT.getVectorElementType();
18881 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
18882 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
18884 SDValue Extra = DAG.getValueType(ExtraVT);
18886 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
18887 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
18889 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
18894 SDValue Op0 = Op.getOperand(0);
18896 // This is a sign extension of some low part of vector elements without
18897 // changing the size of the vector elements themselves:
18898 // Shift-Left + Shift-Right-Algebraic.
18899 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
18901 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
18907 /// Returns true if the operand type is exactly twice the native width, and
18908 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18909 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18910 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18911 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
18912 const X86Subtarget &Subtarget =
18913 getTargetMachine().getSubtarget<X86Subtarget>();
18914 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18917 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18918 else if (OpWidth == 128)
18919 return Subtarget.hasCmpxchg16b();
18924 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18925 return needsCmpXchgNb(SI->getValueOperand()->getType());
18928 // Note: this turns large loads into lock cmpxchg8b/16b.
18929 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18930 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18931 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18932 return needsCmpXchgNb(PTy->getElementType());
18935 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18936 const X86Subtarget &Subtarget =
18937 getTargetMachine().getSubtarget<X86Subtarget>();
18938 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18939 const Type *MemType = AI->getType();
18941 // If the operand is too big, we must see if cmpxchg8/16b is available
18942 // and default to library calls otherwise.
18943 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18944 return needsCmpXchgNb(MemType);
18946 AtomicRMWInst::BinOp Op = AI->getOperation();
18949 llvm_unreachable("Unknown atomic operation");
18950 case AtomicRMWInst::Xchg:
18951 case AtomicRMWInst::Add:
18952 case AtomicRMWInst::Sub:
18953 // It's better to use xadd, xsub or xchg for these in all cases.
18955 case AtomicRMWInst::Or:
18956 case AtomicRMWInst::And:
18957 case AtomicRMWInst::Xor:
18958 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18959 // prefix to a normal instruction for these operations.
18960 return !AI->use_empty();
18961 case AtomicRMWInst::Nand:
18962 case AtomicRMWInst::Max:
18963 case AtomicRMWInst::Min:
18964 case AtomicRMWInst::UMax:
18965 case AtomicRMWInst::UMin:
18966 // These always require a non-trivial set of data operations on x86. We must
18967 // use a cmpxchg loop.
18972 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18973 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18974 // no-sse2). There isn't any reason to disable it if the target processor
18976 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18980 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18981 const X86Subtarget &Subtarget =
18982 getTargetMachine().getSubtarget<X86Subtarget>();
18983 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18984 const Type *MemType = AI->getType();
18985 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18986 // there is no benefit in turning such RMWs into loads, and it is actually
18987 // harmful as it introduces a mfence.
18988 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18991 auto Builder = IRBuilder<>(AI);
18992 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18993 auto SynchScope = AI->getSynchScope();
18994 // We must restrict the ordering to avoid generating loads with Release or
18995 // ReleaseAcquire orderings.
18996 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18997 auto Ptr = AI->getPointerOperand();
18999 // Before the load we need a fence. Here is an example lifted from
19000 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
19003 // x.store(1, relaxed);
19004 // r1 = y.fetch_add(0, release);
19006 // y.fetch_add(42, acquire);
19007 // r2 = x.load(relaxed);
19008 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
19009 // lowered to just a load without a fence. A mfence flushes the store buffer,
19010 // making the optimization clearly correct.
19011 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
19012 // otherwise, we might be able to be more agressive on relaxed idempotent
19013 // rmw. In practice, they do not look useful, so we don't try to be
19014 // especially clever.
19015 if (SynchScope == SingleThread) {
19016 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19017 // the IR level, so we must wrap it in an intrinsic.
19019 } else if (hasMFENCE(Subtarget)) {
19020 Function *MFence = llvm::Intrinsic::getDeclaration(M,
19021 Intrinsic::x86_sse2_mfence);
19022 Builder.CreateCall(MFence);
19024 // FIXME: it might make sense to use a locked operation here but on a
19025 // different cache-line to prevent cache-line bouncing. In practice it
19026 // is probably a small win, and x86 processors without mfence are rare
19027 // enough that we do not bother.
19031 // Finally we can emit the atomic load.
19032 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19033 AI->getType()->getPrimitiveSizeInBits());
19034 Loaded->setAtomic(Order, SynchScope);
19035 AI->replaceAllUsesWith(Loaded);
19036 AI->eraseFromParent();
19040 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19041 SelectionDAG &DAG) {
19043 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19044 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19045 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19046 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19048 // The only fence that needs an instruction is a sequentially-consistent
19049 // cross-thread fence.
19050 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19051 if (hasMFENCE(*Subtarget))
19052 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19054 SDValue Chain = Op.getOperand(0);
19055 SDValue Zero = DAG.getConstant(0, MVT::i32);
19057 DAG.getRegister(X86::ESP, MVT::i32), // Base
19058 DAG.getTargetConstant(1, MVT::i8), // Scale
19059 DAG.getRegister(0, MVT::i32), // Index
19060 DAG.getTargetConstant(0, MVT::i32), // Disp
19061 DAG.getRegister(0, MVT::i32), // Segment.
19065 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19066 return SDValue(Res, 0);
19069 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19070 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19073 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19074 SelectionDAG &DAG) {
19075 MVT T = Op.getSimpleValueType();
19079 switch(T.SimpleTy) {
19080 default: llvm_unreachable("Invalid value type!");
19081 case MVT::i8: Reg = X86::AL; size = 1; break;
19082 case MVT::i16: Reg = X86::AX; size = 2; break;
19083 case MVT::i32: Reg = X86::EAX; size = 4; break;
19085 assert(Subtarget->is64Bit() && "Node not type legal!");
19086 Reg = X86::RAX; size = 8;
19089 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19090 Op.getOperand(2), SDValue());
19091 SDValue Ops[] = { cpIn.getValue(0),
19094 DAG.getTargetConstant(size, MVT::i8),
19095 cpIn.getValue(1) };
19096 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19097 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19098 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19102 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19103 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19104 MVT::i32, cpOut.getValue(2));
19105 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19106 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19108 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19109 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19110 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19114 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19115 SelectionDAG &DAG) {
19116 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19117 MVT DstVT = Op.getSimpleValueType();
19119 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19120 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19121 if (DstVT != MVT::f64)
19122 // This conversion needs to be expanded.
19125 SDValue InVec = Op->getOperand(0);
19127 unsigned NumElts = SrcVT.getVectorNumElements();
19128 EVT SVT = SrcVT.getVectorElementType();
19130 // Widen the vector in input in the case of MVT::v2i32.
19131 // Example: from MVT::v2i32 to MVT::v4i32.
19132 SmallVector<SDValue, 16> Elts;
19133 for (unsigned i = 0, e = NumElts; i != e; ++i)
19134 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19135 DAG.getIntPtrConstant(i)));
19137 // Explicitly mark the extra elements as Undef.
19138 SDValue Undef = DAG.getUNDEF(SVT);
19139 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
19140 Elts.push_back(Undef);
19142 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19143 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19144 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
19145 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19146 DAG.getIntPtrConstant(0));
19149 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19150 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19151 assert((DstVT == MVT::i64 ||
19152 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19153 "Unexpected custom BITCAST");
19154 // i64 <=> MMX conversions are Legal.
19155 if (SrcVT==MVT::i64 && DstVT.isVector())
19157 if (DstVT==MVT::i64 && SrcVT.isVector())
19159 // MMX <=> MMX conversions are Legal.
19160 if (SrcVT.isVector() && DstVT.isVector())
19162 // All other conversions need to be expanded.
19166 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19167 SDNode *Node = Op.getNode();
19169 EVT T = Node->getValueType(0);
19170 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19171 DAG.getConstant(0, T), Node->getOperand(2));
19172 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19173 cast<AtomicSDNode>(Node)->getMemoryVT(),
19174 Node->getOperand(0),
19175 Node->getOperand(1), negOp,
19176 cast<AtomicSDNode>(Node)->getMemOperand(),
19177 cast<AtomicSDNode>(Node)->getOrdering(),
19178 cast<AtomicSDNode>(Node)->getSynchScope());
19181 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19182 SDNode *Node = Op.getNode();
19184 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19186 // Convert seq_cst store -> xchg
19187 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19188 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19189 // (The only way to get a 16-byte store is cmpxchg16b)
19190 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19191 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19192 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19193 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19194 cast<AtomicSDNode>(Node)->getMemoryVT(),
19195 Node->getOperand(0),
19196 Node->getOperand(1), Node->getOperand(2),
19197 cast<AtomicSDNode>(Node)->getMemOperand(),
19198 cast<AtomicSDNode>(Node)->getOrdering(),
19199 cast<AtomicSDNode>(Node)->getSynchScope());
19200 return Swap.getValue(1);
19202 // Other atomic stores have a simple pattern.
19206 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19207 EVT VT = Op.getNode()->getSimpleValueType(0);
19209 // Let legalize expand this if it isn't a legal type yet.
19210 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19213 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19216 bool ExtraOp = false;
19217 switch (Op.getOpcode()) {
19218 default: llvm_unreachable("Invalid code");
19219 case ISD::ADDC: Opc = X86ISD::ADD; break;
19220 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19221 case ISD::SUBC: Opc = X86ISD::SUB; break;
19222 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19226 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19228 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19229 Op.getOperand(1), Op.getOperand(2));
19232 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19233 SelectionDAG &DAG) {
19234 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19236 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19237 // which returns the values as { float, float } (in XMM0) or
19238 // { double, double } (which is returned in XMM0, XMM1).
19240 SDValue Arg = Op.getOperand(0);
19241 EVT ArgVT = Arg.getValueType();
19242 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19244 TargetLowering::ArgListTy Args;
19245 TargetLowering::ArgListEntry Entry;
19249 Entry.isSExt = false;
19250 Entry.isZExt = false;
19251 Args.push_back(Entry);
19253 bool isF64 = ArgVT == MVT::f64;
19254 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19255 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19256 // the results are returned via SRet in memory.
19257 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19258 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19259 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
19261 Type *RetTy = isF64
19262 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19263 : (Type*)VectorType::get(ArgTy, 4);
19265 TargetLowering::CallLoweringInfo CLI(DAG);
19266 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19267 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19269 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19272 // Returned in xmm0 and xmm1.
19273 return CallResult.first;
19275 // Returned in bits 0:31 and 32:64 xmm0.
19276 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19277 CallResult.first, DAG.getIntPtrConstant(0));
19278 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19279 CallResult.first, DAG.getIntPtrConstant(1));
19280 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19281 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19284 /// LowerOperation - Provide custom lowering hooks for some operations.
19286 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19287 switch (Op.getOpcode()) {
19288 default: llvm_unreachable("Should not custom lower this!");
19289 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
19290 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19291 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19292 return LowerCMP_SWAP(Op, Subtarget, DAG);
19293 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19294 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19295 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19296 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
19297 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
19298 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19299 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19300 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19301 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19302 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19303 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19304 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19305 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19306 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19307 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19308 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19309 case ISD::SHL_PARTS:
19310 case ISD::SRA_PARTS:
19311 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19312 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19313 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19314 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19315 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19316 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19317 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19318 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19319 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19320 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19321 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19323 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19324 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19325 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19326 case ISD::SETCC: return LowerSETCC(Op, DAG);
19327 case ISD::SELECT: return LowerSELECT(Op, DAG);
19328 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19329 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19330 case ISD::VASTART: return LowerVASTART(Op, DAG);
19331 case ISD::VAARG: return LowerVAARG(Op, DAG);
19332 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19333 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19334 case ISD::INTRINSIC_VOID:
19335 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19336 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19337 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19338 case ISD::FRAME_TO_ARGS_OFFSET:
19339 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19340 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19341 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19342 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19343 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19344 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19345 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19346 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19347 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19348 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19349 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
19350 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19351 case ISD::UMUL_LOHI:
19352 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19355 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19361 case ISD::UMULO: return LowerXALUO(Op, DAG);
19362 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19363 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19367 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19368 case ISD::ADD: return LowerADD(Op, DAG);
19369 case ISD::SUB: return LowerSUB(Op, DAG);
19370 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19374 /// ReplaceNodeResults - Replace a node with an illegal result type
19375 /// with a new node built out of custom code.
19376 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19377 SmallVectorImpl<SDValue>&Results,
19378 SelectionDAG &DAG) const {
19380 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19381 switch (N->getOpcode()) {
19383 llvm_unreachable("Do not know how to custom type legalize this operation!");
19384 case ISD::SIGN_EXTEND_INREG:
19389 // We don't want to expand or promote these.
19396 case ISD::UDIVREM: {
19397 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19398 Results.push_back(V);
19401 case ISD::FP_TO_SINT:
19402 case ISD::FP_TO_UINT: {
19403 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19405 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
19408 std::pair<SDValue,SDValue> Vals =
19409 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19410 SDValue FIST = Vals.first, StackSlot = Vals.second;
19411 if (FIST.getNode()) {
19412 EVT VT = N->getValueType(0);
19413 // Return a load from the stack slot.
19414 if (StackSlot.getNode())
19415 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19416 MachinePointerInfo(),
19417 false, false, false, 0));
19419 Results.push_back(FIST);
19423 case ISD::UINT_TO_FP: {
19424 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19425 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19426 N->getValueType(0) != MVT::v2f32)
19428 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19430 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
19432 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19433 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19434 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
19435 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
19436 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19437 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19440 case ISD::FP_ROUND: {
19441 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19443 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19444 Results.push_back(V);
19447 case ISD::INTRINSIC_W_CHAIN: {
19448 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19450 default : llvm_unreachable("Do not know how to custom type "
19451 "legalize this intrinsic operation!");
19452 case Intrinsic::x86_rdtsc:
19453 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19455 case Intrinsic::x86_rdtscp:
19456 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19458 case Intrinsic::x86_rdpmc:
19459 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19462 case ISD::READCYCLECOUNTER: {
19463 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19466 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19467 EVT T = N->getValueType(0);
19468 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19469 bool Regs64bit = T == MVT::i128;
19470 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19471 SDValue cpInL, cpInH;
19472 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19473 DAG.getConstant(0, HalfT));
19474 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19475 DAG.getConstant(1, HalfT));
19476 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19477 Regs64bit ? X86::RAX : X86::EAX,
19479 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19480 Regs64bit ? X86::RDX : X86::EDX,
19481 cpInH, cpInL.getValue(1));
19482 SDValue swapInL, swapInH;
19483 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19484 DAG.getConstant(0, HalfT));
19485 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19486 DAG.getConstant(1, HalfT));
19487 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19488 Regs64bit ? X86::RBX : X86::EBX,
19489 swapInL, cpInH.getValue(1));
19490 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19491 Regs64bit ? X86::RCX : X86::ECX,
19492 swapInH, swapInL.getValue(1));
19493 SDValue Ops[] = { swapInH.getValue(0),
19495 swapInH.getValue(1) };
19496 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19497 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19498 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19499 X86ISD::LCMPXCHG8_DAG;
19500 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19501 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19502 Regs64bit ? X86::RAX : X86::EAX,
19503 HalfT, Result.getValue(1));
19504 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19505 Regs64bit ? X86::RDX : X86::EDX,
19506 HalfT, cpOutL.getValue(2));
19507 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19509 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19510 MVT::i32, cpOutH.getValue(2));
19512 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19513 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19514 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19516 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19517 Results.push_back(Success);
19518 Results.push_back(EFLAGS.getValue(1));
19521 case ISD::ATOMIC_SWAP:
19522 case ISD::ATOMIC_LOAD_ADD:
19523 case ISD::ATOMIC_LOAD_SUB:
19524 case ISD::ATOMIC_LOAD_AND:
19525 case ISD::ATOMIC_LOAD_OR:
19526 case ISD::ATOMIC_LOAD_XOR:
19527 case ISD::ATOMIC_LOAD_NAND:
19528 case ISD::ATOMIC_LOAD_MIN:
19529 case ISD::ATOMIC_LOAD_MAX:
19530 case ISD::ATOMIC_LOAD_UMIN:
19531 case ISD::ATOMIC_LOAD_UMAX:
19532 case ISD::ATOMIC_LOAD: {
19533 // Delegate to generic TypeLegalization. Situations we can really handle
19534 // should have already been dealt with by AtomicExpandPass.cpp.
19537 case ISD::BITCAST: {
19538 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19539 EVT DstVT = N->getValueType(0);
19540 EVT SrcVT = N->getOperand(0)->getValueType(0);
19542 if (SrcVT != MVT::f64 ||
19543 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19546 unsigned NumElts = DstVT.getVectorNumElements();
19547 EVT SVT = DstVT.getVectorElementType();
19548 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19549 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19550 MVT::v2f64, N->getOperand(0));
19551 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
19553 if (ExperimentalVectorWideningLegalization) {
19554 // If we are legalizing vectors by widening, we already have the desired
19555 // legal vector type, just return it.
19556 Results.push_back(ToVecInt);
19560 SmallVector<SDValue, 8> Elts;
19561 for (unsigned i = 0, e = NumElts; i != e; ++i)
19562 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19563 ToVecInt, DAG.getIntPtrConstant(i)));
19565 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19570 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19572 default: return nullptr;
19573 case X86ISD::BSF: return "X86ISD::BSF";
19574 case X86ISD::BSR: return "X86ISD::BSR";
19575 case X86ISD::SHLD: return "X86ISD::SHLD";
19576 case X86ISD::SHRD: return "X86ISD::SHRD";
19577 case X86ISD::FAND: return "X86ISD::FAND";
19578 case X86ISD::FANDN: return "X86ISD::FANDN";
19579 case X86ISD::FOR: return "X86ISD::FOR";
19580 case X86ISD::FXOR: return "X86ISD::FXOR";
19581 case X86ISD::FSRL: return "X86ISD::FSRL";
19582 case X86ISD::FILD: return "X86ISD::FILD";
19583 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19584 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19585 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19586 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19587 case X86ISD::FLD: return "X86ISD::FLD";
19588 case X86ISD::FST: return "X86ISD::FST";
19589 case X86ISD::CALL: return "X86ISD::CALL";
19590 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19591 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19592 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19593 case X86ISD::BT: return "X86ISD::BT";
19594 case X86ISD::CMP: return "X86ISD::CMP";
19595 case X86ISD::COMI: return "X86ISD::COMI";
19596 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19597 case X86ISD::CMPM: return "X86ISD::CMPM";
19598 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19599 case X86ISD::SETCC: return "X86ISD::SETCC";
19600 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19601 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19602 case X86ISD::CMOV: return "X86ISD::CMOV";
19603 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19604 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19605 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19606 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19607 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19608 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19609 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19610 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19611 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19612 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19613 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19614 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19615 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19616 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19617 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19618 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19619 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19620 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19621 case X86ISD::HADD: return "X86ISD::HADD";
19622 case X86ISD::HSUB: return "X86ISD::HSUB";
19623 case X86ISD::FHADD: return "X86ISD::FHADD";
19624 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19625 case X86ISD::UMAX: return "X86ISD::UMAX";
19626 case X86ISD::UMIN: return "X86ISD::UMIN";
19627 case X86ISD::SMAX: return "X86ISD::SMAX";
19628 case X86ISD::SMIN: return "X86ISD::SMIN";
19629 case X86ISD::FMAX: return "X86ISD::FMAX";
19630 case X86ISD::FMIN: return "X86ISD::FMIN";
19631 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19632 case X86ISD::FMINC: return "X86ISD::FMINC";
19633 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19634 case X86ISD::FRCP: return "X86ISD::FRCP";
19635 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19636 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19637 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19638 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19639 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19640 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19641 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19642 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19643 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19644 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19645 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19646 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19647 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19648 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19649 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19650 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19651 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19652 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
19653 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19654 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19655 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19656 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19657 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19658 case X86ISD::VSHL: return "X86ISD::VSHL";
19659 case X86ISD::VSRL: return "X86ISD::VSRL";
19660 case X86ISD::VSRA: return "X86ISD::VSRA";
19661 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19662 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19663 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19664 case X86ISD::CMPP: return "X86ISD::CMPP";
19665 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19666 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19667 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19668 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19669 case X86ISD::ADD: return "X86ISD::ADD";
19670 case X86ISD::SUB: return "X86ISD::SUB";
19671 case X86ISD::ADC: return "X86ISD::ADC";
19672 case X86ISD::SBB: return "X86ISD::SBB";
19673 case X86ISD::SMUL: return "X86ISD::SMUL";
19674 case X86ISD::UMUL: return "X86ISD::UMUL";
19675 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19676 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19677 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19678 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19679 case X86ISD::INC: return "X86ISD::INC";
19680 case X86ISD::DEC: return "X86ISD::DEC";
19681 case X86ISD::OR: return "X86ISD::OR";
19682 case X86ISD::XOR: return "X86ISD::XOR";
19683 case X86ISD::AND: return "X86ISD::AND";
19684 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19685 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19686 case X86ISD::PTEST: return "X86ISD::PTEST";
19687 case X86ISD::TESTP: return "X86ISD::TESTP";
19688 case X86ISD::TESTM: return "X86ISD::TESTM";
19689 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19690 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19691 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19692 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19693 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19694 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19695 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19696 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19697 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19698 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19699 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19700 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19701 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19702 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19703 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19704 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19705 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19706 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19707 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19708 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19709 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19710 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19711 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19712 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
19713 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19714 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19715 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19716 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19717 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19718 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19719 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19720 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19721 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19722 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19723 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19724 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19725 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19726 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19727 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
19728 case X86ISD::SAHF: return "X86ISD::SAHF";
19729 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19730 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19731 case X86ISD::FMADD: return "X86ISD::FMADD";
19732 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19733 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19734 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19735 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19736 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19737 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19738 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19739 case X86ISD::XTEST: return "X86ISD::XTEST";
19740 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
19741 case X86ISD::EXPAND: return "X86ISD::EXPAND";
19745 // isLegalAddressingMode - Return true if the addressing mode represented
19746 // by AM is legal for this target, for a load/store of the specified type.
19747 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
19749 // X86 supports extremely general addressing modes.
19750 CodeModel::Model M = getTargetMachine().getCodeModel();
19751 Reloc::Model R = getTargetMachine().getRelocationModel();
19753 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19754 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19759 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19761 // If a reference to this global requires an extra load, we can't fold it.
19762 if (isGlobalStubReference(GVFlags))
19765 // If BaseGV requires a register for the PIC base, we cannot also have a
19766 // BaseReg specified.
19767 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19770 // If lower 4G is not available, then we must use rip-relative addressing.
19771 if ((M != CodeModel::Small || R != Reloc::Static) &&
19772 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19776 switch (AM.Scale) {
19782 // These scales always work.
19787 // These scales are formed with basereg+scalereg. Only accept if there is
19792 default: // Other stuff never works.
19799 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19800 unsigned Bits = Ty->getScalarSizeInBits();
19802 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19803 // particularly cheaper than those without.
19807 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19808 // variable shifts just as cheap as scalar ones.
19809 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19812 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19813 // fully general vector.
19817 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19818 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19820 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19821 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19822 return NumBits1 > NumBits2;
19825 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19826 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19829 if (!isTypeLegal(EVT::getEVT(Ty1)))
19832 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19834 // Assuming the caller doesn't have a zeroext or signext return parameter,
19835 // truncation all the way down to i1 is valid.
19839 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19840 return isInt<32>(Imm);
19843 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19844 // Can also use sub to handle negated immediates.
19845 return isInt<32>(Imm);
19848 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
19849 if (!VT1.isInteger() || !VT2.isInteger())
19851 unsigned NumBits1 = VT1.getSizeInBits();
19852 unsigned NumBits2 = VT2.getSizeInBits();
19853 return NumBits1 > NumBits2;
19856 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19857 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19858 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19861 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19862 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19863 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19866 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19867 EVT VT1 = Val.getValueType();
19868 if (isZExtFree(VT1, VT2))
19871 if (Val.getOpcode() != ISD::LOAD)
19874 if (!VT1.isSimple() || !VT1.isInteger() ||
19875 !VT2.isSimple() || !VT2.isInteger())
19878 switch (VT1.getSimpleVT().SimpleTy) {
19883 // X86 has 8, 16, and 32-bit zero-extending loads.
19891 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
19892 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
19895 VT = VT.getScalarType();
19897 if (!VT.isSimple())
19900 switch (VT.getSimpleVT().SimpleTy) {
19911 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
19912 // i16 instructions are longer (0x66 prefix) and potentially slower.
19913 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19916 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19917 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19918 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19919 /// are assumed to be legal.
19921 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19923 if (!VT.isSimple())
19926 MVT SVT = VT.getSimpleVT();
19928 // Very little shuffling can be done for 64-bit vectors right now.
19929 if (VT.getSizeInBits() == 64)
19932 // If this is a single-input shuffle with no 128 bit lane crossings we can
19933 // lower it into pshufb.
19934 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
19935 (SVT.is256BitVector() && Subtarget->hasInt256())) {
19936 bool isLegal = true;
19937 for (unsigned I = 0, E = M.size(); I != E; ++I) {
19938 if (M[I] >= (int)SVT.getVectorNumElements() ||
19939 ShuffleCrosses128bitLane(SVT, I, M[I])) {
19948 // FIXME: blends, shifts.
19949 return (SVT.getVectorNumElements() == 2 ||
19950 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
19951 isMOVLMask(M, SVT) ||
19952 isCommutedMOVLMask(M, SVT) ||
19953 isMOVHLPSMask(M, SVT) ||
19954 isSHUFPMask(M, SVT) ||
19955 isSHUFPMask(M, SVT, /* Commuted */ true) ||
19956 isPSHUFDMask(M, SVT) ||
19957 isPSHUFDMask(M, SVT, /* SecondOperand */ true) ||
19958 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
19959 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
19960 isPALIGNRMask(M, SVT, Subtarget) ||
19961 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
19962 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
19963 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19964 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19965 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()) ||
19966 (Subtarget->hasSSE41() && isINSERTPSMask(M, SVT)));
19970 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
19972 if (!VT.isSimple())
19975 MVT SVT = VT.getSimpleVT();
19976 unsigned NumElts = SVT.getVectorNumElements();
19977 // FIXME: This collection of masks seems suspect.
19980 if (NumElts == 4 && SVT.is128BitVector()) {
19981 return (isMOVLMask(Mask, SVT) ||
19982 isCommutedMOVLMask(Mask, SVT, true) ||
19983 isSHUFPMask(Mask, SVT) ||
19984 isSHUFPMask(Mask, SVT, /* Commuted */ true) ||
19985 isBlendMask(Mask, SVT, Subtarget->hasSSE41(),
19986 Subtarget->hasInt256()));
19991 //===----------------------------------------------------------------------===//
19992 // X86 Scheduler Hooks
19993 //===----------------------------------------------------------------------===//
19995 /// Utility function to emit xbegin specifying the start of an RTM region.
19996 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
19997 const TargetInstrInfo *TII) {
19998 DebugLoc DL = MI->getDebugLoc();
20000 const BasicBlock *BB = MBB->getBasicBlock();
20001 MachineFunction::iterator I = MBB;
20004 // For the v = xbegin(), we generate
20015 MachineBasicBlock *thisMBB = MBB;
20016 MachineFunction *MF = MBB->getParent();
20017 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20018 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20019 MF->insert(I, mainMBB);
20020 MF->insert(I, sinkMBB);
20022 // Transfer the remainder of BB and its successor edges to sinkMBB.
20023 sinkMBB->splice(sinkMBB->begin(), MBB,
20024 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20025 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20029 // # fallthrough to mainMBB
20030 // # abortion to sinkMBB
20031 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20032 thisMBB->addSuccessor(mainMBB);
20033 thisMBB->addSuccessor(sinkMBB);
20037 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20038 mainMBB->addSuccessor(sinkMBB);
20041 // EAX is live into the sinkMBB
20042 sinkMBB->addLiveIn(X86::EAX);
20043 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20044 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20047 MI->eraseFromParent();
20051 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20052 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20053 // in the .td file.
20054 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20055 const TargetInstrInfo *TII) {
20057 switch (MI->getOpcode()) {
20058 default: llvm_unreachable("illegal opcode!");
20059 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20060 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20061 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20062 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20063 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20064 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20065 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20066 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20069 DebugLoc dl = MI->getDebugLoc();
20070 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20072 unsigned NumArgs = MI->getNumOperands();
20073 for (unsigned i = 1; i < NumArgs; ++i) {
20074 MachineOperand &Op = MI->getOperand(i);
20075 if (!(Op.isReg() && Op.isImplicit()))
20076 MIB.addOperand(Op);
20078 if (MI->hasOneMemOperand())
20079 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20081 BuildMI(*BB, MI, dl,
20082 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20083 .addReg(X86::XMM0);
20085 MI->eraseFromParent();
20089 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20090 // defs in an instruction pattern
20091 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20092 const TargetInstrInfo *TII) {
20094 switch (MI->getOpcode()) {
20095 default: llvm_unreachable("illegal opcode!");
20096 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20097 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20098 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20099 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20100 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20101 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20102 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20103 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20106 DebugLoc dl = MI->getDebugLoc();
20107 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20109 unsigned NumArgs = MI->getNumOperands(); // remove the results
20110 for (unsigned i = 1; i < NumArgs; ++i) {
20111 MachineOperand &Op = MI->getOperand(i);
20112 if (!(Op.isReg() && Op.isImplicit()))
20113 MIB.addOperand(Op);
20115 if (MI->hasOneMemOperand())
20116 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20118 BuildMI(*BB, MI, dl,
20119 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20122 MI->eraseFromParent();
20126 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20127 const TargetInstrInfo *TII,
20128 const X86Subtarget* Subtarget) {
20129 DebugLoc dl = MI->getDebugLoc();
20131 // Address into RAX/EAX, other two args into ECX, EDX.
20132 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20133 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20134 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20135 for (int i = 0; i < X86::AddrNumOperands; ++i)
20136 MIB.addOperand(MI->getOperand(i));
20138 unsigned ValOps = X86::AddrNumOperands;
20139 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20140 .addReg(MI->getOperand(ValOps).getReg());
20141 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20142 .addReg(MI->getOperand(ValOps+1).getReg());
20144 // The instruction doesn't actually take any operands though.
20145 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20147 MI->eraseFromParent(); // The pseudo is gone now.
20151 MachineBasicBlock *
20152 X86TargetLowering::EmitVAARG64WithCustomInserter(
20154 MachineBasicBlock *MBB) const {
20155 // Emit va_arg instruction on X86-64.
20157 // Operands to this pseudo-instruction:
20158 // 0 ) Output : destination address (reg)
20159 // 1-5) Input : va_list address (addr, i64mem)
20160 // 6 ) ArgSize : Size (in bytes) of vararg type
20161 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20162 // 8 ) Align : Alignment of type
20163 // 9 ) EFLAGS (implicit-def)
20165 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20166 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
20168 unsigned DestReg = MI->getOperand(0).getReg();
20169 MachineOperand &Base = MI->getOperand(1);
20170 MachineOperand &Scale = MI->getOperand(2);
20171 MachineOperand &Index = MI->getOperand(3);
20172 MachineOperand &Disp = MI->getOperand(4);
20173 MachineOperand &Segment = MI->getOperand(5);
20174 unsigned ArgSize = MI->getOperand(6).getImm();
20175 unsigned ArgMode = MI->getOperand(7).getImm();
20176 unsigned Align = MI->getOperand(8).getImm();
20178 // Memory Reference
20179 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20180 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20181 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20183 // Machine Information
20184 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20185 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20186 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20187 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20188 DebugLoc DL = MI->getDebugLoc();
20190 // struct va_list {
20193 // i64 overflow_area (address)
20194 // i64 reg_save_area (address)
20196 // sizeof(va_list) = 24
20197 // alignment(va_list) = 8
20199 unsigned TotalNumIntRegs = 6;
20200 unsigned TotalNumXMMRegs = 8;
20201 bool UseGPOffset = (ArgMode == 1);
20202 bool UseFPOffset = (ArgMode == 2);
20203 unsigned MaxOffset = TotalNumIntRegs * 8 +
20204 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20206 /* Align ArgSize to a multiple of 8 */
20207 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20208 bool NeedsAlign = (Align > 8);
20210 MachineBasicBlock *thisMBB = MBB;
20211 MachineBasicBlock *overflowMBB;
20212 MachineBasicBlock *offsetMBB;
20213 MachineBasicBlock *endMBB;
20215 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20216 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20217 unsigned OffsetReg = 0;
20219 if (!UseGPOffset && !UseFPOffset) {
20220 // If we only pull from the overflow region, we don't create a branch.
20221 // We don't need to alter control flow.
20222 OffsetDestReg = 0; // unused
20223 OverflowDestReg = DestReg;
20225 offsetMBB = nullptr;
20226 overflowMBB = thisMBB;
20229 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20230 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20231 // If not, pull from overflow_area. (branch to overflowMBB)
20236 // offsetMBB overflowMBB
20241 // Registers for the PHI in endMBB
20242 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20243 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20245 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20246 MachineFunction *MF = MBB->getParent();
20247 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20248 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20249 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20251 MachineFunction::iterator MBBIter = MBB;
20254 // Insert the new basic blocks
20255 MF->insert(MBBIter, offsetMBB);
20256 MF->insert(MBBIter, overflowMBB);
20257 MF->insert(MBBIter, endMBB);
20259 // Transfer the remainder of MBB and its successor edges to endMBB.
20260 endMBB->splice(endMBB->begin(), thisMBB,
20261 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20262 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20264 // Make offsetMBB and overflowMBB successors of thisMBB
20265 thisMBB->addSuccessor(offsetMBB);
20266 thisMBB->addSuccessor(overflowMBB);
20268 // endMBB is a successor of both offsetMBB and overflowMBB
20269 offsetMBB->addSuccessor(endMBB);
20270 overflowMBB->addSuccessor(endMBB);
20272 // Load the offset value into a register
20273 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20274 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20278 .addDisp(Disp, UseFPOffset ? 4 : 0)
20279 .addOperand(Segment)
20280 .setMemRefs(MMOBegin, MMOEnd);
20282 // Check if there is enough room left to pull this argument.
20283 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20285 .addImm(MaxOffset + 8 - ArgSizeA8);
20287 // Branch to "overflowMBB" if offset >= max
20288 // Fall through to "offsetMBB" otherwise
20289 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20290 .addMBB(overflowMBB);
20293 // In offsetMBB, emit code to use the reg_save_area.
20295 assert(OffsetReg != 0);
20297 // Read the reg_save_area address.
20298 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20299 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20304 .addOperand(Segment)
20305 .setMemRefs(MMOBegin, MMOEnd);
20307 // Zero-extend the offset
20308 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20309 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20312 .addImm(X86::sub_32bit);
20314 // Add the offset to the reg_save_area to get the final address.
20315 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20316 .addReg(OffsetReg64)
20317 .addReg(RegSaveReg);
20319 // Compute the offset for the next argument
20320 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20321 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20323 .addImm(UseFPOffset ? 16 : 8);
20325 // Store it back into the va_list.
20326 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20330 .addDisp(Disp, UseFPOffset ? 4 : 0)
20331 .addOperand(Segment)
20332 .addReg(NextOffsetReg)
20333 .setMemRefs(MMOBegin, MMOEnd);
20336 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
20341 // Emit code to use overflow area
20344 // Load the overflow_area address into a register.
20345 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20346 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20351 .addOperand(Segment)
20352 .setMemRefs(MMOBegin, MMOEnd);
20354 // If we need to align it, do so. Otherwise, just copy the address
20355 // to OverflowDestReg.
20357 // Align the overflow address
20358 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20359 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20361 // aligned_addr = (addr + (align-1)) & ~(align-1)
20362 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20363 .addReg(OverflowAddrReg)
20366 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20368 .addImm(~(uint64_t)(Align-1));
20370 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20371 .addReg(OverflowAddrReg);
20374 // Compute the next overflow address after this argument.
20375 // (the overflow address should be kept 8-byte aligned)
20376 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20377 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20378 .addReg(OverflowDestReg)
20379 .addImm(ArgSizeA8);
20381 // Store the new overflow address.
20382 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20387 .addOperand(Segment)
20388 .addReg(NextAddrReg)
20389 .setMemRefs(MMOBegin, MMOEnd);
20391 // If we branched, emit the PHI to the front of endMBB.
20393 BuildMI(*endMBB, endMBB->begin(), DL,
20394 TII->get(X86::PHI), DestReg)
20395 .addReg(OffsetDestReg).addMBB(offsetMBB)
20396 .addReg(OverflowDestReg).addMBB(overflowMBB);
20399 // Erase the pseudo instruction
20400 MI->eraseFromParent();
20405 MachineBasicBlock *
20406 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20408 MachineBasicBlock *MBB) const {
20409 // Emit code to save XMM registers to the stack. The ABI says that the
20410 // number of registers to save is given in %al, so it's theoretically
20411 // possible to do an indirect jump trick to avoid saving all of them,
20412 // however this code takes a simpler approach and just executes all
20413 // of the stores if %al is non-zero. It's less code, and it's probably
20414 // easier on the hardware branch predictor, and stores aren't all that
20415 // expensive anyway.
20417 // Create the new basic blocks. One block contains all the XMM stores,
20418 // and one block is the final destination regardless of whether any
20419 // stores were performed.
20420 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20421 MachineFunction *F = MBB->getParent();
20422 MachineFunction::iterator MBBIter = MBB;
20424 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20425 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20426 F->insert(MBBIter, XMMSaveMBB);
20427 F->insert(MBBIter, EndMBB);
20429 // Transfer the remainder of MBB and its successor edges to EndMBB.
20430 EndMBB->splice(EndMBB->begin(), MBB,
20431 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20432 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20434 // The original block will now fall through to the XMM save block.
20435 MBB->addSuccessor(XMMSaveMBB);
20436 // The XMMSaveMBB will fall through to the end block.
20437 XMMSaveMBB->addSuccessor(EndMBB);
20439 // Now add the instructions.
20440 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20441 DebugLoc DL = MI->getDebugLoc();
20443 unsigned CountReg = MI->getOperand(0).getReg();
20444 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20445 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20447 if (!Subtarget->isTargetWin64()) {
20448 // If %al is 0, branch around the XMM save block.
20449 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20450 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
20451 MBB->addSuccessor(EndMBB);
20454 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20455 // that was just emitted, but clearly shouldn't be "saved".
20456 assert((MI->getNumOperands() <= 3 ||
20457 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20458 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20459 && "Expected last argument to be EFLAGS");
20460 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20461 // In the XMM save block, save all the XMM argument registers.
20462 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20463 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20464 MachineMemOperand *MMO =
20465 F->getMachineMemOperand(
20466 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
20467 MachineMemOperand::MOStore,
20468 /*Size=*/16, /*Align=*/16);
20469 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20470 .addFrameIndex(RegSaveFrameIndex)
20471 .addImm(/*Scale=*/1)
20472 .addReg(/*IndexReg=*/0)
20473 .addImm(/*Disp=*/Offset)
20474 .addReg(/*Segment=*/0)
20475 .addReg(MI->getOperand(i).getReg())
20476 .addMemOperand(MMO);
20479 MI->eraseFromParent(); // The pseudo instruction is gone now.
20484 // The EFLAGS operand of SelectItr might be missing a kill marker
20485 // because there were multiple uses of EFLAGS, and ISel didn't know
20486 // which to mark. Figure out whether SelectItr should have had a
20487 // kill marker, and set it if it should. Returns the correct kill
20489 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20490 MachineBasicBlock* BB,
20491 const TargetRegisterInfo* TRI) {
20492 // Scan forward through BB for a use/def of EFLAGS.
20493 MachineBasicBlock::iterator miI(std::next(SelectItr));
20494 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20495 const MachineInstr& mi = *miI;
20496 if (mi.readsRegister(X86::EFLAGS))
20498 if (mi.definesRegister(X86::EFLAGS))
20499 break; // Should have kill-flag - update below.
20502 // If we hit the end of the block, check whether EFLAGS is live into a
20504 if (miI == BB->end()) {
20505 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20506 sEnd = BB->succ_end();
20507 sItr != sEnd; ++sItr) {
20508 MachineBasicBlock* succ = *sItr;
20509 if (succ->isLiveIn(X86::EFLAGS))
20514 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20515 // out. SelectMI should have a kill flag on EFLAGS.
20516 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20520 MachineBasicBlock *
20521 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20522 MachineBasicBlock *BB) const {
20523 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20524 DebugLoc DL = MI->getDebugLoc();
20526 // To "insert" a SELECT_CC instruction, we actually have to insert the
20527 // diamond control-flow pattern. The incoming instruction knows the
20528 // destination vreg to set, the condition code register to branch on, the
20529 // true/false values to select between, and a branch opcode to use.
20530 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20531 MachineFunction::iterator It = BB;
20537 // cmpTY ccX, r1, r2
20539 // fallthrough --> copy0MBB
20540 MachineBasicBlock *thisMBB = BB;
20541 MachineFunction *F = BB->getParent();
20542 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20543 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20544 F->insert(It, copy0MBB);
20545 F->insert(It, sinkMBB);
20547 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20548 // live into the sink and copy blocks.
20549 const TargetRegisterInfo *TRI =
20550 BB->getParent()->getSubtarget().getRegisterInfo();
20551 if (!MI->killsRegister(X86::EFLAGS) &&
20552 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
20553 copy0MBB->addLiveIn(X86::EFLAGS);
20554 sinkMBB->addLiveIn(X86::EFLAGS);
20557 // Transfer the remainder of BB and its successor edges to sinkMBB.
20558 sinkMBB->splice(sinkMBB->begin(), BB,
20559 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20560 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20562 // Add the true and fallthrough blocks as its successors.
20563 BB->addSuccessor(copy0MBB);
20564 BB->addSuccessor(sinkMBB);
20566 // Create the conditional branch instruction.
20568 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
20569 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20572 // %FalseValue = ...
20573 // # fallthrough to sinkMBB
20574 copy0MBB->addSuccessor(sinkMBB);
20577 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20579 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20580 TII->get(X86::PHI), MI->getOperand(0).getReg())
20581 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
20582 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
20584 MI->eraseFromParent(); // The pseudo instruction is gone now.
20588 MachineBasicBlock *
20589 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20590 MachineBasicBlock *BB) const {
20591 MachineFunction *MF = BB->getParent();
20592 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20593 DebugLoc DL = MI->getDebugLoc();
20594 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20596 assert(MF->shouldSplitStack());
20598 const bool Is64Bit = Subtarget->is64Bit();
20599 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20601 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20602 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20605 // ... [Till the alloca]
20606 // If stacklet is not large enough, jump to mallocMBB
20609 // Allocate by subtracting from RSP
20610 // Jump to continueMBB
20613 // Allocate by call to runtime
20617 // [rest of original BB]
20620 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20621 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20622 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20624 MachineRegisterInfo &MRI = MF->getRegInfo();
20625 const TargetRegisterClass *AddrRegClass =
20626 getRegClassFor(getPointerTy());
20628 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20629 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20630 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20631 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20632 sizeVReg = MI->getOperand(1).getReg(),
20633 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20635 MachineFunction::iterator MBBIter = BB;
20638 MF->insert(MBBIter, bumpMBB);
20639 MF->insert(MBBIter, mallocMBB);
20640 MF->insert(MBBIter, continueMBB);
20642 continueMBB->splice(continueMBB->begin(), BB,
20643 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20644 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20646 // Add code to the main basic block to check if the stack limit has been hit,
20647 // and if so, jump to mallocMBB otherwise to bumpMBB.
20648 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20649 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20650 .addReg(tmpSPVReg).addReg(sizeVReg);
20651 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20652 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20653 .addReg(SPLimitVReg);
20654 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
20656 // bumpMBB simply decreases the stack pointer, since we know the current
20657 // stacklet has enough space.
20658 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20659 .addReg(SPLimitVReg);
20660 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20661 .addReg(SPLimitVReg);
20662 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20664 // Calls into a routine in libgcc to allocate more space from the heap.
20665 const uint32_t *RegMask = MF->getTarget()
20666 .getSubtargetImpl()
20667 ->getRegisterInfo()
20668 ->getCallPreservedMask(CallingConv::C);
20670 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
20672 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20673 .addExternalSymbol("__morestack_allocate_stack_space")
20674 .addRegMask(RegMask)
20675 .addReg(X86::RDI, RegState::Implicit)
20676 .addReg(X86::RAX, RegState::ImplicitDefine);
20677 } else if (Is64Bit) {
20678 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20680 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20681 .addExternalSymbol("__morestack_allocate_stack_space")
20682 .addRegMask(RegMask)
20683 .addReg(X86::EDI, RegState::Implicit)
20684 .addReg(X86::EAX, RegState::ImplicitDefine);
20686 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20688 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
20689 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
20690 .addExternalSymbol("__morestack_allocate_stack_space")
20691 .addRegMask(RegMask)
20692 .addReg(X86::EAX, RegState::ImplicitDefine);
20696 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
20699 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
20700 .addReg(IsLP64 ? X86::RAX : X86::EAX);
20701 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20703 // Set up the CFG correctly.
20704 BB->addSuccessor(bumpMBB);
20705 BB->addSuccessor(mallocMBB);
20706 mallocMBB->addSuccessor(continueMBB);
20707 bumpMBB->addSuccessor(continueMBB);
20709 // Take care of the PHI nodes.
20710 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
20711 MI->getOperand(0).getReg())
20712 .addReg(mallocPtrVReg).addMBB(mallocMBB)
20713 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
20715 // Delete the original pseudo instruction.
20716 MI->eraseFromParent();
20719 return continueMBB;
20722 MachineBasicBlock *
20723 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
20724 MachineBasicBlock *BB) const {
20725 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20726 DebugLoc DL = MI->getDebugLoc();
20728 assert(!Subtarget->isTargetMachO());
20730 // The lowering is pretty easy: we're just emitting the call to _alloca. The
20731 // non-trivial part is impdef of ESP.
20733 if (Subtarget->isTargetWin64()) {
20734 if (Subtarget->isTargetCygMing()) {
20735 // ___chkstk(Mingw64):
20736 // Clobbers R10, R11, RAX and EFLAGS.
20738 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20739 .addExternalSymbol("___chkstk")
20740 .addReg(X86::RAX, RegState::Implicit)
20741 .addReg(X86::RSP, RegState::Implicit)
20742 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
20743 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
20744 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20746 // __chkstk(MSVCRT): does not update stack pointer.
20747 // Clobbers R10, R11 and EFLAGS.
20748 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20749 .addExternalSymbol("__chkstk")
20750 .addReg(X86::RAX, RegState::Implicit)
20751 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20752 // RAX has the offset to be subtracted from RSP.
20753 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
20758 const char *StackProbeSymbol = (Subtarget->isTargetKnownWindowsMSVC() ||
20759 Subtarget->isTargetWindowsItanium())
20763 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
20764 .addExternalSymbol(StackProbeSymbol)
20765 .addReg(X86::EAX, RegState::Implicit)
20766 .addReg(X86::ESP, RegState::Implicit)
20767 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
20768 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
20769 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20772 MI->eraseFromParent(); // The pseudo instruction is gone now.
20776 MachineBasicBlock *
20777 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20778 MachineBasicBlock *BB) const {
20779 // This is pretty easy. We're taking the value that we received from
20780 // our load from the relocation, sticking it in either RDI (x86-64)
20781 // or EAX and doing an indirect call. The return value will then
20782 // be in the normal return register.
20783 MachineFunction *F = BB->getParent();
20784 const X86InstrInfo *TII =
20785 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
20786 DebugLoc DL = MI->getDebugLoc();
20788 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
20789 assert(MI->getOperand(3).isGlobal() && "This should be a global");
20791 // Get a register mask for the lowered call.
20792 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
20793 // proper register mask.
20794 const uint32_t *RegMask = F->getTarget()
20795 .getSubtargetImpl()
20796 ->getRegisterInfo()
20797 ->getCallPreservedMask(CallingConv::C);
20798 if (Subtarget->is64Bit()) {
20799 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20800 TII->get(X86::MOV64rm), X86::RDI)
20802 .addImm(0).addReg(0)
20803 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20804 MI->getOperand(3).getTargetFlags())
20806 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
20807 addDirectMem(MIB, X86::RDI);
20808 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
20809 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
20810 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20811 TII->get(X86::MOV32rm), X86::EAX)
20813 .addImm(0).addReg(0)
20814 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20815 MI->getOperand(3).getTargetFlags())
20817 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20818 addDirectMem(MIB, X86::EAX);
20819 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20821 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20822 TII->get(X86::MOV32rm), X86::EAX)
20823 .addReg(TII->getGlobalBaseReg(F))
20824 .addImm(0).addReg(0)
20825 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20826 MI->getOperand(3).getTargetFlags())
20828 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20829 addDirectMem(MIB, X86::EAX);
20830 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20833 MI->eraseFromParent(); // The pseudo instruction is gone now.
20837 MachineBasicBlock *
20838 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
20839 MachineBasicBlock *MBB) const {
20840 DebugLoc DL = MI->getDebugLoc();
20841 MachineFunction *MF = MBB->getParent();
20842 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20843 MachineRegisterInfo &MRI = MF->getRegInfo();
20845 const BasicBlock *BB = MBB->getBasicBlock();
20846 MachineFunction::iterator I = MBB;
20849 // Memory Reference
20850 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20851 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20854 unsigned MemOpndSlot = 0;
20856 unsigned CurOp = 0;
20858 DstReg = MI->getOperand(CurOp++).getReg();
20859 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
20860 assert(RC->hasType(MVT::i32) && "Invalid destination!");
20861 unsigned mainDstReg = MRI.createVirtualRegister(RC);
20862 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
20864 MemOpndSlot = CurOp;
20866 MVT PVT = getPointerTy();
20867 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20868 "Invalid Pointer Size!");
20870 // For v = setjmp(buf), we generate
20873 // buf[LabelOffset] = restoreMBB
20874 // SjLjSetup restoreMBB
20880 // v = phi(main, restore)
20883 // if base pointer being used, load it from frame
20886 MachineBasicBlock *thisMBB = MBB;
20887 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20888 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20889 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
20890 MF->insert(I, mainMBB);
20891 MF->insert(I, sinkMBB);
20892 MF->push_back(restoreMBB);
20894 MachineInstrBuilder MIB;
20896 // Transfer the remainder of BB and its successor edges to sinkMBB.
20897 sinkMBB->splice(sinkMBB->begin(), MBB,
20898 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20899 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20902 unsigned PtrStoreOpc = 0;
20903 unsigned LabelReg = 0;
20904 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20905 Reloc::Model RM = MF->getTarget().getRelocationModel();
20906 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
20907 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
20909 // Prepare IP either in reg or imm.
20910 if (!UseImmLabel) {
20911 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
20912 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
20913 LabelReg = MRI.createVirtualRegister(PtrRC);
20914 if (Subtarget->is64Bit()) {
20915 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
20919 .addMBB(restoreMBB)
20922 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
20923 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
20924 .addReg(XII->getGlobalBaseReg(MF))
20927 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
20931 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
20933 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
20934 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20935 if (i == X86::AddrDisp)
20936 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
20938 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
20941 MIB.addReg(LabelReg);
20943 MIB.addMBB(restoreMBB);
20944 MIB.setMemRefs(MMOBegin, MMOEnd);
20946 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
20947 .addMBB(restoreMBB);
20949 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20950 MF->getSubtarget().getRegisterInfo());
20951 MIB.addRegMask(RegInfo->getNoPreservedMask());
20952 thisMBB->addSuccessor(mainMBB);
20953 thisMBB->addSuccessor(restoreMBB);
20957 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
20958 mainMBB->addSuccessor(sinkMBB);
20961 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20962 TII->get(X86::PHI), DstReg)
20963 .addReg(mainDstReg).addMBB(mainMBB)
20964 .addReg(restoreDstReg).addMBB(restoreMBB);
20967 if (RegInfo->hasBasePointer(*MF)) {
20968 const X86Subtarget &STI = MF->getTarget().getSubtarget<X86Subtarget>();
20969 const bool Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
20970 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
20971 X86FI->setRestoreBasePointer(MF);
20972 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
20973 unsigned BasePtr = RegInfo->getBaseRegister();
20974 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
20975 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
20976 FramePtr, true, X86FI->getRestoreBasePointerOffset())
20977 .setMIFlag(MachineInstr::FrameSetup);
20979 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
20980 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
20981 restoreMBB->addSuccessor(sinkMBB);
20983 MI->eraseFromParent();
20987 MachineBasicBlock *
20988 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
20989 MachineBasicBlock *MBB) const {
20990 DebugLoc DL = MI->getDebugLoc();
20991 MachineFunction *MF = MBB->getParent();
20992 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20993 MachineRegisterInfo &MRI = MF->getRegInfo();
20995 // Memory Reference
20996 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20997 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20999 MVT PVT = getPointerTy();
21000 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21001 "Invalid Pointer Size!");
21003 const TargetRegisterClass *RC =
21004 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21005 unsigned Tmp = MRI.createVirtualRegister(RC);
21006 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21007 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
21008 MF->getSubtarget().getRegisterInfo());
21009 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21010 unsigned SP = RegInfo->getStackRegister();
21012 MachineInstrBuilder MIB;
21014 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21015 const int64_t SPOffset = 2 * PVT.getStoreSize();
21017 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21018 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21021 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21022 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21023 MIB.addOperand(MI->getOperand(i));
21024 MIB.setMemRefs(MMOBegin, MMOEnd);
21026 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21027 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21028 if (i == X86::AddrDisp)
21029 MIB.addDisp(MI->getOperand(i), LabelOffset);
21031 MIB.addOperand(MI->getOperand(i));
21033 MIB.setMemRefs(MMOBegin, MMOEnd);
21035 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21036 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21037 if (i == X86::AddrDisp)
21038 MIB.addDisp(MI->getOperand(i), SPOffset);
21040 MIB.addOperand(MI->getOperand(i));
21042 MIB.setMemRefs(MMOBegin, MMOEnd);
21044 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21046 MI->eraseFromParent();
21050 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21051 // accumulator loops. Writing back to the accumulator allows the coalescer
21052 // to remove extra copies in the loop.
21053 MachineBasicBlock *
21054 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21055 MachineBasicBlock *MBB) const {
21056 MachineOperand &AddendOp = MI->getOperand(3);
21058 // Bail out early if the addend isn't a register - we can't switch these.
21059 if (!AddendOp.isReg())
21062 MachineFunction &MF = *MBB->getParent();
21063 MachineRegisterInfo &MRI = MF.getRegInfo();
21065 // Check whether the addend is defined by a PHI:
21066 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21067 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21068 if (!AddendDef.isPHI())
21071 // Look for the following pattern:
21073 // %addend = phi [%entry, 0], [%loop, %result]
21075 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21079 // %addend = phi [%entry, 0], [%loop, %result]
21081 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21083 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21084 assert(AddendDef.getOperand(i).isReg());
21085 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21086 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21087 if (&PHISrcInst == MI) {
21088 // Found a matching instruction.
21089 unsigned NewFMAOpc = 0;
21090 switch (MI->getOpcode()) {
21091 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21092 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21093 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21094 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21095 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21096 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21097 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21098 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21099 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21100 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21101 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21102 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21103 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21104 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21105 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21106 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21107 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21108 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21109 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21110 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21112 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21113 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21114 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21115 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21116 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21117 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21118 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21119 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21120 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21121 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21122 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21123 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21124 default: llvm_unreachable("Unrecognized FMA variant.");
21127 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
21128 MachineInstrBuilder MIB =
21129 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21130 .addOperand(MI->getOperand(0))
21131 .addOperand(MI->getOperand(3))
21132 .addOperand(MI->getOperand(2))
21133 .addOperand(MI->getOperand(1));
21134 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21135 MI->eraseFromParent();
21142 MachineBasicBlock *
21143 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21144 MachineBasicBlock *BB) const {
21145 switch (MI->getOpcode()) {
21146 default: llvm_unreachable("Unexpected instr type to insert");
21147 case X86::TAILJMPd64:
21148 case X86::TAILJMPr64:
21149 case X86::TAILJMPm64:
21150 llvm_unreachable("TAILJMP64 would not be touched here.");
21151 case X86::TCRETURNdi64:
21152 case X86::TCRETURNri64:
21153 case X86::TCRETURNmi64:
21155 case X86::WIN_ALLOCA:
21156 return EmitLoweredWinAlloca(MI, BB);
21157 case X86::SEG_ALLOCA_32:
21158 case X86::SEG_ALLOCA_64:
21159 return EmitLoweredSegAlloca(MI, BB);
21160 case X86::TLSCall_32:
21161 case X86::TLSCall_64:
21162 return EmitLoweredTLSCall(MI, BB);
21163 case X86::CMOV_GR8:
21164 case X86::CMOV_FR32:
21165 case X86::CMOV_FR64:
21166 case X86::CMOV_V4F32:
21167 case X86::CMOV_V2F64:
21168 case X86::CMOV_V2I64:
21169 case X86::CMOV_V8F32:
21170 case X86::CMOV_V4F64:
21171 case X86::CMOV_V4I64:
21172 case X86::CMOV_V16F32:
21173 case X86::CMOV_V8F64:
21174 case X86::CMOV_V8I64:
21175 case X86::CMOV_GR16:
21176 case X86::CMOV_GR32:
21177 case X86::CMOV_RFP32:
21178 case X86::CMOV_RFP64:
21179 case X86::CMOV_RFP80:
21180 return EmitLoweredSelect(MI, BB);
21182 case X86::FP32_TO_INT16_IN_MEM:
21183 case X86::FP32_TO_INT32_IN_MEM:
21184 case X86::FP32_TO_INT64_IN_MEM:
21185 case X86::FP64_TO_INT16_IN_MEM:
21186 case X86::FP64_TO_INT32_IN_MEM:
21187 case X86::FP64_TO_INT64_IN_MEM:
21188 case X86::FP80_TO_INT16_IN_MEM:
21189 case X86::FP80_TO_INT32_IN_MEM:
21190 case X86::FP80_TO_INT64_IN_MEM: {
21191 MachineFunction *F = BB->getParent();
21192 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
21193 DebugLoc DL = MI->getDebugLoc();
21195 // Change the floating point control register to use "round towards zero"
21196 // mode when truncating to an integer value.
21197 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21198 addFrameReference(BuildMI(*BB, MI, DL,
21199 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21201 // Load the old value of the high byte of the control word...
21203 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21204 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21207 // Set the high part to be round to zero...
21208 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21211 // Reload the modified control word now...
21212 addFrameReference(BuildMI(*BB, MI, DL,
21213 TII->get(X86::FLDCW16m)), CWFrameIdx);
21215 // Restore the memory image of control word to original value
21216 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21219 // Get the X86 opcode to use.
21221 switch (MI->getOpcode()) {
21222 default: llvm_unreachable("illegal opcode!");
21223 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21224 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21225 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21226 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21227 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21228 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21229 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21230 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21231 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21235 MachineOperand &Op = MI->getOperand(0);
21237 AM.BaseType = X86AddressMode::RegBase;
21238 AM.Base.Reg = Op.getReg();
21240 AM.BaseType = X86AddressMode::FrameIndexBase;
21241 AM.Base.FrameIndex = Op.getIndex();
21243 Op = MI->getOperand(1);
21245 AM.Scale = Op.getImm();
21246 Op = MI->getOperand(2);
21248 AM.IndexReg = Op.getImm();
21249 Op = MI->getOperand(3);
21250 if (Op.isGlobal()) {
21251 AM.GV = Op.getGlobal();
21253 AM.Disp = Op.getImm();
21255 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21256 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21258 // Reload the original control word now.
21259 addFrameReference(BuildMI(*BB, MI, DL,
21260 TII->get(X86::FLDCW16m)), CWFrameIdx);
21262 MI->eraseFromParent(); // The pseudo instruction is gone now.
21265 // String/text processing lowering.
21266 case X86::PCMPISTRM128REG:
21267 case X86::VPCMPISTRM128REG:
21268 case X86::PCMPISTRM128MEM:
21269 case X86::VPCMPISTRM128MEM:
21270 case X86::PCMPESTRM128REG:
21271 case X86::VPCMPESTRM128REG:
21272 case X86::PCMPESTRM128MEM:
21273 case X86::VPCMPESTRM128MEM:
21274 assert(Subtarget->hasSSE42() &&
21275 "Target must have SSE4.2 or AVX features enabled");
21276 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21278 // String/text processing lowering.
21279 case X86::PCMPISTRIREG:
21280 case X86::VPCMPISTRIREG:
21281 case X86::PCMPISTRIMEM:
21282 case X86::VPCMPISTRIMEM:
21283 case X86::PCMPESTRIREG:
21284 case X86::VPCMPESTRIREG:
21285 case X86::PCMPESTRIMEM:
21286 case X86::VPCMPESTRIMEM:
21287 assert(Subtarget->hasSSE42() &&
21288 "Target must have SSE4.2 or AVX features enabled");
21289 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21291 // Thread synchronization.
21293 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
21298 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21300 case X86::VASTART_SAVE_XMM_REGS:
21301 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21303 case X86::VAARG_64:
21304 return EmitVAARG64WithCustomInserter(MI, BB);
21306 case X86::EH_SjLj_SetJmp32:
21307 case X86::EH_SjLj_SetJmp64:
21308 return emitEHSjLjSetJmp(MI, BB);
21310 case X86::EH_SjLj_LongJmp32:
21311 case X86::EH_SjLj_LongJmp64:
21312 return emitEHSjLjLongJmp(MI, BB);
21314 case TargetOpcode::STATEPOINT:
21315 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21316 // this point in the process. We diverge later.
21317 return emitPatchPoint(MI, BB);
21319 case TargetOpcode::STACKMAP:
21320 case TargetOpcode::PATCHPOINT:
21321 return emitPatchPoint(MI, BB);
21323 case X86::VFMADDPDr213r:
21324 case X86::VFMADDPSr213r:
21325 case X86::VFMADDSDr213r:
21326 case X86::VFMADDSSr213r:
21327 case X86::VFMSUBPDr213r:
21328 case X86::VFMSUBPSr213r:
21329 case X86::VFMSUBSDr213r:
21330 case X86::VFMSUBSSr213r:
21331 case X86::VFNMADDPDr213r:
21332 case X86::VFNMADDPSr213r:
21333 case X86::VFNMADDSDr213r:
21334 case X86::VFNMADDSSr213r:
21335 case X86::VFNMSUBPDr213r:
21336 case X86::VFNMSUBPSr213r:
21337 case X86::VFNMSUBSDr213r:
21338 case X86::VFNMSUBSSr213r:
21339 case X86::VFMADDSUBPDr213r:
21340 case X86::VFMADDSUBPSr213r:
21341 case X86::VFMSUBADDPDr213r:
21342 case X86::VFMSUBADDPSr213r:
21343 case X86::VFMADDPDr213rY:
21344 case X86::VFMADDPSr213rY:
21345 case X86::VFMSUBPDr213rY:
21346 case X86::VFMSUBPSr213rY:
21347 case X86::VFNMADDPDr213rY:
21348 case X86::VFNMADDPSr213rY:
21349 case X86::VFNMSUBPDr213rY:
21350 case X86::VFNMSUBPSr213rY:
21351 case X86::VFMADDSUBPDr213rY:
21352 case X86::VFMADDSUBPSr213rY:
21353 case X86::VFMSUBADDPDr213rY:
21354 case X86::VFMSUBADDPSr213rY:
21355 return emitFMA3Instr(MI, BB);
21359 //===----------------------------------------------------------------------===//
21360 // X86 Optimization Hooks
21361 //===----------------------------------------------------------------------===//
21363 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21366 const SelectionDAG &DAG,
21367 unsigned Depth) const {
21368 unsigned BitWidth = KnownZero.getBitWidth();
21369 unsigned Opc = Op.getOpcode();
21370 assert((Opc >= ISD::BUILTIN_OP_END ||
21371 Opc == ISD::INTRINSIC_WO_CHAIN ||
21372 Opc == ISD::INTRINSIC_W_CHAIN ||
21373 Opc == ISD::INTRINSIC_VOID) &&
21374 "Should use MaskedValueIsZero if you don't know whether Op"
21375 " is a target node!");
21377 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21391 // These nodes' second result is a boolean.
21392 if (Op.getResNo() == 0)
21395 case X86ISD::SETCC:
21396 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21398 case ISD::INTRINSIC_WO_CHAIN: {
21399 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21400 unsigned NumLoBits = 0;
21403 case Intrinsic::x86_sse_movmsk_ps:
21404 case Intrinsic::x86_avx_movmsk_ps_256:
21405 case Intrinsic::x86_sse2_movmsk_pd:
21406 case Intrinsic::x86_avx_movmsk_pd_256:
21407 case Intrinsic::x86_mmx_pmovmskb:
21408 case Intrinsic::x86_sse2_pmovmskb_128:
21409 case Intrinsic::x86_avx2_pmovmskb: {
21410 // High bits of movmskp{s|d}, pmovmskb are known zero.
21412 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21413 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21414 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21415 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21416 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21417 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21418 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21419 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21421 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21430 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21432 const SelectionDAG &,
21433 unsigned Depth) const {
21434 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21435 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21436 return Op.getValueType().getScalarType().getSizeInBits();
21442 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21443 /// node is a GlobalAddress + offset.
21444 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21445 const GlobalValue* &GA,
21446 int64_t &Offset) const {
21447 if (N->getOpcode() == X86ISD::Wrapper) {
21448 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21449 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21450 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21454 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21457 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21458 /// same as extracting the high 128-bit part of 256-bit vector and then
21459 /// inserting the result into the low part of a new 256-bit vector
21460 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21461 EVT VT = SVOp->getValueType(0);
21462 unsigned NumElems = VT.getVectorNumElements();
21464 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21465 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21466 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21467 SVOp->getMaskElt(j) >= 0)
21473 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21474 /// same as extracting the low 128-bit part of 256-bit vector and then
21475 /// inserting the result into the high part of a new 256-bit vector
21476 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21477 EVT VT = SVOp->getValueType(0);
21478 unsigned NumElems = VT.getVectorNumElements();
21480 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21481 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21482 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21483 SVOp->getMaskElt(j) >= 0)
21489 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21490 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21491 TargetLowering::DAGCombinerInfo &DCI,
21492 const X86Subtarget* Subtarget) {
21494 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21495 SDValue V1 = SVOp->getOperand(0);
21496 SDValue V2 = SVOp->getOperand(1);
21497 EVT VT = SVOp->getValueType(0);
21498 unsigned NumElems = VT.getVectorNumElements();
21500 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21501 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21505 // V UNDEF BUILD_VECTOR UNDEF
21507 // CONCAT_VECTOR CONCAT_VECTOR
21510 // RESULT: V + zero extended
21512 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21513 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21514 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21517 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21520 // To match the shuffle mask, the first half of the mask should
21521 // be exactly the first vector, and all the rest a splat with the
21522 // first element of the second one.
21523 for (unsigned i = 0; i != NumElems/2; ++i)
21524 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21525 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21528 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21529 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21530 if (Ld->hasNUsesOfValue(1, 0)) {
21531 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21532 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21534 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21536 Ld->getPointerInfo(),
21537 Ld->getAlignment(),
21538 false/*isVolatile*/, true/*ReadMem*/,
21539 false/*WriteMem*/);
21541 // Make sure the newly-created LOAD is in the same position as Ld in
21542 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21543 // and update uses of Ld's output chain to use the TokenFactor.
21544 if (Ld->hasAnyUseOfValue(1)) {
21545 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21546 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21547 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21548 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21549 SDValue(ResNode.getNode(), 1));
21552 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
21556 // Emit a zeroed vector and insert the desired subvector on its
21558 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21559 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21560 return DCI.CombineTo(N, InsV);
21563 //===--------------------------------------------------------------------===//
21564 // Combine some shuffles into subvector extracts and inserts:
21567 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21568 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21569 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21570 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21571 return DCI.CombineTo(N, InsV);
21574 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21575 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21576 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21577 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21578 return DCI.CombineTo(N, InsV);
21584 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21587 /// This is the leaf of the recursive combinine below. When we have found some
21588 /// chain of single-use x86 shuffle instructions and accumulated the combined
21589 /// shuffle mask represented by them, this will try to pattern match that mask
21590 /// into either a single instruction if there is a special purpose instruction
21591 /// for this operation, or into a PSHUFB instruction which is a fully general
21592 /// instruction but should only be used to replace chains over a certain depth.
21593 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21594 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21595 TargetLowering::DAGCombinerInfo &DCI,
21596 const X86Subtarget *Subtarget) {
21597 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21599 // Find the operand that enters the chain. Note that multiple uses are OK
21600 // here, we're not going to remove the operand we find.
21601 SDValue Input = Op.getOperand(0);
21602 while (Input.getOpcode() == ISD::BITCAST)
21603 Input = Input.getOperand(0);
21605 MVT VT = Input.getSimpleValueType();
21606 MVT RootVT = Root.getSimpleValueType();
21609 // Just remove no-op shuffle masks.
21610 if (Mask.size() == 1) {
21611 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
21616 // Use the float domain if the operand type is a floating point type.
21617 bool FloatDomain = VT.isFloatingPoint();
21619 // For floating point shuffles, we don't have free copies in the shuffle
21620 // instructions or the ability to load as part of the instruction, so
21621 // canonicalize their shuffles to UNPCK or MOV variants.
21623 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21624 // vectors because it can have a load folded into it that UNPCK cannot. This
21625 // doesn't preclude something switching to the shorter encoding post-RA.
21627 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
21628 bool Lo = Mask.equals(0, 0);
21631 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21632 // is no slower than UNPCKLPD but has the option to fold the input operand
21633 // into even an unaligned memory load.
21634 if (Lo && Subtarget->hasSSE3()) {
21635 Shuffle = X86ISD::MOVDDUP;
21636 ShuffleVT = MVT::v2f64;
21638 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21639 // than the UNPCK variants.
21640 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21641 ShuffleVT = MVT::v4f32;
21643 if (Depth == 1 && Root->getOpcode() == Shuffle)
21644 return false; // Nothing to do!
21645 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21646 DCI.AddToWorklist(Op.getNode());
21647 if (Shuffle == X86ISD::MOVDDUP)
21648 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21650 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21651 DCI.AddToWorklist(Op.getNode());
21652 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21656 if (Subtarget->hasSSE3() &&
21657 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
21658 bool Lo = Mask.equals(0, 0, 2, 2);
21659 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21660 MVT ShuffleVT = MVT::v4f32;
21661 if (Depth == 1 && Root->getOpcode() == Shuffle)
21662 return false; // Nothing to do!
21663 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21664 DCI.AddToWorklist(Op.getNode());
21665 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21666 DCI.AddToWorklist(Op.getNode());
21667 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21671 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
21672 bool Lo = Mask.equals(0, 0, 1, 1);
21673 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21674 MVT ShuffleVT = MVT::v4f32;
21675 if (Depth == 1 && Root->getOpcode() == Shuffle)
21676 return false; // Nothing to do!
21677 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21678 DCI.AddToWorklist(Op.getNode());
21679 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21680 DCI.AddToWorklist(Op.getNode());
21681 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21687 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
21688 // variants as none of these have single-instruction variants that are
21689 // superior to the UNPCK formulation.
21690 if (!FloatDomain &&
21691 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
21692 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
21693 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
21694 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
21696 bool Lo = Mask[0] == 0;
21697 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21698 if (Depth == 1 && Root->getOpcode() == Shuffle)
21699 return false; // Nothing to do!
21701 switch (Mask.size()) {
21703 ShuffleVT = MVT::v8i16;
21706 ShuffleVT = MVT::v16i8;
21709 llvm_unreachable("Impossible mask size!");
21711 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21712 DCI.AddToWorklist(Op.getNode());
21713 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21714 DCI.AddToWorklist(Op.getNode());
21715 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21720 // Don't try to re-form single instruction chains under any circumstances now
21721 // that we've done encoding canonicalization for them.
21725 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
21726 // can replace them with a single PSHUFB instruction profitably. Intel's
21727 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
21728 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
21729 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
21730 SmallVector<SDValue, 16> PSHUFBMask;
21731 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
21732 int Ratio = 16 / Mask.size();
21733 for (unsigned i = 0; i < 16; ++i) {
21734 if (Mask[i / Ratio] == SM_SentinelUndef) {
21735 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
21738 int M = Mask[i / Ratio] != SM_SentinelZero
21739 ? Ratio * Mask[i / Ratio] + i % Ratio
21741 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
21743 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
21744 DCI.AddToWorklist(Op.getNode());
21745 SDValue PSHUFBMaskOp =
21746 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
21747 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
21748 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
21749 DCI.AddToWorklist(Op.getNode());
21750 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21755 // Failed to find any combines.
21759 /// \brief Fully generic combining of x86 shuffle instructions.
21761 /// This should be the last combine run over the x86 shuffle instructions. Once
21762 /// they have been fully optimized, this will recursively consider all chains
21763 /// of single-use shuffle instructions, build a generic model of the cumulative
21764 /// shuffle operation, and check for simpler instructions which implement this
21765 /// operation. We use this primarily for two purposes:
21767 /// 1) Collapse generic shuffles to specialized single instructions when
21768 /// equivalent. In most cases, this is just an encoding size win, but
21769 /// sometimes we will collapse multiple generic shuffles into a single
21770 /// special-purpose shuffle.
21771 /// 2) Look for sequences of shuffle instructions with 3 or more total
21772 /// instructions, and replace them with the slightly more expensive SSSE3
21773 /// PSHUFB instruction if available. We do this as the last combining step
21774 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
21775 /// a suitable short sequence of other instructions. The PHUFB will either
21776 /// use a register or have to read from memory and so is slightly (but only
21777 /// slightly) more expensive than the other shuffle instructions.
21779 /// Because this is inherently a quadratic operation (for each shuffle in
21780 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
21781 /// This should never be an issue in practice as the shuffle lowering doesn't
21782 /// produce sequences of more than 8 instructions.
21784 /// FIXME: We will currently miss some cases where the redundant shuffling
21785 /// would simplify under the threshold for PSHUFB formation because of
21786 /// combine-ordering. To fix this, we should do the redundant instruction
21787 /// combining in this recursive walk.
21788 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
21789 ArrayRef<int> RootMask,
21790 int Depth, bool HasPSHUFB,
21792 TargetLowering::DAGCombinerInfo &DCI,
21793 const X86Subtarget *Subtarget) {
21794 // Bound the depth of our recursive combine because this is ultimately
21795 // quadratic in nature.
21799 // Directly rip through bitcasts to find the underlying operand.
21800 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
21801 Op = Op.getOperand(0);
21803 MVT VT = Op.getSimpleValueType();
21804 if (!VT.isVector())
21805 return false; // Bail if we hit a non-vector.
21806 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
21807 // version should be added.
21808 if (VT.getSizeInBits() != 128)
21811 assert(Root.getSimpleValueType().isVector() &&
21812 "Shuffles operate on vector types!");
21813 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
21814 "Can only combine shuffles of the same vector register size.");
21816 if (!isTargetShuffle(Op.getOpcode()))
21818 SmallVector<int, 16> OpMask;
21820 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
21821 // We only can combine unary shuffles which we can decode the mask for.
21822 if (!HaveMask || !IsUnary)
21825 assert(VT.getVectorNumElements() == OpMask.size() &&
21826 "Different mask size from vector size!");
21827 assert(((RootMask.size() > OpMask.size() &&
21828 RootMask.size() % OpMask.size() == 0) ||
21829 (OpMask.size() > RootMask.size() &&
21830 OpMask.size() % RootMask.size() == 0) ||
21831 OpMask.size() == RootMask.size()) &&
21832 "The smaller number of elements must divide the larger.");
21833 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
21834 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
21835 assert(((RootRatio == 1 && OpRatio == 1) ||
21836 (RootRatio == 1) != (OpRatio == 1)) &&
21837 "Must not have a ratio for both incoming and op masks!");
21839 SmallVector<int, 16> Mask;
21840 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
21842 // Merge this shuffle operation's mask into our accumulated mask. Note that
21843 // this shuffle's mask will be the first applied to the input, followed by the
21844 // root mask to get us all the way to the root value arrangement. The reason
21845 // for this order is that we are recursing up the operation chain.
21846 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
21847 int RootIdx = i / RootRatio;
21848 if (RootMask[RootIdx] < 0) {
21849 // This is a zero or undef lane, we're done.
21850 Mask.push_back(RootMask[RootIdx]);
21854 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
21855 int OpIdx = RootMaskedIdx / OpRatio;
21856 if (OpMask[OpIdx] < 0) {
21857 // The incoming lanes are zero or undef, it doesn't matter which ones we
21859 Mask.push_back(OpMask[OpIdx]);
21863 // Ok, we have non-zero lanes, map them through.
21864 Mask.push_back(OpMask[OpIdx] * OpRatio +
21865 RootMaskedIdx % OpRatio);
21868 // See if we can recurse into the operand to combine more things.
21869 switch (Op.getOpcode()) {
21870 case X86ISD::PSHUFB:
21872 case X86ISD::PSHUFD:
21873 case X86ISD::PSHUFHW:
21874 case X86ISD::PSHUFLW:
21875 if (Op.getOperand(0).hasOneUse() &&
21876 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21877 HasPSHUFB, DAG, DCI, Subtarget))
21881 case X86ISD::UNPCKL:
21882 case X86ISD::UNPCKH:
21883 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
21884 // We can't check for single use, we have to check that this shuffle is the only user.
21885 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
21886 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21887 HasPSHUFB, DAG, DCI, Subtarget))
21892 // Minor canonicalization of the accumulated shuffle mask to make it easier
21893 // to match below. All this does is detect masks with squential pairs of
21894 // elements, and shrink them to the half-width mask. It does this in a loop
21895 // so it will reduce the size of the mask to the minimal width mask which
21896 // performs an equivalent shuffle.
21897 SmallVector<int, 16> WidenedMask;
21898 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
21899 Mask = std::move(WidenedMask);
21900 WidenedMask.clear();
21903 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
21907 /// \brief Get the PSHUF-style mask from PSHUF node.
21909 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
21910 /// PSHUF-style masks that can be reused with such instructions.
21911 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
21912 SmallVector<int, 4> Mask;
21914 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
21918 switch (N.getOpcode()) {
21919 case X86ISD::PSHUFD:
21921 case X86ISD::PSHUFLW:
21924 case X86ISD::PSHUFHW:
21925 Mask.erase(Mask.begin(), Mask.begin() + 4);
21926 for (int &M : Mask)
21930 llvm_unreachable("No valid shuffle instruction found!");
21934 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
21936 /// We walk up the chain and look for a combinable shuffle, skipping over
21937 /// shuffles that we could hoist this shuffle's transformation past without
21938 /// altering anything.
21940 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
21942 TargetLowering::DAGCombinerInfo &DCI) {
21943 assert(N.getOpcode() == X86ISD::PSHUFD &&
21944 "Called with something other than an x86 128-bit half shuffle!");
21947 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
21948 // of the shuffles in the chain so that we can form a fresh chain to replace
21950 SmallVector<SDValue, 8> Chain;
21951 SDValue V = N.getOperand(0);
21952 for (; V.hasOneUse(); V = V.getOperand(0)) {
21953 switch (V.getOpcode()) {
21955 return SDValue(); // Nothing combined!
21958 // Skip bitcasts as we always know the type for the target specific
21962 case X86ISD::PSHUFD:
21963 // Found another dword shuffle.
21966 case X86ISD::PSHUFLW:
21967 // Check that the low words (being shuffled) are the identity in the
21968 // dword shuffle, and the high words are self-contained.
21969 if (Mask[0] != 0 || Mask[1] != 1 ||
21970 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
21973 Chain.push_back(V);
21976 case X86ISD::PSHUFHW:
21977 // Check that the high words (being shuffled) are the identity in the
21978 // dword shuffle, and the low words are self-contained.
21979 if (Mask[2] != 2 || Mask[3] != 3 ||
21980 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
21983 Chain.push_back(V);
21986 case X86ISD::UNPCKL:
21987 case X86ISD::UNPCKH:
21988 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
21989 // shuffle into a preceding word shuffle.
21990 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
21993 // Search for a half-shuffle which we can combine with.
21994 unsigned CombineOp =
21995 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
21996 if (V.getOperand(0) != V.getOperand(1) ||
21997 !V->isOnlyUserOf(V.getOperand(0).getNode()))
21999 Chain.push_back(V);
22000 V = V.getOperand(0);
22002 switch (V.getOpcode()) {
22004 return SDValue(); // Nothing to combine.
22006 case X86ISD::PSHUFLW:
22007 case X86ISD::PSHUFHW:
22008 if (V.getOpcode() == CombineOp)
22011 Chain.push_back(V);
22015 V = V.getOperand(0);
22019 } while (V.hasOneUse());
22022 // Break out of the loop if we break out of the switch.
22026 if (!V.hasOneUse())
22027 // We fell out of the loop without finding a viable combining instruction.
22030 // Merge this node's mask and our incoming mask.
22031 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22032 for (int &M : Mask)
22034 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22035 getV4X86ShuffleImm8ForMask(Mask, DAG));
22037 // Rebuild the chain around this new shuffle.
22038 while (!Chain.empty()) {
22039 SDValue W = Chain.pop_back_val();
22041 if (V.getValueType() != W.getOperand(0).getValueType())
22042 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
22044 switch (W.getOpcode()) {
22046 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22048 case X86ISD::UNPCKL:
22049 case X86ISD::UNPCKH:
22050 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22053 case X86ISD::PSHUFD:
22054 case X86ISD::PSHUFLW:
22055 case X86ISD::PSHUFHW:
22056 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22060 if (V.getValueType() != N.getValueType())
22061 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
22063 // Return the new chain to replace N.
22067 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
22069 /// We walk up the chain, skipping shuffles of the other half and looking
22070 /// through shuffles which switch halves trying to find a shuffle of the same
22071 /// pair of dwords.
22072 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22074 TargetLowering::DAGCombinerInfo &DCI) {
22076 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22077 "Called with something other than an x86 128-bit half shuffle!");
22079 unsigned CombineOpcode = N.getOpcode();
22081 // Walk up a single-use chain looking for a combinable shuffle.
22082 SDValue V = N.getOperand(0);
22083 for (; V.hasOneUse(); V = V.getOperand(0)) {
22084 switch (V.getOpcode()) {
22086 return false; // Nothing combined!
22089 // Skip bitcasts as we always know the type for the target specific
22093 case X86ISD::PSHUFLW:
22094 case X86ISD::PSHUFHW:
22095 if (V.getOpcode() == CombineOpcode)
22098 // Other-half shuffles are no-ops.
22101 // Break out of the loop if we break out of the switch.
22105 if (!V.hasOneUse())
22106 // We fell out of the loop without finding a viable combining instruction.
22109 // Combine away the bottom node as its shuffle will be accumulated into
22110 // a preceding shuffle.
22111 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22113 // Record the old value.
22116 // Merge this node's mask and our incoming mask (adjusted to account for all
22117 // the pshufd instructions encountered).
22118 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22119 for (int &M : Mask)
22121 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22122 getV4X86ShuffleImm8ForMask(Mask, DAG));
22124 // Check that the shuffles didn't cancel each other out. If not, we need to
22125 // combine to the new one.
22127 // Replace the combinable shuffle with the combined one, updating all users
22128 // so that we re-evaluate the chain here.
22129 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22134 /// \brief Try to combine x86 target specific shuffles.
22135 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22136 TargetLowering::DAGCombinerInfo &DCI,
22137 const X86Subtarget *Subtarget) {
22139 MVT VT = N.getSimpleValueType();
22140 SmallVector<int, 4> Mask;
22142 switch (N.getOpcode()) {
22143 case X86ISD::PSHUFD:
22144 case X86ISD::PSHUFLW:
22145 case X86ISD::PSHUFHW:
22146 Mask = getPSHUFShuffleMask(N);
22147 assert(Mask.size() == 4);
22153 // Nuke no-op shuffles that show up after combining.
22154 if (isNoopShuffleMask(Mask))
22155 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22157 // Look for simplifications involving one or two shuffle instructions.
22158 SDValue V = N.getOperand(0);
22159 switch (N.getOpcode()) {
22162 case X86ISD::PSHUFLW:
22163 case X86ISD::PSHUFHW:
22164 assert(VT == MVT::v8i16);
22167 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22168 return SDValue(); // We combined away this shuffle, so we're done.
22170 // See if this reduces to a PSHUFD which is no more expensive and can
22171 // combine with more operations. Note that it has to at least flip the
22172 // dwords as otherwise it would have been removed as a no-op.
22173 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
22174 int DMask[] = {0, 1, 2, 3};
22175 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22176 DMask[DOffset + 0] = DOffset + 1;
22177 DMask[DOffset + 1] = DOffset + 0;
22178 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
22179 DCI.AddToWorklist(V.getNode());
22180 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
22181 getV4X86ShuffleImm8ForMask(DMask, DAG));
22182 DCI.AddToWorklist(V.getNode());
22183 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
22186 // Look for shuffle patterns which can be implemented as a single unpack.
22187 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22188 // only works when we have a PSHUFD followed by two half-shuffles.
22189 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22190 (V.getOpcode() == X86ISD::PSHUFLW ||
22191 V.getOpcode() == X86ISD::PSHUFHW) &&
22192 V.getOpcode() != N.getOpcode() &&
22194 SDValue D = V.getOperand(0);
22195 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22196 D = D.getOperand(0);
22197 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22198 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22199 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22200 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22201 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22203 for (int i = 0; i < 4; ++i) {
22204 WordMask[i + NOffset] = Mask[i] + NOffset;
22205 WordMask[i + VOffset] = VMask[i] + VOffset;
22207 // Map the word mask through the DWord mask.
22209 for (int i = 0; i < 8; ++i)
22210 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22211 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
22212 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
22213 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
22214 std::begin(UnpackLoMask)) ||
22215 std::equal(std::begin(MappedMask), std::end(MappedMask),
22216 std::begin(UnpackHiMask))) {
22217 // We can replace all three shuffles with an unpack.
22218 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
22219 DCI.AddToWorklist(V.getNode());
22220 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22222 DL, MVT::v8i16, V, V);
22229 case X86ISD::PSHUFD:
22230 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22239 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22241 /// We combine this directly on the abstract vector shuffle nodes so it is
22242 /// easier to generically match. We also insert dummy vector shuffle nodes for
22243 /// the operands which explicitly discard the lanes which are unused by this
22244 /// operation to try to flow through the rest of the combiner the fact that
22245 /// they're unused.
22246 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22248 EVT VT = N->getValueType(0);
22250 // We only handle target-independent shuffles.
22251 // FIXME: It would be easy and harmless to use the target shuffle mask
22252 // extraction tool to support more.
22253 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22256 auto *SVN = cast<ShuffleVectorSDNode>(N);
22257 ArrayRef<int> Mask = SVN->getMask();
22258 SDValue V1 = N->getOperand(0);
22259 SDValue V2 = N->getOperand(1);
22261 // We require the first shuffle operand to be the SUB node, and the second to
22262 // be the ADD node.
22263 // FIXME: We should support the commuted patterns.
22264 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22267 // If there are other uses of these operations we can't fold them.
22268 if (!V1->hasOneUse() || !V2->hasOneUse())
22271 // Ensure that both operations have the same operands. Note that we can
22272 // commute the FADD operands.
22273 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22274 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22275 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22278 // We're looking for blends between FADD and FSUB nodes. We insist on these
22279 // nodes being lined up in a specific expected pattern.
22280 if (!(isShuffleEquivalent(Mask, 0, 3) ||
22281 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
22282 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
22285 // Only specific types are legal at this point, assert so we notice if and
22286 // when these change.
22287 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22288 VT == MVT::v4f64) &&
22289 "Unknown vector type encountered!");
22291 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22294 /// PerformShuffleCombine - Performs several different shuffle combines.
22295 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22296 TargetLowering::DAGCombinerInfo &DCI,
22297 const X86Subtarget *Subtarget) {
22299 SDValue N0 = N->getOperand(0);
22300 SDValue N1 = N->getOperand(1);
22301 EVT VT = N->getValueType(0);
22303 // Don't create instructions with illegal types after legalize types has run.
22304 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22305 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22308 // If we have legalized the vector types, look for blends of FADD and FSUB
22309 // nodes that we can fuse into an ADDSUB node.
22310 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22311 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22314 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22315 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22316 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22317 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22319 // During Type Legalization, when promoting illegal vector types,
22320 // the backend might introduce new shuffle dag nodes and bitcasts.
22322 // This code performs the following transformation:
22323 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22324 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22326 // We do this only if both the bitcast and the BINOP dag nodes have
22327 // one use. Also, perform this transformation only if the new binary
22328 // operation is legal. This is to avoid introducing dag nodes that
22329 // potentially need to be further expanded (or custom lowered) into a
22330 // less optimal sequence of dag nodes.
22331 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22332 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22333 N0.getOpcode() == ISD::BITCAST) {
22334 SDValue BC0 = N0.getOperand(0);
22335 EVT SVT = BC0.getValueType();
22336 unsigned Opcode = BC0.getOpcode();
22337 unsigned NumElts = VT.getVectorNumElements();
22339 if (BC0.hasOneUse() && SVT.isVector() &&
22340 SVT.getVectorNumElements() * 2 == NumElts &&
22341 TLI.isOperationLegal(Opcode, VT)) {
22342 bool CanFold = false;
22354 unsigned SVTNumElts = SVT.getVectorNumElements();
22355 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22356 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22357 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22358 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22359 CanFold = SVOp->getMaskElt(i) < 0;
22362 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
22363 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
22364 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22365 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22370 // Only handle 128 wide vector from here on.
22371 if (!VT.is128BitVector())
22374 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22375 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22376 // consecutive, non-overlapping, and in the right order.
22377 SmallVector<SDValue, 16> Elts;
22378 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22379 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22381 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
22385 if (isTargetShuffle(N->getOpcode())) {
22387 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22388 if (Shuffle.getNode())
22391 // Try recursively combining arbitrary sequences of x86 shuffle
22392 // instructions into higher-order shuffles. We do this after combining
22393 // specific PSHUF instruction sequences into their minimal form so that we
22394 // can evaluate how many specialized shuffle instructions are involved in
22395 // a particular chain.
22396 SmallVector<int, 1> NonceMask; // Just a placeholder.
22397 NonceMask.push_back(0);
22398 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22399 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22401 return SDValue(); // This routine will use CombineTo to replace N.
22407 /// PerformTruncateCombine - Converts truncate operation to
22408 /// a sequence of vector shuffle operations.
22409 /// It is possible when we truncate 256-bit vector to 128-bit vector
22410 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
22411 TargetLowering::DAGCombinerInfo &DCI,
22412 const X86Subtarget *Subtarget) {
22416 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22417 /// specific shuffle of a load can be folded into a single element load.
22418 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22419 /// shuffles have been custom lowered so we need to handle those here.
22420 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22421 TargetLowering::DAGCombinerInfo &DCI) {
22422 if (DCI.isBeforeLegalizeOps())
22425 SDValue InVec = N->getOperand(0);
22426 SDValue EltNo = N->getOperand(1);
22428 if (!isa<ConstantSDNode>(EltNo))
22431 EVT OriginalVT = InVec.getValueType();
22433 if (InVec.getOpcode() == ISD::BITCAST) {
22434 // Don't duplicate a load with other uses.
22435 if (!InVec.hasOneUse())
22437 EVT BCVT = InVec.getOperand(0).getValueType();
22438 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22440 InVec = InVec.getOperand(0);
22443 EVT CurrentVT = InVec.getValueType();
22445 if (!isTargetShuffle(InVec.getOpcode()))
22448 // Don't duplicate a load with other uses.
22449 if (!InVec.hasOneUse())
22452 SmallVector<int, 16> ShuffleMask;
22454 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22455 ShuffleMask, UnaryShuffle))
22458 // Select the input vector, guarding against out of range extract vector.
22459 unsigned NumElems = CurrentVT.getVectorNumElements();
22460 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22461 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22462 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22463 : InVec.getOperand(1);
22465 // If inputs to shuffle are the same for both ops, then allow 2 uses
22466 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22468 if (LdNode.getOpcode() == ISD::BITCAST) {
22469 // Don't duplicate a load with other uses.
22470 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22473 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22474 LdNode = LdNode.getOperand(0);
22477 if (!ISD::isNormalLoad(LdNode.getNode()))
22480 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22482 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22485 EVT EltVT = N->getValueType(0);
22486 // If there's a bitcast before the shuffle, check if the load type and
22487 // alignment is valid.
22488 unsigned Align = LN0->getAlignment();
22489 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22490 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
22491 EltVT.getTypeForEVT(*DAG.getContext()));
22493 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22496 // All checks match so transform back to vector_shuffle so that DAG combiner
22497 // can finish the job
22500 // Create shuffle node taking into account the case that its a unary shuffle
22501 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22502 : InVec.getOperand(1);
22503 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22504 InVec.getOperand(0), Shuffle,
22506 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
22507 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22511 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22512 /// generation and convert it from being a bunch of shuffles and extracts
22513 /// into a somewhat faster sequence. For i686, the best sequence is apparently
22514 /// storing the value and loading scalars back, while for x64 we should
22515 /// use 64-bit extracts and shifts.
22516 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22517 TargetLowering::DAGCombinerInfo &DCI) {
22518 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
22519 if (NewOp.getNode())
22522 SDValue InputVector = N->getOperand(0);
22524 // Detect whether we are trying to convert from mmx to i32 and the bitcast
22525 // from mmx to v2i32 has a single usage.
22526 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
22527 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
22528 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
22529 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22530 N->getValueType(0),
22531 InputVector.getNode()->getOperand(0));
22533 // Only operate on vectors of 4 elements, where the alternative shuffling
22534 // gets to be more expensive.
22535 if (InputVector.getValueType() != MVT::v4i32)
22538 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22539 // single use which is a sign-extend or zero-extend, and all elements are
22541 SmallVector<SDNode *, 4> Uses;
22542 unsigned ExtractedElements = 0;
22543 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22544 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22545 if (UI.getUse().getResNo() != InputVector.getResNo())
22548 SDNode *Extract = *UI;
22549 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22552 if (Extract->getValueType(0) != MVT::i32)
22554 if (!Extract->hasOneUse())
22556 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22557 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22559 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22562 // Record which element was extracted.
22563 ExtractedElements |=
22564 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22566 Uses.push_back(Extract);
22569 // If not all the elements were used, this may not be worthwhile.
22570 if (ExtractedElements != 15)
22573 // Ok, we've now decided to do the transformation.
22574 // If 64-bit shifts are legal, use the extract-shift sequence,
22575 // otherwise bounce the vector off the cache.
22576 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22578 SDLoc dl(InputVector);
22580 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
22581 SDValue Cst = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, InputVector);
22582 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();
22583 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22584 DAG.getConstant(0, VecIdxTy));
22585 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22586 DAG.getConstant(1, VecIdxTy));
22588 SDValue ShAmt = DAG.getConstant(32,
22589 DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));
22590 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
22591 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22592 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
22593 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
22594 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22595 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
22597 // Store the value to a temporary stack slot.
22598 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22599 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22600 MachinePointerInfo(), false, false, 0);
22602 EVT ElementType = InputVector.getValueType().getVectorElementType();
22603 unsigned EltSize = ElementType.getSizeInBits() / 8;
22605 // Replace each use (extract) with a load of the appropriate element.
22606 for (unsigned i = 0; i < 4; ++i) {
22607 uint64_t Offset = EltSize * i;
22608 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
22610 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
22611 StackPtr, OffsetVal);
22613 // Load the scalar.
22614 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
22615 ScalarAddr, MachinePointerInfo(),
22616 false, false, false, 0);
22621 // Replace the extracts
22622 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22623 UE = Uses.end(); UI != UE; ++UI) {
22624 SDNode *Extract = *UI;
22626 SDValue Idx = Extract->getOperand(1);
22627 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
22628 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
22631 // The replacement was made in place; don't return anything.
22635 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
22636 static std::pair<unsigned, bool>
22637 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
22638 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
22639 if (!VT.isVector())
22640 return std::make_pair(0, false);
22642 bool NeedSplit = false;
22643 switch (VT.getSimpleVT().SimpleTy) {
22644 default: return std::make_pair(0, false);
22647 if (!Subtarget->hasVLX())
22648 return std::make_pair(0, false);
22652 if (!Subtarget->hasBWI())
22653 return std::make_pair(0, false);
22657 if (!Subtarget->hasAVX512())
22658 return std::make_pair(0, false);
22663 if (!Subtarget->hasAVX2())
22665 if (!Subtarget->hasAVX())
22666 return std::make_pair(0, false);
22671 if (!Subtarget->hasSSE2())
22672 return std::make_pair(0, false);
22675 // SSE2 has only a small subset of the operations.
22676 bool hasUnsigned = Subtarget->hasSSE41() ||
22677 (Subtarget->hasSSE2() && VT == MVT::v16i8);
22678 bool hasSigned = Subtarget->hasSSE41() ||
22679 (Subtarget->hasSSE2() && VT == MVT::v8i16);
22681 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22684 // Check for x CC y ? x : y.
22685 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22686 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22691 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22694 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22697 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22700 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22702 // Check for x CC y ? y : x -- a min/max with reversed arms.
22703 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22704 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22709 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22712 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22715 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22718 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22722 return std::make_pair(Opc, NeedSplit);
22726 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22727 const X86Subtarget *Subtarget) {
22729 SDValue Cond = N->getOperand(0);
22730 SDValue LHS = N->getOperand(1);
22731 SDValue RHS = N->getOperand(2);
22733 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22734 SDValue CondSrc = Cond->getOperand(0);
22735 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22736 Cond = CondSrc->getOperand(0);
22739 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
22742 // A vselect where all conditions and data are constants can be optimized into
22743 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
22744 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
22745 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
22748 unsigned MaskValue = 0;
22749 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22752 MVT VT = N->getSimpleValueType(0);
22753 unsigned NumElems = VT.getVectorNumElements();
22754 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22755 for (unsigned i = 0; i < NumElems; ++i) {
22756 // Be sure we emit undef where we can.
22757 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
22758 ShuffleMask[i] = -1;
22760 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
22763 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22764 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
22766 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
22769 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
22771 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
22772 TargetLowering::DAGCombinerInfo &DCI,
22773 const X86Subtarget *Subtarget) {
22775 SDValue Cond = N->getOperand(0);
22776 // Get the LHS/RHS of the select.
22777 SDValue LHS = N->getOperand(1);
22778 SDValue RHS = N->getOperand(2);
22779 EVT VT = LHS.getValueType();
22780 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22782 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
22783 // instructions match the semantics of the common C idiom x<y?x:y but not
22784 // x<=y?x:y, because of how they handle negative zero (which can be
22785 // ignored in unsafe-math mode).
22786 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
22787 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
22788 (Subtarget->hasSSE2() ||
22789 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
22790 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22792 unsigned Opcode = 0;
22793 // Check for x CC y ? x : y.
22794 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22795 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22799 // Converting this to a min would handle NaNs incorrectly, and swapping
22800 // the operands would cause it to handle comparisons between positive
22801 // and negative zero incorrectly.
22802 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22803 if (!DAG.getTarget().Options.UnsafeFPMath &&
22804 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22806 std::swap(LHS, RHS);
22808 Opcode = X86ISD::FMIN;
22811 // Converting this to a min would handle comparisons between positive
22812 // and negative zero incorrectly.
22813 if (!DAG.getTarget().Options.UnsafeFPMath &&
22814 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22816 Opcode = X86ISD::FMIN;
22819 // Converting this to a min would handle both negative zeros and NaNs
22820 // incorrectly, but we can swap the operands to fix both.
22821 std::swap(LHS, RHS);
22825 Opcode = X86ISD::FMIN;
22829 // Converting this to a max would handle comparisons between positive
22830 // and negative zero incorrectly.
22831 if (!DAG.getTarget().Options.UnsafeFPMath &&
22832 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22834 Opcode = X86ISD::FMAX;
22837 // Converting this to a max would handle NaNs incorrectly, and swapping
22838 // the operands would cause it to handle comparisons between positive
22839 // and negative zero incorrectly.
22840 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22841 if (!DAG.getTarget().Options.UnsafeFPMath &&
22842 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22844 std::swap(LHS, RHS);
22846 Opcode = X86ISD::FMAX;
22849 // Converting this to a max would handle both negative zeros and NaNs
22850 // incorrectly, but we can swap the operands to fix both.
22851 std::swap(LHS, RHS);
22855 Opcode = X86ISD::FMAX;
22858 // Check for x CC y ? y : x -- a min/max with reversed arms.
22859 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22860 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22864 // Converting this to a min would handle comparisons between positive
22865 // and negative zero incorrectly, and swapping the operands would
22866 // cause it to handle NaNs incorrectly.
22867 if (!DAG.getTarget().Options.UnsafeFPMath &&
22868 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
22869 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22871 std::swap(LHS, RHS);
22873 Opcode = X86ISD::FMIN;
22876 // Converting this to a min would handle NaNs incorrectly.
22877 if (!DAG.getTarget().Options.UnsafeFPMath &&
22878 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
22880 Opcode = X86ISD::FMIN;
22883 // Converting this to a min would handle both negative zeros and NaNs
22884 // incorrectly, but we can swap the operands to fix both.
22885 std::swap(LHS, RHS);
22889 Opcode = X86ISD::FMIN;
22893 // Converting this to a max would handle NaNs incorrectly.
22894 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22896 Opcode = X86ISD::FMAX;
22899 // Converting this to a max would handle comparisons between positive
22900 // and negative zero incorrectly, and swapping the operands would
22901 // cause it to handle NaNs incorrectly.
22902 if (!DAG.getTarget().Options.UnsafeFPMath &&
22903 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
22904 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22906 std::swap(LHS, RHS);
22908 Opcode = X86ISD::FMAX;
22911 // Converting this to a max would handle both negative zeros and NaNs
22912 // incorrectly, but we can swap the operands to fix both.
22913 std::swap(LHS, RHS);
22917 Opcode = X86ISD::FMAX;
22923 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
22926 EVT CondVT = Cond.getValueType();
22927 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
22928 CondVT.getVectorElementType() == MVT::i1) {
22929 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
22930 // lowering on KNL. In this case we convert it to
22931 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
22932 // The same situation for all 128 and 256-bit vectors of i8 and i16.
22933 // Since SKX these selects have a proper lowering.
22934 EVT OpVT = LHS.getValueType();
22935 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
22936 (OpVT.getVectorElementType() == MVT::i8 ||
22937 OpVT.getVectorElementType() == MVT::i16) &&
22938 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
22939 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
22940 DCI.AddToWorklist(Cond.getNode());
22941 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
22944 // If this is a select between two integer constants, try to do some
22946 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
22947 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
22948 // Don't do this for crazy integer types.
22949 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
22950 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
22951 // so that TrueC (the true value) is larger than FalseC.
22952 bool NeedsCondInvert = false;
22954 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
22955 // Efficiently invertible.
22956 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
22957 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
22958 isa<ConstantSDNode>(Cond.getOperand(1))))) {
22959 NeedsCondInvert = true;
22960 std::swap(TrueC, FalseC);
22963 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
22964 if (FalseC->getAPIntValue() == 0 &&
22965 TrueC->getAPIntValue().isPowerOf2()) {
22966 if (NeedsCondInvert) // Invert the condition if needed.
22967 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22968 DAG.getConstant(1, Cond.getValueType()));
22970 // Zero extend the condition if needed.
22971 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
22973 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22974 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
22975 DAG.getConstant(ShAmt, MVT::i8));
22978 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
22979 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22980 if (NeedsCondInvert) // Invert the condition if needed.
22981 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22982 DAG.getConstant(1, Cond.getValueType()));
22984 // Zero extend the condition if needed.
22985 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22986 FalseC->getValueType(0), Cond);
22987 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22988 SDValue(FalseC, 0));
22991 // Optimize cases that will turn into an LEA instruction. This requires
22992 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22993 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22994 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22995 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22997 bool isFastMultiplier = false;
22999 switch ((unsigned char)Diff) {
23001 case 1: // result = add base, cond
23002 case 2: // result = lea base( , cond*2)
23003 case 3: // result = lea base(cond, cond*2)
23004 case 4: // result = lea base( , cond*4)
23005 case 5: // result = lea base(cond, cond*4)
23006 case 8: // result = lea base( , cond*8)
23007 case 9: // result = lea base(cond, cond*8)
23008 isFastMultiplier = true;
23013 if (isFastMultiplier) {
23014 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23015 if (NeedsCondInvert) // Invert the condition if needed.
23016 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23017 DAG.getConstant(1, Cond.getValueType()));
23019 // Zero extend the condition if needed.
23020 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23022 // Scale the condition by the difference.
23024 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23025 DAG.getConstant(Diff, Cond.getValueType()));
23027 // Add the base if non-zero.
23028 if (FalseC->getAPIntValue() != 0)
23029 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23030 SDValue(FalseC, 0));
23037 // Canonicalize max and min:
23038 // (x > y) ? x : y -> (x >= y) ? x : y
23039 // (x < y) ? x : y -> (x <= y) ? x : y
23040 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23041 // the need for an extra compare
23042 // against zero. e.g.
23043 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23045 // testl %edi, %edi
23047 // cmovgl %edi, %eax
23051 // cmovsl %eax, %edi
23052 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23053 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23054 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23055 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23060 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23061 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23062 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23063 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23068 // Early exit check
23069 if (!TLI.isTypeLegal(VT))
23072 // Match VSELECTs into subs with unsigned saturation.
23073 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23074 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23075 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23076 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23077 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23079 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23080 // left side invert the predicate to simplify logic below.
23082 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23084 CC = ISD::getSetCCInverse(CC, true);
23085 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23089 if (Other.getNode() && Other->getNumOperands() == 2 &&
23090 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23091 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23092 SDValue CondRHS = Cond->getOperand(1);
23094 // Look for a general sub with unsigned saturation first.
23095 // x >= y ? x-y : 0 --> subus x, y
23096 // x > y ? x-y : 0 --> subus x, y
23097 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23098 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23099 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23101 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23102 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23103 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23104 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23105 // If the RHS is a constant we have to reverse the const
23106 // canonicalization.
23107 // x > C-1 ? x+-C : 0 --> subus x, C
23108 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23109 CondRHSConst->getAPIntValue() ==
23110 (-OpRHSConst->getAPIntValue() - 1))
23111 return DAG.getNode(
23112 X86ISD::SUBUS, DL, VT, OpLHS,
23113 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
23115 // Another special case: If C was a sign bit, the sub has been
23116 // canonicalized into a xor.
23117 // FIXME: Would it be better to use computeKnownBits to determine
23118 // whether it's safe to decanonicalize the xor?
23119 // x s< 0 ? x^C : 0 --> subus x, C
23120 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23121 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23122 OpRHSConst->getAPIntValue().isSignBit())
23123 // Note that we have to rebuild the RHS constant here to ensure we
23124 // don't rely on particular values of undef lanes.
23125 return DAG.getNode(
23126 X86ISD::SUBUS, DL, VT, OpLHS,
23127 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
23132 // Try to match a min/max vector operation.
23133 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
23134 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
23135 unsigned Opc = ret.first;
23136 bool NeedSplit = ret.second;
23138 if (Opc && NeedSplit) {
23139 unsigned NumElems = VT.getVectorNumElements();
23140 // Extract the LHS vectors
23141 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
23142 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
23144 // Extract the RHS vectors
23145 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
23146 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
23148 // Create min/max for each subvector
23149 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
23150 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
23152 // Merge the result
23153 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
23155 return DAG.getNode(Opc, DL, VT, LHS, RHS);
23158 // Simplify vector selection if condition value type matches vselect
23160 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23161 assert(Cond.getValueType().isVector() &&
23162 "vector select expects a vector selector!");
23164 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23165 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23167 // Try invert the condition if true value is not all 1s and false value
23169 if (!TValIsAllOnes && !FValIsAllZeros &&
23170 // Check if the selector will be produced by CMPP*/PCMP*
23171 Cond.getOpcode() == ISD::SETCC &&
23172 // Check if SETCC has already been promoted
23173 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
23174 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23175 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23177 if (TValIsAllZeros || FValIsAllOnes) {
23178 SDValue CC = Cond.getOperand(2);
23179 ISD::CondCode NewCC =
23180 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23181 Cond.getOperand(0).getValueType().isInteger());
23182 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23183 std::swap(LHS, RHS);
23184 TValIsAllOnes = FValIsAllOnes;
23185 FValIsAllZeros = TValIsAllZeros;
23189 if (TValIsAllOnes || FValIsAllZeros) {
23192 if (TValIsAllOnes && FValIsAllZeros)
23194 else if (TValIsAllOnes)
23195 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
23196 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
23197 else if (FValIsAllZeros)
23198 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23199 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
23201 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
23205 // If we know that this node is legal then we know that it is going to be
23206 // matched by one of the SSE/AVX BLEND instructions. These instructions only
23207 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
23208 // to simplify previous instructions.
23209 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23210 !DCI.isBeforeLegalize() &&
23211 // We explicitly check against v8i16 and v16i16 because, although
23212 // they're marked as Custom, they might only be legal when Cond is a
23213 // build_vector of constants. This will be taken care in a later
23215 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
23216 VT != MVT::v8i16) &&
23217 // Don't optimize vector of constants. Those are handled by
23218 // the generic code and all the bits must be properly set for
23219 // the generic optimizer.
23220 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23221 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23223 // Don't optimize vector selects that map to mask-registers.
23227 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23228 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23230 APInt KnownZero, KnownOne;
23231 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23232 DCI.isBeforeLegalizeOps());
23233 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23234 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23236 // If we changed the computation somewhere in the DAG, this change
23237 // will affect all users of Cond.
23238 // Make sure it is fine and update all the nodes so that we do not
23239 // use the generic VSELECT anymore. Otherwise, we may perform
23240 // wrong optimizations as we messed up with the actual expectation
23241 // for the vector boolean values.
23242 if (Cond != TLO.Old) {
23243 // Check all uses of that condition operand to check whether it will be
23244 // consumed by non-BLEND instructions, which may depend on all bits are
23246 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23248 if (I->getOpcode() != ISD::VSELECT)
23249 // TODO: Add other opcodes eventually lowered into BLEND.
23252 // Update all the users of the condition, before committing the change,
23253 // so that the VSELECT optimizations that expect the correct vector
23254 // boolean value will not be triggered.
23255 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23257 DAG.ReplaceAllUsesOfValueWith(
23259 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23260 Cond, I->getOperand(1), I->getOperand(2)));
23261 DCI.CommitTargetLoweringOpt(TLO);
23264 // At this point, only Cond is changed. Change the condition
23265 // just for N to keep the opportunity to optimize all other
23266 // users their own way.
23267 DAG.ReplaceAllUsesOfValueWith(
23269 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23270 TLO.New, N->getOperand(1), N->getOperand(2)));
23275 // We should generate an X86ISD::BLENDI from a vselect if its argument
23276 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23277 // constants. This specific pattern gets generated when we split a
23278 // selector for a 512 bit vector in a machine without AVX512 (but with
23279 // 256-bit vectors), during legalization:
23281 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23283 // Iff we find this pattern and the build_vectors are built from
23284 // constants, we translate the vselect into a shuffle_vector that we
23285 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23286 if ((N->getOpcode() == ISD::VSELECT ||
23287 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23288 !DCI.isBeforeLegalize()) {
23289 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23290 if (Shuffle.getNode())
23297 // Check whether a boolean test is testing a boolean value generated by
23298 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23301 // Simplify the following patterns:
23302 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23303 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23304 // to (Op EFLAGS Cond)
23306 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23307 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23308 // to (Op EFLAGS !Cond)
23310 // where Op could be BRCOND or CMOV.
23312 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23313 // Quit if not CMP and SUB with its value result used.
23314 if (Cmp.getOpcode() != X86ISD::CMP &&
23315 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23318 // Quit if not used as a boolean value.
23319 if (CC != X86::COND_E && CC != X86::COND_NE)
23322 // Check CMP operands. One of them should be 0 or 1 and the other should be
23323 // an SetCC or extended from it.
23324 SDValue Op1 = Cmp.getOperand(0);
23325 SDValue Op2 = Cmp.getOperand(1);
23328 const ConstantSDNode* C = nullptr;
23329 bool needOppositeCond = (CC == X86::COND_E);
23330 bool checkAgainstTrue = false; // Is it a comparison against 1?
23332 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23334 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23336 else // Quit if all operands are not constants.
23339 if (C->getZExtValue() == 1) {
23340 needOppositeCond = !needOppositeCond;
23341 checkAgainstTrue = true;
23342 } else if (C->getZExtValue() != 0)
23343 // Quit if the constant is neither 0 or 1.
23346 bool truncatedToBoolWithAnd = false;
23347 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23348 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23349 SetCC.getOpcode() == ISD::TRUNCATE ||
23350 SetCC.getOpcode() == ISD::AND) {
23351 if (SetCC.getOpcode() == ISD::AND) {
23353 ConstantSDNode *CS;
23354 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23355 CS->getZExtValue() == 1)
23357 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23358 CS->getZExtValue() == 1)
23362 SetCC = SetCC.getOperand(OpIdx);
23363 truncatedToBoolWithAnd = true;
23365 SetCC = SetCC.getOperand(0);
23368 switch (SetCC.getOpcode()) {
23369 case X86ISD::SETCC_CARRY:
23370 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23371 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23372 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23373 // truncated to i1 using 'and'.
23374 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23376 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23377 "Invalid use of SETCC_CARRY!");
23379 case X86ISD::SETCC:
23380 // Set the condition code or opposite one if necessary.
23381 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23382 if (needOppositeCond)
23383 CC = X86::GetOppositeBranchCondition(CC);
23384 return SetCC.getOperand(1);
23385 case X86ISD::CMOV: {
23386 // Check whether false/true value has canonical one, i.e. 0 or 1.
23387 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23388 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23389 // Quit if true value is not a constant.
23392 // Quit if false value is not a constant.
23394 SDValue Op = SetCC.getOperand(0);
23395 // Skip 'zext' or 'trunc' node.
23396 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23397 Op.getOpcode() == ISD::TRUNCATE)
23398 Op = Op.getOperand(0);
23399 // A special case for rdrand/rdseed, where 0 is set if false cond is
23401 if ((Op.getOpcode() != X86ISD::RDRAND &&
23402 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23405 // Quit if false value is not the constant 0 or 1.
23406 bool FValIsFalse = true;
23407 if (FVal && FVal->getZExtValue() != 0) {
23408 if (FVal->getZExtValue() != 1)
23410 // If FVal is 1, opposite cond is needed.
23411 needOppositeCond = !needOppositeCond;
23412 FValIsFalse = false;
23414 // Quit if TVal is not the constant opposite of FVal.
23415 if (FValIsFalse && TVal->getZExtValue() != 1)
23417 if (!FValIsFalse && TVal->getZExtValue() != 0)
23419 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23420 if (needOppositeCond)
23421 CC = X86::GetOppositeBranchCondition(CC);
23422 return SetCC.getOperand(3);
23429 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23430 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23431 TargetLowering::DAGCombinerInfo &DCI,
23432 const X86Subtarget *Subtarget) {
23435 // If the flag operand isn't dead, don't touch this CMOV.
23436 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23439 SDValue FalseOp = N->getOperand(0);
23440 SDValue TrueOp = N->getOperand(1);
23441 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23442 SDValue Cond = N->getOperand(3);
23444 if (CC == X86::COND_E || CC == X86::COND_NE) {
23445 switch (Cond.getOpcode()) {
23449 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23450 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23451 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23457 Flags = checkBoolTestSetCCCombine(Cond, CC);
23458 if (Flags.getNode() &&
23459 // Extra check as FCMOV only supports a subset of X86 cond.
23460 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23461 SDValue Ops[] = { FalseOp, TrueOp,
23462 DAG.getConstant(CC, MVT::i8), Flags };
23463 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23466 // If this is a select between two integer constants, try to do some
23467 // optimizations. Note that the operands are ordered the opposite of SELECT
23469 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23470 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23471 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23472 // larger than FalseC (the false value).
23473 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23474 CC = X86::GetOppositeBranchCondition(CC);
23475 std::swap(TrueC, FalseC);
23476 std::swap(TrueOp, FalseOp);
23479 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23480 // This is efficient for any integer data type (including i8/i16) and
23482 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23483 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23484 DAG.getConstant(CC, MVT::i8), Cond);
23486 // Zero extend the condition if needed.
23487 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23489 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23490 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23491 DAG.getConstant(ShAmt, MVT::i8));
23492 if (N->getNumValues() == 2) // Dead flag value?
23493 return DCI.CombineTo(N, Cond, SDValue());
23497 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23498 // for any integer data type, including i8/i16.
23499 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23500 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23501 DAG.getConstant(CC, MVT::i8), Cond);
23503 // Zero extend the condition if needed.
23504 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23505 FalseC->getValueType(0), Cond);
23506 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23507 SDValue(FalseC, 0));
23509 if (N->getNumValues() == 2) // Dead flag value?
23510 return DCI.CombineTo(N, Cond, SDValue());
23514 // Optimize cases that will turn into an LEA instruction. This requires
23515 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23516 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23517 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23518 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23520 bool isFastMultiplier = false;
23522 switch ((unsigned char)Diff) {
23524 case 1: // result = add base, cond
23525 case 2: // result = lea base( , cond*2)
23526 case 3: // result = lea base(cond, cond*2)
23527 case 4: // result = lea base( , cond*4)
23528 case 5: // result = lea base(cond, cond*4)
23529 case 8: // result = lea base( , cond*8)
23530 case 9: // result = lea base(cond, cond*8)
23531 isFastMultiplier = true;
23536 if (isFastMultiplier) {
23537 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23538 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23539 DAG.getConstant(CC, MVT::i8), Cond);
23540 // Zero extend the condition if needed.
23541 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23543 // Scale the condition by the difference.
23545 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23546 DAG.getConstant(Diff, Cond.getValueType()));
23548 // Add the base if non-zero.
23549 if (FalseC->getAPIntValue() != 0)
23550 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23551 SDValue(FalseC, 0));
23552 if (N->getNumValues() == 2) // Dead flag value?
23553 return DCI.CombineTo(N, Cond, SDValue());
23560 // Handle these cases:
23561 // (select (x != c), e, c) -> select (x != c), e, x),
23562 // (select (x == c), c, e) -> select (x == c), x, e)
23563 // where the c is an integer constant, and the "select" is the combination
23564 // of CMOV and CMP.
23566 // The rationale for this change is that the conditional-move from a constant
23567 // needs two instructions, however, conditional-move from a register needs
23568 // only one instruction.
23570 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23571 // some instruction-combining opportunities. This opt needs to be
23572 // postponed as late as possible.
23574 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23575 // the DCI.xxxx conditions are provided to postpone the optimization as
23576 // late as possible.
23578 ConstantSDNode *CmpAgainst = nullptr;
23579 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23580 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23581 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23583 if (CC == X86::COND_NE &&
23584 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23585 CC = X86::GetOppositeBranchCondition(CC);
23586 std::swap(TrueOp, FalseOp);
23589 if (CC == X86::COND_E &&
23590 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23591 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23592 DAG.getConstant(CC, MVT::i8), Cond };
23593 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23601 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
23602 const X86Subtarget *Subtarget) {
23603 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
23605 default: return SDValue();
23606 // SSE/AVX/AVX2 blend intrinsics.
23607 case Intrinsic::x86_avx2_pblendvb:
23608 case Intrinsic::x86_avx2_pblendw:
23609 case Intrinsic::x86_avx2_pblendd_128:
23610 case Intrinsic::x86_avx2_pblendd_256:
23611 // Don't try to simplify this intrinsic if we don't have AVX2.
23612 if (!Subtarget->hasAVX2())
23615 case Intrinsic::x86_avx_blend_pd_256:
23616 case Intrinsic::x86_avx_blend_ps_256:
23617 case Intrinsic::x86_avx_blendv_pd_256:
23618 case Intrinsic::x86_avx_blendv_ps_256:
23619 // Don't try to simplify this intrinsic if we don't have AVX.
23620 if (!Subtarget->hasAVX())
23623 case Intrinsic::x86_sse41_pblendw:
23624 case Intrinsic::x86_sse41_blendpd:
23625 case Intrinsic::x86_sse41_blendps:
23626 case Intrinsic::x86_sse41_blendvps:
23627 case Intrinsic::x86_sse41_blendvpd:
23628 case Intrinsic::x86_sse41_pblendvb: {
23629 SDValue Op0 = N->getOperand(1);
23630 SDValue Op1 = N->getOperand(2);
23631 SDValue Mask = N->getOperand(3);
23633 // Don't try to simplify this intrinsic if we don't have SSE4.1.
23634 if (!Subtarget->hasSSE41())
23637 // fold (blend A, A, Mask) -> A
23640 // fold (blend A, B, allZeros) -> A
23641 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
23643 // fold (blend A, B, allOnes) -> B
23644 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
23647 // Simplify the case where the mask is a constant i32 value.
23648 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
23649 if (C->isNullValue())
23651 if (C->isAllOnesValue())
23658 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
23659 case Intrinsic::x86_sse2_psrai_w:
23660 case Intrinsic::x86_sse2_psrai_d:
23661 case Intrinsic::x86_avx2_psrai_w:
23662 case Intrinsic::x86_avx2_psrai_d:
23663 case Intrinsic::x86_sse2_psra_w:
23664 case Intrinsic::x86_sse2_psra_d:
23665 case Intrinsic::x86_avx2_psra_w:
23666 case Intrinsic::x86_avx2_psra_d: {
23667 SDValue Op0 = N->getOperand(1);
23668 SDValue Op1 = N->getOperand(2);
23669 EVT VT = Op0.getValueType();
23670 assert(VT.isVector() && "Expected a vector type!");
23672 if (isa<BuildVectorSDNode>(Op1))
23673 Op1 = Op1.getOperand(0);
23675 if (!isa<ConstantSDNode>(Op1))
23678 EVT SVT = VT.getVectorElementType();
23679 unsigned SVTBits = SVT.getSizeInBits();
23681 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
23682 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
23683 uint64_t ShAmt = C.getZExtValue();
23685 // Don't try to convert this shift into a ISD::SRA if the shift
23686 // count is bigger than or equal to the element size.
23687 if (ShAmt >= SVTBits)
23690 // Trivial case: if the shift count is zero, then fold this
23691 // into the first operand.
23695 // Replace this packed shift intrinsic with a target independent
23697 SDValue Splat = DAG.getConstant(C, VT);
23698 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
23703 /// PerformMulCombine - Optimize a single multiply with constant into two
23704 /// in order to implement it with two cheaper instructions, e.g.
23705 /// LEA + SHL, LEA + LEA.
23706 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23707 TargetLowering::DAGCombinerInfo &DCI) {
23708 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23711 EVT VT = N->getValueType(0);
23712 if (VT != MVT::i64)
23715 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23718 uint64_t MulAmt = C->getZExtValue();
23719 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23722 uint64_t MulAmt1 = 0;
23723 uint64_t MulAmt2 = 0;
23724 if ((MulAmt % 9) == 0) {
23726 MulAmt2 = MulAmt / 9;
23727 } else if ((MulAmt % 5) == 0) {
23729 MulAmt2 = MulAmt / 5;
23730 } else if ((MulAmt % 3) == 0) {
23732 MulAmt2 = MulAmt / 3;
23735 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23738 if (isPowerOf2_64(MulAmt2) &&
23739 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23740 // If second multiplifer is pow2, issue it first. We want the multiply by
23741 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23743 std::swap(MulAmt1, MulAmt2);
23746 if (isPowerOf2_64(MulAmt1))
23747 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23748 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
23750 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23751 DAG.getConstant(MulAmt1, VT));
23753 if (isPowerOf2_64(MulAmt2))
23754 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23755 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
23757 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23758 DAG.getConstant(MulAmt2, VT));
23760 // Do not add new nodes to DAG combiner worklist.
23761 DCI.CombineTo(N, NewMul, false);
23766 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23767 SDValue N0 = N->getOperand(0);
23768 SDValue N1 = N->getOperand(1);
23769 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23770 EVT VT = N0.getValueType();
23772 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23773 // since the result of setcc_c is all zero's or all ones.
23774 if (VT.isInteger() && !VT.isVector() &&
23775 N1C && N0.getOpcode() == ISD::AND &&
23776 N0.getOperand(1).getOpcode() == ISD::Constant) {
23777 SDValue N00 = N0.getOperand(0);
23778 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
23779 ((N00.getOpcode() == ISD::ANY_EXTEND ||
23780 N00.getOpcode() == ISD::ZERO_EXTEND) &&
23781 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
23782 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
23783 APInt ShAmt = N1C->getAPIntValue();
23784 Mask = Mask.shl(ShAmt);
23786 return DAG.getNode(ISD::AND, SDLoc(N), VT,
23787 N00, DAG.getConstant(Mask, VT));
23791 // Hardware support for vector shifts is sparse which makes us scalarize the
23792 // vector operations in many cases. Also, on sandybridge ADD is faster than
23794 // (shl V, 1) -> add V,V
23795 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23796 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23797 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23798 // We shift all of the values by one. In many cases we do not have
23799 // hardware support for this operation. This is better expressed as an ADD
23801 if (N1SplatC->getZExtValue() == 1)
23802 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
23808 /// \brief Returns a vector of 0s if the node in input is a vector logical
23809 /// shift by a constant amount which is known to be bigger than or equal
23810 /// to the vector element size in bits.
23811 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
23812 const X86Subtarget *Subtarget) {
23813 EVT VT = N->getValueType(0);
23815 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
23816 (!Subtarget->hasInt256() ||
23817 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
23820 SDValue Amt = N->getOperand(1);
23822 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
23823 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
23824 APInt ShiftAmt = AmtSplat->getAPIntValue();
23825 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
23827 // SSE2/AVX2 logical shifts always return a vector of 0s
23828 // if the shift amount is bigger than or equal to
23829 // the element size. The constant shift amount will be
23830 // encoded as a 8-bit immediate.
23831 if (ShiftAmt.trunc(8).uge(MaxAmount))
23832 return getZeroVector(VT, Subtarget, DAG, DL);
23838 /// PerformShiftCombine - Combine shifts.
23839 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
23840 TargetLowering::DAGCombinerInfo &DCI,
23841 const X86Subtarget *Subtarget) {
23842 if (N->getOpcode() == ISD::SHL) {
23843 SDValue V = PerformSHLCombine(N, DAG);
23844 if (V.getNode()) return V;
23847 if (N->getOpcode() != ISD::SRA) {
23848 // Try to fold this logical shift into a zero vector.
23849 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
23850 if (V.getNode()) return V;
23856 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
23857 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
23858 // and friends. Likewise for OR -> CMPNEQSS.
23859 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
23860 TargetLowering::DAGCombinerInfo &DCI,
23861 const X86Subtarget *Subtarget) {
23864 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
23865 // we're requiring SSE2 for both.
23866 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
23867 SDValue N0 = N->getOperand(0);
23868 SDValue N1 = N->getOperand(1);
23869 SDValue CMP0 = N0->getOperand(1);
23870 SDValue CMP1 = N1->getOperand(1);
23873 // The SETCCs should both refer to the same CMP.
23874 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
23877 SDValue CMP00 = CMP0->getOperand(0);
23878 SDValue CMP01 = CMP0->getOperand(1);
23879 EVT VT = CMP00.getValueType();
23881 if (VT == MVT::f32 || VT == MVT::f64) {
23882 bool ExpectingFlags = false;
23883 // Check for any users that want flags:
23884 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
23885 !ExpectingFlags && UI != UE; ++UI)
23886 switch (UI->getOpcode()) {
23891 ExpectingFlags = true;
23893 case ISD::CopyToReg:
23894 case ISD::SIGN_EXTEND:
23895 case ISD::ZERO_EXTEND:
23896 case ISD::ANY_EXTEND:
23900 if (!ExpectingFlags) {
23901 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
23902 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
23904 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
23905 X86::CondCode tmp = cc0;
23910 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
23911 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
23912 // FIXME: need symbolic constants for these magic numbers.
23913 // See X86ATTInstPrinter.cpp:printSSECC().
23914 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
23915 if (Subtarget->hasAVX512()) {
23916 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
23917 CMP01, DAG.getConstant(x86cc, MVT::i8));
23918 if (N->getValueType(0) != MVT::i1)
23919 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
23923 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
23924 CMP00.getValueType(), CMP00, CMP01,
23925 DAG.getConstant(x86cc, MVT::i8));
23927 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
23928 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
23930 if (is64BitFP && !Subtarget->is64Bit()) {
23931 // On a 32-bit target, we cannot bitcast the 64-bit float to a
23932 // 64-bit integer, since that's not a legal type. Since
23933 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
23934 // bits, but can do this little dance to extract the lowest 32 bits
23935 // and work with those going forward.
23936 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
23938 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
23940 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
23941 Vector32, DAG.getIntPtrConstant(0));
23945 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
23946 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
23947 DAG.getConstant(1, IntVT));
23948 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
23949 return OneBitOfTruth;
23957 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
23958 /// so it can be folded inside ANDNP.
23959 static bool CanFoldXORWithAllOnes(const SDNode *N) {
23960 EVT VT = N->getValueType(0);
23962 // Match direct AllOnes for 128 and 256-bit vectors
23963 if (ISD::isBuildVectorAllOnes(N))
23966 // Look through a bit convert.
23967 if (N->getOpcode() == ISD::BITCAST)
23968 N = N->getOperand(0).getNode();
23970 // Sometimes the operand may come from a insert_subvector building a 256-bit
23972 if (VT.is256BitVector() &&
23973 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
23974 SDValue V1 = N->getOperand(0);
23975 SDValue V2 = N->getOperand(1);
23977 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
23978 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
23979 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
23980 ISD::isBuildVectorAllOnes(V2.getNode()))
23987 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
23988 // register. In most cases we actually compare or select YMM-sized registers
23989 // and mixing the two types creates horrible code. This method optimizes
23990 // some of the transition sequences.
23991 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
23992 TargetLowering::DAGCombinerInfo &DCI,
23993 const X86Subtarget *Subtarget) {
23994 EVT VT = N->getValueType(0);
23995 if (!VT.is256BitVector())
23998 assert((N->getOpcode() == ISD::ANY_EXTEND ||
23999 N->getOpcode() == ISD::ZERO_EXTEND ||
24000 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24002 SDValue Narrow = N->getOperand(0);
24003 EVT NarrowVT = Narrow->getValueType(0);
24004 if (!NarrowVT.is128BitVector())
24007 if (Narrow->getOpcode() != ISD::XOR &&
24008 Narrow->getOpcode() != ISD::AND &&
24009 Narrow->getOpcode() != ISD::OR)
24012 SDValue N0 = Narrow->getOperand(0);
24013 SDValue N1 = Narrow->getOperand(1);
24016 // The Left side has to be a trunc.
24017 if (N0.getOpcode() != ISD::TRUNCATE)
24020 // The type of the truncated inputs.
24021 EVT WideVT = N0->getOperand(0)->getValueType(0);
24025 // The right side has to be a 'trunc' or a constant vector.
24026 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24027 ConstantSDNode *RHSConstSplat = nullptr;
24028 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24029 RHSConstSplat = RHSBV->getConstantSplatNode();
24030 if (!RHSTrunc && !RHSConstSplat)
24033 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24035 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24038 // Set N0 and N1 to hold the inputs to the new wide operation.
24039 N0 = N0->getOperand(0);
24040 if (RHSConstSplat) {
24041 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
24042 SDValue(RHSConstSplat, 0));
24043 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24044 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24045 } else if (RHSTrunc) {
24046 N1 = N1->getOperand(0);
24049 // Generate the wide operation.
24050 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24051 unsigned Opcode = N->getOpcode();
24053 case ISD::ANY_EXTEND:
24055 case ISD::ZERO_EXTEND: {
24056 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24057 APInt Mask = APInt::getAllOnesValue(InBits);
24058 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24059 return DAG.getNode(ISD::AND, DL, VT,
24060 Op, DAG.getConstant(Mask, VT));
24062 case ISD::SIGN_EXTEND:
24063 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24064 Op, DAG.getValueType(NarrowVT));
24066 llvm_unreachable("Unexpected opcode");
24070 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24071 TargetLowering::DAGCombinerInfo &DCI,
24072 const X86Subtarget *Subtarget) {
24073 EVT VT = N->getValueType(0);
24074 if (DCI.isBeforeLegalizeOps())
24077 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24081 // Create BEXTR instructions
24082 // BEXTR is ((X >> imm) & (2**size-1))
24083 if (VT == MVT::i32 || VT == MVT::i64) {
24084 SDValue N0 = N->getOperand(0);
24085 SDValue N1 = N->getOperand(1);
24088 // Check for BEXTR.
24089 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24090 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24091 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24092 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24093 if (MaskNode && ShiftNode) {
24094 uint64_t Mask = MaskNode->getZExtValue();
24095 uint64_t Shift = ShiftNode->getZExtValue();
24096 if (isMask_64(Mask)) {
24097 uint64_t MaskSize = CountPopulation_64(Mask);
24098 if (Shift + MaskSize <= VT.getSizeInBits())
24099 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24100 DAG.getConstant(Shift | (MaskSize << 8), VT));
24108 // Want to form ANDNP nodes:
24109 // 1) In the hopes of then easily combining them with OR and AND nodes
24110 // to form PBLEND/PSIGN.
24111 // 2) To match ANDN packed intrinsics
24112 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24115 SDValue N0 = N->getOperand(0);
24116 SDValue N1 = N->getOperand(1);
24119 // Check LHS for vnot
24120 if (N0.getOpcode() == ISD::XOR &&
24121 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24122 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24123 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24125 // Check RHS for vnot
24126 if (N1.getOpcode() == ISD::XOR &&
24127 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24128 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24129 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24134 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24135 TargetLowering::DAGCombinerInfo &DCI,
24136 const X86Subtarget *Subtarget) {
24137 if (DCI.isBeforeLegalizeOps())
24140 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24144 SDValue N0 = N->getOperand(0);
24145 SDValue N1 = N->getOperand(1);
24146 EVT VT = N->getValueType(0);
24148 // look for psign/blend
24149 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24150 if (!Subtarget->hasSSSE3() ||
24151 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24154 // Canonicalize pandn to RHS
24155 if (N0.getOpcode() == X86ISD::ANDNP)
24157 // or (and (m, y), (pandn m, x))
24158 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24159 SDValue Mask = N1.getOperand(0);
24160 SDValue X = N1.getOperand(1);
24162 if (N0.getOperand(0) == Mask)
24163 Y = N0.getOperand(1);
24164 if (N0.getOperand(1) == Mask)
24165 Y = N0.getOperand(0);
24167 // Check to see if the mask appeared in both the AND and ANDNP and
24171 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24172 // Look through mask bitcast.
24173 if (Mask.getOpcode() == ISD::BITCAST)
24174 Mask = Mask.getOperand(0);
24175 if (X.getOpcode() == ISD::BITCAST)
24176 X = X.getOperand(0);
24177 if (Y.getOpcode() == ISD::BITCAST)
24178 Y = Y.getOperand(0);
24180 EVT MaskVT = Mask.getValueType();
24182 // Validate that the Mask operand is a vector sra node.
24183 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24184 // there is no psrai.b
24185 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24186 unsigned SraAmt = ~0;
24187 if (Mask.getOpcode() == ISD::SRA) {
24188 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24189 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24190 SraAmt = AmtConst->getZExtValue();
24191 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24192 SDValue SraC = Mask.getOperand(1);
24193 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24195 if ((SraAmt + 1) != EltBits)
24200 // Now we know we at least have a plendvb with the mask val. See if
24201 // we can form a psignb/w/d.
24202 // psign = x.type == y.type == mask.type && y = sub(0, x);
24203 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24204 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24205 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24206 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24207 "Unsupported VT for PSIGN");
24208 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24209 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24211 // PBLENDVB only available on SSE 4.1
24212 if (!Subtarget->hasSSE41())
24215 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24217 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
24218 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
24219 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
24220 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24221 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24225 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24228 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24229 MachineFunction &MF = DAG.getMachineFunction();
24230 bool OptForSize = MF.getFunction()->getAttributes().
24231 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
24233 // SHLD/SHRD instructions have lower register pressure, but on some
24234 // platforms they have higher latency than the equivalent
24235 // series of shifts/or that would otherwise be generated.
24236 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24237 // have higher latencies and we are not optimizing for size.
24238 if (!OptForSize && Subtarget->isSHLDSlow())
24241 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24243 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24245 if (!N0.hasOneUse() || !N1.hasOneUse())
24248 SDValue ShAmt0 = N0.getOperand(1);
24249 if (ShAmt0.getValueType() != MVT::i8)
24251 SDValue ShAmt1 = N1.getOperand(1);
24252 if (ShAmt1.getValueType() != MVT::i8)
24254 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24255 ShAmt0 = ShAmt0.getOperand(0);
24256 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24257 ShAmt1 = ShAmt1.getOperand(0);
24260 unsigned Opc = X86ISD::SHLD;
24261 SDValue Op0 = N0.getOperand(0);
24262 SDValue Op1 = N1.getOperand(0);
24263 if (ShAmt0.getOpcode() == ISD::SUB) {
24264 Opc = X86ISD::SHRD;
24265 std::swap(Op0, Op1);
24266 std::swap(ShAmt0, ShAmt1);
24269 unsigned Bits = VT.getSizeInBits();
24270 if (ShAmt1.getOpcode() == ISD::SUB) {
24271 SDValue Sum = ShAmt1.getOperand(0);
24272 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24273 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24274 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24275 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24276 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24277 return DAG.getNode(Opc, DL, VT,
24279 DAG.getNode(ISD::TRUNCATE, DL,
24282 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24283 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24285 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24286 return DAG.getNode(Opc, DL, VT,
24287 N0.getOperand(0), N1.getOperand(0),
24288 DAG.getNode(ISD::TRUNCATE, DL,
24295 // Generate NEG and CMOV for integer abs.
24296 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24297 EVT VT = N->getValueType(0);
24299 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24300 // 8-bit integer abs to NEG and CMOV.
24301 if (VT.isInteger() && VT.getSizeInBits() == 8)
24304 SDValue N0 = N->getOperand(0);
24305 SDValue N1 = N->getOperand(1);
24308 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24309 // and change it to SUB and CMOV.
24310 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24311 N0.getOpcode() == ISD::ADD &&
24312 N0.getOperand(1) == N1 &&
24313 N1.getOpcode() == ISD::SRA &&
24314 N1.getOperand(0) == N0.getOperand(0))
24315 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24316 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24317 // Generate SUB & CMOV.
24318 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24319 DAG.getConstant(0, VT), N0.getOperand(0));
24321 SDValue Ops[] = { N0.getOperand(0), Neg,
24322 DAG.getConstant(X86::COND_GE, MVT::i8),
24323 SDValue(Neg.getNode(), 1) };
24324 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24329 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
24330 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24331 TargetLowering::DAGCombinerInfo &DCI,
24332 const X86Subtarget *Subtarget) {
24333 if (DCI.isBeforeLegalizeOps())
24336 if (Subtarget->hasCMov()) {
24337 SDValue RV = performIntegerAbsCombine(N, DAG);
24345 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24346 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24347 TargetLowering::DAGCombinerInfo &DCI,
24348 const X86Subtarget *Subtarget) {
24349 LoadSDNode *Ld = cast<LoadSDNode>(N);
24350 EVT RegVT = Ld->getValueType(0);
24351 EVT MemVT = Ld->getMemoryVT();
24353 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24355 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
24356 // into two 16-byte operations.
24357 ISD::LoadExtType Ext = Ld->getExtensionType();
24358 unsigned Alignment = Ld->getAlignment();
24359 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
24360 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24361 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
24362 unsigned NumElems = RegVT.getVectorNumElements();
24366 SDValue Ptr = Ld->getBasePtr();
24367 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
24369 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24371 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24372 Ld->getPointerInfo(), Ld->isVolatile(),
24373 Ld->isNonTemporal(), Ld->isInvariant(),
24375 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24376 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24377 Ld->getPointerInfo(), Ld->isVolatile(),
24378 Ld->isNonTemporal(), Ld->isInvariant(),
24379 std::min(16U, Alignment));
24380 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24382 Load2.getValue(1));
24384 SDValue NewVec = DAG.getUNDEF(RegVT);
24385 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24386 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24387 return DCI.CombineTo(N, NewVec, TF, true);
24393 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
24394 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
24395 const X86Subtarget *Subtarget) {
24396 StoreSDNode *St = cast<StoreSDNode>(N);
24397 EVT VT = St->getValue().getValueType();
24398 EVT StVT = St->getMemoryVT();
24400 SDValue StoredVal = St->getOperand(1);
24401 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24403 // If we are saving a concatenation of two XMM registers and 32-byte stores
24404 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
24405 unsigned Alignment = St->getAlignment();
24406 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
24407 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24408 StVT == VT && !IsAligned) {
24409 unsigned NumElems = VT.getVectorNumElements();
24413 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24414 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24416 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
24417 SDValue Ptr0 = St->getBasePtr();
24418 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
24420 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
24421 St->getPointerInfo(), St->isVolatile(),
24422 St->isNonTemporal(), Alignment);
24423 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
24424 St->getPointerInfo(), St->isVolatile(),
24425 St->isNonTemporal(),
24426 std::min(16U, Alignment));
24427 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
24430 // Optimize trunc store (of multiple scalars) to shuffle and store.
24431 // First, pack all of the elements in one place. Next, store to memory
24432 // in fewer chunks.
24433 if (St->isTruncatingStore() && VT.isVector()) {
24434 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24435 unsigned NumElems = VT.getVectorNumElements();
24436 assert(StVT != VT && "Cannot truncate to the same type");
24437 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24438 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24440 // From, To sizes and ElemCount must be pow of two
24441 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24442 // We are going to use the original vector elt for storing.
24443 // Accumulated smaller vector elements must be a multiple of the store size.
24444 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24446 unsigned SizeRatio = FromSz / ToSz;
24448 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24450 // Create a type on which we perform the shuffle
24451 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24452 StVT.getScalarType(), NumElems*SizeRatio);
24454 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24456 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
24457 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24458 for (unsigned i = 0; i != NumElems; ++i)
24459 ShuffleVec[i] = i * SizeRatio;
24461 // Can't shuffle using an illegal type.
24462 if (!TLI.isTypeLegal(WideVecVT))
24465 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24466 DAG.getUNDEF(WideVecVT),
24468 // At this point all of the data is stored at the bottom of the
24469 // register. We now need to save it to mem.
24471 // Find the largest store unit
24472 MVT StoreType = MVT::i8;
24473 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
24474 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
24475 MVT Tp = (MVT::SimpleValueType)tp;
24476 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24480 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24481 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24482 (64 <= NumElems * ToSz))
24483 StoreType = MVT::f64;
24485 // Bitcast the original vector into a vector of store-size units
24486 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24487 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24488 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24489 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
24490 SmallVector<SDValue, 8> Chains;
24491 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
24492 TLI.getPointerTy());
24493 SDValue Ptr = St->getBasePtr();
24495 // Perform one or more big stores into memory.
24496 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24497 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24498 StoreType, ShuffWide,
24499 DAG.getIntPtrConstant(i));
24500 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24501 St->getPointerInfo(), St->isVolatile(),
24502 St->isNonTemporal(), St->getAlignment());
24503 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24504 Chains.push_back(Ch);
24507 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24510 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24511 // the FP state in cases where an emms may be missing.
24512 // A preferable solution to the general problem is to figure out the right
24513 // places to insert EMMS. This qualifies as a quick hack.
24515 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24516 if (VT.getSizeInBits() != 64)
24519 const Function *F = DAG.getMachineFunction().getFunction();
24520 bool NoImplicitFloatOps = F->getAttributes().
24521 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
24522 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
24523 && Subtarget->hasSSE2();
24524 if ((VT.isVector() ||
24525 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24526 isa<LoadSDNode>(St->getValue()) &&
24527 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24528 St->getChain().hasOneUse() && !St->isVolatile()) {
24529 SDNode* LdVal = St->getValue().getNode();
24530 LoadSDNode *Ld = nullptr;
24531 int TokenFactorIndex = -1;
24532 SmallVector<SDValue, 8> Ops;
24533 SDNode* ChainVal = St->getChain().getNode();
24534 // Must be a store of a load. We currently handle two cases: the load
24535 // is a direct child, and it's under an intervening TokenFactor. It is
24536 // possible to dig deeper under nested TokenFactors.
24537 if (ChainVal == LdVal)
24538 Ld = cast<LoadSDNode>(St->getChain());
24539 else if (St->getValue().hasOneUse() &&
24540 ChainVal->getOpcode() == ISD::TokenFactor) {
24541 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24542 if (ChainVal->getOperand(i).getNode() == LdVal) {
24543 TokenFactorIndex = i;
24544 Ld = cast<LoadSDNode>(St->getValue());
24546 Ops.push_back(ChainVal->getOperand(i));
24550 if (!Ld || !ISD::isNormalLoad(Ld))
24553 // If this is not the MMX case, i.e. we are just turning i64 load/store
24554 // into f64 load/store, avoid the transformation if there are multiple
24555 // uses of the loaded value.
24556 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24561 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24562 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24564 if (Subtarget->is64Bit() || F64IsLegal) {
24565 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24566 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24567 Ld->getPointerInfo(), Ld->isVolatile(),
24568 Ld->isNonTemporal(), Ld->isInvariant(),
24569 Ld->getAlignment());
24570 SDValue NewChain = NewLd.getValue(1);
24571 if (TokenFactorIndex != -1) {
24572 Ops.push_back(NewChain);
24573 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24575 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24576 St->getPointerInfo(),
24577 St->isVolatile(), St->isNonTemporal(),
24578 St->getAlignment());
24581 // Otherwise, lower to two pairs of 32-bit loads / stores.
24582 SDValue LoAddr = Ld->getBasePtr();
24583 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24584 DAG.getConstant(4, MVT::i32));
24586 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24587 Ld->getPointerInfo(),
24588 Ld->isVolatile(), Ld->isNonTemporal(),
24589 Ld->isInvariant(), Ld->getAlignment());
24590 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24591 Ld->getPointerInfo().getWithOffset(4),
24592 Ld->isVolatile(), Ld->isNonTemporal(),
24594 MinAlign(Ld->getAlignment(), 4));
24596 SDValue NewChain = LoLd.getValue(1);
24597 if (TokenFactorIndex != -1) {
24598 Ops.push_back(LoLd);
24599 Ops.push_back(HiLd);
24600 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24603 LoAddr = St->getBasePtr();
24604 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24605 DAG.getConstant(4, MVT::i32));
24607 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24608 St->getPointerInfo(),
24609 St->isVolatile(), St->isNonTemporal(),
24610 St->getAlignment());
24611 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24612 St->getPointerInfo().getWithOffset(4),
24614 St->isNonTemporal(),
24615 MinAlign(St->getAlignment(), 4));
24616 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24621 /// Return 'true' if this vector operation is "horizontal"
24622 /// and return the operands for the horizontal operation in LHS and RHS. A
24623 /// horizontal operation performs the binary operation on successive elements
24624 /// of its first operand, then on successive elements of its second operand,
24625 /// returning the resulting values in a vector. For example, if
24626 /// A = < float a0, float a1, float a2, float a3 >
24628 /// B = < float b0, float b1, float b2, float b3 >
24629 /// then the result of doing a horizontal operation on A and B is
24630 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
24631 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
24632 /// A horizontal-op B, for some already available A and B, and if so then LHS is
24633 /// set to A, RHS to B, and the routine returns 'true'.
24634 /// Note that the binary operation should have the property that if one of the
24635 /// operands is UNDEF then the result is UNDEF.
24636 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
24637 // Look for the following pattern: if
24638 // A = < float a0, float a1, float a2, float a3 >
24639 // B = < float b0, float b1, float b2, float b3 >
24641 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
24642 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
24643 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
24644 // which is A horizontal-op B.
24646 // At least one of the operands should be a vector shuffle.
24647 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
24648 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
24651 MVT VT = LHS.getSimpleValueType();
24653 assert((VT.is128BitVector() || VT.is256BitVector()) &&
24654 "Unsupported vector type for horizontal add/sub");
24656 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
24657 // operate independently on 128-bit lanes.
24658 unsigned NumElts = VT.getVectorNumElements();
24659 unsigned NumLanes = VT.getSizeInBits()/128;
24660 unsigned NumLaneElts = NumElts / NumLanes;
24661 assert((NumLaneElts % 2 == 0) &&
24662 "Vector type should have an even number of elements in each lane");
24663 unsigned HalfLaneElts = NumLaneElts/2;
24665 // View LHS in the form
24666 // LHS = VECTOR_SHUFFLE A, B, LMask
24667 // If LHS is not a shuffle then pretend it is the shuffle
24668 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24669 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24672 SmallVector<int, 16> LMask(NumElts);
24673 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24674 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24675 A = LHS.getOperand(0);
24676 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24677 B = LHS.getOperand(1);
24678 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24679 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24681 if (LHS.getOpcode() != ISD::UNDEF)
24683 for (unsigned i = 0; i != NumElts; ++i)
24687 // Likewise, view RHS in the form
24688 // RHS = VECTOR_SHUFFLE C, D, RMask
24690 SmallVector<int, 16> RMask(NumElts);
24691 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24692 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24693 C = RHS.getOperand(0);
24694 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24695 D = RHS.getOperand(1);
24696 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24697 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24699 if (RHS.getOpcode() != ISD::UNDEF)
24701 for (unsigned i = 0; i != NumElts; ++i)
24705 // Check that the shuffles are both shuffling the same vectors.
24706 if (!(A == C && B == D) && !(A == D && B == C))
24709 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24710 if (!A.getNode() && !B.getNode())
24713 // If A and B occur in reverse order in RHS, then "swap" them (which means
24714 // rewriting the mask).
24716 CommuteVectorShuffleMask(RMask, NumElts);
24718 // At this point LHS and RHS are equivalent to
24719 // LHS = VECTOR_SHUFFLE A, B, LMask
24720 // RHS = VECTOR_SHUFFLE A, B, RMask
24721 // Check that the masks correspond to performing a horizontal operation.
24722 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24723 for (unsigned i = 0; i != NumLaneElts; ++i) {
24724 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24726 // Ignore any UNDEF components.
24727 if (LIdx < 0 || RIdx < 0 ||
24728 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24729 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24732 // Check that successive elements are being operated on. If not, this is
24733 // not a horizontal operation.
24734 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24735 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24736 if (!(LIdx == Index && RIdx == Index + 1) &&
24737 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24742 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24743 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24747 /// Do target-specific dag combines on floating point adds.
24748 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24749 const X86Subtarget *Subtarget) {
24750 EVT VT = N->getValueType(0);
24751 SDValue LHS = N->getOperand(0);
24752 SDValue RHS = N->getOperand(1);
24754 // Try to synthesize horizontal adds from adds of shuffles.
24755 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24756 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24757 isHorizontalBinOp(LHS, RHS, true))
24758 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24762 /// Do target-specific dag combines on floating point subs.
24763 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24764 const X86Subtarget *Subtarget) {
24765 EVT VT = N->getValueType(0);
24766 SDValue LHS = N->getOperand(0);
24767 SDValue RHS = N->getOperand(1);
24769 // Try to synthesize horizontal subs from subs of shuffles.
24770 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24771 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24772 isHorizontalBinOp(LHS, RHS, false))
24773 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24777 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
24778 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24779 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24780 // F[X]OR(0.0, x) -> x
24781 // F[X]OR(x, 0.0) -> x
24782 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24783 if (C->getValueAPF().isPosZero())
24784 return N->getOperand(1);
24785 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24786 if (C->getValueAPF().isPosZero())
24787 return N->getOperand(0);
24791 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
24792 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24793 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24795 // Only perform optimizations if UnsafeMath is used.
24796 if (!DAG.getTarget().Options.UnsafeFPMath)
24799 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24800 // into FMINC and FMAXC, which are Commutative operations.
24801 unsigned NewOp = 0;
24802 switch (N->getOpcode()) {
24803 default: llvm_unreachable("unknown opcode");
24804 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24805 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
24808 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
24809 N->getOperand(0), N->getOperand(1));
24812 /// Do target-specific dag combines on X86ISD::FAND nodes.
24813 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
24814 // FAND(0.0, x) -> 0.0
24815 // FAND(x, 0.0) -> 0.0
24816 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24817 if (C->getValueAPF().isPosZero())
24818 return N->getOperand(0);
24819 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24820 if (C->getValueAPF().isPosZero())
24821 return N->getOperand(1);
24825 /// Do target-specific dag combines on X86ISD::FANDN nodes
24826 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
24827 // FANDN(x, 0.0) -> 0.0
24828 // FANDN(0.0, x) -> x
24829 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24830 if (C->getValueAPF().isPosZero())
24831 return N->getOperand(1);
24832 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24833 if (C->getValueAPF().isPosZero())
24834 return N->getOperand(1);
24838 static SDValue PerformBTCombine(SDNode *N,
24840 TargetLowering::DAGCombinerInfo &DCI) {
24841 // BT ignores high bits in the bit index operand.
24842 SDValue Op1 = N->getOperand(1);
24843 if (Op1.hasOneUse()) {
24844 unsigned BitWidth = Op1.getValueSizeInBits();
24845 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
24846 APInt KnownZero, KnownOne;
24847 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
24848 !DCI.isBeforeLegalizeOps());
24849 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24850 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
24851 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
24852 DCI.CommitTargetLoweringOpt(TLO);
24857 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
24858 SDValue Op = N->getOperand(0);
24859 if (Op.getOpcode() == ISD::BITCAST)
24860 Op = Op.getOperand(0);
24861 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
24862 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
24863 VT.getVectorElementType().getSizeInBits() ==
24864 OpVT.getVectorElementType().getSizeInBits()) {
24865 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
24870 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
24871 const X86Subtarget *Subtarget) {
24872 EVT VT = N->getValueType(0);
24873 if (!VT.isVector())
24876 SDValue N0 = N->getOperand(0);
24877 SDValue N1 = N->getOperand(1);
24878 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
24881 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
24882 // both SSE and AVX2 since there is no sign-extended shift right
24883 // operation on a vector with 64-bit elements.
24884 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
24885 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
24886 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
24887 N0.getOpcode() == ISD::SIGN_EXTEND)) {
24888 SDValue N00 = N0.getOperand(0);
24890 // EXTLOAD has a better solution on AVX2,
24891 // it may be replaced with X86ISD::VSEXT node.
24892 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
24893 if (!ISD::isNormalLoad(N00.getNode()))
24896 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
24897 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
24899 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24905 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24906 TargetLowering::DAGCombinerInfo &DCI,
24907 const X86Subtarget *Subtarget) {
24908 SDValue N0 = N->getOperand(0);
24909 EVT VT = N->getValueType(0);
24911 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
24912 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
24913 // This exposes the sext to the sdivrem lowering, so that it directly extends
24914 // from AH (which we otherwise need to do contortions to access).
24915 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
24916 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
24918 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24919 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
24920 N0.getOperand(0), N0.getOperand(1));
24921 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24922 return R.getValue(1);
24925 if (!DCI.isBeforeLegalizeOps())
24928 if (!Subtarget->hasFp256())
24931 if (VT.isVector() && VT.getSizeInBits() == 256) {
24932 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24940 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24941 const X86Subtarget* Subtarget) {
24943 EVT VT = N->getValueType(0);
24945 // Let legalize expand this if it isn't a legal type yet.
24946 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
24949 EVT ScalarVT = VT.getScalarType();
24950 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
24951 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
24954 SDValue A = N->getOperand(0);
24955 SDValue B = N->getOperand(1);
24956 SDValue C = N->getOperand(2);
24958 bool NegA = (A.getOpcode() == ISD::FNEG);
24959 bool NegB = (B.getOpcode() == ISD::FNEG);
24960 bool NegC = (C.getOpcode() == ISD::FNEG);
24962 // Negative multiplication when NegA xor NegB
24963 bool NegMul = (NegA != NegB);
24965 A = A.getOperand(0);
24967 B = B.getOperand(0);
24969 C = C.getOperand(0);
24973 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
24975 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
24977 return DAG.getNode(Opcode, dl, VT, A, B, C);
24980 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
24981 TargetLowering::DAGCombinerInfo &DCI,
24982 const X86Subtarget *Subtarget) {
24983 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
24984 // (and (i32 x86isd::setcc_carry), 1)
24985 // This eliminates the zext. This transformation is necessary because
24986 // ISD::SETCC is always legalized to i8.
24988 SDValue N0 = N->getOperand(0);
24989 EVT VT = N->getValueType(0);
24991 if (N0.getOpcode() == ISD::AND &&
24993 N0.getOperand(0).hasOneUse()) {
24994 SDValue N00 = N0.getOperand(0);
24995 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24996 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24997 if (!C || C->getZExtValue() != 1)
24999 return DAG.getNode(ISD::AND, dl, VT,
25000 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25001 N00.getOperand(0), N00.getOperand(1)),
25002 DAG.getConstant(1, VT));
25006 if (N0.getOpcode() == ISD::TRUNCATE &&
25008 N0.getOperand(0).hasOneUse()) {
25009 SDValue N00 = N0.getOperand(0);
25010 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25011 return DAG.getNode(ISD::AND, dl, VT,
25012 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25013 N00.getOperand(0), N00.getOperand(1)),
25014 DAG.getConstant(1, VT));
25017 if (VT.is256BitVector()) {
25018 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
25023 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
25024 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
25025 // This exposes the zext to the udivrem lowering, so that it directly extends
25026 // from AH (which we otherwise need to do contortions to access).
25027 if (N0.getOpcode() == ISD::UDIVREM &&
25028 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
25029 (VT == MVT::i32 || VT == MVT::i64)) {
25030 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25031 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
25032 N0.getOperand(0), N0.getOperand(1));
25033 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25034 return R.getValue(1);
25040 // Optimize x == -y --> x+y == 0
25041 // x != -y --> x+y != 0
25042 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
25043 const X86Subtarget* Subtarget) {
25044 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
25045 SDValue LHS = N->getOperand(0);
25046 SDValue RHS = N->getOperand(1);
25047 EVT VT = N->getValueType(0);
25050 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
25051 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
25052 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
25053 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25054 LHS.getValueType(), RHS, LHS.getOperand(1));
25055 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25056 addV, DAG.getConstant(0, addV.getValueType()), CC);
25058 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
25059 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
25060 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
25061 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25062 RHS.getValueType(), LHS, RHS.getOperand(1));
25063 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25064 addV, DAG.getConstant(0, addV.getValueType()), CC);
25067 if (VT.getScalarType() == MVT::i1) {
25068 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25069 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25070 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
25071 if (!IsSEXT0 && !IsVZero0)
25073 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
25074 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25075 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25077 if (!IsSEXT1 && !IsVZero1)
25080 if (IsSEXT0 && IsVZero1) {
25081 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
25082 if (CC == ISD::SETEQ)
25083 return DAG.getNOT(DL, LHS.getOperand(0), VT);
25084 return LHS.getOperand(0);
25086 if (IsSEXT1 && IsVZero0) {
25087 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
25088 if (CC == ISD::SETEQ)
25089 return DAG.getNOT(DL, RHS.getOperand(0), VT);
25090 return RHS.getOperand(0);
25097 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
25098 const X86Subtarget *Subtarget) {
25100 MVT VT = N->getOperand(1)->getSimpleValueType(0);
25101 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
25102 "X86insertps is only defined for v4x32");
25104 SDValue Ld = N->getOperand(1);
25105 if (MayFoldLoad(Ld)) {
25106 // Extract the countS bits from the immediate so we can get the proper
25107 // address when narrowing the vector load to a specific element.
25108 // When the second source op is a memory address, interps doesn't use
25109 // countS and just gets an f32 from that address.
25110 unsigned DestIndex =
25111 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
25112 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
25116 // Create this as a scalar to vector to match the instruction pattern.
25117 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
25118 // countS bits are ignored when loading from memory on insertps, which
25119 // means we don't need to explicitly set them to 0.
25120 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
25121 LoadScalarToVector, N->getOperand(2));
25124 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
25125 // as "sbb reg,reg", since it can be extended without zext and produces
25126 // an all-ones bit which is more useful than 0/1 in some cases.
25127 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
25130 return DAG.getNode(ISD::AND, DL, VT,
25131 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25132 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
25133 DAG.getConstant(1, VT));
25134 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
25135 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
25136 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25137 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
25140 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
25141 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
25142 TargetLowering::DAGCombinerInfo &DCI,
25143 const X86Subtarget *Subtarget) {
25145 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
25146 SDValue EFLAGS = N->getOperand(1);
25148 if (CC == X86::COND_A) {
25149 // Try to convert COND_A into COND_B in an attempt to facilitate
25150 // materializing "setb reg".
25152 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
25153 // cannot take an immediate as its first operand.
25155 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
25156 EFLAGS.getValueType().isInteger() &&
25157 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
25158 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
25159 EFLAGS.getNode()->getVTList(),
25160 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
25161 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
25162 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
25166 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
25167 // a zext and produces an all-ones bit which is more useful than 0/1 in some
25169 if (CC == X86::COND_B)
25170 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
25174 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25175 if (Flags.getNode()) {
25176 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25177 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
25183 // Optimize branch condition evaluation.
25185 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
25186 TargetLowering::DAGCombinerInfo &DCI,
25187 const X86Subtarget *Subtarget) {
25189 SDValue Chain = N->getOperand(0);
25190 SDValue Dest = N->getOperand(1);
25191 SDValue EFLAGS = N->getOperand(3);
25192 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
25196 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25197 if (Flags.getNode()) {
25198 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25199 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
25206 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
25207 SelectionDAG &DAG) {
25208 // Take advantage of vector comparisons producing 0 or -1 in each lane to
25209 // optimize away operation when it's from a constant.
25211 // The general transformation is:
25212 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
25213 // AND(VECTOR_CMP(x,y), constant2)
25214 // constant2 = UNARYOP(constant)
25216 // Early exit if this isn't a vector operation, the operand of the
25217 // unary operation isn't a bitwise AND, or if the sizes of the operations
25218 // aren't the same.
25219 EVT VT = N->getValueType(0);
25220 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
25221 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
25222 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
25225 // Now check that the other operand of the AND is a constant. We could
25226 // make the transformation for non-constant splats as well, but it's unclear
25227 // that would be a benefit as it would not eliminate any operations, just
25228 // perform one more step in scalar code before moving to the vector unit.
25229 if (BuildVectorSDNode *BV =
25230 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
25231 // Bail out if the vector isn't a constant.
25232 if (!BV->isConstant())
25235 // Everything checks out. Build up the new and improved node.
25237 EVT IntVT = BV->getValueType(0);
25238 // Create a new constant of the appropriate type for the transformed
25240 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
25241 // The AND node needs bitcasts to/from an integer vector type around it.
25242 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
25243 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
25244 N->getOperand(0)->getOperand(0), MaskConst);
25245 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
25252 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25253 const X86TargetLowering *XTLI) {
25254 // First try to optimize away the conversion entirely when it's
25255 // conditionally from a constant. Vectors only.
25256 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
25257 if (Res != SDValue())
25260 // Now move on to more general possibilities.
25261 SDValue Op0 = N->getOperand(0);
25262 EVT InVT = Op0->getValueType(0);
25264 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
25265 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
25267 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
25268 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
25269 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
25272 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
25273 // a 32-bit target where SSE doesn't support i64->FP operations.
25274 if (Op0.getOpcode() == ISD::LOAD) {
25275 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
25276 EVT VT = Ld->getValueType(0);
25277 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
25278 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
25279 !XTLI->getSubtarget()->is64Bit() &&
25281 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
25282 Ld->getChain(), Op0, DAG);
25283 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
25290 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
25291 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
25292 X86TargetLowering::DAGCombinerInfo &DCI) {
25293 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
25294 // the result is either zero or one (depending on the input carry bit).
25295 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
25296 if (X86::isZeroNode(N->getOperand(0)) &&
25297 X86::isZeroNode(N->getOperand(1)) &&
25298 // We don't have a good way to replace an EFLAGS use, so only do this when
25300 SDValue(N, 1).use_empty()) {
25302 EVT VT = N->getValueType(0);
25303 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
25304 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
25305 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
25306 DAG.getConstant(X86::COND_B,MVT::i8),
25308 DAG.getConstant(1, VT));
25309 return DCI.CombineTo(N, Res1, CarryOut);
25315 // fold (add Y, (sete X, 0)) -> adc 0, Y
25316 // (add Y, (setne X, 0)) -> sbb -1, Y
25317 // (sub (sete X, 0), Y) -> sbb 0, Y
25318 // (sub (setne X, 0), Y) -> adc -1, Y
25319 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
25322 // Look through ZExts.
25323 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
25324 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25327 SDValue SetCC = Ext.getOperand(0);
25328 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25331 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25332 if (CC != X86::COND_E && CC != X86::COND_NE)
25335 SDValue Cmp = SetCC.getOperand(1);
25336 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25337 !X86::isZeroNode(Cmp.getOperand(1)) ||
25338 !Cmp.getOperand(0).getValueType().isInteger())
25341 SDValue CmpOp0 = Cmp.getOperand(0);
25342 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25343 DAG.getConstant(1, CmpOp0.getValueType()));
25345 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25346 if (CC == X86::COND_NE)
25347 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25348 DL, OtherVal.getValueType(), OtherVal,
25349 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
25350 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25351 DL, OtherVal.getValueType(), OtherVal,
25352 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
25355 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25356 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25357 const X86Subtarget *Subtarget) {
25358 EVT VT = N->getValueType(0);
25359 SDValue Op0 = N->getOperand(0);
25360 SDValue Op1 = N->getOperand(1);
25362 // Try to synthesize horizontal adds from adds of shuffles.
25363 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25364 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25365 isHorizontalBinOp(Op0, Op1, true))
25366 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25368 return OptimizeConditionalInDecrement(N, DAG);
25371 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25372 const X86Subtarget *Subtarget) {
25373 SDValue Op0 = N->getOperand(0);
25374 SDValue Op1 = N->getOperand(1);
25376 // X86 can't encode an immediate LHS of a sub. See if we can push the
25377 // negation into a preceding instruction.
25378 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25379 // If the RHS of the sub is a XOR with one use and a constant, invert the
25380 // immediate. Then add one to the LHS of the sub so we can turn
25381 // X-Y -> X+~Y+1, saving one register.
25382 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25383 isa<ConstantSDNode>(Op1.getOperand(1))) {
25384 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25385 EVT VT = Op0.getValueType();
25386 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25388 DAG.getConstant(~XorC, VT));
25389 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25390 DAG.getConstant(C->getAPIntValue()+1, VT));
25394 // Try to synthesize horizontal adds from adds of shuffles.
25395 EVT VT = N->getValueType(0);
25396 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25397 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25398 isHorizontalBinOp(Op0, Op1, true))
25399 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25401 return OptimizeConditionalInDecrement(N, DAG);
25404 /// performVZEXTCombine - Performs build vector combines
25405 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25406 TargetLowering::DAGCombinerInfo &DCI,
25407 const X86Subtarget *Subtarget) {
25409 MVT VT = N->getSimpleValueType(0);
25410 SDValue Op = N->getOperand(0);
25411 MVT OpVT = Op.getSimpleValueType();
25412 MVT OpEltVT = OpVT.getVectorElementType();
25413 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25415 // (vzext (bitcast (vzext (x)) -> (vzext x)
25417 while (V.getOpcode() == ISD::BITCAST)
25418 V = V.getOperand(0);
25420 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25421 MVT InnerVT = V.getSimpleValueType();
25422 MVT InnerEltVT = InnerVT.getVectorElementType();
25424 // If the element sizes match exactly, we can just do one larger vzext. This
25425 // is always an exact type match as vzext operates on integer types.
25426 if (OpEltVT == InnerEltVT) {
25427 assert(OpVT == InnerVT && "Types must match for vzext!");
25428 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25431 // The only other way we can combine them is if only a single element of the
25432 // inner vzext is used in the input to the outer vzext.
25433 if (InnerEltVT.getSizeInBits() < InputBits)
25436 // In this case, the inner vzext is completely dead because we're going to
25437 // only look at bits inside of the low element. Just do the outer vzext on
25438 // a bitcast of the input to the inner.
25439 return DAG.getNode(X86ISD::VZEXT, DL, VT,
25440 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
25443 // Check if we can bypass extracting and re-inserting an element of an input
25444 // vector. Essentialy:
25445 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25446 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25447 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25448 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25449 SDValue ExtractedV = V.getOperand(0);
25450 SDValue OrigV = ExtractedV.getOperand(0);
25451 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25452 if (ExtractIdx->getZExtValue() == 0) {
25453 MVT OrigVT = OrigV.getSimpleValueType();
25454 // Extract a subvector if necessary...
25455 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25456 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25457 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25458 OrigVT.getVectorNumElements() / Ratio);
25459 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25460 DAG.getIntPtrConstant(0));
25462 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
25463 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25470 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25471 DAGCombinerInfo &DCI) const {
25472 SelectionDAG &DAG = DCI.DAG;
25473 switch (N->getOpcode()) {
25475 case ISD::EXTRACT_VECTOR_ELT:
25476 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
25479 case X86ISD::SHRUNKBLEND:
25480 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
25481 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
25482 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
25483 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
25484 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
25485 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
25488 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
25489 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
25490 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
25491 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
25492 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
25493 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
25494 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
25495 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
25496 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
25498 case X86ISD::FOR: return PerformFORCombine(N, DAG);
25500 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
25501 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
25502 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
25503 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
25504 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
25505 case ISD::ANY_EXTEND:
25506 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
25507 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
25508 case ISD::SIGN_EXTEND_INREG:
25509 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
25510 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
25511 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
25512 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
25513 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
25514 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
25515 case X86ISD::SHUFP: // Handle all target specific shuffles
25516 case X86ISD::PALIGNR:
25517 case X86ISD::UNPCKH:
25518 case X86ISD::UNPCKL:
25519 case X86ISD::MOVHLPS:
25520 case X86ISD::MOVLHPS:
25521 case X86ISD::PSHUFB:
25522 case X86ISD::PSHUFD:
25523 case X86ISD::PSHUFHW:
25524 case X86ISD::PSHUFLW:
25525 case X86ISD::MOVSS:
25526 case X86ISD::MOVSD:
25527 case X86ISD::VPERMILPI:
25528 case X86ISD::VPERM2X128:
25529 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
25530 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
25531 case ISD::INTRINSIC_WO_CHAIN:
25532 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
25533 case X86ISD::INSERTPS:
25534 return PerformINSERTPSCombine(N, DAG, Subtarget);
25535 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
25541 /// isTypeDesirableForOp - Return true if the target has native support for
25542 /// the specified value type and it is 'desirable' to use the type for the
25543 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
25544 /// instruction encodings are longer and some i16 instructions are slow.
25545 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
25546 if (!isTypeLegal(VT))
25548 if (VT != MVT::i16)
25555 case ISD::SIGN_EXTEND:
25556 case ISD::ZERO_EXTEND:
25557 case ISD::ANY_EXTEND:
25570 /// IsDesirableToPromoteOp - This method query the target whether it is
25571 /// beneficial for dag combiner to promote the specified node. If true, it
25572 /// should return the desired promotion type by reference.
25573 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25574 EVT VT = Op.getValueType();
25575 if (VT != MVT::i16)
25578 bool Promote = false;
25579 bool Commute = false;
25580 switch (Op.getOpcode()) {
25583 LoadSDNode *LD = cast<LoadSDNode>(Op);
25584 // If the non-extending load has a single use and it's not live out, then it
25585 // might be folded.
25586 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25587 Op.hasOneUse()*/) {
25588 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25589 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25590 // The only case where we'd want to promote LOAD (rather then it being
25591 // promoted as an operand is when it's only use is liveout.
25592 if (UI->getOpcode() != ISD::CopyToReg)
25599 case ISD::SIGN_EXTEND:
25600 case ISD::ZERO_EXTEND:
25601 case ISD::ANY_EXTEND:
25606 SDValue N0 = Op.getOperand(0);
25607 // Look out for (store (shl (load), x)).
25608 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25621 SDValue N0 = Op.getOperand(0);
25622 SDValue N1 = Op.getOperand(1);
25623 if (!Commute && MayFoldLoad(N1))
25625 // Avoid disabling potential load folding opportunities.
25626 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25628 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25638 //===----------------------------------------------------------------------===//
25639 // X86 Inline Assembly Support
25640 //===----------------------------------------------------------------------===//
25643 // Helper to match a string separated by whitespace.
25644 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
25645 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
25647 for (unsigned i = 0, e = args.size(); i != e; ++i) {
25648 StringRef piece(*args[i]);
25649 if (!s.startswith(piece)) // Check if the piece matches.
25652 s = s.substr(piece.size());
25653 StringRef::size_type pos = s.find_first_not_of(" \t");
25654 if (pos == 0) // We matched a prefix.
25662 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
25665 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25667 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25668 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25669 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25670 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25672 if (AsmPieces.size() == 3)
25674 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25681 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25682 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25684 std::string AsmStr = IA->getAsmString();
25686 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25687 if (!Ty || Ty->getBitWidth() % 16 != 0)
25690 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25691 SmallVector<StringRef, 4> AsmPieces;
25692 SplitString(AsmStr, AsmPieces, ";\n");
25694 switch (AsmPieces.size()) {
25695 default: return false;
25697 // FIXME: this should verify that we are targeting a 486 or better. If not,
25698 // we will turn this bswap into something that will be lowered to logical
25699 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25700 // lower so don't worry about this.
25702 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
25703 matchAsm(AsmPieces[0], "bswapl", "$0") ||
25704 matchAsm(AsmPieces[0], "bswapq", "$0") ||
25705 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
25706 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
25707 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
25708 // No need to check constraints, nothing other than the equivalent of
25709 // "=r,0" would be valid here.
25710 return IntrinsicLowering::LowerToByteSwap(CI);
25713 // rorw $$8, ${0:w} --> llvm.bswap.i16
25714 if (CI->getType()->isIntegerTy(16) &&
25715 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25716 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
25717 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
25719 const std::string &ConstraintsStr = IA->getConstraintString();
25720 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25721 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25722 if (clobbersFlagRegisters(AsmPieces))
25723 return IntrinsicLowering::LowerToByteSwap(CI);
25727 if (CI->getType()->isIntegerTy(32) &&
25728 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25729 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
25730 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
25731 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
25733 const std::string &ConstraintsStr = IA->getConstraintString();
25734 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25735 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25736 if (clobbersFlagRegisters(AsmPieces))
25737 return IntrinsicLowering::LowerToByteSwap(CI);
25740 if (CI->getType()->isIntegerTy(64)) {
25741 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25742 if (Constraints.size() >= 2 &&
25743 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25744 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25745 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25746 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
25747 matchAsm(AsmPieces[1], "bswap", "%edx") &&
25748 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
25749 return IntrinsicLowering::LowerToByteSwap(CI);
25757 /// getConstraintType - Given a constraint letter, return the type of
25758 /// constraint it is for this target.
25759 X86TargetLowering::ConstraintType
25760 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
25761 if (Constraint.size() == 1) {
25762 switch (Constraint[0]) {
25773 return C_RegisterClass;
25797 return TargetLowering::getConstraintType(Constraint);
25800 /// Examine constraint type and operand type and determine a weight value.
25801 /// This object must already have been set up with the operand type
25802 /// and the current alternative constraint selected.
25803 TargetLowering::ConstraintWeight
25804 X86TargetLowering::getSingleConstraintMatchWeight(
25805 AsmOperandInfo &info, const char *constraint) const {
25806 ConstraintWeight weight = CW_Invalid;
25807 Value *CallOperandVal = info.CallOperandVal;
25808 // If we don't have a value, we can't do a match,
25809 // but allow it at the lowest weight.
25810 if (!CallOperandVal)
25812 Type *type = CallOperandVal->getType();
25813 // Look at the constraint type.
25814 switch (*constraint) {
25816 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
25827 if (CallOperandVal->getType()->isIntegerTy())
25828 weight = CW_SpecificReg;
25833 if (type->isFloatingPointTy())
25834 weight = CW_SpecificReg;
25837 if (type->isX86_MMXTy() && Subtarget->hasMMX())
25838 weight = CW_SpecificReg;
25842 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
25843 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
25844 weight = CW_Register;
25847 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
25848 if (C->getZExtValue() <= 31)
25849 weight = CW_Constant;
25853 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25854 if (C->getZExtValue() <= 63)
25855 weight = CW_Constant;
25859 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25860 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
25861 weight = CW_Constant;
25865 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25866 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
25867 weight = CW_Constant;
25871 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25872 if (C->getZExtValue() <= 3)
25873 weight = CW_Constant;
25877 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25878 if (C->getZExtValue() <= 0xff)
25879 weight = CW_Constant;
25884 if (dyn_cast<ConstantFP>(CallOperandVal)) {
25885 weight = CW_Constant;
25889 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25890 if ((C->getSExtValue() >= -0x80000000LL) &&
25891 (C->getSExtValue() <= 0x7fffffffLL))
25892 weight = CW_Constant;
25896 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25897 if (C->getZExtValue() <= 0xffffffff)
25898 weight = CW_Constant;
25905 /// LowerXConstraint - try to replace an X constraint, which matches anything,
25906 /// with another that has more specific requirements based on the type of the
25907 /// corresponding operand.
25908 const char *X86TargetLowering::
25909 LowerXConstraint(EVT ConstraintVT) const {
25910 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
25911 // 'f' like normal targets.
25912 if (ConstraintVT.isFloatingPoint()) {
25913 if (Subtarget->hasSSE2())
25915 if (Subtarget->hasSSE1())
25919 return TargetLowering::LowerXConstraint(ConstraintVT);
25922 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
25923 /// vector. If it is invalid, don't add anything to Ops.
25924 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
25925 std::string &Constraint,
25926 std::vector<SDValue>&Ops,
25927 SelectionDAG &DAG) const {
25930 // Only support length 1 constraints for now.
25931 if (Constraint.length() > 1) return;
25933 char ConstraintLetter = Constraint[0];
25934 switch (ConstraintLetter) {
25937 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25938 if (C->getZExtValue() <= 31) {
25939 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25945 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25946 if (C->getZExtValue() <= 63) {
25947 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25953 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25954 if (isInt<8>(C->getSExtValue())) {
25955 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25961 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25962 if (C->getZExtValue() <= 255) {
25963 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25969 // 32-bit signed value
25970 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25971 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25972 C->getSExtValue())) {
25973 // Widen to 64 bits here to get it sign extended.
25974 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
25977 // FIXME gcc accepts some relocatable values here too, but only in certain
25978 // memory models; it's complicated.
25983 // 32-bit unsigned value
25984 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25985 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25986 C->getZExtValue())) {
25987 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25991 // FIXME gcc accepts some relocatable values here too, but only in certain
25992 // memory models; it's complicated.
25996 // Literal immediates are always ok.
25997 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
25998 // Widen to 64 bits here to get it sign extended.
25999 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
26003 // In any sort of PIC mode addresses need to be computed at runtime by
26004 // adding in a register or some sort of table lookup. These can't
26005 // be used as immediates.
26006 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
26009 // If we are in non-pic codegen mode, we allow the address of a global (with
26010 // an optional displacement) to be used with 'i'.
26011 GlobalAddressSDNode *GA = nullptr;
26012 int64_t Offset = 0;
26014 // Match either (GA), (GA+C), (GA+C1+C2), etc.
26016 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
26017 Offset += GA->getOffset();
26019 } else if (Op.getOpcode() == ISD::ADD) {
26020 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26021 Offset += C->getZExtValue();
26022 Op = Op.getOperand(0);
26025 } else if (Op.getOpcode() == ISD::SUB) {
26026 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26027 Offset += -C->getZExtValue();
26028 Op = Op.getOperand(0);
26033 // Otherwise, this isn't something we can handle, reject it.
26037 const GlobalValue *GV = GA->getGlobal();
26038 // If we require an extra load to get this address, as in PIC mode, we
26039 // can't accept it.
26040 if (isGlobalStubReference(
26041 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
26044 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
26045 GA->getValueType(0), Offset);
26050 if (Result.getNode()) {
26051 Ops.push_back(Result);
26054 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
26057 std::pair<unsigned, const TargetRegisterClass*>
26058 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
26060 // First, see if this is a constraint that directly corresponds to an LLVM
26062 if (Constraint.size() == 1) {
26063 // GCC Constraint Letters
26064 switch (Constraint[0]) {
26066 // TODO: Slight differences here in allocation order and leaving
26067 // RIP in the class. Do they matter any more here than they do
26068 // in the normal allocation?
26069 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
26070 if (Subtarget->is64Bit()) {
26071 if (VT == MVT::i32 || VT == MVT::f32)
26072 return std::make_pair(0U, &X86::GR32RegClass);
26073 if (VT == MVT::i16)
26074 return std::make_pair(0U, &X86::GR16RegClass);
26075 if (VT == MVT::i8 || VT == MVT::i1)
26076 return std::make_pair(0U, &X86::GR8RegClass);
26077 if (VT == MVT::i64 || VT == MVT::f64)
26078 return std::make_pair(0U, &X86::GR64RegClass);
26081 // 32-bit fallthrough
26082 case 'Q': // Q_REGS
26083 if (VT == MVT::i32 || VT == MVT::f32)
26084 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
26085 if (VT == MVT::i16)
26086 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
26087 if (VT == MVT::i8 || VT == MVT::i1)
26088 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
26089 if (VT == MVT::i64)
26090 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
26092 case 'r': // GENERAL_REGS
26093 case 'l': // INDEX_REGS
26094 if (VT == MVT::i8 || VT == MVT::i1)
26095 return std::make_pair(0U, &X86::GR8RegClass);
26096 if (VT == MVT::i16)
26097 return std::make_pair(0U, &X86::GR16RegClass);
26098 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
26099 return std::make_pair(0U, &X86::GR32RegClass);
26100 return std::make_pair(0U, &X86::GR64RegClass);
26101 case 'R': // LEGACY_REGS
26102 if (VT == MVT::i8 || VT == MVT::i1)
26103 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
26104 if (VT == MVT::i16)
26105 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
26106 if (VT == MVT::i32 || !Subtarget->is64Bit())
26107 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
26108 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
26109 case 'f': // FP Stack registers.
26110 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
26111 // value to the correct fpstack register class.
26112 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
26113 return std::make_pair(0U, &X86::RFP32RegClass);
26114 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
26115 return std::make_pair(0U, &X86::RFP64RegClass);
26116 return std::make_pair(0U, &X86::RFP80RegClass);
26117 case 'y': // MMX_REGS if MMX allowed.
26118 if (!Subtarget->hasMMX()) break;
26119 return std::make_pair(0U, &X86::VR64RegClass);
26120 case 'Y': // SSE_REGS if SSE2 allowed
26121 if (!Subtarget->hasSSE2()) break;
26123 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
26124 if (!Subtarget->hasSSE1()) break;
26126 switch (VT.SimpleTy) {
26128 // Scalar SSE types.
26131 return std::make_pair(0U, &X86::FR32RegClass);
26134 return std::make_pair(0U, &X86::FR64RegClass);
26142 return std::make_pair(0U, &X86::VR128RegClass);
26150 return std::make_pair(0U, &X86::VR256RegClass);
26155 return std::make_pair(0U, &X86::VR512RegClass);
26161 // Use the default implementation in TargetLowering to convert the register
26162 // constraint into a member of a register class.
26163 std::pair<unsigned, const TargetRegisterClass*> Res;
26164 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
26166 // Not found as a standard register?
26168 // Map st(0) -> st(7) -> ST0
26169 if (Constraint.size() == 7 && Constraint[0] == '{' &&
26170 tolower(Constraint[1]) == 's' &&
26171 tolower(Constraint[2]) == 't' &&
26172 Constraint[3] == '(' &&
26173 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
26174 Constraint[5] == ')' &&
26175 Constraint[6] == '}') {
26177 Res.first = X86::FP0+Constraint[4]-'0';
26178 Res.second = &X86::RFP80RegClass;
26182 // GCC allows "st(0)" to be called just plain "st".
26183 if (StringRef("{st}").equals_lower(Constraint)) {
26184 Res.first = X86::FP0;
26185 Res.second = &X86::RFP80RegClass;
26190 if (StringRef("{flags}").equals_lower(Constraint)) {
26191 Res.first = X86::EFLAGS;
26192 Res.second = &X86::CCRRegClass;
26196 // 'A' means EAX + EDX.
26197 if (Constraint == "A") {
26198 Res.first = X86::EAX;
26199 Res.second = &X86::GR32_ADRegClass;
26205 // Otherwise, check to see if this is a register class of the wrong value
26206 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
26207 // turn into {ax},{dx}.
26208 if (Res.second->hasType(VT))
26209 return Res; // Correct type already, nothing to do.
26211 // All of the single-register GCC register classes map their values onto
26212 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
26213 // really want an 8-bit or 32-bit register, map to the appropriate register
26214 // class and return the appropriate register.
26215 if (Res.second == &X86::GR16RegClass) {
26216 if (VT == MVT::i8 || VT == MVT::i1) {
26217 unsigned DestReg = 0;
26218 switch (Res.first) {
26220 case X86::AX: DestReg = X86::AL; break;
26221 case X86::DX: DestReg = X86::DL; break;
26222 case X86::CX: DestReg = X86::CL; break;
26223 case X86::BX: DestReg = X86::BL; break;
26226 Res.first = DestReg;
26227 Res.second = &X86::GR8RegClass;
26229 } else if (VT == MVT::i32 || VT == MVT::f32) {
26230 unsigned DestReg = 0;
26231 switch (Res.first) {
26233 case X86::AX: DestReg = X86::EAX; break;
26234 case X86::DX: DestReg = X86::EDX; break;
26235 case X86::CX: DestReg = X86::ECX; break;
26236 case X86::BX: DestReg = X86::EBX; break;
26237 case X86::SI: DestReg = X86::ESI; break;
26238 case X86::DI: DestReg = X86::EDI; break;
26239 case X86::BP: DestReg = X86::EBP; break;
26240 case X86::SP: DestReg = X86::ESP; break;
26243 Res.first = DestReg;
26244 Res.second = &X86::GR32RegClass;
26246 } else if (VT == MVT::i64 || VT == MVT::f64) {
26247 unsigned DestReg = 0;
26248 switch (Res.first) {
26250 case X86::AX: DestReg = X86::RAX; break;
26251 case X86::DX: DestReg = X86::RDX; break;
26252 case X86::CX: DestReg = X86::RCX; break;
26253 case X86::BX: DestReg = X86::RBX; break;
26254 case X86::SI: DestReg = X86::RSI; break;
26255 case X86::DI: DestReg = X86::RDI; break;
26256 case X86::BP: DestReg = X86::RBP; break;
26257 case X86::SP: DestReg = X86::RSP; break;
26260 Res.first = DestReg;
26261 Res.second = &X86::GR64RegClass;
26264 } else if (Res.second == &X86::FR32RegClass ||
26265 Res.second == &X86::FR64RegClass ||
26266 Res.second == &X86::VR128RegClass ||
26267 Res.second == &X86::VR256RegClass ||
26268 Res.second == &X86::FR32XRegClass ||
26269 Res.second == &X86::FR64XRegClass ||
26270 Res.second == &X86::VR128XRegClass ||
26271 Res.second == &X86::VR256XRegClass ||
26272 Res.second == &X86::VR512RegClass) {
26273 // Handle references to XMM physical registers that got mapped into the
26274 // wrong class. This can happen with constraints like {xmm0} where the
26275 // target independent register mapper will just pick the first match it can
26276 // find, ignoring the required type.
26278 if (VT == MVT::f32 || VT == MVT::i32)
26279 Res.second = &X86::FR32RegClass;
26280 else if (VT == MVT::f64 || VT == MVT::i64)
26281 Res.second = &X86::FR64RegClass;
26282 else if (X86::VR128RegClass.hasType(VT))
26283 Res.second = &X86::VR128RegClass;
26284 else if (X86::VR256RegClass.hasType(VT))
26285 Res.second = &X86::VR256RegClass;
26286 else if (X86::VR512RegClass.hasType(VT))
26287 Res.second = &X86::VR512RegClass;
26293 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
26295 // Scaling factors are not free at all.
26296 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
26297 // will take 2 allocations in the out of order engine instead of 1
26298 // for plain addressing mode, i.e. inst (reg1).
26300 // vaddps (%rsi,%drx), %ymm0, %ymm1
26301 // Requires two allocations (one for the load, one for the computation)
26303 // vaddps (%rsi), %ymm0, %ymm1
26304 // Requires just 1 allocation, i.e., freeing allocations for other operations
26305 // and having less micro operations to execute.
26307 // For some X86 architectures, this is even worse because for instance for
26308 // stores, the complex addressing mode forces the instruction to use the
26309 // "load" ports instead of the dedicated "store" port.
26310 // E.g., on Haswell:
26311 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
26312 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
26313 if (isLegalAddressingMode(AM, Ty))
26314 // Scale represents reg2 * scale, thus account for 1
26315 // as soon as we use a second register.
26316 return AM.Scale != 0;
26320 bool X86TargetLowering::isTargetFTOL() const {
26321 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();