1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(true),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 static cl::opt<int> ReciprocalEstimateRefinementSteps(
75 "x86-recip-refinement-steps", cl::init(1),
76 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
77 "result of the hardware reciprocal estimate instruction."),
80 // Forward declarations.
81 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
84 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
85 SelectionDAG &DAG, SDLoc dl,
86 unsigned vectorWidth) {
87 assert((vectorWidth == 128 || vectorWidth == 256) &&
88 "Unsupported vector width");
89 EVT VT = Vec.getValueType();
90 EVT ElVT = VT.getVectorElementType();
91 unsigned Factor = VT.getSizeInBits()/vectorWidth;
92 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
93 VT.getVectorNumElements()/Factor);
95 // Extract from UNDEF is UNDEF.
96 if (Vec.getOpcode() == ISD::UNDEF)
97 return DAG.getUNDEF(ResultVT);
99 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
100 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
102 // This is the index of the first element of the vectorWidth-bit chunk
104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
107 // If the input is a buildvector just emit a smaller one.
108 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
109 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
110 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
113 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
114 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
120 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
121 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
122 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
123 /// instructions or a simple subregister reference. Idx is an index in the
124 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
125 /// lowering EXTRACT_VECTOR_ELT operations easier.
126 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
127 SelectionDAG &DAG, SDLoc dl) {
128 assert((Vec.getValueType().is256BitVector() ||
129 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
130 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
133 /// Generate a DAG to grab 256-bits from a 512-bit vector.
134 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
135 SelectionDAG &DAG, SDLoc dl) {
136 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
137 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
140 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
141 unsigned IdxVal, SelectionDAG &DAG,
142 SDLoc dl, unsigned vectorWidth) {
143 assert((vectorWidth == 128 || vectorWidth == 256) &&
144 "Unsupported vector width");
145 // Inserting UNDEF is Result
146 if (Vec.getOpcode() == ISD::UNDEF)
148 EVT VT = Vec.getValueType();
149 EVT ElVT = VT.getVectorElementType();
150 EVT ResultVT = Result.getValueType();
152 // Insert the relevant vectorWidth bits.
153 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
155 // This is the index of the first element of the vectorWidth-bit chunk
157 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
160 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
161 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
164 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
165 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
166 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
167 /// simple superregister reference. Idx is an index in the 128 bits
168 /// we want. It need not be aligned to a 128-bit boundary. That makes
169 /// lowering INSERT_VECTOR_ELT operations easier.
170 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
171 SelectionDAG &DAG,SDLoc dl) {
172 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
173 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
176 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
177 SelectionDAG &DAG, SDLoc dl) {
178 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
179 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
182 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
183 /// instructions. This is used because creating CONCAT_VECTOR nodes of
184 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
185 /// large BUILD_VECTORS.
186 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
187 unsigned NumElems, SelectionDAG &DAG,
189 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
190 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
193 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
194 unsigned NumElems, SelectionDAG &DAG,
196 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
197 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
200 // FIXME: This should stop caching the target machine as soon as
201 // we can remove resetOperationActions et al.
202 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
203 : TargetLowering(TM) {
204 Subtarget = &TM.getSubtarget<X86Subtarget>();
205 X86ScalarSSEf64 = Subtarget->hasSSE2();
206 X86ScalarSSEf32 = Subtarget->hasSSE1();
207 TD = getDataLayout();
209 resetOperationActions();
212 void X86TargetLowering::resetOperationActions() {
213 const TargetMachine &TM = getTargetMachine();
214 static bool FirstTimeThrough = true;
216 // If none of the target options have changed, then we don't need to reset the
217 // operation actions.
218 if (!FirstTimeThrough && TO == TM.Options) return;
220 if (!FirstTimeThrough) {
221 // Reinitialize the actions.
223 FirstTimeThrough = false;
228 // Set up the TargetLowering object.
229 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
231 // X86 is weird. It always uses i8 for shift amounts and setcc results.
232 setBooleanContents(ZeroOrOneBooleanContent);
233 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
234 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
236 // For 64-bit, since we have so many registers, use the ILP scheduler.
237 // For 32-bit, use the register pressure specific scheduling.
238 // For Atom, always use ILP scheduling.
239 if (Subtarget->isAtom())
240 setSchedulingPreference(Sched::ILP);
241 else if (Subtarget->is64Bit())
242 setSchedulingPreference(Sched::ILP);
244 setSchedulingPreference(Sched::RegPressure);
245 const X86RegisterInfo *RegInfo =
246 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
247 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
249 // Bypass expensive divides on Atom when compiling with O2.
250 if (TM.getOptLevel() >= CodeGenOpt::Default) {
251 if (Subtarget->hasSlowDivide32())
252 addBypassSlowDiv(32, 8);
253 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
254 addBypassSlowDiv(64, 16);
257 if (Subtarget->isTargetKnownWindowsMSVC()) {
258 // Setup Windows compiler runtime calls.
259 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
260 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
261 setLibcallName(RTLIB::SREM_I64, "_allrem");
262 setLibcallName(RTLIB::UREM_I64, "_aullrem");
263 setLibcallName(RTLIB::MUL_I64, "_allmul");
264 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
265 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
266 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
267 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
268 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
270 // The _ftol2 runtime function has an unusual calling conv, which
271 // is modeled by a special pseudo-instruction.
272 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
273 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
274 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
275 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
278 if (Subtarget->isTargetDarwin()) {
279 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
280 setUseUnderscoreSetJmp(false);
281 setUseUnderscoreLongJmp(false);
282 } else if (Subtarget->isTargetWindowsGNU()) {
283 // MS runtime is weird: it exports _setjmp, but longjmp!
284 setUseUnderscoreSetJmp(true);
285 setUseUnderscoreLongJmp(false);
287 setUseUnderscoreSetJmp(true);
288 setUseUnderscoreLongJmp(true);
291 // Set up the register classes.
292 addRegisterClass(MVT::i8, &X86::GR8RegClass);
293 addRegisterClass(MVT::i16, &X86::GR16RegClass);
294 addRegisterClass(MVT::i32, &X86::GR32RegClass);
295 if (Subtarget->is64Bit())
296 addRegisterClass(MVT::i64, &X86::GR64RegClass);
298 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
300 // We don't accept any truncstore of integer registers.
301 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
302 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
303 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
304 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
305 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
306 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
308 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
310 // SETOEQ and SETUNE require checking two conditions.
311 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
312 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
313 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
314 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
315 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
316 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
318 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
320 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
321 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
322 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
324 if (Subtarget->is64Bit()) {
325 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
326 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
327 } else if (!TM.Options.UseSoftFloat) {
328 // We have an algorithm for SSE2->double, and we turn this into a
329 // 64-bit FILD followed by conditional FADD for other targets.
330 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
331 // We have an algorithm for SSE2, and we turn this into a 64-bit
332 // FILD for other targets.
333 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
336 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
338 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
339 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
341 if (!TM.Options.UseSoftFloat) {
342 // SSE has no i16 to fp conversion, only i32
343 if (X86ScalarSSEf32) {
344 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
345 // f32 and f64 cases are Legal, f80 case is not
346 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
348 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
349 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
352 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
353 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
356 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
357 // are Legal, f80 is custom lowered.
358 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
359 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
361 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
363 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
364 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
366 if (X86ScalarSSEf32) {
367 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
368 // f32 and f64 cases are Legal, f80 case is not
369 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
371 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
372 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
375 // Handle FP_TO_UINT by promoting the destination to a larger signed
377 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
378 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
379 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
381 if (Subtarget->is64Bit()) {
382 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
383 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
384 } else if (!TM.Options.UseSoftFloat) {
385 // Since AVX is a superset of SSE3, only check for SSE here.
386 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
387 // Expand FP_TO_UINT into a select.
388 // FIXME: We would like to use a Custom expander here eventually to do
389 // the optimal thing for SSE vs. the default expansion in the legalizer.
390 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
392 // With SSE3 we can use fisttpll to convert to a signed i64; without
393 // SSE, we're stuck with a fistpll.
394 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
397 if (isTargetFTOL()) {
398 // Use the _ftol2 runtime function, which has a pseudo-instruction
399 // to handle its weird calling convention.
400 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
403 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
404 if (!X86ScalarSSEf64) {
405 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
406 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
407 if (Subtarget->is64Bit()) {
408 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
409 // Without SSE, i64->f64 goes through memory.
410 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
414 // Scalar integer divide and remainder are lowered to use operations that
415 // produce two results, to match the available instructions. This exposes
416 // the two-result form to trivial CSE, which is able to combine x/y and x%y
417 // into a single instruction.
419 // Scalar integer multiply-high is also lowered to use two-result
420 // operations, to match the available instructions. However, plain multiply
421 // (low) operations are left as Legal, as there are single-result
422 // instructions for this in x86. Using the two-result multiply instructions
423 // when both high and low results are needed must be arranged by dagcombine.
424 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
426 setOperationAction(ISD::MULHS, VT, Expand);
427 setOperationAction(ISD::MULHU, VT, Expand);
428 setOperationAction(ISD::SDIV, VT, Expand);
429 setOperationAction(ISD::UDIV, VT, Expand);
430 setOperationAction(ISD::SREM, VT, Expand);
431 setOperationAction(ISD::UREM, VT, Expand);
433 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
434 setOperationAction(ISD::ADDC, VT, Custom);
435 setOperationAction(ISD::ADDE, VT, Custom);
436 setOperationAction(ISD::SUBC, VT, Custom);
437 setOperationAction(ISD::SUBE, VT, Custom);
440 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
441 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
442 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
443 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
444 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
445 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
446 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
447 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
448 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
449 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
450 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
451 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
452 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
453 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
454 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
455 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
456 if (Subtarget->is64Bit())
457 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
458 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
459 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
460 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
461 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
462 setOperationAction(ISD::FREM , MVT::f32 , Expand);
463 setOperationAction(ISD::FREM , MVT::f64 , Expand);
464 setOperationAction(ISD::FREM , MVT::f80 , Expand);
465 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
467 // Promote the i8 variants and force them on up to i32 which has a shorter
469 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
470 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
471 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
472 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
473 if (Subtarget->hasBMI()) {
474 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
475 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
476 if (Subtarget->is64Bit())
477 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
479 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
480 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
481 if (Subtarget->is64Bit())
482 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
485 if (Subtarget->hasLZCNT()) {
486 // When promoting the i8 variants, force them to i32 for a shorter
488 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
489 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
490 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
491 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
492 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
493 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
494 if (Subtarget->is64Bit())
495 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
497 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
498 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
499 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
500 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
501 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
502 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
503 if (Subtarget->is64Bit()) {
504 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
509 // Special handling for half-precision floating point conversions.
510 // If we don't have F16C support, then lower half float conversions
511 // into library calls.
512 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
513 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
514 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
517 // There's never any support for operations beyond MVT::f32.
518 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
519 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
520 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
521 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
523 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
524 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
525 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
526 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
528 if (Subtarget->hasPOPCNT()) {
529 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
531 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
532 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
533 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
534 if (Subtarget->is64Bit())
535 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
538 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
540 if (!Subtarget->hasMOVBE())
541 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
543 // These should be promoted to a larger select which is supported.
544 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
545 // X86 wants to expand cmov itself.
546 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
547 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
548 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
549 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
550 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
551 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
552 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
553 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
554 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
555 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
556 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
557 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
558 if (Subtarget->is64Bit()) {
559 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
560 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
562 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
563 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
564 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
565 // support continuation, user-level threading, and etc.. As a result, no
566 // other SjLj exception interfaces are implemented and please don't build
567 // your own exception handling based on them.
568 // LLVM/Clang supports zero-cost DWARF exception handling.
569 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
570 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
573 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
574 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
575 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
576 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
577 if (Subtarget->is64Bit())
578 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
579 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
580 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
581 if (Subtarget->is64Bit()) {
582 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
583 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
584 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
585 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
586 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
588 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
589 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
590 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
591 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
592 if (Subtarget->is64Bit()) {
593 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
594 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
595 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
598 if (Subtarget->hasSSE1())
599 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
601 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
603 // Expand certain atomics
604 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
606 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
607 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
608 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
611 if (Subtarget->hasCmpxchg16b()) {
612 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
615 // FIXME - use subtarget debug flags
616 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
617 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
618 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
621 if (Subtarget->is64Bit()) {
622 setExceptionPointerRegister(X86::RAX);
623 setExceptionSelectorRegister(X86::RDX);
625 setExceptionPointerRegister(X86::EAX);
626 setExceptionSelectorRegister(X86::EDX);
628 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
629 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
631 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
632 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
634 setOperationAction(ISD::TRAP, MVT::Other, Legal);
635 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
637 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
638 setOperationAction(ISD::VASTART , MVT::Other, Custom);
639 setOperationAction(ISD::VAEND , MVT::Other, Expand);
640 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
641 // TargetInfo::X86_64ABIBuiltinVaList
642 setOperationAction(ISD::VAARG , MVT::Other, Custom);
643 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
645 // TargetInfo::CharPtrBuiltinVaList
646 setOperationAction(ISD::VAARG , MVT::Other, Expand);
647 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
650 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
651 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
653 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
655 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
656 // f32 and f64 use SSE.
657 // Set up the FP register classes.
658 addRegisterClass(MVT::f32, &X86::FR32RegClass);
659 addRegisterClass(MVT::f64, &X86::FR64RegClass);
661 // Use ANDPD to simulate FABS.
662 setOperationAction(ISD::FABS , MVT::f64, Custom);
663 setOperationAction(ISD::FABS , MVT::f32, Custom);
665 // Use XORP to simulate FNEG.
666 setOperationAction(ISD::FNEG , MVT::f64, Custom);
667 setOperationAction(ISD::FNEG , MVT::f32, Custom);
669 // Use ANDPD and ORPD to simulate FCOPYSIGN.
670 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
671 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
673 // Lower this to FGETSIGNx86 plus an AND.
674 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
675 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
677 // We don't support sin/cos/fmod
678 setOperationAction(ISD::FSIN , MVT::f64, Expand);
679 setOperationAction(ISD::FCOS , MVT::f64, Expand);
680 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
681 setOperationAction(ISD::FSIN , MVT::f32, Expand);
682 setOperationAction(ISD::FCOS , MVT::f32, Expand);
683 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
685 // Expand FP immediates into loads from the stack, except for the special
687 addLegalFPImmediate(APFloat(+0.0)); // xorpd
688 addLegalFPImmediate(APFloat(+0.0f)); // xorps
689 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
690 // Use SSE for f32, x87 for f64.
691 // Set up the FP register classes.
692 addRegisterClass(MVT::f32, &X86::FR32RegClass);
693 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
695 // Use ANDPS to simulate FABS.
696 setOperationAction(ISD::FABS , MVT::f32, Custom);
698 // Use XORP to simulate FNEG.
699 setOperationAction(ISD::FNEG , MVT::f32, Custom);
701 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
703 // Use ANDPS and ORPS to simulate FCOPYSIGN.
704 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
705 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
707 // We don't support sin/cos/fmod
708 setOperationAction(ISD::FSIN , MVT::f32, Expand);
709 setOperationAction(ISD::FCOS , MVT::f32, Expand);
710 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
712 // Special cases we handle for FP constants.
713 addLegalFPImmediate(APFloat(+0.0f)); // xorps
714 addLegalFPImmediate(APFloat(+0.0)); // FLD0
715 addLegalFPImmediate(APFloat(+1.0)); // FLD1
716 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
717 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
719 if (!TM.Options.UnsafeFPMath) {
720 setOperationAction(ISD::FSIN , MVT::f64, Expand);
721 setOperationAction(ISD::FCOS , MVT::f64, Expand);
722 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
724 } else if (!TM.Options.UseSoftFloat) {
725 // f32 and f64 in x87.
726 // Set up the FP register classes.
727 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
728 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
730 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
731 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
732 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
733 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
735 if (!TM.Options.UnsafeFPMath) {
736 setOperationAction(ISD::FSIN , MVT::f64, Expand);
737 setOperationAction(ISD::FSIN , MVT::f32, Expand);
738 setOperationAction(ISD::FCOS , MVT::f64, Expand);
739 setOperationAction(ISD::FCOS , MVT::f32, Expand);
740 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
741 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
743 addLegalFPImmediate(APFloat(+0.0)); // FLD0
744 addLegalFPImmediate(APFloat(+1.0)); // FLD1
745 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
746 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
747 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
748 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
749 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
750 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
753 // We don't support FMA.
754 setOperationAction(ISD::FMA, MVT::f64, Expand);
755 setOperationAction(ISD::FMA, MVT::f32, Expand);
757 // Long double always uses X87.
758 if (!TM.Options.UseSoftFloat) {
759 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
760 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
761 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
763 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
764 addLegalFPImmediate(TmpFlt); // FLD0
766 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
769 APFloat TmpFlt2(+1.0);
770 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
772 addLegalFPImmediate(TmpFlt2); // FLD1
773 TmpFlt2.changeSign();
774 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
777 if (!TM.Options.UnsafeFPMath) {
778 setOperationAction(ISD::FSIN , MVT::f80, Expand);
779 setOperationAction(ISD::FCOS , MVT::f80, Expand);
780 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
783 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
784 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
785 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
786 setOperationAction(ISD::FRINT, MVT::f80, Expand);
787 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
788 setOperationAction(ISD::FMA, MVT::f80, Expand);
791 // Always use a library call for pow.
792 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
793 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
794 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
796 setOperationAction(ISD::FLOG, MVT::f80, Expand);
797 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
798 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
799 setOperationAction(ISD::FEXP, MVT::f80, Expand);
800 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
801 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
802 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
804 // First set operation action for all vector types to either promote
805 // (for widening) or expand (for scalarization). Then we will selectively
806 // turn on ones that can be effectively codegen'd.
807 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
808 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
809 MVT VT = (MVT::SimpleValueType)i;
810 setOperationAction(ISD::ADD , VT, Expand);
811 setOperationAction(ISD::SUB , VT, Expand);
812 setOperationAction(ISD::FADD, VT, Expand);
813 setOperationAction(ISD::FNEG, VT, Expand);
814 setOperationAction(ISD::FSUB, VT, Expand);
815 setOperationAction(ISD::MUL , VT, Expand);
816 setOperationAction(ISD::FMUL, VT, Expand);
817 setOperationAction(ISD::SDIV, VT, Expand);
818 setOperationAction(ISD::UDIV, VT, Expand);
819 setOperationAction(ISD::FDIV, VT, Expand);
820 setOperationAction(ISD::SREM, VT, Expand);
821 setOperationAction(ISD::UREM, VT, Expand);
822 setOperationAction(ISD::LOAD, VT, Expand);
823 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
824 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
825 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
826 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
827 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
828 setOperationAction(ISD::FABS, VT, Expand);
829 setOperationAction(ISD::FSIN, VT, Expand);
830 setOperationAction(ISD::FSINCOS, VT, Expand);
831 setOperationAction(ISD::FCOS, VT, Expand);
832 setOperationAction(ISD::FSINCOS, VT, Expand);
833 setOperationAction(ISD::FREM, VT, Expand);
834 setOperationAction(ISD::FMA, VT, Expand);
835 setOperationAction(ISD::FPOWI, VT, Expand);
836 setOperationAction(ISD::FSQRT, VT, Expand);
837 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
838 setOperationAction(ISD::FFLOOR, VT, Expand);
839 setOperationAction(ISD::FCEIL, VT, Expand);
840 setOperationAction(ISD::FTRUNC, VT, Expand);
841 setOperationAction(ISD::FRINT, VT, Expand);
842 setOperationAction(ISD::FNEARBYINT, VT, Expand);
843 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
844 setOperationAction(ISD::MULHS, VT, Expand);
845 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
846 setOperationAction(ISD::MULHU, VT, Expand);
847 setOperationAction(ISD::SDIVREM, VT, Expand);
848 setOperationAction(ISD::UDIVREM, VT, Expand);
849 setOperationAction(ISD::FPOW, VT, Expand);
850 setOperationAction(ISD::CTPOP, VT, Expand);
851 setOperationAction(ISD::CTTZ, VT, Expand);
852 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
853 setOperationAction(ISD::CTLZ, VT, Expand);
854 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
855 setOperationAction(ISD::SHL, VT, Expand);
856 setOperationAction(ISD::SRA, VT, Expand);
857 setOperationAction(ISD::SRL, VT, Expand);
858 setOperationAction(ISD::ROTL, VT, Expand);
859 setOperationAction(ISD::ROTR, VT, Expand);
860 setOperationAction(ISD::BSWAP, VT, Expand);
861 setOperationAction(ISD::SETCC, VT, Expand);
862 setOperationAction(ISD::FLOG, VT, Expand);
863 setOperationAction(ISD::FLOG2, VT, Expand);
864 setOperationAction(ISD::FLOG10, VT, Expand);
865 setOperationAction(ISD::FEXP, VT, Expand);
866 setOperationAction(ISD::FEXP2, VT, Expand);
867 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
868 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
869 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
870 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
871 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
872 setOperationAction(ISD::TRUNCATE, VT, Expand);
873 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
874 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
875 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
876 setOperationAction(ISD::VSELECT, VT, Expand);
877 setOperationAction(ISD::SELECT_CC, VT, Expand);
878 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
879 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
880 setTruncStoreAction(VT,
881 (MVT::SimpleValueType)InnerVT, Expand);
882 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
883 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
885 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
886 // we have to deal with them whether we ask for Expansion or not. Setting
887 // Expand causes its own optimisation problems though, so leave them legal.
888 if (VT.getVectorElementType() == MVT::i1)
889 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
892 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
893 // with -msoft-float, disable use of MMX as well.
894 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
895 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
896 // No operations on x86mmx supported, everything uses intrinsics.
899 // MMX-sized vectors (other than x86mmx) are expected to be expanded
900 // into smaller operations.
901 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
902 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
903 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
904 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
905 setOperationAction(ISD::AND, MVT::v8i8, Expand);
906 setOperationAction(ISD::AND, MVT::v4i16, Expand);
907 setOperationAction(ISD::AND, MVT::v2i32, Expand);
908 setOperationAction(ISD::AND, MVT::v1i64, Expand);
909 setOperationAction(ISD::OR, MVT::v8i8, Expand);
910 setOperationAction(ISD::OR, MVT::v4i16, Expand);
911 setOperationAction(ISD::OR, MVT::v2i32, Expand);
912 setOperationAction(ISD::OR, MVT::v1i64, Expand);
913 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
914 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
915 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
916 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
917 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
918 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
919 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
920 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
921 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
922 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
923 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
924 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
925 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
926 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
927 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
928 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
929 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
931 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
932 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
934 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
935 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
936 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
937 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
938 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
939 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
940 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
941 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
942 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
943 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
944 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
945 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
946 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
949 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
950 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
952 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
953 // registers cannot be used even for integer operations.
954 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
955 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
956 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
957 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
959 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
960 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
961 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
962 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
963 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
964 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
965 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
966 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
967 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
968 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
969 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
970 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
971 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
972 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
973 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
974 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
975 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
976 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
977 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
978 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
979 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
980 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
982 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
983 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
984 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
985 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
987 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
988 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
989 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
990 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
991 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
993 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
994 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
995 MVT VT = (MVT::SimpleValueType)i;
996 // Do not attempt to custom lower non-power-of-2 vectors
997 if (!isPowerOf2_32(VT.getVectorNumElements()))
999 // Do not attempt to custom lower non-128-bit vectors
1000 if (!VT.is128BitVector())
1002 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1003 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1004 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1007 // We support custom legalizing of sext and anyext loads for specific
1008 // memory vector types which we can load as a scalar (or sequence of
1009 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1010 // loads these must work with a single scalar load.
1011 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1012 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1013 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1014 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1015 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1016 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1017 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1018 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1019 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1021 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1022 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1023 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1024 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1025 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1026 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1028 if (Subtarget->is64Bit()) {
1029 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1030 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1033 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1034 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1035 MVT VT = (MVT::SimpleValueType)i;
1037 // Do not attempt to promote non-128-bit vectors
1038 if (!VT.is128BitVector())
1041 setOperationAction(ISD::AND, VT, Promote);
1042 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1043 setOperationAction(ISD::OR, VT, Promote);
1044 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1045 setOperationAction(ISD::XOR, VT, Promote);
1046 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1047 setOperationAction(ISD::LOAD, VT, Promote);
1048 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1049 setOperationAction(ISD::SELECT, VT, Promote);
1050 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1053 // Custom lower v2i64 and v2f64 selects.
1054 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1055 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1056 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1057 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1059 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1060 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1062 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1063 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1064 // As there is no 64-bit GPR available, we need build a special custom
1065 // sequence to convert from v2i32 to v2f32.
1066 if (!Subtarget->is64Bit())
1067 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1069 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1070 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1072 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1074 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1075 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1076 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1079 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1080 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1081 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1082 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1083 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1084 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1085 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1086 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1087 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1088 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1089 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1091 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1092 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1093 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1094 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1095 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1096 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1097 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1098 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1099 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1100 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1102 // FIXME: Do we need to handle scalar-to-vector here?
1103 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1105 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1106 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1107 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1108 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1109 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1110 // There is no BLENDI for byte vectors. We don't need to custom lower
1111 // some vselects for now.
1112 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1114 // SSE41 brings specific instructions for doing vector sign extend even in
1115 // cases where we don't have SRA.
1116 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1117 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1118 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1120 // i8 and i16 vectors are custom because the source register and source
1121 // source memory operand types are not the same width. f32 vectors are
1122 // custom since the immediate controlling the insert encodes additional
1124 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1125 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1126 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1127 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1129 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1130 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1131 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1132 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1134 // FIXME: these should be Legal, but that's only for the case where
1135 // the index is constant. For now custom expand to deal with that.
1136 if (Subtarget->is64Bit()) {
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1138 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1142 if (Subtarget->hasSSE2()) {
1143 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1144 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1146 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1147 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1149 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1150 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1152 // In the customized shift lowering, the legal cases in AVX2 will be
1154 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1155 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1157 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1158 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1160 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1163 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1164 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1165 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1166 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1167 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1168 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1169 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1171 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1172 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1173 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1175 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1176 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1177 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1178 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1179 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1180 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1181 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1182 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1183 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1184 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1185 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1186 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1188 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1189 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1190 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1191 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1192 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1193 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1194 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1195 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1196 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1197 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1198 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1199 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1201 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1202 // even though v8i16 is a legal type.
1203 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1204 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1205 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1207 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1208 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1209 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1211 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1212 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1214 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1216 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1217 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1219 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1220 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1222 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1223 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1225 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1226 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1227 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1228 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1230 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1231 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1232 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1234 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1235 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1236 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1237 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1239 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1240 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1241 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1242 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1243 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1244 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1245 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1246 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1247 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1248 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1249 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1250 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1252 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1253 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1254 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1255 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1256 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1257 setOperationAction(ISD::FMA, MVT::f32, Legal);
1258 setOperationAction(ISD::FMA, MVT::f64, Legal);
1261 if (Subtarget->hasInt256()) {
1262 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1263 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1264 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1265 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1267 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1268 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1269 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1270 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1272 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1273 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1274 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1275 // Don't lower v32i8 because there is no 128-bit byte mul
1277 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1278 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1279 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1280 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1282 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1283 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1285 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1286 // when we have a 256bit-wide blend with immediate.
1287 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1289 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1290 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1291 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1292 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1294 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1295 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1296 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1297 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1299 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1300 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1301 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1302 // Don't lower v32i8 because there is no 128-bit byte mul
1305 // In the customized shift lowering, the legal cases in AVX2 will be
1307 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1308 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1310 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1311 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1313 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1315 // Custom lower several nodes for 256-bit types.
1316 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1317 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1318 MVT VT = (MVT::SimpleValueType)i;
1320 // Extract subvector is special because the value type
1321 // (result) is 128-bit but the source is 256-bit wide.
1322 if (VT.is128BitVector())
1323 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1325 // Do not attempt to custom lower other non-256-bit vectors
1326 if (!VT.is256BitVector())
1329 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1330 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1331 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1332 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1333 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1334 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1335 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1338 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1339 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1340 MVT VT = (MVT::SimpleValueType)i;
1342 // Do not attempt to promote non-256-bit vectors
1343 if (!VT.is256BitVector())
1346 setOperationAction(ISD::AND, VT, Promote);
1347 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1348 setOperationAction(ISD::OR, VT, Promote);
1349 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1350 setOperationAction(ISD::XOR, VT, Promote);
1351 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1352 setOperationAction(ISD::LOAD, VT, Promote);
1353 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1354 setOperationAction(ISD::SELECT, VT, Promote);
1355 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1359 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1360 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1361 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1362 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1363 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1365 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1366 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1367 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1369 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1370 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1371 setOperationAction(ISD::XOR, MVT::i1, Legal);
1372 setOperationAction(ISD::OR, MVT::i1, Legal);
1373 setOperationAction(ISD::AND, MVT::i1, Legal);
1374 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1375 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1376 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1377 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1378 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1379 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1381 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1382 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1383 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1384 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1385 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1386 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1388 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1389 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1390 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1391 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1392 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1393 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1394 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1395 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1397 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1398 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1399 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1400 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1401 if (Subtarget->is64Bit()) {
1402 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1403 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1404 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1405 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1407 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1408 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1409 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1410 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1411 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1412 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1413 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1414 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1415 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1416 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1417 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1419 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1420 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1422 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1423 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1424 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1428 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1429 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1430 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1431 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1436 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1437 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1443 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1444 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1446 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1448 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1449 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1450 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1451 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1452 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1453 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1454 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1455 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1458 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1459 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1461 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1462 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1464 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1466 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1467 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1469 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1470 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1472 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1473 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1475 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1476 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1477 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1478 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1479 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1480 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1482 if (Subtarget->hasCDI()) {
1483 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1484 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1487 // Custom lower several nodes.
1488 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1489 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1490 MVT VT = (MVT::SimpleValueType)i;
1492 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1493 // Extract subvector is special because the value type
1494 // (result) is 256/128-bit but the source is 512-bit wide.
1495 if (VT.is128BitVector() || VT.is256BitVector())
1496 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1498 if (VT.getVectorElementType() == MVT::i1)
1499 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1501 // Do not attempt to custom lower other non-512-bit vectors
1502 if (!VT.is512BitVector())
1505 if ( EltSize >= 32) {
1506 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1507 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1508 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1509 setOperationAction(ISD::VSELECT, VT, Legal);
1510 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1511 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1512 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1515 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1516 MVT VT = (MVT::SimpleValueType)i;
1518 // Do not attempt to promote non-256-bit vectors.
1519 if (!VT.is512BitVector())
1522 setOperationAction(ISD::SELECT, VT, Promote);
1523 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1527 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1528 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1529 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1531 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1532 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1534 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1535 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1536 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1537 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1539 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1540 const MVT VT = (MVT::SimpleValueType)i;
1542 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1544 // Do not attempt to promote non-256-bit vectors.
1545 if (!VT.is512BitVector())
1549 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1550 setOperationAction(ISD::VSELECT, VT, Legal);
1555 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1556 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1557 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1559 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1560 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1561 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1564 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1565 // of this type with custom code.
1566 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1567 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1568 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1572 // We want to custom lower some of our intrinsics.
1573 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1574 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1575 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1576 if (!Subtarget->is64Bit())
1577 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1579 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1580 // handle type legalization for these operations here.
1582 // FIXME: We really should do custom legalization for addition and
1583 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1584 // than generic legalization for 64-bit multiplication-with-overflow, though.
1585 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1586 // Add/Sub/Mul with overflow operations are custom lowered.
1588 setOperationAction(ISD::SADDO, VT, Custom);
1589 setOperationAction(ISD::UADDO, VT, Custom);
1590 setOperationAction(ISD::SSUBO, VT, Custom);
1591 setOperationAction(ISD::USUBO, VT, Custom);
1592 setOperationAction(ISD::SMULO, VT, Custom);
1593 setOperationAction(ISD::UMULO, VT, Custom);
1597 if (!Subtarget->is64Bit()) {
1598 // These libcalls are not available in 32-bit.
1599 setLibcallName(RTLIB::SHL_I128, nullptr);
1600 setLibcallName(RTLIB::SRL_I128, nullptr);
1601 setLibcallName(RTLIB::SRA_I128, nullptr);
1604 // Combine sin / cos into one node or libcall if possible.
1605 if (Subtarget->hasSinCos()) {
1606 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1607 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1608 if (Subtarget->isTargetDarwin()) {
1609 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1610 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1611 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1612 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1616 if (Subtarget->isTargetWin64()) {
1617 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1618 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1619 setOperationAction(ISD::SREM, MVT::i128, Custom);
1620 setOperationAction(ISD::UREM, MVT::i128, Custom);
1621 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1622 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1625 // We have target-specific dag combine patterns for the following nodes:
1626 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1627 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1628 setTargetDAGCombine(ISD::VSELECT);
1629 setTargetDAGCombine(ISD::SELECT);
1630 setTargetDAGCombine(ISD::SHL);
1631 setTargetDAGCombine(ISD::SRA);
1632 setTargetDAGCombine(ISD::SRL);
1633 setTargetDAGCombine(ISD::OR);
1634 setTargetDAGCombine(ISD::AND);
1635 setTargetDAGCombine(ISD::ADD);
1636 setTargetDAGCombine(ISD::FADD);
1637 setTargetDAGCombine(ISD::FSUB);
1638 setTargetDAGCombine(ISD::FMA);
1639 setTargetDAGCombine(ISD::SUB);
1640 setTargetDAGCombine(ISD::LOAD);
1641 setTargetDAGCombine(ISD::STORE);
1642 setTargetDAGCombine(ISD::ZERO_EXTEND);
1643 setTargetDAGCombine(ISD::ANY_EXTEND);
1644 setTargetDAGCombine(ISD::SIGN_EXTEND);
1645 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1646 setTargetDAGCombine(ISD::TRUNCATE);
1647 setTargetDAGCombine(ISD::SINT_TO_FP);
1648 setTargetDAGCombine(ISD::SETCC);
1649 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1650 setTargetDAGCombine(ISD::BUILD_VECTOR);
1651 if (Subtarget->is64Bit())
1652 setTargetDAGCombine(ISD::MUL);
1653 setTargetDAGCombine(ISD::XOR);
1655 computeRegisterProperties();
1657 // On Darwin, -Os means optimize for size without hurting performance,
1658 // do not reduce the limit.
1659 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1660 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1661 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1662 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1663 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1664 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1665 setPrefLoopAlignment(4); // 2^4 bytes.
1667 // Predictable cmov don't hurt on atom because it's in-order.
1668 PredictableSelectIsExpensive = !Subtarget->isAtom();
1670 setPrefFunctionAlignment(4); // 2^4 bytes.
1672 verifyIntrinsicTables();
1675 // This has so far only been implemented for 64-bit MachO.
1676 bool X86TargetLowering::useLoadStackGuardNode() const {
1677 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1678 Subtarget->is64Bit();
1681 TargetLoweringBase::LegalizeTypeAction
1682 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1683 if (ExperimentalVectorWideningLegalization &&
1684 VT.getVectorNumElements() != 1 &&
1685 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1686 return TypeWidenVector;
1688 return TargetLoweringBase::getPreferredVectorAction(VT);
1691 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1693 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1695 const unsigned NumElts = VT.getVectorNumElements();
1696 const EVT EltVT = VT.getVectorElementType();
1697 if (VT.is512BitVector()) {
1698 if (Subtarget->hasAVX512())
1699 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1700 EltVT == MVT::f32 || EltVT == MVT::f64)
1702 case 8: return MVT::v8i1;
1703 case 16: return MVT::v16i1;
1705 if (Subtarget->hasBWI())
1706 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1708 case 32: return MVT::v32i1;
1709 case 64: return MVT::v64i1;
1713 if (VT.is256BitVector() || VT.is128BitVector()) {
1714 if (Subtarget->hasVLX())
1715 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1716 EltVT == MVT::f32 || EltVT == MVT::f64)
1718 case 2: return MVT::v2i1;
1719 case 4: return MVT::v4i1;
1720 case 8: return MVT::v8i1;
1722 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1723 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1725 case 8: return MVT::v8i1;
1726 case 16: return MVT::v16i1;
1727 case 32: return MVT::v32i1;
1731 return VT.changeVectorElementTypeToInteger();
1734 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1735 /// the desired ByVal argument alignment.
1736 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1739 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1740 if (VTy->getBitWidth() == 128)
1742 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1743 unsigned EltAlign = 0;
1744 getMaxByValAlign(ATy->getElementType(), EltAlign);
1745 if (EltAlign > MaxAlign)
1746 MaxAlign = EltAlign;
1747 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1748 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1749 unsigned EltAlign = 0;
1750 getMaxByValAlign(STy->getElementType(i), EltAlign);
1751 if (EltAlign > MaxAlign)
1752 MaxAlign = EltAlign;
1759 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1760 /// function arguments in the caller parameter area. For X86, aggregates
1761 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1762 /// are at 4-byte boundaries.
1763 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1764 if (Subtarget->is64Bit()) {
1765 // Max of 8 and alignment of type.
1766 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1773 if (Subtarget->hasSSE1())
1774 getMaxByValAlign(Ty, Align);
1778 /// getOptimalMemOpType - Returns the target specific optimal type for load
1779 /// and store operations as a result of memset, memcpy, and memmove
1780 /// lowering. If DstAlign is zero that means it's safe to destination
1781 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1782 /// means there isn't a need to check it against alignment requirement,
1783 /// probably because the source does not need to be loaded. If 'IsMemset' is
1784 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1785 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1786 /// source is constant so it does not need to be loaded.
1787 /// It returns EVT::Other if the type should be determined using generic
1788 /// target-independent logic.
1790 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1791 unsigned DstAlign, unsigned SrcAlign,
1792 bool IsMemset, bool ZeroMemset,
1794 MachineFunction &MF) const {
1795 const Function *F = MF.getFunction();
1796 if ((!IsMemset || ZeroMemset) &&
1797 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1798 Attribute::NoImplicitFloat)) {
1800 (Subtarget->isUnalignedMemAccessFast() ||
1801 ((DstAlign == 0 || DstAlign >= 16) &&
1802 (SrcAlign == 0 || SrcAlign >= 16)))) {
1804 if (Subtarget->hasInt256())
1806 if (Subtarget->hasFp256())
1809 if (Subtarget->hasSSE2())
1811 if (Subtarget->hasSSE1())
1813 } else if (!MemcpyStrSrc && Size >= 8 &&
1814 !Subtarget->is64Bit() &&
1815 Subtarget->hasSSE2()) {
1816 // Do not use f64 to lower memcpy if source is string constant. It's
1817 // better to use i32 to avoid the loads.
1821 if (Subtarget->is64Bit() && Size >= 8)
1826 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1828 return X86ScalarSSEf32;
1829 else if (VT == MVT::f64)
1830 return X86ScalarSSEf64;
1835 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1840 *Fast = Subtarget->isUnalignedMemAccessFast();
1844 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1845 /// current function. The returned value is a member of the
1846 /// MachineJumpTableInfo::JTEntryKind enum.
1847 unsigned X86TargetLowering::getJumpTableEncoding() const {
1848 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1850 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1851 Subtarget->isPICStyleGOT())
1852 return MachineJumpTableInfo::EK_Custom32;
1854 // Otherwise, use the normal jump table encoding heuristics.
1855 return TargetLowering::getJumpTableEncoding();
1859 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1860 const MachineBasicBlock *MBB,
1861 unsigned uid,MCContext &Ctx) const{
1862 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1863 Subtarget->isPICStyleGOT());
1864 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1866 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1867 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1870 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1872 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1873 SelectionDAG &DAG) const {
1874 if (!Subtarget->is64Bit())
1875 // This doesn't have SDLoc associated with it, but is not really the
1876 // same as a Register.
1877 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1881 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1882 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1884 const MCExpr *X86TargetLowering::
1885 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1886 MCContext &Ctx) const {
1887 // X86-64 uses RIP relative addressing based on the jump table label.
1888 if (Subtarget->isPICStyleRIPRel())
1889 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1891 // Otherwise, the reference is relative to the PIC base.
1892 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1895 // FIXME: Why this routine is here? Move to RegInfo!
1896 std::pair<const TargetRegisterClass*, uint8_t>
1897 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1898 const TargetRegisterClass *RRC = nullptr;
1900 switch (VT.SimpleTy) {
1902 return TargetLowering::findRepresentativeClass(VT);
1903 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1904 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1907 RRC = &X86::VR64RegClass;
1909 case MVT::f32: case MVT::f64:
1910 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1911 case MVT::v4f32: case MVT::v2f64:
1912 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1914 RRC = &X86::VR128RegClass;
1917 return std::make_pair(RRC, Cost);
1920 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1921 unsigned &Offset) const {
1922 if (!Subtarget->isTargetLinux())
1925 if (Subtarget->is64Bit()) {
1926 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1928 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1940 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1941 unsigned DestAS) const {
1942 assert(SrcAS != DestAS && "Expected different address spaces!");
1944 return SrcAS < 256 && DestAS < 256;
1947 //===----------------------------------------------------------------------===//
1948 // Return Value Calling Convention Implementation
1949 //===----------------------------------------------------------------------===//
1951 #include "X86GenCallingConv.inc"
1954 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1955 MachineFunction &MF, bool isVarArg,
1956 const SmallVectorImpl<ISD::OutputArg> &Outs,
1957 LLVMContext &Context) const {
1958 SmallVector<CCValAssign, 16> RVLocs;
1959 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1960 return CCInfo.CheckReturn(Outs, RetCC_X86);
1963 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1964 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1969 X86TargetLowering::LowerReturn(SDValue Chain,
1970 CallingConv::ID CallConv, bool isVarArg,
1971 const SmallVectorImpl<ISD::OutputArg> &Outs,
1972 const SmallVectorImpl<SDValue> &OutVals,
1973 SDLoc dl, SelectionDAG &DAG) const {
1974 MachineFunction &MF = DAG.getMachineFunction();
1975 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1977 SmallVector<CCValAssign, 16> RVLocs;
1978 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1979 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1982 SmallVector<SDValue, 6> RetOps;
1983 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1984 // Operand #1 = Bytes To Pop
1985 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1988 // Copy the result values into the output registers.
1989 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1990 CCValAssign &VA = RVLocs[i];
1991 assert(VA.isRegLoc() && "Can only return in registers!");
1992 SDValue ValToCopy = OutVals[i];
1993 EVT ValVT = ValToCopy.getValueType();
1995 // Promote values to the appropriate types.
1996 if (VA.getLocInfo() == CCValAssign::SExt)
1997 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1998 else if (VA.getLocInfo() == CCValAssign::ZExt)
1999 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2000 else if (VA.getLocInfo() == CCValAssign::AExt)
2001 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2002 else if (VA.getLocInfo() == CCValAssign::BCvt)
2003 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2005 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2006 "Unexpected FP-extend for return value.");
2008 // If this is x86-64, and we disabled SSE, we can't return FP values,
2009 // or SSE or MMX vectors.
2010 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2011 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2012 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2013 report_fatal_error("SSE register return with SSE disabled");
2015 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2016 // llvm-gcc has never done it right and no one has noticed, so this
2017 // should be OK for now.
2018 if (ValVT == MVT::f64 &&
2019 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2020 report_fatal_error("SSE2 register return with SSE2 disabled");
2022 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2023 // the RET instruction and handled by the FP Stackifier.
2024 if (VA.getLocReg() == X86::FP0 ||
2025 VA.getLocReg() == X86::FP1) {
2026 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2027 // change the value to the FP stack register class.
2028 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2029 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2030 RetOps.push_back(ValToCopy);
2031 // Don't emit a copytoreg.
2035 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2036 // which is returned in RAX / RDX.
2037 if (Subtarget->is64Bit()) {
2038 if (ValVT == MVT::x86mmx) {
2039 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2040 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2041 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2043 // If we don't have SSE2 available, convert to v4f32 so the generated
2044 // register is legal.
2045 if (!Subtarget->hasSSE2())
2046 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2051 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2052 Flag = Chain.getValue(1);
2053 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2056 // The x86-64 ABIs require that for returning structs by value we copy
2057 // the sret argument into %rax/%eax (depending on ABI) for the return.
2058 // Win32 requires us to put the sret argument to %eax as well.
2059 // We saved the argument into a virtual register in the entry block,
2060 // so now we copy the value out and into %rax/%eax.
2061 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2062 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2063 MachineFunction &MF = DAG.getMachineFunction();
2064 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2065 unsigned Reg = FuncInfo->getSRetReturnReg();
2067 "SRetReturnReg should have been set in LowerFormalArguments().");
2068 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2071 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2072 X86::RAX : X86::EAX;
2073 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2074 Flag = Chain.getValue(1);
2076 // RAX/EAX now acts like a return value.
2077 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2080 RetOps[0] = Chain; // Update chain.
2082 // Add the flag if we have it.
2084 RetOps.push_back(Flag);
2086 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2089 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2090 if (N->getNumValues() != 1)
2092 if (!N->hasNUsesOfValue(1, 0))
2095 SDValue TCChain = Chain;
2096 SDNode *Copy = *N->use_begin();
2097 if (Copy->getOpcode() == ISD::CopyToReg) {
2098 // If the copy has a glue operand, we conservatively assume it isn't safe to
2099 // perform a tail call.
2100 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2102 TCChain = Copy->getOperand(0);
2103 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2106 bool HasRet = false;
2107 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2109 if (UI->getOpcode() != X86ISD::RET_FLAG)
2111 // If we are returning more than one value, we can definitely
2112 // not make a tail call see PR19530
2113 if (UI->getNumOperands() > 4)
2115 if (UI->getNumOperands() == 4 &&
2116 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2129 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2130 ISD::NodeType ExtendKind) const {
2132 // TODO: Is this also valid on 32-bit?
2133 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2134 ReturnMVT = MVT::i8;
2136 ReturnMVT = MVT::i32;
2138 EVT MinVT = getRegisterType(Context, ReturnMVT);
2139 return VT.bitsLT(MinVT) ? MinVT : VT;
2142 /// LowerCallResult - Lower the result values of a call into the
2143 /// appropriate copies out of appropriate physical registers.
2146 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2147 CallingConv::ID CallConv, bool isVarArg,
2148 const SmallVectorImpl<ISD::InputArg> &Ins,
2149 SDLoc dl, SelectionDAG &DAG,
2150 SmallVectorImpl<SDValue> &InVals) const {
2152 // Assign locations to each value returned by this call.
2153 SmallVector<CCValAssign, 16> RVLocs;
2154 bool Is64Bit = Subtarget->is64Bit();
2155 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2157 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2159 // Copy all of the result registers out of their specified physreg.
2160 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2161 CCValAssign &VA = RVLocs[i];
2162 EVT CopyVT = VA.getValVT();
2164 // If this is x86-64, and we disabled SSE, we can't return FP values
2165 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2166 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2167 report_fatal_error("SSE register return with SSE disabled");
2170 // If we prefer to use the value in xmm registers, copy it out as f80 and
2171 // use a truncate to move it from fp stack reg to xmm reg.
2172 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2173 isScalarFPTypeInSSEReg(VA.getValVT()))
2176 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2177 CopyVT, InFlag).getValue(1);
2178 SDValue Val = Chain.getValue(0);
2180 if (CopyVT != VA.getValVT())
2181 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2182 // This truncation won't change the value.
2183 DAG.getIntPtrConstant(1));
2185 InFlag = Chain.getValue(2);
2186 InVals.push_back(Val);
2192 //===----------------------------------------------------------------------===//
2193 // C & StdCall & Fast Calling Convention implementation
2194 //===----------------------------------------------------------------------===//
2195 // StdCall calling convention seems to be standard for many Windows' API
2196 // routines and around. It differs from C calling convention just a little:
2197 // callee should clean up the stack, not caller. Symbols should be also
2198 // decorated in some fancy way :) It doesn't support any vector arguments.
2199 // For info on fast calling convention see Fast Calling Convention (tail call)
2200 // implementation LowerX86_32FastCCCallTo.
2202 /// CallIsStructReturn - Determines whether a call uses struct return
2204 enum StructReturnType {
2209 static StructReturnType
2210 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2212 return NotStructReturn;
2214 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2215 if (!Flags.isSRet())
2216 return NotStructReturn;
2217 if (Flags.isInReg())
2218 return RegStructReturn;
2219 return StackStructReturn;
2222 /// ArgsAreStructReturn - Determines whether a function uses struct
2223 /// return semantics.
2224 static StructReturnType
2225 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2227 return NotStructReturn;
2229 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2230 if (!Flags.isSRet())
2231 return NotStructReturn;
2232 if (Flags.isInReg())
2233 return RegStructReturn;
2234 return StackStructReturn;
2237 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2238 /// by "Src" to address "Dst" with size and alignment information specified by
2239 /// the specific parameter attribute. The copy will be passed as a byval
2240 /// function parameter.
2242 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2243 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2245 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2247 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2248 /*isVolatile*/false, /*AlwaysInline=*/true,
2249 MachinePointerInfo(), MachinePointerInfo());
2252 /// IsTailCallConvention - Return true if the calling convention is one that
2253 /// supports tail call optimization.
2254 static bool IsTailCallConvention(CallingConv::ID CC) {
2255 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2256 CC == CallingConv::HiPE);
2259 /// \brief Return true if the calling convention is a C calling convention.
2260 static bool IsCCallConvention(CallingConv::ID CC) {
2261 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2262 CC == CallingConv::X86_64_SysV);
2265 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2266 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2270 CallingConv::ID CalleeCC = CS.getCallingConv();
2271 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2277 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2278 /// a tailcall target by changing its ABI.
2279 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2280 bool GuaranteedTailCallOpt) {
2281 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2285 X86TargetLowering::LowerMemArgument(SDValue Chain,
2286 CallingConv::ID CallConv,
2287 const SmallVectorImpl<ISD::InputArg> &Ins,
2288 SDLoc dl, SelectionDAG &DAG,
2289 const CCValAssign &VA,
2290 MachineFrameInfo *MFI,
2292 // Create the nodes corresponding to a load from this parameter slot.
2293 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2294 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2295 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2296 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2299 // If value is passed by pointer we have address passed instead of the value
2301 if (VA.getLocInfo() == CCValAssign::Indirect)
2302 ValVT = VA.getLocVT();
2304 ValVT = VA.getValVT();
2306 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2307 // changed with more analysis.
2308 // In case of tail call optimization mark all arguments mutable. Since they
2309 // could be overwritten by lowering of arguments in case of a tail call.
2310 if (Flags.isByVal()) {
2311 unsigned Bytes = Flags.getByValSize();
2312 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2313 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2314 return DAG.getFrameIndex(FI, getPointerTy());
2316 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2317 VA.getLocMemOffset(), isImmutable);
2318 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2319 return DAG.getLoad(ValVT, dl, Chain, FIN,
2320 MachinePointerInfo::getFixedStack(FI),
2321 false, false, false, 0);
2325 // FIXME: Get this from tablegen.
2326 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2327 const X86Subtarget *Subtarget) {
2328 assert(Subtarget->is64Bit());
2330 if (Subtarget->isCallingConvWin64(CallConv)) {
2331 static const MCPhysReg GPR64ArgRegsWin64[] = {
2332 X86::RCX, X86::RDX, X86::R8, X86::R9
2334 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2337 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2338 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2340 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2343 // FIXME: Get this from tablegen.
2344 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2345 CallingConv::ID CallConv,
2346 const X86Subtarget *Subtarget) {
2347 assert(Subtarget->is64Bit());
2348 if (Subtarget->isCallingConvWin64(CallConv)) {
2349 // The XMM registers which might contain var arg parameters are shadowed
2350 // in their paired GPR. So we only need to save the GPR to their home
2352 // TODO: __vectorcall will change this.
2356 const Function *Fn = MF.getFunction();
2357 bool NoImplicitFloatOps = Fn->getAttributes().
2358 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2359 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2360 "SSE register cannot be used when SSE is disabled!");
2361 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2362 !Subtarget->hasSSE1())
2363 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2367 static const MCPhysReg XMMArgRegs64Bit[] = {
2368 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2369 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2371 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2375 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2376 CallingConv::ID CallConv,
2378 const SmallVectorImpl<ISD::InputArg> &Ins,
2381 SmallVectorImpl<SDValue> &InVals)
2383 MachineFunction &MF = DAG.getMachineFunction();
2384 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2386 const Function* Fn = MF.getFunction();
2387 if (Fn->hasExternalLinkage() &&
2388 Subtarget->isTargetCygMing() &&
2389 Fn->getName() == "main")
2390 FuncInfo->setForceFramePointer(true);
2392 MachineFrameInfo *MFI = MF.getFrameInfo();
2393 bool Is64Bit = Subtarget->is64Bit();
2394 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2396 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2397 "Var args not supported with calling convention fastcc, ghc or hipe");
2399 // Assign locations to all of the incoming arguments.
2400 SmallVector<CCValAssign, 16> ArgLocs;
2401 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2403 // Allocate shadow area for Win64
2405 CCInfo.AllocateStack(32, 8);
2407 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2409 unsigned LastVal = ~0U;
2411 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2412 CCValAssign &VA = ArgLocs[i];
2413 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2415 assert(VA.getValNo() != LastVal &&
2416 "Don't support value assigned to multiple locs yet");
2418 LastVal = VA.getValNo();
2420 if (VA.isRegLoc()) {
2421 EVT RegVT = VA.getLocVT();
2422 const TargetRegisterClass *RC;
2423 if (RegVT == MVT::i32)
2424 RC = &X86::GR32RegClass;
2425 else if (Is64Bit && RegVT == MVT::i64)
2426 RC = &X86::GR64RegClass;
2427 else if (RegVT == MVT::f32)
2428 RC = &X86::FR32RegClass;
2429 else if (RegVT == MVT::f64)
2430 RC = &X86::FR64RegClass;
2431 else if (RegVT.is512BitVector())
2432 RC = &X86::VR512RegClass;
2433 else if (RegVT.is256BitVector())
2434 RC = &X86::VR256RegClass;
2435 else if (RegVT.is128BitVector())
2436 RC = &X86::VR128RegClass;
2437 else if (RegVT == MVT::x86mmx)
2438 RC = &X86::VR64RegClass;
2439 else if (RegVT == MVT::i1)
2440 RC = &X86::VK1RegClass;
2441 else if (RegVT == MVT::v8i1)
2442 RC = &X86::VK8RegClass;
2443 else if (RegVT == MVT::v16i1)
2444 RC = &X86::VK16RegClass;
2445 else if (RegVT == MVT::v32i1)
2446 RC = &X86::VK32RegClass;
2447 else if (RegVT == MVT::v64i1)
2448 RC = &X86::VK64RegClass;
2450 llvm_unreachable("Unknown argument type!");
2452 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2453 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2455 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2456 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2458 if (VA.getLocInfo() == CCValAssign::SExt)
2459 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2460 DAG.getValueType(VA.getValVT()));
2461 else if (VA.getLocInfo() == CCValAssign::ZExt)
2462 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2463 DAG.getValueType(VA.getValVT()));
2464 else if (VA.getLocInfo() == CCValAssign::BCvt)
2465 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2467 if (VA.isExtInLoc()) {
2468 // Handle MMX values passed in XMM regs.
2469 if (RegVT.isVector())
2470 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2472 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2475 assert(VA.isMemLoc());
2476 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2479 // If value is passed via pointer - do a load.
2480 if (VA.getLocInfo() == CCValAssign::Indirect)
2481 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2482 MachinePointerInfo(), false, false, false, 0);
2484 InVals.push_back(ArgValue);
2487 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2488 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2489 // The x86-64 ABIs require that for returning structs by value we copy
2490 // the sret argument into %rax/%eax (depending on ABI) for the return.
2491 // Win32 requires us to put the sret argument to %eax as well.
2492 // Save the argument into a virtual register so that we can access it
2493 // from the return points.
2494 if (Ins[i].Flags.isSRet()) {
2495 unsigned Reg = FuncInfo->getSRetReturnReg();
2497 MVT PtrTy = getPointerTy();
2498 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2499 FuncInfo->setSRetReturnReg(Reg);
2501 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2502 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2508 unsigned StackSize = CCInfo.getNextStackOffset();
2509 // Align stack specially for tail calls.
2510 if (FuncIsMadeTailCallSafe(CallConv,
2511 MF.getTarget().Options.GuaranteedTailCallOpt))
2512 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2514 // If the function takes variable number of arguments, make a frame index for
2515 // the start of the first vararg value... for expansion of llvm.va_start. We
2516 // can skip this if there are no va_start calls.
2517 if (MFI->hasVAStart() &&
2518 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2519 CallConv != CallingConv::X86_ThisCall))) {
2520 FuncInfo->setVarArgsFrameIndex(
2521 MFI->CreateFixedObject(1, StackSize, true));
2524 // 64-bit calling conventions support varargs and register parameters, so we
2525 // have to do extra work to spill them in the prologue or forward them to
2527 if (Is64Bit && isVarArg &&
2528 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2529 // Find the first unallocated argument registers.
2530 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2531 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2532 unsigned NumIntRegs =
2533 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2534 unsigned NumXMMRegs =
2535 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2536 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2537 "SSE register cannot be used when SSE is disabled!");
2539 // Gather all the live in physical registers.
2540 SmallVector<SDValue, 6> LiveGPRs;
2541 SmallVector<SDValue, 8> LiveXMMRegs;
2543 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2544 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2546 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2548 if (!ArgXMMs.empty()) {
2549 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2550 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2551 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2552 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2553 LiveXMMRegs.push_back(
2554 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2558 // Store them to the va_list returned by va_start.
2559 if (MFI->hasVAStart()) {
2561 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2562 // Get to the caller-allocated home save location. Add 8 to account
2563 // for the return address.
2564 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2565 FuncInfo->setRegSaveFrameIndex(
2566 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2567 // Fixup to set vararg frame on shadow area (4 x i64).
2569 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2571 // For X86-64, if there are vararg parameters that are passed via
2572 // registers, then we must store them to their spots on the stack so
2573 // they may be loaded by deferencing the result of va_next.
2574 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2575 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2576 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2577 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2580 // Store the integer parameter registers.
2581 SmallVector<SDValue, 8> MemOps;
2582 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2584 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2585 for (SDValue Val : LiveGPRs) {
2586 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2587 DAG.getIntPtrConstant(Offset));
2589 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2590 MachinePointerInfo::getFixedStack(
2591 FuncInfo->getRegSaveFrameIndex(), Offset),
2593 MemOps.push_back(Store);
2597 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2598 // Now store the XMM (fp + vector) parameter registers.
2599 SmallVector<SDValue, 12> SaveXMMOps;
2600 SaveXMMOps.push_back(Chain);
2601 SaveXMMOps.push_back(ALVal);
2602 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2603 FuncInfo->getRegSaveFrameIndex()));
2604 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2605 FuncInfo->getVarArgsFPOffset()));
2606 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2608 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2609 MVT::Other, SaveXMMOps));
2612 if (!MemOps.empty())
2613 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2615 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2616 // to the liveout set on a musttail call.
2617 assert(MFI->hasMustTailInVarArgFunc());
2618 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2619 typedef X86MachineFunctionInfo::Forward Forward;
2621 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2623 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2624 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2625 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2628 if (!ArgXMMs.empty()) {
2630 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2631 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2632 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2634 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2636 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2637 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2639 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2645 // Some CCs need callee pop.
2646 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2647 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2648 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2650 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2651 // If this is an sret function, the return should pop the hidden pointer.
2652 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2653 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2654 argsAreStructReturn(Ins) == StackStructReturn)
2655 FuncInfo->setBytesToPopOnReturn(4);
2659 // RegSaveFrameIndex is X86-64 only.
2660 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2661 if (CallConv == CallingConv::X86_FastCall ||
2662 CallConv == CallingConv::X86_ThisCall)
2663 // fastcc functions can't have varargs.
2664 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2667 FuncInfo->setArgumentStackSize(StackSize);
2673 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2674 SDValue StackPtr, SDValue Arg,
2675 SDLoc dl, SelectionDAG &DAG,
2676 const CCValAssign &VA,
2677 ISD::ArgFlagsTy Flags) const {
2678 unsigned LocMemOffset = VA.getLocMemOffset();
2679 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2680 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2681 if (Flags.isByVal())
2682 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2684 return DAG.getStore(Chain, dl, Arg, PtrOff,
2685 MachinePointerInfo::getStack(LocMemOffset),
2689 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2690 /// optimization is performed and it is required.
2692 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2693 SDValue &OutRetAddr, SDValue Chain,
2694 bool IsTailCall, bool Is64Bit,
2695 int FPDiff, SDLoc dl) const {
2696 // Adjust the Return address stack slot.
2697 EVT VT = getPointerTy();
2698 OutRetAddr = getReturnAddressFrameIndex(DAG);
2700 // Load the "old" Return address.
2701 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2702 false, false, false, 0);
2703 return SDValue(OutRetAddr.getNode(), 1);
2706 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2707 /// optimization is performed and it is required (FPDiff!=0).
2708 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2709 SDValue Chain, SDValue RetAddrFrIdx,
2710 EVT PtrVT, unsigned SlotSize,
2711 int FPDiff, SDLoc dl) {
2712 // Store the return address to the appropriate stack slot.
2713 if (!FPDiff) return Chain;
2714 // Calculate the new stack slot for the return address.
2715 int NewReturnAddrFI =
2716 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2718 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2719 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2720 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2726 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2727 SmallVectorImpl<SDValue> &InVals) const {
2728 SelectionDAG &DAG = CLI.DAG;
2730 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2731 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2732 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2733 SDValue Chain = CLI.Chain;
2734 SDValue Callee = CLI.Callee;
2735 CallingConv::ID CallConv = CLI.CallConv;
2736 bool &isTailCall = CLI.IsTailCall;
2737 bool isVarArg = CLI.IsVarArg;
2739 MachineFunction &MF = DAG.getMachineFunction();
2740 bool Is64Bit = Subtarget->is64Bit();
2741 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2742 StructReturnType SR = callIsStructReturn(Outs);
2743 bool IsSibcall = false;
2744 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2746 if (MF.getTarget().Options.DisableTailCalls)
2749 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2751 // Force this to be a tail call. The verifier rules are enough to ensure
2752 // that we can lower this successfully without moving the return address
2755 } else if (isTailCall) {
2756 // Check if it's really possible to do a tail call.
2757 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2758 isVarArg, SR != NotStructReturn,
2759 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2760 Outs, OutVals, Ins, DAG);
2762 // Sibcalls are automatically detected tailcalls which do not require
2764 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2771 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2772 "Var args not supported with calling convention fastcc, ghc or hipe");
2774 // Analyze operands of the call, assigning locations to each operand.
2775 SmallVector<CCValAssign, 16> ArgLocs;
2776 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2778 // Allocate shadow area for Win64
2780 CCInfo.AllocateStack(32, 8);
2782 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2784 // Get a count of how many bytes are to be pushed on the stack.
2785 unsigned NumBytes = CCInfo.getNextStackOffset();
2787 // This is a sibcall. The memory operands are available in caller's
2788 // own caller's stack.
2790 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2791 IsTailCallConvention(CallConv))
2792 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2795 if (isTailCall && !IsSibcall && !IsMustTail) {
2796 // Lower arguments at fp - stackoffset + fpdiff.
2797 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2799 FPDiff = NumBytesCallerPushed - NumBytes;
2801 // Set the delta of movement of the returnaddr stackslot.
2802 // But only set if delta is greater than previous delta.
2803 if (FPDiff < X86Info->getTCReturnAddrDelta())
2804 X86Info->setTCReturnAddrDelta(FPDiff);
2807 unsigned NumBytesToPush = NumBytes;
2808 unsigned NumBytesToPop = NumBytes;
2810 // If we have an inalloca argument, all stack space has already been allocated
2811 // for us and be right at the top of the stack. We don't support multiple
2812 // arguments passed in memory when using inalloca.
2813 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2815 if (!ArgLocs.back().isMemLoc())
2816 report_fatal_error("cannot use inalloca attribute on a register "
2818 if (ArgLocs.back().getLocMemOffset() != 0)
2819 report_fatal_error("any parameter with the inalloca attribute must be "
2820 "the only memory argument");
2824 Chain = DAG.getCALLSEQ_START(
2825 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2827 SDValue RetAddrFrIdx;
2828 // Load return address for tail calls.
2829 if (isTailCall && FPDiff)
2830 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2831 Is64Bit, FPDiff, dl);
2833 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2834 SmallVector<SDValue, 8> MemOpChains;
2837 // Walk the register/memloc assignments, inserting copies/loads. In the case
2838 // of tail call optimization arguments are handle later.
2839 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2840 DAG.getSubtarget().getRegisterInfo());
2841 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2842 // Skip inalloca arguments, they have already been written.
2843 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2844 if (Flags.isInAlloca())
2847 CCValAssign &VA = ArgLocs[i];
2848 EVT RegVT = VA.getLocVT();
2849 SDValue Arg = OutVals[i];
2850 bool isByVal = Flags.isByVal();
2852 // Promote the value if needed.
2853 switch (VA.getLocInfo()) {
2854 default: llvm_unreachable("Unknown loc info!");
2855 case CCValAssign::Full: break;
2856 case CCValAssign::SExt:
2857 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2859 case CCValAssign::ZExt:
2860 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2862 case CCValAssign::AExt:
2863 if (RegVT.is128BitVector()) {
2864 // Special case: passing MMX values in XMM registers.
2865 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2866 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2867 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2869 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2871 case CCValAssign::BCvt:
2872 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2874 case CCValAssign::Indirect: {
2875 // Store the argument.
2876 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2877 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2878 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2879 MachinePointerInfo::getFixedStack(FI),
2886 if (VA.isRegLoc()) {
2887 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2888 if (isVarArg && IsWin64) {
2889 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2890 // shadow reg if callee is a varargs function.
2891 unsigned ShadowReg = 0;
2892 switch (VA.getLocReg()) {
2893 case X86::XMM0: ShadowReg = X86::RCX; break;
2894 case X86::XMM1: ShadowReg = X86::RDX; break;
2895 case X86::XMM2: ShadowReg = X86::R8; break;
2896 case X86::XMM3: ShadowReg = X86::R9; break;
2899 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2901 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2902 assert(VA.isMemLoc());
2903 if (!StackPtr.getNode())
2904 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2906 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2907 dl, DAG, VA, Flags));
2911 if (!MemOpChains.empty())
2912 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2914 if (Subtarget->isPICStyleGOT()) {
2915 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2918 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2919 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2921 // If we are tail calling and generating PIC/GOT style code load the
2922 // address of the callee into ECX. The value in ecx is used as target of
2923 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2924 // for tail calls on PIC/GOT architectures. Normally we would just put the
2925 // address of GOT into ebx and then call target@PLT. But for tail calls
2926 // ebx would be restored (since ebx is callee saved) before jumping to the
2929 // Note: The actual moving to ECX is done further down.
2930 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2931 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2932 !G->getGlobal()->hasProtectedVisibility())
2933 Callee = LowerGlobalAddress(Callee, DAG);
2934 else if (isa<ExternalSymbolSDNode>(Callee))
2935 Callee = LowerExternalSymbol(Callee, DAG);
2939 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2940 // From AMD64 ABI document:
2941 // For calls that may call functions that use varargs or stdargs
2942 // (prototype-less calls or calls to functions containing ellipsis (...) in
2943 // the declaration) %al is used as hidden argument to specify the number
2944 // of SSE registers used. The contents of %al do not need to match exactly
2945 // the number of registers, but must be an ubound on the number of SSE
2946 // registers used and is in the range 0 - 8 inclusive.
2948 // Count the number of XMM registers allocated.
2949 static const MCPhysReg XMMArgRegs[] = {
2950 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2951 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2953 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2954 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2955 && "SSE registers cannot be used when SSE is disabled");
2957 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2958 DAG.getConstant(NumXMMRegs, MVT::i8)));
2961 if (Is64Bit && isVarArg && IsMustTail) {
2962 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2963 for (const auto &F : Forwards) {
2964 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2965 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2969 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2970 // don't need this because the eligibility check rejects calls that require
2971 // shuffling arguments passed in memory.
2972 if (!IsSibcall && isTailCall) {
2973 // Force all the incoming stack arguments to be loaded from the stack
2974 // before any new outgoing arguments are stored to the stack, because the
2975 // outgoing stack slots may alias the incoming argument stack slots, and
2976 // the alias isn't otherwise explicit. This is slightly more conservative
2977 // than necessary, because it means that each store effectively depends
2978 // on every argument instead of just those arguments it would clobber.
2979 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2981 SmallVector<SDValue, 8> MemOpChains2;
2984 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2985 CCValAssign &VA = ArgLocs[i];
2988 assert(VA.isMemLoc());
2989 SDValue Arg = OutVals[i];
2990 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2991 // Skip inalloca arguments. They don't require any work.
2992 if (Flags.isInAlloca())
2994 // Create frame index.
2995 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2996 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2997 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2998 FIN = DAG.getFrameIndex(FI, getPointerTy());
3000 if (Flags.isByVal()) {
3001 // Copy relative to framepointer.
3002 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3003 if (!StackPtr.getNode())
3004 StackPtr = DAG.getCopyFromReg(Chain, dl,
3005 RegInfo->getStackRegister(),
3007 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3009 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3013 // Store relative to framepointer.
3014 MemOpChains2.push_back(
3015 DAG.getStore(ArgChain, dl, Arg, FIN,
3016 MachinePointerInfo::getFixedStack(FI),
3021 if (!MemOpChains2.empty())
3022 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3024 // Store the return address to the appropriate stack slot.
3025 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3026 getPointerTy(), RegInfo->getSlotSize(),
3030 // Build a sequence of copy-to-reg nodes chained together with token chain
3031 // and flag operands which copy the outgoing args into registers.
3033 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3034 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3035 RegsToPass[i].second, InFlag);
3036 InFlag = Chain.getValue(1);
3039 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3040 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3041 // In the 64-bit large code model, we have to make all calls
3042 // through a register, since the call instruction's 32-bit
3043 // pc-relative offset may not be large enough to hold the whole
3045 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3046 // If the callee is a GlobalAddress node (quite common, every direct call
3047 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3050 // We should use extra load for direct calls to dllimported functions in
3052 const GlobalValue *GV = G->getGlobal();
3053 if (!GV->hasDLLImportStorageClass()) {
3054 unsigned char OpFlags = 0;
3055 bool ExtraLoad = false;
3056 unsigned WrapperKind = ISD::DELETED_NODE;
3058 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3059 // external symbols most go through the PLT in PIC mode. If the symbol
3060 // has hidden or protected visibility, or if it is static or local, then
3061 // we don't need to use the PLT - we can directly call it.
3062 if (Subtarget->isTargetELF() &&
3063 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3064 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3065 OpFlags = X86II::MO_PLT;
3066 } else if (Subtarget->isPICStyleStubAny() &&
3067 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3068 (!Subtarget->getTargetTriple().isMacOSX() ||
3069 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3070 // PC-relative references to external symbols should go through $stub,
3071 // unless we're building with the leopard linker or later, which
3072 // automatically synthesizes these stubs.
3073 OpFlags = X86II::MO_DARWIN_STUB;
3074 } else if (Subtarget->isPICStyleRIPRel() &&
3075 isa<Function>(GV) &&
3076 cast<Function>(GV)->getAttributes().
3077 hasAttribute(AttributeSet::FunctionIndex,
3078 Attribute::NonLazyBind)) {
3079 // If the function is marked as non-lazy, generate an indirect call
3080 // which loads from the GOT directly. This avoids runtime overhead
3081 // at the cost of eager binding (and one extra byte of encoding).
3082 OpFlags = X86II::MO_GOTPCREL;
3083 WrapperKind = X86ISD::WrapperRIP;
3087 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3088 G->getOffset(), OpFlags);
3090 // Add a wrapper if needed.
3091 if (WrapperKind != ISD::DELETED_NODE)
3092 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3093 // Add extra indirection if needed.
3095 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3096 MachinePointerInfo::getGOT(),
3097 false, false, false, 0);
3099 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3100 unsigned char OpFlags = 0;
3102 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3103 // external symbols should go through the PLT.
3104 if (Subtarget->isTargetELF() &&
3105 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3106 OpFlags = X86II::MO_PLT;
3107 } else if (Subtarget->isPICStyleStubAny() &&
3108 (!Subtarget->getTargetTriple().isMacOSX() ||
3109 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3110 // PC-relative references to external symbols should go through $stub,
3111 // unless we're building with the leopard linker or later, which
3112 // automatically synthesizes these stubs.
3113 OpFlags = X86II::MO_DARWIN_STUB;
3116 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3118 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3119 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3120 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3123 // Returns a chain & a flag for retval copy to use.
3124 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3125 SmallVector<SDValue, 8> Ops;
3127 if (!IsSibcall && isTailCall) {
3128 Chain = DAG.getCALLSEQ_END(Chain,
3129 DAG.getIntPtrConstant(NumBytesToPop, true),
3130 DAG.getIntPtrConstant(0, true), InFlag, dl);
3131 InFlag = Chain.getValue(1);
3134 Ops.push_back(Chain);
3135 Ops.push_back(Callee);
3138 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3140 // Add argument registers to the end of the list so that they are known live
3142 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3143 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3144 RegsToPass[i].second.getValueType()));
3146 // Add a register mask operand representing the call-preserved registers.
3147 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3148 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3149 assert(Mask && "Missing call preserved mask for calling convention");
3150 Ops.push_back(DAG.getRegisterMask(Mask));
3152 if (InFlag.getNode())
3153 Ops.push_back(InFlag);
3157 //// If this is the first return lowered for this function, add the regs
3158 //// to the liveout set for the function.
3159 // This isn't right, although it's probably harmless on x86; liveouts
3160 // should be computed from returns not tail calls. Consider a void
3161 // function making a tail call to a function returning int.
3162 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3165 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3166 InFlag = Chain.getValue(1);
3168 // Create the CALLSEQ_END node.
3169 unsigned NumBytesForCalleeToPop;
3170 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3171 DAG.getTarget().Options.GuaranteedTailCallOpt))
3172 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3173 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3174 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3175 SR == StackStructReturn)
3176 // If this is a call to a struct-return function, the callee
3177 // pops the hidden struct pointer, so we have to push it back.
3178 // This is common for Darwin/X86, Linux & Mingw32 targets.
3179 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3180 NumBytesForCalleeToPop = 4;
3182 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3184 // Returns a flag for retval copy to use.
3186 Chain = DAG.getCALLSEQ_END(Chain,
3187 DAG.getIntPtrConstant(NumBytesToPop, true),
3188 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3191 InFlag = Chain.getValue(1);
3194 // Handle result values, copying them out of physregs into vregs that we
3196 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3197 Ins, dl, DAG, InVals);
3200 //===----------------------------------------------------------------------===//
3201 // Fast Calling Convention (tail call) implementation
3202 //===----------------------------------------------------------------------===//
3204 // Like std call, callee cleans arguments, convention except that ECX is
3205 // reserved for storing the tail called function address. Only 2 registers are
3206 // free for argument passing (inreg). Tail call optimization is performed
3208 // * tailcallopt is enabled
3209 // * caller/callee are fastcc
3210 // On X86_64 architecture with GOT-style position independent code only local
3211 // (within module) calls are supported at the moment.
3212 // To keep the stack aligned according to platform abi the function
3213 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3214 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3215 // If a tail called function callee has more arguments than the caller the
3216 // caller needs to make sure that there is room to move the RETADDR to. This is
3217 // achieved by reserving an area the size of the argument delta right after the
3218 // original RETADDR, but before the saved framepointer or the spilled registers
3219 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3231 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3232 /// for a 16 byte align requirement.
3234 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3235 SelectionDAG& DAG) const {
3236 MachineFunction &MF = DAG.getMachineFunction();
3237 const TargetMachine &TM = MF.getTarget();
3238 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3239 TM.getSubtargetImpl()->getRegisterInfo());
3240 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3241 unsigned StackAlignment = TFI.getStackAlignment();
3242 uint64_t AlignMask = StackAlignment - 1;
3243 int64_t Offset = StackSize;
3244 unsigned SlotSize = RegInfo->getSlotSize();
3245 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3246 // Number smaller than 12 so just add the difference.
3247 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3249 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3250 Offset = ((~AlignMask) & Offset) + StackAlignment +
3251 (StackAlignment-SlotSize);
3256 /// MatchingStackOffset - Return true if the given stack call argument is
3257 /// already available in the same position (relatively) of the caller's
3258 /// incoming argument stack.
3260 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3261 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3262 const X86InstrInfo *TII) {
3263 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3265 if (Arg.getOpcode() == ISD::CopyFromReg) {
3266 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3267 if (!TargetRegisterInfo::isVirtualRegister(VR))
3269 MachineInstr *Def = MRI->getVRegDef(VR);
3272 if (!Flags.isByVal()) {
3273 if (!TII->isLoadFromStackSlot(Def, FI))
3276 unsigned Opcode = Def->getOpcode();
3277 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3278 Def->getOperand(1).isFI()) {
3279 FI = Def->getOperand(1).getIndex();
3280 Bytes = Flags.getByValSize();
3284 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3285 if (Flags.isByVal())
3286 // ByVal argument is passed in as a pointer but it's now being
3287 // dereferenced. e.g.
3288 // define @foo(%struct.X* %A) {
3289 // tail call @bar(%struct.X* byval %A)
3292 SDValue Ptr = Ld->getBasePtr();
3293 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3296 FI = FINode->getIndex();
3297 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3298 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3299 FI = FINode->getIndex();
3300 Bytes = Flags.getByValSize();
3304 assert(FI != INT_MAX);
3305 if (!MFI->isFixedObjectIndex(FI))
3307 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3310 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3311 /// for tail call optimization. Targets which want to do tail call
3312 /// optimization should implement this function.
3314 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3315 CallingConv::ID CalleeCC,
3317 bool isCalleeStructRet,
3318 bool isCallerStructRet,
3320 const SmallVectorImpl<ISD::OutputArg> &Outs,
3321 const SmallVectorImpl<SDValue> &OutVals,
3322 const SmallVectorImpl<ISD::InputArg> &Ins,
3323 SelectionDAG &DAG) const {
3324 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3327 // If -tailcallopt is specified, make fastcc functions tail-callable.
3328 const MachineFunction &MF = DAG.getMachineFunction();
3329 const Function *CallerF = MF.getFunction();
3331 // If the function return type is x86_fp80 and the callee return type is not,
3332 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3333 // perform a tailcall optimization here.
3334 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3337 CallingConv::ID CallerCC = CallerF->getCallingConv();
3338 bool CCMatch = CallerCC == CalleeCC;
3339 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3340 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3342 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3343 if (IsTailCallConvention(CalleeCC) && CCMatch)
3348 // Look for obvious safe cases to perform tail call optimization that do not
3349 // require ABI changes. This is what gcc calls sibcall.
3351 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3352 // emit a special epilogue.
3353 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3354 DAG.getSubtarget().getRegisterInfo());
3355 if (RegInfo->needsStackRealignment(MF))
3358 // Also avoid sibcall optimization if either caller or callee uses struct
3359 // return semantics.
3360 if (isCalleeStructRet || isCallerStructRet)
3363 // An stdcall/thiscall caller is expected to clean up its arguments; the
3364 // callee isn't going to do that.
3365 // FIXME: this is more restrictive than needed. We could produce a tailcall
3366 // when the stack adjustment matches. For example, with a thiscall that takes
3367 // only one argument.
3368 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3369 CallerCC == CallingConv::X86_ThisCall))
3372 // Do not sibcall optimize vararg calls unless all arguments are passed via
3374 if (isVarArg && !Outs.empty()) {
3376 // Optimizing for varargs on Win64 is unlikely to be safe without
3377 // additional testing.
3378 if (IsCalleeWin64 || IsCallerWin64)
3381 SmallVector<CCValAssign, 16> ArgLocs;
3382 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3385 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3386 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3387 if (!ArgLocs[i].isRegLoc())
3391 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3392 // stack. Therefore, if it's not used by the call it is not safe to optimize
3393 // this into a sibcall.
3394 bool Unused = false;
3395 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3402 SmallVector<CCValAssign, 16> RVLocs;
3403 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3405 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3406 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3407 CCValAssign &VA = RVLocs[i];
3408 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3413 // If the calling conventions do not match, then we'd better make sure the
3414 // results are returned in the same way as what the caller expects.
3416 SmallVector<CCValAssign, 16> RVLocs1;
3417 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3419 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3421 SmallVector<CCValAssign, 16> RVLocs2;
3422 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3424 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3426 if (RVLocs1.size() != RVLocs2.size())
3428 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3429 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3431 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3433 if (RVLocs1[i].isRegLoc()) {
3434 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3437 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3443 // If the callee takes no arguments then go on to check the results of the
3445 if (!Outs.empty()) {
3446 // Check if stack adjustment is needed. For now, do not do this if any
3447 // argument is passed on the stack.
3448 SmallVector<CCValAssign, 16> ArgLocs;
3449 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3452 // Allocate shadow area for Win64
3454 CCInfo.AllocateStack(32, 8);
3456 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3457 if (CCInfo.getNextStackOffset()) {
3458 MachineFunction &MF = DAG.getMachineFunction();
3459 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3462 // Check if the arguments are already laid out in the right way as
3463 // the caller's fixed stack objects.
3464 MachineFrameInfo *MFI = MF.getFrameInfo();
3465 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3466 const X86InstrInfo *TII =
3467 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3468 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3469 CCValAssign &VA = ArgLocs[i];
3470 SDValue Arg = OutVals[i];
3471 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3472 if (VA.getLocInfo() == CCValAssign::Indirect)
3474 if (!VA.isRegLoc()) {
3475 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3482 // If the tailcall address may be in a register, then make sure it's
3483 // possible to register allocate for it. In 32-bit, the call address can
3484 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3485 // callee-saved registers are restored. These happen to be the same
3486 // registers used to pass 'inreg' arguments so watch out for those.
3487 if (!Subtarget->is64Bit() &&
3488 ((!isa<GlobalAddressSDNode>(Callee) &&
3489 !isa<ExternalSymbolSDNode>(Callee)) ||
3490 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3491 unsigned NumInRegs = 0;
3492 // In PIC we need an extra register to formulate the address computation
3494 unsigned MaxInRegs =
3495 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3497 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3498 CCValAssign &VA = ArgLocs[i];
3501 unsigned Reg = VA.getLocReg();
3504 case X86::EAX: case X86::EDX: case X86::ECX:
3505 if (++NumInRegs == MaxInRegs)
3517 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3518 const TargetLibraryInfo *libInfo) const {
3519 return X86::createFastISel(funcInfo, libInfo);
3522 //===----------------------------------------------------------------------===//
3523 // Other Lowering Hooks
3524 //===----------------------------------------------------------------------===//
3526 static bool MayFoldLoad(SDValue Op) {
3527 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3530 static bool MayFoldIntoStore(SDValue Op) {
3531 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3534 static bool isTargetShuffle(unsigned Opcode) {
3536 default: return false;
3537 case X86ISD::BLENDI:
3538 case X86ISD::PSHUFB:
3539 case X86ISD::PSHUFD:
3540 case X86ISD::PSHUFHW:
3541 case X86ISD::PSHUFLW:
3543 case X86ISD::PALIGNR:
3544 case X86ISD::MOVLHPS:
3545 case X86ISD::MOVLHPD:
3546 case X86ISD::MOVHLPS:
3547 case X86ISD::MOVLPS:
3548 case X86ISD::MOVLPD:
3549 case X86ISD::MOVSHDUP:
3550 case X86ISD::MOVSLDUP:
3551 case X86ISD::MOVDDUP:
3554 case X86ISD::UNPCKL:
3555 case X86ISD::UNPCKH:
3556 case X86ISD::VPERMILPI:
3557 case X86ISD::VPERM2X128:
3558 case X86ISD::VPERMI:
3563 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3564 SDValue V1, SelectionDAG &DAG) {
3566 default: llvm_unreachable("Unknown x86 shuffle node");
3567 case X86ISD::MOVSHDUP:
3568 case X86ISD::MOVSLDUP:
3569 case X86ISD::MOVDDUP:
3570 return DAG.getNode(Opc, dl, VT, V1);
3574 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3575 SDValue V1, unsigned TargetMask,
3576 SelectionDAG &DAG) {
3578 default: llvm_unreachable("Unknown x86 shuffle node");
3579 case X86ISD::PSHUFD:
3580 case X86ISD::PSHUFHW:
3581 case X86ISD::PSHUFLW:
3582 case X86ISD::VPERMILPI:
3583 case X86ISD::VPERMI:
3584 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3588 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3589 SDValue V1, SDValue V2, unsigned TargetMask,
3590 SelectionDAG &DAG) {
3592 default: llvm_unreachable("Unknown x86 shuffle node");
3593 case X86ISD::PALIGNR:
3594 case X86ISD::VALIGN:
3596 case X86ISD::VPERM2X128:
3597 return DAG.getNode(Opc, dl, VT, V1, V2,
3598 DAG.getConstant(TargetMask, MVT::i8));
3602 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3603 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3605 default: llvm_unreachable("Unknown x86 shuffle node");
3606 case X86ISD::MOVLHPS:
3607 case X86ISD::MOVLHPD:
3608 case X86ISD::MOVHLPS:
3609 case X86ISD::MOVLPS:
3610 case X86ISD::MOVLPD:
3613 case X86ISD::UNPCKL:
3614 case X86ISD::UNPCKH:
3615 return DAG.getNode(Opc, dl, VT, V1, V2);
3619 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3620 MachineFunction &MF = DAG.getMachineFunction();
3621 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3622 DAG.getSubtarget().getRegisterInfo());
3623 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3624 int ReturnAddrIndex = FuncInfo->getRAIndex();
3626 if (ReturnAddrIndex == 0) {
3627 // Set up a frame object for the return address.
3628 unsigned SlotSize = RegInfo->getSlotSize();
3629 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3632 FuncInfo->setRAIndex(ReturnAddrIndex);
3635 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3638 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3639 bool hasSymbolicDisplacement) {
3640 // Offset should fit into 32 bit immediate field.
3641 if (!isInt<32>(Offset))
3644 // If we don't have a symbolic displacement - we don't have any extra
3646 if (!hasSymbolicDisplacement)
3649 // FIXME: Some tweaks might be needed for medium code model.
3650 if (M != CodeModel::Small && M != CodeModel::Kernel)
3653 // For small code model we assume that latest object is 16MB before end of 31
3654 // bits boundary. We may also accept pretty large negative constants knowing
3655 // that all objects are in the positive half of address space.
3656 if (M == CodeModel::Small && Offset < 16*1024*1024)
3659 // For kernel code model we know that all object resist in the negative half
3660 // of 32bits address space. We may not accept negative offsets, since they may
3661 // be just off and we may accept pretty large positive ones.
3662 if (M == CodeModel::Kernel && Offset > 0)
3668 /// isCalleePop - Determines whether the callee is required to pop its
3669 /// own arguments. Callee pop is necessary to support tail calls.
3670 bool X86::isCalleePop(CallingConv::ID CallingConv,
3671 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3672 switch (CallingConv) {
3675 case CallingConv::X86_StdCall:
3676 case CallingConv::X86_FastCall:
3677 case CallingConv::X86_ThisCall:
3679 case CallingConv::Fast:
3680 case CallingConv::GHC:
3681 case CallingConv::HiPE:
3688 /// \brief Return true if the condition is an unsigned comparison operation.
3689 static bool isX86CCUnsigned(unsigned X86CC) {
3691 default: llvm_unreachable("Invalid integer condition!");
3692 case X86::COND_E: return true;
3693 case X86::COND_G: return false;
3694 case X86::COND_GE: return false;
3695 case X86::COND_L: return false;
3696 case X86::COND_LE: return false;
3697 case X86::COND_NE: return true;
3698 case X86::COND_B: return true;
3699 case X86::COND_A: return true;
3700 case X86::COND_BE: return true;
3701 case X86::COND_AE: return true;
3703 llvm_unreachable("covered switch fell through?!");
3706 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3707 /// specific condition code, returning the condition code and the LHS/RHS of the
3708 /// comparison to make.
3709 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3710 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3712 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3713 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3714 // X > -1 -> X == 0, jump !sign.
3715 RHS = DAG.getConstant(0, RHS.getValueType());
3716 return X86::COND_NS;
3718 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3719 // X < 0 -> X == 0, jump on sign.
3722 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3724 RHS = DAG.getConstant(0, RHS.getValueType());
3725 return X86::COND_LE;
3729 switch (SetCCOpcode) {
3730 default: llvm_unreachable("Invalid integer condition!");
3731 case ISD::SETEQ: return X86::COND_E;
3732 case ISD::SETGT: return X86::COND_G;
3733 case ISD::SETGE: return X86::COND_GE;
3734 case ISD::SETLT: return X86::COND_L;
3735 case ISD::SETLE: return X86::COND_LE;
3736 case ISD::SETNE: return X86::COND_NE;
3737 case ISD::SETULT: return X86::COND_B;
3738 case ISD::SETUGT: return X86::COND_A;
3739 case ISD::SETULE: return X86::COND_BE;
3740 case ISD::SETUGE: return X86::COND_AE;
3744 // First determine if it is required or is profitable to flip the operands.
3746 // If LHS is a foldable load, but RHS is not, flip the condition.
3747 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3748 !ISD::isNON_EXTLoad(RHS.getNode())) {
3749 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3750 std::swap(LHS, RHS);
3753 switch (SetCCOpcode) {
3759 std::swap(LHS, RHS);
3763 // On a floating point condition, the flags are set as follows:
3765 // 0 | 0 | 0 | X > Y
3766 // 0 | 0 | 1 | X < Y
3767 // 1 | 0 | 0 | X == Y
3768 // 1 | 1 | 1 | unordered
3769 switch (SetCCOpcode) {
3770 default: llvm_unreachable("Condcode should be pre-legalized away");
3772 case ISD::SETEQ: return X86::COND_E;
3773 case ISD::SETOLT: // flipped
3775 case ISD::SETGT: return X86::COND_A;
3776 case ISD::SETOLE: // flipped
3778 case ISD::SETGE: return X86::COND_AE;
3779 case ISD::SETUGT: // flipped
3781 case ISD::SETLT: return X86::COND_B;
3782 case ISD::SETUGE: // flipped
3784 case ISD::SETLE: return X86::COND_BE;
3786 case ISD::SETNE: return X86::COND_NE;
3787 case ISD::SETUO: return X86::COND_P;
3788 case ISD::SETO: return X86::COND_NP;
3790 case ISD::SETUNE: return X86::COND_INVALID;
3794 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3795 /// code. Current x86 isa includes the following FP cmov instructions:
3796 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3797 static bool hasFPCMov(unsigned X86CC) {
3813 /// isFPImmLegal - Returns true if the target can instruction select the
3814 /// specified FP immediate natively. If false, the legalizer will
3815 /// materialize the FP immediate as a load from a constant pool.
3816 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3817 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3818 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3824 /// \brief Returns true if it is beneficial to convert a load of a constant
3825 /// to just the constant itself.
3826 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3828 assert(Ty->isIntegerTy());
3830 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3831 if (BitSize == 0 || BitSize > 64)
3836 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3837 /// the specified range (L, H].
3838 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3839 return (Val < 0) || (Val >= Low && Val < Hi);
3842 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3843 /// specified value.
3844 static bool isUndefOrEqual(int Val, int CmpVal) {
3845 return (Val < 0 || Val == CmpVal);
3848 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3849 /// from position Pos and ending in Pos+Size, falls within the specified
3850 /// sequential range (L, L+Pos]. or is undef.
3851 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3852 unsigned Pos, unsigned Size, int Low) {
3853 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3854 if (!isUndefOrEqual(Mask[i], Low))
3859 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3860 /// is suitable for input to PSHUFD. That is, it doesn't reference the other
3861 /// operand - by default will match for first operand.
3862 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT,
3863 bool TestSecondOperand = false) {
3864 if (VT != MVT::v4f32 && VT != MVT::v4i32 &&
3865 VT != MVT::v2f64 && VT != MVT::v2i64)
3868 unsigned NumElems = VT.getVectorNumElements();
3869 unsigned Lo = TestSecondOperand ? NumElems : 0;
3870 unsigned Hi = Lo + NumElems;
3872 for (unsigned i = 0; i < NumElems; ++i)
3873 if (!isUndefOrInRange(Mask[i], (int)Lo, (int)Hi))
3879 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3880 /// is suitable for input to PSHUFHW.
3881 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3882 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3885 // Lower quadword copied in order or undef.
3886 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3889 // Upper quadword shuffled.
3890 for (unsigned i = 4; i != 8; ++i)
3891 if (!isUndefOrInRange(Mask[i], 4, 8))
3894 if (VT == MVT::v16i16) {
3895 // Lower quadword copied in order or undef.
3896 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3899 // Upper quadword shuffled.
3900 for (unsigned i = 12; i != 16; ++i)
3901 if (!isUndefOrInRange(Mask[i], 12, 16))
3908 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3909 /// is suitable for input to PSHUFLW.
3910 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3911 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3914 // Upper quadword copied in order.
3915 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3918 // Lower quadword shuffled.
3919 for (unsigned i = 0; i != 4; ++i)
3920 if (!isUndefOrInRange(Mask[i], 0, 4))
3923 if (VT == MVT::v16i16) {
3924 // Upper quadword copied in order.
3925 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3928 // Lower quadword shuffled.
3929 for (unsigned i = 8; i != 12; ++i)
3930 if (!isUndefOrInRange(Mask[i], 8, 12))
3937 /// \brief Return true if the mask specifies a shuffle of elements that is
3938 /// suitable for input to intralane (palignr) or interlane (valign) vector
3940 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3941 unsigned NumElts = VT.getVectorNumElements();
3942 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3943 unsigned NumLaneElts = NumElts/NumLanes;
3945 // Do not handle 64-bit element shuffles with palignr.
3946 if (NumLaneElts == 2)
3949 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3951 for (i = 0; i != NumLaneElts; ++i) {
3956 // Lane is all undef, go to next lane
3957 if (i == NumLaneElts)
3960 int Start = Mask[i+l];
3962 // Make sure its in this lane in one of the sources
3963 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3964 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3967 // If not lane 0, then we must match lane 0
3968 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3971 // Correct second source to be contiguous with first source
3972 if (Start >= (int)NumElts)
3973 Start -= NumElts - NumLaneElts;
3975 // Make sure we're shifting in the right direction.
3976 if (Start <= (int)(i+l))
3981 // Check the rest of the elements to see if they are consecutive.
3982 for (++i; i != NumLaneElts; ++i) {
3983 int Idx = Mask[i+l];
3985 // Make sure its in this lane
3986 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3987 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3990 // If not lane 0, then we must match lane 0
3991 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3994 if (Idx >= (int)NumElts)
3995 Idx -= NumElts - NumLaneElts;
3997 if (!isUndefOrEqual(Idx, Start+i))
4006 /// \brief Return true if the node specifies a shuffle of elements that is
4007 /// suitable for input to PALIGNR.
4008 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4009 const X86Subtarget *Subtarget) {
4010 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4011 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4012 VT.is512BitVector())
4013 // FIXME: Add AVX512BW.
4016 return isAlignrMask(Mask, VT, false);
4019 /// \brief Return true if the node specifies a shuffle of elements that is
4020 /// suitable for input to VALIGN.
4021 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4022 const X86Subtarget *Subtarget) {
4023 // FIXME: Add AVX512VL.
4024 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4026 return isAlignrMask(Mask, VT, true);
4029 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4030 /// the two vector operands have swapped position.
4031 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4032 unsigned NumElems) {
4033 for (unsigned i = 0; i != NumElems; ++i) {
4037 else if (idx < (int)NumElems)
4038 Mask[i] = idx + NumElems;
4040 Mask[i] = idx - NumElems;
4044 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4045 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4046 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4047 /// reverse of what x86 shuffles want.
4048 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4050 unsigned NumElems = VT.getVectorNumElements();
4051 unsigned NumLanes = VT.getSizeInBits()/128;
4052 unsigned NumLaneElems = NumElems/NumLanes;
4054 if (NumLaneElems != 2 && NumLaneElems != 4)
4057 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4058 bool symetricMaskRequired =
4059 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4061 // VSHUFPSY divides the resulting vector into 4 chunks.
4062 // The sources are also splitted into 4 chunks, and each destination
4063 // chunk must come from a different source chunk.
4065 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4066 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4068 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4069 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4071 // VSHUFPDY divides the resulting vector into 4 chunks.
4072 // The sources are also splitted into 4 chunks, and each destination
4073 // chunk must come from a different source chunk.
4075 // SRC1 => X3 X2 X1 X0
4076 // SRC2 => Y3 Y2 Y1 Y0
4078 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4080 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4081 unsigned HalfLaneElems = NumLaneElems/2;
4082 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4083 for (unsigned i = 0; i != NumLaneElems; ++i) {
4084 int Idx = Mask[i+l];
4085 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4086 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4088 // For VSHUFPSY, the mask of the second half must be the same as the
4089 // first but with the appropriate offsets. This works in the same way as
4090 // VPERMILPS works with masks.
4091 if (!symetricMaskRequired || Idx < 0)
4093 if (MaskVal[i] < 0) {
4094 MaskVal[i] = Idx - l;
4097 if ((signed)(Idx - l) != MaskVal[i])
4105 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4106 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4107 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4108 if (!VT.is128BitVector())
4111 unsigned NumElems = VT.getVectorNumElements();
4116 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4117 return isUndefOrEqual(Mask[0], 6) &&
4118 isUndefOrEqual(Mask[1], 7) &&
4119 isUndefOrEqual(Mask[2], 2) &&
4120 isUndefOrEqual(Mask[3], 3);
4123 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4124 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4126 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4127 if (!VT.is128BitVector())
4130 unsigned NumElems = VT.getVectorNumElements();
4135 return isUndefOrEqual(Mask[0], 2) &&
4136 isUndefOrEqual(Mask[1], 3) &&
4137 isUndefOrEqual(Mask[2], 2) &&
4138 isUndefOrEqual(Mask[3], 3);
4141 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4142 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4143 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4144 if (!VT.is128BitVector())
4147 unsigned NumElems = VT.getVectorNumElements();
4149 if (NumElems != 2 && NumElems != 4)
4152 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4153 if (!isUndefOrEqual(Mask[i], i + NumElems))
4156 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4157 if (!isUndefOrEqual(Mask[i], i))
4163 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4164 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4165 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4166 if (!VT.is128BitVector())
4169 unsigned NumElems = VT.getVectorNumElements();
4171 if (NumElems != 2 && NumElems != 4)
4174 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4175 if (!isUndefOrEqual(Mask[i], i))
4178 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4179 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4185 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4186 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4187 /// i. e: If all but one element come from the same vector.
4188 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4189 // TODO: Deal with AVX's VINSERTPS
4190 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4193 unsigned CorrectPosV1 = 0;
4194 unsigned CorrectPosV2 = 0;
4195 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4196 if (Mask[i] == -1) {
4204 else if (Mask[i] == i + 4)
4208 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4209 // We have 3 elements (undefs count as elements from any vector) from one
4210 // vector, and one from another.
4217 // Some special combinations that can be optimized.
4220 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4221 SelectionDAG &DAG) {
4222 MVT VT = SVOp->getSimpleValueType(0);
4225 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4228 ArrayRef<int> Mask = SVOp->getMask();
4230 // These are the special masks that may be optimized.
4231 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4232 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4233 bool MatchEvenMask = true;
4234 bool MatchOddMask = true;
4235 for (int i=0; i<8; ++i) {
4236 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4237 MatchEvenMask = false;
4238 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4239 MatchOddMask = false;
4242 if (!MatchEvenMask && !MatchOddMask)
4245 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4247 SDValue Op0 = SVOp->getOperand(0);
4248 SDValue Op1 = SVOp->getOperand(1);
4250 if (MatchEvenMask) {
4251 // Shift the second operand right to 32 bits.
4252 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4253 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4255 // Shift the first operand left to 32 bits.
4256 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4257 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4259 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4260 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4263 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4264 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4265 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4266 bool HasInt256, bool V2IsSplat = false) {
4268 assert(VT.getSizeInBits() >= 128 &&
4269 "Unsupported vector type for unpckl");
4271 unsigned NumElts = VT.getVectorNumElements();
4272 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4273 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4276 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4277 "Unsupported vector type for unpckh");
4279 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4280 unsigned NumLanes = VT.getSizeInBits()/128;
4281 unsigned NumLaneElts = NumElts/NumLanes;
4283 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4284 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4285 int BitI = Mask[l+i];
4286 int BitI1 = Mask[l+i+1];
4287 if (!isUndefOrEqual(BitI, j))
4290 if (!isUndefOrEqual(BitI1, NumElts))
4293 if (!isUndefOrEqual(BitI1, j + NumElts))
4302 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4303 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4304 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4305 bool HasInt256, bool V2IsSplat = false) {
4306 assert(VT.getSizeInBits() >= 128 &&
4307 "Unsupported vector type for unpckh");
4309 unsigned NumElts = VT.getVectorNumElements();
4310 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4311 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4314 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4315 "Unsupported vector type for unpckh");
4317 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4318 unsigned NumLanes = VT.getSizeInBits()/128;
4319 unsigned NumLaneElts = NumElts/NumLanes;
4321 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4322 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4323 int BitI = Mask[l+i];
4324 int BitI1 = Mask[l+i+1];
4325 if (!isUndefOrEqual(BitI, j))
4328 if (isUndefOrEqual(BitI1, NumElts))
4331 if (!isUndefOrEqual(BitI1, j+NumElts))
4339 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4340 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4342 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4343 unsigned NumElts = VT.getVectorNumElements();
4344 bool Is256BitVec = VT.is256BitVector();
4346 if (VT.is512BitVector())
4348 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4349 "Unsupported vector type for unpckh");
4351 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4352 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4355 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4356 // FIXME: Need a better way to get rid of this, there's no latency difference
4357 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4358 // the former later. We should also remove the "_undef" special mask.
4359 if (NumElts == 4 && Is256BitVec)
4362 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4363 // independently on 128-bit lanes.
4364 unsigned NumLanes = VT.getSizeInBits()/128;
4365 unsigned NumLaneElts = NumElts/NumLanes;
4367 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4368 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4369 int BitI = Mask[l+i];
4370 int BitI1 = Mask[l+i+1];
4372 if (!isUndefOrEqual(BitI, j))
4374 if (!isUndefOrEqual(BitI1, j))
4382 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4383 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4385 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4386 unsigned NumElts = VT.getVectorNumElements();
4388 if (VT.is512BitVector())
4391 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4392 "Unsupported vector type for unpckh");
4394 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4395 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4398 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4399 // independently on 128-bit lanes.
4400 unsigned NumLanes = VT.getSizeInBits()/128;
4401 unsigned NumLaneElts = NumElts/NumLanes;
4403 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4404 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4405 int BitI = Mask[l+i];
4406 int BitI1 = Mask[l+i+1];
4407 if (!isUndefOrEqual(BitI, j))
4409 if (!isUndefOrEqual(BitI1, j))
4416 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4417 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4418 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4419 if (!VT.is512BitVector())
4422 unsigned NumElts = VT.getVectorNumElements();
4423 unsigned HalfSize = NumElts/2;
4424 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4425 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4430 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4431 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4439 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4440 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4441 /// MOVSD, and MOVD, i.e. setting the lowest element.
4442 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4443 if (VT.getVectorElementType().getSizeInBits() < 32)
4445 if (!VT.is128BitVector())
4448 unsigned NumElts = VT.getVectorNumElements();
4450 if (!isUndefOrEqual(Mask[0], NumElts))
4453 for (unsigned i = 1; i != NumElts; ++i)
4454 if (!isUndefOrEqual(Mask[i], i))
4460 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4461 /// as permutations between 128-bit chunks or halves. As an example: this
4463 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4464 /// The first half comes from the second half of V1 and the second half from the
4465 /// the second half of V2.
4466 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4467 if (!HasFp256 || !VT.is256BitVector())
4470 // The shuffle result is divided into half A and half B. In total the two
4471 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4472 // B must come from C, D, E or F.
4473 unsigned HalfSize = VT.getVectorNumElements()/2;
4474 bool MatchA = false, MatchB = false;
4476 // Check if A comes from one of C, D, E, F.
4477 for (unsigned Half = 0; Half != 4; ++Half) {
4478 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4484 // Check if B comes from one of C, D, E, F.
4485 for (unsigned Half = 0; Half != 4; ++Half) {
4486 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4492 return MatchA && MatchB;
4495 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4496 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4497 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4498 MVT VT = SVOp->getSimpleValueType(0);
4500 unsigned HalfSize = VT.getVectorNumElements()/2;
4502 unsigned FstHalf = 0, SndHalf = 0;
4503 for (unsigned i = 0; i < HalfSize; ++i) {
4504 if (SVOp->getMaskElt(i) > 0) {
4505 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4509 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4510 if (SVOp->getMaskElt(i) > 0) {
4511 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4516 return (FstHalf | (SndHalf << 4));
4519 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4520 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4521 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4525 unsigned NumElts = VT.getVectorNumElements();
4527 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4528 for (unsigned i = 0; i != NumElts; ++i) {
4531 Imm8 |= Mask[i] << (i*2);
4536 unsigned LaneSize = 4;
4537 SmallVector<int, 4> MaskVal(LaneSize, -1);
4539 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4540 for (unsigned i = 0; i != LaneSize; ++i) {
4541 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4545 if (MaskVal[i] < 0) {
4546 MaskVal[i] = Mask[i+l] - l;
4547 Imm8 |= MaskVal[i] << (i*2);
4550 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4557 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4558 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4559 /// Note that VPERMIL mask matching is different depending whether theunderlying
4560 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4561 /// to the same elements of the low, but to the higher half of the source.
4562 /// In VPERMILPD the two lanes could be shuffled independently of each other
4563 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4564 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4565 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4566 if (VT.getSizeInBits() < 256 || EltSize < 32)
4568 bool symetricMaskRequired = (EltSize == 32);
4569 unsigned NumElts = VT.getVectorNumElements();
4571 unsigned NumLanes = VT.getSizeInBits()/128;
4572 unsigned LaneSize = NumElts/NumLanes;
4573 // 2 or 4 elements in one lane
4575 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4576 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4577 for (unsigned i = 0; i != LaneSize; ++i) {
4578 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4580 if (symetricMaskRequired) {
4581 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4582 ExpectedMaskVal[i] = Mask[i+l] - l;
4585 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4593 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4594 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4595 /// element of vector 2 and the other elements to come from vector 1 in order.
4596 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4597 bool V2IsSplat = false, bool V2IsUndef = false) {
4598 if (!VT.is128BitVector())
4601 unsigned NumOps = VT.getVectorNumElements();
4602 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4605 if (!isUndefOrEqual(Mask[0], 0))
4608 for (unsigned i = 1; i != NumOps; ++i)
4609 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4610 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4611 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4617 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4618 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4619 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4620 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4621 const X86Subtarget *Subtarget) {
4622 if (!Subtarget->hasSSE3())
4625 unsigned NumElems = VT.getVectorNumElements();
4627 if ((VT.is128BitVector() && NumElems != 4) ||
4628 (VT.is256BitVector() && NumElems != 8) ||
4629 (VT.is512BitVector() && NumElems != 16))
4632 // "i+1" is the value the indexed mask element must have
4633 for (unsigned i = 0; i != NumElems; i += 2)
4634 if (!isUndefOrEqual(Mask[i], i+1) ||
4635 !isUndefOrEqual(Mask[i+1], i+1))
4641 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4642 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4643 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4644 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4645 const X86Subtarget *Subtarget) {
4646 if (!Subtarget->hasSSE3())
4649 unsigned NumElems = VT.getVectorNumElements();
4651 if ((VT.is128BitVector() && NumElems != 4) ||
4652 (VT.is256BitVector() && NumElems != 8) ||
4653 (VT.is512BitVector() && NumElems != 16))
4656 // "i" is the value the indexed mask element must have
4657 for (unsigned i = 0; i != NumElems; i += 2)
4658 if (!isUndefOrEqual(Mask[i], i) ||
4659 !isUndefOrEqual(Mask[i+1], i))
4665 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4666 /// specifies a shuffle of elements that is suitable for input to 256-bit
4667 /// version of MOVDDUP.
4668 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4669 if (!HasFp256 || !VT.is256BitVector())
4672 unsigned NumElts = VT.getVectorNumElements();
4676 for (unsigned i = 0; i != NumElts/2; ++i)
4677 if (!isUndefOrEqual(Mask[i], 0))
4679 for (unsigned i = NumElts/2; i != NumElts; ++i)
4680 if (!isUndefOrEqual(Mask[i], NumElts/2))
4685 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4686 /// specifies a shuffle of elements that is suitable for input to 128-bit
4687 /// version of MOVDDUP.
4688 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4689 if (!VT.is128BitVector())
4692 unsigned e = VT.getVectorNumElements() / 2;
4693 for (unsigned i = 0; i != e; ++i)
4694 if (!isUndefOrEqual(Mask[i], i))
4696 for (unsigned i = 0; i != e; ++i)
4697 if (!isUndefOrEqual(Mask[e+i], i))
4702 /// isVEXTRACTIndex - Return true if the specified
4703 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4704 /// suitable for instruction that extract 128 or 256 bit vectors
4705 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4706 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4707 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4710 // The index should be aligned on a vecWidth-bit boundary.
4712 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4714 MVT VT = N->getSimpleValueType(0);
4715 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4716 bool Result = (Index * ElSize) % vecWidth == 0;
4721 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4722 /// operand specifies a subvector insert that is suitable for input to
4723 /// insertion of 128 or 256-bit subvectors
4724 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4725 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4726 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4728 // The index should be aligned on a vecWidth-bit boundary.
4730 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4732 MVT VT = N->getSimpleValueType(0);
4733 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4734 bool Result = (Index * ElSize) % vecWidth == 0;
4739 bool X86::isVINSERT128Index(SDNode *N) {
4740 return isVINSERTIndex(N, 128);
4743 bool X86::isVINSERT256Index(SDNode *N) {
4744 return isVINSERTIndex(N, 256);
4747 bool X86::isVEXTRACT128Index(SDNode *N) {
4748 return isVEXTRACTIndex(N, 128);
4751 bool X86::isVEXTRACT256Index(SDNode *N) {
4752 return isVEXTRACTIndex(N, 256);
4755 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4756 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4757 /// Handles 128-bit and 256-bit.
4758 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4759 MVT VT = N->getSimpleValueType(0);
4761 assert((VT.getSizeInBits() >= 128) &&
4762 "Unsupported vector type for PSHUF/SHUFP");
4764 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4765 // independently on 128-bit lanes.
4766 unsigned NumElts = VT.getVectorNumElements();
4767 unsigned NumLanes = VT.getSizeInBits()/128;
4768 unsigned NumLaneElts = NumElts/NumLanes;
4770 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4771 "Only supports 2, 4 or 8 elements per lane");
4773 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4775 for (unsigned i = 0; i != NumElts; ++i) {
4776 int Elt = N->getMaskElt(i);
4777 if (Elt < 0) continue;
4778 Elt &= NumLaneElts - 1;
4779 unsigned ShAmt = (i << Shift) % 8;
4780 Mask |= Elt << ShAmt;
4786 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4787 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4788 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4789 MVT VT = N->getSimpleValueType(0);
4791 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4792 "Unsupported vector type for PSHUFHW");
4794 unsigned NumElts = VT.getVectorNumElements();
4797 for (unsigned l = 0; l != NumElts; l += 8) {
4798 // 8 nodes per lane, but we only care about the last 4.
4799 for (unsigned i = 0; i < 4; ++i) {
4800 int Elt = N->getMaskElt(l+i+4);
4801 if (Elt < 0) continue;
4802 Elt &= 0x3; // only 2-bits.
4803 Mask |= Elt << (i * 2);
4810 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4811 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4812 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4813 MVT VT = N->getSimpleValueType(0);
4815 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4816 "Unsupported vector type for PSHUFHW");
4818 unsigned NumElts = VT.getVectorNumElements();
4821 for (unsigned l = 0; l != NumElts; l += 8) {
4822 // 8 nodes per lane, but we only care about the first 4.
4823 for (unsigned i = 0; i < 4; ++i) {
4824 int Elt = N->getMaskElt(l+i);
4825 if (Elt < 0) continue;
4826 Elt &= 0x3; // only 2-bits
4827 Mask |= Elt << (i * 2);
4834 /// \brief Return the appropriate immediate to shuffle the specified
4835 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4836 /// VALIGN (if Interlane is true) instructions.
4837 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4839 MVT VT = SVOp->getSimpleValueType(0);
4840 unsigned EltSize = InterLane ? 1 :
4841 VT.getVectorElementType().getSizeInBits() >> 3;
4843 unsigned NumElts = VT.getVectorNumElements();
4844 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4845 unsigned NumLaneElts = NumElts/NumLanes;
4849 for (i = 0; i != NumElts; ++i) {
4850 Val = SVOp->getMaskElt(i);
4854 if (Val >= (int)NumElts)
4855 Val -= NumElts - NumLaneElts;
4857 assert(Val - i > 0 && "PALIGNR imm should be positive");
4858 return (Val - i) * EltSize;
4861 /// \brief Return the appropriate immediate to shuffle the specified
4862 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4863 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4864 return getShuffleAlignrImmediate(SVOp, false);
4867 /// \brief Return the appropriate immediate to shuffle the specified
4868 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4869 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4870 return getShuffleAlignrImmediate(SVOp, true);
4874 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4875 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4876 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4877 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4880 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4882 MVT VecVT = N->getOperand(0).getSimpleValueType();
4883 MVT ElVT = VecVT.getVectorElementType();
4885 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4886 return Index / NumElemsPerChunk;
4889 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4890 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4891 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4892 llvm_unreachable("Illegal insert subvector for VINSERT");
4895 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4897 MVT VecVT = N->getSimpleValueType(0);
4898 MVT ElVT = VecVT.getVectorElementType();
4900 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4901 return Index / NumElemsPerChunk;
4904 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4905 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4906 /// and VINSERTI128 instructions.
4907 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4908 return getExtractVEXTRACTImmediate(N, 128);
4911 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4912 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4913 /// and VINSERTI64x4 instructions.
4914 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4915 return getExtractVEXTRACTImmediate(N, 256);
4918 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4919 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4920 /// and VINSERTI128 instructions.
4921 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4922 return getInsertVINSERTImmediate(N, 128);
4925 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4926 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4927 /// and VINSERTI64x4 instructions.
4928 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4929 return getInsertVINSERTImmediate(N, 256);
4932 /// isZero - Returns true if Elt is a constant integer zero
4933 static bool isZero(SDValue V) {
4934 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4935 return C && C->isNullValue();
4938 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4940 bool X86::isZeroNode(SDValue Elt) {
4943 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4944 return CFP->getValueAPF().isPosZero();
4948 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4949 /// match movhlps. The lower half elements should come from upper half of
4950 /// V1 (and in order), and the upper half elements should come from the upper
4951 /// half of V2 (and in order).
4952 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4953 if (!VT.is128BitVector())
4955 if (VT.getVectorNumElements() != 4)
4957 for (unsigned i = 0, e = 2; i != e; ++i)
4958 if (!isUndefOrEqual(Mask[i], i+2))
4960 for (unsigned i = 2; i != 4; ++i)
4961 if (!isUndefOrEqual(Mask[i], i+4))
4966 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4967 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4969 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4970 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4972 N = N->getOperand(0).getNode();
4973 if (!ISD::isNON_EXTLoad(N))
4976 *LD = cast<LoadSDNode>(N);
4980 // Test whether the given value is a vector value which will be legalized
4982 static bool WillBeConstantPoolLoad(SDNode *N) {
4983 if (N->getOpcode() != ISD::BUILD_VECTOR)
4986 // Check for any non-constant elements.
4987 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4988 switch (N->getOperand(i).getNode()->getOpcode()) {
4990 case ISD::ConstantFP:
4997 // Vectors of all-zeros and all-ones are materialized with special
4998 // instructions rather than being loaded.
4999 return !ISD::isBuildVectorAllZeros(N) &&
5000 !ISD::isBuildVectorAllOnes(N);
5003 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5004 /// match movlp{s|d}. The lower half elements should come from lower half of
5005 /// V1 (and in order), and the upper half elements should come from the upper
5006 /// half of V2 (and in order). And since V1 will become the source of the
5007 /// MOVLP, it must be either a vector load or a scalar load to vector.
5008 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5009 ArrayRef<int> Mask, MVT VT) {
5010 if (!VT.is128BitVector())
5013 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5015 // Is V2 is a vector load, don't do this transformation. We will try to use
5016 // load folding shufps op.
5017 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5020 unsigned NumElems = VT.getVectorNumElements();
5022 if (NumElems != 2 && NumElems != 4)
5024 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5025 if (!isUndefOrEqual(Mask[i], i))
5027 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5028 if (!isUndefOrEqual(Mask[i], i+NumElems))
5033 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5034 /// to an zero vector.
5035 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5036 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5037 SDValue V1 = N->getOperand(0);
5038 SDValue V2 = N->getOperand(1);
5039 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5040 for (unsigned i = 0; i != NumElems; ++i) {
5041 int Idx = N->getMaskElt(i);
5042 if (Idx >= (int)NumElems) {
5043 unsigned Opc = V2.getOpcode();
5044 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5046 if (Opc != ISD::BUILD_VECTOR ||
5047 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5049 } else if (Idx >= 0) {
5050 unsigned Opc = V1.getOpcode();
5051 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5053 if (Opc != ISD::BUILD_VECTOR ||
5054 !X86::isZeroNode(V1.getOperand(Idx)))
5061 /// getZeroVector - Returns a vector of specified type with all zero elements.
5063 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5064 SelectionDAG &DAG, SDLoc dl) {
5065 assert(VT.isVector() && "Expected a vector type");
5067 // Always build SSE zero vectors as <4 x i32> bitcasted
5068 // to their dest type. This ensures they get CSE'd.
5070 if (VT.is128BitVector()) { // SSE
5071 if (Subtarget->hasSSE2()) { // SSE2
5072 SDValue Cst = DAG.getConstant(0, MVT::i32);
5073 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5075 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5076 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5078 } else if (VT.is256BitVector()) { // AVX
5079 if (Subtarget->hasInt256()) { // AVX2
5080 SDValue Cst = DAG.getConstant(0, MVT::i32);
5081 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5082 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5084 // 256-bit logic and arithmetic instructions in AVX are all
5085 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5086 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5087 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5088 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5090 } else if (VT.is512BitVector()) { // AVX-512
5091 SDValue Cst = DAG.getConstant(0, MVT::i32);
5092 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5093 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5094 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5095 } else if (VT.getScalarType() == MVT::i1) {
5096 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5097 SDValue Cst = DAG.getConstant(0, MVT::i1);
5098 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5099 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5101 llvm_unreachable("Unexpected vector type");
5103 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5106 /// getOnesVector - Returns a vector of specified type with all bits set.
5107 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5108 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5109 /// Then bitcast to their original type, ensuring they get CSE'd.
5110 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5112 assert(VT.isVector() && "Expected a vector type");
5114 SDValue Cst = DAG.getConstant(~0U, MVT::i32);
5116 if (VT.is256BitVector()) {
5117 if (HasInt256) { // AVX2
5118 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5119 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5121 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5122 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5124 } else if (VT.is128BitVector()) {
5125 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5127 llvm_unreachable("Unexpected vector type");
5129 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5132 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5133 /// that point to V2 points to its first element.
5134 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5135 for (unsigned i = 0; i != NumElems; ++i) {
5136 if (Mask[i] > (int)NumElems) {
5142 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5143 /// operation of specified width.
5144 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5146 unsigned NumElems = VT.getVectorNumElements();
5147 SmallVector<int, 8> Mask;
5148 Mask.push_back(NumElems);
5149 for (unsigned i = 1; i != NumElems; ++i)
5151 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5154 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5155 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5157 unsigned NumElems = VT.getVectorNumElements();
5158 SmallVector<int, 8> Mask;
5159 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5161 Mask.push_back(i + NumElems);
5163 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5166 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5167 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5169 unsigned NumElems = VT.getVectorNumElements();
5170 SmallVector<int, 8> Mask;
5171 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5172 Mask.push_back(i + Half);
5173 Mask.push_back(i + NumElems + Half);
5175 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5178 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5179 // a generic shuffle instruction because the target has no such instructions.
5180 // Generate shuffles which repeat i16 and i8 several times until they can be
5181 // represented by v4f32 and then be manipulated by target suported shuffles.
5182 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5183 MVT VT = V.getSimpleValueType();
5184 int NumElems = VT.getVectorNumElements();
5187 while (NumElems > 4) {
5188 if (EltNo < NumElems/2) {
5189 V = getUnpackl(DAG, dl, VT, V, V);
5191 V = getUnpackh(DAG, dl, VT, V, V);
5192 EltNo -= NumElems/2;
5199 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5200 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5201 MVT VT = V.getSimpleValueType();
5204 if (VT.is128BitVector()) {
5205 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5206 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5207 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5209 } else if (VT.is256BitVector()) {
5210 // To use VPERMILPS to splat scalars, the second half of indicies must
5211 // refer to the higher part, which is a duplication of the lower one,
5212 // because VPERMILPS can only handle in-lane permutations.
5213 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5214 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5216 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5217 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5220 llvm_unreachable("Vector size not supported");
5222 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5225 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5226 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5227 MVT SrcVT = SV->getSimpleValueType(0);
5228 SDValue V1 = SV->getOperand(0);
5231 int EltNo = SV->getSplatIndex();
5232 int NumElems = SrcVT.getVectorNumElements();
5233 bool Is256BitVec = SrcVT.is256BitVector();
5235 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5236 "Unknown how to promote splat for type");
5238 // Extract the 128-bit part containing the splat element and update
5239 // the splat element index when it refers to the higher register.
5241 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5242 if (EltNo >= NumElems/2)
5243 EltNo -= NumElems/2;
5246 // All i16 and i8 vector types can't be used directly by a generic shuffle
5247 // instruction because the target has no such instruction. Generate shuffles
5248 // which repeat i16 and i8 several times until they fit in i32, and then can
5249 // be manipulated by target suported shuffles.
5250 MVT EltVT = SrcVT.getVectorElementType();
5251 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5252 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5254 // Recreate the 256-bit vector and place the same 128-bit vector
5255 // into the low and high part. This is necessary because we want
5256 // to use VPERM* to shuffle the vectors
5258 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5261 return getLegalSplat(DAG, V1, EltNo);
5264 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5265 /// vector of zero or undef vector. This produces a shuffle where the low
5266 /// element of V2 is swizzled into the zero/undef vector, landing at element
5267 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5268 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5270 const X86Subtarget *Subtarget,
5271 SelectionDAG &DAG) {
5272 MVT VT = V2.getSimpleValueType();
5274 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5275 unsigned NumElems = VT.getVectorNumElements();
5276 SmallVector<int, 16> MaskVec;
5277 for (unsigned i = 0; i != NumElems; ++i)
5278 // If this is the insertion idx, put the low elt of V2 here.
5279 MaskVec.push_back(i == Idx ? NumElems : i);
5280 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5283 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5284 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5285 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5286 /// shuffles which use a single input multiple times, and in those cases it will
5287 /// adjust the mask to only have indices within that single input.
5288 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5289 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5290 unsigned NumElems = VT.getVectorNumElements();
5294 bool IsFakeUnary = false;
5295 switch(N->getOpcode()) {
5296 case X86ISD::BLENDI:
5297 ImmN = N->getOperand(N->getNumOperands()-1);
5298 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5301 ImmN = N->getOperand(N->getNumOperands()-1);
5302 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5303 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5305 case X86ISD::UNPCKH:
5306 DecodeUNPCKHMask(VT, Mask);
5307 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5309 case X86ISD::UNPCKL:
5310 DecodeUNPCKLMask(VT, Mask);
5311 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5313 case X86ISD::MOVHLPS:
5314 DecodeMOVHLPSMask(NumElems, Mask);
5315 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5317 case X86ISD::MOVLHPS:
5318 DecodeMOVLHPSMask(NumElems, Mask);
5319 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5321 case X86ISD::PALIGNR:
5322 ImmN = N->getOperand(N->getNumOperands()-1);
5323 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5325 case X86ISD::PSHUFD:
5326 case X86ISD::VPERMILPI:
5327 ImmN = N->getOperand(N->getNumOperands()-1);
5328 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5331 case X86ISD::PSHUFHW:
5332 ImmN = N->getOperand(N->getNumOperands()-1);
5333 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5336 case X86ISD::PSHUFLW:
5337 ImmN = N->getOperand(N->getNumOperands()-1);
5338 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5341 case X86ISD::PSHUFB: {
5343 SDValue MaskNode = N->getOperand(1);
5344 while (MaskNode->getOpcode() == ISD::BITCAST)
5345 MaskNode = MaskNode->getOperand(0);
5347 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5348 // If we have a build-vector, then things are easy.
5349 EVT VT = MaskNode.getValueType();
5350 assert(VT.isVector() &&
5351 "Can't produce a non-vector with a build_vector!");
5352 if (!VT.isInteger())
5355 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5357 SmallVector<uint64_t, 32> RawMask;
5358 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5359 SDValue Op = MaskNode->getOperand(i);
5360 if (Op->getOpcode() == ISD::UNDEF) {
5361 RawMask.push_back((uint64_t)SM_SentinelUndef);
5364 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5367 APInt MaskElement = CN->getAPIntValue();
5369 // We now have to decode the element which could be any integer size and
5370 // extract each byte of it.
5371 for (int j = 0; j < NumBytesPerElement; ++j) {
5372 // Note that this is x86 and so always little endian: the low byte is
5373 // the first byte of the mask.
5374 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5375 MaskElement = MaskElement.lshr(8);
5378 DecodePSHUFBMask(RawMask, Mask);
5382 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5386 SDValue Ptr = MaskLoad->getBasePtr();
5387 if (Ptr->getOpcode() == X86ISD::Wrapper)
5388 Ptr = Ptr->getOperand(0);
5390 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5391 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5394 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5395 // FIXME: Support AVX-512 here.
5396 Type *Ty = C->getType();
5397 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5398 Ty->getVectorNumElements() != 32))
5401 DecodePSHUFBMask(C, Mask);
5407 case X86ISD::VPERMI:
5408 ImmN = N->getOperand(N->getNumOperands()-1);
5409 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5413 case X86ISD::MOVSD: {
5414 // The index 0 always comes from the first element of the second source,
5415 // this is why MOVSS and MOVSD are used in the first place. The other
5416 // elements come from the other positions of the first source vector
5417 Mask.push_back(NumElems);
5418 for (unsigned i = 1; i != NumElems; ++i) {
5423 case X86ISD::VPERM2X128:
5424 ImmN = N->getOperand(N->getNumOperands()-1);
5425 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5426 if (Mask.empty()) return false;
5428 case X86ISD::MOVSLDUP:
5429 DecodeMOVSLDUPMask(VT, Mask);
5431 case X86ISD::MOVSHDUP:
5432 DecodeMOVSHDUPMask(VT, Mask);
5434 case X86ISD::MOVDDUP:
5435 case X86ISD::MOVLHPD:
5436 case X86ISD::MOVLPD:
5437 case X86ISD::MOVLPS:
5438 // Not yet implemented
5440 default: llvm_unreachable("unknown target shuffle node");
5443 // If we have a fake unary shuffle, the shuffle mask is spread across two
5444 // inputs that are actually the same node. Re-map the mask to always point
5445 // into the first input.
5448 if (M >= (int)Mask.size())
5454 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5455 /// element of the result of the vector shuffle.
5456 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5459 return SDValue(); // Limit search depth.
5461 SDValue V = SDValue(N, 0);
5462 EVT VT = V.getValueType();
5463 unsigned Opcode = V.getOpcode();
5465 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5466 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5467 int Elt = SV->getMaskElt(Index);
5470 return DAG.getUNDEF(VT.getVectorElementType());
5472 unsigned NumElems = VT.getVectorNumElements();
5473 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5474 : SV->getOperand(1);
5475 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5478 // Recurse into target specific vector shuffles to find scalars.
5479 if (isTargetShuffle(Opcode)) {
5480 MVT ShufVT = V.getSimpleValueType();
5481 unsigned NumElems = ShufVT.getVectorNumElements();
5482 SmallVector<int, 16> ShuffleMask;
5485 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5488 int Elt = ShuffleMask[Index];
5490 return DAG.getUNDEF(ShufVT.getVectorElementType());
5492 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5494 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5498 // Actual nodes that may contain scalar elements
5499 if (Opcode == ISD::BITCAST) {
5500 V = V.getOperand(0);
5501 EVT SrcVT = V.getValueType();
5502 unsigned NumElems = VT.getVectorNumElements();
5504 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5508 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5509 return (Index == 0) ? V.getOperand(0)
5510 : DAG.getUNDEF(VT.getVectorElementType());
5512 if (V.getOpcode() == ISD::BUILD_VECTOR)
5513 return V.getOperand(Index);
5518 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5519 /// shuffle operation which come from a consecutively from a zero. The
5520 /// search can start in two different directions, from left or right.
5521 /// We count undefs as zeros until PreferredNum is reached.
5522 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5523 unsigned NumElems, bool ZerosFromLeft,
5525 unsigned PreferredNum = -1U) {
5526 unsigned NumZeros = 0;
5527 for (unsigned i = 0; i != NumElems; ++i) {
5528 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5529 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5533 if (X86::isZeroNode(Elt))
5535 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5536 NumZeros = std::min(NumZeros + 1, PreferredNum);
5544 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5545 /// correspond consecutively to elements from one of the vector operands,
5546 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5548 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5549 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5550 unsigned NumElems, unsigned &OpNum) {
5551 bool SeenV1 = false;
5552 bool SeenV2 = false;
5554 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5555 int Idx = SVOp->getMaskElt(i);
5556 // Ignore undef indicies
5560 if (Idx < (int)NumElems)
5565 // Only accept consecutive elements from the same vector
5566 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5570 OpNum = SeenV1 ? 0 : 1;
5574 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5575 /// logical left shift of a vector.
5576 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5577 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5579 SVOp->getSimpleValueType(0).getVectorNumElements();
5580 unsigned NumZeros = getNumOfConsecutiveZeros(
5581 SVOp, NumElems, false /* check zeros from right */, DAG,
5582 SVOp->getMaskElt(0));
5588 // Considering the elements in the mask that are not consecutive zeros,
5589 // check if they consecutively come from only one of the source vectors.
5591 // V1 = {X, A, B, C} 0
5593 // vector_shuffle V1, V2 <1, 2, 3, X>
5595 if (!isShuffleMaskConsecutive(SVOp,
5596 0, // Mask Start Index
5597 NumElems-NumZeros, // Mask End Index(exclusive)
5598 NumZeros, // Where to start looking in the src vector
5599 NumElems, // Number of elements in vector
5600 OpSrc)) // Which source operand ?
5605 ShVal = SVOp->getOperand(OpSrc);
5609 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5610 /// logical left shift of a vector.
5611 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5612 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5614 SVOp->getSimpleValueType(0).getVectorNumElements();
5615 unsigned NumZeros = getNumOfConsecutiveZeros(
5616 SVOp, NumElems, true /* check zeros from left */, DAG,
5617 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5623 // Considering the elements in the mask that are not consecutive zeros,
5624 // check if they consecutively come from only one of the source vectors.
5626 // 0 { A, B, X, X } = V2
5628 // vector_shuffle V1, V2 <X, X, 4, 5>
5630 if (!isShuffleMaskConsecutive(SVOp,
5631 NumZeros, // Mask Start Index
5632 NumElems, // Mask End Index(exclusive)
5633 0, // Where to start looking in the src vector
5634 NumElems, // Number of elements in vector
5635 OpSrc)) // Which source operand ?
5640 ShVal = SVOp->getOperand(OpSrc);
5644 /// isVectorShift - Returns true if the shuffle can be implemented as a
5645 /// logical left or right shift of a vector.
5646 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5647 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5648 // Although the logic below support any bitwidth size, there are no
5649 // shift instructions which handle more than 128-bit vectors.
5650 if (!SVOp->getSimpleValueType(0).is128BitVector())
5653 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5654 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5660 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5662 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5663 unsigned NumNonZero, unsigned NumZero,
5665 const X86Subtarget* Subtarget,
5666 const TargetLowering &TLI) {
5673 for (unsigned i = 0; i < 16; ++i) {
5674 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5675 if (ThisIsNonZero && First) {
5677 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5679 V = DAG.getUNDEF(MVT::v8i16);
5684 SDValue ThisElt, LastElt;
5685 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5686 if (LastIsNonZero) {
5687 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5688 MVT::i16, Op.getOperand(i-1));
5690 if (ThisIsNonZero) {
5691 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5692 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5693 ThisElt, DAG.getConstant(8, MVT::i8));
5695 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5699 if (ThisElt.getNode())
5700 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5701 DAG.getIntPtrConstant(i/2));
5705 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5708 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5710 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5711 unsigned NumNonZero, unsigned NumZero,
5713 const X86Subtarget* Subtarget,
5714 const TargetLowering &TLI) {
5721 for (unsigned i = 0; i < 8; ++i) {
5722 bool isNonZero = (NonZeros & (1 << i)) != 0;
5726 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5728 V = DAG.getUNDEF(MVT::v8i16);
5731 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5732 MVT::v8i16, V, Op.getOperand(i),
5733 DAG.getIntPtrConstant(i));
5740 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5741 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5742 const X86Subtarget *Subtarget,
5743 const TargetLowering &TLI) {
5744 // Find all zeroable elements.
5746 for (int i=0; i < 4; ++i) {
5747 SDValue Elt = Op->getOperand(i);
5748 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5750 assert(std::count_if(&Zeroable[0], &Zeroable[4],
5751 [](bool M) { return !M; }) > 1 &&
5752 "We expect at least two non-zero elements!");
5754 // We only know how to deal with build_vector nodes where elements are either
5755 // zeroable or extract_vector_elt with constant index.
5756 SDValue FirstNonZero;
5757 unsigned FirstNonZeroIdx;
5758 for (unsigned i=0; i < 4; ++i) {
5761 SDValue Elt = Op->getOperand(i);
5762 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5763 !isa<ConstantSDNode>(Elt.getOperand(1)))
5765 // Make sure that this node is extracting from a 128-bit vector.
5766 MVT VT = Elt.getOperand(0).getSimpleValueType();
5767 if (!VT.is128BitVector())
5769 if (!FirstNonZero.getNode()) {
5771 FirstNonZeroIdx = i;
5775 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5776 SDValue V1 = FirstNonZero.getOperand(0);
5777 MVT VT = V1.getSimpleValueType();
5779 // See if this build_vector can be lowered as a blend with zero.
5781 unsigned EltMaskIdx, EltIdx;
5783 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5784 if (Zeroable[EltIdx]) {
5785 // The zero vector will be on the right hand side.
5786 Mask[EltIdx] = EltIdx+4;
5790 Elt = Op->getOperand(EltIdx);
5791 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5792 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5793 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5795 Mask[EltIdx] = EltIdx;
5799 // Let the shuffle legalizer deal with blend operations.
5800 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5801 if (V1.getSimpleValueType() != VT)
5802 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5803 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5806 // See if we can lower this build_vector to a INSERTPS.
5807 if (!Subtarget->hasSSE41())
5810 SDValue V2 = Elt.getOperand(0);
5811 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5814 bool CanFold = true;
5815 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5819 SDValue Current = Op->getOperand(i);
5820 SDValue SrcVector = Current->getOperand(0);
5823 CanFold = SrcVector == V1 &&
5824 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5830 assert(V1.getNode() && "Expected at least two non-zero elements!");
5831 if (V1.getSimpleValueType() != MVT::v4f32)
5832 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5833 if (V2.getSimpleValueType() != MVT::v4f32)
5834 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5836 // Ok, we can emit an INSERTPS instruction.
5838 for (int i = 0; i < 4; ++i)
5842 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5843 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5844 SDValue Result = DAG.getNode(X86ISD::INSERTPS, SDLoc(Op), MVT::v4f32, V1, V2,
5845 DAG.getIntPtrConstant(InsertPSMask));
5846 return DAG.getNode(ISD::BITCAST, SDLoc(Op), VT, Result);
5849 /// getVShift - Return a vector logical shift node.
5851 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5852 unsigned NumBits, SelectionDAG &DAG,
5853 const TargetLowering &TLI, SDLoc dl) {
5854 assert(VT.is128BitVector() && "Unknown type for VShift");
5855 EVT ShVT = MVT::v2i64;
5856 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5857 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5858 return DAG.getNode(ISD::BITCAST, dl, VT,
5859 DAG.getNode(Opc, dl, ShVT, SrcOp,
5860 DAG.getConstant(NumBits,
5861 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5865 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5867 // Check if the scalar load can be widened into a vector load. And if
5868 // the address is "base + cst" see if the cst can be "absorbed" into
5869 // the shuffle mask.
5870 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5871 SDValue Ptr = LD->getBasePtr();
5872 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5874 EVT PVT = LD->getValueType(0);
5875 if (PVT != MVT::i32 && PVT != MVT::f32)
5880 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5881 FI = FINode->getIndex();
5883 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5884 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5885 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5886 Offset = Ptr.getConstantOperandVal(1);
5887 Ptr = Ptr.getOperand(0);
5892 // FIXME: 256-bit vector instructions don't require a strict alignment,
5893 // improve this code to support it better.
5894 unsigned RequiredAlign = VT.getSizeInBits()/8;
5895 SDValue Chain = LD->getChain();
5896 // Make sure the stack object alignment is at least 16 or 32.
5897 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5898 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5899 if (MFI->isFixedObjectIndex(FI)) {
5900 // Can't change the alignment. FIXME: It's possible to compute
5901 // the exact stack offset and reference FI + adjust offset instead.
5902 // If someone *really* cares about this. That's the way to implement it.
5905 MFI->setObjectAlignment(FI, RequiredAlign);
5909 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5910 // Ptr + (Offset & ~15).
5913 if ((Offset % RequiredAlign) & 3)
5915 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5917 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5918 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5920 int EltNo = (Offset - StartOffset) >> 2;
5921 unsigned NumElems = VT.getVectorNumElements();
5923 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5924 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5925 LD->getPointerInfo().getWithOffset(StartOffset),
5926 false, false, false, 0);
5928 SmallVector<int, 8> Mask;
5929 for (unsigned i = 0; i != NumElems; ++i)
5930 Mask.push_back(EltNo);
5932 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5938 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5939 /// vector of type 'VT', see if the elements can be replaced by a single large
5940 /// load which has the same value as a build_vector whose operands are 'elts'.
5942 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5944 /// FIXME: we'd also like to handle the case where the last elements are zero
5945 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5946 /// There's even a handy isZeroNode for that purpose.
5947 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5948 SDLoc &DL, SelectionDAG &DAG,
5949 bool isAfterLegalize) {
5950 EVT EltVT = VT.getVectorElementType();
5951 unsigned NumElems = Elts.size();
5953 LoadSDNode *LDBase = nullptr;
5954 unsigned LastLoadedElt = -1U;
5956 // For each element in the initializer, see if we've found a load or an undef.
5957 // If we don't find an initial load element, or later load elements are
5958 // non-consecutive, bail out.
5959 for (unsigned i = 0; i < NumElems; ++i) {
5960 SDValue Elt = Elts[i];
5962 if (!Elt.getNode() ||
5963 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5966 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5968 LDBase = cast<LoadSDNode>(Elt.getNode());
5972 if (Elt.getOpcode() == ISD::UNDEF)
5975 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5976 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5981 // If we have found an entire vector of loads and undefs, then return a large
5982 // load of the entire vector width starting at the base pointer. If we found
5983 // consecutive loads for the low half, generate a vzext_load node.
5984 if (LastLoadedElt == NumElems - 1) {
5986 if (isAfterLegalize &&
5987 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5990 SDValue NewLd = SDValue();
5992 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5993 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5994 LDBase->getPointerInfo(),
5995 LDBase->isVolatile(), LDBase->isNonTemporal(),
5996 LDBase->isInvariant(), 0);
5997 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5998 LDBase->getPointerInfo(),
5999 LDBase->isVolatile(), LDBase->isNonTemporal(),
6000 LDBase->isInvariant(), LDBase->getAlignment());
6002 if (LDBase->hasAnyUseOfValue(1)) {
6003 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6005 SDValue(NewLd.getNode(), 1));
6006 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6007 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6008 SDValue(NewLd.getNode(), 1));
6013 if (NumElems == 4 && LastLoadedElt == 1 &&
6014 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
6015 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
6016 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
6018 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
6019 LDBase->getPointerInfo(),
6020 LDBase->getAlignment(),
6021 false/*isVolatile*/, true/*ReadMem*/,
6024 // Make sure the newly-created LOAD is in the same position as LDBase in
6025 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
6026 // update uses of LDBase's output chain to use the TokenFactor.
6027 if (LDBase->hasAnyUseOfValue(1)) {
6028 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6029 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
6030 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6031 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6032 SDValue(ResNode.getNode(), 1));
6035 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6040 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6041 /// to generate a splat value for the following cases:
6042 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6043 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6044 /// a scalar load, or a constant.
6045 /// The VBROADCAST node is returned when a pattern is found,
6046 /// or SDValue() otherwise.
6047 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6048 SelectionDAG &DAG) {
6049 // VBROADCAST requires AVX.
6050 // TODO: Splats could be generated for non-AVX CPUs using SSE
6051 // instructions, but there's less potential gain for only 128-bit vectors.
6052 if (!Subtarget->hasAVX())
6055 MVT VT = Op.getSimpleValueType();
6058 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6059 "Unsupported vector type for broadcast.");
6064 switch (Op.getOpcode()) {
6066 // Unknown pattern found.
6069 case ISD::BUILD_VECTOR: {
6070 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6071 BitVector UndefElements;
6072 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6074 // We need a splat of a single value to use broadcast, and it doesn't
6075 // make any sense if the value is only in one element of the vector.
6076 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6080 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6081 Ld.getOpcode() == ISD::ConstantFP);
6083 // Make sure that all of the users of a non-constant load are from the
6084 // BUILD_VECTOR node.
6085 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6090 case ISD::VECTOR_SHUFFLE: {
6091 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6093 // Shuffles must have a splat mask where the first element is
6095 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6098 SDValue Sc = Op.getOperand(0);
6099 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6100 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6102 if (!Subtarget->hasInt256())
6105 // Use the register form of the broadcast instruction available on AVX2.
6106 if (VT.getSizeInBits() >= 256)
6107 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6108 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6111 Ld = Sc.getOperand(0);
6112 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6113 Ld.getOpcode() == ISD::ConstantFP);
6115 // The scalar_to_vector node and the suspected
6116 // load node must have exactly one user.
6117 // Constants may have multiple users.
6119 // AVX-512 has register version of the broadcast
6120 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6121 Ld.getValueType().getSizeInBits() >= 32;
6122 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6129 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6130 bool IsGE256 = (VT.getSizeInBits() >= 256);
6132 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6133 // instruction to save 8 or more bytes of constant pool data.
6134 // TODO: If multiple splats are generated to load the same constant,
6135 // it may be detrimental to overall size. There needs to be a way to detect
6136 // that condition to know if this is truly a size win.
6137 const Function *F = DAG.getMachineFunction().getFunction();
6138 bool OptForSize = F->getAttributes().
6139 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6141 // Handle broadcasting a single constant scalar from the constant pool
6143 // On Sandybridge (no AVX2), it is still better to load a constant vector
6144 // from the constant pool and not to broadcast it from a scalar.
6145 // But override that restriction when optimizing for size.
6146 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6147 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6148 EVT CVT = Ld.getValueType();
6149 assert(!CVT.isVector() && "Must not broadcast a vector type");
6151 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6152 // For size optimization, also splat v2f64 and v2i64, and for size opt
6153 // with AVX2, also splat i8 and i16.
6154 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6155 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6156 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6157 const Constant *C = nullptr;
6158 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6159 C = CI->getConstantIntValue();
6160 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6161 C = CF->getConstantFPValue();
6163 assert(C && "Invalid constant type");
6165 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6166 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6167 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6168 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6169 MachinePointerInfo::getConstantPool(),
6170 false, false, false, Alignment);
6172 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6176 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6178 // Handle AVX2 in-register broadcasts.
6179 if (!IsLoad && Subtarget->hasInt256() &&
6180 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6181 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6183 // The scalar source must be a normal load.
6187 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6188 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6190 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6191 // double since there is no vbroadcastsd xmm
6192 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6193 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6194 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6197 // Unsupported broadcast.
6201 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6202 /// underlying vector and index.
6204 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6206 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6208 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6209 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6212 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6214 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6216 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6217 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6220 // In this case the vector is the extract_subvector expression and the index
6221 // is 2, as specified by the shuffle.
6222 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6223 SDValue ShuffleVec = SVOp->getOperand(0);
6224 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6225 assert(ShuffleVecVT.getVectorElementType() ==
6226 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6228 int ShuffleIdx = SVOp->getMaskElt(Idx);
6229 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6230 ExtractedFromVec = ShuffleVec;
6236 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6237 MVT VT = Op.getSimpleValueType();
6239 // Skip if insert_vec_elt is not supported.
6240 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6241 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6245 unsigned NumElems = Op.getNumOperands();
6249 SmallVector<unsigned, 4> InsertIndices;
6250 SmallVector<int, 8> Mask(NumElems, -1);
6252 for (unsigned i = 0; i != NumElems; ++i) {
6253 unsigned Opc = Op.getOperand(i).getOpcode();
6255 if (Opc == ISD::UNDEF)
6258 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6259 // Quit if more than 1 elements need inserting.
6260 if (InsertIndices.size() > 1)
6263 InsertIndices.push_back(i);
6267 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6268 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6269 // Quit if non-constant index.
6270 if (!isa<ConstantSDNode>(ExtIdx))
6272 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6274 // Quit if extracted from vector of different type.
6275 if (ExtractedFromVec.getValueType() != VT)
6278 if (!VecIn1.getNode())
6279 VecIn1 = ExtractedFromVec;
6280 else if (VecIn1 != ExtractedFromVec) {
6281 if (!VecIn2.getNode())
6282 VecIn2 = ExtractedFromVec;
6283 else if (VecIn2 != ExtractedFromVec)
6284 // Quit if more than 2 vectors to shuffle
6288 if (ExtractedFromVec == VecIn1)
6290 else if (ExtractedFromVec == VecIn2)
6291 Mask[i] = Idx + NumElems;
6294 if (!VecIn1.getNode())
6297 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6298 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6299 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6300 unsigned Idx = InsertIndices[i];
6301 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6302 DAG.getIntPtrConstant(Idx));
6308 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6310 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6312 MVT VT = Op.getSimpleValueType();
6313 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6314 "Unexpected type in LowerBUILD_VECTORvXi1!");
6317 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6318 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6319 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6320 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6323 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6324 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6325 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6326 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6329 bool AllContants = true;
6330 uint64_t Immediate = 0;
6331 int NonConstIdx = -1;
6332 bool IsSplat = true;
6333 unsigned NumNonConsts = 0;
6334 unsigned NumConsts = 0;
6335 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6336 SDValue In = Op.getOperand(idx);
6337 if (In.getOpcode() == ISD::UNDEF)
6339 if (!isa<ConstantSDNode>(In)) {
6340 AllContants = false;
6346 if (cast<ConstantSDNode>(In)->getZExtValue())
6347 Immediate |= (1ULL << idx);
6349 if (In != Op.getOperand(0))
6354 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6355 DAG.getConstant(Immediate, MVT::i16));
6356 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6357 DAG.getIntPtrConstant(0));
6360 if (NumNonConsts == 1 && NonConstIdx != 0) {
6363 SDValue VecAsImm = DAG.getConstant(Immediate,
6364 MVT::getIntegerVT(VT.getSizeInBits()));
6365 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6368 DstVec = DAG.getUNDEF(VT);
6369 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6370 Op.getOperand(NonConstIdx),
6371 DAG.getIntPtrConstant(NonConstIdx));
6373 if (!IsSplat && (NonConstIdx != 0))
6374 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6375 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6378 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6379 DAG.getConstant(-1, SelectVT),
6380 DAG.getConstant(0, SelectVT));
6382 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6383 DAG.getConstant((Immediate | 1), SelectVT),
6384 DAG.getConstant(Immediate, SelectVT));
6385 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6388 /// \brief Return true if \p N implements a horizontal binop and return the
6389 /// operands for the horizontal binop into V0 and V1.
6391 /// This is a helper function of PerformBUILD_VECTORCombine.
6392 /// This function checks that the build_vector \p N in input implements a
6393 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6394 /// operation to match.
6395 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6396 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6397 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6400 /// This function only analyzes elements of \p N whose indices are
6401 /// in range [BaseIdx, LastIdx).
6402 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6404 unsigned BaseIdx, unsigned LastIdx,
6405 SDValue &V0, SDValue &V1) {
6406 EVT VT = N->getValueType(0);
6408 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6409 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6410 "Invalid Vector in input!");
6412 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6413 bool CanFold = true;
6414 unsigned ExpectedVExtractIdx = BaseIdx;
6415 unsigned NumElts = LastIdx - BaseIdx;
6416 V0 = DAG.getUNDEF(VT);
6417 V1 = DAG.getUNDEF(VT);
6419 // Check if N implements a horizontal binop.
6420 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6421 SDValue Op = N->getOperand(i + BaseIdx);
6424 if (Op->getOpcode() == ISD::UNDEF) {
6425 // Update the expected vector extract index.
6426 if (i * 2 == NumElts)
6427 ExpectedVExtractIdx = BaseIdx;
6428 ExpectedVExtractIdx += 2;
6432 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6437 SDValue Op0 = Op.getOperand(0);
6438 SDValue Op1 = Op.getOperand(1);
6440 // Try to match the following pattern:
6441 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6442 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6443 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6444 Op0.getOperand(0) == Op1.getOperand(0) &&
6445 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6446 isa<ConstantSDNode>(Op1.getOperand(1)));
6450 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6451 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6453 if (i * 2 < NumElts) {
6454 if (V0.getOpcode() == ISD::UNDEF)
6455 V0 = Op0.getOperand(0);
6457 if (V1.getOpcode() == ISD::UNDEF)
6458 V1 = Op0.getOperand(0);
6459 if (i * 2 == NumElts)
6460 ExpectedVExtractIdx = BaseIdx;
6463 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6464 if (I0 == ExpectedVExtractIdx)
6465 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6466 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6467 // Try to match the following dag sequence:
6468 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6469 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6473 ExpectedVExtractIdx += 2;
6479 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6480 /// a concat_vector.
6482 /// This is a helper function of PerformBUILD_VECTORCombine.
6483 /// This function expects two 256-bit vectors called V0 and V1.
6484 /// At first, each vector is split into two separate 128-bit vectors.
6485 /// Then, the resulting 128-bit vectors are used to implement two
6486 /// horizontal binary operations.
6488 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6490 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6491 /// the two new horizontal binop.
6492 /// When Mode is set, the first horizontal binop dag node would take as input
6493 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6494 /// horizontal binop dag node would take as input the lower 128-bit of V1
6495 /// and the upper 128-bit of V1.
6497 /// HADD V0_LO, V0_HI
6498 /// HADD V1_LO, V1_HI
6500 /// Otherwise, the first horizontal binop dag node takes as input the lower
6501 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6502 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6504 /// HADD V0_LO, V1_LO
6505 /// HADD V0_HI, V1_HI
6507 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6508 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6509 /// the upper 128-bits of the result.
6510 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6511 SDLoc DL, SelectionDAG &DAG,
6512 unsigned X86Opcode, bool Mode,
6513 bool isUndefLO, bool isUndefHI) {
6514 EVT VT = V0.getValueType();
6515 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6516 "Invalid nodes in input!");
6518 unsigned NumElts = VT.getVectorNumElements();
6519 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6520 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6521 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6522 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6523 EVT NewVT = V0_LO.getValueType();
6525 SDValue LO = DAG.getUNDEF(NewVT);
6526 SDValue HI = DAG.getUNDEF(NewVT);
6529 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6530 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6531 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6532 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6533 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6535 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6536 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6537 V1_LO->getOpcode() != ISD::UNDEF))
6538 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6540 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6541 V1_HI->getOpcode() != ISD::UNDEF))
6542 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6545 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6548 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6549 /// sequence of 'vadd + vsub + blendi'.
6550 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6551 const X86Subtarget *Subtarget) {
6553 EVT VT = BV->getValueType(0);
6554 unsigned NumElts = VT.getVectorNumElements();
6555 SDValue InVec0 = DAG.getUNDEF(VT);
6556 SDValue InVec1 = DAG.getUNDEF(VT);
6558 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6559 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6561 // Odd-numbered elements in the input build vector are obtained from
6562 // adding two integer/float elements.
6563 // Even-numbered elements in the input build vector are obtained from
6564 // subtracting two integer/float elements.
6565 unsigned ExpectedOpcode = ISD::FSUB;
6566 unsigned NextExpectedOpcode = ISD::FADD;
6567 bool AddFound = false;
6568 bool SubFound = false;
6570 for (unsigned i = 0, e = NumElts; i != e; i++) {
6571 SDValue Op = BV->getOperand(i);
6573 // Skip 'undef' values.
6574 unsigned Opcode = Op.getOpcode();
6575 if (Opcode == ISD::UNDEF) {
6576 std::swap(ExpectedOpcode, NextExpectedOpcode);
6580 // Early exit if we found an unexpected opcode.
6581 if (Opcode != ExpectedOpcode)
6584 SDValue Op0 = Op.getOperand(0);
6585 SDValue Op1 = Op.getOperand(1);
6587 // Try to match the following pattern:
6588 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6589 // Early exit if we cannot match that sequence.
6590 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6591 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6592 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6593 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6594 Op0.getOperand(1) != Op1.getOperand(1))
6597 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6601 // We found a valid add/sub node. Update the information accordingly.
6607 // Update InVec0 and InVec1.
6608 if (InVec0.getOpcode() == ISD::UNDEF)
6609 InVec0 = Op0.getOperand(0);
6610 if (InVec1.getOpcode() == ISD::UNDEF)
6611 InVec1 = Op1.getOperand(0);
6613 // Make sure that operands in input to each add/sub node always
6614 // come from a same pair of vectors.
6615 if (InVec0 != Op0.getOperand(0)) {
6616 if (ExpectedOpcode == ISD::FSUB)
6619 // FADD is commutable. Try to commute the operands
6620 // and then test again.
6621 std::swap(Op0, Op1);
6622 if (InVec0 != Op0.getOperand(0))
6626 if (InVec1 != Op1.getOperand(0))
6629 // Update the pair of expected opcodes.
6630 std::swap(ExpectedOpcode, NextExpectedOpcode);
6633 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6634 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6635 InVec1.getOpcode() != ISD::UNDEF)
6636 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6641 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6642 const X86Subtarget *Subtarget) {
6644 EVT VT = N->getValueType(0);
6645 unsigned NumElts = VT.getVectorNumElements();
6646 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6647 SDValue InVec0, InVec1;
6649 // Try to match an ADDSUB.
6650 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6651 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6652 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6653 if (Value.getNode())
6657 // Try to match horizontal ADD/SUB.
6658 unsigned NumUndefsLO = 0;
6659 unsigned NumUndefsHI = 0;
6660 unsigned Half = NumElts/2;
6662 // Count the number of UNDEF operands in the build_vector in input.
6663 for (unsigned i = 0, e = Half; i != e; ++i)
6664 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6667 for (unsigned i = Half, e = NumElts; i != e; ++i)
6668 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6671 // Early exit if this is either a build_vector of all UNDEFs or all the
6672 // operands but one are UNDEF.
6673 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6676 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6677 // Try to match an SSE3 float HADD/HSUB.
6678 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6679 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6681 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6682 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6683 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6684 // Try to match an SSSE3 integer HADD/HSUB.
6685 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6686 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6688 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6689 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6692 if (!Subtarget->hasAVX())
6695 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6696 // Try to match an AVX horizontal add/sub of packed single/double
6697 // precision floating point values from 256-bit vectors.
6698 SDValue InVec2, InVec3;
6699 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6700 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6701 ((InVec0.getOpcode() == ISD::UNDEF ||
6702 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6703 ((InVec1.getOpcode() == ISD::UNDEF ||
6704 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6705 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6707 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6708 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6709 ((InVec0.getOpcode() == ISD::UNDEF ||
6710 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6711 ((InVec1.getOpcode() == ISD::UNDEF ||
6712 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6713 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6714 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6715 // Try to match an AVX2 horizontal add/sub of signed integers.
6716 SDValue InVec2, InVec3;
6718 bool CanFold = true;
6720 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6721 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6722 ((InVec0.getOpcode() == ISD::UNDEF ||
6723 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6724 ((InVec1.getOpcode() == ISD::UNDEF ||
6725 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6726 X86Opcode = X86ISD::HADD;
6727 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6728 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6729 ((InVec0.getOpcode() == ISD::UNDEF ||
6730 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6731 ((InVec1.getOpcode() == ISD::UNDEF ||
6732 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6733 X86Opcode = X86ISD::HSUB;
6738 // Fold this build_vector into a single horizontal add/sub.
6739 // Do this only if the target has AVX2.
6740 if (Subtarget->hasAVX2())
6741 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6743 // Do not try to expand this build_vector into a pair of horizontal
6744 // add/sub if we can emit a pair of scalar add/sub.
6745 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6748 // Convert this build_vector into a pair of horizontal binop followed by
6750 bool isUndefLO = NumUndefsLO == Half;
6751 bool isUndefHI = NumUndefsHI == Half;
6752 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6753 isUndefLO, isUndefHI);
6757 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6758 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6760 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6761 X86Opcode = X86ISD::HADD;
6762 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6763 X86Opcode = X86ISD::HSUB;
6764 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6765 X86Opcode = X86ISD::FHADD;
6766 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6767 X86Opcode = X86ISD::FHSUB;
6771 // Don't try to expand this build_vector into a pair of horizontal add/sub
6772 // if we can simply emit a pair of scalar add/sub.
6773 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6776 // Convert this build_vector into two horizontal add/sub followed by
6778 bool isUndefLO = NumUndefsLO == Half;
6779 bool isUndefHI = NumUndefsHI == Half;
6780 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6781 isUndefLO, isUndefHI);
6788 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6791 MVT VT = Op.getSimpleValueType();
6792 MVT ExtVT = VT.getVectorElementType();
6793 unsigned NumElems = Op.getNumOperands();
6795 // Generate vectors for predicate vectors.
6796 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6797 return LowerBUILD_VECTORvXi1(Op, DAG);
6799 // Vectors containing all zeros can be matched by pxor and xorps later
6800 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6801 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6802 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6803 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6806 return getZeroVector(VT, Subtarget, DAG, dl);
6809 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6810 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6811 // vpcmpeqd on 256-bit vectors.
6812 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6813 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6816 if (!VT.is512BitVector())
6817 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6820 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6821 if (Broadcast.getNode())
6824 unsigned EVTBits = ExtVT.getSizeInBits();
6826 unsigned NumZero = 0;
6827 unsigned NumNonZero = 0;
6828 unsigned NonZeros = 0;
6829 bool IsAllConstants = true;
6830 SmallSet<SDValue, 8> Values;
6831 for (unsigned i = 0; i < NumElems; ++i) {
6832 SDValue Elt = Op.getOperand(i);
6833 if (Elt.getOpcode() == ISD::UNDEF)
6836 if (Elt.getOpcode() != ISD::Constant &&
6837 Elt.getOpcode() != ISD::ConstantFP)
6838 IsAllConstants = false;
6839 if (X86::isZeroNode(Elt))
6842 NonZeros |= (1 << i);
6847 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6848 if (NumNonZero == 0)
6849 return DAG.getUNDEF(VT);
6851 // Special case for single non-zero, non-undef, element.
6852 if (NumNonZero == 1) {
6853 unsigned Idx = countTrailingZeros(NonZeros);
6854 SDValue Item = Op.getOperand(Idx);
6856 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6857 // the value are obviously zero, truncate the value to i32 and do the
6858 // insertion that way. Only do this if the value is non-constant or if the
6859 // value is a constant being inserted into element 0. It is cheaper to do
6860 // a constant pool load than it is to do a movd + shuffle.
6861 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6862 (!IsAllConstants || Idx == 0)) {
6863 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6865 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6866 EVT VecVT = MVT::v4i32;
6867 unsigned VecElts = 4;
6869 // Truncate the value (which may itself be a constant) to i32, and
6870 // convert it to a vector with movd (S2V+shuffle to zero extend).
6871 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6872 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6874 // If using the new shuffle lowering, just directly insert this.
6875 if (ExperimentalVectorShuffleLowering)
6877 ISD::BITCAST, dl, VT,
6878 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6880 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6882 // Now we have our 32-bit value zero extended in the low element of
6883 // a vector. If Idx != 0, swizzle it into place.
6885 SmallVector<int, 4> Mask;
6886 Mask.push_back(Idx);
6887 for (unsigned i = 1; i != VecElts; ++i)
6889 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6892 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6896 // If we have a constant or non-constant insertion into the low element of
6897 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6898 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6899 // depending on what the source datatype is.
6902 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6904 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6905 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6906 if (VT.is256BitVector() || VT.is512BitVector()) {
6907 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6908 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6909 Item, DAG.getIntPtrConstant(0));
6911 assert(VT.is128BitVector() && "Expected an SSE value type!");
6912 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6913 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6914 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6917 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6918 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6919 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6920 if (VT.is256BitVector()) {
6921 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6922 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6924 assert(VT.is128BitVector() && "Expected an SSE value type!");
6925 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6927 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6931 // Is it a vector logical left shift?
6932 if (NumElems == 2 && Idx == 1 &&
6933 X86::isZeroNode(Op.getOperand(0)) &&
6934 !X86::isZeroNode(Op.getOperand(1))) {
6935 unsigned NumBits = VT.getSizeInBits();
6936 return getVShift(true, VT,
6937 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6938 VT, Op.getOperand(1)),
6939 NumBits/2, DAG, *this, dl);
6942 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6945 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6946 // is a non-constant being inserted into an element other than the low one,
6947 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6948 // movd/movss) to move this into the low element, then shuffle it into
6950 if (EVTBits == 32) {
6951 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6953 // If using the new shuffle lowering, just directly insert this.
6954 if (ExperimentalVectorShuffleLowering)
6955 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6957 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6958 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6959 SmallVector<int, 8> MaskVec;
6960 for (unsigned i = 0; i != NumElems; ++i)
6961 MaskVec.push_back(i == Idx ? 0 : 1);
6962 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6966 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6967 if (Values.size() == 1) {
6968 if (EVTBits == 32) {
6969 // Instead of a shuffle like this:
6970 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6971 // Check if it's possible to issue this instead.
6972 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6973 unsigned Idx = countTrailingZeros(NonZeros);
6974 SDValue Item = Op.getOperand(Idx);
6975 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6976 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6981 // A vector full of immediates; various special cases are already
6982 // handled, so this is best done with a single constant-pool load.
6986 // For AVX-length vectors, build the individual 128-bit pieces and use
6987 // shuffles to put them in place.
6988 if (VT.is256BitVector() || VT.is512BitVector()) {
6989 SmallVector<SDValue, 64> V;
6990 for (unsigned i = 0; i != NumElems; ++i)
6991 V.push_back(Op.getOperand(i));
6993 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6995 // Build both the lower and upper subvector.
6996 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6997 makeArrayRef(&V[0], NumElems/2));
6998 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6999 makeArrayRef(&V[NumElems / 2], NumElems/2));
7001 // Recreate the wider vector with the lower and upper part.
7002 if (VT.is256BitVector())
7003 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7004 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7007 // Let legalizer expand 2-wide build_vectors.
7008 if (EVTBits == 64) {
7009 if (NumNonZero == 1) {
7010 // One half is zero or undef.
7011 unsigned Idx = countTrailingZeros(NonZeros);
7012 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
7013 Op.getOperand(Idx));
7014 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
7019 // If element VT is < 32 bits, convert it to inserts into a zero vector.
7020 if (EVTBits == 8 && NumElems == 16) {
7021 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
7023 if (V.getNode()) return V;
7026 if (EVTBits == 16 && NumElems == 8) {
7027 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
7029 if (V.getNode()) return V;
7032 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
7033 if (EVTBits == 32 && NumElems == 4) {
7034 SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this);
7039 // If element VT is == 32 bits, turn it into a number of shuffles.
7040 SmallVector<SDValue, 8> V(NumElems);
7041 if (NumElems == 4 && NumZero > 0) {
7042 for (unsigned i = 0; i < 4; ++i) {
7043 bool isZero = !(NonZeros & (1 << i));
7045 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7047 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7050 for (unsigned i = 0; i < 2; ++i) {
7051 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7054 V[i] = V[i*2]; // Must be a zero vector.
7057 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7060 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7063 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7068 bool Reverse1 = (NonZeros & 0x3) == 2;
7069 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7073 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7074 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7076 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7079 if (Values.size() > 1 && VT.is128BitVector()) {
7080 // Check for a build vector of consecutive loads.
7081 for (unsigned i = 0; i < NumElems; ++i)
7082 V[i] = Op.getOperand(i);
7084 // Check for elements which are consecutive loads.
7085 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7089 // Check for a build vector from mostly shuffle plus few inserting.
7090 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7094 // For SSE 4.1, use insertps to put the high elements into the low element.
7095 if (getSubtarget()->hasSSE41()) {
7097 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7098 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7100 Result = DAG.getUNDEF(VT);
7102 for (unsigned i = 1; i < NumElems; ++i) {
7103 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7104 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7105 Op.getOperand(i), DAG.getIntPtrConstant(i));
7110 // Otherwise, expand into a number of unpckl*, start by extending each of
7111 // our (non-undef) elements to the full vector width with the element in the
7112 // bottom slot of the vector (which generates no code for SSE).
7113 for (unsigned i = 0; i < NumElems; ++i) {
7114 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7115 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7117 V[i] = DAG.getUNDEF(VT);
7120 // Next, we iteratively mix elements, e.g. for v4f32:
7121 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7122 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7123 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7124 unsigned EltStride = NumElems >> 1;
7125 while (EltStride != 0) {
7126 for (unsigned i = 0; i < EltStride; ++i) {
7127 // If V[i+EltStride] is undef and this is the first round of mixing,
7128 // then it is safe to just drop this shuffle: V[i] is already in the
7129 // right place, the one element (since it's the first round) being
7130 // inserted as undef can be dropped. This isn't safe for successive
7131 // rounds because they will permute elements within both vectors.
7132 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7133 EltStride == NumElems/2)
7136 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7145 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7146 // to create 256-bit vectors from two other 128-bit ones.
7147 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7149 MVT ResVT = Op.getSimpleValueType();
7151 assert((ResVT.is256BitVector() ||
7152 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7154 SDValue V1 = Op.getOperand(0);
7155 SDValue V2 = Op.getOperand(1);
7156 unsigned NumElems = ResVT.getVectorNumElements();
7157 if(ResVT.is256BitVector())
7158 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7160 if (Op.getNumOperands() == 4) {
7161 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7162 ResVT.getVectorNumElements()/2);
7163 SDValue V3 = Op.getOperand(2);
7164 SDValue V4 = Op.getOperand(3);
7165 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7166 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7168 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7171 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7172 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7173 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7174 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7175 Op.getNumOperands() == 4)));
7177 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7178 // from two other 128-bit ones.
7180 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7181 return LowerAVXCONCAT_VECTORS(Op, DAG);
7185 //===----------------------------------------------------------------------===//
7186 // Vector shuffle lowering
7188 // This is an experimental code path for lowering vector shuffles on x86. It is
7189 // designed to handle arbitrary vector shuffles and blends, gracefully
7190 // degrading performance as necessary. It works hard to recognize idiomatic
7191 // shuffles and lower them to optimal instruction patterns without leaving
7192 // a framework that allows reasonably efficient handling of all vector shuffle
7194 //===----------------------------------------------------------------------===//
7196 /// \brief Tiny helper function to identify a no-op mask.
7198 /// This is a somewhat boring predicate function. It checks whether the mask
7199 /// array input, which is assumed to be a single-input shuffle mask of the kind
7200 /// used by the X86 shuffle instructions (not a fully general
7201 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7202 /// in-place shuffle are 'no-op's.
7203 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7204 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7205 if (Mask[i] != -1 && Mask[i] != i)
7210 /// \brief Helper function to classify a mask as a single-input mask.
7212 /// This isn't a generic single-input test because in the vector shuffle
7213 /// lowering we canonicalize single inputs to be the first input operand. This
7214 /// means we can more quickly test for a single input by only checking whether
7215 /// an input from the second operand exists. We also assume that the size of
7216 /// mask corresponds to the size of the input vectors which isn't true in the
7217 /// fully general case.
7218 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7220 if (M >= (int)Mask.size())
7225 /// \brief Test whether there are elements crossing 128-bit lanes in this
7228 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7229 /// and we routinely test for these.
7230 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7231 int LaneSize = 128 / VT.getScalarSizeInBits();
7232 int Size = Mask.size();
7233 for (int i = 0; i < Size; ++i)
7234 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7239 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7241 /// This checks a shuffle mask to see if it is performing the same
7242 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7243 /// that it is also not lane-crossing. It may however involve a blend from the
7244 /// same lane of a second vector.
7246 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7247 /// non-trivial to compute in the face of undef lanes. The representation is
7248 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7249 /// entries from both V1 and V2 inputs to the wider mask.
7251 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7252 SmallVectorImpl<int> &RepeatedMask) {
7253 int LaneSize = 128 / VT.getScalarSizeInBits();
7254 RepeatedMask.resize(LaneSize, -1);
7255 int Size = Mask.size();
7256 for (int i = 0; i < Size; ++i) {
7259 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7260 // This entry crosses lanes, so there is no way to model this shuffle.
7263 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7264 if (RepeatedMask[i % LaneSize] == -1)
7265 // This is the first non-undef entry in this slot of a 128-bit lane.
7266 RepeatedMask[i % LaneSize] =
7267 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7268 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7269 // Found a mismatch with the repeated mask.
7275 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7276 // 2013 will allow us to use it as a non-type template parameter.
7279 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7281 /// See its documentation for details.
7282 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7283 if (Mask.size() != Args.size())
7285 for (int i = 0, e = Mask.size(); i < e; ++i) {
7286 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7287 if (Mask[i] != -1 && Mask[i] != *Args[i])
7295 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7298 /// This is a fast way to test a shuffle mask against a fixed pattern:
7300 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7302 /// It returns true if the mask is exactly as wide as the argument list, and
7303 /// each element of the mask is either -1 (signifying undef) or the value given
7304 /// in the argument.
7305 static const VariadicFunction1<
7306 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7308 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7310 /// This helper function produces an 8-bit shuffle immediate corresponding to
7311 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7312 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7315 /// NB: We rely heavily on "undef" masks preserving the input lane.
7316 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7317 SelectionDAG &DAG) {
7318 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7319 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7320 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7321 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7322 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7325 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7326 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7327 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7328 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7329 return DAG.getConstant(Imm, MVT::i8);
7332 /// \brief Try to emit a blend instruction for a shuffle.
7334 /// This doesn't do any checks for the availability of instructions for blending
7335 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7336 /// be matched in the backend with the type given. What it does check for is
7337 /// that the shuffle mask is in fact a blend.
7338 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7339 SDValue V2, ArrayRef<int> Mask,
7340 const X86Subtarget *Subtarget,
7341 SelectionDAG &DAG) {
7343 unsigned BlendMask = 0;
7344 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7345 if (Mask[i] >= Size) {
7346 if (Mask[i] != i + Size)
7347 return SDValue(); // Shuffled V2 input!
7348 BlendMask |= 1u << i;
7351 if (Mask[i] >= 0 && Mask[i] != i)
7352 return SDValue(); // Shuffled V1 input!
7354 switch (VT.SimpleTy) {
7359 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7360 DAG.getConstant(BlendMask, MVT::i8));
7364 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7368 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7369 // that instruction.
7370 if (Subtarget->hasAVX2()) {
7371 // Scale the blend by the number of 32-bit dwords per element.
7372 int Scale = VT.getScalarSizeInBits() / 32;
7374 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7375 if (Mask[i] >= Size)
7376 for (int j = 0; j < Scale; ++j)
7377 BlendMask |= 1u << (i * Scale + j);
7379 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7380 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7381 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7382 return DAG.getNode(ISD::BITCAST, DL, VT,
7383 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7384 DAG.getConstant(BlendMask, MVT::i8)));
7388 // For integer shuffles we need to expand the mask and cast the inputs to
7389 // v8i16s prior to blending.
7390 int Scale = 8 / VT.getVectorNumElements();
7392 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7393 if (Mask[i] >= Size)
7394 for (int j = 0; j < Scale; ++j)
7395 BlendMask |= 1u << (i * Scale + j);
7397 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7398 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7399 return DAG.getNode(ISD::BITCAST, DL, VT,
7400 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7401 DAG.getConstant(BlendMask, MVT::i8)));
7405 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7406 SmallVector<int, 8> RepeatedMask;
7407 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7408 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7409 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7411 for (int i = 0; i < 8; ++i)
7412 if (RepeatedMask[i] >= 16)
7413 BlendMask |= 1u << i;
7414 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7415 DAG.getConstant(BlendMask, MVT::i8));
7420 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7421 // Scale the blend by the number of bytes per element.
7422 int Scale = VT.getScalarSizeInBits() / 8;
7423 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7425 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7426 // mix of LLVM's code generator and the x86 backend. We tell the code
7427 // generator that boolean values in the elements of an x86 vector register
7428 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7429 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7430 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7431 // of the element (the remaining are ignored) and 0 in that high bit would
7432 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7433 // the LLVM model for boolean values in vector elements gets the relevant
7434 // bit set, it is set backwards and over constrained relative to x86's
7436 SDValue VSELECTMask[32];
7437 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7438 for (int j = 0; j < Scale; ++j)
7439 VSELECTMask[Scale * i + j] =
7440 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7441 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7443 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7444 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7446 ISD::BITCAST, DL, VT,
7447 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7448 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7453 llvm_unreachable("Not a supported integer vector type!");
7457 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7458 /// unblended shuffles followed by an unshuffled blend.
7460 /// This matches the extremely common pattern for handling combined
7461 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7463 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7467 SelectionDAG &DAG) {
7468 // Shuffle the input elements into the desired positions in V1 and V2 and
7469 // blend them together.
7470 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7471 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7472 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7473 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7474 if (Mask[i] >= 0 && Mask[i] < Size) {
7475 V1Mask[i] = Mask[i];
7477 } else if (Mask[i] >= Size) {
7478 V2Mask[i] = Mask[i] - Size;
7479 BlendMask[i] = i + Size;
7482 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7483 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7484 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7487 /// \brief Try to lower a vector shuffle as a byte rotation.
7489 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7490 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7491 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7492 /// try to generically lower a vector shuffle through such an pattern. It
7493 /// does not check for the profitability of lowering either as PALIGNR or
7494 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7495 /// This matches shuffle vectors that look like:
7497 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7499 /// Essentially it concatenates V1 and V2, shifts right by some number of
7500 /// elements, and takes the low elements as the result. Note that while this is
7501 /// specified as a *right shift* because x86 is little-endian, it is a *left
7502 /// rotate* of the vector lanes.
7504 /// Note that this only handles 128-bit vector widths currently.
7505 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7508 const X86Subtarget *Subtarget,
7509 SelectionDAG &DAG) {
7510 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7512 // We need to detect various ways of spelling a rotation:
7513 // [11, 12, 13, 14, 15, 0, 1, 2]
7514 // [-1, 12, 13, 14, -1, -1, 1, -1]
7515 // [-1, -1, -1, -1, -1, -1, 1, 2]
7516 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7517 // [-1, 4, 5, 6, -1, -1, 9, -1]
7518 // [-1, 4, 5, 6, -1, -1, -1, -1]
7521 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7524 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7526 // Based on the mod-Size value of this mask element determine where
7527 // a rotated vector would have started.
7528 int StartIdx = i - (Mask[i] % Size);
7530 // The identity rotation isn't interesting, stop.
7533 // If we found the tail of a vector the rotation must be the missing
7534 // front. If we found the head of a vector, it must be how much of the head.
7535 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7538 Rotation = CandidateRotation;
7539 else if (Rotation != CandidateRotation)
7540 // The rotations don't match, so we can't match this mask.
7543 // Compute which value this mask is pointing at.
7544 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7546 // Compute which of the two target values this index should be assigned to.
7547 // This reflects whether the high elements are remaining or the low elements
7549 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7551 // Either set up this value if we've not encountered it before, or check
7552 // that it remains consistent.
7555 else if (TargetV != MaskV)
7556 // This may be a rotation, but it pulls from the inputs in some
7557 // unsupported interleaving.
7561 // Check that we successfully analyzed the mask, and normalize the results.
7562 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7563 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7569 assert(VT.getSizeInBits() == 128 &&
7570 "Rotate-based lowering only supports 128-bit lowering!");
7571 assert(Mask.size() <= 16 &&
7572 "Can shuffle at most 16 bytes in a 128-bit vector!");
7574 // The actual rotate instruction rotates bytes, so we need to scale the
7575 // rotation based on how many bytes are in the vector.
7576 int Scale = 16 / Mask.size();
7578 // SSSE3 targets can use the palignr instruction
7579 if (Subtarget->hasSSSE3()) {
7580 // Cast the inputs to v16i8 to match PALIGNR.
7581 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7582 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7584 return DAG.getNode(ISD::BITCAST, DL, VT,
7585 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7586 DAG.getConstant(Rotation * Scale, MVT::i8)));
7589 // Default SSE2 implementation
7590 int LoByteShift = 16 - Rotation * Scale;
7591 int HiByteShift = Rotation * Scale;
7593 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7594 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
7595 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
7597 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7598 DAG.getConstant(8 * LoByteShift, MVT::i8));
7599 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7600 DAG.getConstant(8 * HiByteShift, MVT::i8));
7601 return DAG.getNode(ISD::BITCAST, DL, VT,
7602 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7605 /// \brief Compute whether each element of a shuffle is zeroable.
7607 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7608 /// Either it is an undef element in the shuffle mask, the element of the input
7609 /// referenced is undef, or the element of the input referenced is known to be
7610 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7611 /// as many lanes with this technique as possible to simplify the remaining
7613 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7614 SDValue V1, SDValue V2) {
7615 SmallBitVector Zeroable(Mask.size(), false);
7617 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7618 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7620 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7622 // Handle the easy cases.
7623 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7628 // If this is an index into a build_vector node, dig out the input value and
7630 SDValue V = M < Size ? V1 : V2;
7631 if (V.getOpcode() != ISD::BUILD_VECTOR)
7634 SDValue Input = V.getOperand(M % Size);
7635 // The UNDEF opcode check really should be dead code here, but not quite
7636 // worth asserting on (it isn't invalid, just unexpected).
7637 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7644 /// \brief Try to lower a vector shuffle as a byte shift (shifts in zeros).
7646 /// Attempts to match a shuffle mask against the PSRLDQ and PSLLDQ SSE2
7647 /// byte-shift instructions. The mask must consist of a shifted sequential
7648 /// shuffle from one of the input vectors and zeroable elements for the
7649 /// remaining 'shifted in' elements.
7651 /// Note that this only handles 128-bit vector widths currently.
7652 static SDValue lowerVectorShuffleAsByteShift(SDLoc DL, MVT VT, SDValue V1,
7653 SDValue V2, ArrayRef<int> Mask,
7654 SelectionDAG &DAG) {
7655 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7657 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7659 int Size = Mask.size();
7660 int Scale = 16 / Size;
7662 auto isSequential = [](int Base, int StartIndex, int EndIndex, int MaskOffset,
7663 ArrayRef<int> Mask) {
7664 for (int i = StartIndex; i < EndIndex; i++) {
7667 if (i + Base != Mask[i] - MaskOffset)
7673 for (int Shift = 1; Shift < Size; Shift++) {
7674 int ByteShift = Shift * Scale;
7676 // PSRLDQ : (little-endian) right byte shift
7677 // [ 5, 6, 7, zz, zz, zz, zz, zz]
7678 // [ -1, 5, 6, 7, zz, zz, zz, zz]
7679 // [ 1, 2, -1, -1, -1, -1, zz, zz]
7680 bool ZeroableRight = true;
7681 for (int i = Size - Shift; i < Size; i++) {
7682 ZeroableRight &= Zeroable[i];
7685 if (ZeroableRight) {
7686 bool ValidShiftRight1 = isSequential(Shift, 0, Size - Shift, 0, Mask);
7687 bool ValidShiftRight2 = isSequential(Shift, 0, Size - Shift, Size, Mask);
7689 if (ValidShiftRight1 || ValidShiftRight2) {
7690 // Cast the inputs to v2i64 to match PSRLDQ.
7691 SDValue &TargetV = ValidShiftRight1 ? V1 : V2;
7692 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7693 SDValue Shifted = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, V,
7694 DAG.getConstant(ByteShift * 8, MVT::i8));
7695 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7699 // PSLLDQ : (little-endian) left byte shift
7700 // [ zz, 0, 1, 2, 3, 4, 5, 6]
7701 // [ zz, zz, -1, -1, 2, 3, 4, -1]
7702 // [ zz, zz, zz, zz, zz, zz, -1, 1]
7703 bool ZeroableLeft = true;
7704 for (int i = 0; i < Shift; i++) {
7705 ZeroableLeft &= Zeroable[i];
7709 bool ValidShiftLeft1 = isSequential(-Shift, Shift, Size, 0, Mask);
7710 bool ValidShiftLeft2 = isSequential(-Shift, Shift, Size, Size, Mask);
7712 if (ValidShiftLeft1 || ValidShiftLeft2) {
7713 // Cast the inputs to v2i64 to match PSLLDQ.
7714 SDValue &TargetV = ValidShiftLeft1 ? V1 : V2;
7715 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7716 SDValue Shifted = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, V,
7717 DAG.getConstant(ByteShift * 8, MVT::i8));
7718 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7726 /// \brief Lower a vector shuffle as a zero or any extension.
7728 /// Given a specific number of elements, element bit width, and extension
7729 /// stride, produce either a zero or any extension based on the available
7730 /// features of the subtarget.
7731 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7732 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7733 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7734 assert(Scale > 1 && "Need a scale to extend.");
7735 int EltBits = VT.getSizeInBits() / NumElements;
7736 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7737 "Only 8, 16, and 32 bit elements can be extended.");
7738 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7740 // Found a valid zext mask! Try various lowering strategies based on the
7741 // input type and available ISA extensions.
7742 if (Subtarget->hasSSE41()) {
7743 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7744 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7745 NumElements / Scale);
7746 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7747 return DAG.getNode(ISD::BITCAST, DL, VT,
7748 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7751 // For any extends we can cheat for larger element sizes and use shuffle
7752 // instructions that can fold with a load and/or copy.
7753 if (AnyExt && EltBits == 32) {
7754 int PSHUFDMask[4] = {0, -1, 1, -1};
7756 ISD::BITCAST, DL, VT,
7757 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7758 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7759 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7761 if (AnyExt && EltBits == 16 && Scale > 2) {
7762 int PSHUFDMask[4] = {0, -1, 0, -1};
7763 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7764 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7765 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7766 int PSHUFHWMask[4] = {1, -1, -1, -1};
7768 ISD::BITCAST, DL, VT,
7769 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7770 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7771 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7774 // If this would require more than 2 unpack instructions to expand, use
7775 // pshufb when available. We can only use more than 2 unpack instructions
7776 // when zero extending i8 elements which also makes it easier to use pshufb.
7777 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7778 assert(NumElements == 16 && "Unexpected byte vector width!");
7779 SDValue PSHUFBMask[16];
7780 for (int i = 0; i < 16; ++i)
7782 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7783 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7784 return DAG.getNode(ISD::BITCAST, DL, VT,
7785 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7786 DAG.getNode(ISD::BUILD_VECTOR, DL,
7787 MVT::v16i8, PSHUFBMask)));
7790 // Otherwise emit a sequence of unpacks.
7792 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7793 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7794 : getZeroVector(InputVT, Subtarget, DAG, DL);
7795 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7796 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7800 } while (Scale > 1);
7801 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7804 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7806 /// This routine will try to do everything in its power to cleverly lower
7807 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7808 /// check for the profitability of this lowering, it tries to aggressively
7809 /// match this pattern. It will use all of the micro-architectural details it
7810 /// can to emit an efficient lowering. It handles both blends with all-zero
7811 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7812 /// masking out later).
7814 /// The reason we have dedicated lowering for zext-style shuffles is that they
7815 /// are both incredibly common and often quite performance sensitive.
7816 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7817 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7818 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7819 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7821 int Bits = VT.getSizeInBits();
7822 int NumElements = Mask.size();
7824 // Define a helper function to check a particular ext-scale and lower to it if
7826 auto Lower = [&](int Scale) -> SDValue {
7829 for (int i = 0; i < NumElements; ++i) {
7831 continue; // Valid anywhere but doesn't tell us anything.
7832 if (i % Scale != 0) {
7833 // Each of the extend elements needs to be zeroable.
7837 // We no lorger are in the anyext case.
7842 // Each of the base elements needs to be consecutive indices into the
7843 // same input vector.
7844 SDValue V = Mask[i] < NumElements ? V1 : V2;
7847 else if (InputV != V)
7848 return SDValue(); // Flip-flopping inputs.
7850 if (Mask[i] % NumElements != i / Scale)
7851 return SDValue(); // Non-consecutive strided elemenst.
7854 // If we fail to find an input, we have a zero-shuffle which should always
7855 // have already been handled.
7856 // FIXME: Maybe handle this here in case during blending we end up with one?
7860 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7861 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7864 // The widest scale possible for extending is to a 64-bit integer.
7865 assert(Bits % 64 == 0 &&
7866 "The number of bits in a vector must be divisible by 64 on x86!");
7867 int NumExtElements = Bits / 64;
7869 // Each iteration, try extending the elements half as much, but into twice as
7871 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7872 assert(NumElements % NumExtElements == 0 &&
7873 "The input vector size must be divisble by the extended size.");
7874 if (SDValue V = Lower(NumElements / NumExtElements))
7878 // No viable ext lowering found.
7882 /// \brief Try to get a scalar value for a specific element of a vector.
7884 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7885 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7886 SelectionDAG &DAG) {
7887 MVT VT = V.getSimpleValueType();
7888 MVT EltVT = VT.getVectorElementType();
7889 while (V.getOpcode() == ISD::BITCAST)
7890 V = V.getOperand(0);
7891 // If the bitcasts shift the element size, we can't extract an equivalent
7893 MVT NewVT = V.getSimpleValueType();
7894 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7897 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7898 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
7899 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
7904 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7906 /// This is particularly important because the set of instructions varies
7907 /// significantly based on whether the operand is a load or not.
7908 static bool isShuffleFoldableLoad(SDValue V) {
7909 while (V.getOpcode() == ISD::BITCAST)
7910 V = V.getOperand(0);
7912 return ISD::isNON_EXTLoad(V.getNode());
7915 /// \brief Try to lower insertion of a single element into a zero vector.
7917 /// This is a common pattern that we have especially efficient patterns to lower
7918 /// across all subtarget feature sets.
7919 static SDValue lowerVectorShuffleAsElementInsertion(
7920 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7921 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7922 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7924 MVT EltVT = VT.getVectorElementType();
7926 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7927 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7929 bool IsV1Zeroable = true;
7930 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7931 if (i != V2Index && !Zeroable[i]) {
7932 IsV1Zeroable = false;
7936 // Check for a single input from a SCALAR_TO_VECTOR node.
7937 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7938 // all the smarts here sunk into that routine. However, the current
7939 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7940 // vector shuffle lowering is dead.
7941 if (SDValue V2S = getScalarValueForVectorElement(
7942 V2, Mask[V2Index] - Mask.size(), DAG)) {
7943 // We need to zext the scalar if it is smaller than an i32.
7944 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7945 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7946 // Using zext to expand a narrow element won't work for non-zero
7951 // Zero-extend directly to i32.
7953 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7955 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7956 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7957 EltVT == MVT::i16) {
7958 // Either not inserting from the low element of the input or the input
7959 // element size is too small to use VZEXT_MOVL to clear the high bits.
7963 if (!IsV1Zeroable) {
7964 // If V1 can't be treated as a zero vector we have fewer options to lower
7965 // this. We can't support integer vectors or non-zero targets cheaply, and
7966 // the V1 elements can't be permuted in any way.
7967 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7968 if (!VT.isFloatingPoint() || V2Index != 0)
7970 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7971 V1Mask[V2Index] = -1;
7972 if (!isNoopShuffleMask(V1Mask))
7974 // This is essentially a special case blend operation, but if we have
7975 // general purpose blend operations, they are always faster. Bail and let
7976 // the rest of the lowering handle these as blends.
7977 if (Subtarget->hasSSE41())
7980 // Otherwise, use MOVSD or MOVSS.
7981 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7982 "Only two types of floating point element types to handle!");
7983 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7987 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7989 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7992 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7993 // the desired position. Otherwise it is more efficient to do a vector
7994 // shift left. We know that we can do a vector shift left because all
7995 // the inputs are zero.
7996 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7997 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7998 V2Shuffle[V2Index] = 0;
7999 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
8001 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
8003 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
8005 V2Index * EltVT.getSizeInBits(),
8006 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
8007 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8013 /// \brief Try to lower broadcast of a single element.
8015 /// For convenience, this code also bundles all of the subtarget feature set
8016 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8017 /// a convenient way to factor it out.
8018 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
8020 const X86Subtarget *Subtarget,
8021 SelectionDAG &DAG) {
8022 if (!Subtarget->hasAVX())
8024 if (VT.isInteger() && !Subtarget->hasAVX2())
8027 // Check that the mask is a broadcast.
8028 int BroadcastIdx = -1;
8030 if (M >= 0 && BroadcastIdx == -1)
8032 else if (M >= 0 && M != BroadcastIdx)
8035 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8036 "a sorted mask where the broadcast "
8039 // Go up the chain of (vector) values to try and find a scalar load that
8040 // we can combine with the broadcast.
8042 switch (V.getOpcode()) {
8043 case ISD::CONCAT_VECTORS: {
8044 int OperandSize = Mask.size() / V.getNumOperands();
8045 V = V.getOperand(BroadcastIdx / OperandSize);
8046 BroadcastIdx %= OperandSize;
8050 case ISD::INSERT_SUBVECTOR: {
8051 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8052 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8056 int BeginIdx = (int)ConstantIdx->getZExtValue();
8058 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
8059 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8060 BroadcastIdx -= BeginIdx;
8071 // Check if this is a broadcast of a scalar. We special case lowering
8072 // for scalars so that we can more effectively fold with loads.
8073 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8074 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8075 V = V.getOperand(BroadcastIdx);
8077 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
8079 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8081 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8082 // We can't broadcast from a vector register w/o AVX2, and we can only
8083 // broadcast from the zero-element of a vector register.
8087 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8090 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8092 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8093 /// support for floating point shuffles but not integer shuffles. These
8094 /// instructions will incur a domain crossing penalty on some chips though so
8095 /// it is better to avoid lowering through this for integer vectors where
8097 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8098 const X86Subtarget *Subtarget,
8099 SelectionDAG &DAG) {
8101 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8102 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8103 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8104 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8105 ArrayRef<int> Mask = SVOp->getMask();
8106 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8108 if (isSingleInputShuffleMask(Mask)) {
8109 // Straight shuffle of a single input vector. Simulate this by using the
8110 // single input as both of the "inputs" to this instruction..
8111 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8113 if (Subtarget->hasAVX()) {
8114 // If we have AVX, we can use VPERMILPS which will allow folding a load
8115 // into the shuffle.
8116 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8117 DAG.getConstant(SHUFPDMask, MVT::i8));
8120 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
8121 DAG.getConstant(SHUFPDMask, MVT::i8));
8123 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8124 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8126 // Use dedicated unpack instructions for masks that match their pattern.
8127 if (isShuffleEquivalent(Mask, 0, 2))
8128 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8129 if (isShuffleEquivalent(Mask, 1, 3))
8130 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8132 // If we have a single input, insert that into V1 if we can do so cheaply.
8133 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8134 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8135 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
8137 // Try inverting the insertion since for v2 masks it is easy to do and we
8138 // can't reliably sort the mask one way or the other.
8139 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8140 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8141 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8142 MVT::v2f64, DL, V2, V1, InverseMask, Subtarget, DAG))
8146 // Try to use one of the special instruction patterns to handle two common
8147 // blend patterns if a zero-blend above didn't work.
8148 if (isShuffleEquivalent(Mask, 0, 3) || isShuffleEquivalent(Mask, 1, 3))
8149 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8150 // We can either use a special instruction to load over the low double or
8151 // to move just the low double.
8153 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8155 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8157 if (Subtarget->hasSSE41())
8158 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8162 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8163 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
8164 DAG.getConstant(SHUFPDMask, MVT::i8));
8167 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8169 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8170 /// the integer unit to minimize domain crossing penalties. However, for blends
8171 /// it falls back to the floating point shuffle operation with appropriate bit
8173 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8174 const X86Subtarget *Subtarget,
8175 SelectionDAG &DAG) {
8177 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8178 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8179 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8180 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8181 ArrayRef<int> Mask = SVOp->getMask();
8182 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8184 if (isSingleInputShuffleMask(Mask)) {
8185 // Check for being able to broadcast a single element.
8186 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
8187 Mask, Subtarget, DAG))
8190 // Straight shuffle of a single input vector. For everything from SSE2
8191 // onward this has a single fast instruction with no scary immediates.
8192 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8193 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
8194 int WidenedMask[4] = {
8195 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8196 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8198 ISD::BITCAST, DL, MVT::v2i64,
8199 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
8200 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
8203 // Try to use byte shift instructions.
8204 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8205 DL, MVT::v2i64, V1, V2, Mask, DAG))
8208 // If we have a single input from V2 insert that into V1 if we can do so
8210 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8211 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8212 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
8214 // Try inverting the insertion since for v2 masks it is easy to do and we
8215 // can't reliably sort the mask one way or the other.
8216 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8217 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8218 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8219 MVT::v2i64, DL, V2, V1, InverseMask, Subtarget, DAG))
8223 // Use dedicated unpack instructions for masks that match their pattern.
8224 if (isShuffleEquivalent(Mask, 0, 2))
8225 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8226 if (isShuffleEquivalent(Mask, 1, 3))
8227 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8229 if (Subtarget->hasSSE41())
8230 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8234 // Try to use byte rotation instructions.
8235 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8236 if (Subtarget->hasSSSE3())
8237 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8238 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8241 // We implement this with SHUFPD which is pretty lame because it will likely
8242 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8243 // However, all the alternatives are still more cycles and newer chips don't
8244 // have this problem. It would be really nice if x86 had better shuffles here.
8245 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
8246 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
8247 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
8248 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8251 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8253 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8254 /// It makes no assumptions about whether this is the *best* lowering, it simply
8256 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8257 ArrayRef<int> Mask, SDValue V1,
8258 SDValue V2, SelectionDAG &DAG) {
8259 SDValue LowV = V1, HighV = V2;
8260 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8263 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8265 if (NumV2Elements == 1) {
8267 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8270 // Compute the index adjacent to V2Index and in the same half by toggling
8272 int V2AdjIndex = V2Index ^ 1;
8274 if (Mask[V2AdjIndex] == -1) {
8275 // Handles all the cases where we have a single V2 element and an undef.
8276 // This will only ever happen in the high lanes because we commute the
8277 // vector otherwise.
8279 std::swap(LowV, HighV);
8280 NewMask[V2Index] -= 4;
8282 // Handle the case where the V2 element ends up adjacent to a V1 element.
8283 // To make this work, blend them together as the first step.
8284 int V1Index = V2AdjIndex;
8285 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8286 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8287 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8289 // Now proceed to reconstruct the final blend as we have the necessary
8290 // high or low half formed.
8297 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8298 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8300 } else if (NumV2Elements == 2) {
8301 if (Mask[0] < 4 && Mask[1] < 4) {
8302 // Handle the easy case where we have V1 in the low lanes and V2 in the
8306 } else if (Mask[2] < 4 && Mask[3] < 4) {
8307 // We also handle the reversed case because this utility may get called
8308 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8309 // arrange things in the right direction.
8315 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8316 // trying to place elements directly, just blend them and set up the final
8317 // shuffle to place them.
8319 // The first two blend mask elements are for V1, the second two are for
8321 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8322 Mask[2] < 4 ? Mask[2] : Mask[3],
8323 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8324 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8325 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8326 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8328 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8331 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8332 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8333 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8334 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8337 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8338 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8341 /// \brief Lower 4-lane 32-bit floating point shuffles.
8343 /// Uses instructions exclusively from the floating point unit to minimize
8344 /// domain crossing penalties, as these are sufficient to implement all v4f32
8346 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8347 const X86Subtarget *Subtarget,
8348 SelectionDAG &DAG) {
8350 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8351 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8352 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8353 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8354 ArrayRef<int> Mask = SVOp->getMask();
8355 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8358 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8360 if (NumV2Elements == 0) {
8361 // Check for being able to broadcast a single element.
8362 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8363 Mask, Subtarget, DAG))
8366 if (Subtarget->hasAVX()) {
8367 // If we have AVX, we can use VPERMILPS which will allow folding a load
8368 // into the shuffle.
8369 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8370 getV4X86ShuffleImm8ForMask(Mask, DAG));
8373 // Otherwise, use a straight shuffle of a single input vector. We pass the
8374 // input vector to both operands to simulate this with a SHUFPS.
8375 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8376 getV4X86ShuffleImm8ForMask(Mask, DAG));
8379 // Use dedicated unpack instructions for masks that match their pattern.
8380 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8381 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8382 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8383 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8385 // There are special ways we can lower some single-element blends. However, we
8386 // have custom ways we can lower more complex single-element blends below that
8387 // we defer to if both this and BLENDPS fail to match, so restrict this to
8388 // when the V2 input is targeting element 0 of the mask -- that is the fast
8390 if (NumV2Elements == 1 && Mask[0] >= 4)
8391 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8392 Mask, Subtarget, DAG))
8395 if (Subtarget->hasSSE41())
8396 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8400 // Check for whether we can use INSERTPS to perform the blend. We only use
8401 // INSERTPS when the V1 elements are already in the correct locations
8402 // because otherwise we can just always use two SHUFPS instructions which
8403 // are much smaller to encode than a SHUFPS and an INSERTPS.
8404 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8406 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8409 // When using INSERTPS we can zero any lane of the destination. Collect
8410 // the zero inputs into a mask and drop them from the lanes of V1 which
8411 // actually need to be present as inputs to the INSERTPS.
8412 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8414 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8415 bool InsertNeedsShuffle = false;
8417 for (int i = 0; i < 4; ++i)
8421 } else if (Mask[i] != i) {
8422 InsertNeedsShuffle = true;
8427 // We don't want to use INSERTPS or other insertion techniques if it will
8428 // require shuffling anyways.
8429 if (!InsertNeedsShuffle) {
8430 // If all of V1 is zeroable, replace it with undef.
8431 if ((ZMask | 1 << V2Index) == 0xF)
8432 V1 = DAG.getUNDEF(MVT::v4f32);
8434 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8435 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8437 // Insert the V2 element into the desired position.
8438 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8439 DAG.getConstant(InsertPSMask, MVT::i8));
8443 // Otherwise fall back to a SHUFPS lowering strategy.
8444 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8447 /// \brief Lower 4-lane i32 vector shuffles.
8449 /// We try to handle these with integer-domain shuffles where we can, but for
8450 /// blends we use the floating point domain blend instructions.
8451 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8452 const X86Subtarget *Subtarget,
8453 SelectionDAG &DAG) {
8455 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8456 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8457 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8458 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8459 ArrayRef<int> Mask = SVOp->getMask();
8460 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8462 // Whenever we can lower this as a zext, that instruction is strictly faster
8463 // than any alternative. It also allows us to fold memory operands into the
8464 // shuffle in many cases.
8465 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8466 Mask, Subtarget, DAG))
8470 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8472 if (NumV2Elements == 0) {
8473 // Check for being able to broadcast a single element.
8474 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8475 Mask, Subtarget, DAG))
8478 // Straight shuffle of a single input vector. For everything from SSE2
8479 // onward this has a single fast instruction with no scary immediates.
8480 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8481 // but we aren't actually going to use the UNPCK instruction because doing
8482 // so prevents folding a load into this instruction or making a copy.
8483 const int UnpackLoMask[] = {0, 0, 1, 1};
8484 const int UnpackHiMask[] = {2, 2, 3, 3};
8485 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8486 Mask = UnpackLoMask;
8487 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8488 Mask = UnpackHiMask;
8490 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8491 getV4X86ShuffleImm8ForMask(Mask, DAG));
8494 // Try to use byte shift instructions.
8495 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8496 DL, MVT::v4i32, V1, V2, Mask, DAG))
8499 // There are special ways we can lower some single-element blends.
8500 if (NumV2Elements == 1)
8501 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8502 Mask, Subtarget, DAG))
8505 // Use dedicated unpack instructions for masks that match their pattern.
8506 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8507 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8508 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8509 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8511 if (Subtarget->hasSSE41())
8512 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8516 // Try to use byte rotation instructions.
8517 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8518 if (Subtarget->hasSSSE3())
8519 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8520 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8523 // We implement this with SHUFPS because it can blend from two vectors.
8524 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8525 // up the inputs, bypassing domain shift penalties that we would encur if we
8526 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8528 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8529 DAG.getVectorShuffle(
8531 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8532 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8535 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8536 /// shuffle lowering, and the most complex part.
8538 /// The lowering strategy is to try to form pairs of input lanes which are
8539 /// targeted at the same half of the final vector, and then use a dword shuffle
8540 /// to place them onto the right half, and finally unpack the paired lanes into
8541 /// their final position.
8543 /// The exact breakdown of how to form these dword pairs and align them on the
8544 /// correct sides is really tricky. See the comments within the function for
8545 /// more of the details.
8546 static SDValue lowerV8I16SingleInputVectorShuffle(
8547 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8548 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8549 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8550 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8551 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8553 SmallVector<int, 4> LoInputs;
8554 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8555 [](int M) { return M >= 0; });
8556 std::sort(LoInputs.begin(), LoInputs.end());
8557 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8558 SmallVector<int, 4> HiInputs;
8559 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8560 [](int M) { return M >= 0; });
8561 std::sort(HiInputs.begin(), HiInputs.end());
8562 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8564 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8565 int NumHToL = LoInputs.size() - NumLToL;
8567 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8568 int NumHToH = HiInputs.size() - NumLToH;
8569 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8570 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8571 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8572 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8574 // Check for being able to broadcast a single element.
8575 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8576 Mask, Subtarget, DAG))
8579 // Try to use byte shift instructions.
8580 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8581 DL, MVT::v8i16, V, V, Mask, DAG))
8584 // Use dedicated unpack instructions for masks that match their pattern.
8585 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8586 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8587 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8588 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8590 // Try to use byte rotation instructions.
8591 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8592 DL, MVT::v8i16, V, V, Mask, Subtarget, DAG))
8595 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8596 // such inputs we can swap two of the dwords across the half mark and end up
8597 // with <=2 inputs to each half in each half. Once there, we can fall through
8598 // to the generic code below. For example:
8600 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8601 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8603 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8604 // and an existing 2-into-2 on the other half. In this case we may have to
8605 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8606 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8607 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8608 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8609 // half than the one we target for fixing) will be fixed when we re-enter this
8610 // path. We will also combine away any sequence of PSHUFD instructions that
8611 // result into a single instruction. Here is an example of the tricky case:
8613 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8614 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8616 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8618 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8619 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8621 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8622 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8624 // The result is fine to be handled by the generic logic.
8625 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8626 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8627 int AOffset, int BOffset) {
8628 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8629 "Must call this with A having 3 or 1 inputs from the A half.");
8630 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8631 "Must call this with B having 1 or 3 inputs from the B half.");
8632 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8633 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8635 // Compute the index of dword with only one word among the three inputs in
8636 // a half by taking the sum of the half with three inputs and subtracting
8637 // the sum of the actual three inputs. The difference is the remaining
8640 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8641 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8642 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8643 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8644 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8645 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8646 int TripleNonInputIdx =
8647 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8648 TripleDWord = TripleNonInputIdx / 2;
8650 // We use xor with one to compute the adjacent DWord to whichever one the
8652 OneInputDWord = (OneInput / 2) ^ 1;
8654 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8655 // and BToA inputs. If there is also such a problem with the BToB and AToB
8656 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8657 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8658 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8659 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8660 // Compute how many inputs will be flipped by swapping these DWords. We
8662 // to balance this to ensure we don't form a 3-1 shuffle in the other
8664 int NumFlippedAToBInputs =
8665 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8666 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8667 int NumFlippedBToBInputs =
8668 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8669 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8670 if ((NumFlippedAToBInputs == 1 &&
8671 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8672 (NumFlippedBToBInputs == 1 &&
8673 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8674 // We choose whether to fix the A half or B half based on whether that
8675 // half has zero flipped inputs. At zero, we may not be able to fix it
8676 // with that half. We also bias towards fixing the B half because that
8677 // will more commonly be the high half, and we have to bias one way.
8678 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8679 ArrayRef<int> Inputs) {
8680 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8681 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8682 PinnedIdx ^ 1) != Inputs.end();
8683 // Determine whether the free index is in the flipped dword or the
8684 // unflipped dword based on where the pinned index is. We use this bit
8685 // in an xor to conditionally select the adjacent dword.
8686 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8687 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8688 FixFreeIdx) != Inputs.end();
8689 if (IsFixIdxInput == IsFixFreeIdxInput)
8691 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8692 FixFreeIdx) != Inputs.end();
8693 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8694 "We need to be changing the number of flipped inputs!");
8695 int PSHUFHalfMask[] = {0, 1, 2, 3};
8696 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8697 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8699 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8702 if (M != -1 && M == FixIdx)
8704 else if (M != -1 && M == FixFreeIdx)
8707 if (NumFlippedBToBInputs != 0) {
8709 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8710 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8712 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8714 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8715 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8720 int PSHUFDMask[] = {0, 1, 2, 3};
8721 PSHUFDMask[ADWord] = BDWord;
8722 PSHUFDMask[BDWord] = ADWord;
8723 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8724 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8725 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8726 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8728 // Adjust the mask to match the new locations of A and B.
8730 if (M != -1 && M/2 == ADWord)
8731 M = 2 * BDWord + M % 2;
8732 else if (M != -1 && M/2 == BDWord)
8733 M = 2 * ADWord + M % 2;
8735 // Recurse back into this routine to re-compute state now that this isn't
8736 // a 3 and 1 problem.
8737 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8740 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8741 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8742 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8743 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8745 // At this point there are at most two inputs to the low and high halves from
8746 // each half. That means the inputs can always be grouped into dwords and
8747 // those dwords can then be moved to the correct half with a dword shuffle.
8748 // We use at most one low and one high word shuffle to collect these paired
8749 // inputs into dwords, and finally a dword shuffle to place them.
8750 int PSHUFLMask[4] = {-1, -1, -1, -1};
8751 int PSHUFHMask[4] = {-1, -1, -1, -1};
8752 int PSHUFDMask[4] = {-1, -1, -1, -1};
8754 // First fix the masks for all the inputs that are staying in their
8755 // original halves. This will then dictate the targets of the cross-half
8757 auto fixInPlaceInputs =
8758 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8759 MutableArrayRef<int> SourceHalfMask,
8760 MutableArrayRef<int> HalfMask, int HalfOffset) {
8761 if (InPlaceInputs.empty())
8763 if (InPlaceInputs.size() == 1) {
8764 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8765 InPlaceInputs[0] - HalfOffset;
8766 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8769 if (IncomingInputs.empty()) {
8770 // Just fix all of the in place inputs.
8771 for (int Input : InPlaceInputs) {
8772 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8773 PSHUFDMask[Input / 2] = Input / 2;
8778 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8779 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8780 InPlaceInputs[0] - HalfOffset;
8781 // Put the second input next to the first so that they are packed into
8782 // a dword. We find the adjacent index by toggling the low bit.
8783 int AdjIndex = InPlaceInputs[0] ^ 1;
8784 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8785 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8786 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8788 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8789 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8791 // Now gather the cross-half inputs and place them into a free dword of
8792 // their target half.
8793 // FIXME: This operation could almost certainly be simplified dramatically to
8794 // look more like the 3-1 fixing operation.
8795 auto moveInputsToRightHalf = [&PSHUFDMask](
8796 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8797 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8798 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8800 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8801 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8803 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8805 int LowWord = Word & ~1;
8806 int HighWord = Word | 1;
8807 return isWordClobbered(SourceHalfMask, LowWord) ||
8808 isWordClobbered(SourceHalfMask, HighWord);
8811 if (IncomingInputs.empty())
8814 if (ExistingInputs.empty()) {
8815 // Map any dwords with inputs from them into the right half.
8816 for (int Input : IncomingInputs) {
8817 // If the source half mask maps over the inputs, turn those into
8818 // swaps and use the swapped lane.
8819 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8820 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8821 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8822 Input - SourceOffset;
8823 // We have to swap the uses in our half mask in one sweep.
8824 for (int &M : HalfMask)
8825 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8827 else if (M == Input)
8828 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8830 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8831 Input - SourceOffset &&
8832 "Previous placement doesn't match!");
8834 // Note that this correctly re-maps both when we do a swap and when
8835 // we observe the other side of the swap above. We rely on that to
8836 // avoid swapping the members of the input list directly.
8837 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8840 // Map the input's dword into the correct half.
8841 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8842 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8844 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8846 "Previous placement doesn't match!");
8849 // And just directly shift any other-half mask elements to be same-half
8850 // as we will have mirrored the dword containing the element into the
8851 // same position within that half.
8852 for (int &M : HalfMask)
8853 if (M >= SourceOffset && M < SourceOffset + 4) {
8854 M = M - SourceOffset + DestOffset;
8855 assert(M >= 0 && "This should never wrap below zero!");
8860 // Ensure we have the input in a viable dword of its current half. This
8861 // is particularly tricky because the original position may be clobbered
8862 // by inputs being moved and *staying* in that half.
8863 if (IncomingInputs.size() == 1) {
8864 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8865 int InputFixed = std::find(std::begin(SourceHalfMask),
8866 std::end(SourceHalfMask), -1) -
8867 std::begin(SourceHalfMask) + SourceOffset;
8868 SourceHalfMask[InputFixed - SourceOffset] =
8869 IncomingInputs[0] - SourceOffset;
8870 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8872 IncomingInputs[0] = InputFixed;
8874 } else if (IncomingInputs.size() == 2) {
8875 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8876 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8877 // We have two non-adjacent or clobbered inputs we need to extract from
8878 // the source half. To do this, we need to map them into some adjacent
8879 // dword slot in the source mask.
8880 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8881 IncomingInputs[1] - SourceOffset};
8883 // If there is a free slot in the source half mask adjacent to one of
8884 // the inputs, place the other input in it. We use (Index XOR 1) to
8885 // compute an adjacent index.
8886 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8887 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8888 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8889 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8890 InputsFixed[1] = InputsFixed[0] ^ 1;
8891 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8892 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8893 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8894 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8895 InputsFixed[0] = InputsFixed[1] ^ 1;
8896 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8897 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8898 // The two inputs are in the same DWord but it is clobbered and the
8899 // adjacent DWord isn't used at all. Move both inputs to the free
8901 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8902 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8903 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8904 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8906 // The only way we hit this point is if there is no clobbering
8907 // (because there are no off-half inputs to this half) and there is no
8908 // free slot adjacent to one of the inputs. In this case, we have to
8909 // swap an input with a non-input.
8910 for (int i = 0; i < 4; ++i)
8911 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8912 "We can't handle any clobbers here!");
8913 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8914 "Cannot have adjacent inputs here!");
8916 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8917 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8919 // We also have to update the final source mask in this case because
8920 // it may need to undo the above swap.
8921 for (int &M : FinalSourceHalfMask)
8922 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8923 M = InputsFixed[1] + SourceOffset;
8924 else if (M == InputsFixed[1] + SourceOffset)
8925 M = (InputsFixed[0] ^ 1) + SourceOffset;
8927 InputsFixed[1] = InputsFixed[0] ^ 1;
8930 // Point everything at the fixed inputs.
8931 for (int &M : HalfMask)
8932 if (M == IncomingInputs[0])
8933 M = InputsFixed[0] + SourceOffset;
8934 else if (M == IncomingInputs[1])
8935 M = InputsFixed[1] + SourceOffset;
8937 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8938 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8941 llvm_unreachable("Unhandled input size!");
8944 // Now hoist the DWord down to the right half.
8945 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8946 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8947 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8948 for (int &M : HalfMask)
8949 for (int Input : IncomingInputs)
8951 M = FreeDWord * 2 + Input % 2;
8953 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8954 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8955 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8956 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8958 // Now enact all the shuffles we've computed to move the inputs into their
8960 if (!isNoopShuffleMask(PSHUFLMask))
8961 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8962 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8963 if (!isNoopShuffleMask(PSHUFHMask))
8964 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8965 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8966 if (!isNoopShuffleMask(PSHUFDMask))
8967 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8968 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8969 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8970 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8972 // At this point, each half should contain all its inputs, and we can then
8973 // just shuffle them into their final position.
8974 assert(std::count_if(LoMask.begin(), LoMask.end(),
8975 [](int M) { return M >= 4; }) == 0 &&
8976 "Failed to lift all the high half inputs to the low mask!");
8977 assert(std::count_if(HiMask.begin(), HiMask.end(),
8978 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8979 "Failed to lift all the low half inputs to the high mask!");
8981 // Do a half shuffle for the low mask.
8982 if (!isNoopShuffleMask(LoMask))
8983 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8984 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8986 // Do a half shuffle with the high mask after shifting its values down.
8987 for (int &M : HiMask)
8990 if (!isNoopShuffleMask(HiMask))
8991 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8992 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8997 /// \brief Detect whether the mask pattern should be lowered through
9000 /// This essentially tests whether viewing the mask as an interleaving of two
9001 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
9002 /// lowering it through interleaving is a significantly better strategy.
9003 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
9004 int NumEvenInputs[2] = {0, 0};
9005 int NumOddInputs[2] = {0, 0};
9006 int NumLoInputs[2] = {0, 0};
9007 int NumHiInputs[2] = {0, 0};
9008 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
9012 int InputIdx = Mask[i] >= Size;
9015 ++NumLoInputs[InputIdx];
9017 ++NumHiInputs[InputIdx];
9020 ++NumEvenInputs[InputIdx];
9022 ++NumOddInputs[InputIdx];
9025 // The minimum number of cross-input results for both the interleaved and
9026 // split cases. If interleaving results in fewer cross-input results, return
9028 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
9029 NumEvenInputs[0] + NumOddInputs[1]);
9030 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
9031 NumLoInputs[0] + NumHiInputs[1]);
9032 return InterleavedCrosses < SplitCrosses;
9035 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
9037 /// This strategy only works when the inputs from each vector fit into a single
9038 /// half of that vector, and generally there are not so many inputs as to leave
9039 /// the in-place shuffles required highly constrained (and thus expensive). It
9040 /// shifts all the inputs into a single side of both input vectors and then
9041 /// uses an unpack to interleave these inputs in a single vector. At that
9042 /// point, we will fall back on the generic single input shuffle lowering.
9043 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
9045 MutableArrayRef<int> Mask,
9046 const X86Subtarget *Subtarget,
9047 SelectionDAG &DAG) {
9048 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9049 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9050 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
9051 for (int i = 0; i < 8; ++i)
9052 if (Mask[i] >= 0 && Mask[i] < 4)
9053 LoV1Inputs.push_back(i);
9054 else if (Mask[i] >= 4 && Mask[i] < 8)
9055 HiV1Inputs.push_back(i);
9056 else if (Mask[i] >= 8 && Mask[i] < 12)
9057 LoV2Inputs.push_back(i);
9058 else if (Mask[i] >= 12)
9059 HiV2Inputs.push_back(i);
9061 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
9062 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
9065 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
9066 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
9067 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
9069 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
9070 HiV1Inputs.size() + HiV2Inputs.size();
9072 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
9073 ArrayRef<int> HiInputs, bool MoveToLo,
9075 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
9076 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
9077 if (BadInputs.empty())
9080 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9081 int MoveOffset = MoveToLo ? 0 : 4;
9083 if (GoodInputs.empty()) {
9084 for (int BadInput : BadInputs) {
9085 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
9086 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
9089 if (GoodInputs.size() == 2) {
9090 // If the low inputs are spread across two dwords, pack them into
9092 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
9093 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
9094 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
9095 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
9097 // Otherwise pin the good inputs.
9098 for (int GoodInput : GoodInputs)
9099 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
9102 if (BadInputs.size() == 2) {
9103 // If we have two bad inputs then there may be either one or two good
9104 // inputs fixed in place. Find a fixed input, and then find the *other*
9105 // two adjacent indices by using modular arithmetic.
9107 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
9108 [](int M) { return M >= 0; }) -
9109 std::begin(MoveMask);
9111 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
9112 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
9113 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
9114 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9115 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
9116 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9117 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
9119 assert(BadInputs.size() == 1 && "All sizes handled");
9120 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
9121 std::end(MoveMask), -1) -
9122 std::begin(MoveMask);
9123 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9124 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9128 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
9131 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
9133 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
9136 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
9137 // cross-half traffic in the final shuffle.
9139 // Munge the mask to be a single-input mask after the unpack merges the
9143 M = 2 * (M % 4) + (M / 8);
9145 return DAG.getVectorShuffle(
9146 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
9147 DL, MVT::v8i16, V1, V2),
9148 DAG.getUNDEF(MVT::v8i16), Mask);
9151 /// \brief Generic lowering of 8-lane i16 shuffles.
9153 /// This handles both single-input shuffles and combined shuffle/blends with
9154 /// two inputs. The single input shuffles are immediately delegated to
9155 /// a dedicated lowering routine.
9157 /// The blends are lowered in one of three fundamental ways. If there are few
9158 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9159 /// of the input is significantly cheaper when lowered as an interleaving of
9160 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9161 /// halves of the inputs separately (making them have relatively few inputs)
9162 /// and then concatenate them.
9163 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9164 const X86Subtarget *Subtarget,
9165 SelectionDAG &DAG) {
9167 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9168 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9169 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9170 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9171 ArrayRef<int> OrigMask = SVOp->getMask();
9172 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9173 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9174 MutableArrayRef<int> Mask(MaskStorage);
9176 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9178 // Whenever we can lower this as a zext, that instruction is strictly faster
9179 // than any alternative.
9180 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9181 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9184 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9185 auto isV2 = [](int M) { return M >= 8; };
9187 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
9188 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9190 if (NumV2Inputs == 0)
9191 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
9193 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
9194 "to be V1-input shuffles.");
9196 // Try to use byte shift instructions.
9197 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9198 DL, MVT::v8i16, V1, V2, Mask, DAG))
9201 // There are special ways we can lower some single-element blends.
9202 if (NumV2Inputs == 1)
9203 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
9204 Mask, Subtarget, DAG))
9207 // Use dedicated unpack instructions for masks that match their pattern.
9208 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 2, 10, 3, 11))
9209 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9210 if (isShuffleEquivalent(Mask, 4, 12, 5, 13, 6, 14, 7, 15))
9211 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9213 if (Subtarget->hasSSE41())
9214 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9218 // Try to use byte rotation instructions.
9219 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9220 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9223 if (NumV1Inputs + NumV2Inputs <= 4)
9224 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
9226 // Check whether an interleaving lowering is likely to be more efficient.
9227 // This isn't perfect but it is a strong heuristic that tends to work well on
9228 // the kinds of shuffles that show up in practice.
9230 // FIXME: Handle 1x, 2x, and 4x interleaving.
9231 if (shouldLowerAsInterleaving(Mask)) {
9232 // FIXME: Figure out whether we should pack these into the low or high
9235 int EMask[8], OMask[8];
9236 for (int i = 0; i < 4; ++i) {
9237 EMask[i] = Mask[2*i];
9238 OMask[i] = Mask[2*i + 1];
9243 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
9244 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
9246 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
9249 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9250 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9252 for (int i = 0; i < 4; ++i) {
9253 LoBlendMask[i] = Mask[i];
9254 HiBlendMask[i] = Mask[i + 4];
9257 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9258 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9259 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
9260 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
9262 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9263 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
9266 /// \brief Check whether a compaction lowering can be done by dropping even
9267 /// elements and compute how many times even elements must be dropped.
9269 /// This handles shuffles which take every Nth element where N is a power of
9270 /// two. Example shuffle masks:
9272 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9273 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9274 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9275 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9276 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9277 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9279 /// Any of these lanes can of course be undef.
9281 /// This routine only supports N <= 3.
9282 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9285 /// \returns N above, or the number of times even elements must be dropped if
9286 /// there is such a number. Otherwise returns zero.
9287 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9288 // Figure out whether we're looping over two inputs or just one.
9289 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9291 // The modulus for the shuffle vector entries is based on whether this is
9292 // a single input or not.
9293 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9294 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9295 "We should only be called with masks with a power-of-2 size!");
9297 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9299 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9300 // and 2^3 simultaneously. This is because we may have ambiguity with
9301 // partially undef inputs.
9302 bool ViableForN[3] = {true, true, true};
9304 for (int i = 0, e = Mask.size(); i < e; ++i) {
9305 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9310 bool IsAnyViable = false;
9311 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9312 if (ViableForN[j]) {
9315 // The shuffle mask must be equal to (i * 2^N) % M.
9316 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9319 ViableForN[j] = false;
9321 // Early exit if we exhaust the possible powers of two.
9326 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9330 // Return 0 as there is no viable power of two.
9334 /// \brief Generic lowering of v16i8 shuffles.
9336 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9337 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9338 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9339 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9341 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9342 const X86Subtarget *Subtarget,
9343 SelectionDAG &DAG) {
9345 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9346 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9347 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9348 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9349 ArrayRef<int> OrigMask = SVOp->getMask();
9350 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9352 // Try to use byte shift instructions.
9353 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9354 DL, MVT::v16i8, V1, V2, OrigMask, DAG))
9357 // Try to use byte rotation instructions.
9358 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9359 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9362 // Try to use a zext lowering.
9363 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9364 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9367 int MaskStorage[16] = {
9368 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9369 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9370 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9371 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9372 MutableArrayRef<int> Mask(MaskStorage);
9373 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9374 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9377 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9379 // For single-input shuffles, there are some nicer lowering tricks we can use.
9380 if (NumV2Elements == 0) {
9381 // Check for being able to broadcast a single element.
9382 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9383 Mask, Subtarget, DAG))
9386 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9387 // Notably, this handles splat and partial-splat shuffles more efficiently.
9388 // However, it only makes sense if the pre-duplication shuffle simplifies
9389 // things significantly. Currently, this means we need to be able to
9390 // express the pre-duplication shuffle as an i16 shuffle.
9392 // FIXME: We should check for other patterns which can be widened into an
9393 // i16 shuffle as well.
9394 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9395 for (int i = 0; i < 16; i += 2)
9396 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9401 auto tryToWidenViaDuplication = [&]() -> SDValue {
9402 if (!canWidenViaDuplication(Mask))
9404 SmallVector<int, 4> LoInputs;
9405 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9406 [](int M) { return M >= 0 && M < 8; });
9407 std::sort(LoInputs.begin(), LoInputs.end());
9408 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9410 SmallVector<int, 4> HiInputs;
9411 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9412 [](int M) { return M >= 8; });
9413 std::sort(HiInputs.begin(), HiInputs.end());
9414 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9417 bool TargetLo = LoInputs.size() >= HiInputs.size();
9418 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9419 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9421 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9422 SmallDenseMap<int, int, 8> LaneMap;
9423 for (int I : InPlaceInputs) {
9424 PreDupI16Shuffle[I/2] = I/2;
9427 int j = TargetLo ? 0 : 4, je = j + 4;
9428 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9429 // Check if j is already a shuffle of this input. This happens when
9430 // there are two adjacent bytes after we move the low one.
9431 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9432 // If we haven't yet mapped the input, search for a slot into which
9434 while (j < je && PreDupI16Shuffle[j] != -1)
9438 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9441 // Map this input with the i16 shuffle.
9442 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9445 // Update the lane map based on the mapping we ended up with.
9446 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9449 ISD::BITCAST, DL, MVT::v16i8,
9450 DAG.getVectorShuffle(MVT::v8i16, DL,
9451 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9452 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9454 // Unpack the bytes to form the i16s that will be shuffled into place.
9455 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9456 MVT::v16i8, V1, V1);
9458 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9459 for (int i = 0; i < 16; ++i)
9460 if (Mask[i] != -1) {
9461 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9462 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9463 if (PostDupI16Shuffle[i / 2] == -1)
9464 PostDupI16Shuffle[i / 2] = MappedMask;
9466 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9467 "Conflicting entrties in the original shuffle!");
9470 ISD::BITCAST, DL, MVT::v16i8,
9471 DAG.getVectorShuffle(MVT::v8i16, DL,
9472 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9473 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9475 if (SDValue V = tryToWidenViaDuplication())
9479 // Check whether an interleaving lowering is likely to be more efficient.
9480 // This isn't perfect but it is a strong heuristic that tends to work well on
9481 // the kinds of shuffles that show up in practice.
9483 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9484 if (shouldLowerAsInterleaving(Mask)) {
9485 int NumLoHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9486 return (M >= 0 && M < 8) || (M >= 16 && M < 24);
9488 int NumHiHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9489 return (M >= 8 && M < 16) || M >= 24;
9491 int EMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9492 -1, -1, -1, -1, -1, -1, -1, -1};
9493 int OMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9494 -1, -1, -1, -1, -1, -1, -1, -1};
9495 bool UnpackLo = NumLoHalf >= NumHiHalf;
9496 MutableArrayRef<int> TargetEMask(UnpackLo ? EMask : EMask + 8, 8);
9497 MutableArrayRef<int> TargetOMask(UnpackLo ? OMask : OMask + 8, 8);
9498 for (int i = 0; i < 8; ++i) {
9499 TargetEMask[i] = Mask[2 * i];
9500 TargetOMask[i] = Mask[2 * i + 1];
9503 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9504 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9506 return DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9507 MVT::v16i8, Evens, Odds);
9510 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9511 // with PSHUFB. It is important to do this before we attempt to generate any
9512 // blends but after all of the single-input lowerings. If the single input
9513 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9514 // want to preserve that and we can DAG combine any longer sequences into
9515 // a PSHUFB in the end. But once we start blending from multiple inputs,
9516 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9517 // and there are *very* few patterns that would actually be faster than the
9518 // PSHUFB approach because of its ability to zero lanes.
9520 // FIXME: The only exceptions to the above are blends which are exact
9521 // interleavings with direct instructions supporting them. We currently don't
9522 // handle those well here.
9523 if (Subtarget->hasSSSE3()) {
9526 for (int i = 0; i < 16; ++i)
9527 if (Mask[i] == -1) {
9528 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9530 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9532 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9534 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9535 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9536 if (isSingleInputShuffleMask(Mask))
9537 return V1; // Single inputs are easy.
9539 // Otherwise, blend the two.
9540 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9541 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9542 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9545 // There are special ways we can lower some single-element blends.
9546 if (NumV2Elements == 1)
9547 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9548 Mask, Subtarget, DAG))
9551 // Check whether a compaction lowering can be done. This handles shuffles
9552 // which take every Nth element for some even N. See the helper function for
9555 // We special case these as they can be particularly efficiently handled with
9556 // the PACKUSB instruction on x86 and they show up in common patterns of
9557 // rearranging bytes to truncate wide elements.
9558 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9559 // NumEvenDrops is the power of two stride of the elements. Another way of
9560 // thinking about it is that we need to drop the even elements this many
9561 // times to get the original input.
9562 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9564 // First we need to zero all the dropped bytes.
9565 assert(NumEvenDrops <= 3 &&
9566 "No support for dropping even elements more than 3 times.");
9567 // We use the mask type to pick which bytes are preserved based on how many
9568 // elements are dropped.
9569 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9570 SDValue ByteClearMask =
9571 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9572 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9573 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9575 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9577 // Now pack things back together.
9578 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9579 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9580 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9581 for (int i = 1; i < NumEvenDrops; ++i) {
9582 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9583 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9589 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9590 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9591 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9592 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9594 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9595 MutableArrayRef<int> V1HalfBlendMask,
9596 MutableArrayRef<int> V2HalfBlendMask) {
9597 for (int i = 0; i < 8; ++i)
9598 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9599 V1HalfBlendMask[i] = HalfMask[i];
9601 } else if (HalfMask[i] >= 16) {
9602 V2HalfBlendMask[i] = HalfMask[i] - 16;
9603 HalfMask[i] = i + 8;
9606 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9607 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9609 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9611 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9612 MutableArrayRef<int> HiBlendMask) {
9614 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9615 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9617 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9618 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9619 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9620 [](int M) { return M >= 0 && M % 2 == 1; })) {
9621 // Use a mask to drop the high bytes.
9622 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9623 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9624 DAG.getConstant(0x00FF, MVT::v8i16));
9626 // This will be a single vector shuffle instead of a blend so nuke V2.
9627 V2 = DAG.getUNDEF(MVT::v8i16);
9629 // Squash the masks to point directly into V1.
9630 for (int &M : LoBlendMask)
9633 for (int &M : HiBlendMask)
9637 // Otherwise just unpack the low half of V into V1 and the high half into
9638 // V2 so that we can blend them as i16s.
9639 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9640 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9641 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9642 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9645 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9646 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9647 return std::make_pair(BlendedLo, BlendedHi);
9649 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9650 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9651 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9653 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9654 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9656 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9659 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9661 /// This routine breaks down the specific type of 128-bit shuffle and
9662 /// dispatches to the lowering routines accordingly.
9663 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9664 MVT VT, const X86Subtarget *Subtarget,
9665 SelectionDAG &DAG) {
9666 switch (VT.SimpleTy) {
9668 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9670 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9672 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9674 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9676 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9678 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9681 llvm_unreachable("Unimplemented!");
9685 /// \brief Helper function to test whether a shuffle mask could be
9686 /// simplified by widening the elements being shuffled.
9688 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9689 /// leaves it in an unspecified state.
9691 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9692 /// shuffle masks. The latter have the special property of a '-2' representing
9693 /// a zero-ed lane of a vector.
9694 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9695 SmallVectorImpl<int> &WidenedMask) {
9696 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9697 // If both elements are undef, its trivial.
9698 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9699 WidenedMask.push_back(SM_SentinelUndef);
9703 // Check for an undef mask and a mask value properly aligned to fit with
9704 // a pair of values. If we find such a case, use the non-undef mask's value.
9705 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9706 WidenedMask.push_back(Mask[i + 1] / 2);
9709 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9710 WidenedMask.push_back(Mask[i] / 2);
9714 // When zeroing, we need to spread the zeroing across both lanes to widen.
9715 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9716 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9717 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9718 WidenedMask.push_back(SM_SentinelZero);
9724 // Finally check if the two mask values are adjacent and aligned with
9726 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9727 WidenedMask.push_back(Mask[i] / 2);
9731 // Otherwise we can't safely widen the elements used in this shuffle.
9734 assert(WidenedMask.size() == Mask.size() / 2 &&
9735 "Incorrect size of mask after widening the elements!");
9740 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9742 /// This routine just extracts two subvectors, shuffles them independently, and
9743 /// then concatenates them back together. This should work effectively with all
9744 /// AVX vector shuffle types.
9745 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9746 SDValue V2, ArrayRef<int> Mask,
9747 SelectionDAG &DAG) {
9748 assert(VT.getSizeInBits() >= 256 &&
9749 "Only for 256-bit or wider vector shuffles!");
9750 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9751 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9753 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9754 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9756 int NumElements = VT.getVectorNumElements();
9757 int SplitNumElements = NumElements / 2;
9758 MVT ScalarVT = VT.getScalarType();
9759 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9761 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9762 DAG.getIntPtrConstant(0));
9763 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9764 DAG.getIntPtrConstant(SplitNumElements));
9765 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9766 DAG.getIntPtrConstant(0));
9767 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9768 DAG.getIntPtrConstant(SplitNumElements));
9770 // Now create two 4-way blends of these half-width vectors.
9771 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9772 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9773 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9774 for (int i = 0; i < SplitNumElements; ++i) {
9775 int M = HalfMask[i];
9776 if (M >= NumElements) {
9777 if (M >= NumElements + SplitNumElements)
9781 V2BlendMask.push_back(M - NumElements);
9782 V1BlendMask.push_back(-1);
9783 BlendMask.push_back(SplitNumElements + i);
9784 } else if (M >= 0) {
9785 if (M >= SplitNumElements)
9789 V2BlendMask.push_back(-1);
9790 V1BlendMask.push_back(M);
9791 BlendMask.push_back(i);
9793 V2BlendMask.push_back(-1);
9794 V1BlendMask.push_back(-1);
9795 BlendMask.push_back(-1);
9799 // Because the lowering happens after all combining takes place, we need to
9800 // manually combine these blend masks as much as possible so that we create
9801 // a minimal number of high-level vector shuffle nodes.
9803 // First try just blending the halves of V1 or V2.
9804 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9805 return DAG.getUNDEF(SplitVT);
9806 if (!UseLoV2 && !UseHiV2)
9807 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9808 if (!UseLoV1 && !UseHiV1)
9809 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9811 SDValue V1Blend, V2Blend;
9812 if (UseLoV1 && UseHiV1) {
9814 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9816 // We only use half of V1 so map the usage down into the final blend mask.
9817 V1Blend = UseLoV1 ? LoV1 : HiV1;
9818 for (int i = 0; i < SplitNumElements; ++i)
9819 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9820 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9822 if (UseLoV2 && UseHiV2) {
9824 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9826 // We only use half of V2 so map the usage down into the final blend mask.
9827 V2Blend = UseLoV2 ? LoV2 : HiV2;
9828 for (int i = 0; i < SplitNumElements; ++i)
9829 if (BlendMask[i] >= SplitNumElements)
9830 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9832 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9834 SDValue Lo = HalfBlend(LoMask);
9835 SDValue Hi = HalfBlend(HiMask);
9836 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9839 /// \brief Either split a vector in halves or decompose the shuffles and the
9842 /// This is provided as a good fallback for many lowerings of non-single-input
9843 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9844 /// between splitting the shuffle into 128-bit components and stitching those
9845 /// back together vs. extracting the single-input shuffles and blending those
9847 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9848 SDValue V2, ArrayRef<int> Mask,
9849 SelectionDAG &DAG) {
9850 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9851 "lower single-input shuffles as it "
9852 "could then recurse on itself.");
9853 int Size = Mask.size();
9855 // If this can be modeled as a broadcast of two elements followed by a blend,
9856 // prefer that lowering. This is especially important because broadcasts can
9857 // often fold with memory operands.
9858 auto DoBothBroadcast = [&] {
9859 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9862 if (V2BroadcastIdx == -1)
9863 V2BroadcastIdx = M - Size;
9864 else if (M - Size != V2BroadcastIdx)
9866 } else if (M >= 0) {
9867 if (V1BroadcastIdx == -1)
9869 else if (M != V1BroadcastIdx)
9874 if (DoBothBroadcast())
9875 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9878 // If the inputs all stem from a single 128-bit lane of each input, then we
9879 // split them rather than blending because the split will decompose to
9880 // unusually few instructions.
9881 int LaneCount = VT.getSizeInBits() / 128;
9882 int LaneSize = Size / LaneCount;
9883 SmallBitVector LaneInputs[2];
9884 LaneInputs[0].resize(LaneCount, false);
9885 LaneInputs[1].resize(LaneCount, false);
9886 for (int i = 0; i < Size; ++i)
9888 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9889 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9890 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9892 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9893 // that the decomposed single-input shuffles don't end up here.
9894 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9897 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9898 /// a permutation and blend of those lanes.
9900 /// This essentially blends the out-of-lane inputs to each lane into the lane
9901 /// from a permuted copy of the vector. This lowering strategy results in four
9902 /// instructions in the worst case for a single-input cross lane shuffle which
9903 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9904 /// of. Special cases for each particular shuffle pattern should be handled
9905 /// prior to trying this lowering.
9906 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9907 SDValue V1, SDValue V2,
9909 SelectionDAG &DAG) {
9910 // FIXME: This should probably be generalized for 512-bit vectors as well.
9911 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9912 int LaneSize = Mask.size() / 2;
9914 // If there are only inputs from one 128-bit lane, splitting will in fact be
9915 // less expensive. The flags track wether the given lane contains an element
9916 // that crosses to another lane.
9917 bool LaneCrossing[2] = {false, false};
9918 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9919 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9920 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9921 if (!LaneCrossing[0] || !LaneCrossing[1])
9922 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9924 if (isSingleInputShuffleMask(Mask)) {
9925 SmallVector<int, 32> FlippedBlendMask;
9926 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9927 FlippedBlendMask.push_back(
9928 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9930 : Mask[i] % LaneSize +
9931 (i / LaneSize) * LaneSize + Size));
9933 // Flip the vector, and blend the results which should now be in-lane. The
9934 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9935 // 5 for the high source. The value 3 selects the high half of source 2 and
9936 // the value 2 selects the low half of source 2. We only use source 2 to
9937 // allow folding it into a memory operand.
9938 unsigned PERMMask = 3 | 2 << 4;
9939 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9940 V1, DAG.getConstant(PERMMask, MVT::i8));
9941 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9944 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9945 // will be handled by the above logic and a blend of the results, much like
9946 // other patterns in AVX.
9947 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9950 /// \brief Handle lowering 2-lane 128-bit shuffles.
9951 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9952 SDValue V2, ArrayRef<int> Mask,
9953 const X86Subtarget *Subtarget,
9954 SelectionDAG &DAG) {
9955 // Blends are faster and handle all the non-lane-crossing cases.
9956 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9960 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9961 VT.getVectorNumElements() / 2);
9962 // Check for patterns which can be matched with a single insert of a 128-bit
9964 if (isShuffleEquivalent(Mask, 0, 1, 0, 1) ||
9965 isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
9966 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9967 DAG.getIntPtrConstant(0));
9968 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9969 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
9970 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9972 if (isShuffleEquivalent(Mask, 0, 1, 6, 7)) {
9973 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9974 DAG.getIntPtrConstant(0));
9975 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
9976 DAG.getIntPtrConstant(2));
9977 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9980 // Otherwise form a 128-bit permutation.
9981 // FIXME: Detect zero-vector inputs and use the VPERM2X128 to zero that half.
9982 unsigned PermMask = Mask[0] / 2 | (Mask[2] / 2) << 4;
9983 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9984 DAG.getConstant(PermMask, MVT::i8));
9987 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
9988 /// shuffling each lane.
9990 /// This will only succeed when the result of fixing the 128-bit lanes results
9991 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
9992 /// each 128-bit lanes. This handles many cases where we can quickly blend away
9993 /// the lane crosses early and then use simpler shuffles within each lane.
9995 /// FIXME: It might be worthwhile at some point to support this without
9996 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
9997 /// in x86 only floating point has interesting non-repeating shuffles, and even
9998 /// those are still *marginally* more expensive.
9999 static SDValue lowerVectorShuffleByMerging128BitLanes(
10000 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10001 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10002 assert(!isSingleInputShuffleMask(Mask) &&
10003 "This is only useful with multiple inputs.");
10005 int Size = Mask.size();
10006 int LaneSize = 128 / VT.getScalarSizeInBits();
10007 int NumLanes = Size / LaneSize;
10008 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10010 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10011 // check whether the in-128-bit lane shuffles share a repeating pattern.
10012 SmallVector<int, 4> Lanes;
10013 Lanes.resize(NumLanes, -1);
10014 SmallVector<int, 4> InLaneMask;
10015 InLaneMask.resize(LaneSize, -1);
10016 for (int i = 0; i < Size; ++i) {
10020 int j = i / LaneSize;
10022 if (Lanes[j] < 0) {
10023 // First entry we've seen for this lane.
10024 Lanes[j] = Mask[i] / LaneSize;
10025 } else if (Lanes[j] != Mask[i] / LaneSize) {
10026 // This doesn't match the lane selected previously!
10030 // Check that within each lane we have a consistent shuffle mask.
10031 int k = i % LaneSize;
10032 if (InLaneMask[k] < 0) {
10033 InLaneMask[k] = Mask[i] % LaneSize;
10034 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10035 // This doesn't fit a repeating in-lane mask.
10040 // First shuffle the lanes into place.
10041 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10042 VT.getSizeInBits() / 64);
10043 SmallVector<int, 8> LaneMask;
10044 LaneMask.resize(NumLanes * 2, -1);
10045 for (int i = 0; i < NumLanes; ++i)
10046 if (Lanes[i] >= 0) {
10047 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10048 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10051 V1 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V1);
10052 V2 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V2);
10053 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10055 // Cast it back to the type we actually want.
10056 LaneShuffle = DAG.getNode(ISD::BITCAST, DL, VT, LaneShuffle);
10058 // Now do a simple shuffle that isn't lane crossing.
10059 SmallVector<int, 8> NewMask;
10060 NewMask.resize(Size, -1);
10061 for (int i = 0; i < Size; ++i)
10063 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10064 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10065 "Must not introduce lane crosses at this point!");
10067 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10070 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10073 /// This returns true if the elements from a particular input are already in the
10074 /// slot required by the given mask and require no permutation.
10075 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10076 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10077 int Size = Mask.size();
10078 for (int i = 0; i < Size; ++i)
10079 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10085 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10087 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10088 /// isn't available.
10089 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10090 const X86Subtarget *Subtarget,
10091 SelectionDAG &DAG) {
10093 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10094 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10095 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10096 ArrayRef<int> Mask = SVOp->getMask();
10097 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10099 SmallVector<int, 4> WidenedMask;
10100 if (canWidenShuffleElements(Mask, WidenedMask))
10101 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10104 if (isSingleInputShuffleMask(Mask)) {
10105 // Check for being able to broadcast a single element.
10106 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
10107 Mask, Subtarget, DAG))
10110 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10111 // Non-half-crossing single input shuffles can be lowerid with an
10112 // interleaved permutation.
10113 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10114 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10115 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10116 DAG.getConstant(VPERMILPMask, MVT::i8));
10119 // With AVX2 we have direct support for this permutation.
10120 if (Subtarget->hasAVX2())
10121 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10122 getV4X86ShuffleImm8ForMask(Mask, DAG));
10124 // Otherwise, fall back.
10125 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10129 // X86 has dedicated unpack instructions that can handle specific blend
10130 // operations: UNPCKH and UNPCKL.
10131 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10132 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10133 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10134 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10136 // If we have a single input to the zero element, insert that into V1 if we
10137 // can do so cheaply.
10138 int NumV2Elements =
10139 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
10140 if (NumV2Elements == 1 && Mask[0] >= 4)
10141 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10142 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
10145 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10149 // Check if the blend happens to exactly fit that of SHUFPD.
10150 if ((Mask[0] == -1 || Mask[0] < 2) &&
10151 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
10152 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
10153 (Mask[3] == -1 || Mask[3] >= 6)) {
10154 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
10155 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
10156 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
10157 DAG.getConstant(SHUFPDMask, MVT::i8));
10159 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
10160 (Mask[1] == -1 || Mask[1] < 2) &&
10161 (Mask[2] == -1 || Mask[2] >= 6) &&
10162 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
10163 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
10164 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
10165 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
10166 DAG.getConstant(SHUFPDMask, MVT::i8));
10169 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10170 // shuffle. However, if we have AVX2 and either inputs are already in place,
10171 // we will be able to shuffle even across lanes the other input in a single
10172 // instruction so skip this pattern.
10173 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10174 isShuffleMaskInputInPlace(1, Mask))))
10175 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10176 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10179 // If we have AVX2 then we always want to lower with a blend because an v4 we
10180 // can fully permute the elements.
10181 if (Subtarget->hasAVX2())
10182 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10185 // Otherwise fall back on generic lowering.
10186 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10189 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10191 /// This routine is only called when we have AVX2 and thus a reasonable
10192 /// instruction set for v4i64 shuffling..
10193 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10194 const X86Subtarget *Subtarget,
10195 SelectionDAG &DAG) {
10197 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10198 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10199 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10200 ArrayRef<int> Mask = SVOp->getMask();
10201 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10202 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10204 SmallVector<int, 4> WidenedMask;
10205 if (canWidenShuffleElements(Mask, WidenedMask))
10206 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10209 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10213 // Check for being able to broadcast a single element.
10214 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
10215 Mask, Subtarget, DAG))
10218 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10219 // use lower latency instructions that will operate on both 128-bit lanes.
10220 SmallVector<int, 2> RepeatedMask;
10221 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10222 if (isSingleInputShuffleMask(Mask)) {
10223 int PSHUFDMask[] = {-1, -1, -1, -1};
10224 for (int i = 0; i < 2; ++i)
10225 if (RepeatedMask[i] >= 0) {
10226 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10227 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10229 return DAG.getNode(
10230 ISD::BITCAST, DL, MVT::v4i64,
10231 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10232 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
10233 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
10236 // Use dedicated unpack instructions for masks that match their pattern.
10237 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10238 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10239 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10240 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10243 // AVX2 provides a direct instruction for permuting a single input across
10245 if (isSingleInputShuffleMask(Mask))
10246 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10247 getV4X86ShuffleImm8ForMask(Mask, DAG));
10249 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10250 // shuffle. However, if we have AVX2 and either inputs are already in place,
10251 // we will be able to shuffle even across lanes the other input in a single
10252 // instruction so skip this pattern.
10253 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10254 isShuffleMaskInputInPlace(1, Mask))))
10255 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10256 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10259 // Otherwise fall back on generic blend lowering.
10260 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10264 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10266 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10267 /// isn't available.
10268 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10269 const X86Subtarget *Subtarget,
10270 SelectionDAG &DAG) {
10272 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10273 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10274 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10275 ArrayRef<int> Mask = SVOp->getMask();
10276 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10278 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10282 // Check for being able to broadcast a single element.
10283 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
10284 Mask, Subtarget, DAG))
10287 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10288 // options to efficiently lower the shuffle.
10289 SmallVector<int, 4> RepeatedMask;
10290 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10291 assert(RepeatedMask.size() == 4 &&
10292 "Repeated masks must be half the mask width!");
10293 if (isSingleInputShuffleMask(Mask))
10294 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10295 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10297 // Use dedicated unpack instructions for masks that match their pattern.
10298 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10299 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10300 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10301 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10303 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10304 // have already handled any direct blends. We also need to squash the
10305 // repeated mask into a simulated v4f32 mask.
10306 for (int i = 0; i < 4; ++i)
10307 if (RepeatedMask[i] >= 8)
10308 RepeatedMask[i] -= 4;
10309 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10312 // If we have a single input shuffle with different shuffle patterns in the
10313 // two 128-bit lanes use the variable mask to VPERMILPS.
10314 if (isSingleInputShuffleMask(Mask)) {
10315 SDValue VPermMask[8];
10316 for (int i = 0; i < 8; ++i)
10317 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10318 : DAG.getConstant(Mask[i], MVT::i32);
10319 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10320 return DAG.getNode(
10321 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10322 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10324 if (Subtarget->hasAVX2())
10325 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
10326 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
10327 DAG.getNode(ISD::BUILD_VECTOR, DL,
10328 MVT::v8i32, VPermMask)),
10331 // Otherwise, fall back.
10332 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10336 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10338 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10339 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10342 // If we have AVX2 then we always want to lower with a blend because at v8 we
10343 // can fully permute the elements.
10344 if (Subtarget->hasAVX2())
10345 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10348 // Otherwise fall back on generic lowering.
10349 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10352 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10354 /// This routine is only called when we have AVX2 and thus a reasonable
10355 /// instruction set for v8i32 shuffling..
10356 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10357 const X86Subtarget *Subtarget,
10358 SelectionDAG &DAG) {
10360 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10361 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10362 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10363 ArrayRef<int> Mask = SVOp->getMask();
10364 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10365 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10367 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10371 // Check for being able to broadcast a single element.
10372 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
10373 Mask, Subtarget, DAG))
10376 // If the shuffle mask is repeated in each 128-bit lane we can use more
10377 // efficient instructions that mirror the shuffles across the two 128-bit
10379 SmallVector<int, 4> RepeatedMask;
10380 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10381 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10382 if (isSingleInputShuffleMask(Mask))
10383 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10384 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10386 // Use dedicated unpack instructions for masks that match their pattern.
10387 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10388 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10389 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10390 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10393 // If the shuffle patterns aren't repeated but it is a single input, directly
10394 // generate a cross-lane VPERMD instruction.
10395 if (isSingleInputShuffleMask(Mask)) {
10396 SDValue VPermMask[8];
10397 for (int i = 0; i < 8; ++i)
10398 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10399 : DAG.getConstant(Mask[i], MVT::i32);
10400 return DAG.getNode(
10401 X86ISD::VPERMV, DL, MVT::v8i32,
10402 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10405 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10407 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10408 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10411 // Otherwise fall back on generic blend lowering.
10412 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10416 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10418 /// This routine is only called when we have AVX2 and thus a reasonable
10419 /// instruction set for v16i16 shuffling..
10420 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10421 const X86Subtarget *Subtarget,
10422 SelectionDAG &DAG) {
10424 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10425 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10426 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10427 ArrayRef<int> Mask = SVOp->getMask();
10428 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10429 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10431 // Check for being able to broadcast a single element.
10432 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
10433 Mask, Subtarget, DAG))
10436 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10440 // Use dedicated unpack instructions for masks that match their pattern.
10441 if (isShuffleEquivalent(Mask,
10442 // First 128-bit lane:
10443 0, 16, 1, 17, 2, 18, 3, 19,
10444 // Second 128-bit lane:
10445 8, 24, 9, 25, 10, 26, 11, 27))
10446 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10447 if (isShuffleEquivalent(Mask,
10448 // First 128-bit lane:
10449 4, 20, 5, 21, 6, 22, 7, 23,
10450 // Second 128-bit lane:
10451 12, 28, 13, 29, 14, 30, 15, 31))
10452 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10454 if (isSingleInputShuffleMask(Mask)) {
10455 // There are no generalized cross-lane shuffle operations available on i16
10457 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10458 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10461 SDValue PSHUFBMask[32];
10462 for (int i = 0; i < 16; ++i) {
10463 if (Mask[i] == -1) {
10464 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10468 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10469 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10470 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
10471 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
10473 return DAG.getNode(
10474 ISD::BITCAST, DL, MVT::v16i16,
10476 X86ISD::PSHUFB, DL, MVT::v32i8,
10477 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
10478 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
10481 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10483 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10484 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10487 // Otherwise fall back on generic lowering.
10488 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10491 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10493 /// This routine is only called when we have AVX2 and thus a reasonable
10494 /// instruction set for v32i8 shuffling..
10495 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10496 const X86Subtarget *Subtarget,
10497 SelectionDAG &DAG) {
10499 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10500 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10501 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10502 ArrayRef<int> Mask = SVOp->getMask();
10503 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10504 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10506 // Check for being able to broadcast a single element.
10507 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
10508 Mask, Subtarget, DAG))
10511 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10515 // Use dedicated unpack instructions for masks that match their pattern.
10516 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10518 if (isShuffleEquivalent(
10520 // First 128-bit lane:
10521 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10522 // Second 128-bit lane:
10523 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
10524 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10525 if (isShuffleEquivalent(
10527 // First 128-bit lane:
10528 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10529 // Second 128-bit lane:
10530 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
10531 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10533 if (isSingleInputShuffleMask(Mask)) {
10534 // There are no generalized cross-lane shuffle operations available on i8
10536 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10537 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10540 SDValue PSHUFBMask[32];
10541 for (int i = 0; i < 32; ++i)
10544 ? DAG.getUNDEF(MVT::i8)
10545 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
10547 return DAG.getNode(
10548 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10549 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10552 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10554 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10555 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10558 // Otherwise fall back on generic lowering.
10559 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10562 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10564 /// This routine either breaks down the specific type of a 256-bit x86 vector
10565 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10566 /// together based on the available instructions.
10567 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10568 MVT VT, const X86Subtarget *Subtarget,
10569 SelectionDAG &DAG) {
10571 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10572 ArrayRef<int> Mask = SVOp->getMask();
10574 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10575 // check for those subtargets here and avoid much of the subtarget querying in
10576 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10577 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10578 // floating point types there eventually, just immediately cast everything to
10579 // a float and operate entirely in that domain.
10580 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10581 int ElementBits = VT.getScalarSizeInBits();
10582 if (ElementBits < 32)
10583 // No floating point type available, decompose into 128-bit vectors.
10584 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10586 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10587 VT.getVectorNumElements());
10588 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10589 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10590 return DAG.getNode(ISD::BITCAST, DL, VT,
10591 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10594 switch (VT.SimpleTy) {
10596 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10598 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10600 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10602 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10604 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10606 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10609 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10613 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10614 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10615 const X86Subtarget *Subtarget,
10616 SelectionDAG &DAG) {
10618 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10619 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10620 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10621 ArrayRef<int> Mask = SVOp->getMask();
10622 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10624 // FIXME: Implement direct support for this type!
10625 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10628 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10629 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10630 const X86Subtarget *Subtarget,
10631 SelectionDAG &DAG) {
10633 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10634 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10635 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10636 ArrayRef<int> Mask = SVOp->getMask();
10637 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10639 // FIXME: Implement direct support for this type!
10640 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10643 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10644 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10645 const X86Subtarget *Subtarget,
10646 SelectionDAG &DAG) {
10648 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10649 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10650 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10651 ArrayRef<int> Mask = SVOp->getMask();
10652 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10654 // FIXME: Implement direct support for this type!
10655 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10658 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10659 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10660 const X86Subtarget *Subtarget,
10661 SelectionDAG &DAG) {
10663 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10664 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10665 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10666 ArrayRef<int> Mask = SVOp->getMask();
10667 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10669 // FIXME: Implement direct support for this type!
10670 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10673 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10674 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10675 const X86Subtarget *Subtarget,
10676 SelectionDAG &DAG) {
10678 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10679 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10680 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10681 ArrayRef<int> Mask = SVOp->getMask();
10682 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10683 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10685 // FIXME: Implement direct support for this type!
10686 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10689 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10690 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10691 const X86Subtarget *Subtarget,
10692 SelectionDAG &DAG) {
10694 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10695 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10696 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10697 ArrayRef<int> Mask = SVOp->getMask();
10698 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10699 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10701 // FIXME: Implement direct support for this type!
10702 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10705 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10707 /// This routine either breaks down the specific type of a 512-bit x86 vector
10708 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10709 /// together based on the available instructions.
10710 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10711 MVT VT, const X86Subtarget *Subtarget,
10712 SelectionDAG &DAG) {
10714 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10715 ArrayRef<int> Mask = SVOp->getMask();
10716 assert(Subtarget->hasAVX512() &&
10717 "Cannot lower 512-bit vectors w/ basic ISA!");
10719 // Check for being able to broadcast a single element.
10720 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(VT.SimpleTy, DL, V1,
10721 Mask, Subtarget, DAG))
10724 // Dispatch to each element type for lowering. If we don't have supprot for
10725 // specific element type shuffles at 512 bits, immediately split them and
10726 // lower them. Each lowering routine of a given type is allowed to assume that
10727 // the requisite ISA extensions for that element type are available.
10728 switch (VT.SimpleTy) {
10730 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10732 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10734 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10736 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10738 if (Subtarget->hasBWI())
10739 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10742 if (Subtarget->hasBWI())
10743 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10747 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10750 // Otherwise fall back on splitting.
10751 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10754 /// \brief Top-level lowering for x86 vector shuffles.
10756 /// This handles decomposition, canonicalization, and lowering of all x86
10757 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10758 /// above in helper routines. The canonicalization attempts to widen shuffles
10759 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10760 /// s.t. only one of the two inputs needs to be tested, etc.
10761 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10762 SelectionDAG &DAG) {
10763 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10764 ArrayRef<int> Mask = SVOp->getMask();
10765 SDValue V1 = Op.getOperand(0);
10766 SDValue V2 = Op.getOperand(1);
10767 MVT VT = Op.getSimpleValueType();
10768 int NumElements = VT.getVectorNumElements();
10771 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10773 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10774 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10775 if (V1IsUndef && V2IsUndef)
10776 return DAG.getUNDEF(VT);
10778 // When we create a shuffle node we put the UNDEF node to second operand,
10779 // but in some cases the first operand may be transformed to UNDEF.
10780 // In this case we should just commute the node.
10782 return DAG.getCommutedVectorShuffle(*SVOp);
10784 // Check for non-undef masks pointing at an undef vector and make the masks
10785 // undef as well. This makes it easier to match the shuffle based solely on
10789 if (M >= NumElements) {
10790 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10791 for (int &M : NewMask)
10792 if (M >= NumElements)
10794 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10797 // Try to collapse shuffles into using a vector type with fewer elements but
10798 // wider element types. We cap this to not form integers or floating point
10799 // elements wider than 64 bits, but it might be interesting to form i128
10800 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10801 SmallVector<int, 16> WidenedMask;
10802 if (VT.getScalarSizeInBits() < 64 &&
10803 canWidenShuffleElements(Mask, WidenedMask)) {
10804 MVT NewEltVT = VT.isFloatingPoint()
10805 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10806 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10807 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10808 // Make sure that the new vector type is legal. For example, v2f64 isn't
10810 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10811 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10812 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10813 return DAG.getNode(ISD::BITCAST, dl, VT,
10814 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10818 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10819 for (int M : SVOp->getMask())
10821 ++NumUndefElements;
10822 else if (M < NumElements)
10827 // Commute the shuffle as needed such that more elements come from V1 than
10828 // V2. This allows us to match the shuffle pattern strictly on how many
10829 // elements come from V1 without handling the symmetric cases.
10830 if (NumV2Elements > NumV1Elements)
10831 return DAG.getCommutedVectorShuffle(*SVOp);
10833 // When the number of V1 and V2 elements are the same, try to minimize the
10834 // number of uses of V2 in the low half of the vector. When that is tied,
10835 // ensure that the sum of indices for V1 is equal to or lower than the sum
10836 // indices for V2. When those are equal, try to ensure that the number of odd
10837 // indices for V1 is lower than the number of odd indices for V2.
10838 if (NumV1Elements == NumV2Elements) {
10839 int LowV1Elements = 0, LowV2Elements = 0;
10840 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10841 if (M >= NumElements)
10845 if (LowV2Elements > LowV1Elements) {
10846 return DAG.getCommutedVectorShuffle(*SVOp);
10847 } else if (LowV2Elements == LowV1Elements) {
10848 int SumV1Indices = 0, SumV2Indices = 0;
10849 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10850 if (SVOp->getMask()[i] >= NumElements)
10852 else if (SVOp->getMask()[i] >= 0)
10854 if (SumV2Indices < SumV1Indices) {
10855 return DAG.getCommutedVectorShuffle(*SVOp);
10856 } else if (SumV2Indices == SumV1Indices) {
10857 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10858 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10859 if (SVOp->getMask()[i] >= NumElements)
10860 NumV2OddIndices += i % 2;
10861 else if (SVOp->getMask()[i] >= 0)
10862 NumV1OddIndices += i % 2;
10863 if (NumV2OddIndices < NumV1OddIndices)
10864 return DAG.getCommutedVectorShuffle(*SVOp);
10869 // For each vector width, delegate to a specialized lowering routine.
10870 if (VT.getSizeInBits() == 128)
10871 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10873 if (VT.getSizeInBits() == 256)
10874 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10876 // Force AVX-512 vectors to be scalarized for now.
10877 // FIXME: Implement AVX-512 support!
10878 if (VT.getSizeInBits() == 512)
10879 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10881 llvm_unreachable("Unimplemented!");
10885 //===----------------------------------------------------------------------===//
10886 // Legacy vector shuffle lowering
10888 // This code is the legacy code handling vector shuffles until the above
10889 // replaces its functionality and performance.
10890 //===----------------------------------------------------------------------===//
10892 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10893 bool hasInt256, unsigned *MaskOut = nullptr) {
10894 MVT EltVT = VT.getVectorElementType();
10896 // There is no blend with immediate in AVX-512.
10897 if (VT.is512BitVector())
10900 if (!hasSSE41 || EltVT == MVT::i8)
10902 if (!hasInt256 && VT == MVT::v16i16)
10905 unsigned MaskValue = 0;
10906 unsigned NumElems = VT.getVectorNumElements();
10907 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10908 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10909 unsigned NumElemsInLane = NumElems / NumLanes;
10911 // Blend for v16i16 should be symetric for the both lanes.
10912 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10914 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10915 int EltIdx = MaskVals[i];
10917 if ((EltIdx < 0 || EltIdx == (int)i) &&
10918 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10921 if (((unsigned)EltIdx == (i + NumElems)) &&
10922 (SndLaneEltIdx < 0 ||
10923 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10924 MaskValue |= (1 << i);
10930 *MaskOut = MaskValue;
10934 // Try to lower a shuffle node into a simple blend instruction.
10935 // This function assumes isBlendMask returns true for this
10936 // SuffleVectorSDNode
10937 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
10938 unsigned MaskValue,
10939 const X86Subtarget *Subtarget,
10940 SelectionDAG &DAG) {
10941 MVT VT = SVOp->getSimpleValueType(0);
10942 MVT EltVT = VT.getVectorElementType();
10943 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
10944 Subtarget->hasInt256() && "Trying to lower a "
10945 "VECTOR_SHUFFLE to a Blend but "
10946 "with the wrong mask"));
10947 SDValue V1 = SVOp->getOperand(0);
10948 SDValue V2 = SVOp->getOperand(1);
10950 unsigned NumElems = VT.getVectorNumElements();
10952 // Convert i32 vectors to floating point if it is not AVX2.
10953 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10955 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10956 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10958 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
10959 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
10962 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
10963 DAG.getConstant(MaskValue, MVT::i32));
10964 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10967 /// In vector type \p VT, return true if the element at index \p InputIdx
10968 /// falls on a different 128-bit lane than \p OutputIdx.
10969 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
10970 unsigned OutputIdx) {
10971 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
10972 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
10975 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
10976 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
10977 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
10978 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
10980 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
10981 SelectionDAG &DAG) {
10982 MVT VT = V1.getSimpleValueType();
10983 assert(VT.is128BitVector() || VT.is256BitVector());
10985 MVT EltVT = VT.getVectorElementType();
10986 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
10987 unsigned NumElts = VT.getVectorNumElements();
10989 SmallVector<SDValue, 32> PshufbMask;
10990 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
10991 int InputIdx = MaskVals[OutputIdx];
10992 unsigned InputByteIdx;
10994 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
10995 InputByteIdx = 0x80;
10997 // Cross lane is not allowed.
10998 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
11000 InputByteIdx = InputIdx * EltSizeInBytes;
11001 // Index is an byte offset within the 128-bit lane.
11002 InputByteIdx &= 0xf;
11005 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
11006 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
11007 if (InputByteIdx != 0x80)
11012 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
11014 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
11015 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
11016 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
11019 // v8i16 shuffles - Prefer shuffles in the following order:
11020 // 1. [all] pshuflw, pshufhw, optional move
11021 // 2. [ssse3] 1 x pshufb
11022 // 3. [ssse3] 2 x pshufb + 1 x por
11023 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
11025 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
11026 SelectionDAG &DAG) {
11027 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11028 SDValue V1 = SVOp->getOperand(0);
11029 SDValue V2 = SVOp->getOperand(1);
11031 SmallVector<int, 8> MaskVals;
11033 // Determine if more than 1 of the words in each of the low and high quadwords
11034 // of the result come from the same quadword of one of the two inputs. Undef
11035 // mask values count as coming from any quadword, for better codegen.
11037 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
11038 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
11039 unsigned LoQuad[] = { 0, 0, 0, 0 };
11040 unsigned HiQuad[] = { 0, 0, 0, 0 };
11041 // Indices of quads used.
11042 std::bitset<4> InputQuads;
11043 for (unsigned i = 0; i < 8; ++i) {
11044 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
11045 int EltIdx = SVOp->getMaskElt(i);
11046 MaskVals.push_back(EltIdx);
11054 ++Quad[EltIdx / 4];
11055 InputQuads.set(EltIdx / 4);
11058 int BestLoQuad = -1;
11059 unsigned MaxQuad = 1;
11060 for (unsigned i = 0; i < 4; ++i) {
11061 if (LoQuad[i] > MaxQuad) {
11063 MaxQuad = LoQuad[i];
11067 int BestHiQuad = -1;
11069 for (unsigned i = 0; i < 4; ++i) {
11070 if (HiQuad[i] > MaxQuad) {
11072 MaxQuad = HiQuad[i];
11076 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
11077 // of the two input vectors, shuffle them into one input vector so only a
11078 // single pshufb instruction is necessary. If there are more than 2 input
11079 // quads, disable the next transformation since it does not help SSSE3.
11080 bool V1Used = InputQuads[0] || InputQuads[1];
11081 bool V2Used = InputQuads[2] || InputQuads[3];
11082 if (Subtarget->hasSSSE3()) {
11083 if (InputQuads.count() == 2 && V1Used && V2Used) {
11084 BestLoQuad = InputQuads[0] ? 0 : 1;
11085 BestHiQuad = InputQuads[2] ? 2 : 3;
11087 if (InputQuads.count() > 2) {
11093 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
11094 // the shuffle mask. If a quad is scored as -1, that means that it contains
11095 // words from all 4 input quadwords.
11097 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
11099 BestLoQuad < 0 ? 0 : BestLoQuad,
11100 BestHiQuad < 0 ? 1 : BestHiQuad
11102 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
11103 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
11104 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
11105 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
11107 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
11108 // source words for the shuffle, to aid later transformations.
11109 bool AllWordsInNewV = true;
11110 bool InOrder[2] = { true, true };
11111 for (unsigned i = 0; i != 8; ++i) {
11112 int idx = MaskVals[i];
11114 InOrder[i/4] = false;
11115 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
11117 AllWordsInNewV = false;
11121 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
11122 if (AllWordsInNewV) {
11123 for (int i = 0; i != 8; ++i) {
11124 int idx = MaskVals[i];
11127 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
11128 if ((idx != i) && idx < 4)
11130 if ((idx != i) && idx > 3)
11139 // If we've eliminated the use of V2, and the new mask is a pshuflw or
11140 // pshufhw, that's as cheap as it gets. Return the new shuffle.
11141 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
11142 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
11143 unsigned TargetMask = 0;
11144 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
11145 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
11146 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11147 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
11148 getShufflePSHUFLWImmediate(SVOp);
11149 V1 = NewV.getOperand(0);
11150 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
11154 // Promote splats to a larger type which usually leads to more efficient code.
11155 // FIXME: Is this true if pshufb is available?
11156 if (SVOp->isSplat())
11157 return PromoteSplat(SVOp, DAG);
11159 // If we have SSSE3, and all words of the result are from 1 input vector,
11160 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
11161 // is present, fall back to case 4.
11162 if (Subtarget->hasSSSE3()) {
11163 SmallVector<SDValue,16> pshufbMask;
11165 // If we have elements from both input vectors, set the high bit of the
11166 // shuffle mask element to zero out elements that come from V2 in the V1
11167 // mask, and elements that come from V1 in the V2 mask, so that the two
11168 // results can be OR'd together.
11169 bool TwoInputs = V1Used && V2Used;
11170 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
11172 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11174 // Calculate the shuffle mask for the second input, shuffle it, and
11175 // OR it with the first shuffled input.
11176 CommuteVectorShuffleMask(MaskVals, 8);
11177 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
11178 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11179 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11182 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
11183 // and update MaskVals with new element order.
11184 std::bitset<8> InOrder;
11185 if (BestLoQuad >= 0) {
11186 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
11187 for (int i = 0; i != 4; ++i) {
11188 int idx = MaskVals[i];
11191 } else if ((idx / 4) == BestLoQuad) {
11192 MaskV[i] = idx & 3;
11196 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11199 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11200 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11201 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
11202 NewV.getOperand(0),
11203 getShufflePSHUFLWImmediate(SVOp), DAG);
11207 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
11208 // and update MaskVals with the new element order.
11209 if (BestHiQuad >= 0) {
11210 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
11211 for (unsigned i = 4; i != 8; ++i) {
11212 int idx = MaskVals[i];
11215 } else if ((idx / 4) == BestHiQuad) {
11216 MaskV[i] = (idx & 3) + 4;
11220 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11223 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11224 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11225 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
11226 NewV.getOperand(0),
11227 getShufflePSHUFHWImmediate(SVOp), DAG);
11231 // In case BestHi & BestLo were both -1, which means each quadword has a word
11232 // from each of the four input quadwords, calculate the InOrder bitvector now
11233 // before falling through to the insert/extract cleanup.
11234 if (BestLoQuad == -1 && BestHiQuad == -1) {
11236 for (int i = 0; i != 8; ++i)
11237 if (MaskVals[i] < 0 || MaskVals[i] == i)
11241 // The other elements are put in the right place using pextrw and pinsrw.
11242 for (unsigned i = 0; i != 8; ++i) {
11245 int EltIdx = MaskVals[i];
11248 SDValue ExtOp = (EltIdx < 8) ?
11249 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
11250 DAG.getIntPtrConstant(EltIdx)) :
11251 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
11252 DAG.getIntPtrConstant(EltIdx - 8));
11253 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
11254 DAG.getIntPtrConstant(i));
11259 /// \brief v16i16 shuffles
11261 /// FIXME: We only support generation of a single pshufb currently. We can
11262 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
11263 /// well (e.g 2 x pshufb + 1 x por).
11265 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
11266 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11267 SDValue V1 = SVOp->getOperand(0);
11268 SDValue V2 = SVOp->getOperand(1);
11271 if (V2.getOpcode() != ISD::UNDEF)
11274 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11275 return getPSHUFB(MaskVals, V1, dl, DAG);
11278 // v16i8 shuffles - Prefer shuffles in the following order:
11279 // 1. [ssse3] 1 x pshufb
11280 // 2. [ssse3] 2 x pshufb + 1 x por
11281 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
11282 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
11283 const X86Subtarget* Subtarget,
11284 SelectionDAG &DAG) {
11285 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11286 SDValue V1 = SVOp->getOperand(0);
11287 SDValue V2 = SVOp->getOperand(1);
11289 ArrayRef<int> MaskVals = SVOp->getMask();
11291 // Promote splats to a larger type which usually leads to more efficient code.
11292 // FIXME: Is this true if pshufb is available?
11293 if (SVOp->isSplat())
11294 return PromoteSplat(SVOp, DAG);
11296 // If we have SSSE3, case 1 is generated when all result bytes come from
11297 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
11298 // present, fall back to case 3.
11300 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
11301 if (Subtarget->hasSSSE3()) {
11302 SmallVector<SDValue,16> pshufbMask;
11304 // If all result elements are from one input vector, then only translate
11305 // undef mask values to 0x80 (zero out result) in the pshufb mask.
11307 // Otherwise, we have elements from both input vectors, and must zero out
11308 // elements that come from V2 in the first mask, and V1 in the second mask
11309 // so that we can OR them together.
11310 for (unsigned i = 0; i != 16; ++i) {
11311 int EltIdx = MaskVals[i];
11312 if (EltIdx < 0 || EltIdx >= 16)
11314 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11316 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
11317 DAG.getNode(ISD::BUILD_VECTOR, dl,
11318 MVT::v16i8, pshufbMask));
11320 // As PSHUFB will zero elements with negative indices, it's safe to ignore
11321 // the 2nd operand if it's undefined or zero.
11322 if (V2.getOpcode() == ISD::UNDEF ||
11323 ISD::isBuildVectorAllZeros(V2.getNode()))
11326 // Calculate the shuffle mask for the second input, shuffle it, and
11327 // OR it with the first shuffled input.
11328 pshufbMask.clear();
11329 for (unsigned i = 0; i != 16; ++i) {
11330 int EltIdx = MaskVals[i];
11331 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
11332 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11334 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
11335 DAG.getNode(ISD::BUILD_VECTOR, dl,
11336 MVT::v16i8, pshufbMask));
11337 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11340 // No SSSE3 - Calculate in place words and then fix all out of place words
11341 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
11342 // the 16 different words that comprise the two doublequadword input vectors.
11343 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11344 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
11346 for (int i = 0; i != 8; ++i) {
11347 int Elt0 = MaskVals[i*2];
11348 int Elt1 = MaskVals[i*2+1];
11350 // This word of the result is all undef, skip it.
11351 if (Elt0 < 0 && Elt1 < 0)
11354 // This word of the result is already in the correct place, skip it.
11355 if ((Elt0 == i*2) && (Elt1 == i*2+1))
11358 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
11359 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
11362 // If Elt0 and Elt1 are defined, are consecutive, and can be load
11363 // using a single extract together, load it and store it.
11364 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
11365 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11366 DAG.getIntPtrConstant(Elt1 / 2));
11367 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11368 DAG.getIntPtrConstant(i));
11372 // If Elt1 is defined, extract it from the appropriate source. If the
11373 // source byte is not also odd, shift the extracted word left 8 bits
11374 // otherwise clear the bottom 8 bits if we need to do an or.
11376 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11377 DAG.getIntPtrConstant(Elt1 / 2));
11378 if ((Elt1 & 1) == 0)
11379 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
11381 TLI.getShiftAmountTy(InsElt.getValueType())));
11382 else if (Elt0 >= 0)
11383 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
11384 DAG.getConstant(0xFF00, MVT::i16));
11386 // If Elt0 is defined, extract it from the appropriate source. If the
11387 // source byte is not also even, shift the extracted word right 8 bits. If
11388 // Elt1 was also defined, OR the extracted values together before
11389 // inserting them in the result.
11391 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
11392 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
11393 if ((Elt0 & 1) != 0)
11394 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
11396 TLI.getShiftAmountTy(InsElt0.getValueType())));
11397 else if (Elt1 >= 0)
11398 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
11399 DAG.getConstant(0x00FF, MVT::i16));
11400 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
11403 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11404 DAG.getIntPtrConstant(i));
11406 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
11409 // v32i8 shuffles - Translate to VPSHUFB if possible.
11411 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
11412 const X86Subtarget *Subtarget,
11413 SelectionDAG &DAG) {
11414 MVT VT = SVOp->getSimpleValueType(0);
11415 SDValue V1 = SVOp->getOperand(0);
11416 SDValue V2 = SVOp->getOperand(1);
11418 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11420 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11421 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
11422 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
11424 // VPSHUFB may be generated if
11425 // (1) one of input vector is undefined or zeroinitializer.
11426 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
11427 // And (2) the mask indexes don't cross the 128-bit lane.
11428 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
11429 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
11432 if (V1IsAllZero && !V2IsAllZero) {
11433 CommuteVectorShuffleMask(MaskVals, 32);
11436 return getPSHUFB(MaskVals, V1, dl, DAG);
11439 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
11440 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
11441 /// done when every pair / quad of shuffle mask elements point to elements in
11442 /// the right sequence. e.g.
11443 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
11445 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
11446 SelectionDAG &DAG) {
11447 MVT VT = SVOp->getSimpleValueType(0);
11449 unsigned NumElems = VT.getVectorNumElements();
11452 switch (VT.SimpleTy) {
11453 default: llvm_unreachable("Unexpected!");
11456 return SDValue(SVOp, 0);
11457 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
11458 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
11459 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
11460 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
11461 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
11462 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
11465 SmallVector<int, 8> MaskVec;
11466 for (unsigned i = 0; i != NumElems; i += Scale) {
11468 for (unsigned j = 0; j != Scale; ++j) {
11469 int EltIdx = SVOp->getMaskElt(i+j);
11473 StartIdx = (EltIdx / Scale);
11474 if (EltIdx != (int)(StartIdx*Scale + j))
11477 MaskVec.push_back(StartIdx);
11480 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
11481 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
11482 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
11485 /// getVZextMovL - Return a zero-extending vector move low node.
11487 static SDValue getVZextMovL(MVT VT, MVT OpVT,
11488 SDValue SrcOp, SelectionDAG &DAG,
11489 const X86Subtarget *Subtarget, SDLoc dl) {
11490 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
11491 LoadSDNode *LD = nullptr;
11492 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
11493 LD = dyn_cast<LoadSDNode>(SrcOp);
11495 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
11497 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
11498 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
11499 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
11500 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
11501 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
11503 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
11504 return DAG.getNode(ISD::BITCAST, dl, VT,
11505 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11506 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11508 SrcOp.getOperand(0)
11514 return DAG.getNode(ISD::BITCAST, dl, VT,
11515 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11516 DAG.getNode(ISD::BITCAST, dl,
11520 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
11521 /// which could not be matched by any known target speficic shuffle
11523 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11525 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
11526 if (NewOp.getNode())
11529 MVT VT = SVOp->getSimpleValueType(0);
11531 unsigned NumElems = VT.getVectorNumElements();
11532 unsigned NumLaneElems = NumElems / 2;
11535 MVT EltVT = VT.getVectorElementType();
11536 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
11539 SmallVector<int, 16> Mask;
11540 for (unsigned l = 0; l < 2; ++l) {
11541 // Build a shuffle mask for the output, discovering on the fly which
11542 // input vectors to use as shuffle operands (recorded in InputUsed).
11543 // If building a suitable shuffle vector proves too hard, then bail
11544 // out with UseBuildVector set.
11545 bool UseBuildVector = false;
11546 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
11547 unsigned LaneStart = l * NumLaneElems;
11548 for (unsigned i = 0; i != NumLaneElems; ++i) {
11549 // The mask element. This indexes into the input.
11550 int Idx = SVOp->getMaskElt(i+LaneStart);
11552 // the mask element does not index into any input vector.
11553 Mask.push_back(-1);
11557 // The input vector this mask element indexes into.
11558 int Input = Idx / NumLaneElems;
11560 // Turn the index into an offset from the start of the input vector.
11561 Idx -= Input * NumLaneElems;
11563 // Find or create a shuffle vector operand to hold this input.
11565 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
11566 if (InputUsed[OpNo] == Input)
11567 // This input vector is already an operand.
11569 if (InputUsed[OpNo] < 0) {
11570 // Create a new operand for this input vector.
11571 InputUsed[OpNo] = Input;
11576 if (OpNo >= array_lengthof(InputUsed)) {
11577 // More than two input vectors used! Give up on trying to create a
11578 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
11579 UseBuildVector = true;
11583 // Add the mask index for the new shuffle vector.
11584 Mask.push_back(Idx + OpNo * NumLaneElems);
11587 if (UseBuildVector) {
11588 SmallVector<SDValue, 16> SVOps;
11589 for (unsigned i = 0; i != NumLaneElems; ++i) {
11590 // The mask element. This indexes into the input.
11591 int Idx = SVOp->getMaskElt(i+LaneStart);
11593 SVOps.push_back(DAG.getUNDEF(EltVT));
11597 // The input vector this mask element indexes into.
11598 int Input = Idx / NumElems;
11600 // Turn the index into an offset from the start of the input vector.
11601 Idx -= Input * NumElems;
11603 // Extract the vector element by hand.
11604 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11605 SVOp->getOperand(Input),
11606 DAG.getIntPtrConstant(Idx)));
11609 // Construct the output using a BUILD_VECTOR.
11610 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11611 } else if (InputUsed[0] < 0) {
11612 // No input vectors were used! The result is undefined.
11613 Output[l] = DAG.getUNDEF(NVT);
11615 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11616 (InputUsed[0] % 2) * NumLaneElems,
11618 // If only one input was used, use an undefined vector for the other.
11619 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11620 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11621 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11622 // At least one input vector was used. Create a new shuffle vector.
11623 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11629 // Concatenate the result back
11630 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11633 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11634 /// 4 elements, and match them with several different shuffle types.
11636 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11637 SDValue V1 = SVOp->getOperand(0);
11638 SDValue V2 = SVOp->getOperand(1);
11640 MVT VT = SVOp->getSimpleValueType(0);
11642 assert(VT.is128BitVector() && "Unsupported vector size");
11644 std::pair<int, int> Locs[4];
11645 int Mask1[] = { -1, -1, -1, -1 };
11646 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11648 unsigned NumHi = 0;
11649 unsigned NumLo = 0;
11650 for (unsigned i = 0; i != 4; ++i) {
11651 int Idx = PermMask[i];
11653 Locs[i] = std::make_pair(-1, -1);
11655 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11657 Locs[i] = std::make_pair(0, NumLo);
11658 Mask1[NumLo] = Idx;
11661 Locs[i] = std::make_pair(1, NumHi);
11663 Mask1[2+NumHi] = Idx;
11669 if (NumLo <= 2 && NumHi <= 2) {
11670 // If no more than two elements come from either vector. This can be
11671 // implemented with two shuffles. First shuffle gather the elements.
11672 // The second shuffle, which takes the first shuffle as both of its
11673 // vector operands, put the elements into the right order.
11674 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11676 int Mask2[] = { -1, -1, -1, -1 };
11678 for (unsigned i = 0; i != 4; ++i)
11679 if (Locs[i].first != -1) {
11680 unsigned Idx = (i < 2) ? 0 : 4;
11681 Idx += Locs[i].first * 2 + Locs[i].second;
11685 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11688 if (NumLo == 3 || NumHi == 3) {
11689 // Otherwise, we must have three elements from one vector, call it X, and
11690 // one element from the other, call it Y. First, use a shufps to build an
11691 // intermediate vector with the one element from Y and the element from X
11692 // that will be in the same half in the final destination (the indexes don't
11693 // matter). Then, use a shufps to build the final vector, taking the half
11694 // containing the element from Y from the intermediate, and the other half
11697 // Normalize it so the 3 elements come from V1.
11698 CommuteVectorShuffleMask(PermMask, 4);
11702 // Find the element from V2.
11704 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11705 int Val = PermMask[HiIndex];
11712 Mask1[0] = PermMask[HiIndex];
11714 Mask1[2] = PermMask[HiIndex^1];
11716 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11718 if (HiIndex >= 2) {
11719 Mask1[0] = PermMask[0];
11720 Mask1[1] = PermMask[1];
11721 Mask1[2] = HiIndex & 1 ? 6 : 4;
11722 Mask1[3] = HiIndex & 1 ? 4 : 6;
11723 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11726 Mask1[0] = HiIndex & 1 ? 2 : 0;
11727 Mask1[1] = HiIndex & 1 ? 0 : 2;
11728 Mask1[2] = PermMask[2];
11729 Mask1[3] = PermMask[3];
11734 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11737 // Break it into (shuffle shuffle_hi, shuffle_lo).
11738 int LoMask[] = { -1, -1, -1, -1 };
11739 int HiMask[] = { -1, -1, -1, -1 };
11741 int *MaskPtr = LoMask;
11742 unsigned MaskIdx = 0;
11743 unsigned LoIdx = 0;
11744 unsigned HiIdx = 2;
11745 for (unsigned i = 0; i != 4; ++i) {
11752 int Idx = PermMask[i];
11754 Locs[i] = std::make_pair(-1, -1);
11755 } else if (Idx < 4) {
11756 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11757 MaskPtr[LoIdx] = Idx;
11760 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11761 MaskPtr[HiIdx] = Idx;
11766 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11767 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11768 int MaskOps[] = { -1, -1, -1, -1 };
11769 for (unsigned i = 0; i != 4; ++i)
11770 if (Locs[i].first != -1)
11771 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11772 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11775 static bool MayFoldVectorLoad(SDValue V) {
11776 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11777 V = V.getOperand(0);
11779 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11780 V = V.getOperand(0);
11781 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11782 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11783 // BUILD_VECTOR (load), undef
11784 V = V.getOperand(0);
11786 return MayFoldLoad(V);
11790 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11791 MVT VT = Op.getSimpleValueType();
11793 // Canonizalize to v2f64.
11794 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11795 return DAG.getNode(ISD::BITCAST, dl, VT,
11796 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11801 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11803 SDValue V1 = Op.getOperand(0);
11804 SDValue V2 = Op.getOperand(1);
11805 MVT VT = Op.getSimpleValueType();
11807 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11809 if (HasSSE2 && VT == MVT::v2f64)
11810 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11812 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11813 return DAG.getNode(ISD::BITCAST, dl, VT,
11814 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11815 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11816 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11820 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11821 SDValue V1 = Op.getOperand(0);
11822 SDValue V2 = Op.getOperand(1);
11823 MVT VT = Op.getSimpleValueType();
11825 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11826 "unsupported shuffle type");
11828 if (V2.getOpcode() == ISD::UNDEF)
11832 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11836 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11837 SDValue V1 = Op.getOperand(0);
11838 SDValue V2 = Op.getOperand(1);
11839 MVT VT = Op.getSimpleValueType();
11840 unsigned NumElems = VT.getVectorNumElements();
11842 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11843 // operand of these instructions is only memory, so check if there's a
11844 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11846 bool CanFoldLoad = false;
11848 // Trivial case, when V2 comes from a load.
11849 if (MayFoldVectorLoad(V2))
11850 CanFoldLoad = true;
11852 // When V1 is a load, it can be folded later into a store in isel, example:
11853 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11855 // (MOVLPSmr addr:$src1, VR128:$src2)
11856 // So, recognize this potential and also use MOVLPS or MOVLPD
11857 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11858 CanFoldLoad = true;
11860 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11862 if (HasSSE2 && NumElems == 2)
11863 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11866 // If we don't care about the second element, proceed to use movss.
11867 if (SVOp->getMaskElt(1) != -1)
11868 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11871 // movl and movlp will both match v2i64, but v2i64 is never matched by
11872 // movl earlier because we make it strict to avoid messing with the movlp load
11873 // folding logic (see the code above getMOVLP call). Match it here then,
11874 // this is horrible, but will stay like this until we move all shuffle
11875 // matching to x86 specific nodes. Note that for the 1st condition all
11876 // types are matched with movsd.
11878 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11879 // as to remove this logic from here, as much as possible
11880 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11881 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11882 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11885 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11887 // Invert the operand order and use SHUFPS to match it.
11888 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11889 getShuffleSHUFImmediate(SVOp), DAG);
11892 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11893 SelectionDAG &DAG) {
11895 MVT VT = Load->getSimpleValueType(0);
11896 MVT EVT = VT.getVectorElementType();
11897 SDValue Addr = Load->getOperand(1);
11898 SDValue NewAddr = DAG.getNode(
11899 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11900 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11903 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11904 DAG.getMachineFunction().getMachineMemOperand(
11905 Load->getMemOperand(), 0, EVT.getStoreSize()));
11909 // It is only safe to call this function if isINSERTPSMask is true for
11910 // this shufflevector mask.
11911 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11912 SelectionDAG &DAG) {
11913 // Generate an insertps instruction when inserting an f32 from memory onto a
11914 // v4f32 or when copying a member from one v4f32 to another.
11915 // We also use it for transferring i32 from one register to another,
11916 // since it simply copies the same bits.
11917 // If we're transferring an i32 from memory to a specific element in a
11918 // register, we output a generic DAG that will match the PINSRD
11920 MVT VT = SVOp->getSimpleValueType(0);
11921 MVT EVT = VT.getVectorElementType();
11922 SDValue V1 = SVOp->getOperand(0);
11923 SDValue V2 = SVOp->getOperand(1);
11924 auto Mask = SVOp->getMask();
11925 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11926 "unsupported vector type for insertps/pinsrd");
11928 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11929 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11930 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11934 unsigned DestIndex;
11938 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
11941 // If we have 1 element from each vector, we have to check if we're
11942 // changing V1's element's place. If so, we're done. Otherwise, we
11943 // should assume we're changing V2's element's place and behave
11945 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
11946 assert(DestIndex <= INT32_MAX && "truncated destination index");
11947 if (FromV1 == FromV2 &&
11948 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
11952 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11955 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
11956 "More than one element from V1 and from V2, or no elements from one "
11957 "of the vectors. This case should not have returned true from "
11962 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11965 // Get an index into the source vector in the range [0,4) (the mask is
11966 // in the range [0,8) because it can address V1 and V2)
11967 unsigned SrcIndex = Mask[DestIndex] % 4;
11968 if (MayFoldLoad(From)) {
11969 // Trivial case, when From comes from a load and is only used by the
11970 // shuffle. Make it use insertps from the vector that we need from that
11973 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
11974 if (!NewLoad.getNode())
11977 if (EVT == MVT::f32) {
11978 // Create this as a scalar to vector to match the instruction pattern.
11979 SDValue LoadScalarToVector =
11980 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
11981 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
11982 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
11984 } else { // EVT == MVT::i32
11985 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
11986 // instruction, to match the PINSRD instruction, which loads an i32 to a
11987 // certain vector element.
11988 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
11989 DAG.getConstant(DestIndex, MVT::i32));
11993 // Vector-element-to-vector
11994 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
11995 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
11998 // Reduce a vector shuffle to zext.
11999 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
12000 SelectionDAG &DAG) {
12001 // PMOVZX is only available from SSE41.
12002 if (!Subtarget->hasSSE41())
12005 MVT VT = Op.getSimpleValueType();
12007 // Only AVX2 support 256-bit vector integer extending.
12008 if (!Subtarget->hasInt256() && VT.is256BitVector())
12011 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12013 SDValue V1 = Op.getOperand(0);
12014 SDValue V2 = Op.getOperand(1);
12015 unsigned NumElems = VT.getVectorNumElements();
12017 // Extending is an unary operation and the element type of the source vector
12018 // won't be equal to or larger than i64.
12019 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
12020 VT.getVectorElementType() == MVT::i64)
12023 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
12024 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
12025 while ((1U << Shift) < NumElems) {
12026 if (SVOp->getMaskElt(1U << Shift) == 1)
12029 // The maximal ratio is 8, i.e. from i8 to i64.
12034 // Check the shuffle mask.
12035 unsigned Mask = (1U << Shift) - 1;
12036 for (unsigned i = 0; i != NumElems; ++i) {
12037 int EltIdx = SVOp->getMaskElt(i);
12038 if ((i & Mask) != 0 && EltIdx != -1)
12040 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
12044 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
12045 MVT NeVT = MVT::getIntegerVT(NBits);
12046 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
12048 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
12051 return DAG.getNode(ISD::BITCAST, DL, VT,
12052 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
12055 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
12056 SelectionDAG &DAG) {
12057 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12058 MVT VT = Op.getSimpleValueType();
12060 SDValue V1 = Op.getOperand(0);
12061 SDValue V2 = Op.getOperand(1);
12063 if (isZeroShuffle(SVOp))
12064 return getZeroVector(VT, Subtarget, DAG, dl);
12066 // Handle splat operations
12067 if (SVOp->isSplat()) {
12068 // Use vbroadcast whenever the splat comes from a foldable load
12069 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
12070 if (Broadcast.getNode())
12074 // Check integer expanding shuffles.
12075 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
12076 if (NewOp.getNode())
12079 // If the shuffle can be profitably rewritten as a narrower shuffle, then
12081 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
12082 VT == MVT::v32i8) {
12083 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12084 if (NewOp.getNode())
12085 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
12086 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
12087 // FIXME: Figure out a cleaner way to do this.
12088 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
12089 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12090 if (NewOp.getNode()) {
12091 MVT NewVT = NewOp.getSimpleValueType();
12092 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
12093 NewVT, true, false))
12094 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
12097 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
12098 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12099 if (NewOp.getNode()) {
12100 MVT NewVT = NewOp.getSimpleValueType();
12101 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
12102 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
12111 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
12112 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12113 SDValue V1 = Op.getOperand(0);
12114 SDValue V2 = Op.getOperand(1);
12115 MVT VT = Op.getSimpleValueType();
12117 unsigned NumElems = VT.getVectorNumElements();
12118 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
12119 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
12120 bool V1IsSplat = false;
12121 bool V2IsSplat = false;
12122 bool HasSSE2 = Subtarget->hasSSE2();
12123 bool HasFp256 = Subtarget->hasFp256();
12124 bool HasInt256 = Subtarget->hasInt256();
12125 MachineFunction &MF = DAG.getMachineFunction();
12126 bool OptForSize = MF.getFunction()->getAttributes().
12127 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
12129 // Check if we should use the experimental vector shuffle lowering. If so,
12130 // delegate completely to that code path.
12131 if (ExperimentalVectorShuffleLowering)
12132 return lowerVectorShuffle(Op, Subtarget, DAG);
12134 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
12136 if (V1IsUndef && V2IsUndef)
12137 return DAG.getUNDEF(VT);
12139 // When we create a shuffle node we put the UNDEF node to second operand,
12140 // but in some cases the first operand may be transformed to UNDEF.
12141 // In this case we should just commute the node.
12143 return DAG.getCommutedVectorShuffle(*SVOp);
12145 // Vector shuffle lowering takes 3 steps:
12147 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
12148 // narrowing and commutation of operands should be handled.
12149 // 2) Matching of shuffles with known shuffle masks to x86 target specific
12151 // 3) Rewriting of unmatched masks into new generic shuffle operations,
12152 // so the shuffle can be broken into other shuffles and the legalizer can
12153 // try the lowering again.
12155 // The general idea is that no vector_shuffle operation should be left to
12156 // be matched during isel, all of them must be converted to a target specific
12159 // Normalize the input vectors. Here splats, zeroed vectors, profitable
12160 // narrowing and commutation of operands should be handled. The actual code
12161 // doesn't include all of those, work in progress...
12162 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
12163 if (NewOp.getNode())
12166 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
12168 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
12169 // unpckh_undef). Only use pshufd if speed is more important than size.
12170 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12171 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12172 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12173 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12175 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
12176 V2IsUndef && MayFoldVectorLoad(V1))
12177 return getMOVDDup(Op, dl, V1, DAG);
12179 if (isMOVHLPS_v_undef_Mask(M, VT))
12180 return getMOVHighToLow(Op, dl, DAG);
12182 // Use to match splats
12183 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
12184 (VT == MVT::v2f64 || VT == MVT::v2i64))
12185 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12187 if (isPSHUFDMask(M, VT)) {
12188 // The actual implementation will match the mask in the if above and then
12189 // during isel it can match several different instructions, not only pshufd
12190 // as its name says, sad but true, emulate the behavior for now...
12191 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
12192 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
12194 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
12196 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
12197 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
12199 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
12200 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
12203 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
12207 if (isPALIGNRMask(M, VT, Subtarget))
12208 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
12209 getShufflePALIGNRImmediate(SVOp),
12212 if (isVALIGNMask(M, VT, Subtarget))
12213 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
12214 getShuffleVALIGNImmediate(SVOp),
12217 // Check if this can be converted into a logical shift.
12218 bool isLeft = false;
12219 unsigned ShAmt = 0;
12221 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
12222 if (isShift && ShVal.hasOneUse()) {
12223 // If the shifted value has multiple uses, it may be cheaper to use
12224 // v_set0 + movlhps or movhlps, etc.
12225 MVT EltVT = VT.getVectorElementType();
12226 ShAmt *= EltVT.getSizeInBits();
12227 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12230 if (isMOVLMask(M, VT)) {
12231 if (ISD::isBuildVectorAllZeros(V1.getNode()))
12232 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
12233 if (!isMOVLPMask(M, VT)) {
12234 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
12235 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
12237 if (VT == MVT::v4i32 || VT == MVT::v4f32)
12238 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
12242 // FIXME: fold these into legal mask.
12243 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
12244 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
12246 if (isMOVHLPSMask(M, VT))
12247 return getMOVHighToLow(Op, dl, DAG);
12249 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
12250 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
12252 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
12253 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
12255 if (isMOVLPMask(M, VT))
12256 return getMOVLP(Op, dl, DAG, HasSSE2);
12258 if (ShouldXformToMOVHLPS(M, VT) ||
12259 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
12260 return DAG.getCommutedVectorShuffle(*SVOp);
12263 // No better options. Use a vshldq / vsrldq.
12264 MVT EltVT = VT.getVectorElementType();
12265 ShAmt *= EltVT.getSizeInBits();
12266 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12269 bool Commuted = false;
12270 // FIXME: This should also accept a bitcast of a splat? Be careful, not
12271 // 1,1,1,1 -> v8i16 though.
12272 BitVector UndefElements;
12273 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
12274 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12276 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
12277 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12280 // Canonicalize the splat or undef, if present, to be on the RHS.
12281 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
12282 CommuteVectorShuffleMask(M, NumElems);
12284 std::swap(V1IsSplat, V2IsSplat);
12288 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
12289 // Shuffling low element of v1 into undef, just return v1.
12292 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
12293 // the instruction selector will not match, so get a canonical MOVL with
12294 // swapped operands to undo the commute.
12295 return getMOVL(DAG, dl, VT, V2, V1);
12298 if (isUNPCKLMask(M, VT, HasInt256))
12299 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12301 if (isUNPCKHMask(M, VT, HasInt256))
12302 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12305 // Normalize mask so all entries that point to V2 points to its first
12306 // element then try to match unpck{h|l} again. If match, return a
12307 // new vector_shuffle with the corrected mask.p
12308 SmallVector<int, 8> NewMask(M.begin(), M.end());
12309 NormalizeMask(NewMask, NumElems);
12310 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
12311 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12312 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
12313 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12317 // Commute is back and try unpck* again.
12318 // FIXME: this seems wrong.
12319 CommuteVectorShuffleMask(M, NumElems);
12321 std::swap(V1IsSplat, V2IsSplat);
12323 if (isUNPCKLMask(M, VT, HasInt256))
12324 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12326 if (isUNPCKHMask(M, VT, HasInt256))
12327 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12330 // Normalize the node to match x86 shuffle ops if needed
12331 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
12332 return DAG.getCommutedVectorShuffle(*SVOp);
12334 // The checks below are all present in isShuffleMaskLegal, but they are
12335 // inlined here right now to enable us to directly emit target specific
12336 // nodes, and remove one by one until they don't return Op anymore.
12338 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
12339 SVOp->getSplatIndex() == 0 && V2IsUndef) {
12340 if (VT == MVT::v2f64 || VT == MVT::v2i64)
12341 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12344 if (isPSHUFHWMask(M, VT, HasInt256))
12345 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
12346 getShufflePSHUFHWImmediate(SVOp),
12349 if (isPSHUFLWMask(M, VT, HasInt256))
12350 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
12351 getShufflePSHUFLWImmediate(SVOp),
12354 unsigned MaskValue;
12355 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
12357 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
12359 if (isSHUFPMask(M, VT))
12360 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
12361 getShuffleSHUFImmediate(SVOp), DAG);
12363 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12364 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12365 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12366 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12368 //===--------------------------------------------------------------------===//
12369 // Generate target specific nodes for 128 or 256-bit shuffles only
12370 // supported in the AVX instruction set.
12373 // Handle VMOVDDUPY permutations
12374 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
12375 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
12377 // Handle VPERMILPS/D* permutations
12378 if (isVPERMILPMask(M, VT)) {
12379 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
12380 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
12381 getShuffleSHUFImmediate(SVOp), DAG);
12382 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
12383 getShuffleSHUFImmediate(SVOp), DAG);
12387 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
12388 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
12389 Idx*(NumElems/2), DAG, dl);
12391 // Handle VPERM2F128/VPERM2I128 permutations
12392 if (isVPERM2X128Mask(M, VT, HasFp256))
12393 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
12394 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
12396 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
12397 return getINSERTPS(SVOp, dl, DAG);
12400 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
12401 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
12403 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
12404 VT.is512BitVector()) {
12405 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
12406 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
12407 SmallVector<SDValue, 16> permclMask;
12408 for (unsigned i = 0; i != NumElems; ++i) {
12409 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
12412 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
12414 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
12415 return DAG.getNode(X86ISD::VPERMV, dl, VT,
12416 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
12417 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
12418 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
12421 //===--------------------------------------------------------------------===//
12422 // Since no target specific shuffle was selected for this generic one,
12423 // lower it into other known shuffles. FIXME: this isn't true yet, but
12424 // this is the plan.
12427 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
12428 if (VT == MVT::v8i16) {
12429 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
12430 if (NewOp.getNode())
12434 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
12435 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
12436 if (NewOp.getNode())
12440 if (VT == MVT::v16i8) {
12441 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
12442 if (NewOp.getNode())
12446 if (VT == MVT::v32i8) {
12447 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
12448 if (NewOp.getNode())
12452 // Handle all 128-bit wide vectors with 4 elements, and match them with
12453 // several different shuffle types.
12454 if (NumElems == 4 && VT.is128BitVector())
12455 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
12457 // Handle general 256-bit shuffles
12458 if (VT.is256BitVector())
12459 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
12464 // This function assumes its argument is a BUILD_VECTOR of constants or
12465 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
12467 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
12468 unsigned &MaskValue) {
12470 unsigned NumElems = BuildVector->getNumOperands();
12471 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
12472 unsigned NumLanes = (NumElems - 1) / 8 + 1;
12473 unsigned NumElemsInLane = NumElems / NumLanes;
12475 // Blend for v16i16 should be symetric for the both lanes.
12476 for (unsigned i = 0; i < NumElemsInLane; ++i) {
12477 SDValue EltCond = BuildVector->getOperand(i);
12478 SDValue SndLaneEltCond =
12479 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
12481 int Lane1Cond = -1, Lane2Cond = -1;
12482 if (isa<ConstantSDNode>(EltCond))
12483 Lane1Cond = !isZero(EltCond);
12484 if (isa<ConstantSDNode>(SndLaneEltCond))
12485 Lane2Cond = !isZero(SndLaneEltCond);
12487 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
12488 // Lane1Cond != 0, means we want the first argument.
12489 // Lane1Cond == 0, means we want the second argument.
12490 // The encoding of this argument is 0 for the first argument, 1
12491 // for the second. Therefore, invert the condition.
12492 MaskValue |= !Lane1Cond << i;
12493 else if (Lane1Cond < 0)
12494 MaskValue |= !Lane2Cond << i;
12501 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
12503 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
12504 SelectionDAG &DAG) {
12505 SDValue Cond = Op.getOperand(0);
12506 SDValue LHS = Op.getOperand(1);
12507 SDValue RHS = Op.getOperand(2);
12509 MVT VT = Op.getSimpleValueType();
12510 MVT EltVT = VT.getVectorElementType();
12511 unsigned NumElems = VT.getVectorNumElements();
12513 // There is no blend with immediate in AVX-512.
12514 if (VT.is512BitVector())
12517 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
12519 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
12522 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
12525 // Check the mask for BLEND and build the value.
12526 unsigned MaskValue = 0;
12527 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
12530 // Convert i32 vectors to floating point if it is not AVX2.
12531 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
12533 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
12534 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
12536 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
12537 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
12540 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
12541 DAG.getConstant(MaskValue, MVT::i32));
12542 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
12545 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
12546 // A vselect where all conditions and data are constants can be optimized into
12547 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
12548 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
12549 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
12550 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
12553 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
12554 if (BlendOp.getNode())
12557 // Some types for vselect were previously set to Expand, not Legal or
12558 // Custom. Return an empty SDValue so we fall-through to Expand, after
12559 // the Custom lowering phase.
12560 MVT VT = Op.getSimpleValueType();
12561 switch (VT.SimpleTy) {
12566 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12571 // We couldn't create a "Blend with immediate" node.
12572 // This node should still be legal, but we'll have to emit a blendv*
12577 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12578 MVT VT = Op.getSimpleValueType();
12581 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12584 if (VT.getSizeInBits() == 8) {
12585 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12586 Op.getOperand(0), Op.getOperand(1));
12587 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12588 DAG.getValueType(VT));
12589 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12592 if (VT.getSizeInBits() == 16) {
12593 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12594 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12596 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12597 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12598 DAG.getNode(ISD::BITCAST, dl,
12601 Op.getOperand(1)));
12602 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12603 Op.getOperand(0), Op.getOperand(1));
12604 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12605 DAG.getValueType(VT));
12606 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12609 if (VT == MVT::f32) {
12610 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12611 // the result back to FR32 register. It's only worth matching if the
12612 // result has a single use which is a store or a bitcast to i32. And in
12613 // the case of a store, it's not worth it if the index is a constant 0,
12614 // because a MOVSSmr can be used instead, which is smaller and faster.
12615 if (!Op.hasOneUse())
12617 SDNode *User = *Op.getNode()->use_begin();
12618 if ((User->getOpcode() != ISD::STORE ||
12619 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12620 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12621 (User->getOpcode() != ISD::BITCAST ||
12622 User->getValueType(0) != MVT::i32))
12624 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12625 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12628 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12631 if (VT == MVT::i32 || VT == MVT::i64) {
12632 // ExtractPS/pextrq works with constant index.
12633 if (isa<ConstantSDNode>(Op.getOperand(1)))
12639 /// Extract one bit from mask vector, like v16i1 or v8i1.
12640 /// AVX-512 feature.
12642 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12643 SDValue Vec = Op.getOperand(0);
12645 MVT VecVT = Vec.getSimpleValueType();
12646 SDValue Idx = Op.getOperand(1);
12647 MVT EltVT = Op.getSimpleValueType();
12649 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12651 // variable index can't be handled in mask registers,
12652 // extend vector to VR512
12653 if (!isa<ConstantSDNode>(Idx)) {
12654 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12655 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12656 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12657 ExtVT.getVectorElementType(), Ext, Idx);
12658 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12661 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12662 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12663 unsigned MaxSift = rc->getSize()*8 - 1;
12664 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12665 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12666 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12667 DAG.getConstant(MaxSift, MVT::i8));
12668 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12669 DAG.getIntPtrConstant(0));
12673 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12674 SelectionDAG &DAG) const {
12676 SDValue Vec = Op.getOperand(0);
12677 MVT VecVT = Vec.getSimpleValueType();
12678 SDValue Idx = Op.getOperand(1);
12680 if (Op.getSimpleValueType() == MVT::i1)
12681 return ExtractBitFromMaskVector(Op, DAG);
12683 if (!isa<ConstantSDNode>(Idx)) {
12684 if (VecVT.is512BitVector() ||
12685 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12686 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12689 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12690 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12691 MaskEltVT.getSizeInBits());
12693 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12694 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12695 getZeroVector(MaskVT, Subtarget, DAG, dl),
12696 Idx, DAG.getConstant(0, getPointerTy()));
12697 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12698 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12699 Perm, DAG.getConstant(0, getPointerTy()));
12704 // If this is a 256-bit vector result, first extract the 128-bit vector and
12705 // then extract the element from the 128-bit vector.
12706 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12708 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12709 // Get the 128-bit vector.
12710 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12711 MVT EltVT = VecVT.getVectorElementType();
12713 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12715 //if (IdxVal >= NumElems/2)
12716 // IdxVal -= NumElems/2;
12717 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12718 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12719 DAG.getConstant(IdxVal, MVT::i32));
12722 assert(VecVT.is128BitVector() && "Unexpected vector length");
12724 if (Subtarget->hasSSE41()) {
12725 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12730 MVT VT = Op.getSimpleValueType();
12731 // TODO: handle v16i8.
12732 if (VT.getSizeInBits() == 16) {
12733 SDValue Vec = Op.getOperand(0);
12734 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12736 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12737 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12738 DAG.getNode(ISD::BITCAST, dl,
12740 Op.getOperand(1)));
12741 // Transform it so it match pextrw which produces a 32-bit result.
12742 MVT EltVT = MVT::i32;
12743 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12744 Op.getOperand(0), Op.getOperand(1));
12745 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12746 DAG.getValueType(VT));
12747 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12750 if (VT.getSizeInBits() == 32) {
12751 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12755 // SHUFPS the element to the lowest double word, then movss.
12756 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12757 MVT VVT = Op.getOperand(0).getSimpleValueType();
12758 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12759 DAG.getUNDEF(VVT), Mask);
12760 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12761 DAG.getIntPtrConstant(0));
12764 if (VT.getSizeInBits() == 64) {
12765 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12766 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12767 // to match extract_elt for f64.
12768 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12772 // UNPCKHPD the element to the lowest double word, then movsd.
12773 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12774 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12775 int Mask[2] = { 1, -1 };
12776 MVT VVT = Op.getOperand(0).getSimpleValueType();
12777 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12778 DAG.getUNDEF(VVT), Mask);
12779 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12780 DAG.getIntPtrConstant(0));
12786 /// Insert one bit to mask vector, like v16i1 or v8i1.
12787 /// AVX-512 feature.
12789 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12791 SDValue Vec = Op.getOperand(0);
12792 SDValue Elt = Op.getOperand(1);
12793 SDValue Idx = Op.getOperand(2);
12794 MVT VecVT = Vec.getSimpleValueType();
12796 if (!isa<ConstantSDNode>(Idx)) {
12797 // Non constant index. Extend source and destination,
12798 // insert element and then truncate the result.
12799 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12800 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12801 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12802 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12803 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12804 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12807 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12808 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12809 if (Vec.getOpcode() == ISD::UNDEF)
12810 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12811 DAG.getConstant(IdxVal, MVT::i8));
12812 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12813 unsigned MaxSift = rc->getSize()*8 - 1;
12814 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12815 DAG.getConstant(MaxSift, MVT::i8));
12816 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12817 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12818 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12821 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12822 SelectionDAG &DAG) const {
12823 MVT VT = Op.getSimpleValueType();
12824 MVT EltVT = VT.getVectorElementType();
12826 if (EltVT == MVT::i1)
12827 return InsertBitToMaskVector(Op, DAG);
12830 SDValue N0 = Op.getOperand(0);
12831 SDValue N1 = Op.getOperand(1);
12832 SDValue N2 = Op.getOperand(2);
12833 if (!isa<ConstantSDNode>(N2))
12835 auto *N2C = cast<ConstantSDNode>(N2);
12836 unsigned IdxVal = N2C->getZExtValue();
12838 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12839 // into that, and then insert the subvector back into the result.
12840 if (VT.is256BitVector() || VT.is512BitVector()) {
12841 // Get the desired 128-bit vector half.
12842 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12844 // Insert the element into the desired half.
12845 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12846 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12848 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12849 DAG.getConstant(IdxIn128, MVT::i32));
12851 // Insert the changed part back to the 256-bit vector
12852 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12854 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12856 if (Subtarget->hasSSE41()) {
12857 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12859 if (VT == MVT::v8i16) {
12860 Opc = X86ISD::PINSRW;
12862 assert(VT == MVT::v16i8);
12863 Opc = X86ISD::PINSRB;
12866 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12868 if (N1.getValueType() != MVT::i32)
12869 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12870 if (N2.getValueType() != MVT::i32)
12871 N2 = DAG.getIntPtrConstant(IdxVal);
12872 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12875 if (EltVT == MVT::f32) {
12876 // Bits [7:6] of the constant are the source select. This will always be
12877 // zero here. The DAG Combiner may combine an extract_elt index into
12879 // bits. For example (insert (extract, 3), 2) could be matched by
12881 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12882 // Bits [5:4] of the constant are the destination select. This is the
12883 // value of the incoming immediate.
12884 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12885 // combine either bitwise AND or insert of float 0.0 to set these bits.
12886 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12887 // Create this as a scalar to vector..
12888 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12889 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12892 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12893 // PINSR* works with constant index.
12898 if (EltVT == MVT::i8)
12901 if (EltVT.getSizeInBits() == 16) {
12902 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12903 // as its second argument.
12904 if (N1.getValueType() != MVT::i32)
12905 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12906 if (N2.getValueType() != MVT::i32)
12907 N2 = DAG.getIntPtrConstant(IdxVal);
12908 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12913 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12915 MVT OpVT = Op.getSimpleValueType();
12917 // If this is a 256-bit vector result, first insert into a 128-bit
12918 // vector and then insert into the 256-bit vector.
12919 if (!OpVT.is128BitVector()) {
12920 // Insert into a 128-bit vector.
12921 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12922 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12923 OpVT.getVectorNumElements() / SizeFactor);
12925 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12927 // Insert the 128-bit vector.
12928 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12931 if (OpVT == MVT::v1i64 &&
12932 Op.getOperand(0).getValueType() == MVT::i64)
12933 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12935 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12936 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12937 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12938 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12941 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12942 // a simple subregister reference or explicit instructions to grab
12943 // upper bits of a vector.
12944 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12945 SelectionDAG &DAG) {
12947 SDValue In = Op.getOperand(0);
12948 SDValue Idx = Op.getOperand(1);
12949 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12950 MVT ResVT = Op.getSimpleValueType();
12951 MVT InVT = In.getSimpleValueType();
12953 if (Subtarget->hasFp256()) {
12954 if (ResVT.is128BitVector() &&
12955 (InVT.is256BitVector() || InVT.is512BitVector()) &&
12956 isa<ConstantSDNode>(Idx)) {
12957 return Extract128BitVector(In, IdxVal, DAG, dl);
12959 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
12960 isa<ConstantSDNode>(Idx)) {
12961 return Extract256BitVector(In, IdxVal, DAG, dl);
12967 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12968 // simple superregister reference or explicit instructions to insert
12969 // the upper bits of a vector.
12970 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12971 SelectionDAG &DAG) {
12972 if (Subtarget->hasFp256()) {
12973 SDLoc dl(Op.getNode());
12974 SDValue Vec = Op.getNode()->getOperand(0);
12975 SDValue SubVec = Op.getNode()->getOperand(1);
12976 SDValue Idx = Op.getNode()->getOperand(2);
12978 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
12979 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
12980 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
12981 isa<ConstantSDNode>(Idx)) {
12982 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12983 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
12986 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
12987 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
12988 isa<ConstantSDNode>(Idx)) {
12989 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12990 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
12996 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
12997 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
12998 // one of the above mentioned nodes. It has to be wrapped because otherwise
12999 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
13000 // be used to form addressing mode. These wrapped nodes will be selected
13003 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
13004 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
13006 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13007 // global base reg.
13008 unsigned char OpFlag = 0;
13009 unsigned WrapperKind = X86ISD::Wrapper;
13010 CodeModel::Model M = DAG.getTarget().getCodeModel();
13012 if (Subtarget->isPICStyleRIPRel() &&
13013 (M == CodeModel::Small || M == CodeModel::Kernel))
13014 WrapperKind = X86ISD::WrapperRIP;
13015 else if (Subtarget->isPICStyleGOT())
13016 OpFlag = X86II::MO_GOTOFF;
13017 else if (Subtarget->isPICStyleStubPIC())
13018 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13020 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
13021 CP->getAlignment(),
13022 CP->getOffset(), OpFlag);
13024 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13025 // With PIC, the address is actually $g + Offset.
13027 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13028 DAG.getNode(X86ISD::GlobalBaseReg,
13029 SDLoc(), getPointerTy()),
13036 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
13037 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
13039 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13040 // global base reg.
13041 unsigned char OpFlag = 0;
13042 unsigned WrapperKind = X86ISD::Wrapper;
13043 CodeModel::Model M = DAG.getTarget().getCodeModel();
13045 if (Subtarget->isPICStyleRIPRel() &&
13046 (M == CodeModel::Small || M == CodeModel::Kernel))
13047 WrapperKind = X86ISD::WrapperRIP;
13048 else if (Subtarget->isPICStyleGOT())
13049 OpFlag = X86II::MO_GOTOFF;
13050 else if (Subtarget->isPICStyleStubPIC())
13051 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13053 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
13056 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13058 // With PIC, the address is actually $g + Offset.
13060 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13061 DAG.getNode(X86ISD::GlobalBaseReg,
13062 SDLoc(), getPointerTy()),
13069 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
13070 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
13072 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13073 // global base reg.
13074 unsigned char OpFlag = 0;
13075 unsigned WrapperKind = X86ISD::Wrapper;
13076 CodeModel::Model M = DAG.getTarget().getCodeModel();
13078 if (Subtarget->isPICStyleRIPRel() &&
13079 (M == CodeModel::Small || M == CodeModel::Kernel)) {
13080 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
13081 OpFlag = X86II::MO_GOTPCREL;
13082 WrapperKind = X86ISD::WrapperRIP;
13083 } else if (Subtarget->isPICStyleGOT()) {
13084 OpFlag = X86II::MO_GOT;
13085 } else if (Subtarget->isPICStyleStubPIC()) {
13086 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
13087 } else if (Subtarget->isPICStyleStubNoDynamic()) {
13088 OpFlag = X86II::MO_DARWIN_NONLAZY;
13091 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
13094 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13096 // With PIC, the address is actually $g + Offset.
13097 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
13098 !Subtarget->is64Bit()) {
13099 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13100 DAG.getNode(X86ISD::GlobalBaseReg,
13101 SDLoc(), getPointerTy()),
13105 // For symbols that require a load from a stub to get the address, emit the
13107 if (isGlobalStubReference(OpFlag))
13108 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
13109 MachinePointerInfo::getGOT(), false, false, false, 0);
13115 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
13116 // Create the TargetBlockAddressAddress node.
13117 unsigned char OpFlags =
13118 Subtarget->ClassifyBlockAddressReference();
13119 CodeModel::Model M = DAG.getTarget().getCodeModel();
13120 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
13121 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
13123 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
13126 if (Subtarget->isPICStyleRIPRel() &&
13127 (M == CodeModel::Small || M == CodeModel::Kernel))
13128 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13130 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13132 // With PIC, the address is actually $g + Offset.
13133 if (isGlobalRelativeToPICBase(OpFlags)) {
13134 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13135 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13143 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
13144 int64_t Offset, SelectionDAG &DAG) const {
13145 // Create the TargetGlobalAddress node, folding in the constant
13146 // offset if it is legal.
13147 unsigned char OpFlags =
13148 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
13149 CodeModel::Model M = DAG.getTarget().getCodeModel();
13151 if (OpFlags == X86II::MO_NO_FLAG &&
13152 X86::isOffsetSuitableForCodeModel(Offset, M)) {
13153 // A direct static reference to a global.
13154 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
13157 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
13160 if (Subtarget->isPICStyleRIPRel() &&
13161 (M == CodeModel::Small || M == CodeModel::Kernel))
13162 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13164 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13166 // With PIC, the address is actually $g + Offset.
13167 if (isGlobalRelativeToPICBase(OpFlags)) {
13168 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13169 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13173 // For globals that require a load from a stub to get the address, emit the
13175 if (isGlobalStubReference(OpFlags))
13176 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
13177 MachinePointerInfo::getGOT(), false, false, false, 0);
13179 // If there was a non-zero offset that we didn't fold, create an explicit
13180 // addition for it.
13182 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
13183 DAG.getConstant(Offset, getPointerTy()));
13189 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
13190 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
13191 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
13192 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
13196 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
13197 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
13198 unsigned char OperandFlags, bool LocalDynamic = false) {
13199 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13200 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13202 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13203 GA->getValueType(0),
13207 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
13211 SDValue Ops[] = { Chain, TGA, *InFlag };
13212 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13214 SDValue Ops[] = { Chain, TGA };
13215 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13218 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
13219 MFI->setAdjustsStack(true);
13220 MFI->setHasCalls(true);
13222 SDValue Flag = Chain.getValue(1);
13223 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
13226 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
13228 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13231 SDLoc dl(GA); // ? function entry point might be better
13232 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13233 DAG.getNode(X86ISD::GlobalBaseReg,
13234 SDLoc(), PtrVT), InFlag);
13235 InFlag = Chain.getValue(1);
13237 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
13240 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
13242 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13244 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
13245 X86::RAX, X86II::MO_TLSGD);
13248 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
13254 // Get the start address of the TLS block for this module.
13255 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
13256 .getInfo<X86MachineFunctionInfo>();
13257 MFI->incNumLocalDynamicTLSAccesses();
13261 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
13262 X86II::MO_TLSLD, /*LocalDynamic=*/true);
13265 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13266 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
13267 InFlag = Chain.getValue(1);
13268 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
13269 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
13272 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
13276 unsigned char OperandFlags = X86II::MO_DTPOFF;
13277 unsigned WrapperKind = X86ISD::Wrapper;
13278 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13279 GA->getValueType(0),
13280 GA->getOffset(), OperandFlags);
13281 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13283 // Add x@dtpoff with the base.
13284 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
13287 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
13288 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13289 const EVT PtrVT, TLSModel::Model model,
13290 bool is64Bit, bool isPIC) {
13293 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
13294 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
13295 is64Bit ? 257 : 256));
13297 SDValue ThreadPointer =
13298 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
13299 MachinePointerInfo(Ptr), false, false, false, 0);
13301 unsigned char OperandFlags = 0;
13302 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
13304 unsigned WrapperKind = X86ISD::Wrapper;
13305 if (model == TLSModel::LocalExec) {
13306 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
13307 } else if (model == TLSModel::InitialExec) {
13309 OperandFlags = X86II::MO_GOTTPOFF;
13310 WrapperKind = X86ISD::WrapperRIP;
13312 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
13315 llvm_unreachable("Unexpected model");
13318 // emit "addl x@ntpoff,%eax" (local exec)
13319 // or "addl x@indntpoff,%eax" (initial exec)
13320 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
13322 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
13323 GA->getOffset(), OperandFlags);
13324 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13326 if (model == TLSModel::InitialExec) {
13327 if (isPIC && !is64Bit) {
13328 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
13329 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
13333 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
13334 MachinePointerInfo::getGOT(), false, false, false, 0);
13337 // The address of the thread local variable is the add of the thread
13338 // pointer with the offset of the variable.
13339 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
13343 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
13345 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
13346 const GlobalValue *GV = GA->getGlobal();
13348 if (Subtarget->isTargetELF()) {
13349 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
13352 case TLSModel::GeneralDynamic:
13353 if (Subtarget->is64Bit())
13354 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
13355 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
13356 case TLSModel::LocalDynamic:
13357 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
13358 Subtarget->is64Bit());
13359 case TLSModel::InitialExec:
13360 case TLSModel::LocalExec:
13361 return LowerToTLSExecModel(
13362 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
13363 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
13365 llvm_unreachable("Unknown TLS model.");
13368 if (Subtarget->isTargetDarwin()) {
13369 // Darwin only has one model of TLS. Lower to that.
13370 unsigned char OpFlag = 0;
13371 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
13372 X86ISD::WrapperRIP : X86ISD::Wrapper;
13374 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13375 // global base reg.
13376 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
13377 !Subtarget->is64Bit();
13379 OpFlag = X86II::MO_TLVP_PIC_BASE;
13381 OpFlag = X86II::MO_TLVP;
13383 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
13384 GA->getValueType(0),
13385 GA->getOffset(), OpFlag);
13386 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13388 // With PIC32, the address is actually $g + Offset.
13390 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13391 DAG.getNode(X86ISD::GlobalBaseReg,
13392 SDLoc(), getPointerTy()),
13395 // Lowering the machine isd will make sure everything is in the right
13397 SDValue Chain = DAG.getEntryNode();
13398 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13399 SDValue Args[] = { Chain, Offset };
13400 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
13402 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
13403 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13404 MFI->setAdjustsStack(true);
13406 // And our return value (tls address) is in the standard call return value
13408 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
13409 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
13410 Chain.getValue(1));
13413 if (Subtarget->isTargetKnownWindowsMSVC() ||
13414 Subtarget->isTargetWindowsGNU()) {
13415 // Just use the implicit TLS architecture
13416 // Need to generate someting similar to:
13417 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
13419 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
13420 // mov rcx, qword [rdx+rcx*8]
13421 // mov eax, .tls$:tlsvar
13422 // [rax+rcx] contains the address
13423 // Windows 64bit: gs:0x58
13424 // Windows 32bit: fs:__tls_array
13427 SDValue Chain = DAG.getEntryNode();
13429 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
13430 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
13431 // use its literal value of 0x2C.
13432 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
13433 ? Type::getInt8PtrTy(*DAG.getContext(),
13435 : Type::getInt32PtrTy(*DAG.getContext(),
13439 Subtarget->is64Bit()
13440 ? DAG.getIntPtrConstant(0x58)
13441 : (Subtarget->isTargetWindowsGNU()
13442 ? DAG.getIntPtrConstant(0x2C)
13443 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
13445 SDValue ThreadPointer =
13446 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
13447 MachinePointerInfo(Ptr), false, false, false, 0);
13449 // Load the _tls_index variable
13450 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
13451 if (Subtarget->is64Bit())
13452 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
13453 IDX, MachinePointerInfo(), MVT::i32,
13454 false, false, false, 0);
13456 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
13457 false, false, false, 0);
13459 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
13461 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
13463 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
13464 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
13465 false, false, false, 0);
13467 // Get the offset of start of .tls section
13468 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13469 GA->getValueType(0),
13470 GA->getOffset(), X86II::MO_SECREL);
13471 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
13473 // The address of the thread local variable is the add of the thread
13474 // pointer with the offset of the variable.
13475 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
13478 llvm_unreachable("TLS not implemented for this target.");
13481 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
13482 /// and take a 2 x i32 value to shift plus a shift amount.
13483 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
13484 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
13485 MVT VT = Op.getSimpleValueType();
13486 unsigned VTBits = VT.getSizeInBits();
13488 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
13489 SDValue ShOpLo = Op.getOperand(0);
13490 SDValue ShOpHi = Op.getOperand(1);
13491 SDValue ShAmt = Op.getOperand(2);
13492 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
13493 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
13495 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13496 DAG.getConstant(VTBits - 1, MVT::i8));
13497 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
13498 DAG.getConstant(VTBits - 1, MVT::i8))
13499 : DAG.getConstant(0, VT);
13501 SDValue Tmp2, Tmp3;
13502 if (Op.getOpcode() == ISD::SHL_PARTS) {
13503 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
13504 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
13506 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
13507 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
13510 // If the shift amount is larger or equal than the width of a part we can't
13511 // rely on the results of shld/shrd. Insert a test and select the appropriate
13512 // values for large shift amounts.
13513 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13514 DAG.getConstant(VTBits, MVT::i8));
13515 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13516 AndNode, DAG.getConstant(0, MVT::i8));
13519 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13520 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13521 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13523 if (Op.getOpcode() == ISD::SHL_PARTS) {
13524 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13525 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13527 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13528 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13531 SDValue Ops[2] = { Lo, Hi };
13532 return DAG.getMergeValues(Ops, dl);
13535 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
13536 SelectionDAG &DAG) const {
13537 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13540 if (SrcVT.isVector()) {
13541 if (SrcVT.getVectorElementType() == MVT::i1) {
13542 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
13543 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13544 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
13545 Op.getOperand(0)));
13550 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
13551 "Unknown SINT_TO_FP to lower!");
13553 // These are really Legal; return the operand so the caller accepts it as
13555 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
13557 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
13558 Subtarget->is64Bit()) {
13562 unsigned Size = SrcVT.getSizeInBits()/8;
13563 MachineFunction &MF = DAG.getMachineFunction();
13564 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
13565 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13566 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13568 MachinePointerInfo::getFixedStack(SSFI),
13570 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13573 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13575 SelectionDAG &DAG) const {
13579 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13581 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13583 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13585 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13587 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13588 MachineMemOperand *MMO;
13590 int SSFI = FI->getIndex();
13592 DAG.getMachineFunction()
13593 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13594 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13596 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13597 StackSlot = StackSlot.getOperand(1);
13599 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13600 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13602 Tys, Ops, SrcVT, MMO);
13605 Chain = Result.getValue(1);
13606 SDValue InFlag = Result.getValue(2);
13608 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13609 // shouldn't be necessary except that RFP cannot be live across
13610 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13611 MachineFunction &MF = DAG.getMachineFunction();
13612 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13613 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13614 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13615 Tys = DAG.getVTList(MVT::Other);
13617 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13619 MachineMemOperand *MMO =
13620 DAG.getMachineFunction()
13621 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13622 MachineMemOperand::MOStore, SSFISize, SSFISize);
13624 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13625 Ops, Op.getValueType(), MMO);
13626 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13627 MachinePointerInfo::getFixedStack(SSFI),
13628 false, false, false, 0);
13634 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13635 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13636 SelectionDAG &DAG) const {
13637 // This algorithm is not obvious. Here it is what we're trying to output:
13640 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13641 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13643 haddpd %xmm0, %xmm0
13645 pshufd $0x4e, %xmm0, %xmm1
13651 LLVMContext *Context = DAG.getContext();
13653 // Build some magic constants.
13654 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13655 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13656 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13658 SmallVector<Constant*,2> CV1;
13660 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13661 APInt(64, 0x4330000000000000ULL))));
13663 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13664 APInt(64, 0x4530000000000000ULL))));
13665 Constant *C1 = ConstantVector::get(CV1);
13666 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13668 // Load the 64-bit value into an XMM register.
13669 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13671 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13672 MachinePointerInfo::getConstantPool(),
13673 false, false, false, 16);
13674 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13675 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13678 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13679 MachinePointerInfo::getConstantPool(),
13680 false, false, false, 16);
13681 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13682 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13685 if (Subtarget->hasSSE3()) {
13686 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13687 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13689 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13690 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13692 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13693 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13697 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13698 DAG.getIntPtrConstant(0));
13701 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13702 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13703 SelectionDAG &DAG) const {
13705 // FP constant to bias correct the final result.
13706 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13709 // Load the 32-bit value into an XMM register.
13710 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13713 // Zero out the upper parts of the register.
13714 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13716 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13717 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13718 DAG.getIntPtrConstant(0));
13720 // Or the load with the bias.
13721 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13722 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13723 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13724 MVT::v2f64, Load)),
13725 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13726 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13727 MVT::v2f64, Bias)));
13728 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13729 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13730 DAG.getIntPtrConstant(0));
13732 // Subtract the bias.
13733 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13735 // Handle final rounding.
13736 EVT DestVT = Op.getValueType();
13738 if (DestVT.bitsLT(MVT::f64))
13739 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13740 DAG.getIntPtrConstant(0));
13741 if (DestVT.bitsGT(MVT::f64))
13742 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13744 // Handle final rounding.
13748 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
13749 const X86Subtarget &Subtarget) {
13750 // The algorithm is the following:
13751 // #ifdef __SSE4_1__
13752 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13753 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13754 // (uint4) 0x53000000, 0xaa);
13756 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13757 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13759 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13760 // return (float4) lo + fhi;
13763 SDValue V = Op->getOperand(0);
13764 EVT VecIntVT = V.getValueType();
13765 bool Is128 = VecIntVT == MVT::v4i32;
13766 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
13767 // If we convert to something else than the supported type, e.g., to v4f64,
13769 if (VecFloatVT != Op->getValueType(0))
13772 unsigned NumElts = VecIntVT.getVectorNumElements();
13773 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
13774 "Unsupported custom type");
13775 assert(NumElts <= 8 && "The size of the constant array must be fixed");
13777 // In the #idef/#else code, we have in common:
13778 // - The vector of constants:
13784 // Create the splat vector for 0x4b000000.
13785 SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);
13786 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
13787 CstLow, CstLow, CstLow, CstLow};
13788 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13789 makeArrayRef(&CstLowArray[0], NumElts));
13790 // Create the splat vector for 0x53000000.
13791 SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);
13792 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
13793 CstHigh, CstHigh, CstHigh, CstHigh};
13794 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13795 makeArrayRef(&CstHighArray[0], NumElts));
13797 // Create the right shift.
13798 SDValue CstShift = DAG.getConstant(16, MVT::i32);
13799 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
13800 CstShift, CstShift, CstShift, CstShift};
13801 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13802 makeArrayRef(&CstShiftArray[0], NumElts));
13803 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
13806 if (Subtarget.hasSSE41()) {
13807 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
13808 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13809 SDValue VecCstLowBitcast =
13810 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
13811 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
13812 // Low will be bitcasted right away, so do not bother bitcasting back to its
13814 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
13815 VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));
13816 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13817 // (uint4) 0x53000000, 0xaa);
13818 SDValue VecCstHighBitcast =
13819 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
13820 SDValue VecShiftBitcast =
13821 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
13822 // High will be bitcasted right away, so do not bother bitcasting back to
13823 // its original type.
13824 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
13825 VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32));
13827 SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);
13828 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
13829 CstMask, CstMask, CstMask);
13830 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13831 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
13832 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
13834 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13835 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
13838 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
13839 SDValue CstFAdd = DAG.getConstantFP(
13840 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);
13841 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
13842 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
13843 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
13844 makeArrayRef(&CstFAddArray[0], NumElts));
13846 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13847 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
13849 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
13850 // return (float4) lo + fhi;
13851 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
13852 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
13855 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13856 SelectionDAG &DAG) const {
13857 SDValue N0 = Op.getOperand(0);
13858 MVT SVT = N0.getSimpleValueType();
13861 switch (SVT.SimpleTy) {
13863 llvm_unreachable("Custom UINT_TO_FP is not supported!");
13868 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13869 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13870 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13874 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
13876 llvm_unreachable(nullptr);
13879 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13880 SelectionDAG &DAG) const {
13881 SDValue N0 = Op.getOperand(0);
13884 if (Op.getValueType().isVector())
13885 return lowerUINT_TO_FP_vec(Op, DAG);
13887 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13888 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13889 // the optimization here.
13890 if (DAG.SignBitIsZero(N0))
13891 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13893 MVT SrcVT = N0.getSimpleValueType();
13894 MVT DstVT = Op.getSimpleValueType();
13895 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13896 return LowerUINT_TO_FP_i64(Op, DAG);
13897 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13898 return LowerUINT_TO_FP_i32(Op, DAG);
13899 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13902 // Make a 64-bit buffer, and use it to build an FILD.
13903 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13904 if (SrcVT == MVT::i32) {
13905 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13906 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13907 getPointerTy(), StackSlot, WordOff);
13908 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13909 StackSlot, MachinePointerInfo(),
13911 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13912 OffsetSlot, MachinePointerInfo(),
13914 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13918 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13919 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13920 StackSlot, MachinePointerInfo(),
13922 // For i64 source, we need to add the appropriate power of 2 if the input
13923 // was negative. This is the same as the optimization in
13924 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13925 // we must be careful to do the computation in x87 extended precision, not
13926 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13927 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13928 MachineMemOperand *MMO =
13929 DAG.getMachineFunction()
13930 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13931 MachineMemOperand::MOLoad, 8, 8);
13933 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13934 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13935 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13938 APInt FF(32, 0x5F800000ULL);
13940 // Check whether the sign bit is set.
13941 SDValue SignSet = DAG.getSetCC(dl,
13942 getSetCCResultType(*DAG.getContext(), MVT::i64),
13943 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
13946 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
13947 SDValue FudgePtr = DAG.getConstantPool(
13948 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
13951 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
13952 SDValue Zero = DAG.getIntPtrConstant(0);
13953 SDValue Four = DAG.getIntPtrConstant(4);
13954 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
13956 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
13958 // Load the value out, extending it from f32 to f80.
13959 // FIXME: Avoid the extend by constructing the right constant pool?
13960 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
13961 FudgePtr, MachinePointerInfo::getConstantPool(),
13962 MVT::f32, false, false, false, 4);
13963 // Extend everything to 80 bits to force it to be done on x87.
13964 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
13965 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
13968 std::pair<SDValue,SDValue>
13969 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
13970 bool IsSigned, bool IsReplace) const {
13973 EVT DstTy = Op.getValueType();
13975 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
13976 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
13980 assert(DstTy.getSimpleVT() <= MVT::i64 &&
13981 DstTy.getSimpleVT() >= MVT::i16 &&
13982 "Unknown FP_TO_INT to lower!");
13984 // These are really Legal.
13985 if (DstTy == MVT::i32 &&
13986 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13987 return std::make_pair(SDValue(), SDValue());
13988 if (Subtarget->is64Bit() &&
13989 DstTy == MVT::i64 &&
13990 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13991 return std::make_pair(SDValue(), SDValue());
13993 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
13994 // stack slot, or into the FTOL runtime function.
13995 MachineFunction &MF = DAG.getMachineFunction();
13996 unsigned MemSize = DstTy.getSizeInBits()/8;
13997 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13998 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14001 if (!IsSigned && isIntegerTypeFTOL(DstTy))
14002 Opc = X86ISD::WIN_FTOL;
14004 switch (DstTy.getSimpleVT().SimpleTy) {
14005 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
14006 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
14007 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
14008 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
14011 SDValue Chain = DAG.getEntryNode();
14012 SDValue Value = Op.getOperand(0);
14013 EVT TheVT = Op.getOperand(0).getValueType();
14014 // FIXME This causes a redundant load/store if the SSE-class value is already
14015 // in memory, such as if it is on the callstack.
14016 if (isScalarFPTypeInSSEReg(TheVT)) {
14017 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
14018 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
14019 MachinePointerInfo::getFixedStack(SSFI),
14021 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
14023 Chain, StackSlot, DAG.getValueType(TheVT)
14026 MachineMemOperand *MMO =
14027 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14028 MachineMemOperand::MOLoad, MemSize, MemSize);
14029 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
14030 Chain = Value.getValue(1);
14031 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14032 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14035 MachineMemOperand *MMO =
14036 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14037 MachineMemOperand::MOStore, MemSize, MemSize);
14039 if (Opc != X86ISD::WIN_FTOL) {
14040 // Build the FP_TO_INT*_IN_MEM
14041 SDValue Ops[] = { Chain, Value, StackSlot };
14042 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
14044 return std::make_pair(FIST, StackSlot);
14046 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
14047 DAG.getVTList(MVT::Other, MVT::Glue),
14049 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
14050 MVT::i32, ftol.getValue(1));
14051 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
14052 MVT::i32, eax.getValue(2));
14053 SDValue Ops[] = { eax, edx };
14054 SDValue pair = IsReplace
14055 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
14056 : DAG.getMergeValues(Ops, DL);
14057 return std::make_pair(pair, SDValue());
14061 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
14062 const X86Subtarget *Subtarget) {
14063 MVT VT = Op->getSimpleValueType(0);
14064 SDValue In = Op->getOperand(0);
14065 MVT InVT = In.getSimpleValueType();
14068 // Optimize vectors in AVX mode:
14071 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14072 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14073 // Concat upper and lower parts.
14076 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14077 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14078 // Concat upper and lower parts.
14081 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
14082 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
14083 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
14086 if (Subtarget->hasInt256())
14087 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
14089 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
14090 SDValue Undef = DAG.getUNDEF(InVT);
14091 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
14092 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14093 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14095 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
14096 VT.getVectorNumElements()/2);
14098 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14099 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14101 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14104 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
14105 SelectionDAG &DAG) {
14106 MVT VT = Op->getSimpleValueType(0);
14107 SDValue In = Op->getOperand(0);
14108 MVT InVT = In.getSimpleValueType();
14110 unsigned int NumElts = VT.getVectorNumElements();
14111 if (NumElts != 8 && NumElts != 16)
14114 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14115 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
14117 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
14118 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14119 // Now we have only mask extension
14120 assert(InVT.getVectorElementType() == MVT::i1);
14121 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
14122 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14123 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14124 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14125 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14126 MachinePointerInfo::getConstantPool(),
14127 false, false, false, Alignment);
14129 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
14130 if (VT.is512BitVector())
14132 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
14135 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14136 SelectionDAG &DAG) {
14137 if (Subtarget->hasFp256()) {
14138 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14146 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14147 SelectionDAG &DAG) {
14149 MVT VT = Op.getSimpleValueType();
14150 SDValue In = Op.getOperand(0);
14151 MVT SVT = In.getSimpleValueType();
14153 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
14154 return LowerZERO_EXTEND_AVX512(Op, DAG);
14156 if (Subtarget->hasFp256()) {
14157 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14162 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
14163 VT.getVectorNumElements() != SVT.getVectorNumElements());
14167 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
14169 MVT VT = Op.getSimpleValueType();
14170 SDValue In = Op.getOperand(0);
14171 MVT InVT = In.getSimpleValueType();
14173 if (VT == MVT::i1) {
14174 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
14175 "Invalid scalar TRUNCATE operation");
14176 if (InVT.getSizeInBits() >= 32)
14178 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
14179 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
14181 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
14182 "Invalid TRUNCATE operation");
14184 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
14185 if (VT.getVectorElementType().getSizeInBits() >=8)
14186 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
14188 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14189 unsigned NumElts = InVT.getVectorNumElements();
14190 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
14191 if (InVT.getSizeInBits() < 512) {
14192 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
14193 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
14197 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
14198 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14199 SDValue CP = DAG.getConstantPool(C, getPointerTy());
14200 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14201 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14202 MachinePointerInfo::getConstantPool(),
14203 false, false, false, Alignment);
14204 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
14205 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
14206 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
14209 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
14210 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
14211 if (Subtarget->hasInt256()) {
14212 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
14213 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
14214 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
14216 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
14217 DAG.getIntPtrConstant(0));
14220 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14221 DAG.getIntPtrConstant(0));
14222 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14223 DAG.getIntPtrConstant(2));
14224 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14225 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14226 static const int ShufMask[] = {0, 2, 4, 6};
14227 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
14230 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
14231 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
14232 if (Subtarget->hasInt256()) {
14233 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
14235 SmallVector<SDValue,32> pshufbMask;
14236 for (unsigned i = 0; i < 2; ++i) {
14237 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
14238 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
14239 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
14240 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
14241 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
14242 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
14243 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
14244 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
14245 for (unsigned j = 0; j < 8; ++j)
14246 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
14248 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
14249 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
14250 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
14252 static const int ShufMask[] = {0, 2, -1, -1};
14253 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
14255 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14256 DAG.getIntPtrConstant(0));
14257 return DAG.getNode(ISD::BITCAST, DL, VT, In);
14260 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14261 DAG.getIntPtrConstant(0));
14263 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14264 DAG.getIntPtrConstant(4));
14266 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
14267 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
14269 // The PSHUFB mask:
14270 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
14271 -1, -1, -1, -1, -1, -1, -1, -1};
14273 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
14274 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
14275 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
14277 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14278 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14280 // The MOVLHPS Mask:
14281 static const int ShufMask2[] = {0, 1, 4, 5};
14282 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
14283 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
14286 // Handle truncation of V256 to V128 using shuffles.
14287 if (!VT.is128BitVector() || !InVT.is256BitVector())
14290 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
14292 unsigned NumElems = VT.getVectorNumElements();
14293 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
14295 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
14296 // Prepare truncation shuffle mask
14297 for (unsigned i = 0; i != NumElems; ++i)
14298 MaskVec[i] = i * 2;
14299 SDValue V = DAG.getVectorShuffle(NVT, DL,
14300 DAG.getNode(ISD::BITCAST, DL, NVT, In),
14301 DAG.getUNDEF(NVT), &MaskVec[0]);
14302 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
14303 DAG.getIntPtrConstant(0));
14306 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
14307 SelectionDAG &DAG) const {
14308 assert(!Op.getSimpleValueType().isVector());
14310 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14311 /*IsSigned=*/ true, /*IsReplace=*/ false);
14312 SDValue FIST = Vals.first, StackSlot = Vals.second;
14313 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
14314 if (!FIST.getNode()) return Op;
14316 if (StackSlot.getNode())
14317 // Load the result.
14318 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14319 FIST, StackSlot, MachinePointerInfo(),
14320 false, false, false, 0);
14322 // The node is the result.
14326 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
14327 SelectionDAG &DAG) const {
14328 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14329 /*IsSigned=*/ false, /*IsReplace=*/ false);
14330 SDValue FIST = Vals.first, StackSlot = Vals.second;
14331 assert(FIST.getNode() && "Unexpected failure");
14333 if (StackSlot.getNode())
14334 // Load the result.
14335 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14336 FIST, StackSlot, MachinePointerInfo(),
14337 false, false, false, 0);
14339 // The node is the result.
14343 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
14345 MVT VT = Op.getSimpleValueType();
14346 SDValue In = Op.getOperand(0);
14347 MVT SVT = In.getSimpleValueType();
14349 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
14351 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
14352 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
14353 In, DAG.getUNDEF(SVT)));
14356 /// The only differences between FABS and FNEG are the mask and the logic op.
14357 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
14358 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
14359 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
14360 "Wrong opcode for lowering FABS or FNEG.");
14362 bool IsFABS = (Op.getOpcode() == ISD::FABS);
14364 // If this is a FABS and it has an FNEG user, bail out to fold the combination
14365 // into an FNABS. We'll lower the FABS after that if it is still in use.
14367 for (SDNode *User : Op->uses())
14368 if (User->getOpcode() == ISD::FNEG)
14371 SDValue Op0 = Op.getOperand(0);
14372 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
14375 MVT VT = Op.getSimpleValueType();
14376 // Assume scalar op for initialization; update for vector if needed.
14377 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
14378 // generate a 16-byte vector constant and logic op even for the scalar case.
14379 // Using a 16-byte mask allows folding the load of the mask with
14380 // the logic op, so it can save (~4 bytes) on code size.
14382 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
14383 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
14384 // decide if we should generate a 16-byte constant mask when we only need 4 or
14385 // 8 bytes for the scalar case.
14386 if (VT.isVector()) {
14387 EltVT = VT.getVectorElementType();
14388 NumElts = VT.getVectorNumElements();
14391 unsigned EltBits = EltVT.getSizeInBits();
14392 LLVMContext *Context = DAG.getContext();
14393 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
14395 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
14396 Constant *C = ConstantInt::get(*Context, MaskElt);
14397 C = ConstantVector::getSplat(NumElts, C);
14398 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14399 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
14400 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
14401 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14402 MachinePointerInfo::getConstantPool(),
14403 false, false, false, Alignment);
14405 if (VT.isVector()) {
14406 // For a vector, cast operands to a vector type, perform the logic op,
14407 // and cast the result back to the original value type.
14408 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
14409 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
14410 SDValue Operand = IsFNABS ?
14411 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
14412 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
14413 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
14414 return DAG.getNode(ISD::BITCAST, dl, VT,
14415 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
14418 // If not vector, then scalar.
14419 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
14420 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
14421 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
14424 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
14425 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14426 LLVMContext *Context = DAG.getContext();
14427 SDValue Op0 = Op.getOperand(0);
14428 SDValue Op1 = Op.getOperand(1);
14430 MVT VT = Op.getSimpleValueType();
14431 MVT SrcVT = Op1.getSimpleValueType();
14433 // If second operand is smaller, extend it first.
14434 if (SrcVT.bitsLT(VT)) {
14435 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
14438 // And if it is bigger, shrink it first.
14439 if (SrcVT.bitsGT(VT)) {
14440 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
14444 // At this point the operands and the result should have the same
14445 // type, and that won't be f80 since that is not custom lowered.
14447 // First get the sign bit of second operand.
14448 SmallVector<Constant*,4> CV;
14449 if (SrcVT == MVT::f64) {
14450 const fltSemantics &Sem = APFloat::IEEEdouble;
14451 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
14452 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
14454 const fltSemantics &Sem = APFloat::IEEEsingle;
14455 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
14456 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14457 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14458 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14460 Constant *C = ConstantVector::get(CV);
14461 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14462 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
14463 MachinePointerInfo::getConstantPool(),
14464 false, false, false, 16);
14465 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
14467 // Shift sign bit right or left if the two operands have different types.
14468 if (SrcVT.bitsGT(VT)) {
14469 // Op0 is MVT::f32, Op1 is MVT::f64.
14470 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
14471 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
14472 DAG.getConstant(32, MVT::i32));
14473 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
14474 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
14475 DAG.getIntPtrConstant(0));
14478 // Clear first operand sign bit.
14480 if (VT == MVT::f64) {
14481 const fltSemantics &Sem = APFloat::IEEEdouble;
14482 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
14483 APInt(64, ~(1ULL << 63)))));
14484 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
14486 const fltSemantics &Sem = APFloat::IEEEsingle;
14487 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
14488 APInt(32, ~(1U << 31)))));
14489 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14490 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14491 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
14493 C = ConstantVector::get(CV);
14494 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14495 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14496 MachinePointerInfo::getConstantPool(),
14497 false, false, false, 16);
14498 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
14500 // Or the value with the sign bit.
14501 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
14504 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
14505 SDValue N0 = Op.getOperand(0);
14507 MVT VT = Op.getSimpleValueType();
14509 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
14510 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
14511 DAG.getConstant(1, VT));
14512 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
14515 // Check whether an OR'd tree is PTEST-able.
14516 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
14517 SelectionDAG &DAG) {
14518 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
14520 if (!Subtarget->hasSSE41())
14523 if (!Op->hasOneUse())
14526 SDNode *N = Op.getNode();
14529 SmallVector<SDValue, 8> Opnds;
14530 DenseMap<SDValue, unsigned> VecInMap;
14531 SmallVector<SDValue, 8> VecIns;
14532 EVT VT = MVT::Other;
14534 // Recognize a special case where a vector is casted into wide integer to
14536 Opnds.push_back(N->getOperand(0));
14537 Opnds.push_back(N->getOperand(1));
14539 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
14540 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
14541 // BFS traverse all OR'd operands.
14542 if (I->getOpcode() == ISD::OR) {
14543 Opnds.push_back(I->getOperand(0));
14544 Opnds.push_back(I->getOperand(1));
14545 // Re-evaluate the number of nodes to be traversed.
14546 e += 2; // 2 more nodes (LHS and RHS) are pushed.
14550 // Quit if a non-EXTRACT_VECTOR_ELT
14551 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14554 // Quit if without a constant index.
14555 SDValue Idx = I->getOperand(1);
14556 if (!isa<ConstantSDNode>(Idx))
14559 SDValue ExtractedFromVec = I->getOperand(0);
14560 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
14561 if (M == VecInMap.end()) {
14562 VT = ExtractedFromVec.getValueType();
14563 // Quit if not 128/256-bit vector.
14564 if (!VT.is128BitVector() && !VT.is256BitVector())
14566 // Quit if not the same type.
14567 if (VecInMap.begin() != VecInMap.end() &&
14568 VT != VecInMap.begin()->first.getValueType())
14570 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
14571 VecIns.push_back(ExtractedFromVec);
14573 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
14576 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14577 "Not extracted from 128-/256-bit vector.");
14579 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
14581 for (DenseMap<SDValue, unsigned>::const_iterator
14582 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
14583 // Quit if not all elements are used.
14584 if (I->second != FullMask)
14588 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
14590 // Cast all vectors into TestVT for PTEST.
14591 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
14592 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
14594 // If more than one full vectors are evaluated, OR them first before PTEST.
14595 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
14596 // Each iteration will OR 2 nodes and append the result until there is only
14597 // 1 node left, i.e. the final OR'd value of all vectors.
14598 SDValue LHS = VecIns[Slot];
14599 SDValue RHS = VecIns[Slot + 1];
14600 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
14603 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
14604 VecIns.back(), VecIns.back());
14607 /// \brief return true if \c Op has a use that doesn't just read flags.
14608 static bool hasNonFlagsUse(SDValue Op) {
14609 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
14611 SDNode *User = *UI;
14612 unsigned UOpNo = UI.getOperandNo();
14613 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
14614 // Look pass truncate.
14615 UOpNo = User->use_begin().getOperandNo();
14616 User = *User->use_begin();
14619 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
14620 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
14626 /// Emit nodes that will be selected as "test Op0,Op0", or something
14628 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
14629 SelectionDAG &DAG) const {
14630 if (Op.getValueType() == MVT::i1)
14631 // KORTEST instruction should be selected
14632 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14633 DAG.getConstant(0, Op.getValueType()));
14635 // CF and OF aren't always set the way we want. Determine which
14636 // of these we need.
14637 bool NeedCF = false;
14638 bool NeedOF = false;
14641 case X86::COND_A: case X86::COND_AE:
14642 case X86::COND_B: case X86::COND_BE:
14645 case X86::COND_G: case X86::COND_GE:
14646 case X86::COND_L: case X86::COND_LE:
14647 case X86::COND_O: case X86::COND_NO: {
14648 // Check if we really need to set the
14649 // Overflow flag. If NoSignedWrap is present
14650 // that is not actually needed.
14651 switch (Op->getOpcode()) {
14656 const BinaryWithFlagsSDNode *BinNode =
14657 cast<BinaryWithFlagsSDNode>(Op.getNode());
14658 if (BinNode->hasNoSignedWrap())
14668 // See if we can use the EFLAGS value from the operand instead of
14669 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
14670 // we prove that the arithmetic won't overflow, we can't use OF or CF.
14671 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
14672 // Emit a CMP with 0, which is the TEST pattern.
14673 //if (Op.getValueType() == MVT::i1)
14674 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
14675 // DAG.getConstant(0, MVT::i1));
14676 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14677 DAG.getConstant(0, Op.getValueType()));
14679 unsigned Opcode = 0;
14680 unsigned NumOperands = 0;
14682 // Truncate operations may prevent the merge of the SETCC instruction
14683 // and the arithmetic instruction before it. Attempt to truncate the operands
14684 // of the arithmetic instruction and use a reduced bit-width instruction.
14685 bool NeedTruncation = false;
14686 SDValue ArithOp = Op;
14687 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
14688 SDValue Arith = Op->getOperand(0);
14689 // Both the trunc and the arithmetic op need to have one user each.
14690 if (Arith->hasOneUse())
14691 switch (Arith.getOpcode()) {
14698 NeedTruncation = true;
14704 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14705 // which may be the result of a CAST. We use the variable 'Op', which is the
14706 // non-casted variable when we check for possible users.
14707 switch (ArithOp.getOpcode()) {
14709 // Due to an isel shortcoming, be conservative if this add is likely to be
14710 // selected as part of a load-modify-store instruction. When the root node
14711 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14712 // uses of other nodes in the match, such as the ADD in this case. This
14713 // leads to the ADD being left around and reselected, with the result being
14714 // two adds in the output. Alas, even if none our users are stores, that
14715 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14716 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14717 // climbing the DAG back to the root, and it doesn't seem to be worth the
14719 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14720 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14721 if (UI->getOpcode() != ISD::CopyToReg &&
14722 UI->getOpcode() != ISD::SETCC &&
14723 UI->getOpcode() != ISD::STORE)
14726 if (ConstantSDNode *C =
14727 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14728 // An add of one will be selected as an INC.
14729 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14730 Opcode = X86ISD::INC;
14735 // An add of negative one (subtract of one) will be selected as a DEC.
14736 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14737 Opcode = X86ISD::DEC;
14743 // Otherwise use a regular EFLAGS-setting add.
14744 Opcode = X86ISD::ADD;
14749 // If we have a constant logical shift that's only used in a comparison
14750 // against zero turn it into an equivalent AND. This allows turning it into
14751 // a TEST instruction later.
14752 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14753 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14754 EVT VT = Op.getValueType();
14755 unsigned BitWidth = VT.getSizeInBits();
14756 unsigned ShAmt = Op->getConstantOperandVal(1);
14757 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14759 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14760 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14761 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14762 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14764 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14765 DAG.getConstant(Mask, VT));
14766 DAG.ReplaceAllUsesWith(Op, New);
14772 // If the primary and result isn't used, don't bother using X86ISD::AND,
14773 // because a TEST instruction will be better.
14774 if (!hasNonFlagsUse(Op))
14780 // Due to the ISEL shortcoming noted above, be conservative if this op is
14781 // likely to be selected as part of a load-modify-store instruction.
14782 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14783 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14784 if (UI->getOpcode() == ISD::STORE)
14787 // Otherwise use a regular EFLAGS-setting instruction.
14788 switch (ArithOp.getOpcode()) {
14789 default: llvm_unreachable("unexpected operator!");
14790 case ISD::SUB: Opcode = X86ISD::SUB; break;
14791 case ISD::XOR: Opcode = X86ISD::XOR; break;
14792 case ISD::AND: Opcode = X86ISD::AND; break;
14794 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14795 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14796 if (EFLAGS.getNode())
14799 Opcode = X86ISD::OR;
14813 return SDValue(Op.getNode(), 1);
14819 // If we found that truncation is beneficial, perform the truncation and
14821 if (NeedTruncation) {
14822 EVT VT = Op.getValueType();
14823 SDValue WideVal = Op->getOperand(0);
14824 EVT WideVT = WideVal.getValueType();
14825 unsigned ConvertedOp = 0;
14826 // Use a target machine opcode to prevent further DAGCombine
14827 // optimizations that may separate the arithmetic operations
14828 // from the setcc node.
14829 switch (WideVal.getOpcode()) {
14831 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14832 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14833 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14834 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14835 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14839 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14840 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14841 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14842 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14843 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14849 // Emit a CMP with 0, which is the TEST pattern.
14850 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14851 DAG.getConstant(0, Op.getValueType()));
14853 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14854 SmallVector<SDValue, 4> Ops;
14855 for (unsigned i = 0; i != NumOperands; ++i)
14856 Ops.push_back(Op.getOperand(i));
14858 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14859 DAG.ReplaceAllUsesWith(Op, New);
14860 return SDValue(New.getNode(), 1);
14863 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14865 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14866 SDLoc dl, SelectionDAG &DAG) const {
14867 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14868 if (C->getAPIntValue() == 0)
14869 return EmitTest(Op0, X86CC, dl, DAG);
14871 if (Op0.getValueType() == MVT::i1)
14872 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14875 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14876 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14877 // Do the comparison at i32 if it's smaller, besides the Atom case.
14878 // This avoids subregister aliasing issues. Keep the smaller reference
14879 // if we're optimizing for size, however, as that'll allow better folding
14880 // of memory operations.
14881 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14882 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14883 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14884 !Subtarget->isAtom()) {
14885 unsigned ExtendOp =
14886 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14887 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14888 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14890 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14891 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14892 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14894 return SDValue(Sub.getNode(), 1);
14896 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14899 /// Convert a comparison if required by the subtarget.
14900 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14901 SelectionDAG &DAG) const {
14902 // If the subtarget does not support the FUCOMI instruction, floating-point
14903 // comparisons have to be converted.
14904 if (Subtarget->hasCMov() ||
14905 Cmp.getOpcode() != X86ISD::CMP ||
14906 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14907 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14910 // The instruction selector will select an FUCOM instruction instead of
14911 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14912 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14913 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14915 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14916 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14917 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14918 DAG.getConstant(8, MVT::i8));
14919 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14920 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14923 /// The minimum architected relative accuracy is 2^-12. We need one
14924 /// Newton-Raphson step to have a good float result (24 bits of precision).
14925 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
14926 DAGCombinerInfo &DCI,
14927 unsigned &RefinementSteps,
14928 bool &UseOneConstNR) const {
14929 // FIXME: We should use instruction latency models to calculate the cost of
14930 // each potential sequence, but this is very hard to do reliably because
14931 // at least Intel's Core* chips have variable timing based on the number of
14932 // significant digits in the divisor and/or sqrt operand.
14933 if (!Subtarget->useSqrtEst())
14936 EVT VT = Op.getValueType();
14938 // SSE1 has rsqrtss and rsqrtps.
14939 // TODO: Add support for AVX512 (v16f32).
14940 // It is likely not profitable to do this for f64 because a double-precision
14941 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
14942 // instructions: convert to single, rsqrtss, convert back to double, refine
14943 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
14944 // along with FMA, this could be a throughput win.
14945 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14946 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14947 RefinementSteps = 1;
14948 UseOneConstNR = false;
14949 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
14954 /// The minimum architected relative accuracy is 2^-12. We need one
14955 /// Newton-Raphson step to have a good float result (24 bits of precision).
14956 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
14957 DAGCombinerInfo &DCI,
14958 unsigned &RefinementSteps) const {
14959 // FIXME: We should use instruction latency models to calculate the cost of
14960 // each potential sequence, but this is very hard to do reliably because
14961 // at least Intel's Core* chips have variable timing based on the number of
14962 // significant digits in the divisor.
14963 if (!Subtarget->useReciprocalEst())
14966 EVT VT = Op.getValueType();
14968 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
14969 // TODO: Add support for AVX512 (v16f32).
14970 // It is likely not profitable to do this for f64 because a double-precision
14971 // reciprocal estimate with refinement on x86 prior to FMA requires
14972 // 15 instructions: convert to single, rcpss, convert back to double, refine
14973 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
14974 // along with FMA, this could be a throughput win.
14975 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14976 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14977 RefinementSteps = ReciprocalEstimateRefinementSteps;
14978 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
14983 static bool isAllOnes(SDValue V) {
14984 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
14985 return C && C->isAllOnesValue();
14988 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14989 /// if it's possible.
14990 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14991 SDLoc dl, SelectionDAG &DAG) const {
14992 SDValue Op0 = And.getOperand(0);
14993 SDValue Op1 = And.getOperand(1);
14994 if (Op0.getOpcode() == ISD::TRUNCATE)
14995 Op0 = Op0.getOperand(0);
14996 if (Op1.getOpcode() == ISD::TRUNCATE)
14997 Op1 = Op1.getOperand(0);
15000 if (Op1.getOpcode() == ISD::SHL)
15001 std::swap(Op0, Op1);
15002 if (Op0.getOpcode() == ISD::SHL) {
15003 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
15004 if (And00C->getZExtValue() == 1) {
15005 // If we looked past a truncate, check that it's only truncating away
15007 unsigned BitWidth = Op0.getValueSizeInBits();
15008 unsigned AndBitWidth = And.getValueSizeInBits();
15009 if (BitWidth > AndBitWidth) {
15011 DAG.computeKnownBits(Op0, Zeros, Ones);
15012 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
15016 RHS = Op0.getOperand(1);
15018 } else if (Op1.getOpcode() == ISD::Constant) {
15019 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
15020 uint64_t AndRHSVal = AndRHS->getZExtValue();
15021 SDValue AndLHS = Op0;
15023 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
15024 LHS = AndLHS.getOperand(0);
15025 RHS = AndLHS.getOperand(1);
15028 // Use BT if the immediate can't be encoded in a TEST instruction.
15029 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
15031 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
15035 if (LHS.getNode()) {
15036 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
15037 // instruction. Since the shift amount is in-range-or-undefined, we know
15038 // that doing a bittest on the i32 value is ok. We extend to i32 because
15039 // the encoding for the i16 version is larger than the i32 version.
15040 // Also promote i16 to i32 for performance / code size reason.
15041 if (LHS.getValueType() == MVT::i8 ||
15042 LHS.getValueType() == MVT::i16)
15043 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
15045 // If the operand types disagree, extend the shift amount to match. Since
15046 // BT ignores high bits (like shifts) we can use anyextend.
15047 if (LHS.getValueType() != RHS.getValueType())
15048 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
15050 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
15051 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
15052 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15053 DAG.getConstant(Cond, MVT::i8), BT);
15059 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
15061 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
15066 // SSE Condition code mapping:
15075 switch (SetCCOpcode) {
15076 default: llvm_unreachable("Unexpected SETCC condition");
15078 case ISD::SETEQ: SSECC = 0; break;
15080 case ISD::SETGT: Swap = true; // Fallthrough
15082 case ISD::SETOLT: SSECC = 1; break;
15084 case ISD::SETGE: Swap = true; // Fallthrough
15086 case ISD::SETOLE: SSECC = 2; break;
15087 case ISD::SETUO: SSECC = 3; break;
15089 case ISD::SETNE: SSECC = 4; break;
15090 case ISD::SETULE: Swap = true; // Fallthrough
15091 case ISD::SETUGE: SSECC = 5; break;
15092 case ISD::SETULT: Swap = true; // Fallthrough
15093 case ISD::SETUGT: SSECC = 6; break;
15094 case ISD::SETO: SSECC = 7; break;
15096 case ISD::SETONE: SSECC = 8; break;
15099 std::swap(Op0, Op1);
15104 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
15105 // ones, and then concatenate the result back.
15106 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
15107 MVT VT = Op.getSimpleValueType();
15109 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
15110 "Unsupported value type for operation");
15112 unsigned NumElems = VT.getVectorNumElements();
15114 SDValue CC = Op.getOperand(2);
15116 // Extract the LHS vectors
15117 SDValue LHS = Op.getOperand(0);
15118 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15119 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15121 // Extract the RHS vectors
15122 SDValue RHS = Op.getOperand(1);
15123 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15124 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15126 // Issue the operation on the smaller types and concatenate the result back
15127 MVT EltVT = VT.getVectorElementType();
15128 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15129 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15130 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
15131 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
15134 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
15135 const X86Subtarget *Subtarget) {
15136 SDValue Op0 = Op.getOperand(0);
15137 SDValue Op1 = Op.getOperand(1);
15138 SDValue CC = Op.getOperand(2);
15139 MVT VT = Op.getSimpleValueType();
15142 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
15143 Op.getValueType().getScalarType() == MVT::i1 &&
15144 "Cannot set masked compare for this operation");
15146 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15148 bool Unsigned = false;
15151 switch (SetCCOpcode) {
15152 default: llvm_unreachable("Unexpected SETCC condition");
15153 case ISD::SETNE: SSECC = 4; break;
15154 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
15155 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
15156 case ISD::SETLT: Swap = true; //fall-through
15157 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
15158 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
15159 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
15160 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
15161 case ISD::SETULE: Unsigned = true; //fall-through
15162 case ISD::SETLE: SSECC = 2; break;
15166 std::swap(Op0, Op1);
15168 return DAG.getNode(Opc, dl, VT, Op0, Op1);
15169 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
15170 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15171 DAG.getConstant(SSECC, MVT::i8));
15174 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
15175 /// operand \p Op1. If non-trivial (for example because it's not constant)
15176 /// return an empty value.
15177 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
15179 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
15183 MVT VT = Op1.getSimpleValueType();
15184 MVT EVT = VT.getVectorElementType();
15185 unsigned n = VT.getVectorNumElements();
15186 SmallVector<SDValue, 8> ULTOp1;
15188 for (unsigned i = 0; i < n; ++i) {
15189 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
15190 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
15193 // Avoid underflow.
15194 APInt Val = Elt->getAPIntValue();
15198 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
15201 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
15204 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
15205 SelectionDAG &DAG) {
15206 SDValue Op0 = Op.getOperand(0);
15207 SDValue Op1 = Op.getOperand(1);
15208 SDValue CC = Op.getOperand(2);
15209 MVT VT = Op.getSimpleValueType();
15210 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15211 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
15216 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
15217 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
15220 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
15221 unsigned Opc = X86ISD::CMPP;
15222 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
15223 assert(VT.getVectorNumElements() <= 16);
15224 Opc = X86ISD::CMPM;
15226 // In the two special cases we can't handle, emit two comparisons.
15229 unsigned CombineOpc;
15230 if (SetCCOpcode == ISD::SETUEQ) {
15231 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
15233 assert(SetCCOpcode == ISD::SETONE);
15234 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
15237 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15238 DAG.getConstant(CC0, MVT::i8));
15239 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15240 DAG.getConstant(CC1, MVT::i8));
15241 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
15243 // Handle all other FP comparisons here.
15244 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15245 DAG.getConstant(SSECC, MVT::i8));
15248 // Break 256-bit integer vector compare into smaller ones.
15249 if (VT.is256BitVector() && !Subtarget->hasInt256())
15250 return Lower256IntVSETCC(Op, DAG);
15252 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
15253 EVT OpVT = Op1.getValueType();
15254 if (Subtarget->hasAVX512()) {
15255 if (Op1.getValueType().is512BitVector() ||
15256 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
15257 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
15258 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
15260 // In AVX-512 architecture setcc returns mask with i1 elements,
15261 // But there is no compare instruction for i8 and i16 elements in KNL.
15262 // We are not talking about 512-bit operands in this case, these
15263 // types are illegal.
15265 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
15266 OpVT.getVectorElementType().getSizeInBits() >= 8))
15267 return DAG.getNode(ISD::TRUNCATE, dl, VT,
15268 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
15271 // We are handling one of the integer comparisons here. Since SSE only has
15272 // GT and EQ comparisons for integer, swapping operands and multiple
15273 // operations may be required for some comparisons.
15275 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
15276 bool Subus = false;
15278 switch (SetCCOpcode) {
15279 default: llvm_unreachable("Unexpected SETCC condition");
15280 case ISD::SETNE: Invert = true;
15281 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
15282 case ISD::SETLT: Swap = true;
15283 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
15284 case ISD::SETGE: Swap = true;
15285 case ISD::SETLE: Opc = X86ISD::PCMPGT;
15286 Invert = true; break;
15287 case ISD::SETULT: Swap = true;
15288 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
15289 FlipSigns = true; break;
15290 case ISD::SETUGE: Swap = true;
15291 case ISD::SETULE: Opc = X86ISD::PCMPGT;
15292 FlipSigns = true; Invert = true; break;
15295 // Special case: Use min/max operations for SETULE/SETUGE
15296 MVT VET = VT.getVectorElementType();
15298 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
15299 || (Subtarget->hasSSE2() && (VET == MVT::i8));
15302 switch (SetCCOpcode) {
15304 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
15305 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
15308 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
15311 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
15312 if (!MinMax && hasSubus) {
15313 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
15315 // t = psubus Op0, Op1
15316 // pcmpeq t, <0..0>
15317 switch (SetCCOpcode) {
15319 case ISD::SETULT: {
15320 // If the comparison is against a constant we can turn this into a
15321 // setule. With psubus, setule does not require a swap. This is
15322 // beneficial because the constant in the register is no longer
15323 // destructed as the destination so it can be hoisted out of a loop.
15324 // Only do this pre-AVX since vpcmp* is no longer destructive.
15325 if (Subtarget->hasAVX())
15327 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
15328 if (ULEOp1.getNode()) {
15330 Subus = true; Invert = false; Swap = false;
15334 // Psubus is better than flip-sign because it requires no inversion.
15335 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
15336 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
15340 Opc = X86ISD::SUBUS;
15346 std::swap(Op0, Op1);
15348 // Check that the operation in question is available (most are plain SSE2,
15349 // but PCMPGTQ and PCMPEQQ have different requirements).
15350 if (VT == MVT::v2i64) {
15351 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
15352 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
15354 // First cast everything to the right type.
15355 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15356 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15358 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15359 // bits of the inputs before performing those operations. The lower
15360 // compare is always unsigned.
15363 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
15365 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
15366 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
15367 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
15368 Sign, Zero, Sign, Zero);
15370 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
15371 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
15373 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
15374 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
15375 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
15377 // Create masks for only the low parts/high parts of the 64 bit integers.
15378 static const int MaskHi[] = { 1, 1, 3, 3 };
15379 static const int MaskLo[] = { 0, 0, 2, 2 };
15380 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
15381 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
15382 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
15384 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
15385 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
15388 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15390 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15393 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
15394 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
15395 // pcmpeqd + pshufd + pand.
15396 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
15398 // First cast everything to the right type.
15399 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15400 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15403 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
15405 // Make sure the lower and upper halves are both all-ones.
15406 static const int Mask[] = { 1, 0, 3, 2 };
15407 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
15408 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
15411 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15413 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15417 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15418 // bits of the inputs before performing those operations.
15420 EVT EltVT = VT.getVectorElementType();
15421 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
15422 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
15423 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
15426 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
15428 // If the logical-not of the result is required, perform that now.
15430 Result = DAG.getNOT(dl, Result, VT);
15433 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
15436 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
15437 getZeroVector(VT, Subtarget, DAG, dl));
15442 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
15444 MVT VT = Op.getSimpleValueType();
15446 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
15448 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
15449 && "SetCC type must be 8-bit or 1-bit integer");
15450 SDValue Op0 = Op.getOperand(0);
15451 SDValue Op1 = Op.getOperand(1);
15453 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
15455 // Optimize to BT if possible.
15456 // Lower (X & (1 << N)) == 0 to BT(X, N).
15457 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
15458 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
15459 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
15460 Op1.getOpcode() == ISD::Constant &&
15461 cast<ConstantSDNode>(Op1)->isNullValue() &&
15462 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15463 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
15464 if (NewSetCC.getNode())
15468 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
15470 if (Op1.getOpcode() == ISD::Constant &&
15471 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
15472 cast<ConstantSDNode>(Op1)->isNullValue()) &&
15473 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15475 // If the input is a setcc, then reuse the input setcc or use a new one with
15476 // the inverted condition.
15477 if (Op0.getOpcode() == X86ISD::SETCC) {
15478 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
15479 bool Invert = (CC == ISD::SETNE) ^
15480 cast<ConstantSDNode>(Op1)->isNullValue();
15484 CCode = X86::GetOppositeBranchCondition(CCode);
15485 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15486 DAG.getConstant(CCode, MVT::i8),
15487 Op0.getOperand(1));
15489 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15493 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
15494 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
15495 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15497 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
15498 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
15501 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
15502 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
15503 if (X86CC == X86::COND_INVALID)
15506 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
15507 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
15508 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15509 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
15511 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15515 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
15516 static bool isX86LogicalCmp(SDValue Op) {
15517 unsigned Opc = Op.getNode()->getOpcode();
15518 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
15519 Opc == X86ISD::SAHF)
15521 if (Op.getResNo() == 1 &&
15522 (Opc == X86ISD::ADD ||
15523 Opc == X86ISD::SUB ||
15524 Opc == X86ISD::ADC ||
15525 Opc == X86ISD::SBB ||
15526 Opc == X86ISD::SMUL ||
15527 Opc == X86ISD::UMUL ||
15528 Opc == X86ISD::INC ||
15529 Opc == X86ISD::DEC ||
15530 Opc == X86ISD::OR ||
15531 Opc == X86ISD::XOR ||
15532 Opc == X86ISD::AND))
15535 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
15541 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
15542 if (V.getOpcode() != ISD::TRUNCATE)
15545 SDValue VOp0 = V.getOperand(0);
15546 unsigned InBits = VOp0.getValueSizeInBits();
15547 unsigned Bits = V.getValueSizeInBits();
15548 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
15551 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
15552 bool addTest = true;
15553 SDValue Cond = Op.getOperand(0);
15554 SDValue Op1 = Op.getOperand(1);
15555 SDValue Op2 = Op.getOperand(2);
15557 EVT VT = Op1.getValueType();
15560 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
15561 // are available. Otherwise fp cmovs get lowered into a less efficient branch
15562 // sequence later on.
15563 if (Cond.getOpcode() == ISD::SETCC &&
15564 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
15565 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
15566 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
15567 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
15568 int SSECC = translateX86FSETCC(
15569 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
15572 if (Subtarget->hasAVX512()) {
15573 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
15574 DAG.getConstant(SSECC, MVT::i8));
15575 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
15577 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
15578 DAG.getConstant(SSECC, MVT::i8));
15579 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
15580 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
15581 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
15585 if (Cond.getOpcode() == ISD::SETCC) {
15586 SDValue NewCond = LowerSETCC(Cond, DAG);
15587 if (NewCond.getNode())
15591 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
15592 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
15593 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
15594 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
15595 if (Cond.getOpcode() == X86ISD::SETCC &&
15596 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
15597 isZero(Cond.getOperand(1).getOperand(1))) {
15598 SDValue Cmp = Cond.getOperand(1);
15600 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
15602 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
15603 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
15604 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
15606 SDValue CmpOp0 = Cmp.getOperand(0);
15607 // Apply further optimizations for special cases
15608 // (select (x != 0), -1, 0) -> neg & sbb
15609 // (select (x == 0), 0, -1) -> neg & sbb
15610 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
15611 if (YC->isNullValue() &&
15612 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
15613 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
15614 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
15615 DAG.getConstant(0, CmpOp0.getValueType()),
15617 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15618 DAG.getConstant(X86::COND_B, MVT::i8),
15619 SDValue(Neg.getNode(), 1));
15623 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
15624 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
15625 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15627 SDValue Res = // Res = 0 or -1.
15628 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15629 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
15631 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
15632 Res = DAG.getNOT(DL, Res, Res.getValueType());
15634 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
15635 if (!N2C || !N2C->isNullValue())
15636 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
15641 // Look past (and (setcc_carry (cmp ...)), 1).
15642 if (Cond.getOpcode() == ISD::AND &&
15643 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15644 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15645 if (C && C->getAPIntValue() == 1)
15646 Cond = Cond.getOperand(0);
15649 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15650 // setting operand in place of the X86ISD::SETCC.
15651 unsigned CondOpcode = Cond.getOpcode();
15652 if (CondOpcode == X86ISD::SETCC ||
15653 CondOpcode == X86ISD::SETCC_CARRY) {
15654 CC = Cond.getOperand(0);
15656 SDValue Cmp = Cond.getOperand(1);
15657 unsigned Opc = Cmp.getOpcode();
15658 MVT VT = Op.getSimpleValueType();
15660 bool IllegalFPCMov = false;
15661 if (VT.isFloatingPoint() && !VT.isVector() &&
15662 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15663 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15665 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15666 Opc == X86ISD::BT) { // FIXME
15670 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15671 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15672 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15673 Cond.getOperand(0).getValueType() != MVT::i8)) {
15674 SDValue LHS = Cond.getOperand(0);
15675 SDValue RHS = Cond.getOperand(1);
15676 unsigned X86Opcode;
15679 switch (CondOpcode) {
15680 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15681 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15682 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15683 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15684 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15685 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15686 default: llvm_unreachable("unexpected overflowing operator");
15688 if (CondOpcode == ISD::UMULO)
15689 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15692 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15694 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15696 if (CondOpcode == ISD::UMULO)
15697 Cond = X86Op.getValue(2);
15699 Cond = X86Op.getValue(1);
15701 CC = DAG.getConstant(X86Cond, MVT::i8);
15706 // Look pass the truncate if the high bits are known zero.
15707 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15708 Cond = Cond.getOperand(0);
15710 // We know the result of AND is compared against zero. Try to match
15712 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15713 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
15714 if (NewSetCC.getNode()) {
15715 CC = NewSetCC.getOperand(0);
15716 Cond = NewSetCC.getOperand(1);
15723 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15724 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15727 // a < b ? -1 : 0 -> RES = ~setcc_carry
15728 // a < b ? 0 : -1 -> RES = setcc_carry
15729 // a >= b ? -1 : 0 -> RES = setcc_carry
15730 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15731 if (Cond.getOpcode() == X86ISD::SUB) {
15732 Cond = ConvertCmpIfNecessary(Cond, DAG);
15733 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15735 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15736 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
15737 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15738 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
15739 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
15740 return DAG.getNOT(DL, Res, Res.getValueType());
15745 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15746 // widen the cmov and push the truncate through. This avoids introducing a new
15747 // branch during isel and doesn't add any extensions.
15748 if (Op.getValueType() == MVT::i8 &&
15749 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15750 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15751 if (T1.getValueType() == T2.getValueType() &&
15752 // Blacklist CopyFromReg to avoid partial register stalls.
15753 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15754 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15755 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15756 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15760 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15761 // condition is true.
15762 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15763 SDValue Ops[] = { Op2, Op1, CC, Cond };
15764 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15767 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
15768 SelectionDAG &DAG) {
15769 MVT VT = Op->getSimpleValueType(0);
15770 SDValue In = Op->getOperand(0);
15771 MVT InVT = In.getSimpleValueType();
15772 MVT VTElt = VT.getVectorElementType();
15773 MVT InVTElt = InVT.getVectorElementType();
15777 if ((InVTElt == MVT::i1) &&
15778 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15779 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15781 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15782 VTElt.getSizeInBits() <= 16)) ||
15784 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15785 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15787 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15788 VTElt.getSizeInBits() >= 32))))
15789 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15791 unsigned int NumElts = VT.getVectorNumElements();
15793 if (NumElts != 8 && NumElts != 16)
15796 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15797 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15798 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15799 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15802 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15803 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15805 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15806 Constant *C = ConstantInt::get(*DAG.getContext(),
15807 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15809 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15810 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15811 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15812 MachinePointerInfo::getConstantPool(),
15813 false, false, false, Alignment);
15814 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15815 if (VT.is512BitVector())
15817 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15820 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15821 SelectionDAG &DAG) {
15822 MVT VT = Op->getSimpleValueType(0);
15823 SDValue In = Op->getOperand(0);
15824 MVT InVT = In.getSimpleValueType();
15827 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15828 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15830 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15831 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15832 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15835 if (Subtarget->hasInt256())
15836 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15838 // Optimize vectors in AVX mode
15839 // Sign extend v8i16 to v8i32 and
15842 // Divide input vector into two parts
15843 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15844 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15845 // concat the vectors to original VT
15847 unsigned NumElems = InVT.getVectorNumElements();
15848 SDValue Undef = DAG.getUNDEF(InVT);
15850 SmallVector<int,8> ShufMask1(NumElems, -1);
15851 for (unsigned i = 0; i != NumElems/2; ++i)
15854 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15856 SmallVector<int,8> ShufMask2(NumElems, -1);
15857 for (unsigned i = 0; i != NumElems/2; ++i)
15858 ShufMask2[i] = i + NumElems/2;
15860 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15862 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15863 VT.getVectorNumElements()/2);
15865 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15866 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15868 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15871 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15872 // may emit an illegal shuffle but the expansion is still better than scalar
15873 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15874 // we'll emit a shuffle and a arithmetic shift.
15875 // TODO: It is possible to support ZExt by zeroing the undef values during
15876 // the shuffle phase or after the shuffle.
15877 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15878 SelectionDAG &DAG) {
15879 MVT RegVT = Op.getSimpleValueType();
15880 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15881 assert(RegVT.isInteger() &&
15882 "We only custom lower integer vector sext loads.");
15884 // Nothing useful we can do without SSE2 shuffles.
15885 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15887 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15889 EVT MemVT = Ld->getMemoryVT();
15890 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15891 unsigned RegSz = RegVT.getSizeInBits();
15893 ISD::LoadExtType Ext = Ld->getExtensionType();
15895 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15896 && "Only anyext and sext are currently implemented.");
15897 assert(MemVT != RegVT && "Cannot extend to the same type");
15898 assert(MemVT.isVector() && "Must load a vector from memory");
15900 unsigned NumElems = RegVT.getVectorNumElements();
15901 unsigned MemSz = MemVT.getSizeInBits();
15902 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15904 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15905 // The only way in which we have a legal 256-bit vector result but not the
15906 // integer 256-bit operations needed to directly lower a sextload is if we
15907 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15908 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15909 // correctly legalized. We do this late to allow the canonical form of
15910 // sextload to persist throughout the rest of the DAG combiner -- it wants
15911 // to fold together any extensions it can, and so will fuse a sign_extend
15912 // of an sextload into a sextload targeting a wider value.
15914 if (MemSz == 128) {
15915 // Just switch this to a normal load.
15916 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15917 "it must be a legal 128-bit vector "
15919 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15920 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15921 Ld->isInvariant(), Ld->getAlignment());
15923 assert(MemSz < 128 &&
15924 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15925 // Do an sext load to a 128-bit vector type. We want to use the same
15926 // number of elements, but elements half as wide. This will end up being
15927 // recursively lowered by this routine, but will succeed as we definitely
15928 // have all the necessary features if we're using AVX1.
15930 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15931 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15933 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15934 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15935 Ld->isNonTemporal(), Ld->isInvariant(),
15936 Ld->getAlignment());
15939 // Replace chain users with the new chain.
15940 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15941 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15943 // Finally, do a normal sign-extend to the desired register.
15944 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15947 // All sizes must be a power of two.
15948 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15949 "Non-power-of-two elements are not custom lowered!");
15951 // Attempt to load the original value using scalar loads.
15952 // Find the largest scalar type that divides the total loaded size.
15953 MVT SclrLoadTy = MVT::i8;
15954 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15955 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15956 MVT Tp = (MVT::SimpleValueType)tp;
15957 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15962 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15963 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15965 SclrLoadTy = MVT::f64;
15967 // Calculate the number of scalar loads that we need to perform
15968 // in order to load our vector from memory.
15969 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15971 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15972 "Can only lower sext loads with a single scalar load!");
15974 unsigned loadRegZize = RegSz;
15975 if (Ext == ISD::SEXTLOAD && RegSz == 256)
15978 // Represent our vector as a sequence of elements which are the
15979 // largest scalar that we can load.
15980 EVT LoadUnitVecVT = EVT::getVectorVT(
15981 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15983 // Represent the data using the same element type that is stored in
15984 // memory. In practice, we ''widen'' MemVT.
15986 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15987 loadRegZize / MemVT.getScalarType().getSizeInBits());
15989 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15990 "Invalid vector type");
15992 // We can't shuffle using an illegal type.
15993 assert(TLI.isTypeLegal(WideVecVT) &&
15994 "We only lower types that form legal widened vector types");
15996 SmallVector<SDValue, 8> Chains;
15997 SDValue Ptr = Ld->getBasePtr();
15998 SDValue Increment =
15999 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
16000 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
16002 for (unsigned i = 0; i < NumLoads; ++i) {
16003 // Perform a single load.
16004 SDValue ScalarLoad =
16005 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
16006 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
16007 Ld->getAlignment());
16008 Chains.push_back(ScalarLoad.getValue(1));
16009 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
16010 // another round of DAGCombining.
16012 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
16014 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
16015 ScalarLoad, DAG.getIntPtrConstant(i));
16017 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16020 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
16022 // Bitcast the loaded value to a vector of the original element type, in
16023 // the size of the target vector type.
16024 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
16025 unsigned SizeRatio = RegSz / MemSz;
16027 if (Ext == ISD::SEXTLOAD) {
16028 // If we have SSE4.1, we can directly emit a VSEXT node.
16029 if (Subtarget->hasSSE41()) {
16030 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
16031 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16035 // Otherwise we'll shuffle the small elements in the high bits of the
16036 // larger type and perform an arithmetic shift. If the shift is not legal
16037 // it's better to scalarize.
16038 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
16039 "We can't implement a sext load without an arithmetic right shift!");
16041 // Redistribute the loaded elements into the different locations.
16042 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16043 for (unsigned i = 0; i != NumElems; ++i)
16044 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
16046 SDValue Shuff = DAG.getVectorShuffle(
16047 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16049 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16051 // Build the arithmetic shift.
16052 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
16053 MemVT.getVectorElementType().getSizeInBits();
16055 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
16057 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16061 // Redistribute the loaded elements into the different locations.
16062 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16063 for (unsigned i = 0; i != NumElems; ++i)
16064 ShuffleVec[i * SizeRatio] = i;
16066 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
16067 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16069 // Bitcast to the requested type.
16070 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16071 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16075 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
16076 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
16077 // from the AND / OR.
16078 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
16079 Opc = Op.getOpcode();
16080 if (Opc != ISD::OR && Opc != ISD::AND)
16082 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16083 Op.getOperand(0).hasOneUse() &&
16084 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
16085 Op.getOperand(1).hasOneUse());
16088 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
16089 // 1 and that the SETCC node has a single use.
16090 static bool isXor1OfSetCC(SDValue Op) {
16091 if (Op.getOpcode() != ISD::XOR)
16093 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
16094 if (N1C && N1C->getAPIntValue() == 1) {
16095 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16096 Op.getOperand(0).hasOneUse();
16101 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
16102 bool addTest = true;
16103 SDValue Chain = Op.getOperand(0);
16104 SDValue Cond = Op.getOperand(1);
16105 SDValue Dest = Op.getOperand(2);
16108 bool Inverted = false;
16110 if (Cond.getOpcode() == ISD::SETCC) {
16111 // Check for setcc([su]{add,sub,mul}o == 0).
16112 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
16113 isa<ConstantSDNode>(Cond.getOperand(1)) &&
16114 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
16115 Cond.getOperand(0).getResNo() == 1 &&
16116 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
16117 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
16118 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
16119 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
16120 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
16121 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
16123 Cond = Cond.getOperand(0);
16125 SDValue NewCond = LowerSETCC(Cond, DAG);
16126 if (NewCond.getNode())
16131 // FIXME: LowerXALUO doesn't handle these!!
16132 else if (Cond.getOpcode() == X86ISD::ADD ||
16133 Cond.getOpcode() == X86ISD::SUB ||
16134 Cond.getOpcode() == X86ISD::SMUL ||
16135 Cond.getOpcode() == X86ISD::UMUL)
16136 Cond = LowerXALUO(Cond, DAG);
16139 // Look pass (and (setcc_carry (cmp ...)), 1).
16140 if (Cond.getOpcode() == ISD::AND &&
16141 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
16142 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
16143 if (C && C->getAPIntValue() == 1)
16144 Cond = Cond.getOperand(0);
16147 // If condition flag is set by a X86ISD::CMP, then use it as the condition
16148 // setting operand in place of the X86ISD::SETCC.
16149 unsigned CondOpcode = Cond.getOpcode();
16150 if (CondOpcode == X86ISD::SETCC ||
16151 CondOpcode == X86ISD::SETCC_CARRY) {
16152 CC = Cond.getOperand(0);
16154 SDValue Cmp = Cond.getOperand(1);
16155 unsigned Opc = Cmp.getOpcode();
16156 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
16157 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
16161 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
16165 // These can only come from an arithmetic instruction with overflow,
16166 // e.g. SADDO, UADDO.
16167 Cond = Cond.getNode()->getOperand(1);
16173 CondOpcode = Cond.getOpcode();
16174 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
16175 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
16176 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
16177 Cond.getOperand(0).getValueType() != MVT::i8)) {
16178 SDValue LHS = Cond.getOperand(0);
16179 SDValue RHS = Cond.getOperand(1);
16180 unsigned X86Opcode;
16183 // Keep this in sync with LowerXALUO, otherwise we might create redundant
16184 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
16186 switch (CondOpcode) {
16187 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
16189 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16191 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
16194 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
16195 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
16197 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16199 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
16202 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
16203 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
16204 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
16205 default: llvm_unreachable("unexpected overflowing operator");
16208 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
16209 if (CondOpcode == ISD::UMULO)
16210 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
16213 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
16215 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
16217 if (CondOpcode == ISD::UMULO)
16218 Cond = X86Op.getValue(2);
16220 Cond = X86Op.getValue(1);
16222 CC = DAG.getConstant(X86Cond, MVT::i8);
16226 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
16227 SDValue Cmp = Cond.getOperand(0).getOperand(1);
16228 if (CondOpc == ISD::OR) {
16229 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
16230 // two branches instead of an explicit OR instruction with a
16232 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16233 isX86LogicalCmp(Cmp)) {
16234 CC = Cond.getOperand(0).getOperand(0);
16235 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16236 Chain, Dest, CC, Cmp);
16237 CC = Cond.getOperand(1).getOperand(0);
16241 } else { // ISD::AND
16242 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
16243 // two branches instead of an explicit AND instruction with a
16244 // separate test. However, we only do this if this block doesn't
16245 // have a fall-through edge, because this requires an explicit
16246 // jmp when the condition is false.
16247 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16248 isX86LogicalCmp(Cmp) &&
16249 Op.getNode()->hasOneUse()) {
16250 X86::CondCode CCode =
16251 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16252 CCode = X86::GetOppositeBranchCondition(CCode);
16253 CC = DAG.getConstant(CCode, MVT::i8);
16254 SDNode *User = *Op.getNode()->use_begin();
16255 // Look for an unconditional branch following this conditional branch.
16256 // We need this because we need to reverse the successors in order
16257 // to implement FCMP_OEQ.
16258 if (User->getOpcode() == ISD::BR) {
16259 SDValue FalseBB = User->getOperand(1);
16261 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16262 assert(NewBR == User);
16266 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16267 Chain, Dest, CC, Cmp);
16268 X86::CondCode CCode =
16269 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
16270 CCode = X86::GetOppositeBranchCondition(CCode);
16271 CC = DAG.getConstant(CCode, MVT::i8);
16277 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
16278 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
16279 // It should be transformed during dag combiner except when the condition
16280 // is set by a arithmetics with overflow node.
16281 X86::CondCode CCode =
16282 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16283 CCode = X86::GetOppositeBranchCondition(CCode);
16284 CC = DAG.getConstant(CCode, MVT::i8);
16285 Cond = Cond.getOperand(0).getOperand(1);
16287 } else if (Cond.getOpcode() == ISD::SETCC &&
16288 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
16289 // For FCMP_OEQ, we can emit
16290 // two branches instead of an explicit AND instruction with a
16291 // separate test. However, we only do this if this block doesn't
16292 // have a fall-through edge, because this requires an explicit
16293 // jmp when the condition is false.
16294 if (Op.getNode()->hasOneUse()) {
16295 SDNode *User = *Op.getNode()->use_begin();
16296 // Look for an unconditional branch following this conditional branch.
16297 // We need this because we need to reverse the successors in order
16298 // to implement FCMP_OEQ.
16299 if (User->getOpcode() == ISD::BR) {
16300 SDValue FalseBB = User->getOperand(1);
16302 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16303 assert(NewBR == User);
16307 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16308 Cond.getOperand(0), Cond.getOperand(1));
16309 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16310 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16311 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16312 Chain, Dest, CC, Cmp);
16313 CC = DAG.getConstant(X86::COND_P, MVT::i8);
16318 } else if (Cond.getOpcode() == ISD::SETCC &&
16319 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
16320 // For FCMP_UNE, we can emit
16321 // two branches instead of an explicit AND instruction with a
16322 // separate test. However, we only do this if this block doesn't
16323 // have a fall-through edge, because this requires an explicit
16324 // jmp when the condition is false.
16325 if (Op.getNode()->hasOneUse()) {
16326 SDNode *User = *Op.getNode()->use_begin();
16327 // Look for an unconditional branch following this conditional branch.
16328 // We need this because we need to reverse the successors in order
16329 // to implement FCMP_UNE.
16330 if (User->getOpcode() == ISD::BR) {
16331 SDValue FalseBB = User->getOperand(1);
16333 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16334 assert(NewBR == User);
16337 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16338 Cond.getOperand(0), Cond.getOperand(1));
16339 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16340 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16341 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16342 Chain, Dest, CC, Cmp);
16343 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
16353 // Look pass the truncate if the high bits are known zero.
16354 if (isTruncWithZeroHighBitsInput(Cond, DAG))
16355 Cond = Cond.getOperand(0);
16357 // We know the result of AND is compared against zero. Try to match
16359 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
16360 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
16361 if (NewSetCC.getNode()) {
16362 CC = NewSetCC.getOperand(0);
16363 Cond = NewSetCC.getOperand(1);
16370 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
16371 CC = DAG.getConstant(X86Cond, MVT::i8);
16372 Cond = EmitTest(Cond, X86Cond, dl, DAG);
16374 Cond = ConvertCmpIfNecessary(Cond, DAG);
16375 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16376 Chain, Dest, CC, Cond);
16379 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
16380 // Calls to _alloca are needed to probe the stack when allocating more than 4k
16381 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
16382 // that the guard pages used by the OS virtual memory manager are allocated in
16383 // correct sequence.
16385 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
16386 SelectionDAG &DAG) const {
16387 MachineFunction &MF = DAG.getMachineFunction();
16388 bool SplitStack = MF.shouldSplitStack();
16389 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
16394 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16395 SDNode* Node = Op.getNode();
16397 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
16398 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
16399 " not tell us which reg is the stack pointer!");
16400 EVT VT = Node->getValueType(0);
16401 SDValue Tmp1 = SDValue(Node, 0);
16402 SDValue Tmp2 = SDValue(Node, 1);
16403 SDValue Tmp3 = Node->getOperand(2);
16404 SDValue Chain = Tmp1.getOperand(0);
16406 // Chain the dynamic stack allocation so that it doesn't modify the stack
16407 // pointer when other instructions are using the stack.
16408 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
16411 SDValue Size = Tmp2.getOperand(1);
16412 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
16413 Chain = SP.getValue(1);
16414 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
16415 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
16416 unsigned StackAlign = TFI.getStackAlignment();
16417 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
16418 if (Align > StackAlign)
16419 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
16420 DAG.getConstant(-(uint64_t)Align, VT));
16421 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
16423 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
16424 DAG.getIntPtrConstant(0, true), SDValue(),
16427 SDValue Ops[2] = { Tmp1, Tmp2 };
16428 return DAG.getMergeValues(Ops, dl);
16432 SDValue Chain = Op.getOperand(0);
16433 SDValue Size = Op.getOperand(1);
16434 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
16435 EVT VT = Op.getNode()->getValueType(0);
16437 bool Is64Bit = Subtarget->is64Bit();
16438 EVT SPTy = getPointerTy();
16441 MachineRegisterInfo &MRI = MF.getRegInfo();
16444 // The 64 bit implementation of segmented stacks needs to clobber both r10
16445 // r11. This makes it impossible to use it along with nested parameters.
16446 const Function *F = MF.getFunction();
16448 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
16450 if (I->hasNestAttr())
16451 report_fatal_error("Cannot use segmented stacks with functions that "
16452 "have nested arguments.");
16455 const TargetRegisterClass *AddrRegClass =
16456 getRegClassFor(getPointerTy());
16457 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
16458 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
16459 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
16460 DAG.getRegister(Vreg, SPTy));
16461 SDValue Ops1[2] = { Value, Chain };
16462 return DAG.getMergeValues(Ops1, dl);
16465 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
16467 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
16468 Flag = Chain.getValue(1);
16469 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
16471 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
16473 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16474 DAG.getSubtarget().getRegisterInfo());
16475 unsigned SPReg = RegInfo->getStackRegister();
16476 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
16477 Chain = SP.getValue(1);
16480 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
16481 DAG.getConstant(-(uint64_t)Align, VT));
16482 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
16485 SDValue Ops1[2] = { SP, Chain };
16486 return DAG.getMergeValues(Ops1, dl);
16490 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
16491 MachineFunction &MF = DAG.getMachineFunction();
16492 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16494 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16497 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
16498 // vastart just stores the address of the VarArgsFrameIndex slot into the
16499 // memory location argument.
16500 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16502 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
16503 MachinePointerInfo(SV), false, false, 0);
16507 // gp_offset (0 - 6 * 8)
16508 // fp_offset (48 - 48 + 8 * 16)
16509 // overflow_arg_area (point to parameters coming in memory).
16511 SmallVector<SDValue, 8> MemOps;
16512 SDValue FIN = Op.getOperand(1);
16514 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
16515 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
16517 FIN, MachinePointerInfo(SV), false, false, 0);
16518 MemOps.push_back(Store);
16521 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16522 FIN, DAG.getIntPtrConstant(4));
16523 Store = DAG.getStore(Op.getOperand(0), DL,
16524 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
16526 FIN, MachinePointerInfo(SV, 4), false, false, 0);
16527 MemOps.push_back(Store);
16529 // Store ptr to overflow_arg_area
16530 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16531 FIN, DAG.getIntPtrConstant(4));
16532 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16534 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
16535 MachinePointerInfo(SV, 8),
16537 MemOps.push_back(Store);
16539 // Store ptr to reg_save_area.
16540 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16541 FIN, DAG.getIntPtrConstant(8));
16542 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
16544 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
16545 MachinePointerInfo(SV, 16), false, false, 0);
16546 MemOps.push_back(Store);
16547 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
16550 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
16551 assert(Subtarget->is64Bit() &&
16552 "LowerVAARG only handles 64-bit va_arg!");
16553 assert((Subtarget->isTargetLinux() ||
16554 Subtarget->isTargetDarwin()) &&
16555 "Unhandled target in LowerVAARG");
16556 assert(Op.getNode()->getNumOperands() == 4);
16557 SDValue Chain = Op.getOperand(0);
16558 SDValue SrcPtr = Op.getOperand(1);
16559 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16560 unsigned Align = Op.getConstantOperandVal(3);
16563 EVT ArgVT = Op.getNode()->getValueType(0);
16564 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16565 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
16568 // Decide which area this value should be read from.
16569 // TODO: Implement the AMD64 ABI in its entirety. This simple
16570 // selection mechanism works only for the basic types.
16571 if (ArgVT == MVT::f80) {
16572 llvm_unreachable("va_arg for f80 not yet implemented");
16573 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
16574 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
16575 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
16576 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
16578 llvm_unreachable("Unhandled argument type in LowerVAARG");
16581 if (ArgMode == 2) {
16582 // Sanity Check: Make sure using fp_offset makes sense.
16583 assert(!DAG.getTarget().Options.UseSoftFloat &&
16584 !(DAG.getMachineFunction()
16585 .getFunction()->getAttributes()
16586 .hasAttribute(AttributeSet::FunctionIndex,
16587 Attribute::NoImplicitFloat)) &&
16588 Subtarget->hasSSE1());
16591 // Insert VAARG_64 node into the DAG
16592 // VAARG_64 returns two values: Variable Argument Address, Chain
16593 SmallVector<SDValue, 11> InstOps;
16594 InstOps.push_back(Chain);
16595 InstOps.push_back(SrcPtr);
16596 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
16597 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
16598 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
16599 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
16600 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
16601 VTs, InstOps, MVT::i64,
16602 MachinePointerInfo(SV),
16604 /*Volatile=*/false,
16606 /*WriteMem=*/true);
16607 Chain = VAARG.getValue(1);
16609 // Load the next argument and return it
16610 return DAG.getLoad(ArgVT, dl,
16613 MachinePointerInfo(),
16614 false, false, false, 0);
16617 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
16618 SelectionDAG &DAG) {
16619 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
16620 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
16621 SDValue Chain = Op.getOperand(0);
16622 SDValue DstPtr = Op.getOperand(1);
16623 SDValue SrcPtr = Op.getOperand(2);
16624 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
16625 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16628 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
16629 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
16631 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
16634 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
16635 // amount is a constant. Takes immediate version of shift as input.
16636 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16637 SDValue SrcOp, uint64_t ShiftAmt,
16638 SelectionDAG &DAG) {
16639 MVT ElementType = VT.getVectorElementType();
16641 // Fold this packed shift into its first operand if ShiftAmt is 0.
16645 // Check for ShiftAmt >= element width
16646 if (ShiftAmt >= ElementType.getSizeInBits()) {
16647 if (Opc == X86ISD::VSRAI)
16648 ShiftAmt = ElementType.getSizeInBits() - 1;
16650 return DAG.getConstant(0, VT);
16653 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16654 && "Unknown target vector shift-by-constant node");
16656 // Fold this packed vector shift into a build vector if SrcOp is a
16657 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16658 if (VT == SrcOp.getSimpleValueType() &&
16659 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16660 SmallVector<SDValue, 8> Elts;
16661 unsigned NumElts = SrcOp->getNumOperands();
16662 ConstantSDNode *ND;
16665 default: llvm_unreachable(nullptr);
16666 case X86ISD::VSHLI:
16667 for (unsigned i=0; i!=NumElts; ++i) {
16668 SDValue CurrentOp = SrcOp->getOperand(i);
16669 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16670 Elts.push_back(CurrentOp);
16673 ND = cast<ConstantSDNode>(CurrentOp);
16674 const APInt &C = ND->getAPIntValue();
16675 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
16678 case X86ISD::VSRLI:
16679 for (unsigned i=0; i!=NumElts; ++i) {
16680 SDValue CurrentOp = SrcOp->getOperand(i);
16681 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16682 Elts.push_back(CurrentOp);
16685 ND = cast<ConstantSDNode>(CurrentOp);
16686 const APInt &C = ND->getAPIntValue();
16687 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
16690 case X86ISD::VSRAI:
16691 for (unsigned i=0; i!=NumElts; ++i) {
16692 SDValue CurrentOp = SrcOp->getOperand(i);
16693 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16694 Elts.push_back(CurrentOp);
16697 ND = cast<ConstantSDNode>(CurrentOp);
16698 const APInt &C = ND->getAPIntValue();
16699 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
16704 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16707 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
16710 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16711 // may or may not be a constant. Takes immediate version of shift as input.
16712 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16713 SDValue SrcOp, SDValue ShAmt,
16714 SelectionDAG &DAG) {
16715 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
16717 // Catch shift-by-constant.
16718 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16719 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16720 CShAmt->getZExtValue(), DAG);
16722 // Change opcode to non-immediate version
16724 default: llvm_unreachable("Unknown target vector shift node");
16725 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16726 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16727 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16730 // Need to build a vector containing shift amount
16731 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
16734 ShOps[1] = DAG.getConstant(0, MVT::i32);
16735 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
16736 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
16738 // The return type has to be a 128-bit type with the same element
16739 // type as the input type.
16740 MVT EltVT = VT.getVectorElementType();
16741 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16743 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
16744 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16747 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16748 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16749 /// necessary casting for \p Mask when lowering masking intrinsics.
16750 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16751 SDValue PreservedSrc,
16752 const X86Subtarget *Subtarget,
16753 SelectionDAG &DAG) {
16754 EVT VT = Op.getValueType();
16755 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16756 MVT::i1, VT.getVectorNumElements());
16757 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16758 Mask.getValueType().getSizeInBits());
16761 assert(MaskVT.isSimple() && "invalid mask type");
16763 if (isAllOnes(Mask))
16766 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16767 // are extracted by EXTRACT_SUBVECTOR.
16768 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16769 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16770 DAG.getIntPtrConstant(0));
16772 switch (Op.getOpcode()) {
16774 case X86ISD::PCMPEQM:
16775 case X86ISD::PCMPGTM:
16777 case X86ISD::CMPMU:
16778 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16780 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16781 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16782 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
16785 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
16786 SDValue PreservedSrc,
16787 const X86Subtarget *Subtarget,
16788 SelectionDAG &DAG) {
16789 if (isAllOnes(Mask))
16792 EVT VT = Op.getValueType();
16794 // The mask should be of type MVT::i1
16795 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
16797 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16798 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16799 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
16802 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
16804 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16805 case Intrinsic::x86_fma_vfmadd_ps:
16806 case Intrinsic::x86_fma_vfmadd_pd:
16807 case Intrinsic::x86_fma_vfmadd_ps_256:
16808 case Intrinsic::x86_fma_vfmadd_pd_256:
16809 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16810 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16811 return X86ISD::FMADD;
16812 case Intrinsic::x86_fma_vfmsub_ps:
16813 case Intrinsic::x86_fma_vfmsub_pd:
16814 case Intrinsic::x86_fma_vfmsub_ps_256:
16815 case Intrinsic::x86_fma_vfmsub_pd_256:
16816 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16817 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16818 return X86ISD::FMSUB;
16819 case Intrinsic::x86_fma_vfnmadd_ps:
16820 case Intrinsic::x86_fma_vfnmadd_pd:
16821 case Intrinsic::x86_fma_vfnmadd_ps_256:
16822 case Intrinsic::x86_fma_vfnmadd_pd_256:
16823 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16824 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16825 return X86ISD::FNMADD;
16826 case Intrinsic::x86_fma_vfnmsub_ps:
16827 case Intrinsic::x86_fma_vfnmsub_pd:
16828 case Intrinsic::x86_fma_vfnmsub_ps_256:
16829 case Intrinsic::x86_fma_vfnmsub_pd_256:
16830 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16831 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16832 return X86ISD::FNMSUB;
16833 case Intrinsic::x86_fma_vfmaddsub_ps:
16834 case Intrinsic::x86_fma_vfmaddsub_pd:
16835 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16836 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16837 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16838 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16839 return X86ISD::FMADDSUB;
16840 case Intrinsic::x86_fma_vfmsubadd_ps:
16841 case Intrinsic::x86_fma_vfmsubadd_pd:
16842 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16843 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16844 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16845 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16846 return X86ISD::FMSUBADD;
16850 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16851 SelectionDAG &DAG) {
16853 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16854 EVT VT = Op.getValueType();
16855 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16857 switch(IntrData->Type) {
16858 case INTR_TYPE_1OP:
16859 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16860 case INTR_TYPE_2OP:
16861 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16863 case INTR_TYPE_3OP:
16864 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16865 Op.getOperand(2), Op.getOperand(3));
16866 case INTR_TYPE_1OP_MASK_RM: {
16867 SDValue Src = Op.getOperand(1);
16868 SDValue Src0 = Op.getOperand(2);
16869 SDValue Mask = Op.getOperand(3);
16870 SDValue RoundingMode = Op.getOperand(4);
16871 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16873 Mask, Src0, Subtarget, DAG);
16875 case INTR_TYPE_SCALAR_MASK_RM: {
16876 SDValue Src1 = Op.getOperand(1);
16877 SDValue Src2 = Op.getOperand(2);
16878 SDValue Src0 = Op.getOperand(3);
16879 SDValue Mask = Op.getOperand(4);
16880 SDValue RoundingMode = Op.getOperand(5);
16881 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16883 Mask, Src0, Subtarget, DAG);
16885 case INTR_TYPE_2OP_MASK: {
16886 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Op.getOperand(1),
16888 Op.getOperand(4), Op.getOperand(3), Subtarget, DAG);
16891 case CMP_MASK_CC: {
16892 // Comparison intrinsics with masks.
16893 // Example of transformation:
16894 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16895 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16897 // (v8i1 (insert_subvector undef,
16898 // (v2i1 (and (PCMPEQM %a, %b),
16899 // (extract_subvector
16900 // (v8i1 (bitcast %mask)), 0))), 0))))
16901 EVT VT = Op.getOperand(1).getValueType();
16902 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16903 VT.getVectorNumElements());
16904 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16905 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16906 Mask.getValueType().getSizeInBits());
16908 if (IntrData->Type == CMP_MASK_CC) {
16909 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16910 Op.getOperand(2), Op.getOperand(3));
16912 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16913 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16916 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16917 DAG.getTargetConstant(0, MaskVT),
16919 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16920 DAG.getUNDEF(BitcastVT), CmpMask,
16921 DAG.getIntPtrConstant(0));
16922 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
16924 case COMI: { // Comparison intrinsics
16925 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16926 SDValue LHS = Op.getOperand(1);
16927 SDValue RHS = Op.getOperand(2);
16928 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
16929 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16930 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16931 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16932 DAG.getConstant(X86CC, MVT::i8), Cond);
16933 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16936 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16937 Op.getOperand(1), Op.getOperand(2), DAG);
16939 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16940 Op.getOperand(1), Op.getOperand(2), DAG),
16941 Op.getOperand(4), Op.getOperand(3), Subtarget, DAG);
16948 default: return SDValue(); // Don't custom lower most intrinsics.
16950 // Arithmetic intrinsics.
16951 case Intrinsic::x86_sse2_pmulu_dq:
16952 case Intrinsic::x86_avx2_pmulu_dq:
16953 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
16954 Op.getOperand(1), Op.getOperand(2));
16956 case Intrinsic::x86_sse41_pmuldq:
16957 case Intrinsic::x86_avx2_pmul_dq:
16958 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
16959 Op.getOperand(1), Op.getOperand(2));
16961 case Intrinsic::x86_sse2_pmulhu_w:
16962 case Intrinsic::x86_avx2_pmulhu_w:
16963 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
16964 Op.getOperand(1), Op.getOperand(2));
16966 case Intrinsic::x86_sse2_pmulh_w:
16967 case Intrinsic::x86_avx2_pmulh_w:
16968 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
16969 Op.getOperand(1), Op.getOperand(2));
16971 // SSE/SSE2/AVX floating point max/min intrinsics.
16972 case Intrinsic::x86_sse_max_ps:
16973 case Intrinsic::x86_sse2_max_pd:
16974 case Intrinsic::x86_avx_max_ps_256:
16975 case Intrinsic::x86_avx_max_pd_256:
16976 case Intrinsic::x86_sse_min_ps:
16977 case Intrinsic::x86_sse2_min_pd:
16978 case Intrinsic::x86_avx_min_ps_256:
16979 case Intrinsic::x86_avx_min_pd_256: {
16982 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16983 case Intrinsic::x86_sse_max_ps:
16984 case Intrinsic::x86_sse2_max_pd:
16985 case Intrinsic::x86_avx_max_ps_256:
16986 case Intrinsic::x86_avx_max_pd_256:
16987 Opcode = X86ISD::FMAX;
16989 case Intrinsic::x86_sse_min_ps:
16990 case Intrinsic::x86_sse2_min_pd:
16991 case Intrinsic::x86_avx_min_ps_256:
16992 case Intrinsic::x86_avx_min_pd_256:
16993 Opcode = X86ISD::FMIN;
16996 return DAG.getNode(Opcode, dl, Op.getValueType(),
16997 Op.getOperand(1), Op.getOperand(2));
17000 // AVX2 variable shift intrinsics
17001 case Intrinsic::x86_avx2_psllv_d:
17002 case Intrinsic::x86_avx2_psllv_q:
17003 case Intrinsic::x86_avx2_psllv_d_256:
17004 case Intrinsic::x86_avx2_psllv_q_256:
17005 case Intrinsic::x86_avx2_psrlv_d:
17006 case Intrinsic::x86_avx2_psrlv_q:
17007 case Intrinsic::x86_avx2_psrlv_d_256:
17008 case Intrinsic::x86_avx2_psrlv_q_256:
17009 case Intrinsic::x86_avx2_psrav_d:
17010 case Intrinsic::x86_avx2_psrav_d_256: {
17013 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
17014 case Intrinsic::x86_avx2_psllv_d:
17015 case Intrinsic::x86_avx2_psllv_q:
17016 case Intrinsic::x86_avx2_psllv_d_256:
17017 case Intrinsic::x86_avx2_psllv_q_256:
17020 case Intrinsic::x86_avx2_psrlv_d:
17021 case Intrinsic::x86_avx2_psrlv_q:
17022 case Intrinsic::x86_avx2_psrlv_d_256:
17023 case Intrinsic::x86_avx2_psrlv_q_256:
17026 case Intrinsic::x86_avx2_psrav_d:
17027 case Intrinsic::x86_avx2_psrav_d_256:
17031 return DAG.getNode(Opcode, dl, Op.getValueType(),
17032 Op.getOperand(1), Op.getOperand(2));
17035 case Intrinsic::x86_sse2_packssdw_128:
17036 case Intrinsic::x86_sse2_packsswb_128:
17037 case Intrinsic::x86_avx2_packssdw:
17038 case Intrinsic::x86_avx2_packsswb:
17039 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
17040 Op.getOperand(1), Op.getOperand(2));
17042 case Intrinsic::x86_sse2_packuswb_128:
17043 case Intrinsic::x86_sse41_packusdw:
17044 case Intrinsic::x86_avx2_packuswb:
17045 case Intrinsic::x86_avx2_packusdw:
17046 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
17047 Op.getOperand(1), Op.getOperand(2));
17049 case Intrinsic::x86_ssse3_pshuf_b_128:
17050 case Intrinsic::x86_avx2_pshuf_b:
17051 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
17052 Op.getOperand(1), Op.getOperand(2));
17054 case Intrinsic::x86_sse2_pshuf_d:
17055 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
17056 Op.getOperand(1), Op.getOperand(2));
17058 case Intrinsic::x86_sse2_pshufl_w:
17059 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
17060 Op.getOperand(1), Op.getOperand(2));
17062 case Intrinsic::x86_sse2_pshufh_w:
17063 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
17064 Op.getOperand(1), Op.getOperand(2));
17066 case Intrinsic::x86_ssse3_psign_b_128:
17067 case Intrinsic::x86_ssse3_psign_w_128:
17068 case Intrinsic::x86_ssse3_psign_d_128:
17069 case Intrinsic::x86_avx2_psign_b:
17070 case Intrinsic::x86_avx2_psign_w:
17071 case Intrinsic::x86_avx2_psign_d:
17072 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
17073 Op.getOperand(1), Op.getOperand(2));
17075 case Intrinsic::x86_avx2_permd:
17076 case Intrinsic::x86_avx2_permps:
17077 // Operands intentionally swapped. Mask is last operand to intrinsic,
17078 // but second operand for node/instruction.
17079 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
17080 Op.getOperand(2), Op.getOperand(1));
17082 case Intrinsic::x86_avx512_mask_valign_q_512:
17083 case Intrinsic::x86_avx512_mask_valign_d_512:
17084 // Vector source operands are swapped.
17085 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
17086 Op.getValueType(), Op.getOperand(2),
17089 Op.getOperand(5), Op.getOperand(4),
17092 // ptest and testp intrinsics. The intrinsic these come from are designed to
17093 // return an integer value, not just an instruction so lower it to the ptest
17094 // or testp pattern and a setcc for the result.
17095 case Intrinsic::x86_sse41_ptestz:
17096 case Intrinsic::x86_sse41_ptestc:
17097 case Intrinsic::x86_sse41_ptestnzc:
17098 case Intrinsic::x86_avx_ptestz_256:
17099 case Intrinsic::x86_avx_ptestc_256:
17100 case Intrinsic::x86_avx_ptestnzc_256:
17101 case Intrinsic::x86_avx_vtestz_ps:
17102 case Intrinsic::x86_avx_vtestc_ps:
17103 case Intrinsic::x86_avx_vtestnzc_ps:
17104 case Intrinsic::x86_avx_vtestz_pd:
17105 case Intrinsic::x86_avx_vtestc_pd:
17106 case Intrinsic::x86_avx_vtestnzc_pd:
17107 case Intrinsic::x86_avx_vtestz_ps_256:
17108 case Intrinsic::x86_avx_vtestc_ps_256:
17109 case Intrinsic::x86_avx_vtestnzc_ps_256:
17110 case Intrinsic::x86_avx_vtestz_pd_256:
17111 case Intrinsic::x86_avx_vtestc_pd_256:
17112 case Intrinsic::x86_avx_vtestnzc_pd_256: {
17113 bool IsTestPacked = false;
17116 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
17117 case Intrinsic::x86_avx_vtestz_ps:
17118 case Intrinsic::x86_avx_vtestz_pd:
17119 case Intrinsic::x86_avx_vtestz_ps_256:
17120 case Intrinsic::x86_avx_vtestz_pd_256:
17121 IsTestPacked = true; // Fallthrough
17122 case Intrinsic::x86_sse41_ptestz:
17123 case Intrinsic::x86_avx_ptestz_256:
17125 X86CC = X86::COND_E;
17127 case Intrinsic::x86_avx_vtestc_ps:
17128 case Intrinsic::x86_avx_vtestc_pd:
17129 case Intrinsic::x86_avx_vtestc_ps_256:
17130 case Intrinsic::x86_avx_vtestc_pd_256:
17131 IsTestPacked = true; // Fallthrough
17132 case Intrinsic::x86_sse41_ptestc:
17133 case Intrinsic::x86_avx_ptestc_256:
17135 X86CC = X86::COND_B;
17137 case Intrinsic::x86_avx_vtestnzc_ps:
17138 case Intrinsic::x86_avx_vtestnzc_pd:
17139 case Intrinsic::x86_avx_vtestnzc_ps_256:
17140 case Intrinsic::x86_avx_vtestnzc_pd_256:
17141 IsTestPacked = true; // Fallthrough
17142 case Intrinsic::x86_sse41_ptestnzc:
17143 case Intrinsic::x86_avx_ptestnzc_256:
17145 X86CC = X86::COND_A;
17149 SDValue LHS = Op.getOperand(1);
17150 SDValue RHS = Op.getOperand(2);
17151 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
17152 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
17153 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17154 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
17155 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17157 case Intrinsic::x86_avx512_kortestz_w:
17158 case Intrinsic::x86_avx512_kortestc_w: {
17159 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
17160 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
17161 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
17162 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17163 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
17164 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
17165 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17168 case Intrinsic::x86_sse42_pcmpistria128:
17169 case Intrinsic::x86_sse42_pcmpestria128:
17170 case Intrinsic::x86_sse42_pcmpistric128:
17171 case Intrinsic::x86_sse42_pcmpestric128:
17172 case Intrinsic::x86_sse42_pcmpistrio128:
17173 case Intrinsic::x86_sse42_pcmpestrio128:
17174 case Intrinsic::x86_sse42_pcmpistris128:
17175 case Intrinsic::x86_sse42_pcmpestris128:
17176 case Intrinsic::x86_sse42_pcmpistriz128:
17177 case Intrinsic::x86_sse42_pcmpestriz128: {
17181 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
17182 case Intrinsic::x86_sse42_pcmpistria128:
17183 Opcode = X86ISD::PCMPISTRI;
17184 X86CC = X86::COND_A;
17186 case Intrinsic::x86_sse42_pcmpestria128:
17187 Opcode = X86ISD::PCMPESTRI;
17188 X86CC = X86::COND_A;
17190 case Intrinsic::x86_sse42_pcmpistric128:
17191 Opcode = X86ISD::PCMPISTRI;
17192 X86CC = X86::COND_B;
17194 case Intrinsic::x86_sse42_pcmpestric128:
17195 Opcode = X86ISD::PCMPESTRI;
17196 X86CC = X86::COND_B;
17198 case Intrinsic::x86_sse42_pcmpistrio128:
17199 Opcode = X86ISD::PCMPISTRI;
17200 X86CC = X86::COND_O;
17202 case Intrinsic::x86_sse42_pcmpestrio128:
17203 Opcode = X86ISD::PCMPESTRI;
17204 X86CC = X86::COND_O;
17206 case Intrinsic::x86_sse42_pcmpistris128:
17207 Opcode = X86ISD::PCMPISTRI;
17208 X86CC = X86::COND_S;
17210 case Intrinsic::x86_sse42_pcmpestris128:
17211 Opcode = X86ISD::PCMPESTRI;
17212 X86CC = X86::COND_S;
17214 case Intrinsic::x86_sse42_pcmpistriz128:
17215 Opcode = X86ISD::PCMPISTRI;
17216 X86CC = X86::COND_E;
17218 case Intrinsic::x86_sse42_pcmpestriz128:
17219 Opcode = X86ISD::PCMPESTRI;
17220 X86CC = X86::COND_E;
17223 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17224 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17225 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
17226 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17227 DAG.getConstant(X86CC, MVT::i8),
17228 SDValue(PCMP.getNode(), 1));
17229 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17232 case Intrinsic::x86_sse42_pcmpistri128:
17233 case Intrinsic::x86_sse42_pcmpestri128: {
17235 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
17236 Opcode = X86ISD::PCMPISTRI;
17238 Opcode = X86ISD::PCMPESTRI;
17240 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17241 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17242 return DAG.getNode(Opcode, dl, VTs, NewOps);
17245 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
17246 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
17247 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
17248 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
17249 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
17250 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
17251 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
17252 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
17253 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
17254 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
17255 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
17256 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
17257 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
17258 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
17259 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
17260 dl, Op.getValueType(),
17264 Op.getOperand(4), Op.getOperand(1),
17270 case Intrinsic::x86_fma_vfmadd_ps:
17271 case Intrinsic::x86_fma_vfmadd_pd:
17272 case Intrinsic::x86_fma_vfmsub_ps:
17273 case Intrinsic::x86_fma_vfmsub_pd:
17274 case Intrinsic::x86_fma_vfnmadd_ps:
17275 case Intrinsic::x86_fma_vfnmadd_pd:
17276 case Intrinsic::x86_fma_vfnmsub_ps:
17277 case Intrinsic::x86_fma_vfnmsub_pd:
17278 case Intrinsic::x86_fma_vfmaddsub_ps:
17279 case Intrinsic::x86_fma_vfmaddsub_pd:
17280 case Intrinsic::x86_fma_vfmsubadd_ps:
17281 case Intrinsic::x86_fma_vfmsubadd_pd:
17282 case Intrinsic::x86_fma_vfmadd_ps_256:
17283 case Intrinsic::x86_fma_vfmadd_pd_256:
17284 case Intrinsic::x86_fma_vfmsub_ps_256:
17285 case Intrinsic::x86_fma_vfmsub_pd_256:
17286 case Intrinsic::x86_fma_vfnmadd_ps_256:
17287 case Intrinsic::x86_fma_vfnmadd_pd_256:
17288 case Intrinsic::x86_fma_vfnmsub_ps_256:
17289 case Intrinsic::x86_fma_vfnmsub_pd_256:
17290 case Intrinsic::x86_fma_vfmaddsub_ps_256:
17291 case Intrinsic::x86_fma_vfmaddsub_pd_256:
17292 case Intrinsic::x86_fma_vfmsubadd_ps_256:
17293 case Intrinsic::x86_fma_vfmsubadd_pd_256:
17294 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
17295 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
17299 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17300 SDValue Src, SDValue Mask, SDValue Base,
17301 SDValue Index, SDValue ScaleOp, SDValue Chain,
17302 const X86Subtarget * Subtarget) {
17304 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17305 assert(C && "Invalid scale type");
17306 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17307 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17308 Index.getSimpleValueType().getVectorNumElements());
17310 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17312 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17314 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17315 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
17316 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17317 SDValue Segment = DAG.getRegister(0, MVT::i32);
17318 if (Src.getOpcode() == ISD::UNDEF)
17319 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
17320 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17321 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17322 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
17323 return DAG.getMergeValues(RetOps, dl);
17326 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17327 SDValue Src, SDValue Mask, SDValue Base,
17328 SDValue Index, SDValue ScaleOp, SDValue Chain) {
17330 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17331 assert(C && "Invalid scale type");
17332 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17333 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17334 SDValue Segment = DAG.getRegister(0, MVT::i32);
17335 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17336 Index.getSimpleValueType().getVectorNumElements());
17338 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17340 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17342 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17343 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
17344 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
17345 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17346 return SDValue(Res, 1);
17349 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17350 SDValue Mask, SDValue Base, SDValue Index,
17351 SDValue ScaleOp, SDValue Chain) {
17353 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17354 assert(C && "Invalid scale type");
17355 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17356 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17357 SDValue Segment = DAG.getRegister(0, MVT::i32);
17359 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
17361 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17363 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17365 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17366 //SDVTList VTs = DAG.getVTList(MVT::Other);
17367 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17368 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
17369 return SDValue(Res, 0);
17372 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
17373 // read performance monitor counters (x86_rdpmc).
17374 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
17375 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17376 SmallVectorImpl<SDValue> &Results) {
17377 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17378 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17381 // The ECX register is used to select the index of the performance counter
17383 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
17385 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
17387 // Reads the content of a 64-bit performance counter and returns it in the
17388 // registers EDX:EAX.
17389 if (Subtarget->is64Bit()) {
17390 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17391 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17394 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17395 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17398 Chain = HI.getValue(1);
17400 if (Subtarget->is64Bit()) {
17401 // The EAX register is loaded with the low-order 32 bits. The EDX register
17402 // is loaded with the supported high-order bits of the counter.
17403 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17404 DAG.getConstant(32, MVT::i8));
17405 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17406 Results.push_back(Chain);
17410 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17411 SDValue Ops[] = { LO, HI };
17412 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17413 Results.push_back(Pair);
17414 Results.push_back(Chain);
17417 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
17418 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
17419 // also used to custom lower READCYCLECOUNTER nodes.
17420 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
17421 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17422 SmallVectorImpl<SDValue> &Results) {
17423 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17424 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
17427 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
17428 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
17429 // and the EAX register is loaded with the low-order 32 bits.
17430 if (Subtarget->is64Bit()) {
17431 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17432 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17435 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17436 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17439 SDValue Chain = HI.getValue(1);
17441 if (Opcode == X86ISD::RDTSCP_DAG) {
17442 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17444 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
17445 // the ECX register. Add 'ecx' explicitly to the chain.
17446 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
17448 // Explicitly store the content of ECX at the location passed in input
17449 // to the 'rdtscp' intrinsic.
17450 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
17451 MachinePointerInfo(), false, false, 0);
17454 if (Subtarget->is64Bit()) {
17455 // The EDX register is loaded with the high-order 32 bits of the MSR, and
17456 // the EAX register is loaded with the low-order 32 bits.
17457 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17458 DAG.getConstant(32, MVT::i8));
17459 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17460 Results.push_back(Chain);
17464 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17465 SDValue Ops[] = { LO, HI };
17466 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17467 Results.push_back(Pair);
17468 Results.push_back(Chain);
17471 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17472 SelectionDAG &DAG) {
17473 SmallVector<SDValue, 2> Results;
17475 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17477 return DAG.getMergeValues(Results, DL);
17481 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17482 SelectionDAG &DAG) {
17483 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17485 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17490 switch(IntrData->Type) {
17492 llvm_unreachable("Unknown Intrinsic Type");
17496 // Emit the node with the right value type.
17497 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17498 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17500 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17501 // Otherwise return the value from Rand, which is always 0, casted to i32.
17502 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17503 DAG.getConstant(1, Op->getValueType(1)),
17504 DAG.getConstant(X86::COND_B, MVT::i32),
17505 SDValue(Result.getNode(), 1) };
17506 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17507 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17510 // Return { result, isValid, chain }.
17511 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17512 SDValue(Result.getNode(), 2));
17515 //gather(v1, mask, index, base, scale);
17516 SDValue Chain = Op.getOperand(0);
17517 SDValue Src = Op.getOperand(2);
17518 SDValue Base = Op.getOperand(3);
17519 SDValue Index = Op.getOperand(4);
17520 SDValue Mask = Op.getOperand(5);
17521 SDValue Scale = Op.getOperand(6);
17522 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
17526 //scatter(base, mask, index, v1, scale);
17527 SDValue Chain = Op.getOperand(0);
17528 SDValue Base = Op.getOperand(2);
17529 SDValue Mask = Op.getOperand(3);
17530 SDValue Index = Op.getOperand(4);
17531 SDValue Src = Op.getOperand(5);
17532 SDValue Scale = Op.getOperand(6);
17533 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
17536 SDValue Hint = Op.getOperand(6);
17538 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
17539 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
17540 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
17541 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17542 SDValue Chain = Op.getOperand(0);
17543 SDValue Mask = Op.getOperand(2);
17544 SDValue Index = Op.getOperand(3);
17545 SDValue Base = Op.getOperand(4);
17546 SDValue Scale = Op.getOperand(5);
17547 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17549 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17551 SmallVector<SDValue, 2> Results;
17552 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
17553 return DAG.getMergeValues(Results, dl);
17555 // Read Performance Monitoring Counters.
17557 SmallVector<SDValue, 2> Results;
17558 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17559 return DAG.getMergeValues(Results, dl);
17561 // XTEST intrinsics.
17563 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17564 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17565 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17566 DAG.getConstant(X86::COND_NE, MVT::i8),
17568 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17569 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17570 Ret, SDValue(InTrans.getNode(), 1));
17574 SmallVector<SDValue, 2> Results;
17575 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17576 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17577 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17578 DAG.getConstant(-1, MVT::i8));
17579 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17580 Op.getOperand(4), GenCF.getValue(1));
17581 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17582 Op.getOperand(5), MachinePointerInfo(),
17584 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17585 DAG.getConstant(X86::COND_B, MVT::i8),
17587 Results.push_back(SetCC);
17588 Results.push_back(Store);
17589 return DAG.getMergeValues(Results, dl);
17594 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17595 SelectionDAG &DAG) const {
17596 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17597 MFI->setReturnAddressIsTaken(true);
17599 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17602 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17604 EVT PtrVT = getPointerTy();
17607 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17608 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17609 DAG.getSubtarget().getRegisterInfo());
17610 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
17611 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17612 DAG.getNode(ISD::ADD, dl, PtrVT,
17613 FrameAddr, Offset),
17614 MachinePointerInfo(), false, false, false, 0);
17617 // Just load the return address.
17618 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17619 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17620 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17623 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17624 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17625 MFI->setFrameAddressIsTaken(true);
17627 EVT VT = Op.getValueType();
17628 SDLoc dl(Op); // FIXME probably not meaningful
17629 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17630 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17631 DAG.getSubtarget().getRegisterInfo());
17632 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17633 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17634 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17635 "Invalid Frame Register!");
17636 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17638 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17639 MachinePointerInfo(),
17640 false, false, false, 0);
17644 // FIXME? Maybe this could be a TableGen attribute on some registers and
17645 // this table could be generated automatically from RegInfo.
17646 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
17648 unsigned Reg = StringSwitch<unsigned>(RegName)
17649 .Case("esp", X86::ESP)
17650 .Case("rsp", X86::RSP)
17654 report_fatal_error("Invalid register name global variable");
17657 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17658 SelectionDAG &DAG) const {
17659 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17660 DAG.getSubtarget().getRegisterInfo());
17661 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
17664 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17665 SDValue Chain = Op.getOperand(0);
17666 SDValue Offset = Op.getOperand(1);
17667 SDValue Handler = Op.getOperand(2);
17670 EVT PtrVT = getPointerTy();
17671 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17672 DAG.getSubtarget().getRegisterInfo());
17673 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17674 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17675 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17676 "Invalid Frame Register!");
17677 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17678 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17680 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17681 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
17682 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17683 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17685 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17687 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17688 DAG.getRegister(StoreAddrReg, PtrVT));
17691 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17692 SelectionDAG &DAG) const {
17694 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17695 DAG.getVTList(MVT::i32, MVT::Other),
17696 Op.getOperand(0), Op.getOperand(1));
17699 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17700 SelectionDAG &DAG) const {
17702 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17703 Op.getOperand(0), Op.getOperand(1));
17706 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17707 return Op.getOperand(0);
17710 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17711 SelectionDAG &DAG) const {
17712 SDValue Root = Op.getOperand(0);
17713 SDValue Trmp = Op.getOperand(1); // trampoline
17714 SDValue FPtr = Op.getOperand(2); // nested function
17715 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17718 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17719 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
17721 if (Subtarget->is64Bit()) {
17722 SDValue OutChains[6];
17724 // Large code-model.
17725 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17726 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17728 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17729 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17731 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17733 // Load the pointer to the nested function into R11.
17734 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17735 SDValue Addr = Trmp;
17736 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17737 Addr, MachinePointerInfo(TrmpAddr),
17740 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17741 DAG.getConstant(2, MVT::i64));
17742 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17743 MachinePointerInfo(TrmpAddr, 2),
17746 // Load the 'nest' parameter value into R10.
17747 // R10 is specified in X86CallingConv.td
17748 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17749 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17750 DAG.getConstant(10, MVT::i64));
17751 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17752 Addr, MachinePointerInfo(TrmpAddr, 10),
17755 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17756 DAG.getConstant(12, MVT::i64));
17757 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17758 MachinePointerInfo(TrmpAddr, 12),
17761 // Jump to the nested function.
17762 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17763 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17764 DAG.getConstant(20, MVT::i64));
17765 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17766 Addr, MachinePointerInfo(TrmpAddr, 20),
17769 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17770 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17771 DAG.getConstant(22, MVT::i64));
17772 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
17773 MachinePointerInfo(TrmpAddr, 22),
17776 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17778 const Function *Func =
17779 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17780 CallingConv::ID CC = Func->getCallingConv();
17785 llvm_unreachable("Unsupported calling convention");
17786 case CallingConv::C:
17787 case CallingConv::X86_StdCall: {
17788 // Pass 'nest' parameter in ECX.
17789 // Must be kept in sync with X86CallingConv.td
17790 NestReg = X86::ECX;
17792 // Check that ECX wasn't needed by an 'inreg' parameter.
17793 FunctionType *FTy = Func->getFunctionType();
17794 const AttributeSet &Attrs = Func->getAttributes();
17796 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17797 unsigned InRegCount = 0;
17800 for (FunctionType::param_iterator I = FTy->param_begin(),
17801 E = FTy->param_end(); I != E; ++I, ++Idx)
17802 if (Attrs.hasAttribute(Idx, Attribute::InReg))
17803 // FIXME: should only count parameters that are lowered to integers.
17804 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
17806 if (InRegCount > 2) {
17807 report_fatal_error("Nest register in use - reduce number of inreg"
17813 case CallingConv::X86_FastCall:
17814 case CallingConv::X86_ThisCall:
17815 case CallingConv::Fast:
17816 // Pass 'nest' parameter in EAX.
17817 // Must be kept in sync with X86CallingConv.td
17818 NestReg = X86::EAX;
17822 SDValue OutChains[4];
17823 SDValue Addr, Disp;
17825 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17826 DAG.getConstant(10, MVT::i32));
17827 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17829 // This is storing the opcode for MOV32ri.
17830 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17831 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17832 OutChains[0] = DAG.getStore(Root, dl,
17833 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
17834 Trmp, MachinePointerInfo(TrmpAddr),
17837 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17838 DAG.getConstant(1, MVT::i32));
17839 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17840 MachinePointerInfo(TrmpAddr, 1),
17843 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17844 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17845 DAG.getConstant(5, MVT::i32));
17846 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17847 MachinePointerInfo(TrmpAddr, 5),
17850 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17851 DAG.getConstant(6, MVT::i32));
17852 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17853 MachinePointerInfo(TrmpAddr, 6),
17856 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17860 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17861 SelectionDAG &DAG) const {
17863 The rounding mode is in bits 11:10 of FPSR, and has the following
17865 00 Round to nearest
17870 FLT_ROUNDS, on the other hand, expects the following:
17877 To perform the conversion, we do:
17878 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17881 MachineFunction &MF = DAG.getMachineFunction();
17882 const TargetMachine &TM = MF.getTarget();
17883 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17884 unsigned StackAlignment = TFI.getStackAlignment();
17885 MVT VT = Op.getSimpleValueType();
17888 // Save FP Control Word to stack slot
17889 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17890 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
17892 MachineMemOperand *MMO =
17893 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
17894 MachineMemOperand::MOStore, 2, 2);
17896 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17897 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17898 DAG.getVTList(MVT::Other),
17899 Ops, MVT::i16, MMO);
17901 // Load FP Control Word from stack slot
17902 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17903 MachinePointerInfo(), false, false, false, 0);
17905 // Transform as necessary
17907 DAG.getNode(ISD::SRL, DL, MVT::i16,
17908 DAG.getNode(ISD::AND, DL, MVT::i16,
17909 CWD, DAG.getConstant(0x800, MVT::i16)),
17910 DAG.getConstant(11, MVT::i8));
17912 DAG.getNode(ISD::SRL, DL, MVT::i16,
17913 DAG.getNode(ISD::AND, DL, MVT::i16,
17914 CWD, DAG.getConstant(0x400, MVT::i16)),
17915 DAG.getConstant(9, MVT::i8));
17918 DAG.getNode(ISD::AND, DL, MVT::i16,
17919 DAG.getNode(ISD::ADD, DL, MVT::i16,
17920 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17921 DAG.getConstant(1, MVT::i16)),
17922 DAG.getConstant(3, MVT::i16));
17924 return DAG.getNode((VT.getSizeInBits() < 16 ?
17925 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17928 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17929 MVT VT = Op.getSimpleValueType();
17931 unsigned NumBits = VT.getSizeInBits();
17934 Op = Op.getOperand(0);
17935 if (VT == MVT::i8) {
17936 // Zero extend to i32 since there is not an i8 bsr.
17938 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17941 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17942 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17943 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17945 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17948 DAG.getConstant(NumBits+NumBits-1, OpVT),
17949 DAG.getConstant(X86::COND_E, MVT::i8),
17952 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17954 // Finally xor with NumBits-1.
17955 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17958 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17962 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17963 MVT VT = Op.getSimpleValueType();
17965 unsigned NumBits = VT.getSizeInBits();
17968 Op = Op.getOperand(0);
17969 if (VT == MVT::i8) {
17970 // Zero extend to i32 since there is not an i8 bsr.
17972 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17975 // Issue a bsr (scan bits in reverse).
17976 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17977 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17979 // And xor with NumBits-1.
17980 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17983 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17987 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17988 MVT VT = Op.getSimpleValueType();
17989 unsigned NumBits = VT.getSizeInBits();
17991 Op = Op.getOperand(0);
17993 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17994 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17995 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
17997 // If src is zero (i.e. bsf sets ZF), returns NumBits.
18000 DAG.getConstant(NumBits, VT),
18001 DAG.getConstant(X86::COND_E, MVT::i8),
18004 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
18007 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
18008 // ones, and then concatenate the result back.
18009 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
18010 MVT VT = Op.getSimpleValueType();
18012 assert(VT.is256BitVector() && VT.isInteger() &&
18013 "Unsupported value type for operation");
18015 unsigned NumElems = VT.getVectorNumElements();
18018 // Extract the LHS vectors
18019 SDValue LHS = Op.getOperand(0);
18020 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18021 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18023 // Extract the RHS vectors
18024 SDValue RHS = Op.getOperand(1);
18025 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
18026 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
18028 MVT EltVT = VT.getVectorElementType();
18029 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18031 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
18032 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
18033 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
18036 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
18037 assert(Op.getSimpleValueType().is256BitVector() &&
18038 Op.getSimpleValueType().isInteger() &&
18039 "Only handle AVX 256-bit vector integer operation");
18040 return Lower256IntArith(Op, DAG);
18043 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
18044 assert(Op.getSimpleValueType().is256BitVector() &&
18045 Op.getSimpleValueType().isInteger() &&
18046 "Only handle AVX 256-bit vector integer operation");
18047 return Lower256IntArith(Op, DAG);
18050 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
18051 SelectionDAG &DAG) {
18053 MVT VT = Op.getSimpleValueType();
18055 // Decompose 256-bit ops into smaller 128-bit ops.
18056 if (VT.is256BitVector() && !Subtarget->hasInt256())
18057 return Lower256IntArith(Op, DAG);
18059 SDValue A = Op.getOperand(0);
18060 SDValue B = Op.getOperand(1);
18062 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
18063 if (VT == MVT::v4i32) {
18064 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
18065 "Should not custom lower when pmuldq is available!");
18067 // Extract the odd parts.
18068 static const int UnpackMask[] = { 1, -1, 3, -1 };
18069 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
18070 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
18072 // Multiply the even parts.
18073 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
18074 // Now multiply odd parts.
18075 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
18077 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
18078 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
18080 // Merge the two vectors back together with a shuffle. This expands into 2
18082 static const int ShufMask[] = { 0, 4, 2, 6 };
18083 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
18086 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
18087 "Only know how to lower V2I64/V4I64/V8I64 multiply");
18089 // Ahi = psrlqi(a, 32);
18090 // Bhi = psrlqi(b, 32);
18092 // AloBlo = pmuludq(a, b);
18093 // AloBhi = pmuludq(a, Bhi);
18094 // AhiBlo = pmuludq(Ahi, b);
18096 // AloBhi = psllqi(AloBhi, 32);
18097 // AhiBlo = psllqi(AhiBlo, 32);
18098 // return AloBlo + AloBhi + AhiBlo;
18100 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
18101 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
18103 // Bit cast to 32-bit vectors for MULUDQ
18104 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
18105 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
18106 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
18107 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
18108 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
18109 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
18111 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
18112 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
18113 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
18115 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
18116 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
18118 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
18119 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
18122 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
18123 assert(Subtarget->isTargetWin64() && "Unexpected target");
18124 EVT VT = Op.getValueType();
18125 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
18126 "Unexpected return type for lowering");
18130 switch (Op->getOpcode()) {
18131 default: llvm_unreachable("Unexpected request for libcall!");
18132 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
18133 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
18134 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
18135 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
18136 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
18137 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
18141 SDValue InChain = DAG.getEntryNode();
18143 TargetLowering::ArgListTy Args;
18144 TargetLowering::ArgListEntry Entry;
18145 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
18146 EVT ArgVT = Op->getOperand(i).getValueType();
18147 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
18148 "Unexpected argument type for lowering");
18149 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
18150 Entry.Node = StackPtr;
18151 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
18153 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18154 Entry.Ty = PointerType::get(ArgTy,0);
18155 Entry.isSExt = false;
18156 Entry.isZExt = false;
18157 Args.push_back(Entry);
18160 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
18163 TargetLowering::CallLoweringInfo CLI(DAG);
18164 CLI.setDebugLoc(dl).setChain(InChain)
18165 .setCallee(getLibcallCallingConv(LC),
18166 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
18167 Callee, std::move(Args), 0)
18168 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
18170 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
18171 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
18174 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
18175 SelectionDAG &DAG) {
18176 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
18177 EVT VT = Op0.getValueType();
18180 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
18181 (VT == MVT::v8i32 && Subtarget->hasInt256()));
18183 // PMULxD operations multiply each even value (starting at 0) of LHS with
18184 // the related value of RHS and produce a widen result.
18185 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18186 // => <2 x i64> <ae|cg>
18188 // In other word, to have all the results, we need to perform two PMULxD:
18189 // 1. one with the even values.
18190 // 2. one with the odd values.
18191 // To achieve #2, with need to place the odd values at an even position.
18193 // Place the odd value at an even position (basically, shift all values 1
18194 // step to the left):
18195 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18196 // <a|b|c|d> => <b|undef|d|undef>
18197 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18198 // <e|f|g|h> => <f|undef|h|undef>
18199 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18201 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18203 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18204 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18206 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18207 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18208 // => <2 x i64> <ae|cg>
18209 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
18210 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18211 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18212 // => <2 x i64> <bf|dh>
18213 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
18214 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18216 // Shuffle it back into the right order.
18217 SDValue Highs, Lows;
18218 if (VT == MVT::v8i32) {
18219 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18220 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18221 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18222 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18224 const int HighMask[] = {1, 5, 3, 7};
18225 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18226 const int LowMask[] = {0, 4, 2, 6};
18227 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18230 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18231 // unsigned multiply.
18232 if (IsSigned && !Subtarget->hasSSE41()) {
18234 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
18235 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18236 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18237 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18238 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18240 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18241 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18244 // The first result of MUL_LOHI is actually the low value, followed by the
18246 SDValue Ops[] = {Lows, Highs};
18247 return DAG.getMergeValues(Ops, dl);
18250 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18251 const X86Subtarget *Subtarget) {
18252 MVT VT = Op.getSimpleValueType();
18254 SDValue R = Op.getOperand(0);
18255 SDValue Amt = Op.getOperand(1);
18257 // Optimize shl/srl/sra with constant shift amount.
18258 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18259 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18260 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18262 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
18263 (Subtarget->hasInt256() &&
18264 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18265 (Subtarget->hasAVX512() &&
18266 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18267 if (Op.getOpcode() == ISD::SHL)
18268 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18270 if (Op.getOpcode() == ISD::SRL)
18271 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18273 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
18274 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18278 if (VT == MVT::v16i8) {
18279 if (Op.getOpcode() == ISD::SHL) {
18280 // Make a large shift.
18281 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18282 MVT::v8i16, R, ShiftAmt,
18284 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18285 // Zero out the rightmost bits.
18286 SmallVector<SDValue, 16> V(16,
18287 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18289 return DAG.getNode(ISD::AND, dl, VT, SHL,
18290 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18292 if (Op.getOpcode() == ISD::SRL) {
18293 // Make a large shift.
18294 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18295 MVT::v8i16, R, ShiftAmt,
18297 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18298 // Zero out the leftmost bits.
18299 SmallVector<SDValue, 16> V(16,
18300 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18302 return DAG.getNode(ISD::AND, dl, VT, SRL,
18303 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18305 if (Op.getOpcode() == ISD::SRA) {
18306 if (ShiftAmt == 7) {
18307 // R s>> 7 === R s< 0
18308 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18309 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18312 // R s>> a === ((R u>> a) ^ m) - m
18313 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18314 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
18316 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18317 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18318 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18321 llvm_unreachable("Unknown shift opcode.");
18324 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
18325 if (Op.getOpcode() == ISD::SHL) {
18326 // Make a large shift.
18327 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18328 MVT::v16i16, R, ShiftAmt,
18330 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18331 // Zero out the rightmost bits.
18332 SmallVector<SDValue, 32> V(32,
18333 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18335 return DAG.getNode(ISD::AND, dl, VT, SHL,
18336 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18338 if (Op.getOpcode() == ISD::SRL) {
18339 // Make a large shift.
18340 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18341 MVT::v16i16, R, ShiftAmt,
18343 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18344 // Zero out the leftmost bits.
18345 SmallVector<SDValue, 32> V(32,
18346 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18348 return DAG.getNode(ISD::AND, dl, VT, SRL,
18349 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18351 if (Op.getOpcode() == ISD::SRA) {
18352 if (ShiftAmt == 7) {
18353 // R s>> 7 === R s< 0
18354 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18355 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18358 // R s>> a === ((R u>> a) ^ m) - m
18359 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18360 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
18362 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18363 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18364 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18367 llvm_unreachable("Unknown shift opcode.");
18372 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18373 if (!Subtarget->is64Bit() &&
18374 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18375 Amt.getOpcode() == ISD::BITCAST &&
18376 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18377 Amt = Amt.getOperand(0);
18378 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18379 VT.getVectorNumElements();
18380 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18381 uint64_t ShiftAmt = 0;
18382 for (unsigned i = 0; i != Ratio; ++i) {
18383 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
18387 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18389 // Check remaining shift amounts.
18390 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18391 uint64_t ShAmt = 0;
18392 for (unsigned j = 0; j != Ratio; ++j) {
18393 ConstantSDNode *C =
18394 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18398 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18400 if (ShAmt != ShiftAmt)
18403 switch (Op.getOpcode()) {
18405 llvm_unreachable("Unknown shift opcode!");
18407 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18410 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18413 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18421 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18422 const X86Subtarget* Subtarget) {
18423 MVT VT = Op.getSimpleValueType();
18425 SDValue R = Op.getOperand(0);
18426 SDValue Amt = Op.getOperand(1);
18428 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
18429 VT == MVT::v4i32 || VT == MVT::v8i16 ||
18430 (Subtarget->hasInt256() &&
18431 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
18432 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18433 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18435 EVT EltVT = VT.getVectorElementType();
18437 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18438 unsigned NumElts = VT.getVectorNumElements();
18440 for (i = 0; i != NumElts; ++i) {
18441 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
18445 for (j = i; j != NumElts; ++j) {
18446 SDValue Arg = Amt.getOperand(j);
18447 if (Arg.getOpcode() == ISD::UNDEF) continue;
18448 if (Arg != Amt.getOperand(i))
18451 if (i != NumElts && j == NumElts)
18452 BaseShAmt = Amt.getOperand(i);
18454 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18455 Amt = Amt.getOperand(0);
18456 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
18457 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
18458 SDValue InVec = Amt.getOperand(0);
18459 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18460 unsigned NumElts = InVec.getValueType().getVectorNumElements();
18462 for (; i != NumElts; ++i) {
18463 SDValue Arg = InVec.getOperand(i);
18464 if (Arg.getOpcode() == ISD::UNDEF) continue;
18468 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18469 if (ConstantSDNode *C =
18470 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18471 unsigned SplatIdx =
18472 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
18473 if (C->getZExtValue() == SplatIdx)
18474 BaseShAmt = InVec.getOperand(1);
18477 if (!BaseShAmt.getNode())
18478 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
18479 DAG.getIntPtrConstant(0));
18483 if (BaseShAmt.getNode()) {
18484 if (EltVT.bitsGT(MVT::i32))
18485 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
18486 else if (EltVT.bitsLT(MVT::i32))
18487 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18489 switch (Op.getOpcode()) {
18491 llvm_unreachable("Unknown shift opcode!");
18493 switch (VT.SimpleTy) {
18494 default: return SDValue();
18503 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
18506 switch (VT.SimpleTy) {
18507 default: return SDValue();
18514 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
18517 switch (VT.SimpleTy) {
18518 default: return SDValue();
18527 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
18533 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18534 if (!Subtarget->is64Bit() &&
18535 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
18536 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
18537 Amt.getOpcode() == ISD::BITCAST &&
18538 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18539 Amt = Amt.getOperand(0);
18540 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18541 VT.getVectorNumElements();
18542 std::vector<SDValue> Vals(Ratio);
18543 for (unsigned i = 0; i != Ratio; ++i)
18544 Vals[i] = Amt.getOperand(i);
18545 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18546 for (unsigned j = 0; j != Ratio; ++j)
18547 if (Vals[j] != Amt.getOperand(i + j))
18550 switch (Op.getOpcode()) {
18552 llvm_unreachable("Unknown shift opcode!");
18554 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
18556 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
18558 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
18565 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18566 SelectionDAG &DAG) {
18567 MVT VT = Op.getSimpleValueType();
18569 SDValue R = Op.getOperand(0);
18570 SDValue Amt = Op.getOperand(1);
18573 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18574 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18576 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
18580 V = LowerScalarVariableShift(Op, DAG, Subtarget);
18584 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
18586 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
18587 if (Subtarget->hasInt256()) {
18588 if (Op.getOpcode() == ISD::SRL &&
18589 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18590 VT == MVT::v4i64 || VT == MVT::v8i32))
18592 if (Op.getOpcode() == ISD::SHL &&
18593 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18594 VT == MVT::v4i64 || VT == MVT::v8i32))
18596 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
18600 // If possible, lower this packed shift into a vector multiply instead of
18601 // expanding it into a sequence of scalar shifts.
18602 // Do this only if the vector shift count is a constant build_vector.
18603 if (Op.getOpcode() == ISD::SHL &&
18604 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18605 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18606 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18607 SmallVector<SDValue, 8> Elts;
18608 EVT SVT = VT.getScalarType();
18609 unsigned SVTBits = SVT.getSizeInBits();
18610 const APInt &One = APInt(SVTBits, 1);
18611 unsigned NumElems = VT.getVectorNumElements();
18613 for (unsigned i=0; i !=NumElems; ++i) {
18614 SDValue Op = Amt->getOperand(i);
18615 if (Op->getOpcode() == ISD::UNDEF) {
18616 Elts.push_back(Op);
18620 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18621 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18622 uint64_t ShAmt = C.getZExtValue();
18623 if (ShAmt >= SVTBits) {
18624 Elts.push_back(DAG.getUNDEF(SVT));
18627 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
18629 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18630 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18633 // Lower SHL with variable shift amount.
18634 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18635 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
18637 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
18638 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
18639 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18640 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18643 // If possible, lower this shift as a sequence of two shifts by
18644 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18646 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18648 // Could be rewritten as:
18649 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18651 // The advantage is that the two shifts from the example would be
18652 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18653 // the vector shift into four scalar shifts plus four pairs of vector
18655 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18656 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18657 unsigned TargetOpcode = X86ISD::MOVSS;
18658 bool CanBeSimplified;
18659 // The splat value for the first packed shift (the 'X' from the example).
18660 SDValue Amt1 = Amt->getOperand(0);
18661 // The splat value for the second packed shift (the 'Y' from the example).
18662 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18663 Amt->getOperand(2);
18665 // See if it is possible to replace this node with a sequence of
18666 // two shifts followed by a MOVSS/MOVSD
18667 if (VT == MVT::v4i32) {
18668 // Check if it is legal to use a MOVSS.
18669 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18670 Amt2 == Amt->getOperand(3);
18671 if (!CanBeSimplified) {
18672 // Otherwise, check if we can still simplify this node using a MOVSD.
18673 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18674 Amt->getOperand(2) == Amt->getOperand(3);
18675 TargetOpcode = X86ISD::MOVSD;
18676 Amt2 = Amt->getOperand(2);
18679 // Do similar checks for the case where the machine value type
18681 CanBeSimplified = Amt1 == Amt->getOperand(1);
18682 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18683 CanBeSimplified = Amt2 == Amt->getOperand(i);
18685 if (!CanBeSimplified) {
18686 TargetOpcode = X86ISD::MOVSD;
18687 CanBeSimplified = true;
18688 Amt2 = Amt->getOperand(4);
18689 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18690 CanBeSimplified = Amt1 == Amt->getOperand(i);
18691 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18692 CanBeSimplified = Amt2 == Amt->getOperand(j);
18696 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18697 isa<ConstantSDNode>(Amt2)) {
18698 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18699 EVT CastVT = MVT::v4i32;
18701 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
18702 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18704 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
18705 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18706 if (TargetOpcode == X86ISD::MOVSD)
18707 CastVT = MVT::v2i64;
18708 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
18709 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
18710 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18712 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
18716 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
18717 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
18720 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
18721 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
18723 // Turn 'a' into a mask suitable for VSELECT
18724 SDValue VSelM = DAG.getConstant(0x80, VT);
18725 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18726 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18728 SDValue CM1 = DAG.getConstant(0x0f, VT);
18729 SDValue CM2 = DAG.getConstant(0x3f, VT);
18731 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
18732 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
18733 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
18734 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18735 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18738 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18739 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18740 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18742 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
18743 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
18744 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
18745 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18746 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18749 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18750 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18751 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18753 // return VSELECT(r, r+r, a);
18754 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
18755 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
18759 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18760 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18761 // solution better.
18762 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18763 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
18765 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18766 R = DAG.getNode(ExtOpc, dl, NewVT, R);
18767 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
18768 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18769 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
18772 // Decompose 256-bit shifts into smaller 128-bit shifts.
18773 if (VT.is256BitVector()) {
18774 unsigned NumElems = VT.getVectorNumElements();
18775 MVT EltVT = VT.getVectorElementType();
18776 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18778 // Extract the two vectors
18779 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18780 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18782 // Recreate the shift amount vectors
18783 SDValue Amt1, Amt2;
18784 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18785 // Constant shift amount
18786 SmallVector<SDValue, 4> Amt1Csts;
18787 SmallVector<SDValue, 4> Amt2Csts;
18788 for (unsigned i = 0; i != NumElems/2; ++i)
18789 Amt1Csts.push_back(Amt->getOperand(i));
18790 for (unsigned i = NumElems/2; i != NumElems; ++i)
18791 Amt2Csts.push_back(Amt->getOperand(i));
18793 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18794 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18796 // Variable shift amount
18797 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18798 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18801 // Issue new vector shifts for the smaller types
18802 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18803 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18805 // Concatenate the result back
18806 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18812 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18813 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18814 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18815 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18816 // has only one use.
18817 SDNode *N = Op.getNode();
18818 SDValue LHS = N->getOperand(0);
18819 SDValue RHS = N->getOperand(1);
18820 unsigned BaseOp = 0;
18823 switch (Op.getOpcode()) {
18824 default: llvm_unreachable("Unknown ovf instruction!");
18826 // A subtract of one will be selected as a INC. Note that INC doesn't
18827 // set CF, so we can't do this for UADDO.
18828 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18830 BaseOp = X86ISD::INC;
18831 Cond = X86::COND_O;
18834 BaseOp = X86ISD::ADD;
18835 Cond = X86::COND_O;
18838 BaseOp = X86ISD::ADD;
18839 Cond = X86::COND_B;
18842 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18843 // set CF, so we can't do this for USUBO.
18844 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18846 BaseOp = X86ISD::DEC;
18847 Cond = X86::COND_O;
18850 BaseOp = X86ISD::SUB;
18851 Cond = X86::COND_O;
18854 BaseOp = X86ISD::SUB;
18855 Cond = X86::COND_B;
18858 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18859 Cond = X86::COND_O;
18861 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18862 if (N->getValueType(0) == MVT::i8) {
18863 BaseOp = X86ISD::UMUL8;
18864 Cond = X86::COND_O;
18867 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18869 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18872 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18873 DAG.getConstant(X86::COND_O, MVT::i32),
18874 SDValue(Sum.getNode(), 2));
18876 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18880 // Also sets EFLAGS.
18881 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18882 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18885 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18886 DAG.getConstant(Cond, MVT::i32),
18887 SDValue(Sum.getNode(), 1));
18889 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18892 // Sign extension of the low part of vector elements. This may be used either
18893 // when sign extend instructions are not available or if the vector element
18894 // sizes already match the sign-extended size. If the vector elements are in
18895 // their pre-extended size and sign extend instructions are available, that will
18896 // be handled by LowerSIGN_EXTEND.
18897 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18898 SelectionDAG &DAG) const {
18900 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18901 MVT VT = Op.getSimpleValueType();
18903 if (!Subtarget->hasSSE2() || !VT.isVector())
18906 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
18907 ExtraVT.getScalarType().getSizeInBits();
18909 switch (VT.SimpleTy) {
18910 default: return SDValue();
18913 if (!Subtarget->hasFp256())
18915 if (!Subtarget->hasInt256()) {
18916 // needs to be split
18917 unsigned NumElems = VT.getVectorNumElements();
18919 // Extract the LHS vectors
18920 SDValue LHS = Op.getOperand(0);
18921 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18922 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18924 MVT EltVT = VT.getVectorElementType();
18925 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18927 EVT ExtraEltVT = ExtraVT.getVectorElementType();
18928 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
18929 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
18931 SDValue Extra = DAG.getValueType(ExtraVT);
18933 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
18934 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
18936 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
18941 SDValue Op0 = Op.getOperand(0);
18943 // This is a sign extension of some low part of vector elements without
18944 // changing the size of the vector elements themselves:
18945 // Shift-Left + Shift-Right-Algebraic.
18946 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
18948 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
18954 /// Returns true if the operand type is exactly twice the native width, and
18955 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18956 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18957 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18958 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
18959 const X86Subtarget &Subtarget =
18960 getTargetMachine().getSubtarget<X86Subtarget>();
18961 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18964 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18965 else if (OpWidth == 128)
18966 return Subtarget.hasCmpxchg16b();
18971 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18972 return needsCmpXchgNb(SI->getValueOperand()->getType());
18975 // Note: this turns large loads into lock cmpxchg8b/16b.
18976 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18977 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18978 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18979 return needsCmpXchgNb(PTy->getElementType());
18982 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18983 const X86Subtarget &Subtarget =
18984 getTargetMachine().getSubtarget<X86Subtarget>();
18985 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18986 const Type *MemType = AI->getType();
18988 // If the operand is too big, we must see if cmpxchg8/16b is available
18989 // and default to library calls otherwise.
18990 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18991 return needsCmpXchgNb(MemType);
18993 AtomicRMWInst::BinOp Op = AI->getOperation();
18996 llvm_unreachable("Unknown atomic operation");
18997 case AtomicRMWInst::Xchg:
18998 case AtomicRMWInst::Add:
18999 case AtomicRMWInst::Sub:
19000 // It's better to use xadd, xsub or xchg for these in all cases.
19002 case AtomicRMWInst::Or:
19003 case AtomicRMWInst::And:
19004 case AtomicRMWInst::Xor:
19005 // If the atomicrmw's result isn't actually used, we can just add a "lock"
19006 // prefix to a normal instruction for these operations.
19007 return !AI->use_empty();
19008 case AtomicRMWInst::Nand:
19009 case AtomicRMWInst::Max:
19010 case AtomicRMWInst::Min:
19011 case AtomicRMWInst::UMax:
19012 case AtomicRMWInst::UMin:
19013 // These always require a non-trivial set of data operations on x86. We must
19014 // use a cmpxchg loop.
19019 static bool hasMFENCE(const X86Subtarget& Subtarget) {
19020 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
19021 // no-sse2). There isn't any reason to disable it if the target processor
19023 return Subtarget.hasSSE2() || Subtarget.is64Bit();
19027 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
19028 const X86Subtarget &Subtarget =
19029 getTargetMachine().getSubtarget<X86Subtarget>();
19030 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
19031 const Type *MemType = AI->getType();
19032 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
19033 // there is no benefit in turning such RMWs into loads, and it is actually
19034 // harmful as it introduces a mfence.
19035 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19038 auto Builder = IRBuilder<>(AI);
19039 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
19040 auto SynchScope = AI->getSynchScope();
19041 // We must restrict the ordering to avoid generating loads with Release or
19042 // ReleaseAcquire orderings.
19043 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
19044 auto Ptr = AI->getPointerOperand();
19046 // Before the load we need a fence. Here is an example lifted from
19047 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
19050 // x.store(1, relaxed);
19051 // r1 = y.fetch_add(0, release);
19053 // y.fetch_add(42, acquire);
19054 // r2 = x.load(relaxed);
19055 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
19056 // lowered to just a load without a fence. A mfence flushes the store buffer,
19057 // making the optimization clearly correct.
19058 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
19059 // otherwise, we might be able to be more agressive on relaxed idempotent
19060 // rmw. In practice, they do not look useful, so we don't try to be
19061 // especially clever.
19062 if (SynchScope == SingleThread) {
19063 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19064 // the IR level, so we must wrap it in an intrinsic.
19066 } else if (hasMFENCE(Subtarget)) {
19067 Function *MFence = llvm::Intrinsic::getDeclaration(M,
19068 Intrinsic::x86_sse2_mfence);
19069 Builder.CreateCall(MFence);
19071 // FIXME: it might make sense to use a locked operation here but on a
19072 // different cache-line to prevent cache-line bouncing. In practice it
19073 // is probably a small win, and x86 processors without mfence are rare
19074 // enough that we do not bother.
19078 // Finally we can emit the atomic load.
19079 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19080 AI->getType()->getPrimitiveSizeInBits());
19081 Loaded->setAtomic(Order, SynchScope);
19082 AI->replaceAllUsesWith(Loaded);
19083 AI->eraseFromParent();
19087 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19088 SelectionDAG &DAG) {
19090 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19091 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19092 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19093 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19095 // The only fence that needs an instruction is a sequentially-consistent
19096 // cross-thread fence.
19097 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19098 if (hasMFENCE(*Subtarget))
19099 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19101 SDValue Chain = Op.getOperand(0);
19102 SDValue Zero = DAG.getConstant(0, MVT::i32);
19104 DAG.getRegister(X86::ESP, MVT::i32), // Base
19105 DAG.getTargetConstant(1, MVT::i8), // Scale
19106 DAG.getRegister(0, MVT::i32), // Index
19107 DAG.getTargetConstant(0, MVT::i32), // Disp
19108 DAG.getRegister(0, MVT::i32), // Segment.
19112 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19113 return SDValue(Res, 0);
19116 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19117 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19120 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19121 SelectionDAG &DAG) {
19122 MVT T = Op.getSimpleValueType();
19126 switch(T.SimpleTy) {
19127 default: llvm_unreachable("Invalid value type!");
19128 case MVT::i8: Reg = X86::AL; size = 1; break;
19129 case MVT::i16: Reg = X86::AX; size = 2; break;
19130 case MVT::i32: Reg = X86::EAX; size = 4; break;
19132 assert(Subtarget->is64Bit() && "Node not type legal!");
19133 Reg = X86::RAX; size = 8;
19136 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19137 Op.getOperand(2), SDValue());
19138 SDValue Ops[] = { cpIn.getValue(0),
19141 DAG.getTargetConstant(size, MVT::i8),
19142 cpIn.getValue(1) };
19143 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19144 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19145 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19149 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19150 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19151 MVT::i32, cpOut.getValue(2));
19152 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19153 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19155 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19156 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19157 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19161 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19162 SelectionDAG &DAG) {
19163 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19164 MVT DstVT = Op.getSimpleValueType();
19166 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19167 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19168 if (DstVT != MVT::f64)
19169 // This conversion needs to be expanded.
19172 SDValue InVec = Op->getOperand(0);
19174 unsigned NumElts = SrcVT.getVectorNumElements();
19175 EVT SVT = SrcVT.getVectorElementType();
19177 // Widen the vector in input in the case of MVT::v2i32.
19178 // Example: from MVT::v2i32 to MVT::v4i32.
19179 SmallVector<SDValue, 16> Elts;
19180 for (unsigned i = 0, e = NumElts; i != e; ++i)
19181 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19182 DAG.getIntPtrConstant(i)));
19184 // Explicitly mark the extra elements as Undef.
19185 SDValue Undef = DAG.getUNDEF(SVT);
19186 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
19187 Elts.push_back(Undef);
19189 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19190 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19191 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
19192 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19193 DAG.getIntPtrConstant(0));
19196 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19197 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19198 assert((DstVT == MVT::i64 ||
19199 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19200 "Unexpected custom BITCAST");
19201 // i64 <=> MMX conversions are Legal.
19202 if (SrcVT==MVT::i64 && DstVT.isVector())
19204 if (DstVT==MVT::i64 && SrcVT.isVector())
19206 // MMX <=> MMX conversions are Legal.
19207 if (SrcVT.isVector() && DstVT.isVector())
19209 // All other conversions need to be expanded.
19213 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19214 SDNode *Node = Op.getNode();
19216 EVT T = Node->getValueType(0);
19217 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19218 DAG.getConstant(0, T), Node->getOperand(2));
19219 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19220 cast<AtomicSDNode>(Node)->getMemoryVT(),
19221 Node->getOperand(0),
19222 Node->getOperand(1), negOp,
19223 cast<AtomicSDNode>(Node)->getMemOperand(),
19224 cast<AtomicSDNode>(Node)->getOrdering(),
19225 cast<AtomicSDNode>(Node)->getSynchScope());
19228 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19229 SDNode *Node = Op.getNode();
19231 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19233 // Convert seq_cst store -> xchg
19234 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19235 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19236 // (The only way to get a 16-byte store is cmpxchg16b)
19237 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19238 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19239 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19240 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19241 cast<AtomicSDNode>(Node)->getMemoryVT(),
19242 Node->getOperand(0),
19243 Node->getOperand(1), Node->getOperand(2),
19244 cast<AtomicSDNode>(Node)->getMemOperand(),
19245 cast<AtomicSDNode>(Node)->getOrdering(),
19246 cast<AtomicSDNode>(Node)->getSynchScope());
19247 return Swap.getValue(1);
19249 // Other atomic stores have a simple pattern.
19253 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19254 EVT VT = Op.getNode()->getSimpleValueType(0);
19256 // Let legalize expand this if it isn't a legal type yet.
19257 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19260 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19263 bool ExtraOp = false;
19264 switch (Op.getOpcode()) {
19265 default: llvm_unreachable("Invalid code");
19266 case ISD::ADDC: Opc = X86ISD::ADD; break;
19267 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19268 case ISD::SUBC: Opc = X86ISD::SUB; break;
19269 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19273 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19275 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19276 Op.getOperand(1), Op.getOperand(2));
19279 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19280 SelectionDAG &DAG) {
19281 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19283 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19284 // which returns the values as { float, float } (in XMM0) or
19285 // { double, double } (which is returned in XMM0, XMM1).
19287 SDValue Arg = Op.getOperand(0);
19288 EVT ArgVT = Arg.getValueType();
19289 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19291 TargetLowering::ArgListTy Args;
19292 TargetLowering::ArgListEntry Entry;
19296 Entry.isSExt = false;
19297 Entry.isZExt = false;
19298 Args.push_back(Entry);
19300 bool isF64 = ArgVT == MVT::f64;
19301 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19302 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19303 // the results are returned via SRet in memory.
19304 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19305 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19306 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
19308 Type *RetTy = isF64
19309 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19310 : (Type*)VectorType::get(ArgTy, 4);
19312 TargetLowering::CallLoweringInfo CLI(DAG);
19313 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19314 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19316 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19319 // Returned in xmm0 and xmm1.
19320 return CallResult.first;
19322 // Returned in bits 0:31 and 32:64 xmm0.
19323 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19324 CallResult.first, DAG.getIntPtrConstant(0));
19325 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19326 CallResult.first, DAG.getIntPtrConstant(1));
19327 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19328 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19331 /// LowerOperation - Provide custom lowering hooks for some operations.
19333 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19334 switch (Op.getOpcode()) {
19335 default: llvm_unreachable("Should not custom lower this!");
19336 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
19337 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19338 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19339 return LowerCMP_SWAP(Op, Subtarget, DAG);
19340 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19341 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19342 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19343 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
19344 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
19345 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19346 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19347 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19348 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19349 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19350 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19351 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19352 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19353 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19354 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19355 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19356 case ISD::SHL_PARTS:
19357 case ISD::SRA_PARTS:
19358 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19359 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19360 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19361 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19362 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19363 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19364 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19365 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19366 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19367 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19368 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19370 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19371 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19372 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19373 case ISD::SETCC: return LowerSETCC(Op, DAG);
19374 case ISD::SELECT: return LowerSELECT(Op, DAG);
19375 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19376 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19377 case ISD::VASTART: return LowerVASTART(Op, DAG);
19378 case ISD::VAARG: return LowerVAARG(Op, DAG);
19379 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19380 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19381 case ISD::INTRINSIC_VOID:
19382 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19383 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19384 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19385 case ISD::FRAME_TO_ARGS_OFFSET:
19386 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19387 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19388 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19389 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19390 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19391 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19392 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19393 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19394 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19395 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19396 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
19397 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19398 case ISD::UMUL_LOHI:
19399 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19402 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19408 case ISD::UMULO: return LowerXALUO(Op, DAG);
19409 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19410 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19414 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19415 case ISD::ADD: return LowerADD(Op, DAG);
19416 case ISD::SUB: return LowerSUB(Op, DAG);
19417 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19421 /// ReplaceNodeResults - Replace a node with an illegal result type
19422 /// with a new node built out of custom code.
19423 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19424 SmallVectorImpl<SDValue>&Results,
19425 SelectionDAG &DAG) const {
19427 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19428 switch (N->getOpcode()) {
19430 llvm_unreachable("Do not know how to custom type legalize this operation!");
19431 case ISD::SIGN_EXTEND_INREG:
19436 // We don't want to expand or promote these.
19443 case ISD::UDIVREM: {
19444 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19445 Results.push_back(V);
19448 case ISD::FP_TO_SINT:
19449 case ISD::FP_TO_UINT: {
19450 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19452 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
19455 std::pair<SDValue,SDValue> Vals =
19456 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19457 SDValue FIST = Vals.first, StackSlot = Vals.second;
19458 if (FIST.getNode()) {
19459 EVT VT = N->getValueType(0);
19460 // Return a load from the stack slot.
19461 if (StackSlot.getNode())
19462 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19463 MachinePointerInfo(),
19464 false, false, false, 0));
19466 Results.push_back(FIST);
19470 case ISD::UINT_TO_FP: {
19471 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19472 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19473 N->getValueType(0) != MVT::v2f32)
19475 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19477 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
19479 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19480 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19481 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
19482 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
19483 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19484 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19487 case ISD::FP_ROUND: {
19488 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19490 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19491 Results.push_back(V);
19494 case ISD::INTRINSIC_W_CHAIN: {
19495 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19497 default : llvm_unreachable("Do not know how to custom type "
19498 "legalize this intrinsic operation!");
19499 case Intrinsic::x86_rdtsc:
19500 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19502 case Intrinsic::x86_rdtscp:
19503 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19505 case Intrinsic::x86_rdpmc:
19506 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19509 case ISD::READCYCLECOUNTER: {
19510 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19513 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19514 EVT T = N->getValueType(0);
19515 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19516 bool Regs64bit = T == MVT::i128;
19517 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19518 SDValue cpInL, cpInH;
19519 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19520 DAG.getConstant(0, HalfT));
19521 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19522 DAG.getConstant(1, HalfT));
19523 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19524 Regs64bit ? X86::RAX : X86::EAX,
19526 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19527 Regs64bit ? X86::RDX : X86::EDX,
19528 cpInH, cpInL.getValue(1));
19529 SDValue swapInL, swapInH;
19530 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19531 DAG.getConstant(0, HalfT));
19532 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19533 DAG.getConstant(1, HalfT));
19534 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19535 Regs64bit ? X86::RBX : X86::EBX,
19536 swapInL, cpInH.getValue(1));
19537 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19538 Regs64bit ? X86::RCX : X86::ECX,
19539 swapInH, swapInL.getValue(1));
19540 SDValue Ops[] = { swapInH.getValue(0),
19542 swapInH.getValue(1) };
19543 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19544 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19545 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19546 X86ISD::LCMPXCHG8_DAG;
19547 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19548 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19549 Regs64bit ? X86::RAX : X86::EAX,
19550 HalfT, Result.getValue(1));
19551 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19552 Regs64bit ? X86::RDX : X86::EDX,
19553 HalfT, cpOutL.getValue(2));
19554 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19556 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19557 MVT::i32, cpOutH.getValue(2));
19559 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19560 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19561 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19563 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19564 Results.push_back(Success);
19565 Results.push_back(EFLAGS.getValue(1));
19568 case ISD::ATOMIC_SWAP:
19569 case ISD::ATOMIC_LOAD_ADD:
19570 case ISD::ATOMIC_LOAD_SUB:
19571 case ISD::ATOMIC_LOAD_AND:
19572 case ISD::ATOMIC_LOAD_OR:
19573 case ISD::ATOMIC_LOAD_XOR:
19574 case ISD::ATOMIC_LOAD_NAND:
19575 case ISD::ATOMIC_LOAD_MIN:
19576 case ISD::ATOMIC_LOAD_MAX:
19577 case ISD::ATOMIC_LOAD_UMIN:
19578 case ISD::ATOMIC_LOAD_UMAX:
19579 case ISD::ATOMIC_LOAD: {
19580 // Delegate to generic TypeLegalization. Situations we can really handle
19581 // should have already been dealt with by AtomicExpandPass.cpp.
19584 case ISD::BITCAST: {
19585 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19586 EVT DstVT = N->getValueType(0);
19587 EVT SrcVT = N->getOperand(0)->getValueType(0);
19589 if (SrcVT != MVT::f64 ||
19590 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19593 unsigned NumElts = DstVT.getVectorNumElements();
19594 EVT SVT = DstVT.getVectorElementType();
19595 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19596 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19597 MVT::v2f64, N->getOperand(0));
19598 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
19600 if (ExperimentalVectorWideningLegalization) {
19601 // If we are legalizing vectors by widening, we already have the desired
19602 // legal vector type, just return it.
19603 Results.push_back(ToVecInt);
19607 SmallVector<SDValue, 8> Elts;
19608 for (unsigned i = 0, e = NumElts; i != e; ++i)
19609 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19610 ToVecInt, DAG.getIntPtrConstant(i)));
19612 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19617 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19619 default: return nullptr;
19620 case X86ISD::BSF: return "X86ISD::BSF";
19621 case X86ISD::BSR: return "X86ISD::BSR";
19622 case X86ISD::SHLD: return "X86ISD::SHLD";
19623 case X86ISD::SHRD: return "X86ISD::SHRD";
19624 case X86ISD::FAND: return "X86ISD::FAND";
19625 case X86ISD::FANDN: return "X86ISD::FANDN";
19626 case X86ISD::FOR: return "X86ISD::FOR";
19627 case X86ISD::FXOR: return "X86ISD::FXOR";
19628 case X86ISD::FSRL: return "X86ISD::FSRL";
19629 case X86ISD::FILD: return "X86ISD::FILD";
19630 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19631 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19632 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19633 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19634 case X86ISD::FLD: return "X86ISD::FLD";
19635 case X86ISD::FST: return "X86ISD::FST";
19636 case X86ISD::CALL: return "X86ISD::CALL";
19637 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19638 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19639 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19640 case X86ISD::BT: return "X86ISD::BT";
19641 case X86ISD::CMP: return "X86ISD::CMP";
19642 case X86ISD::COMI: return "X86ISD::COMI";
19643 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19644 case X86ISD::CMPM: return "X86ISD::CMPM";
19645 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19646 case X86ISD::SETCC: return "X86ISD::SETCC";
19647 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19648 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19649 case X86ISD::CMOV: return "X86ISD::CMOV";
19650 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19651 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19652 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19653 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19654 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19655 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19656 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19657 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19658 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19659 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19660 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19661 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19662 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19663 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19664 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19665 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19666 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19667 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19668 case X86ISD::HADD: return "X86ISD::HADD";
19669 case X86ISD::HSUB: return "X86ISD::HSUB";
19670 case X86ISD::FHADD: return "X86ISD::FHADD";
19671 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19672 case X86ISD::UMAX: return "X86ISD::UMAX";
19673 case X86ISD::UMIN: return "X86ISD::UMIN";
19674 case X86ISD::SMAX: return "X86ISD::SMAX";
19675 case X86ISD::SMIN: return "X86ISD::SMIN";
19676 case X86ISD::FMAX: return "X86ISD::FMAX";
19677 case X86ISD::FMIN: return "X86ISD::FMIN";
19678 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19679 case X86ISD::FMINC: return "X86ISD::FMINC";
19680 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19681 case X86ISD::FRCP: return "X86ISD::FRCP";
19682 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19683 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19684 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19685 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19686 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19687 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19688 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19689 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19690 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19691 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19692 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19693 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19694 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19695 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19696 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19697 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19698 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19699 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
19700 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19701 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19702 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19703 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19704 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19705 case X86ISD::VSHL: return "X86ISD::VSHL";
19706 case X86ISD::VSRL: return "X86ISD::VSRL";
19707 case X86ISD::VSRA: return "X86ISD::VSRA";
19708 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19709 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19710 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19711 case X86ISD::CMPP: return "X86ISD::CMPP";
19712 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19713 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19714 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19715 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19716 case X86ISD::ADD: return "X86ISD::ADD";
19717 case X86ISD::SUB: return "X86ISD::SUB";
19718 case X86ISD::ADC: return "X86ISD::ADC";
19719 case X86ISD::SBB: return "X86ISD::SBB";
19720 case X86ISD::SMUL: return "X86ISD::SMUL";
19721 case X86ISD::UMUL: return "X86ISD::UMUL";
19722 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19723 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19724 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19725 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19726 case X86ISD::INC: return "X86ISD::INC";
19727 case X86ISD::DEC: return "X86ISD::DEC";
19728 case X86ISD::OR: return "X86ISD::OR";
19729 case X86ISD::XOR: return "X86ISD::XOR";
19730 case X86ISD::AND: return "X86ISD::AND";
19731 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19732 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19733 case X86ISD::PTEST: return "X86ISD::PTEST";
19734 case X86ISD::TESTP: return "X86ISD::TESTP";
19735 case X86ISD::TESTM: return "X86ISD::TESTM";
19736 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19737 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19738 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19739 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19740 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19741 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19742 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19743 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19744 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19745 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19746 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19747 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19748 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19749 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19750 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19751 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19752 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19753 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19754 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19755 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19756 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19757 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19758 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19759 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
19760 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19761 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19762 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19763 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19764 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19765 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19766 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19767 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19768 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19769 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19770 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19771 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19772 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19773 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19774 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
19775 case X86ISD::SAHF: return "X86ISD::SAHF";
19776 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19777 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19778 case X86ISD::FMADD: return "X86ISD::FMADD";
19779 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19780 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19781 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19782 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19783 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19784 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19785 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19786 case X86ISD::XTEST: return "X86ISD::XTEST";
19790 // isLegalAddressingMode - Return true if the addressing mode represented
19791 // by AM is legal for this target, for a load/store of the specified type.
19792 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
19794 // X86 supports extremely general addressing modes.
19795 CodeModel::Model M = getTargetMachine().getCodeModel();
19796 Reloc::Model R = getTargetMachine().getRelocationModel();
19798 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19799 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19804 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19806 // If a reference to this global requires an extra load, we can't fold it.
19807 if (isGlobalStubReference(GVFlags))
19810 // If BaseGV requires a register for the PIC base, we cannot also have a
19811 // BaseReg specified.
19812 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19815 // If lower 4G is not available, then we must use rip-relative addressing.
19816 if ((M != CodeModel::Small || R != Reloc::Static) &&
19817 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19821 switch (AM.Scale) {
19827 // These scales always work.
19832 // These scales are formed with basereg+scalereg. Only accept if there is
19837 default: // Other stuff never works.
19844 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19845 unsigned Bits = Ty->getScalarSizeInBits();
19847 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19848 // particularly cheaper than those without.
19852 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19853 // variable shifts just as cheap as scalar ones.
19854 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19857 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19858 // fully general vector.
19862 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19863 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19865 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19866 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19867 return NumBits1 > NumBits2;
19870 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19871 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19874 if (!isTypeLegal(EVT::getEVT(Ty1)))
19877 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19879 // Assuming the caller doesn't have a zeroext or signext return parameter,
19880 // truncation all the way down to i1 is valid.
19884 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19885 return isInt<32>(Imm);
19888 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19889 // Can also use sub to handle negated immediates.
19890 return isInt<32>(Imm);
19893 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
19894 if (!VT1.isInteger() || !VT2.isInteger())
19896 unsigned NumBits1 = VT1.getSizeInBits();
19897 unsigned NumBits2 = VT2.getSizeInBits();
19898 return NumBits1 > NumBits2;
19901 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19902 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19903 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19906 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19907 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19908 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19911 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19912 EVT VT1 = Val.getValueType();
19913 if (isZExtFree(VT1, VT2))
19916 if (Val.getOpcode() != ISD::LOAD)
19919 if (!VT1.isSimple() || !VT1.isInteger() ||
19920 !VT2.isSimple() || !VT2.isInteger())
19923 switch (VT1.getSimpleVT().SimpleTy) {
19928 // X86 has 8, 16, and 32-bit zero-extending loads.
19936 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
19937 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
19940 VT = VT.getScalarType();
19942 if (!VT.isSimple())
19945 switch (VT.getSimpleVT().SimpleTy) {
19956 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
19957 // i16 instructions are longer (0x66 prefix) and potentially slower.
19958 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19961 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19962 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19963 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19964 /// are assumed to be legal.
19966 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19968 if (!VT.isSimple())
19971 MVT SVT = VT.getSimpleVT();
19973 // Very little shuffling can be done for 64-bit vectors right now.
19974 if (VT.getSizeInBits() == 64)
19977 // If this is a single-input shuffle with no 128 bit lane crossings we can
19978 // lower it into pshufb.
19979 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
19980 (SVT.is256BitVector() && Subtarget->hasInt256())) {
19981 bool isLegal = true;
19982 for (unsigned I = 0, E = M.size(); I != E; ++I) {
19983 if (M[I] >= (int)SVT.getVectorNumElements() ||
19984 ShuffleCrosses128bitLane(SVT, I, M[I])) {
19993 // FIXME: blends, shifts.
19994 return (SVT.getVectorNumElements() == 2 ||
19995 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
19996 isMOVLMask(M, SVT) ||
19997 isCommutedMOVLMask(M, SVT) ||
19998 isMOVHLPSMask(M, SVT) ||
19999 isSHUFPMask(M, SVT) ||
20000 isSHUFPMask(M, SVT, /* Commuted */ true) ||
20001 isPSHUFDMask(M, SVT) ||
20002 isPSHUFDMask(M, SVT, /* SecondOperand */ true) ||
20003 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
20004 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
20005 isPALIGNRMask(M, SVT, Subtarget) ||
20006 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
20007 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
20008 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
20009 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
20010 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()) ||
20011 (Subtarget->hasSSE41() && isINSERTPSMask(M, SVT)));
20015 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20017 if (!VT.isSimple())
20020 MVT SVT = VT.getSimpleVT();
20021 unsigned NumElts = SVT.getVectorNumElements();
20022 // FIXME: This collection of masks seems suspect.
20025 if (NumElts == 4 && SVT.is128BitVector()) {
20026 return (isMOVLMask(Mask, SVT) ||
20027 isCommutedMOVLMask(Mask, SVT, true) ||
20028 isSHUFPMask(Mask, SVT) ||
20029 isSHUFPMask(Mask, SVT, /* Commuted */ true) ||
20030 isBlendMask(Mask, SVT, Subtarget->hasSSE41(),
20031 Subtarget->hasInt256()));
20036 //===----------------------------------------------------------------------===//
20037 // X86 Scheduler Hooks
20038 //===----------------------------------------------------------------------===//
20040 /// Utility function to emit xbegin specifying the start of an RTM region.
20041 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20042 const TargetInstrInfo *TII) {
20043 DebugLoc DL = MI->getDebugLoc();
20045 const BasicBlock *BB = MBB->getBasicBlock();
20046 MachineFunction::iterator I = MBB;
20049 // For the v = xbegin(), we generate
20060 MachineBasicBlock *thisMBB = MBB;
20061 MachineFunction *MF = MBB->getParent();
20062 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20063 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20064 MF->insert(I, mainMBB);
20065 MF->insert(I, sinkMBB);
20067 // Transfer the remainder of BB and its successor edges to sinkMBB.
20068 sinkMBB->splice(sinkMBB->begin(), MBB,
20069 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20070 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20074 // # fallthrough to mainMBB
20075 // # abortion to sinkMBB
20076 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20077 thisMBB->addSuccessor(mainMBB);
20078 thisMBB->addSuccessor(sinkMBB);
20082 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20083 mainMBB->addSuccessor(sinkMBB);
20086 // EAX is live into the sinkMBB
20087 sinkMBB->addLiveIn(X86::EAX);
20088 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20089 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20092 MI->eraseFromParent();
20096 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20097 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20098 // in the .td file.
20099 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20100 const TargetInstrInfo *TII) {
20102 switch (MI->getOpcode()) {
20103 default: llvm_unreachable("illegal opcode!");
20104 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20105 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20106 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20107 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20108 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20109 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20110 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20111 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20114 DebugLoc dl = MI->getDebugLoc();
20115 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20117 unsigned NumArgs = MI->getNumOperands();
20118 for (unsigned i = 1; i < NumArgs; ++i) {
20119 MachineOperand &Op = MI->getOperand(i);
20120 if (!(Op.isReg() && Op.isImplicit()))
20121 MIB.addOperand(Op);
20123 if (MI->hasOneMemOperand())
20124 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20126 BuildMI(*BB, MI, dl,
20127 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20128 .addReg(X86::XMM0);
20130 MI->eraseFromParent();
20134 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20135 // defs in an instruction pattern
20136 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20137 const TargetInstrInfo *TII) {
20139 switch (MI->getOpcode()) {
20140 default: llvm_unreachable("illegal opcode!");
20141 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20142 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20143 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20144 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20145 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20146 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20147 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20148 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20151 DebugLoc dl = MI->getDebugLoc();
20152 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20154 unsigned NumArgs = MI->getNumOperands(); // remove the results
20155 for (unsigned i = 1; i < NumArgs; ++i) {
20156 MachineOperand &Op = MI->getOperand(i);
20157 if (!(Op.isReg() && Op.isImplicit()))
20158 MIB.addOperand(Op);
20160 if (MI->hasOneMemOperand())
20161 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20163 BuildMI(*BB, MI, dl,
20164 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20167 MI->eraseFromParent();
20171 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20172 const TargetInstrInfo *TII,
20173 const X86Subtarget* Subtarget) {
20174 DebugLoc dl = MI->getDebugLoc();
20176 // Address into RAX/EAX, other two args into ECX, EDX.
20177 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20178 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20179 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20180 for (int i = 0; i < X86::AddrNumOperands; ++i)
20181 MIB.addOperand(MI->getOperand(i));
20183 unsigned ValOps = X86::AddrNumOperands;
20184 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20185 .addReg(MI->getOperand(ValOps).getReg());
20186 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20187 .addReg(MI->getOperand(ValOps+1).getReg());
20189 // The instruction doesn't actually take any operands though.
20190 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20192 MI->eraseFromParent(); // The pseudo is gone now.
20196 MachineBasicBlock *
20197 X86TargetLowering::EmitVAARG64WithCustomInserter(
20199 MachineBasicBlock *MBB) const {
20200 // Emit va_arg instruction on X86-64.
20202 // Operands to this pseudo-instruction:
20203 // 0 ) Output : destination address (reg)
20204 // 1-5) Input : va_list address (addr, i64mem)
20205 // 6 ) ArgSize : Size (in bytes) of vararg type
20206 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20207 // 8 ) Align : Alignment of type
20208 // 9 ) EFLAGS (implicit-def)
20210 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20211 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
20213 unsigned DestReg = MI->getOperand(0).getReg();
20214 MachineOperand &Base = MI->getOperand(1);
20215 MachineOperand &Scale = MI->getOperand(2);
20216 MachineOperand &Index = MI->getOperand(3);
20217 MachineOperand &Disp = MI->getOperand(4);
20218 MachineOperand &Segment = MI->getOperand(5);
20219 unsigned ArgSize = MI->getOperand(6).getImm();
20220 unsigned ArgMode = MI->getOperand(7).getImm();
20221 unsigned Align = MI->getOperand(8).getImm();
20223 // Memory Reference
20224 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20225 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20226 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20228 // Machine Information
20229 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20230 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20231 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20232 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20233 DebugLoc DL = MI->getDebugLoc();
20235 // struct va_list {
20238 // i64 overflow_area (address)
20239 // i64 reg_save_area (address)
20241 // sizeof(va_list) = 24
20242 // alignment(va_list) = 8
20244 unsigned TotalNumIntRegs = 6;
20245 unsigned TotalNumXMMRegs = 8;
20246 bool UseGPOffset = (ArgMode == 1);
20247 bool UseFPOffset = (ArgMode == 2);
20248 unsigned MaxOffset = TotalNumIntRegs * 8 +
20249 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20251 /* Align ArgSize to a multiple of 8 */
20252 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20253 bool NeedsAlign = (Align > 8);
20255 MachineBasicBlock *thisMBB = MBB;
20256 MachineBasicBlock *overflowMBB;
20257 MachineBasicBlock *offsetMBB;
20258 MachineBasicBlock *endMBB;
20260 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20261 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20262 unsigned OffsetReg = 0;
20264 if (!UseGPOffset && !UseFPOffset) {
20265 // If we only pull from the overflow region, we don't create a branch.
20266 // We don't need to alter control flow.
20267 OffsetDestReg = 0; // unused
20268 OverflowDestReg = DestReg;
20270 offsetMBB = nullptr;
20271 overflowMBB = thisMBB;
20274 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20275 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20276 // If not, pull from overflow_area. (branch to overflowMBB)
20281 // offsetMBB overflowMBB
20286 // Registers for the PHI in endMBB
20287 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20288 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20290 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20291 MachineFunction *MF = MBB->getParent();
20292 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20293 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20294 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20296 MachineFunction::iterator MBBIter = MBB;
20299 // Insert the new basic blocks
20300 MF->insert(MBBIter, offsetMBB);
20301 MF->insert(MBBIter, overflowMBB);
20302 MF->insert(MBBIter, endMBB);
20304 // Transfer the remainder of MBB and its successor edges to endMBB.
20305 endMBB->splice(endMBB->begin(), thisMBB,
20306 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20307 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20309 // Make offsetMBB and overflowMBB successors of thisMBB
20310 thisMBB->addSuccessor(offsetMBB);
20311 thisMBB->addSuccessor(overflowMBB);
20313 // endMBB is a successor of both offsetMBB and overflowMBB
20314 offsetMBB->addSuccessor(endMBB);
20315 overflowMBB->addSuccessor(endMBB);
20317 // Load the offset value into a register
20318 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20319 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20323 .addDisp(Disp, UseFPOffset ? 4 : 0)
20324 .addOperand(Segment)
20325 .setMemRefs(MMOBegin, MMOEnd);
20327 // Check if there is enough room left to pull this argument.
20328 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20330 .addImm(MaxOffset + 8 - ArgSizeA8);
20332 // Branch to "overflowMBB" if offset >= max
20333 // Fall through to "offsetMBB" otherwise
20334 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20335 .addMBB(overflowMBB);
20338 // In offsetMBB, emit code to use the reg_save_area.
20340 assert(OffsetReg != 0);
20342 // Read the reg_save_area address.
20343 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20344 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20349 .addOperand(Segment)
20350 .setMemRefs(MMOBegin, MMOEnd);
20352 // Zero-extend the offset
20353 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20354 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20357 .addImm(X86::sub_32bit);
20359 // Add the offset to the reg_save_area to get the final address.
20360 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20361 .addReg(OffsetReg64)
20362 .addReg(RegSaveReg);
20364 // Compute the offset for the next argument
20365 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20366 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20368 .addImm(UseFPOffset ? 16 : 8);
20370 // Store it back into the va_list.
20371 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20375 .addDisp(Disp, UseFPOffset ? 4 : 0)
20376 .addOperand(Segment)
20377 .addReg(NextOffsetReg)
20378 .setMemRefs(MMOBegin, MMOEnd);
20381 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
20386 // Emit code to use overflow area
20389 // Load the overflow_area address into a register.
20390 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20391 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20396 .addOperand(Segment)
20397 .setMemRefs(MMOBegin, MMOEnd);
20399 // If we need to align it, do so. Otherwise, just copy the address
20400 // to OverflowDestReg.
20402 // Align the overflow address
20403 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20404 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20406 // aligned_addr = (addr + (align-1)) & ~(align-1)
20407 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20408 .addReg(OverflowAddrReg)
20411 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20413 .addImm(~(uint64_t)(Align-1));
20415 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20416 .addReg(OverflowAddrReg);
20419 // Compute the next overflow address after this argument.
20420 // (the overflow address should be kept 8-byte aligned)
20421 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20422 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20423 .addReg(OverflowDestReg)
20424 .addImm(ArgSizeA8);
20426 // Store the new overflow address.
20427 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20432 .addOperand(Segment)
20433 .addReg(NextAddrReg)
20434 .setMemRefs(MMOBegin, MMOEnd);
20436 // If we branched, emit the PHI to the front of endMBB.
20438 BuildMI(*endMBB, endMBB->begin(), DL,
20439 TII->get(X86::PHI), DestReg)
20440 .addReg(OffsetDestReg).addMBB(offsetMBB)
20441 .addReg(OverflowDestReg).addMBB(overflowMBB);
20444 // Erase the pseudo instruction
20445 MI->eraseFromParent();
20450 MachineBasicBlock *
20451 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20453 MachineBasicBlock *MBB) const {
20454 // Emit code to save XMM registers to the stack. The ABI says that the
20455 // number of registers to save is given in %al, so it's theoretically
20456 // possible to do an indirect jump trick to avoid saving all of them,
20457 // however this code takes a simpler approach and just executes all
20458 // of the stores if %al is non-zero. It's less code, and it's probably
20459 // easier on the hardware branch predictor, and stores aren't all that
20460 // expensive anyway.
20462 // Create the new basic blocks. One block contains all the XMM stores,
20463 // and one block is the final destination regardless of whether any
20464 // stores were performed.
20465 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20466 MachineFunction *F = MBB->getParent();
20467 MachineFunction::iterator MBBIter = MBB;
20469 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20470 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20471 F->insert(MBBIter, XMMSaveMBB);
20472 F->insert(MBBIter, EndMBB);
20474 // Transfer the remainder of MBB and its successor edges to EndMBB.
20475 EndMBB->splice(EndMBB->begin(), MBB,
20476 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20477 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20479 // The original block will now fall through to the XMM save block.
20480 MBB->addSuccessor(XMMSaveMBB);
20481 // The XMMSaveMBB will fall through to the end block.
20482 XMMSaveMBB->addSuccessor(EndMBB);
20484 // Now add the instructions.
20485 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20486 DebugLoc DL = MI->getDebugLoc();
20488 unsigned CountReg = MI->getOperand(0).getReg();
20489 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20490 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20492 if (!Subtarget->isTargetWin64()) {
20493 // If %al is 0, branch around the XMM save block.
20494 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20495 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
20496 MBB->addSuccessor(EndMBB);
20499 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20500 // that was just emitted, but clearly shouldn't be "saved".
20501 assert((MI->getNumOperands() <= 3 ||
20502 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20503 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20504 && "Expected last argument to be EFLAGS");
20505 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20506 // In the XMM save block, save all the XMM argument registers.
20507 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20508 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20509 MachineMemOperand *MMO =
20510 F->getMachineMemOperand(
20511 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
20512 MachineMemOperand::MOStore,
20513 /*Size=*/16, /*Align=*/16);
20514 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20515 .addFrameIndex(RegSaveFrameIndex)
20516 .addImm(/*Scale=*/1)
20517 .addReg(/*IndexReg=*/0)
20518 .addImm(/*Disp=*/Offset)
20519 .addReg(/*Segment=*/0)
20520 .addReg(MI->getOperand(i).getReg())
20521 .addMemOperand(MMO);
20524 MI->eraseFromParent(); // The pseudo instruction is gone now.
20529 // The EFLAGS operand of SelectItr might be missing a kill marker
20530 // because there were multiple uses of EFLAGS, and ISel didn't know
20531 // which to mark. Figure out whether SelectItr should have had a
20532 // kill marker, and set it if it should. Returns the correct kill
20534 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20535 MachineBasicBlock* BB,
20536 const TargetRegisterInfo* TRI) {
20537 // Scan forward through BB for a use/def of EFLAGS.
20538 MachineBasicBlock::iterator miI(std::next(SelectItr));
20539 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20540 const MachineInstr& mi = *miI;
20541 if (mi.readsRegister(X86::EFLAGS))
20543 if (mi.definesRegister(X86::EFLAGS))
20544 break; // Should have kill-flag - update below.
20547 // If we hit the end of the block, check whether EFLAGS is live into a
20549 if (miI == BB->end()) {
20550 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20551 sEnd = BB->succ_end();
20552 sItr != sEnd; ++sItr) {
20553 MachineBasicBlock* succ = *sItr;
20554 if (succ->isLiveIn(X86::EFLAGS))
20559 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20560 // out. SelectMI should have a kill flag on EFLAGS.
20561 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20565 MachineBasicBlock *
20566 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20567 MachineBasicBlock *BB) const {
20568 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20569 DebugLoc DL = MI->getDebugLoc();
20571 // To "insert" a SELECT_CC instruction, we actually have to insert the
20572 // diamond control-flow pattern. The incoming instruction knows the
20573 // destination vreg to set, the condition code register to branch on, the
20574 // true/false values to select between, and a branch opcode to use.
20575 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20576 MachineFunction::iterator It = BB;
20582 // cmpTY ccX, r1, r2
20584 // fallthrough --> copy0MBB
20585 MachineBasicBlock *thisMBB = BB;
20586 MachineFunction *F = BB->getParent();
20587 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20588 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20589 F->insert(It, copy0MBB);
20590 F->insert(It, sinkMBB);
20592 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20593 // live into the sink and copy blocks.
20594 const TargetRegisterInfo *TRI =
20595 BB->getParent()->getSubtarget().getRegisterInfo();
20596 if (!MI->killsRegister(X86::EFLAGS) &&
20597 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
20598 copy0MBB->addLiveIn(X86::EFLAGS);
20599 sinkMBB->addLiveIn(X86::EFLAGS);
20602 // Transfer the remainder of BB and its successor edges to sinkMBB.
20603 sinkMBB->splice(sinkMBB->begin(), BB,
20604 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20605 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20607 // Add the true and fallthrough blocks as its successors.
20608 BB->addSuccessor(copy0MBB);
20609 BB->addSuccessor(sinkMBB);
20611 // Create the conditional branch instruction.
20613 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
20614 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20617 // %FalseValue = ...
20618 // # fallthrough to sinkMBB
20619 copy0MBB->addSuccessor(sinkMBB);
20622 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20624 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20625 TII->get(X86::PHI), MI->getOperand(0).getReg())
20626 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
20627 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
20629 MI->eraseFromParent(); // The pseudo instruction is gone now.
20633 MachineBasicBlock *
20634 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20635 MachineBasicBlock *BB) const {
20636 MachineFunction *MF = BB->getParent();
20637 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20638 DebugLoc DL = MI->getDebugLoc();
20639 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20641 assert(MF->shouldSplitStack());
20643 const bool Is64Bit = Subtarget->is64Bit();
20644 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20646 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20647 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20650 // ... [Till the alloca]
20651 // If stacklet is not large enough, jump to mallocMBB
20654 // Allocate by subtracting from RSP
20655 // Jump to continueMBB
20658 // Allocate by call to runtime
20662 // [rest of original BB]
20665 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20666 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20667 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20669 MachineRegisterInfo &MRI = MF->getRegInfo();
20670 const TargetRegisterClass *AddrRegClass =
20671 getRegClassFor(getPointerTy());
20673 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20674 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20675 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20676 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20677 sizeVReg = MI->getOperand(1).getReg(),
20678 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20680 MachineFunction::iterator MBBIter = BB;
20683 MF->insert(MBBIter, bumpMBB);
20684 MF->insert(MBBIter, mallocMBB);
20685 MF->insert(MBBIter, continueMBB);
20687 continueMBB->splice(continueMBB->begin(), BB,
20688 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20689 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20691 // Add code to the main basic block to check if the stack limit has been hit,
20692 // and if so, jump to mallocMBB otherwise to bumpMBB.
20693 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20694 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20695 .addReg(tmpSPVReg).addReg(sizeVReg);
20696 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20697 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20698 .addReg(SPLimitVReg);
20699 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
20701 // bumpMBB simply decreases the stack pointer, since we know the current
20702 // stacklet has enough space.
20703 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20704 .addReg(SPLimitVReg);
20705 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20706 .addReg(SPLimitVReg);
20707 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20709 // Calls into a routine in libgcc to allocate more space from the heap.
20710 const uint32_t *RegMask = MF->getTarget()
20711 .getSubtargetImpl()
20712 ->getRegisterInfo()
20713 ->getCallPreservedMask(CallingConv::C);
20715 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
20717 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20718 .addExternalSymbol("__morestack_allocate_stack_space")
20719 .addRegMask(RegMask)
20720 .addReg(X86::RDI, RegState::Implicit)
20721 .addReg(X86::RAX, RegState::ImplicitDefine);
20722 } else if (Is64Bit) {
20723 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20725 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20726 .addExternalSymbol("__morestack_allocate_stack_space")
20727 .addRegMask(RegMask)
20728 .addReg(X86::EDI, RegState::Implicit)
20729 .addReg(X86::EAX, RegState::ImplicitDefine);
20731 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20733 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
20734 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
20735 .addExternalSymbol("__morestack_allocate_stack_space")
20736 .addRegMask(RegMask)
20737 .addReg(X86::EAX, RegState::ImplicitDefine);
20741 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
20744 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
20745 .addReg(IsLP64 ? X86::RAX : X86::EAX);
20746 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20748 // Set up the CFG correctly.
20749 BB->addSuccessor(bumpMBB);
20750 BB->addSuccessor(mallocMBB);
20751 mallocMBB->addSuccessor(continueMBB);
20752 bumpMBB->addSuccessor(continueMBB);
20754 // Take care of the PHI nodes.
20755 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
20756 MI->getOperand(0).getReg())
20757 .addReg(mallocPtrVReg).addMBB(mallocMBB)
20758 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
20760 // Delete the original pseudo instruction.
20761 MI->eraseFromParent();
20764 return continueMBB;
20767 MachineBasicBlock *
20768 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
20769 MachineBasicBlock *BB) const {
20770 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20771 DebugLoc DL = MI->getDebugLoc();
20773 assert(!Subtarget->isTargetMacho());
20775 // The lowering is pretty easy: we're just emitting the call to _alloca. The
20776 // non-trivial part is impdef of ESP.
20778 if (Subtarget->isTargetWin64()) {
20779 if (Subtarget->isTargetCygMing()) {
20780 // ___chkstk(Mingw64):
20781 // Clobbers R10, R11, RAX and EFLAGS.
20783 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20784 .addExternalSymbol("___chkstk")
20785 .addReg(X86::RAX, RegState::Implicit)
20786 .addReg(X86::RSP, RegState::Implicit)
20787 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
20788 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
20789 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20791 // __chkstk(MSVCRT): does not update stack pointer.
20792 // Clobbers R10, R11 and EFLAGS.
20793 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20794 .addExternalSymbol("__chkstk")
20795 .addReg(X86::RAX, RegState::Implicit)
20796 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20797 // RAX has the offset to be subtracted from RSP.
20798 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
20803 const char *StackProbeSymbol = (Subtarget->isTargetKnownWindowsMSVC() ||
20804 Subtarget->isTargetWindowsItanium())
20808 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
20809 .addExternalSymbol(StackProbeSymbol)
20810 .addReg(X86::EAX, RegState::Implicit)
20811 .addReg(X86::ESP, RegState::Implicit)
20812 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
20813 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
20814 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20817 MI->eraseFromParent(); // The pseudo instruction is gone now.
20821 MachineBasicBlock *
20822 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20823 MachineBasicBlock *BB) const {
20824 // This is pretty easy. We're taking the value that we received from
20825 // our load from the relocation, sticking it in either RDI (x86-64)
20826 // or EAX and doing an indirect call. The return value will then
20827 // be in the normal return register.
20828 MachineFunction *F = BB->getParent();
20829 const X86InstrInfo *TII =
20830 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
20831 DebugLoc DL = MI->getDebugLoc();
20833 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
20834 assert(MI->getOperand(3).isGlobal() && "This should be a global");
20836 // Get a register mask for the lowered call.
20837 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
20838 // proper register mask.
20839 const uint32_t *RegMask = F->getTarget()
20840 .getSubtargetImpl()
20841 ->getRegisterInfo()
20842 ->getCallPreservedMask(CallingConv::C);
20843 if (Subtarget->is64Bit()) {
20844 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20845 TII->get(X86::MOV64rm), X86::RDI)
20847 .addImm(0).addReg(0)
20848 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20849 MI->getOperand(3).getTargetFlags())
20851 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
20852 addDirectMem(MIB, X86::RDI);
20853 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
20854 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
20855 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20856 TII->get(X86::MOV32rm), X86::EAX)
20858 .addImm(0).addReg(0)
20859 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20860 MI->getOperand(3).getTargetFlags())
20862 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20863 addDirectMem(MIB, X86::EAX);
20864 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20866 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20867 TII->get(X86::MOV32rm), X86::EAX)
20868 .addReg(TII->getGlobalBaseReg(F))
20869 .addImm(0).addReg(0)
20870 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20871 MI->getOperand(3).getTargetFlags())
20873 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20874 addDirectMem(MIB, X86::EAX);
20875 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20878 MI->eraseFromParent(); // The pseudo instruction is gone now.
20882 MachineBasicBlock *
20883 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
20884 MachineBasicBlock *MBB) const {
20885 DebugLoc DL = MI->getDebugLoc();
20886 MachineFunction *MF = MBB->getParent();
20887 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20888 MachineRegisterInfo &MRI = MF->getRegInfo();
20890 const BasicBlock *BB = MBB->getBasicBlock();
20891 MachineFunction::iterator I = MBB;
20894 // Memory Reference
20895 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20896 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20899 unsigned MemOpndSlot = 0;
20901 unsigned CurOp = 0;
20903 DstReg = MI->getOperand(CurOp++).getReg();
20904 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
20905 assert(RC->hasType(MVT::i32) && "Invalid destination!");
20906 unsigned mainDstReg = MRI.createVirtualRegister(RC);
20907 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
20909 MemOpndSlot = CurOp;
20911 MVT PVT = getPointerTy();
20912 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20913 "Invalid Pointer Size!");
20915 // For v = setjmp(buf), we generate
20918 // buf[LabelOffset] = restoreMBB
20919 // SjLjSetup restoreMBB
20925 // v = phi(main, restore)
20928 // if base pointer being used, load it from frame
20931 MachineBasicBlock *thisMBB = MBB;
20932 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20933 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20934 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
20935 MF->insert(I, mainMBB);
20936 MF->insert(I, sinkMBB);
20937 MF->push_back(restoreMBB);
20939 MachineInstrBuilder MIB;
20941 // Transfer the remainder of BB and its successor edges to sinkMBB.
20942 sinkMBB->splice(sinkMBB->begin(), MBB,
20943 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20944 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20947 unsigned PtrStoreOpc = 0;
20948 unsigned LabelReg = 0;
20949 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20950 Reloc::Model RM = MF->getTarget().getRelocationModel();
20951 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
20952 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
20954 // Prepare IP either in reg or imm.
20955 if (!UseImmLabel) {
20956 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
20957 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
20958 LabelReg = MRI.createVirtualRegister(PtrRC);
20959 if (Subtarget->is64Bit()) {
20960 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
20964 .addMBB(restoreMBB)
20967 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
20968 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
20969 .addReg(XII->getGlobalBaseReg(MF))
20972 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
20976 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
20978 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
20979 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20980 if (i == X86::AddrDisp)
20981 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
20983 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
20986 MIB.addReg(LabelReg);
20988 MIB.addMBB(restoreMBB);
20989 MIB.setMemRefs(MMOBegin, MMOEnd);
20991 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
20992 .addMBB(restoreMBB);
20994 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20995 MF->getSubtarget().getRegisterInfo());
20996 MIB.addRegMask(RegInfo->getNoPreservedMask());
20997 thisMBB->addSuccessor(mainMBB);
20998 thisMBB->addSuccessor(restoreMBB);
21002 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21003 mainMBB->addSuccessor(sinkMBB);
21006 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21007 TII->get(X86::PHI), DstReg)
21008 .addReg(mainDstReg).addMBB(mainMBB)
21009 .addReg(restoreDstReg).addMBB(restoreMBB);
21012 if (RegInfo->hasBasePointer(*MF)) {
21013 const X86Subtarget &STI = MF->getTarget().getSubtarget<X86Subtarget>();
21014 const bool Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
21015 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21016 X86FI->setRestoreBasePointer(MF);
21017 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21018 unsigned BasePtr = RegInfo->getBaseRegister();
21019 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21020 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21021 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21022 .setMIFlag(MachineInstr::FrameSetup);
21024 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21025 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
21026 restoreMBB->addSuccessor(sinkMBB);
21028 MI->eraseFromParent();
21032 MachineBasicBlock *
21033 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21034 MachineBasicBlock *MBB) const {
21035 DebugLoc DL = MI->getDebugLoc();
21036 MachineFunction *MF = MBB->getParent();
21037 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
21038 MachineRegisterInfo &MRI = MF->getRegInfo();
21040 // Memory Reference
21041 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21042 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21044 MVT PVT = getPointerTy();
21045 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21046 "Invalid Pointer Size!");
21048 const TargetRegisterClass *RC =
21049 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21050 unsigned Tmp = MRI.createVirtualRegister(RC);
21051 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21052 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
21053 MF->getSubtarget().getRegisterInfo());
21054 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21055 unsigned SP = RegInfo->getStackRegister();
21057 MachineInstrBuilder MIB;
21059 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21060 const int64_t SPOffset = 2 * PVT.getStoreSize();
21062 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21063 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21066 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21067 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21068 MIB.addOperand(MI->getOperand(i));
21069 MIB.setMemRefs(MMOBegin, MMOEnd);
21071 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21072 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21073 if (i == X86::AddrDisp)
21074 MIB.addDisp(MI->getOperand(i), LabelOffset);
21076 MIB.addOperand(MI->getOperand(i));
21078 MIB.setMemRefs(MMOBegin, MMOEnd);
21080 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21081 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21082 if (i == X86::AddrDisp)
21083 MIB.addDisp(MI->getOperand(i), SPOffset);
21085 MIB.addOperand(MI->getOperand(i));
21087 MIB.setMemRefs(MMOBegin, MMOEnd);
21089 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21091 MI->eraseFromParent();
21095 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21096 // accumulator loops. Writing back to the accumulator allows the coalescer
21097 // to remove extra copies in the loop.
21098 MachineBasicBlock *
21099 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21100 MachineBasicBlock *MBB) const {
21101 MachineOperand &AddendOp = MI->getOperand(3);
21103 // Bail out early if the addend isn't a register - we can't switch these.
21104 if (!AddendOp.isReg())
21107 MachineFunction &MF = *MBB->getParent();
21108 MachineRegisterInfo &MRI = MF.getRegInfo();
21110 // Check whether the addend is defined by a PHI:
21111 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21112 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21113 if (!AddendDef.isPHI())
21116 // Look for the following pattern:
21118 // %addend = phi [%entry, 0], [%loop, %result]
21120 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21124 // %addend = phi [%entry, 0], [%loop, %result]
21126 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21128 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21129 assert(AddendDef.getOperand(i).isReg());
21130 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21131 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21132 if (&PHISrcInst == MI) {
21133 // Found a matching instruction.
21134 unsigned NewFMAOpc = 0;
21135 switch (MI->getOpcode()) {
21136 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21137 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21138 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21139 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21140 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21141 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21142 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21143 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21144 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21145 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21146 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21147 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21148 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21149 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21150 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21151 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21152 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21153 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21154 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21155 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21157 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21158 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21159 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21160 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21161 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21162 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21163 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21164 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21165 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21166 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21167 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21168 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21169 default: llvm_unreachable("Unrecognized FMA variant.");
21172 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
21173 MachineInstrBuilder MIB =
21174 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21175 .addOperand(MI->getOperand(0))
21176 .addOperand(MI->getOperand(3))
21177 .addOperand(MI->getOperand(2))
21178 .addOperand(MI->getOperand(1));
21179 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21180 MI->eraseFromParent();
21187 MachineBasicBlock *
21188 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21189 MachineBasicBlock *BB) const {
21190 switch (MI->getOpcode()) {
21191 default: llvm_unreachable("Unexpected instr type to insert");
21192 case X86::TAILJMPd64:
21193 case X86::TAILJMPr64:
21194 case X86::TAILJMPm64:
21195 llvm_unreachable("TAILJMP64 would not be touched here.");
21196 case X86::TCRETURNdi64:
21197 case X86::TCRETURNri64:
21198 case X86::TCRETURNmi64:
21200 case X86::WIN_ALLOCA:
21201 return EmitLoweredWinAlloca(MI, BB);
21202 case X86::SEG_ALLOCA_32:
21203 case X86::SEG_ALLOCA_64:
21204 return EmitLoweredSegAlloca(MI, BB);
21205 case X86::TLSCall_32:
21206 case X86::TLSCall_64:
21207 return EmitLoweredTLSCall(MI, BB);
21208 case X86::CMOV_GR8:
21209 case X86::CMOV_FR32:
21210 case X86::CMOV_FR64:
21211 case X86::CMOV_V4F32:
21212 case X86::CMOV_V2F64:
21213 case X86::CMOV_V2I64:
21214 case X86::CMOV_V8F32:
21215 case X86::CMOV_V4F64:
21216 case X86::CMOV_V4I64:
21217 case X86::CMOV_V16F32:
21218 case X86::CMOV_V8F64:
21219 case X86::CMOV_V8I64:
21220 case X86::CMOV_GR16:
21221 case X86::CMOV_GR32:
21222 case X86::CMOV_RFP32:
21223 case X86::CMOV_RFP64:
21224 case X86::CMOV_RFP80:
21225 return EmitLoweredSelect(MI, BB);
21227 case X86::FP32_TO_INT16_IN_MEM:
21228 case X86::FP32_TO_INT32_IN_MEM:
21229 case X86::FP32_TO_INT64_IN_MEM:
21230 case X86::FP64_TO_INT16_IN_MEM:
21231 case X86::FP64_TO_INT32_IN_MEM:
21232 case X86::FP64_TO_INT64_IN_MEM:
21233 case X86::FP80_TO_INT16_IN_MEM:
21234 case X86::FP80_TO_INT32_IN_MEM:
21235 case X86::FP80_TO_INT64_IN_MEM: {
21236 MachineFunction *F = BB->getParent();
21237 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
21238 DebugLoc DL = MI->getDebugLoc();
21240 // Change the floating point control register to use "round towards zero"
21241 // mode when truncating to an integer value.
21242 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21243 addFrameReference(BuildMI(*BB, MI, DL,
21244 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21246 // Load the old value of the high byte of the control word...
21248 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21249 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21252 // Set the high part to be round to zero...
21253 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21256 // Reload the modified control word now...
21257 addFrameReference(BuildMI(*BB, MI, DL,
21258 TII->get(X86::FLDCW16m)), CWFrameIdx);
21260 // Restore the memory image of control word to original value
21261 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21264 // Get the X86 opcode to use.
21266 switch (MI->getOpcode()) {
21267 default: llvm_unreachable("illegal opcode!");
21268 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21269 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21270 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21271 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21272 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21273 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21274 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21275 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21276 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21280 MachineOperand &Op = MI->getOperand(0);
21282 AM.BaseType = X86AddressMode::RegBase;
21283 AM.Base.Reg = Op.getReg();
21285 AM.BaseType = X86AddressMode::FrameIndexBase;
21286 AM.Base.FrameIndex = Op.getIndex();
21288 Op = MI->getOperand(1);
21290 AM.Scale = Op.getImm();
21291 Op = MI->getOperand(2);
21293 AM.IndexReg = Op.getImm();
21294 Op = MI->getOperand(3);
21295 if (Op.isGlobal()) {
21296 AM.GV = Op.getGlobal();
21298 AM.Disp = Op.getImm();
21300 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21301 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21303 // Reload the original control word now.
21304 addFrameReference(BuildMI(*BB, MI, DL,
21305 TII->get(X86::FLDCW16m)), CWFrameIdx);
21307 MI->eraseFromParent(); // The pseudo instruction is gone now.
21310 // String/text processing lowering.
21311 case X86::PCMPISTRM128REG:
21312 case X86::VPCMPISTRM128REG:
21313 case X86::PCMPISTRM128MEM:
21314 case X86::VPCMPISTRM128MEM:
21315 case X86::PCMPESTRM128REG:
21316 case X86::VPCMPESTRM128REG:
21317 case X86::PCMPESTRM128MEM:
21318 case X86::VPCMPESTRM128MEM:
21319 assert(Subtarget->hasSSE42() &&
21320 "Target must have SSE4.2 or AVX features enabled");
21321 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21323 // String/text processing lowering.
21324 case X86::PCMPISTRIREG:
21325 case X86::VPCMPISTRIREG:
21326 case X86::PCMPISTRIMEM:
21327 case X86::VPCMPISTRIMEM:
21328 case X86::PCMPESTRIREG:
21329 case X86::VPCMPESTRIREG:
21330 case X86::PCMPESTRIMEM:
21331 case X86::VPCMPESTRIMEM:
21332 assert(Subtarget->hasSSE42() &&
21333 "Target must have SSE4.2 or AVX features enabled");
21334 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21336 // Thread synchronization.
21338 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
21343 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21345 case X86::VASTART_SAVE_XMM_REGS:
21346 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21348 case X86::VAARG_64:
21349 return EmitVAARG64WithCustomInserter(MI, BB);
21351 case X86::EH_SjLj_SetJmp32:
21352 case X86::EH_SjLj_SetJmp64:
21353 return emitEHSjLjSetJmp(MI, BB);
21355 case X86::EH_SjLj_LongJmp32:
21356 case X86::EH_SjLj_LongJmp64:
21357 return emitEHSjLjLongJmp(MI, BB);
21359 case TargetOpcode::STATEPOINT:
21360 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21361 // this point in the process. We diverge later.
21362 return emitPatchPoint(MI, BB);
21364 case TargetOpcode::STACKMAP:
21365 case TargetOpcode::PATCHPOINT:
21366 return emitPatchPoint(MI, BB);
21368 case X86::VFMADDPDr213r:
21369 case X86::VFMADDPSr213r:
21370 case X86::VFMADDSDr213r:
21371 case X86::VFMADDSSr213r:
21372 case X86::VFMSUBPDr213r:
21373 case X86::VFMSUBPSr213r:
21374 case X86::VFMSUBSDr213r:
21375 case X86::VFMSUBSSr213r:
21376 case X86::VFNMADDPDr213r:
21377 case X86::VFNMADDPSr213r:
21378 case X86::VFNMADDSDr213r:
21379 case X86::VFNMADDSSr213r:
21380 case X86::VFNMSUBPDr213r:
21381 case X86::VFNMSUBPSr213r:
21382 case X86::VFNMSUBSDr213r:
21383 case X86::VFNMSUBSSr213r:
21384 case X86::VFMADDSUBPDr213r:
21385 case X86::VFMADDSUBPSr213r:
21386 case X86::VFMSUBADDPDr213r:
21387 case X86::VFMSUBADDPSr213r:
21388 case X86::VFMADDPDr213rY:
21389 case X86::VFMADDPSr213rY:
21390 case X86::VFMSUBPDr213rY:
21391 case X86::VFMSUBPSr213rY:
21392 case X86::VFNMADDPDr213rY:
21393 case X86::VFNMADDPSr213rY:
21394 case X86::VFNMSUBPDr213rY:
21395 case X86::VFNMSUBPSr213rY:
21396 case X86::VFMADDSUBPDr213rY:
21397 case X86::VFMADDSUBPSr213rY:
21398 case X86::VFMSUBADDPDr213rY:
21399 case X86::VFMSUBADDPSr213rY:
21400 return emitFMA3Instr(MI, BB);
21404 //===----------------------------------------------------------------------===//
21405 // X86 Optimization Hooks
21406 //===----------------------------------------------------------------------===//
21408 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21411 const SelectionDAG &DAG,
21412 unsigned Depth) const {
21413 unsigned BitWidth = KnownZero.getBitWidth();
21414 unsigned Opc = Op.getOpcode();
21415 assert((Opc >= ISD::BUILTIN_OP_END ||
21416 Opc == ISD::INTRINSIC_WO_CHAIN ||
21417 Opc == ISD::INTRINSIC_W_CHAIN ||
21418 Opc == ISD::INTRINSIC_VOID) &&
21419 "Should use MaskedValueIsZero if you don't know whether Op"
21420 " is a target node!");
21422 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21436 // These nodes' second result is a boolean.
21437 if (Op.getResNo() == 0)
21440 case X86ISD::SETCC:
21441 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21443 case ISD::INTRINSIC_WO_CHAIN: {
21444 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21445 unsigned NumLoBits = 0;
21448 case Intrinsic::x86_sse_movmsk_ps:
21449 case Intrinsic::x86_avx_movmsk_ps_256:
21450 case Intrinsic::x86_sse2_movmsk_pd:
21451 case Intrinsic::x86_avx_movmsk_pd_256:
21452 case Intrinsic::x86_mmx_pmovmskb:
21453 case Intrinsic::x86_sse2_pmovmskb_128:
21454 case Intrinsic::x86_avx2_pmovmskb: {
21455 // High bits of movmskp{s|d}, pmovmskb are known zero.
21457 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21458 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21459 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21460 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21461 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21462 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21463 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21464 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21466 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21475 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21477 const SelectionDAG &,
21478 unsigned Depth) const {
21479 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21480 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21481 return Op.getValueType().getScalarType().getSizeInBits();
21487 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21488 /// node is a GlobalAddress + offset.
21489 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21490 const GlobalValue* &GA,
21491 int64_t &Offset) const {
21492 if (N->getOpcode() == X86ISD::Wrapper) {
21493 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21494 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21495 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21499 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21502 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21503 /// same as extracting the high 128-bit part of 256-bit vector and then
21504 /// inserting the result into the low part of a new 256-bit vector
21505 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21506 EVT VT = SVOp->getValueType(0);
21507 unsigned NumElems = VT.getVectorNumElements();
21509 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21510 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21511 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21512 SVOp->getMaskElt(j) >= 0)
21518 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21519 /// same as extracting the low 128-bit part of 256-bit vector and then
21520 /// inserting the result into the high part of a new 256-bit vector
21521 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21522 EVT VT = SVOp->getValueType(0);
21523 unsigned NumElems = VT.getVectorNumElements();
21525 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21526 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21527 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21528 SVOp->getMaskElt(j) >= 0)
21534 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21535 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21536 TargetLowering::DAGCombinerInfo &DCI,
21537 const X86Subtarget* Subtarget) {
21539 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21540 SDValue V1 = SVOp->getOperand(0);
21541 SDValue V2 = SVOp->getOperand(1);
21542 EVT VT = SVOp->getValueType(0);
21543 unsigned NumElems = VT.getVectorNumElements();
21545 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21546 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21550 // V UNDEF BUILD_VECTOR UNDEF
21552 // CONCAT_VECTOR CONCAT_VECTOR
21555 // RESULT: V + zero extended
21557 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21558 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21559 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21562 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21565 // To match the shuffle mask, the first half of the mask should
21566 // be exactly the first vector, and all the rest a splat with the
21567 // first element of the second one.
21568 for (unsigned i = 0; i != NumElems/2; ++i)
21569 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21570 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21573 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21574 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21575 if (Ld->hasNUsesOfValue(1, 0)) {
21576 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21577 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21579 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21581 Ld->getPointerInfo(),
21582 Ld->getAlignment(),
21583 false/*isVolatile*/, true/*ReadMem*/,
21584 false/*WriteMem*/);
21586 // Make sure the newly-created LOAD is in the same position as Ld in
21587 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21588 // and update uses of Ld's output chain to use the TokenFactor.
21589 if (Ld->hasAnyUseOfValue(1)) {
21590 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21591 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21592 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21593 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21594 SDValue(ResNode.getNode(), 1));
21597 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
21601 // Emit a zeroed vector and insert the desired subvector on its
21603 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21604 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21605 return DCI.CombineTo(N, InsV);
21608 //===--------------------------------------------------------------------===//
21609 // Combine some shuffles into subvector extracts and inserts:
21612 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21613 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21614 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21615 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21616 return DCI.CombineTo(N, InsV);
21619 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21620 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21621 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21622 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21623 return DCI.CombineTo(N, InsV);
21629 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21632 /// This is the leaf of the recursive combinine below. When we have found some
21633 /// chain of single-use x86 shuffle instructions and accumulated the combined
21634 /// shuffle mask represented by them, this will try to pattern match that mask
21635 /// into either a single instruction if there is a special purpose instruction
21636 /// for this operation, or into a PSHUFB instruction which is a fully general
21637 /// instruction but should only be used to replace chains over a certain depth.
21638 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21639 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21640 TargetLowering::DAGCombinerInfo &DCI,
21641 const X86Subtarget *Subtarget) {
21642 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21644 // Find the operand that enters the chain. Note that multiple uses are OK
21645 // here, we're not going to remove the operand we find.
21646 SDValue Input = Op.getOperand(0);
21647 while (Input.getOpcode() == ISD::BITCAST)
21648 Input = Input.getOperand(0);
21650 MVT VT = Input.getSimpleValueType();
21651 MVT RootVT = Root.getSimpleValueType();
21654 // Just remove no-op shuffle masks.
21655 if (Mask.size() == 1) {
21656 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
21661 // Use the float domain if the operand type is a floating point type.
21662 bool FloatDomain = VT.isFloatingPoint();
21664 // For floating point shuffles, we don't have free copies in the shuffle
21665 // instructions or the ability to load as part of the instruction, so
21666 // canonicalize their shuffles to UNPCK or MOV variants.
21668 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21669 // vectors because it can have a load folded into it that UNPCK cannot. This
21670 // doesn't preclude something switching to the shorter encoding post-RA.
21672 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
21673 bool Lo = Mask.equals(0, 0);
21676 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21677 // is no slower than UNPCKLPD but has the option to fold the input operand
21678 // into even an unaligned memory load.
21679 if (Lo && Subtarget->hasSSE3()) {
21680 Shuffle = X86ISD::MOVDDUP;
21681 ShuffleVT = MVT::v2f64;
21683 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21684 // than the UNPCK variants.
21685 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21686 ShuffleVT = MVT::v4f32;
21688 if (Depth == 1 && Root->getOpcode() == Shuffle)
21689 return false; // Nothing to do!
21690 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21691 DCI.AddToWorklist(Op.getNode());
21692 if (Shuffle == X86ISD::MOVDDUP)
21693 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21695 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21696 DCI.AddToWorklist(Op.getNode());
21697 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21701 if (Subtarget->hasSSE3() &&
21702 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
21703 bool Lo = Mask.equals(0, 0, 2, 2);
21704 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21705 MVT ShuffleVT = MVT::v4f32;
21706 if (Depth == 1 && Root->getOpcode() == Shuffle)
21707 return false; // Nothing to do!
21708 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21709 DCI.AddToWorklist(Op.getNode());
21710 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21711 DCI.AddToWorklist(Op.getNode());
21712 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21716 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
21717 bool Lo = Mask.equals(0, 0, 1, 1);
21718 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21719 MVT ShuffleVT = MVT::v4f32;
21720 if (Depth == 1 && Root->getOpcode() == Shuffle)
21721 return false; // Nothing to do!
21722 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21723 DCI.AddToWorklist(Op.getNode());
21724 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21725 DCI.AddToWorklist(Op.getNode());
21726 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21732 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
21733 // variants as none of these have single-instruction variants that are
21734 // superior to the UNPCK formulation.
21735 if (!FloatDomain &&
21736 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
21737 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
21738 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
21739 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
21741 bool Lo = Mask[0] == 0;
21742 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21743 if (Depth == 1 && Root->getOpcode() == Shuffle)
21744 return false; // Nothing to do!
21746 switch (Mask.size()) {
21748 ShuffleVT = MVT::v8i16;
21751 ShuffleVT = MVT::v16i8;
21754 llvm_unreachable("Impossible mask size!");
21756 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21757 DCI.AddToWorklist(Op.getNode());
21758 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21759 DCI.AddToWorklist(Op.getNode());
21760 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21765 // Don't try to re-form single instruction chains under any circumstances now
21766 // that we've done encoding canonicalization for them.
21770 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
21771 // can replace them with a single PSHUFB instruction profitably. Intel's
21772 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
21773 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
21774 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
21775 SmallVector<SDValue, 16> PSHUFBMask;
21776 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
21777 int Ratio = 16 / Mask.size();
21778 for (unsigned i = 0; i < 16; ++i) {
21779 if (Mask[i / Ratio] == SM_SentinelUndef) {
21780 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
21783 int M = Mask[i / Ratio] != SM_SentinelZero
21784 ? Ratio * Mask[i / Ratio] + i % Ratio
21786 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
21788 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
21789 DCI.AddToWorklist(Op.getNode());
21790 SDValue PSHUFBMaskOp =
21791 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
21792 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
21793 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
21794 DCI.AddToWorklist(Op.getNode());
21795 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21800 // Failed to find any combines.
21804 /// \brief Fully generic combining of x86 shuffle instructions.
21806 /// This should be the last combine run over the x86 shuffle instructions. Once
21807 /// they have been fully optimized, this will recursively consider all chains
21808 /// of single-use shuffle instructions, build a generic model of the cumulative
21809 /// shuffle operation, and check for simpler instructions which implement this
21810 /// operation. We use this primarily for two purposes:
21812 /// 1) Collapse generic shuffles to specialized single instructions when
21813 /// equivalent. In most cases, this is just an encoding size win, but
21814 /// sometimes we will collapse multiple generic shuffles into a single
21815 /// special-purpose shuffle.
21816 /// 2) Look for sequences of shuffle instructions with 3 or more total
21817 /// instructions, and replace them with the slightly more expensive SSSE3
21818 /// PSHUFB instruction if available. We do this as the last combining step
21819 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
21820 /// a suitable short sequence of other instructions. The PHUFB will either
21821 /// use a register or have to read from memory and so is slightly (but only
21822 /// slightly) more expensive than the other shuffle instructions.
21824 /// Because this is inherently a quadratic operation (for each shuffle in
21825 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
21826 /// This should never be an issue in practice as the shuffle lowering doesn't
21827 /// produce sequences of more than 8 instructions.
21829 /// FIXME: We will currently miss some cases where the redundant shuffling
21830 /// would simplify under the threshold for PSHUFB formation because of
21831 /// combine-ordering. To fix this, we should do the redundant instruction
21832 /// combining in this recursive walk.
21833 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
21834 ArrayRef<int> RootMask,
21835 int Depth, bool HasPSHUFB,
21837 TargetLowering::DAGCombinerInfo &DCI,
21838 const X86Subtarget *Subtarget) {
21839 // Bound the depth of our recursive combine because this is ultimately
21840 // quadratic in nature.
21844 // Directly rip through bitcasts to find the underlying operand.
21845 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
21846 Op = Op.getOperand(0);
21848 MVT VT = Op.getSimpleValueType();
21849 if (!VT.isVector())
21850 return false; // Bail if we hit a non-vector.
21851 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
21852 // version should be added.
21853 if (VT.getSizeInBits() != 128)
21856 assert(Root.getSimpleValueType().isVector() &&
21857 "Shuffles operate on vector types!");
21858 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
21859 "Can only combine shuffles of the same vector register size.");
21861 if (!isTargetShuffle(Op.getOpcode()))
21863 SmallVector<int, 16> OpMask;
21865 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
21866 // We only can combine unary shuffles which we can decode the mask for.
21867 if (!HaveMask || !IsUnary)
21870 assert(VT.getVectorNumElements() == OpMask.size() &&
21871 "Different mask size from vector size!");
21872 assert(((RootMask.size() > OpMask.size() &&
21873 RootMask.size() % OpMask.size() == 0) ||
21874 (OpMask.size() > RootMask.size() &&
21875 OpMask.size() % RootMask.size() == 0) ||
21876 OpMask.size() == RootMask.size()) &&
21877 "The smaller number of elements must divide the larger.");
21878 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
21879 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
21880 assert(((RootRatio == 1 && OpRatio == 1) ||
21881 (RootRatio == 1) != (OpRatio == 1)) &&
21882 "Must not have a ratio for both incoming and op masks!");
21884 SmallVector<int, 16> Mask;
21885 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
21887 // Merge this shuffle operation's mask into our accumulated mask. Note that
21888 // this shuffle's mask will be the first applied to the input, followed by the
21889 // root mask to get us all the way to the root value arrangement. The reason
21890 // for this order is that we are recursing up the operation chain.
21891 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
21892 int RootIdx = i / RootRatio;
21893 if (RootMask[RootIdx] < 0) {
21894 // This is a zero or undef lane, we're done.
21895 Mask.push_back(RootMask[RootIdx]);
21899 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
21900 int OpIdx = RootMaskedIdx / OpRatio;
21901 if (OpMask[OpIdx] < 0) {
21902 // The incoming lanes are zero or undef, it doesn't matter which ones we
21904 Mask.push_back(OpMask[OpIdx]);
21908 // Ok, we have non-zero lanes, map them through.
21909 Mask.push_back(OpMask[OpIdx] * OpRatio +
21910 RootMaskedIdx % OpRatio);
21913 // See if we can recurse into the operand to combine more things.
21914 switch (Op.getOpcode()) {
21915 case X86ISD::PSHUFB:
21917 case X86ISD::PSHUFD:
21918 case X86ISD::PSHUFHW:
21919 case X86ISD::PSHUFLW:
21920 if (Op.getOperand(0).hasOneUse() &&
21921 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21922 HasPSHUFB, DAG, DCI, Subtarget))
21926 case X86ISD::UNPCKL:
21927 case X86ISD::UNPCKH:
21928 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
21929 // We can't check for single use, we have to check that this shuffle is the only user.
21930 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
21931 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21932 HasPSHUFB, DAG, DCI, Subtarget))
21937 // Minor canonicalization of the accumulated shuffle mask to make it easier
21938 // to match below. All this does is detect masks with squential pairs of
21939 // elements, and shrink them to the half-width mask. It does this in a loop
21940 // so it will reduce the size of the mask to the minimal width mask which
21941 // performs an equivalent shuffle.
21942 SmallVector<int, 16> WidenedMask;
21943 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
21944 Mask = std::move(WidenedMask);
21945 WidenedMask.clear();
21948 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
21952 /// \brief Get the PSHUF-style mask from PSHUF node.
21954 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
21955 /// PSHUF-style masks that can be reused with such instructions.
21956 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
21957 SmallVector<int, 4> Mask;
21959 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
21963 switch (N.getOpcode()) {
21964 case X86ISD::PSHUFD:
21966 case X86ISD::PSHUFLW:
21969 case X86ISD::PSHUFHW:
21970 Mask.erase(Mask.begin(), Mask.begin() + 4);
21971 for (int &M : Mask)
21975 llvm_unreachable("No valid shuffle instruction found!");
21979 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
21981 /// We walk up the chain and look for a combinable shuffle, skipping over
21982 /// shuffles that we could hoist this shuffle's transformation past without
21983 /// altering anything.
21985 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
21987 TargetLowering::DAGCombinerInfo &DCI) {
21988 assert(N.getOpcode() == X86ISD::PSHUFD &&
21989 "Called with something other than an x86 128-bit half shuffle!");
21992 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
21993 // of the shuffles in the chain so that we can form a fresh chain to replace
21995 SmallVector<SDValue, 8> Chain;
21996 SDValue V = N.getOperand(0);
21997 for (; V.hasOneUse(); V = V.getOperand(0)) {
21998 switch (V.getOpcode()) {
22000 return SDValue(); // Nothing combined!
22003 // Skip bitcasts as we always know the type for the target specific
22007 case X86ISD::PSHUFD:
22008 // Found another dword shuffle.
22011 case X86ISD::PSHUFLW:
22012 // Check that the low words (being shuffled) are the identity in the
22013 // dword shuffle, and the high words are self-contained.
22014 if (Mask[0] != 0 || Mask[1] != 1 ||
22015 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22018 Chain.push_back(V);
22021 case X86ISD::PSHUFHW:
22022 // Check that the high words (being shuffled) are the identity in the
22023 // dword shuffle, and the low words are self-contained.
22024 if (Mask[2] != 2 || Mask[3] != 3 ||
22025 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22028 Chain.push_back(V);
22031 case X86ISD::UNPCKL:
22032 case X86ISD::UNPCKH:
22033 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22034 // shuffle into a preceding word shuffle.
22035 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
22038 // Search for a half-shuffle which we can combine with.
22039 unsigned CombineOp =
22040 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22041 if (V.getOperand(0) != V.getOperand(1) ||
22042 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22044 Chain.push_back(V);
22045 V = V.getOperand(0);
22047 switch (V.getOpcode()) {
22049 return SDValue(); // Nothing to combine.
22051 case X86ISD::PSHUFLW:
22052 case X86ISD::PSHUFHW:
22053 if (V.getOpcode() == CombineOp)
22056 Chain.push_back(V);
22060 V = V.getOperand(0);
22064 } while (V.hasOneUse());
22067 // Break out of the loop if we break out of the switch.
22071 if (!V.hasOneUse())
22072 // We fell out of the loop without finding a viable combining instruction.
22075 // Merge this node's mask and our incoming mask.
22076 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22077 for (int &M : Mask)
22079 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22080 getV4X86ShuffleImm8ForMask(Mask, DAG));
22082 // Rebuild the chain around this new shuffle.
22083 while (!Chain.empty()) {
22084 SDValue W = Chain.pop_back_val();
22086 if (V.getValueType() != W.getOperand(0).getValueType())
22087 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
22089 switch (W.getOpcode()) {
22091 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22093 case X86ISD::UNPCKL:
22094 case X86ISD::UNPCKH:
22095 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22098 case X86ISD::PSHUFD:
22099 case X86ISD::PSHUFLW:
22100 case X86ISD::PSHUFHW:
22101 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22105 if (V.getValueType() != N.getValueType())
22106 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
22108 // Return the new chain to replace N.
22112 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
22114 /// We walk up the chain, skipping shuffles of the other half and looking
22115 /// through shuffles which switch halves trying to find a shuffle of the same
22116 /// pair of dwords.
22117 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22119 TargetLowering::DAGCombinerInfo &DCI) {
22121 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22122 "Called with something other than an x86 128-bit half shuffle!");
22124 unsigned CombineOpcode = N.getOpcode();
22126 // Walk up a single-use chain looking for a combinable shuffle.
22127 SDValue V = N.getOperand(0);
22128 for (; V.hasOneUse(); V = V.getOperand(0)) {
22129 switch (V.getOpcode()) {
22131 return false; // Nothing combined!
22134 // Skip bitcasts as we always know the type for the target specific
22138 case X86ISD::PSHUFLW:
22139 case X86ISD::PSHUFHW:
22140 if (V.getOpcode() == CombineOpcode)
22143 // Other-half shuffles are no-ops.
22146 // Break out of the loop if we break out of the switch.
22150 if (!V.hasOneUse())
22151 // We fell out of the loop without finding a viable combining instruction.
22154 // Combine away the bottom node as its shuffle will be accumulated into
22155 // a preceding shuffle.
22156 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22158 // Record the old value.
22161 // Merge this node's mask and our incoming mask (adjusted to account for all
22162 // the pshufd instructions encountered).
22163 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22164 for (int &M : Mask)
22166 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22167 getV4X86ShuffleImm8ForMask(Mask, DAG));
22169 // Check that the shuffles didn't cancel each other out. If not, we need to
22170 // combine to the new one.
22172 // Replace the combinable shuffle with the combined one, updating all users
22173 // so that we re-evaluate the chain here.
22174 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22179 /// \brief Try to combine x86 target specific shuffles.
22180 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22181 TargetLowering::DAGCombinerInfo &DCI,
22182 const X86Subtarget *Subtarget) {
22184 MVT VT = N.getSimpleValueType();
22185 SmallVector<int, 4> Mask;
22187 switch (N.getOpcode()) {
22188 case X86ISD::PSHUFD:
22189 case X86ISD::PSHUFLW:
22190 case X86ISD::PSHUFHW:
22191 Mask = getPSHUFShuffleMask(N);
22192 assert(Mask.size() == 4);
22198 // Nuke no-op shuffles that show up after combining.
22199 if (isNoopShuffleMask(Mask))
22200 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22202 // Look for simplifications involving one or two shuffle instructions.
22203 SDValue V = N.getOperand(0);
22204 switch (N.getOpcode()) {
22207 case X86ISD::PSHUFLW:
22208 case X86ISD::PSHUFHW:
22209 assert(VT == MVT::v8i16);
22212 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22213 return SDValue(); // We combined away this shuffle, so we're done.
22215 // See if this reduces to a PSHUFD which is no more expensive and can
22216 // combine with more operations. Note that it has to at least flip the
22217 // dwords as otherwise it would have been removed as a no-op.
22218 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
22219 int DMask[] = {0, 1, 2, 3};
22220 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22221 DMask[DOffset + 0] = DOffset + 1;
22222 DMask[DOffset + 1] = DOffset + 0;
22223 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
22224 DCI.AddToWorklist(V.getNode());
22225 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
22226 getV4X86ShuffleImm8ForMask(DMask, DAG));
22227 DCI.AddToWorklist(V.getNode());
22228 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
22231 // Look for shuffle patterns which can be implemented as a single unpack.
22232 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22233 // only works when we have a PSHUFD followed by two half-shuffles.
22234 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22235 (V.getOpcode() == X86ISD::PSHUFLW ||
22236 V.getOpcode() == X86ISD::PSHUFHW) &&
22237 V.getOpcode() != N.getOpcode() &&
22239 SDValue D = V.getOperand(0);
22240 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22241 D = D.getOperand(0);
22242 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22243 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22244 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22245 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22246 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22248 for (int i = 0; i < 4; ++i) {
22249 WordMask[i + NOffset] = Mask[i] + NOffset;
22250 WordMask[i + VOffset] = VMask[i] + VOffset;
22252 // Map the word mask through the DWord mask.
22254 for (int i = 0; i < 8; ++i)
22255 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22256 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
22257 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
22258 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
22259 std::begin(UnpackLoMask)) ||
22260 std::equal(std::begin(MappedMask), std::end(MappedMask),
22261 std::begin(UnpackHiMask))) {
22262 // We can replace all three shuffles with an unpack.
22263 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
22264 DCI.AddToWorklist(V.getNode());
22265 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22267 DL, MVT::v8i16, V, V);
22274 case X86ISD::PSHUFD:
22275 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22284 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22286 /// We combine this directly on the abstract vector shuffle nodes so it is
22287 /// easier to generically match. We also insert dummy vector shuffle nodes for
22288 /// the operands which explicitly discard the lanes which are unused by this
22289 /// operation to try to flow through the rest of the combiner the fact that
22290 /// they're unused.
22291 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22293 EVT VT = N->getValueType(0);
22295 // We only handle target-independent shuffles.
22296 // FIXME: It would be easy and harmless to use the target shuffle mask
22297 // extraction tool to support more.
22298 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22301 auto *SVN = cast<ShuffleVectorSDNode>(N);
22302 ArrayRef<int> Mask = SVN->getMask();
22303 SDValue V1 = N->getOperand(0);
22304 SDValue V2 = N->getOperand(1);
22306 // We require the first shuffle operand to be the SUB node, and the second to
22307 // be the ADD node.
22308 // FIXME: We should support the commuted patterns.
22309 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22312 // If there are other uses of these operations we can't fold them.
22313 if (!V1->hasOneUse() || !V2->hasOneUse())
22316 // Ensure that both operations have the same operands. Note that we can
22317 // commute the FADD operands.
22318 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22319 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22320 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22323 // We're looking for blends between FADD and FSUB nodes. We insist on these
22324 // nodes being lined up in a specific expected pattern.
22325 if (!(isShuffleEquivalent(Mask, 0, 3) ||
22326 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
22327 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
22330 // Only specific types are legal at this point, assert so we notice if and
22331 // when these change.
22332 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22333 VT == MVT::v4f64) &&
22334 "Unknown vector type encountered!");
22336 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22339 /// PerformShuffleCombine - Performs several different shuffle combines.
22340 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22341 TargetLowering::DAGCombinerInfo &DCI,
22342 const X86Subtarget *Subtarget) {
22344 SDValue N0 = N->getOperand(0);
22345 SDValue N1 = N->getOperand(1);
22346 EVT VT = N->getValueType(0);
22348 // Don't create instructions with illegal types after legalize types has run.
22349 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22350 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22353 // If we have legalized the vector types, look for blends of FADD and FSUB
22354 // nodes that we can fuse into an ADDSUB node.
22355 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22356 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22359 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22360 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22361 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22362 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22364 // During Type Legalization, when promoting illegal vector types,
22365 // the backend might introduce new shuffle dag nodes and bitcasts.
22367 // This code performs the following transformation:
22368 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22369 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22371 // We do this only if both the bitcast and the BINOP dag nodes have
22372 // one use. Also, perform this transformation only if the new binary
22373 // operation is legal. This is to avoid introducing dag nodes that
22374 // potentially need to be further expanded (or custom lowered) into a
22375 // less optimal sequence of dag nodes.
22376 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22377 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22378 N0.getOpcode() == ISD::BITCAST) {
22379 SDValue BC0 = N0.getOperand(0);
22380 EVT SVT = BC0.getValueType();
22381 unsigned Opcode = BC0.getOpcode();
22382 unsigned NumElts = VT.getVectorNumElements();
22384 if (BC0.hasOneUse() && SVT.isVector() &&
22385 SVT.getVectorNumElements() * 2 == NumElts &&
22386 TLI.isOperationLegal(Opcode, VT)) {
22387 bool CanFold = false;
22399 unsigned SVTNumElts = SVT.getVectorNumElements();
22400 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22401 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22402 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22403 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22404 CanFold = SVOp->getMaskElt(i) < 0;
22407 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
22408 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
22409 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22410 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22415 // Only handle 128 wide vector from here on.
22416 if (!VT.is128BitVector())
22419 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22420 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22421 // consecutive, non-overlapping, and in the right order.
22422 SmallVector<SDValue, 16> Elts;
22423 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22424 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22426 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
22430 if (isTargetShuffle(N->getOpcode())) {
22432 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22433 if (Shuffle.getNode())
22436 // Try recursively combining arbitrary sequences of x86 shuffle
22437 // instructions into higher-order shuffles. We do this after combining
22438 // specific PSHUF instruction sequences into their minimal form so that we
22439 // can evaluate how many specialized shuffle instructions are involved in
22440 // a particular chain.
22441 SmallVector<int, 1> NonceMask; // Just a placeholder.
22442 NonceMask.push_back(0);
22443 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22444 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22446 return SDValue(); // This routine will use CombineTo to replace N.
22452 /// PerformTruncateCombine - Converts truncate operation to
22453 /// a sequence of vector shuffle operations.
22454 /// It is possible when we truncate 256-bit vector to 128-bit vector
22455 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
22456 TargetLowering::DAGCombinerInfo &DCI,
22457 const X86Subtarget *Subtarget) {
22461 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22462 /// specific shuffle of a load can be folded into a single element load.
22463 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22464 /// shuffles have been custom lowered so we need to handle those here.
22465 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22466 TargetLowering::DAGCombinerInfo &DCI) {
22467 if (DCI.isBeforeLegalizeOps())
22470 SDValue InVec = N->getOperand(0);
22471 SDValue EltNo = N->getOperand(1);
22473 if (!isa<ConstantSDNode>(EltNo))
22476 EVT OriginalVT = InVec.getValueType();
22478 if (InVec.getOpcode() == ISD::BITCAST) {
22479 // Don't duplicate a load with other uses.
22480 if (!InVec.hasOneUse())
22482 EVT BCVT = InVec.getOperand(0).getValueType();
22483 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22485 InVec = InVec.getOperand(0);
22488 EVT CurrentVT = InVec.getValueType();
22490 if (!isTargetShuffle(InVec.getOpcode()))
22493 // Don't duplicate a load with other uses.
22494 if (!InVec.hasOneUse())
22497 SmallVector<int, 16> ShuffleMask;
22499 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22500 ShuffleMask, UnaryShuffle))
22503 // Select the input vector, guarding against out of range extract vector.
22504 unsigned NumElems = CurrentVT.getVectorNumElements();
22505 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22506 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22507 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22508 : InVec.getOperand(1);
22510 // If inputs to shuffle are the same for both ops, then allow 2 uses
22511 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22513 if (LdNode.getOpcode() == ISD::BITCAST) {
22514 // Don't duplicate a load with other uses.
22515 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22518 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22519 LdNode = LdNode.getOperand(0);
22522 if (!ISD::isNormalLoad(LdNode.getNode()))
22525 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22527 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22530 EVT EltVT = N->getValueType(0);
22531 // If there's a bitcast before the shuffle, check if the load type and
22532 // alignment is valid.
22533 unsigned Align = LN0->getAlignment();
22534 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22535 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
22536 EltVT.getTypeForEVT(*DAG.getContext()));
22538 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22541 // All checks match so transform back to vector_shuffle so that DAG combiner
22542 // can finish the job
22545 // Create shuffle node taking into account the case that its a unary shuffle
22546 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22547 : InVec.getOperand(1);
22548 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22549 InVec.getOperand(0), Shuffle,
22551 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
22552 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22556 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22557 /// generation and convert it from being a bunch of shuffles and extracts
22558 /// to a simple store and scalar loads to extract the elements.
22559 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22560 TargetLowering::DAGCombinerInfo &DCI) {
22561 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
22562 if (NewOp.getNode())
22565 SDValue InputVector = N->getOperand(0);
22567 // Detect whether we are trying to convert from mmx to i32 and the bitcast
22568 // from mmx to v2i32 has a single usage.
22569 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
22570 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
22571 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
22572 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22573 N->getValueType(0),
22574 InputVector.getNode()->getOperand(0));
22576 // Only operate on vectors of 4 elements, where the alternative shuffling
22577 // gets to be more expensive.
22578 if (InputVector.getValueType() != MVT::v4i32)
22581 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22582 // single use which is a sign-extend or zero-extend, and all elements are
22584 SmallVector<SDNode *, 4> Uses;
22585 unsigned ExtractedElements = 0;
22586 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22587 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22588 if (UI.getUse().getResNo() != InputVector.getResNo())
22591 SDNode *Extract = *UI;
22592 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22595 if (Extract->getValueType(0) != MVT::i32)
22597 if (!Extract->hasOneUse())
22599 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22600 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22602 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22605 // Record which element was extracted.
22606 ExtractedElements |=
22607 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22609 Uses.push_back(Extract);
22612 // If not all the elements were used, this may not be worthwhile.
22613 if (ExtractedElements != 15)
22616 // Ok, we've now decided to do the transformation.
22617 SDLoc dl(InputVector);
22619 // Store the value to a temporary stack slot.
22620 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22621 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22622 MachinePointerInfo(), false, false, 0);
22624 // Replace each use (extract) with a load of the appropriate element.
22625 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22626 UE = Uses.end(); UI != UE; ++UI) {
22627 SDNode *Extract = *UI;
22629 // cOMpute the element's address.
22630 SDValue Idx = Extract->getOperand(1);
22632 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
22633 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
22634 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22635 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
22637 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
22638 StackPtr, OffsetVal);
22640 // Load the scalar.
22641 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
22642 ScalarAddr, MachinePointerInfo(),
22643 false, false, false, 0);
22645 // Replace the exact with the load.
22646 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
22649 // The replacement was made in place; don't return anything.
22653 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
22654 static std::pair<unsigned, bool>
22655 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
22656 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
22657 if (!VT.isVector())
22658 return std::make_pair(0, false);
22660 bool NeedSplit = false;
22661 switch (VT.getSimpleVT().SimpleTy) {
22662 default: return std::make_pair(0, false);
22666 if (!Subtarget->hasAVX2())
22668 if (!Subtarget->hasAVX())
22669 return std::make_pair(0, false);
22674 if (!Subtarget->hasSSE2())
22675 return std::make_pair(0, false);
22678 // SSE2 has only a small subset of the operations.
22679 bool hasUnsigned = Subtarget->hasSSE41() ||
22680 (Subtarget->hasSSE2() && VT == MVT::v16i8);
22681 bool hasSigned = Subtarget->hasSSE41() ||
22682 (Subtarget->hasSSE2() && VT == MVT::v8i16);
22684 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22687 // Check for x CC y ? x : y.
22688 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22689 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22694 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22697 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22700 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22703 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22705 // Check for x CC y ? y : x -- a min/max with reversed arms.
22706 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22707 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22712 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22715 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22718 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22721 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22725 return std::make_pair(Opc, NeedSplit);
22729 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22730 const X86Subtarget *Subtarget) {
22732 SDValue Cond = N->getOperand(0);
22733 SDValue LHS = N->getOperand(1);
22734 SDValue RHS = N->getOperand(2);
22736 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22737 SDValue CondSrc = Cond->getOperand(0);
22738 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22739 Cond = CondSrc->getOperand(0);
22742 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
22745 // A vselect where all conditions and data are constants can be optimized into
22746 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
22747 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
22748 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
22751 unsigned MaskValue = 0;
22752 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22755 MVT VT = N->getSimpleValueType(0);
22756 unsigned NumElems = VT.getVectorNumElements();
22757 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22758 for (unsigned i = 0; i < NumElems; ++i) {
22759 // Be sure we emit undef where we can.
22760 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
22761 ShuffleMask[i] = -1;
22763 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
22766 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22767 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
22769 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
22772 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
22774 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
22775 TargetLowering::DAGCombinerInfo &DCI,
22776 const X86Subtarget *Subtarget) {
22778 SDValue Cond = N->getOperand(0);
22779 // Get the LHS/RHS of the select.
22780 SDValue LHS = N->getOperand(1);
22781 SDValue RHS = N->getOperand(2);
22782 EVT VT = LHS.getValueType();
22783 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22785 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
22786 // instructions match the semantics of the common C idiom x<y?x:y but not
22787 // x<=y?x:y, because of how they handle negative zero (which can be
22788 // ignored in unsafe-math mode).
22789 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
22790 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
22791 (Subtarget->hasSSE2() ||
22792 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
22793 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22795 unsigned Opcode = 0;
22796 // Check for x CC y ? x : y.
22797 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22798 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22802 // Converting this to a min would handle NaNs incorrectly, and swapping
22803 // the operands would cause it to handle comparisons between positive
22804 // and negative zero incorrectly.
22805 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22806 if (!DAG.getTarget().Options.UnsafeFPMath &&
22807 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22809 std::swap(LHS, RHS);
22811 Opcode = X86ISD::FMIN;
22814 // Converting this to a min would handle comparisons between positive
22815 // and negative zero incorrectly.
22816 if (!DAG.getTarget().Options.UnsafeFPMath &&
22817 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22819 Opcode = X86ISD::FMIN;
22822 // Converting this to a min would handle both negative zeros and NaNs
22823 // incorrectly, but we can swap the operands to fix both.
22824 std::swap(LHS, RHS);
22828 Opcode = X86ISD::FMIN;
22832 // Converting this to a max would handle comparisons between positive
22833 // and negative zero incorrectly.
22834 if (!DAG.getTarget().Options.UnsafeFPMath &&
22835 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22837 Opcode = X86ISD::FMAX;
22840 // Converting this to a max would handle NaNs incorrectly, and swapping
22841 // the operands would cause it to handle comparisons between positive
22842 // and negative zero incorrectly.
22843 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22844 if (!DAG.getTarget().Options.UnsafeFPMath &&
22845 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22847 std::swap(LHS, RHS);
22849 Opcode = X86ISD::FMAX;
22852 // Converting this to a max would handle both negative zeros and NaNs
22853 // incorrectly, but we can swap the operands to fix both.
22854 std::swap(LHS, RHS);
22858 Opcode = X86ISD::FMAX;
22861 // Check for x CC y ? y : x -- a min/max with reversed arms.
22862 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22863 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22867 // Converting this to a min would handle comparisons between positive
22868 // and negative zero incorrectly, and swapping the operands would
22869 // cause it to handle NaNs incorrectly.
22870 if (!DAG.getTarget().Options.UnsafeFPMath &&
22871 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
22872 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22874 std::swap(LHS, RHS);
22876 Opcode = X86ISD::FMIN;
22879 // Converting this to a min would handle NaNs incorrectly.
22880 if (!DAG.getTarget().Options.UnsafeFPMath &&
22881 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
22883 Opcode = X86ISD::FMIN;
22886 // Converting this to a min would handle both negative zeros and NaNs
22887 // incorrectly, but we can swap the operands to fix both.
22888 std::swap(LHS, RHS);
22892 Opcode = X86ISD::FMIN;
22896 // Converting this to a max would handle NaNs incorrectly.
22897 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22899 Opcode = X86ISD::FMAX;
22902 // Converting this to a max would handle comparisons between positive
22903 // and negative zero incorrectly, and swapping the operands would
22904 // cause it to handle NaNs incorrectly.
22905 if (!DAG.getTarget().Options.UnsafeFPMath &&
22906 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
22907 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22909 std::swap(LHS, RHS);
22911 Opcode = X86ISD::FMAX;
22914 // Converting this to a max would handle both negative zeros and NaNs
22915 // incorrectly, but we can swap the operands to fix both.
22916 std::swap(LHS, RHS);
22920 Opcode = X86ISD::FMAX;
22926 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
22929 EVT CondVT = Cond.getValueType();
22930 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
22931 CondVT.getVectorElementType() == MVT::i1) {
22932 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
22933 // lowering on KNL. In this case we convert it to
22934 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
22935 // The same situation for all 128 and 256-bit vectors of i8 and i16.
22936 // Since SKX these selects have a proper lowering.
22937 EVT OpVT = LHS.getValueType();
22938 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
22939 (OpVT.getVectorElementType() == MVT::i8 ||
22940 OpVT.getVectorElementType() == MVT::i16) &&
22941 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
22942 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
22943 DCI.AddToWorklist(Cond.getNode());
22944 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
22947 // If this is a select between two integer constants, try to do some
22949 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
22950 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
22951 // Don't do this for crazy integer types.
22952 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
22953 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
22954 // so that TrueC (the true value) is larger than FalseC.
22955 bool NeedsCondInvert = false;
22957 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
22958 // Efficiently invertible.
22959 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
22960 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
22961 isa<ConstantSDNode>(Cond.getOperand(1))))) {
22962 NeedsCondInvert = true;
22963 std::swap(TrueC, FalseC);
22966 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
22967 if (FalseC->getAPIntValue() == 0 &&
22968 TrueC->getAPIntValue().isPowerOf2()) {
22969 if (NeedsCondInvert) // Invert the condition if needed.
22970 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22971 DAG.getConstant(1, Cond.getValueType()));
22973 // Zero extend the condition if needed.
22974 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
22976 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22977 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
22978 DAG.getConstant(ShAmt, MVT::i8));
22981 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
22982 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22983 if (NeedsCondInvert) // Invert the condition if needed.
22984 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22985 DAG.getConstant(1, Cond.getValueType()));
22987 // Zero extend the condition if needed.
22988 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22989 FalseC->getValueType(0), Cond);
22990 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22991 SDValue(FalseC, 0));
22994 // Optimize cases that will turn into an LEA instruction. This requires
22995 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22996 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22997 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22998 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23000 bool isFastMultiplier = false;
23002 switch ((unsigned char)Diff) {
23004 case 1: // result = add base, cond
23005 case 2: // result = lea base( , cond*2)
23006 case 3: // result = lea base(cond, cond*2)
23007 case 4: // result = lea base( , cond*4)
23008 case 5: // result = lea base(cond, cond*4)
23009 case 8: // result = lea base( , cond*8)
23010 case 9: // result = lea base(cond, cond*8)
23011 isFastMultiplier = true;
23016 if (isFastMultiplier) {
23017 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23018 if (NeedsCondInvert) // Invert the condition if needed.
23019 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23020 DAG.getConstant(1, Cond.getValueType()));
23022 // Zero extend the condition if needed.
23023 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23025 // Scale the condition by the difference.
23027 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23028 DAG.getConstant(Diff, Cond.getValueType()));
23030 // Add the base if non-zero.
23031 if (FalseC->getAPIntValue() != 0)
23032 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23033 SDValue(FalseC, 0));
23040 // Canonicalize max and min:
23041 // (x > y) ? x : y -> (x >= y) ? x : y
23042 // (x < y) ? x : y -> (x <= y) ? x : y
23043 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23044 // the need for an extra compare
23045 // against zero. e.g.
23046 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23048 // testl %edi, %edi
23050 // cmovgl %edi, %eax
23054 // cmovsl %eax, %edi
23055 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23056 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23057 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23058 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23063 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23064 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23065 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23066 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23071 // Early exit check
23072 if (!TLI.isTypeLegal(VT))
23075 // Match VSELECTs into subs with unsigned saturation.
23076 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23077 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23078 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23079 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23080 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23082 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23083 // left side invert the predicate to simplify logic below.
23085 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23087 CC = ISD::getSetCCInverse(CC, true);
23088 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23092 if (Other.getNode() && Other->getNumOperands() == 2 &&
23093 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23094 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23095 SDValue CondRHS = Cond->getOperand(1);
23097 // Look for a general sub with unsigned saturation first.
23098 // x >= y ? x-y : 0 --> subus x, y
23099 // x > y ? x-y : 0 --> subus x, y
23100 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23101 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23102 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23104 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23105 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23106 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23107 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23108 // If the RHS is a constant we have to reverse the const
23109 // canonicalization.
23110 // x > C-1 ? x+-C : 0 --> subus x, C
23111 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23112 CondRHSConst->getAPIntValue() ==
23113 (-OpRHSConst->getAPIntValue() - 1))
23114 return DAG.getNode(
23115 X86ISD::SUBUS, DL, VT, OpLHS,
23116 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
23118 // Another special case: If C was a sign bit, the sub has been
23119 // canonicalized into a xor.
23120 // FIXME: Would it be better to use computeKnownBits to determine
23121 // whether it's safe to decanonicalize the xor?
23122 // x s< 0 ? x^C : 0 --> subus x, C
23123 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23124 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23125 OpRHSConst->getAPIntValue().isSignBit())
23126 // Note that we have to rebuild the RHS constant here to ensure we
23127 // don't rely on particular values of undef lanes.
23128 return DAG.getNode(
23129 X86ISD::SUBUS, DL, VT, OpLHS,
23130 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
23135 // Try to match a min/max vector operation.
23136 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
23137 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
23138 unsigned Opc = ret.first;
23139 bool NeedSplit = ret.second;
23141 if (Opc && NeedSplit) {
23142 unsigned NumElems = VT.getVectorNumElements();
23143 // Extract the LHS vectors
23144 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
23145 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
23147 // Extract the RHS vectors
23148 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
23149 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
23151 // Create min/max for each subvector
23152 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
23153 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
23155 // Merge the result
23156 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
23158 return DAG.getNode(Opc, DL, VT, LHS, RHS);
23161 // Simplify vector selection if condition value type matches vselect
23163 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23164 assert(Cond.getValueType().isVector() &&
23165 "vector select expects a vector selector!");
23167 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23168 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23170 // Try invert the condition if true value is not all 1s and false value
23172 if (!TValIsAllOnes && !FValIsAllZeros &&
23173 // Check if the selector will be produced by CMPP*/PCMP*
23174 Cond.getOpcode() == ISD::SETCC &&
23175 // Check if SETCC has already been promoted
23176 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
23177 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23178 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23180 if (TValIsAllZeros || FValIsAllOnes) {
23181 SDValue CC = Cond.getOperand(2);
23182 ISD::CondCode NewCC =
23183 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23184 Cond.getOperand(0).getValueType().isInteger());
23185 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23186 std::swap(LHS, RHS);
23187 TValIsAllOnes = FValIsAllOnes;
23188 FValIsAllZeros = TValIsAllZeros;
23192 if (TValIsAllOnes || FValIsAllZeros) {
23195 if (TValIsAllOnes && FValIsAllZeros)
23197 else if (TValIsAllOnes)
23198 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
23199 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
23200 else if (FValIsAllZeros)
23201 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23202 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
23204 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
23208 // If we know that this node is legal then we know that it is going to be
23209 // matched by one of the SSE/AVX BLEND instructions. These instructions only
23210 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
23211 // to simplify previous instructions.
23212 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23213 !DCI.isBeforeLegalize() &&
23214 // We explicitly check against v8i16 and v16i16 because, although
23215 // they're marked as Custom, they might only be legal when Cond is a
23216 // build_vector of constants. This will be taken care in a later
23218 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
23219 VT != MVT::v8i16) &&
23220 // Don't optimize vector of constants. Those are handled by
23221 // the generic code and all the bits must be properly set for
23222 // the generic optimizer.
23223 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23224 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23226 // Don't optimize vector selects that map to mask-registers.
23230 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23231 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23233 APInt KnownZero, KnownOne;
23234 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23235 DCI.isBeforeLegalizeOps());
23236 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23237 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23239 // If we changed the computation somewhere in the DAG, this change
23240 // will affect all users of Cond.
23241 // Make sure it is fine and update all the nodes so that we do not
23242 // use the generic VSELECT anymore. Otherwise, we may perform
23243 // wrong optimizations as we messed up with the actual expectation
23244 // for the vector boolean values.
23245 if (Cond != TLO.Old) {
23246 // Check all uses of that condition operand to check whether it will be
23247 // consumed by non-BLEND instructions, which may depend on all bits are
23249 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23251 if (I->getOpcode() != ISD::VSELECT)
23252 // TODO: Add other opcodes eventually lowered into BLEND.
23255 // Update all the users of the condition, before committing the change,
23256 // so that the VSELECT optimizations that expect the correct vector
23257 // boolean value will not be triggered.
23258 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23260 DAG.ReplaceAllUsesOfValueWith(
23262 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23263 Cond, I->getOperand(1), I->getOperand(2)));
23264 DCI.CommitTargetLoweringOpt(TLO);
23267 // At this point, only Cond is changed. Change the condition
23268 // just for N to keep the opportunity to optimize all other
23269 // users their own way.
23270 DAG.ReplaceAllUsesOfValueWith(
23272 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23273 TLO.New, N->getOperand(1), N->getOperand(2)));
23278 // We should generate an X86ISD::BLENDI from a vselect if its argument
23279 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23280 // constants. This specific pattern gets generated when we split a
23281 // selector for a 512 bit vector in a machine without AVX512 (but with
23282 // 256-bit vectors), during legalization:
23284 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23286 // Iff we find this pattern and the build_vectors are built from
23287 // constants, we translate the vselect into a shuffle_vector that we
23288 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23289 if ((N->getOpcode() == ISD::VSELECT ||
23290 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23291 !DCI.isBeforeLegalize()) {
23292 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23293 if (Shuffle.getNode())
23300 // Check whether a boolean test is testing a boolean value generated by
23301 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23304 // Simplify the following patterns:
23305 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23306 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23307 // to (Op EFLAGS Cond)
23309 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23310 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23311 // to (Op EFLAGS !Cond)
23313 // where Op could be BRCOND or CMOV.
23315 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23316 // Quit if not CMP and SUB with its value result used.
23317 if (Cmp.getOpcode() != X86ISD::CMP &&
23318 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23321 // Quit if not used as a boolean value.
23322 if (CC != X86::COND_E && CC != X86::COND_NE)
23325 // Check CMP operands. One of them should be 0 or 1 and the other should be
23326 // an SetCC or extended from it.
23327 SDValue Op1 = Cmp.getOperand(0);
23328 SDValue Op2 = Cmp.getOperand(1);
23331 const ConstantSDNode* C = nullptr;
23332 bool needOppositeCond = (CC == X86::COND_E);
23333 bool checkAgainstTrue = false; // Is it a comparison against 1?
23335 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23337 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23339 else // Quit if all operands are not constants.
23342 if (C->getZExtValue() == 1) {
23343 needOppositeCond = !needOppositeCond;
23344 checkAgainstTrue = true;
23345 } else if (C->getZExtValue() != 0)
23346 // Quit if the constant is neither 0 or 1.
23349 bool truncatedToBoolWithAnd = false;
23350 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23351 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23352 SetCC.getOpcode() == ISD::TRUNCATE ||
23353 SetCC.getOpcode() == ISD::AND) {
23354 if (SetCC.getOpcode() == ISD::AND) {
23356 ConstantSDNode *CS;
23357 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23358 CS->getZExtValue() == 1)
23360 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23361 CS->getZExtValue() == 1)
23365 SetCC = SetCC.getOperand(OpIdx);
23366 truncatedToBoolWithAnd = true;
23368 SetCC = SetCC.getOperand(0);
23371 switch (SetCC.getOpcode()) {
23372 case X86ISD::SETCC_CARRY:
23373 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23374 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23375 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23376 // truncated to i1 using 'and'.
23377 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23379 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23380 "Invalid use of SETCC_CARRY!");
23382 case X86ISD::SETCC:
23383 // Set the condition code or opposite one if necessary.
23384 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23385 if (needOppositeCond)
23386 CC = X86::GetOppositeBranchCondition(CC);
23387 return SetCC.getOperand(1);
23388 case X86ISD::CMOV: {
23389 // Check whether false/true value has canonical one, i.e. 0 or 1.
23390 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23391 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23392 // Quit if true value is not a constant.
23395 // Quit if false value is not a constant.
23397 SDValue Op = SetCC.getOperand(0);
23398 // Skip 'zext' or 'trunc' node.
23399 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23400 Op.getOpcode() == ISD::TRUNCATE)
23401 Op = Op.getOperand(0);
23402 // A special case for rdrand/rdseed, where 0 is set if false cond is
23404 if ((Op.getOpcode() != X86ISD::RDRAND &&
23405 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23408 // Quit if false value is not the constant 0 or 1.
23409 bool FValIsFalse = true;
23410 if (FVal && FVal->getZExtValue() != 0) {
23411 if (FVal->getZExtValue() != 1)
23413 // If FVal is 1, opposite cond is needed.
23414 needOppositeCond = !needOppositeCond;
23415 FValIsFalse = false;
23417 // Quit if TVal is not the constant opposite of FVal.
23418 if (FValIsFalse && TVal->getZExtValue() != 1)
23420 if (!FValIsFalse && TVal->getZExtValue() != 0)
23422 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23423 if (needOppositeCond)
23424 CC = X86::GetOppositeBranchCondition(CC);
23425 return SetCC.getOperand(3);
23432 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23433 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23434 TargetLowering::DAGCombinerInfo &DCI,
23435 const X86Subtarget *Subtarget) {
23438 // If the flag operand isn't dead, don't touch this CMOV.
23439 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23442 SDValue FalseOp = N->getOperand(0);
23443 SDValue TrueOp = N->getOperand(1);
23444 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23445 SDValue Cond = N->getOperand(3);
23447 if (CC == X86::COND_E || CC == X86::COND_NE) {
23448 switch (Cond.getOpcode()) {
23452 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23453 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23454 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23460 Flags = checkBoolTestSetCCCombine(Cond, CC);
23461 if (Flags.getNode() &&
23462 // Extra check as FCMOV only supports a subset of X86 cond.
23463 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23464 SDValue Ops[] = { FalseOp, TrueOp,
23465 DAG.getConstant(CC, MVT::i8), Flags };
23466 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23469 // If this is a select between two integer constants, try to do some
23470 // optimizations. Note that the operands are ordered the opposite of SELECT
23472 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23473 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23474 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23475 // larger than FalseC (the false value).
23476 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23477 CC = X86::GetOppositeBranchCondition(CC);
23478 std::swap(TrueC, FalseC);
23479 std::swap(TrueOp, FalseOp);
23482 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23483 // This is efficient for any integer data type (including i8/i16) and
23485 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23486 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23487 DAG.getConstant(CC, MVT::i8), Cond);
23489 // Zero extend the condition if needed.
23490 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23492 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23493 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23494 DAG.getConstant(ShAmt, MVT::i8));
23495 if (N->getNumValues() == 2) // Dead flag value?
23496 return DCI.CombineTo(N, Cond, SDValue());
23500 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23501 // for any integer data type, including i8/i16.
23502 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23503 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23504 DAG.getConstant(CC, MVT::i8), Cond);
23506 // Zero extend the condition if needed.
23507 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23508 FalseC->getValueType(0), Cond);
23509 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23510 SDValue(FalseC, 0));
23512 if (N->getNumValues() == 2) // Dead flag value?
23513 return DCI.CombineTo(N, Cond, SDValue());
23517 // Optimize cases that will turn into an LEA instruction. This requires
23518 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23519 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23520 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23521 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23523 bool isFastMultiplier = false;
23525 switch ((unsigned char)Diff) {
23527 case 1: // result = add base, cond
23528 case 2: // result = lea base( , cond*2)
23529 case 3: // result = lea base(cond, cond*2)
23530 case 4: // result = lea base( , cond*4)
23531 case 5: // result = lea base(cond, cond*4)
23532 case 8: // result = lea base( , cond*8)
23533 case 9: // result = lea base(cond, cond*8)
23534 isFastMultiplier = true;
23539 if (isFastMultiplier) {
23540 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23541 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23542 DAG.getConstant(CC, MVT::i8), Cond);
23543 // Zero extend the condition if needed.
23544 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23546 // Scale the condition by the difference.
23548 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23549 DAG.getConstant(Diff, Cond.getValueType()));
23551 // Add the base if non-zero.
23552 if (FalseC->getAPIntValue() != 0)
23553 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23554 SDValue(FalseC, 0));
23555 if (N->getNumValues() == 2) // Dead flag value?
23556 return DCI.CombineTo(N, Cond, SDValue());
23563 // Handle these cases:
23564 // (select (x != c), e, c) -> select (x != c), e, x),
23565 // (select (x == c), c, e) -> select (x == c), x, e)
23566 // where the c is an integer constant, and the "select" is the combination
23567 // of CMOV and CMP.
23569 // The rationale for this change is that the conditional-move from a constant
23570 // needs two instructions, however, conditional-move from a register needs
23571 // only one instruction.
23573 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23574 // some instruction-combining opportunities. This opt needs to be
23575 // postponed as late as possible.
23577 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23578 // the DCI.xxxx conditions are provided to postpone the optimization as
23579 // late as possible.
23581 ConstantSDNode *CmpAgainst = nullptr;
23582 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23583 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23584 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23586 if (CC == X86::COND_NE &&
23587 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23588 CC = X86::GetOppositeBranchCondition(CC);
23589 std::swap(TrueOp, FalseOp);
23592 if (CC == X86::COND_E &&
23593 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23594 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23595 DAG.getConstant(CC, MVT::i8), Cond };
23596 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23604 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
23605 const X86Subtarget *Subtarget) {
23606 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
23608 default: return SDValue();
23609 // SSE/AVX/AVX2 blend intrinsics.
23610 case Intrinsic::x86_avx2_pblendvb:
23611 case Intrinsic::x86_avx2_pblendw:
23612 case Intrinsic::x86_avx2_pblendd_128:
23613 case Intrinsic::x86_avx2_pblendd_256:
23614 // Don't try to simplify this intrinsic if we don't have AVX2.
23615 if (!Subtarget->hasAVX2())
23618 case Intrinsic::x86_avx_blend_pd_256:
23619 case Intrinsic::x86_avx_blend_ps_256:
23620 case Intrinsic::x86_avx_blendv_pd_256:
23621 case Intrinsic::x86_avx_blendv_ps_256:
23622 // Don't try to simplify this intrinsic if we don't have AVX.
23623 if (!Subtarget->hasAVX())
23626 case Intrinsic::x86_sse41_pblendw:
23627 case Intrinsic::x86_sse41_blendpd:
23628 case Intrinsic::x86_sse41_blendps:
23629 case Intrinsic::x86_sse41_blendvps:
23630 case Intrinsic::x86_sse41_blendvpd:
23631 case Intrinsic::x86_sse41_pblendvb: {
23632 SDValue Op0 = N->getOperand(1);
23633 SDValue Op1 = N->getOperand(2);
23634 SDValue Mask = N->getOperand(3);
23636 // Don't try to simplify this intrinsic if we don't have SSE4.1.
23637 if (!Subtarget->hasSSE41())
23640 // fold (blend A, A, Mask) -> A
23643 // fold (blend A, B, allZeros) -> A
23644 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
23646 // fold (blend A, B, allOnes) -> B
23647 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
23650 // Simplify the case where the mask is a constant i32 value.
23651 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
23652 if (C->isNullValue())
23654 if (C->isAllOnesValue())
23661 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
23662 case Intrinsic::x86_sse2_psrai_w:
23663 case Intrinsic::x86_sse2_psrai_d:
23664 case Intrinsic::x86_avx2_psrai_w:
23665 case Intrinsic::x86_avx2_psrai_d:
23666 case Intrinsic::x86_sse2_psra_w:
23667 case Intrinsic::x86_sse2_psra_d:
23668 case Intrinsic::x86_avx2_psra_w:
23669 case Intrinsic::x86_avx2_psra_d: {
23670 SDValue Op0 = N->getOperand(1);
23671 SDValue Op1 = N->getOperand(2);
23672 EVT VT = Op0.getValueType();
23673 assert(VT.isVector() && "Expected a vector type!");
23675 if (isa<BuildVectorSDNode>(Op1))
23676 Op1 = Op1.getOperand(0);
23678 if (!isa<ConstantSDNode>(Op1))
23681 EVT SVT = VT.getVectorElementType();
23682 unsigned SVTBits = SVT.getSizeInBits();
23684 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
23685 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
23686 uint64_t ShAmt = C.getZExtValue();
23688 // Don't try to convert this shift into a ISD::SRA if the shift
23689 // count is bigger than or equal to the element size.
23690 if (ShAmt >= SVTBits)
23693 // Trivial case: if the shift count is zero, then fold this
23694 // into the first operand.
23698 // Replace this packed shift intrinsic with a target independent
23700 SDValue Splat = DAG.getConstant(C, VT);
23701 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
23706 /// PerformMulCombine - Optimize a single multiply with constant into two
23707 /// in order to implement it with two cheaper instructions, e.g.
23708 /// LEA + SHL, LEA + LEA.
23709 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23710 TargetLowering::DAGCombinerInfo &DCI) {
23711 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23714 EVT VT = N->getValueType(0);
23715 if (VT != MVT::i64)
23718 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23721 uint64_t MulAmt = C->getZExtValue();
23722 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23725 uint64_t MulAmt1 = 0;
23726 uint64_t MulAmt2 = 0;
23727 if ((MulAmt % 9) == 0) {
23729 MulAmt2 = MulAmt / 9;
23730 } else if ((MulAmt % 5) == 0) {
23732 MulAmt2 = MulAmt / 5;
23733 } else if ((MulAmt % 3) == 0) {
23735 MulAmt2 = MulAmt / 3;
23738 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23741 if (isPowerOf2_64(MulAmt2) &&
23742 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23743 // If second multiplifer is pow2, issue it first. We want the multiply by
23744 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23746 std::swap(MulAmt1, MulAmt2);
23749 if (isPowerOf2_64(MulAmt1))
23750 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23751 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
23753 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23754 DAG.getConstant(MulAmt1, VT));
23756 if (isPowerOf2_64(MulAmt2))
23757 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23758 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
23760 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23761 DAG.getConstant(MulAmt2, VT));
23763 // Do not add new nodes to DAG combiner worklist.
23764 DCI.CombineTo(N, NewMul, false);
23769 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23770 SDValue N0 = N->getOperand(0);
23771 SDValue N1 = N->getOperand(1);
23772 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23773 EVT VT = N0.getValueType();
23775 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23776 // since the result of setcc_c is all zero's or all ones.
23777 if (VT.isInteger() && !VT.isVector() &&
23778 N1C && N0.getOpcode() == ISD::AND &&
23779 N0.getOperand(1).getOpcode() == ISD::Constant) {
23780 SDValue N00 = N0.getOperand(0);
23781 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
23782 ((N00.getOpcode() == ISD::ANY_EXTEND ||
23783 N00.getOpcode() == ISD::ZERO_EXTEND) &&
23784 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
23785 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
23786 APInt ShAmt = N1C->getAPIntValue();
23787 Mask = Mask.shl(ShAmt);
23789 return DAG.getNode(ISD::AND, SDLoc(N), VT,
23790 N00, DAG.getConstant(Mask, VT));
23794 // Hardware support for vector shifts is sparse which makes us scalarize the
23795 // vector operations in many cases. Also, on sandybridge ADD is faster than
23797 // (shl V, 1) -> add V,V
23798 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23799 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23800 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23801 // We shift all of the values by one. In many cases we do not have
23802 // hardware support for this operation. This is better expressed as an ADD
23804 if (N1SplatC->getZExtValue() == 1)
23805 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
23811 /// \brief Returns a vector of 0s if the node in input is a vector logical
23812 /// shift by a constant amount which is known to be bigger than or equal
23813 /// to the vector element size in bits.
23814 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
23815 const X86Subtarget *Subtarget) {
23816 EVT VT = N->getValueType(0);
23818 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
23819 (!Subtarget->hasInt256() ||
23820 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
23823 SDValue Amt = N->getOperand(1);
23825 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
23826 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
23827 APInt ShiftAmt = AmtSplat->getAPIntValue();
23828 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
23830 // SSE2/AVX2 logical shifts always return a vector of 0s
23831 // if the shift amount is bigger than or equal to
23832 // the element size. The constant shift amount will be
23833 // encoded as a 8-bit immediate.
23834 if (ShiftAmt.trunc(8).uge(MaxAmount))
23835 return getZeroVector(VT, Subtarget, DAG, DL);
23841 /// PerformShiftCombine - Combine shifts.
23842 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
23843 TargetLowering::DAGCombinerInfo &DCI,
23844 const X86Subtarget *Subtarget) {
23845 if (N->getOpcode() == ISD::SHL) {
23846 SDValue V = PerformSHLCombine(N, DAG);
23847 if (V.getNode()) return V;
23850 if (N->getOpcode() != ISD::SRA) {
23851 // Try to fold this logical shift into a zero vector.
23852 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
23853 if (V.getNode()) return V;
23859 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
23860 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
23861 // and friends. Likewise for OR -> CMPNEQSS.
23862 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
23863 TargetLowering::DAGCombinerInfo &DCI,
23864 const X86Subtarget *Subtarget) {
23867 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
23868 // we're requiring SSE2 for both.
23869 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
23870 SDValue N0 = N->getOperand(0);
23871 SDValue N1 = N->getOperand(1);
23872 SDValue CMP0 = N0->getOperand(1);
23873 SDValue CMP1 = N1->getOperand(1);
23876 // The SETCCs should both refer to the same CMP.
23877 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
23880 SDValue CMP00 = CMP0->getOperand(0);
23881 SDValue CMP01 = CMP0->getOperand(1);
23882 EVT VT = CMP00.getValueType();
23884 if (VT == MVT::f32 || VT == MVT::f64) {
23885 bool ExpectingFlags = false;
23886 // Check for any users that want flags:
23887 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
23888 !ExpectingFlags && UI != UE; ++UI)
23889 switch (UI->getOpcode()) {
23894 ExpectingFlags = true;
23896 case ISD::CopyToReg:
23897 case ISD::SIGN_EXTEND:
23898 case ISD::ZERO_EXTEND:
23899 case ISD::ANY_EXTEND:
23903 if (!ExpectingFlags) {
23904 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
23905 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
23907 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
23908 X86::CondCode tmp = cc0;
23913 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
23914 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
23915 // FIXME: need symbolic constants for these magic numbers.
23916 // See X86ATTInstPrinter.cpp:printSSECC().
23917 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
23918 if (Subtarget->hasAVX512()) {
23919 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
23920 CMP01, DAG.getConstant(x86cc, MVT::i8));
23921 if (N->getValueType(0) != MVT::i1)
23922 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
23926 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
23927 CMP00.getValueType(), CMP00, CMP01,
23928 DAG.getConstant(x86cc, MVT::i8));
23930 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
23931 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
23933 if (is64BitFP && !Subtarget->is64Bit()) {
23934 // On a 32-bit target, we cannot bitcast the 64-bit float to a
23935 // 64-bit integer, since that's not a legal type. Since
23936 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
23937 // bits, but can do this little dance to extract the lowest 32 bits
23938 // and work with those going forward.
23939 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
23941 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
23943 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
23944 Vector32, DAG.getIntPtrConstant(0));
23948 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
23949 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
23950 DAG.getConstant(1, IntVT));
23951 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
23952 return OneBitOfTruth;
23960 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
23961 /// so it can be folded inside ANDNP.
23962 static bool CanFoldXORWithAllOnes(const SDNode *N) {
23963 EVT VT = N->getValueType(0);
23965 // Match direct AllOnes for 128 and 256-bit vectors
23966 if (ISD::isBuildVectorAllOnes(N))
23969 // Look through a bit convert.
23970 if (N->getOpcode() == ISD::BITCAST)
23971 N = N->getOperand(0).getNode();
23973 // Sometimes the operand may come from a insert_subvector building a 256-bit
23975 if (VT.is256BitVector() &&
23976 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
23977 SDValue V1 = N->getOperand(0);
23978 SDValue V2 = N->getOperand(1);
23980 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
23981 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
23982 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
23983 ISD::isBuildVectorAllOnes(V2.getNode()))
23990 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
23991 // register. In most cases we actually compare or select YMM-sized registers
23992 // and mixing the two types creates horrible code. This method optimizes
23993 // some of the transition sequences.
23994 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
23995 TargetLowering::DAGCombinerInfo &DCI,
23996 const X86Subtarget *Subtarget) {
23997 EVT VT = N->getValueType(0);
23998 if (!VT.is256BitVector())
24001 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24002 N->getOpcode() == ISD::ZERO_EXTEND ||
24003 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24005 SDValue Narrow = N->getOperand(0);
24006 EVT NarrowVT = Narrow->getValueType(0);
24007 if (!NarrowVT.is128BitVector())
24010 if (Narrow->getOpcode() != ISD::XOR &&
24011 Narrow->getOpcode() != ISD::AND &&
24012 Narrow->getOpcode() != ISD::OR)
24015 SDValue N0 = Narrow->getOperand(0);
24016 SDValue N1 = Narrow->getOperand(1);
24019 // The Left side has to be a trunc.
24020 if (N0.getOpcode() != ISD::TRUNCATE)
24023 // The type of the truncated inputs.
24024 EVT WideVT = N0->getOperand(0)->getValueType(0);
24028 // The right side has to be a 'trunc' or a constant vector.
24029 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24030 ConstantSDNode *RHSConstSplat = nullptr;
24031 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24032 RHSConstSplat = RHSBV->getConstantSplatNode();
24033 if (!RHSTrunc && !RHSConstSplat)
24036 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24038 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24041 // Set N0 and N1 to hold the inputs to the new wide operation.
24042 N0 = N0->getOperand(0);
24043 if (RHSConstSplat) {
24044 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
24045 SDValue(RHSConstSplat, 0));
24046 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24047 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24048 } else if (RHSTrunc) {
24049 N1 = N1->getOperand(0);
24052 // Generate the wide operation.
24053 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24054 unsigned Opcode = N->getOpcode();
24056 case ISD::ANY_EXTEND:
24058 case ISD::ZERO_EXTEND: {
24059 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24060 APInt Mask = APInt::getAllOnesValue(InBits);
24061 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24062 return DAG.getNode(ISD::AND, DL, VT,
24063 Op, DAG.getConstant(Mask, VT));
24065 case ISD::SIGN_EXTEND:
24066 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24067 Op, DAG.getValueType(NarrowVT));
24069 llvm_unreachable("Unexpected opcode");
24073 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24074 TargetLowering::DAGCombinerInfo &DCI,
24075 const X86Subtarget *Subtarget) {
24076 EVT VT = N->getValueType(0);
24077 if (DCI.isBeforeLegalizeOps())
24080 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24084 // Create BEXTR instructions
24085 // BEXTR is ((X >> imm) & (2**size-1))
24086 if (VT == MVT::i32 || VT == MVT::i64) {
24087 SDValue N0 = N->getOperand(0);
24088 SDValue N1 = N->getOperand(1);
24091 // Check for BEXTR.
24092 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24093 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24094 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24095 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24096 if (MaskNode && ShiftNode) {
24097 uint64_t Mask = MaskNode->getZExtValue();
24098 uint64_t Shift = ShiftNode->getZExtValue();
24099 if (isMask_64(Mask)) {
24100 uint64_t MaskSize = CountPopulation_64(Mask);
24101 if (Shift + MaskSize <= VT.getSizeInBits())
24102 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24103 DAG.getConstant(Shift | (MaskSize << 8), VT));
24111 // Want to form ANDNP nodes:
24112 // 1) In the hopes of then easily combining them with OR and AND nodes
24113 // to form PBLEND/PSIGN.
24114 // 2) To match ANDN packed intrinsics
24115 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24118 SDValue N0 = N->getOperand(0);
24119 SDValue N1 = N->getOperand(1);
24122 // Check LHS for vnot
24123 if (N0.getOpcode() == ISD::XOR &&
24124 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24125 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24126 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24128 // Check RHS for vnot
24129 if (N1.getOpcode() == ISD::XOR &&
24130 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24131 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24132 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24137 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24138 TargetLowering::DAGCombinerInfo &DCI,
24139 const X86Subtarget *Subtarget) {
24140 if (DCI.isBeforeLegalizeOps())
24143 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24147 SDValue N0 = N->getOperand(0);
24148 SDValue N1 = N->getOperand(1);
24149 EVT VT = N->getValueType(0);
24151 // look for psign/blend
24152 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24153 if (!Subtarget->hasSSSE3() ||
24154 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24157 // Canonicalize pandn to RHS
24158 if (N0.getOpcode() == X86ISD::ANDNP)
24160 // or (and (m, y), (pandn m, x))
24161 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24162 SDValue Mask = N1.getOperand(0);
24163 SDValue X = N1.getOperand(1);
24165 if (N0.getOperand(0) == Mask)
24166 Y = N0.getOperand(1);
24167 if (N0.getOperand(1) == Mask)
24168 Y = N0.getOperand(0);
24170 // Check to see if the mask appeared in both the AND and ANDNP and
24174 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24175 // Look through mask bitcast.
24176 if (Mask.getOpcode() == ISD::BITCAST)
24177 Mask = Mask.getOperand(0);
24178 if (X.getOpcode() == ISD::BITCAST)
24179 X = X.getOperand(0);
24180 if (Y.getOpcode() == ISD::BITCAST)
24181 Y = Y.getOperand(0);
24183 EVT MaskVT = Mask.getValueType();
24185 // Validate that the Mask operand is a vector sra node.
24186 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24187 // there is no psrai.b
24188 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24189 unsigned SraAmt = ~0;
24190 if (Mask.getOpcode() == ISD::SRA) {
24191 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24192 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24193 SraAmt = AmtConst->getZExtValue();
24194 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24195 SDValue SraC = Mask.getOperand(1);
24196 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24198 if ((SraAmt + 1) != EltBits)
24203 // Now we know we at least have a plendvb with the mask val. See if
24204 // we can form a psignb/w/d.
24205 // psign = x.type == y.type == mask.type && y = sub(0, x);
24206 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24207 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24208 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24209 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24210 "Unsupported VT for PSIGN");
24211 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24212 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24214 // PBLENDVB only available on SSE 4.1
24215 if (!Subtarget->hasSSE41())
24218 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24220 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
24221 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
24222 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
24223 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24224 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24228 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24231 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24232 MachineFunction &MF = DAG.getMachineFunction();
24233 bool OptForSize = MF.getFunction()->getAttributes().
24234 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
24236 // SHLD/SHRD instructions have lower register pressure, but on some
24237 // platforms they have higher latency than the equivalent
24238 // series of shifts/or that would otherwise be generated.
24239 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24240 // have higher latencies and we are not optimizing for size.
24241 if (!OptForSize && Subtarget->isSHLDSlow())
24244 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24246 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24248 if (!N0.hasOneUse() || !N1.hasOneUse())
24251 SDValue ShAmt0 = N0.getOperand(1);
24252 if (ShAmt0.getValueType() != MVT::i8)
24254 SDValue ShAmt1 = N1.getOperand(1);
24255 if (ShAmt1.getValueType() != MVT::i8)
24257 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24258 ShAmt0 = ShAmt0.getOperand(0);
24259 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24260 ShAmt1 = ShAmt1.getOperand(0);
24263 unsigned Opc = X86ISD::SHLD;
24264 SDValue Op0 = N0.getOperand(0);
24265 SDValue Op1 = N1.getOperand(0);
24266 if (ShAmt0.getOpcode() == ISD::SUB) {
24267 Opc = X86ISD::SHRD;
24268 std::swap(Op0, Op1);
24269 std::swap(ShAmt0, ShAmt1);
24272 unsigned Bits = VT.getSizeInBits();
24273 if (ShAmt1.getOpcode() == ISD::SUB) {
24274 SDValue Sum = ShAmt1.getOperand(0);
24275 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24276 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24277 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24278 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24279 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24280 return DAG.getNode(Opc, DL, VT,
24282 DAG.getNode(ISD::TRUNCATE, DL,
24285 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24286 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24288 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24289 return DAG.getNode(Opc, DL, VT,
24290 N0.getOperand(0), N1.getOperand(0),
24291 DAG.getNode(ISD::TRUNCATE, DL,
24298 // Generate NEG and CMOV for integer abs.
24299 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24300 EVT VT = N->getValueType(0);
24302 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24303 // 8-bit integer abs to NEG and CMOV.
24304 if (VT.isInteger() && VT.getSizeInBits() == 8)
24307 SDValue N0 = N->getOperand(0);
24308 SDValue N1 = N->getOperand(1);
24311 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24312 // and change it to SUB and CMOV.
24313 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24314 N0.getOpcode() == ISD::ADD &&
24315 N0.getOperand(1) == N1 &&
24316 N1.getOpcode() == ISD::SRA &&
24317 N1.getOperand(0) == N0.getOperand(0))
24318 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24319 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24320 // Generate SUB & CMOV.
24321 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24322 DAG.getConstant(0, VT), N0.getOperand(0));
24324 SDValue Ops[] = { N0.getOperand(0), Neg,
24325 DAG.getConstant(X86::COND_GE, MVT::i8),
24326 SDValue(Neg.getNode(), 1) };
24327 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24332 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
24333 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24334 TargetLowering::DAGCombinerInfo &DCI,
24335 const X86Subtarget *Subtarget) {
24336 if (DCI.isBeforeLegalizeOps())
24339 if (Subtarget->hasCMov()) {
24340 SDValue RV = performIntegerAbsCombine(N, DAG);
24348 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24349 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24350 TargetLowering::DAGCombinerInfo &DCI,
24351 const X86Subtarget *Subtarget) {
24352 LoadSDNode *Ld = cast<LoadSDNode>(N);
24353 EVT RegVT = Ld->getValueType(0);
24354 EVT MemVT = Ld->getMemoryVT();
24356 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24358 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
24359 // into two 16-byte operations.
24360 ISD::LoadExtType Ext = Ld->getExtensionType();
24361 unsigned Alignment = Ld->getAlignment();
24362 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
24363 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24364 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
24365 unsigned NumElems = RegVT.getVectorNumElements();
24369 SDValue Ptr = Ld->getBasePtr();
24370 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
24372 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24374 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24375 Ld->getPointerInfo(), Ld->isVolatile(),
24376 Ld->isNonTemporal(), Ld->isInvariant(),
24378 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24379 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24380 Ld->getPointerInfo(), Ld->isVolatile(),
24381 Ld->isNonTemporal(), Ld->isInvariant(),
24382 std::min(16U, Alignment));
24383 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24385 Load2.getValue(1));
24387 SDValue NewVec = DAG.getUNDEF(RegVT);
24388 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24389 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24390 return DCI.CombineTo(N, NewVec, TF, true);
24396 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
24397 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
24398 const X86Subtarget *Subtarget) {
24399 StoreSDNode *St = cast<StoreSDNode>(N);
24400 EVT VT = St->getValue().getValueType();
24401 EVT StVT = St->getMemoryVT();
24403 SDValue StoredVal = St->getOperand(1);
24404 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24406 // If we are saving a concatenation of two XMM registers and 32-byte stores
24407 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
24408 unsigned Alignment = St->getAlignment();
24409 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
24410 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24411 StVT == VT && !IsAligned) {
24412 unsigned NumElems = VT.getVectorNumElements();
24416 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24417 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24419 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
24420 SDValue Ptr0 = St->getBasePtr();
24421 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
24423 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
24424 St->getPointerInfo(), St->isVolatile(),
24425 St->isNonTemporal(), Alignment);
24426 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
24427 St->getPointerInfo(), St->isVolatile(),
24428 St->isNonTemporal(),
24429 std::min(16U, Alignment));
24430 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
24433 // Optimize trunc store (of multiple scalars) to shuffle and store.
24434 // First, pack all of the elements in one place. Next, store to memory
24435 // in fewer chunks.
24436 if (St->isTruncatingStore() && VT.isVector()) {
24437 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24438 unsigned NumElems = VT.getVectorNumElements();
24439 assert(StVT != VT && "Cannot truncate to the same type");
24440 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24441 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24443 // From, To sizes and ElemCount must be pow of two
24444 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24445 // We are going to use the original vector elt for storing.
24446 // Accumulated smaller vector elements must be a multiple of the store size.
24447 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24449 unsigned SizeRatio = FromSz / ToSz;
24451 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24453 // Create a type on which we perform the shuffle
24454 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24455 StVT.getScalarType(), NumElems*SizeRatio);
24457 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24459 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
24460 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24461 for (unsigned i = 0; i != NumElems; ++i)
24462 ShuffleVec[i] = i * SizeRatio;
24464 // Can't shuffle using an illegal type.
24465 if (!TLI.isTypeLegal(WideVecVT))
24468 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24469 DAG.getUNDEF(WideVecVT),
24471 // At this point all of the data is stored at the bottom of the
24472 // register. We now need to save it to mem.
24474 // Find the largest store unit
24475 MVT StoreType = MVT::i8;
24476 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
24477 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
24478 MVT Tp = (MVT::SimpleValueType)tp;
24479 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24483 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24484 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24485 (64 <= NumElems * ToSz))
24486 StoreType = MVT::f64;
24488 // Bitcast the original vector into a vector of store-size units
24489 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24490 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24491 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24492 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
24493 SmallVector<SDValue, 8> Chains;
24494 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
24495 TLI.getPointerTy());
24496 SDValue Ptr = St->getBasePtr();
24498 // Perform one or more big stores into memory.
24499 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24500 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24501 StoreType, ShuffWide,
24502 DAG.getIntPtrConstant(i));
24503 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24504 St->getPointerInfo(), St->isVolatile(),
24505 St->isNonTemporal(), St->getAlignment());
24506 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24507 Chains.push_back(Ch);
24510 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24513 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24514 // the FP state in cases where an emms may be missing.
24515 // A preferable solution to the general problem is to figure out the right
24516 // places to insert EMMS. This qualifies as a quick hack.
24518 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24519 if (VT.getSizeInBits() != 64)
24522 const Function *F = DAG.getMachineFunction().getFunction();
24523 bool NoImplicitFloatOps = F->getAttributes().
24524 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
24525 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
24526 && Subtarget->hasSSE2();
24527 if ((VT.isVector() ||
24528 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24529 isa<LoadSDNode>(St->getValue()) &&
24530 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24531 St->getChain().hasOneUse() && !St->isVolatile()) {
24532 SDNode* LdVal = St->getValue().getNode();
24533 LoadSDNode *Ld = nullptr;
24534 int TokenFactorIndex = -1;
24535 SmallVector<SDValue, 8> Ops;
24536 SDNode* ChainVal = St->getChain().getNode();
24537 // Must be a store of a load. We currently handle two cases: the load
24538 // is a direct child, and it's under an intervening TokenFactor. It is
24539 // possible to dig deeper under nested TokenFactors.
24540 if (ChainVal == LdVal)
24541 Ld = cast<LoadSDNode>(St->getChain());
24542 else if (St->getValue().hasOneUse() &&
24543 ChainVal->getOpcode() == ISD::TokenFactor) {
24544 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24545 if (ChainVal->getOperand(i).getNode() == LdVal) {
24546 TokenFactorIndex = i;
24547 Ld = cast<LoadSDNode>(St->getValue());
24549 Ops.push_back(ChainVal->getOperand(i));
24553 if (!Ld || !ISD::isNormalLoad(Ld))
24556 // If this is not the MMX case, i.e. we are just turning i64 load/store
24557 // into f64 load/store, avoid the transformation if there are multiple
24558 // uses of the loaded value.
24559 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24564 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24565 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24567 if (Subtarget->is64Bit() || F64IsLegal) {
24568 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24569 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24570 Ld->getPointerInfo(), Ld->isVolatile(),
24571 Ld->isNonTemporal(), Ld->isInvariant(),
24572 Ld->getAlignment());
24573 SDValue NewChain = NewLd.getValue(1);
24574 if (TokenFactorIndex != -1) {
24575 Ops.push_back(NewChain);
24576 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24578 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24579 St->getPointerInfo(),
24580 St->isVolatile(), St->isNonTemporal(),
24581 St->getAlignment());
24584 // Otherwise, lower to two pairs of 32-bit loads / stores.
24585 SDValue LoAddr = Ld->getBasePtr();
24586 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24587 DAG.getConstant(4, MVT::i32));
24589 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24590 Ld->getPointerInfo(),
24591 Ld->isVolatile(), Ld->isNonTemporal(),
24592 Ld->isInvariant(), Ld->getAlignment());
24593 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24594 Ld->getPointerInfo().getWithOffset(4),
24595 Ld->isVolatile(), Ld->isNonTemporal(),
24597 MinAlign(Ld->getAlignment(), 4));
24599 SDValue NewChain = LoLd.getValue(1);
24600 if (TokenFactorIndex != -1) {
24601 Ops.push_back(LoLd);
24602 Ops.push_back(HiLd);
24603 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24606 LoAddr = St->getBasePtr();
24607 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24608 DAG.getConstant(4, MVT::i32));
24610 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24611 St->getPointerInfo(),
24612 St->isVolatile(), St->isNonTemporal(),
24613 St->getAlignment());
24614 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24615 St->getPointerInfo().getWithOffset(4),
24617 St->isNonTemporal(),
24618 MinAlign(St->getAlignment(), 4));
24619 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24624 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
24625 /// and return the operands for the horizontal operation in LHS and RHS. A
24626 /// horizontal operation performs the binary operation on successive elements
24627 /// of its first operand, then on successive elements of its second operand,
24628 /// returning the resulting values in a vector. For example, if
24629 /// A = < float a0, float a1, float a2, float a3 >
24631 /// B = < float b0, float b1, float b2, float b3 >
24632 /// then the result of doing a horizontal operation on A and B is
24633 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
24634 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
24635 /// A horizontal-op B, for some already available A and B, and if so then LHS is
24636 /// set to A, RHS to B, and the routine returns 'true'.
24637 /// Note that the binary operation should have the property that if one of the
24638 /// operands is UNDEF then the result is UNDEF.
24639 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
24640 // Look for the following pattern: if
24641 // A = < float a0, float a1, float a2, float a3 >
24642 // B = < float b0, float b1, float b2, float b3 >
24644 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
24645 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
24646 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
24647 // which is A horizontal-op B.
24649 // At least one of the operands should be a vector shuffle.
24650 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
24651 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
24654 MVT VT = LHS.getSimpleValueType();
24656 assert((VT.is128BitVector() || VT.is256BitVector()) &&
24657 "Unsupported vector type for horizontal add/sub");
24659 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
24660 // operate independently on 128-bit lanes.
24661 unsigned NumElts = VT.getVectorNumElements();
24662 unsigned NumLanes = VT.getSizeInBits()/128;
24663 unsigned NumLaneElts = NumElts / NumLanes;
24664 assert((NumLaneElts % 2 == 0) &&
24665 "Vector type should have an even number of elements in each lane");
24666 unsigned HalfLaneElts = NumLaneElts/2;
24668 // View LHS in the form
24669 // LHS = VECTOR_SHUFFLE A, B, LMask
24670 // If LHS is not a shuffle then pretend it is the shuffle
24671 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24672 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24675 SmallVector<int, 16> LMask(NumElts);
24676 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24677 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24678 A = LHS.getOperand(0);
24679 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24680 B = LHS.getOperand(1);
24681 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24682 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24684 if (LHS.getOpcode() != ISD::UNDEF)
24686 for (unsigned i = 0; i != NumElts; ++i)
24690 // Likewise, view RHS in the form
24691 // RHS = VECTOR_SHUFFLE C, D, RMask
24693 SmallVector<int, 16> RMask(NumElts);
24694 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24695 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24696 C = RHS.getOperand(0);
24697 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24698 D = RHS.getOperand(1);
24699 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24700 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24702 if (RHS.getOpcode() != ISD::UNDEF)
24704 for (unsigned i = 0; i != NumElts; ++i)
24708 // Check that the shuffles are both shuffling the same vectors.
24709 if (!(A == C && B == D) && !(A == D && B == C))
24712 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24713 if (!A.getNode() && !B.getNode())
24716 // If A and B occur in reverse order in RHS, then "swap" them (which means
24717 // rewriting the mask).
24719 CommuteVectorShuffleMask(RMask, NumElts);
24721 // At this point LHS and RHS are equivalent to
24722 // LHS = VECTOR_SHUFFLE A, B, LMask
24723 // RHS = VECTOR_SHUFFLE A, B, RMask
24724 // Check that the masks correspond to performing a horizontal operation.
24725 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24726 for (unsigned i = 0; i != NumLaneElts; ++i) {
24727 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24729 // Ignore any UNDEF components.
24730 if (LIdx < 0 || RIdx < 0 ||
24731 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24732 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24735 // Check that successive elements are being operated on. If not, this is
24736 // not a horizontal operation.
24737 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24738 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24739 if (!(LIdx == Index && RIdx == Index + 1) &&
24740 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24745 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24746 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24750 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
24751 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24752 const X86Subtarget *Subtarget) {
24753 EVT VT = N->getValueType(0);
24754 SDValue LHS = N->getOperand(0);
24755 SDValue RHS = N->getOperand(1);
24757 // Try to synthesize horizontal adds from adds of shuffles.
24758 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24759 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24760 isHorizontalBinOp(LHS, RHS, true))
24761 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24765 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
24766 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24767 const X86Subtarget *Subtarget) {
24768 EVT VT = N->getValueType(0);
24769 SDValue LHS = N->getOperand(0);
24770 SDValue RHS = N->getOperand(1);
24772 // Try to synthesize horizontal subs from subs of shuffles.
24773 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24774 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24775 isHorizontalBinOp(LHS, RHS, false))
24776 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24780 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
24781 /// X86ISD::FXOR nodes.
24782 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24783 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24784 // F[X]OR(0.0, x) -> x
24785 // F[X]OR(x, 0.0) -> x
24786 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24787 if (C->getValueAPF().isPosZero())
24788 return N->getOperand(1);
24789 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24790 if (C->getValueAPF().isPosZero())
24791 return N->getOperand(0);
24795 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
24796 /// X86ISD::FMAX nodes.
24797 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24798 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24800 // Only perform optimizations if UnsafeMath is used.
24801 if (!DAG.getTarget().Options.UnsafeFPMath)
24804 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24805 // into FMINC and FMAXC, which are Commutative operations.
24806 unsigned NewOp = 0;
24807 switch (N->getOpcode()) {
24808 default: llvm_unreachable("unknown opcode");
24809 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24810 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
24813 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
24814 N->getOperand(0), N->getOperand(1));
24817 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
24818 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
24819 // FAND(0.0, x) -> 0.0
24820 // FAND(x, 0.0) -> 0.0
24821 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24822 if (C->getValueAPF().isPosZero())
24823 return N->getOperand(0);
24824 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24825 if (C->getValueAPF().isPosZero())
24826 return N->getOperand(1);
24830 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
24831 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
24832 // FANDN(x, 0.0) -> 0.0
24833 // FANDN(0.0, x) -> x
24834 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24835 if (C->getValueAPF().isPosZero())
24836 return N->getOperand(1);
24837 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24838 if (C->getValueAPF().isPosZero())
24839 return N->getOperand(1);
24843 static SDValue PerformBTCombine(SDNode *N,
24845 TargetLowering::DAGCombinerInfo &DCI) {
24846 // BT ignores high bits in the bit index operand.
24847 SDValue Op1 = N->getOperand(1);
24848 if (Op1.hasOneUse()) {
24849 unsigned BitWidth = Op1.getValueSizeInBits();
24850 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
24851 APInt KnownZero, KnownOne;
24852 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
24853 !DCI.isBeforeLegalizeOps());
24854 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24855 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
24856 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
24857 DCI.CommitTargetLoweringOpt(TLO);
24862 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
24863 SDValue Op = N->getOperand(0);
24864 if (Op.getOpcode() == ISD::BITCAST)
24865 Op = Op.getOperand(0);
24866 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
24867 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
24868 VT.getVectorElementType().getSizeInBits() ==
24869 OpVT.getVectorElementType().getSizeInBits()) {
24870 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
24875 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
24876 const X86Subtarget *Subtarget) {
24877 EVT VT = N->getValueType(0);
24878 if (!VT.isVector())
24881 SDValue N0 = N->getOperand(0);
24882 SDValue N1 = N->getOperand(1);
24883 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
24886 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
24887 // both SSE and AVX2 since there is no sign-extended shift right
24888 // operation on a vector with 64-bit elements.
24889 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
24890 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
24891 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
24892 N0.getOpcode() == ISD::SIGN_EXTEND)) {
24893 SDValue N00 = N0.getOperand(0);
24895 // EXTLOAD has a better solution on AVX2,
24896 // it may be replaced with X86ISD::VSEXT node.
24897 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
24898 if (!ISD::isNormalLoad(N00.getNode()))
24901 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
24902 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
24904 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24910 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24911 TargetLowering::DAGCombinerInfo &DCI,
24912 const X86Subtarget *Subtarget) {
24913 SDValue N0 = N->getOperand(0);
24914 EVT VT = N->getValueType(0);
24916 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
24917 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
24918 // This exposes the sext to the sdivrem lowering, so that it directly extends
24919 // from AH (which we otherwise need to do contortions to access).
24920 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
24921 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
24923 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24924 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
24925 N0.getOperand(0), N0.getOperand(1));
24926 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24927 return R.getValue(1);
24930 if (!DCI.isBeforeLegalizeOps())
24933 if (!Subtarget->hasFp256())
24936 if (VT.isVector() && VT.getSizeInBits() == 256) {
24937 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24945 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24946 const X86Subtarget* Subtarget) {
24948 EVT VT = N->getValueType(0);
24950 // Let legalize expand this if it isn't a legal type yet.
24951 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
24954 EVT ScalarVT = VT.getScalarType();
24955 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
24956 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
24959 SDValue A = N->getOperand(0);
24960 SDValue B = N->getOperand(1);
24961 SDValue C = N->getOperand(2);
24963 bool NegA = (A.getOpcode() == ISD::FNEG);
24964 bool NegB = (B.getOpcode() == ISD::FNEG);
24965 bool NegC = (C.getOpcode() == ISD::FNEG);
24967 // Negative multiplication when NegA xor NegB
24968 bool NegMul = (NegA != NegB);
24970 A = A.getOperand(0);
24972 B = B.getOperand(0);
24974 C = C.getOperand(0);
24978 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
24980 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
24982 return DAG.getNode(Opcode, dl, VT, A, B, C);
24985 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
24986 TargetLowering::DAGCombinerInfo &DCI,
24987 const X86Subtarget *Subtarget) {
24988 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
24989 // (and (i32 x86isd::setcc_carry), 1)
24990 // This eliminates the zext. This transformation is necessary because
24991 // ISD::SETCC is always legalized to i8.
24993 SDValue N0 = N->getOperand(0);
24994 EVT VT = N->getValueType(0);
24996 if (N0.getOpcode() == ISD::AND &&
24998 N0.getOperand(0).hasOneUse()) {
24999 SDValue N00 = N0.getOperand(0);
25000 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25001 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25002 if (!C || C->getZExtValue() != 1)
25004 return DAG.getNode(ISD::AND, dl, VT,
25005 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25006 N00.getOperand(0), N00.getOperand(1)),
25007 DAG.getConstant(1, VT));
25011 if (N0.getOpcode() == ISD::TRUNCATE &&
25013 N0.getOperand(0).hasOneUse()) {
25014 SDValue N00 = N0.getOperand(0);
25015 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25016 return DAG.getNode(ISD::AND, dl, VT,
25017 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
25018 N00.getOperand(0), N00.getOperand(1)),
25019 DAG.getConstant(1, VT));
25022 if (VT.is256BitVector()) {
25023 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
25028 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
25029 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
25030 // This exposes the zext to the udivrem lowering, so that it directly extends
25031 // from AH (which we otherwise need to do contortions to access).
25032 if (N0.getOpcode() == ISD::UDIVREM &&
25033 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
25034 (VT == MVT::i32 || VT == MVT::i64)) {
25035 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25036 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
25037 N0.getOperand(0), N0.getOperand(1));
25038 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25039 return R.getValue(1);
25045 // Optimize x == -y --> x+y == 0
25046 // x != -y --> x+y != 0
25047 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
25048 const X86Subtarget* Subtarget) {
25049 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
25050 SDValue LHS = N->getOperand(0);
25051 SDValue RHS = N->getOperand(1);
25052 EVT VT = N->getValueType(0);
25055 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
25056 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
25057 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
25058 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25059 LHS.getValueType(), RHS, LHS.getOperand(1));
25060 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25061 addV, DAG.getConstant(0, addV.getValueType()), CC);
25063 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
25064 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
25065 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
25066 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25067 RHS.getValueType(), LHS, RHS.getOperand(1));
25068 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25069 addV, DAG.getConstant(0, addV.getValueType()), CC);
25072 if (VT.getScalarType() == MVT::i1) {
25073 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25074 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25075 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
25076 if (!IsSEXT0 && !IsVZero0)
25078 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
25079 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25080 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25082 if (!IsSEXT1 && !IsVZero1)
25085 if (IsSEXT0 && IsVZero1) {
25086 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
25087 if (CC == ISD::SETEQ)
25088 return DAG.getNOT(DL, LHS.getOperand(0), VT);
25089 return LHS.getOperand(0);
25091 if (IsSEXT1 && IsVZero0) {
25092 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
25093 if (CC == ISD::SETEQ)
25094 return DAG.getNOT(DL, RHS.getOperand(0), VT);
25095 return RHS.getOperand(0);
25102 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
25103 const X86Subtarget *Subtarget) {
25105 MVT VT = N->getOperand(1)->getSimpleValueType(0);
25106 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
25107 "X86insertps is only defined for v4x32");
25109 SDValue Ld = N->getOperand(1);
25110 if (MayFoldLoad(Ld)) {
25111 // Extract the countS bits from the immediate so we can get the proper
25112 // address when narrowing the vector load to a specific element.
25113 // When the second source op is a memory address, interps doesn't use
25114 // countS and just gets an f32 from that address.
25115 unsigned DestIndex =
25116 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
25117 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
25121 // Create this as a scalar to vector to match the instruction pattern.
25122 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
25123 // countS bits are ignored when loading from memory on insertps, which
25124 // means we don't need to explicitly set them to 0.
25125 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
25126 LoadScalarToVector, N->getOperand(2));
25129 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
25130 // as "sbb reg,reg", since it can be extended without zext and produces
25131 // an all-ones bit which is more useful than 0/1 in some cases.
25132 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
25135 return DAG.getNode(ISD::AND, DL, VT,
25136 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25137 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
25138 DAG.getConstant(1, VT));
25139 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
25140 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
25141 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25142 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
25145 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
25146 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
25147 TargetLowering::DAGCombinerInfo &DCI,
25148 const X86Subtarget *Subtarget) {
25150 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
25151 SDValue EFLAGS = N->getOperand(1);
25153 if (CC == X86::COND_A) {
25154 // Try to convert COND_A into COND_B in an attempt to facilitate
25155 // materializing "setb reg".
25157 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
25158 // cannot take an immediate as its first operand.
25160 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
25161 EFLAGS.getValueType().isInteger() &&
25162 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
25163 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
25164 EFLAGS.getNode()->getVTList(),
25165 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
25166 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
25167 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
25171 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
25172 // a zext and produces an all-ones bit which is more useful than 0/1 in some
25174 if (CC == X86::COND_B)
25175 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
25179 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25180 if (Flags.getNode()) {
25181 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25182 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
25188 // Optimize branch condition evaluation.
25190 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
25191 TargetLowering::DAGCombinerInfo &DCI,
25192 const X86Subtarget *Subtarget) {
25194 SDValue Chain = N->getOperand(0);
25195 SDValue Dest = N->getOperand(1);
25196 SDValue EFLAGS = N->getOperand(3);
25197 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
25201 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25202 if (Flags.getNode()) {
25203 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25204 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
25211 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
25212 SelectionDAG &DAG) {
25213 // Take advantage of vector comparisons producing 0 or -1 in each lane to
25214 // optimize away operation when it's from a constant.
25216 // The general transformation is:
25217 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
25218 // AND(VECTOR_CMP(x,y), constant2)
25219 // constant2 = UNARYOP(constant)
25221 // Early exit if this isn't a vector operation, the operand of the
25222 // unary operation isn't a bitwise AND, or if the sizes of the operations
25223 // aren't the same.
25224 EVT VT = N->getValueType(0);
25225 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
25226 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
25227 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
25230 // Now check that the other operand of the AND is a constant. We could
25231 // make the transformation for non-constant splats as well, but it's unclear
25232 // that would be a benefit as it would not eliminate any operations, just
25233 // perform one more step in scalar code before moving to the vector unit.
25234 if (BuildVectorSDNode *BV =
25235 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
25236 // Bail out if the vector isn't a constant.
25237 if (!BV->isConstant())
25240 // Everything checks out. Build up the new and improved node.
25242 EVT IntVT = BV->getValueType(0);
25243 // Create a new constant of the appropriate type for the transformed
25245 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
25246 // The AND node needs bitcasts to/from an integer vector type around it.
25247 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
25248 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
25249 N->getOperand(0)->getOperand(0), MaskConst);
25250 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
25257 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25258 const X86TargetLowering *XTLI) {
25259 // First try to optimize away the conversion entirely when it's
25260 // conditionally from a constant. Vectors only.
25261 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
25262 if (Res != SDValue())
25265 // Now move on to more general possibilities.
25266 SDValue Op0 = N->getOperand(0);
25267 EVT InVT = Op0->getValueType(0);
25269 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
25270 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
25272 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
25273 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
25274 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
25277 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
25278 // a 32-bit target where SSE doesn't support i64->FP operations.
25279 if (Op0.getOpcode() == ISD::LOAD) {
25280 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
25281 EVT VT = Ld->getValueType(0);
25282 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
25283 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
25284 !XTLI->getSubtarget()->is64Bit() &&
25286 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
25287 Ld->getChain(), Op0, DAG);
25288 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
25295 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
25296 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
25297 X86TargetLowering::DAGCombinerInfo &DCI) {
25298 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
25299 // the result is either zero or one (depending on the input carry bit).
25300 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
25301 if (X86::isZeroNode(N->getOperand(0)) &&
25302 X86::isZeroNode(N->getOperand(1)) &&
25303 // We don't have a good way to replace an EFLAGS use, so only do this when
25305 SDValue(N, 1).use_empty()) {
25307 EVT VT = N->getValueType(0);
25308 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
25309 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
25310 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
25311 DAG.getConstant(X86::COND_B,MVT::i8),
25313 DAG.getConstant(1, VT));
25314 return DCI.CombineTo(N, Res1, CarryOut);
25320 // fold (add Y, (sete X, 0)) -> adc 0, Y
25321 // (add Y, (setne X, 0)) -> sbb -1, Y
25322 // (sub (sete X, 0), Y) -> sbb 0, Y
25323 // (sub (setne X, 0), Y) -> adc -1, Y
25324 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
25327 // Look through ZExts.
25328 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
25329 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25332 SDValue SetCC = Ext.getOperand(0);
25333 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25336 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25337 if (CC != X86::COND_E && CC != X86::COND_NE)
25340 SDValue Cmp = SetCC.getOperand(1);
25341 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25342 !X86::isZeroNode(Cmp.getOperand(1)) ||
25343 !Cmp.getOperand(0).getValueType().isInteger())
25346 SDValue CmpOp0 = Cmp.getOperand(0);
25347 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25348 DAG.getConstant(1, CmpOp0.getValueType()));
25350 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25351 if (CC == X86::COND_NE)
25352 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25353 DL, OtherVal.getValueType(), OtherVal,
25354 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
25355 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25356 DL, OtherVal.getValueType(), OtherVal,
25357 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
25360 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25361 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25362 const X86Subtarget *Subtarget) {
25363 EVT VT = N->getValueType(0);
25364 SDValue Op0 = N->getOperand(0);
25365 SDValue Op1 = N->getOperand(1);
25367 // Try to synthesize horizontal adds from adds of shuffles.
25368 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25369 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25370 isHorizontalBinOp(Op0, Op1, true))
25371 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25373 return OptimizeConditionalInDecrement(N, DAG);
25376 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25377 const X86Subtarget *Subtarget) {
25378 SDValue Op0 = N->getOperand(0);
25379 SDValue Op1 = N->getOperand(1);
25381 // X86 can't encode an immediate LHS of a sub. See if we can push the
25382 // negation into a preceding instruction.
25383 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25384 // If the RHS of the sub is a XOR with one use and a constant, invert the
25385 // immediate. Then add one to the LHS of the sub so we can turn
25386 // X-Y -> X+~Y+1, saving one register.
25387 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25388 isa<ConstantSDNode>(Op1.getOperand(1))) {
25389 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25390 EVT VT = Op0.getValueType();
25391 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25393 DAG.getConstant(~XorC, VT));
25394 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25395 DAG.getConstant(C->getAPIntValue()+1, VT));
25399 // Try to synthesize horizontal adds from adds of shuffles.
25400 EVT VT = N->getValueType(0);
25401 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25402 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25403 isHorizontalBinOp(Op0, Op1, true))
25404 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25406 return OptimizeConditionalInDecrement(N, DAG);
25409 /// performVZEXTCombine - Performs build vector combines
25410 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25411 TargetLowering::DAGCombinerInfo &DCI,
25412 const X86Subtarget *Subtarget) {
25414 MVT VT = N->getSimpleValueType(0);
25415 SDValue Op = N->getOperand(0);
25416 MVT OpVT = Op.getSimpleValueType();
25417 MVT OpEltVT = OpVT.getVectorElementType();
25418 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25420 // (vzext (bitcast (vzext (x)) -> (vzext x)
25422 while (V.getOpcode() == ISD::BITCAST)
25423 V = V.getOperand(0);
25425 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25426 MVT InnerVT = V.getSimpleValueType();
25427 MVT InnerEltVT = InnerVT.getVectorElementType();
25429 // If the element sizes match exactly, we can just do one larger vzext. This
25430 // is always an exact type match as vzext operates on integer types.
25431 if (OpEltVT == InnerEltVT) {
25432 assert(OpVT == InnerVT && "Types must match for vzext!");
25433 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25436 // The only other way we can combine them is if only a single element of the
25437 // inner vzext is used in the input to the outer vzext.
25438 if (InnerEltVT.getSizeInBits() < InputBits)
25441 // In this case, the inner vzext is completely dead because we're going to
25442 // only look at bits inside of the low element. Just do the outer vzext on
25443 // a bitcast of the input to the inner.
25444 return DAG.getNode(X86ISD::VZEXT, DL, VT,
25445 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
25448 // Check if we can bypass extracting and re-inserting an element of an input
25449 // vector. Essentialy:
25450 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25451 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25452 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25453 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25454 SDValue ExtractedV = V.getOperand(0);
25455 SDValue OrigV = ExtractedV.getOperand(0);
25456 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25457 if (ExtractIdx->getZExtValue() == 0) {
25458 MVT OrigVT = OrigV.getSimpleValueType();
25459 // Extract a subvector if necessary...
25460 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25461 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25462 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25463 OrigVT.getVectorNumElements() / Ratio);
25464 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25465 DAG.getIntPtrConstant(0));
25467 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
25468 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25475 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25476 DAGCombinerInfo &DCI) const {
25477 SelectionDAG &DAG = DCI.DAG;
25478 switch (N->getOpcode()) {
25480 case ISD::EXTRACT_VECTOR_ELT:
25481 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
25484 case X86ISD::SHRUNKBLEND:
25485 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
25486 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
25487 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
25488 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
25489 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
25490 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
25493 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
25494 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
25495 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
25496 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
25497 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
25498 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
25499 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
25500 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
25501 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
25503 case X86ISD::FOR: return PerformFORCombine(N, DAG);
25505 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
25506 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
25507 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
25508 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
25509 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
25510 case ISD::ANY_EXTEND:
25511 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
25512 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
25513 case ISD::SIGN_EXTEND_INREG:
25514 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
25515 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
25516 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
25517 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
25518 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
25519 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
25520 case X86ISD::SHUFP: // Handle all target specific shuffles
25521 case X86ISD::PALIGNR:
25522 case X86ISD::UNPCKH:
25523 case X86ISD::UNPCKL:
25524 case X86ISD::MOVHLPS:
25525 case X86ISD::MOVLHPS:
25526 case X86ISD::PSHUFB:
25527 case X86ISD::PSHUFD:
25528 case X86ISD::PSHUFHW:
25529 case X86ISD::PSHUFLW:
25530 case X86ISD::MOVSS:
25531 case X86ISD::MOVSD:
25532 case X86ISD::VPERMILPI:
25533 case X86ISD::VPERM2X128:
25534 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
25535 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
25536 case ISD::INTRINSIC_WO_CHAIN:
25537 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
25538 case X86ISD::INSERTPS:
25539 return PerformINSERTPSCombine(N, DAG, Subtarget);
25540 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
25546 /// isTypeDesirableForOp - Return true if the target has native support for
25547 /// the specified value type and it is 'desirable' to use the type for the
25548 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
25549 /// instruction encodings are longer and some i16 instructions are slow.
25550 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
25551 if (!isTypeLegal(VT))
25553 if (VT != MVT::i16)
25560 case ISD::SIGN_EXTEND:
25561 case ISD::ZERO_EXTEND:
25562 case ISD::ANY_EXTEND:
25575 /// IsDesirableToPromoteOp - This method query the target whether it is
25576 /// beneficial for dag combiner to promote the specified node. If true, it
25577 /// should return the desired promotion type by reference.
25578 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25579 EVT VT = Op.getValueType();
25580 if (VT != MVT::i16)
25583 bool Promote = false;
25584 bool Commute = false;
25585 switch (Op.getOpcode()) {
25588 LoadSDNode *LD = cast<LoadSDNode>(Op);
25589 // If the non-extending load has a single use and it's not live out, then it
25590 // might be folded.
25591 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25592 Op.hasOneUse()*/) {
25593 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25594 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25595 // The only case where we'd want to promote LOAD (rather then it being
25596 // promoted as an operand is when it's only use is liveout.
25597 if (UI->getOpcode() != ISD::CopyToReg)
25604 case ISD::SIGN_EXTEND:
25605 case ISD::ZERO_EXTEND:
25606 case ISD::ANY_EXTEND:
25611 SDValue N0 = Op.getOperand(0);
25612 // Look out for (store (shl (load), x)).
25613 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25626 SDValue N0 = Op.getOperand(0);
25627 SDValue N1 = Op.getOperand(1);
25628 if (!Commute && MayFoldLoad(N1))
25630 // Avoid disabling potential load folding opportunities.
25631 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25633 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25643 //===----------------------------------------------------------------------===//
25644 // X86 Inline Assembly Support
25645 //===----------------------------------------------------------------------===//
25648 // Helper to match a string separated by whitespace.
25649 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
25650 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
25652 for (unsigned i = 0, e = args.size(); i != e; ++i) {
25653 StringRef piece(*args[i]);
25654 if (!s.startswith(piece)) // Check if the piece matches.
25657 s = s.substr(piece.size());
25658 StringRef::size_type pos = s.find_first_not_of(" \t");
25659 if (pos == 0) // We matched a prefix.
25667 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
25670 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25672 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25673 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25674 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25675 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25677 if (AsmPieces.size() == 3)
25679 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25686 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25687 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25689 std::string AsmStr = IA->getAsmString();
25691 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25692 if (!Ty || Ty->getBitWidth() % 16 != 0)
25695 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25696 SmallVector<StringRef, 4> AsmPieces;
25697 SplitString(AsmStr, AsmPieces, ";\n");
25699 switch (AsmPieces.size()) {
25700 default: return false;
25702 // FIXME: this should verify that we are targeting a 486 or better. If not,
25703 // we will turn this bswap into something that will be lowered to logical
25704 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25705 // lower so don't worry about this.
25707 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
25708 matchAsm(AsmPieces[0], "bswapl", "$0") ||
25709 matchAsm(AsmPieces[0], "bswapq", "$0") ||
25710 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
25711 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
25712 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
25713 // No need to check constraints, nothing other than the equivalent of
25714 // "=r,0" would be valid here.
25715 return IntrinsicLowering::LowerToByteSwap(CI);
25718 // rorw $$8, ${0:w} --> llvm.bswap.i16
25719 if (CI->getType()->isIntegerTy(16) &&
25720 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25721 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
25722 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
25724 const std::string &ConstraintsStr = IA->getConstraintString();
25725 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25726 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25727 if (clobbersFlagRegisters(AsmPieces))
25728 return IntrinsicLowering::LowerToByteSwap(CI);
25732 if (CI->getType()->isIntegerTy(32) &&
25733 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25734 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
25735 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
25736 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
25738 const std::string &ConstraintsStr = IA->getConstraintString();
25739 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25740 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25741 if (clobbersFlagRegisters(AsmPieces))
25742 return IntrinsicLowering::LowerToByteSwap(CI);
25745 if (CI->getType()->isIntegerTy(64)) {
25746 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25747 if (Constraints.size() >= 2 &&
25748 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25749 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25750 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25751 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
25752 matchAsm(AsmPieces[1], "bswap", "%edx") &&
25753 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
25754 return IntrinsicLowering::LowerToByteSwap(CI);
25762 /// getConstraintType - Given a constraint letter, return the type of
25763 /// constraint it is for this target.
25764 X86TargetLowering::ConstraintType
25765 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
25766 if (Constraint.size() == 1) {
25767 switch (Constraint[0]) {
25778 return C_RegisterClass;
25802 return TargetLowering::getConstraintType(Constraint);
25805 /// Examine constraint type and operand type and determine a weight value.
25806 /// This object must already have been set up with the operand type
25807 /// and the current alternative constraint selected.
25808 TargetLowering::ConstraintWeight
25809 X86TargetLowering::getSingleConstraintMatchWeight(
25810 AsmOperandInfo &info, const char *constraint) const {
25811 ConstraintWeight weight = CW_Invalid;
25812 Value *CallOperandVal = info.CallOperandVal;
25813 // If we don't have a value, we can't do a match,
25814 // but allow it at the lowest weight.
25815 if (!CallOperandVal)
25817 Type *type = CallOperandVal->getType();
25818 // Look at the constraint type.
25819 switch (*constraint) {
25821 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
25832 if (CallOperandVal->getType()->isIntegerTy())
25833 weight = CW_SpecificReg;
25838 if (type->isFloatingPointTy())
25839 weight = CW_SpecificReg;
25842 if (type->isX86_MMXTy() && Subtarget->hasMMX())
25843 weight = CW_SpecificReg;
25847 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
25848 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
25849 weight = CW_Register;
25852 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
25853 if (C->getZExtValue() <= 31)
25854 weight = CW_Constant;
25858 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25859 if (C->getZExtValue() <= 63)
25860 weight = CW_Constant;
25864 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25865 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
25866 weight = CW_Constant;
25870 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25871 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
25872 weight = CW_Constant;
25876 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25877 if (C->getZExtValue() <= 3)
25878 weight = CW_Constant;
25882 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25883 if (C->getZExtValue() <= 0xff)
25884 weight = CW_Constant;
25889 if (dyn_cast<ConstantFP>(CallOperandVal)) {
25890 weight = CW_Constant;
25894 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25895 if ((C->getSExtValue() >= -0x80000000LL) &&
25896 (C->getSExtValue() <= 0x7fffffffLL))
25897 weight = CW_Constant;
25901 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25902 if (C->getZExtValue() <= 0xffffffff)
25903 weight = CW_Constant;
25910 /// LowerXConstraint - try to replace an X constraint, which matches anything,
25911 /// with another that has more specific requirements based on the type of the
25912 /// corresponding operand.
25913 const char *X86TargetLowering::
25914 LowerXConstraint(EVT ConstraintVT) const {
25915 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
25916 // 'f' like normal targets.
25917 if (ConstraintVT.isFloatingPoint()) {
25918 if (Subtarget->hasSSE2())
25920 if (Subtarget->hasSSE1())
25924 return TargetLowering::LowerXConstraint(ConstraintVT);
25927 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
25928 /// vector. If it is invalid, don't add anything to Ops.
25929 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
25930 std::string &Constraint,
25931 std::vector<SDValue>&Ops,
25932 SelectionDAG &DAG) const {
25935 // Only support length 1 constraints for now.
25936 if (Constraint.length() > 1) return;
25938 char ConstraintLetter = Constraint[0];
25939 switch (ConstraintLetter) {
25942 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25943 if (C->getZExtValue() <= 31) {
25944 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25950 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25951 if (C->getZExtValue() <= 63) {
25952 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25958 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25959 if (isInt<8>(C->getSExtValue())) {
25960 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25966 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25967 if (C->getZExtValue() <= 255) {
25968 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25974 // 32-bit signed value
25975 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25976 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25977 C->getSExtValue())) {
25978 // Widen to 64 bits here to get it sign extended.
25979 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
25982 // FIXME gcc accepts some relocatable values here too, but only in certain
25983 // memory models; it's complicated.
25988 // 32-bit unsigned value
25989 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25990 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25991 C->getZExtValue())) {
25992 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25996 // FIXME gcc accepts some relocatable values here too, but only in certain
25997 // memory models; it's complicated.
26001 // Literal immediates are always ok.
26002 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
26003 // Widen to 64 bits here to get it sign extended.
26004 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
26008 // In any sort of PIC mode addresses need to be computed at runtime by
26009 // adding in a register or some sort of table lookup. These can't
26010 // be used as immediates.
26011 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
26014 // If we are in non-pic codegen mode, we allow the address of a global (with
26015 // an optional displacement) to be used with 'i'.
26016 GlobalAddressSDNode *GA = nullptr;
26017 int64_t Offset = 0;
26019 // Match either (GA), (GA+C), (GA+C1+C2), etc.
26021 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
26022 Offset += GA->getOffset();
26024 } else if (Op.getOpcode() == ISD::ADD) {
26025 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26026 Offset += C->getZExtValue();
26027 Op = Op.getOperand(0);
26030 } else if (Op.getOpcode() == ISD::SUB) {
26031 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
26032 Offset += -C->getZExtValue();
26033 Op = Op.getOperand(0);
26038 // Otherwise, this isn't something we can handle, reject it.
26042 const GlobalValue *GV = GA->getGlobal();
26043 // If we require an extra load to get this address, as in PIC mode, we
26044 // can't accept it.
26045 if (isGlobalStubReference(
26046 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
26049 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
26050 GA->getValueType(0), Offset);
26055 if (Result.getNode()) {
26056 Ops.push_back(Result);
26059 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
26062 std::pair<unsigned, const TargetRegisterClass*>
26063 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
26065 // First, see if this is a constraint that directly corresponds to an LLVM
26067 if (Constraint.size() == 1) {
26068 // GCC Constraint Letters
26069 switch (Constraint[0]) {
26071 // TODO: Slight differences here in allocation order and leaving
26072 // RIP in the class. Do they matter any more here than they do
26073 // in the normal allocation?
26074 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
26075 if (Subtarget->is64Bit()) {
26076 if (VT == MVT::i32 || VT == MVT::f32)
26077 return std::make_pair(0U, &X86::GR32RegClass);
26078 if (VT == MVT::i16)
26079 return std::make_pair(0U, &X86::GR16RegClass);
26080 if (VT == MVT::i8 || VT == MVT::i1)
26081 return std::make_pair(0U, &X86::GR8RegClass);
26082 if (VT == MVT::i64 || VT == MVT::f64)
26083 return std::make_pair(0U, &X86::GR64RegClass);
26086 // 32-bit fallthrough
26087 case 'Q': // Q_REGS
26088 if (VT == MVT::i32 || VT == MVT::f32)
26089 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
26090 if (VT == MVT::i16)
26091 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
26092 if (VT == MVT::i8 || VT == MVT::i1)
26093 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
26094 if (VT == MVT::i64)
26095 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
26097 case 'r': // GENERAL_REGS
26098 case 'l': // INDEX_REGS
26099 if (VT == MVT::i8 || VT == MVT::i1)
26100 return std::make_pair(0U, &X86::GR8RegClass);
26101 if (VT == MVT::i16)
26102 return std::make_pair(0U, &X86::GR16RegClass);
26103 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
26104 return std::make_pair(0U, &X86::GR32RegClass);
26105 return std::make_pair(0U, &X86::GR64RegClass);
26106 case 'R': // LEGACY_REGS
26107 if (VT == MVT::i8 || VT == MVT::i1)
26108 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
26109 if (VT == MVT::i16)
26110 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
26111 if (VT == MVT::i32 || !Subtarget->is64Bit())
26112 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
26113 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
26114 case 'f': // FP Stack registers.
26115 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
26116 // value to the correct fpstack register class.
26117 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
26118 return std::make_pair(0U, &X86::RFP32RegClass);
26119 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
26120 return std::make_pair(0U, &X86::RFP64RegClass);
26121 return std::make_pair(0U, &X86::RFP80RegClass);
26122 case 'y': // MMX_REGS if MMX allowed.
26123 if (!Subtarget->hasMMX()) break;
26124 return std::make_pair(0U, &X86::VR64RegClass);
26125 case 'Y': // SSE_REGS if SSE2 allowed
26126 if (!Subtarget->hasSSE2()) break;
26128 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
26129 if (!Subtarget->hasSSE1()) break;
26131 switch (VT.SimpleTy) {
26133 // Scalar SSE types.
26136 return std::make_pair(0U, &X86::FR32RegClass);
26139 return std::make_pair(0U, &X86::FR64RegClass);
26147 return std::make_pair(0U, &X86::VR128RegClass);
26155 return std::make_pair(0U, &X86::VR256RegClass);
26160 return std::make_pair(0U, &X86::VR512RegClass);
26166 // Use the default implementation in TargetLowering to convert the register
26167 // constraint into a member of a register class.
26168 std::pair<unsigned, const TargetRegisterClass*> Res;
26169 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
26171 // Not found as a standard register?
26173 // Map st(0) -> st(7) -> ST0
26174 if (Constraint.size() == 7 && Constraint[0] == '{' &&
26175 tolower(Constraint[1]) == 's' &&
26176 tolower(Constraint[2]) == 't' &&
26177 Constraint[3] == '(' &&
26178 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
26179 Constraint[5] == ')' &&
26180 Constraint[6] == '}') {
26182 Res.first = X86::FP0+Constraint[4]-'0';
26183 Res.second = &X86::RFP80RegClass;
26187 // GCC allows "st(0)" to be called just plain "st".
26188 if (StringRef("{st}").equals_lower(Constraint)) {
26189 Res.first = X86::FP0;
26190 Res.second = &X86::RFP80RegClass;
26195 if (StringRef("{flags}").equals_lower(Constraint)) {
26196 Res.first = X86::EFLAGS;
26197 Res.second = &X86::CCRRegClass;
26201 // 'A' means EAX + EDX.
26202 if (Constraint == "A") {
26203 Res.first = X86::EAX;
26204 Res.second = &X86::GR32_ADRegClass;
26210 // Otherwise, check to see if this is a register class of the wrong value
26211 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
26212 // turn into {ax},{dx}.
26213 if (Res.second->hasType(VT))
26214 return Res; // Correct type already, nothing to do.
26216 // All of the single-register GCC register classes map their values onto
26217 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
26218 // really want an 8-bit or 32-bit register, map to the appropriate register
26219 // class and return the appropriate register.
26220 if (Res.second == &X86::GR16RegClass) {
26221 if (VT == MVT::i8 || VT == MVT::i1) {
26222 unsigned DestReg = 0;
26223 switch (Res.first) {
26225 case X86::AX: DestReg = X86::AL; break;
26226 case X86::DX: DestReg = X86::DL; break;
26227 case X86::CX: DestReg = X86::CL; break;
26228 case X86::BX: DestReg = X86::BL; break;
26231 Res.first = DestReg;
26232 Res.second = &X86::GR8RegClass;
26234 } else if (VT == MVT::i32 || VT == MVT::f32) {
26235 unsigned DestReg = 0;
26236 switch (Res.first) {
26238 case X86::AX: DestReg = X86::EAX; break;
26239 case X86::DX: DestReg = X86::EDX; break;
26240 case X86::CX: DestReg = X86::ECX; break;
26241 case X86::BX: DestReg = X86::EBX; break;
26242 case X86::SI: DestReg = X86::ESI; break;
26243 case X86::DI: DestReg = X86::EDI; break;
26244 case X86::BP: DestReg = X86::EBP; break;
26245 case X86::SP: DestReg = X86::ESP; break;
26248 Res.first = DestReg;
26249 Res.second = &X86::GR32RegClass;
26251 } else if (VT == MVT::i64 || VT == MVT::f64) {
26252 unsigned DestReg = 0;
26253 switch (Res.first) {
26255 case X86::AX: DestReg = X86::RAX; break;
26256 case X86::DX: DestReg = X86::RDX; break;
26257 case X86::CX: DestReg = X86::RCX; break;
26258 case X86::BX: DestReg = X86::RBX; break;
26259 case X86::SI: DestReg = X86::RSI; break;
26260 case X86::DI: DestReg = X86::RDI; break;
26261 case X86::BP: DestReg = X86::RBP; break;
26262 case X86::SP: DestReg = X86::RSP; break;
26265 Res.first = DestReg;
26266 Res.second = &X86::GR64RegClass;
26269 } else if (Res.second == &X86::FR32RegClass ||
26270 Res.second == &X86::FR64RegClass ||
26271 Res.second == &X86::VR128RegClass ||
26272 Res.second == &X86::VR256RegClass ||
26273 Res.second == &X86::FR32XRegClass ||
26274 Res.second == &X86::FR64XRegClass ||
26275 Res.second == &X86::VR128XRegClass ||
26276 Res.second == &X86::VR256XRegClass ||
26277 Res.second == &X86::VR512RegClass) {
26278 // Handle references to XMM physical registers that got mapped into the
26279 // wrong class. This can happen with constraints like {xmm0} where the
26280 // target independent register mapper will just pick the first match it can
26281 // find, ignoring the required type.
26283 if (VT == MVT::f32 || VT == MVT::i32)
26284 Res.second = &X86::FR32RegClass;
26285 else if (VT == MVT::f64 || VT == MVT::i64)
26286 Res.second = &X86::FR64RegClass;
26287 else if (X86::VR128RegClass.hasType(VT))
26288 Res.second = &X86::VR128RegClass;
26289 else if (X86::VR256RegClass.hasType(VT))
26290 Res.second = &X86::VR256RegClass;
26291 else if (X86::VR512RegClass.hasType(VT))
26292 Res.second = &X86::VR512RegClass;
26298 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
26300 // Scaling factors are not free at all.
26301 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
26302 // will take 2 allocations in the out of order engine instead of 1
26303 // for plain addressing mode, i.e. inst (reg1).
26305 // vaddps (%rsi,%drx), %ymm0, %ymm1
26306 // Requires two allocations (one for the load, one for the computation)
26308 // vaddps (%rsi), %ymm0, %ymm1
26309 // Requires just 1 allocation, i.e., freeing allocations for other operations
26310 // and having less micro operations to execute.
26312 // For some X86 architectures, this is even worse because for instance for
26313 // stores, the complex addressing mode forces the instruction to use the
26314 // "load" ports instead of the dedicated "store" port.
26315 // E.g., on Haswell:
26316 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
26317 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
26318 if (isLegalAddressingMode(AM, Ty))
26319 // Scale represents reg2 * scale, thus account for 1
26320 // as soon as we use a second register.
26321 return AM.Scale != 0;
26325 bool X86TargetLowering::isTargetFTOL() const {
26326 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();