1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
17 #include "Utils/X86ShuffleDecode.h"
19 #include "X86CallingConv.h"
20 #include "X86InstrBuilder.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/VariadicFunction.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/IR/CallingConv.h"
35 #include "llvm/IR/Constants.h"
36 #include "llvm/IR/DerivedTypes.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/IR/GlobalAlias.h"
39 #include "llvm/IR/GlobalVariable.h"
40 #include "llvm/IR/Instructions.h"
41 #include "llvm/IR/Intrinsics.h"
42 #include "llvm/MC/MCAsmInfo.h"
43 #include "llvm/MC/MCContext.h"
44 #include "llvm/MC/MCExpr.h"
45 #include "llvm/MC/MCSymbol.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
55 STATISTIC(NumTailCalls, "Number of tail calls");
57 // Forward declarations.
58 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
61 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
62 SelectionDAG &DAG, SDLoc dl,
63 unsigned vectorWidth) {
64 assert((vectorWidth == 128 || vectorWidth == 256) &&
65 "Unsupported vector width");
66 EVT VT = Vec.getValueType();
67 EVT ElVT = VT.getVectorElementType();
68 unsigned Factor = VT.getSizeInBits()/vectorWidth;
69 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
70 VT.getVectorNumElements()/Factor);
72 // Extract from UNDEF is UNDEF.
73 if (Vec.getOpcode() == ISD::UNDEF)
74 return DAG.getUNDEF(ResultVT);
76 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
77 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
79 // This is the index of the first element of the vectorWidth-bit chunk
81 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
84 // If the input is a buildvector just emit a smaller one.
85 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
86 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
87 Vec->op_begin()+NormalizedIdxVal, ElemsPerChunk);
89 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
90 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
96 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
97 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
98 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
99 /// instructions or a simple subregister reference. Idx is an index in the
100 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
101 /// lowering EXTRACT_VECTOR_ELT operations easier.
102 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
103 SelectionDAG &DAG, SDLoc dl) {
104 assert((Vec.getValueType().is256BitVector() ||
105 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
106 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
109 /// Generate a DAG to grab 256-bits from a 512-bit vector.
110 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
111 SelectionDAG &DAG, SDLoc dl) {
112 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
113 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
116 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
117 unsigned IdxVal, SelectionDAG &DAG,
118 SDLoc dl, unsigned vectorWidth) {
119 assert((vectorWidth == 128 || vectorWidth == 256) &&
120 "Unsupported vector width");
121 // Inserting UNDEF is Result
122 if (Vec.getOpcode() == ISD::UNDEF)
124 EVT VT = Vec.getValueType();
125 EVT ElVT = VT.getVectorElementType();
126 EVT ResultVT = Result.getValueType();
128 // Insert the relevant vectorWidth bits.
129 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
131 // This is the index of the first element of the vectorWidth-bit chunk
133 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
136 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
137 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
140 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
141 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
142 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
143 /// simple superregister reference. Idx is an index in the 128 bits
144 /// we want. It need not be aligned to a 128-bit bounday. That makes
145 /// lowering INSERT_VECTOR_ELT operations easier.
146 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
147 unsigned IdxVal, SelectionDAG &DAG,
149 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
150 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
153 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
154 unsigned IdxVal, SelectionDAG &DAG,
156 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
157 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
160 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
161 /// instructions. This is used because creating CONCAT_VECTOR nodes of
162 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
163 /// large BUILD_VECTORS.
164 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
165 unsigned NumElems, SelectionDAG &DAG,
167 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
168 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
171 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
172 unsigned NumElems, SelectionDAG &DAG,
174 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
175 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
178 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
179 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
180 bool is64Bit = Subtarget->is64Bit();
182 if (Subtarget->isTargetMacho()) {
184 return new X86_64MachoTargetObjectFile();
185 return new TargetLoweringObjectFileMachO();
188 if (Subtarget->isTargetLinux())
189 return new X86LinuxTargetObjectFile();
190 if (Subtarget->isTargetELF())
191 return new TargetLoweringObjectFileELF();
192 if (Subtarget->isTargetWindows())
193 return new X86WindowsTargetObjectFile();
194 if (Subtarget->isTargetCOFF())
195 return new TargetLoweringObjectFileCOFF();
196 llvm_unreachable("unknown subtarget type");
199 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
200 : TargetLowering(TM, createTLOF(TM)) {
201 Subtarget = &TM.getSubtarget<X86Subtarget>();
202 X86ScalarSSEf64 = Subtarget->hasSSE2();
203 X86ScalarSSEf32 = Subtarget->hasSSE1();
204 TD = getDataLayout();
206 resetOperationActions();
209 void X86TargetLowering::resetOperationActions() {
210 const TargetMachine &TM = getTargetMachine();
211 static bool FirstTimeThrough = true;
213 // If none of the target options have changed, then we don't need to reset the
214 // operation actions.
215 if (!FirstTimeThrough && TO == TM.Options) return;
217 if (!FirstTimeThrough) {
218 // Reinitialize the actions.
220 FirstTimeThrough = false;
225 // Set up the TargetLowering object.
226 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
228 // X86 is weird, it always uses i8 for shift amounts and setcc results.
229 setBooleanContents(ZeroOrOneBooleanContent);
230 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
231 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
233 // For 64-bit since we have so many registers use the ILP scheduler, for
234 // 32-bit code use the register pressure specific scheduling.
235 // For Atom, always use ILP scheduling.
236 if (Subtarget->isAtom())
237 setSchedulingPreference(Sched::ILP);
238 else if (Subtarget->is64Bit())
239 setSchedulingPreference(Sched::ILP);
241 setSchedulingPreference(Sched::RegPressure);
242 const X86RegisterInfo *RegInfo =
243 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
244 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
246 // Bypass expensive divides on Atom when compiling with O2
247 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
248 addBypassSlowDiv(32, 8);
249 if (Subtarget->is64Bit())
250 addBypassSlowDiv(64, 16);
253 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
254 // Setup Windows compiler runtime calls.
255 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
256 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
257 setLibcallName(RTLIB::SREM_I64, "_allrem");
258 setLibcallName(RTLIB::UREM_I64, "_aullrem");
259 setLibcallName(RTLIB::MUL_I64, "_allmul");
260 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
261 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
262 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
263 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
264 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
266 // The _ftol2 runtime function has an unusual calling conv, which
267 // is modeled by a special pseudo-instruction.
268 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
269 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
270 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
271 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
274 if (Subtarget->isTargetDarwin()) {
275 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
276 setUseUnderscoreSetJmp(false);
277 setUseUnderscoreLongJmp(false);
278 } else if (Subtarget->isTargetMingw()) {
279 // MS runtime is weird: it exports _setjmp, but longjmp!
280 setUseUnderscoreSetJmp(true);
281 setUseUnderscoreLongJmp(false);
283 setUseUnderscoreSetJmp(true);
284 setUseUnderscoreLongJmp(true);
287 // Set up the register classes.
288 addRegisterClass(MVT::i8, &X86::GR8RegClass);
289 addRegisterClass(MVT::i16, &X86::GR16RegClass);
290 addRegisterClass(MVT::i32, &X86::GR32RegClass);
291 if (Subtarget->is64Bit())
292 addRegisterClass(MVT::i64, &X86::GR64RegClass);
294 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
296 // We don't accept any truncstore of integer registers.
297 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
298 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
299 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
300 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
301 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
302 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
304 // SETOEQ and SETUNE require checking two conditions.
305 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
306 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
307 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
308 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
309 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
310 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
312 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
314 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
315 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
316 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
318 if (Subtarget->is64Bit()) {
319 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
320 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
321 } else if (!TM.Options.UseSoftFloat) {
322 // We have an algorithm for SSE2->double, and we turn this into a
323 // 64-bit FILD followed by conditional FADD for other targets.
324 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
325 // We have an algorithm for SSE2, and we turn this into a 64-bit
326 // FILD for other targets.
327 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
330 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
332 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
333 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
335 if (!TM.Options.UseSoftFloat) {
336 // SSE has no i16 to fp conversion, only i32
337 if (X86ScalarSSEf32) {
338 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
339 // f32 and f64 cases are Legal, f80 case is not
340 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
342 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
343 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
346 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
347 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
350 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
351 // are Legal, f80 is custom lowered.
352 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
353 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
355 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
357 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
358 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
360 if (X86ScalarSSEf32) {
361 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
362 // f32 and f64 cases are Legal, f80 case is not
363 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
365 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
366 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
369 // Handle FP_TO_UINT by promoting the destination to a larger signed
371 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
372 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
373 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
375 if (Subtarget->is64Bit()) {
376 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
377 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
378 } else if (!TM.Options.UseSoftFloat) {
379 // Since AVX is a superset of SSE3, only check for SSE here.
380 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
381 // Expand FP_TO_UINT into a select.
382 // FIXME: We would like to use a Custom expander here eventually to do
383 // the optimal thing for SSE vs. the default expansion in the legalizer.
384 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
386 // With SSE3 we can use fisttpll to convert to a signed i64; without
387 // SSE, we're stuck with a fistpll.
388 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
391 if (isTargetFTOL()) {
392 // Use the _ftol2 runtime function, which has a pseudo-instruction
393 // to handle its weird calling convention.
394 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
397 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
398 if (!X86ScalarSSEf64) {
399 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
400 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
401 if (Subtarget->is64Bit()) {
402 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
403 // Without SSE, i64->f64 goes through memory.
404 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
408 // Scalar integer divide and remainder are lowered to use operations that
409 // produce two results, to match the available instructions. This exposes
410 // the two-result form to trivial CSE, which is able to combine x/y and x%y
411 // into a single instruction.
413 // Scalar integer multiply-high is also lowered to use two-result
414 // operations, to match the available instructions. However, plain multiply
415 // (low) operations are left as Legal, as there are single-result
416 // instructions for this in x86. Using the two-result multiply instructions
417 // when both high and low results are needed must be arranged by dagcombine.
418 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
420 setOperationAction(ISD::MULHS, VT, Expand);
421 setOperationAction(ISD::MULHU, VT, Expand);
422 setOperationAction(ISD::SDIV, VT, Expand);
423 setOperationAction(ISD::UDIV, VT, Expand);
424 setOperationAction(ISD::SREM, VT, Expand);
425 setOperationAction(ISD::UREM, VT, Expand);
427 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
428 setOperationAction(ISD::ADDC, VT, Custom);
429 setOperationAction(ISD::ADDE, VT, Custom);
430 setOperationAction(ISD::SUBC, VT, Custom);
431 setOperationAction(ISD::SUBE, VT, Custom);
434 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
435 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
436 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
437 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
438 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
439 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
440 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
441 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
442 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
443 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
444 if (Subtarget->is64Bit())
445 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
446 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
447 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
448 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
449 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
450 setOperationAction(ISD::FREM , MVT::f32 , Expand);
451 setOperationAction(ISD::FREM , MVT::f64 , Expand);
452 setOperationAction(ISD::FREM , MVT::f80 , Expand);
453 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
455 // Promote the i8 variants and force them on up to i32 which has a shorter
457 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
458 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
459 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
460 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
461 if (Subtarget->hasBMI()) {
462 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
463 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
464 if (Subtarget->is64Bit())
465 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
467 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
468 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
469 if (Subtarget->is64Bit())
470 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
473 if (Subtarget->hasLZCNT()) {
474 // When promoting the i8 variants, force them to i32 for a shorter
476 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
477 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
478 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
479 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
480 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
481 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
482 if (Subtarget->is64Bit())
483 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
485 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
486 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
487 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
488 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
489 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
490 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
491 if (Subtarget->is64Bit()) {
492 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
493 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
497 if (Subtarget->hasPOPCNT()) {
498 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
500 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
501 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
502 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
503 if (Subtarget->is64Bit())
504 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
507 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
508 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
510 // These should be promoted to a larger select which is supported.
511 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
512 // X86 wants to expand cmov itself.
513 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
514 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
515 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
516 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
517 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
518 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
519 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
520 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
521 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
522 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
523 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
524 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
525 if (Subtarget->is64Bit()) {
526 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
527 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
529 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
530 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
531 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
532 // support continuation, user-level threading, and etc.. As a result, no
533 // other SjLj exception interfaces are implemented and please don't build
534 // your own exception handling based on them.
535 // LLVM/Clang supports zero-cost DWARF exception handling.
536 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
537 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
540 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
541 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
542 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
543 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
544 if (Subtarget->is64Bit())
545 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
546 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
547 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
548 if (Subtarget->is64Bit()) {
549 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
550 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
551 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
552 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
553 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
555 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
556 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
557 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
558 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
559 if (Subtarget->is64Bit()) {
560 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
561 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
562 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
565 if (Subtarget->hasSSE1())
566 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
568 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
570 // Expand certain atomics
571 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
573 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
574 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
575 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
578 if (!Subtarget->is64Bit()) {
579 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
580 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
581 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
582 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
583 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
584 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
585 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
586 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
587 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
588 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
589 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
590 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
593 if (Subtarget->hasCmpxchg16b()) {
594 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
597 // FIXME - use subtarget debug flags
598 if (!Subtarget->isTargetDarwin() &&
599 !Subtarget->isTargetELF() &&
600 !Subtarget->isTargetCygMing()) {
601 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
604 if (Subtarget->is64Bit()) {
605 setExceptionPointerRegister(X86::RAX);
606 setExceptionSelectorRegister(X86::RDX);
608 setExceptionPointerRegister(X86::EAX);
609 setExceptionSelectorRegister(X86::EDX);
611 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
612 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
614 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
615 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
617 setOperationAction(ISD::TRAP, MVT::Other, Legal);
618 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
620 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
621 setOperationAction(ISD::VASTART , MVT::Other, Custom);
622 setOperationAction(ISD::VAEND , MVT::Other, Expand);
623 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
624 // TargetInfo::X86_64ABIBuiltinVaList
625 setOperationAction(ISD::VAARG , MVT::Other, Custom);
626 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
628 // TargetInfo::CharPtrBuiltinVaList
629 setOperationAction(ISD::VAARG , MVT::Other, Expand);
630 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
633 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
634 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
636 if (Subtarget->isOSWindows() && !Subtarget->isTargetMacho())
637 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
638 MVT::i64 : MVT::i32, Custom);
639 else if (TM.Options.EnableSegmentedStacks)
640 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
641 MVT::i64 : MVT::i32, Custom);
643 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
644 MVT::i64 : MVT::i32, Expand);
646 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
647 // f32 and f64 use SSE.
648 // Set up the FP register classes.
649 addRegisterClass(MVT::f32, &X86::FR32RegClass);
650 addRegisterClass(MVT::f64, &X86::FR64RegClass);
652 // Use ANDPD to simulate FABS.
653 setOperationAction(ISD::FABS , MVT::f64, Custom);
654 setOperationAction(ISD::FABS , MVT::f32, Custom);
656 // Use XORP to simulate FNEG.
657 setOperationAction(ISD::FNEG , MVT::f64, Custom);
658 setOperationAction(ISD::FNEG , MVT::f32, Custom);
660 // Use ANDPD and ORPD to simulate FCOPYSIGN.
661 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
662 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
664 // Lower this to FGETSIGNx86 plus an AND.
665 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
666 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
668 // We don't support sin/cos/fmod
669 setOperationAction(ISD::FSIN , MVT::f64, Expand);
670 setOperationAction(ISD::FCOS , MVT::f64, Expand);
671 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
672 setOperationAction(ISD::FSIN , MVT::f32, Expand);
673 setOperationAction(ISD::FCOS , MVT::f32, Expand);
674 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
676 // Expand FP immediates into loads from the stack, except for the special
678 addLegalFPImmediate(APFloat(+0.0)); // xorpd
679 addLegalFPImmediate(APFloat(+0.0f)); // xorps
680 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
681 // Use SSE for f32, x87 for f64.
682 // Set up the FP register classes.
683 addRegisterClass(MVT::f32, &X86::FR32RegClass);
684 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
686 // Use ANDPS to simulate FABS.
687 setOperationAction(ISD::FABS , MVT::f32, Custom);
689 // Use XORP to simulate FNEG.
690 setOperationAction(ISD::FNEG , MVT::f32, Custom);
692 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
694 // Use ANDPS and ORPS to simulate FCOPYSIGN.
695 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
696 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
698 // We don't support sin/cos/fmod
699 setOperationAction(ISD::FSIN , MVT::f32, Expand);
700 setOperationAction(ISD::FCOS , MVT::f32, Expand);
701 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
703 // Special cases we handle for FP constants.
704 addLegalFPImmediate(APFloat(+0.0f)); // xorps
705 addLegalFPImmediate(APFloat(+0.0)); // FLD0
706 addLegalFPImmediate(APFloat(+1.0)); // FLD1
707 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
708 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
710 if (!TM.Options.UnsafeFPMath) {
711 setOperationAction(ISD::FSIN , MVT::f64, Expand);
712 setOperationAction(ISD::FCOS , MVT::f64, Expand);
713 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
715 } else if (!TM.Options.UseSoftFloat) {
716 // f32 and f64 in x87.
717 // Set up the FP register classes.
718 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
719 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
721 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
722 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
723 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
724 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
726 if (!TM.Options.UnsafeFPMath) {
727 setOperationAction(ISD::FSIN , MVT::f64, Expand);
728 setOperationAction(ISD::FSIN , MVT::f32, Expand);
729 setOperationAction(ISD::FCOS , MVT::f64, Expand);
730 setOperationAction(ISD::FCOS , MVT::f32, Expand);
731 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
732 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
734 addLegalFPImmediate(APFloat(+0.0)); // FLD0
735 addLegalFPImmediate(APFloat(+1.0)); // FLD1
736 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
737 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
738 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
739 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
740 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
741 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
744 // We don't support FMA.
745 setOperationAction(ISD::FMA, MVT::f64, Expand);
746 setOperationAction(ISD::FMA, MVT::f32, Expand);
748 // Long double always uses X87.
749 if (!TM.Options.UseSoftFloat) {
750 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
751 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
752 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
754 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
755 addLegalFPImmediate(TmpFlt); // FLD0
757 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
760 APFloat TmpFlt2(+1.0);
761 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
763 addLegalFPImmediate(TmpFlt2); // FLD1
764 TmpFlt2.changeSign();
765 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
768 if (!TM.Options.UnsafeFPMath) {
769 setOperationAction(ISD::FSIN , MVT::f80, Expand);
770 setOperationAction(ISD::FCOS , MVT::f80, Expand);
771 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
774 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
775 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
776 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
777 setOperationAction(ISD::FRINT, MVT::f80, Expand);
778 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
779 setOperationAction(ISD::FMA, MVT::f80, Expand);
782 // Always use a library call for pow.
783 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
784 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
785 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
787 setOperationAction(ISD::FLOG, MVT::f80, Expand);
788 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
789 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
790 setOperationAction(ISD::FEXP, MVT::f80, Expand);
791 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
793 // First set operation action for all vector types to either promote
794 // (for widening) or expand (for scalarization). Then we will selectively
795 // turn on ones that can be effectively codegen'd.
796 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
797 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
798 MVT VT = (MVT::SimpleValueType)i;
799 setOperationAction(ISD::ADD , VT, Expand);
800 setOperationAction(ISD::SUB , VT, Expand);
801 setOperationAction(ISD::FADD, VT, Expand);
802 setOperationAction(ISD::FNEG, VT, Expand);
803 setOperationAction(ISD::FSUB, VT, Expand);
804 setOperationAction(ISD::MUL , VT, Expand);
805 setOperationAction(ISD::FMUL, VT, Expand);
806 setOperationAction(ISD::SDIV, VT, Expand);
807 setOperationAction(ISD::UDIV, VT, Expand);
808 setOperationAction(ISD::FDIV, VT, Expand);
809 setOperationAction(ISD::SREM, VT, Expand);
810 setOperationAction(ISD::UREM, VT, Expand);
811 setOperationAction(ISD::LOAD, VT, Expand);
812 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
813 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
814 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
815 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
816 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
817 setOperationAction(ISD::FABS, VT, Expand);
818 setOperationAction(ISD::FSIN, VT, Expand);
819 setOperationAction(ISD::FSINCOS, VT, Expand);
820 setOperationAction(ISD::FCOS, VT, Expand);
821 setOperationAction(ISD::FSINCOS, VT, Expand);
822 setOperationAction(ISD::FREM, VT, Expand);
823 setOperationAction(ISD::FMA, VT, Expand);
824 setOperationAction(ISD::FPOWI, VT, Expand);
825 setOperationAction(ISD::FSQRT, VT, Expand);
826 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
827 setOperationAction(ISD::FFLOOR, VT, Expand);
828 setOperationAction(ISD::FCEIL, VT, Expand);
829 setOperationAction(ISD::FTRUNC, VT, Expand);
830 setOperationAction(ISD::FRINT, VT, Expand);
831 setOperationAction(ISD::FNEARBYINT, VT, Expand);
832 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
833 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
834 setOperationAction(ISD::SDIVREM, VT, Expand);
835 setOperationAction(ISD::UDIVREM, VT, Expand);
836 setOperationAction(ISD::FPOW, VT, Expand);
837 setOperationAction(ISD::CTPOP, VT, Expand);
838 setOperationAction(ISD::CTTZ, VT, Expand);
839 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
840 setOperationAction(ISD::CTLZ, VT, Expand);
841 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
842 setOperationAction(ISD::SHL, VT, Expand);
843 setOperationAction(ISD::SRA, VT, Expand);
844 setOperationAction(ISD::SRL, VT, Expand);
845 setOperationAction(ISD::ROTL, VT, Expand);
846 setOperationAction(ISD::ROTR, VT, Expand);
847 setOperationAction(ISD::BSWAP, VT, Expand);
848 setOperationAction(ISD::SETCC, VT, Expand);
849 setOperationAction(ISD::FLOG, VT, Expand);
850 setOperationAction(ISD::FLOG2, VT, Expand);
851 setOperationAction(ISD::FLOG10, VT, Expand);
852 setOperationAction(ISD::FEXP, VT, Expand);
853 setOperationAction(ISD::FEXP2, VT, Expand);
854 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
855 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
856 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
857 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
858 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
859 setOperationAction(ISD::TRUNCATE, VT, Expand);
860 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
861 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
862 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
863 setOperationAction(ISD::VSELECT, VT, Expand);
864 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
865 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
866 setTruncStoreAction(VT,
867 (MVT::SimpleValueType)InnerVT, Expand);
868 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
869 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
870 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
873 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
874 // with -msoft-float, disable use of MMX as well.
875 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
876 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
877 // No operations on x86mmx supported, everything uses intrinsics.
880 // MMX-sized vectors (other than x86mmx) are expected to be expanded
881 // into smaller operations.
882 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
883 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
884 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
885 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
886 setOperationAction(ISD::AND, MVT::v8i8, Expand);
887 setOperationAction(ISD::AND, MVT::v4i16, Expand);
888 setOperationAction(ISD::AND, MVT::v2i32, Expand);
889 setOperationAction(ISD::AND, MVT::v1i64, Expand);
890 setOperationAction(ISD::OR, MVT::v8i8, Expand);
891 setOperationAction(ISD::OR, MVT::v4i16, Expand);
892 setOperationAction(ISD::OR, MVT::v2i32, Expand);
893 setOperationAction(ISD::OR, MVT::v1i64, Expand);
894 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
895 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
896 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
897 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
898 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
899 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
900 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
901 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
902 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
903 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
904 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
905 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
906 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
907 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
908 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
909 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
910 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
912 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
913 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
915 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
916 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
917 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
918 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
919 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
920 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
921 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
922 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
923 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
924 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
925 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
926 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
929 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
930 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
932 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
933 // registers cannot be used even for integer operations.
934 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
935 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
936 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
937 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
939 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
940 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
941 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
942 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
943 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
944 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
945 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
946 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
947 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
948 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
949 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
950 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
951 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
952 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
953 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
954 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
955 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
956 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
958 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
959 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
960 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
961 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
963 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
964 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
966 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
967 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
969 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
970 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
971 MVT VT = (MVT::SimpleValueType)i;
972 // Do not attempt to custom lower non-power-of-2 vectors
973 if (!isPowerOf2_32(VT.getVectorNumElements()))
975 // Do not attempt to custom lower non-128-bit vectors
976 if (!VT.is128BitVector())
978 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
979 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
980 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
983 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
984 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
985 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
986 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
987 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
988 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
990 if (Subtarget->is64Bit()) {
991 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
992 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
995 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
996 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
997 MVT VT = (MVT::SimpleValueType)i;
999 // Do not attempt to promote non-128-bit vectors
1000 if (!VT.is128BitVector())
1003 setOperationAction(ISD::AND, VT, Promote);
1004 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1005 setOperationAction(ISD::OR, VT, Promote);
1006 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1007 setOperationAction(ISD::XOR, VT, Promote);
1008 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1009 setOperationAction(ISD::LOAD, VT, Promote);
1010 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1011 setOperationAction(ISD::SELECT, VT, Promote);
1012 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1015 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1017 // Custom lower v2i64 and v2f64 selects.
1018 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1019 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1020 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1021 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1023 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1024 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1026 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1027 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1028 // As there is no 64-bit GPR available, we need build a special custom
1029 // sequence to convert from v2i32 to v2f32.
1030 if (!Subtarget->is64Bit())
1031 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1033 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1034 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1036 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1039 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1040 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1041 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1042 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1043 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1044 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1045 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1046 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1047 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1048 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1049 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1051 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1052 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1053 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1054 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1055 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1056 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1057 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1058 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1059 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1060 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1062 // FIXME: Do we need to handle scalar-to-vector here?
1063 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1065 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
1066 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
1067 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1068 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
1069 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
1071 // i8 and i16 vectors are custom , because the source register and source
1072 // source memory operand types are not the same width. f32 vectors are
1073 // custom since the immediate controlling the insert encodes additional
1075 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1076 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1077 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1078 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1080 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1081 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1082 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1083 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1085 // FIXME: these should be Legal but thats only for the case where
1086 // the index is constant. For now custom expand to deal with that.
1087 if (Subtarget->is64Bit()) {
1088 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1089 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1093 if (Subtarget->hasSSE2()) {
1094 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1095 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1097 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1098 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1100 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1101 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1103 // In the customized shift lowering, the legal cases in AVX2 will be
1105 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1106 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1108 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1109 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1111 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1113 setOperationAction(ISD::SDIV, MVT::v8i16, Custom);
1114 setOperationAction(ISD::SDIV, MVT::v4i32, Custom);
1117 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1118 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1119 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1120 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1121 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1122 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1123 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1125 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1126 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1127 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1129 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1130 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1131 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1132 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1133 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1134 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1135 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1136 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1137 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1138 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1139 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1140 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1142 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1143 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1144 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1145 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1146 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1147 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1148 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1149 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1150 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1151 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1152 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1153 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1155 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
1157 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1158 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1159 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1160 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1162 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1163 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1165 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1167 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1168 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1170 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1171 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1173 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1174 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1176 setOperationAction(ISD::SDIV, MVT::v16i16, Custom);
1178 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1179 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1180 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1181 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1183 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1184 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1185 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1187 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1188 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1189 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1190 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1192 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1193 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1194 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1195 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1196 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1197 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1198 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1199 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1200 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1201 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1202 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1203 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1205 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1206 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1207 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1209 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1210 setOperationAction(ISD::FMA, MVT::f32, Legal);
1211 setOperationAction(ISD::FMA, MVT::f64, Legal);
1214 if (Subtarget->hasInt256()) {
1215 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1216 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1217 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1218 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1220 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1221 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1222 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1223 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1225 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1226 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1227 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1228 // Don't lower v32i8 because there is no 128-bit byte mul
1230 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1232 setOperationAction(ISD::SDIV, MVT::v8i32, Custom);
1234 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1235 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1236 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1237 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1239 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1240 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1241 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1242 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1244 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1245 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1246 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1247 // Don't lower v32i8 because there is no 128-bit byte mul
1250 // In the customized shift lowering, the legal cases in AVX2 will be
1252 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1253 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1255 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1256 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1258 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1260 // Custom lower several nodes for 256-bit types.
1261 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1262 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1263 MVT VT = (MVT::SimpleValueType)i;
1265 // Extract subvector is special because the value type
1266 // (result) is 128-bit but the source is 256-bit wide.
1267 if (VT.is128BitVector())
1268 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1270 // Do not attempt to custom lower other non-256-bit vectors
1271 if (!VT.is256BitVector())
1274 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1275 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1276 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1277 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1278 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1279 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1280 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1283 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1284 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1285 MVT VT = (MVT::SimpleValueType)i;
1287 // Do not attempt to promote non-256-bit vectors
1288 if (!VT.is256BitVector())
1291 setOperationAction(ISD::AND, VT, Promote);
1292 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1293 setOperationAction(ISD::OR, VT, Promote);
1294 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1295 setOperationAction(ISD::XOR, VT, Promote);
1296 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1297 setOperationAction(ISD::LOAD, VT, Promote);
1298 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1299 setOperationAction(ISD::SELECT, VT, Promote);
1300 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1304 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1305 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1306 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1307 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1308 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1310 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1311 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1312 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1314 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1315 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1316 setOperationAction(ISD::XOR, MVT::i1, Legal);
1317 setOperationAction(ISD::OR, MVT::i1, Legal);
1318 setOperationAction(ISD::AND, MVT::i1, Legal);
1319 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1320 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1321 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1322 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1323 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1324 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1326 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1327 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1328 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1329 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1330 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1331 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1333 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1334 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1335 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1336 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1337 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1338 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1339 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1340 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1341 setOperationAction(ISD::SDIV, MVT::v16i32, Custom);
1343 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1344 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1345 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1346 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1347 if (Subtarget->is64Bit()) {
1348 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1349 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1350 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1351 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1353 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1354 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1355 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1356 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1357 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1358 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1359 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1360 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1362 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1363 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1364 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1365 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1366 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1367 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1368 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1369 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1370 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1371 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1372 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1373 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1374 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1376 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1377 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1378 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1379 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1380 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1381 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1383 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1384 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1386 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1388 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1389 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1390 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1391 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1392 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1393 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1394 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1396 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1397 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1399 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1400 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1402 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1404 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1405 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1407 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1408 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1410 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1411 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1413 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1414 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1415 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1416 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1417 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1418 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1420 // Custom lower several nodes.
1421 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1422 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1423 MVT VT = (MVT::SimpleValueType)i;
1425 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1426 // Extract subvector is special because the value type
1427 // (result) is 256/128-bit but the source is 512-bit wide.
1428 if (VT.is128BitVector() || VT.is256BitVector())
1429 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1431 if (VT.getVectorElementType() == MVT::i1)
1432 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1434 // Do not attempt to custom lower other non-512-bit vectors
1435 if (!VT.is512BitVector())
1438 if ( EltSize >= 32) {
1439 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1440 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1441 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1442 setOperationAction(ISD::VSELECT, VT, Legal);
1443 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1444 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1445 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1448 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1449 MVT VT = (MVT::SimpleValueType)i;
1451 // Do not attempt to promote non-256-bit vectors
1452 if (!VT.is512BitVector())
1455 setOperationAction(ISD::SELECT, VT, Promote);
1456 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1460 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1461 // of this type with custom code.
1462 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1463 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1464 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1468 // We want to custom lower some of our intrinsics.
1469 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1470 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1471 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1473 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1474 // handle type legalization for these operations here.
1476 // FIXME: We really should do custom legalization for addition and
1477 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1478 // than generic legalization for 64-bit multiplication-with-overflow, though.
1479 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1480 // Add/Sub/Mul with overflow operations are custom lowered.
1482 setOperationAction(ISD::SADDO, VT, Custom);
1483 setOperationAction(ISD::UADDO, VT, Custom);
1484 setOperationAction(ISD::SSUBO, VT, Custom);
1485 setOperationAction(ISD::USUBO, VT, Custom);
1486 setOperationAction(ISD::SMULO, VT, Custom);
1487 setOperationAction(ISD::UMULO, VT, Custom);
1490 // There are no 8-bit 3-address imul/mul instructions
1491 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1492 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1494 if (!Subtarget->is64Bit()) {
1495 // These libcalls are not available in 32-bit.
1496 setLibcallName(RTLIB::SHL_I128, 0);
1497 setLibcallName(RTLIB::SRL_I128, 0);
1498 setLibcallName(RTLIB::SRA_I128, 0);
1501 // Combine sin / cos into one node or libcall if possible.
1502 if (Subtarget->hasSinCos()) {
1503 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1504 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1505 if (Subtarget->isTargetDarwin()) {
1506 // For MacOSX, we don't want to the normal expansion of a libcall to
1507 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1509 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1510 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1514 // We have target-specific dag combine patterns for the following nodes:
1515 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1516 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1517 setTargetDAGCombine(ISD::VSELECT);
1518 setTargetDAGCombine(ISD::SELECT);
1519 setTargetDAGCombine(ISD::SHL);
1520 setTargetDAGCombine(ISD::SRA);
1521 setTargetDAGCombine(ISD::SRL);
1522 setTargetDAGCombine(ISD::OR);
1523 setTargetDAGCombine(ISD::AND);
1524 setTargetDAGCombine(ISD::ADD);
1525 setTargetDAGCombine(ISD::FADD);
1526 setTargetDAGCombine(ISD::FSUB);
1527 setTargetDAGCombine(ISD::FMA);
1528 setTargetDAGCombine(ISD::SUB);
1529 setTargetDAGCombine(ISD::LOAD);
1530 setTargetDAGCombine(ISD::STORE);
1531 setTargetDAGCombine(ISD::ZERO_EXTEND);
1532 setTargetDAGCombine(ISD::ANY_EXTEND);
1533 setTargetDAGCombine(ISD::SIGN_EXTEND);
1534 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1535 setTargetDAGCombine(ISD::TRUNCATE);
1536 setTargetDAGCombine(ISD::SINT_TO_FP);
1537 setTargetDAGCombine(ISD::SETCC);
1538 if (Subtarget->is64Bit())
1539 setTargetDAGCombine(ISD::MUL);
1540 setTargetDAGCombine(ISD::XOR);
1542 computeRegisterProperties();
1544 // On Darwin, -Os means optimize for size without hurting performance,
1545 // do not reduce the limit.
1546 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1547 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1548 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1549 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1550 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1551 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1552 setPrefLoopAlignment(4); // 2^4 bytes.
1554 // Predictable cmov don't hurt on atom because it's in-order.
1555 PredictableSelectIsExpensive = !Subtarget->isAtom();
1557 setPrefFunctionAlignment(4); // 2^4 bytes.
1560 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1562 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1564 if (Subtarget->hasAVX512())
1565 switch(VT.getVectorNumElements()) {
1566 case 8: return MVT::v8i1;
1567 case 16: return MVT::v16i1;
1570 return VT.changeVectorElementTypeToInteger();
1573 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1574 /// the desired ByVal argument alignment.
1575 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1578 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1579 if (VTy->getBitWidth() == 128)
1581 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1582 unsigned EltAlign = 0;
1583 getMaxByValAlign(ATy->getElementType(), EltAlign);
1584 if (EltAlign > MaxAlign)
1585 MaxAlign = EltAlign;
1586 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1587 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1588 unsigned EltAlign = 0;
1589 getMaxByValAlign(STy->getElementType(i), EltAlign);
1590 if (EltAlign > MaxAlign)
1591 MaxAlign = EltAlign;
1598 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1599 /// function arguments in the caller parameter area. For X86, aggregates
1600 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1601 /// are at 4-byte boundaries.
1602 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1603 if (Subtarget->is64Bit()) {
1604 // Max of 8 and alignment of type.
1605 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1612 if (Subtarget->hasSSE1())
1613 getMaxByValAlign(Ty, Align);
1617 /// getOptimalMemOpType - Returns the target specific optimal type for load
1618 /// and store operations as a result of memset, memcpy, and memmove
1619 /// lowering. If DstAlign is zero that means it's safe to destination
1620 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1621 /// means there isn't a need to check it against alignment requirement,
1622 /// probably because the source does not need to be loaded. If 'IsMemset' is
1623 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1624 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1625 /// source is constant so it does not need to be loaded.
1626 /// It returns EVT::Other if the type should be determined using generic
1627 /// target-independent logic.
1629 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1630 unsigned DstAlign, unsigned SrcAlign,
1631 bool IsMemset, bool ZeroMemset,
1633 MachineFunction &MF) const {
1634 const Function *F = MF.getFunction();
1635 if ((!IsMemset || ZeroMemset) &&
1636 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1637 Attribute::NoImplicitFloat)) {
1639 (Subtarget->isUnalignedMemAccessFast() ||
1640 ((DstAlign == 0 || DstAlign >= 16) &&
1641 (SrcAlign == 0 || SrcAlign >= 16)))) {
1643 if (Subtarget->hasInt256())
1645 if (Subtarget->hasFp256())
1648 if (Subtarget->hasSSE2())
1650 if (Subtarget->hasSSE1())
1652 } else if (!MemcpyStrSrc && Size >= 8 &&
1653 !Subtarget->is64Bit() &&
1654 Subtarget->hasSSE2()) {
1655 // Do not use f64 to lower memcpy if source is string constant. It's
1656 // better to use i32 to avoid the loads.
1660 if (Subtarget->is64Bit() && Size >= 8)
1665 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1667 return X86ScalarSSEf32;
1668 else if (VT == MVT::f64)
1669 return X86ScalarSSEf64;
1674 X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
1676 *Fast = Subtarget->isUnalignedMemAccessFast();
1680 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1681 /// current function. The returned value is a member of the
1682 /// MachineJumpTableInfo::JTEntryKind enum.
1683 unsigned X86TargetLowering::getJumpTableEncoding() const {
1684 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1686 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1687 Subtarget->isPICStyleGOT())
1688 return MachineJumpTableInfo::EK_Custom32;
1690 // Otherwise, use the normal jump table encoding heuristics.
1691 return TargetLowering::getJumpTableEncoding();
1695 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1696 const MachineBasicBlock *MBB,
1697 unsigned uid,MCContext &Ctx) const{
1698 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1699 Subtarget->isPICStyleGOT());
1700 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1702 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1703 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1706 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1708 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1709 SelectionDAG &DAG) const {
1710 if (!Subtarget->is64Bit())
1711 // This doesn't have SDLoc associated with it, but is not really the
1712 // same as a Register.
1713 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1717 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1718 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1720 const MCExpr *X86TargetLowering::
1721 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1722 MCContext &Ctx) const {
1723 // X86-64 uses RIP relative addressing based on the jump table label.
1724 if (Subtarget->isPICStyleRIPRel())
1725 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1727 // Otherwise, the reference is relative to the PIC base.
1728 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1731 // FIXME: Why this routine is here? Move to RegInfo!
1732 std::pair<const TargetRegisterClass*, uint8_t>
1733 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1734 const TargetRegisterClass *RRC = 0;
1736 switch (VT.SimpleTy) {
1738 return TargetLowering::findRepresentativeClass(VT);
1739 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1740 RRC = Subtarget->is64Bit() ?
1741 (const TargetRegisterClass*)&X86::GR64RegClass :
1742 (const TargetRegisterClass*)&X86::GR32RegClass;
1745 RRC = &X86::VR64RegClass;
1747 case MVT::f32: case MVT::f64:
1748 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1749 case MVT::v4f32: case MVT::v2f64:
1750 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1752 RRC = &X86::VR128RegClass;
1755 return std::make_pair(RRC, Cost);
1758 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1759 unsigned &Offset) const {
1760 if (!Subtarget->isTargetLinux())
1763 if (Subtarget->is64Bit()) {
1764 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1766 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1778 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1779 unsigned DestAS) const {
1780 assert(SrcAS != DestAS && "Expected different address spaces!");
1782 return SrcAS < 256 && DestAS < 256;
1785 //===----------------------------------------------------------------------===//
1786 // Return Value Calling Convention Implementation
1787 //===----------------------------------------------------------------------===//
1789 #include "X86GenCallingConv.inc"
1792 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1793 MachineFunction &MF, bool isVarArg,
1794 const SmallVectorImpl<ISD::OutputArg> &Outs,
1795 LLVMContext &Context) const {
1796 SmallVector<CCValAssign, 16> RVLocs;
1797 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1799 return CCInfo.CheckReturn(Outs, RetCC_X86);
1802 const uint16_t *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1803 static const uint16_t ScratchRegs[] = { X86::R11, 0 };
1808 X86TargetLowering::LowerReturn(SDValue Chain,
1809 CallingConv::ID CallConv, bool isVarArg,
1810 const SmallVectorImpl<ISD::OutputArg> &Outs,
1811 const SmallVectorImpl<SDValue> &OutVals,
1812 SDLoc dl, SelectionDAG &DAG) const {
1813 MachineFunction &MF = DAG.getMachineFunction();
1814 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1816 SmallVector<CCValAssign, 16> RVLocs;
1817 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1818 RVLocs, *DAG.getContext());
1819 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1822 SmallVector<SDValue, 6> RetOps;
1823 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1824 // Operand #1 = Bytes To Pop
1825 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1828 // Copy the result values into the output registers.
1829 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1830 CCValAssign &VA = RVLocs[i];
1831 assert(VA.isRegLoc() && "Can only return in registers!");
1832 SDValue ValToCopy = OutVals[i];
1833 EVT ValVT = ValToCopy.getValueType();
1835 // Promote values to the appropriate types
1836 if (VA.getLocInfo() == CCValAssign::SExt)
1837 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1838 else if (VA.getLocInfo() == CCValAssign::ZExt)
1839 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1840 else if (VA.getLocInfo() == CCValAssign::AExt)
1841 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1842 else if (VA.getLocInfo() == CCValAssign::BCvt)
1843 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1845 assert(VA.getLocInfo() != CCValAssign::FPExt &&
1846 "Unexpected FP-extend for return value.");
1848 // If this is x86-64, and we disabled SSE, we can't return FP values,
1849 // or SSE or MMX vectors.
1850 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1851 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1852 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1853 report_fatal_error("SSE register return with SSE disabled");
1855 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1856 // llvm-gcc has never done it right and no one has noticed, so this
1857 // should be OK for now.
1858 if (ValVT == MVT::f64 &&
1859 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1860 report_fatal_error("SSE2 register return with SSE2 disabled");
1862 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1863 // the RET instruction and handled by the FP Stackifier.
1864 if (VA.getLocReg() == X86::ST0 ||
1865 VA.getLocReg() == X86::ST1) {
1866 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1867 // change the value to the FP stack register class.
1868 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1869 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1870 RetOps.push_back(ValToCopy);
1871 // Don't emit a copytoreg.
1875 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1876 // which is returned in RAX / RDX.
1877 if (Subtarget->is64Bit()) {
1878 if (ValVT == MVT::x86mmx) {
1879 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1880 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1881 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1883 // If we don't have SSE2 available, convert to v4f32 so the generated
1884 // register is legal.
1885 if (!Subtarget->hasSSE2())
1886 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1891 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1892 Flag = Chain.getValue(1);
1893 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1896 // The x86-64 ABIs require that for returning structs by value we copy
1897 // the sret argument into %rax/%eax (depending on ABI) for the return.
1898 // Win32 requires us to put the sret argument to %eax as well.
1899 // We saved the argument into a virtual register in the entry block,
1900 // so now we copy the value out and into %rax/%eax.
1901 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
1902 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
1903 MachineFunction &MF = DAG.getMachineFunction();
1904 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1905 unsigned Reg = FuncInfo->getSRetReturnReg();
1907 "SRetReturnReg should have been set in LowerFormalArguments().");
1908 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1911 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
1912 X86::RAX : X86::EAX;
1913 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1914 Flag = Chain.getValue(1);
1916 // RAX/EAX now acts like a return value.
1917 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
1920 RetOps[0] = Chain; // Update chain.
1922 // Add the flag if we have it.
1924 RetOps.push_back(Flag);
1926 return DAG.getNode(X86ISD::RET_FLAG, dl,
1927 MVT::Other, &RetOps[0], RetOps.size());
1930 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1931 if (N->getNumValues() != 1)
1933 if (!N->hasNUsesOfValue(1, 0))
1936 SDValue TCChain = Chain;
1937 SDNode *Copy = *N->use_begin();
1938 if (Copy->getOpcode() == ISD::CopyToReg) {
1939 // If the copy has a glue operand, we conservatively assume it isn't safe to
1940 // perform a tail call.
1941 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1943 TCChain = Copy->getOperand(0);
1944 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1947 bool HasRet = false;
1948 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1950 if (UI->getOpcode() != X86ISD::RET_FLAG)
1963 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
1964 ISD::NodeType ExtendKind) const {
1966 // TODO: Is this also valid on 32-bit?
1967 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1968 ReturnMVT = MVT::i8;
1970 ReturnMVT = MVT::i32;
1972 MVT MinVT = getRegisterType(ReturnMVT);
1973 return VT.bitsLT(MinVT) ? MinVT : VT;
1976 /// LowerCallResult - Lower the result values of a call into the
1977 /// appropriate copies out of appropriate physical registers.
1980 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1981 CallingConv::ID CallConv, bool isVarArg,
1982 const SmallVectorImpl<ISD::InputArg> &Ins,
1983 SDLoc dl, SelectionDAG &DAG,
1984 SmallVectorImpl<SDValue> &InVals) const {
1986 // Assign locations to each value returned by this call.
1987 SmallVector<CCValAssign, 16> RVLocs;
1988 bool Is64Bit = Subtarget->is64Bit();
1989 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1990 getTargetMachine(), RVLocs, *DAG.getContext());
1991 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1993 // Copy all of the result registers out of their specified physreg.
1994 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1995 CCValAssign &VA = RVLocs[i];
1996 EVT CopyVT = VA.getValVT();
1998 // If this is x86-64, and we disabled SSE, we can't return FP values
1999 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2000 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2001 report_fatal_error("SSE register return with SSE disabled");
2006 // If this is a call to a function that returns an fp value on the floating
2007 // point stack, we must guarantee the value is popped from the stack, so
2008 // a CopyFromReg is not good enough - the copy instruction may be eliminated
2009 // if the return value is not used. We use the FpPOP_RETVAL instruction
2011 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
2012 // If we prefer to use the value in xmm registers, copy it out as f80 and
2013 // use a truncate to move it from fp stack reg to xmm reg.
2014 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
2015 SDValue Ops[] = { Chain, InFlag };
2016 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
2017 MVT::Other, MVT::Glue, Ops), 1);
2018 Val = Chain.getValue(0);
2020 // Round the f80 to the right size, which also moves it to the appropriate
2022 if (CopyVT != VA.getValVT())
2023 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2024 // This truncation won't change the value.
2025 DAG.getIntPtrConstant(1));
2027 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2028 CopyVT, InFlag).getValue(1);
2029 Val = Chain.getValue(0);
2031 InFlag = Chain.getValue(2);
2032 InVals.push_back(Val);
2038 //===----------------------------------------------------------------------===//
2039 // C & StdCall & Fast Calling Convention implementation
2040 //===----------------------------------------------------------------------===//
2041 // StdCall calling convention seems to be standard for many Windows' API
2042 // routines and around. It differs from C calling convention just a little:
2043 // callee should clean up the stack, not caller. Symbols should be also
2044 // decorated in some fancy way :) It doesn't support any vector arguments.
2045 // For info on fast calling convention see Fast Calling Convention (tail call)
2046 // implementation LowerX86_32FastCCCallTo.
2048 /// CallIsStructReturn - Determines whether a call uses struct return
2050 enum StructReturnType {
2055 static StructReturnType
2056 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2058 return NotStructReturn;
2060 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2061 if (!Flags.isSRet())
2062 return NotStructReturn;
2063 if (Flags.isInReg())
2064 return RegStructReturn;
2065 return StackStructReturn;
2068 /// ArgsAreStructReturn - Determines whether a function uses struct
2069 /// return semantics.
2070 static StructReturnType
2071 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2073 return NotStructReturn;
2075 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2076 if (!Flags.isSRet())
2077 return NotStructReturn;
2078 if (Flags.isInReg())
2079 return RegStructReturn;
2080 return StackStructReturn;
2083 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2084 /// by "Src" to address "Dst" with size and alignment information specified by
2085 /// the specific parameter attribute. The copy will be passed as a byval
2086 /// function parameter.
2088 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2089 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2091 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2093 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2094 /*isVolatile*/false, /*AlwaysInline=*/true,
2095 MachinePointerInfo(), MachinePointerInfo());
2098 /// IsTailCallConvention - Return true if the calling convention is one that
2099 /// supports tail call optimization.
2100 static bool IsTailCallConvention(CallingConv::ID CC) {
2101 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2102 CC == CallingConv::HiPE);
2105 /// \brief Return true if the calling convention is a C calling convention.
2106 static bool IsCCallConvention(CallingConv::ID CC) {
2107 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2108 CC == CallingConv::X86_64_SysV);
2111 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2112 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2116 CallingConv::ID CalleeCC = CS.getCallingConv();
2117 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2123 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2124 /// a tailcall target by changing its ABI.
2125 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2126 bool GuaranteedTailCallOpt) {
2127 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2131 X86TargetLowering::LowerMemArgument(SDValue Chain,
2132 CallingConv::ID CallConv,
2133 const SmallVectorImpl<ISD::InputArg> &Ins,
2134 SDLoc dl, SelectionDAG &DAG,
2135 const CCValAssign &VA,
2136 MachineFrameInfo *MFI,
2138 // Create the nodes corresponding to a load from this parameter slot.
2139 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2140 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
2141 getTargetMachine().Options.GuaranteedTailCallOpt);
2142 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2145 // If value is passed by pointer we have address passed instead of the value
2147 if (VA.getLocInfo() == CCValAssign::Indirect)
2148 ValVT = VA.getLocVT();
2150 ValVT = VA.getValVT();
2152 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2153 // changed with more analysis.
2154 // In case of tail call optimization mark all arguments mutable. Since they
2155 // could be overwritten by lowering of arguments in case of a tail call.
2156 if (Flags.isByVal()) {
2157 unsigned Bytes = Flags.getByValSize();
2158 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2159 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2160 return DAG.getFrameIndex(FI, getPointerTy());
2162 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2163 VA.getLocMemOffset(), isImmutable);
2164 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2165 return DAG.getLoad(ValVT, dl, Chain, FIN,
2166 MachinePointerInfo::getFixedStack(FI),
2167 false, false, false, 0);
2172 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2173 CallingConv::ID CallConv,
2175 const SmallVectorImpl<ISD::InputArg> &Ins,
2178 SmallVectorImpl<SDValue> &InVals)
2180 MachineFunction &MF = DAG.getMachineFunction();
2181 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2183 const Function* Fn = MF.getFunction();
2184 if (Fn->hasExternalLinkage() &&
2185 Subtarget->isTargetCygMing() &&
2186 Fn->getName() == "main")
2187 FuncInfo->setForceFramePointer(true);
2189 MachineFrameInfo *MFI = MF.getFrameInfo();
2190 bool Is64Bit = Subtarget->is64Bit();
2191 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2193 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2194 "Var args not supported with calling convention fastcc, ghc or hipe");
2196 // Assign locations to all of the incoming arguments.
2197 SmallVector<CCValAssign, 16> ArgLocs;
2198 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2199 ArgLocs, *DAG.getContext());
2201 // Allocate shadow area for Win64
2203 CCInfo.AllocateStack(32, 8);
2205 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2207 unsigned LastVal = ~0U;
2209 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2210 CCValAssign &VA = ArgLocs[i];
2211 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2213 assert(VA.getValNo() != LastVal &&
2214 "Don't support value assigned to multiple locs yet");
2216 LastVal = VA.getValNo();
2218 if (VA.isRegLoc()) {
2219 EVT RegVT = VA.getLocVT();
2220 const TargetRegisterClass *RC;
2221 if (RegVT == MVT::i32)
2222 RC = &X86::GR32RegClass;
2223 else if (Is64Bit && RegVT == MVT::i64)
2224 RC = &X86::GR64RegClass;
2225 else if (RegVT == MVT::f32)
2226 RC = &X86::FR32RegClass;
2227 else if (RegVT == MVT::f64)
2228 RC = &X86::FR64RegClass;
2229 else if (RegVT.is512BitVector())
2230 RC = &X86::VR512RegClass;
2231 else if (RegVT.is256BitVector())
2232 RC = &X86::VR256RegClass;
2233 else if (RegVT.is128BitVector())
2234 RC = &X86::VR128RegClass;
2235 else if (RegVT == MVT::x86mmx)
2236 RC = &X86::VR64RegClass;
2237 else if (RegVT == MVT::i1)
2238 RC = &X86::VK1RegClass;
2239 else if (RegVT == MVT::v8i1)
2240 RC = &X86::VK8RegClass;
2241 else if (RegVT == MVT::v16i1)
2242 RC = &X86::VK16RegClass;
2244 llvm_unreachable("Unknown argument type!");
2246 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2247 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2249 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2250 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2252 if (VA.getLocInfo() == CCValAssign::SExt)
2253 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2254 DAG.getValueType(VA.getValVT()));
2255 else if (VA.getLocInfo() == CCValAssign::ZExt)
2256 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2257 DAG.getValueType(VA.getValVT()));
2258 else if (VA.getLocInfo() == CCValAssign::BCvt)
2259 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2261 if (VA.isExtInLoc()) {
2262 // Handle MMX values passed in XMM regs.
2263 if (RegVT.isVector())
2264 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2266 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2269 assert(VA.isMemLoc());
2270 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2273 // If value is passed via pointer - do a load.
2274 if (VA.getLocInfo() == CCValAssign::Indirect)
2275 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2276 MachinePointerInfo(), false, false, false, 0);
2278 InVals.push_back(ArgValue);
2281 // The x86-64 ABIs require that for returning structs by value we copy
2282 // the sret argument into %rax/%eax (depending on ABI) for the return.
2283 // Win32 requires us to put the sret argument to %eax as well.
2284 // Save the argument into a virtual register so that we can access it
2285 // from the return points.
2286 if (MF.getFunction()->hasStructRetAttr() &&
2287 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
2288 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2289 unsigned Reg = FuncInfo->getSRetReturnReg();
2291 MVT PtrTy = getPointerTy();
2292 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2293 FuncInfo->setSRetReturnReg(Reg);
2295 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
2296 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2299 unsigned StackSize = CCInfo.getNextStackOffset();
2300 // Align stack specially for tail calls.
2301 if (FuncIsMadeTailCallSafe(CallConv,
2302 MF.getTarget().Options.GuaranteedTailCallOpt))
2303 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2305 // If the function takes variable number of arguments, make a frame index for
2306 // the start of the first vararg value... for expansion of llvm.va_start.
2308 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2309 CallConv != CallingConv::X86_ThisCall)) {
2310 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2313 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2315 // FIXME: We should really autogenerate these arrays
2316 static const uint16_t GPR64ArgRegsWin64[] = {
2317 X86::RCX, X86::RDX, X86::R8, X86::R9
2319 static const uint16_t GPR64ArgRegs64Bit[] = {
2320 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2322 static const uint16_t XMMArgRegs64Bit[] = {
2323 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2324 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2326 const uint16_t *GPR64ArgRegs;
2327 unsigned NumXMMRegs = 0;
2330 // The XMM registers which might contain var arg parameters are shadowed
2331 // in their paired GPR. So we only need to save the GPR to their home
2333 TotalNumIntRegs = 4;
2334 GPR64ArgRegs = GPR64ArgRegsWin64;
2336 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2337 GPR64ArgRegs = GPR64ArgRegs64Bit;
2339 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2342 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2345 bool NoImplicitFloatOps = Fn->getAttributes().
2346 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2347 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2348 "SSE register cannot be used when SSE is disabled!");
2349 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2350 NoImplicitFloatOps) &&
2351 "SSE register cannot be used when SSE is disabled!");
2352 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2353 !Subtarget->hasSSE1())
2354 // Kernel mode asks for SSE to be disabled, so don't push them
2356 TotalNumXMMRegs = 0;
2359 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
2360 // Get to the caller-allocated home save location. Add 8 to account
2361 // for the return address.
2362 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2363 FuncInfo->setRegSaveFrameIndex(
2364 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2365 // Fixup to set vararg frame on shadow area (4 x i64).
2367 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2369 // For X86-64, if there are vararg parameters that are passed via
2370 // registers, then we must store them to their spots on the stack so
2371 // they may be loaded by deferencing the result of va_next.
2372 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2373 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2374 FuncInfo->setRegSaveFrameIndex(
2375 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2379 // Store the integer parameter registers.
2380 SmallVector<SDValue, 8> MemOps;
2381 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2383 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2384 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2385 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2386 DAG.getIntPtrConstant(Offset));
2387 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2388 &X86::GR64RegClass);
2389 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2391 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2392 MachinePointerInfo::getFixedStack(
2393 FuncInfo->getRegSaveFrameIndex(), Offset),
2395 MemOps.push_back(Store);
2399 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2400 // Now store the XMM (fp + vector) parameter registers.
2401 SmallVector<SDValue, 11> SaveXMMOps;
2402 SaveXMMOps.push_back(Chain);
2404 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2405 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2406 SaveXMMOps.push_back(ALVal);
2408 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2409 FuncInfo->getRegSaveFrameIndex()));
2410 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2411 FuncInfo->getVarArgsFPOffset()));
2413 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2414 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2415 &X86::VR128RegClass);
2416 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2417 SaveXMMOps.push_back(Val);
2419 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2421 &SaveXMMOps[0], SaveXMMOps.size()));
2424 if (!MemOps.empty())
2425 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2426 &MemOps[0], MemOps.size());
2430 // Some CCs need callee pop.
2431 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2432 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2433 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2435 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2436 // If this is an sret function, the return should pop the hidden pointer.
2437 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2438 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2439 argsAreStructReturn(Ins) == StackStructReturn)
2440 FuncInfo->setBytesToPopOnReturn(4);
2444 // RegSaveFrameIndex is X86-64 only.
2445 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2446 if (CallConv == CallingConv::X86_FastCall ||
2447 CallConv == CallingConv::X86_ThisCall)
2448 // fastcc functions can't have varargs.
2449 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2452 FuncInfo->setArgumentStackSize(StackSize);
2458 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2459 SDValue StackPtr, SDValue Arg,
2460 SDLoc dl, SelectionDAG &DAG,
2461 const CCValAssign &VA,
2462 ISD::ArgFlagsTy Flags) const {
2463 unsigned LocMemOffset = VA.getLocMemOffset();
2464 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2465 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2466 if (Flags.isByVal())
2467 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2469 return DAG.getStore(Chain, dl, Arg, PtrOff,
2470 MachinePointerInfo::getStack(LocMemOffset),
2474 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2475 /// optimization is performed and it is required.
2477 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2478 SDValue &OutRetAddr, SDValue Chain,
2479 bool IsTailCall, bool Is64Bit,
2480 int FPDiff, SDLoc dl) const {
2481 // Adjust the Return address stack slot.
2482 EVT VT = getPointerTy();
2483 OutRetAddr = getReturnAddressFrameIndex(DAG);
2485 // Load the "old" Return address.
2486 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2487 false, false, false, 0);
2488 return SDValue(OutRetAddr.getNode(), 1);
2491 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2492 /// optimization is performed and it is required (FPDiff!=0).
2494 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2495 SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT,
2496 unsigned SlotSize, int FPDiff, SDLoc dl) {
2497 // Store the return address to the appropriate stack slot.
2498 if (!FPDiff) return Chain;
2499 // Calculate the new stack slot for the return address.
2500 int NewReturnAddrFI =
2501 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2503 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2504 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2505 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2511 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2512 SmallVectorImpl<SDValue> &InVals) const {
2513 SelectionDAG &DAG = CLI.DAG;
2515 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2516 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2517 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2518 SDValue Chain = CLI.Chain;
2519 SDValue Callee = CLI.Callee;
2520 CallingConv::ID CallConv = CLI.CallConv;
2521 bool &isTailCall = CLI.IsTailCall;
2522 bool isVarArg = CLI.IsVarArg;
2524 MachineFunction &MF = DAG.getMachineFunction();
2525 bool Is64Bit = Subtarget->is64Bit();
2526 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2527 StructReturnType SR = callIsStructReturn(Outs);
2528 bool IsSibcall = false;
2530 if (MF.getTarget().Options.DisableTailCalls)
2534 // Check if it's really possible to do a tail call.
2535 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2536 isVarArg, SR != NotStructReturn,
2537 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2538 Outs, OutVals, Ins, DAG);
2540 // Sibcalls are automatically detected tailcalls which do not require
2542 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2549 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2550 "Var args not supported with calling convention fastcc, ghc or hipe");
2552 // Analyze operands of the call, assigning locations to each operand.
2553 SmallVector<CCValAssign, 16> ArgLocs;
2554 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2555 ArgLocs, *DAG.getContext());
2557 // Allocate shadow area for Win64
2559 CCInfo.AllocateStack(32, 8);
2561 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2563 // Get a count of how many bytes are to be pushed on the stack.
2564 unsigned NumBytes = CCInfo.getNextStackOffset();
2566 // This is a sibcall. The memory operands are available in caller's
2567 // own caller's stack.
2569 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2570 IsTailCallConvention(CallConv))
2571 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2574 if (isTailCall && !IsSibcall) {
2575 // Lower arguments at fp - stackoffset + fpdiff.
2576 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2577 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2579 FPDiff = NumBytesCallerPushed - NumBytes;
2581 // Set the delta of movement of the returnaddr stackslot.
2582 // But only set if delta is greater than previous delta.
2583 if (FPDiff < X86Info->getTCReturnAddrDelta())
2584 X86Info->setTCReturnAddrDelta(FPDiff);
2588 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
2591 SDValue RetAddrFrIdx;
2592 // Load return address for tail calls.
2593 if (isTailCall && FPDiff)
2594 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2595 Is64Bit, FPDiff, dl);
2597 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2598 SmallVector<SDValue, 8> MemOpChains;
2601 // Walk the register/memloc assignments, inserting copies/loads. In the case
2602 // of tail call optimization arguments are handle later.
2603 const X86RegisterInfo *RegInfo =
2604 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
2605 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2606 CCValAssign &VA = ArgLocs[i];
2607 EVT RegVT = VA.getLocVT();
2608 SDValue Arg = OutVals[i];
2609 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2610 bool isByVal = Flags.isByVal();
2612 // Promote the value if needed.
2613 switch (VA.getLocInfo()) {
2614 default: llvm_unreachable("Unknown loc info!");
2615 case CCValAssign::Full: break;
2616 case CCValAssign::SExt:
2617 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2619 case CCValAssign::ZExt:
2620 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2622 case CCValAssign::AExt:
2623 if (RegVT.is128BitVector()) {
2624 // Special case: passing MMX values in XMM registers.
2625 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2626 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2627 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2629 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2631 case CCValAssign::BCvt:
2632 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2634 case CCValAssign::Indirect: {
2635 // Store the argument.
2636 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2637 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2638 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2639 MachinePointerInfo::getFixedStack(FI),
2646 if (VA.isRegLoc()) {
2647 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2648 if (isVarArg && IsWin64) {
2649 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2650 // shadow reg if callee is a varargs function.
2651 unsigned ShadowReg = 0;
2652 switch (VA.getLocReg()) {
2653 case X86::XMM0: ShadowReg = X86::RCX; break;
2654 case X86::XMM1: ShadowReg = X86::RDX; break;
2655 case X86::XMM2: ShadowReg = X86::R8; break;
2656 case X86::XMM3: ShadowReg = X86::R9; break;
2659 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2661 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2662 assert(VA.isMemLoc());
2663 if (StackPtr.getNode() == 0)
2664 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2666 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2667 dl, DAG, VA, Flags));
2671 if (!MemOpChains.empty())
2672 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2673 &MemOpChains[0], MemOpChains.size());
2675 if (Subtarget->isPICStyleGOT()) {
2676 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2679 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2680 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2682 // If we are tail calling and generating PIC/GOT style code load the
2683 // address of the callee into ECX. The value in ecx is used as target of
2684 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2685 // for tail calls on PIC/GOT architectures. Normally we would just put the
2686 // address of GOT into ebx and then call target@PLT. But for tail calls
2687 // ebx would be restored (since ebx is callee saved) before jumping to the
2690 // Note: The actual moving to ECX is done further down.
2691 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2692 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2693 !G->getGlobal()->hasProtectedVisibility())
2694 Callee = LowerGlobalAddress(Callee, DAG);
2695 else if (isa<ExternalSymbolSDNode>(Callee))
2696 Callee = LowerExternalSymbol(Callee, DAG);
2700 if (Is64Bit && isVarArg && !IsWin64) {
2701 // From AMD64 ABI document:
2702 // For calls that may call functions that use varargs or stdargs
2703 // (prototype-less calls or calls to functions containing ellipsis (...) in
2704 // the declaration) %al is used as hidden argument to specify the number
2705 // of SSE registers used. The contents of %al do not need to match exactly
2706 // the number of registers, but must be an ubound on the number of SSE
2707 // registers used and is in the range 0 - 8 inclusive.
2709 // Count the number of XMM registers allocated.
2710 static const uint16_t XMMArgRegs[] = {
2711 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2712 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2714 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2715 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2716 && "SSE registers cannot be used when SSE is disabled");
2718 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2719 DAG.getConstant(NumXMMRegs, MVT::i8)));
2722 // For tail calls lower the arguments to the 'real' stack slot.
2724 // Force all the incoming stack arguments to be loaded from the stack
2725 // before any new outgoing arguments are stored to the stack, because the
2726 // outgoing stack slots may alias the incoming argument stack slots, and
2727 // the alias isn't otherwise explicit. This is slightly more conservative
2728 // than necessary, because it means that each store effectively depends
2729 // on every argument instead of just those arguments it would clobber.
2730 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2732 SmallVector<SDValue, 8> MemOpChains2;
2735 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2736 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2737 CCValAssign &VA = ArgLocs[i];
2740 assert(VA.isMemLoc());
2741 SDValue Arg = OutVals[i];
2742 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2743 // Create frame index.
2744 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2745 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2746 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2747 FIN = DAG.getFrameIndex(FI, getPointerTy());
2749 if (Flags.isByVal()) {
2750 // Copy relative to framepointer.
2751 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2752 if (StackPtr.getNode() == 0)
2753 StackPtr = DAG.getCopyFromReg(Chain, dl,
2754 RegInfo->getStackRegister(),
2756 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2758 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2762 // Store relative to framepointer.
2763 MemOpChains2.push_back(
2764 DAG.getStore(ArgChain, dl, Arg, FIN,
2765 MachinePointerInfo::getFixedStack(FI),
2771 if (!MemOpChains2.empty())
2772 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2773 &MemOpChains2[0], MemOpChains2.size());
2775 // Store the return address to the appropriate stack slot.
2776 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2777 getPointerTy(), RegInfo->getSlotSize(),
2781 // Build a sequence of copy-to-reg nodes chained together with token chain
2782 // and flag operands which copy the outgoing args into registers.
2784 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2785 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2786 RegsToPass[i].second, InFlag);
2787 InFlag = Chain.getValue(1);
2790 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2791 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2792 // In the 64-bit large code model, we have to make all calls
2793 // through a register, since the call instruction's 32-bit
2794 // pc-relative offset may not be large enough to hold the whole
2796 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2797 // If the callee is a GlobalAddress node (quite common, every direct call
2798 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2801 // We should use extra load for direct calls to dllimported functions in
2803 const GlobalValue *GV = G->getGlobal();
2804 if (!GV->hasDLLImportStorageClass()) {
2805 unsigned char OpFlags = 0;
2806 bool ExtraLoad = false;
2807 unsigned WrapperKind = ISD::DELETED_NODE;
2809 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2810 // external symbols most go through the PLT in PIC mode. If the symbol
2811 // has hidden or protected visibility, or if it is static or local, then
2812 // we don't need to use the PLT - we can directly call it.
2813 if (Subtarget->isTargetELF() &&
2814 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2815 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2816 OpFlags = X86II::MO_PLT;
2817 } else if (Subtarget->isPICStyleStubAny() &&
2818 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2819 (!Subtarget->getTargetTriple().isMacOSX() ||
2820 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2821 // PC-relative references to external symbols should go through $stub,
2822 // unless we're building with the leopard linker or later, which
2823 // automatically synthesizes these stubs.
2824 OpFlags = X86II::MO_DARWIN_STUB;
2825 } else if (Subtarget->isPICStyleRIPRel() &&
2826 isa<Function>(GV) &&
2827 cast<Function>(GV)->getAttributes().
2828 hasAttribute(AttributeSet::FunctionIndex,
2829 Attribute::NonLazyBind)) {
2830 // If the function is marked as non-lazy, generate an indirect call
2831 // which loads from the GOT directly. This avoids runtime overhead
2832 // at the cost of eager binding (and one extra byte of encoding).
2833 OpFlags = X86II::MO_GOTPCREL;
2834 WrapperKind = X86ISD::WrapperRIP;
2838 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2839 G->getOffset(), OpFlags);
2841 // Add a wrapper if needed.
2842 if (WrapperKind != ISD::DELETED_NODE)
2843 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2844 // Add extra indirection if needed.
2846 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2847 MachinePointerInfo::getGOT(),
2848 false, false, false, 0);
2850 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2851 unsigned char OpFlags = 0;
2853 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2854 // external symbols should go through the PLT.
2855 if (Subtarget->isTargetELF() &&
2856 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2857 OpFlags = X86II::MO_PLT;
2858 } else if (Subtarget->isPICStyleStubAny() &&
2859 (!Subtarget->getTargetTriple().isMacOSX() ||
2860 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2861 // PC-relative references to external symbols should go through $stub,
2862 // unless we're building with the leopard linker or later, which
2863 // automatically synthesizes these stubs.
2864 OpFlags = X86II::MO_DARWIN_STUB;
2867 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2871 // Returns a chain & a flag for retval copy to use.
2872 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2873 SmallVector<SDValue, 8> Ops;
2875 if (!IsSibcall && isTailCall) {
2876 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2877 DAG.getIntPtrConstant(0, true), InFlag, dl);
2878 InFlag = Chain.getValue(1);
2881 Ops.push_back(Chain);
2882 Ops.push_back(Callee);
2885 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2887 // Add argument registers to the end of the list so that they are known live
2889 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2890 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2891 RegsToPass[i].second.getValueType()));
2893 // Add a register mask operand representing the call-preserved registers.
2894 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2895 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2896 assert(Mask && "Missing call preserved mask for calling convention");
2897 Ops.push_back(DAG.getRegisterMask(Mask));
2899 if (InFlag.getNode())
2900 Ops.push_back(InFlag);
2904 //// If this is the first return lowered for this function, add the regs
2905 //// to the liveout set for the function.
2906 // This isn't right, although it's probably harmless on x86; liveouts
2907 // should be computed from returns not tail calls. Consider a void
2908 // function making a tail call to a function returning int.
2909 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
2912 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2913 InFlag = Chain.getValue(1);
2915 // Create the CALLSEQ_END node.
2916 unsigned NumBytesForCalleeToPush;
2917 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2918 getTargetMachine().Options.GuaranteedTailCallOpt))
2919 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2920 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2921 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2922 SR == StackStructReturn)
2923 // If this is a call to a struct-return function, the callee
2924 // pops the hidden struct pointer, so we have to push it back.
2925 // This is common for Darwin/X86, Linux & Mingw32 targets.
2926 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2927 NumBytesForCalleeToPush = 4;
2929 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2931 // Returns a flag for retval copy to use.
2933 Chain = DAG.getCALLSEQ_END(Chain,
2934 DAG.getIntPtrConstant(NumBytes, true),
2935 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2938 InFlag = Chain.getValue(1);
2941 // Handle result values, copying them out of physregs into vregs that we
2943 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2944 Ins, dl, DAG, InVals);
2947 //===----------------------------------------------------------------------===//
2948 // Fast Calling Convention (tail call) implementation
2949 //===----------------------------------------------------------------------===//
2951 // Like std call, callee cleans arguments, convention except that ECX is
2952 // reserved for storing the tail called function address. Only 2 registers are
2953 // free for argument passing (inreg). Tail call optimization is performed
2955 // * tailcallopt is enabled
2956 // * caller/callee are fastcc
2957 // On X86_64 architecture with GOT-style position independent code only local
2958 // (within module) calls are supported at the moment.
2959 // To keep the stack aligned according to platform abi the function
2960 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2961 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2962 // If a tail called function callee has more arguments than the caller the
2963 // caller needs to make sure that there is room to move the RETADDR to. This is
2964 // achieved by reserving an area the size of the argument delta right after the
2965 // original REtADDR, but before the saved framepointer or the spilled registers
2966 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2978 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2979 /// for a 16 byte align requirement.
2981 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2982 SelectionDAG& DAG) const {
2983 MachineFunction &MF = DAG.getMachineFunction();
2984 const TargetMachine &TM = MF.getTarget();
2985 const X86RegisterInfo *RegInfo =
2986 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
2987 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2988 unsigned StackAlignment = TFI.getStackAlignment();
2989 uint64_t AlignMask = StackAlignment - 1;
2990 int64_t Offset = StackSize;
2991 unsigned SlotSize = RegInfo->getSlotSize();
2992 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2993 // Number smaller than 12 so just add the difference.
2994 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2996 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2997 Offset = ((~AlignMask) & Offset) + StackAlignment +
2998 (StackAlignment-SlotSize);
3003 /// MatchingStackOffset - Return true if the given stack call argument is
3004 /// already available in the same position (relatively) of the caller's
3005 /// incoming argument stack.
3007 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3008 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3009 const X86InstrInfo *TII) {
3010 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3012 if (Arg.getOpcode() == ISD::CopyFromReg) {
3013 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3014 if (!TargetRegisterInfo::isVirtualRegister(VR))
3016 MachineInstr *Def = MRI->getVRegDef(VR);
3019 if (!Flags.isByVal()) {
3020 if (!TII->isLoadFromStackSlot(Def, FI))
3023 unsigned Opcode = Def->getOpcode();
3024 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3025 Def->getOperand(1).isFI()) {
3026 FI = Def->getOperand(1).getIndex();
3027 Bytes = Flags.getByValSize();
3031 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3032 if (Flags.isByVal())
3033 // ByVal argument is passed in as a pointer but it's now being
3034 // dereferenced. e.g.
3035 // define @foo(%struct.X* %A) {
3036 // tail call @bar(%struct.X* byval %A)
3039 SDValue Ptr = Ld->getBasePtr();
3040 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3043 FI = FINode->getIndex();
3044 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3045 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3046 FI = FINode->getIndex();
3047 Bytes = Flags.getByValSize();
3051 assert(FI != INT_MAX);
3052 if (!MFI->isFixedObjectIndex(FI))
3054 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3057 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3058 /// for tail call optimization. Targets which want to do tail call
3059 /// optimization should implement this function.
3061 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3062 CallingConv::ID CalleeCC,
3064 bool isCalleeStructRet,
3065 bool isCallerStructRet,
3067 const SmallVectorImpl<ISD::OutputArg> &Outs,
3068 const SmallVectorImpl<SDValue> &OutVals,
3069 const SmallVectorImpl<ISD::InputArg> &Ins,
3070 SelectionDAG &DAG) const {
3071 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3074 // If -tailcallopt is specified, make fastcc functions tail-callable.
3075 const MachineFunction &MF = DAG.getMachineFunction();
3076 const Function *CallerF = MF.getFunction();
3078 // If the function return type is x86_fp80 and the callee return type is not,
3079 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3080 // perform a tailcall optimization here.
3081 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3084 CallingConv::ID CallerCC = CallerF->getCallingConv();
3085 bool CCMatch = CallerCC == CalleeCC;
3086 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3087 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3089 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
3090 if (IsTailCallConvention(CalleeCC) && CCMatch)
3095 // Look for obvious safe cases to perform tail call optimization that do not
3096 // require ABI changes. This is what gcc calls sibcall.
3098 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3099 // emit a special epilogue.
3100 const X86RegisterInfo *RegInfo =
3101 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3102 if (RegInfo->needsStackRealignment(MF))
3105 // Also avoid sibcall optimization if either caller or callee uses struct
3106 // return semantics.
3107 if (isCalleeStructRet || isCallerStructRet)
3110 // An stdcall/thiscall caller is expected to clean up its arguments; the
3111 // callee isn't going to do that.
3112 // FIXME: this is more restrictive than needed. We could produce a tailcall
3113 // when the stack adjustment matches. For example, with a thiscall that takes
3114 // only one argument.
3115 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3116 CallerCC == CallingConv::X86_ThisCall))
3119 // Do not sibcall optimize vararg calls unless all arguments are passed via
3121 if (isVarArg && !Outs.empty()) {
3123 // Optimizing for varargs on Win64 is unlikely to be safe without
3124 // additional testing.
3125 if (IsCalleeWin64 || IsCallerWin64)
3128 SmallVector<CCValAssign, 16> ArgLocs;
3129 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3130 getTargetMachine(), ArgLocs, *DAG.getContext());
3132 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3133 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3134 if (!ArgLocs[i].isRegLoc())
3138 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3139 // stack. Therefore, if it's not used by the call it is not safe to optimize
3140 // this into a sibcall.
3141 bool Unused = false;
3142 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3149 SmallVector<CCValAssign, 16> RVLocs;
3150 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
3151 getTargetMachine(), RVLocs, *DAG.getContext());
3152 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3153 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3154 CCValAssign &VA = RVLocs[i];
3155 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
3160 // If the calling conventions do not match, then we'd better make sure the
3161 // results are returned in the same way as what the caller expects.
3163 SmallVector<CCValAssign, 16> RVLocs1;
3164 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
3165 getTargetMachine(), RVLocs1, *DAG.getContext());
3166 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3168 SmallVector<CCValAssign, 16> RVLocs2;
3169 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
3170 getTargetMachine(), RVLocs2, *DAG.getContext());
3171 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3173 if (RVLocs1.size() != RVLocs2.size())
3175 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3176 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3178 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3180 if (RVLocs1[i].isRegLoc()) {
3181 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3184 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3190 // If the callee takes no arguments then go on to check the results of the
3192 if (!Outs.empty()) {
3193 // Check if stack adjustment is needed. For now, do not do this if any
3194 // argument is passed on the stack.
3195 SmallVector<CCValAssign, 16> ArgLocs;
3196 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3197 getTargetMachine(), ArgLocs, *DAG.getContext());
3199 // Allocate shadow area for Win64
3201 CCInfo.AllocateStack(32, 8);
3203 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3204 if (CCInfo.getNextStackOffset()) {
3205 MachineFunction &MF = DAG.getMachineFunction();
3206 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3209 // Check if the arguments are already laid out in the right way as
3210 // the caller's fixed stack objects.
3211 MachineFrameInfo *MFI = MF.getFrameInfo();
3212 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3213 const X86InstrInfo *TII =
3214 ((const X86TargetMachine&)getTargetMachine()).getInstrInfo();
3215 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3216 CCValAssign &VA = ArgLocs[i];
3217 SDValue Arg = OutVals[i];
3218 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3219 if (VA.getLocInfo() == CCValAssign::Indirect)
3221 if (!VA.isRegLoc()) {
3222 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3229 // If the tailcall address may be in a register, then make sure it's
3230 // possible to register allocate for it. In 32-bit, the call address can
3231 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3232 // callee-saved registers are restored. These happen to be the same
3233 // registers used to pass 'inreg' arguments so watch out for those.
3234 if (!Subtarget->is64Bit() &&
3235 ((!isa<GlobalAddressSDNode>(Callee) &&
3236 !isa<ExternalSymbolSDNode>(Callee)) ||
3237 getTargetMachine().getRelocationModel() == Reloc::PIC_)) {
3238 unsigned NumInRegs = 0;
3239 // In PIC we need an extra register to formulate the address computation
3241 unsigned MaxInRegs =
3242 (getTargetMachine().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3244 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3245 CCValAssign &VA = ArgLocs[i];
3248 unsigned Reg = VA.getLocReg();
3251 case X86::EAX: case X86::EDX: case X86::ECX:
3252 if (++NumInRegs == MaxInRegs)
3264 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3265 const TargetLibraryInfo *libInfo) const {
3266 return X86::createFastISel(funcInfo, libInfo);
3269 //===----------------------------------------------------------------------===//
3270 // Other Lowering Hooks
3271 //===----------------------------------------------------------------------===//
3273 static bool MayFoldLoad(SDValue Op) {
3274 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3277 static bool MayFoldIntoStore(SDValue Op) {
3278 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3281 static bool isTargetShuffle(unsigned Opcode) {
3283 default: return false;
3284 case X86ISD::PSHUFD:
3285 case X86ISD::PSHUFHW:
3286 case X86ISD::PSHUFLW:
3288 case X86ISD::PALIGNR:
3289 case X86ISD::MOVLHPS:
3290 case X86ISD::MOVLHPD:
3291 case X86ISD::MOVHLPS:
3292 case X86ISD::MOVLPS:
3293 case X86ISD::MOVLPD:
3294 case X86ISD::MOVSHDUP:
3295 case X86ISD::MOVSLDUP:
3296 case X86ISD::MOVDDUP:
3299 case X86ISD::UNPCKL:
3300 case X86ISD::UNPCKH:
3301 case X86ISD::VPERMILP:
3302 case X86ISD::VPERM2X128:
3303 case X86ISD::VPERMI:
3308 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3309 SDValue V1, SelectionDAG &DAG) {
3311 default: llvm_unreachable("Unknown x86 shuffle node");
3312 case X86ISD::MOVSHDUP:
3313 case X86ISD::MOVSLDUP:
3314 case X86ISD::MOVDDUP:
3315 return DAG.getNode(Opc, dl, VT, V1);
3319 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3320 SDValue V1, unsigned TargetMask,
3321 SelectionDAG &DAG) {
3323 default: llvm_unreachable("Unknown x86 shuffle node");
3324 case X86ISD::PSHUFD:
3325 case X86ISD::PSHUFHW:
3326 case X86ISD::PSHUFLW:
3327 case X86ISD::VPERMILP:
3328 case X86ISD::VPERMI:
3329 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3333 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3334 SDValue V1, SDValue V2, unsigned TargetMask,
3335 SelectionDAG &DAG) {
3337 default: llvm_unreachable("Unknown x86 shuffle node");
3338 case X86ISD::PALIGNR:
3340 case X86ISD::VPERM2X128:
3341 return DAG.getNode(Opc, dl, VT, V1, V2,
3342 DAG.getConstant(TargetMask, MVT::i8));
3346 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3347 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3349 default: llvm_unreachable("Unknown x86 shuffle node");
3350 case X86ISD::MOVLHPS:
3351 case X86ISD::MOVLHPD:
3352 case X86ISD::MOVHLPS:
3353 case X86ISD::MOVLPS:
3354 case X86ISD::MOVLPD:
3357 case X86ISD::UNPCKL:
3358 case X86ISD::UNPCKH:
3359 return DAG.getNode(Opc, dl, VT, V1, V2);
3363 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3364 MachineFunction &MF = DAG.getMachineFunction();
3365 const X86RegisterInfo *RegInfo =
3366 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3367 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3368 int ReturnAddrIndex = FuncInfo->getRAIndex();
3370 if (ReturnAddrIndex == 0) {
3371 // Set up a frame object for the return address.
3372 unsigned SlotSize = RegInfo->getSlotSize();
3373 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3376 FuncInfo->setRAIndex(ReturnAddrIndex);
3379 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3382 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3383 bool hasSymbolicDisplacement) {
3384 // Offset should fit into 32 bit immediate field.
3385 if (!isInt<32>(Offset))
3388 // If we don't have a symbolic displacement - we don't have any extra
3390 if (!hasSymbolicDisplacement)
3393 // FIXME: Some tweaks might be needed for medium code model.
3394 if (M != CodeModel::Small && M != CodeModel::Kernel)
3397 // For small code model we assume that latest object is 16MB before end of 31
3398 // bits boundary. We may also accept pretty large negative constants knowing
3399 // that all objects are in the positive half of address space.
3400 if (M == CodeModel::Small && Offset < 16*1024*1024)
3403 // For kernel code model we know that all object resist in the negative half
3404 // of 32bits address space. We may not accept negative offsets, since they may
3405 // be just off and we may accept pretty large positive ones.
3406 if (M == CodeModel::Kernel && Offset > 0)
3412 /// isCalleePop - Determines whether the callee is required to pop its
3413 /// own arguments. Callee pop is necessary to support tail calls.
3414 bool X86::isCalleePop(CallingConv::ID CallingConv,
3415 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3419 switch (CallingConv) {
3422 case CallingConv::X86_StdCall:
3424 case CallingConv::X86_FastCall:
3426 case CallingConv::X86_ThisCall:
3428 case CallingConv::Fast:
3430 case CallingConv::GHC:
3432 case CallingConv::HiPE:
3437 /// \brief Return true if the condition is an unsigned comparison operation.
3438 static bool isX86CCUnsigned(unsigned X86CC) {
3440 default: llvm_unreachable("Invalid integer condition!");
3441 case X86::COND_E: return true;
3442 case X86::COND_G: return false;
3443 case X86::COND_GE: return false;
3444 case X86::COND_L: return false;
3445 case X86::COND_LE: return false;
3446 case X86::COND_NE: return true;
3447 case X86::COND_B: return true;
3448 case X86::COND_A: return true;
3449 case X86::COND_BE: return true;
3450 case X86::COND_AE: return true;
3452 llvm_unreachable("covered switch fell through?!");
3455 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3456 /// specific condition code, returning the condition code and the LHS/RHS of the
3457 /// comparison to make.
3458 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3459 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3461 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3462 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3463 // X > -1 -> X == 0, jump !sign.
3464 RHS = DAG.getConstant(0, RHS.getValueType());
3465 return X86::COND_NS;
3467 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3468 // X < 0 -> X == 0, jump on sign.
3471 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3473 RHS = DAG.getConstant(0, RHS.getValueType());
3474 return X86::COND_LE;
3478 switch (SetCCOpcode) {
3479 default: llvm_unreachable("Invalid integer condition!");
3480 case ISD::SETEQ: return X86::COND_E;
3481 case ISD::SETGT: return X86::COND_G;
3482 case ISD::SETGE: return X86::COND_GE;
3483 case ISD::SETLT: return X86::COND_L;
3484 case ISD::SETLE: return X86::COND_LE;
3485 case ISD::SETNE: return X86::COND_NE;
3486 case ISD::SETULT: return X86::COND_B;
3487 case ISD::SETUGT: return X86::COND_A;
3488 case ISD::SETULE: return X86::COND_BE;
3489 case ISD::SETUGE: return X86::COND_AE;
3493 // First determine if it is required or is profitable to flip the operands.
3495 // If LHS is a foldable load, but RHS is not, flip the condition.
3496 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3497 !ISD::isNON_EXTLoad(RHS.getNode())) {
3498 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3499 std::swap(LHS, RHS);
3502 switch (SetCCOpcode) {
3508 std::swap(LHS, RHS);
3512 // On a floating point condition, the flags are set as follows:
3514 // 0 | 0 | 0 | X > Y
3515 // 0 | 0 | 1 | X < Y
3516 // 1 | 0 | 0 | X == Y
3517 // 1 | 1 | 1 | unordered
3518 switch (SetCCOpcode) {
3519 default: llvm_unreachable("Condcode should be pre-legalized away");
3521 case ISD::SETEQ: return X86::COND_E;
3522 case ISD::SETOLT: // flipped
3524 case ISD::SETGT: return X86::COND_A;
3525 case ISD::SETOLE: // flipped
3527 case ISD::SETGE: return X86::COND_AE;
3528 case ISD::SETUGT: // flipped
3530 case ISD::SETLT: return X86::COND_B;
3531 case ISD::SETUGE: // flipped
3533 case ISD::SETLE: return X86::COND_BE;
3535 case ISD::SETNE: return X86::COND_NE;
3536 case ISD::SETUO: return X86::COND_P;
3537 case ISD::SETO: return X86::COND_NP;
3539 case ISD::SETUNE: return X86::COND_INVALID;
3543 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3544 /// code. Current x86 isa includes the following FP cmov instructions:
3545 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3546 static bool hasFPCMov(unsigned X86CC) {
3562 /// isFPImmLegal - Returns true if the target can instruction select the
3563 /// specified FP immediate natively. If false, the legalizer will
3564 /// materialize the FP immediate as a load from a constant pool.
3565 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3566 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3567 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3573 /// \brief Returns true if it is beneficial to convert a load of a constant
3574 /// to just the constant itself.
3575 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3577 assert(Ty->isIntegerTy());
3579 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3580 if (BitSize == 0 || BitSize > 64)
3585 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3586 /// the specified range (L, H].
3587 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3588 return (Val < 0) || (Val >= Low && Val < Hi);
3591 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3592 /// specified value.
3593 static bool isUndefOrEqual(int Val, int CmpVal) {
3594 return (Val < 0 || Val == CmpVal);
3597 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3598 /// from position Pos and ending in Pos+Size, falls within the specified
3599 /// sequential range (L, L+Pos]. or is undef.
3600 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3601 unsigned Pos, unsigned Size, int Low) {
3602 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3603 if (!isUndefOrEqual(Mask[i], Low))
3608 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3609 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3610 /// the second operand.
3611 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3612 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3613 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3614 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3615 return (Mask[0] < 2 && Mask[1] < 2);
3619 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3620 /// is suitable for input to PSHUFHW.
3621 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3622 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3625 // Lower quadword copied in order or undef.
3626 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3629 // Upper quadword shuffled.
3630 for (unsigned i = 4; i != 8; ++i)
3631 if (!isUndefOrInRange(Mask[i], 4, 8))
3634 if (VT == MVT::v16i16) {
3635 // Lower quadword copied in order or undef.
3636 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3639 // Upper quadword shuffled.
3640 for (unsigned i = 12; i != 16; ++i)
3641 if (!isUndefOrInRange(Mask[i], 12, 16))
3648 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3649 /// is suitable for input to PSHUFLW.
3650 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3651 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3654 // Upper quadword copied in order.
3655 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3658 // Lower quadword shuffled.
3659 for (unsigned i = 0; i != 4; ++i)
3660 if (!isUndefOrInRange(Mask[i], 0, 4))
3663 if (VT == MVT::v16i16) {
3664 // Upper quadword copied in order.
3665 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3668 // Lower quadword shuffled.
3669 for (unsigned i = 8; i != 12; ++i)
3670 if (!isUndefOrInRange(Mask[i], 8, 12))
3677 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3678 /// is suitable for input to PALIGNR.
3679 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
3680 const X86Subtarget *Subtarget) {
3681 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3682 (VT.is256BitVector() && !Subtarget->hasInt256()))
3685 unsigned NumElts = VT.getVectorNumElements();
3686 unsigned NumLanes = VT.is512BitVector() ? 1: VT.getSizeInBits()/128;
3687 unsigned NumLaneElts = NumElts/NumLanes;
3689 // Do not handle 64-bit element shuffles with palignr.
3690 if (NumLaneElts == 2)
3693 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3695 for (i = 0; i != NumLaneElts; ++i) {
3700 // Lane is all undef, go to next lane
3701 if (i == NumLaneElts)
3704 int Start = Mask[i+l];
3706 // Make sure its in this lane in one of the sources
3707 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3708 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3711 // If not lane 0, then we must match lane 0
3712 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3715 // Correct second source to be contiguous with first source
3716 if (Start >= (int)NumElts)
3717 Start -= NumElts - NumLaneElts;
3719 // Make sure we're shifting in the right direction.
3720 if (Start <= (int)(i+l))
3725 // Check the rest of the elements to see if they are consecutive.
3726 for (++i; i != NumLaneElts; ++i) {
3727 int Idx = Mask[i+l];
3729 // Make sure its in this lane
3730 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3731 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3734 // If not lane 0, then we must match lane 0
3735 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3738 if (Idx >= (int)NumElts)
3739 Idx -= NumElts - NumLaneElts;
3741 if (!isUndefOrEqual(Idx, Start+i))
3750 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3751 /// the two vector operands have swapped position.
3752 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3753 unsigned NumElems) {
3754 for (unsigned i = 0; i != NumElems; ++i) {
3758 else if (idx < (int)NumElems)
3759 Mask[i] = idx + NumElems;
3761 Mask[i] = idx - NumElems;
3765 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3766 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3767 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3768 /// reverse of what x86 shuffles want.
3769 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
3771 unsigned NumElems = VT.getVectorNumElements();
3772 unsigned NumLanes = VT.getSizeInBits()/128;
3773 unsigned NumLaneElems = NumElems/NumLanes;
3775 if (NumLaneElems != 2 && NumLaneElems != 4)
3778 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3779 bool symetricMaskRequired =
3780 (VT.getSizeInBits() >= 256) && (EltSize == 32);
3782 // VSHUFPSY divides the resulting vector into 4 chunks.
3783 // The sources are also splitted into 4 chunks, and each destination
3784 // chunk must come from a different source chunk.
3786 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3787 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3789 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3790 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3792 // VSHUFPDY divides the resulting vector into 4 chunks.
3793 // The sources are also splitted into 4 chunks, and each destination
3794 // chunk must come from a different source chunk.
3796 // SRC1 => X3 X2 X1 X0
3797 // SRC2 => Y3 Y2 Y1 Y0
3799 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3801 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
3802 unsigned HalfLaneElems = NumLaneElems/2;
3803 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3804 for (unsigned i = 0; i != NumLaneElems; ++i) {
3805 int Idx = Mask[i+l];
3806 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3807 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3809 // For VSHUFPSY, the mask of the second half must be the same as the
3810 // first but with the appropriate offsets. This works in the same way as
3811 // VPERMILPS works with masks.
3812 if (!symetricMaskRequired || Idx < 0)
3814 if (MaskVal[i] < 0) {
3815 MaskVal[i] = Idx - l;
3818 if ((signed)(Idx - l) != MaskVal[i])
3826 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3827 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3828 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
3829 if (!VT.is128BitVector())
3832 unsigned NumElems = VT.getVectorNumElements();
3837 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3838 return isUndefOrEqual(Mask[0], 6) &&
3839 isUndefOrEqual(Mask[1], 7) &&
3840 isUndefOrEqual(Mask[2], 2) &&
3841 isUndefOrEqual(Mask[3], 3);
3844 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3845 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3847 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
3848 if (!VT.is128BitVector())
3851 unsigned NumElems = VT.getVectorNumElements();
3856 return isUndefOrEqual(Mask[0], 2) &&
3857 isUndefOrEqual(Mask[1], 3) &&
3858 isUndefOrEqual(Mask[2], 2) &&
3859 isUndefOrEqual(Mask[3], 3);
3862 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3863 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3864 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
3865 if (!VT.is128BitVector())
3868 unsigned NumElems = VT.getVectorNumElements();
3870 if (NumElems != 2 && NumElems != 4)
3873 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3874 if (!isUndefOrEqual(Mask[i], i + NumElems))
3877 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3878 if (!isUndefOrEqual(Mask[i], i))
3884 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3885 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3886 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
3887 if (!VT.is128BitVector())
3890 unsigned NumElems = VT.getVectorNumElements();
3892 if (NumElems != 2 && NumElems != 4)
3895 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3896 if (!isUndefOrEqual(Mask[i], i))
3899 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3900 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3907 // Some special combinations that can be optimized.
3910 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3911 SelectionDAG &DAG) {
3912 MVT VT = SVOp->getSimpleValueType(0);
3915 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3918 ArrayRef<int> Mask = SVOp->getMask();
3920 // These are the special masks that may be optimized.
3921 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3922 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3923 bool MatchEvenMask = true;
3924 bool MatchOddMask = true;
3925 for (int i=0; i<8; ++i) {
3926 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
3927 MatchEvenMask = false;
3928 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
3929 MatchOddMask = false;
3932 if (!MatchEvenMask && !MatchOddMask)
3935 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
3937 SDValue Op0 = SVOp->getOperand(0);
3938 SDValue Op1 = SVOp->getOperand(1);
3940 if (MatchEvenMask) {
3941 // Shift the second operand right to 32 bits.
3942 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
3943 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
3945 // Shift the first operand left to 32 bits.
3946 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
3947 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
3949 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
3950 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
3953 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3954 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3955 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
3956 bool HasInt256, bool V2IsSplat = false) {
3958 assert(VT.getSizeInBits() >= 128 &&
3959 "Unsupported vector type for unpckl");
3961 // AVX defines UNPCK* to operate independently on 128-bit lanes.
3963 unsigned NumOf256BitLanes;
3964 unsigned NumElts = VT.getVectorNumElements();
3965 if (VT.is256BitVector()) {
3966 if (NumElts != 4 && NumElts != 8 &&
3967 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3970 NumOf256BitLanes = 1;
3971 } else if (VT.is512BitVector()) {
3972 assert(VT.getScalarType().getSizeInBits() >= 32 &&
3973 "Unsupported vector type for unpckh");
3975 NumOf256BitLanes = 2;
3978 NumOf256BitLanes = 1;
3981 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
3982 unsigned NumLaneElts = NumEltsInStride/NumLanes;
3984 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
3985 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
3986 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
3987 int BitI = Mask[l256*NumEltsInStride+l+i];
3988 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
3989 if (!isUndefOrEqual(BitI, j+l256*NumElts))
3991 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
3993 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4001 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4002 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4003 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4004 bool HasInt256, bool V2IsSplat = false) {
4005 assert(VT.getSizeInBits() >= 128 &&
4006 "Unsupported vector type for unpckh");
4008 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4010 unsigned NumOf256BitLanes;
4011 unsigned NumElts = VT.getVectorNumElements();
4012 if (VT.is256BitVector()) {
4013 if (NumElts != 4 && NumElts != 8 &&
4014 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4017 NumOf256BitLanes = 1;
4018 } else if (VT.is512BitVector()) {
4019 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4020 "Unsupported vector type for unpckh");
4022 NumOf256BitLanes = 2;
4025 NumOf256BitLanes = 1;
4028 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4029 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4031 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4032 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4033 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4034 int BitI = Mask[l256*NumEltsInStride+l+i];
4035 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4036 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4038 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4040 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4048 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4049 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4051 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4052 unsigned NumElts = VT.getVectorNumElements();
4053 bool Is256BitVec = VT.is256BitVector();
4055 if (VT.is512BitVector())
4057 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4058 "Unsupported vector type for unpckh");
4060 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4061 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4064 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4065 // FIXME: Need a better way to get rid of this, there's no latency difference
4066 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4067 // the former later. We should also remove the "_undef" special mask.
4068 if (NumElts == 4 && Is256BitVec)
4071 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4072 // independently on 128-bit lanes.
4073 unsigned NumLanes = VT.getSizeInBits()/128;
4074 unsigned NumLaneElts = NumElts/NumLanes;
4076 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4077 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4078 int BitI = Mask[l+i];
4079 int BitI1 = Mask[l+i+1];
4081 if (!isUndefOrEqual(BitI, j))
4083 if (!isUndefOrEqual(BitI1, j))
4091 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4092 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4094 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4095 unsigned NumElts = VT.getVectorNumElements();
4097 if (VT.is512BitVector())
4100 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4101 "Unsupported vector type for unpckh");
4103 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4104 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4107 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4108 // independently on 128-bit lanes.
4109 unsigned NumLanes = VT.getSizeInBits()/128;
4110 unsigned NumLaneElts = NumElts/NumLanes;
4112 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4113 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4114 int BitI = Mask[l+i];
4115 int BitI1 = Mask[l+i+1];
4116 if (!isUndefOrEqual(BitI, j))
4118 if (!isUndefOrEqual(BitI1, j))
4125 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4126 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4127 /// MOVSD, and MOVD, i.e. setting the lowest element.
4128 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4129 if (VT.getVectorElementType().getSizeInBits() < 32)
4131 if (!VT.is128BitVector())
4134 unsigned NumElts = VT.getVectorNumElements();
4136 if (!isUndefOrEqual(Mask[0], NumElts))
4139 for (unsigned i = 1; i != NumElts; ++i)
4140 if (!isUndefOrEqual(Mask[i], i))
4146 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4147 /// as permutations between 128-bit chunks or halves. As an example: this
4149 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4150 /// The first half comes from the second half of V1 and the second half from the
4151 /// the second half of V2.
4152 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4153 if (!HasFp256 || !VT.is256BitVector())
4156 // The shuffle result is divided into half A and half B. In total the two
4157 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4158 // B must come from C, D, E or F.
4159 unsigned HalfSize = VT.getVectorNumElements()/2;
4160 bool MatchA = false, MatchB = false;
4162 // Check if A comes from one of C, D, E, F.
4163 for (unsigned Half = 0; Half != 4; ++Half) {
4164 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4170 // Check if B comes from one of C, D, E, F.
4171 for (unsigned Half = 0; Half != 4; ++Half) {
4172 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4178 return MatchA && MatchB;
4181 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4182 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4183 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4184 MVT VT = SVOp->getSimpleValueType(0);
4186 unsigned HalfSize = VT.getVectorNumElements()/2;
4188 unsigned FstHalf = 0, SndHalf = 0;
4189 for (unsigned i = 0; i < HalfSize; ++i) {
4190 if (SVOp->getMaskElt(i) > 0) {
4191 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4195 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4196 if (SVOp->getMaskElt(i) > 0) {
4197 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4202 return (FstHalf | (SndHalf << 4));
4205 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4206 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4207 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4211 unsigned NumElts = VT.getVectorNumElements();
4213 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4214 for (unsigned i = 0; i != NumElts; ++i) {
4217 Imm8 |= Mask[i] << (i*2);
4222 unsigned LaneSize = 4;
4223 SmallVector<int, 4> MaskVal(LaneSize, -1);
4225 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4226 for (unsigned i = 0; i != LaneSize; ++i) {
4227 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4231 if (MaskVal[i] < 0) {
4232 MaskVal[i] = Mask[i+l] - l;
4233 Imm8 |= MaskVal[i] << (i*2);
4236 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4243 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4244 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4245 /// Note that VPERMIL mask matching is different depending whether theunderlying
4246 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4247 /// to the same elements of the low, but to the higher half of the source.
4248 /// In VPERMILPD the two lanes could be shuffled independently of each other
4249 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4250 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4251 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4252 if (VT.getSizeInBits() < 256 || EltSize < 32)
4254 bool symetricMaskRequired = (EltSize == 32);
4255 unsigned NumElts = VT.getVectorNumElements();
4257 unsigned NumLanes = VT.getSizeInBits()/128;
4258 unsigned LaneSize = NumElts/NumLanes;
4259 // 2 or 4 elements in one lane
4261 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4262 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4263 for (unsigned i = 0; i != LaneSize; ++i) {
4264 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4266 if (symetricMaskRequired) {
4267 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4268 ExpectedMaskVal[i] = Mask[i+l] - l;
4271 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4279 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4280 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4281 /// element of vector 2 and the other elements to come from vector 1 in order.
4282 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4283 bool V2IsSplat = false, bool V2IsUndef = false) {
4284 if (!VT.is128BitVector())
4287 unsigned NumOps = VT.getVectorNumElements();
4288 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4291 if (!isUndefOrEqual(Mask[0], 0))
4294 for (unsigned i = 1; i != NumOps; ++i)
4295 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4296 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4297 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4303 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4304 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4305 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4306 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4307 const X86Subtarget *Subtarget) {
4308 if (!Subtarget->hasSSE3())
4311 unsigned NumElems = VT.getVectorNumElements();
4313 if ((VT.is128BitVector() && NumElems != 4) ||
4314 (VT.is256BitVector() && NumElems != 8) ||
4315 (VT.is512BitVector() && NumElems != 16))
4318 // "i+1" is the value the indexed mask element must have
4319 for (unsigned i = 0; i != NumElems; i += 2)
4320 if (!isUndefOrEqual(Mask[i], i+1) ||
4321 !isUndefOrEqual(Mask[i+1], i+1))
4327 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4328 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4329 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4330 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4331 const X86Subtarget *Subtarget) {
4332 if (!Subtarget->hasSSE3())
4335 unsigned NumElems = VT.getVectorNumElements();
4337 if ((VT.is128BitVector() && NumElems != 4) ||
4338 (VT.is256BitVector() && NumElems != 8) ||
4339 (VT.is512BitVector() && NumElems != 16))
4342 // "i" is the value the indexed mask element must have
4343 for (unsigned i = 0; i != NumElems; i += 2)
4344 if (!isUndefOrEqual(Mask[i], i) ||
4345 !isUndefOrEqual(Mask[i+1], i))
4351 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4352 /// specifies a shuffle of elements that is suitable for input to 256-bit
4353 /// version of MOVDDUP.
4354 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4355 if (!HasFp256 || !VT.is256BitVector())
4358 unsigned NumElts = VT.getVectorNumElements();
4362 for (unsigned i = 0; i != NumElts/2; ++i)
4363 if (!isUndefOrEqual(Mask[i], 0))
4365 for (unsigned i = NumElts/2; i != NumElts; ++i)
4366 if (!isUndefOrEqual(Mask[i], NumElts/2))
4371 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4372 /// specifies a shuffle of elements that is suitable for input to 128-bit
4373 /// version of MOVDDUP.
4374 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4375 if (!VT.is128BitVector())
4378 unsigned e = VT.getVectorNumElements() / 2;
4379 for (unsigned i = 0; i != e; ++i)
4380 if (!isUndefOrEqual(Mask[i], i))
4382 for (unsigned i = 0; i != e; ++i)
4383 if (!isUndefOrEqual(Mask[e+i], i))
4388 /// isVEXTRACTIndex - Return true if the specified
4389 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4390 /// suitable for instruction that extract 128 or 256 bit vectors
4391 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4392 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4393 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4396 // The index should be aligned on a vecWidth-bit boundary.
4398 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4400 MVT VT = N->getSimpleValueType(0);
4401 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4402 bool Result = (Index * ElSize) % vecWidth == 0;
4407 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4408 /// operand specifies a subvector insert that is suitable for input to
4409 /// insertion of 128 or 256-bit subvectors
4410 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4411 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4412 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4414 // The index should be aligned on a vecWidth-bit boundary.
4416 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4418 MVT VT = N->getSimpleValueType(0);
4419 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4420 bool Result = (Index * ElSize) % vecWidth == 0;
4425 bool X86::isVINSERT128Index(SDNode *N) {
4426 return isVINSERTIndex(N, 128);
4429 bool X86::isVINSERT256Index(SDNode *N) {
4430 return isVINSERTIndex(N, 256);
4433 bool X86::isVEXTRACT128Index(SDNode *N) {
4434 return isVEXTRACTIndex(N, 128);
4437 bool X86::isVEXTRACT256Index(SDNode *N) {
4438 return isVEXTRACTIndex(N, 256);
4441 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4442 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4443 /// Handles 128-bit and 256-bit.
4444 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4445 MVT VT = N->getSimpleValueType(0);
4447 assert((VT.getSizeInBits() >= 128) &&
4448 "Unsupported vector type for PSHUF/SHUFP");
4450 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4451 // independently on 128-bit lanes.
4452 unsigned NumElts = VT.getVectorNumElements();
4453 unsigned NumLanes = VT.getSizeInBits()/128;
4454 unsigned NumLaneElts = NumElts/NumLanes;
4456 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4457 "Only supports 2, 4 or 8 elements per lane");
4459 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4461 for (unsigned i = 0; i != NumElts; ++i) {
4462 int Elt = N->getMaskElt(i);
4463 if (Elt < 0) continue;
4464 Elt &= NumLaneElts - 1;
4465 unsigned ShAmt = (i << Shift) % 8;
4466 Mask |= Elt << ShAmt;
4472 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4473 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4474 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4475 MVT VT = N->getSimpleValueType(0);
4477 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4478 "Unsupported vector type for PSHUFHW");
4480 unsigned NumElts = VT.getVectorNumElements();
4483 for (unsigned l = 0; l != NumElts; l += 8) {
4484 // 8 nodes per lane, but we only care about the last 4.
4485 for (unsigned i = 0; i < 4; ++i) {
4486 int Elt = N->getMaskElt(l+i+4);
4487 if (Elt < 0) continue;
4488 Elt &= 0x3; // only 2-bits.
4489 Mask |= Elt << (i * 2);
4496 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4497 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4498 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4499 MVT VT = N->getSimpleValueType(0);
4501 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4502 "Unsupported vector type for PSHUFHW");
4504 unsigned NumElts = VT.getVectorNumElements();
4507 for (unsigned l = 0; l != NumElts; l += 8) {
4508 // 8 nodes per lane, but we only care about the first 4.
4509 for (unsigned i = 0; i < 4; ++i) {
4510 int Elt = N->getMaskElt(l+i);
4511 if (Elt < 0) continue;
4512 Elt &= 0x3; // only 2-bits
4513 Mask |= Elt << (i * 2);
4520 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4521 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4522 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4523 MVT VT = SVOp->getSimpleValueType(0);
4524 unsigned EltSize = VT.is512BitVector() ? 1 :
4525 VT.getVectorElementType().getSizeInBits() >> 3;
4527 unsigned NumElts = VT.getVectorNumElements();
4528 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4529 unsigned NumLaneElts = NumElts/NumLanes;
4533 for (i = 0; i != NumElts; ++i) {
4534 Val = SVOp->getMaskElt(i);
4538 if (Val >= (int)NumElts)
4539 Val -= NumElts - NumLaneElts;
4541 assert(Val - i > 0 && "PALIGNR imm should be positive");
4542 return (Val - i) * EltSize;
4545 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4546 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4547 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4548 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4551 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4553 MVT VecVT = N->getOperand(0).getSimpleValueType();
4554 MVT ElVT = VecVT.getVectorElementType();
4556 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4557 return Index / NumElemsPerChunk;
4560 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4561 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4562 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4563 llvm_unreachable("Illegal insert subvector for VINSERT");
4566 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4568 MVT VecVT = N->getSimpleValueType(0);
4569 MVT ElVT = VecVT.getVectorElementType();
4571 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4572 return Index / NumElemsPerChunk;
4575 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4576 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4577 /// and VINSERTI128 instructions.
4578 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4579 return getExtractVEXTRACTImmediate(N, 128);
4582 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4583 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4584 /// and VINSERTI64x4 instructions.
4585 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4586 return getExtractVEXTRACTImmediate(N, 256);
4589 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4590 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4591 /// and VINSERTI128 instructions.
4592 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4593 return getInsertVINSERTImmediate(N, 128);
4596 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4597 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4598 /// and VINSERTI64x4 instructions.
4599 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4600 return getInsertVINSERTImmediate(N, 256);
4603 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4605 bool X86::isZeroNode(SDValue Elt) {
4606 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Elt))
4607 return CN->isNullValue();
4608 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4609 return CFP->getValueAPF().isPosZero();
4613 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4614 /// their permute mask.
4615 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4616 SelectionDAG &DAG) {
4617 MVT VT = SVOp->getSimpleValueType(0);
4618 unsigned NumElems = VT.getVectorNumElements();
4619 SmallVector<int, 8> MaskVec;
4621 for (unsigned i = 0; i != NumElems; ++i) {
4622 int Idx = SVOp->getMaskElt(i);
4624 if (Idx < (int)NumElems)
4629 MaskVec.push_back(Idx);
4631 return DAG.getVectorShuffle(VT, SDLoc(SVOp), SVOp->getOperand(1),
4632 SVOp->getOperand(0), &MaskVec[0]);
4635 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4636 /// match movhlps. The lower half elements should come from upper half of
4637 /// V1 (and in order), and the upper half elements should come from the upper
4638 /// half of V2 (and in order).
4639 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4640 if (!VT.is128BitVector())
4642 if (VT.getVectorNumElements() != 4)
4644 for (unsigned i = 0, e = 2; i != e; ++i)
4645 if (!isUndefOrEqual(Mask[i], i+2))
4647 for (unsigned i = 2; i != 4; ++i)
4648 if (!isUndefOrEqual(Mask[i], i+4))
4653 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4654 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4656 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4657 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4659 N = N->getOperand(0).getNode();
4660 if (!ISD::isNON_EXTLoad(N))
4663 *LD = cast<LoadSDNode>(N);
4667 // Test whether the given value is a vector value which will be legalized
4669 static bool WillBeConstantPoolLoad(SDNode *N) {
4670 if (N->getOpcode() != ISD::BUILD_VECTOR)
4673 // Check for any non-constant elements.
4674 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4675 switch (N->getOperand(i).getNode()->getOpcode()) {
4677 case ISD::ConstantFP:
4684 // Vectors of all-zeros and all-ones are materialized with special
4685 // instructions rather than being loaded.
4686 return !ISD::isBuildVectorAllZeros(N) &&
4687 !ISD::isBuildVectorAllOnes(N);
4690 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4691 /// match movlp{s|d}. The lower half elements should come from lower half of
4692 /// V1 (and in order), and the upper half elements should come from the upper
4693 /// half of V2 (and in order). And since V1 will become the source of the
4694 /// MOVLP, it must be either a vector load or a scalar load to vector.
4695 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4696 ArrayRef<int> Mask, MVT VT) {
4697 if (!VT.is128BitVector())
4700 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4702 // Is V2 is a vector load, don't do this transformation. We will try to use
4703 // load folding shufps op.
4704 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4707 unsigned NumElems = VT.getVectorNumElements();
4709 if (NumElems != 2 && NumElems != 4)
4711 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4712 if (!isUndefOrEqual(Mask[i], i))
4714 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4715 if (!isUndefOrEqual(Mask[i], i+NumElems))
4720 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4722 static bool isSplatVector(SDNode *N) {
4723 if (N->getOpcode() != ISD::BUILD_VECTOR)
4726 SDValue SplatValue = N->getOperand(0);
4727 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4728 if (N->getOperand(i) != SplatValue)
4733 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4734 /// to an zero vector.
4735 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4736 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4737 SDValue V1 = N->getOperand(0);
4738 SDValue V2 = N->getOperand(1);
4739 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4740 for (unsigned i = 0; i != NumElems; ++i) {
4741 int Idx = N->getMaskElt(i);
4742 if (Idx >= (int)NumElems) {
4743 unsigned Opc = V2.getOpcode();
4744 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4746 if (Opc != ISD::BUILD_VECTOR ||
4747 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4749 } else if (Idx >= 0) {
4750 unsigned Opc = V1.getOpcode();
4751 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4753 if (Opc != ISD::BUILD_VECTOR ||
4754 !X86::isZeroNode(V1.getOperand(Idx)))
4761 /// getZeroVector - Returns a vector of specified type with all zero elements.
4763 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4764 SelectionDAG &DAG, SDLoc dl) {
4765 assert(VT.isVector() && "Expected a vector type");
4767 // Always build SSE zero vectors as <4 x i32> bitcasted
4768 // to their dest type. This ensures they get CSE'd.
4770 if (VT.is128BitVector()) { // SSE
4771 if (Subtarget->hasSSE2()) { // SSE2
4772 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4773 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4775 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4776 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4778 } else if (VT.is256BitVector()) { // AVX
4779 if (Subtarget->hasInt256()) { // AVX2
4780 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4781 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4782 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4783 array_lengthof(Ops));
4785 // 256-bit logic and arithmetic instructions in AVX are all
4786 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4787 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4788 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4789 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops,
4790 array_lengthof(Ops));
4792 } else if (VT.is512BitVector()) { // AVX-512
4793 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4794 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4795 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4796 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops, 16);
4798 llvm_unreachable("Unexpected vector type");
4800 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4803 /// getOnesVector - Returns a vector of specified type with all bits set.
4804 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4805 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4806 /// Then bitcast to their original type, ensuring they get CSE'd.
4807 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4809 assert(VT.isVector() && "Expected a vector type");
4811 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4813 if (VT.is256BitVector()) {
4814 if (HasInt256) { // AVX2
4815 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4816 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4817 array_lengthof(Ops));
4819 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4820 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4822 } else if (VT.is128BitVector()) {
4823 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4825 llvm_unreachable("Unexpected vector type");
4827 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4830 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4831 /// that point to V2 points to its first element.
4832 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4833 for (unsigned i = 0; i != NumElems; ++i) {
4834 if (Mask[i] > (int)NumElems) {
4840 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4841 /// operation of specified width.
4842 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4844 unsigned NumElems = VT.getVectorNumElements();
4845 SmallVector<int, 8> Mask;
4846 Mask.push_back(NumElems);
4847 for (unsigned i = 1; i != NumElems; ++i)
4849 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4852 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4853 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4855 unsigned NumElems = VT.getVectorNumElements();
4856 SmallVector<int, 8> Mask;
4857 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4859 Mask.push_back(i + NumElems);
4861 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4864 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4865 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4867 unsigned NumElems = VT.getVectorNumElements();
4868 SmallVector<int, 8> Mask;
4869 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4870 Mask.push_back(i + Half);
4871 Mask.push_back(i + NumElems + Half);
4873 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4876 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4877 // a generic shuffle instruction because the target has no such instructions.
4878 // Generate shuffles which repeat i16 and i8 several times until they can be
4879 // represented by v4f32 and then be manipulated by target suported shuffles.
4880 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4881 MVT VT = V.getSimpleValueType();
4882 int NumElems = VT.getVectorNumElements();
4885 while (NumElems > 4) {
4886 if (EltNo < NumElems/2) {
4887 V = getUnpackl(DAG, dl, VT, V, V);
4889 V = getUnpackh(DAG, dl, VT, V, V);
4890 EltNo -= NumElems/2;
4897 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4898 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4899 MVT VT = V.getSimpleValueType();
4902 if (VT.is128BitVector()) {
4903 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4904 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4905 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4907 } else if (VT.is256BitVector()) {
4908 // To use VPERMILPS to splat scalars, the second half of indicies must
4909 // refer to the higher part, which is a duplication of the lower one,
4910 // because VPERMILPS can only handle in-lane permutations.
4911 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4912 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4914 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4915 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4918 llvm_unreachable("Vector size not supported");
4920 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4923 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4924 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4925 MVT SrcVT = SV->getSimpleValueType(0);
4926 SDValue V1 = SV->getOperand(0);
4929 int EltNo = SV->getSplatIndex();
4930 int NumElems = SrcVT.getVectorNumElements();
4931 bool Is256BitVec = SrcVT.is256BitVector();
4933 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
4934 "Unknown how to promote splat for type");
4936 // Extract the 128-bit part containing the splat element and update
4937 // the splat element index when it refers to the higher register.
4939 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4940 if (EltNo >= NumElems/2)
4941 EltNo -= NumElems/2;
4944 // All i16 and i8 vector types can't be used directly by a generic shuffle
4945 // instruction because the target has no such instruction. Generate shuffles
4946 // which repeat i16 and i8 several times until they fit in i32, and then can
4947 // be manipulated by target suported shuffles.
4948 MVT EltVT = SrcVT.getVectorElementType();
4949 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4950 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4952 // Recreate the 256-bit vector and place the same 128-bit vector
4953 // into the low and high part. This is necessary because we want
4954 // to use VPERM* to shuffle the vectors
4956 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4959 return getLegalSplat(DAG, V1, EltNo);
4962 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4963 /// vector of zero or undef vector. This produces a shuffle where the low
4964 /// element of V2 is swizzled into the zero/undef vector, landing at element
4965 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4966 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4968 const X86Subtarget *Subtarget,
4969 SelectionDAG &DAG) {
4970 MVT VT = V2.getSimpleValueType();
4972 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4973 unsigned NumElems = VT.getVectorNumElements();
4974 SmallVector<int, 16> MaskVec;
4975 for (unsigned i = 0; i != NumElems; ++i)
4976 // If this is the insertion idx, put the low elt of V2 here.
4977 MaskVec.push_back(i == Idx ? NumElems : i);
4978 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4981 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4982 /// target specific opcode. Returns true if the Mask could be calculated.
4983 /// Sets IsUnary to true if only uses one source.
4984 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4985 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4986 unsigned NumElems = VT.getVectorNumElements();
4990 switch(N->getOpcode()) {
4992 ImmN = N->getOperand(N->getNumOperands()-1);
4993 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4995 case X86ISD::UNPCKH:
4996 DecodeUNPCKHMask(VT, Mask);
4998 case X86ISD::UNPCKL:
4999 DecodeUNPCKLMask(VT, Mask);
5001 case X86ISD::MOVHLPS:
5002 DecodeMOVHLPSMask(NumElems, Mask);
5004 case X86ISD::MOVLHPS:
5005 DecodeMOVLHPSMask(NumElems, Mask);
5007 case X86ISD::PALIGNR:
5008 ImmN = N->getOperand(N->getNumOperands()-1);
5009 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5011 case X86ISD::PSHUFD:
5012 case X86ISD::VPERMILP:
5013 ImmN = N->getOperand(N->getNumOperands()-1);
5014 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5017 case X86ISD::PSHUFHW:
5018 ImmN = N->getOperand(N->getNumOperands()-1);
5019 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5022 case X86ISD::PSHUFLW:
5023 ImmN = N->getOperand(N->getNumOperands()-1);
5024 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5027 case X86ISD::VPERMI:
5028 ImmN = N->getOperand(N->getNumOperands()-1);
5029 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5033 case X86ISD::MOVSD: {
5034 // The index 0 always comes from the first element of the second source,
5035 // this is why MOVSS and MOVSD are used in the first place. The other
5036 // elements come from the other positions of the first source vector
5037 Mask.push_back(NumElems);
5038 for (unsigned i = 1; i != NumElems; ++i) {
5043 case X86ISD::VPERM2X128:
5044 ImmN = N->getOperand(N->getNumOperands()-1);
5045 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5046 if (Mask.empty()) return false;
5048 case X86ISD::MOVDDUP:
5049 case X86ISD::MOVLHPD:
5050 case X86ISD::MOVLPD:
5051 case X86ISD::MOVLPS:
5052 case X86ISD::MOVSHDUP:
5053 case X86ISD::MOVSLDUP:
5054 // Not yet implemented
5056 default: llvm_unreachable("unknown target shuffle node");
5062 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5063 /// element of the result of the vector shuffle.
5064 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5067 return SDValue(); // Limit search depth.
5069 SDValue V = SDValue(N, 0);
5070 EVT VT = V.getValueType();
5071 unsigned Opcode = V.getOpcode();
5073 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5074 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5075 int Elt = SV->getMaskElt(Index);
5078 return DAG.getUNDEF(VT.getVectorElementType());
5080 unsigned NumElems = VT.getVectorNumElements();
5081 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5082 : SV->getOperand(1);
5083 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5086 // Recurse into target specific vector shuffles to find scalars.
5087 if (isTargetShuffle(Opcode)) {
5088 MVT ShufVT = V.getSimpleValueType();
5089 unsigned NumElems = ShufVT.getVectorNumElements();
5090 SmallVector<int, 16> ShuffleMask;
5093 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5096 int Elt = ShuffleMask[Index];
5098 return DAG.getUNDEF(ShufVT.getVectorElementType());
5100 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5102 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5106 // Actual nodes that may contain scalar elements
5107 if (Opcode == ISD::BITCAST) {
5108 V = V.getOperand(0);
5109 EVT SrcVT = V.getValueType();
5110 unsigned NumElems = VT.getVectorNumElements();
5112 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5116 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5117 return (Index == 0) ? V.getOperand(0)
5118 : DAG.getUNDEF(VT.getVectorElementType());
5120 if (V.getOpcode() == ISD::BUILD_VECTOR)
5121 return V.getOperand(Index);
5126 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5127 /// shuffle operation which come from a consecutively from a zero. The
5128 /// search can start in two different directions, from left or right.
5129 /// We count undefs as zeros until PreferredNum is reached.
5130 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5131 unsigned NumElems, bool ZerosFromLeft,
5133 unsigned PreferredNum = -1U) {
5134 unsigned NumZeros = 0;
5135 for (unsigned i = 0; i != NumElems; ++i) {
5136 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5137 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5141 if (X86::isZeroNode(Elt))
5143 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5144 NumZeros = std::min(NumZeros + 1, PreferredNum);
5152 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5153 /// correspond consecutively to elements from one of the vector operands,
5154 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5156 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5157 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5158 unsigned NumElems, unsigned &OpNum) {
5159 bool SeenV1 = false;
5160 bool SeenV2 = false;
5162 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5163 int Idx = SVOp->getMaskElt(i);
5164 // Ignore undef indicies
5168 if (Idx < (int)NumElems)
5173 // Only accept consecutive elements from the same vector
5174 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5178 OpNum = SeenV1 ? 0 : 1;
5182 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5183 /// logical left shift of a vector.
5184 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5185 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5187 SVOp->getSimpleValueType(0).getVectorNumElements();
5188 unsigned NumZeros = getNumOfConsecutiveZeros(
5189 SVOp, NumElems, false /* check zeros from right */, DAG,
5190 SVOp->getMaskElt(0));
5196 // Considering the elements in the mask that are not consecutive zeros,
5197 // check if they consecutively come from only one of the source vectors.
5199 // V1 = {X, A, B, C} 0
5201 // vector_shuffle V1, V2 <1, 2, 3, X>
5203 if (!isShuffleMaskConsecutive(SVOp,
5204 0, // Mask Start Index
5205 NumElems-NumZeros, // Mask End Index(exclusive)
5206 NumZeros, // Where to start looking in the src vector
5207 NumElems, // Number of elements in vector
5208 OpSrc)) // Which source operand ?
5213 ShVal = SVOp->getOperand(OpSrc);
5217 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5218 /// logical left shift of a vector.
5219 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5220 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5222 SVOp->getSimpleValueType(0).getVectorNumElements();
5223 unsigned NumZeros = getNumOfConsecutiveZeros(
5224 SVOp, NumElems, true /* check zeros from left */, DAG,
5225 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5231 // Considering the elements in the mask that are not consecutive zeros,
5232 // check if they consecutively come from only one of the source vectors.
5234 // 0 { A, B, X, X } = V2
5236 // vector_shuffle V1, V2 <X, X, 4, 5>
5238 if (!isShuffleMaskConsecutive(SVOp,
5239 NumZeros, // Mask Start Index
5240 NumElems, // Mask End Index(exclusive)
5241 0, // Where to start looking in the src vector
5242 NumElems, // Number of elements in vector
5243 OpSrc)) // Which source operand ?
5248 ShVal = SVOp->getOperand(OpSrc);
5252 /// isVectorShift - Returns true if the shuffle can be implemented as a
5253 /// logical left or right shift of a vector.
5254 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5255 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5256 // Although the logic below support any bitwidth size, there are no
5257 // shift instructions which handle more than 128-bit vectors.
5258 if (!SVOp->getSimpleValueType(0).is128BitVector())
5261 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5262 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5268 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5270 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5271 unsigned NumNonZero, unsigned NumZero,
5273 const X86Subtarget* Subtarget,
5274 const TargetLowering &TLI) {
5281 for (unsigned i = 0; i < 16; ++i) {
5282 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5283 if (ThisIsNonZero && First) {
5285 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5287 V = DAG.getUNDEF(MVT::v8i16);
5292 SDValue ThisElt(0, 0), LastElt(0, 0);
5293 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5294 if (LastIsNonZero) {
5295 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5296 MVT::i16, Op.getOperand(i-1));
5298 if (ThisIsNonZero) {
5299 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5300 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5301 ThisElt, DAG.getConstant(8, MVT::i8));
5303 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5307 if (ThisElt.getNode())
5308 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5309 DAG.getIntPtrConstant(i/2));
5313 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5316 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5318 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5319 unsigned NumNonZero, unsigned NumZero,
5321 const X86Subtarget* Subtarget,
5322 const TargetLowering &TLI) {
5329 for (unsigned i = 0; i < 8; ++i) {
5330 bool isNonZero = (NonZeros & (1 << i)) != 0;
5334 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5336 V = DAG.getUNDEF(MVT::v8i16);
5339 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5340 MVT::v8i16, V, Op.getOperand(i),
5341 DAG.getIntPtrConstant(i));
5348 /// getVShift - Return a vector logical shift node.
5350 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5351 unsigned NumBits, SelectionDAG &DAG,
5352 const TargetLowering &TLI, SDLoc dl) {
5353 assert(VT.is128BitVector() && "Unknown type for VShift");
5354 EVT ShVT = MVT::v2i64;
5355 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5356 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5357 return DAG.getNode(ISD::BITCAST, dl, VT,
5358 DAG.getNode(Opc, dl, ShVT, SrcOp,
5359 DAG.getConstant(NumBits,
5360 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5364 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5366 // Check if the scalar load can be widened into a vector load. And if
5367 // the address is "base + cst" see if the cst can be "absorbed" into
5368 // the shuffle mask.
5369 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5370 SDValue Ptr = LD->getBasePtr();
5371 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5373 EVT PVT = LD->getValueType(0);
5374 if (PVT != MVT::i32 && PVT != MVT::f32)
5379 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5380 FI = FINode->getIndex();
5382 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5383 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5384 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5385 Offset = Ptr.getConstantOperandVal(1);
5386 Ptr = Ptr.getOperand(0);
5391 // FIXME: 256-bit vector instructions don't require a strict alignment,
5392 // improve this code to support it better.
5393 unsigned RequiredAlign = VT.getSizeInBits()/8;
5394 SDValue Chain = LD->getChain();
5395 // Make sure the stack object alignment is at least 16 or 32.
5396 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5397 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5398 if (MFI->isFixedObjectIndex(FI)) {
5399 // Can't change the alignment. FIXME: It's possible to compute
5400 // the exact stack offset and reference FI + adjust offset instead.
5401 // If someone *really* cares about this. That's the way to implement it.
5404 MFI->setObjectAlignment(FI, RequiredAlign);
5408 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5409 // Ptr + (Offset & ~15).
5412 if ((Offset % RequiredAlign) & 3)
5414 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5416 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5417 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5419 int EltNo = (Offset - StartOffset) >> 2;
5420 unsigned NumElems = VT.getVectorNumElements();
5422 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5423 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5424 LD->getPointerInfo().getWithOffset(StartOffset),
5425 false, false, false, 0);
5427 SmallVector<int, 8> Mask;
5428 for (unsigned i = 0; i != NumElems; ++i)
5429 Mask.push_back(EltNo);
5431 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5437 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5438 /// vector of type 'VT', see if the elements can be replaced by a single large
5439 /// load which has the same value as a build_vector whose operands are 'elts'.
5441 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5443 /// FIXME: we'd also like to handle the case where the last elements are zero
5444 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5445 /// There's even a handy isZeroNode for that purpose.
5446 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5447 SDLoc &DL, SelectionDAG &DAG,
5448 bool isAfterLegalize) {
5449 EVT EltVT = VT.getVectorElementType();
5450 unsigned NumElems = Elts.size();
5452 LoadSDNode *LDBase = NULL;
5453 unsigned LastLoadedElt = -1U;
5455 // For each element in the initializer, see if we've found a load or an undef.
5456 // If we don't find an initial load element, or later load elements are
5457 // non-consecutive, bail out.
5458 for (unsigned i = 0; i < NumElems; ++i) {
5459 SDValue Elt = Elts[i];
5461 if (!Elt.getNode() ||
5462 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5465 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5467 LDBase = cast<LoadSDNode>(Elt.getNode());
5471 if (Elt.getOpcode() == ISD::UNDEF)
5474 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5475 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5480 // If we have found an entire vector of loads and undefs, then return a large
5481 // load of the entire vector width starting at the base pointer. If we found
5482 // consecutive loads for the low half, generate a vzext_load node.
5483 if (LastLoadedElt == NumElems - 1) {
5485 if (isAfterLegalize &&
5486 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5489 SDValue NewLd = SDValue();
5491 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5492 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5493 LDBase->getPointerInfo(),
5494 LDBase->isVolatile(), LDBase->isNonTemporal(),
5495 LDBase->isInvariant(), 0);
5496 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5497 LDBase->getPointerInfo(),
5498 LDBase->isVolatile(), LDBase->isNonTemporal(),
5499 LDBase->isInvariant(), LDBase->getAlignment());
5501 if (LDBase->hasAnyUseOfValue(1)) {
5502 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5504 SDValue(NewLd.getNode(), 1));
5505 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5506 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5507 SDValue(NewLd.getNode(), 1));
5512 if (NumElems == 4 && LastLoadedElt == 1 &&
5513 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5514 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5515 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5517 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops,
5518 array_lengthof(Ops), MVT::i64,
5519 LDBase->getPointerInfo(),
5520 LDBase->getAlignment(),
5521 false/*isVolatile*/, true/*ReadMem*/,
5524 // Make sure the newly-created LOAD is in the same position as LDBase in
5525 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5526 // update uses of LDBase's output chain to use the TokenFactor.
5527 if (LDBase->hasAnyUseOfValue(1)) {
5528 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5529 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5530 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5531 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5532 SDValue(ResNode.getNode(), 1));
5535 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5540 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5541 /// to generate a splat value for the following cases:
5542 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5543 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5544 /// a scalar load, or a constant.
5545 /// The VBROADCAST node is returned when a pattern is found,
5546 /// or SDValue() otherwise.
5547 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5548 SelectionDAG &DAG) {
5549 if (!Subtarget->hasFp256())
5552 MVT VT = Op.getSimpleValueType();
5555 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5556 "Unsupported vector type for broadcast.");
5561 switch (Op.getOpcode()) {
5563 // Unknown pattern found.
5566 case ISD::BUILD_VECTOR: {
5567 // The BUILD_VECTOR node must be a splat.
5568 if (!isSplatVector(Op.getNode()))
5571 Ld = Op.getOperand(0);
5572 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5573 Ld.getOpcode() == ISD::ConstantFP);
5575 // The suspected load node has several users. Make sure that all
5576 // of its users are from the BUILD_VECTOR node.
5577 // Constants may have multiple users.
5578 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5583 case ISD::VECTOR_SHUFFLE: {
5584 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5586 // Shuffles must have a splat mask where the first element is
5588 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5591 SDValue Sc = Op.getOperand(0);
5592 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5593 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5595 if (!Subtarget->hasInt256())
5598 // Use the register form of the broadcast instruction available on AVX2.
5599 if (VT.getSizeInBits() >= 256)
5600 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5601 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5604 Ld = Sc.getOperand(0);
5605 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5606 Ld.getOpcode() == ISD::ConstantFP);
5608 // The scalar_to_vector node and the suspected
5609 // load node must have exactly one user.
5610 // Constants may have multiple users.
5612 // AVX-512 has register version of the broadcast
5613 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5614 Ld.getValueType().getSizeInBits() >= 32;
5615 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5622 bool IsGE256 = (VT.getSizeInBits() >= 256);
5624 // Handle the broadcasting a single constant scalar from the constant pool
5625 // into a vector. On Sandybridge it is still better to load a constant vector
5626 // from the constant pool and not to broadcast it from a scalar.
5627 if (ConstSplatVal && Subtarget->hasInt256()) {
5628 EVT CVT = Ld.getValueType();
5629 assert(!CVT.isVector() && "Must not broadcast a vector type");
5630 unsigned ScalarSize = CVT.getSizeInBits();
5632 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
5633 const Constant *C = 0;
5634 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5635 C = CI->getConstantIntValue();
5636 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5637 C = CF->getConstantFPValue();
5639 assert(C && "Invalid constant type");
5641 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5642 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5643 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5644 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5645 MachinePointerInfo::getConstantPool(),
5646 false, false, false, Alignment);
5648 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5652 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5653 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5655 // Handle AVX2 in-register broadcasts.
5656 if (!IsLoad && Subtarget->hasInt256() &&
5657 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5658 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5660 // The scalar source must be a normal load.
5664 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
5665 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5667 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5668 // double since there is no vbroadcastsd xmm
5669 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5670 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5671 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5674 // Unsupported broadcast.
5678 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5679 MVT VT = Op.getSimpleValueType();
5681 // Skip if insert_vec_elt is not supported.
5682 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5683 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5687 unsigned NumElems = Op.getNumOperands();
5691 SmallVector<unsigned, 4> InsertIndices;
5692 SmallVector<int, 8> Mask(NumElems, -1);
5694 for (unsigned i = 0; i != NumElems; ++i) {
5695 unsigned Opc = Op.getOperand(i).getOpcode();
5697 if (Opc == ISD::UNDEF)
5700 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5701 // Quit if more than 1 elements need inserting.
5702 if (InsertIndices.size() > 1)
5705 InsertIndices.push_back(i);
5709 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5710 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5712 // Quit if extracted from vector of different type.
5713 if (ExtractedFromVec.getValueType() != VT)
5716 // Quit if non-constant index.
5717 if (!isa<ConstantSDNode>(ExtIdx))
5720 if (VecIn1.getNode() == 0)
5721 VecIn1 = ExtractedFromVec;
5722 else if (VecIn1 != ExtractedFromVec) {
5723 if (VecIn2.getNode() == 0)
5724 VecIn2 = ExtractedFromVec;
5725 else if (VecIn2 != ExtractedFromVec)
5726 // Quit if more than 2 vectors to shuffle
5730 unsigned Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5732 if (ExtractedFromVec == VecIn1)
5734 else if (ExtractedFromVec == VecIn2)
5735 Mask[i] = Idx + NumElems;
5738 if (VecIn1.getNode() == 0)
5741 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5742 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5743 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5744 unsigned Idx = InsertIndices[i];
5745 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5746 DAG.getIntPtrConstant(Idx));
5752 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5754 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5756 MVT VT = Op.getSimpleValueType();
5757 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5758 "Unexpected type in LowerBUILD_VECTORvXi1!");
5761 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5762 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5763 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5764 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5765 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5766 Ops, VT.getVectorNumElements());
5769 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5770 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
5771 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5772 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5773 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5774 Ops, VT.getVectorNumElements());
5777 bool AllContants = true;
5778 uint64_t Immediate = 0;
5779 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5780 SDValue In = Op.getOperand(idx);
5781 if (In.getOpcode() == ISD::UNDEF)
5783 if (!isa<ConstantSDNode>(In)) {
5784 AllContants = false;
5787 if (cast<ConstantSDNode>(In)->getZExtValue())
5788 Immediate |= (1ULL << idx);
5792 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
5793 DAG.getConstant(Immediate, MVT::i16));
5794 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
5795 DAG.getIntPtrConstant(0));
5798 // Splat vector (with undefs)
5799 SDValue In = Op.getOperand(0);
5800 for (unsigned i = 1, e = Op.getNumOperands(); i != e; ++i) {
5801 if (Op.getOperand(i) != In && Op.getOperand(i).getOpcode() != ISD::UNDEF)
5802 llvm_unreachable("Unsupported predicate operation");
5805 SDValue EFLAGS, X86CC;
5806 if (In.getOpcode() == ISD::SETCC) {
5807 SDValue Op0 = In.getOperand(0);
5808 SDValue Op1 = In.getOperand(1);
5809 ISD::CondCode CC = cast<CondCodeSDNode>(In.getOperand(2))->get();
5810 bool isFP = Op1.getValueType().isFloatingPoint();
5811 unsigned X86CCVal = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5813 assert(X86CCVal != X86::COND_INVALID && "Unsupported predicate operation");
5815 X86CC = DAG.getConstant(X86CCVal, MVT::i8);
5816 EFLAGS = EmitCmp(Op0, Op1, X86CCVal, DAG);
5817 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
5818 } else if (In.getOpcode() == X86ISD::SETCC) {
5819 X86CC = In.getOperand(0);
5820 EFLAGS = In.getOperand(1);
5829 // res = allOnes ### CMOVNE -1, %res
5832 MVT InVT = In.getSimpleValueType();
5833 SDValue Bit1 = DAG.getNode(ISD::AND, dl, InVT, In, DAG.getConstant(1, InVT));
5834 EFLAGS = EmitTest(Bit1, X86::COND_NE, DAG);
5835 X86CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5838 if (VT == MVT::v16i1) {
5839 SDValue Cst1 = DAG.getConstant(-1, MVT::i16);
5840 SDValue Cst0 = DAG.getConstant(0, MVT::i16);
5841 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i16,
5842 Cst0, Cst1, X86CC, EFLAGS);
5843 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5846 if (VT == MVT::v8i1) {
5847 SDValue Cst1 = DAG.getConstant(-1, MVT::i32);
5848 SDValue Cst0 = DAG.getConstant(0, MVT::i32);
5849 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i32,
5850 Cst0, Cst1, X86CC, EFLAGS);
5851 CmovOp = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CmovOp);
5852 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5854 llvm_unreachable("Unsupported predicate operation");
5858 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5861 MVT VT = Op.getSimpleValueType();
5862 MVT ExtVT = VT.getVectorElementType();
5863 unsigned NumElems = Op.getNumOperands();
5865 // Generate vectors for predicate vectors.
5866 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5867 return LowerBUILD_VECTORvXi1(Op, DAG);
5869 // Vectors containing all zeros can be matched by pxor and xorps later
5870 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5871 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5872 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5873 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5876 return getZeroVector(VT, Subtarget, DAG, dl);
5879 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5880 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5881 // vpcmpeqd on 256-bit vectors.
5882 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5883 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5886 if (!VT.is512BitVector())
5887 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5890 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
5891 if (Broadcast.getNode())
5894 unsigned EVTBits = ExtVT.getSizeInBits();
5896 unsigned NumZero = 0;
5897 unsigned NumNonZero = 0;
5898 unsigned NonZeros = 0;
5899 bool IsAllConstants = true;
5900 SmallSet<SDValue, 8> Values;
5901 for (unsigned i = 0; i < NumElems; ++i) {
5902 SDValue Elt = Op.getOperand(i);
5903 if (Elt.getOpcode() == ISD::UNDEF)
5906 if (Elt.getOpcode() != ISD::Constant &&
5907 Elt.getOpcode() != ISD::ConstantFP)
5908 IsAllConstants = false;
5909 if (X86::isZeroNode(Elt))
5912 NonZeros |= (1 << i);
5917 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5918 if (NumNonZero == 0)
5919 return DAG.getUNDEF(VT);
5921 // Special case for single non-zero, non-undef, element.
5922 if (NumNonZero == 1) {
5923 unsigned Idx = countTrailingZeros(NonZeros);
5924 SDValue Item = Op.getOperand(Idx);
5926 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5927 // the value are obviously zero, truncate the value to i32 and do the
5928 // insertion that way. Only do this if the value is non-constant or if the
5929 // value is a constant being inserted into element 0. It is cheaper to do
5930 // a constant pool load than it is to do a movd + shuffle.
5931 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5932 (!IsAllConstants || Idx == 0)) {
5933 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5935 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5936 EVT VecVT = MVT::v4i32;
5937 unsigned VecElts = 4;
5939 // Truncate the value (which may itself be a constant) to i32, and
5940 // convert it to a vector with movd (S2V+shuffle to zero extend).
5941 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5942 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5943 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5945 // Now we have our 32-bit value zero extended in the low element of
5946 // a vector. If Idx != 0, swizzle it into place.
5948 SmallVector<int, 4> Mask;
5949 Mask.push_back(Idx);
5950 for (unsigned i = 1; i != VecElts; ++i)
5952 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5955 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5959 // If we have a constant or non-constant insertion into the low element of
5960 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5961 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5962 // depending on what the source datatype is.
5965 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5967 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5968 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5969 if (VT.is256BitVector() || VT.is512BitVector()) {
5970 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5971 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5972 Item, DAG.getIntPtrConstant(0));
5974 assert(VT.is128BitVector() && "Expected an SSE value type!");
5975 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5976 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5977 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5980 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5981 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5982 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5983 if (VT.is256BitVector()) {
5984 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5985 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5987 assert(VT.is128BitVector() && "Expected an SSE value type!");
5988 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5990 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5994 // Is it a vector logical left shift?
5995 if (NumElems == 2 && Idx == 1 &&
5996 X86::isZeroNode(Op.getOperand(0)) &&
5997 !X86::isZeroNode(Op.getOperand(1))) {
5998 unsigned NumBits = VT.getSizeInBits();
5999 return getVShift(true, VT,
6000 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6001 VT, Op.getOperand(1)),
6002 NumBits/2, DAG, *this, dl);
6005 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6008 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6009 // is a non-constant being inserted into an element other than the low one,
6010 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6011 // movd/movss) to move this into the low element, then shuffle it into
6013 if (EVTBits == 32) {
6014 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6016 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6017 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6018 SmallVector<int, 8> MaskVec;
6019 for (unsigned i = 0; i != NumElems; ++i)
6020 MaskVec.push_back(i == Idx ? 0 : 1);
6021 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6025 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6026 if (Values.size() == 1) {
6027 if (EVTBits == 32) {
6028 // Instead of a shuffle like this:
6029 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6030 // Check if it's possible to issue this instead.
6031 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6032 unsigned Idx = countTrailingZeros(NonZeros);
6033 SDValue Item = Op.getOperand(Idx);
6034 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6035 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6040 // A vector full of immediates; various special cases are already
6041 // handled, so this is best done with a single constant-pool load.
6045 // For AVX-length vectors, build the individual 128-bit pieces and use
6046 // shuffles to put them in place.
6047 if (VT.is256BitVector()) {
6048 SmallVector<SDValue, 32> V;
6049 for (unsigned i = 0; i != NumElems; ++i)
6050 V.push_back(Op.getOperand(i));
6052 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6054 // Build both the lower and upper subvector.
6055 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
6056 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
6059 // Recreate the wider vector with the lower and upper part.
6060 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6063 // Let legalizer expand 2-wide build_vectors.
6064 if (EVTBits == 64) {
6065 if (NumNonZero == 1) {
6066 // One half is zero or undef.
6067 unsigned Idx = countTrailingZeros(NonZeros);
6068 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6069 Op.getOperand(Idx));
6070 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6075 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6076 if (EVTBits == 8 && NumElems == 16) {
6077 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6079 if (V.getNode()) return V;
6082 if (EVTBits == 16 && NumElems == 8) {
6083 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6085 if (V.getNode()) return V;
6088 // If element VT is == 32 bits, turn it into a number of shuffles.
6089 SmallVector<SDValue, 8> V(NumElems);
6090 if (NumElems == 4 && NumZero > 0) {
6091 for (unsigned i = 0; i < 4; ++i) {
6092 bool isZero = !(NonZeros & (1 << i));
6094 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6096 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6099 for (unsigned i = 0; i < 2; ++i) {
6100 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6103 V[i] = V[i*2]; // Must be a zero vector.
6106 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6109 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6112 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6117 bool Reverse1 = (NonZeros & 0x3) == 2;
6118 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6122 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6123 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6125 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6128 if (Values.size() > 1 && VT.is128BitVector()) {
6129 // Check for a build vector of consecutive loads.
6130 for (unsigned i = 0; i < NumElems; ++i)
6131 V[i] = Op.getOperand(i);
6133 // Check for elements which are consecutive loads.
6134 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
6138 // Check for a build vector from mostly shuffle plus few inserting.
6139 SDValue Sh = buildFromShuffleMostly(Op, DAG);
6143 // For SSE 4.1, use insertps to put the high elements into the low element.
6144 if (getSubtarget()->hasSSE41()) {
6146 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6147 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6149 Result = DAG.getUNDEF(VT);
6151 for (unsigned i = 1; i < NumElems; ++i) {
6152 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6153 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6154 Op.getOperand(i), DAG.getIntPtrConstant(i));
6159 // Otherwise, expand into a number of unpckl*, start by extending each of
6160 // our (non-undef) elements to the full vector width with the element in the
6161 // bottom slot of the vector (which generates no code for SSE).
6162 for (unsigned i = 0; i < NumElems; ++i) {
6163 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6164 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6166 V[i] = DAG.getUNDEF(VT);
6169 // Next, we iteratively mix elements, e.g. for v4f32:
6170 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6171 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6172 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6173 unsigned EltStride = NumElems >> 1;
6174 while (EltStride != 0) {
6175 for (unsigned i = 0; i < EltStride; ++i) {
6176 // If V[i+EltStride] is undef and this is the first round of mixing,
6177 // then it is safe to just drop this shuffle: V[i] is already in the
6178 // right place, the one element (since it's the first round) being
6179 // inserted as undef can be dropped. This isn't safe for successive
6180 // rounds because they will permute elements within both vectors.
6181 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6182 EltStride == NumElems/2)
6185 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6194 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6195 // to create 256-bit vectors from two other 128-bit ones.
6196 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6198 MVT ResVT = Op.getSimpleValueType();
6200 assert((ResVT.is256BitVector() ||
6201 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6203 SDValue V1 = Op.getOperand(0);
6204 SDValue V2 = Op.getOperand(1);
6205 unsigned NumElems = ResVT.getVectorNumElements();
6206 if(ResVT.is256BitVector())
6207 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6209 if (Op.getNumOperands() == 4) {
6210 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6211 ResVT.getVectorNumElements()/2);
6212 SDValue V3 = Op.getOperand(2);
6213 SDValue V4 = Op.getOperand(3);
6214 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6215 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6217 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6220 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6221 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
6222 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6223 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6224 Op.getNumOperands() == 4)));
6226 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6227 // from two other 128-bit ones.
6229 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6230 return LowerAVXCONCAT_VECTORS(Op, DAG);
6233 // Try to lower a shuffle node into a simple blend instruction.
6235 LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
6236 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6237 SDValue V1 = SVOp->getOperand(0);
6238 SDValue V2 = SVOp->getOperand(1);
6240 MVT VT = SVOp->getSimpleValueType(0);
6241 MVT EltVT = VT.getVectorElementType();
6242 unsigned NumElems = VT.getVectorNumElements();
6244 // There is no blend with immediate in AVX-512.
6245 if (VT.is512BitVector())
6248 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
6250 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
6253 // Check the mask for BLEND and build the value.
6254 unsigned MaskValue = 0;
6255 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
6256 unsigned NumLanes = (NumElems-1)/8 + 1;
6257 unsigned NumElemsInLane = NumElems / NumLanes;
6259 // Blend for v16i16 should be symetric for the both lanes.
6260 for (unsigned i = 0; i < NumElemsInLane; ++i) {
6262 int SndLaneEltIdx = (NumLanes == 2) ?
6263 SVOp->getMaskElt(i + NumElemsInLane) : -1;
6264 int EltIdx = SVOp->getMaskElt(i);
6266 if ((EltIdx < 0 || EltIdx == (int)i) &&
6267 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
6270 if (((unsigned)EltIdx == (i + NumElems)) &&
6271 (SndLaneEltIdx < 0 ||
6272 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
6273 MaskValue |= (1<<i);
6278 // Convert i32 vectors to floating point if it is not AVX2.
6279 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
6281 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
6282 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
6284 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
6285 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
6288 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
6289 DAG.getConstant(MaskValue, MVT::i32));
6290 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
6293 // v8i16 shuffles - Prefer shuffles in the following order:
6294 // 1. [all] pshuflw, pshufhw, optional move
6295 // 2. [ssse3] 1 x pshufb
6296 // 3. [ssse3] 2 x pshufb + 1 x por
6297 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
6299 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
6300 SelectionDAG &DAG) {
6301 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6302 SDValue V1 = SVOp->getOperand(0);
6303 SDValue V2 = SVOp->getOperand(1);
6305 SmallVector<int, 8> MaskVals;
6307 // Determine if more than 1 of the words in each of the low and high quadwords
6308 // of the result come from the same quadword of one of the two inputs. Undef
6309 // mask values count as coming from any quadword, for better codegen.
6310 unsigned LoQuad[] = { 0, 0, 0, 0 };
6311 unsigned HiQuad[] = { 0, 0, 0, 0 };
6312 std::bitset<4> InputQuads;
6313 for (unsigned i = 0; i < 8; ++i) {
6314 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
6315 int EltIdx = SVOp->getMaskElt(i);
6316 MaskVals.push_back(EltIdx);
6325 InputQuads.set(EltIdx / 4);
6328 int BestLoQuad = -1;
6329 unsigned MaxQuad = 1;
6330 for (unsigned i = 0; i < 4; ++i) {
6331 if (LoQuad[i] > MaxQuad) {
6333 MaxQuad = LoQuad[i];
6337 int BestHiQuad = -1;
6339 for (unsigned i = 0; i < 4; ++i) {
6340 if (HiQuad[i] > MaxQuad) {
6342 MaxQuad = HiQuad[i];
6346 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
6347 // of the two input vectors, shuffle them into one input vector so only a
6348 // single pshufb instruction is necessary. If There are more than 2 input
6349 // quads, disable the next transformation since it does not help SSSE3.
6350 bool V1Used = InputQuads[0] || InputQuads[1];
6351 bool V2Used = InputQuads[2] || InputQuads[3];
6352 if (Subtarget->hasSSSE3()) {
6353 if (InputQuads.count() == 2 && V1Used && V2Used) {
6354 BestLoQuad = InputQuads[0] ? 0 : 1;
6355 BestHiQuad = InputQuads[2] ? 2 : 3;
6357 if (InputQuads.count() > 2) {
6363 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
6364 // the shuffle mask. If a quad is scored as -1, that means that it contains
6365 // words from all 4 input quadwords.
6367 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
6369 BestLoQuad < 0 ? 0 : BestLoQuad,
6370 BestHiQuad < 0 ? 1 : BestHiQuad
6372 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
6373 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
6374 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
6375 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
6377 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
6378 // source words for the shuffle, to aid later transformations.
6379 bool AllWordsInNewV = true;
6380 bool InOrder[2] = { true, true };
6381 for (unsigned i = 0; i != 8; ++i) {
6382 int idx = MaskVals[i];
6384 InOrder[i/4] = false;
6385 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
6387 AllWordsInNewV = false;
6391 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
6392 if (AllWordsInNewV) {
6393 for (int i = 0; i != 8; ++i) {
6394 int idx = MaskVals[i];
6397 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
6398 if ((idx != i) && idx < 4)
6400 if ((idx != i) && idx > 3)
6409 // If we've eliminated the use of V2, and the new mask is a pshuflw or
6410 // pshufhw, that's as cheap as it gets. Return the new shuffle.
6411 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
6412 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
6413 unsigned TargetMask = 0;
6414 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
6415 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
6416 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6417 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
6418 getShufflePSHUFLWImmediate(SVOp);
6419 V1 = NewV.getOperand(0);
6420 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
6424 // Promote splats to a larger type which usually leads to more efficient code.
6425 // FIXME: Is this true if pshufb is available?
6426 if (SVOp->isSplat())
6427 return PromoteSplat(SVOp, DAG);
6429 // If we have SSSE3, and all words of the result are from 1 input vector,
6430 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
6431 // is present, fall back to case 4.
6432 if (Subtarget->hasSSSE3()) {
6433 SmallVector<SDValue,16> pshufbMask;
6435 // If we have elements from both input vectors, set the high bit of the
6436 // shuffle mask element to zero out elements that come from V2 in the V1
6437 // mask, and elements that come from V1 in the V2 mask, so that the two
6438 // results can be OR'd together.
6439 bool TwoInputs = V1Used && V2Used;
6440 for (unsigned i = 0; i != 8; ++i) {
6441 int EltIdx = MaskVals[i] * 2;
6442 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
6443 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
6444 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6445 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6447 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
6448 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6449 DAG.getNode(ISD::BUILD_VECTOR, dl,
6450 MVT::v16i8, &pshufbMask[0], 16));
6452 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6454 // Calculate the shuffle mask for the second input, shuffle it, and
6455 // OR it with the first shuffled input.
6457 for (unsigned i = 0; i != 8; ++i) {
6458 int EltIdx = MaskVals[i] * 2;
6459 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6460 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
6461 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6462 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6464 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
6465 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6466 DAG.getNode(ISD::BUILD_VECTOR, dl,
6467 MVT::v16i8, &pshufbMask[0], 16));
6468 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6469 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6472 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
6473 // and update MaskVals with new element order.
6474 std::bitset<8> InOrder;
6475 if (BestLoQuad >= 0) {
6476 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
6477 for (int i = 0; i != 4; ++i) {
6478 int idx = MaskVals[i];
6481 } else if ((idx / 4) == BestLoQuad) {
6486 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6489 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6490 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6491 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
6493 getShufflePSHUFLWImmediate(SVOp), DAG);
6497 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
6498 // and update MaskVals with the new element order.
6499 if (BestHiQuad >= 0) {
6500 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
6501 for (unsigned i = 4; i != 8; ++i) {
6502 int idx = MaskVals[i];
6505 } else if ((idx / 4) == BestHiQuad) {
6506 MaskV[i] = (idx & 3) + 4;
6510 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6513 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6514 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6515 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
6517 getShufflePSHUFHWImmediate(SVOp), DAG);
6521 // In case BestHi & BestLo were both -1, which means each quadword has a word
6522 // from each of the four input quadwords, calculate the InOrder bitvector now
6523 // before falling through to the insert/extract cleanup.
6524 if (BestLoQuad == -1 && BestHiQuad == -1) {
6526 for (int i = 0; i != 8; ++i)
6527 if (MaskVals[i] < 0 || MaskVals[i] == i)
6531 // The other elements are put in the right place using pextrw and pinsrw.
6532 for (unsigned i = 0; i != 8; ++i) {
6535 int EltIdx = MaskVals[i];
6538 SDValue ExtOp = (EltIdx < 8) ?
6539 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
6540 DAG.getIntPtrConstant(EltIdx)) :
6541 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
6542 DAG.getIntPtrConstant(EltIdx - 8));
6543 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
6544 DAG.getIntPtrConstant(i));
6549 // v16i8 shuffles - Prefer shuffles in the following order:
6550 // 1. [ssse3] 1 x pshufb
6551 // 2. [ssse3] 2 x pshufb + 1 x por
6552 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
6553 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
6554 const X86Subtarget* Subtarget,
6555 SelectionDAG &DAG) {
6556 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6557 SDValue V1 = SVOp->getOperand(0);
6558 SDValue V2 = SVOp->getOperand(1);
6560 ArrayRef<int> MaskVals = SVOp->getMask();
6562 // Promote splats to a larger type which usually leads to more efficient code.
6563 // FIXME: Is this true if pshufb is available?
6564 if (SVOp->isSplat())
6565 return PromoteSplat(SVOp, DAG);
6567 // If we have SSSE3, case 1 is generated when all result bytes come from
6568 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
6569 // present, fall back to case 3.
6571 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
6572 if (Subtarget->hasSSSE3()) {
6573 SmallVector<SDValue,16> pshufbMask;
6575 // If all result elements are from one input vector, then only translate
6576 // undef mask values to 0x80 (zero out result) in the pshufb mask.
6578 // Otherwise, we have elements from both input vectors, and must zero out
6579 // elements that come from V2 in the first mask, and V1 in the second mask
6580 // so that we can OR them together.
6581 for (unsigned i = 0; i != 16; ++i) {
6582 int EltIdx = MaskVals[i];
6583 if (EltIdx < 0 || EltIdx >= 16)
6585 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6587 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6588 DAG.getNode(ISD::BUILD_VECTOR, dl,
6589 MVT::v16i8, &pshufbMask[0], 16));
6591 // As PSHUFB will zero elements with negative indices, it's safe to ignore
6592 // the 2nd operand if it's undefined or zero.
6593 if (V2.getOpcode() == ISD::UNDEF ||
6594 ISD::isBuildVectorAllZeros(V2.getNode()))
6597 // Calculate the shuffle mask for the second input, shuffle it, and
6598 // OR it with the first shuffled input.
6600 for (unsigned i = 0; i != 16; ++i) {
6601 int EltIdx = MaskVals[i];
6602 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6603 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6605 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6606 DAG.getNode(ISD::BUILD_VECTOR, dl,
6607 MVT::v16i8, &pshufbMask[0], 16));
6608 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6611 // No SSSE3 - Calculate in place words and then fix all out of place words
6612 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
6613 // the 16 different words that comprise the two doublequadword input vectors.
6614 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6615 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
6617 for (int i = 0; i != 8; ++i) {
6618 int Elt0 = MaskVals[i*2];
6619 int Elt1 = MaskVals[i*2+1];
6621 // This word of the result is all undef, skip it.
6622 if (Elt0 < 0 && Elt1 < 0)
6625 // This word of the result is already in the correct place, skip it.
6626 if ((Elt0 == i*2) && (Elt1 == i*2+1))
6629 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
6630 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
6633 // If Elt0 and Elt1 are defined, are consecutive, and can be load
6634 // using a single extract together, load it and store it.
6635 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
6636 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6637 DAG.getIntPtrConstant(Elt1 / 2));
6638 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6639 DAG.getIntPtrConstant(i));
6643 // If Elt1 is defined, extract it from the appropriate source. If the
6644 // source byte is not also odd, shift the extracted word left 8 bits
6645 // otherwise clear the bottom 8 bits if we need to do an or.
6647 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6648 DAG.getIntPtrConstant(Elt1 / 2));
6649 if ((Elt1 & 1) == 0)
6650 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
6652 TLI.getShiftAmountTy(InsElt.getValueType())));
6654 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
6655 DAG.getConstant(0xFF00, MVT::i16));
6657 // If Elt0 is defined, extract it from the appropriate source. If the
6658 // source byte is not also even, shift the extracted word right 8 bits. If
6659 // Elt1 was also defined, OR the extracted values together before
6660 // inserting them in the result.
6662 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
6663 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
6664 if ((Elt0 & 1) != 0)
6665 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
6667 TLI.getShiftAmountTy(InsElt0.getValueType())));
6669 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
6670 DAG.getConstant(0x00FF, MVT::i16));
6671 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
6674 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6675 DAG.getIntPtrConstant(i));
6677 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
6680 // v32i8 shuffles - Translate to VPSHUFB if possible.
6682 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
6683 const X86Subtarget *Subtarget,
6684 SelectionDAG &DAG) {
6685 MVT VT = SVOp->getSimpleValueType(0);
6686 SDValue V1 = SVOp->getOperand(0);
6687 SDValue V2 = SVOp->getOperand(1);
6689 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
6691 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6692 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
6693 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
6695 // VPSHUFB may be generated if
6696 // (1) one of input vector is undefined or zeroinitializer.
6697 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
6698 // And (2) the mask indexes don't cross the 128-bit lane.
6699 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
6700 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
6703 if (V1IsAllZero && !V2IsAllZero) {
6704 CommuteVectorShuffleMask(MaskVals, 32);
6707 SmallVector<SDValue, 32> pshufbMask;
6708 for (unsigned i = 0; i != 32; i++) {
6709 int EltIdx = MaskVals[i];
6710 if (EltIdx < 0 || EltIdx >= 32)
6713 if ((EltIdx >= 16 && i < 16) || (EltIdx < 16 && i >= 16))
6714 // Cross lane is not allowed.
6718 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6720 return DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, V1,
6721 DAG.getNode(ISD::BUILD_VECTOR, dl,
6722 MVT::v32i8, &pshufbMask[0], 32));
6725 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
6726 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
6727 /// done when every pair / quad of shuffle mask elements point to elements in
6728 /// the right sequence. e.g.
6729 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
6731 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
6732 SelectionDAG &DAG) {
6733 MVT VT = SVOp->getSimpleValueType(0);
6735 unsigned NumElems = VT.getVectorNumElements();
6738 switch (VT.SimpleTy) {
6739 default: llvm_unreachable("Unexpected!");
6740 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
6741 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
6742 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
6743 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
6744 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
6745 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
6748 SmallVector<int, 8> MaskVec;
6749 for (unsigned i = 0; i != NumElems; i += Scale) {
6751 for (unsigned j = 0; j != Scale; ++j) {
6752 int EltIdx = SVOp->getMaskElt(i+j);
6756 StartIdx = (EltIdx / Scale);
6757 if (EltIdx != (int)(StartIdx*Scale + j))
6760 MaskVec.push_back(StartIdx);
6763 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
6764 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
6765 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
6768 /// getVZextMovL - Return a zero-extending vector move low node.
6770 static SDValue getVZextMovL(MVT VT, MVT OpVT,
6771 SDValue SrcOp, SelectionDAG &DAG,
6772 const X86Subtarget *Subtarget, SDLoc dl) {
6773 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
6774 LoadSDNode *LD = NULL;
6775 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
6776 LD = dyn_cast<LoadSDNode>(SrcOp);
6778 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
6780 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
6781 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
6782 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6783 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
6784 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
6786 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
6787 return DAG.getNode(ISD::BITCAST, dl, VT,
6788 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6789 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6797 return DAG.getNode(ISD::BITCAST, dl, VT,
6798 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6799 DAG.getNode(ISD::BITCAST, dl,
6803 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
6804 /// which could not be matched by any known target speficic shuffle
6806 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6808 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
6809 if (NewOp.getNode())
6812 MVT VT = SVOp->getSimpleValueType(0);
6814 unsigned NumElems = VT.getVectorNumElements();
6815 unsigned NumLaneElems = NumElems / 2;
6818 MVT EltVT = VT.getVectorElementType();
6819 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6822 SmallVector<int, 16> Mask;
6823 for (unsigned l = 0; l < 2; ++l) {
6824 // Build a shuffle mask for the output, discovering on the fly which
6825 // input vectors to use as shuffle operands (recorded in InputUsed).
6826 // If building a suitable shuffle vector proves too hard, then bail
6827 // out with UseBuildVector set.
6828 bool UseBuildVector = false;
6829 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6830 unsigned LaneStart = l * NumLaneElems;
6831 for (unsigned i = 0; i != NumLaneElems; ++i) {
6832 // The mask element. This indexes into the input.
6833 int Idx = SVOp->getMaskElt(i+LaneStart);
6835 // the mask element does not index into any input vector.
6840 // The input vector this mask element indexes into.
6841 int Input = Idx / NumLaneElems;
6843 // Turn the index into an offset from the start of the input vector.
6844 Idx -= Input * NumLaneElems;
6846 // Find or create a shuffle vector operand to hold this input.
6848 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6849 if (InputUsed[OpNo] == Input)
6850 // This input vector is already an operand.
6852 if (InputUsed[OpNo] < 0) {
6853 // Create a new operand for this input vector.
6854 InputUsed[OpNo] = Input;
6859 if (OpNo >= array_lengthof(InputUsed)) {
6860 // More than two input vectors used! Give up on trying to create a
6861 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6862 UseBuildVector = true;
6866 // Add the mask index for the new shuffle vector.
6867 Mask.push_back(Idx + OpNo * NumLaneElems);
6870 if (UseBuildVector) {
6871 SmallVector<SDValue, 16> SVOps;
6872 for (unsigned i = 0; i != NumLaneElems; ++i) {
6873 // The mask element. This indexes into the input.
6874 int Idx = SVOp->getMaskElt(i+LaneStart);
6876 SVOps.push_back(DAG.getUNDEF(EltVT));
6880 // The input vector this mask element indexes into.
6881 int Input = Idx / NumElems;
6883 // Turn the index into an offset from the start of the input vector.
6884 Idx -= Input * NumElems;
6886 // Extract the vector element by hand.
6887 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6888 SVOp->getOperand(Input),
6889 DAG.getIntPtrConstant(Idx)));
6892 // Construct the output using a BUILD_VECTOR.
6893 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6895 } else if (InputUsed[0] < 0) {
6896 // No input vectors were used! The result is undefined.
6897 Output[l] = DAG.getUNDEF(NVT);
6899 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6900 (InputUsed[0] % 2) * NumLaneElems,
6902 // If only one input was used, use an undefined vector for the other.
6903 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6904 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6905 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6906 // At least one input vector was used. Create a new shuffle vector.
6907 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6913 // Concatenate the result back
6914 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6917 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6918 /// 4 elements, and match them with several different shuffle types.
6920 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6921 SDValue V1 = SVOp->getOperand(0);
6922 SDValue V2 = SVOp->getOperand(1);
6924 MVT VT = SVOp->getSimpleValueType(0);
6926 assert(VT.is128BitVector() && "Unsupported vector size");
6928 std::pair<int, int> Locs[4];
6929 int Mask1[] = { -1, -1, -1, -1 };
6930 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6934 for (unsigned i = 0; i != 4; ++i) {
6935 int Idx = PermMask[i];
6937 Locs[i] = std::make_pair(-1, -1);
6939 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6941 Locs[i] = std::make_pair(0, NumLo);
6945 Locs[i] = std::make_pair(1, NumHi);
6947 Mask1[2+NumHi] = Idx;
6953 if (NumLo <= 2 && NumHi <= 2) {
6954 // If no more than two elements come from either vector. This can be
6955 // implemented with two shuffles. First shuffle gather the elements.
6956 // The second shuffle, which takes the first shuffle as both of its
6957 // vector operands, put the elements into the right order.
6958 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6960 int Mask2[] = { -1, -1, -1, -1 };
6962 for (unsigned i = 0; i != 4; ++i)
6963 if (Locs[i].first != -1) {
6964 unsigned Idx = (i < 2) ? 0 : 4;
6965 Idx += Locs[i].first * 2 + Locs[i].second;
6969 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6972 if (NumLo == 3 || NumHi == 3) {
6973 // Otherwise, we must have three elements from one vector, call it X, and
6974 // one element from the other, call it Y. First, use a shufps to build an
6975 // intermediate vector with the one element from Y and the element from X
6976 // that will be in the same half in the final destination (the indexes don't
6977 // matter). Then, use a shufps to build the final vector, taking the half
6978 // containing the element from Y from the intermediate, and the other half
6981 // Normalize it so the 3 elements come from V1.
6982 CommuteVectorShuffleMask(PermMask, 4);
6986 // Find the element from V2.
6988 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6989 int Val = PermMask[HiIndex];
6996 Mask1[0] = PermMask[HiIndex];
6998 Mask1[2] = PermMask[HiIndex^1];
7000 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
7003 Mask1[0] = PermMask[0];
7004 Mask1[1] = PermMask[1];
7005 Mask1[2] = HiIndex & 1 ? 6 : 4;
7006 Mask1[3] = HiIndex & 1 ? 4 : 6;
7007 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
7010 Mask1[0] = HiIndex & 1 ? 2 : 0;
7011 Mask1[1] = HiIndex & 1 ? 0 : 2;
7012 Mask1[2] = PermMask[2];
7013 Mask1[3] = PermMask[3];
7018 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
7021 // Break it into (shuffle shuffle_hi, shuffle_lo).
7022 int LoMask[] = { -1, -1, -1, -1 };
7023 int HiMask[] = { -1, -1, -1, -1 };
7025 int *MaskPtr = LoMask;
7026 unsigned MaskIdx = 0;
7029 for (unsigned i = 0; i != 4; ++i) {
7036 int Idx = PermMask[i];
7038 Locs[i] = std::make_pair(-1, -1);
7039 } else if (Idx < 4) {
7040 Locs[i] = std::make_pair(MaskIdx, LoIdx);
7041 MaskPtr[LoIdx] = Idx;
7044 Locs[i] = std::make_pair(MaskIdx, HiIdx);
7045 MaskPtr[HiIdx] = Idx;
7050 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
7051 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
7052 int MaskOps[] = { -1, -1, -1, -1 };
7053 for (unsigned i = 0; i != 4; ++i)
7054 if (Locs[i].first != -1)
7055 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
7056 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
7059 static bool MayFoldVectorLoad(SDValue V) {
7060 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
7061 V = V.getOperand(0);
7063 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
7064 V = V.getOperand(0);
7065 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
7066 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
7067 // BUILD_VECTOR (load), undef
7068 V = V.getOperand(0);
7070 return MayFoldLoad(V);
7074 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
7075 MVT VT = Op.getSimpleValueType();
7077 // Canonizalize to v2f64.
7078 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
7079 return DAG.getNode(ISD::BITCAST, dl, VT,
7080 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
7085 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
7087 SDValue V1 = Op.getOperand(0);
7088 SDValue V2 = Op.getOperand(1);
7089 MVT VT = Op.getSimpleValueType();
7091 assert(VT != MVT::v2i64 && "unsupported shuffle type");
7093 if (HasSSE2 && VT == MVT::v2f64)
7094 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
7096 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
7097 return DAG.getNode(ISD::BITCAST, dl, VT,
7098 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
7099 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
7100 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
7104 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
7105 SDValue V1 = Op.getOperand(0);
7106 SDValue V2 = Op.getOperand(1);
7107 MVT VT = Op.getSimpleValueType();
7109 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
7110 "unsupported shuffle type");
7112 if (V2.getOpcode() == ISD::UNDEF)
7116 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
7120 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
7121 SDValue V1 = Op.getOperand(0);
7122 SDValue V2 = Op.getOperand(1);
7123 MVT VT = Op.getSimpleValueType();
7124 unsigned NumElems = VT.getVectorNumElements();
7126 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
7127 // operand of these instructions is only memory, so check if there's a
7128 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
7130 bool CanFoldLoad = false;
7132 // Trivial case, when V2 comes from a load.
7133 if (MayFoldVectorLoad(V2))
7136 // When V1 is a load, it can be folded later into a store in isel, example:
7137 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
7139 // (MOVLPSmr addr:$src1, VR128:$src2)
7140 // So, recognize this potential and also use MOVLPS or MOVLPD
7141 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
7144 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7146 if (HasSSE2 && NumElems == 2)
7147 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
7150 // If we don't care about the second element, proceed to use movss.
7151 if (SVOp->getMaskElt(1) != -1)
7152 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
7155 // movl and movlp will both match v2i64, but v2i64 is never matched by
7156 // movl earlier because we make it strict to avoid messing with the movlp load
7157 // folding logic (see the code above getMOVLP call). Match it here then,
7158 // this is horrible, but will stay like this until we move all shuffle
7159 // matching to x86 specific nodes. Note that for the 1st condition all
7160 // types are matched with movsd.
7162 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
7163 // as to remove this logic from here, as much as possible
7164 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
7165 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7166 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7169 assert(VT != MVT::v4i32 && "unsupported shuffle type");
7171 // Invert the operand order and use SHUFPS to match it.
7172 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
7173 getShuffleSHUFImmediate(SVOp), DAG);
7176 // Reduce a vector shuffle to zext.
7177 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
7178 SelectionDAG &DAG) {
7179 // PMOVZX is only available from SSE41.
7180 if (!Subtarget->hasSSE41())
7183 MVT VT = Op.getSimpleValueType();
7185 // Only AVX2 support 256-bit vector integer extending.
7186 if (!Subtarget->hasInt256() && VT.is256BitVector())
7189 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7191 SDValue V1 = Op.getOperand(0);
7192 SDValue V2 = Op.getOperand(1);
7193 unsigned NumElems = VT.getVectorNumElements();
7195 // Extending is an unary operation and the element type of the source vector
7196 // won't be equal to or larger than i64.
7197 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
7198 VT.getVectorElementType() == MVT::i64)
7201 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
7202 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
7203 while ((1U << Shift) < NumElems) {
7204 if (SVOp->getMaskElt(1U << Shift) == 1)
7207 // The maximal ratio is 8, i.e. from i8 to i64.
7212 // Check the shuffle mask.
7213 unsigned Mask = (1U << Shift) - 1;
7214 for (unsigned i = 0; i != NumElems; ++i) {
7215 int EltIdx = SVOp->getMaskElt(i);
7216 if ((i & Mask) != 0 && EltIdx != -1)
7218 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
7222 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
7223 MVT NeVT = MVT::getIntegerVT(NBits);
7224 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
7226 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
7229 // Simplify the operand as it's prepared to be fed into shuffle.
7230 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
7231 if (V1.getOpcode() == ISD::BITCAST &&
7232 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
7233 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
7234 V1.getOperand(0).getOperand(0)
7235 .getSimpleValueType().getSizeInBits() == SignificantBits) {
7236 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
7237 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
7238 ConstantSDNode *CIdx =
7239 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
7240 // If it's foldable, i.e. normal load with single use, we will let code
7241 // selection to fold it. Otherwise, we will short the conversion sequence.
7242 if (CIdx && CIdx->getZExtValue() == 0 &&
7243 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
7244 MVT FullVT = V.getSimpleValueType();
7245 MVT V1VT = V1.getSimpleValueType();
7246 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
7247 // The "ext_vec_elt" node is wider than the result node.
7248 // In this case we should extract subvector from V.
7249 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
7250 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
7251 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
7252 FullVT.getVectorNumElements()/Ratio);
7253 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
7254 DAG.getIntPtrConstant(0));
7256 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
7260 return DAG.getNode(ISD::BITCAST, DL, VT,
7261 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
7265 NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
7266 SelectionDAG &DAG) {
7267 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7268 MVT VT = Op.getSimpleValueType();
7270 SDValue V1 = Op.getOperand(0);
7271 SDValue V2 = Op.getOperand(1);
7273 if (isZeroShuffle(SVOp))
7274 return getZeroVector(VT, Subtarget, DAG, dl);
7276 // Handle splat operations
7277 if (SVOp->isSplat()) {
7278 // Use vbroadcast whenever the splat comes from a foldable load
7279 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
7280 if (Broadcast.getNode())
7284 // Check integer expanding shuffles.
7285 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
7286 if (NewOp.getNode())
7289 // If the shuffle can be profitably rewritten as a narrower shuffle, then
7291 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
7292 VT == MVT::v16i16 || VT == MVT::v32i8) {
7293 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7294 if (NewOp.getNode())
7295 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
7296 } else if ((VT == MVT::v4i32 ||
7297 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
7298 // FIXME: Figure out a cleaner way to do this.
7299 // Try to make use of movq to zero out the top part.
7300 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
7301 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7302 if (NewOp.getNode()) {
7303 MVT NewVT = NewOp.getSimpleValueType();
7304 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
7305 NewVT, true, false))
7306 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
7307 DAG, Subtarget, dl);
7309 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
7310 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7311 if (NewOp.getNode()) {
7312 MVT NewVT = NewOp.getSimpleValueType();
7313 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
7314 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
7315 DAG, Subtarget, dl);
7323 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
7324 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7325 SDValue V1 = Op.getOperand(0);
7326 SDValue V2 = Op.getOperand(1);
7327 MVT VT = Op.getSimpleValueType();
7329 unsigned NumElems = VT.getVectorNumElements();
7330 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
7331 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
7332 bool V1IsSplat = false;
7333 bool V2IsSplat = false;
7334 bool HasSSE2 = Subtarget->hasSSE2();
7335 bool HasFp256 = Subtarget->hasFp256();
7336 bool HasInt256 = Subtarget->hasInt256();
7337 MachineFunction &MF = DAG.getMachineFunction();
7338 bool OptForSize = MF.getFunction()->getAttributes().
7339 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
7341 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
7343 if (V1IsUndef && V2IsUndef)
7344 return DAG.getUNDEF(VT);
7346 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
7348 // Vector shuffle lowering takes 3 steps:
7350 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
7351 // narrowing and commutation of operands should be handled.
7352 // 2) Matching of shuffles with known shuffle masks to x86 target specific
7354 // 3) Rewriting of unmatched masks into new generic shuffle operations,
7355 // so the shuffle can be broken into other shuffles and the legalizer can
7356 // try the lowering again.
7358 // The general idea is that no vector_shuffle operation should be left to
7359 // be matched during isel, all of them must be converted to a target specific
7362 // Normalize the input vectors. Here splats, zeroed vectors, profitable
7363 // narrowing and commutation of operands should be handled. The actual code
7364 // doesn't include all of those, work in progress...
7365 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
7366 if (NewOp.getNode())
7369 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
7371 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
7372 // unpckh_undef). Only use pshufd if speed is more important than size.
7373 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7374 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7375 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7376 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7378 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
7379 V2IsUndef && MayFoldVectorLoad(V1))
7380 return getMOVDDup(Op, dl, V1, DAG);
7382 if (isMOVHLPS_v_undef_Mask(M, VT))
7383 return getMOVHighToLow(Op, dl, DAG);
7385 // Use to match splats
7386 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
7387 (VT == MVT::v2f64 || VT == MVT::v2i64))
7388 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7390 if (isPSHUFDMask(M, VT)) {
7391 // The actual implementation will match the mask in the if above and then
7392 // during isel it can match several different instructions, not only pshufd
7393 // as its name says, sad but true, emulate the behavior for now...
7394 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
7395 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
7397 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
7399 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
7400 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
7402 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
7403 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
7406 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
7410 if (isPALIGNRMask(M, VT, Subtarget))
7411 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
7412 getShufflePALIGNRImmediate(SVOp),
7415 // Check if this can be converted into a logical shift.
7416 bool isLeft = false;
7419 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
7420 if (isShift && ShVal.hasOneUse()) {
7421 // If the shifted value has multiple uses, it may be cheaper to use
7422 // v_set0 + movlhps or movhlps, etc.
7423 MVT EltVT = VT.getVectorElementType();
7424 ShAmt *= EltVT.getSizeInBits();
7425 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7428 if (isMOVLMask(M, VT)) {
7429 if (ISD::isBuildVectorAllZeros(V1.getNode()))
7430 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
7431 if (!isMOVLPMask(M, VT)) {
7432 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
7433 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7435 if (VT == MVT::v4i32 || VT == MVT::v4f32)
7436 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7440 // FIXME: fold these into legal mask.
7441 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
7442 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
7444 if (isMOVHLPSMask(M, VT))
7445 return getMOVHighToLow(Op, dl, DAG);
7447 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
7448 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
7450 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
7451 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
7453 if (isMOVLPMask(M, VT))
7454 return getMOVLP(Op, dl, DAG, HasSSE2);
7456 if (ShouldXformToMOVHLPS(M, VT) ||
7457 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
7458 return CommuteVectorShuffle(SVOp, DAG);
7461 // No better options. Use a vshldq / vsrldq.
7462 MVT EltVT = VT.getVectorElementType();
7463 ShAmt *= EltVT.getSizeInBits();
7464 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7467 bool Commuted = false;
7468 // FIXME: This should also accept a bitcast of a splat? Be careful, not
7469 // 1,1,1,1 -> v8i16 though.
7470 V1IsSplat = isSplatVector(V1.getNode());
7471 V2IsSplat = isSplatVector(V2.getNode());
7473 // Canonicalize the splat or undef, if present, to be on the RHS.
7474 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
7475 CommuteVectorShuffleMask(M, NumElems);
7477 std::swap(V1IsSplat, V2IsSplat);
7481 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
7482 // Shuffling low element of v1 into undef, just return v1.
7485 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
7486 // the instruction selector will not match, so get a canonical MOVL with
7487 // swapped operands to undo the commute.
7488 return getMOVL(DAG, dl, VT, V2, V1);
7491 if (isUNPCKLMask(M, VT, HasInt256))
7492 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7494 if (isUNPCKHMask(M, VT, HasInt256))
7495 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7498 // Normalize mask so all entries that point to V2 points to its first
7499 // element then try to match unpck{h|l} again. If match, return a
7500 // new vector_shuffle with the corrected mask.p
7501 SmallVector<int, 8> NewMask(M.begin(), M.end());
7502 NormalizeMask(NewMask, NumElems);
7503 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
7504 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7505 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
7506 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7510 // Commute is back and try unpck* again.
7511 // FIXME: this seems wrong.
7512 CommuteVectorShuffleMask(M, NumElems);
7514 std::swap(V1IsSplat, V2IsSplat);
7517 if (isUNPCKLMask(M, VT, HasInt256))
7518 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7520 if (isUNPCKHMask(M, VT, HasInt256))
7521 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7524 // Normalize the node to match x86 shuffle ops if needed
7525 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
7526 return CommuteVectorShuffle(SVOp, DAG);
7528 // The checks below are all present in isShuffleMaskLegal, but they are
7529 // inlined here right now to enable us to directly emit target specific
7530 // nodes, and remove one by one until they don't return Op anymore.
7532 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
7533 SVOp->getSplatIndex() == 0 && V2IsUndef) {
7534 if (VT == MVT::v2f64 || VT == MVT::v2i64)
7535 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7538 if (isPSHUFHWMask(M, VT, HasInt256))
7539 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
7540 getShufflePSHUFHWImmediate(SVOp),
7543 if (isPSHUFLWMask(M, VT, HasInt256))
7544 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
7545 getShufflePSHUFLWImmediate(SVOp),
7548 if (isSHUFPMask(M, VT))
7549 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
7550 getShuffleSHUFImmediate(SVOp), DAG);
7552 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7553 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7554 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7555 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7557 //===--------------------------------------------------------------------===//
7558 // Generate target specific nodes for 128 or 256-bit shuffles only
7559 // supported in the AVX instruction set.
7562 // Handle VMOVDDUPY permutations
7563 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
7564 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
7566 // Handle VPERMILPS/D* permutations
7567 if (isVPERMILPMask(M, VT)) {
7568 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
7569 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
7570 getShuffleSHUFImmediate(SVOp), DAG);
7571 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
7572 getShuffleSHUFImmediate(SVOp), DAG);
7575 // Handle VPERM2F128/VPERM2I128 permutations
7576 if (isVPERM2X128Mask(M, VT, HasFp256))
7577 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
7578 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
7580 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
7581 if (BlendOp.getNode())
7585 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
7586 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
7588 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
7589 VT.is512BitVector()) {
7590 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
7591 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
7592 SmallVector<SDValue, 16> permclMask;
7593 for (unsigned i = 0; i != NumElems; ++i) {
7594 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
7597 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT,
7598 &permclMask[0], NumElems);
7600 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
7601 return DAG.getNode(X86ISD::VPERMV, dl, VT,
7602 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
7603 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
7604 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
7607 //===--------------------------------------------------------------------===//
7608 // Since no target specific shuffle was selected for this generic one,
7609 // lower it into other known shuffles. FIXME: this isn't true yet, but
7610 // this is the plan.
7613 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
7614 if (VT == MVT::v8i16) {
7615 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
7616 if (NewOp.getNode())
7620 if (VT == MVT::v16i8) {
7621 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
7622 if (NewOp.getNode())
7626 if (VT == MVT::v32i8) {
7627 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
7628 if (NewOp.getNode())
7632 // Handle all 128-bit wide vectors with 4 elements, and match them with
7633 // several different shuffle types.
7634 if (NumElems == 4 && VT.is128BitVector())
7635 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
7637 // Handle general 256-bit shuffles
7638 if (VT.is256BitVector())
7639 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
7644 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7645 MVT VT = Op.getSimpleValueType();
7648 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
7651 if (VT.getSizeInBits() == 8) {
7652 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
7653 Op.getOperand(0), Op.getOperand(1));
7654 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7655 DAG.getValueType(VT));
7656 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7659 if (VT.getSizeInBits() == 16) {
7660 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7661 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
7663 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7664 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7665 DAG.getNode(ISD::BITCAST, dl,
7669 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
7670 Op.getOperand(0), Op.getOperand(1));
7671 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7672 DAG.getValueType(VT));
7673 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7676 if (VT == MVT::f32) {
7677 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
7678 // the result back to FR32 register. It's only worth matching if the
7679 // result has a single use which is a store or a bitcast to i32. And in
7680 // the case of a store, it's not worth it if the index is a constant 0,
7681 // because a MOVSSmr can be used instead, which is smaller and faster.
7682 if (!Op.hasOneUse())
7684 SDNode *User = *Op.getNode()->use_begin();
7685 if ((User->getOpcode() != ISD::STORE ||
7686 (isa<ConstantSDNode>(Op.getOperand(1)) &&
7687 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
7688 (User->getOpcode() != ISD::BITCAST ||
7689 User->getValueType(0) != MVT::i32))
7691 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7692 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
7695 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
7698 if (VT == MVT::i32 || VT == MVT::i64) {
7699 // ExtractPS/pextrq works with constant index.
7700 if (isa<ConstantSDNode>(Op.getOperand(1)))
7706 /// Extract one bit from mask vector, like v16i1 or v8i1.
7707 /// AVX-512 feature.
7708 static SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) {
7709 SDValue Vec = Op.getOperand(0);
7711 MVT VecVT = Vec.getSimpleValueType();
7712 SDValue Idx = Op.getOperand(1);
7713 MVT EltVT = Op.getSimpleValueType();
7715 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
7717 // variable index can't be handled in mask registers,
7718 // extend vector to VR512
7719 if (!isa<ConstantSDNode>(Idx)) {
7720 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
7721 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
7722 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
7723 ExtVT.getVectorElementType(), Ext, Idx);
7724 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
7727 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7729 unsigned MaxSift = VecVT.getSizeInBits() - 1;
7730 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
7731 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
7732 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
7733 DAG.getConstant(MaxSift, MVT::i8));
7735 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i1, Vec,
7736 DAG.getIntPtrConstant(0));
7740 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7741 SelectionDAG &DAG) const {
7743 SDValue Vec = Op.getOperand(0);
7744 MVT VecVT = Vec.getSimpleValueType();
7745 SDValue Idx = Op.getOperand(1);
7747 if (Op.getSimpleValueType() == MVT::i1)
7748 return ExtractBitFromMaskVector(Op, DAG);
7750 if (!isa<ConstantSDNode>(Idx)) {
7751 if (VecVT.is512BitVector() ||
7752 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
7753 VecVT.getVectorElementType().getSizeInBits() == 32)) {
7756 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
7757 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
7758 MaskEltVT.getSizeInBits());
7760 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
7761 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
7762 getZeroVector(MaskVT, Subtarget, DAG, dl),
7763 Idx, DAG.getConstant(0, getPointerTy()));
7764 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
7765 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
7766 Perm, DAG.getConstant(0, getPointerTy()));
7771 // If this is a 256-bit vector result, first extract the 128-bit vector and
7772 // then extract the element from the 128-bit vector.
7773 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
7775 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7776 // Get the 128-bit vector.
7777 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
7778 MVT EltVT = VecVT.getVectorElementType();
7780 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
7782 //if (IdxVal >= NumElems/2)
7783 // IdxVal -= NumElems/2;
7784 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
7785 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
7786 DAG.getConstant(IdxVal, MVT::i32));
7789 assert(VecVT.is128BitVector() && "Unexpected vector length");
7791 if (Subtarget->hasSSE41()) {
7792 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
7797 MVT VT = Op.getSimpleValueType();
7798 // TODO: handle v16i8.
7799 if (VT.getSizeInBits() == 16) {
7800 SDValue Vec = Op.getOperand(0);
7801 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7803 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7804 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7805 DAG.getNode(ISD::BITCAST, dl,
7808 // Transform it so it match pextrw which produces a 32-bit result.
7809 MVT EltVT = MVT::i32;
7810 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
7811 Op.getOperand(0), Op.getOperand(1));
7812 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
7813 DAG.getValueType(VT));
7814 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7817 if (VT.getSizeInBits() == 32) {
7818 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7822 // SHUFPS the element to the lowest double word, then movss.
7823 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
7824 MVT VVT = Op.getOperand(0).getSimpleValueType();
7825 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7826 DAG.getUNDEF(VVT), Mask);
7827 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7828 DAG.getIntPtrConstant(0));
7831 if (VT.getSizeInBits() == 64) {
7832 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
7833 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
7834 // to match extract_elt for f64.
7835 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7839 // UNPCKHPD the element to the lowest double word, then movsd.
7840 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
7841 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
7842 int Mask[2] = { 1, -1 };
7843 MVT VVT = Op.getOperand(0).getSimpleValueType();
7844 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7845 DAG.getUNDEF(VVT), Mask);
7846 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7847 DAG.getIntPtrConstant(0));
7853 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7854 MVT VT = Op.getSimpleValueType();
7855 MVT EltVT = VT.getVectorElementType();
7858 SDValue N0 = Op.getOperand(0);
7859 SDValue N1 = Op.getOperand(1);
7860 SDValue N2 = Op.getOperand(2);
7862 if (!VT.is128BitVector())
7865 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
7866 isa<ConstantSDNode>(N2)) {
7868 if (VT == MVT::v8i16)
7869 Opc = X86ISD::PINSRW;
7870 else if (VT == MVT::v16i8)
7871 Opc = X86ISD::PINSRB;
7873 Opc = X86ISD::PINSRB;
7875 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
7877 if (N1.getValueType() != MVT::i32)
7878 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7879 if (N2.getValueType() != MVT::i32)
7880 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7881 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7884 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
7885 // Bits [7:6] of the constant are the source select. This will always be
7886 // zero here. The DAG Combiner may combine an extract_elt index into these
7887 // bits. For example (insert (extract, 3), 2) could be matched by putting
7888 // the '3' into bits [7:6] of X86ISD::INSERTPS.
7889 // Bits [5:4] of the constant are the destination select. This is the
7890 // value of the incoming immediate.
7891 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
7892 // combine either bitwise AND or insert of float 0.0 to set these bits.
7893 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
7894 // Create this as a scalar to vector..
7895 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7896 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7899 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
7900 // PINSR* works with constant index.
7907 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7908 MVT VT = Op.getSimpleValueType();
7909 MVT EltVT = VT.getVectorElementType();
7912 SDValue N0 = Op.getOperand(0);
7913 SDValue N1 = Op.getOperand(1);
7914 SDValue N2 = Op.getOperand(2);
7916 // If this is a 256-bit vector result, first extract the 128-bit vector,
7917 // insert the element into the extracted half and then place it back.
7918 if (VT.is256BitVector() || VT.is512BitVector()) {
7919 if (!isa<ConstantSDNode>(N2))
7922 // Get the desired 128-bit vector half.
7923 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7924 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
7926 // Insert the element into the desired half.
7927 unsigned NumEltsIn128 = 128/EltVT.getSizeInBits();
7928 unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128;
7930 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
7931 DAG.getConstant(IdxIn128, MVT::i32));
7933 // Insert the changed part back to the 256-bit vector
7934 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
7937 if (Subtarget->hasSSE41())
7938 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7940 if (EltVT == MVT::i8)
7943 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7944 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7945 // as its second argument.
7946 if (N1.getValueType() != MVT::i32)
7947 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7948 if (N2.getValueType() != MVT::i32)
7949 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7950 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7955 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
7957 MVT OpVT = Op.getSimpleValueType();
7959 // If this is a 256-bit vector result, first insert into a 128-bit
7960 // vector and then insert into the 256-bit vector.
7961 if (!OpVT.is128BitVector()) {
7962 // Insert into a 128-bit vector.
7963 unsigned SizeFactor = OpVT.getSizeInBits()/128;
7964 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
7965 OpVT.getVectorNumElements() / SizeFactor);
7967 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7969 // Insert the 128-bit vector.
7970 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
7973 if (OpVT == MVT::v1i64 &&
7974 Op.getOperand(0).getValueType() == MVT::i64)
7975 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7977 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7978 assert(OpVT.is128BitVector() && "Expected an SSE type!");
7979 return DAG.getNode(ISD::BITCAST, dl, OpVT,
7980 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7983 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7984 // a simple subregister reference or explicit instructions to grab
7985 // upper bits of a vector.
7986 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7987 SelectionDAG &DAG) {
7989 SDValue In = Op.getOperand(0);
7990 SDValue Idx = Op.getOperand(1);
7991 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7992 MVT ResVT = Op.getSimpleValueType();
7993 MVT InVT = In.getSimpleValueType();
7995 if (Subtarget->hasFp256()) {
7996 if (ResVT.is128BitVector() &&
7997 (InVT.is256BitVector() || InVT.is512BitVector()) &&
7998 isa<ConstantSDNode>(Idx)) {
7999 return Extract128BitVector(In, IdxVal, DAG, dl);
8001 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
8002 isa<ConstantSDNode>(Idx)) {
8003 return Extract256BitVector(In, IdxVal, DAG, dl);
8009 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
8010 // simple superregister reference or explicit instructions to insert
8011 // the upper bits of a vector.
8012 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
8013 SelectionDAG &DAG) {
8014 if (Subtarget->hasFp256()) {
8015 SDLoc dl(Op.getNode());
8016 SDValue Vec = Op.getNode()->getOperand(0);
8017 SDValue SubVec = Op.getNode()->getOperand(1);
8018 SDValue Idx = Op.getNode()->getOperand(2);
8020 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
8021 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
8022 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
8023 isa<ConstantSDNode>(Idx)) {
8024 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
8025 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
8028 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
8029 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
8030 isa<ConstantSDNode>(Idx)) {
8031 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
8032 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
8038 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
8039 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
8040 // one of the above mentioned nodes. It has to be wrapped because otherwise
8041 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
8042 // be used to form addressing mode. These wrapped nodes will be selected
8045 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
8046 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
8048 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8050 unsigned char OpFlag = 0;
8051 unsigned WrapperKind = X86ISD::Wrapper;
8052 CodeModel::Model M = getTargetMachine().getCodeModel();
8054 if (Subtarget->isPICStyleRIPRel() &&
8055 (M == CodeModel::Small || M == CodeModel::Kernel))
8056 WrapperKind = X86ISD::WrapperRIP;
8057 else if (Subtarget->isPICStyleGOT())
8058 OpFlag = X86II::MO_GOTOFF;
8059 else if (Subtarget->isPICStyleStubPIC())
8060 OpFlag = X86II::MO_PIC_BASE_OFFSET;
8062 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
8064 CP->getOffset(), OpFlag);
8066 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8067 // With PIC, the address is actually $g + Offset.
8069 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8070 DAG.getNode(X86ISD::GlobalBaseReg,
8071 SDLoc(), getPointerTy()),
8078 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
8079 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
8081 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8083 unsigned char OpFlag = 0;
8084 unsigned WrapperKind = X86ISD::Wrapper;
8085 CodeModel::Model M = getTargetMachine().getCodeModel();
8087 if (Subtarget->isPICStyleRIPRel() &&
8088 (M == CodeModel::Small || M == CodeModel::Kernel))
8089 WrapperKind = X86ISD::WrapperRIP;
8090 else if (Subtarget->isPICStyleGOT())
8091 OpFlag = X86II::MO_GOTOFF;
8092 else if (Subtarget->isPICStyleStubPIC())
8093 OpFlag = X86II::MO_PIC_BASE_OFFSET;
8095 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
8098 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8100 // With PIC, the address is actually $g + Offset.
8102 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8103 DAG.getNode(X86ISD::GlobalBaseReg,
8104 SDLoc(), getPointerTy()),
8111 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
8112 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
8114 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8116 unsigned char OpFlag = 0;
8117 unsigned WrapperKind = X86ISD::Wrapper;
8118 CodeModel::Model M = getTargetMachine().getCodeModel();
8120 if (Subtarget->isPICStyleRIPRel() &&
8121 (M == CodeModel::Small || M == CodeModel::Kernel)) {
8122 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
8123 OpFlag = X86II::MO_GOTPCREL;
8124 WrapperKind = X86ISD::WrapperRIP;
8125 } else if (Subtarget->isPICStyleGOT()) {
8126 OpFlag = X86II::MO_GOT;
8127 } else if (Subtarget->isPICStyleStubPIC()) {
8128 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
8129 } else if (Subtarget->isPICStyleStubNoDynamic()) {
8130 OpFlag = X86II::MO_DARWIN_NONLAZY;
8133 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
8136 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8138 // With PIC, the address is actually $g + Offset.
8139 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
8140 !Subtarget->is64Bit()) {
8141 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8142 DAG.getNode(X86ISD::GlobalBaseReg,
8143 SDLoc(), getPointerTy()),
8147 // For symbols that require a load from a stub to get the address, emit the
8149 if (isGlobalStubReference(OpFlag))
8150 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
8151 MachinePointerInfo::getGOT(), false, false, false, 0);
8157 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
8158 // Create the TargetBlockAddressAddress node.
8159 unsigned char OpFlags =
8160 Subtarget->ClassifyBlockAddressReference();
8161 CodeModel::Model M = getTargetMachine().getCodeModel();
8162 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
8163 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
8165 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
8168 if (Subtarget->isPICStyleRIPRel() &&
8169 (M == CodeModel::Small || M == CodeModel::Kernel))
8170 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8172 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8174 // With PIC, the address is actually $g + Offset.
8175 if (isGlobalRelativeToPICBase(OpFlags)) {
8176 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8177 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8185 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
8186 int64_t Offset, SelectionDAG &DAG) const {
8187 // Create the TargetGlobalAddress node, folding in the constant
8188 // offset if it is legal.
8189 unsigned char OpFlags =
8190 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
8191 CodeModel::Model M = getTargetMachine().getCodeModel();
8193 if (OpFlags == X86II::MO_NO_FLAG &&
8194 X86::isOffsetSuitableForCodeModel(Offset, M)) {
8195 // A direct static reference to a global.
8196 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
8199 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
8202 if (Subtarget->isPICStyleRIPRel() &&
8203 (M == CodeModel::Small || M == CodeModel::Kernel))
8204 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8206 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8208 // With PIC, the address is actually $g + Offset.
8209 if (isGlobalRelativeToPICBase(OpFlags)) {
8210 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8211 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8215 // For globals that require a load from a stub to get the address, emit the
8217 if (isGlobalStubReference(OpFlags))
8218 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
8219 MachinePointerInfo::getGOT(), false, false, false, 0);
8221 // If there was a non-zero offset that we didn't fold, create an explicit
8224 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
8225 DAG.getConstant(Offset, getPointerTy()));
8231 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
8232 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
8233 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
8234 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
8238 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
8239 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
8240 unsigned char OperandFlags, bool LocalDynamic = false) {
8241 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8242 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8244 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8245 GA->getValueType(0),
8249 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
8253 SDValue Ops[] = { Chain, TGA, *InFlag };
8254 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8256 SDValue Ops[] = { Chain, TGA };
8257 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8260 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
8261 MFI->setAdjustsStack(true);
8263 SDValue Flag = Chain.getValue(1);
8264 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
8267 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
8269 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8272 SDLoc dl(GA); // ? function entry point might be better
8273 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8274 DAG.getNode(X86ISD::GlobalBaseReg,
8275 SDLoc(), PtrVT), InFlag);
8276 InFlag = Chain.getValue(1);
8278 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
8281 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
8283 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8285 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
8286 X86::RAX, X86II::MO_TLSGD);
8289 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
8295 // Get the start address of the TLS block for this module.
8296 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
8297 .getInfo<X86MachineFunctionInfo>();
8298 MFI->incNumLocalDynamicTLSAccesses();
8302 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
8303 X86II::MO_TLSLD, /*LocalDynamic=*/true);
8306 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8307 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
8308 InFlag = Chain.getValue(1);
8309 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
8310 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
8313 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
8317 unsigned char OperandFlags = X86II::MO_DTPOFF;
8318 unsigned WrapperKind = X86ISD::Wrapper;
8319 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8320 GA->getValueType(0),
8321 GA->getOffset(), OperandFlags);
8322 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8324 // Add x@dtpoff with the base.
8325 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
8328 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
8329 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8330 const EVT PtrVT, TLSModel::Model model,
8331 bool is64Bit, bool isPIC) {
8334 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
8335 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
8336 is64Bit ? 257 : 256));
8338 SDValue ThreadPointer =
8339 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
8340 MachinePointerInfo(Ptr), false, false, false, 0);
8342 unsigned char OperandFlags = 0;
8343 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
8345 unsigned WrapperKind = X86ISD::Wrapper;
8346 if (model == TLSModel::LocalExec) {
8347 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
8348 } else if (model == TLSModel::InitialExec) {
8350 OperandFlags = X86II::MO_GOTTPOFF;
8351 WrapperKind = X86ISD::WrapperRIP;
8353 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
8356 llvm_unreachable("Unexpected model");
8359 // emit "addl x@ntpoff,%eax" (local exec)
8360 // or "addl x@indntpoff,%eax" (initial exec)
8361 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
8363 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
8364 GA->getOffset(), OperandFlags);
8365 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8367 if (model == TLSModel::InitialExec) {
8368 if (isPIC && !is64Bit) {
8369 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
8370 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
8374 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
8375 MachinePointerInfo::getGOT(), false, false, false, 0);
8378 // The address of the thread local variable is the add of the thread
8379 // pointer with the offset of the variable.
8380 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
8384 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
8386 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
8387 const GlobalValue *GV = GA->getGlobal();
8389 if (Subtarget->isTargetELF()) {
8390 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
8393 case TLSModel::GeneralDynamic:
8394 if (Subtarget->is64Bit())
8395 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
8396 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
8397 case TLSModel::LocalDynamic:
8398 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
8399 Subtarget->is64Bit());
8400 case TLSModel::InitialExec:
8401 case TLSModel::LocalExec:
8402 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
8403 Subtarget->is64Bit(),
8404 getTargetMachine().getRelocationModel() == Reloc::PIC_);
8406 llvm_unreachable("Unknown TLS model.");
8409 if (Subtarget->isTargetDarwin()) {
8410 // Darwin only has one model of TLS. Lower to that.
8411 unsigned char OpFlag = 0;
8412 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
8413 X86ISD::WrapperRIP : X86ISD::Wrapper;
8415 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8417 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
8418 !Subtarget->is64Bit();
8420 OpFlag = X86II::MO_TLVP_PIC_BASE;
8422 OpFlag = X86II::MO_TLVP;
8424 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
8425 GA->getValueType(0),
8426 GA->getOffset(), OpFlag);
8427 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8429 // With PIC32, the address is actually $g + Offset.
8431 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8432 DAG.getNode(X86ISD::GlobalBaseReg,
8433 SDLoc(), getPointerTy()),
8436 // Lowering the machine isd will make sure everything is in the right
8438 SDValue Chain = DAG.getEntryNode();
8439 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8440 SDValue Args[] = { Chain, Offset };
8441 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
8443 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
8444 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8445 MFI->setAdjustsStack(true);
8447 // And our return value (tls address) is in the standard call return value
8449 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
8450 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
8454 if (Subtarget->isTargetWindows() || Subtarget->isTargetMingw()) {
8455 // Just use the implicit TLS architecture
8456 // Need to generate someting similar to:
8457 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
8459 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
8460 // mov rcx, qword [rdx+rcx*8]
8461 // mov eax, .tls$:tlsvar
8462 // [rax+rcx] contains the address
8463 // Windows 64bit: gs:0x58
8464 // Windows 32bit: fs:__tls_array
8466 // If GV is an alias then use the aliasee for determining
8467 // thread-localness.
8468 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
8469 GV = GA->resolveAliasedGlobal(false);
8471 SDValue Chain = DAG.getEntryNode();
8473 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
8474 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
8475 // use its literal value of 0x2C.
8476 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
8477 ? Type::getInt8PtrTy(*DAG.getContext(),
8479 : Type::getInt32PtrTy(*DAG.getContext(),
8482 SDValue TlsArray = Subtarget->is64Bit() ? DAG.getIntPtrConstant(0x58) :
8483 (Subtarget->isTargetMingw() ? DAG.getIntPtrConstant(0x2C) :
8484 DAG.getExternalSymbol("_tls_array", getPointerTy()));
8486 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
8487 MachinePointerInfo(Ptr),
8488 false, false, false, 0);
8490 // Load the _tls_index variable
8491 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
8492 if (Subtarget->is64Bit())
8493 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
8494 IDX, MachinePointerInfo(), MVT::i32,
8497 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
8498 false, false, false, 0);
8500 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
8502 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
8504 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
8505 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
8506 false, false, false, 0);
8508 // Get the offset of start of .tls section
8509 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8510 GA->getValueType(0),
8511 GA->getOffset(), X86II::MO_SECREL);
8512 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
8514 // The address of the thread local variable is the add of the thread
8515 // pointer with the offset of the variable.
8516 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
8519 llvm_unreachable("TLS not implemented for this target.");
8522 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
8523 /// and take a 2 x i32 value to shift plus a shift amount.
8524 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
8525 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
8526 MVT VT = Op.getSimpleValueType();
8527 unsigned VTBits = VT.getSizeInBits();
8529 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
8530 SDValue ShOpLo = Op.getOperand(0);
8531 SDValue ShOpHi = Op.getOperand(1);
8532 SDValue ShAmt = Op.getOperand(2);
8533 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
8534 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
8536 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
8537 DAG.getConstant(VTBits - 1, MVT::i8));
8538 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
8539 DAG.getConstant(VTBits - 1, MVT::i8))
8540 : DAG.getConstant(0, VT);
8543 if (Op.getOpcode() == ISD::SHL_PARTS) {
8544 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
8545 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
8547 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
8548 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
8551 // If the shift amount is larger or equal than the width of a part we can't
8552 // rely on the results of shld/shrd. Insert a test and select the appropriate
8553 // values for large shift amounts.
8554 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
8555 DAG.getConstant(VTBits, MVT::i8));
8556 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8557 AndNode, DAG.getConstant(0, MVT::i8));
8560 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8561 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
8562 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
8564 if (Op.getOpcode() == ISD::SHL_PARTS) {
8565 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8566 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8568 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8569 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8572 SDValue Ops[2] = { Lo, Hi };
8573 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
8576 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
8577 SelectionDAG &DAG) const {
8578 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
8580 if (SrcVT.isVector())
8583 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
8584 "Unknown SINT_TO_FP to lower!");
8586 // These are really Legal; return the operand so the caller accepts it as
8588 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
8590 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
8591 Subtarget->is64Bit()) {
8596 unsigned Size = SrcVT.getSizeInBits()/8;
8597 MachineFunction &MF = DAG.getMachineFunction();
8598 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
8599 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8600 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8602 MachinePointerInfo::getFixedStack(SSFI),
8604 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
8607 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
8609 SelectionDAG &DAG) const {
8613 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
8615 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
8617 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
8619 unsigned ByteSize = SrcVT.getSizeInBits()/8;
8621 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
8622 MachineMemOperand *MMO;
8624 int SSFI = FI->getIndex();
8626 DAG.getMachineFunction()
8627 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8628 MachineMemOperand::MOLoad, ByteSize, ByteSize);
8630 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
8631 StackSlot = StackSlot.getOperand(1);
8633 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
8634 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
8636 Tys, Ops, array_lengthof(Ops),
8640 Chain = Result.getValue(1);
8641 SDValue InFlag = Result.getValue(2);
8643 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
8644 // shouldn't be necessary except that RFP cannot be live across
8645 // multiple blocks. When stackifier is fixed, they can be uncoupled.
8646 MachineFunction &MF = DAG.getMachineFunction();
8647 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
8648 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
8649 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8650 Tys = DAG.getVTList(MVT::Other);
8652 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
8654 MachineMemOperand *MMO =
8655 DAG.getMachineFunction()
8656 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8657 MachineMemOperand::MOStore, SSFISize, SSFISize);
8659 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
8660 Ops, array_lengthof(Ops),
8661 Op.getValueType(), MMO);
8662 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
8663 MachinePointerInfo::getFixedStack(SSFI),
8664 false, false, false, 0);
8670 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
8671 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
8672 SelectionDAG &DAG) const {
8673 // This algorithm is not obvious. Here it is what we're trying to output:
8676 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
8677 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
8681 pshufd $0x4e, %xmm0, %xmm1
8687 LLVMContext *Context = DAG.getContext();
8689 // Build some magic constants.
8690 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
8691 Constant *C0 = ConstantDataVector::get(*Context, CV0);
8692 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
8694 SmallVector<Constant*,2> CV1;
8696 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8697 APInt(64, 0x4330000000000000ULL))));
8699 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8700 APInt(64, 0x4530000000000000ULL))));
8701 Constant *C1 = ConstantVector::get(CV1);
8702 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
8704 // Load the 64-bit value into an XMM register.
8705 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
8707 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
8708 MachinePointerInfo::getConstantPool(),
8709 false, false, false, 16);
8710 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
8711 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
8714 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
8715 MachinePointerInfo::getConstantPool(),
8716 false, false, false, 16);
8717 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
8718 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
8721 if (Subtarget->hasSSE3()) {
8722 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
8723 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
8725 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
8726 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
8728 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
8729 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
8733 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
8734 DAG.getIntPtrConstant(0));
8737 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
8738 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
8739 SelectionDAG &DAG) const {
8741 // FP constant to bias correct the final result.
8742 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
8745 // Load the 32-bit value into an XMM register.
8746 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
8749 // Zero out the upper parts of the register.
8750 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
8752 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8753 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
8754 DAG.getIntPtrConstant(0));
8756 // Or the load with the bias.
8757 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
8758 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8759 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8761 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8762 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8763 MVT::v2f64, Bias)));
8764 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8765 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
8766 DAG.getIntPtrConstant(0));
8768 // Subtract the bias.
8769 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
8771 // Handle final rounding.
8772 EVT DestVT = Op.getValueType();
8774 if (DestVT.bitsLT(MVT::f64))
8775 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
8776 DAG.getIntPtrConstant(0));
8777 if (DestVT.bitsGT(MVT::f64))
8778 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
8780 // Handle final rounding.
8784 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
8785 SelectionDAG &DAG) const {
8786 SDValue N0 = Op.getOperand(0);
8787 MVT SVT = N0.getSimpleValueType();
8790 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
8791 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
8792 "Custom UINT_TO_FP is not supported!");
8794 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
8795 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
8796 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
8799 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
8800 SelectionDAG &DAG) const {
8801 SDValue N0 = Op.getOperand(0);
8804 if (Op.getValueType().isVector())
8805 return lowerUINT_TO_FP_vec(Op, DAG);
8807 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
8808 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
8809 // the optimization here.
8810 if (DAG.SignBitIsZero(N0))
8811 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
8813 MVT SrcVT = N0.getSimpleValueType();
8814 MVT DstVT = Op.getSimpleValueType();
8815 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
8816 return LowerUINT_TO_FP_i64(Op, DAG);
8817 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
8818 return LowerUINT_TO_FP_i32(Op, DAG);
8819 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
8822 // Make a 64-bit buffer, and use it to build an FILD.
8823 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
8824 if (SrcVT == MVT::i32) {
8825 SDValue WordOff = DAG.getConstant(4, getPointerTy());
8826 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
8827 getPointerTy(), StackSlot, WordOff);
8828 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8829 StackSlot, MachinePointerInfo(),
8831 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
8832 OffsetSlot, MachinePointerInfo(),
8834 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
8838 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
8839 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8840 StackSlot, MachinePointerInfo(),
8842 // For i64 source, we need to add the appropriate power of 2 if the input
8843 // was negative. This is the same as the optimization in
8844 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
8845 // we must be careful to do the computation in x87 extended precision, not
8846 // in SSE. (The generic code can't know it's OK to do this, or how to.)
8847 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
8848 MachineMemOperand *MMO =
8849 DAG.getMachineFunction()
8850 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8851 MachineMemOperand::MOLoad, 8, 8);
8853 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
8854 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
8855 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
8856 array_lengthof(Ops), MVT::i64, MMO);
8858 APInt FF(32, 0x5F800000ULL);
8860 // Check whether the sign bit is set.
8861 SDValue SignSet = DAG.getSetCC(dl,
8862 getSetCCResultType(*DAG.getContext(), MVT::i64),
8863 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
8866 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
8867 SDValue FudgePtr = DAG.getConstantPool(
8868 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
8871 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
8872 SDValue Zero = DAG.getIntPtrConstant(0);
8873 SDValue Four = DAG.getIntPtrConstant(4);
8874 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
8876 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
8878 // Load the value out, extending it from f32 to f80.
8879 // FIXME: Avoid the extend by constructing the right constant pool?
8880 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
8881 FudgePtr, MachinePointerInfo::getConstantPool(),
8882 MVT::f32, false, false, 4);
8883 // Extend everything to 80 bits to force it to be done on x87.
8884 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
8885 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
8888 std::pair<SDValue,SDValue>
8889 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
8890 bool IsSigned, bool IsReplace) const {
8893 EVT DstTy = Op.getValueType();
8895 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
8896 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
8900 assert(DstTy.getSimpleVT() <= MVT::i64 &&
8901 DstTy.getSimpleVT() >= MVT::i16 &&
8902 "Unknown FP_TO_INT to lower!");
8904 // These are really Legal.
8905 if (DstTy == MVT::i32 &&
8906 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8907 return std::make_pair(SDValue(), SDValue());
8908 if (Subtarget->is64Bit() &&
8909 DstTy == MVT::i64 &&
8910 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8911 return std::make_pair(SDValue(), SDValue());
8913 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
8914 // stack slot, or into the FTOL runtime function.
8915 MachineFunction &MF = DAG.getMachineFunction();
8916 unsigned MemSize = DstTy.getSizeInBits()/8;
8917 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8918 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8921 if (!IsSigned && isIntegerTypeFTOL(DstTy))
8922 Opc = X86ISD::WIN_FTOL;
8924 switch (DstTy.getSimpleVT().SimpleTy) {
8925 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
8926 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
8927 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
8928 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
8931 SDValue Chain = DAG.getEntryNode();
8932 SDValue Value = Op.getOperand(0);
8933 EVT TheVT = Op.getOperand(0).getValueType();
8934 // FIXME This causes a redundant load/store if the SSE-class value is already
8935 // in memory, such as if it is on the callstack.
8936 if (isScalarFPTypeInSSEReg(TheVT)) {
8937 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
8938 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
8939 MachinePointerInfo::getFixedStack(SSFI),
8941 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
8943 Chain, StackSlot, DAG.getValueType(TheVT)
8946 MachineMemOperand *MMO =
8947 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8948 MachineMemOperand::MOLoad, MemSize, MemSize);
8949 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops,
8950 array_lengthof(Ops), DstTy, MMO);
8951 Chain = Value.getValue(1);
8952 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8953 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8956 MachineMemOperand *MMO =
8957 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8958 MachineMemOperand::MOStore, MemSize, MemSize);
8960 if (Opc != X86ISD::WIN_FTOL) {
8961 // Build the FP_TO_INT*_IN_MEM
8962 SDValue Ops[] = { Chain, Value, StackSlot };
8963 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
8964 Ops, array_lengthof(Ops), DstTy,
8966 return std::make_pair(FIST, StackSlot);
8968 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
8969 DAG.getVTList(MVT::Other, MVT::Glue),
8971 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
8972 MVT::i32, ftol.getValue(1));
8973 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
8974 MVT::i32, eax.getValue(2));
8975 SDValue Ops[] = { eax, edx };
8976 SDValue pair = IsReplace
8977 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, array_lengthof(Ops))
8978 : DAG.getMergeValues(Ops, array_lengthof(Ops), DL);
8979 return std::make_pair(pair, SDValue());
8983 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
8984 const X86Subtarget *Subtarget) {
8985 MVT VT = Op->getSimpleValueType(0);
8986 SDValue In = Op->getOperand(0);
8987 MVT InVT = In.getSimpleValueType();
8990 // Optimize vectors in AVX mode:
8993 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
8994 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
8995 // Concat upper and lower parts.
8998 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
8999 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
9000 // Concat upper and lower parts.
9003 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
9004 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
9005 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
9008 if (Subtarget->hasInt256())
9009 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, In);
9011 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
9012 SDValue Undef = DAG.getUNDEF(InVT);
9013 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
9014 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
9015 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
9017 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
9018 VT.getVectorNumElements()/2);
9020 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
9021 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
9023 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
9026 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
9027 SelectionDAG &DAG) {
9028 MVT VT = Op->getSimpleValueType(0);
9029 SDValue In = Op->getOperand(0);
9030 MVT InVT = In.getSimpleValueType();
9032 unsigned int NumElts = VT.getVectorNumElements();
9033 if (NumElts != 8 && NumElts != 16)
9036 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
9037 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
9039 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
9040 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9041 // Now we have only mask extension
9042 assert(InVT.getVectorElementType() == MVT::i1);
9043 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
9044 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
9045 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
9046 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
9047 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
9048 MachinePointerInfo::getConstantPool(),
9049 false, false, false, Alignment);
9051 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
9052 if (VT.is512BitVector())
9054 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
9057 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
9058 SelectionDAG &DAG) {
9059 if (Subtarget->hasFp256()) {
9060 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
9068 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
9069 SelectionDAG &DAG) {
9071 MVT VT = Op.getSimpleValueType();
9072 SDValue In = Op.getOperand(0);
9073 MVT SVT = In.getSimpleValueType();
9075 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
9076 return LowerZERO_EXTEND_AVX512(Op, DAG);
9078 if (Subtarget->hasFp256()) {
9079 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
9084 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
9085 VT.getVectorNumElements() != SVT.getVectorNumElements());
9089 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
9091 MVT VT = Op.getSimpleValueType();
9092 SDValue In = Op.getOperand(0);
9093 MVT InVT = In.getSimpleValueType();
9095 if (VT == MVT::i1) {
9096 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
9097 "Invalid scalar TRUNCATE operation");
9098 if (InVT == MVT::i32)
9100 if (InVT.getSizeInBits() == 64)
9101 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::i32, In);
9102 else if (InVT.getSizeInBits() < 32)
9103 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
9104 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
9106 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
9107 "Invalid TRUNCATE operation");
9109 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
9110 if (VT.getVectorElementType().getSizeInBits() >=8)
9111 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
9113 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
9114 unsigned NumElts = InVT.getVectorNumElements();
9115 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
9116 if (InVT.getSizeInBits() < 512) {
9117 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
9118 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
9121 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
9122 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
9123 SDValue CP = DAG.getConstantPool(C, getPointerTy());
9124 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
9125 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
9126 MachinePointerInfo::getConstantPool(),
9127 false, false, false, Alignment);
9128 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
9129 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
9130 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
9133 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
9134 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
9135 if (Subtarget->hasInt256()) {
9136 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
9137 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
9138 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
9140 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
9141 DAG.getIntPtrConstant(0));
9144 // On AVX, v4i64 -> v4i32 becomes a sequence that uses PSHUFD and MOVLHPS.
9145 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9146 DAG.getIntPtrConstant(0));
9147 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9148 DAG.getIntPtrConstant(2));
9150 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9151 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9154 static const int ShufMask1[] = {0, 2, 0, 0};
9155 SDValue Undef = DAG.getUNDEF(VT);
9156 OpLo = DAG.getVectorShuffle(VT, DL, OpLo, Undef, ShufMask1);
9157 OpHi = DAG.getVectorShuffle(VT, DL, OpHi, Undef, ShufMask1);
9159 // The MOVLHPS mask:
9160 static const int ShufMask2[] = {0, 1, 4, 5};
9161 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask2);
9164 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
9165 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
9166 if (Subtarget->hasInt256()) {
9167 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
9169 SmallVector<SDValue,32> pshufbMask;
9170 for (unsigned i = 0; i < 2; ++i) {
9171 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
9172 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
9173 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
9174 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
9175 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
9176 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
9177 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
9178 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
9179 for (unsigned j = 0; j < 8; ++j)
9180 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
9182 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8,
9183 &pshufbMask[0], 32);
9184 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
9185 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
9187 static const int ShufMask[] = {0, 2, -1, -1};
9188 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
9190 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9191 DAG.getIntPtrConstant(0));
9192 return DAG.getNode(ISD::BITCAST, DL, VT, In);
9195 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9196 DAG.getIntPtrConstant(0));
9198 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9199 DAG.getIntPtrConstant(4));
9201 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
9202 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
9205 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
9206 -1, -1, -1, -1, -1, -1, -1, -1};
9208 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
9209 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
9210 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
9212 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9213 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9215 // The MOVLHPS Mask:
9216 static const int ShufMask2[] = {0, 1, 4, 5};
9217 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
9218 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
9221 // Handle truncation of V256 to V128 using shuffles.
9222 if (!VT.is128BitVector() || !InVT.is256BitVector())
9225 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
9227 unsigned NumElems = VT.getVectorNumElements();
9228 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
9230 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
9231 // Prepare truncation shuffle mask
9232 for (unsigned i = 0; i != NumElems; ++i)
9234 SDValue V = DAG.getVectorShuffle(NVT, DL,
9235 DAG.getNode(ISD::BITCAST, DL, NVT, In),
9236 DAG.getUNDEF(NVT), &MaskVec[0]);
9237 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
9238 DAG.getIntPtrConstant(0));
9241 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
9242 SelectionDAG &DAG) const {
9243 MVT VT = Op.getSimpleValueType();
9244 if (VT.isVector()) {
9245 if (VT == MVT::v8i16)
9246 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT,
9247 DAG.getNode(ISD::FP_TO_SINT, SDLoc(Op),
9248 MVT::v8i32, Op.getOperand(0)));
9252 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9253 /*IsSigned=*/ true, /*IsReplace=*/ false);
9254 SDValue FIST = Vals.first, StackSlot = Vals.second;
9255 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
9256 if (FIST.getNode() == 0) return Op;
9258 if (StackSlot.getNode())
9260 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9261 FIST, StackSlot, MachinePointerInfo(),
9262 false, false, false, 0);
9264 // The node is the result.
9268 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
9269 SelectionDAG &DAG) const {
9270 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9271 /*IsSigned=*/ false, /*IsReplace=*/ false);
9272 SDValue FIST = Vals.first, StackSlot = Vals.second;
9273 assert(FIST.getNode() && "Unexpected failure");
9275 if (StackSlot.getNode())
9277 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9278 FIST, StackSlot, MachinePointerInfo(),
9279 false, false, false, 0);
9281 // The node is the result.
9285 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
9287 MVT VT = Op.getSimpleValueType();
9288 SDValue In = Op.getOperand(0);
9289 MVT SVT = In.getSimpleValueType();
9291 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
9293 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
9294 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
9295 In, DAG.getUNDEF(SVT)));
9298 static SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) {
9299 LLVMContext *Context = DAG.getContext();
9301 MVT VT = Op.getSimpleValueType();
9303 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9304 if (VT.isVector()) {
9305 EltVT = VT.getVectorElementType();
9306 NumElts = VT.getVectorNumElements();
9309 if (EltVT == MVT::f64)
9310 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9311 APInt(64, ~(1ULL << 63))));
9313 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9314 APInt(32, ~(1U << 31))));
9315 C = ConstantVector::getSplat(NumElts, C);
9316 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9317 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
9318 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9319 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9320 MachinePointerInfo::getConstantPool(),
9321 false, false, false, Alignment);
9322 if (VT.isVector()) {
9323 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9324 return DAG.getNode(ISD::BITCAST, dl, VT,
9325 DAG.getNode(ISD::AND, dl, ANDVT,
9326 DAG.getNode(ISD::BITCAST, dl, ANDVT,
9328 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
9330 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
9333 static SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) {
9334 LLVMContext *Context = DAG.getContext();
9336 MVT VT = Op.getSimpleValueType();
9338 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9339 if (VT.isVector()) {
9340 EltVT = VT.getVectorElementType();
9341 NumElts = VT.getVectorNumElements();
9344 if (EltVT == MVT::f64)
9345 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9346 APInt(64, 1ULL << 63)));
9348 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9349 APInt(32, 1U << 31)));
9350 C = ConstantVector::getSplat(NumElts, C);
9351 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9352 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
9353 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9354 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9355 MachinePointerInfo::getConstantPool(),
9356 false, false, false, Alignment);
9357 if (VT.isVector()) {
9358 MVT XORVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits()/64);
9359 return DAG.getNode(ISD::BITCAST, dl, VT,
9360 DAG.getNode(ISD::XOR, dl, XORVT,
9361 DAG.getNode(ISD::BITCAST, dl, XORVT,
9363 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
9366 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
9369 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
9370 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9371 LLVMContext *Context = DAG.getContext();
9372 SDValue Op0 = Op.getOperand(0);
9373 SDValue Op1 = Op.getOperand(1);
9375 MVT VT = Op.getSimpleValueType();
9376 MVT SrcVT = Op1.getSimpleValueType();
9378 // If second operand is smaller, extend it first.
9379 if (SrcVT.bitsLT(VT)) {
9380 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
9383 // And if it is bigger, shrink it first.
9384 if (SrcVT.bitsGT(VT)) {
9385 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
9389 // At this point the operands and the result should have the same
9390 // type, and that won't be f80 since that is not custom lowered.
9392 // First get the sign bit of second operand.
9393 SmallVector<Constant*,4> CV;
9394 if (SrcVT == MVT::f64) {
9395 const fltSemantics &Sem = APFloat::IEEEdouble;
9396 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
9397 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9399 const fltSemantics &Sem = APFloat::IEEEsingle;
9400 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
9401 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9402 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9403 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9405 Constant *C = ConstantVector::get(CV);
9406 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
9407 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
9408 MachinePointerInfo::getConstantPool(),
9409 false, false, false, 16);
9410 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
9412 // Shift sign bit right or left if the two operands have different types.
9413 if (SrcVT.bitsGT(VT)) {
9414 // Op0 is MVT::f32, Op1 is MVT::f64.
9415 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
9416 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
9417 DAG.getConstant(32, MVT::i32));
9418 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
9419 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
9420 DAG.getIntPtrConstant(0));
9423 // Clear first operand sign bit.
9425 if (VT == MVT::f64) {
9426 const fltSemantics &Sem = APFloat::IEEEdouble;
9427 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9428 APInt(64, ~(1ULL << 63)))));
9429 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9431 const fltSemantics &Sem = APFloat::IEEEsingle;
9432 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9433 APInt(32, ~(1U << 31)))));
9434 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9435 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9436 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9438 C = ConstantVector::get(CV);
9439 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
9440 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9441 MachinePointerInfo::getConstantPool(),
9442 false, false, false, 16);
9443 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
9445 // Or the value with the sign bit.
9446 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
9449 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
9450 SDValue N0 = Op.getOperand(0);
9452 MVT VT = Op.getSimpleValueType();
9454 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
9455 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
9456 DAG.getConstant(1, VT));
9457 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
9460 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
9462 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
9463 SelectionDAG &DAG) {
9464 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
9466 if (!Subtarget->hasSSE41())
9469 if (!Op->hasOneUse())
9472 SDNode *N = Op.getNode();
9475 SmallVector<SDValue, 8> Opnds;
9476 DenseMap<SDValue, unsigned> VecInMap;
9477 EVT VT = MVT::Other;
9479 // Recognize a special case where a vector is casted into wide integer to
9481 Opnds.push_back(N->getOperand(0));
9482 Opnds.push_back(N->getOperand(1));
9484 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
9485 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
9486 // BFS traverse all OR'd operands.
9487 if (I->getOpcode() == ISD::OR) {
9488 Opnds.push_back(I->getOperand(0));
9489 Opnds.push_back(I->getOperand(1));
9490 // Re-evaluate the number of nodes to be traversed.
9491 e += 2; // 2 more nodes (LHS and RHS) are pushed.
9495 // Quit if a non-EXTRACT_VECTOR_ELT
9496 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9499 // Quit if without a constant index.
9500 SDValue Idx = I->getOperand(1);
9501 if (!isa<ConstantSDNode>(Idx))
9504 SDValue ExtractedFromVec = I->getOperand(0);
9505 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
9506 if (M == VecInMap.end()) {
9507 VT = ExtractedFromVec.getValueType();
9508 // Quit if not 128/256-bit vector.
9509 if (!VT.is128BitVector() && !VT.is256BitVector())
9511 // Quit if not the same type.
9512 if (VecInMap.begin() != VecInMap.end() &&
9513 VT != VecInMap.begin()->first.getValueType())
9515 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
9517 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
9520 assert((VT.is128BitVector() || VT.is256BitVector()) &&
9521 "Not extracted from 128-/256-bit vector.");
9523 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
9524 SmallVector<SDValue, 8> VecIns;
9526 for (DenseMap<SDValue, unsigned>::const_iterator
9527 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
9528 // Quit if not all elements are used.
9529 if (I->second != FullMask)
9531 VecIns.push_back(I->first);
9534 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9536 // Cast all vectors into TestVT for PTEST.
9537 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
9538 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
9540 // If more than one full vectors are evaluated, OR them first before PTEST.
9541 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
9542 // Each iteration will OR 2 nodes and append the result until there is only
9543 // 1 node left, i.e. the final OR'd value of all vectors.
9544 SDValue LHS = VecIns[Slot];
9545 SDValue RHS = VecIns[Slot + 1];
9546 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
9549 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
9550 VecIns.back(), VecIns.back());
9553 /// Emit nodes that will be selected as "test Op0,Op0", or something
9555 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
9556 SelectionDAG &DAG) const {
9559 if (Op.getValueType() == MVT::i1)
9560 // KORTEST instruction should be selected
9561 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9562 DAG.getConstant(0, Op.getValueType()));
9564 // CF and OF aren't always set the way we want. Determine which
9565 // of these we need.
9566 bool NeedCF = false;
9567 bool NeedOF = false;
9570 case X86::COND_A: case X86::COND_AE:
9571 case X86::COND_B: case X86::COND_BE:
9574 case X86::COND_G: case X86::COND_GE:
9575 case X86::COND_L: case X86::COND_LE:
9576 case X86::COND_O: case X86::COND_NO:
9580 // See if we can use the EFLAGS value from the operand instead of
9581 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
9582 // we prove that the arithmetic won't overflow, we can't use OF or CF.
9583 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
9584 // Emit a CMP with 0, which is the TEST pattern.
9585 //if (Op.getValueType() == MVT::i1)
9586 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
9587 // DAG.getConstant(0, MVT::i1));
9588 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9589 DAG.getConstant(0, Op.getValueType()));
9591 unsigned Opcode = 0;
9592 unsigned NumOperands = 0;
9594 // Truncate operations may prevent the merge of the SETCC instruction
9595 // and the arithmetic instruction before it. Attempt to truncate the operands
9596 // of the arithmetic instruction and use a reduced bit-width instruction.
9597 bool NeedTruncation = false;
9598 SDValue ArithOp = Op;
9599 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
9600 SDValue Arith = Op->getOperand(0);
9601 // Both the trunc and the arithmetic op need to have one user each.
9602 if (Arith->hasOneUse())
9603 switch (Arith.getOpcode()) {
9610 NeedTruncation = true;
9616 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
9617 // which may be the result of a CAST. We use the variable 'Op', which is the
9618 // non-casted variable when we check for possible users.
9619 switch (ArithOp.getOpcode()) {
9621 // Due to an isel shortcoming, be conservative if this add is likely to be
9622 // selected as part of a load-modify-store instruction. When the root node
9623 // in a match is a store, isel doesn't know how to remap non-chain non-flag
9624 // uses of other nodes in the match, such as the ADD in this case. This
9625 // leads to the ADD being left around and reselected, with the result being
9626 // two adds in the output. Alas, even if none our users are stores, that
9627 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
9628 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
9629 // climbing the DAG back to the root, and it doesn't seem to be worth the
9631 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9632 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9633 if (UI->getOpcode() != ISD::CopyToReg &&
9634 UI->getOpcode() != ISD::SETCC &&
9635 UI->getOpcode() != ISD::STORE)
9638 if (ConstantSDNode *C =
9639 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
9640 // An add of one will be selected as an INC.
9641 if (C->getAPIntValue() == 1) {
9642 Opcode = X86ISD::INC;
9647 // An add of negative one (subtract of one) will be selected as a DEC.
9648 if (C->getAPIntValue().isAllOnesValue()) {
9649 Opcode = X86ISD::DEC;
9655 // Otherwise use a regular EFLAGS-setting add.
9656 Opcode = X86ISD::ADD;
9660 // If the primary and result isn't used, don't bother using X86ISD::AND,
9661 // because a TEST instruction will be better.
9662 bool NonFlagUse = false;
9663 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9664 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
9666 unsigned UOpNo = UI.getOperandNo();
9667 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
9668 // Look pass truncate.
9669 UOpNo = User->use_begin().getOperandNo();
9670 User = *User->use_begin();
9673 if (User->getOpcode() != ISD::BRCOND &&
9674 User->getOpcode() != ISD::SETCC &&
9675 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) {
9688 // Due to the ISEL shortcoming noted above, be conservative if this op is
9689 // likely to be selected as part of a load-modify-store instruction.
9690 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9691 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9692 if (UI->getOpcode() == ISD::STORE)
9695 // Otherwise use a regular EFLAGS-setting instruction.
9696 switch (ArithOp.getOpcode()) {
9697 default: llvm_unreachable("unexpected operator!");
9698 case ISD::SUB: Opcode = X86ISD::SUB; break;
9699 case ISD::XOR: Opcode = X86ISD::XOR; break;
9700 case ISD::AND: Opcode = X86ISD::AND; break;
9702 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
9703 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
9704 if (EFLAGS.getNode())
9707 Opcode = X86ISD::OR;
9721 return SDValue(Op.getNode(), 1);
9727 // If we found that truncation is beneficial, perform the truncation and
9729 if (NeedTruncation) {
9730 EVT VT = Op.getValueType();
9731 SDValue WideVal = Op->getOperand(0);
9732 EVT WideVT = WideVal.getValueType();
9733 unsigned ConvertedOp = 0;
9734 // Use a target machine opcode to prevent further DAGCombine
9735 // optimizations that may separate the arithmetic operations
9736 // from the setcc node.
9737 switch (WideVal.getOpcode()) {
9739 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
9740 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
9741 case ISD::AND: ConvertedOp = X86ISD::AND; break;
9742 case ISD::OR: ConvertedOp = X86ISD::OR; break;
9743 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
9747 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9748 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
9749 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
9750 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
9751 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
9757 // Emit a CMP with 0, which is the TEST pattern.
9758 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9759 DAG.getConstant(0, Op.getValueType()));
9761 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
9762 SmallVector<SDValue, 4> Ops;
9763 for (unsigned i = 0; i != NumOperands; ++i)
9764 Ops.push_back(Op.getOperand(i));
9766 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
9767 DAG.ReplaceAllUsesWith(Op, New);
9768 return SDValue(New.getNode(), 1);
9771 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
9773 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
9774 SelectionDAG &DAG) const {
9776 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
9777 if (C->getAPIntValue() == 0)
9778 return EmitTest(Op0, X86CC, DAG);
9780 if (Op0.getValueType() == MVT::i1) {
9782 Op0 = DAG.getNode(ISD::XOR, dl, MVT::i1, Op0,
9783 DAG.getConstant(-1, MVT::i1));
9784 return EmitTest(Op0, X86CC, DAG);
9788 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
9789 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
9790 // Do the comparison at i32 if it's smaller. This avoids subregister
9791 // aliasing issues. Keep the smaller reference if we're optimizing for
9792 // size, however, as that'll allow better folding of memory operations.
9793 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
9794 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
9795 AttributeSet::FunctionIndex, Attribute::MinSize)) {
9797 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
9798 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
9799 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
9801 // Use SUB instead of CMP to enable CSE between SUB and CMP.
9802 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
9803 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
9805 return SDValue(Sub.getNode(), 1);
9807 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
9810 /// Convert a comparison if required by the subtarget.
9811 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
9812 SelectionDAG &DAG) const {
9813 // If the subtarget does not support the FUCOMI instruction, floating-point
9814 // comparisons have to be converted.
9815 if (Subtarget->hasCMov() ||
9816 Cmp.getOpcode() != X86ISD::CMP ||
9817 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
9818 !Cmp.getOperand(1).getValueType().isFloatingPoint())
9821 // The instruction selector will select an FUCOM instruction instead of
9822 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
9823 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
9824 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
9826 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
9827 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
9828 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
9829 DAG.getConstant(8, MVT::i8));
9830 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
9831 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
9834 static bool isAllOnes(SDValue V) {
9835 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
9836 return C && C->isAllOnesValue();
9839 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
9840 /// if it's possible.
9841 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
9842 SDLoc dl, SelectionDAG &DAG) const {
9843 SDValue Op0 = And.getOperand(0);
9844 SDValue Op1 = And.getOperand(1);
9845 if (Op0.getOpcode() == ISD::TRUNCATE)
9846 Op0 = Op0.getOperand(0);
9847 if (Op1.getOpcode() == ISD::TRUNCATE)
9848 Op1 = Op1.getOperand(0);
9851 if (Op1.getOpcode() == ISD::SHL)
9852 std::swap(Op0, Op1);
9853 if (Op0.getOpcode() == ISD::SHL) {
9854 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
9855 if (And00C->getZExtValue() == 1) {
9856 // If we looked past a truncate, check that it's only truncating away
9858 unsigned BitWidth = Op0.getValueSizeInBits();
9859 unsigned AndBitWidth = And.getValueSizeInBits();
9860 if (BitWidth > AndBitWidth) {
9862 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
9863 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
9867 RHS = Op0.getOperand(1);
9869 } else if (Op1.getOpcode() == ISD::Constant) {
9870 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
9871 uint64_t AndRHSVal = AndRHS->getZExtValue();
9872 SDValue AndLHS = Op0;
9874 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
9875 LHS = AndLHS.getOperand(0);
9876 RHS = AndLHS.getOperand(1);
9879 // Use BT if the immediate can't be encoded in a TEST instruction.
9880 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
9882 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
9886 if (LHS.getNode()) {
9887 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
9888 // instruction. Since the shift amount is in-range-or-undefined, we know
9889 // that doing a bittest on the i32 value is ok. We extend to i32 because
9890 // the encoding for the i16 version is larger than the i32 version.
9891 // Also promote i16 to i32 for performance / code size reason.
9892 if (LHS.getValueType() == MVT::i8 ||
9893 LHS.getValueType() == MVT::i16)
9894 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
9896 // If the operand types disagree, extend the shift amount to match. Since
9897 // BT ignores high bits (like shifts) we can use anyextend.
9898 if (LHS.getValueType() != RHS.getValueType())
9899 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
9901 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
9902 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
9903 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9904 DAG.getConstant(Cond, MVT::i8), BT);
9910 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
9912 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
9917 // SSE Condition code mapping:
9926 switch (SetCCOpcode) {
9927 default: llvm_unreachable("Unexpected SETCC condition");
9929 case ISD::SETEQ: SSECC = 0; break;
9931 case ISD::SETGT: Swap = true; // Fallthrough
9933 case ISD::SETOLT: SSECC = 1; break;
9935 case ISD::SETGE: Swap = true; // Fallthrough
9937 case ISD::SETOLE: SSECC = 2; break;
9938 case ISD::SETUO: SSECC = 3; break;
9940 case ISD::SETNE: SSECC = 4; break;
9941 case ISD::SETULE: Swap = true; // Fallthrough
9942 case ISD::SETUGE: SSECC = 5; break;
9943 case ISD::SETULT: Swap = true; // Fallthrough
9944 case ISD::SETUGT: SSECC = 6; break;
9945 case ISD::SETO: SSECC = 7; break;
9947 case ISD::SETONE: SSECC = 8; break;
9950 std::swap(Op0, Op1);
9955 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
9956 // ones, and then concatenate the result back.
9957 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
9958 MVT VT = Op.getSimpleValueType();
9960 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
9961 "Unsupported value type for operation");
9963 unsigned NumElems = VT.getVectorNumElements();
9965 SDValue CC = Op.getOperand(2);
9967 // Extract the LHS vectors
9968 SDValue LHS = Op.getOperand(0);
9969 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
9970 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
9972 // Extract the RHS vectors
9973 SDValue RHS = Op.getOperand(1);
9974 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
9975 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
9977 // Issue the operation on the smaller types and concatenate the result back
9978 MVT EltVT = VT.getVectorElementType();
9979 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9980 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9981 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
9982 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
9985 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
9986 SDValue Op0 = Op.getOperand(0);
9987 SDValue Op1 = Op.getOperand(1);
9988 SDValue CC = Op.getOperand(2);
9989 MVT VT = Op.getSimpleValueType();
9991 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 32 &&
9992 Op.getValueType().getScalarType() == MVT::i1 &&
9993 "Cannot set masked compare for this operation");
9995 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9998 bool Unsigned = false;
10000 switch (SetCCOpcode) {
10001 default: llvm_unreachable("Unexpected SETCC condition");
10002 case ISD::SETNE: SSECC = 4; break;
10003 case ISD::SETEQ: SSECC = 0; break;
10004 case ISD::SETUGT: Unsigned = true;
10005 case ISD::SETGT: SSECC = 6; break; // NLE
10006 case ISD::SETULT: Unsigned = true;
10007 case ISD::SETLT: SSECC = 1; break;
10008 case ISD::SETUGE: Unsigned = true;
10009 case ISD::SETGE: SSECC = 5; break; // NLT
10010 case ISD::SETULE: Unsigned = true;
10011 case ISD::SETLE: SSECC = 2; break;
10013 unsigned Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
10014 return DAG.getNode(Opc, dl, VT, Op0, Op1,
10015 DAG.getConstant(SSECC, MVT::i8));
10019 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
10020 SelectionDAG &DAG) {
10021 SDValue Op0 = Op.getOperand(0);
10022 SDValue Op1 = Op.getOperand(1);
10023 SDValue CC = Op.getOperand(2);
10024 MVT VT = Op.getSimpleValueType();
10025 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
10026 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
10031 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
10032 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
10035 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
10036 unsigned Opc = X86ISD::CMPP;
10037 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
10038 assert(VT.getVectorNumElements() <= 16);
10039 Opc = X86ISD::CMPM;
10041 // In the two special cases we can't handle, emit two comparisons.
10044 unsigned CombineOpc;
10045 if (SetCCOpcode == ISD::SETUEQ) {
10046 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
10048 assert(SetCCOpcode == ISD::SETONE);
10049 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
10052 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
10053 DAG.getConstant(CC0, MVT::i8));
10054 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
10055 DAG.getConstant(CC1, MVT::i8));
10056 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
10058 // Handle all other FP comparisons here.
10059 return DAG.getNode(Opc, dl, VT, Op0, Op1,
10060 DAG.getConstant(SSECC, MVT::i8));
10063 // Break 256-bit integer vector compare into smaller ones.
10064 if (VT.is256BitVector() && !Subtarget->hasInt256())
10065 return Lower256IntVSETCC(Op, DAG);
10067 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
10068 EVT OpVT = Op1.getValueType();
10069 if (Subtarget->hasAVX512()) {
10070 if (Op1.getValueType().is512BitVector() ||
10071 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
10072 return LowerIntVSETCC_AVX512(Op, DAG);
10074 // In AVX-512 architecture setcc returns mask with i1 elements,
10075 // But there is no compare instruction for i8 and i16 elements.
10076 // We are not talking about 512-bit operands in this case, these
10077 // types are illegal.
10079 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
10080 OpVT.getVectorElementType().getSizeInBits() >= 8))
10081 return DAG.getNode(ISD::TRUNCATE, dl, VT,
10082 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
10085 // We are handling one of the integer comparisons here. Since SSE only has
10086 // GT and EQ comparisons for integer, swapping operands and multiple
10087 // operations may be required for some comparisons.
10089 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
10091 switch (SetCCOpcode) {
10092 default: llvm_unreachable("Unexpected SETCC condition");
10093 case ISD::SETNE: Invert = true;
10094 case ISD::SETEQ: Opc = MaskResult? X86ISD::PCMPEQM: X86ISD::PCMPEQ; break;
10095 case ISD::SETLT: Swap = true;
10096 case ISD::SETGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT; break;
10097 case ISD::SETGE: Swap = true;
10098 case ISD::SETLE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
10099 Invert = true; break;
10100 case ISD::SETULT: Swap = true;
10101 case ISD::SETUGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
10102 FlipSigns = true; break;
10103 case ISD::SETUGE: Swap = true;
10104 case ISD::SETULE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
10105 FlipSigns = true; Invert = true; break;
10108 // Special case: Use min/max operations for SETULE/SETUGE
10109 MVT VET = VT.getVectorElementType();
10111 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
10112 || (Subtarget->hasSSE2() && (VET == MVT::i8));
10115 switch (SetCCOpcode) {
10117 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
10118 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
10121 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
10125 std::swap(Op0, Op1);
10127 // Check that the operation in question is available (most are plain SSE2,
10128 // but PCMPGTQ and PCMPEQQ have different requirements).
10129 if (VT == MVT::v2i64) {
10130 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
10131 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
10133 // First cast everything to the right type.
10134 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
10135 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
10137 // Since SSE has no unsigned integer comparisons, we need to flip the sign
10138 // bits of the inputs before performing those operations. The lower
10139 // compare is always unsigned.
10142 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
10144 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
10145 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
10146 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
10147 Sign, Zero, Sign, Zero);
10149 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
10150 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
10152 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
10153 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
10154 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
10156 // Create masks for only the low parts/high parts of the 64 bit integers.
10157 static const int MaskHi[] = { 1, 1, 3, 3 };
10158 static const int MaskLo[] = { 0, 0, 2, 2 };
10159 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
10160 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
10161 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
10163 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
10164 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
10167 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10169 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10172 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
10173 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
10174 // pcmpeqd + pshufd + pand.
10175 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
10177 // First cast everything to the right type.
10178 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
10179 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
10182 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
10184 // Make sure the lower and upper halves are both all-ones.
10185 static const int Mask[] = { 1, 0, 3, 2 };
10186 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
10187 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
10190 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10192 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10196 // Since SSE has no unsigned integer comparisons, we need to flip the sign
10197 // bits of the inputs before performing those operations.
10199 EVT EltVT = VT.getVectorElementType();
10200 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
10201 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
10202 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
10205 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
10207 // If the logical-not of the result is required, perform that now.
10209 Result = DAG.getNOT(dl, Result, VT);
10212 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
10217 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
10219 MVT VT = Op.getSimpleValueType();
10221 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
10223 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
10224 && "SetCC type must be 8-bit or 1-bit integer");
10225 SDValue Op0 = Op.getOperand(0);
10226 SDValue Op1 = Op.getOperand(1);
10228 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
10230 // Optimize to BT if possible.
10231 // Lower (X & (1 << N)) == 0 to BT(X, N).
10232 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
10233 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
10234 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
10235 Op1.getOpcode() == ISD::Constant &&
10236 cast<ConstantSDNode>(Op1)->isNullValue() &&
10237 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10238 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
10239 if (NewSetCC.getNode())
10243 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
10245 if (Op1.getOpcode() == ISD::Constant &&
10246 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
10247 cast<ConstantSDNode>(Op1)->isNullValue()) &&
10248 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10250 // If the input is a setcc, then reuse the input setcc or use a new one with
10251 // the inverted condition.
10252 if (Op0.getOpcode() == X86ISD::SETCC) {
10253 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
10254 bool Invert = (CC == ISD::SETNE) ^
10255 cast<ConstantSDNode>(Op1)->isNullValue();
10259 CCode = X86::GetOppositeBranchCondition(CCode);
10260 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10261 DAG.getConstant(CCode, MVT::i8),
10262 Op0.getOperand(1));
10264 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
10269 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
10270 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
10271 if (X86CC == X86::COND_INVALID)
10274 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
10275 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
10276 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10277 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
10279 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
10283 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
10284 static bool isX86LogicalCmp(SDValue Op) {
10285 unsigned Opc = Op.getNode()->getOpcode();
10286 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
10287 Opc == X86ISD::SAHF)
10289 if (Op.getResNo() == 1 &&
10290 (Opc == X86ISD::ADD ||
10291 Opc == X86ISD::SUB ||
10292 Opc == X86ISD::ADC ||
10293 Opc == X86ISD::SBB ||
10294 Opc == X86ISD::SMUL ||
10295 Opc == X86ISD::UMUL ||
10296 Opc == X86ISD::INC ||
10297 Opc == X86ISD::DEC ||
10298 Opc == X86ISD::OR ||
10299 Opc == X86ISD::XOR ||
10300 Opc == X86ISD::AND))
10303 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
10309 static bool isZero(SDValue V) {
10310 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
10311 return C && C->isNullValue();
10314 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
10315 if (V.getOpcode() != ISD::TRUNCATE)
10318 SDValue VOp0 = V.getOperand(0);
10319 unsigned InBits = VOp0.getValueSizeInBits();
10320 unsigned Bits = V.getValueSizeInBits();
10321 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
10324 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
10325 bool addTest = true;
10326 SDValue Cond = Op.getOperand(0);
10327 SDValue Op1 = Op.getOperand(1);
10328 SDValue Op2 = Op.getOperand(2);
10330 EVT VT = Op1.getValueType();
10333 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
10334 // are available. Otherwise fp cmovs get lowered into a less efficient branch
10335 // sequence later on.
10336 if (Cond.getOpcode() == ISD::SETCC &&
10337 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
10338 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
10339 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
10340 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
10341 int SSECC = translateX86FSETCC(
10342 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
10345 if (Subtarget->hasAVX512()) {
10346 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
10347 DAG.getConstant(SSECC, MVT::i8));
10348 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
10350 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
10351 DAG.getConstant(SSECC, MVT::i8));
10352 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
10353 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
10354 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
10358 if (Cond.getOpcode() == ISD::SETCC) {
10359 SDValue NewCond = LowerSETCC(Cond, DAG);
10360 if (NewCond.getNode())
10364 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
10365 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
10366 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
10367 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
10368 if (Cond.getOpcode() == X86ISD::SETCC &&
10369 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
10370 isZero(Cond.getOperand(1).getOperand(1))) {
10371 SDValue Cmp = Cond.getOperand(1);
10373 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
10375 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
10376 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
10377 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
10379 SDValue CmpOp0 = Cmp.getOperand(0);
10380 // Apply further optimizations for special cases
10381 // (select (x != 0), -1, 0) -> neg & sbb
10382 // (select (x == 0), 0, -1) -> neg & sbb
10383 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
10384 if (YC->isNullValue() &&
10385 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
10386 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
10387 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
10388 DAG.getConstant(0, CmpOp0.getValueType()),
10390 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10391 DAG.getConstant(X86::COND_B, MVT::i8),
10392 SDValue(Neg.getNode(), 1));
10396 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
10397 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
10398 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10400 SDValue Res = // Res = 0 or -1.
10401 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10402 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
10404 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
10405 Res = DAG.getNOT(DL, Res, Res.getValueType());
10407 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
10408 if (N2C == 0 || !N2C->isNullValue())
10409 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
10414 // Look past (and (setcc_carry (cmp ...)), 1).
10415 if (Cond.getOpcode() == ISD::AND &&
10416 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10417 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10418 if (C && C->getAPIntValue() == 1)
10419 Cond = Cond.getOperand(0);
10422 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10423 // setting operand in place of the X86ISD::SETCC.
10424 unsigned CondOpcode = Cond.getOpcode();
10425 if (CondOpcode == X86ISD::SETCC ||
10426 CondOpcode == X86ISD::SETCC_CARRY) {
10427 CC = Cond.getOperand(0);
10429 SDValue Cmp = Cond.getOperand(1);
10430 unsigned Opc = Cmp.getOpcode();
10431 MVT VT = Op.getSimpleValueType();
10433 bool IllegalFPCMov = false;
10434 if (VT.isFloatingPoint() && !VT.isVector() &&
10435 !isScalarFPTypeInSSEReg(VT)) // FPStack?
10436 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
10438 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
10439 Opc == X86ISD::BT) { // FIXME
10443 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10444 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10445 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10446 Cond.getOperand(0).getValueType() != MVT::i8)) {
10447 SDValue LHS = Cond.getOperand(0);
10448 SDValue RHS = Cond.getOperand(1);
10449 unsigned X86Opcode;
10452 switch (CondOpcode) {
10453 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10454 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10455 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10456 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10457 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10458 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10459 default: llvm_unreachable("unexpected overflowing operator");
10461 if (CondOpcode == ISD::UMULO)
10462 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10465 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10467 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
10469 if (CondOpcode == ISD::UMULO)
10470 Cond = X86Op.getValue(2);
10472 Cond = X86Op.getValue(1);
10474 CC = DAG.getConstant(X86Cond, MVT::i8);
10479 // Look pass the truncate if the high bits are known zero.
10480 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10481 Cond = Cond.getOperand(0);
10483 // We know the result of AND is compared against zero. Try to match
10485 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10486 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
10487 if (NewSetCC.getNode()) {
10488 CC = NewSetCC.getOperand(0);
10489 Cond = NewSetCC.getOperand(1);
10496 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10497 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10500 // a < b ? -1 : 0 -> RES = ~setcc_carry
10501 // a < b ? 0 : -1 -> RES = setcc_carry
10502 // a >= b ? -1 : 0 -> RES = setcc_carry
10503 // a >= b ? 0 : -1 -> RES = ~setcc_carry
10504 if (Cond.getOpcode() == X86ISD::SUB) {
10505 Cond = ConvertCmpIfNecessary(Cond, DAG);
10506 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
10508 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
10509 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
10510 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10511 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
10512 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
10513 return DAG.getNOT(DL, Res, Res.getValueType());
10518 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
10519 // widen the cmov and push the truncate through. This avoids introducing a new
10520 // branch during isel and doesn't add any extensions.
10521 if (Op.getValueType() == MVT::i8 &&
10522 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
10523 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
10524 if (T1.getValueType() == T2.getValueType() &&
10525 // Blacklist CopyFromReg to avoid partial register stalls.
10526 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
10527 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
10528 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
10529 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
10533 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
10534 // condition is true.
10535 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
10536 SDValue Ops[] = { Op2, Op1, CC, Cond };
10537 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
10540 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
10541 MVT VT = Op->getSimpleValueType(0);
10542 SDValue In = Op->getOperand(0);
10543 MVT InVT = In.getSimpleValueType();
10546 unsigned int NumElts = VT.getVectorNumElements();
10547 if (NumElts != 8 && NumElts != 16)
10550 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
10551 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
10553 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10554 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
10556 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
10557 Constant *C = ConstantInt::get(*DAG.getContext(),
10558 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
10560 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
10561 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
10562 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
10563 MachinePointerInfo::getConstantPool(),
10564 false, false, false, Alignment);
10565 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
10566 if (VT.is512BitVector())
10568 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
10571 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
10572 SelectionDAG &DAG) {
10573 MVT VT = Op->getSimpleValueType(0);
10574 SDValue In = Op->getOperand(0);
10575 MVT InVT = In.getSimpleValueType();
10578 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
10579 return LowerSIGN_EXTEND_AVX512(Op, DAG);
10581 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
10582 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
10583 (VT != MVT::v16i16 || InVT != MVT::v16i8))
10586 if (Subtarget->hasInt256())
10587 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, In);
10589 // Optimize vectors in AVX mode
10590 // Sign extend v8i16 to v8i32 and
10593 // Divide input vector into two parts
10594 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
10595 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
10596 // concat the vectors to original VT
10598 unsigned NumElems = InVT.getVectorNumElements();
10599 SDValue Undef = DAG.getUNDEF(InVT);
10601 SmallVector<int,8> ShufMask1(NumElems, -1);
10602 for (unsigned i = 0; i != NumElems/2; ++i)
10605 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
10607 SmallVector<int,8> ShufMask2(NumElems, -1);
10608 for (unsigned i = 0; i != NumElems/2; ++i)
10609 ShufMask2[i] = i + NumElems/2;
10611 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
10613 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
10614 VT.getVectorNumElements()/2);
10616 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
10617 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
10619 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
10622 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
10623 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
10624 // from the AND / OR.
10625 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
10626 Opc = Op.getOpcode();
10627 if (Opc != ISD::OR && Opc != ISD::AND)
10629 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10630 Op.getOperand(0).hasOneUse() &&
10631 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
10632 Op.getOperand(1).hasOneUse());
10635 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
10636 // 1 and that the SETCC node has a single use.
10637 static bool isXor1OfSetCC(SDValue Op) {
10638 if (Op.getOpcode() != ISD::XOR)
10640 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
10641 if (N1C && N1C->getAPIntValue() == 1) {
10642 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10643 Op.getOperand(0).hasOneUse();
10648 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
10649 bool addTest = true;
10650 SDValue Chain = Op.getOperand(0);
10651 SDValue Cond = Op.getOperand(1);
10652 SDValue Dest = Op.getOperand(2);
10655 bool Inverted = false;
10657 if (Cond.getOpcode() == ISD::SETCC) {
10658 // Check for setcc([su]{add,sub,mul}o == 0).
10659 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
10660 isa<ConstantSDNode>(Cond.getOperand(1)) &&
10661 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
10662 Cond.getOperand(0).getResNo() == 1 &&
10663 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
10664 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
10665 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
10666 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
10667 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
10668 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
10670 Cond = Cond.getOperand(0);
10672 SDValue NewCond = LowerSETCC(Cond, DAG);
10673 if (NewCond.getNode())
10678 // FIXME: LowerXALUO doesn't handle these!!
10679 else if (Cond.getOpcode() == X86ISD::ADD ||
10680 Cond.getOpcode() == X86ISD::SUB ||
10681 Cond.getOpcode() == X86ISD::SMUL ||
10682 Cond.getOpcode() == X86ISD::UMUL)
10683 Cond = LowerXALUO(Cond, DAG);
10686 // Look pass (and (setcc_carry (cmp ...)), 1).
10687 if (Cond.getOpcode() == ISD::AND &&
10688 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10689 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10690 if (C && C->getAPIntValue() == 1)
10691 Cond = Cond.getOperand(0);
10694 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10695 // setting operand in place of the X86ISD::SETCC.
10696 unsigned CondOpcode = Cond.getOpcode();
10697 if (CondOpcode == X86ISD::SETCC ||
10698 CondOpcode == X86ISD::SETCC_CARRY) {
10699 CC = Cond.getOperand(0);
10701 SDValue Cmp = Cond.getOperand(1);
10702 unsigned Opc = Cmp.getOpcode();
10703 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
10704 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
10708 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
10712 // These can only come from an arithmetic instruction with overflow,
10713 // e.g. SADDO, UADDO.
10714 Cond = Cond.getNode()->getOperand(1);
10720 CondOpcode = Cond.getOpcode();
10721 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10722 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10723 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10724 Cond.getOperand(0).getValueType() != MVT::i8)) {
10725 SDValue LHS = Cond.getOperand(0);
10726 SDValue RHS = Cond.getOperand(1);
10727 unsigned X86Opcode;
10730 // Keep this in sync with LowerXALUO, otherwise we might create redundant
10731 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
10733 switch (CondOpcode) {
10734 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10736 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10738 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
10741 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10742 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10744 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10746 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
10749 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10750 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10751 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10752 default: llvm_unreachable("unexpected overflowing operator");
10755 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
10756 if (CondOpcode == ISD::UMULO)
10757 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10760 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10762 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
10764 if (CondOpcode == ISD::UMULO)
10765 Cond = X86Op.getValue(2);
10767 Cond = X86Op.getValue(1);
10769 CC = DAG.getConstant(X86Cond, MVT::i8);
10773 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
10774 SDValue Cmp = Cond.getOperand(0).getOperand(1);
10775 if (CondOpc == ISD::OR) {
10776 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
10777 // two branches instead of an explicit OR instruction with a
10779 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10780 isX86LogicalCmp(Cmp)) {
10781 CC = Cond.getOperand(0).getOperand(0);
10782 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10783 Chain, Dest, CC, Cmp);
10784 CC = Cond.getOperand(1).getOperand(0);
10788 } else { // ISD::AND
10789 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
10790 // two branches instead of an explicit AND instruction with a
10791 // separate test. However, we only do this if this block doesn't
10792 // have a fall-through edge, because this requires an explicit
10793 // jmp when the condition is false.
10794 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10795 isX86LogicalCmp(Cmp) &&
10796 Op.getNode()->hasOneUse()) {
10797 X86::CondCode CCode =
10798 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10799 CCode = X86::GetOppositeBranchCondition(CCode);
10800 CC = DAG.getConstant(CCode, MVT::i8);
10801 SDNode *User = *Op.getNode()->use_begin();
10802 // Look for an unconditional branch following this conditional branch.
10803 // We need this because we need to reverse the successors in order
10804 // to implement FCMP_OEQ.
10805 if (User->getOpcode() == ISD::BR) {
10806 SDValue FalseBB = User->getOperand(1);
10808 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10809 assert(NewBR == User);
10813 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10814 Chain, Dest, CC, Cmp);
10815 X86::CondCode CCode =
10816 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
10817 CCode = X86::GetOppositeBranchCondition(CCode);
10818 CC = DAG.getConstant(CCode, MVT::i8);
10824 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
10825 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
10826 // It should be transformed during dag combiner except when the condition
10827 // is set by a arithmetics with overflow node.
10828 X86::CondCode CCode =
10829 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10830 CCode = X86::GetOppositeBranchCondition(CCode);
10831 CC = DAG.getConstant(CCode, MVT::i8);
10832 Cond = Cond.getOperand(0).getOperand(1);
10834 } else if (Cond.getOpcode() == ISD::SETCC &&
10835 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
10836 // For FCMP_OEQ, we can emit
10837 // two branches instead of an explicit AND instruction with a
10838 // separate test. However, we only do this if this block doesn't
10839 // have a fall-through edge, because this requires an explicit
10840 // jmp when the condition is false.
10841 if (Op.getNode()->hasOneUse()) {
10842 SDNode *User = *Op.getNode()->use_begin();
10843 // Look for an unconditional branch following this conditional branch.
10844 // We need this because we need to reverse the successors in order
10845 // to implement FCMP_OEQ.
10846 if (User->getOpcode() == ISD::BR) {
10847 SDValue FalseBB = User->getOperand(1);
10849 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10850 assert(NewBR == User);
10854 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10855 Cond.getOperand(0), Cond.getOperand(1));
10856 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10857 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10858 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10859 Chain, Dest, CC, Cmp);
10860 CC = DAG.getConstant(X86::COND_P, MVT::i8);
10865 } else if (Cond.getOpcode() == ISD::SETCC &&
10866 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
10867 // For FCMP_UNE, we can emit
10868 // two branches instead of an explicit AND instruction with a
10869 // separate test. However, we only do this if this block doesn't
10870 // have a fall-through edge, because this requires an explicit
10871 // jmp when the condition is false.
10872 if (Op.getNode()->hasOneUse()) {
10873 SDNode *User = *Op.getNode()->use_begin();
10874 // Look for an unconditional branch following this conditional branch.
10875 // We need this because we need to reverse the successors in order
10876 // to implement FCMP_UNE.
10877 if (User->getOpcode() == ISD::BR) {
10878 SDValue FalseBB = User->getOperand(1);
10880 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10881 assert(NewBR == User);
10884 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10885 Cond.getOperand(0), Cond.getOperand(1));
10886 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10887 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10888 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10889 Chain, Dest, CC, Cmp);
10890 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
10900 // Look pass the truncate if the high bits are known zero.
10901 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10902 Cond = Cond.getOperand(0);
10904 // We know the result of AND is compared against zero. Try to match
10906 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10907 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
10908 if (NewSetCC.getNode()) {
10909 CC = NewSetCC.getOperand(0);
10910 Cond = NewSetCC.getOperand(1);
10917 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10918 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10920 Cond = ConvertCmpIfNecessary(Cond, DAG);
10921 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10922 Chain, Dest, CC, Cond);
10925 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
10926 // Calls to _alloca is needed to probe the stack when allocating more than 4k
10927 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
10928 // that the guard pages used by the OS virtual memory manager are allocated in
10929 // correct sequence.
10931 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
10932 SelectionDAG &DAG) const {
10933 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
10934 getTargetMachine().Options.EnableSegmentedStacks) &&
10935 "This should be used only on Windows targets or when segmented stacks "
10937 assert(!Subtarget->isTargetMacho() && "Not implemented");
10941 SDValue Chain = Op.getOperand(0);
10942 SDValue Size = Op.getOperand(1);
10943 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10944 EVT VT = Op.getNode()->getValueType(0);
10946 bool Is64Bit = Subtarget->is64Bit();
10947 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
10949 if (getTargetMachine().Options.EnableSegmentedStacks) {
10950 MachineFunction &MF = DAG.getMachineFunction();
10951 MachineRegisterInfo &MRI = MF.getRegInfo();
10954 // The 64 bit implementation of segmented stacks needs to clobber both r10
10955 // r11. This makes it impossible to use it along with nested parameters.
10956 const Function *F = MF.getFunction();
10958 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
10960 if (I->hasNestAttr())
10961 report_fatal_error("Cannot use segmented stacks with functions that "
10962 "have nested arguments.");
10965 const TargetRegisterClass *AddrRegClass =
10966 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
10967 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
10968 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
10969 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
10970 DAG.getRegister(Vreg, SPTy));
10971 SDValue Ops1[2] = { Value, Chain };
10972 return DAG.getMergeValues(Ops1, 2, dl);
10975 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
10977 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
10978 Flag = Chain.getValue(1);
10979 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10981 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
10983 const X86RegisterInfo *RegInfo =
10984 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
10985 unsigned SPReg = RegInfo->getStackRegister();
10986 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
10987 Chain = SP.getValue(1);
10990 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
10991 DAG.getConstant(-(uint64_t)Align, VT));
10992 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
10995 SDValue Ops1[2] = { SP, Chain };
10996 return DAG.getMergeValues(Ops1, 2, dl);
11000 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
11001 MachineFunction &MF = DAG.getMachineFunction();
11002 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
11004 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
11007 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
11008 // vastart just stores the address of the VarArgsFrameIndex slot into the
11009 // memory location argument.
11010 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
11012 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
11013 MachinePointerInfo(SV), false, false, 0);
11017 // gp_offset (0 - 6 * 8)
11018 // fp_offset (48 - 48 + 8 * 16)
11019 // overflow_arg_area (point to parameters coming in memory).
11021 SmallVector<SDValue, 8> MemOps;
11022 SDValue FIN = Op.getOperand(1);
11024 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
11025 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
11027 FIN, MachinePointerInfo(SV), false, false, 0);
11028 MemOps.push_back(Store);
11031 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11032 FIN, DAG.getIntPtrConstant(4));
11033 Store = DAG.getStore(Op.getOperand(0), DL,
11034 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
11036 FIN, MachinePointerInfo(SV, 4), false, false, 0);
11037 MemOps.push_back(Store);
11039 // Store ptr to overflow_arg_area
11040 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11041 FIN, DAG.getIntPtrConstant(4));
11042 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
11044 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
11045 MachinePointerInfo(SV, 8),
11047 MemOps.push_back(Store);
11049 // Store ptr to reg_save_area.
11050 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11051 FIN, DAG.getIntPtrConstant(8));
11052 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
11054 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
11055 MachinePointerInfo(SV, 16), false, false, 0);
11056 MemOps.push_back(Store);
11057 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
11058 &MemOps[0], MemOps.size());
11061 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
11062 assert(Subtarget->is64Bit() &&
11063 "LowerVAARG only handles 64-bit va_arg!");
11064 assert((Subtarget->isTargetLinux() ||
11065 Subtarget->isTargetDarwin()) &&
11066 "Unhandled target in LowerVAARG");
11067 assert(Op.getNode()->getNumOperands() == 4);
11068 SDValue Chain = Op.getOperand(0);
11069 SDValue SrcPtr = Op.getOperand(1);
11070 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
11071 unsigned Align = Op.getConstantOperandVal(3);
11074 EVT ArgVT = Op.getNode()->getValueType(0);
11075 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
11076 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
11079 // Decide which area this value should be read from.
11080 // TODO: Implement the AMD64 ABI in its entirety. This simple
11081 // selection mechanism works only for the basic types.
11082 if (ArgVT == MVT::f80) {
11083 llvm_unreachable("va_arg for f80 not yet implemented");
11084 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
11085 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
11086 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
11087 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
11089 llvm_unreachable("Unhandled argument type in LowerVAARG");
11092 if (ArgMode == 2) {
11093 // Sanity Check: Make sure using fp_offset makes sense.
11094 assert(!getTargetMachine().Options.UseSoftFloat &&
11095 !(DAG.getMachineFunction()
11096 .getFunction()->getAttributes()
11097 .hasAttribute(AttributeSet::FunctionIndex,
11098 Attribute::NoImplicitFloat)) &&
11099 Subtarget->hasSSE1());
11102 // Insert VAARG_64 node into the DAG
11103 // VAARG_64 returns two values: Variable Argument Address, Chain
11104 SmallVector<SDValue, 11> InstOps;
11105 InstOps.push_back(Chain);
11106 InstOps.push_back(SrcPtr);
11107 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
11108 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
11109 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
11110 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
11111 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
11112 VTs, &InstOps[0], InstOps.size(),
11114 MachinePointerInfo(SV),
11116 /*Volatile=*/false,
11118 /*WriteMem=*/true);
11119 Chain = VAARG.getValue(1);
11121 // Load the next argument and return it
11122 return DAG.getLoad(ArgVT, dl,
11125 MachinePointerInfo(),
11126 false, false, false, 0);
11129 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
11130 SelectionDAG &DAG) {
11131 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
11132 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
11133 SDValue Chain = Op.getOperand(0);
11134 SDValue DstPtr = Op.getOperand(1);
11135 SDValue SrcPtr = Op.getOperand(2);
11136 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
11137 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
11140 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
11141 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
11143 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
11146 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
11147 // amount is a constant. Takes immediate version of shift as input.
11148 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
11149 SDValue SrcOp, uint64_t ShiftAmt,
11150 SelectionDAG &DAG) {
11151 MVT ElementType = VT.getVectorElementType();
11153 // Check for ShiftAmt >= element width
11154 if (ShiftAmt >= ElementType.getSizeInBits()) {
11155 if (Opc == X86ISD::VSRAI)
11156 ShiftAmt = ElementType.getSizeInBits() - 1;
11158 return DAG.getConstant(0, VT);
11161 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
11162 && "Unknown target vector shift-by-constant node");
11164 // Fold this packed vector shift into a build vector if SrcOp is a
11165 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
11166 if (VT == SrcOp.getSimpleValueType() &&
11167 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
11168 SmallVector<SDValue, 8> Elts;
11169 unsigned NumElts = SrcOp->getNumOperands();
11170 ConstantSDNode *ND;
11173 default: llvm_unreachable(0);
11174 case X86ISD::VSHLI:
11175 for (unsigned i=0; i!=NumElts; ++i) {
11176 SDValue CurrentOp = SrcOp->getOperand(i);
11177 if (CurrentOp->getOpcode() == ISD::UNDEF) {
11178 Elts.push_back(CurrentOp);
11181 ND = cast<ConstantSDNode>(CurrentOp);
11182 const APInt &C = ND->getAPIntValue();
11183 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
11186 case X86ISD::VSRLI:
11187 for (unsigned i=0; i!=NumElts; ++i) {
11188 SDValue CurrentOp = SrcOp->getOperand(i);
11189 if (CurrentOp->getOpcode() == ISD::UNDEF) {
11190 Elts.push_back(CurrentOp);
11193 ND = cast<ConstantSDNode>(CurrentOp);
11194 const APInt &C = ND->getAPIntValue();
11195 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
11198 case X86ISD::VSRAI:
11199 for (unsigned i=0; i!=NumElts; ++i) {
11200 SDValue CurrentOp = SrcOp->getOperand(i);
11201 if (CurrentOp->getOpcode() == ISD::UNDEF) {
11202 Elts.push_back(CurrentOp);
11205 ND = cast<ConstantSDNode>(CurrentOp);
11206 const APInt &C = ND->getAPIntValue();
11207 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
11212 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Elts[0], NumElts);
11215 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
11218 // getTargetVShiftNode - Handle vector element shifts where the shift amount
11219 // may or may not be a constant. Takes immediate version of shift as input.
11220 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
11221 SDValue SrcOp, SDValue ShAmt,
11222 SelectionDAG &DAG) {
11223 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
11225 // Catch shift-by-constant.
11226 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
11227 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
11228 CShAmt->getZExtValue(), DAG);
11230 // Change opcode to non-immediate version
11232 default: llvm_unreachable("Unknown target vector shift node");
11233 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
11234 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
11235 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
11238 // Need to build a vector containing shift amount
11239 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
11242 ShOps[1] = DAG.getConstant(0, MVT::i32);
11243 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
11244 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
11246 // The return type has to be a 128-bit type with the same element
11247 // type as the input type.
11248 MVT EltVT = VT.getVectorElementType();
11249 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
11251 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
11252 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
11255 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
11257 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11259 default: return SDValue(); // Don't custom lower most intrinsics.
11260 // Comparison intrinsics.
11261 case Intrinsic::x86_sse_comieq_ss:
11262 case Intrinsic::x86_sse_comilt_ss:
11263 case Intrinsic::x86_sse_comile_ss:
11264 case Intrinsic::x86_sse_comigt_ss:
11265 case Intrinsic::x86_sse_comige_ss:
11266 case Intrinsic::x86_sse_comineq_ss:
11267 case Intrinsic::x86_sse_ucomieq_ss:
11268 case Intrinsic::x86_sse_ucomilt_ss:
11269 case Intrinsic::x86_sse_ucomile_ss:
11270 case Intrinsic::x86_sse_ucomigt_ss:
11271 case Intrinsic::x86_sse_ucomige_ss:
11272 case Intrinsic::x86_sse_ucomineq_ss:
11273 case Intrinsic::x86_sse2_comieq_sd:
11274 case Intrinsic::x86_sse2_comilt_sd:
11275 case Intrinsic::x86_sse2_comile_sd:
11276 case Intrinsic::x86_sse2_comigt_sd:
11277 case Intrinsic::x86_sse2_comige_sd:
11278 case Intrinsic::x86_sse2_comineq_sd:
11279 case Intrinsic::x86_sse2_ucomieq_sd:
11280 case Intrinsic::x86_sse2_ucomilt_sd:
11281 case Intrinsic::x86_sse2_ucomile_sd:
11282 case Intrinsic::x86_sse2_ucomigt_sd:
11283 case Intrinsic::x86_sse2_ucomige_sd:
11284 case Intrinsic::x86_sse2_ucomineq_sd: {
11288 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11289 case Intrinsic::x86_sse_comieq_ss:
11290 case Intrinsic::x86_sse2_comieq_sd:
11291 Opc = X86ISD::COMI;
11294 case Intrinsic::x86_sse_comilt_ss:
11295 case Intrinsic::x86_sse2_comilt_sd:
11296 Opc = X86ISD::COMI;
11299 case Intrinsic::x86_sse_comile_ss:
11300 case Intrinsic::x86_sse2_comile_sd:
11301 Opc = X86ISD::COMI;
11304 case Intrinsic::x86_sse_comigt_ss:
11305 case Intrinsic::x86_sse2_comigt_sd:
11306 Opc = X86ISD::COMI;
11309 case Intrinsic::x86_sse_comige_ss:
11310 case Intrinsic::x86_sse2_comige_sd:
11311 Opc = X86ISD::COMI;
11314 case Intrinsic::x86_sse_comineq_ss:
11315 case Intrinsic::x86_sse2_comineq_sd:
11316 Opc = X86ISD::COMI;
11319 case Intrinsic::x86_sse_ucomieq_ss:
11320 case Intrinsic::x86_sse2_ucomieq_sd:
11321 Opc = X86ISD::UCOMI;
11324 case Intrinsic::x86_sse_ucomilt_ss:
11325 case Intrinsic::x86_sse2_ucomilt_sd:
11326 Opc = X86ISD::UCOMI;
11329 case Intrinsic::x86_sse_ucomile_ss:
11330 case Intrinsic::x86_sse2_ucomile_sd:
11331 Opc = X86ISD::UCOMI;
11334 case Intrinsic::x86_sse_ucomigt_ss:
11335 case Intrinsic::x86_sse2_ucomigt_sd:
11336 Opc = X86ISD::UCOMI;
11339 case Intrinsic::x86_sse_ucomige_ss:
11340 case Intrinsic::x86_sse2_ucomige_sd:
11341 Opc = X86ISD::UCOMI;
11344 case Intrinsic::x86_sse_ucomineq_ss:
11345 case Intrinsic::x86_sse2_ucomineq_sd:
11346 Opc = X86ISD::UCOMI;
11351 SDValue LHS = Op.getOperand(1);
11352 SDValue RHS = Op.getOperand(2);
11353 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
11354 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
11355 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
11356 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11357 DAG.getConstant(X86CC, MVT::i8), Cond);
11358 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11361 // Arithmetic intrinsics.
11362 case Intrinsic::x86_sse2_pmulu_dq:
11363 case Intrinsic::x86_avx2_pmulu_dq:
11364 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
11365 Op.getOperand(1), Op.getOperand(2));
11367 // SSE2/AVX2 sub with unsigned saturation intrinsics
11368 case Intrinsic::x86_sse2_psubus_b:
11369 case Intrinsic::x86_sse2_psubus_w:
11370 case Intrinsic::x86_avx2_psubus_b:
11371 case Intrinsic::x86_avx2_psubus_w:
11372 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
11373 Op.getOperand(1), Op.getOperand(2));
11375 // SSE3/AVX horizontal add/sub intrinsics
11376 case Intrinsic::x86_sse3_hadd_ps:
11377 case Intrinsic::x86_sse3_hadd_pd:
11378 case Intrinsic::x86_avx_hadd_ps_256:
11379 case Intrinsic::x86_avx_hadd_pd_256:
11380 case Intrinsic::x86_sse3_hsub_ps:
11381 case Intrinsic::x86_sse3_hsub_pd:
11382 case Intrinsic::x86_avx_hsub_ps_256:
11383 case Intrinsic::x86_avx_hsub_pd_256:
11384 case Intrinsic::x86_ssse3_phadd_w_128:
11385 case Intrinsic::x86_ssse3_phadd_d_128:
11386 case Intrinsic::x86_avx2_phadd_w:
11387 case Intrinsic::x86_avx2_phadd_d:
11388 case Intrinsic::x86_ssse3_phsub_w_128:
11389 case Intrinsic::x86_ssse3_phsub_d_128:
11390 case Intrinsic::x86_avx2_phsub_w:
11391 case Intrinsic::x86_avx2_phsub_d: {
11394 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11395 case Intrinsic::x86_sse3_hadd_ps:
11396 case Intrinsic::x86_sse3_hadd_pd:
11397 case Intrinsic::x86_avx_hadd_ps_256:
11398 case Intrinsic::x86_avx_hadd_pd_256:
11399 Opcode = X86ISD::FHADD;
11401 case Intrinsic::x86_sse3_hsub_ps:
11402 case Intrinsic::x86_sse3_hsub_pd:
11403 case Intrinsic::x86_avx_hsub_ps_256:
11404 case Intrinsic::x86_avx_hsub_pd_256:
11405 Opcode = X86ISD::FHSUB;
11407 case Intrinsic::x86_ssse3_phadd_w_128:
11408 case Intrinsic::x86_ssse3_phadd_d_128:
11409 case Intrinsic::x86_avx2_phadd_w:
11410 case Intrinsic::x86_avx2_phadd_d:
11411 Opcode = X86ISD::HADD;
11413 case Intrinsic::x86_ssse3_phsub_w_128:
11414 case Intrinsic::x86_ssse3_phsub_d_128:
11415 case Intrinsic::x86_avx2_phsub_w:
11416 case Intrinsic::x86_avx2_phsub_d:
11417 Opcode = X86ISD::HSUB;
11420 return DAG.getNode(Opcode, dl, Op.getValueType(),
11421 Op.getOperand(1), Op.getOperand(2));
11424 // SSE2/SSE41/AVX2 integer max/min intrinsics.
11425 case Intrinsic::x86_sse2_pmaxu_b:
11426 case Intrinsic::x86_sse41_pmaxuw:
11427 case Intrinsic::x86_sse41_pmaxud:
11428 case Intrinsic::x86_avx2_pmaxu_b:
11429 case Intrinsic::x86_avx2_pmaxu_w:
11430 case Intrinsic::x86_avx2_pmaxu_d:
11431 case Intrinsic::x86_sse2_pminu_b:
11432 case Intrinsic::x86_sse41_pminuw:
11433 case Intrinsic::x86_sse41_pminud:
11434 case Intrinsic::x86_avx2_pminu_b:
11435 case Intrinsic::x86_avx2_pminu_w:
11436 case Intrinsic::x86_avx2_pminu_d:
11437 case Intrinsic::x86_sse41_pmaxsb:
11438 case Intrinsic::x86_sse2_pmaxs_w:
11439 case Intrinsic::x86_sse41_pmaxsd:
11440 case Intrinsic::x86_avx2_pmaxs_b:
11441 case Intrinsic::x86_avx2_pmaxs_w:
11442 case Intrinsic::x86_avx2_pmaxs_d:
11443 case Intrinsic::x86_sse41_pminsb:
11444 case Intrinsic::x86_sse2_pmins_w:
11445 case Intrinsic::x86_sse41_pminsd:
11446 case Intrinsic::x86_avx2_pmins_b:
11447 case Intrinsic::x86_avx2_pmins_w:
11448 case Intrinsic::x86_avx2_pmins_d: {
11451 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11452 case Intrinsic::x86_sse2_pmaxu_b:
11453 case Intrinsic::x86_sse41_pmaxuw:
11454 case Intrinsic::x86_sse41_pmaxud:
11455 case Intrinsic::x86_avx2_pmaxu_b:
11456 case Intrinsic::x86_avx2_pmaxu_w:
11457 case Intrinsic::x86_avx2_pmaxu_d:
11458 Opcode = X86ISD::UMAX;
11460 case Intrinsic::x86_sse2_pminu_b:
11461 case Intrinsic::x86_sse41_pminuw:
11462 case Intrinsic::x86_sse41_pminud:
11463 case Intrinsic::x86_avx2_pminu_b:
11464 case Intrinsic::x86_avx2_pminu_w:
11465 case Intrinsic::x86_avx2_pminu_d:
11466 Opcode = X86ISD::UMIN;
11468 case Intrinsic::x86_sse41_pmaxsb:
11469 case Intrinsic::x86_sse2_pmaxs_w:
11470 case Intrinsic::x86_sse41_pmaxsd:
11471 case Intrinsic::x86_avx2_pmaxs_b:
11472 case Intrinsic::x86_avx2_pmaxs_w:
11473 case Intrinsic::x86_avx2_pmaxs_d:
11474 Opcode = X86ISD::SMAX;
11476 case Intrinsic::x86_sse41_pminsb:
11477 case Intrinsic::x86_sse2_pmins_w:
11478 case Intrinsic::x86_sse41_pminsd:
11479 case Intrinsic::x86_avx2_pmins_b:
11480 case Intrinsic::x86_avx2_pmins_w:
11481 case Intrinsic::x86_avx2_pmins_d:
11482 Opcode = X86ISD::SMIN;
11485 return DAG.getNode(Opcode, dl, Op.getValueType(),
11486 Op.getOperand(1), Op.getOperand(2));
11489 // SSE/SSE2/AVX floating point max/min intrinsics.
11490 case Intrinsic::x86_sse_max_ps:
11491 case Intrinsic::x86_sse2_max_pd:
11492 case Intrinsic::x86_avx_max_ps_256:
11493 case Intrinsic::x86_avx_max_pd_256:
11494 case Intrinsic::x86_sse_min_ps:
11495 case Intrinsic::x86_sse2_min_pd:
11496 case Intrinsic::x86_avx_min_ps_256:
11497 case Intrinsic::x86_avx_min_pd_256: {
11500 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11501 case Intrinsic::x86_sse_max_ps:
11502 case Intrinsic::x86_sse2_max_pd:
11503 case Intrinsic::x86_avx_max_ps_256:
11504 case Intrinsic::x86_avx_max_pd_256:
11505 Opcode = X86ISD::FMAX;
11507 case Intrinsic::x86_sse_min_ps:
11508 case Intrinsic::x86_sse2_min_pd:
11509 case Intrinsic::x86_avx_min_ps_256:
11510 case Intrinsic::x86_avx_min_pd_256:
11511 Opcode = X86ISD::FMIN;
11514 return DAG.getNode(Opcode, dl, Op.getValueType(),
11515 Op.getOperand(1), Op.getOperand(2));
11518 // AVX2 variable shift intrinsics
11519 case Intrinsic::x86_avx2_psllv_d:
11520 case Intrinsic::x86_avx2_psllv_q:
11521 case Intrinsic::x86_avx2_psllv_d_256:
11522 case Intrinsic::x86_avx2_psllv_q_256:
11523 case Intrinsic::x86_avx2_psrlv_d:
11524 case Intrinsic::x86_avx2_psrlv_q:
11525 case Intrinsic::x86_avx2_psrlv_d_256:
11526 case Intrinsic::x86_avx2_psrlv_q_256:
11527 case Intrinsic::x86_avx2_psrav_d:
11528 case Intrinsic::x86_avx2_psrav_d_256: {
11531 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11532 case Intrinsic::x86_avx2_psllv_d:
11533 case Intrinsic::x86_avx2_psllv_q:
11534 case Intrinsic::x86_avx2_psllv_d_256:
11535 case Intrinsic::x86_avx2_psllv_q_256:
11538 case Intrinsic::x86_avx2_psrlv_d:
11539 case Intrinsic::x86_avx2_psrlv_q:
11540 case Intrinsic::x86_avx2_psrlv_d_256:
11541 case Intrinsic::x86_avx2_psrlv_q_256:
11544 case Intrinsic::x86_avx2_psrav_d:
11545 case Intrinsic::x86_avx2_psrav_d_256:
11549 return DAG.getNode(Opcode, dl, Op.getValueType(),
11550 Op.getOperand(1), Op.getOperand(2));
11553 case Intrinsic::x86_ssse3_pshuf_b_128:
11554 case Intrinsic::x86_avx2_pshuf_b:
11555 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
11556 Op.getOperand(1), Op.getOperand(2));
11558 case Intrinsic::x86_ssse3_psign_b_128:
11559 case Intrinsic::x86_ssse3_psign_w_128:
11560 case Intrinsic::x86_ssse3_psign_d_128:
11561 case Intrinsic::x86_avx2_psign_b:
11562 case Intrinsic::x86_avx2_psign_w:
11563 case Intrinsic::x86_avx2_psign_d:
11564 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
11565 Op.getOperand(1), Op.getOperand(2));
11567 case Intrinsic::x86_sse41_insertps:
11568 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
11569 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11571 case Intrinsic::x86_avx_vperm2f128_ps_256:
11572 case Intrinsic::x86_avx_vperm2f128_pd_256:
11573 case Intrinsic::x86_avx_vperm2f128_si_256:
11574 case Intrinsic::x86_avx2_vperm2i128:
11575 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
11576 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11578 case Intrinsic::x86_avx2_permd:
11579 case Intrinsic::x86_avx2_permps:
11580 // Operands intentionally swapped. Mask is last operand to intrinsic,
11581 // but second operand for node/instruction.
11582 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
11583 Op.getOperand(2), Op.getOperand(1));
11585 case Intrinsic::x86_sse_sqrt_ps:
11586 case Intrinsic::x86_sse2_sqrt_pd:
11587 case Intrinsic::x86_avx_sqrt_ps_256:
11588 case Intrinsic::x86_avx_sqrt_pd_256:
11589 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
11591 // ptest and testp intrinsics. The intrinsic these come from are designed to
11592 // return an integer value, not just an instruction so lower it to the ptest
11593 // or testp pattern and a setcc for the result.
11594 case Intrinsic::x86_sse41_ptestz:
11595 case Intrinsic::x86_sse41_ptestc:
11596 case Intrinsic::x86_sse41_ptestnzc:
11597 case Intrinsic::x86_avx_ptestz_256:
11598 case Intrinsic::x86_avx_ptestc_256:
11599 case Intrinsic::x86_avx_ptestnzc_256:
11600 case Intrinsic::x86_avx_vtestz_ps:
11601 case Intrinsic::x86_avx_vtestc_ps:
11602 case Intrinsic::x86_avx_vtestnzc_ps:
11603 case Intrinsic::x86_avx_vtestz_pd:
11604 case Intrinsic::x86_avx_vtestc_pd:
11605 case Intrinsic::x86_avx_vtestnzc_pd:
11606 case Intrinsic::x86_avx_vtestz_ps_256:
11607 case Intrinsic::x86_avx_vtestc_ps_256:
11608 case Intrinsic::x86_avx_vtestnzc_ps_256:
11609 case Intrinsic::x86_avx_vtestz_pd_256:
11610 case Intrinsic::x86_avx_vtestc_pd_256:
11611 case Intrinsic::x86_avx_vtestnzc_pd_256: {
11612 bool IsTestPacked = false;
11615 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
11616 case Intrinsic::x86_avx_vtestz_ps:
11617 case Intrinsic::x86_avx_vtestz_pd:
11618 case Intrinsic::x86_avx_vtestz_ps_256:
11619 case Intrinsic::x86_avx_vtestz_pd_256:
11620 IsTestPacked = true; // Fallthrough
11621 case Intrinsic::x86_sse41_ptestz:
11622 case Intrinsic::x86_avx_ptestz_256:
11624 X86CC = X86::COND_E;
11626 case Intrinsic::x86_avx_vtestc_ps:
11627 case Intrinsic::x86_avx_vtestc_pd:
11628 case Intrinsic::x86_avx_vtestc_ps_256:
11629 case Intrinsic::x86_avx_vtestc_pd_256:
11630 IsTestPacked = true; // Fallthrough
11631 case Intrinsic::x86_sse41_ptestc:
11632 case Intrinsic::x86_avx_ptestc_256:
11634 X86CC = X86::COND_B;
11636 case Intrinsic::x86_avx_vtestnzc_ps:
11637 case Intrinsic::x86_avx_vtestnzc_pd:
11638 case Intrinsic::x86_avx_vtestnzc_ps_256:
11639 case Intrinsic::x86_avx_vtestnzc_pd_256:
11640 IsTestPacked = true; // Fallthrough
11641 case Intrinsic::x86_sse41_ptestnzc:
11642 case Intrinsic::x86_avx_ptestnzc_256:
11644 X86CC = X86::COND_A;
11648 SDValue LHS = Op.getOperand(1);
11649 SDValue RHS = Op.getOperand(2);
11650 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
11651 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
11652 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11653 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
11654 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11656 case Intrinsic::x86_avx512_kortestz_w:
11657 case Intrinsic::x86_avx512_kortestc_w: {
11658 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
11659 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
11660 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
11661 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11662 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
11663 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
11664 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11667 // SSE/AVX shift intrinsics
11668 case Intrinsic::x86_sse2_psll_w:
11669 case Intrinsic::x86_sse2_psll_d:
11670 case Intrinsic::x86_sse2_psll_q:
11671 case Intrinsic::x86_avx2_psll_w:
11672 case Intrinsic::x86_avx2_psll_d:
11673 case Intrinsic::x86_avx2_psll_q:
11674 case Intrinsic::x86_sse2_psrl_w:
11675 case Intrinsic::x86_sse2_psrl_d:
11676 case Intrinsic::x86_sse2_psrl_q:
11677 case Intrinsic::x86_avx2_psrl_w:
11678 case Intrinsic::x86_avx2_psrl_d:
11679 case Intrinsic::x86_avx2_psrl_q:
11680 case Intrinsic::x86_sse2_psra_w:
11681 case Intrinsic::x86_sse2_psra_d:
11682 case Intrinsic::x86_avx2_psra_w:
11683 case Intrinsic::x86_avx2_psra_d: {
11686 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11687 case Intrinsic::x86_sse2_psll_w:
11688 case Intrinsic::x86_sse2_psll_d:
11689 case Intrinsic::x86_sse2_psll_q:
11690 case Intrinsic::x86_avx2_psll_w:
11691 case Intrinsic::x86_avx2_psll_d:
11692 case Intrinsic::x86_avx2_psll_q:
11693 Opcode = X86ISD::VSHL;
11695 case Intrinsic::x86_sse2_psrl_w:
11696 case Intrinsic::x86_sse2_psrl_d:
11697 case Intrinsic::x86_sse2_psrl_q:
11698 case Intrinsic::x86_avx2_psrl_w:
11699 case Intrinsic::x86_avx2_psrl_d:
11700 case Intrinsic::x86_avx2_psrl_q:
11701 Opcode = X86ISD::VSRL;
11703 case Intrinsic::x86_sse2_psra_w:
11704 case Intrinsic::x86_sse2_psra_d:
11705 case Intrinsic::x86_avx2_psra_w:
11706 case Intrinsic::x86_avx2_psra_d:
11707 Opcode = X86ISD::VSRA;
11710 return DAG.getNode(Opcode, dl, Op.getValueType(),
11711 Op.getOperand(1), Op.getOperand(2));
11714 // SSE/AVX immediate shift intrinsics
11715 case Intrinsic::x86_sse2_pslli_w:
11716 case Intrinsic::x86_sse2_pslli_d:
11717 case Intrinsic::x86_sse2_pslli_q:
11718 case Intrinsic::x86_avx2_pslli_w:
11719 case Intrinsic::x86_avx2_pslli_d:
11720 case Intrinsic::x86_avx2_pslli_q:
11721 case Intrinsic::x86_sse2_psrli_w:
11722 case Intrinsic::x86_sse2_psrli_d:
11723 case Intrinsic::x86_sse2_psrli_q:
11724 case Intrinsic::x86_avx2_psrli_w:
11725 case Intrinsic::x86_avx2_psrli_d:
11726 case Intrinsic::x86_avx2_psrli_q:
11727 case Intrinsic::x86_sse2_psrai_w:
11728 case Intrinsic::x86_sse2_psrai_d:
11729 case Intrinsic::x86_avx2_psrai_w:
11730 case Intrinsic::x86_avx2_psrai_d: {
11733 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11734 case Intrinsic::x86_sse2_pslli_w:
11735 case Intrinsic::x86_sse2_pslli_d:
11736 case Intrinsic::x86_sse2_pslli_q:
11737 case Intrinsic::x86_avx2_pslli_w:
11738 case Intrinsic::x86_avx2_pslli_d:
11739 case Intrinsic::x86_avx2_pslli_q:
11740 Opcode = X86ISD::VSHLI;
11742 case Intrinsic::x86_sse2_psrli_w:
11743 case Intrinsic::x86_sse2_psrli_d:
11744 case Intrinsic::x86_sse2_psrli_q:
11745 case Intrinsic::x86_avx2_psrli_w:
11746 case Intrinsic::x86_avx2_psrli_d:
11747 case Intrinsic::x86_avx2_psrli_q:
11748 Opcode = X86ISD::VSRLI;
11750 case Intrinsic::x86_sse2_psrai_w:
11751 case Intrinsic::x86_sse2_psrai_d:
11752 case Intrinsic::x86_avx2_psrai_w:
11753 case Intrinsic::x86_avx2_psrai_d:
11754 Opcode = X86ISD::VSRAI;
11757 return getTargetVShiftNode(Opcode, dl, Op.getSimpleValueType(),
11758 Op.getOperand(1), Op.getOperand(2), DAG);
11761 case Intrinsic::x86_sse42_pcmpistria128:
11762 case Intrinsic::x86_sse42_pcmpestria128:
11763 case Intrinsic::x86_sse42_pcmpistric128:
11764 case Intrinsic::x86_sse42_pcmpestric128:
11765 case Intrinsic::x86_sse42_pcmpistrio128:
11766 case Intrinsic::x86_sse42_pcmpestrio128:
11767 case Intrinsic::x86_sse42_pcmpistris128:
11768 case Intrinsic::x86_sse42_pcmpestris128:
11769 case Intrinsic::x86_sse42_pcmpistriz128:
11770 case Intrinsic::x86_sse42_pcmpestriz128: {
11774 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11775 case Intrinsic::x86_sse42_pcmpistria128:
11776 Opcode = X86ISD::PCMPISTRI;
11777 X86CC = X86::COND_A;
11779 case Intrinsic::x86_sse42_pcmpestria128:
11780 Opcode = X86ISD::PCMPESTRI;
11781 X86CC = X86::COND_A;
11783 case Intrinsic::x86_sse42_pcmpistric128:
11784 Opcode = X86ISD::PCMPISTRI;
11785 X86CC = X86::COND_B;
11787 case Intrinsic::x86_sse42_pcmpestric128:
11788 Opcode = X86ISD::PCMPESTRI;
11789 X86CC = X86::COND_B;
11791 case Intrinsic::x86_sse42_pcmpistrio128:
11792 Opcode = X86ISD::PCMPISTRI;
11793 X86CC = X86::COND_O;
11795 case Intrinsic::x86_sse42_pcmpestrio128:
11796 Opcode = X86ISD::PCMPESTRI;
11797 X86CC = X86::COND_O;
11799 case Intrinsic::x86_sse42_pcmpistris128:
11800 Opcode = X86ISD::PCMPISTRI;
11801 X86CC = X86::COND_S;
11803 case Intrinsic::x86_sse42_pcmpestris128:
11804 Opcode = X86ISD::PCMPESTRI;
11805 X86CC = X86::COND_S;
11807 case Intrinsic::x86_sse42_pcmpistriz128:
11808 Opcode = X86ISD::PCMPISTRI;
11809 X86CC = X86::COND_E;
11811 case Intrinsic::x86_sse42_pcmpestriz128:
11812 Opcode = X86ISD::PCMPESTRI;
11813 X86CC = X86::COND_E;
11816 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11817 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11818 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11819 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11820 DAG.getConstant(X86CC, MVT::i8),
11821 SDValue(PCMP.getNode(), 1));
11822 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11825 case Intrinsic::x86_sse42_pcmpistri128:
11826 case Intrinsic::x86_sse42_pcmpestri128: {
11828 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
11829 Opcode = X86ISD::PCMPISTRI;
11831 Opcode = X86ISD::PCMPESTRI;
11833 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11834 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11835 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11837 case Intrinsic::x86_fma_vfmadd_ps:
11838 case Intrinsic::x86_fma_vfmadd_pd:
11839 case Intrinsic::x86_fma_vfmsub_ps:
11840 case Intrinsic::x86_fma_vfmsub_pd:
11841 case Intrinsic::x86_fma_vfnmadd_ps:
11842 case Intrinsic::x86_fma_vfnmadd_pd:
11843 case Intrinsic::x86_fma_vfnmsub_ps:
11844 case Intrinsic::x86_fma_vfnmsub_pd:
11845 case Intrinsic::x86_fma_vfmaddsub_ps:
11846 case Intrinsic::x86_fma_vfmaddsub_pd:
11847 case Intrinsic::x86_fma_vfmsubadd_ps:
11848 case Intrinsic::x86_fma_vfmsubadd_pd:
11849 case Intrinsic::x86_fma_vfmadd_ps_256:
11850 case Intrinsic::x86_fma_vfmadd_pd_256:
11851 case Intrinsic::x86_fma_vfmsub_ps_256:
11852 case Intrinsic::x86_fma_vfmsub_pd_256:
11853 case Intrinsic::x86_fma_vfnmadd_ps_256:
11854 case Intrinsic::x86_fma_vfnmadd_pd_256:
11855 case Intrinsic::x86_fma_vfnmsub_ps_256:
11856 case Intrinsic::x86_fma_vfnmsub_pd_256:
11857 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11858 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11859 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11860 case Intrinsic::x86_fma_vfmsubadd_pd_256:
11861 case Intrinsic::x86_fma_vfmadd_ps_512:
11862 case Intrinsic::x86_fma_vfmadd_pd_512:
11863 case Intrinsic::x86_fma_vfmsub_ps_512:
11864 case Intrinsic::x86_fma_vfmsub_pd_512:
11865 case Intrinsic::x86_fma_vfnmadd_ps_512:
11866 case Intrinsic::x86_fma_vfnmadd_pd_512:
11867 case Intrinsic::x86_fma_vfnmsub_ps_512:
11868 case Intrinsic::x86_fma_vfnmsub_pd_512:
11869 case Intrinsic::x86_fma_vfmaddsub_ps_512:
11870 case Intrinsic::x86_fma_vfmaddsub_pd_512:
11871 case Intrinsic::x86_fma_vfmsubadd_ps_512:
11872 case Intrinsic::x86_fma_vfmsubadd_pd_512: {
11875 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11876 case Intrinsic::x86_fma_vfmadd_ps:
11877 case Intrinsic::x86_fma_vfmadd_pd:
11878 case Intrinsic::x86_fma_vfmadd_ps_256:
11879 case Intrinsic::x86_fma_vfmadd_pd_256:
11880 case Intrinsic::x86_fma_vfmadd_ps_512:
11881 case Intrinsic::x86_fma_vfmadd_pd_512:
11882 Opc = X86ISD::FMADD;
11884 case Intrinsic::x86_fma_vfmsub_ps:
11885 case Intrinsic::x86_fma_vfmsub_pd:
11886 case Intrinsic::x86_fma_vfmsub_ps_256:
11887 case Intrinsic::x86_fma_vfmsub_pd_256:
11888 case Intrinsic::x86_fma_vfmsub_ps_512:
11889 case Intrinsic::x86_fma_vfmsub_pd_512:
11890 Opc = X86ISD::FMSUB;
11892 case Intrinsic::x86_fma_vfnmadd_ps:
11893 case Intrinsic::x86_fma_vfnmadd_pd:
11894 case Intrinsic::x86_fma_vfnmadd_ps_256:
11895 case Intrinsic::x86_fma_vfnmadd_pd_256:
11896 case Intrinsic::x86_fma_vfnmadd_ps_512:
11897 case Intrinsic::x86_fma_vfnmadd_pd_512:
11898 Opc = X86ISD::FNMADD;
11900 case Intrinsic::x86_fma_vfnmsub_ps:
11901 case Intrinsic::x86_fma_vfnmsub_pd:
11902 case Intrinsic::x86_fma_vfnmsub_ps_256:
11903 case Intrinsic::x86_fma_vfnmsub_pd_256:
11904 case Intrinsic::x86_fma_vfnmsub_ps_512:
11905 case Intrinsic::x86_fma_vfnmsub_pd_512:
11906 Opc = X86ISD::FNMSUB;
11908 case Intrinsic::x86_fma_vfmaddsub_ps:
11909 case Intrinsic::x86_fma_vfmaddsub_pd:
11910 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11911 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11912 case Intrinsic::x86_fma_vfmaddsub_ps_512:
11913 case Intrinsic::x86_fma_vfmaddsub_pd_512:
11914 Opc = X86ISD::FMADDSUB;
11916 case Intrinsic::x86_fma_vfmsubadd_ps:
11917 case Intrinsic::x86_fma_vfmsubadd_pd:
11918 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11919 case Intrinsic::x86_fma_vfmsubadd_pd_256:
11920 case Intrinsic::x86_fma_vfmsubadd_ps_512:
11921 case Intrinsic::x86_fma_vfmsubadd_pd_512:
11922 Opc = X86ISD::FMSUBADD;
11926 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
11927 Op.getOperand(2), Op.getOperand(3));
11932 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11933 SDValue Base, SDValue Index,
11934 SDValue ScaleOp, SDValue Chain,
11935 const X86Subtarget * Subtarget) {
11937 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11938 assert(C && "Invalid scale type");
11939 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11940 SDValue Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
11941 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11942 Index.getSimpleValueType().getVectorNumElements());
11943 SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
11944 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
11945 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11946 SDValue Segment = DAG.getRegister(0, MVT::i32);
11947 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
11948 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11949 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
11950 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
11953 static SDValue getMGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11954 SDValue Src, SDValue Mask, SDValue Base,
11955 SDValue Index, SDValue ScaleOp, SDValue Chain,
11956 const X86Subtarget * Subtarget) {
11958 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11959 assert(C && "Invalid scale type");
11960 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11961 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11962 Index.getSimpleValueType().getVectorNumElements());
11963 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
11964 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
11965 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11966 SDValue Segment = DAG.getRegister(0, MVT::i32);
11967 if (Src.getOpcode() == ISD::UNDEF)
11968 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
11969 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
11970 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11971 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
11972 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
11975 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11976 SDValue Src, SDValue Base, SDValue Index,
11977 SDValue ScaleOp, SDValue Chain) {
11979 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11980 assert(C && "Invalid scale type");
11981 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11982 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11983 SDValue Segment = DAG.getRegister(0, MVT::i32);
11984 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11985 Index.getSimpleValueType().getVectorNumElements());
11986 SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
11987 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
11988 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
11989 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11990 return SDValue(Res, 1);
11993 static SDValue getMScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11994 SDValue Src, SDValue Mask, SDValue Base,
11995 SDValue Index, SDValue ScaleOp, SDValue Chain) {
11997 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11998 assert(C && "Invalid scale type");
11999 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
12000 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
12001 SDValue Segment = DAG.getRegister(0, MVT::i32);
12002 EVT MaskVT = MVT::getVectorVT(MVT::i1,
12003 Index.getSimpleValueType().getVectorNumElements());
12004 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
12005 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
12006 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
12007 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
12008 return SDValue(Res, 1);
12011 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
12012 SelectionDAG &DAG) {
12014 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12016 default: return SDValue(); // Don't custom lower most intrinsics.
12018 // RDRAND/RDSEED intrinsics.
12019 case Intrinsic::x86_rdrand_16:
12020 case Intrinsic::x86_rdrand_32:
12021 case Intrinsic::x86_rdrand_64:
12022 case Intrinsic::x86_rdseed_16:
12023 case Intrinsic::x86_rdseed_32:
12024 case Intrinsic::x86_rdseed_64: {
12025 unsigned Opcode = (IntNo == Intrinsic::x86_rdseed_16 ||
12026 IntNo == Intrinsic::x86_rdseed_32 ||
12027 IntNo == Intrinsic::x86_rdseed_64) ? X86ISD::RDSEED :
12029 // Emit the node with the right value type.
12030 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
12031 SDValue Result = DAG.getNode(Opcode, dl, VTs, Op.getOperand(0));
12033 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
12034 // Otherwise return the value from Rand, which is always 0, casted to i32.
12035 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
12036 DAG.getConstant(1, Op->getValueType(1)),
12037 DAG.getConstant(X86::COND_B, MVT::i32),
12038 SDValue(Result.getNode(), 1) };
12039 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
12040 DAG.getVTList(Op->getValueType(1), MVT::Glue),
12041 Ops, array_lengthof(Ops));
12043 // Return { result, isValid, chain }.
12044 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
12045 SDValue(Result.getNode(), 2));
12047 //int_gather(index, base, scale);
12048 case Intrinsic::x86_avx512_gather_qpd_512:
12049 case Intrinsic::x86_avx512_gather_qps_512:
12050 case Intrinsic::x86_avx512_gather_dpd_512:
12051 case Intrinsic::x86_avx512_gather_qpi_512:
12052 case Intrinsic::x86_avx512_gather_qpq_512:
12053 case Intrinsic::x86_avx512_gather_dpq_512:
12054 case Intrinsic::x86_avx512_gather_dps_512:
12055 case Intrinsic::x86_avx512_gather_dpi_512: {
12058 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12059 case Intrinsic::x86_avx512_gather_qps_512: Opc = X86::VGATHERQPSZrm; break;
12060 case Intrinsic::x86_avx512_gather_qpd_512: Opc = X86::VGATHERQPDZrm; break;
12061 case Intrinsic::x86_avx512_gather_dpd_512: Opc = X86::VGATHERDPDZrm; break;
12062 case Intrinsic::x86_avx512_gather_dps_512: Opc = X86::VGATHERDPSZrm; break;
12063 case Intrinsic::x86_avx512_gather_qpi_512: Opc = X86::VPGATHERQDZrm; break;
12064 case Intrinsic::x86_avx512_gather_qpq_512: Opc = X86::VPGATHERQQZrm; break;
12065 case Intrinsic::x86_avx512_gather_dpi_512: Opc = X86::VPGATHERDDZrm; break;
12066 case Intrinsic::x86_avx512_gather_dpq_512: Opc = X86::VPGATHERDQZrm; break;
12068 SDValue Chain = Op.getOperand(0);
12069 SDValue Index = Op.getOperand(2);
12070 SDValue Base = Op.getOperand(3);
12071 SDValue Scale = Op.getOperand(4);
12072 return getGatherNode(Opc, Op, DAG, Base, Index, Scale, Chain, Subtarget);
12074 //int_gather_mask(v1, mask, index, base, scale);
12075 case Intrinsic::x86_avx512_gather_qps_mask_512:
12076 case Intrinsic::x86_avx512_gather_qpd_mask_512:
12077 case Intrinsic::x86_avx512_gather_dpd_mask_512:
12078 case Intrinsic::x86_avx512_gather_dps_mask_512:
12079 case Intrinsic::x86_avx512_gather_qpi_mask_512:
12080 case Intrinsic::x86_avx512_gather_qpq_mask_512:
12081 case Intrinsic::x86_avx512_gather_dpi_mask_512:
12082 case Intrinsic::x86_avx512_gather_dpq_mask_512: {
12085 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12086 case Intrinsic::x86_avx512_gather_qps_mask_512:
12087 Opc = X86::VGATHERQPSZrm; break;
12088 case Intrinsic::x86_avx512_gather_qpd_mask_512:
12089 Opc = X86::VGATHERQPDZrm; break;
12090 case Intrinsic::x86_avx512_gather_dpd_mask_512:
12091 Opc = X86::VGATHERDPDZrm; break;
12092 case Intrinsic::x86_avx512_gather_dps_mask_512:
12093 Opc = X86::VGATHERDPSZrm; break;
12094 case Intrinsic::x86_avx512_gather_qpi_mask_512:
12095 Opc = X86::VPGATHERQDZrm; break;
12096 case Intrinsic::x86_avx512_gather_qpq_mask_512:
12097 Opc = X86::VPGATHERQQZrm; break;
12098 case Intrinsic::x86_avx512_gather_dpi_mask_512:
12099 Opc = X86::VPGATHERDDZrm; break;
12100 case Intrinsic::x86_avx512_gather_dpq_mask_512:
12101 Opc = X86::VPGATHERDQZrm; break;
12103 SDValue Chain = Op.getOperand(0);
12104 SDValue Src = Op.getOperand(2);
12105 SDValue Mask = Op.getOperand(3);
12106 SDValue Index = Op.getOperand(4);
12107 SDValue Base = Op.getOperand(5);
12108 SDValue Scale = Op.getOperand(6);
12109 return getMGatherNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
12112 //int_scatter(base, index, v1, scale);
12113 case Intrinsic::x86_avx512_scatter_qpd_512:
12114 case Intrinsic::x86_avx512_scatter_qps_512:
12115 case Intrinsic::x86_avx512_scatter_dpd_512:
12116 case Intrinsic::x86_avx512_scatter_qpi_512:
12117 case Intrinsic::x86_avx512_scatter_qpq_512:
12118 case Intrinsic::x86_avx512_scatter_dpq_512:
12119 case Intrinsic::x86_avx512_scatter_dps_512:
12120 case Intrinsic::x86_avx512_scatter_dpi_512: {
12123 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12124 case Intrinsic::x86_avx512_scatter_qpd_512:
12125 Opc = X86::VSCATTERQPDZmr; break;
12126 case Intrinsic::x86_avx512_scatter_qps_512:
12127 Opc = X86::VSCATTERQPSZmr; break;
12128 case Intrinsic::x86_avx512_scatter_dpd_512:
12129 Opc = X86::VSCATTERDPDZmr; break;
12130 case Intrinsic::x86_avx512_scatter_dps_512:
12131 Opc = X86::VSCATTERDPSZmr; break;
12132 case Intrinsic::x86_avx512_scatter_qpi_512:
12133 Opc = X86::VPSCATTERQDZmr; break;
12134 case Intrinsic::x86_avx512_scatter_qpq_512:
12135 Opc = X86::VPSCATTERQQZmr; break;
12136 case Intrinsic::x86_avx512_scatter_dpq_512:
12137 Opc = X86::VPSCATTERDQZmr; break;
12138 case Intrinsic::x86_avx512_scatter_dpi_512:
12139 Opc = X86::VPSCATTERDDZmr; break;
12141 SDValue Chain = Op.getOperand(0);
12142 SDValue Base = Op.getOperand(2);
12143 SDValue Index = Op.getOperand(3);
12144 SDValue Src = Op.getOperand(4);
12145 SDValue Scale = Op.getOperand(5);
12146 return getScatterNode(Opc, Op, DAG, Src, Base, Index, Scale, Chain);
12148 //int_scatter_mask(base, mask, index, v1, scale);
12149 case Intrinsic::x86_avx512_scatter_qps_mask_512:
12150 case Intrinsic::x86_avx512_scatter_qpd_mask_512:
12151 case Intrinsic::x86_avx512_scatter_dpd_mask_512:
12152 case Intrinsic::x86_avx512_scatter_dps_mask_512:
12153 case Intrinsic::x86_avx512_scatter_qpi_mask_512:
12154 case Intrinsic::x86_avx512_scatter_qpq_mask_512:
12155 case Intrinsic::x86_avx512_scatter_dpi_mask_512:
12156 case Intrinsic::x86_avx512_scatter_dpq_mask_512: {
12159 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12160 case Intrinsic::x86_avx512_scatter_qpd_mask_512:
12161 Opc = X86::VSCATTERQPDZmr; break;
12162 case Intrinsic::x86_avx512_scatter_qps_mask_512:
12163 Opc = X86::VSCATTERQPSZmr; break;
12164 case Intrinsic::x86_avx512_scatter_dpd_mask_512:
12165 Opc = X86::VSCATTERDPDZmr; break;
12166 case Intrinsic::x86_avx512_scatter_dps_mask_512:
12167 Opc = X86::VSCATTERDPSZmr; break;
12168 case Intrinsic::x86_avx512_scatter_qpi_mask_512:
12169 Opc = X86::VPSCATTERQDZmr; break;
12170 case Intrinsic::x86_avx512_scatter_qpq_mask_512:
12171 Opc = X86::VPSCATTERQQZmr; break;
12172 case Intrinsic::x86_avx512_scatter_dpq_mask_512:
12173 Opc = X86::VPSCATTERDQZmr; break;
12174 case Intrinsic::x86_avx512_scatter_dpi_mask_512:
12175 Opc = X86::VPSCATTERDDZmr; break;
12177 SDValue Chain = Op.getOperand(0);
12178 SDValue Base = Op.getOperand(2);
12179 SDValue Mask = Op.getOperand(3);
12180 SDValue Index = Op.getOperand(4);
12181 SDValue Src = Op.getOperand(5);
12182 SDValue Scale = Op.getOperand(6);
12183 return getMScatterNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
12185 // XTEST intrinsics.
12186 case Intrinsic::x86_xtest: {
12187 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
12188 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
12189 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12190 DAG.getConstant(X86::COND_NE, MVT::i8),
12192 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
12193 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
12194 Ret, SDValue(InTrans.getNode(), 1));
12199 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
12200 SelectionDAG &DAG) const {
12201 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12202 MFI->setReturnAddressIsTaken(true);
12204 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
12207 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12209 EVT PtrVT = getPointerTy();
12212 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
12213 const X86RegisterInfo *RegInfo =
12214 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12215 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
12216 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
12217 DAG.getNode(ISD::ADD, dl, PtrVT,
12218 FrameAddr, Offset),
12219 MachinePointerInfo(), false, false, false, 0);
12222 // Just load the return address.
12223 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
12224 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
12225 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
12228 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
12229 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12230 MFI->setFrameAddressIsTaken(true);
12232 EVT VT = Op.getValueType();
12233 SDLoc dl(Op); // FIXME probably not meaningful
12234 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12235 const X86RegisterInfo *RegInfo =
12236 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12237 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
12238 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
12239 (FrameReg == X86::EBP && VT == MVT::i32)) &&
12240 "Invalid Frame Register!");
12241 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
12243 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
12244 MachinePointerInfo(),
12245 false, false, false, 0);
12249 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
12250 SelectionDAG &DAG) const {
12251 const X86RegisterInfo *RegInfo =
12252 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12253 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
12256 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
12257 SDValue Chain = Op.getOperand(0);
12258 SDValue Offset = Op.getOperand(1);
12259 SDValue Handler = Op.getOperand(2);
12262 EVT PtrVT = getPointerTy();
12263 const X86RegisterInfo *RegInfo =
12264 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
12265 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
12266 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
12267 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
12268 "Invalid Frame Register!");
12269 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
12270 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
12272 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
12273 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
12274 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
12275 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
12277 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
12279 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
12280 DAG.getRegister(StoreAddrReg, PtrVT));
12283 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
12284 SelectionDAG &DAG) const {
12286 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
12287 DAG.getVTList(MVT::i32, MVT::Other),
12288 Op.getOperand(0), Op.getOperand(1));
12291 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
12292 SelectionDAG &DAG) const {
12294 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
12295 Op.getOperand(0), Op.getOperand(1));
12298 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
12299 return Op.getOperand(0);
12302 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
12303 SelectionDAG &DAG) const {
12304 SDValue Root = Op.getOperand(0);
12305 SDValue Trmp = Op.getOperand(1); // trampoline
12306 SDValue FPtr = Op.getOperand(2); // nested function
12307 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
12310 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
12311 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12313 if (Subtarget->is64Bit()) {
12314 SDValue OutChains[6];
12316 // Large code-model.
12317 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
12318 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
12320 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
12321 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
12323 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
12325 // Load the pointer to the nested function into R11.
12326 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
12327 SDValue Addr = Trmp;
12328 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12329 Addr, MachinePointerInfo(TrmpAddr),
12332 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12333 DAG.getConstant(2, MVT::i64));
12334 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
12335 MachinePointerInfo(TrmpAddr, 2),
12338 // Load the 'nest' parameter value into R10.
12339 // R10 is specified in X86CallingConv.td
12340 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
12341 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12342 DAG.getConstant(10, MVT::i64));
12343 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12344 Addr, MachinePointerInfo(TrmpAddr, 10),
12347 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12348 DAG.getConstant(12, MVT::i64));
12349 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
12350 MachinePointerInfo(TrmpAddr, 12),
12353 // Jump to the nested function.
12354 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
12355 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12356 DAG.getConstant(20, MVT::i64));
12357 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12358 Addr, MachinePointerInfo(TrmpAddr, 20),
12361 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
12362 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12363 DAG.getConstant(22, MVT::i64));
12364 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
12365 MachinePointerInfo(TrmpAddr, 22),
12368 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
12370 const Function *Func =
12371 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
12372 CallingConv::ID CC = Func->getCallingConv();
12377 llvm_unreachable("Unsupported calling convention");
12378 case CallingConv::C:
12379 case CallingConv::X86_StdCall: {
12380 // Pass 'nest' parameter in ECX.
12381 // Must be kept in sync with X86CallingConv.td
12382 NestReg = X86::ECX;
12384 // Check that ECX wasn't needed by an 'inreg' parameter.
12385 FunctionType *FTy = Func->getFunctionType();
12386 const AttributeSet &Attrs = Func->getAttributes();
12388 if (!Attrs.isEmpty() && !Func->isVarArg()) {
12389 unsigned InRegCount = 0;
12392 for (FunctionType::param_iterator I = FTy->param_begin(),
12393 E = FTy->param_end(); I != E; ++I, ++Idx)
12394 if (Attrs.hasAttribute(Idx, Attribute::InReg))
12395 // FIXME: should only count parameters that are lowered to integers.
12396 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
12398 if (InRegCount > 2) {
12399 report_fatal_error("Nest register in use - reduce number of inreg"
12405 case CallingConv::X86_FastCall:
12406 case CallingConv::X86_ThisCall:
12407 case CallingConv::Fast:
12408 // Pass 'nest' parameter in EAX.
12409 // Must be kept in sync with X86CallingConv.td
12410 NestReg = X86::EAX;
12414 SDValue OutChains[4];
12415 SDValue Addr, Disp;
12417 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12418 DAG.getConstant(10, MVT::i32));
12419 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
12421 // This is storing the opcode for MOV32ri.
12422 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
12423 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
12424 OutChains[0] = DAG.getStore(Root, dl,
12425 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
12426 Trmp, MachinePointerInfo(TrmpAddr),
12429 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12430 DAG.getConstant(1, MVT::i32));
12431 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
12432 MachinePointerInfo(TrmpAddr, 1),
12435 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
12436 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12437 DAG.getConstant(5, MVT::i32));
12438 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
12439 MachinePointerInfo(TrmpAddr, 5),
12442 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12443 DAG.getConstant(6, MVT::i32));
12444 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
12445 MachinePointerInfo(TrmpAddr, 6),
12448 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
12452 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
12453 SelectionDAG &DAG) const {
12455 The rounding mode is in bits 11:10 of FPSR, and has the following
12457 00 Round to nearest
12462 FLT_ROUNDS, on the other hand, expects the following:
12469 To perform the conversion, we do:
12470 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
12473 MachineFunction &MF = DAG.getMachineFunction();
12474 const TargetMachine &TM = MF.getTarget();
12475 const TargetFrameLowering &TFI = *TM.getFrameLowering();
12476 unsigned StackAlignment = TFI.getStackAlignment();
12477 MVT VT = Op.getSimpleValueType();
12480 // Save FP Control Word to stack slot
12481 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
12482 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12484 MachineMemOperand *MMO =
12485 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12486 MachineMemOperand::MOStore, 2, 2);
12488 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
12489 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
12490 DAG.getVTList(MVT::Other),
12491 Ops, array_lengthof(Ops), MVT::i16,
12494 // Load FP Control Word from stack slot
12495 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
12496 MachinePointerInfo(), false, false, false, 0);
12498 // Transform as necessary
12500 DAG.getNode(ISD::SRL, DL, MVT::i16,
12501 DAG.getNode(ISD::AND, DL, MVT::i16,
12502 CWD, DAG.getConstant(0x800, MVT::i16)),
12503 DAG.getConstant(11, MVT::i8));
12505 DAG.getNode(ISD::SRL, DL, MVT::i16,
12506 DAG.getNode(ISD::AND, DL, MVT::i16,
12507 CWD, DAG.getConstant(0x400, MVT::i16)),
12508 DAG.getConstant(9, MVT::i8));
12511 DAG.getNode(ISD::AND, DL, MVT::i16,
12512 DAG.getNode(ISD::ADD, DL, MVT::i16,
12513 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
12514 DAG.getConstant(1, MVT::i16)),
12515 DAG.getConstant(3, MVT::i16));
12517 return DAG.getNode((VT.getSizeInBits() < 16 ?
12518 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
12521 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
12522 MVT VT = Op.getSimpleValueType();
12524 unsigned NumBits = VT.getSizeInBits();
12527 Op = Op.getOperand(0);
12528 if (VT == MVT::i8) {
12529 // Zero extend to i32 since there is not an i8 bsr.
12531 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
12534 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
12535 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
12536 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
12538 // If src is zero (i.e. bsr sets ZF), returns NumBits.
12541 DAG.getConstant(NumBits+NumBits-1, OpVT),
12542 DAG.getConstant(X86::COND_E, MVT::i8),
12545 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
12547 // Finally xor with NumBits-1.
12548 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
12551 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
12555 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
12556 MVT VT = Op.getSimpleValueType();
12558 unsigned NumBits = VT.getSizeInBits();
12561 Op = Op.getOperand(0);
12562 if (VT == MVT::i8) {
12563 // Zero extend to i32 since there is not an i8 bsr.
12565 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
12568 // Issue a bsr (scan bits in reverse).
12569 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
12570 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
12572 // And xor with NumBits-1.
12573 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
12576 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
12580 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
12581 MVT VT = Op.getSimpleValueType();
12582 unsigned NumBits = VT.getSizeInBits();
12584 Op = Op.getOperand(0);
12586 // Issue a bsf (scan bits forward) which also sets EFLAGS.
12587 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
12588 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
12590 // If src is zero (i.e. bsf sets ZF), returns NumBits.
12593 DAG.getConstant(NumBits, VT),
12594 DAG.getConstant(X86::COND_E, MVT::i8),
12597 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
12600 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
12601 // ones, and then concatenate the result back.
12602 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
12603 MVT VT = Op.getSimpleValueType();
12605 assert(VT.is256BitVector() && VT.isInteger() &&
12606 "Unsupported value type for operation");
12608 unsigned NumElems = VT.getVectorNumElements();
12611 // Extract the LHS vectors
12612 SDValue LHS = Op.getOperand(0);
12613 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12614 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12616 // Extract the RHS vectors
12617 SDValue RHS = Op.getOperand(1);
12618 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
12619 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
12621 MVT EltVT = VT.getVectorElementType();
12622 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12624 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
12625 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
12626 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
12629 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
12630 assert(Op.getSimpleValueType().is256BitVector() &&
12631 Op.getSimpleValueType().isInteger() &&
12632 "Only handle AVX 256-bit vector integer operation");
12633 return Lower256IntArith(Op, DAG);
12636 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
12637 assert(Op.getSimpleValueType().is256BitVector() &&
12638 Op.getSimpleValueType().isInteger() &&
12639 "Only handle AVX 256-bit vector integer operation");
12640 return Lower256IntArith(Op, DAG);
12643 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
12644 SelectionDAG &DAG) {
12646 MVT VT = Op.getSimpleValueType();
12648 // Decompose 256-bit ops into smaller 128-bit ops.
12649 if (VT.is256BitVector() && !Subtarget->hasInt256())
12650 return Lower256IntArith(Op, DAG);
12652 SDValue A = Op.getOperand(0);
12653 SDValue B = Op.getOperand(1);
12655 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
12656 if (VT == MVT::v4i32) {
12657 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
12658 "Should not custom lower when pmuldq is available!");
12660 // Extract the odd parts.
12661 static const int UnpackMask[] = { 1, -1, 3, -1 };
12662 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
12663 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
12665 // Multiply the even parts.
12666 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
12667 // Now multiply odd parts.
12668 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
12670 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
12671 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
12673 // Merge the two vectors back together with a shuffle. This expands into 2
12675 static const int ShufMask[] = { 0, 4, 2, 6 };
12676 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
12679 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
12680 "Only know how to lower V2I64/V4I64/V8I64 multiply");
12682 // Ahi = psrlqi(a, 32);
12683 // Bhi = psrlqi(b, 32);
12685 // AloBlo = pmuludq(a, b);
12686 // AloBhi = pmuludq(a, Bhi);
12687 // AhiBlo = pmuludq(Ahi, b);
12689 // AloBhi = psllqi(AloBhi, 32);
12690 // AhiBlo = psllqi(AhiBlo, 32);
12691 // return AloBlo + AloBhi + AhiBlo;
12693 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
12694 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
12696 // Bit cast to 32-bit vectors for MULUDQ
12697 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
12698 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
12699 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
12700 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
12701 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
12702 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
12704 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
12705 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
12706 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
12708 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
12709 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
12711 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
12712 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
12715 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
12716 MVT VT = Op.getSimpleValueType();
12717 MVT EltTy = VT.getVectorElementType();
12718 unsigned NumElts = VT.getVectorNumElements();
12719 SDValue N0 = Op.getOperand(0);
12722 // Lower sdiv X, pow2-const.
12723 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(Op.getOperand(1));
12727 APInt SplatValue, SplatUndef;
12728 unsigned SplatBitSize;
12730 if (!C->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
12732 EltTy.getSizeInBits() < SplatBitSize)
12735 if ((SplatValue != 0) &&
12736 (SplatValue.isPowerOf2() || (-SplatValue).isPowerOf2())) {
12737 unsigned Lg2 = SplatValue.countTrailingZeros();
12738 // Splat the sign bit.
12739 SmallVector<SDValue, 16> Sz(NumElts,
12740 DAG.getConstant(EltTy.getSizeInBits() - 1,
12742 SDValue SGN = DAG.getNode(ISD::SRA, dl, VT, N0,
12743 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Sz[0],
12745 // Add (N0 < 0) ? abs2 - 1 : 0;
12746 SmallVector<SDValue, 16> Amt(NumElts,
12747 DAG.getConstant(EltTy.getSizeInBits() - Lg2,
12749 SDValue SRL = DAG.getNode(ISD::SRL, dl, VT, SGN,
12750 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Amt[0],
12752 SDValue ADD = DAG.getNode(ISD::ADD, dl, VT, N0, SRL);
12753 SmallVector<SDValue, 16> Lg2Amt(NumElts, DAG.getConstant(Lg2, EltTy));
12754 SDValue SRA = DAG.getNode(ISD::SRA, dl, VT, ADD,
12755 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Lg2Amt[0],
12758 // If we're dividing by a positive value, we're done. Otherwise, we must
12759 // negate the result.
12760 if (SplatValue.isNonNegative())
12763 SmallVector<SDValue, 16> V(NumElts, DAG.getConstant(0, EltTy));
12764 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], NumElts);
12765 return DAG.getNode(ISD::SUB, dl, VT, Zero, SRA);
12770 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
12771 const X86Subtarget *Subtarget) {
12772 MVT VT = Op.getSimpleValueType();
12774 SDValue R = Op.getOperand(0);
12775 SDValue Amt = Op.getOperand(1);
12777 // Optimize shl/srl/sra with constant shift amount.
12778 if (isSplatVector(Amt.getNode())) {
12779 SDValue SclrAmt = Amt->getOperand(0);
12780 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
12781 uint64_t ShiftAmt = C->getZExtValue();
12783 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
12784 (Subtarget->hasInt256() &&
12785 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
12786 (Subtarget->hasAVX512() &&
12787 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
12788 if (Op.getOpcode() == ISD::SHL)
12789 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
12791 if (Op.getOpcode() == ISD::SRL)
12792 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
12794 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
12795 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
12799 if (VT == MVT::v16i8) {
12800 if (Op.getOpcode() == ISD::SHL) {
12801 // Make a large shift.
12802 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
12803 MVT::v8i16, R, ShiftAmt,
12805 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12806 // Zero out the rightmost bits.
12807 SmallVector<SDValue, 16> V(16,
12808 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12810 return DAG.getNode(ISD::AND, dl, VT, SHL,
12811 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12813 if (Op.getOpcode() == ISD::SRL) {
12814 // Make a large shift.
12815 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
12816 MVT::v8i16, R, ShiftAmt,
12818 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12819 // Zero out the leftmost bits.
12820 SmallVector<SDValue, 16> V(16,
12821 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12823 return DAG.getNode(ISD::AND, dl, VT, SRL,
12824 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12826 if (Op.getOpcode() == ISD::SRA) {
12827 if (ShiftAmt == 7) {
12828 // R s>> 7 === R s< 0
12829 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12830 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12833 // R s>> a === ((R u>> a) ^ m) - m
12834 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12835 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
12837 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
12838 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12839 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12842 llvm_unreachable("Unknown shift opcode.");
12845 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
12846 if (Op.getOpcode() == ISD::SHL) {
12847 // Make a large shift.
12848 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
12849 MVT::v16i16, R, ShiftAmt,
12851 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12852 // Zero out the rightmost bits.
12853 SmallVector<SDValue, 32> V(32,
12854 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12856 return DAG.getNode(ISD::AND, dl, VT, SHL,
12857 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12859 if (Op.getOpcode() == ISD::SRL) {
12860 // Make a large shift.
12861 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
12862 MVT::v16i16, R, ShiftAmt,
12864 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12865 // Zero out the leftmost bits.
12866 SmallVector<SDValue, 32> V(32,
12867 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12869 return DAG.getNode(ISD::AND, dl, VT, SRL,
12870 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12872 if (Op.getOpcode() == ISD::SRA) {
12873 if (ShiftAmt == 7) {
12874 // R s>> 7 === R s< 0
12875 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12876 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12879 // R s>> a === ((R u>> a) ^ m) - m
12880 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12881 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
12883 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
12884 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12885 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12888 llvm_unreachable("Unknown shift opcode.");
12893 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
12894 if (!Subtarget->is64Bit() &&
12895 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
12896 Amt.getOpcode() == ISD::BITCAST &&
12897 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
12898 Amt = Amt.getOperand(0);
12899 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
12900 VT.getVectorNumElements();
12901 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
12902 uint64_t ShiftAmt = 0;
12903 for (unsigned i = 0; i != Ratio; ++i) {
12904 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
12908 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
12910 // Check remaining shift amounts.
12911 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
12912 uint64_t ShAmt = 0;
12913 for (unsigned j = 0; j != Ratio; ++j) {
12914 ConstantSDNode *C =
12915 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
12919 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
12921 if (ShAmt != ShiftAmt)
12924 switch (Op.getOpcode()) {
12926 llvm_unreachable("Unknown shift opcode!");
12928 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
12931 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
12934 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
12942 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
12943 const X86Subtarget* Subtarget) {
12944 MVT VT = Op.getSimpleValueType();
12946 SDValue R = Op.getOperand(0);
12947 SDValue Amt = Op.getOperand(1);
12949 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
12950 VT == MVT::v4i32 || VT == MVT::v8i16 ||
12951 (Subtarget->hasInt256() &&
12952 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
12953 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
12954 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
12956 EVT EltVT = VT.getVectorElementType();
12958 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
12959 unsigned NumElts = VT.getVectorNumElements();
12961 for (i = 0; i != NumElts; ++i) {
12962 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
12966 for (j = i; j != NumElts; ++j) {
12967 SDValue Arg = Amt.getOperand(j);
12968 if (Arg.getOpcode() == ISD::UNDEF) continue;
12969 if (Arg != Amt.getOperand(i))
12972 if (i != NumElts && j == NumElts)
12973 BaseShAmt = Amt.getOperand(i);
12975 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
12976 Amt = Amt.getOperand(0);
12977 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
12978 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
12979 SDValue InVec = Amt.getOperand(0);
12980 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
12981 unsigned NumElts = InVec.getValueType().getVectorNumElements();
12983 for (; i != NumElts; ++i) {
12984 SDValue Arg = InVec.getOperand(i);
12985 if (Arg.getOpcode() == ISD::UNDEF) continue;
12989 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
12990 if (ConstantSDNode *C =
12991 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
12992 unsigned SplatIdx =
12993 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
12994 if (C->getZExtValue() == SplatIdx)
12995 BaseShAmt = InVec.getOperand(1);
12998 if (BaseShAmt.getNode() == 0)
12999 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
13000 DAG.getIntPtrConstant(0));
13004 if (BaseShAmt.getNode()) {
13005 if (EltVT.bitsGT(MVT::i32))
13006 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
13007 else if (EltVT.bitsLT(MVT::i32))
13008 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
13010 switch (Op.getOpcode()) {
13012 llvm_unreachable("Unknown shift opcode!");
13014 switch (VT.SimpleTy) {
13015 default: return SDValue();
13024 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
13027 switch (VT.SimpleTy) {
13028 default: return SDValue();
13035 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
13038 switch (VT.SimpleTy) {
13039 default: return SDValue();
13048 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
13054 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
13055 if (!Subtarget->is64Bit() &&
13056 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
13057 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
13058 Amt.getOpcode() == ISD::BITCAST &&
13059 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
13060 Amt = Amt.getOperand(0);
13061 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
13062 VT.getVectorNumElements();
13063 std::vector<SDValue> Vals(Ratio);
13064 for (unsigned i = 0; i != Ratio; ++i)
13065 Vals[i] = Amt.getOperand(i);
13066 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
13067 for (unsigned j = 0; j != Ratio; ++j)
13068 if (Vals[j] != Amt.getOperand(i + j))
13071 switch (Op.getOpcode()) {
13073 llvm_unreachable("Unknown shift opcode!");
13075 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
13077 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
13079 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
13086 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
13087 SelectionDAG &DAG) {
13089 MVT VT = Op.getSimpleValueType();
13091 SDValue R = Op.getOperand(0);
13092 SDValue Amt = Op.getOperand(1);
13095 if (!Subtarget->hasSSE2())
13098 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
13102 V = LowerScalarVariableShift(Op, DAG, Subtarget);
13106 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
13108 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
13109 if (Subtarget->hasInt256()) {
13110 if (Op.getOpcode() == ISD::SRL &&
13111 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
13112 VT == MVT::v4i64 || VT == MVT::v8i32))
13114 if (Op.getOpcode() == ISD::SHL &&
13115 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
13116 VT == MVT::v4i64 || VT == MVT::v8i32))
13118 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
13122 // Lower SHL with variable shift amount.
13123 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
13124 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
13126 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
13127 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
13128 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
13129 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
13131 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
13132 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
13135 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
13136 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
13138 // Turn 'a' into a mask suitable for VSELECT
13139 SDValue VSelM = DAG.getConstant(0x80, VT);
13140 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
13141 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
13143 SDValue CM1 = DAG.getConstant(0x0f, VT);
13144 SDValue CM2 = DAG.getConstant(0x3f, VT);
13146 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
13147 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
13148 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
13149 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
13150 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
13153 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
13154 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
13155 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
13157 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
13158 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
13159 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
13160 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
13161 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
13164 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
13165 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
13166 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
13168 // return VSELECT(r, r+r, a);
13169 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
13170 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
13174 // Decompose 256-bit shifts into smaller 128-bit shifts.
13175 if (VT.is256BitVector()) {
13176 unsigned NumElems = VT.getVectorNumElements();
13177 MVT EltVT = VT.getVectorElementType();
13178 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13180 // Extract the two vectors
13181 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
13182 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
13184 // Recreate the shift amount vectors
13185 SDValue Amt1, Amt2;
13186 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
13187 // Constant shift amount
13188 SmallVector<SDValue, 4> Amt1Csts;
13189 SmallVector<SDValue, 4> Amt2Csts;
13190 for (unsigned i = 0; i != NumElems/2; ++i)
13191 Amt1Csts.push_back(Amt->getOperand(i));
13192 for (unsigned i = NumElems/2; i != NumElems; ++i)
13193 Amt2Csts.push_back(Amt->getOperand(i));
13195 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
13196 &Amt1Csts[0], NumElems/2);
13197 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
13198 &Amt2Csts[0], NumElems/2);
13200 // Variable shift amount
13201 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
13202 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
13205 // Issue new vector shifts for the smaller types
13206 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
13207 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
13209 // Concatenate the result back
13210 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
13216 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
13217 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
13218 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
13219 // looks for this combo and may remove the "setcc" instruction if the "setcc"
13220 // has only one use.
13221 SDNode *N = Op.getNode();
13222 SDValue LHS = N->getOperand(0);
13223 SDValue RHS = N->getOperand(1);
13224 unsigned BaseOp = 0;
13227 switch (Op.getOpcode()) {
13228 default: llvm_unreachable("Unknown ovf instruction!");
13230 // A subtract of one will be selected as a INC. Note that INC doesn't
13231 // set CF, so we can't do this for UADDO.
13232 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13234 BaseOp = X86ISD::INC;
13235 Cond = X86::COND_O;
13238 BaseOp = X86ISD::ADD;
13239 Cond = X86::COND_O;
13242 BaseOp = X86ISD::ADD;
13243 Cond = X86::COND_B;
13246 // A subtract of one will be selected as a DEC. Note that DEC doesn't
13247 // set CF, so we can't do this for USUBO.
13248 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13250 BaseOp = X86ISD::DEC;
13251 Cond = X86::COND_O;
13254 BaseOp = X86ISD::SUB;
13255 Cond = X86::COND_O;
13258 BaseOp = X86ISD::SUB;
13259 Cond = X86::COND_B;
13262 BaseOp = X86ISD::SMUL;
13263 Cond = X86::COND_O;
13265 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
13266 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
13268 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
13271 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13272 DAG.getConstant(X86::COND_O, MVT::i32),
13273 SDValue(Sum.getNode(), 2));
13275 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
13279 // Also sets EFLAGS.
13280 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
13281 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
13284 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
13285 DAG.getConstant(Cond, MVT::i32),
13286 SDValue(Sum.getNode(), 1));
13288 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
13291 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
13292 SelectionDAG &DAG) const {
13294 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
13295 MVT VT = Op.getSimpleValueType();
13297 if (!Subtarget->hasSSE2() || !VT.isVector())
13300 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
13301 ExtraVT.getScalarType().getSizeInBits();
13303 switch (VT.SimpleTy) {
13304 default: return SDValue();
13307 if (!Subtarget->hasFp256())
13309 if (!Subtarget->hasInt256()) {
13310 // needs to be split
13311 unsigned NumElems = VT.getVectorNumElements();
13313 // Extract the LHS vectors
13314 SDValue LHS = Op.getOperand(0);
13315 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13316 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13318 MVT EltVT = VT.getVectorElementType();
13319 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13321 EVT ExtraEltVT = ExtraVT.getVectorElementType();
13322 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
13323 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
13325 SDValue Extra = DAG.getValueType(ExtraVT);
13327 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
13328 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
13330 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
13335 SDValue Op0 = Op.getOperand(0);
13336 SDValue Op00 = Op0.getOperand(0);
13338 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
13339 if (Op0.getOpcode() == ISD::BITCAST &&
13340 Op00.getOpcode() == ISD::VECTOR_SHUFFLE) {
13341 // (sext (vzext x)) -> (vsext x)
13342 Tmp1 = LowerVectorIntExtend(Op00, Subtarget, DAG);
13343 if (Tmp1.getNode()) {
13344 EVT ExtraEltVT = ExtraVT.getVectorElementType();
13345 // This folding is only valid when the in-reg type is a vector of i8,
13347 if (ExtraEltVT == MVT::i8 || ExtraEltVT == MVT::i16 ||
13348 ExtraEltVT == MVT::i32) {
13349 SDValue Tmp1Op0 = Tmp1.getOperand(0);
13350 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
13351 "This optimization is invalid without a VZEXT.");
13352 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
13358 // If the above didn't work, then just use Shift-Left + Shift-Right.
13359 Tmp1 = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0, BitsDiff,
13361 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Tmp1, BitsDiff,
13367 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
13368 SelectionDAG &DAG) {
13370 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
13371 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
13372 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
13373 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
13375 // The only fence that needs an instruction is a sequentially-consistent
13376 // cross-thread fence.
13377 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
13378 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
13379 // no-sse2). There isn't any reason to disable it if the target processor
13381 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
13382 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
13384 SDValue Chain = Op.getOperand(0);
13385 SDValue Zero = DAG.getConstant(0, MVT::i32);
13387 DAG.getRegister(X86::ESP, MVT::i32), // Base
13388 DAG.getTargetConstant(1, MVT::i8), // Scale
13389 DAG.getRegister(0, MVT::i32), // Index
13390 DAG.getTargetConstant(0, MVT::i32), // Disp
13391 DAG.getRegister(0, MVT::i32), // Segment.
13395 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
13396 return SDValue(Res, 0);
13399 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
13400 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
13403 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
13404 SelectionDAG &DAG) {
13405 MVT T = Op.getSimpleValueType();
13409 switch(T.SimpleTy) {
13410 default: llvm_unreachable("Invalid value type!");
13411 case MVT::i8: Reg = X86::AL; size = 1; break;
13412 case MVT::i16: Reg = X86::AX; size = 2; break;
13413 case MVT::i32: Reg = X86::EAX; size = 4; break;
13415 assert(Subtarget->is64Bit() && "Node not type legal!");
13416 Reg = X86::RAX; size = 8;
13419 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
13420 Op.getOperand(2), SDValue());
13421 SDValue Ops[] = { cpIn.getValue(0),
13424 DAG.getTargetConstant(size, MVT::i8),
13425 cpIn.getValue(1) };
13426 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13427 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
13428 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
13429 Ops, array_lengthof(Ops), T, MMO);
13431 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
13435 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
13436 SelectionDAG &DAG) {
13437 assert(Subtarget->is64Bit() && "Result not type legalized?");
13438 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13439 SDValue TheChain = Op.getOperand(0);
13441 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13442 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
13443 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
13445 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
13446 DAG.getConstant(32, MVT::i8));
13448 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
13451 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
13454 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
13455 SelectionDAG &DAG) {
13456 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13457 MVT DstVT = Op.getSimpleValueType();
13458 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
13459 Subtarget->hasMMX() && "Unexpected custom BITCAST");
13460 assert((DstVT == MVT::i64 ||
13461 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
13462 "Unexpected custom BITCAST");
13463 // i64 <=> MMX conversions are Legal.
13464 if (SrcVT==MVT::i64 && DstVT.isVector())
13466 if (DstVT==MVT::i64 && SrcVT.isVector())
13468 // MMX <=> MMX conversions are Legal.
13469 if (SrcVT.isVector() && DstVT.isVector())
13471 // All other conversions need to be expanded.
13475 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
13476 SDNode *Node = Op.getNode();
13478 EVT T = Node->getValueType(0);
13479 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
13480 DAG.getConstant(0, T), Node->getOperand(2));
13481 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
13482 cast<AtomicSDNode>(Node)->getMemoryVT(),
13483 Node->getOperand(0),
13484 Node->getOperand(1), negOp,
13485 cast<AtomicSDNode>(Node)->getSrcValue(),
13486 cast<AtomicSDNode>(Node)->getAlignment(),
13487 cast<AtomicSDNode>(Node)->getOrdering(),
13488 cast<AtomicSDNode>(Node)->getSynchScope());
13491 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
13492 SDNode *Node = Op.getNode();
13494 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13496 // Convert seq_cst store -> xchg
13497 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
13498 // FIXME: On 32-bit, store -> fist or movq would be more efficient
13499 // (The only way to get a 16-byte store is cmpxchg16b)
13500 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
13501 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
13502 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
13503 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
13504 cast<AtomicSDNode>(Node)->getMemoryVT(),
13505 Node->getOperand(0),
13506 Node->getOperand(1), Node->getOperand(2),
13507 cast<AtomicSDNode>(Node)->getMemOperand(),
13508 cast<AtomicSDNode>(Node)->getOrdering(),
13509 cast<AtomicSDNode>(Node)->getSynchScope());
13510 return Swap.getValue(1);
13512 // Other atomic stores have a simple pattern.
13516 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
13517 EVT VT = Op.getNode()->getSimpleValueType(0);
13519 // Let legalize expand this if it isn't a legal type yet.
13520 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
13523 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
13526 bool ExtraOp = false;
13527 switch (Op.getOpcode()) {
13528 default: llvm_unreachable("Invalid code");
13529 case ISD::ADDC: Opc = X86ISD::ADD; break;
13530 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
13531 case ISD::SUBC: Opc = X86ISD::SUB; break;
13532 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
13536 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
13538 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
13539 Op.getOperand(1), Op.getOperand(2));
13542 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
13543 SelectionDAG &DAG) {
13544 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
13546 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
13547 // which returns the values as { float, float } (in XMM0) or
13548 // { double, double } (which is returned in XMM0, XMM1).
13550 SDValue Arg = Op.getOperand(0);
13551 EVT ArgVT = Arg.getValueType();
13552 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
13554 TargetLowering::ArgListTy Args;
13555 TargetLowering::ArgListEntry Entry;
13559 Entry.isSExt = false;
13560 Entry.isZExt = false;
13561 Args.push_back(Entry);
13563 bool isF64 = ArgVT == MVT::f64;
13564 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
13565 // the small struct {f32, f32} is returned in (eax, edx). For f64,
13566 // the results are returned via SRet in memory.
13567 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
13568 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13569 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
13571 Type *RetTy = isF64
13572 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
13573 : (Type*)VectorType::get(ArgTy, 4);
13575 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy,
13576 false, false, false, false, 0,
13577 CallingConv::C, /*isTaillCall=*/false,
13578 /*doesNotRet=*/false, /*isReturnValueUsed*/true,
13579 Callee, Args, DAG, dl);
13580 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
13583 // Returned in xmm0 and xmm1.
13584 return CallResult.first;
13586 // Returned in bits 0:31 and 32:64 xmm0.
13587 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
13588 CallResult.first, DAG.getIntPtrConstant(0));
13589 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
13590 CallResult.first, DAG.getIntPtrConstant(1));
13591 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
13592 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
13595 /// LowerOperation - Provide custom lowering hooks for some operations.
13597 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
13598 switch (Op.getOpcode()) {
13599 default: llvm_unreachable("Should not custom lower this!");
13600 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
13601 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
13602 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG);
13603 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
13604 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
13605 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
13606 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
13607 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
13608 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
13609 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
13610 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
13611 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
13612 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
13613 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
13614 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
13615 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
13616 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
13617 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
13618 case ISD::SHL_PARTS:
13619 case ISD::SRA_PARTS:
13620 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
13621 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
13622 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
13623 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
13624 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
13625 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
13626 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
13627 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
13628 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
13629 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
13630 case ISD::FABS: return LowerFABS(Op, DAG);
13631 case ISD::FNEG: return LowerFNEG(Op, DAG);
13632 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
13633 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
13634 case ISD::SETCC: return LowerSETCC(Op, DAG);
13635 case ISD::SELECT: return LowerSELECT(Op, DAG);
13636 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
13637 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
13638 case ISD::VASTART: return LowerVASTART(Op, DAG);
13639 case ISD::VAARG: return LowerVAARG(Op, DAG);
13640 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
13641 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
13642 case ISD::INTRINSIC_VOID:
13643 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
13644 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
13645 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
13646 case ISD::FRAME_TO_ARGS_OFFSET:
13647 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
13648 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
13649 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
13650 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
13651 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
13652 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
13653 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
13654 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
13655 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
13656 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
13657 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
13658 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
13661 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
13667 case ISD::UMULO: return LowerXALUO(Op, DAG);
13668 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
13669 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
13673 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
13674 case ISD::ADD: return LowerADD(Op, DAG);
13675 case ISD::SUB: return LowerSUB(Op, DAG);
13676 case ISD::SDIV: return LowerSDIV(Op, DAG);
13677 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
13681 static void ReplaceATOMIC_LOAD(SDNode *Node,
13682 SmallVectorImpl<SDValue> &Results,
13683 SelectionDAG &DAG) {
13685 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13687 // Convert wide load -> cmpxchg8b/cmpxchg16b
13688 // FIXME: On 32-bit, load -> fild or movq would be more efficient
13689 // (The only way to get a 16-byte load is cmpxchg16b)
13690 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
13691 SDValue Zero = DAG.getConstant(0, VT);
13692 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
13693 Node->getOperand(0),
13694 Node->getOperand(1), Zero, Zero,
13695 cast<AtomicSDNode>(Node)->getMemOperand(),
13696 cast<AtomicSDNode>(Node)->getOrdering(),
13697 cast<AtomicSDNode>(Node)->getSynchScope());
13698 Results.push_back(Swap.getValue(0));
13699 Results.push_back(Swap.getValue(1));
13703 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
13704 SelectionDAG &DAG, unsigned NewOp) {
13706 assert (Node->getValueType(0) == MVT::i64 &&
13707 "Only know how to expand i64 atomics");
13709 SDValue Chain = Node->getOperand(0);
13710 SDValue In1 = Node->getOperand(1);
13711 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13712 Node->getOperand(2), DAG.getIntPtrConstant(0));
13713 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13714 Node->getOperand(2), DAG.getIntPtrConstant(1));
13715 SDValue Ops[] = { Chain, In1, In2L, In2H };
13716 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
13718 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, array_lengthof(Ops), MVT::i64,
13719 cast<MemSDNode>(Node)->getMemOperand());
13720 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
13721 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
13722 Results.push_back(Result.getValue(2));
13725 /// ReplaceNodeResults - Replace a node with an illegal result type
13726 /// with a new node built out of custom code.
13727 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
13728 SmallVectorImpl<SDValue>&Results,
13729 SelectionDAG &DAG) const {
13731 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13732 switch (N->getOpcode()) {
13734 llvm_unreachable("Do not know how to custom type legalize this operation!");
13735 case ISD::SIGN_EXTEND_INREG:
13740 // We don't want to expand or promote these.
13742 case ISD::FP_TO_SINT:
13743 case ISD::FP_TO_UINT: {
13744 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
13746 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
13749 std::pair<SDValue,SDValue> Vals =
13750 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
13751 SDValue FIST = Vals.first, StackSlot = Vals.second;
13752 if (FIST.getNode() != 0) {
13753 EVT VT = N->getValueType(0);
13754 // Return a load from the stack slot.
13755 if (StackSlot.getNode() != 0)
13756 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
13757 MachinePointerInfo(),
13758 false, false, false, 0));
13760 Results.push_back(FIST);
13764 case ISD::UINT_TO_FP: {
13765 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
13766 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
13767 N->getValueType(0) != MVT::v2f32)
13769 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
13771 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13773 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
13774 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
13775 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
13776 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
13777 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
13778 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
13781 case ISD::FP_ROUND: {
13782 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
13784 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
13785 Results.push_back(V);
13788 case ISD::READCYCLECOUNTER: {
13789 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13790 SDValue TheChain = N->getOperand(0);
13791 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13792 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
13794 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
13796 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
13797 SDValue Ops[] = { eax, edx };
13798 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops,
13799 array_lengthof(Ops)));
13800 Results.push_back(edx.getValue(1));
13803 case ISD::ATOMIC_CMP_SWAP: {
13804 EVT T = N->getValueType(0);
13805 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
13806 bool Regs64bit = T == MVT::i128;
13807 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
13808 SDValue cpInL, cpInH;
13809 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13810 DAG.getConstant(0, HalfT));
13811 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13812 DAG.getConstant(1, HalfT));
13813 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
13814 Regs64bit ? X86::RAX : X86::EAX,
13816 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
13817 Regs64bit ? X86::RDX : X86::EDX,
13818 cpInH, cpInL.getValue(1));
13819 SDValue swapInL, swapInH;
13820 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13821 DAG.getConstant(0, HalfT));
13822 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13823 DAG.getConstant(1, HalfT));
13824 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
13825 Regs64bit ? X86::RBX : X86::EBX,
13826 swapInL, cpInH.getValue(1));
13827 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
13828 Regs64bit ? X86::RCX : X86::ECX,
13829 swapInH, swapInL.getValue(1));
13830 SDValue Ops[] = { swapInH.getValue(0),
13832 swapInH.getValue(1) };
13833 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13834 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
13835 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
13836 X86ISD::LCMPXCHG8_DAG;
13837 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
13838 Ops, array_lengthof(Ops), T, MMO);
13839 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
13840 Regs64bit ? X86::RAX : X86::EAX,
13841 HalfT, Result.getValue(1));
13842 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
13843 Regs64bit ? X86::RDX : X86::EDX,
13844 HalfT, cpOutL.getValue(2));
13845 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
13846 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
13847 Results.push_back(cpOutH.getValue(1));
13850 case ISD::ATOMIC_LOAD_ADD:
13851 case ISD::ATOMIC_LOAD_AND:
13852 case ISD::ATOMIC_LOAD_NAND:
13853 case ISD::ATOMIC_LOAD_OR:
13854 case ISD::ATOMIC_LOAD_SUB:
13855 case ISD::ATOMIC_LOAD_XOR:
13856 case ISD::ATOMIC_LOAD_MAX:
13857 case ISD::ATOMIC_LOAD_MIN:
13858 case ISD::ATOMIC_LOAD_UMAX:
13859 case ISD::ATOMIC_LOAD_UMIN:
13860 case ISD::ATOMIC_SWAP: {
13862 switch (N->getOpcode()) {
13863 default: llvm_unreachable("Unexpected opcode");
13864 case ISD::ATOMIC_LOAD_ADD:
13865 Opc = X86ISD::ATOMADD64_DAG;
13867 case ISD::ATOMIC_LOAD_AND:
13868 Opc = X86ISD::ATOMAND64_DAG;
13870 case ISD::ATOMIC_LOAD_NAND:
13871 Opc = X86ISD::ATOMNAND64_DAG;
13873 case ISD::ATOMIC_LOAD_OR:
13874 Opc = X86ISD::ATOMOR64_DAG;
13876 case ISD::ATOMIC_LOAD_SUB:
13877 Opc = X86ISD::ATOMSUB64_DAG;
13879 case ISD::ATOMIC_LOAD_XOR:
13880 Opc = X86ISD::ATOMXOR64_DAG;
13882 case ISD::ATOMIC_LOAD_MAX:
13883 Opc = X86ISD::ATOMMAX64_DAG;
13885 case ISD::ATOMIC_LOAD_MIN:
13886 Opc = X86ISD::ATOMMIN64_DAG;
13888 case ISD::ATOMIC_LOAD_UMAX:
13889 Opc = X86ISD::ATOMUMAX64_DAG;
13891 case ISD::ATOMIC_LOAD_UMIN:
13892 Opc = X86ISD::ATOMUMIN64_DAG;
13894 case ISD::ATOMIC_SWAP:
13895 Opc = X86ISD::ATOMSWAP64_DAG;
13898 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc);
13901 case ISD::ATOMIC_LOAD:
13902 ReplaceATOMIC_LOAD(N, Results, DAG);
13906 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
13908 default: return NULL;
13909 case X86ISD::BSF: return "X86ISD::BSF";
13910 case X86ISD::BSR: return "X86ISD::BSR";
13911 case X86ISD::SHLD: return "X86ISD::SHLD";
13912 case X86ISD::SHRD: return "X86ISD::SHRD";
13913 case X86ISD::FAND: return "X86ISD::FAND";
13914 case X86ISD::FANDN: return "X86ISD::FANDN";
13915 case X86ISD::FOR: return "X86ISD::FOR";
13916 case X86ISD::FXOR: return "X86ISD::FXOR";
13917 case X86ISD::FSRL: return "X86ISD::FSRL";
13918 case X86ISD::FILD: return "X86ISD::FILD";
13919 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
13920 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
13921 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
13922 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
13923 case X86ISD::FLD: return "X86ISD::FLD";
13924 case X86ISD::FST: return "X86ISD::FST";
13925 case X86ISD::CALL: return "X86ISD::CALL";
13926 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
13927 case X86ISD::BT: return "X86ISD::BT";
13928 case X86ISD::CMP: return "X86ISD::CMP";
13929 case X86ISD::COMI: return "X86ISD::COMI";
13930 case X86ISD::UCOMI: return "X86ISD::UCOMI";
13931 case X86ISD::CMPM: return "X86ISD::CMPM";
13932 case X86ISD::CMPMU: return "X86ISD::CMPMU";
13933 case X86ISD::SETCC: return "X86ISD::SETCC";
13934 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
13935 case X86ISD::FSETCC: return "X86ISD::FSETCC";
13936 case X86ISD::CMOV: return "X86ISD::CMOV";
13937 case X86ISD::BRCOND: return "X86ISD::BRCOND";
13938 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
13939 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
13940 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
13941 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
13942 case X86ISD::Wrapper: return "X86ISD::Wrapper";
13943 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
13944 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
13945 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
13946 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
13947 case X86ISD::PINSRB: return "X86ISD::PINSRB";
13948 case X86ISD::PINSRW: return "X86ISD::PINSRW";
13949 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
13950 case X86ISD::ANDNP: return "X86ISD::ANDNP";
13951 case X86ISD::PSIGN: return "X86ISD::PSIGN";
13952 case X86ISD::BLENDV: return "X86ISD::BLENDV";
13953 case X86ISD::BLENDI: return "X86ISD::BLENDI";
13954 case X86ISD::SUBUS: return "X86ISD::SUBUS";
13955 case X86ISD::HADD: return "X86ISD::HADD";
13956 case X86ISD::HSUB: return "X86ISD::HSUB";
13957 case X86ISD::FHADD: return "X86ISD::FHADD";
13958 case X86ISD::FHSUB: return "X86ISD::FHSUB";
13959 case X86ISD::UMAX: return "X86ISD::UMAX";
13960 case X86ISD::UMIN: return "X86ISD::UMIN";
13961 case X86ISD::SMAX: return "X86ISD::SMAX";
13962 case X86ISD::SMIN: return "X86ISD::SMIN";
13963 case X86ISD::FMAX: return "X86ISD::FMAX";
13964 case X86ISD::FMIN: return "X86ISD::FMIN";
13965 case X86ISD::FMAXC: return "X86ISD::FMAXC";
13966 case X86ISD::FMINC: return "X86ISD::FMINC";
13967 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
13968 case X86ISD::FRCP: return "X86ISD::FRCP";
13969 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
13970 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
13971 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
13972 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
13973 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
13974 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
13975 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
13976 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
13977 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
13978 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
13979 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
13980 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
13981 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
13982 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
13983 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
13984 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
13985 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
13986 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
13987 case X86ISD::VSEXT_MOVL: return "X86ISD::VSEXT_MOVL";
13988 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
13989 case X86ISD::VZEXT: return "X86ISD::VZEXT";
13990 case X86ISD::VSEXT: return "X86ISD::VSEXT";
13991 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
13992 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
13993 case X86ISD::VINSERT: return "X86ISD::VINSERT";
13994 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
13995 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
13996 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
13997 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
13998 case X86ISD::VSHL: return "X86ISD::VSHL";
13999 case X86ISD::VSRL: return "X86ISD::VSRL";
14000 case X86ISD::VSRA: return "X86ISD::VSRA";
14001 case X86ISD::VSHLI: return "X86ISD::VSHLI";
14002 case X86ISD::VSRLI: return "X86ISD::VSRLI";
14003 case X86ISD::VSRAI: return "X86ISD::VSRAI";
14004 case X86ISD::CMPP: return "X86ISD::CMPP";
14005 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
14006 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
14007 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
14008 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
14009 case X86ISD::ADD: return "X86ISD::ADD";
14010 case X86ISD::SUB: return "X86ISD::SUB";
14011 case X86ISD::ADC: return "X86ISD::ADC";
14012 case X86ISD::SBB: return "X86ISD::SBB";
14013 case X86ISD::SMUL: return "X86ISD::SMUL";
14014 case X86ISD::UMUL: return "X86ISD::UMUL";
14015 case X86ISD::INC: return "X86ISD::INC";
14016 case X86ISD::DEC: return "X86ISD::DEC";
14017 case X86ISD::OR: return "X86ISD::OR";
14018 case X86ISD::XOR: return "X86ISD::XOR";
14019 case X86ISD::AND: return "X86ISD::AND";
14020 case X86ISD::BLSI: return "X86ISD::BLSI";
14021 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
14022 case X86ISD::BLSR: return "X86ISD::BLSR";
14023 case X86ISD::BZHI: return "X86ISD::BZHI";
14024 case X86ISD::BEXTR: return "X86ISD::BEXTR";
14025 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
14026 case X86ISD::PTEST: return "X86ISD::PTEST";
14027 case X86ISD::TESTP: return "X86ISD::TESTP";
14028 case X86ISD::TESTM: return "X86ISD::TESTM";
14029 case X86ISD::KORTEST: return "X86ISD::KORTEST";
14030 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
14031 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
14032 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
14033 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
14034 case X86ISD::SHUFP: return "X86ISD::SHUFP";
14035 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
14036 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
14037 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
14038 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
14039 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
14040 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
14041 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
14042 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
14043 case X86ISD::MOVSD: return "X86ISD::MOVSD";
14044 case X86ISD::MOVSS: return "X86ISD::MOVSS";
14045 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
14046 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
14047 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
14048 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
14049 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
14050 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
14051 case X86ISD::VPERMV: return "X86ISD::VPERMV";
14052 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
14053 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
14054 case X86ISD::VPERMI: return "X86ISD::VPERMI";
14055 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
14056 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
14057 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
14058 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
14059 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
14060 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
14061 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
14062 case X86ISD::SAHF: return "X86ISD::SAHF";
14063 case X86ISD::RDRAND: return "X86ISD::RDRAND";
14064 case X86ISD::RDSEED: return "X86ISD::RDSEED";
14065 case X86ISD::FMADD: return "X86ISD::FMADD";
14066 case X86ISD::FMSUB: return "X86ISD::FMSUB";
14067 case X86ISD::FNMADD: return "X86ISD::FNMADD";
14068 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
14069 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
14070 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
14071 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
14072 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
14073 case X86ISD::XTEST: return "X86ISD::XTEST";
14077 // isLegalAddressingMode - Return true if the addressing mode represented
14078 // by AM is legal for this target, for a load/store of the specified type.
14079 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
14081 // X86 supports extremely general addressing modes.
14082 CodeModel::Model M = getTargetMachine().getCodeModel();
14083 Reloc::Model R = getTargetMachine().getRelocationModel();
14085 // X86 allows a sign-extended 32-bit immediate field as a displacement.
14086 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
14091 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
14093 // If a reference to this global requires an extra load, we can't fold it.
14094 if (isGlobalStubReference(GVFlags))
14097 // If BaseGV requires a register for the PIC base, we cannot also have a
14098 // BaseReg specified.
14099 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
14102 // If lower 4G is not available, then we must use rip-relative addressing.
14103 if ((M != CodeModel::Small || R != Reloc::Static) &&
14104 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
14108 switch (AM.Scale) {
14114 // These scales always work.
14119 // These scales are formed with basereg+scalereg. Only accept if there is
14124 default: // Other stuff never works.
14131 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
14132 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
14134 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
14135 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
14136 return NumBits1 > NumBits2;
14139 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
14140 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
14143 if (!isTypeLegal(EVT::getEVT(Ty1)))
14146 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
14148 // Assuming the caller doesn't have a zeroext or signext return parameter,
14149 // truncation all the way down to i1 is valid.
14153 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
14154 return isInt<32>(Imm);
14157 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
14158 // Can also use sub to handle negated immediates.
14159 return isInt<32>(Imm);
14162 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
14163 if (!VT1.isInteger() || !VT2.isInteger())
14165 unsigned NumBits1 = VT1.getSizeInBits();
14166 unsigned NumBits2 = VT2.getSizeInBits();
14167 return NumBits1 > NumBits2;
14170 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
14171 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
14172 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
14175 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
14176 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
14177 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
14180 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
14181 EVT VT1 = Val.getValueType();
14182 if (isZExtFree(VT1, VT2))
14185 if (Val.getOpcode() != ISD::LOAD)
14188 if (!VT1.isSimple() || !VT1.isInteger() ||
14189 !VT2.isSimple() || !VT2.isInteger())
14192 switch (VT1.getSimpleVT().SimpleTy) {
14197 // X86 has 8, 16, and 32-bit zero-extending loads.
14205 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
14206 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
14209 VT = VT.getScalarType();
14211 if (!VT.isSimple())
14214 switch (VT.getSimpleVT().SimpleTy) {
14225 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
14226 // i16 instructions are longer (0x66 prefix) and potentially slower.
14227 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
14230 /// isShuffleMaskLegal - Targets can use this to indicate that they only
14231 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
14232 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
14233 /// are assumed to be legal.
14235 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
14237 if (!VT.isSimple())
14240 MVT SVT = VT.getSimpleVT();
14242 // Very little shuffling can be done for 64-bit vectors right now.
14243 if (VT.getSizeInBits() == 64)
14246 // FIXME: pshufb, blends, shifts.
14247 return (SVT.getVectorNumElements() == 2 ||
14248 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
14249 isMOVLMask(M, SVT) ||
14250 isSHUFPMask(M, SVT) ||
14251 isPSHUFDMask(M, SVT) ||
14252 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
14253 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
14254 isPALIGNRMask(M, SVT, Subtarget) ||
14255 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
14256 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
14257 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
14258 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()));
14262 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
14264 if (!VT.isSimple())
14267 MVT SVT = VT.getSimpleVT();
14268 unsigned NumElts = SVT.getVectorNumElements();
14269 // FIXME: This collection of masks seems suspect.
14272 if (NumElts == 4 && SVT.is128BitVector()) {
14273 return (isMOVLMask(Mask, SVT) ||
14274 isCommutedMOVLMask(Mask, SVT, true) ||
14275 isSHUFPMask(Mask, SVT) ||
14276 isSHUFPMask(Mask, SVT, /* Commuted */ true));
14281 //===----------------------------------------------------------------------===//
14282 // X86 Scheduler Hooks
14283 //===----------------------------------------------------------------------===//
14285 /// Utility function to emit xbegin specifying the start of an RTM region.
14286 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
14287 const TargetInstrInfo *TII) {
14288 DebugLoc DL = MI->getDebugLoc();
14290 const BasicBlock *BB = MBB->getBasicBlock();
14291 MachineFunction::iterator I = MBB;
14294 // For the v = xbegin(), we generate
14305 MachineBasicBlock *thisMBB = MBB;
14306 MachineFunction *MF = MBB->getParent();
14307 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14308 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14309 MF->insert(I, mainMBB);
14310 MF->insert(I, sinkMBB);
14312 // Transfer the remainder of BB and its successor edges to sinkMBB.
14313 sinkMBB->splice(sinkMBB->begin(), MBB,
14314 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14315 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14319 // # fallthrough to mainMBB
14320 // # abortion to sinkMBB
14321 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
14322 thisMBB->addSuccessor(mainMBB);
14323 thisMBB->addSuccessor(sinkMBB);
14327 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
14328 mainMBB->addSuccessor(sinkMBB);
14331 // EAX is live into the sinkMBB
14332 sinkMBB->addLiveIn(X86::EAX);
14333 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14334 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14337 MI->eraseFromParent();
14341 // Get CMPXCHG opcode for the specified data type.
14342 static unsigned getCmpXChgOpcode(EVT VT) {
14343 switch (VT.getSimpleVT().SimpleTy) {
14344 case MVT::i8: return X86::LCMPXCHG8;
14345 case MVT::i16: return X86::LCMPXCHG16;
14346 case MVT::i32: return X86::LCMPXCHG32;
14347 case MVT::i64: return X86::LCMPXCHG64;
14351 llvm_unreachable("Invalid operand size!");
14354 // Get LOAD opcode for the specified data type.
14355 static unsigned getLoadOpcode(EVT VT) {
14356 switch (VT.getSimpleVT().SimpleTy) {
14357 case MVT::i8: return X86::MOV8rm;
14358 case MVT::i16: return X86::MOV16rm;
14359 case MVT::i32: return X86::MOV32rm;
14360 case MVT::i64: return X86::MOV64rm;
14364 llvm_unreachable("Invalid operand size!");
14367 // Get opcode of the non-atomic one from the specified atomic instruction.
14368 static unsigned getNonAtomicOpcode(unsigned Opc) {
14370 case X86::ATOMAND8: return X86::AND8rr;
14371 case X86::ATOMAND16: return X86::AND16rr;
14372 case X86::ATOMAND32: return X86::AND32rr;
14373 case X86::ATOMAND64: return X86::AND64rr;
14374 case X86::ATOMOR8: return X86::OR8rr;
14375 case X86::ATOMOR16: return X86::OR16rr;
14376 case X86::ATOMOR32: return X86::OR32rr;
14377 case X86::ATOMOR64: return X86::OR64rr;
14378 case X86::ATOMXOR8: return X86::XOR8rr;
14379 case X86::ATOMXOR16: return X86::XOR16rr;
14380 case X86::ATOMXOR32: return X86::XOR32rr;
14381 case X86::ATOMXOR64: return X86::XOR64rr;
14383 llvm_unreachable("Unhandled atomic-load-op opcode!");
14386 // Get opcode of the non-atomic one from the specified atomic instruction with
14388 static unsigned getNonAtomicOpcodeWithExtraOpc(unsigned Opc,
14389 unsigned &ExtraOpc) {
14391 case X86::ATOMNAND8: ExtraOpc = X86::NOT8r; return X86::AND8rr;
14392 case X86::ATOMNAND16: ExtraOpc = X86::NOT16r; return X86::AND16rr;
14393 case X86::ATOMNAND32: ExtraOpc = X86::NOT32r; return X86::AND32rr;
14394 case X86::ATOMNAND64: ExtraOpc = X86::NOT64r; return X86::AND64rr;
14395 case X86::ATOMMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVL32rr;
14396 case X86::ATOMMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVL16rr;
14397 case X86::ATOMMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVL32rr;
14398 case X86::ATOMMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVL64rr;
14399 case X86::ATOMMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVG32rr;
14400 case X86::ATOMMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVG16rr;
14401 case X86::ATOMMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVG32rr;
14402 case X86::ATOMMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVG64rr;
14403 case X86::ATOMUMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVB32rr;
14404 case X86::ATOMUMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVB16rr;
14405 case X86::ATOMUMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVB32rr;
14406 case X86::ATOMUMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVB64rr;
14407 case X86::ATOMUMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVA32rr;
14408 case X86::ATOMUMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVA16rr;
14409 case X86::ATOMUMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVA32rr;
14410 case X86::ATOMUMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVA64rr;
14412 llvm_unreachable("Unhandled atomic-load-op opcode!");
14415 // Get opcode of the non-atomic one from the specified atomic instruction for
14416 // 64-bit data type on 32-bit target.
14417 static unsigned getNonAtomic6432Opcode(unsigned Opc, unsigned &HiOpc) {
14419 case X86::ATOMAND6432: HiOpc = X86::AND32rr; return X86::AND32rr;
14420 case X86::ATOMOR6432: HiOpc = X86::OR32rr; return X86::OR32rr;
14421 case X86::ATOMXOR6432: HiOpc = X86::XOR32rr; return X86::XOR32rr;
14422 case X86::ATOMADD6432: HiOpc = X86::ADC32rr; return X86::ADD32rr;
14423 case X86::ATOMSUB6432: HiOpc = X86::SBB32rr; return X86::SUB32rr;
14424 case X86::ATOMSWAP6432: HiOpc = X86::MOV32rr; return X86::MOV32rr;
14425 case X86::ATOMMAX6432: HiOpc = X86::SETLr; return X86::SETLr;
14426 case X86::ATOMMIN6432: HiOpc = X86::SETGr; return X86::SETGr;
14427 case X86::ATOMUMAX6432: HiOpc = X86::SETBr; return X86::SETBr;
14428 case X86::ATOMUMIN6432: HiOpc = X86::SETAr; return X86::SETAr;
14430 llvm_unreachable("Unhandled atomic-load-op opcode!");
14433 // Get opcode of the non-atomic one from the specified atomic instruction for
14434 // 64-bit data type on 32-bit target with extra opcode.
14435 static unsigned getNonAtomic6432OpcodeWithExtraOpc(unsigned Opc,
14437 unsigned &ExtraOpc) {
14439 case X86::ATOMNAND6432:
14440 ExtraOpc = X86::NOT32r;
14441 HiOpc = X86::AND32rr;
14442 return X86::AND32rr;
14444 llvm_unreachable("Unhandled atomic-load-op opcode!");
14447 // Get pseudo CMOV opcode from the specified data type.
14448 static unsigned getPseudoCMOVOpc(EVT VT) {
14449 switch (VT.getSimpleVT().SimpleTy) {
14450 case MVT::i8: return X86::CMOV_GR8;
14451 case MVT::i16: return X86::CMOV_GR16;
14452 case MVT::i32: return X86::CMOV_GR32;
14456 llvm_unreachable("Unknown CMOV opcode!");
14459 // EmitAtomicLoadArith - emit the code sequence for pseudo atomic instructions.
14460 // They will be translated into a spin-loop or compare-exchange loop from
14463 // dst = atomic-fetch-op MI.addr, MI.val
14469 // t1 = LOAD MI.addr
14471 // t4 = phi(t1, t3 / loop)
14472 // t2 = OP MI.val, t4
14474 // LCMPXCHG [MI.addr], t2, [EAX is implicitly used & defined]
14480 MachineBasicBlock *
14481 X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
14482 MachineBasicBlock *MBB) const {
14483 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14484 DebugLoc DL = MI->getDebugLoc();
14486 MachineFunction *MF = MBB->getParent();
14487 MachineRegisterInfo &MRI = MF->getRegInfo();
14489 const BasicBlock *BB = MBB->getBasicBlock();
14490 MachineFunction::iterator I = MBB;
14493 assert(MI->getNumOperands() <= X86::AddrNumOperands + 4 &&
14494 "Unexpected number of operands");
14496 assert(MI->hasOneMemOperand() &&
14497 "Expected atomic-load-op to have one memoperand");
14499 // Memory Reference
14500 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14501 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14503 unsigned DstReg, SrcReg;
14504 unsigned MemOpndSlot;
14506 unsigned CurOp = 0;
14508 DstReg = MI->getOperand(CurOp++).getReg();
14509 MemOpndSlot = CurOp;
14510 CurOp += X86::AddrNumOperands;
14511 SrcReg = MI->getOperand(CurOp++).getReg();
14513 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
14514 MVT::SimpleValueType VT = *RC->vt_begin();
14515 unsigned t1 = MRI.createVirtualRegister(RC);
14516 unsigned t2 = MRI.createVirtualRegister(RC);
14517 unsigned t3 = MRI.createVirtualRegister(RC);
14518 unsigned t4 = MRI.createVirtualRegister(RC);
14519 unsigned PhyReg = getX86SubSuperRegister(X86::EAX, VT);
14521 unsigned LCMPXCHGOpc = getCmpXChgOpcode(VT);
14522 unsigned LOADOpc = getLoadOpcode(VT);
14524 // For the atomic load-arith operator, we generate
14527 // t1 = LOAD [MI.addr]
14529 // t4 = phi(t1 / thisMBB, t3 / mainMBB)
14530 // t1 = OP MI.val, EAX
14532 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
14538 MachineBasicBlock *thisMBB = MBB;
14539 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14540 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14541 MF->insert(I, mainMBB);
14542 MF->insert(I, sinkMBB);
14544 MachineInstrBuilder MIB;
14546 // Transfer the remainder of BB and its successor edges to sinkMBB.
14547 sinkMBB->splice(sinkMBB->begin(), MBB,
14548 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14549 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14552 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1);
14553 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14554 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14556 NewMO.setIsKill(false);
14557 MIB.addOperand(NewMO);
14559 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14560 unsigned flags = (*MMOI)->getFlags();
14561 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14562 MachineMemOperand *MMO =
14563 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14564 (*MMOI)->getSize(),
14565 (*MMOI)->getBaseAlignment(),
14566 (*MMOI)->getTBAAInfo(),
14567 (*MMOI)->getRanges());
14568 MIB.addMemOperand(MMO);
14571 thisMBB->addSuccessor(mainMBB);
14574 MachineBasicBlock *origMainMBB = mainMBB;
14577 MachineInstr *Phi = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4)
14578 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14580 unsigned Opc = MI->getOpcode();
14583 llvm_unreachable("Unhandled atomic-load-op opcode!");
14584 case X86::ATOMAND8:
14585 case X86::ATOMAND16:
14586 case X86::ATOMAND32:
14587 case X86::ATOMAND64:
14589 case X86::ATOMOR16:
14590 case X86::ATOMOR32:
14591 case X86::ATOMOR64:
14592 case X86::ATOMXOR8:
14593 case X86::ATOMXOR16:
14594 case X86::ATOMXOR32:
14595 case X86::ATOMXOR64: {
14596 unsigned ARITHOpc = getNonAtomicOpcode(Opc);
14597 BuildMI(mainMBB, DL, TII->get(ARITHOpc), t2).addReg(SrcReg)
14601 case X86::ATOMNAND8:
14602 case X86::ATOMNAND16:
14603 case X86::ATOMNAND32:
14604 case X86::ATOMNAND64: {
14605 unsigned Tmp = MRI.createVirtualRegister(RC);
14607 unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc(Opc, NOTOpc);
14608 BuildMI(mainMBB, DL, TII->get(ANDOpc), Tmp).addReg(SrcReg)
14610 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2).addReg(Tmp);
14613 case X86::ATOMMAX8:
14614 case X86::ATOMMAX16:
14615 case X86::ATOMMAX32:
14616 case X86::ATOMMAX64:
14617 case X86::ATOMMIN8:
14618 case X86::ATOMMIN16:
14619 case X86::ATOMMIN32:
14620 case X86::ATOMMIN64:
14621 case X86::ATOMUMAX8:
14622 case X86::ATOMUMAX16:
14623 case X86::ATOMUMAX32:
14624 case X86::ATOMUMAX64:
14625 case X86::ATOMUMIN8:
14626 case X86::ATOMUMIN16:
14627 case X86::ATOMUMIN32:
14628 case X86::ATOMUMIN64: {
14630 unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc(Opc, CMPOpc);
14632 BuildMI(mainMBB, DL, TII->get(CMPOpc))
14636 if (Subtarget->hasCMov()) {
14637 if (VT != MVT::i8) {
14639 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t2)
14643 // Promote i8 to i32 to use CMOV32
14644 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
14645 const TargetRegisterClass *RC32 =
14646 TRI->getSubClassWithSubReg(getRegClassFor(MVT::i32), X86::sub_8bit);
14647 unsigned SrcReg32 = MRI.createVirtualRegister(RC32);
14648 unsigned AccReg32 = MRI.createVirtualRegister(RC32);
14649 unsigned Tmp = MRI.createVirtualRegister(RC32);
14651 unsigned Undef = MRI.createVirtualRegister(RC32);
14652 BuildMI(mainMBB, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Undef);
14654 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), SrcReg32)
14657 .addImm(X86::sub_8bit);
14658 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), AccReg32)
14661 .addImm(X86::sub_8bit);
14663 BuildMI(mainMBB, DL, TII->get(CMOVOpc), Tmp)
14667 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t2)
14668 .addReg(Tmp, 0, X86::sub_8bit);
14671 // Use pseudo select and lower them.
14672 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) &&
14673 "Invalid atomic-load-op transformation!");
14674 unsigned SelOpc = getPseudoCMOVOpc(VT);
14675 X86::CondCode CC = X86::getCondFromCMovOpc(CMOVOpc);
14676 assert(CC != X86::COND_INVALID && "Invalid atomic-load-op transformation!");
14677 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t2)
14678 .addReg(SrcReg).addReg(t4)
14680 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14681 // Replace the original PHI node as mainMBB is changed after CMOV
14683 BuildMI(*origMainMBB, Phi, DL, TII->get(X86::PHI), t4)
14684 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14685 Phi->eraseFromParent();
14691 // Copy PhyReg back from virtual register.
14692 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), PhyReg)
14695 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14696 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14697 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14699 NewMO.setIsKill(false);
14700 MIB.addOperand(NewMO);
14703 MIB.setMemRefs(MMOBegin, MMOEnd);
14705 // Copy PhyReg back to virtual register.
14706 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3)
14709 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14711 mainMBB->addSuccessor(origMainMBB);
14712 mainMBB->addSuccessor(sinkMBB);
14715 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14716 TII->get(TargetOpcode::COPY), DstReg)
14719 MI->eraseFromParent();
14723 // EmitAtomicLoadArith6432 - emit the code sequence for pseudo atomic
14724 // instructions. They will be translated into a spin-loop or compare-exchange
14728 // dst = atomic-fetch-op MI.addr, MI.val
14734 // t1L = LOAD [MI.addr + 0]
14735 // t1H = LOAD [MI.addr + 4]
14737 // t4L = phi(t1L, t3L / loop)
14738 // t4H = phi(t1H, t3H / loop)
14739 // t2L = OP MI.val.lo, t4L
14740 // t2H = OP MI.val.hi, t4H
14745 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14753 MachineBasicBlock *
14754 X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI,
14755 MachineBasicBlock *MBB) const {
14756 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14757 DebugLoc DL = MI->getDebugLoc();
14759 MachineFunction *MF = MBB->getParent();
14760 MachineRegisterInfo &MRI = MF->getRegInfo();
14762 const BasicBlock *BB = MBB->getBasicBlock();
14763 MachineFunction::iterator I = MBB;
14766 assert(MI->getNumOperands() <= X86::AddrNumOperands + 7 &&
14767 "Unexpected number of operands");
14769 assert(MI->hasOneMemOperand() &&
14770 "Expected atomic-load-op32 to have one memoperand");
14772 // Memory Reference
14773 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14774 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14776 unsigned DstLoReg, DstHiReg;
14777 unsigned SrcLoReg, SrcHiReg;
14778 unsigned MemOpndSlot;
14780 unsigned CurOp = 0;
14782 DstLoReg = MI->getOperand(CurOp++).getReg();
14783 DstHiReg = MI->getOperand(CurOp++).getReg();
14784 MemOpndSlot = CurOp;
14785 CurOp += X86::AddrNumOperands;
14786 SrcLoReg = MI->getOperand(CurOp++).getReg();
14787 SrcHiReg = MI->getOperand(CurOp++).getReg();
14789 const TargetRegisterClass *RC = &X86::GR32RegClass;
14790 const TargetRegisterClass *RC8 = &X86::GR8RegClass;
14792 unsigned t1L = MRI.createVirtualRegister(RC);
14793 unsigned t1H = MRI.createVirtualRegister(RC);
14794 unsigned t2L = MRI.createVirtualRegister(RC);
14795 unsigned t2H = MRI.createVirtualRegister(RC);
14796 unsigned t3L = MRI.createVirtualRegister(RC);
14797 unsigned t3H = MRI.createVirtualRegister(RC);
14798 unsigned t4L = MRI.createVirtualRegister(RC);
14799 unsigned t4H = MRI.createVirtualRegister(RC);
14801 unsigned LCMPXCHGOpc = X86::LCMPXCHG8B;
14802 unsigned LOADOpc = X86::MOV32rm;
14804 // For the atomic load-arith operator, we generate
14807 // t1L = LOAD [MI.addr + 0]
14808 // t1H = LOAD [MI.addr + 4]
14810 // t4L = phi(t1L / thisMBB, t3L / mainMBB)
14811 // t4H = phi(t1H / thisMBB, t3H / mainMBB)
14812 // t2L = OP MI.val.lo, t4L
14813 // t2H = OP MI.val.hi, t4H
14816 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14824 MachineBasicBlock *thisMBB = MBB;
14825 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14826 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14827 MF->insert(I, mainMBB);
14828 MF->insert(I, sinkMBB);
14830 MachineInstrBuilder MIB;
14832 // Transfer the remainder of BB and its successor edges to sinkMBB.
14833 sinkMBB->splice(sinkMBB->begin(), MBB,
14834 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14835 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14839 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1L);
14840 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14841 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14843 NewMO.setIsKill(false);
14844 MIB.addOperand(NewMO);
14846 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14847 unsigned flags = (*MMOI)->getFlags();
14848 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14849 MachineMemOperand *MMO =
14850 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14851 (*MMOI)->getSize(),
14852 (*MMOI)->getBaseAlignment(),
14853 (*MMOI)->getTBAAInfo(),
14854 (*MMOI)->getRanges());
14855 MIB.addMemOperand(MMO);
14857 MachineInstr *LowMI = MIB;
14860 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1H);
14861 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14862 if (i == X86::AddrDisp) {
14863 MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32)
14865 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14867 NewMO.setIsKill(false);
14868 MIB.addOperand(NewMO);
14871 MIB.setMemRefs(LowMI->memoperands_begin(), LowMI->memoperands_end());
14873 thisMBB->addSuccessor(mainMBB);
14876 MachineBasicBlock *origMainMBB = mainMBB;
14879 MachineInstr *PhiL = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4L)
14880 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14881 MachineInstr *PhiH = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4H)
14882 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
14884 unsigned Opc = MI->getOpcode();
14887 llvm_unreachable("Unhandled atomic-load-op6432 opcode!");
14888 case X86::ATOMAND6432:
14889 case X86::ATOMOR6432:
14890 case X86::ATOMXOR6432:
14891 case X86::ATOMADD6432:
14892 case X86::ATOMSUB6432: {
14894 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14895 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(t4L)
14897 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(t4H)
14901 case X86::ATOMNAND6432: {
14902 unsigned HiOpc, NOTOpc;
14903 unsigned LoOpc = getNonAtomic6432OpcodeWithExtraOpc(Opc, HiOpc, NOTOpc);
14904 unsigned TmpL = MRI.createVirtualRegister(RC);
14905 unsigned TmpH = MRI.createVirtualRegister(RC);
14906 BuildMI(mainMBB, DL, TII->get(LoOpc), TmpL).addReg(SrcLoReg)
14908 BuildMI(mainMBB, DL, TII->get(HiOpc), TmpH).addReg(SrcHiReg)
14910 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2L).addReg(TmpL);
14911 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2H).addReg(TmpH);
14914 case X86::ATOMMAX6432:
14915 case X86::ATOMMIN6432:
14916 case X86::ATOMUMAX6432:
14917 case X86::ATOMUMIN6432: {
14919 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14920 unsigned cL = MRI.createVirtualRegister(RC8);
14921 unsigned cH = MRI.createVirtualRegister(RC8);
14922 unsigned cL32 = MRI.createVirtualRegister(RC);
14923 unsigned cH32 = MRI.createVirtualRegister(RC);
14924 unsigned cc = MRI.createVirtualRegister(RC);
14925 // cl := cmp src_lo, lo
14926 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14927 .addReg(SrcLoReg).addReg(t4L);
14928 BuildMI(mainMBB, DL, TII->get(LoOpc), cL);
14929 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cL32).addReg(cL);
14930 // ch := cmp src_hi, hi
14931 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14932 .addReg(SrcHiReg).addReg(t4H);
14933 BuildMI(mainMBB, DL, TII->get(HiOpc), cH);
14934 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cH32).addReg(cH);
14935 // cc := if (src_hi == hi) ? cl : ch;
14936 if (Subtarget->hasCMov()) {
14937 BuildMI(mainMBB, DL, TII->get(X86::CMOVE32rr), cc)
14938 .addReg(cH32).addReg(cL32);
14940 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), cc)
14941 .addReg(cH32).addReg(cL32)
14942 .addImm(X86::COND_E);
14943 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14945 BuildMI(mainMBB, DL, TII->get(X86::TEST32rr)).addReg(cc).addReg(cc);
14946 if (Subtarget->hasCMov()) {
14947 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2L)
14948 .addReg(SrcLoReg).addReg(t4L);
14949 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2H)
14950 .addReg(SrcHiReg).addReg(t4H);
14952 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2L)
14953 .addReg(SrcLoReg).addReg(t4L)
14954 .addImm(X86::COND_NE);
14955 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14956 // As the lowered CMOV won't clobber EFLAGS, we could reuse it for the
14957 // 2nd CMOV lowering.
14958 mainMBB->addLiveIn(X86::EFLAGS);
14959 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2H)
14960 .addReg(SrcHiReg).addReg(t4H)
14961 .addImm(X86::COND_NE);
14962 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14963 // Replace the original PHI node as mainMBB is changed after CMOV
14965 BuildMI(*origMainMBB, PhiL, DL, TII->get(X86::PHI), t4L)
14966 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14967 BuildMI(*origMainMBB, PhiH, DL, TII->get(X86::PHI), t4H)
14968 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
14969 PhiL->eraseFromParent();
14970 PhiH->eraseFromParent();
14974 case X86::ATOMSWAP6432: {
14976 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14977 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(SrcLoReg);
14978 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(SrcHiReg);
14983 // Copy EDX:EAX back from HiReg:LoReg
14984 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(t4L);
14985 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(t4H);
14986 // Copy ECX:EBX from t1H:t1L
14987 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t2L);
14988 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t2H);
14990 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14991 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14992 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14994 NewMO.setIsKill(false);
14995 MIB.addOperand(NewMO);
14997 MIB.setMemRefs(MMOBegin, MMOEnd);
14999 // Copy EDX:EAX back to t3H:t3L
15000 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3L).addReg(X86::EAX);
15001 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3H).addReg(X86::EDX);
15003 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
15005 mainMBB->addSuccessor(origMainMBB);
15006 mainMBB->addSuccessor(sinkMBB);
15009 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15010 TII->get(TargetOpcode::COPY), DstLoReg)
15012 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15013 TII->get(TargetOpcode::COPY), DstHiReg)
15016 MI->eraseFromParent();
15020 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
15021 // or XMM0_V32I8 in AVX all of this code can be replaced with that
15022 // in the .td file.
15023 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
15024 const TargetInstrInfo *TII) {
15026 switch (MI->getOpcode()) {
15027 default: llvm_unreachable("illegal opcode!");
15028 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
15029 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
15030 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
15031 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
15032 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
15033 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
15034 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
15035 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
15038 DebugLoc dl = MI->getDebugLoc();
15039 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
15041 unsigned NumArgs = MI->getNumOperands();
15042 for (unsigned i = 1; i < NumArgs; ++i) {
15043 MachineOperand &Op = MI->getOperand(i);
15044 if (!(Op.isReg() && Op.isImplicit()))
15045 MIB.addOperand(Op);
15047 if (MI->hasOneMemOperand())
15048 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
15050 BuildMI(*BB, MI, dl,
15051 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
15052 .addReg(X86::XMM0);
15054 MI->eraseFromParent();
15058 // FIXME: Custom handling because TableGen doesn't support multiple implicit
15059 // defs in an instruction pattern
15060 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
15061 const TargetInstrInfo *TII) {
15063 switch (MI->getOpcode()) {
15064 default: llvm_unreachable("illegal opcode!");
15065 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
15066 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
15067 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
15068 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
15069 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
15070 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
15071 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
15072 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
15075 DebugLoc dl = MI->getDebugLoc();
15076 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
15078 unsigned NumArgs = MI->getNumOperands(); // remove the results
15079 for (unsigned i = 1; i < NumArgs; ++i) {
15080 MachineOperand &Op = MI->getOperand(i);
15081 if (!(Op.isReg() && Op.isImplicit()))
15082 MIB.addOperand(Op);
15084 if (MI->hasOneMemOperand())
15085 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
15087 BuildMI(*BB, MI, dl,
15088 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
15091 MI->eraseFromParent();
15095 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
15096 const TargetInstrInfo *TII,
15097 const X86Subtarget* Subtarget) {
15098 DebugLoc dl = MI->getDebugLoc();
15100 // Address into RAX/EAX, other two args into ECX, EDX.
15101 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
15102 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
15103 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
15104 for (int i = 0; i < X86::AddrNumOperands; ++i)
15105 MIB.addOperand(MI->getOperand(i));
15107 unsigned ValOps = X86::AddrNumOperands;
15108 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
15109 .addReg(MI->getOperand(ValOps).getReg());
15110 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
15111 .addReg(MI->getOperand(ValOps+1).getReg());
15113 // The instruction doesn't actually take any operands though.
15114 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
15116 MI->eraseFromParent(); // The pseudo is gone now.
15120 MachineBasicBlock *
15121 X86TargetLowering::EmitVAARG64WithCustomInserter(
15123 MachineBasicBlock *MBB) const {
15124 // Emit va_arg instruction on X86-64.
15126 // Operands to this pseudo-instruction:
15127 // 0 ) Output : destination address (reg)
15128 // 1-5) Input : va_list address (addr, i64mem)
15129 // 6 ) ArgSize : Size (in bytes) of vararg type
15130 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
15131 // 8 ) Align : Alignment of type
15132 // 9 ) EFLAGS (implicit-def)
15134 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
15135 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
15137 unsigned DestReg = MI->getOperand(0).getReg();
15138 MachineOperand &Base = MI->getOperand(1);
15139 MachineOperand &Scale = MI->getOperand(2);
15140 MachineOperand &Index = MI->getOperand(3);
15141 MachineOperand &Disp = MI->getOperand(4);
15142 MachineOperand &Segment = MI->getOperand(5);
15143 unsigned ArgSize = MI->getOperand(6).getImm();
15144 unsigned ArgMode = MI->getOperand(7).getImm();
15145 unsigned Align = MI->getOperand(8).getImm();
15147 // Memory Reference
15148 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
15149 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15150 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15152 // Machine Information
15153 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15154 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
15155 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
15156 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
15157 DebugLoc DL = MI->getDebugLoc();
15159 // struct va_list {
15162 // i64 overflow_area (address)
15163 // i64 reg_save_area (address)
15165 // sizeof(va_list) = 24
15166 // alignment(va_list) = 8
15168 unsigned TotalNumIntRegs = 6;
15169 unsigned TotalNumXMMRegs = 8;
15170 bool UseGPOffset = (ArgMode == 1);
15171 bool UseFPOffset = (ArgMode == 2);
15172 unsigned MaxOffset = TotalNumIntRegs * 8 +
15173 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
15175 /* Align ArgSize to a multiple of 8 */
15176 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
15177 bool NeedsAlign = (Align > 8);
15179 MachineBasicBlock *thisMBB = MBB;
15180 MachineBasicBlock *overflowMBB;
15181 MachineBasicBlock *offsetMBB;
15182 MachineBasicBlock *endMBB;
15184 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
15185 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
15186 unsigned OffsetReg = 0;
15188 if (!UseGPOffset && !UseFPOffset) {
15189 // If we only pull from the overflow region, we don't create a branch.
15190 // We don't need to alter control flow.
15191 OffsetDestReg = 0; // unused
15192 OverflowDestReg = DestReg;
15195 overflowMBB = thisMBB;
15198 // First emit code to check if gp_offset (or fp_offset) is below the bound.
15199 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
15200 // If not, pull from overflow_area. (branch to overflowMBB)
15205 // offsetMBB overflowMBB
15210 // Registers for the PHI in endMBB
15211 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
15212 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
15214 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
15215 MachineFunction *MF = MBB->getParent();
15216 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15217 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15218 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15220 MachineFunction::iterator MBBIter = MBB;
15223 // Insert the new basic blocks
15224 MF->insert(MBBIter, offsetMBB);
15225 MF->insert(MBBIter, overflowMBB);
15226 MF->insert(MBBIter, endMBB);
15228 // Transfer the remainder of MBB and its successor edges to endMBB.
15229 endMBB->splice(endMBB->begin(), thisMBB,
15230 llvm::next(MachineBasicBlock::iterator(MI)),
15232 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
15234 // Make offsetMBB and overflowMBB successors of thisMBB
15235 thisMBB->addSuccessor(offsetMBB);
15236 thisMBB->addSuccessor(overflowMBB);
15238 // endMBB is a successor of both offsetMBB and overflowMBB
15239 offsetMBB->addSuccessor(endMBB);
15240 overflowMBB->addSuccessor(endMBB);
15242 // Load the offset value into a register
15243 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
15244 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
15248 .addDisp(Disp, UseFPOffset ? 4 : 0)
15249 .addOperand(Segment)
15250 .setMemRefs(MMOBegin, MMOEnd);
15252 // Check if there is enough room left to pull this argument.
15253 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
15255 .addImm(MaxOffset + 8 - ArgSizeA8);
15257 // Branch to "overflowMBB" if offset >= max
15258 // Fall through to "offsetMBB" otherwise
15259 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
15260 .addMBB(overflowMBB);
15263 // In offsetMBB, emit code to use the reg_save_area.
15265 assert(OffsetReg != 0);
15267 // Read the reg_save_area address.
15268 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
15269 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
15274 .addOperand(Segment)
15275 .setMemRefs(MMOBegin, MMOEnd);
15277 // Zero-extend the offset
15278 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
15279 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
15282 .addImm(X86::sub_32bit);
15284 // Add the offset to the reg_save_area to get the final address.
15285 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
15286 .addReg(OffsetReg64)
15287 .addReg(RegSaveReg);
15289 // Compute the offset for the next argument
15290 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
15291 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
15293 .addImm(UseFPOffset ? 16 : 8);
15295 // Store it back into the va_list.
15296 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
15300 .addDisp(Disp, UseFPOffset ? 4 : 0)
15301 .addOperand(Segment)
15302 .addReg(NextOffsetReg)
15303 .setMemRefs(MMOBegin, MMOEnd);
15306 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
15311 // Emit code to use overflow area
15314 // Load the overflow_area address into a register.
15315 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
15316 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
15321 .addOperand(Segment)
15322 .setMemRefs(MMOBegin, MMOEnd);
15324 // If we need to align it, do so. Otherwise, just copy the address
15325 // to OverflowDestReg.
15327 // Align the overflow address
15328 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
15329 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
15331 // aligned_addr = (addr + (align-1)) & ~(align-1)
15332 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
15333 .addReg(OverflowAddrReg)
15336 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
15338 .addImm(~(uint64_t)(Align-1));
15340 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
15341 .addReg(OverflowAddrReg);
15344 // Compute the next overflow address after this argument.
15345 // (the overflow address should be kept 8-byte aligned)
15346 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
15347 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
15348 .addReg(OverflowDestReg)
15349 .addImm(ArgSizeA8);
15351 // Store the new overflow address.
15352 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
15357 .addOperand(Segment)
15358 .addReg(NextAddrReg)
15359 .setMemRefs(MMOBegin, MMOEnd);
15361 // If we branched, emit the PHI to the front of endMBB.
15363 BuildMI(*endMBB, endMBB->begin(), DL,
15364 TII->get(X86::PHI), DestReg)
15365 .addReg(OffsetDestReg).addMBB(offsetMBB)
15366 .addReg(OverflowDestReg).addMBB(overflowMBB);
15369 // Erase the pseudo instruction
15370 MI->eraseFromParent();
15375 MachineBasicBlock *
15376 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
15378 MachineBasicBlock *MBB) const {
15379 // Emit code to save XMM registers to the stack. The ABI says that the
15380 // number of registers to save is given in %al, so it's theoretically
15381 // possible to do an indirect jump trick to avoid saving all of them,
15382 // however this code takes a simpler approach and just executes all
15383 // of the stores if %al is non-zero. It's less code, and it's probably
15384 // easier on the hardware branch predictor, and stores aren't all that
15385 // expensive anyway.
15387 // Create the new basic blocks. One block contains all the XMM stores,
15388 // and one block is the final destination regardless of whether any
15389 // stores were performed.
15390 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
15391 MachineFunction *F = MBB->getParent();
15392 MachineFunction::iterator MBBIter = MBB;
15394 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
15395 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
15396 F->insert(MBBIter, XMMSaveMBB);
15397 F->insert(MBBIter, EndMBB);
15399 // Transfer the remainder of MBB and its successor edges to EndMBB.
15400 EndMBB->splice(EndMBB->begin(), MBB,
15401 llvm::next(MachineBasicBlock::iterator(MI)),
15403 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
15405 // The original block will now fall through to the XMM save block.
15406 MBB->addSuccessor(XMMSaveMBB);
15407 // The XMMSaveMBB will fall through to the end block.
15408 XMMSaveMBB->addSuccessor(EndMBB);
15410 // Now add the instructions.
15411 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15412 DebugLoc DL = MI->getDebugLoc();
15414 unsigned CountReg = MI->getOperand(0).getReg();
15415 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
15416 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
15418 if (!Subtarget->isTargetWin64()) {
15419 // If %al is 0, branch around the XMM save block.
15420 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
15421 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
15422 MBB->addSuccessor(EndMBB);
15425 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
15426 // that was just emitted, but clearly shouldn't be "saved".
15427 assert((MI->getNumOperands() <= 3 ||
15428 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
15429 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
15430 && "Expected last argument to be EFLAGS");
15431 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
15432 // In the XMM save block, save all the XMM argument registers.
15433 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
15434 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
15435 MachineMemOperand *MMO =
15436 F->getMachineMemOperand(
15437 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
15438 MachineMemOperand::MOStore,
15439 /*Size=*/16, /*Align=*/16);
15440 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
15441 .addFrameIndex(RegSaveFrameIndex)
15442 .addImm(/*Scale=*/1)
15443 .addReg(/*IndexReg=*/0)
15444 .addImm(/*Disp=*/Offset)
15445 .addReg(/*Segment=*/0)
15446 .addReg(MI->getOperand(i).getReg())
15447 .addMemOperand(MMO);
15450 MI->eraseFromParent(); // The pseudo instruction is gone now.
15455 // The EFLAGS operand of SelectItr might be missing a kill marker
15456 // because there were multiple uses of EFLAGS, and ISel didn't know
15457 // which to mark. Figure out whether SelectItr should have had a
15458 // kill marker, and set it if it should. Returns the correct kill
15460 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
15461 MachineBasicBlock* BB,
15462 const TargetRegisterInfo* TRI) {
15463 // Scan forward through BB for a use/def of EFLAGS.
15464 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
15465 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
15466 const MachineInstr& mi = *miI;
15467 if (mi.readsRegister(X86::EFLAGS))
15469 if (mi.definesRegister(X86::EFLAGS))
15470 break; // Should have kill-flag - update below.
15473 // If we hit the end of the block, check whether EFLAGS is live into a
15475 if (miI == BB->end()) {
15476 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
15477 sEnd = BB->succ_end();
15478 sItr != sEnd; ++sItr) {
15479 MachineBasicBlock* succ = *sItr;
15480 if (succ->isLiveIn(X86::EFLAGS))
15485 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
15486 // out. SelectMI should have a kill flag on EFLAGS.
15487 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
15491 MachineBasicBlock *
15492 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
15493 MachineBasicBlock *BB) const {
15494 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15495 DebugLoc DL = MI->getDebugLoc();
15497 // To "insert" a SELECT_CC instruction, we actually have to insert the
15498 // diamond control-flow pattern. The incoming instruction knows the
15499 // destination vreg to set, the condition code register to branch on, the
15500 // true/false values to select between, and a branch opcode to use.
15501 const BasicBlock *LLVM_BB = BB->getBasicBlock();
15502 MachineFunction::iterator It = BB;
15508 // cmpTY ccX, r1, r2
15510 // fallthrough --> copy0MBB
15511 MachineBasicBlock *thisMBB = BB;
15512 MachineFunction *F = BB->getParent();
15513 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
15514 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
15515 F->insert(It, copy0MBB);
15516 F->insert(It, sinkMBB);
15518 // If the EFLAGS register isn't dead in the terminator, then claim that it's
15519 // live into the sink and copy blocks.
15520 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
15521 if (!MI->killsRegister(X86::EFLAGS) &&
15522 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
15523 copy0MBB->addLiveIn(X86::EFLAGS);
15524 sinkMBB->addLiveIn(X86::EFLAGS);
15527 // Transfer the remainder of BB and its successor edges to sinkMBB.
15528 sinkMBB->splice(sinkMBB->begin(), BB,
15529 llvm::next(MachineBasicBlock::iterator(MI)),
15531 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
15533 // Add the true and fallthrough blocks as its successors.
15534 BB->addSuccessor(copy0MBB);
15535 BB->addSuccessor(sinkMBB);
15537 // Create the conditional branch instruction.
15539 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
15540 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
15543 // %FalseValue = ...
15544 // # fallthrough to sinkMBB
15545 copy0MBB->addSuccessor(sinkMBB);
15548 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
15550 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15551 TII->get(X86::PHI), MI->getOperand(0).getReg())
15552 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
15553 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
15555 MI->eraseFromParent(); // The pseudo instruction is gone now.
15559 MachineBasicBlock *
15560 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
15561 bool Is64Bit) const {
15562 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15563 DebugLoc DL = MI->getDebugLoc();
15564 MachineFunction *MF = BB->getParent();
15565 const BasicBlock *LLVM_BB = BB->getBasicBlock();
15567 assert(getTargetMachine().Options.EnableSegmentedStacks);
15569 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
15570 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
15573 // ... [Till the alloca]
15574 // If stacklet is not large enough, jump to mallocMBB
15577 // Allocate by subtracting from RSP
15578 // Jump to continueMBB
15581 // Allocate by call to runtime
15585 // [rest of original BB]
15588 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15589 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15590 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15592 MachineRegisterInfo &MRI = MF->getRegInfo();
15593 const TargetRegisterClass *AddrRegClass =
15594 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
15596 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
15597 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
15598 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
15599 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
15600 sizeVReg = MI->getOperand(1).getReg(),
15601 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
15603 MachineFunction::iterator MBBIter = BB;
15606 MF->insert(MBBIter, bumpMBB);
15607 MF->insert(MBBIter, mallocMBB);
15608 MF->insert(MBBIter, continueMBB);
15610 continueMBB->splice(continueMBB->begin(), BB, llvm::next
15611 (MachineBasicBlock::iterator(MI)), BB->end());
15612 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
15614 // Add code to the main basic block to check if the stack limit has been hit,
15615 // and if so, jump to mallocMBB otherwise to bumpMBB.
15616 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
15617 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
15618 .addReg(tmpSPVReg).addReg(sizeVReg);
15619 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
15620 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
15621 .addReg(SPLimitVReg);
15622 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
15624 // bumpMBB simply decreases the stack pointer, since we know the current
15625 // stacklet has enough space.
15626 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
15627 .addReg(SPLimitVReg);
15628 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
15629 .addReg(SPLimitVReg);
15630 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15632 // Calls into a routine in libgcc to allocate more space from the heap.
15633 const uint32_t *RegMask =
15634 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15636 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
15638 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
15639 .addExternalSymbol("__morestack_allocate_stack_space")
15640 .addRegMask(RegMask)
15641 .addReg(X86::RDI, RegState::Implicit)
15642 .addReg(X86::RAX, RegState::ImplicitDefine);
15644 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
15646 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
15647 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
15648 .addExternalSymbol("__morestack_allocate_stack_space")
15649 .addRegMask(RegMask)
15650 .addReg(X86::EAX, RegState::ImplicitDefine);
15654 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
15657 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
15658 .addReg(Is64Bit ? X86::RAX : X86::EAX);
15659 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15661 // Set up the CFG correctly.
15662 BB->addSuccessor(bumpMBB);
15663 BB->addSuccessor(mallocMBB);
15664 mallocMBB->addSuccessor(continueMBB);
15665 bumpMBB->addSuccessor(continueMBB);
15667 // Take care of the PHI nodes.
15668 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
15669 MI->getOperand(0).getReg())
15670 .addReg(mallocPtrVReg).addMBB(mallocMBB)
15671 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
15673 // Delete the original pseudo instruction.
15674 MI->eraseFromParent();
15677 return continueMBB;
15680 MachineBasicBlock *
15681 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
15682 MachineBasicBlock *BB) const {
15683 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15684 DebugLoc DL = MI->getDebugLoc();
15686 assert(!Subtarget->isTargetMacho());
15688 // The lowering is pretty easy: we're just emitting the call to _alloca. The
15689 // non-trivial part is impdef of ESP.
15691 if (Subtarget->isTargetWin64()) {
15692 if (Subtarget->isTargetCygMing()) {
15693 // ___chkstk(Mingw64):
15694 // Clobbers R10, R11, RAX and EFLAGS.
15696 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15697 .addExternalSymbol("___chkstk")
15698 .addReg(X86::RAX, RegState::Implicit)
15699 .addReg(X86::RSP, RegState::Implicit)
15700 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
15701 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
15702 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15704 // __chkstk(MSVCRT): does not update stack pointer.
15705 // Clobbers R10, R11 and EFLAGS.
15706 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15707 .addExternalSymbol("__chkstk")
15708 .addReg(X86::RAX, RegState::Implicit)
15709 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15710 // RAX has the offset to be subtracted from RSP.
15711 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
15716 const char *StackProbeSymbol =
15717 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
15719 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
15720 .addExternalSymbol(StackProbeSymbol)
15721 .addReg(X86::EAX, RegState::Implicit)
15722 .addReg(X86::ESP, RegState::Implicit)
15723 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
15724 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
15725 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15728 MI->eraseFromParent(); // The pseudo instruction is gone now.
15732 MachineBasicBlock *
15733 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
15734 MachineBasicBlock *BB) const {
15735 // This is pretty easy. We're taking the value that we received from
15736 // our load from the relocation, sticking it in either RDI (x86-64)
15737 // or EAX and doing an indirect call. The return value will then
15738 // be in the normal return register.
15739 const X86InstrInfo *TII
15740 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
15741 DebugLoc DL = MI->getDebugLoc();
15742 MachineFunction *F = BB->getParent();
15744 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
15745 assert(MI->getOperand(3).isGlobal() && "This should be a global");
15747 // Get a register mask for the lowered call.
15748 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
15749 // proper register mask.
15750 const uint32_t *RegMask =
15751 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15752 if (Subtarget->is64Bit()) {
15753 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15754 TII->get(X86::MOV64rm), X86::RDI)
15756 .addImm(0).addReg(0)
15757 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15758 MI->getOperand(3).getTargetFlags())
15760 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
15761 addDirectMem(MIB, X86::RDI);
15762 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
15763 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
15764 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15765 TII->get(X86::MOV32rm), X86::EAX)
15767 .addImm(0).addReg(0)
15768 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15769 MI->getOperand(3).getTargetFlags())
15771 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15772 addDirectMem(MIB, X86::EAX);
15773 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15775 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15776 TII->get(X86::MOV32rm), X86::EAX)
15777 .addReg(TII->getGlobalBaseReg(F))
15778 .addImm(0).addReg(0)
15779 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15780 MI->getOperand(3).getTargetFlags())
15782 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15783 addDirectMem(MIB, X86::EAX);
15784 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15787 MI->eraseFromParent(); // The pseudo instruction is gone now.
15791 MachineBasicBlock *
15792 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
15793 MachineBasicBlock *MBB) const {
15794 DebugLoc DL = MI->getDebugLoc();
15795 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15797 MachineFunction *MF = MBB->getParent();
15798 MachineRegisterInfo &MRI = MF->getRegInfo();
15800 const BasicBlock *BB = MBB->getBasicBlock();
15801 MachineFunction::iterator I = MBB;
15804 // Memory Reference
15805 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15806 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15809 unsigned MemOpndSlot = 0;
15811 unsigned CurOp = 0;
15813 DstReg = MI->getOperand(CurOp++).getReg();
15814 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
15815 assert(RC->hasType(MVT::i32) && "Invalid destination!");
15816 unsigned mainDstReg = MRI.createVirtualRegister(RC);
15817 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
15819 MemOpndSlot = CurOp;
15821 MVT PVT = getPointerTy();
15822 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15823 "Invalid Pointer Size!");
15825 // For v = setjmp(buf), we generate
15828 // buf[LabelOffset] = restoreMBB
15829 // SjLjSetup restoreMBB
15835 // v = phi(main, restore)
15840 MachineBasicBlock *thisMBB = MBB;
15841 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
15842 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
15843 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
15844 MF->insert(I, mainMBB);
15845 MF->insert(I, sinkMBB);
15846 MF->push_back(restoreMBB);
15848 MachineInstrBuilder MIB;
15850 // Transfer the remainder of BB and its successor edges to sinkMBB.
15851 sinkMBB->splice(sinkMBB->begin(), MBB,
15852 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
15853 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
15856 unsigned PtrStoreOpc = 0;
15857 unsigned LabelReg = 0;
15858 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15859 Reloc::Model RM = getTargetMachine().getRelocationModel();
15860 bool UseImmLabel = (getTargetMachine().getCodeModel() == CodeModel::Small) &&
15861 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
15863 // Prepare IP either in reg or imm.
15864 if (!UseImmLabel) {
15865 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
15866 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
15867 LabelReg = MRI.createVirtualRegister(PtrRC);
15868 if (Subtarget->is64Bit()) {
15869 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
15873 .addMBB(restoreMBB)
15876 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
15877 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
15878 .addReg(XII->getGlobalBaseReg(MF))
15881 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
15885 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
15887 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
15888 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15889 if (i == X86::AddrDisp)
15890 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
15892 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
15895 MIB.addReg(LabelReg);
15897 MIB.addMBB(restoreMBB);
15898 MIB.setMemRefs(MMOBegin, MMOEnd);
15900 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
15901 .addMBB(restoreMBB);
15903 const X86RegisterInfo *RegInfo =
15904 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15905 MIB.addRegMask(RegInfo->getNoPreservedMask());
15906 thisMBB->addSuccessor(mainMBB);
15907 thisMBB->addSuccessor(restoreMBB);
15911 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
15912 mainMBB->addSuccessor(sinkMBB);
15915 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15916 TII->get(X86::PHI), DstReg)
15917 .addReg(mainDstReg).addMBB(mainMBB)
15918 .addReg(restoreDstReg).addMBB(restoreMBB);
15921 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
15922 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
15923 restoreMBB->addSuccessor(sinkMBB);
15925 MI->eraseFromParent();
15929 MachineBasicBlock *
15930 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
15931 MachineBasicBlock *MBB) const {
15932 DebugLoc DL = MI->getDebugLoc();
15933 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15935 MachineFunction *MF = MBB->getParent();
15936 MachineRegisterInfo &MRI = MF->getRegInfo();
15938 // Memory Reference
15939 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15940 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15942 MVT PVT = getPointerTy();
15943 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15944 "Invalid Pointer Size!");
15946 const TargetRegisterClass *RC =
15947 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
15948 unsigned Tmp = MRI.createVirtualRegister(RC);
15949 // Since FP is only updated here but NOT referenced, it's treated as GPR.
15950 const X86RegisterInfo *RegInfo =
15951 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15952 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
15953 unsigned SP = RegInfo->getStackRegister();
15955 MachineInstrBuilder MIB;
15957 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15958 const int64_t SPOffset = 2 * PVT.getStoreSize();
15960 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
15961 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
15964 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
15965 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
15966 MIB.addOperand(MI->getOperand(i));
15967 MIB.setMemRefs(MMOBegin, MMOEnd);
15969 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
15970 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15971 if (i == X86::AddrDisp)
15972 MIB.addDisp(MI->getOperand(i), LabelOffset);
15974 MIB.addOperand(MI->getOperand(i));
15976 MIB.setMemRefs(MMOBegin, MMOEnd);
15978 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
15979 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15980 if (i == X86::AddrDisp)
15981 MIB.addDisp(MI->getOperand(i), SPOffset);
15983 MIB.addOperand(MI->getOperand(i));
15985 MIB.setMemRefs(MMOBegin, MMOEnd);
15987 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
15989 MI->eraseFromParent();
15993 // Replace 213-type (isel default) FMA3 instructions with 231-type for
15994 // accumulator loops. Writing back to the accumulator allows the coalescer
15995 // to remove extra copies in the loop.
15996 MachineBasicBlock *
15997 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
15998 MachineBasicBlock *MBB) const {
15999 MachineOperand &AddendOp = MI->getOperand(3);
16001 // Bail out early if the addend isn't a register - we can't switch these.
16002 if (!AddendOp.isReg())
16005 MachineFunction &MF = *MBB->getParent();
16006 MachineRegisterInfo &MRI = MF.getRegInfo();
16008 // Check whether the addend is defined by a PHI:
16009 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
16010 MachineInstr &AddendDef = *MRI.def_begin(AddendOp.getReg());
16011 if (!AddendDef.isPHI())
16014 // Look for the following pattern:
16016 // %addend = phi [%entry, 0], [%loop, %result]
16018 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
16022 // %addend = phi [%entry, 0], [%loop, %result]
16024 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
16026 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
16027 assert(AddendDef.getOperand(i).isReg());
16028 MachineOperand PHISrcOp = AddendDef.getOperand(i);
16029 MachineInstr &PHISrcInst = *MRI.def_begin(PHISrcOp.getReg());
16030 if (&PHISrcInst == MI) {
16031 // Found a matching instruction.
16032 unsigned NewFMAOpc = 0;
16033 switch (MI->getOpcode()) {
16034 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
16035 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
16036 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
16037 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
16038 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
16039 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
16040 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
16041 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
16042 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
16043 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
16044 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
16045 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
16046 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
16047 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
16048 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
16049 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
16050 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
16051 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
16052 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
16053 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
16054 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
16055 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
16056 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
16057 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
16058 default: llvm_unreachable("Unrecognized FMA variant.");
16061 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
16062 MachineInstrBuilder MIB =
16063 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
16064 .addOperand(MI->getOperand(0))
16065 .addOperand(MI->getOperand(3))
16066 .addOperand(MI->getOperand(2))
16067 .addOperand(MI->getOperand(1));
16068 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
16069 MI->eraseFromParent();
16076 MachineBasicBlock *
16077 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
16078 MachineBasicBlock *BB) const {
16079 switch (MI->getOpcode()) {
16080 default: llvm_unreachable("Unexpected instr type to insert");
16081 case X86::TAILJMPd64:
16082 case X86::TAILJMPr64:
16083 case X86::TAILJMPm64:
16084 llvm_unreachable("TAILJMP64 would not be touched here.");
16085 case X86::TCRETURNdi64:
16086 case X86::TCRETURNri64:
16087 case X86::TCRETURNmi64:
16089 case X86::WIN_ALLOCA:
16090 return EmitLoweredWinAlloca(MI, BB);
16091 case X86::SEG_ALLOCA_32:
16092 return EmitLoweredSegAlloca(MI, BB, false);
16093 case X86::SEG_ALLOCA_64:
16094 return EmitLoweredSegAlloca(MI, BB, true);
16095 case X86::TLSCall_32:
16096 case X86::TLSCall_64:
16097 return EmitLoweredTLSCall(MI, BB);
16098 case X86::CMOV_GR8:
16099 case X86::CMOV_FR32:
16100 case X86::CMOV_FR64:
16101 case X86::CMOV_V4F32:
16102 case X86::CMOV_V2F64:
16103 case X86::CMOV_V2I64:
16104 case X86::CMOV_V8F32:
16105 case X86::CMOV_V4F64:
16106 case X86::CMOV_V4I64:
16107 case X86::CMOV_V16F32:
16108 case X86::CMOV_V8F64:
16109 case X86::CMOV_V8I64:
16110 case X86::CMOV_GR16:
16111 case X86::CMOV_GR32:
16112 case X86::CMOV_RFP32:
16113 case X86::CMOV_RFP64:
16114 case X86::CMOV_RFP80:
16115 return EmitLoweredSelect(MI, BB);
16117 case X86::FP32_TO_INT16_IN_MEM:
16118 case X86::FP32_TO_INT32_IN_MEM:
16119 case X86::FP32_TO_INT64_IN_MEM:
16120 case X86::FP64_TO_INT16_IN_MEM:
16121 case X86::FP64_TO_INT32_IN_MEM:
16122 case X86::FP64_TO_INT64_IN_MEM:
16123 case X86::FP80_TO_INT16_IN_MEM:
16124 case X86::FP80_TO_INT32_IN_MEM:
16125 case X86::FP80_TO_INT64_IN_MEM: {
16126 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
16127 DebugLoc DL = MI->getDebugLoc();
16129 // Change the floating point control register to use "round towards zero"
16130 // mode when truncating to an integer value.
16131 MachineFunction *F = BB->getParent();
16132 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
16133 addFrameReference(BuildMI(*BB, MI, DL,
16134 TII->get(X86::FNSTCW16m)), CWFrameIdx);
16136 // Load the old value of the high byte of the control word...
16138 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
16139 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
16142 // Set the high part to be round to zero...
16143 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
16146 // Reload the modified control word now...
16147 addFrameReference(BuildMI(*BB, MI, DL,
16148 TII->get(X86::FLDCW16m)), CWFrameIdx);
16150 // Restore the memory image of control word to original value
16151 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
16154 // Get the X86 opcode to use.
16156 switch (MI->getOpcode()) {
16157 default: llvm_unreachable("illegal opcode!");
16158 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
16159 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
16160 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
16161 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
16162 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
16163 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
16164 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
16165 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
16166 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
16170 MachineOperand &Op = MI->getOperand(0);
16172 AM.BaseType = X86AddressMode::RegBase;
16173 AM.Base.Reg = Op.getReg();
16175 AM.BaseType = X86AddressMode::FrameIndexBase;
16176 AM.Base.FrameIndex = Op.getIndex();
16178 Op = MI->getOperand(1);
16180 AM.Scale = Op.getImm();
16181 Op = MI->getOperand(2);
16183 AM.IndexReg = Op.getImm();
16184 Op = MI->getOperand(3);
16185 if (Op.isGlobal()) {
16186 AM.GV = Op.getGlobal();
16188 AM.Disp = Op.getImm();
16190 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
16191 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
16193 // Reload the original control word now.
16194 addFrameReference(BuildMI(*BB, MI, DL,
16195 TII->get(X86::FLDCW16m)), CWFrameIdx);
16197 MI->eraseFromParent(); // The pseudo instruction is gone now.
16200 // String/text processing lowering.
16201 case X86::PCMPISTRM128REG:
16202 case X86::VPCMPISTRM128REG:
16203 case X86::PCMPISTRM128MEM:
16204 case X86::VPCMPISTRM128MEM:
16205 case X86::PCMPESTRM128REG:
16206 case X86::VPCMPESTRM128REG:
16207 case X86::PCMPESTRM128MEM:
16208 case X86::VPCMPESTRM128MEM:
16209 assert(Subtarget->hasSSE42() &&
16210 "Target must have SSE4.2 or AVX features enabled");
16211 return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo());
16213 // String/text processing lowering.
16214 case X86::PCMPISTRIREG:
16215 case X86::VPCMPISTRIREG:
16216 case X86::PCMPISTRIMEM:
16217 case X86::VPCMPISTRIMEM:
16218 case X86::PCMPESTRIREG:
16219 case X86::VPCMPESTRIREG:
16220 case X86::PCMPESTRIMEM:
16221 case X86::VPCMPESTRIMEM:
16222 assert(Subtarget->hasSSE42() &&
16223 "Target must have SSE4.2 or AVX features enabled");
16224 return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo());
16226 // Thread synchronization.
16228 return EmitMonitor(MI, BB, getTargetMachine().getInstrInfo(), Subtarget);
16232 return EmitXBegin(MI, BB, getTargetMachine().getInstrInfo());
16234 // Atomic Lowering.
16235 case X86::ATOMAND8:
16236 case X86::ATOMAND16:
16237 case X86::ATOMAND32:
16238 case X86::ATOMAND64:
16241 case X86::ATOMOR16:
16242 case X86::ATOMOR32:
16243 case X86::ATOMOR64:
16245 case X86::ATOMXOR16:
16246 case X86::ATOMXOR8:
16247 case X86::ATOMXOR32:
16248 case X86::ATOMXOR64:
16250 case X86::ATOMNAND8:
16251 case X86::ATOMNAND16:
16252 case X86::ATOMNAND32:
16253 case X86::ATOMNAND64:
16255 case X86::ATOMMAX8:
16256 case X86::ATOMMAX16:
16257 case X86::ATOMMAX32:
16258 case X86::ATOMMAX64:
16260 case X86::ATOMMIN8:
16261 case X86::ATOMMIN16:
16262 case X86::ATOMMIN32:
16263 case X86::ATOMMIN64:
16265 case X86::ATOMUMAX8:
16266 case X86::ATOMUMAX16:
16267 case X86::ATOMUMAX32:
16268 case X86::ATOMUMAX64:
16270 case X86::ATOMUMIN8:
16271 case X86::ATOMUMIN16:
16272 case X86::ATOMUMIN32:
16273 case X86::ATOMUMIN64:
16274 return EmitAtomicLoadArith(MI, BB);
16276 // This group does 64-bit operations on a 32-bit host.
16277 case X86::ATOMAND6432:
16278 case X86::ATOMOR6432:
16279 case X86::ATOMXOR6432:
16280 case X86::ATOMNAND6432:
16281 case X86::ATOMADD6432:
16282 case X86::ATOMSUB6432:
16283 case X86::ATOMMAX6432:
16284 case X86::ATOMMIN6432:
16285 case X86::ATOMUMAX6432:
16286 case X86::ATOMUMIN6432:
16287 case X86::ATOMSWAP6432:
16288 return EmitAtomicLoadArith6432(MI, BB);
16290 case X86::VASTART_SAVE_XMM_REGS:
16291 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
16293 case X86::VAARG_64:
16294 return EmitVAARG64WithCustomInserter(MI, BB);
16296 case X86::EH_SjLj_SetJmp32:
16297 case X86::EH_SjLj_SetJmp64:
16298 return emitEHSjLjSetJmp(MI, BB);
16300 case X86::EH_SjLj_LongJmp32:
16301 case X86::EH_SjLj_LongJmp64:
16302 return emitEHSjLjLongJmp(MI, BB);
16304 case TargetOpcode::STACKMAP:
16305 case TargetOpcode::PATCHPOINT:
16306 return emitPatchPoint(MI, BB);
16308 case X86::VFMADDPDr213r:
16309 case X86::VFMADDPSr213r:
16310 case X86::VFMADDSDr213r:
16311 case X86::VFMADDSSr213r:
16312 case X86::VFMSUBPDr213r:
16313 case X86::VFMSUBPSr213r:
16314 case X86::VFMSUBSDr213r:
16315 case X86::VFMSUBSSr213r:
16316 case X86::VFNMADDPDr213r:
16317 case X86::VFNMADDPSr213r:
16318 case X86::VFNMADDSDr213r:
16319 case X86::VFNMADDSSr213r:
16320 case X86::VFNMSUBPDr213r:
16321 case X86::VFNMSUBPSr213r:
16322 case X86::VFNMSUBSDr213r:
16323 case X86::VFNMSUBSSr213r:
16324 case X86::VFMADDPDr213rY:
16325 case X86::VFMADDPSr213rY:
16326 case X86::VFMSUBPDr213rY:
16327 case X86::VFMSUBPSr213rY:
16328 case X86::VFNMADDPDr213rY:
16329 case X86::VFNMADDPSr213rY:
16330 case X86::VFNMSUBPDr213rY:
16331 case X86::VFNMSUBPSr213rY:
16332 return emitFMA3Instr(MI, BB);
16336 //===----------------------------------------------------------------------===//
16337 // X86 Optimization Hooks
16338 //===----------------------------------------------------------------------===//
16340 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
16343 const SelectionDAG &DAG,
16344 unsigned Depth) const {
16345 unsigned BitWidth = KnownZero.getBitWidth();
16346 unsigned Opc = Op.getOpcode();
16347 assert((Opc >= ISD::BUILTIN_OP_END ||
16348 Opc == ISD::INTRINSIC_WO_CHAIN ||
16349 Opc == ISD::INTRINSIC_W_CHAIN ||
16350 Opc == ISD::INTRINSIC_VOID) &&
16351 "Should use MaskedValueIsZero if you don't know whether Op"
16352 " is a target node!");
16354 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
16368 // These nodes' second result is a boolean.
16369 if (Op.getResNo() == 0)
16372 case X86ISD::SETCC:
16373 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
16375 case ISD::INTRINSIC_WO_CHAIN: {
16376 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16377 unsigned NumLoBits = 0;
16380 case Intrinsic::x86_sse_movmsk_ps:
16381 case Intrinsic::x86_avx_movmsk_ps_256:
16382 case Intrinsic::x86_sse2_movmsk_pd:
16383 case Intrinsic::x86_avx_movmsk_pd_256:
16384 case Intrinsic::x86_mmx_pmovmskb:
16385 case Intrinsic::x86_sse2_pmovmskb_128:
16386 case Intrinsic::x86_avx2_pmovmskb: {
16387 // High bits of movmskp{s|d}, pmovmskb are known zero.
16389 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16390 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
16391 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
16392 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
16393 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
16394 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
16395 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
16396 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
16398 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
16407 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
16408 unsigned Depth) const {
16409 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
16410 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
16411 return Op.getValueType().getScalarType().getSizeInBits();
16417 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
16418 /// node is a GlobalAddress + offset.
16419 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
16420 const GlobalValue* &GA,
16421 int64_t &Offset) const {
16422 if (N->getOpcode() == X86ISD::Wrapper) {
16423 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
16424 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
16425 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
16429 return TargetLowering::isGAPlusOffset(N, GA, Offset);
16432 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
16433 /// same as extracting the high 128-bit part of 256-bit vector and then
16434 /// inserting the result into the low part of a new 256-bit vector
16435 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
16436 EVT VT = SVOp->getValueType(0);
16437 unsigned NumElems = VT.getVectorNumElements();
16439 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
16440 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
16441 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
16442 SVOp->getMaskElt(j) >= 0)
16448 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
16449 /// same as extracting the low 128-bit part of 256-bit vector and then
16450 /// inserting the result into the high part of a new 256-bit vector
16451 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
16452 EVT VT = SVOp->getValueType(0);
16453 unsigned NumElems = VT.getVectorNumElements();
16455 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
16456 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
16457 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
16458 SVOp->getMaskElt(j) >= 0)
16464 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
16465 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
16466 TargetLowering::DAGCombinerInfo &DCI,
16467 const X86Subtarget* Subtarget) {
16469 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
16470 SDValue V1 = SVOp->getOperand(0);
16471 SDValue V2 = SVOp->getOperand(1);
16472 EVT VT = SVOp->getValueType(0);
16473 unsigned NumElems = VT.getVectorNumElements();
16475 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
16476 V2.getOpcode() == ISD::CONCAT_VECTORS) {
16480 // V UNDEF BUILD_VECTOR UNDEF
16482 // CONCAT_VECTOR CONCAT_VECTOR
16485 // RESULT: V + zero extended
16487 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
16488 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
16489 V1.getOperand(1).getOpcode() != ISD::UNDEF)
16492 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
16495 // To match the shuffle mask, the first half of the mask should
16496 // be exactly the first vector, and all the rest a splat with the
16497 // first element of the second one.
16498 for (unsigned i = 0; i != NumElems/2; ++i)
16499 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
16500 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
16503 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
16504 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
16505 if (Ld->hasNUsesOfValue(1, 0)) {
16506 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
16507 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
16509 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
16510 array_lengthof(Ops),
16512 Ld->getPointerInfo(),
16513 Ld->getAlignment(),
16514 false/*isVolatile*/, true/*ReadMem*/,
16515 false/*WriteMem*/);
16517 // Make sure the newly-created LOAD is in the same position as Ld in
16518 // terms of dependency. We create a TokenFactor for Ld and ResNode,
16519 // and update uses of Ld's output chain to use the TokenFactor.
16520 if (Ld->hasAnyUseOfValue(1)) {
16521 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
16522 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
16523 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
16524 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
16525 SDValue(ResNode.getNode(), 1));
16528 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
16532 // Emit a zeroed vector and insert the desired subvector on its
16534 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16535 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
16536 return DCI.CombineTo(N, InsV);
16539 //===--------------------------------------------------------------------===//
16540 // Combine some shuffles into subvector extracts and inserts:
16543 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
16544 if (isShuffleHigh128VectorInsertLow(SVOp)) {
16545 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
16546 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
16547 return DCI.CombineTo(N, InsV);
16550 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
16551 if (isShuffleLow128VectorInsertHigh(SVOp)) {
16552 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
16553 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
16554 return DCI.CombineTo(N, InsV);
16560 /// PerformShuffleCombine - Performs several different shuffle combines.
16561 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
16562 TargetLowering::DAGCombinerInfo &DCI,
16563 const X86Subtarget *Subtarget) {
16565 EVT VT = N->getValueType(0);
16567 // Don't create instructions with illegal types after legalize types has run.
16568 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16569 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
16572 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
16573 if (Subtarget->hasFp256() && VT.is256BitVector() &&
16574 N->getOpcode() == ISD::VECTOR_SHUFFLE)
16575 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
16577 // Only handle 128 wide vector from here on.
16578 if (!VT.is128BitVector())
16581 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
16582 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
16583 // consecutive, non-overlapping, and in the right order.
16584 SmallVector<SDValue, 16> Elts;
16585 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
16586 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
16588 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
16591 /// PerformTruncateCombine - Converts truncate operation to
16592 /// a sequence of vector shuffle operations.
16593 /// It is possible when we truncate 256-bit vector to 128-bit vector
16594 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
16595 TargetLowering::DAGCombinerInfo &DCI,
16596 const X86Subtarget *Subtarget) {
16600 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
16601 /// specific shuffle of a load can be folded into a single element load.
16602 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
16603 /// shuffles have been customed lowered so we need to handle those here.
16604 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
16605 TargetLowering::DAGCombinerInfo &DCI) {
16606 if (DCI.isBeforeLegalizeOps())
16609 SDValue InVec = N->getOperand(0);
16610 SDValue EltNo = N->getOperand(1);
16612 if (!isa<ConstantSDNode>(EltNo))
16615 EVT VT = InVec.getValueType();
16617 bool HasShuffleIntoBitcast = false;
16618 if (InVec.getOpcode() == ISD::BITCAST) {
16619 // Don't duplicate a load with other uses.
16620 if (!InVec.hasOneUse())
16622 EVT BCVT = InVec.getOperand(0).getValueType();
16623 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
16625 InVec = InVec.getOperand(0);
16626 HasShuffleIntoBitcast = true;
16629 if (!isTargetShuffle(InVec.getOpcode()))
16632 // Don't duplicate a load with other uses.
16633 if (!InVec.hasOneUse())
16636 SmallVector<int, 16> ShuffleMask;
16638 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
16642 // Select the input vector, guarding against out of range extract vector.
16643 unsigned NumElems = VT.getVectorNumElements();
16644 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
16645 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
16646 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
16647 : InVec.getOperand(1);
16649 // If inputs to shuffle are the same for both ops, then allow 2 uses
16650 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
16652 if (LdNode.getOpcode() == ISD::BITCAST) {
16653 // Don't duplicate a load with other uses.
16654 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
16657 AllowedUses = 1; // only allow 1 load use if we have a bitcast
16658 LdNode = LdNode.getOperand(0);
16661 if (!ISD::isNormalLoad(LdNode.getNode()))
16664 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
16666 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
16669 if (HasShuffleIntoBitcast) {
16670 // If there's a bitcast before the shuffle, check if the load type and
16671 // alignment is valid.
16672 unsigned Align = LN0->getAlignment();
16673 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16674 unsigned NewAlign = TLI.getDataLayout()->
16675 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
16677 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
16681 // All checks match so transform back to vector_shuffle so that DAG combiner
16682 // can finish the job
16685 // Create shuffle node taking into account the case that its a unary shuffle
16686 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
16687 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
16688 InVec.getOperand(0), Shuffle,
16690 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
16691 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
16695 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
16696 /// generation and convert it from being a bunch of shuffles and extracts
16697 /// to a simple store and scalar loads to extract the elements.
16698 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
16699 TargetLowering::DAGCombinerInfo &DCI) {
16700 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
16701 if (NewOp.getNode())
16704 SDValue InputVector = N->getOperand(0);
16706 // Detect whether we are trying to convert from mmx to i32 and the bitcast
16707 // from mmx to v2i32 has a single usage.
16708 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
16709 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
16710 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
16711 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
16712 N->getValueType(0),
16713 InputVector.getNode()->getOperand(0));
16715 // Only operate on vectors of 4 elements, where the alternative shuffling
16716 // gets to be more expensive.
16717 if (InputVector.getValueType() != MVT::v4i32)
16720 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
16721 // single use which is a sign-extend or zero-extend, and all elements are
16723 SmallVector<SDNode *, 4> Uses;
16724 unsigned ExtractedElements = 0;
16725 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
16726 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
16727 if (UI.getUse().getResNo() != InputVector.getResNo())
16730 SDNode *Extract = *UI;
16731 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
16734 if (Extract->getValueType(0) != MVT::i32)
16736 if (!Extract->hasOneUse())
16738 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
16739 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
16741 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
16744 // Record which element was extracted.
16745 ExtractedElements |=
16746 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
16748 Uses.push_back(Extract);
16751 // If not all the elements were used, this may not be worthwhile.
16752 if (ExtractedElements != 15)
16755 // Ok, we've now decided to do the transformation.
16756 SDLoc dl(InputVector);
16758 // Store the value to a temporary stack slot.
16759 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
16760 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
16761 MachinePointerInfo(), false, false, 0);
16763 // Replace each use (extract) with a load of the appropriate element.
16764 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
16765 UE = Uses.end(); UI != UE; ++UI) {
16766 SDNode *Extract = *UI;
16768 // cOMpute the element's address.
16769 SDValue Idx = Extract->getOperand(1);
16771 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
16772 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
16773 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16774 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
16776 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
16777 StackPtr, OffsetVal);
16779 // Load the scalar.
16780 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
16781 ScalarAddr, MachinePointerInfo(),
16782 false, false, false, 0);
16784 // Replace the exact with the load.
16785 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
16788 // The replacement was made in place; don't return anything.
16792 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
16793 static std::pair<unsigned, bool>
16794 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
16795 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
16796 if (!VT.isVector())
16797 return std::make_pair(0, false);
16799 bool NeedSplit = false;
16800 switch (VT.getSimpleVT().SimpleTy) {
16801 default: return std::make_pair(0, false);
16805 if (!Subtarget->hasAVX2())
16807 if (!Subtarget->hasAVX())
16808 return std::make_pair(0, false);
16813 if (!Subtarget->hasSSE2())
16814 return std::make_pair(0, false);
16817 // SSE2 has only a small subset of the operations.
16818 bool hasUnsigned = Subtarget->hasSSE41() ||
16819 (Subtarget->hasSSE2() && VT == MVT::v16i8);
16820 bool hasSigned = Subtarget->hasSSE41() ||
16821 (Subtarget->hasSSE2() && VT == MVT::v8i16);
16823 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16826 // Check for x CC y ? x : y.
16827 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16828 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16833 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
16836 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
16839 Opc = hasSigned ? X86ISD::SMIN : 0; break;
16842 Opc = hasSigned ? X86ISD::SMAX : 0; break;
16844 // Check for x CC y ? y : x -- a min/max with reversed arms.
16845 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16846 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16851 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
16854 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
16857 Opc = hasSigned ? X86ISD::SMAX : 0; break;
16860 Opc = hasSigned ? X86ISD::SMIN : 0; break;
16864 return std::make_pair(Opc, NeedSplit);
16867 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
16869 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
16870 TargetLowering::DAGCombinerInfo &DCI,
16871 const X86Subtarget *Subtarget) {
16873 SDValue Cond = N->getOperand(0);
16874 // Get the LHS/RHS of the select.
16875 SDValue LHS = N->getOperand(1);
16876 SDValue RHS = N->getOperand(2);
16877 EVT VT = LHS.getValueType();
16878 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16880 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
16881 // instructions match the semantics of the common C idiom x<y?x:y but not
16882 // x<=y?x:y, because of how they handle negative zero (which can be
16883 // ignored in unsafe-math mode).
16884 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
16885 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
16886 (Subtarget->hasSSE2() ||
16887 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
16888 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16890 unsigned Opcode = 0;
16891 // Check for x CC y ? x : y.
16892 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16893 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16897 // Converting this to a min would handle NaNs incorrectly, and swapping
16898 // the operands would cause it to handle comparisons between positive
16899 // and negative zero incorrectly.
16900 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16901 if (!DAG.getTarget().Options.UnsafeFPMath &&
16902 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16904 std::swap(LHS, RHS);
16906 Opcode = X86ISD::FMIN;
16909 // Converting this to a min would handle comparisons between positive
16910 // and negative zero incorrectly.
16911 if (!DAG.getTarget().Options.UnsafeFPMath &&
16912 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16914 Opcode = X86ISD::FMIN;
16917 // Converting this to a min would handle both negative zeros and NaNs
16918 // incorrectly, but we can swap the operands to fix both.
16919 std::swap(LHS, RHS);
16923 Opcode = X86ISD::FMIN;
16927 // Converting this to a max would handle comparisons between positive
16928 // and negative zero incorrectly.
16929 if (!DAG.getTarget().Options.UnsafeFPMath &&
16930 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16932 Opcode = X86ISD::FMAX;
16935 // Converting this to a max would handle NaNs incorrectly, and swapping
16936 // the operands would cause it to handle comparisons between positive
16937 // and negative zero incorrectly.
16938 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16939 if (!DAG.getTarget().Options.UnsafeFPMath &&
16940 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16942 std::swap(LHS, RHS);
16944 Opcode = X86ISD::FMAX;
16947 // Converting this to a max would handle both negative zeros and NaNs
16948 // incorrectly, but we can swap the operands to fix both.
16949 std::swap(LHS, RHS);
16953 Opcode = X86ISD::FMAX;
16956 // Check for x CC y ? y : x -- a min/max with reversed arms.
16957 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16958 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16962 // Converting this to a min would handle comparisons between positive
16963 // and negative zero incorrectly, and swapping the operands would
16964 // cause it to handle NaNs incorrectly.
16965 if (!DAG.getTarget().Options.UnsafeFPMath &&
16966 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
16967 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16969 std::swap(LHS, RHS);
16971 Opcode = X86ISD::FMIN;
16974 // Converting this to a min would handle NaNs incorrectly.
16975 if (!DAG.getTarget().Options.UnsafeFPMath &&
16976 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
16978 Opcode = X86ISD::FMIN;
16981 // Converting this to a min would handle both negative zeros and NaNs
16982 // incorrectly, but we can swap the operands to fix both.
16983 std::swap(LHS, RHS);
16987 Opcode = X86ISD::FMIN;
16991 // Converting this to a max would handle NaNs incorrectly.
16992 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16994 Opcode = X86ISD::FMAX;
16997 // Converting this to a max would handle comparisons between positive
16998 // and negative zero incorrectly, and swapping the operands would
16999 // cause it to handle NaNs incorrectly.
17000 if (!DAG.getTarget().Options.UnsafeFPMath &&
17001 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
17002 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
17004 std::swap(LHS, RHS);
17006 Opcode = X86ISD::FMAX;
17009 // Converting this to a max would handle both negative zeros and NaNs
17010 // incorrectly, but we can swap the operands to fix both.
17011 std::swap(LHS, RHS);
17015 Opcode = X86ISD::FMAX;
17021 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
17024 EVT CondVT = Cond.getValueType();
17025 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
17026 CondVT.getVectorElementType() == MVT::i1) {
17027 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
17028 // lowering on AVX-512. In this case we convert it to
17029 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
17030 // The same situation for all 128 and 256-bit vectors of i8 and i16
17031 EVT OpVT = LHS.getValueType();
17032 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
17033 (OpVT.getVectorElementType() == MVT::i8 ||
17034 OpVT.getVectorElementType() == MVT::i16)) {
17035 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
17036 DCI.AddToWorklist(Cond.getNode());
17037 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
17040 // If this is a select between two integer constants, try to do some
17042 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
17043 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
17044 // Don't do this for crazy integer types.
17045 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
17046 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
17047 // so that TrueC (the true value) is larger than FalseC.
17048 bool NeedsCondInvert = false;
17050 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
17051 // Efficiently invertible.
17052 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
17053 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
17054 isa<ConstantSDNode>(Cond.getOperand(1))))) {
17055 NeedsCondInvert = true;
17056 std::swap(TrueC, FalseC);
17059 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
17060 if (FalseC->getAPIntValue() == 0 &&
17061 TrueC->getAPIntValue().isPowerOf2()) {
17062 if (NeedsCondInvert) // Invert the condition if needed.
17063 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
17064 DAG.getConstant(1, Cond.getValueType()));
17066 // Zero extend the condition if needed.
17067 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
17069 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
17070 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
17071 DAG.getConstant(ShAmt, MVT::i8));
17074 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
17075 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
17076 if (NeedsCondInvert) // Invert the condition if needed.
17077 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
17078 DAG.getConstant(1, Cond.getValueType()));
17080 // Zero extend the condition if needed.
17081 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
17082 FalseC->getValueType(0), Cond);
17083 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17084 SDValue(FalseC, 0));
17087 // Optimize cases that will turn into an LEA instruction. This requires
17088 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
17089 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
17090 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
17091 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
17093 bool isFastMultiplier = false;
17095 switch ((unsigned char)Diff) {
17097 case 1: // result = add base, cond
17098 case 2: // result = lea base( , cond*2)
17099 case 3: // result = lea base(cond, cond*2)
17100 case 4: // result = lea base( , cond*4)
17101 case 5: // result = lea base(cond, cond*4)
17102 case 8: // result = lea base( , cond*8)
17103 case 9: // result = lea base(cond, cond*8)
17104 isFastMultiplier = true;
17109 if (isFastMultiplier) {
17110 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
17111 if (NeedsCondInvert) // Invert the condition if needed.
17112 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
17113 DAG.getConstant(1, Cond.getValueType()));
17115 // Zero extend the condition if needed.
17116 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
17118 // Scale the condition by the difference.
17120 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
17121 DAG.getConstant(Diff, Cond.getValueType()));
17123 // Add the base if non-zero.
17124 if (FalseC->getAPIntValue() != 0)
17125 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17126 SDValue(FalseC, 0));
17133 // Canonicalize max and min:
17134 // (x > y) ? x : y -> (x >= y) ? x : y
17135 // (x < y) ? x : y -> (x <= y) ? x : y
17136 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
17137 // the need for an extra compare
17138 // against zero. e.g.
17139 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
17141 // testl %edi, %edi
17143 // cmovgl %edi, %eax
17147 // cmovsl %eax, %edi
17148 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
17149 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
17150 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
17151 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
17156 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
17157 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
17158 Cond.getOperand(0), Cond.getOperand(1), NewCC);
17159 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
17164 // Early exit check
17165 if (!TLI.isTypeLegal(VT))
17168 // Match VSELECTs into subs with unsigned saturation.
17169 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
17170 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
17171 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
17172 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
17173 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
17175 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
17176 // left side invert the predicate to simplify logic below.
17178 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
17180 CC = ISD::getSetCCInverse(CC, true);
17181 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
17185 if (Other.getNode() && Other->getNumOperands() == 2 &&
17186 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
17187 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
17188 SDValue CondRHS = Cond->getOperand(1);
17190 // Look for a general sub with unsigned saturation first.
17191 // x >= y ? x-y : 0 --> subus x, y
17192 // x > y ? x-y : 0 --> subus x, y
17193 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
17194 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
17195 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
17197 // If the RHS is a constant we have to reverse the const canonicalization.
17198 // x > C-1 ? x+-C : 0 --> subus x, C
17199 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
17200 isSplatVector(CondRHS.getNode()) && isSplatVector(OpRHS.getNode())) {
17201 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
17202 if (CondRHS.getConstantOperandVal(0) == -A-1)
17203 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS,
17204 DAG.getConstant(-A, VT));
17207 // Another special case: If C was a sign bit, the sub has been
17208 // canonicalized into a xor.
17209 // FIXME: Would it be better to use ComputeMaskedBits to determine whether
17210 // it's safe to decanonicalize the xor?
17211 // x s< 0 ? x^C : 0 --> subus x, C
17212 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
17213 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
17214 isSplatVector(OpRHS.getNode())) {
17215 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
17217 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
17222 // Try to match a min/max vector operation.
17223 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
17224 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
17225 unsigned Opc = ret.first;
17226 bool NeedSplit = ret.second;
17228 if (Opc && NeedSplit) {
17229 unsigned NumElems = VT.getVectorNumElements();
17230 // Extract the LHS vectors
17231 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
17232 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
17234 // Extract the RHS vectors
17235 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
17236 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
17238 // Create min/max for each subvector
17239 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
17240 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
17242 // Merge the result
17243 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
17245 return DAG.getNode(Opc, DL, VT, LHS, RHS);
17248 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
17249 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
17250 // Check if SETCC has already been promoted
17251 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
17252 // Check that condition value type matches vselect operand type
17255 assert(Cond.getValueType().isVector() &&
17256 "vector select expects a vector selector!");
17258 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
17259 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
17261 if (!TValIsAllOnes && !FValIsAllZeros) {
17262 // Try invert the condition if true value is not all 1s and false value
17264 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
17265 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
17267 if (TValIsAllZeros || FValIsAllOnes) {
17268 SDValue CC = Cond.getOperand(2);
17269 ISD::CondCode NewCC =
17270 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
17271 Cond.getOperand(0).getValueType().isInteger());
17272 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
17273 std::swap(LHS, RHS);
17274 TValIsAllOnes = FValIsAllOnes;
17275 FValIsAllZeros = TValIsAllZeros;
17279 if (TValIsAllOnes || FValIsAllZeros) {
17282 if (TValIsAllOnes && FValIsAllZeros)
17284 else if (TValIsAllOnes)
17285 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
17286 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
17287 else if (FValIsAllZeros)
17288 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
17289 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
17291 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
17295 // Try to fold this VSELECT into a MOVSS/MOVSD
17296 if (N->getOpcode() == ISD::VSELECT &&
17297 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
17298 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
17299 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
17300 bool CanFold = false;
17301 unsigned NumElems = Cond.getNumOperands();
17305 if (isZero(Cond.getOperand(0))) {
17308 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
17309 // fold (vselect <0,-1> -> (movsd A, B)
17310 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
17311 CanFold = isAllOnes(Cond.getOperand(i));
17312 } else if (isAllOnes(Cond.getOperand(0))) {
17316 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
17317 // fold (vselect <-1,0> -> (movsd B, A)
17318 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
17319 CanFold = isZero(Cond.getOperand(i));
17323 if (VT == MVT::v4i32 || VT == MVT::v4f32)
17324 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
17325 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
17328 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
17329 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
17330 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
17331 // (v2i64 (bitcast B)))))
17333 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
17334 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
17335 // (v2f64 (bitcast B)))))
17337 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
17338 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
17339 // (v2i64 (bitcast A)))))
17341 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
17342 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
17343 // (v2f64 (bitcast A)))))
17345 CanFold = (isZero(Cond.getOperand(0)) &&
17346 isZero(Cond.getOperand(1)) &&
17347 isAllOnes(Cond.getOperand(2)) &&
17348 isAllOnes(Cond.getOperand(3)));
17350 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
17351 isAllOnes(Cond.getOperand(1)) &&
17352 isZero(Cond.getOperand(2)) &&
17353 isZero(Cond.getOperand(3))) {
17355 std::swap(LHS, RHS);
17359 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
17360 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
17361 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
17362 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
17364 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
17370 // If we know that this node is legal then we know that it is going to be
17371 // matched by one of the SSE/AVX BLEND instructions. These instructions only
17372 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
17373 // to simplify previous instructions.
17374 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
17375 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
17376 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
17378 // Don't optimize vector selects that map to mask-registers.
17382 // Check all uses of that condition operand to check whether it will be
17383 // consumed by non-BLEND instructions, which may depend on all bits are set
17385 for (SDNode::use_iterator I = Cond->use_begin(),
17386 E = Cond->use_end(); I != E; ++I)
17387 if (I->getOpcode() != ISD::VSELECT)
17388 // TODO: Add other opcodes eventually lowered into BLEND.
17391 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
17392 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
17394 APInt KnownZero, KnownOne;
17395 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
17396 DCI.isBeforeLegalizeOps());
17397 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
17398 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
17399 DCI.CommitTargetLoweringOpt(TLO);
17405 // Check whether a boolean test is testing a boolean value generated by
17406 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
17409 // Simplify the following patterns:
17410 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
17411 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
17412 // to (Op EFLAGS Cond)
17414 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
17415 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
17416 // to (Op EFLAGS !Cond)
17418 // where Op could be BRCOND or CMOV.
17420 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
17421 // Quit if not CMP and SUB with its value result used.
17422 if (Cmp.getOpcode() != X86ISD::CMP &&
17423 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
17426 // Quit if not used as a boolean value.
17427 if (CC != X86::COND_E && CC != X86::COND_NE)
17430 // Check CMP operands. One of them should be 0 or 1 and the other should be
17431 // an SetCC or extended from it.
17432 SDValue Op1 = Cmp.getOperand(0);
17433 SDValue Op2 = Cmp.getOperand(1);
17436 const ConstantSDNode* C = 0;
17437 bool needOppositeCond = (CC == X86::COND_E);
17438 bool checkAgainstTrue = false; // Is it a comparison against 1?
17440 if ((C = dyn_cast<ConstantSDNode>(Op1)))
17442 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
17444 else // Quit if all operands are not constants.
17447 if (C->getZExtValue() == 1) {
17448 needOppositeCond = !needOppositeCond;
17449 checkAgainstTrue = true;
17450 } else if (C->getZExtValue() != 0)
17451 // Quit if the constant is neither 0 or 1.
17454 bool truncatedToBoolWithAnd = false;
17455 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
17456 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
17457 SetCC.getOpcode() == ISD::TRUNCATE ||
17458 SetCC.getOpcode() == ISD::AND) {
17459 if (SetCC.getOpcode() == ISD::AND) {
17461 ConstantSDNode *CS;
17462 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
17463 CS->getZExtValue() == 1)
17465 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
17466 CS->getZExtValue() == 1)
17470 SetCC = SetCC.getOperand(OpIdx);
17471 truncatedToBoolWithAnd = true;
17473 SetCC = SetCC.getOperand(0);
17476 switch (SetCC.getOpcode()) {
17477 case X86ISD::SETCC_CARRY:
17478 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
17479 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
17480 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
17481 // truncated to i1 using 'and'.
17482 if (checkAgainstTrue && !truncatedToBoolWithAnd)
17484 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
17485 "Invalid use of SETCC_CARRY!");
17487 case X86ISD::SETCC:
17488 // Set the condition code or opposite one if necessary.
17489 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
17490 if (needOppositeCond)
17491 CC = X86::GetOppositeBranchCondition(CC);
17492 return SetCC.getOperand(1);
17493 case X86ISD::CMOV: {
17494 // Check whether false/true value has canonical one, i.e. 0 or 1.
17495 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
17496 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
17497 // Quit if true value is not a constant.
17500 // Quit if false value is not a constant.
17502 SDValue Op = SetCC.getOperand(0);
17503 // Skip 'zext' or 'trunc' node.
17504 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
17505 Op.getOpcode() == ISD::TRUNCATE)
17506 Op = Op.getOperand(0);
17507 // A special case for rdrand/rdseed, where 0 is set if false cond is
17509 if ((Op.getOpcode() != X86ISD::RDRAND &&
17510 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
17513 // Quit if false value is not the constant 0 or 1.
17514 bool FValIsFalse = true;
17515 if (FVal && FVal->getZExtValue() != 0) {
17516 if (FVal->getZExtValue() != 1)
17518 // If FVal is 1, opposite cond is needed.
17519 needOppositeCond = !needOppositeCond;
17520 FValIsFalse = false;
17522 // Quit if TVal is not the constant opposite of FVal.
17523 if (FValIsFalse && TVal->getZExtValue() != 1)
17525 if (!FValIsFalse && TVal->getZExtValue() != 0)
17527 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
17528 if (needOppositeCond)
17529 CC = X86::GetOppositeBranchCondition(CC);
17530 return SetCC.getOperand(3);
17537 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
17538 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
17539 TargetLowering::DAGCombinerInfo &DCI,
17540 const X86Subtarget *Subtarget) {
17543 // If the flag operand isn't dead, don't touch this CMOV.
17544 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
17547 SDValue FalseOp = N->getOperand(0);
17548 SDValue TrueOp = N->getOperand(1);
17549 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
17550 SDValue Cond = N->getOperand(3);
17552 if (CC == X86::COND_E || CC == X86::COND_NE) {
17553 switch (Cond.getOpcode()) {
17557 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
17558 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
17559 return (CC == X86::COND_E) ? FalseOp : TrueOp;
17565 Flags = checkBoolTestSetCCCombine(Cond, CC);
17566 if (Flags.getNode() &&
17567 // Extra check as FCMOV only supports a subset of X86 cond.
17568 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
17569 SDValue Ops[] = { FalseOp, TrueOp,
17570 DAG.getConstant(CC, MVT::i8), Flags };
17571 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
17572 Ops, array_lengthof(Ops));
17575 // If this is a select between two integer constants, try to do some
17576 // optimizations. Note that the operands are ordered the opposite of SELECT
17578 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
17579 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
17580 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
17581 // larger than FalseC (the false value).
17582 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
17583 CC = X86::GetOppositeBranchCondition(CC);
17584 std::swap(TrueC, FalseC);
17585 std::swap(TrueOp, FalseOp);
17588 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
17589 // This is efficient for any integer data type (including i8/i16) and
17591 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
17592 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17593 DAG.getConstant(CC, MVT::i8), Cond);
17595 // Zero extend the condition if needed.
17596 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
17598 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
17599 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
17600 DAG.getConstant(ShAmt, MVT::i8));
17601 if (N->getNumValues() == 2) // Dead flag value?
17602 return DCI.CombineTo(N, Cond, SDValue());
17606 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
17607 // for any integer data type, including i8/i16.
17608 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
17609 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17610 DAG.getConstant(CC, MVT::i8), Cond);
17612 // Zero extend the condition if needed.
17613 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
17614 FalseC->getValueType(0), Cond);
17615 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17616 SDValue(FalseC, 0));
17618 if (N->getNumValues() == 2) // Dead flag value?
17619 return DCI.CombineTo(N, Cond, SDValue());
17623 // Optimize cases that will turn into an LEA instruction. This requires
17624 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
17625 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
17626 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
17627 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
17629 bool isFastMultiplier = false;
17631 switch ((unsigned char)Diff) {
17633 case 1: // result = add base, cond
17634 case 2: // result = lea base( , cond*2)
17635 case 3: // result = lea base(cond, cond*2)
17636 case 4: // result = lea base( , cond*4)
17637 case 5: // result = lea base(cond, cond*4)
17638 case 8: // result = lea base( , cond*8)
17639 case 9: // result = lea base(cond, cond*8)
17640 isFastMultiplier = true;
17645 if (isFastMultiplier) {
17646 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
17647 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17648 DAG.getConstant(CC, MVT::i8), Cond);
17649 // Zero extend the condition if needed.
17650 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
17652 // Scale the condition by the difference.
17654 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
17655 DAG.getConstant(Diff, Cond.getValueType()));
17657 // Add the base if non-zero.
17658 if (FalseC->getAPIntValue() != 0)
17659 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17660 SDValue(FalseC, 0));
17661 if (N->getNumValues() == 2) // Dead flag value?
17662 return DCI.CombineTo(N, Cond, SDValue());
17669 // Handle these cases:
17670 // (select (x != c), e, c) -> select (x != c), e, x),
17671 // (select (x == c), c, e) -> select (x == c), x, e)
17672 // where the c is an integer constant, and the "select" is the combination
17673 // of CMOV and CMP.
17675 // The rationale for this change is that the conditional-move from a constant
17676 // needs two instructions, however, conditional-move from a register needs
17677 // only one instruction.
17679 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
17680 // some instruction-combining opportunities. This opt needs to be
17681 // postponed as late as possible.
17683 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
17684 // the DCI.xxxx conditions are provided to postpone the optimization as
17685 // late as possible.
17687 ConstantSDNode *CmpAgainst = 0;
17688 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
17689 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
17690 !isa<ConstantSDNode>(Cond.getOperand(0))) {
17692 if (CC == X86::COND_NE &&
17693 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
17694 CC = X86::GetOppositeBranchCondition(CC);
17695 std::swap(TrueOp, FalseOp);
17698 if (CC == X86::COND_E &&
17699 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
17700 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
17701 DAG.getConstant(CC, MVT::i8), Cond };
17702 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops,
17703 array_lengthof(Ops));
17711 /// PerformMulCombine - Optimize a single multiply with constant into two
17712 /// in order to implement it with two cheaper instructions, e.g.
17713 /// LEA + SHL, LEA + LEA.
17714 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
17715 TargetLowering::DAGCombinerInfo &DCI) {
17716 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
17719 EVT VT = N->getValueType(0);
17720 if (VT != MVT::i64)
17723 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
17726 uint64_t MulAmt = C->getZExtValue();
17727 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
17730 uint64_t MulAmt1 = 0;
17731 uint64_t MulAmt2 = 0;
17732 if ((MulAmt % 9) == 0) {
17734 MulAmt2 = MulAmt / 9;
17735 } else if ((MulAmt % 5) == 0) {
17737 MulAmt2 = MulAmt / 5;
17738 } else if ((MulAmt % 3) == 0) {
17740 MulAmt2 = MulAmt / 3;
17743 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
17746 if (isPowerOf2_64(MulAmt2) &&
17747 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
17748 // If second multiplifer is pow2, issue it first. We want the multiply by
17749 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
17751 std::swap(MulAmt1, MulAmt2);
17754 if (isPowerOf2_64(MulAmt1))
17755 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
17756 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
17758 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
17759 DAG.getConstant(MulAmt1, VT));
17761 if (isPowerOf2_64(MulAmt2))
17762 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
17763 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
17765 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
17766 DAG.getConstant(MulAmt2, VT));
17768 // Do not add new nodes to DAG combiner worklist.
17769 DCI.CombineTo(N, NewMul, false);
17774 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
17775 SDValue N0 = N->getOperand(0);
17776 SDValue N1 = N->getOperand(1);
17777 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
17778 EVT VT = N0.getValueType();
17780 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
17781 // since the result of setcc_c is all zero's or all ones.
17782 if (VT.isInteger() && !VT.isVector() &&
17783 N1C && N0.getOpcode() == ISD::AND &&
17784 N0.getOperand(1).getOpcode() == ISD::Constant) {
17785 SDValue N00 = N0.getOperand(0);
17786 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
17787 ((N00.getOpcode() == ISD::ANY_EXTEND ||
17788 N00.getOpcode() == ISD::ZERO_EXTEND) &&
17789 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
17790 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
17791 APInt ShAmt = N1C->getAPIntValue();
17792 Mask = Mask.shl(ShAmt);
17794 return DAG.getNode(ISD::AND, SDLoc(N), VT,
17795 N00, DAG.getConstant(Mask, VT));
17799 // Hardware support for vector shifts is sparse which makes us scalarize the
17800 // vector operations in many cases. Also, on sandybridge ADD is faster than
17802 // (shl V, 1) -> add V,V
17803 if (isSplatVector(N1.getNode())) {
17804 assert(N0.getValueType().isVector() && "Invalid vector shift type");
17805 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
17806 // We shift all of the values by one. In many cases we do not have
17807 // hardware support for this operation. This is better expressed as an ADD
17809 if (N1C && (1 == N1C->getZExtValue())) {
17810 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
17817 /// \brief Returns a vector of 0s if the node in input is a vector logical
17818 /// shift by a constant amount which is known to be bigger than or equal
17819 /// to the vector element size in bits.
17820 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
17821 const X86Subtarget *Subtarget) {
17822 EVT VT = N->getValueType(0);
17824 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
17825 (!Subtarget->hasInt256() ||
17826 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
17829 SDValue Amt = N->getOperand(1);
17831 if (isSplatVector(Amt.getNode())) {
17832 SDValue SclrAmt = Amt->getOperand(0);
17833 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
17834 APInt ShiftAmt = C->getAPIntValue();
17835 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
17837 // SSE2/AVX2 logical shifts always return a vector of 0s
17838 // if the shift amount is bigger than or equal to
17839 // the element size. The constant shift amount will be
17840 // encoded as a 8-bit immediate.
17841 if (ShiftAmt.trunc(8).uge(MaxAmount))
17842 return getZeroVector(VT, Subtarget, DAG, DL);
17849 /// PerformShiftCombine - Combine shifts.
17850 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
17851 TargetLowering::DAGCombinerInfo &DCI,
17852 const X86Subtarget *Subtarget) {
17853 if (N->getOpcode() == ISD::SHL) {
17854 SDValue V = PerformSHLCombine(N, DAG);
17855 if (V.getNode()) return V;
17858 if (N->getOpcode() != ISD::SRA) {
17859 // Try to fold this logical shift into a zero vector.
17860 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
17861 if (V.getNode()) return V;
17867 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
17868 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
17869 // and friends. Likewise for OR -> CMPNEQSS.
17870 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
17871 TargetLowering::DAGCombinerInfo &DCI,
17872 const X86Subtarget *Subtarget) {
17875 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
17876 // we're requiring SSE2 for both.
17877 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
17878 SDValue N0 = N->getOperand(0);
17879 SDValue N1 = N->getOperand(1);
17880 SDValue CMP0 = N0->getOperand(1);
17881 SDValue CMP1 = N1->getOperand(1);
17884 // The SETCCs should both refer to the same CMP.
17885 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
17888 SDValue CMP00 = CMP0->getOperand(0);
17889 SDValue CMP01 = CMP0->getOperand(1);
17890 EVT VT = CMP00.getValueType();
17892 if (VT == MVT::f32 || VT == MVT::f64) {
17893 bool ExpectingFlags = false;
17894 // Check for any users that want flags:
17895 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
17896 !ExpectingFlags && UI != UE; ++UI)
17897 switch (UI->getOpcode()) {
17902 ExpectingFlags = true;
17904 case ISD::CopyToReg:
17905 case ISD::SIGN_EXTEND:
17906 case ISD::ZERO_EXTEND:
17907 case ISD::ANY_EXTEND:
17911 if (!ExpectingFlags) {
17912 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
17913 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
17915 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
17916 X86::CondCode tmp = cc0;
17921 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
17922 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
17923 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
17924 // FIXME: need symbolic constants for these magic numbers.
17925 // See X86ATTInstPrinter.cpp:printSSECC().
17926 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
17927 if (Subtarget->hasAVX512()) {
17928 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
17929 CMP01, DAG.getConstant(x86cc, MVT::i8));
17930 if (N->getValueType(0) != MVT::i1)
17931 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
17935 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
17936 CMP00.getValueType(), CMP00, CMP01,
17937 DAG.getConstant(x86cc, MVT::i8));
17938 MVT IntVT = (is64BitFP ? MVT::i64 : MVT::i32);
17939 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT,
17941 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
17942 DAG.getConstant(1, IntVT));
17943 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
17944 return OneBitOfTruth;
17952 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
17953 /// so it can be folded inside ANDNP.
17954 static bool CanFoldXORWithAllOnes(const SDNode *N) {
17955 EVT VT = N->getValueType(0);
17957 // Match direct AllOnes for 128 and 256-bit vectors
17958 if (ISD::isBuildVectorAllOnes(N))
17961 // Look through a bit convert.
17962 if (N->getOpcode() == ISD::BITCAST)
17963 N = N->getOperand(0).getNode();
17965 // Sometimes the operand may come from a insert_subvector building a 256-bit
17967 if (VT.is256BitVector() &&
17968 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
17969 SDValue V1 = N->getOperand(0);
17970 SDValue V2 = N->getOperand(1);
17972 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
17973 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
17974 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
17975 ISD::isBuildVectorAllOnes(V2.getNode()))
17982 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
17983 // register. In most cases we actually compare or select YMM-sized registers
17984 // and mixing the two types creates horrible code. This method optimizes
17985 // some of the transition sequences.
17986 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
17987 TargetLowering::DAGCombinerInfo &DCI,
17988 const X86Subtarget *Subtarget) {
17989 EVT VT = N->getValueType(0);
17990 if (!VT.is256BitVector())
17993 assert((N->getOpcode() == ISD::ANY_EXTEND ||
17994 N->getOpcode() == ISD::ZERO_EXTEND ||
17995 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
17997 SDValue Narrow = N->getOperand(0);
17998 EVT NarrowVT = Narrow->getValueType(0);
17999 if (!NarrowVT.is128BitVector())
18002 if (Narrow->getOpcode() != ISD::XOR &&
18003 Narrow->getOpcode() != ISD::AND &&
18004 Narrow->getOpcode() != ISD::OR)
18007 SDValue N0 = Narrow->getOperand(0);
18008 SDValue N1 = Narrow->getOperand(1);
18011 // The Left side has to be a trunc.
18012 if (N0.getOpcode() != ISD::TRUNCATE)
18015 // The type of the truncated inputs.
18016 EVT WideVT = N0->getOperand(0)->getValueType(0);
18020 // The right side has to be a 'trunc' or a constant vector.
18021 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
18022 bool RHSConst = (isSplatVector(N1.getNode()) &&
18023 isa<ConstantSDNode>(N1->getOperand(0)));
18024 if (!RHSTrunc && !RHSConst)
18027 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18029 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
18032 // Set N0 and N1 to hold the inputs to the new wide operation.
18033 N0 = N0->getOperand(0);
18035 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
18036 N1->getOperand(0));
18037 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
18038 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, &C[0], C.size());
18039 } else if (RHSTrunc) {
18040 N1 = N1->getOperand(0);
18043 // Generate the wide operation.
18044 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
18045 unsigned Opcode = N->getOpcode();
18047 case ISD::ANY_EXTEND:
18049 case ISD::ZERO_EXTEND: {
18050 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
18051 APInt Mask = APInt::getAllOnesValue(InBits);
18052 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
18053 return DAG.getNode(ISD::AND, DL, VT,
18054 Op, DAG.getConstant(Mask, VT));
18056 case ISD::SIGN_EXTEND:
18057 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
18058 Op, DAG.getValueType(NarrowVT));
18060 llvm_unreachable("Unexpected opcode");
18064 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
18065 TargetLowering::DAGCombinerInfo &DCI,
18066 const X86Subtarget *Subtarget) {
18067 EVT VT = N->getValueType(0);
18068 if (DCI.isBeforeLegalizeOps())
18071 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
18075 // Create BLSI, BLSR, and BZHI instructions
18076 // BLSI is X & (-X)
18077 // BLSR is X & (X-1)
18078 // BZHI is X & ((1 << Y) - 1)
18079 // BEXTR is ((X >> imm) & (2**size-1))
18080 if (VT == MVT::i32 || VT == MVT::i64) {
18081 SDValue N0 = N->getOperand(0);
18082 SDValue N1 = N->getOperand(1);
18085 if (Subtarget->hasBMI()) {
18086 // Check LHS for neg
18087 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
18088 isZero(N0.getOperand(0)))
18089 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
18091 // Check RHS for neg
18092 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
18093 isZero(N1.getOperand(0)))
18094 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
18096 // Check LHS for X-1
18097 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
18098 isAllOnes(N0.getOperand(1)))
18099 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
18101 // Check RHS for X-1
18102 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
18103 isAllOnes(N1.getOperand(1)))
18104 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
18107 if (Subtarget->hasBMI2()) {
18108 // Check for (and (add (shl 1, Y), -1), X)
18109 if (N0.getOpcode() == ISD::ADD && isAllOnes(N0.getOperand(1))) {
18110 SDValue N00 = N0.getOperand(0);
18111 if (N00.getOpcode() == ISD::SHL) {
18112 SDValue N001 = N00.getOperand(1);
18113 assert(N001.getValueType() == MVT::i8 && "unexpected type");
18114 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N00.getOperand(0));
18115 if (C && C->getZExtValue() == 1)
18116 return DAG.getNode(X86ISD::BZHI, DL, VT, N1, N001);
18120 // Check for (and X, (add (shl 1, Y), -1))
18121 if (N1.getOpcode() == ISD::ADD && isAllOnes(N1.getOperand(1))) {
18122 SDValue N10 = N1.getOperand(0);
18123 if (N10.getOpcode() == ISD::SHL) {
18124 SDValue N101 = N10.getOperand(1);
18125 assert(N101.getValueType() == MVT::i8 && "unexpected type");
18126 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N10.getOperand(0));
18127 if (C && C->getZExtValue() == 1)
18128 return DAG.getNode(X86ISD::BZHI, DL, VT, N0, N101);
18133 // Check for BEXTR.
18134 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
18135 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
18136 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
18137 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
18138 if (MaskNode && ShiftNode) {
18139 uint64_t Mask = MaskNode->getZExtValue();
18140 uint64_t Shift = ShiftNode->getZExtValue();
18141 if (isMask_64(Mask)) {
18142 uint64_t MaskSize = CountPopulation_64(Mask);
18143 if (Shift + MaskSize <= VT.getSizeInBits())
18144 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
18145 DAG.getConstant(Shift | (MaskSize << 8), VT));
18153 // Want to form ANDNP nodes:
18154 // 1) In the hopes of then easily combining them with OR and AND nodes
18155 // to form PBLEND/PSIGN.
18156 // 2) To match ANDN packed intrinsics
18157 if (VT != MVT::v2i64 && VT != MVT::v4i64)
18160 SDValue N0 = N->getOperand(0);
18161 SDValue N1 = N->getOperand(1);
18164 // Check LHS for vnot
18165 if (N0.getOpcode() == ISD::XOR &&
18166 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
18167 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
18168 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
18170 // Check RHS for vnot
18171 if (N1.getOpcode() == ISD::XOR &&
18172 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
18173 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
18174 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
18179 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
18180 TargetLowering::DAGCombinerInfo &DCI,
18181 const X86Subtarget *Subtarget) {
18182 if (DCI.isBeforeLegalizeOps())
18185 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
18189 SDValue N0 = N->getOperand(0);
18190 SDValue N1 = N->getOperand(1);
18191 EVT VT = N->getValueType(0);
18193 // look for psign/blend
18194 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
18195 if (!Subtarget->hasSSSE3() ||
18196 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
18199 // Canonicalize pandn to RHS
18200 if (N0.getOpcode() == X86ISD::ANDNP)
18202 // or (and (m, y), (pandn m, x))
18203 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
18204 SDValue Mask = N1.getOperand(0);
18205 SDValue X = N1.getOperand(1);
18207 if (N0.getOperand(0) == Mask)
18208 Y = N0.getOperand(1);
18209 if (N0.getOperand(1) == Mask)
18210 Y = N0.getOperand(0);
18212 // Check to see if the mask appeared in both the AND and ANDNP and
18216 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
18217 // Look through mask bitcast.
18218 if (Mask.getOpcode() == ISD::BITCAST)
18219 Mask = Mask.getOperand(0);
18220 if (X.getOpcode() == ISD::BITCAST)
18221 X = X.getOperand(0);
18222 if (Y.getOpcode() == ISD::BITCAST)
18223 Y = Y.getOperand(0);
18225 EVT MaskVT = Mask.getValueType();
18227 // Validate that the Mask operand is a vector sra node.
18228 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
18229 // there is no psrai.b
18230 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
18231 unsigned SraAmt = ~0;
18232 if (Mask.getOpcode() == ISD::SRA) {
18233 SDValue Amt = Mask.getOperand(1);
18234 if (isSplatVector(Amt.getNode())) {
18235 SDValue SclrAmt = Amt->getOperand(0);
18236 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt))
18237 SraAmt = C->getZExtValue();
18239 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
18240 SDValue SraC = Mask.getOperand(1);
18241 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
18243 if ((SraAmt + 1) != EltBits)
18248 // Now we know we at least have a plendvb with the mask val. See if
18249 // we can form a psignb/w/d.
18250 // psign = x.type == y.type == mask.type && y = sub(0, x);
18251 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
18252 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
18253 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
18254 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
18255 "Unsupported VT for PSIGN");
18256 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
18257 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
18259 // PBLENDVB only available on SSE 4.1
18260 if (!Subtarget->hasSSE41())
18263 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
18265 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
18266 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
18267 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
18268 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
18269 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
18273 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
18276 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
18277 MachineFunction &MF = DAG.getMachineFunction();
18278 bool OptForSize = MF.getFunction()->getAttributes().
18279 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
18281 // SHLD/SHRD instructions have lower register pressure, but on some
18282 // platforms they have higher latency than the equivalent
18283 // series of shifts/or that would otherwise be generated.
18284 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
18285 // have higher latencies and we are not optimizing for size.
18286 if (!OptForSize && Subtarget->isSHLDSlow())
18289 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
18291 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
18293 if (!N0.hasOneUse() || !N1.hasOneUse())
18296 SDValue ShAmt0 = N0.getOperand(1);
18297 if (ShAmt0.getValueType() != MVT::i8)
18299 SDValue ShAmt1 = N1.getOperand(1);
18300 if (ShAmt1.getValueType() != MVT::i8)
18302 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
18303 ShAmt0 = ShAmt0.getOperand(0);
18304 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
18305 ShAmt1 = ShAmt1.getOperand(0);
18308 unsigned Opc = X86ISD::SHLD;
18309 SDValue Op0 = N0.getOperand(0);
18310 SDValue Op1 = N1.getOperand(0);
18311 if (ShAmt0.getOpcode() == ISD::SUB) {
18312 Opc = X86ISD::SHRD;
18313 std::swap(Op0, Op1);
18314 std::swap(ShAmt0, ShAmt1);
18317 unsigned Bits = VT.getSizeInBits();
18318 if (ShAmt1.getOpcode() == ISD::SUB) {
18319 SDValue Sum = ShAmt1.getOperand(0);
18320 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
18321 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
18322 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
18323 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
18324 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
18325 return DAG.getNode(Opc, DL, VT,
18327 DAG.getNode(ISD::TRUNCATE, DL,
18330 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
18331 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
18333 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
18334 return DAG.getNode(Opc, DL, VT,
18335 N0.getOperand(0), N1.getOperand(0),
18336 DAG.getNode(ISD::TRUNCATE, DL,
18343 // Generate NEG and CMOV for integer abs.
18344 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
18345 EVT VT = N->getValueType(0);
18347 // Since X86 does not have CMOV for 8-bit integer, we don't convert
18348 // 8-bit integer abs to NEG and CMOV.
18349 if (VT.isInteger() && VT.getSizeInBits() == 8)
18352 SDValue N0 = N->getOperand(0);
18353 SDValue N1 = N->getOperand(1);
18356 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
18357 // and change it to SUB and CMOV.
18358 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
18359 N0.getOpcode() == ISD::ADD &&
18360 N0.getOperand(1) == N1 &&
18361 N1.getOpcode() == ISD::SRA &&
18362 N1.getOperand(0) == N0.getOperand(0))
18363 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
18364 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
18365 // Generate SUB & CMOV.
18366 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
18367 DAG.getConstant(0, VT), N0.getOperand(0));
18369 SDValue Ops[] = { N0.getOperand(0), Neg,
18370 DAG.getConstant(X86::COND_GE, MVT::i8),
18371 SDValue(Neg.getNode(), 1) };
18372 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
18373 Ops, array_lengthof(Ops));
18378 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
18379 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
18380 TargetLowering::DAGCombinerInfo &DCI,
18381 const X86Subtarget *Subtarget) {
18382 EVT VT = N->getValueType(0);
18383 if (DCI.isBeforeLegalizeOps())
18386 if (Subtarget->hasCMov()) {
18387 SDValue RV = performIntegerAbsCombine(N, DAG);
18392 // Try forming BMI if it is available.
18393 if (!Subtarget->hasBMI())
18396 if (VT != MVT::i32 && VT != MVT::i64)
18399 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
18401 // Create BLSMSK instructions by finding X ^ (X-1)
18402 SDValue N0 = N->getOperand(0);
18403 SDValue N1 = N->getOperand(1);
18406 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
18407 isAllOnes(N0.getOperand(1)))
18408 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
18410 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
18411 isAllOnes(N1.getOperand(1)))
18412 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
18417 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
18418 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
18419 TargetLowering::DAGCombinerInfo &DCI,
18420 const X86Subtarget *Subtarget) {
18421 LoadSDNode *Ld = cast<LoadSDNode>(N);
18422 EVT RegVT = Ld->getValueType(0);
18423 EVT MemVT = Ld->getMemoryVT();
18425 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18426 unsigned RegSz = RegVT.getSizeInBits();
18428 // On Sandybridge unaligned 256bit loads are inefficient.
18429 ISD::LoadExtType Ext = Ld->getExtensionType();
18430 unsigned Alignment = Ld->getAlignment();
18431 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
18432 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
18433 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
18434 unsigned NumElems = RegVT.getVectorNumElements();
18438 SDValue Ptr = Ld->getBasePtr();
18439 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
18441 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
18443 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
18444 Ld->getPointerInfo(), Ld->isVolatile(),
18445 Ld->isNonTemporal(), Ld->isInvariant(),
18447 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18448 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
18449 Ld->getPointerInfo(), Ld->isVolatile(),
18450 Ld->isNonTemporal(), Ld->isInvariant(),
18451 std::min(16U, Alignment));
18452 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
18454 Load2.getValue(1));
18456 SDValue NewVec = DAG.getUNDEF(RegVT);
18457 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
18458 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
18459 return DCI.CombineTo(N, NewVec, TF, true);
18462 // If this is a vector EXT Load then attempt to optimize it using a
18463 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
18464 // expansion is still better than scalar code.
18465 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll
18466 // emit a shuffle and a arithmetic shift.
18467 // TODO: It is possible to support ZExt by zeroing the undef values
18468 // during the shuffle phase or after the shuffle.
18469 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() &&
18470 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) {
18471 assert(MemVT != RegVT && "Cannot extend to the same type");
18472 assert(MemVT.isVector() && "Must load a vector from memory");
18474 unsigned NumElems = RegVT.getVectorNumElements();
18475 unsigned MemSz = MemVT.getSizeInBits();
18476 assert(RegSz > MemSz && "Register size must be greater than the mem size");
18478 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())
18481 // All sizes must be a power of two.
18482 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
18485 // Attempt to load the original value using scalar loads.
18486 // Find the largest scalar type that divides the total loaded size.
18487 MVT SclrLoadTy = MVT::i8;
18488 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
18489 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
18490 MVT Tp = (MVT::SimpleValueType)tp;
18491 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
18496 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
18497 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
18499 SclrLoadTy = MVT::f64;
18501 // Calculate the number of scalar loads that we need to perform
18502 // in order to load our vector from memory.
18503 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
18504 if (Ext == ISD::SEXTLOAD && NumLoads > 1)
18507 unsigned loadRegZize = RegSz;
18508 if (Ext == ISD::SEXTLOAD && RegSz == 256)
18511 // Represent our vector as a sequence of elements which are the
18512 // largest scalar that we can load.
18513 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
18514 loadRegZize/SclrLoadTy.getSizeInBits());
18516 // Represent the data using the same element type that is stored in
18517 // memory. In practice, we ''widen'' MemVT.
18519 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
18520 loadRegZize/MemVT.getScalarType().getSizeInBits());
18522 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
18523 "Invalid vector type");
18525 // We can't shuffle using an illegal type.
18526 if (!TLI.isTypeLegal(WideVecVT))
18529 SmallVector<SDValue, 8> Chains;
18530 SDValue Ptr = Ld->getBasePtr();
18531 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
18532 TLI.getPointerTy());
18533 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
18535 for (unsigned i = 0; i < NumLoads; ++i) {
18536 // Perform a single load.
18537 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
18538 Ptr, Ld->getPointerInfo(),
18539 Ld->isVolatile(), Ld->isNonTemporal(),
18540 Ld->isInvariant(), Ld->getAlignment());
18541 Chains.push_back(ScalarLoad.getValue(1));
18542 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
18543 // another round of DAGCombining.
18545 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
18547 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
18548 ScalarLoad, DAG.getIntPtrConstant(i));
18550 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18553 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
18556 // Bitcast the loaded value to a vector of the original element type, in
18557 // the size of the target vector type.
18558 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
18559 unsigned SizeRatio = RegSz/MemSz;
18561 if (Ext == ISD::SEXTLOAD) {
18562 // If we have SSE4.1 we can directly emit a VSEXT node.
18563 if (Subtarget->hasSSE41()) {
18564 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
18565 return DCI.CombineTo(N, Sext, TF, true);
18568 // Otherwise we'll shuffle the small elements in the high bits of the
18569 // larger type and perform an arithmetic shift. If the shift is not legal
18570 // it's better to scalarize.
18571 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
18574 // Redistribute the loaded elements into the different locations.
18575 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18576 for (unsigned i = 0; i != NumElems; ++i)
18577 ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
18579 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
18580 DAG.getUNDEF(WideVecVT),
18583 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
18585 // Build the arithmetic shift.
18586 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
18587 MemVT.getVectorElementType().getSizeInBits();
18588 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
18589 DAG.getConstant(Amt, RegVT));
18591 return DCI.CombineTo(N, Shuff, TF, true);
18594 // Redistribute the loaded elements into the different locations.
18595 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18596 for (unsigned i = 0; i != NumElems; ++i)
18597 ShuffleVec[i*SizeRatio] = i;
18599 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
18600 DAG.getUNDEF(WideVecVT),
18603 // Bitcast to the requested type.
18604 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
18605 // Replace the original load with the new sequence
18606 // and return the new chain.
18607 return DCI.CombineTo(N, Shuff, TF, true);
18613 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
18614 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
18615 const X86Subtarget *Subtarget) {
18616 StoreSDNode *St = cast<StoreSDNode>(N);
18617 EVT VT = St->getValue().getValueType();
18618 EVT StVT = St->getMemoryVT();
18620 SDValue StoredVal = St->getOperand(1);
18621 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18623 // If we are saving a concatenation of two XMM registers, perform two stores.
18624 // On Sandy Bridge, 256-bit memory operations are executed by two
18625 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
18626 // memory operation.
18627 unsigned Alignment = St->getAlignment();
18628 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
18629 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
18630 StVT == VT && !IsAligned) {
18631 unsigned NumElems = VT.getVectorNumElements();
18635 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
18636 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
18638 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
18639 SDValue Ptr0 = St->getBasePtr();
18640 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
18642 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
18643 St->getPointerInfo(), St->isVolatile(),
18644 St->isNonTemporal(), Alignment);
18645 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
18646 St->getPointerInfo(), St->isVolatile(),
18647 St->isNonTemporal(),
18648 std::min(16U, Alignment));
18649 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
18652 // Optimize trunc store (of multiple scalars) to shuffle and store.
18653 // First, pack all of the elements in one place. Next, store to memory
18654 // in fewer chunks.
18655 if (St->isTruncatingStore() && VT.isVector()) {
18656 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18657 unsigned NumElems = VT.getVectorNumElements();
18658 assert(StVT != VT && "Cannot truncate to the same type");
18659 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
18660 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
18662 // From, To sizes and ElemCount must be pow of two
18663 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
18664 // We are going to use the original vector elt for storing.
18665 // Accumulated smaller vector elements must be a multiple of the store size.
18666 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
18668 unsigned SizeRatio = FromSz / ToSz;
18670 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
18672 // Create a type on which we perform the shuffle
18673 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
18674 StVT.getScalarType(), NumElems*SizeRatio);
18676 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
18678 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
18679 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18680 for (unsigned i = 0; i != NumElems; ++i)
18681 ShuffleVec[i] = i * SizeRatio;
18683 // Can't shuffle using an illegal type.
18684 if (!TLI.isTypeLegal(WideVecVT))
18687 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
18688 DAG.getUNDEF(WideVecVT),
18690 // At this point all of the data is stored at the bottom of the
18691 // register. We now need to save it to mem.
18693 // Find the largest store unit
18694 MVT StoreType = MVT::i8;
18695 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
18696 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
18697 MVT Tp = (MVT::SimpleValueType)tp;
18698 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
18702 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
18703 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
18704 (64 <= NumElems * ToSz))
18705 StoreType = MVT::f64;
18707 // Bitcast the original vector into a vector of store-size units
18708 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
18709 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
18710 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
18711 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
18712 SmallVector<SDValue, 8> Chains;
18713 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
18714 TLI.getPointerTy());
18715 SDValue Ptr = St->getBasePtr();
18717 // Perform one or more big stores into memory.
18718 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
18719 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
18720 StoreType, ShuffWide,
18721 DAG.getIntPtrConstant(i));
18722 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
18723 St->getPointerInfo(), St->isVolatile(),
18724 St->isNonTemporal(), St->getAlignment());
18725 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18726 Chains.push_back(Ch);
18729 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
18733 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
18734 // the FP state in cases where an emms may be missing.
18735 // A preferable solution to the general problem is to figure out the right
18736 // places to insert EMMS. This qualifies as a quick hack.
18738 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
18739 if (VT.getSizeInBits() != 64)
18742 const Function *F = DAG.getMachineFunction().getFunction();
18743 bool NoImplicitFloatOps = F->getAttributes().
18744 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
18745 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
18746 && Subtarget->hasSSE2();
18747 if ((VT.isVector() ||
18748 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
18749 isa<LoadSDNode>(St->getValue()) &&
18750 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
18751 St->getChain().hasOneUse() && !St->isVolatile()) {
18752 SDNode* LdVal = St->getValue().getNode();
18753 LoadSDNode *Ld = 0;
18754 int TokenFactorIndex = -1;
18755 SmallVector<SDValue, 8> Ops;
18756 SDNode* ChainVal = St->getChain().getNode();
18757 // Must be a store of a load. We currently handle two cases: the load
18758 // is a direct child, and it's under an intervening TokenFactor. It is
18759 // possible to dig deeper under nested TokenFactors.
18760 if (ChainVal == LdVal)
18761 Ld = cast<LoadSDNode>(St->getChain());
18762 else if (St->getValue().hasOneUse() &&
18763 ChainVal->getOpcode() == ISD::TokenFactor) {
18764 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
18765 if (ChainVal->getOperand(i).getNode() == LdVal) {
18766 TokenFactorIndex = i;
18767 Ld = cast<LoadSDNode>(St->getValue());
18769 Ops.push_back(ChainVal->getOperand(i));
18773 if (!Ld || !ISD::isNormalLoad(Ld))
18776 // If this is not the MMX case, i.e. we are just turning i64 load/store
18777 // into f64 load/store, avoid the transformation if there are multiple
18778 // uses of the loaded value.
18779 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
18784 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
18785 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
18787 if (Subtarget->is64Bit() || F64IsLegal) {
18788 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
18789 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
18790 Ld->getPointerInfo(), Ld->isVolatile(),
18791 Ld->isNonTemporal(), Ld->isInvariant(),
18792 Ld->getAlignment());
18793 SDValue NewChain = NewLd.getValue(1);
18794 if (TokenFactorIndex != -1) {
18795 Ops.push_back(NewChain);
18796 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
18799 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
18800 St->getPointerInfo(),
18801 St->isVolatile(), St->isNonTemporal(),
18802 St->getAlignment());
18805 // Otherwise, lower to two pairs of 32-bit loads / stores.
18806 SDValue LoAddr = Ld->getBasePtr();
18807 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
18808 DAG.getConstant(4, MVT::i32));
18810 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
18811 Ld->getPointerInfo(),
18812 Ld->isVolatile(), Ld->isNonTemporal(),
18813 Ld->isInvariant(), Ld->getAlignment());
18814 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
18815 Ld->getPointerInfo().getWithOffset(4),
18816 Ld->isVolatile(), Ld->isNonTemporal(),
18818 MinAlign(Ld->getAlignment(), 4));
18820 SDValue NewChain = LoLd.getValue(1);
18821 if (TokenFactorIndex != -1) {
18822 Ops.push_back(LoLd);
18823 Ops.push_back(HiLd);
18824 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
18828 LoAddr = St->getBasePtr();
18829 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
18830 DAG.getConstant(4, MVT::i32));
18832 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
18833 St->getPointerInfo(),
18834 St->isVolatile(), St->isNonTemporal(),
18835 St->getAlignment());
18836 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
18837 St->getPointerInfo().getWithOffset(4),
18839 St->isNonTemporal(),
18840 MinAlign(St->getAlignment(), 4));
18841 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
18846 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
18847 /// and return the operands for the horizontal operation in LHS and RHS. A
18848 /// horizontal operation performs the binary operation on successive elements
18849 /// of its first operand, then on successive elements of its second operand,
18850 /// returning the resulting values in a vector. For example, if
18851 /// A = < float a0, float a1, float a2, float a3 >
18853 /// B = < float b0, float b1, float b2, float b3 >
18854 /// then the result of doing a horizontal operation on A and B is
18855 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
18856 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
18857 /// A horizontal-op B, for some already available A and B, and if so then LHS is
18858 /// set to A, RHS to B, and the routine returns 'true'.
18859 /// Note that the binary operation should have the property that if one of the
18860 /// operands is UNDEF then the result is UNDEF.
18861 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
18862 // Look for the following pattern: if
18863 // A = < float a0, float a1, float a2, float a3 >
18864 // B = < float b0, float b1, float b2, float b3 >
18866 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
18867 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
18868 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
18869 // which is A horizontal-op B.
18871 // At least one of the operands should be a vector shuffle.
18872 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
18873 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
18876 MVT VT = LHS.getSimpleValueType();
18878 assert((VT.is128BitVector() || VT.is256BitVector()) &&
18879 "Unsupported vector type for horizontal add/sub");
18881 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
18882 // operate independently on 128-bit lanes.
18883 unsigned NumElts = VT.getVectorNumElements();
18884 unsigned NumLanes = VT.getSizeInBits()/128;
18885 unsigned NumLaneElts = NumElts / NumLanes;
18886 assert((NumLaneElts % 2 == 0) &&
18887 "Vector type should have an even number of elements in each lane");
18888 unsigned HalfLaneElts = NumLaneElts/2;
18890 // View LHS in the form
18891 // LHS = VECTOR_SHUFFLE A, B, LMask
18892 // If LHS is not a shuffle then pretend it is the shuffle
18893 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
18894 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
18897 SmallVector<int, 16> LMask(NumElts);
18898 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
18899 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
18900 A = LHS.getOperand(0);
18901 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
18902 B = LHS.getOperand(1);
18903 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
18904 std::copy(Mask.begin(), Mask.end(), LMask.begin());
18906 if (LHS.getOpcode() != ISD::UNDEF)
18908 for (unsigned i = 0; i != NumElts; ++i)
18912 // Likewise, view RHS in the form
18913 // RHS = VECTOR_SHUFFLE C, D, RMask
18915 SmallVector<int, 16> RMask(NumElts);
18916 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
18917 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
18918 C = RHS.getOperand(0);
18919 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
18920 D = RHS.getOperand(1);
18921 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
18922 std::copy(Mask.begin(), Mask.end(), RMask.begin());
18924 if (RHS.getOpcode() != ISD::UNDEF)
18926 for (unsigned i = 0; i != NumElts; ++i)
18930 // Check that the shuffles are both shuffling the same vectors.
18931 if (!(A == C && B == D) && !(A == D && B == C))
18934 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
18935 if (!A.getNode() && !B.getNode())
18938 // If A and B occur in reverse order in RHS, then "swap" them (which means
18939 // rewriting the mask).
18941 CommuteVectorShuffleMask(RMask, NumElts);
18943 // At this point LHS and RHS are equivalent to
18944 // LHS = VECTOR_SHUFFLE A, B, LMask
18945 // RHS = VECTOR_SHUFFLE A, B, RMask
18946 // Check that the masks correspond to performing a horizontal operation.
18947 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
18948 for (unsigned i = 0; i != NumLaneElts; ++i) {
18949 int LIdx = LMask[i+l], RIdx = RMask[i+l];
18951 // Ignore any UNDEF components.
18952 if (LIdx < 0 || RIdx < 0 ||
18953 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
18954 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
18957 // Check that successive elements are being operated on. If not, this is
18958 // not a horizontal operation.
18959 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
18960 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
18961 if (!(LIdx == Index && RIdx == Index + 1) &&
18962 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
18967 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
18968 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
18972 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
18973 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
18974 const X86Subtarget *Subtarget) {
18975 EVT VT = N->getValueType(0);
18976 SDValue LHS = N->getOperand(0);
18977 SDValue RHS = N->getOperand(1);
18979 // Try to synthesize horizontal adds from adds of shuffles.
18980 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18981 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18982 isHorizontalBinOp(LHS, RHS, true))
18983 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
18987 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
18988 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
18989 const X86Subtarget *Subtarget) {
18990 EVT VT = N->getValueType(0);
18991 SDValue LHS = N->getOperand(0);
18992 SDValue RHS = N->getOperand(1);
18994 // Try to synthesize horizontal subs from subs of shuffles.
18995 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18996 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18997 isHorizontalBinOp(LHS, RHS, false))
18998 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
19002 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
19003 /// X86ISD::FXOR nodes.
19004 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
19005 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
19006 // F[X]OR(0.0, x) -> x
19007 // F[X]OR(x, 0.0) -> x
19008 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
19009 if (C->getValueAPF().isPosZero())
19010 return N->getOperand(1);
19011 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
19012 if (C->getValueAPF().isPosZero())
19013 return N->getOperand(0);
19017 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
19018 /// X86ISD::FMAX nodes.
19019 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
19020 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
19022 // Only perform optimizations if UnsafeMath is used.
19023 if (!DAG.getTarget().Options.UnsafeFPMath)
19026 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
19027 // into FMINC and FMAXC, which are Commutative operations.
19028 unsigned NewOp = 0;
19029 switch (N->getOpcode()) {
19030 default: llvm_unreachable("unknown opcode");
19031 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
19032 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
19035 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
19036 N->getOperand(0), N->getOperand(1));
19039 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
19040 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
19041 // FAND(0.0, x) -> 0.0
19042 // FAND(x, 0.0) -> 0.0
19043 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
19044 if (C->getValueAPF().isPosZero())
19045 return N->getOperand(0);
19046 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
19047 if (C->getValueAPF().isPosZero())
19048 return N->getOperand(1);
19052 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
19053 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
19054 // FANDN(x, 0.0) -> 0.0
19055 // FANDN(0.0, x) -> x
19056 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
19057 if (C->getValueAPF().isPosZero())
19058 return N->getOperand(1);
19059 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
19060 if (C->getValueAPF().isPosZero())
19061 return N->getOperand(1);
19065 static SDValue PerformBTCombine(SDNode *N,
19067 TargetLowering::DAGCombinerInfo &DCI) {
19068 // BT ignores high bits in the bit index operand.
19069 SDValue Op1 = N->getOperand(1);
19070 if (Op1.hasOneUse()) {
19071 unsigned BitWidth = Op1.getValueSizeInBits();
19072 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
19073 APInt KnownZero, KnownOne;
19074 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
19075 !DCI.isBeforeLegalizeOps());
19076 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19077 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
19078 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
19079 DCI.CommitTargetLoweringOpt(TLO);
19084 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
19085 SDValue Op = N->getOperand(0);
19086 if (Op.getOpcode() == ISD::BITCAST)
19087 Op = Op.getOperand(0);
19088 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
19089 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
19090 VT.getVectorElementType().getSizeInBits() ==
19091 OpVT.getVectorElementType().getSizeInBits()) {
19092 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
19097 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
19098 const X86Subtarget *Subtarget) {
19099 EVT VT = N->getValueType(0);
19100 if (!VT.isVector())
19103 SDValue N0 = N->getOperand(0);
19104 SDValue N1 = N->getOperand(1);
19105 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
19108 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
19109 // both SSE and AVX2 since there is no sign-extended shift right
19110 // operation on a vector with 64-bit elements.
19111 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
19112 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
19113 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
19114 N0.getOpcode() == ISD::SIGN_EXTEND)) {
19115 SDValue N00 = N0.getOperand(0);
19117 // EXTLOAD has a better solution on AVX2,
19118 // it may be replaced with X86ISD::VSEXT node.
19119 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
19120 if (!ISD::isNormalLoad(N00.getNode()))
19123 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
19124 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
19126 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
19132 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
19133 TargetLowering::DAGCombinerInfo &DCI,
19134 const X86Subtarget *Subtarget) {
19135 if (!DCI.isBeforeLegalizeOps())
19138 if (!Subtarget->hasFp256())
19141 EVT VT = N->getValueType(0);
19142 if (VT.isVector() && VT.getSizeInBits() == 256) {
19143 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
19151 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
19152 const X86Subtarget* Subtarget) {
19154 EVT VT = N->getValueType(0);
19156 // Let legalize expand this if it isn't a legal type yet.
19157 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19160 EVT ScalarVT = VT.getScalarType();
19161 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
19162 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
19165 SDValue A = N->getOperand(0);
19166 SDValue B = N->getOperand(1);
19167 SDValue C = N->getOperand(2);
19169 bool NegA = (A.getOpcode() == ISD::FNEG);
19170 bool NegB = (B.getOpcode() == ISD::FNEG);
19171 bool NegC = (C.getOpcode() == ISD::FNEG);
19173 // Negative multiplication when NegA xor NegB
19174 bool NegMul = (NegA != NegB);
19176 A = A.getOperand(0);
19178 B = B.getOperand(0);
19180 C = C.getOperand(0);
19184 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
19186 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
19188 return DAG.getNode(Opcode, dl, VT, A, B, C);
19191 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
19192 TargetLowering::DAGCombinerInfo &DCI,
19193 const X86Subtarget *Subtarget) {
19194 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
19195 // (and (i32 x86isd::setcc_carry), 1)
19196 // This eliminates the zext. This transformation is necessary because
19197 // ISD::SETCC is always legalized to i8.
19199 SDValue N0 = N->getOperand(0);
19200 EVT VT = N->getValueType(0);
19202 if (N0.getOpcode() == ISD::AND &&
19204 N0.getOperand(0).hasOneUse()) {
19205 SDValue N00 = N0.getOperand(0);
19206 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
19207 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
19208 if (!C || C->getZExtValue() != 1)
19210 return DAG.getNode(ISD::AND, dl, VT,
19211 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
19212 N00.getOperand(0), N00.getOperand(1)),
19213 DAG.getConstant(1, VT));
19217 if (N0.getOpcode() == ISD::TRUNCATE &&
19219 N0.getOperand(0).hasOneUse()) {
19220 SDValue N00 = N0.getOperand(0);
19221 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
19222 return DAG.getNode(ISD::AND, dl, VT,
19223 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
19224 N00.getOperand(0), N00.getOperand(1)),
19225 DAG.getConstant(1, VT));
19228 if (VT.is256BitVector()) {
19229 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
19237 // Optimize x == -y --> x+y == 0
19238 // x != -y --> x+y != 0
19239 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
19240 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
19241 SDValue LHS = N->getOperand(0);
19242 SDValue RHS = N->getOperand(1);
19244 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
19245 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
19246 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
19247 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
19248 LHS.getValueType(), RHS, LHS.getOperand(1));
19249 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
19250 addV, DAG.getConstant(0, addV.getValueType()), CC);
19252 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
19253 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
19254 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
19255 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
19256 RHS.getValueType(), LHS, RHS.getOperand(1));
19257 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
19258 addV, DAG.getConstant(0, addV.getValueType()), CC);
19263 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
19264 // as "sbb reg,reg", since it can be extended without zext and produces
19265 // an all-ones bit which is more useful than 0/1 in some cases.
19266 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
19269 return DAG.getNode(ISD::AND, DL, VT,
19270 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
19271 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
19272 DAG.getConstant(1, VT));
19273 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
19274 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
19275 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
19276 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
19279 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
19280 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
19281 TargetLowering::DAGCombinerInfo &DCI,
19282 const X86Subtarget *Subtarget) {
19284 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
19285 SDValue EFLAGS = N->getOperand(1);
19287 if (CC == X86::COND_A) {
19288 // Try to convert COND_A into COND_B in an attempt to facilitate
19289 // materializing "setb reg".
19291 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
19292 // cannot take an immediate as its first operand.
19294 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
19295 EFLAGS.getValueType().isInteger() &&
19296 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
19297 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
19298 EFLAGS.getNode()->getVTList(),
19299 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
19300 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
19301 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
19305 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
19306 // a zext and produces an all-ones bit which is more useful than 0/1 in some
19308 if (CC == X86::COND_B)
19309 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
19313 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
19314 if (Flags.getNode()) {
19315 SDValue Cond = DAG.getConstant(CC, MVT::i8);
19316 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
19322 // Optimize branch condition evaluation.
19324 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
19325 TargetLowering::DAGCombinerInfo &DCI,
19326 const X86Subtarget *Subtarget) {
19328 SDValue Chain = N->getOperand(0);
19329 SDValue Dest = N->getOperand(1);
19330 SDValue EFLAGS = N->getOperand(3);
19331 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
19335 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
19336 if (Flags.getNode()) {
19337 SDValue Cond = DAG.getConstant(CC, MVT::i8);
19338 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
19345 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
19346 const X86TargetLowering *XTLI) {
19347 SDValue Op0 = N->getOperand(0);
19348 EVT InVT = Op0->getValueType(0);
19350 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
19351 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
19353 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
19354 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
19355 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
19358 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
19359 // a 32-bit target where SSE doesn't support i64->FP operations.
19360 if (Op0.getOpcode() == ISD::LOAD) {
19361 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
19362 EVT VT = Ld->getValueType(0);
19363 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
19364 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
19365 !XTLI->getSubtarget()->is64Bit() &&
19367 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
19368 Ld->getChain(), Op0, DAG);
19369 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
19376 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
19377 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
19378 X86TargetLowering::DAGCombinerInfo &DCI) {
19379 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
19380 // the result is either zero or one (depending on the input carry bit).
19381 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
19382 if (X86::isZeroNode(N->getOperand(0)) &&
19383 X86::isZeroNode(N->getOperand(1)) &&
19384 // We don't have a good way to replace an EFLAGS use, so only do this when
19386 SDValue(N, 1).use_empty()) {
19388 EVT VT = N->getValueType(0);
19389 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
19390 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
19391 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
19392 DAG.getConstant(X86::COND_B,MVT::i8),
19394 DAG.getConstant(1, VT));
19395 return DCI.CombineTo(N, Res1, CarryOut);
19401 // fold (add Y, (sete X, 0)) -> adc 0, Y
19402 // (add Y, (setne X, 0)) -> sbb -1, Y
19403 // (sub (sete X, 0), Y) -> sbb 0, Y
19404 // (sub (setne X, 0), Y) -> adc -1, Y
19405 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
19408 // Look through ZExts.
19409 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
19410 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
19413 SDValue SetCC = Ext.getOperand(0);
19414 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
19417 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
19418 if (CC != X86::COND_E && CC != X86::COND_NE)
19421 SDValue Cmp = SetCC.getOperand(1);
19422 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
19423 !X86::isZeroNode(Cmp.getOperand(1)) ||
19424 !Cmp.getOperand(0).getValueType().isInteger())
19427 SDValue CmpOp0 = Cmp.getOperand(0);
19428 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
19429 DAG.getConstant(1, CmpOp0.getValueType()));
19431 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
19432 if (CC == X86::COND_NE)
19433 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
19434 DL, OtherVal.getValueType(), OtherVal,
19435 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
19436 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
19437 DL, OtherVal.getValueType(), OtherVal,
19438 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
19441 /// PerformADDCombine - Do target-specific dag combines on integer adds.
19442 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
19443 const X86Subtarget *Subtarget) {
19444 EVT VT = N->getValueType(0);
19445 SDValue Op0 = N->getOperand(0);
19446 SDValue Op1 = N->getOperand(1);
19448 // Try to synthesize horizontal adds from adds of shuffles.
19449 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
19450 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
19451 isHorizontalBinOp(Op0, Op1, true))
19452 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
19454 return OptimizeConditionalInDecrement(N, DAG);
19457 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
19458 const X86Subtarget *Subtarget) {
19459 SDValue Op0 = N->getOperand(0);
19460 SDValue Op1 = N->getOperand(1);
19462 // X86 can't encode an immediate LHS of a sub. See if we can push the
19463 // negation into a preceding instruction.
19464 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
19465 // If the RHS of the sub is a XOR with one use and a constant, invert the
19466 // immediate. Then add one to the LHS of the sub so we can turn
19467 // X-Y -> X+~Y+1, saving one register.
19468 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
19469 isa<ConstantSDNode>(Op1.getOperand(1))) {
19470 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
19471 EVT VT = Op0.getValueType();
19472 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
19474 DAG.getConstant(~XorC, VT));
19475 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
19476 DAG.getConstant(C->getAPIntValue()+1, VT));
19480 // Try to synthesize horizontal adds from adds of shuffles.
19481 EVT VT = N->getValueType(0);
19482 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
19483 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
19484 isHorizontalBinOp(Op0, Op1, true))
19485 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
19487 return OptimizeConditionalInDecrement(N, DAG);
19490 /// performVZEXTCombine - Performs build vector combines
19491 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
19492 TargetLowering::DAGCombinerInfo &DCI,
19493 const X86Subtarget *Subtarget) {
19494 // (vzext (bitcast (vzext (x)) -> (vzext x)
19495 SDValue In = N->getOperand(0);
19496 while (In.getOpcode() == ISD::BITCAST)
19497 In = In.getOperand(0);
19499 if (In.getOpcode() != X86ISD::VZEXT)
19502 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
19506 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
19507 DAGCombinerInfo &DCI) const {
19508 SelectionDAG &DAG = DCI.DAG;
19509 switch (N->getOpcode()) {
19511 case ISD::EXTRACT_VECTOR_ELT:
19512 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
19514 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
19515 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
19516 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
19517 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
19518 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
19519 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
19522 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
19523 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
19524 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
19525 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
19526 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
19527 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
19528 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
19529 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
19530 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
19532 case X86ISD::FOR: return PerformFORCombine(N, DAG);
19534 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
19535 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
19536 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
19537 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
19538 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
19539 case ISD::ANY_EXTEND:
19540 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
19541 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
19542 case ISD::SIGN_EXTEND_INREG: return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
19543 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
19544 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
19545 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
19546 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
19547 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
19548 case X86ISD::SHUFP: // Handle all target specific shuffles
19549 case X86ISD::PALIGNR:
19550 case X86ISD::UNPCKH:
19551 case X86ISD::UNPCKL:
19552 case X86ISD::MOVHLPS:
19553 case X86ISD::MOVLHPS:
19554 case X86ISD::PSHUFD:
19555 case X86ISD::PSHUFHW:
19556 case X86ISD::PSHUFLW:
19557 case X86ISD::MOVSS:
19558 case X86ISD::MOVSD:
19559 case X86ISD::VPERMILP:
19560 case X86ISD::VPERM2X128:
19561 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
19562 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
19568 /// isTypeDesirableForOp - Return true if the target has native support for
19569 /// the specified value type and it is 'desirable' to use the type for the
19570 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
19571 /// instruction encodings are longer and some i16 instructions are slow.
19572 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
19573 if (!isTypeLegal(VT))
19575 if (VT != MVT::i16)
19582 case ISD::SIGN_EXTEND:
19583 case ISD::ZERO_EXTEND:
19584 case ISD::ANY_EXTEND:
19597 /// IsDesirableToPromoteOp - This method query the target whether it is
19598 /// beneficial for dag combiner to promote the specified node. If true, it
19599 /// should return the desired promotion type by reference.
19600 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
19601 EVT VT = Op.getValueType();
19602 if (VT != MVT::i16)
19605 bool Promote = false;
19606 bool Commute = false;
19607 switch (Op.getOpcode()) {
19610 LoadSDNode *LD = cast<LoadSDNode>(Op);
19611 // If the non-extending load has a single use and it's not live out, then it
19612 // might be folded.
19613 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
19614 Op.hasOneUse()*/) {
19615 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
19616 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
19617 // The only case where we'd want to promote LOAD (rather then it being
19618 // promoted as an operand is when it's only use is liveout.
19619 if (UI->getOpcode() != ISD::CopyToReg)
19626 case ISD::SIGN_EXTEND:
19627 case ISD::ZERO_EXTEND:
19628 case ISD::ANY_EXTEND:
19633 SDValue N0 = Op.getOperand(0);
19634 // Look out for (store (shl (load), x)).
19635 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
19648 SDValue N0 = Op.getOperand(0);
19649 SDValue N1 = Op.getOperand(1);
19650 if (!Commute && MayFoldLoad(N1))
19652 // Avoid disabling potential load folding opportunities.
19653 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
19655 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
19665 //===----------------------------------------------------------------------===//
19666 // X86 Inline Assembly Support
19667 //===----------------------------------------------------------------------===//
19670 // Helper to match a string separated by whitespace.
19671 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
19672 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
19674 for (unsigned i = 0, e = args.size(); i != e; ++i) {
19675 StringRef piece(*args[i]);
19676 if (!s.startswith(piece)) // Check if the piece matches.
19679 s = s.substr(piece.size());
19680 StringRef::size_type pos = s.find_first_not_of(" \t");
19681 if (pos == 0) // We matched a prefix.
19689 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
19692 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
19694 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
19695 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
19696 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
19697 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
19699 if (AsmPieces.size() == 3)
19701 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
19708 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
19709 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
19711 std::string AsmStr = IA->getAsmString();
19713 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
19714 if (!Ty || Ty->getBitWidth() % 16 != 0)
19717 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
19718 SmallVector<StringRef, 4> AsmPieces;
19719 SplitString(AsmStr, AsmPieces, ";\n");
19721 switch (AsmPieces.size()) {
19722 default: return false;
19724 // FIXME: this should verify that we are targeting a 486 or better. If not,
19725 // we will turn this bswap into something that will be lowered to logical
19726 // ops instead of emitting the bswap asm. For now, we don't support 486 or
19727 // lower so don't worry about this.
19729 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
19730 matchAsm(AsmPieces[0], "bswapl", "$0") ||
19731 matchAsm(AsmPieces[0], "bswapq", "$0") ||
19732 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
19733 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
19734 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
19735 // No need to check constraints, nothing other than the equivalent of
19736 // "=r,0" would be valid here.
19737 return IntrinsicLowering::LowerToByteSwap(CI);
19740 // rorw $$8, ${0:w} --> llvm.bswap.i16
19741 if (CI->getType()->isIntegerTy(16) &&
19742 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
19743 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
19744 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
19746 const std::string &ConstraintsStr = IA->getConstraintString();
19747 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
19748 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
19749 if (clobbersFlagRegisters(AsmPieces))
19750 return IntrinsicLowering::LowerToByteSwap(CI);
19754 if (CI->getType()->isIntegerTy(32) &&
19755 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
19756 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
19757 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
19758 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
19760 const std::string &ConstraintsStr = IA->getConstraintString();
19761 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
19762 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
19763 if (clobbersFlagRegisters(AsmPieces))
19764 return IntrinsicLowering::LowerToByteSwap(CI);
19767 if (CI->getType()->isIntegerTy(64)) {
19768 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
19769 if (Constraints.size() >= 2 &&
19770 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
19771 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
19772 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
19773 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
19774 matchAsm(AsmPieces[1], "bswap", "%edx") &&
19775 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
19776 return IntrinsicLowering::LowerToByteSwap(CI);
19784 /// getConstraintType - Given a constraint letter, return the type of
19785 /// constraint it is for this target.
19786 X86TargetLowering::ConstraintType
19787 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
19788 if (Constraint.size() == 1) {
19789 switch (Constraint[0]) {
19800 return C_RegisterClass;
19824 return TargetLowering::getConstraintType(Constraint);
19827 /// Examine constraint type and operand type and determine a weight value.
19828 /// This object must already have been set up with the operand type
19829 /// and the current alternative constraint selected.
19830 TargetLowering::ConstraintWeight
19831 X86TargetLowering::getSingleConstraintMatchWeight(
19832 AsmOperandInfo &info, const char *constraint) const {
19833 ConstraintWeight weight = CW_Invalid;
19834 Value *CallOperandVal = info.CallOperandVal;
19835 // If we don't have a value, we can't do a match,
19836 // but allow it at the lowest weight.
19837 if (CallOperandVal == NULL)
19839 Type *type = CallOperandVal->getType();
19840 // Look at the constraint type.
19841 switch (*constraint) {
19843 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
19854 if (CallOperandVal->getType()->isIntegerTy())
19855 weight = CW_SpecificReg;
19860 if (type->isFloatingPointTy())
19861 weight = CW_SpecificReg;
19864 if (type->isX86_MMXTy() && Subtarget->hasMMX())
19865 weight = CW_SpecificReg;
19869 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
19870 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
19871 weight = CW_Register;
19874 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
19875 if (C->getZExtValue() <= 31)
19876 weight = CW_Constant;
19880 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19881 if (C->getZExtValue() <= 63)
19882 weight = CW_Constant;
19886 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19887 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
19888 weight = CW_Constant;
19892 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19893 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
19894 weight = CW_Constant;
19898 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19899 if (C->getZExtValue() <= 3)
19900 weight = CW_Constant;
19904 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19905 if (C->getZExtValue() <= 0xff)
19906 weight = CW_Constant;
19911 if (dyn_cast<ConstantFP>(CallOperandVal)) {
19912 weight = CW_Constant;
19916 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19917 if ((C->getSExtValue() >= -0x80000000LL) &&
19918 (C->getSExtValue() <= 0x7fffffffLL))
19919 weight = CW_Constant;
19923 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19924 if (C->getZExtValue() <= 0xffffffff)
19925 weight = CW_Constant;
19932 /// LowerXConstraint - try to replace an X constraint, which matches anything,
19933 /// with another that has more specific requirements based on the type of the
19934 /// corresponding operand.
19935 const char *X86TargetLowering::
19936 LowerXConstraint(EVT ConstraintVT) const {
19937 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
19938 // 'f' like normal targets.
19939 if (ConstraintVT.isFloatingPoint()) {
19940 if (Subtarget->hasSSE2())
19942 if (Subtarget->hasSSE1())
19946 return TargetLowering::LowerXConstraint(ConstraintVT);
19949 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
19950 /// vector. If it is invalid, don't add anything to Ops.
19951 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
19952 std::string &Constraint,
19953 std::vector<SDValue>&Ops,
19954 SelectionDAG &DAG) const {
19955 SDValue Result(0, 0);
19957 // Only support length 1 constraints for now.
19958 if (Constraint.length() > 1) return;
19960 char ConstraintLetter = Constraint[0];
19961 switch (ConstraintLetter) {
19964 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19965 if (C->getZExtValue() <= 31) {
19966 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19972 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19973 if (C->getZExtValue() <= 63) {
19974 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19980 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19981 if (isInt<8>(C->getSExtValue())) {
19982 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19988 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19989 if (C->getZExtValue() <= 255) {
19990 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19996 // 32-bit signed value
19997 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19998 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
19999 C->getSExtValue())) {
20000 // Widen to 64 bits here to get it sign extended.
20001 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
20004 // FIXME gcc accepts some relocatable values here too, but only in certain
20005 // memory models; it's complicated.
20010 // 32-bit unsigned value
20011 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
20012 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
20013 C->getZExtValue())) {
20014 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
20018 // FIXME gcc accepts some relocatable values here too, but only in certain
20019 // memory models; it's complicated.
20023 // Literal immediates are always ok.
20024 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
20025 // Widen to 64 bits here to get it sign extended.
20026 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
20030 // In any sort of PIC mode addresses need to be computed at runtime by
20031 // adding in a register or some sort of table lookup. These can't
20032 // be used as immediates.
20033 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
20036 // If we are in non-pic codegen mode, we allow the address of a global (with
20037 // an optional displacement) to be used with 'i'.
20038 GlobalAddressSDNode *GA = 0;
20039 int64_t Offset = 0;
20041 // Match either (GA), (GA+C), (GA+C1+C2), etc.
20043 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
20044 Offset += GA->getOffset();
20046 } else if (Op.getOpcode() == ISD::ADD) {
20047 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
20048 Offset += C->getZExtValue();
20049 Op = Op.getOperand(0);
20052 } else if (Op.getOpcode() == ISD::SUB) {
20053 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
20054 Offset += -C->getZExtValue();
20055 Op = Op.getOperand(0);
20060 // Otherwise, this isn't something we can handle, reject it.
20064 const GlobalValue *GV = GA->getGlobal();
20065 // If we require an extra load to get this address, as in PIC mode, we
20066 // can't accept it.
20067 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
20068 getTargetMachine())))
20071 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
20072 GA->getValueType(0), Offset);
20077 if (Result.getNode()) {
20078 Ops.push_back(Result);
20081 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
20084 std::pair<unsigned, const TargetRegisterClass*>
20085 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
20087 // First, see if this is a constraint that directly corresponds to an LLVM
20089 if (Constraint.size() == 1) {
20090 // GCC Constraint Letters
20091 switch (Constraint[0]) {
20093 // TODO: Slight differences here in allocation order and leaving
20094 // RIP in the class. Do they matter any more here than they do
20095 // in the normal allocation?
20096 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
20097 if (Subtarget->is64Bit()) {
20098 if (VT == MVT::i32 || VT == MVT::f32)
20099 return std::make_pair(0U, &X86::GR32RegClass);
20100 if (VT == MVT::i16)
20101 return std::make_pair(0U, &X86::GR16RegClass);
20102 if (VT == MVT::i8 || VT == MVT::i1)
20103 return std::make_pair(0U, &X86::GR8RegClass);
20104 if (VT == MVT::i64 || VT == MVT::f64)
20105 return std::make_pair(0U, &X86::GR64RegClass);
20108 // 32-bit fallthrough
20109 case 'Q': // Q_REGS
20110 if (VT == MVT::i32 || VT == MVT::f32)
20111 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
20112 if (VT == MVT::i16)
20113 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
20114 if (VT == MVT::i8 || VT == MVT::i1)
20115 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
20116 if (VT == MVT::i64)
20117 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
20119 case 'r': // GENERAL_REGS
20120 case 'l': // INDEX_REGS
20121 if (VT == MVT::i8 || VT == MVT::i1)
20122 return std::make_pair(0U, &X86::GR8RegClass);
20123 if (VT == MVT::i16)
20124 return std::make_pair(0U, &X86::GR16RegClass);
20125 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
20126 return std::make_pair(0U, &X86::GR32RegClass);
20127 return std::make_pair(0U, &X86::GR64RegClass);
20128 case 'R': // LEGACY_REGS
20129 if (VT == MVT::i8 || VT == MVT::i1)
20130 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
20131 if (VT == MVT::i16)
20132 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
20133 if (VT == MVT::i32 || !Subtarget->is64Bit())
20134 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
20135 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
20136 case 'f': // FP Stack registers.
20137 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
20138 // value to the correct fpstack register class.
20139 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
20140 return std::make_pair(0U, &X86::RFP32RegClass);
20141 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
20142 return std::make_pair(0U, &X86::RFP64RegClass);
20143 return std::make_pair(0U, &X86::RFP80RegClass);
20144 case 'y': // MMX_REGS if MMX allowed.
20145 if (!Subtarget->hasMMX()) break;
20146 return std::make_pair(0U, &X86::VR64RegClass);
20147 case 'Y': // SSE_REGS if SSE2 allowed
20148 if (!Subtarget->hasSSE2()) break;
20150 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
20151 if (!Subtarget->hasSSE1()) break;
20153 switch (VT.SimpleTy) {
20155 // Scalar SSE types.
20158 return std::make_pair(0U, &X86::FR32RegClass);
20161 return std::make_pair(0U, &X86::FR64RegClass);
20169 return std::make_pair(0U, &X86::VR128RegClass);
20177 return std::make_pair(0U, &X86::VR256RegClass);
20182 return std::make_pair(0U, &X86::VR512RegClass);
20188 // Use the default implementation in TargetLowering to convert the register
20189 // constraint into a member of a register class.
20190 std::pair<unsigned, const TargetRegisterClass*> Res;
20191 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
20193 // Not found as a standard register?
20194 if (Res.second == 0) {
20195 // Map st(0) -> st(7) -> ST0
20196 if (Constraint.size() == 7 && Constraint[0] == '{' &&
20197 tolower(Constraint[1]) == 's' &&
20198 tolower(Constraint[2]) == 't' &&
20199 Constraint[3] == '(' &&
20200 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
20201 Constraint[5] == ')' &&
20202 Constraint[6] == '}') {
20204 Res.first = X86::ST0+Constraint[4]-'0';
20205 Res.second = &X86::RFP80RegClass;
20209 // GCC allows "st(0)" to be called just plain "st".
20210 if (StringRef("{st}").equals_lower(Constraint)) {
20211 Res.first = X86::ST0;
20212 Res.second = &X86::RFP80RegClass;
20217 if (StringRef("{flags}").equals_lower(Constraint)) {
20218 Res.first = X86::EFLAGS;
20219 Res.second = &X86::CCRRegClass;
20223 // 'A' means EAX + EDX.
20224 if (Constraint == "A") {
20225 Res.first = X86::EAX;
20226 Res.second = &X86::GR32_ADRegClass;
20232 // Otherwise, check to see if this is a register class of the wrong value
20233 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
20234 // turn into {ax},{dx}.
20235 if (Res.second->hasType(VT))
20236 return Res; // Correct type already, nothing to do.
20238 // All of the single-register GCC register classes map their values onto
20239 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
20240 // really want an 8-bit or 32-bit register, map to the appropriate register
20241 // class and return the appropriate register.
20242 if (Res.second == &X86::GR16RegClass) {
20243 if (VT == MVT::i8 || VT == MVT::i1) {
20244 unsigned DestReg = 0;
20245 switch (Res.first) {
20247 case X86::AX: DestReg = X86::AL; break;
20248 case X86::DX: DestReg = X86::DL; break;
20249 case X86::CX: DestReg = X86::CL; break;
20250 case X86::BX: DestReg = X86::BL; break;
20253 Res.first = DestReg;
20254 Res.second = &X86::GR8RegClass;
20256 } else if (VT == MVT::i32 || VT == MVT::f32) {
20257 unsigned DestReg = 0;
20258 switch (Res.first) {
20260 case X86::AX: DestReg = X86::EAX; break;
20261 case X86::DX: DestReg = X86::EDX; break;
20262 case X86::CX: DestReg = X86::ECX; break;
20263 case X86::BX: DestReg = X86::EBX; break;
20264 case X86::SI: DestReg = X86::ESI; break;
20265 case X86::DI: DestReg = X86::EDI; break;
20266 case X86::BP: DestReg = X86::EBP; break;
20267 case X86::SP: DestReg = X86::ESP; break;
20270 Res.first = DestReg;
20271 Res.second = &X86::GR32RegClass;
20273 } else if (VT == MVT::i64 || VT == MVT::f64) {
20274 unsigned DestReg = 0;
20275 switch (Res.first) {
20277 case X86::AX: DestReg = X86::RAX; break;
20278 case X86::DX: DestReg = X86::RDX; break;
20279 case X86::CX: DestReg = X86::RCX; break;
20280 case X86::BX: DestReg = X86::RBX; break;
20281 case X86::SI: DestReg = X86::RSI; break;
20282 case X86::DI: DestReg = X86::RDI; break;
20283 case X86::BP: DestReg = X86::RBP; break;
20284 case X86::SP: DestReg = X86::RSP; break;
20287 Res.first = DestReg;
20288 Res.second = &X86::GR64RegClass;
20291 } else if (Res.second == &X86::FR32RegClass ||
20292 Res.second == &X86::FR64RegClass ||
20293 Res.second == &X86::VR128RegClass ||
20294 Res.second == &X86::VR256RegClass ||
20295 Res.second == &X86::FR32XRegClass ||
20296 Res.second == &X86::FR64XRegClass ||
20297 Res.second == &X86::VR128XRegClass ||
20298 Res.second == &X86::VR256XRegClass ||
20299 Res.second == &X86::VR512RegClass) {
20300 // Handle references to XMM physical registers that got mapped into the
20301 // wrong class. This can happen with constraints like {xmm0} where the
20302 // target independent register mapper will just pick the first match it can
20303 // find, ignoring the required type.
20305 if (VT == MVT::f32 || VT == MVT::i32)
20306 Res.second = &X86::FR32RegClass;
20307 else if (VT == MVT::f64 || VT == MVT::i64)
20308 Res.second = &X86::FR64RegClass;
20309 else if (X86::VR128RegClass.hasType(VT))
20310 Res.second = &X86::VR128RegClass;
20311 else if (X86::VR256RegClass.hasType(VT))
20312 Res.second = &X86::VR256RegClass;
20313 else if (X86::VR512RegClass.hasType(VT))
20314 Res.second = &X86::VR512RegClass;