1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86ISelLowering.h"
17 #include "X86TargetMachine.h"
18 #include "llvm/CallingConv.h"
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SSARegMap.h"
24 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/Support/CommandLine.h"
29 static cl::opt<bool> EnableFastCC("enable-x86-fastcc", cl::Hidden,
30 cl::desc("Enable fastcc on X86"));
32 X86TargetLowering::X86TargetLowering(TargetMachine &TM)
33 : TargetLowering(TM) {
34 // Set up the TargetLowering object.
36 // X86 is weird, it always uses i8 for shift amounts and setcc results.
37 setShiftAmountType(MVT::i8);
38 setSetCCResultType(MVT::i8);
39 setSetCCResultContents(ZeroOrOneSetCCResult);
40 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
42 // Set up the register classes.
43 addRegisterClass(MVT::i8, X86::R8RegisterClass);
44 addRegisterClass(MVT::i16, X86::R16RegisterClass);
45 addRegisterClass(MVT::i32, X86::R32RegisterClass);
47 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
49 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
50 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
51 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
52 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
54 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
56 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
57 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
60 // We can handle SINT_TO_FP and FP_TO_SINT from/TO i64 even though i64
62 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
63 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
64 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
65 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
68 // Handle FP_TO_UINT by promoting the destination to a larger signed
70 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
71 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
72 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
75 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
77 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
79 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
80 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
81 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
84 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
86 setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
87 setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
88 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
89 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
90 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
91 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
92 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
93 setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
94 setOperationAction(ISD::FREM , MVT::f64 , Expand);
95 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
96 setOperationAction(ISD::CTTZ , MVT::i8 , Expand);
97 setOperationAction(ISD::CTLZ , MVT::i8 , Expand);
98 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
99 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
100 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
101 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
102 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
103 setOperationAction(ISD::CTLZ , MVT::i32 , Expand);
104 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
106 setOperationAction(ISD::READIO , MVT::i1 , Expand);
107 setOperationAction(ISD::READIO , MVT::i8 , Expand);
108 setOperationAction(ISD::READIO , MVT::i16 , Expand);
109 setOperationAction(ISD::READIO , MVT::i32 , Expand);
110 setOperationAction(ISD::WRITEIO , MVT::i1 , Expand);
111 setOperationAction(ISD::WRITEIO , MVT::i8 , Expand);
112 setOperationAction(ISD::WRITEIO , MVT::i16 , Expand);
113 setOperationAction(ISD::WRITEIO , MVT::i32 , Expand);
115 // These should be promoted to a larger select which is supported.
116 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
117 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
118 // X86 wants to expand cmov itself.
120 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
121 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
124 // We don't have line number support yet.
125 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
128 // Set up the FP register classes.
129 addRegisterClass(MVT::f32, X86::V4F4RegisterClass);
130 addRegisterClass(MVT::f64, X86::V2F8RegisterClass);
132 // SSE has no load+extend ops
133 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
134 setOperationAction(ISD::ZEXTLOAD, MVT::f32, Expand);
136 // SSE has no i16 to fp conversion, only i32
137 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
138 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
140 // Expand FP_TO_UINT into a select.
141 // FIXME: We would like to use a Custom expander here eventually to do
142 // the optimal thing for SSE vs. the default expansion in the legalizer.
143 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
145 // We don't support sin/cos/sqrt/fmod
146 setOperationAction(ISD::FSIN , MVT::f64, Expand);
147 setOperationAction(ISD::FCOS , MVT::f64, Expand);
148 setOperationAction(ISD::FABS , MVT::f64, Expand);
149 setOperationAction(ISD::FNEG , MVT::f64, Expand);
150 setOperationAction(ISD::FREM , MVT::f64, Expand);
151 setOperationAction(ISD::FSIN , MVT::f32, Expand);
152 setOperationAction(ISD::FCOS , MVT::f32, Expand);
153 setOperationAction(ISD::FABS , MVT::f32, Expand);
154 setOperationAction(ISD::FNEG , MVT::f32, Expand);
155 setOperationAction(ISD::FREM , MVT::f32, Expand);
157 addLegalFPImmediate(+0.0); // xorps / xorpd
159 // Set up the FP register classes.
160 addRegisterClass(MVT::f64, X86::RFPRegisterClass);
163 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
164 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
167 addLegalFPImmediate(+0.0); // FLD0
168 addLegalFPImmediate(+1.0); // FLD1
169 addLegalFPImmediate(-0.0); // FLD0/FCHS
170 addLegalFPImmediate(-1.0); // FLD1/FCHS
172 computeRegisterProperties();
174 maxStoresPerMemSet = 8; // For %llvm.memset -> sequence of stores
175 maxStoresPerMemCpy = 8; // For %llvm.memcpy -> sequence of stores
176 maxStoresPerMemMove = 8; // For %llvm.memmove -> sequence of stores
177 allowUnalignedMemoryAccesses = true; // x86 supports it!
180 std::vector<SDOperand>
181 X86TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
182 if (F.getCallingConv() == CallingConv::Fast && EnableFastCC)
183 return LowerFastCCArguments(F, DAG);
184 return LowerCCCArguments(F, DAG);
187 std::pair<SDOperand, SDOperand>
188 X86TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
189 bool isVarArg, unsigned CallingConv,
191 SDOperand Callee, ArgListTy &Args,
193 assert((!isVarArg || CallingConv == CallingConv::C) &&
194 "Only C takes varargs!");
195 if (CallingConv == CallingConv::Fast && EnableFastCC)
196 return LowerFastCCCallTo(Chain, RetTy, isTailCall, Callee, Args, DAG);
197 return LowerCCCCallTo(Chain, RetTy, isVarArg, isTailCall, Callee, Args, DAG);
200 SDOperand X86TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
203 return DAG.getNode(ISD::RET, MVT::Other, Chain, Op);
206 MVT::ValueType OpVT = Op.getValueType();
208 default: assert(0 && "Unknown type to return!");
210 Copy = DAG.getCopyToReg(Chain, X86::EAX, Op, SDOperand());
213 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
214 DAG.getConstant(1, MVT::i32));
215 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
216 DAG.getConstant(0, MVT::i32));
217 Copy = DAG.getCopyToReg(Chain, X86::EAX, Hi, SDOperand());
218 Copy = DAG.getCopyToReg(Copy, X86::EDX, Lo, Copy.getValue(1));
222 assert(X86ScalarSSE && "MVT::f32 only legal with scalar sse fp");
223 // Fallthrough intended
226 std::vector<MVT::ValueType> Tys;
227 Tys.push_back(MVT::Other);
228 Tys.push_back(MVT::Flag);
229 std::vector<SDOperand> Ops;
230 Ops.push_back(Chain);
232 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
234 // Spill the value to memory and reload it into top of stack.
235 unsigned Size = MVT::getSizeInBits(OpVT)/8;
236 MachineFunction &MF = DAG.getMachineFunction();
237 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
238 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
239 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Op,
240 StackSlot, DAG.getSrcValue(NULL));
241 std::vector<MVT::ValueType> Tys;
242 Tys.push_back(MVT::f64);
243 Tys.push_back(MVT::Other);
244 std::vector<SDOperand> Ops;
245 Ops.push_back(Chain);
246 Ops.push_back(StackSlot);
247 Ops.push_back(DAG.getValueType(OpVT));
248 Copy = DAG.getNode(X86ISD::FLD, Tys, Ops);
250 Tys.push_back(MVT::Other);
251 Tys.push_back(MVT::Flag);
253 Ops.push_back(Copy.getValue(1));
255 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
259 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
262 //===----------------------------------------------------------------------===//
263 // C Calling Convention implementation
264 //===----------------------------------------------------------------------===//
266 std::vector<SDOperand>
267 X86TargetLowering::LowerCCCArguments(Function &F, SelectionDAG &DAG) {
268 std::vector<SDOperand> ArgValues;
270 MachineFunction &MF = DAG.getMachineFunction();
271 MachineFrameInfo *MFI = MF.getFrameInfo();
273 // Add DAG nodes to load the arguments... On entry to a function on the X86,
274 // the stack frame looks like this:
276 // [ESP] -- return address
277 // [ESP + 4] -- first argument (leftmost lexically)
278 // [ESP + 8] -- second argument, if first argument is four bytes in size
281 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
282 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
283 MVT::ValueType ObjectVT = getValueType(I->getType());
284 unsigned ArgIncrement = 4;
287 default: assert(0 && "Unhandled argument type!");
289 case MVT::i8: ObjSize = 1; break;
290 case MVT::i16: ObjSize = 2; break;
291 case MVT::i32: ObjSize = 4; break;
292 case MVT::i64: ObjSize = ArgIncrement = 8; break;
293 case MVT::f32: ObjSize = 4; break;
294 case MVT::f64: ObjSize = ArgIncrement = 8; break;
296 // Create the frame index object for this incoming parameter...
297 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
299 // Create the SelectionDAG nodes corresponding to a load from this parameter
300 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
302 // Don't codegen dead arguments. FIXME: remove this check when we can nuke
306 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
307 DAG.getSrcValue(NULL));
309 if (MVT::isInteger(ObjectVT))
310 ArgValue = DAG.getConstant(0, ObjectVT);
312 ArgValue = DAG.getConstantFP(0, ObjectVT);
314 ArgValues.push_back(ArgValue);
316 ArgOffset += ArgIncrement; // Move on to the next argument...
319 // If the function takes variable number of arguments, make a frame index for
320 // the start of the first vararg value... for expansion of llvm.va_start.
322 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
323 ReturnAddrIndex = 0; // No return address slot generated yet.
324 BytesToPopOnReturn = 0; // Callee pops nothing.
325 BytesCallerReserves = ArgOffset;
327 // Finally, inform the code generator which regs we return values in.
328 switch (getValueType(F.getReturnType())) {
329 default: assert(0 && "Unknown type!");
330 case MVT::isVoid: break;
335 MF.addLiveOut(X86::EAX);
338 MF.addLiveOut(X86::EAX);
339 MF.addLiveOut(X86::EDX);
343 MF.addLiveOut(X86::ST0);
349 std::pair<SDOperand, SDOperand>
350 X86TargetLowering::LowerCCCCallTo(SDOperand Chain, const Type *RetTy,
351 bool isVarArg, bool isTailCall,
352 SDOperand Callee, ArgListTy &Args,
354 // Count how many bytes are to be pushed on the stack.
355 unsigned NumBytes = 0;
359 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
360 DAG.getConstant(0, getPointerTy()));
362 for (unsigned i = 0, e = Args.size(); i != e; ++i)
363 switch (getValueType(Args[i].second)) {
364 default: assert(0 && "Unknown value type!");
378 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
379 DAG.getConstant(NumBytes, getPointerTy()));
381 // Arguments go on the stack in reverse order, as specified by the ABI.
382 unsigned ArgOffset = 0;
383 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
385 std::vector<SDOperand> Stores;
387 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
388 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
389 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
391 switch (getValueType(Args[i].second)) {
392 default: assert(0 && "Unexpected ValueType for argument!");
396 // Promote the integer to 32 bits. If the input type is signed use a
397 // sign extend, otherwise use a zero extend.
398 if (Args[i].second->isSigned())
399 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
401 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
406 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
407 Args[i].first, PtrOff,
408 DAG.getSrcValue(NULL)));
413 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
414 Args[i].first, PtrOff,
415 DAG.getSrcValue(NULL)));
420 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
423 std::vector<MVT::ValueType> RetVals;
424 MVT::ValueType RetTyVT = getValueType(RetTy);
425 RetVals.push_back(MVT::Other);
427 // The result values produced have to be legal. Promote the result.
429 case MVT::isVoid: break;
431 RetVals.push_back(RetTyVT);
436 RetVals.push_back(MVT::i32);
440 RetVals.push_back(MVT::f32);
442 RetVals.push_back(MVT::f64);
445 RetVals.push_back(MVT::i32);
446 RetVals.push_back(MVT::i32);
449 std::vector<SDOperand> Ops;
450 Ops.push_back(Chain);
451 Ops.push_back(Callee);
452 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
453 Ops.push_back(DAG.getConstant(0, getPointerTy()));
454 SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
456 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall);
460 case MVT::isVoid: break;
462 ResultVal = TheCall.getValue(1);
467 ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1));
470 // FIXME: we would really like to remember that this FP_ROUND operation is
471 // okay to eliminate if we allow excess FP precision.
472 ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1));
475 ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1),
476 TheCall.getValue(2));
480 return std::make_pair(ResultVal, Chain);
484 X86TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
485 Value *VAListV, SelectionDAG &DAG) {
486 // vastart just stores the address of the VarArgsFrameIndex slot.
487 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
488 return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
489 DAG.getSrcValue(VAListV));
493 std::pair<SDOperand,SDOperand>
494 X86TargetLowering::LowerVAArg(SDOperand Chain, SDOperand VAListP,
495 Value *VAListV, const Type *ArgTy,
497 MVT::ValueType ArgVT = getValueType(ArgTy);
498 SDOperand Val = DAG.getLoad(MVT::i32, Chain,
499 VAListP, DAG.getSrcValue(VAListV));
500 SDOperand Result = DAG.getLoad(ArgVT, Chain, Val,
501 DAG.getSrcValue(NULL));
503 if (ArgVT == MVT::i32)
506 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
507 "Other types should have been promoted for varargs!");
510 Val = DAG.getNode(ISD::ADD, Val.getValueType(), Val,
511 DAG.getConstant(Amt, Val.getValueType()));
512 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
513 Val, VAListP, DAG.getSrcValue(VAListV));
514 return std::make_pair(Result, Chain);
517 //===----------------------------------------------------------------------===//
518 // Fast Calling Convention implementation
519 //===----------------------------------------------------------------------===//
521 // The X86 'fast' calling convention passes up to two integer arguments in
522 // registers (an appropriate portion of EAX/EDX), passes arguments in C order,
523 // and requires that the callee pop its arguments off the stack (allowing proper
524 // tail calls), and has the same return value conventions as C calling convs.
526 // This calling convention always arranges for the callee pop value to be 8n+4
527 // bytes, which is needed for tail recursion elimination and stack alignment
530 // Note that this can be enhanced in the future to pass fp vals in registers
531 // (when we have a global fp allocator) and do other tricks.
534 /// AddLiveIn - This helper function adds the specified physical register to the
535 /// MachineFunction as a live in value. It also creates a corresponding virtual
537 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
538 TargetRegisterClass *RC) {
539 assert(RC->contains(PReg) && "Not the correct regclass!");
540 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
541 MF.addLiveIn(PReg, VReg);
546 std::vector<SDOperand>
547 X86TargetLowering::LowerFastCCArguments(Function &F, SelectionDAG &DAG) {
548 std::vector<SDOperand> ArgValues;
550 MachineFunction &MF = DAG.getMachineFunction();
551 MachineFrameInfo *MFI = MF.getFrameInfo();
553 // Add DAG nodes to load the arguments... On entry to a function the stack
554 // frame looks like this:
556 // [ESP] -- return address
557 // [ESP + 4] -- first nonreg argument (leftmost lexically)
558 // [ESP + 8] -- second nonreg argument, if first argument is 4 bytes in size
560 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
562 // Keep track of the number of integer regs passed so far. This can be either
563 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
565 unsigned NumIntRegs = 0;
567 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
568 MVT::ValueType ObjectVT = getValueType(I->getType());
569 unsigned ArgIncrement = 4;
570 unsigned ObjSize = 0;
574 default: assert(0 && "Unhandled argument type!");
577 if (NumIntRegs < 2) {
578 if (!I->use_empty()) {
579 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::AL,
580 X86::R8RegisterClass);
581 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i8);
582 DAG.setRoot(ArgValue.getValue(1));
591 if (NumIntRegs < 2) {
592 if (!I->use_empty()) {
593 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::AX,
594 X86::R16RegisterClass);
595 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i16);
596 DAG.setRoot(ArgValue.getValue(1));
604 if (NumIntRegs < 2) {
605 if (!I->use_empty()) {
606 unsigned VReg = AddLiveIn(MF,NumIntRegs ? X86::EDX : X86::EAX,
607 X86::R32RegisterClass);
608 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
609 DAG.setRoot(ArgValue.getValue(1));
617 if (NumIntRegs == 0) {
618 if (!I->use_empty()) {
619 unsigned BotReg = AddLiveIn(MF, X86::EAX, X86::R32RegisterClass);
620 unsigned TopReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
622 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
623 SDOperand Hi = DAG.getCopyFromReg(Low.getValue(1), TopReg, MVT::i32);
624 DAG.setRoot(Hi.getValue(1));
626 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
630 } else if (NumIntRegs == 1) {
631 if (!I->use_empty()) {
632 unsigned BotReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
633 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
634 DAG.setRoot(Low.getValue(1));
636 // Load the high part from memory.
637 // Create the frame index object for this incoming parameter...
638 int FI = MFI->CreateFixedObject(4, ArgOffset);
639 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
640 SDOperand Hi = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
641 DAG.getSrcValue(NULL));
642 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
648 ObjSize = ArgIncrement = 8;
650 case MVT::f32: ObjSize = 4; break;
651 case MVT::f64: ObjSize = ArgIncrement = 8; break;
654 // Don't codegen dead arguments. FIXME: remove this check when we can nuke
656 if (ObjSize && !I->use_empty()) {
657 // Create the frame index object for this incoming parameter...
658 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
660 // Create the SelectionDAG nodes corresponding to a load from this
662 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
664 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
665 DAG.getSrcValue(NULL));
666 } else if (ArgValue.Val == 0) {
667 if (MVT::isInteger(ObjectVT))
668 ArgValue = DAG.getConstant(0, ObjectVT);
670 ArgValue = DAG.getConstantFP(0, ObjectVT);
672 ArgValues.push_back(ArgValue);
675 ArgOffset += ArgIncrement; // Move on to the next argument.
678 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
679 // arguments and the arguments after the retaddr has been pushed are aligned.
680 if ((ArgOffset & 7) == 0)
683 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
684 ReturnAddrIndex = 0; // No return address slot generated yet.
685 BytesToPopOnReturn = ArgOffset; // Callee pops all stack arguments.
686 BytesCallerReserves = 0;
688 // Finally, inform the code generator which regs we return values in.
689 switch (getValueType(F.getReturnType())) {
690 default: assert(0 && "Unknown type!");
691 case MVT::isVoid: break;
696 MF.addLiveOut(X86::EAX);
699 MF.addLiveOut(X86::EAX);
700 MF.addLiveOut(X86::EDX);
704 MF.addLiveOut(X86::ST0);
710 std::pair<SDOperand, SDOperand>
711 X86TargetLowering::LowerFastCCCallTo(SDOperand Chain, const Type *RetTy,
712 bool isTailCall, SDOperand Callee,
713 ArgListTy &Args, SelectionDAG &DAG) {
714 // Count how many bytes are to be pushed on the stack.
715 unsigned NumBytes = 0;
717 // Keep track of the number of integer regs passed so far. This can be either
718 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
720 unsigned NumIntRegs = 0;
722 for (unsigned i = 0, e = Args.size(); i != e; ++i)
723 switch (getValueType(Args[i].second)) {
724 default: assert(0 && "Unknown value type!");
729 if (NumIntRegs < 2) {
738 if (NumIntRegs == 0) {
741 } else if (NumIntRegs == 1) {
753 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
754 // arguments and the arguments after the retaddr has been pushed are aligned.
755 if ((NumBytes & 7) == 0)
758 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
759 DAG.getConstant(NumBytes, getPointerTy()));
761 // Arguments go on the stack in reverse order, as specified by the ABI.
762 unsigned ArgOffset = 0;
763 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
766 std::vector<SDOperand> Stores;
767 std::vector<SDOperand> RegValuesToPass;
768 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
769 switch (getValueType(Args[i].second)) {
770 default: assert(0 && "Unexpected ValueType for argument!");
775 if (NumIntRegs < 2) {
776 RegValuesToPass.push_back(Args[i].first);
782 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
783 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
784 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
785 Args[i].first, PtrOff,
786 DAG.getSrcValue(NULL)));
791 if (NumIntRegs < 2) { // Can pass part of it in regs?
792 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
793 Args[i].first, DAG.getConstant(1, MVT::i32));
794 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
795 Args[i].first, DAG.getConstant(0, MVT::i32));
796 RegValuesToPass.push_back(Lo);
798 if (NumIntRegs < 2) { // Pass both parts in regs?
799 RegValuesToPass.push_back(Hi);
802 // Pass the high part in memory.
803 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
804 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
805 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
806 Hi, PtrOff, DAG.getSrcValue(NULL)));
813 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
814 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
815 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
816 Args[i].first, PtrOff,
817 DAG.getSrcValue(NULL)));
823 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
825 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
826 // arguments and the arguments after the retaddr has been pushed are aligned.
827 if ((ArgOffset & 7) == 0)
830 std::vector<MVT::ValueType> RetVals;
831 MVT::ValueType RetTyVT = getValueType(RetTy);
833 RetVals.push_back(MVT::Other);
835 // The result values produced have to be legal. Promote the result.
837 case MVT::isVoid: break;
839 RetVals.push_back(RetTyVT);
844 RetVals.push_back(MVT::i32);
848 RetVals.push_back(MVT::f32);
850 RetVals.push_back(MVT::f64);
853 RetVals.push_back(MVT::i32);
854 RetVals.push_back(MVT::i32);
858 std::vector<SDOperand> Ops;
859 Ops.push_back(Chain);
860 Ops.push_back(Callee);
861 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
862 // Callee pops all arg values on the stack.
863 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
865 // Pass register arguments as needed.
866 Ops.insert(Ops.end(), RegValuesToPass.begin(), RegValuesToPass.end());
868 SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
870 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall);
874 case MVT::isVoid: break;
876 ResultVal = TheCall.getValue(1);
881 ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1));
884 // FIXME: we would really like to remember that this FP_ROUND operation is
885 // okay to eliminate if we allow excess FP precision.
886 ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1));
889 ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1),
890 TheCall.getValue(2));
894 return std::make_pair(ResultVal, Chain);
897 SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
898 if (ReturnAddrIndex == 0) {
899 // Set up a frame object for the return address.
900 MachineFunction &MF = DAG.getMachineFunction();
901 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
904 return DAG.getFrameIndex(ReturnAddrIndex, MVT::i32);
909 std::pair<SDOperand, SDOperand> X86TargetLowering::
910 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
913 if (Depth) // Depths > 0 not supported yet!
914 Result = DAG.getConstant(0, getPointerTy());
916 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
918 // Just load the return address
919 Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(), RetAddrFI,
920 DAG.getSrcValue(NULL));
922 Result = DAG.getNode(ISD::SUB, MVT::i32, RetAddrFI,
923 DAG.getConstant(4, MVT::i32));
925 return std::make_pair(Result, Chain);
928 //===----------------------------------------------------------------------===//
929 // X86 Custom Lowering Hooks
930 //===----------------------------------------------------------------------===//
932 /// LowerOperation - Provide custom lowering hooks for some operations.
934 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
935 switch (Op.getOpcode()) {
936 default: assert(0 && "Should not custom lower this!");
937 case ISD::SINT_TO_FP: {
938 assert(Op.getValueType() == MVT::f64 &&
939 Op.getOperand(0).getValueType() == MVT::i64 &&
940 "Unknown SINT_TO_FP to lower!");
941 // We lower sint64->FP into a store to a temporary stack slot, followed by a
943 MachineFunction &MF = DAG.getMachineFunction();
944 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
945 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
946 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
947 Op.getOperand(0), StackSlot, DAG.getSrcValue(NULL));
948 std::vector<MVT::ValueType> RTs;
949 RTs.push_back(MVT::f64);
950 RTs.push_back(MVT::Other);
951 std::vector<SDOperand> Ops;
952 Ops.push_back(Store);
953 Ops.push_back(StackSlot);
954 return DAG.getNode(X86ISD::FILD64m, RTs, Ops);
956 case ISD::FP_TO_SINT: {
957 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
958 Op.getOperand(0).getValueType() == MVT::f64 &&
959 "Unknown FP_TO_SINT to lower!");
960 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
962 MachineFunction &MF = DAG.getMachineFunction();
963 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
964 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
965 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
968 switch (Op.getValueType()) {
969 default: assert(0 && "Invalid FP_TO_SINT to lower!");
970 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
971 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
972 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
975 // Build the FP_TO_INT*_IN_MEM
976 std::vector<SDOperand> Ops;
977 Ops.push_back(DAG.getEntryNode());
978 Ops.push_back(Op.getOperand(0));
979 Ops.push_back(StackSlot);
980 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops);
983 return DAG.getLoad(Op.getValueType(), FIST, StackSlot,
984 DAG.getSrcValue(NULL));
986 case ISD::READCYCLECOUNTER: {
987 std::vector<MVT::ValueType> Tys;
988 Tys.push_back(MVT::Other);
989 Tys.push_back(MVT::Flag);
990 std::vector<SDOperand> Ops;
991 Ops.push_back(Op.getOperand(0));
992 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, Ops);
994 Ops.push_back(DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1)));
995 Ops.push_back(DAG.getCopyFromReg(Ops[0].getValue(1), X86::EDX,
996 MVT::i32, Ops[0].getValue(2)));
997 Ops.push_back(Ops[1].getValue(1));
998 Tys[0] = Tys[1] = MVT::i32;
999 Tys.push_back(MVT::Other);
1000 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
1003 SDOperand Cond = Op.getOperand(0);
1005 if (Cond.getOpcode() == ISD::SETCC) {
1006 CC = Cond.getOperand(2);
1007 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1008 Cond.getOperand(0), Cond.getOperand(1));
1010 CC = DAG.getCondCode(ISD::SETEQ);
1011 Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Cond, Cond);
1013 return DAG.getNode(X86ISD::CMOV, Op.getValueType(),
1014 Op.getOperand(1), Op.getOperand(2), CC, Cond);
1017 SDOperand Chain = Op.getOperand(0);
1018 SDOperand Cond = Op.getOperand(1);
1019 SDOperand Dest = Op.getOperand(2);
1021 // TODO: handle Cond == OR / AND / XOR
1022 if (Cond.getOpcode() == ISD::SETCC) {
1023 CC = Cond.getOperand(2);
1024 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1025 Cond.getOperand(0), Cond.getOperand(1));
1027 CC = DAG.getCondCode(ISD::SETNE);
1028 Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Cond, Cond);
1030 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
1031 Op.getOperand(0), Op.getOperand(2), CC, Cond);
1033 case ISD::GlobalAddress:
1034 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1035 // For Darwin, external and weak symbols are indirect, so we want to load
1036 // the value at address GV, not the value of GV itself. This means that
1037 // the GlobalAddress must be in the base or index register of the address,
1038 // not the GV offset field.
1039 if (getTargetMachine().
1040 getSubtarget<X86Subtarget>().getIndirectExternAndWeakGlobals() &&
1041 (GV->hasWeakLinkage() || GV->isExternal()))
1042 return DAG.getLoad(MVT::i32, DAG.getEntryNode(), Op,
1043 DAG.getSrcValue(NULL));
1050 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
1052 default: return NULL;
1053 case X86ISD::FILD64m: return "X86ISD::FILD64m";
1054 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
1055 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
1056 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
1057 case X86ISD::FLD: return "X86ISD::FLD";
1058 case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT";
1059 case X86ISD::CALL: return "X86ISD::CALL";
1060 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
1061 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
1062 case X86ISD::CMP: return "X86ISD::CMP";
1063 case X86ISD::TEST: return "X86ISD::TEST";
1064 case X86ISD::CMOV: return "X86ISD::CMOV";
1065 case X86ISD::BRCOND: return "X86ISD::BRCOND";
1066 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";