1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
17 #include "Utils/X86ShuffleDecode.h"
19 #include "X86InstrBuilder.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/VariadicFunction.h"
26 #include "llvm/CodeGen/IntrinsicLowering.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/IR/CallingConv.h"
34 #include "llvm/IR/Constants.h"
35 #include "llvm/IR/DerivedTypes.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/GlobalAlias.h"
38 #include "llvm/IR/GlobalVariable.h"
39 #include "llvm/IR/Instructions.h"
40 #include "llvm/IR/Intrinsics.h"
41 #include "llvm/IR/LLVMContext.h"
42 #include "llvm/MC/MCAsmInfo.h"
43 #include "llvm/MC/MCContext.h"
44 #include "llvm/MC/MCExpr.h"
45 #include "llvm/MC/MCSymbol.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
55 STATISTIC(NumTailCalls, "Number of tail calls");
57 // Forward declarations.
58 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
61 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
62 SelectionDAG &DAG, SDLoc dl,
63 unsigned vectorWidth) {
64 assert((vectorWidth == 128 || vectorWidth == 256) &&
65 "Unsupported vector width");
66 EVT VT = Vec.getValueType();
67 EVT ElVT = VT.getVectorElementType();
68 unsigned Factor = VT.getSizeInBits()/vectorWidth;
69 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
70 VT.getVectorNumElements()/Factor);
72 // Extract from UNDEF is UNDEF.
73 if (Vec.getOpcode() == ISD::UNDEF)
74 return DAG.getUNDEF(ResultVT);
76 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
77 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
79 // This is the index of the first element of the vectorWidth-bit chunk
81 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
84 // If the input is a buildvector just emit a smaller one.
85 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
86 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
87 Vec->op_begin()+NormalizedIdxVal, ElemsPerChunk);
89 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
90 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
96 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
97 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
98 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
99 /// instructions or a simple subregister reference. Idx is an index in the
100 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
101 /// lowering EXTRACT_VECTOR_ELT operations easier.
102 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
103 SelectionDAG &DAG, SDLoc dl) {
104 assert((Vec.getValueType().is256BitVector() ||
105 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
106 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
109 /// Generate a DAG to grab 256-bits from a 512-bit vector.
110 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
111 SelectionDAG &DAG, SDLoc dl) {
112 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
113 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
116 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
117 unsigned IdxVal, SelectionDAG &DAG,
118 SDLoc dl, unsigned vectorWidth) {
119 assert((vectorWidth == 128 || vectorWidth == 256) &&
120 "Unsupported vector width");
121 // Inserting UNDEF is Result
122 if (Vec.getOpcode() == ISD::UNDEF)
124 EVT VT = Vec.getValueType();
125 EVT ElVT = VT.getVectorElementType();
126 EVT ResultVT = Result.getValueType();
128 // Insert the relevant vectorWidth bits.
129 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
131 // This is the index of the first element of the vectorWidth-bit chunk
133 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
136 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
137 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
140 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
141 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
142 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
143 /// simple superregister reference. Idx is an index in the 128 bits
144 /// we want. It need not be aligned to a 128-bit bounday. That makes
145 /// lowering INSERT_VECTOR_ELT operations easier.
146 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
147 unsigned IdxVal, SelectionDAG &DAG,
149 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
150 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
153 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
154 unsigned IdxVal, SelectionDAG &DAG,
156 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
157 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
160 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
161 /// instructions. This is used because creating CONCAT_VECTOR nodes of
162 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
163 /// large BUILD_VECTORS.
164 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
165 unsigned NumElems, SelectionDAG &DAG,
167 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
168 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
171 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
172 unsigned NumElems, SelectionDAG &DAG,
174 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
175 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
178 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
179 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
180 bool is64Bit = Subtarget->is64Bit();
182 if (Subtarget->isTargetEnvMacho()) {
184 return new X86_64MachoTargetObjectFile();
185 return new TargetLoweringObjectFileMachO();
188 if (Subtarget->isTargetLinux())
189 return new X86LinuxTargetObjectFile();
190 if (Subtarget->isTargetELF())
191 return new TargetLoweringObjectFileELF();
192 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
193 return new TargetLoweringObjectFileCOFF();
194 llvm_unreachable("unknown subtarget type");
197 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
198 : TargetLowering(TM, createTLOF(TM)) {
199 Subtarget = &TM.getSubtarget<X86Subtarget>();
200 X86ScalarSSEf64 = Subtarget->hasSSE2();
201 X86ScalarSSEf32 = Subtarget->hasSSE1();
202 TD = getDataLayout();
204 resetOperationActions();
207 void X86TargetLowering::resetOperationActions() {
208 const TargetMachine &TM = getTargetMachine();
209 static bool FirstTimeThrough = true;
211 // If none of the target options have changed, then we don't need to reset the
212 // operation actions.
213 if (!FirstTimeThrough && TO == TM.Options) return;
215 if (!FirstTimeThrough) {
216 // Reinitialize the actions.
218 FirstTimeThrough = false;
223 // Set up the TargetLowering object.
224 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
226 // X86 is weird, it always uses i8 for shift amounts and setcc results.
227 setBooleanContents(ZeroOrOneBooleanContent);
228 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
229 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
231 // For 64-bit since we have so many registers use the ILP scheduler, for
232 // 32-bit code use the register pressure specific scheduling.
233 // For Atom, always use ILP scheduling.
234 if (Subtarget->isAtom())
235 setSchedulingPreference(Sched::ILP);
236 else if (Subtarget->is64Bit())
237 setSchedulingPreference(Sched::ILP);
239 setSchedulingPreference(Sched::RegPressure);
240 const X86RegisterInfo *RegInfo =
241 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
242 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
244 // Bypass expensive divides on Atom when compiling with O2
245 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
246 addBypassSlowDiv(32, 8);
247 if (Subtarget->is64Bit())
248 addBypassSlowDiv(64, 16);
251 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
252 // Setup Windows compiler runtime calls.
253 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
254 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
255 setLibcallName(RTLIB::SREM_I64, "_allrem");
256 setLibcallName(RTLIB::UREM_I64, "_aullrem");
257 setLibcallName(RTLIB::MUL_I64, "_allmul");
258 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
259 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
260 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
261 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
262 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
264 // The _ftol2 runtime function has an unusual calling conv, which
265 // is modeled by a special pseudo-instruction.
266 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
267 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
268 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
269 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
272 if (Subtarget->isTargetDarwin()) {
273 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
274 setUseUnderscoreSetJmp(false);
275 setUseUnderscoreLongJmp(false);
276 } else if (Subtarget->isTargetMingw()) {
277 // MS runtime is weird: it exports _setjmp, but longjmp!
278 setUseUnderscoreSetJmp(true);
279 setUseUnderscoreLongJmp(false);
281 setUseUnderscoreSetJmp(true);
282 setUseUnderscoreLongJmp(true);
285 // Set up the register classes.
286 addRegisterClass(MVT::i8, &X86::GR8RegClass);
287 addRegisterClass(MVT::i16, &X86::GR16RegClass);
288 addRegisterClass(MVT::i32, &X86::GR32RegClass);
289 if (Subtarget->is64Bit())
290 addRegisterClass(MVT::i64, &X86::GR64RegClass);
292 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
294 // We don't accept any truncstore of integer registers.
295 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
296 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
297 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
298 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
299 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
300 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
302 // SETOEQ and SETUNE require checking two conditions.
303 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
304 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
305 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
306 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
307 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
308 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
310 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
312 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
313 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
314 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
316 if (Subtarget->is64Bit()) {
317 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
318 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
319 } else if (!TM.Options.UseSoftFloat) {
320 // We have an algorithm for SSE2->double, and we turn this into a
321 // 64-bit FILD followed by conditional FADD for other targets.
322 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
323 // We have an algorithm for SSE2, and we turn this into a 64-bit
324 // FILD for other targets.
325 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
328 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
330 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
331 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
333 if (!TM.Options.UseSoftFloat) {
334 // SSE has no i16 to fp conversion, only i32
335 if (X86ScalarSSEf32) {
336 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
337 // f32 and f64 cases are Legal, f80 case is not
338 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
340 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
341 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
344 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
345 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
348 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
349 // are Legal, f80 is custom lowered.
350 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
351 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
353 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
355 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
356 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
358 if (X86ScalarSSEf32) {
359 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
360 // f32 and f64 cases are Legal, f80 case is not
361 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
363 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
364 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
367 // Handle FP_TO_UINT by promoting the destination to a larger signed
369 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
370 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
371 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
373 if (Subtarget->is64Bit()) {
374 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
375 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
376 } else if (!TM.Options.UseSoftFloat) {
377 // Since AVX is a superset of SSE3, only check for SSE here.
378 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
379 // Expand FP_TO_UINT into a select.
380 // FIXME: We would like to use a Custom expander here eventually to do
381 // the optimal thing for SSE vs. the default expansion in the legalizer.
382 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
384 // With SSE3 we can use fisttpll to convert to a signed i64; without
385 // SSE, we're stuck with a fistpll.
386 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
389 if (isTargetFTOL()) {
390 // Use the _ftol2 runtime function, which has a pseudo-instruction
391 // to handle its weird calling convention.
392 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
395 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
396 if (!X86ScalarSSEf64) {
397 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
398 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
399 if (Subtarget->is64Bit()) {
400 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
401 // Without SSE, i64->f64 goes through memory.
402 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
406 // Scalar integer divide and remainder are lowered to use operations that
407 // produce two results, to match the available instructions. This exposes
408 // the two-result form to trivial CSE, which is able to combine x/y and x%y
409 // into a single instruction.
411 // Scalar integer multiply-high is also lowered to use two-result
412 // operations, to match the available instructions. However, plain multiply
413 // (low) operations are left as Legal, as there are single-result
414 // instructions for this in x86. Using the two-result multiply instructions
415 // when both high and low results are needed must be arranged by dagcombine.
416 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
418 setOperationAction(ISD::MULHS, VT, Expand);
419 setOperationAction(ISD::MULHU, VT, Expand);
420 setOperationAction(ISD::SDIV, VT, Expand);
421 setOperationAction(ISD::UDIV, VT, Expand);
422 setOperationAction(ISD::SREM, VT, Expand);
423 setOperationAction(ISD::UREM, VT, Expand);
425 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
426 setOperationAction(ISD::ADDC, VT, Custom);
427 setOperationAction(ISD::ADDE, VT, Custom);
428 setOperationAction(ISD::SUBC, VT, Custom);
429 setOperationAction(ISD::SUBE, VT, Custom);
432 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
433 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
434 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
435 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
436 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
437 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
438 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
439 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
440 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
441 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
442 if (Subtarget->is64Bit())
443 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
444 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
445 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
446 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
447 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
448 setOperationAction(ISD::FREM , MVT::f32 , Expand);
449 setOperationAction(ISD::FREM , MVT::f64 , Expand);
450 setOperationAction(ISD::FREM , MVT::f80 , Expand);
451 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
453 // Promote the i8 variants and force them on up to i32 which has a shorter
455 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
456 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
457 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
458 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
459 if (Subtarget->hasBMI()) {
460 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
461 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
462 if (Subtarget->is64Bit())
463 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
465 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
466 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
467 if (Subtarget->is64Bit())
468 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
471 if (Subtarget->hasLZCNT()) {
472 // When promoting the i8 variants, force them to i32 for a shorter
474 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
475 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
476 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
477 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
478 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
479 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
480 if (Subtarget->is64Bit())
481 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
483 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
484 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
485 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
486 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
487 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
488 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
489 if (Subtarget->is64Bit()) {
490 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
491 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
495 if (Subtarget->hasPOPCNT()) {
496 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
498 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
499 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
500 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
501 if (Subtarget->is64Bit())
502 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
505 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
506 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
508 // These should be promoted to a larger select which is supported.
509 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
510 // X86 wants to expand cmov itself.
511 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
512 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
513 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
514 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
515 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
516 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
517 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
518 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
519 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
520 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
521 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
522 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
523 if (Subtarget->is64Bit()) {
524 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
525 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
527 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
528 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
529 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
530 // support continuation, user-level threading, and etc.. As a result, no
531 // other SjLj exception interfaces are implemented and please don't build
532 // your own exception handling based on them.
533 // LLVM/Clang supports zero-cost DWARF exception handling.
534 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
535 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
538 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
539 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
540 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
541 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
542 if (Subtarget->is64Bit())
543 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
544 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
545 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
546 if (Subtarget->is64Bit()) {
547 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
548 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
549 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
550 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
551 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
553 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
554 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
555 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
556 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
557 if (Subtarget->is64Bit()) {
558 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
559 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
560 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
563 if (Subtarget->hasSSE1())
564 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
566 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
568 // Expand certain atomics
569 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
571 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
572 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
573 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
576 if (!Subtarget->is64Bit()) {
577 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
578 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
579 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
580 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
581 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
582 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
583 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
584 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
585 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
586 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
587 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
588 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
591 if (Subtarget->hasCmpxchg16b()) {
592 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
595 // FIXME - use subtarget debug flags
596 if (!Subtarget->isTargetDarwin() &&
597 !Subtarget->isTargetELF() &&
598 !Subtarget->isTargetCygMing()) {
599 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
602 if (Subtarget->is64Bit()) {
603 setExceptionPointerRegister(X86::RAX);
604 setExceptionSelectorRegister(X86::RDX);
606 setExceptionPointerRegister(X86::EAX);
607 setExceptionSelectorRegister(X86::EDX);
609 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
610 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
612 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
613 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
615 setOperationAction(ISD::TRAP, MVT::Other, Legal);
616 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
618 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
619 setOperationAction(ISD::VASTART , MVT::Other, Custom);
620 setOperationAction(ISD::VAEND , MVT::Other, Expand);
621 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
622 // TargetInfo::X86_64ABIBuiltinVaList
623 setOperationAction(ISD::VAARG , MVT::Other, Custom);
624 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
626 // TargetInfo::CharPtrBuiltinVaList
627 setOperationAction(ISD::VAARG , MVT::Other, Expand);
628 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
631 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
632 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
634 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
635 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
636 MVT::i64 : MVT::i32, Custom);
637 else if (TM.Options.EnableSegmentedStacks)
638 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
639 MVT::i64 : MVT::i32, Custom);
641 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
642 MVT::i64 : MVT::i32, Expand);
644 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
645 // f32 and f64 use SSE.
646 // Set up the FP register classes.
647 addRegisterClass(MVT::f32, &X86::FR32RegClass);
648 addRegisterClass(MVT::f64, &X86::FR64RegClass);
650 // Use ANDPD to simulate FABS.
651 setOperationAction(ISD::FABS , MVT::f64, Custom);
652 setOperationAction(ISD::FABS , MVT::f32, Custom);
654 // Use XORP to simulate FNEG.
655 setOperationAction(ISD::FNEG , MVT::f64, Custom);
656 setOperationAction(ISD::FNEG , MVT::f32, Custom);
658 // Use ANDPD and ORPD to simulate FCOPYSIGN.
659 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
660 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
662 // Lower this to FGETSIGNx86 plus an AND.
663 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
664 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
666 // We don't support sin/cos/fmod
667 setOperationAction(ISD::FSIN , MVT::f64, Expand);
668 setOperationAction(ISD::FCOS , MVT::f64, Expand);
669 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
670 setOperationAction(ISD::FSIN , MVT::f32, Expand);
671 setOperationAction(ISD::FCOS , MVT::f32, Expand);
672 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
674 // Expand FP immediates into loads from the stack, except for the special
676 addLegalFPImmediate(APFloat(+0.0)); // xorpd
677 addLegalFPImmediate(APFloat(+0.0f)); // xorps
678 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
679 // Use SSE for f32, x87 for f64.
680 // Set up the FP register classes.
681 addRegisterClass(MVT::f32, &X86::FR32RegClass);
682 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
684 // Use ANDPS to simulate FABS.
685 setOperationAction(ISD::FABS , MVT::f32, Custom);
687 // Use XORP to simulate FNEG.
688 setOperationAction(ISD::FNEG , MVT::f32, Custom);
690 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
692 // Use ANDPS and ORPS to simulate FCOPYSIGN.
693 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
694 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
696 // We don't support sin/cos/fmod
697 setOperationAction(ISD::FSIN , MVT::f32, Expand);
698 setOperationAction(ISD::FCOS , MVT::f32, Expand);
699 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
701 // Special cases we handle for FP constants.
702 addLegalFPImmediate(APFloat(+0.0f)); // xorps
703 addLegalFPImmediate(APFloat(+0.0)); // FLD0
704 addLegalFPImmediate(APFloat(+1.0)); // FLD1
705 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
706 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
708 if (!TM.Options.UnsafeFPMath) {
709 setOperationAction(ISD::FSIN , MVT::f64, Expand);
710 setOperationAction(ISD::FCOS , MVT::f64, Expand);
711 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
713 } else if (!TM.Options.UseSoftFloat) {
714 // f32 and f64 in x87.
715 // Set up the FP register classes.
716 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
717 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
719 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
720 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
721 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
722 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
724 if (!TM.Options.UnsafeFPMath) {
725 setOperationAction(ISD::FSIN , MVT::f64, Expand);
726 setOperationAction(ISD::FSIN , MVT::f32, Expand);
727 setOperationAction(ISD::FCOS , MVT::f64, Expand);
728 setOperationAction(ISD::FCOS , MVT::f32, Expand);
729 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
730 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
732 addLegalFPImmediate(APFloat(+0.0)); // FLD0
733 addLegalFPImmediate(APFloat(+1.0)); // FLD1
734 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
735 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
736 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
737 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
738 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
739 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
742 // We don't support FMA.
743 setOperationAction(ISD::FMA, MVT::f64, Expand);
744 setOperationAction(ISD::FMA, MVT::f32, Expand);
746 // Long double always uses X87.
747 if (!TM.Options.UseSoftFloat) {
748 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
749 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
750 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
752 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
753 addLegalFPImmediate(TmpFlt); // FLD0
755 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
758 APFloat TmpFlt2(+1.0);
759 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
761 addLegalFPImmediate(TmpFlt2); // FLD1
762 TmpFlt2.changeSign();
763 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
766 if (!TM.Options.UnsafeFPMath) {
767 setOperationAction(ISD::FSIN , MVT::f80, Expand);
768 setOperationAction(ISD::FCOS , MVT::f80, Expand);
769 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
772 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
773 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
774 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
775 setOperationAction(ISD::FRINT, MVT::f80, Expand);
776 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
777 setOperationAction(ISD::FMA, MVT::f80, Expand);
780 // Always use a library call for pow.
781 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
782 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
783 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
785 setOperationAction(ISD::FLOG, MVT::f80, Expand);
786 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
787 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
788 setOperationAction(ISD::FEXP, MVT::f80, Expand);
789 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
791 // First set operation action for all vector types to either promote
792 // (for widening) or expand (for scalarization). Then we will selectively
793 // turn on ones that can be effectively codegen'd.
794 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
795 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
796 MVT VT = (MVT::SimpleValueType)i;
797 setOperationAction(ISD::ADD , VT, Expand);
798 setOperationAction(ISD::SUB , VT, Expand);
799 setOperationAction(ISD::FADD, VT, Expand);
800 setOperationAction(ISD::FNEG, VT, Expand);
801 setOperationAction(ISD::FSUB, VT, Expand);
802 setOperationAction(ISD::MUL , VT, Expand);
803 setOperationAction(ISD::FMUL, VT, Expand);
804 setOperationAction(ISD::SDIV, VT, Expand);
805 setOperationAction(ISD::UDIV, VT, Expand);
806 setOperationAction(ISD::FDIV, VT, Expand);
807 setOperationAction(ISD::SREM, VT, Expand);
808 setOperationAction(ISD::UREM, VT, Expand);
809 setOperationAction(ISD::LOAD, VT, Expand);
810 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
811 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
812 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
813 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
814 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
815 setOperationAction(ISD::FABS, VT, Expand);
816 setOperationAction(ISD::FSIN, VT, Expand);
817 setOperationAction(ISD::FSINCOS, VT, Expand);
818 setOperationAction(ISD::FCOS, VT, Expand);
819 setOperationAction(ISD::FSINCOS, VT, Expand);
820 setOperationAction(ISD::FREM, VT, Expand);
821 setOperationAction(ISD::FMA, VT, Expand);
822 setOperationAction(ISD::FPOWI, VT, Expand);
823 setOperationAction(ISD::FSQRT, VT, Expand);
824 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
825 setOperationAction(ISD::FFLOOR, VT, Expand);
826 setOperationAction(ISD::FCEIL, VT, Expand);
827 setOperationAction(ISD::FTRUNC, VT, Expand);
828 setOperationAction(ISD::FRINT, VT, Expand);
829 setOperationAction(ISD::FNEARBYINT, VT, Expand);
830 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
831 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
832 setOperationAction(ISD::SDIVREM, VT, Expand);
833 setOperationAction(ISD::UDIVREM, VT, Expand);
834 setOperationAction(ISD::FPOW, VT, Expand);
835 setOperationAction(ISD::CTPOP, VT, Expand);
836 setOperationAction(ISD::CTTZ, VT, Expand);
837 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
838 setOperationAction(ISD::CTLZ, VT, Expand);
839 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
840 setOperationAction(ISD::SHL, VT, Expand);
841 setOperationAction(ISD::SRA, VT, Expand);
842 setOperationAction(ISD::SRL, VT, Expand);
843 setOperationAction(ISD::ROTL, VT, Expand);
844 setOperationAction(ISD::ROTR, VT, Expand);
845 setOperationAction(ISD::BSWAP, VT, Expand);
846 setOperationAction(ISD::SETCC, VT, Expand);
847 setOperationAction(ISD::FLOG, VT, Expand);
848 setOperationAction(ISD::FLOG2, VT, Expand);
849 setOperationAction(ISD::FLOG10, VT, Expand);
850 setOperationAction(ISD::FEXP, VT, Expand);
851 setOperationAction(ISD::FEXP2, VT, Expand);
852 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
853 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
854 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
855 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
856 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
857 setOperationAction(ISD::TRUNCATE, VT, Expand);
858 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
859 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
860 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
861 setOperationAction(ISD::VSELECT, VT, Expand);
862 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
863 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
864 setTruncStoreAction(VT,
865 (MVT::SimpleValueType)InnerVT, Expand);
866 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
867 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
868 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
871 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
872 // with -msoft-float, disable use of MMX as well.
873 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
874 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
875 // No operations on x86mmx supported, everything uses intrinsics.
878 // MMX-sized vectors (other than x86mmx) are expected to be expanded
879 // into smaller operations.
880 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
881 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
882 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
883 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
884 setOperationAction(ISD::AND, MVT::v8i8, Expand);
885 setOperationAction(ISD::AND, MVT::v4i16, Expand);
886 setOperationAction(ISD::AND, MVT::v2i32, Expand);
887 setOperationAction(ISD::AND, MVT::v1i64, Expand);
888 setOperationAction(ISD::OR, MVT::v8i8, Expand);
889 setOperationAction(ISD::OR, MVT::v4i16, Expand);
890 setOperationAction(ISD::OR, MVT::v2i32, Expand);
891 setOperationAction(ISD::OR, MVT::v1i64, Expand);
892 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
893 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
894 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
895 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
896 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
897 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
898 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
899 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
900 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
901 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
902 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
903 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
904 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
905 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
906 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
907 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
908 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
910 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
911 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
913 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
914 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
915 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
916 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
917 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
918 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
919 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
920 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
921 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
922 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
923 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
924 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
927 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
928 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
930 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
931 // registers cannot be used even for integer operations.
932 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
933 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
934 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
935 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
937 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
938 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
939 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
940 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
941 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
942 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
943 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
944 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
945 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
946 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
947 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
948 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
949 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
950 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
951 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
952 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
953 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
954 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
956 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
957 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
958 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
959 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
961 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
962 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
963 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
967 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
968 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
969 MVT VT = (MVT::SimpleValueType)i;
970 // Do not attempt to custom lower non-power-of-2 vectors
971 if (!isPowerOf2_32(VT.getVectorNumElements()))
973 // Do not attempt to custom lower non-128-bit vectors
974 if (!VT.is128BitVector())
976 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
977 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
978 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
981 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
982 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
983 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
984 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
985 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
986 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
988 if (Subtarget->is64Bit()) {
989 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
990 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
993 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
994 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
995 MVT VT = (MVT::SimpleValueType)i;
997 // Do not attempt to promote non-128-bit vectors
998 if (!VT.is128BitVector())
1001 setOperationAction(ISD::AND, VT, Promote);
1002 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1003 setOperationAction(ISD::OR, VT, Promote);
1004 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1005 setOperationAction(ISD::XOR, VT, Promote);
1006 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1007 setOperationAction(ISD::LOAD, VT, Promote);
1008 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1009 setOperationAction(ISD::SELECT, VT, Promote);
1010 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1013 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1015 // Custom lower v2i64 and v2f64 selects.
1016 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1017 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1018 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1019 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1021 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1022 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1024 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1025 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1026 // As there is no 64-bit GPR available, we need build a special custom
1027 // sequence to convert from v2i32 to v2f32.
1028 if (!Subtarget->is64Bit())
1029 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1031 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1032 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1034 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1037 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1038 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1039 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1040 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1041 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1042 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1043 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1044 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1045 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1046 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1047 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1049 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1050 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1051 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1052 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1053 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1054 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1055 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1056 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1057 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1058 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1060 // FIXME: Do we need to handle scalar-to-vector here?
1061 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1063 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
1064 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
1065 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1066 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
1067 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
1069 // i8 and i16 vectors are custom , because the source register and source
1070 // source memory operand types are not the same width. f32 vectors are
1071 // custom since the immediate controlling the insert encodes additional
1073 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1074 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1075 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1076 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1078 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1079 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1080 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1081 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1083 // FIXME: these should be Legal but thats only for the case where
1084 // the index is constant. For now custom expand to deal with that.
1085 if (Subtarget->is64Bit()) {
1086 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1087 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1091 if (Subtarget->hasSSE2()) {
1092 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1093 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1095 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1096 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1098 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1099 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1101 // In the customized shift lowering, the legal cases in AVX2 will be
1103 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1104 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1106 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1107 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1109 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1111 setOperationAction(ISD::SDIV, MVT::v8i16, Custom);
1112 setOperationAction(ISD::SDIV, MVT::v4i32, Custom);
1115 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1116 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1117 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1118 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1119 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1120 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1121 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1123 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1124 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1125 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1127 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1128 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1129 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1130 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1131 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1132 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1133 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1134 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1135 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1136 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1137 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1138 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1140 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1141 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1142 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1143 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1144 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1145 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1146 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1147 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1148 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1149 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1150 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1151 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1153 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1154 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1156 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
1158 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1159 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1160 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1161 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1163 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1164 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1165 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1167 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1169 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1170 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1172 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1173 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1175 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1176 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1178 setOperationAction(ISD::SDIV, MVT::v16i16, Custom);
1180 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1181 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1182 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1183 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1185 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1186 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1187 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1189 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1190 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1191 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1192 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1194 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1195 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1196 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1197 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1198 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1199 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1201 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1202 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1203 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1205 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1206 setOperationAction(ISD::FMA, MVT::f32, Legal);
1207 setOperationAction(ISD::FMA, MVT::f64, Legal);
1210 if (Subtarget->hasInt256()) {
1211 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1212 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1213 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1214 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1216 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1217 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1218 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1219 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1221 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1222 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1223 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1224 // Don't lower v32i8 because there is no 128-bit byte mul
1226 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1228 setOperationAction(ISD::SDIV, MVT::v8i32, Custom);
1230 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1231 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1232 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1233 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1236 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1237 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1238 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1240 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1241 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1242 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1243 // Don't lower v32i8 because there is no 128-bit byte mul
1246 // In the customized shift lowering, the legal cases in AVX2 will be
1248 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1249 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1252 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1254 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1256 // Custom lower several nodes for 256-bit types.
1257 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1258 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1259 MVT VT = (MVT::SimpleValueType)i;
1261 // Extract subvector is special because the value type
1262 // (result) is 128-bit but the source is 256-bit wide.
1263 if (VT.is128BitVector())
1264 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1266 // Do not attempt to custom lower other non-256-bit vectors
1267 if (!VT.is256BitVector())
1270 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1271 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1272 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1273 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1274 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1275 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1276 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1279 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1280 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1281 MVT VT = (MVT::SimpleValueType)i;
1283 // Do not attempt to promote non-256-bit vectors
1284 if (!VT.is256BitVector())
1287 setOperationAction(ISD::AND, VT, Promote);
1288 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1289 setOperationAction(ISD::OR, VT, Promote);
1290 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1291 setOperationAction(ISD::XOR, VT, Promote);
1292 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1293 setOperationAction(ISD::LOAD, VT, Promote);
1294 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1295 setOperationAction(ISD::SELECT, VT, Promote);
1296 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1300 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1301 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1302 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1303 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1304 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1306 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1307 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1309 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1310 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1311 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1312 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1313 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1314 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1316 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1317 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1318 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1319 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1320 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1321 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1323 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1324 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1325 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1326 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1327 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1328 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1329 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1330 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1331 setOperationAction(ISD::SDIV, MVT::v16i32, Custom);
1334 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1335 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1336 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1337 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1338 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1339 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1340 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1341 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1343 setOperationAction(ISD::TRUNCATE, MVT::i1, Legal);
1344 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1345 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1346 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1347 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1348 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1349 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1350 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1351 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1352 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1353 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1354 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1356 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1357 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1358 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1359 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1360 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1362 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1363 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1365 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1367 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1368 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1369 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1370 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1371 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1373 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1374 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1376 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1377 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1379 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1381 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1382 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1384 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1385 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1387 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1388 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1390 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1391 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1392 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1394 // Custom lower several nodes.
1395 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1396 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1397 MVT VT = (MVT::SimpleValueType)i;
1399 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1400 // Extract subvector is special because the value type
1401 // (result) is 256/128-bit but the source is 512-bit wide.
1402 if (VT.is128BitVector() || VT.is256BitVector())
1403 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1405 if (VT.getVectorElementType() == MVT::i1)
1406 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1408 // Do not attempt to custom lower other non-512-bit vectors
1409 if (!VT.is512BitVector())
1412 if (VT != MVT::v8i64) {
1413 setOperationAction(ISD::XOR, VT, Promote);
1414 AddPromotedToType (ISD::XOR, VT, MVT::v8i64);
1415 setOperationAction(ISD::OR, VT, Promote);
1416 AddPromotedToType (ISD::OR, VT, MVT::v8i64);
1417 setOperationAction(ISD::AND, VT, Promote);
1418 AddPromotedToType (ISD::AND, VT, MVT::v8i64);
1420 if ( EltSize >= 32) {
1421 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1422 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1423 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1424 setOperationAction(ISD::VSELECT, VT, Legal);
1425 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1426 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1427 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1430 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1431 MVT VT = (MVT::SimpleValueType)i;
1433 // Do not attempt to promote non-256-bit vectors
1434 if (!VT.is512BitVector())
1437 setOperationAction(ISD::LOAD, VT, Promote);
1438 AddPromotedToType (ISD::LOAD, VT, MVT::v8i64);
1439 setOperationAction(ISD::SELECT, VT, Promote);
1440 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1444 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1445 // of this type with custom code.
1446 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1447 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1448 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1452 // We want to custom lower some of our intrinsics.
1453 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1454 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1456 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1457 // handle type legalization for these operations here.
1459 // FIXME: We really should do custom legalization for addition and
1460 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1461 // than generic legalization for 64-bit multiplication-with-overflow, though.
1462 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1463 // Add/Sub/Mul with overflow operations are custom lowered.
1465 setOperationAction(ISD::SADDO, VT, Custom);
1466 setOperationAction(ISD::UADDO, VT, Custom);
1467 setOperationAction(ISD::SSUBO, VT, Custom);
1468 setOperationAction(ISD::USUBO, VT, Custom);
1469 setOperationAction(ISD::SMULO, VT, Custom);
1470 setOperationAction(ISD::UMULO, VT, Custom);
1473 // There are no 8-bit 3-address imul/mul instructions
1474 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1475 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1477 if (!Subtarget->is64Bit()) {
1478 // These libcalls are not available in 32-bit.
1479 setLibcallName(RTLIB::SHL_I128, 0);
1480 setLibcallName(RTLIB::SRL_I128, 0);
1481 setLibcallName(RTLIB::SRA_I128, 0);
1484 // Combine sin / cos into one node or libcall if possible.
1485 if (Subtarget->hasSinCos()) {
1486 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1487 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1488 if (Subtarget->isTargetDarwin()) {
1489 // For MacOSX, we don't want to the normal expansion of a libcall to
1490 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1492 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1493 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1497 // We have target-specific dag combine patterns for the following nodes:
1498 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1499 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1500 setTargetDAGCombine(ISD::VSELECT);
1501 setTargetDAGCombine(ISD::SELECT);
1502 setTargetDAGCombine(ISD::SHL);
1503 setTargetDAGCombine(ISD::SRA);
1504 setTargetDAGCombine(ISD::SRL);
1505 setTargetDAGCombine(ISD::OR);
1506 setTargetDAGCombine(ISD::AND);
1507 setTargetDAGCombine(ISD::ADD);
1508 setTargetDAGCombine(ISD::FADD);
1509 setTargetDAGCombine(ISD::FSUB);
1510 setTargetDAGCombine(ISD::FMA);
1511 setTargetDAGCombine(ISD::SUB);
1512 setTargetDAGCombine(ISD::LOAD);
1513 setTargetDAGCombine(ISD::STORE);
1514 setTargetDAGCombine(ISD::ZERO_EXTEND);
1515 setTargetDAGCombine(ISD::ANY_EXTEND);
1516 setTargetDAGCombine(ISD::SIGN_EXTEND);
1517 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1518 setTargetDAGCombine(ISD::TRUNCATE);
1519 setTargetDAGCombine(ISD::SINT_TO_FP);
1520 setTargetDAGCombine(ISD::SETCC);
1521 if (Subtarget->is64Bit())
1522 setTargetDAGCombine(ISD::MUL);
1523 setTargetDAGCombine(ISD::XOR);
1525 computeRegisterProperties();
1527 // On Darwin, -Os means optimize for size without hurting performance,
1528 // do not reduce the limit.
1529 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1530 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1531 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1532 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1533 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1534 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1535 setPrefLoopAlignment(4); // 2^4 bytes.
1537 // Predictable cmov don't hurt on atom because it's in-order.
1538 PredictableSelectIsExpensive = !Subtarget->isAtom();
1540 setPrefFunctionAlignment(4); // 2^4 bytes.
1543 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1544 if (!VT.isVector()) return MVT::i8;
1545 return VT.changeVectorElementTypeToInteger();
1548 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1549 /// the desired ByVal argument alignment.
1550 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1553 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1554 if (VTy->getBitWidth() == 128)
1556 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1557 unsigned EltAlign = 0;
1558 getMaxByValAlign(ATy->getElementType(), EltAlign);
1559 if (EltAlign > MaxAlign)
1560 MaxAlign = EltAlign;
1561 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1562 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1563 unsigned EltAlign = 0;
1564 getMaxByValAlign(STy->getElementType(i), EltAlign);
1565 if (EltAlign > MaxAlign)
1566 MaxAlign = EltAlign;
1573 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1574 /// function arguments in the caller parameter area. For X86, aggregates
1575 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1576 /// are at 4-byte boundaries.
1577 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1578 if (Subtarget->is64Bit()) {
1579 // Max of 8 and alignment of type.
1580 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1587 if (Subtarget->hasSSE1())
1588 getMaxByValAlign(Ty, Align);
1592 /// getOptimalMemOpType - Returns the target specific optimal type for load
1593 /// and store operations as a result of memset, memcpy, and memmove
1594 /// lowering. If DstAlign is zero that means it's safe to destination
1595 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1596 /// means there isn't a need to check it against alignment requirement,
1597 /// probably because the source does not need to be loaded. If 'IsMemset' is
1598 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1599 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1600 /// source is constant so it does not need to be loaded.
1601 /// It returns EVT::Other if the type should be determined using generic
1602 /// target-independent logic.
1604 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1605 unsigned DstAlign, unsigned SrcAlign,
1606 bool IsMemset, bool ZeroMemset,
1608 MachineFunction &MF) const {
1609 const Function *F = MF.getFunction();
1610 if ((!IsMemset || ZeroMemset) &&
1611 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1612 Attribute::NoImplicitFloat)) {
1614 (Subtarget->isUnalignedMemAccessFast() ||
1615 ((DstAlign == 0 || DstAlign >= 16) &&
1616 (SrcAlign == 0 || SrcAlign >= 16)))) {
1618 if (Subtarget->hasInt256())
1620 if (Subtarget->hasFp256())
1623 if (Subtarget->hasSSE2())
1625 if (Subtarget->hasSSE1())
1627 } else if (!MemcpyStrSrc && Size >= 8 &&
1628 !Subtarget->is64Bit() &&
1629 Subtarget->hasSSE2()) {
1630 // Do not use f64 to lower memcpy if source is string constant. It's
1631 // better to use i32 to avoid the loads.
1635 if (Subtarget->is64Bit() && Size >= 8)
1640 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1642 return X86ScalarSSEf32;
1643 else if (VT == MVT::f64)
1644 return X86ScalarSSEf64;
1649 X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
1651 *Fast = Subtarget->isUnalignedMemAccessFast();
1655 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1656 /// current function. The returned value is a member of the
1657 /// MachineJumpTableInfo::JTEntryKind enum.
1658 unsigned X86TargetLowering::getJumpTableEncoding() const {
1659 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1661 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1662 Subtarget->isPICStyleGOT())
1663 return MachineJumpTableInfo::EK_Custom32;
1665 // Otherwise, use the normal jump table encoding heuristics.
1666 return TargetLowering::getJumpTableEncoding();
1670 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1671 const MachineBasicBlock *MBB,
1672 unsigned uid,MCContext &Ctx) const{
1673 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1674 Subtarget->isPICStyleGOT());
1675 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1677 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1678 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1681 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1683 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1684 SelectionDAG &DAG) const {
1685 if (!Subtarget->is64Bit())
1686 // This doesn't have SDLoc associated with it, but is not really the
1687 // same as a Register.
1688 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1692 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1693 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1695 const MCExpr *X86TargetLowering::
1696 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1697 MCContext &Ctx) const {
1698 // X86-64 uses RIP relative addressing based on the jump table label.
1699 if (Subtarget->isPICStyleRIPRel())
1700 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1702 // Otherwise, the reference is relative to the PIC base.
1703 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1706 // FIXME: Why this routine is here? Move to RegInfo!
1707 std::pair<const TargetRegisterClass*, uint8_t>
1708 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1709 const TargetRegisterClass *RRC = 0;
1711 switch (VT.SimpleTy) {
1713 return TargetLowering::findRepresentativeClass(VT);
1714 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1715 RRC = Subtarget->is64Bit() ?
1716 (const TargetRegisterClass*)&X86::GR64RegClass :
1717 (const TargetRegisterClass*)&X86::GR32RegClass;
1720 RRC = &X86::VR64RegClass;
1722 case MVT::f32: case MVT::f64:
1723 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1724 case MVT::v4f32: case MVT::v2f64:
1725 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1727 RRC = &X86::VR128RegClass;
1730 return std::make_pair(RRC, Cost);
1733 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1734 unsigned &Offset) const {
1735 if (!Subtarget->isTargetLinux())
1738 if (Subtarget->is64Bit()) {
1739 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1741 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1753 //===----------------------------------------------------------------------===//
1754 // Return Value Calling Convention Implementation
1755 //===----------------------------------------------------------------------===//
1757 #include "X86GenCallingConv.inc"
1760 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1761 MachineFunction &MF, bool isVarArg,
1762 const SmallVectorImpl<ISD::OutputArg> &Outs,
1763 LLVMContext &Context) const {
1764 SmallVector<CCValAssign, 16> RVLocs;
1765 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1767 return CCInfo.CheckReturn(Outs, RetCC_X86);
1771 X86TargetLowering::LowerReturn(SDValue Chain,
1772 CallingConv::ID CallConv, bool isVarArg,
1773 const SmallVectorImpl<ISD::OutputArg> &Outs,
1774 const SmallVectorImpl<SDValue> &OutVals,
1775 SDLoc dl, SelectionDAG &DAG) const {
1776 MachineFunction &MF = DAG.getMachineFunction();
1777 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1779 SmallVector<CCValAssign, 16> RVLocs;
1780 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1781 RVLocs, *DAG.getContext());
1782 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1785 SmallVector<SDValue, 6> RetOps;
1786 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1787 // Operand #1 = Bytes To Pop
1788 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1791 // Copy the result values into the output registers.
1792 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1793 CCValAssign &VA = RVLocs[i];
1794 assert(VA.isRegLoc() && "Can only return in registers!");
1795 SDValue ValToCopy = OutVals[i];
1796 EVT ValVT = ValToCopy.getValueType();
1798 // Promote values to the appropriate types
1799 if (VA.getLocInfo() == CCValAssign::SExt)
1800 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1801 else if (VA.getLocInfo() == CCValAssign::ZExt)
1802 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1803 else if (VA.getLocInfo() == CCValAssign::AExt)
1804 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1805 else if (VA.getLocInfo() == CCValAssign::BCvt)
1806 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1808 // If this is x86-64, and we disabled SSE, we can't return FP values,
1809 // or SSE or MMX vectors.
1810 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1811 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1812 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1813 report_fatal_error("SSE register return with SSE disabled");
1815 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1816 // llvm-gcc has never done it right and no one has noticed, so this
1817 // should be OK for now.
1818 if (ValVT == MVT::f64 &&
1819 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1820 report_fatal_error("SSE2 register return with SSE2 disabled");
1822 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1823 // the RET instruction and handled by the FP Stackifier.
1824 if (VA.getLocReg() == X86::ST0 ||
1825 VA.getLocReg() == X86::ST1) {
1826 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1827 // change the value to the FP stack register class.
1828 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1829 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1830 RetOps.push_back(ValToCopy);
1831 // Don't emit a copytoreg.
1835 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1836 // which is returned in RAX / RDX.
1837 if (Subtarget->is64Bit()) {
1838 if (ValVT == MVT::x86mmx) {
1839 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1840 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1841 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1843 // If we don't have SSE2 available, convert to v4f32 so the generated
1844 // register is legal.
1845 if (!Subtarget->hasSSE2())
1846 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1851 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1852 Flag = Chain.getValue(1);
1853 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1856 // The x86-64 ABIs require that for returning structs by value we copy
1857 // the sret argument into %rax/%eax (depending on ABI) for the return.
1858 // Win32 requires us to put the sret argument to %eax as well.
1859 // We saved the argument into a virtual register in the entry block,
1860 // so now we copy the value out and into %rax/%eax.
1861 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
1862 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
1863 MachineFunction &MF = DAG.getMachineFunction();
1864 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1865 unsigned Reg = FuncInfo->getSRetReturnReg();
1867 "SRetReturnReg should have been set in LowerFormalArguments().");
1868 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1871 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
1872 X86::RAX : X86::EAX;
1873 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1874 Flag = Chain.getValue(1);
1876 // RAX/EAX now acts like a return value.
1877 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
1880 RetOps[0] = Chain; // Update chain.
1882 // Add the flag if we have it.
1884 RetOps.push_back(Flag);
1886 return DAG.getNode(X86ISD::RET_FLAG, dl,
1887 MVT::Other, &RetOps[0], RetOps.size());
1890 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1891 if (N->getNumValues() != 1)
1893 if (!N->hasNUsesOfValue(1, 0))
1896 SDValue TCChain = Chain;
1897 SDNode *Copy = *N->use_begin();
1898 if (Copy->getOpcode() == ISD::CopyToReg) {
1899 // If the copy has a glue operand, we conservatively assume it isn't safe to
1900 // perform a tail call.
1901 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1903 TCChain = Copy->getOperand(0);
1904 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1907 bool HasRet = false;
1908 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1910 if (UI->getOpcode() != X86ISD::RET_FLAG)
1923 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
1924 ISD::NodeType ExtendKind) const {
1926 // TODO: Is this also valid on 32-bit?
1927 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1928 ReturnMVT = MVT::i8;
1930 ReturnMVT = MVT::i32;
1932 MVT MinVT = getRegisterType(ReturnMVT);
1933 return VT.bitsLT(MinVT) ? MinVT : VT;
1936 /// LowerCallResult - Lower the result values of a call into the
1937 /// appropriate copies out of appropriate physical registers.
1940 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1941 CallingConv::ID CallConv, bool isVarArg,
1942 const SmallVectorImpl<ISD::InputArg> &Ins,
1943 SDLoc dl, SelectionDAG &DAG,
1944 SmallVectorImpl<SDValue> &InVals) const {
1946 // Assign locations to each value returned by this call.
1947 SmallVector<CCValAssign, 16> RVLocs;
1948 bool Is64Bit = Subtarget->is64Bit();
1949 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1950 getTargetMachine(), RVLocs, *DAG.getContext());
1951 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1953 // Copy all of the result registers out of their specified physreg.
1954 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1955 CCValAssign &VA = RVLocs[i];
1956 EVT CopyVT = VA.getValVT();
1958 // If this is x86-64, and we disabled SSE, we can't return FP values
1959 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1960 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1961 report_fatal_error("SSE register return with SSE disabled");
1966 // If this is a call to a function that returns an fp value on the floating
1967 // point stack, we must guarantee the value is popped from the stack, so
1968 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1969 // if the return value is not used. We use the FpPOP_RETVAL instruction
1971 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1972 // If we prefer to use the value in xmm registers, copy it out as f80 and
1973 // use a truncate to move it from fp stack reg to xmm reg.
1974 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1975 SDValue Ops[] = { Chain, InFlag };
1976 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1977 MVT::Other, MVT::Glue, Ops), 1);
1978 Val = Chain.getValue(0);
1980 // Round the f80 to the right size, which also moves it to the appropriate
1982 if (CopyVT != VA.getValVT())
1983 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1984 // This truncation won't change the value.
1985 DAG.getIntPtrConstant(1));
1987 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1988 CopyVT, InFlag).getValue(1);
1989 Val = Chain.getValue(0);
1991 InFlag = Chain.getValue(2);
1992 InVals.push_back(Val);
1998 //===----------------------------------------------------------------------===//
1999 // C & StdCall & Fast Calling Convention implementation
2000 //===----------------------------------------------------------------------===//
2001 // StdCall calling convention seems to be standard for many Windows' API
2002 // routines and around. It differs from C calling convention just a little:
2003 // callee should clean up the stack, not caller. Symbols should be also
2004 // decorated in some fancy way :) It doesn't support any vector arguments.
2005 // For info on fast calling convention see Fast Calling Convention (tail call)
2006 // implementation LowerX86_32FastCCCallTo.
2008 /// CallIsStructReturn - Determines whether a call uses struct return
2010 enum StructReturnType {
2015 static StructReturnType
2016 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2018 return NotStructReturn;
2020 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2021 if (!Flags.isSRet())
2022 return NotStructReturn;
2023 if (Flags.isInReg())
2024 return RegStructReturn;
2025 return StackStructReturn;
2028 /// ArgsAreStructReturn - Determines whether a function uses struct
2029 /// return semantics.
2030 static StructReturnType
2031 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2033 return NotStructReturn;
2035 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2036 if (!Flags.isSRet())
2037 return NotStructReturn;
2038 if (Flags.isInReg())
2039 return RegStructReturn;
2040 return StackStructReturn;
2043 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2044 /// by "Src" to address "Dst" with size and alignment information specified by
2045 /// the specific parameter attribute. The copy will be passed as a byval
2046 /// function parameter.
2048 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2049 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2051 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2053 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2054 /*isVolatile*/false, /*AlwaysInline=*/true,
2055 MachinePointerInfo(), MachinePointerInfo());
2058 /// IsTailCallConvention - Return true if the calling convention is one that
2059 /// supports tail call optimization.
2060 static bool IsTailCallConvention(CallingConv::ID CC) {
2061 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2062 CC == CallingConv::HiPE);
2065 /// \brief Return true if the calling convention is a C calling convention.
2066 static bool IsCCallConvention(CallingConv::ID CC) {
2067 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2068 CC == CallingConv::X86_64_SysV);
2071 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2072 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2076 CallingConv::ID CalleeCC = CS.getCallingConv();
2077 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2083 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2084 /// a tailcall target by changing its ABI.
2085 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2086 bool GuaranteedTailCallOpt) {
2087 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2091 X86TargetLowering::LowerMemArgument(SDValue Chain,
2092 CallingConv::ID CallConv,
2093 const SmallVectorImpl<ISD::InputArg> &Ins,
2094 SDLoc dl, SelectionDAG &DAG,
2095 const CCValAssign &VA,
2096 MachineFrameInfo *MFI,
2098 // Create the nodes corresponding to a load from this parameter slot.
2099 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2100 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
2101 getTargetMachine().Options.GuaranteedTailCallOpt);
2102 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2105 // If value is passed by pointer we have address passed instead of the value
2107 if (VA.getLocInfo() == CCValAssign::Indirect)
2108 ValVT = VA.getLocVT();
2110 ValVT = VA.getValVT();
2112 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2113 // changed with more analysis.
2114 // In case of tail call optimization mark all arguments mutable. Since they
2115 // could be overwritten by lowering of arguments in case of a tail call.
2116 if (Flags.isByVal()) {
2117 unsigned Bytes = Flags.getByValSize();
2118 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2119 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2120 return DAG.getFrameIndex(FI, getPointerTy());
2122 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2123 VA.getLocMemOffset(), isImmutable);
2124 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2125 return DAG.getLoad(ValVT, dl, Chain, FIN,
2126 MachinePointerInfo::getFixedStack(FI),
2127 false, false, false, 0);
2132 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2133 CallingConv::ID CallConv,
2135 const SmallVectorImpl<ISD::InputArg> &Ins,
2138 SmallVectorImpl<SDValue> &InVals)
2140 MachineFunction &MF = DAG.getMachineFunction();
2141 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2143 const Function* Fn = MF.getFunction();
2144 if (Fn->hasExternalLinkage() &&
2145 Subtarget->isTargetCygMing() &&
2146 Fn->getName() == "main")
2147 FuncInfo->setForceFramePointer(true);
2149 MachineFrameInfo *MFI = MF.getFrameInfo();
2150 bool Is64Bit = Subtarget->is64Bit();
2151 bool IsWindows = Subtarget->isTargetWindows();
2152 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2154 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2155 "Var args not supported with calling convention fastcc, ghc or hipe");
2157 // Assign locations to all of the incoming arguments.
2158 SmallVector<CCValAssign, 16> ArgLocs;
2159 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2160 ArgLocs, *DAG.getContext());
2162 // Allocate shadow area for Win64
2164 CCInfo.AllocateStack(32, 8);
2166 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2168 unsigned LastVal = ~0U;
2170 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2171 CCValAssign &VA = ArgLocs[i];
2172 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2174 assert(VA.getValNo() != LastVal &&
2175 "Don't support value assigned to multiple locs yet");
2177 LastVal = VA.getValNo();
2179 if (VA.isRegLoc()) {
2180 EVT RegVT = VA.getLocVT();
2181 const TargetRegisterClass *RC;
2182 if (RegVT == MVT::i32)
2183 RC = &X86::GR32RegClass;
2184 else if (Is64Bit && RegVT == MVT::i64)
2185 RC = &X86::GR64RegClass;
2186 else if (RegVT == MVT::f32)
2187 RC = &X86::FR32RegClass;
2188 else if (RegVT == MVT::f64)
2189 RC = &X86::FR64RegClass;
2190 else if (RegVT.is512BitVector())
2191 RC = &X86::VR512RegClass;
2192 else if (RegVT.is256BitVector())
2193 RC = &X86::VR256RegClass;
2194 else if (RegVT.is128BitVector())
2195 RC = &X86::VR128RegClass;
2196 else if (RegVT == MVT::x86mmx)
2197 RC = &X86::VR64RegClass;
2198 else if (RegVT == MVT::v8i1)
2199 RC = &X86::VK8RegClass;
2200 else if (RegVT == MVT::v16i1)
2201 RC = &X86::VK16RegClass;
2203 llvm_unreachable("Unknown argument type!");
2205 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2206 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2208 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2209 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2211 if (VA.getLocInfo() == CCValAssign::SExt)
2212 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2213 DAG.getValueType(VA.getValVT()));
2214 else if (VA.getLocInfo() == CCValAssign::ZExt)
2215 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2216 DAG.getValueType(VA.getValVT()));
2217 else if (VA.getLocInfo() == CCValAssign::BCvt)
2218 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2220 if (VA.isExtInLoc()) {
2221 // Handle MMX values passed in XMM regs.
2222 if (RegVT.isVector())
2223 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2225 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2228 assert(VA.isMemLoc());
2229 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2232 // If value is passed via pointer - do a load.
2233 if (VA.getLocInfo() == CCValAssign::Indirect)
2234 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2235 MachinePointerInfo(), false, false, false, 0);
2237 InVals.push_back(ArgValue);
2240 // The x86-64 ABIs require that for returning structs by value we copy
2241 // the sret argument into %rax/%eax (depending on ABI) for the return.
2242 // Win32 requires us to put the sret argument to %eax as well.
2243 // Save the argument into a virtual register so that we can access it
2244 // from the return points.
2245 if (MF.getFunction()->hasStructRetAttr() &&
2246 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
2247 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2248 unsigned Reg = FuncInfo->getSRetReturnReg();
2250 MVT PtrTy = getPointerTy();
2251 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2252 FuncInfo->setSRetReturnReg(Reg);
2254 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
2255 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2258 unsigned StackSize = CCInfo.getNextStackOffset();
2259 // Align stack specially for tail calls.
2260 if (FuncIsMadeTailCallSafe(CallConv,
2261 MF.getTarget().Options.GuaranteedTailCallOpt))
2262 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2264 // If the function takes variable number of arguments, make a frame index for
2265 // the start of the first vararg value... for expansion of llvm.va_start.
2267 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2268 CallConv != CallingConv::X86_ThisCall)) {
2269 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2272 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2274 // FIXME: We should really autogenerate these arrays
2275 static const uint16_t GPR64ArgRegsWin64[] = {
2276 X86::RCX, X86::RDX, X86::R8, X86::R9
2278 static const uint16_t GPR64ArgRegs64Bit[] = {
2279 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2281 static const uint16_t XMMArgRegs64Bit[] = {
2282 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2283 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2285 const uint16_t *GPR64ArgRegs;
2286 unsigned NumXMMRegs = 0;
2289 // The XMM registers which might contain var arg parameters are shadowed
2290 // in their paired GPR. So we only need to save the GPR to their home
2292 TotalNumIntRegs = 4;
2293 GPR64ArgRegs = GPR64ArgRegsWin64;
2295 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2296 GPR64ArgRegs = GPR64ArgRegs64Bit;
2298 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2301 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2304 bool NoImplicitFloatOps = Fn->getAttributes().
2305 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2306 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2307 "SSE register cannot be used when SSE is disabled!");
2308 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2309 NoImplicitFloatOps) &&
2310 "SSE register cannot be used when SSE is disabled!");
2311 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2312 !Subtarget->hasSSE1())
2313 // Kernel mode asks for SSE to be disabled, so don't push them
2315 TotalNumXMMRegs = 0;
2318 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
2319 // Get to the caller-allocated home save location. Add 8 to account
2320 // for the return address.
2321 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2322 FuncInfo->setRegSaveFrameIndex(
2323 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2324 // Fixup to set vararg frame on shadow area (4 x i64).
2326 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2328 // For X86-64, if there are vararg parameters that are passed via
2329 // registers, then we must store them to their spots on the stack so
2330 // they may be loaded by deferencing the result of va_next.
2331 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2332 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2333 FuncInfo->setRegSaveFrameIndex(
2334 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2338 // Store the integer parameter registers.
2339 SmallVector<SDValue, 8> MemOps;
2340 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2342 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2343 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2344 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2345 DAG.getIntPtrConstant(Offset));
2346 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2347 &X86::GR64RegClass);
2348 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2350 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2351 MachinePointerInfo::getFixedStack(
2352 FuncInfo->getRegSaveFrameIndex(), Offset),
2354 MemOps.push_back(Store);
2358 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2359 // Now store the XMM (fp + vector) parameter registers.
2360 SmallVector<SDValue, 11> SaveXMMOps;
2361 SaveXMMOps.push_back(Chain);
2363 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2364 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2365 SaveXMMOps.push_back(ALVal);
2367 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2368 FuncInfo->getRegSaveFrameIndex()));
2369 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2370 FuncInfo->getVarArgsFPOffset()));
2372 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2373 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2374 &X86::VR128RegClass);
2375 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2376 SaveXMMOps.push_back(Val);
2378 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2380 &SaveXMMOps[0], SaveXMMOps.size()));
2383 if (!MemOps.empty())
2384 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2385 &MemOps[0], MemOps.size());
2389 // Some CCs need callee pop.
2390 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2391 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2392 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2394 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2395 // If this is an sret function, the return should pop the hidden pointer.
2396 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2397 argsAreStructReturn(Ins) == StackStructReturn)
2398 FuncInfo->setBytesToPopOnReturn(4);
2402 // RegSaveFrameIndex is X86-64 only.
2403 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2404 if (CallConv == CallingConv::X86_FastCall ||
2405 CallConv == CallingConv::X86_ThisCall)
2406 // fastcc functions can't have varargs.
2407 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2410 FuncInfo->setArgumentStackSize(StackSize);
2416 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2417 SDValue StackPtr, SDValue Arg,
2418 SDLoc dl, SelectionDAG &DAG,
2419 const CCValAssign &VA,
2420 ISD::ArgFlagsTy Flags) const {
2421 unsigned LocMemOffset = VA.getLocMemOffset();
2422 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2423 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2424 if (Flags.isByVal())
2425 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2427 return DAG.getStore(Chain, dl, Arg, PtrOff,
2428 MachinePointerInfo::getStack(LocMemOffset),
2432 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2433 /// optimization is performed and it is required.
2435 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2436 SDValue &OutRetAddr, SDValue Chain,
2437 bool IsTailCall, bool Is64Bit,
2438 int FPDiff, SDLoc dl) const {
2439 // Adjust the Return address stack slot.
2440 EVT VT = getPointerTy();
2441 OutRetAddr = getReturnAddressFrameIndex(DAG);
2443 // Load the "old" Return address.
2444 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2445 false, false, false, 0);
2446 return SDValue(OutRetAddr.getNode(), 1);
2449 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2450 /// optimization is performed and it is required (FPDiff!=0).
2452 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2453 SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT,
2454 unsigned SlotSize, int FPDiff, SDLoc dl) {
2455 // Store the return address to the appropriate stack slot.
2456 if (!FPDiff) return Chain;
2457 // Calculate the new stack slot for the return address.
2458 int NewReturnAddrFI =
2459 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2461 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2462 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2463 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2469 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2470 SmallVectorImpl<SDValue> &InVals) const {
2471 SelectionDAG &DAG = CLI.DAG;
2473 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2474 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2475 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2476 SDValue Chain = CLI.Chain;
2477 SDValue Callee = CLI.Callee;
2478 CallingConv::ID CallConv = CLI.CallConv;
2479 bool &isTailCall = CLI.IsTailCall;
2480 bool isVarArg = CLI.IsVarArg;
2482 MachineFunction &MF = DAG.getMachineFunction();
2483 bool Is64Bit = Subtarget->is64Bit();
2484 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2485 bool IsWindows = Subtarget->isTargetWindows();
2486 StructReturnType SR = callIsStructReturn(Outs);
2487 bool IsSibcall = false;
2489 if (MF.getTarget().Options.DisableTailCalls)
2493 // Check if it's really possible to do a tail call.
2494 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2495 isVarArg, SR != NotStructReturn,
2496 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2497 Outs, OutVals, Ins, DAG);
2499 // Sibcalls are automatically detected tailcalls which do not require
2501 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2508 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2509 "Var args not supported with calling convention fastcc, ghc or hipe");
2511 // Analyze operands of the call, assigning locations to each operand.
2512 SmallVector<CCValAssign, 16> ArgLocs;
2513 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2514 ArgLocs, *DAG.getContext());
2516 // Allocate shadow area for Win64
2518 CCInfo.AllocateStack(32, 8);
2520 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2522 // Get a count of how many bytes are to be pushed on the stack.
2523 unsigned NumBytes = CCInfo.getNextStackOffset();
2525 // This is a sibcall. The memory operands are available in caller's
2526 // own caller's stack.
2528 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2529 IsTailCallConvention(CallConv))
2530 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2533 if (isTailCall && !IsSibcall) {
2534 // Lower arguments at fp - stackoffset + fpdiff.
2535 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2536 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2538 FPDiff = NumBytesCallerPushed - NumBytes;
2540 // Set the delta of movement of the returnaddr stackslot.
2541 // But only set if delta is greater than previous delta.
2542 if (FPDiff < X86Info->getTCReturnAddrDelta())
2543 X86Info->setTCReturnAddrDelta(FPDiff);
2547 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
2550 SDValue RetAddrFrIdx;
2551 // Load return address for tail calls.
2552 if (isTailCall && FPDiff)
2553 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2554 Is64Bit, FPDiff, dl);
2556 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2557 SmallVector<SDValue, 8> MemOpChains;
2560 // Walk the register/memloc assignments, inserting copies/loads. In the case
2561 // of tail call optimization arguments are handle later.
2562 const X86RegisterInfo *RegInfo =
2563 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
2564 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2565 CCValAssign &VA = ArgLocs[i];
2566 EVT RegVT = VA.getLocVT();
2567 SDValue Arg = OutVals[i];
2568 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2569 bool isByVal = Flags.isByVal();
2571 // Promote the value if needed.
2572 switch (VA.getLocInfo()) {
2573 default: llvm_unreachable("Unknown loc info!");
2574 case CCValAssign::Full: break;
2575 case CCValAssign::SExt:
2576 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2578 case CCValAssign::ZExt:
2579 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2581 case CCValAssign::AExt:
2582 if (RegVT.is128BitVector()) {
2583 // Special case: passing MMX values in XMM registers.
2584 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2585 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2586 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2588 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2590 case CCValAssign::BCvt:
2591 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2593 case CCValAssign::Indirect: {
2594 // Store the argument.
2595 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2596 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2597 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2598 MachinePointerInfo::getFixedStack(FI),
2605 if (VA.isRegLoc()) {
2606 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2607 if (isVarArg && IsWin64) {
2608 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2609 // shadow reg if callee is a varargs function.
2610 unsigned ShadowReg = 0;
2611 switch (VA.getLocReg()) {
2612 case X86::XMM0: ShadowReg = X86::RCX; break;
2613 case X86::XMM1: ShadowReg = X86::RDX; break;
2614 case X86::XMM2: ShadowReg = X86::R8; break;
2615 case X86::XMM3: ShadowReg = X86::R9; break;
2618 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2620 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2621 assert(VA.isMemLoc());
2622 if (StackPtr.getNode() == 0)
2623 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2625 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2626 dl, DAG, VA, Flags));
2630 if (!MemOpChains.empty())
2631 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2632 &MemOpChains[0], MemOpChains.size());
2634 if (Subtarget->isPICStyleGOT()) {
2635 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2638 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2639 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2641 // If we are tail calling and generating PIC/GOT style code load the
2642 // address of the callee into ECX. The value in ecx is used as target of
2643 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2644 // for tail calls on PIC/GOT architectures. Normally we would just put the
2645 // address of GOT into ebx and then call target@PLT. But for tail calls
2646 // ebx would be restored (since ebx is callee saved) before jumping to the
2649 // Note: The actual moving to ECX is done further down.
2650 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2651 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2652 !G->getGlobal()->hasProtectedVisibility())
2653 Callee = LowerGlobalAddress(Callee, DAG);
2654 else if (isa<ExternalSymbolSDNode>(Callee))
2655 Callee = LowerExternalSymbol(Callee, DAG);
2659 if (Is64Bit && isVarArg && !IsWin64) {
2660 // From AMD64 ABI document:
2661 // For calls that may call functions that use varargs or stdargs
2662 // (prototype-less calls or calls to functions containing ellipsis (...) in
2663 // the declaration) %al is used as hidden argument to specify the number
2664 // of SSE registers used. The contents of %al do not need to match exactly
2665 // the number of registers, but must be an ubound on the number of SSE
2666 // registers used and is in the range 0 - 8 inclusive.
2668 // Count the number of XMM registers allocated.
2669 static const uint16_t XMMArgRegs[] = {
2670 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2671 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2673 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2674 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2675 && "SSE registers cannot be used when SSE is disabled");
2677 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2678 DAG.getConstant(NumXMMRegs, MVT::i8)));
2681 // For tail calls lower the arguments to the 'real' stack slot.
2683 // Force all the incoming stack arguments to be loaded from the stack
2684 // before any new outgoing arguments are stored to the stack, because the
2685 // outgoing stack slots may alias the incoming argument stack slots, and
2686 // the alias isn't otherwise explicit. This is slightly more conservative
2687 // than necessary, because it means that each store effectively depends
2688 // on every argument instead of just those arguments it would clobber.
2689 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2691 SmallVector<SDValue, 8> MemOpChains2;
2694 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2695 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2696 CCValAssign &VA = ArgLocs[i];
2699 assert(VA.isMemLoc());
2700 SDValue Arg = OutVals[i];
2701 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2702 // Create frame index.
2703 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2704 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2705 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2706 FIN = DAG.getFrameIndex(FI, getPointerTy());
2708 if (Flags.isByVal()) {
2709 // Copy relative to framepointer.
2710 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2711 if (StackPtr.getNode() == 0)
2712 StackPtr = DAG.getCopyFromReg(Chain, dl,
2713 RegInfo->getStackRegister(),
2715 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2717 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2721 // Store relative to framepointer.
2722 MemOpChains2.push_back(
2723 DAG.getStore(ArgChain, dl, Arg, FIN,
2724 MachinePointerInfo::getFixedStack(FI),
2730 if (!MemOpChains2.empty())
2731 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2732 &MemOpChains2[0], MemOpChains2.size());
2734 // Store the return address to the appropriate stack slot.
2735 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2736 getPointerTy(), RegInfo->getSlotSize(),
2740 // Build a sequence of copy-to-reg nodes chained together with token chain
2741 // and flag operands which copy the outgoing args into registers.
2743 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2744 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2745 RegsToPass[i].second, InFlag);
2746 InFlag = Chain.getValue(1);
2749 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2750 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2751 // In the 64-bit large code model, we have to make all calls
2752 // through a register, since the call instruction's 32-bit
2753 // pc-relative offset may not be large enough to hold the whole
2755 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2756 // If the callee is a GlobalAddress node (quite common, every direct call
2757 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2760 // We should use extra load for direct calls to dllimported functions in
2762 const GlobalValue *GV = G->getGlobal();
2763 if (!GV->hasDLLImportLinkage()) {
2764 unsigned char OpFlags = 0;
2765 bool ExtraLoad = false;
2766 unsigned WrapperKind = ISD::DELETED_NODE;
2768 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2769 // external symbols most go through the PLT in PIC mode. If the symbol
2770 // has hidden or protected visibility, or if it is static or local, then
2771 // we don't need to use the PLT - we can directly call it.
2772 if (Subtarget->isTargetELF() &&
2773 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2774 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2775 OpFlags = X86II::MO_PLT;
2776 } else if (Subtarget->isPICStyleStubAny() &&
2777 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2778 (!Subtarget->getTargetTriple().isMacOSX() ||
2779 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2780 // PC-relative references to external symbols should go through $stub,
2781 // unless we're building with the leopard linker or later, which
2782 // automatically synthesizes these stubs.
2783 OpFlags = X86II::MO_DARWIN_STUB;
2784 } else if (Subtarget->isPICStyleRIPRel() &&
2785 isa<Function>(GV) &&
2786 cast<Function>(GV)->getAttributes().
2787 hasAttribute(AttributeSet::FunctionIndex,
2788 Attribute::NonLazyBind)) {
2789 // If the function is marked as non-lazy, generate an indirect call
2790 // which loads from the GOT directly. This avoids runtime overhead
2791 // at the cost of eager binding (and one extra byte of encoding).
2792 OpFlags = X86II::MO_GOTPCREL;
2793 WrapperKind = X86ISD::WrapperRIP;
2797 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2798 G->getOffset(), OpFlags);
2800 // Add a wrapper if needed.
2801 if (WrapperKind != ISD::DELETED_NODE)
2802 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2803 // Add extra indirection if needed.
2805 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2806 MachinePointerInfo::getGOT(),
2807 false, false, false, 0);
2809 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2810 unsigned char OpFlags = 0;
2812 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2813 // external symbols should go through the PLT.
2814 if (Subtarget->isTargetELF() &&
2815 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2816 OpFlags = X86II::MO_PLT;
2817 } else if (Subtarget->isPICStyleStubAny() &&
2818 (!Subtarget->getTargetTriple().isMacOSX() ||
2819 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2820 // PC-relative references to external symbols should go through $stub,
2821 // unless we're building with the leopard linker or later, which
2822 // automatically synthesizes these stubs.
2823 OpFlags = X86II::MO_DARWIN_STUB;
2826 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2830 // Returns a chain & a flag for retval copy to use.
2831 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2832 SmallVector<SDValue, 8> Ops;
2834 if (!IsSibcall && isTailCall) {
2835 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2836 DAG.getIntPtrConstant(0, true), InFlag, dl);
2837 InFlag = Chain.getValue(1);
2840 Ops.push_back(Chain);
2841 Ops.push_back(Callee);
2844 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2846 // Add argument registers to the end of the list so that they are known live
2848 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2849 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2850 RegsToPass[i].second.getValueType()));
2852 // Add a register mask operand representing the call-preserved registers.
2853 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2854 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2855 assert(Mask && "Missing call preserved mask for calling convention");
2856 Ops.push_back(DAG.getRegisterMask(Mask));
2858 if (InFlag.getNode())
2859 Ops.push_back(InFlag);
2863 //// If this is the first return lowered for this function, add the regs
2864 //// to the liveout set for the function.
2865 // This isn't right, although it's probably harmless on x86; liveouts
2866 // should be computed from returns not tail calls. Consider a void
2867 // function making a tail call to a function returning int.
2868 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
2871 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2872 InFlag = Chain.getValue(1);
2874 // Create the CALLSEQ_END node.
2875 unsigned NumBytesForCalleeToPush;
2876 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2877 getTargetMachine().Options.GuaranteedTailCallOpt))
2878 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2879 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2880 SR == StackStructReturn)
2881 // If this is a call to a struct-return function, the callee
2882 // pops the hidden struct pointer, so we have to push it back.
2883 // This is common for Darwin/X86, Linux & Mingw32 targets.
2884 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2885 NumBytesForCalleeToPush = 4;
2887 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2889 // Returns a flag for retval copy to use.
2891 Chain = DAG.getCALLSEQ_END(Chain,
2892 DAG.getIntPtrConstant(NumBytes, true),
2893 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2896 InFlag = Chain.getValue(1);
2899 // Handle result values, copying them out of physregs into vregs that we
2901 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2902 Ins, dl, DAG, InVals);
2905 //===----------------------------------------------------------------------===//
2906 // Fast Calling Convention (tail call) implementation
2907 //===----------------------------------------------------------------------===//
2909 // Like std call, callee cleans arguments, convention except that ECX is
2910 // reserved for storing the tail called function address. Only 2 registers are
2911 // free for argument passing (inreg). Tail call optimization is performed
2913 // * tailcallopt is enabled
2914 // * caller/callee are fastcc
2915 // On X86_64 architecture with GOT-style position independent code only local
2916 // (within module) calls are supported at the moment.
2917 // To keep the stack aligned according to platform abi the function
2918 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2919 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2920 // If a tail called function callee has more arguments than the caller the
2921 // caller needs to make sure that there is room to move the RETADDR to. This is
2922 // achieved by reserving an area the size of the argument delta right after the
2923 // original REtADDR, but before the saved framepointer or the spilled registers
2924 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2936 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2937 /// for a 16 byte align requirement.
2939 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2940 SelectionDAG& DAG) const {
2941 MachineFunction &MF = DAG.getMachineFunction();
2942 const TargetMachine &TM = MF.getTarget();
2943 const X86RegisterInfo *RegInfo =
2944 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
2945 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2946 unsigned StackAlignment = TFI.getStackAlignment();
2947 uint64_t AlignMask = StackAlignment - 1;
2948 int64_t Offset = StackSize;
2949 unsigned SlotSize = RegInfo->getSlotSize();
2950 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2951 // Number smaller than 12 so just add the difference.
2952 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2954 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2955 Offset = ((~AlignMask) & Offset) + StackAlignment +
2956 (StackAlignment-SlotSize);
2961 /// MatchingStackOffset - Return true if the given stack call argument is
2962 /// already available in the same position (relatively) of the caller's
2963 /// incoming argument stack.
2965 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2966 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2967 const X86InstrInfo *TII) {
2968 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2970 if (Arg.getOpcode() == ISD::CopyFromReg) {
2971 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2972 if (!TargetRegisterInfo::isVirtualRegister(VR))
2974 MachineInstr *Def = MRI->getVRegDef(VR);
2977 if (!Flags.isByVal()) {
2978 if (!TII->isLoadFromStackSlot(Def, FI))
2981 unsigned Opcode = Def->getOpcode();
2982 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2983 Def->getOperand(1).isFI()) {
2984 FI = Def->getOperand(1).getIndex();
2985 Bytes = Flags.getByValSize();
2989 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2990 if (Flags.isByVal())
2991 // ByVal argument is passed in as a pointer but it's now being
2992 // dereferenced. e.g.
2993 // define @foo(%struct.X* %A) {
2994 // tail call @bar(%struct.X* byval %A)
2997 SDValue Ptr = Ld->getBasePtr();
2998 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3001 FI = FINode->getIndex();
3002 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3003 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3004 FI = FINode->getIndex();
3005 Bytes = Flags.getByValSize();
3009 assert(FI != INT_MAX);
3010 if (!MFI->isFixedObjectIndex(FI))
3012 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3015 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3016 /// for tail call optimization. Targets which want to do tail call
3017 /// optimization should implement this function.
3019 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3020 CallingConv::ID CalleeCC,
3022 bool isCalleeStructRet,
3023 bool isCallerStructRet,
3025 const SmallVectorImpl<ISD::OutputArg> &Outs,
3026 const SmallVectorImpl<SDValue> &OutVals,
3027 const SmallVectorImpl<ISD::InputArg> &Ins,
3028 SelectionDAG &DAG) const {
3029 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3032 // If -tailcallopt is specified, make fastcc functions tail-callable.
3033 const MachineFunction &MF = DAG.getMachineFunction();
3034 const Function *CallerF = MF.getFunction();
3036 // If the function return type is x86_fp80 and the callee return type is not,
3037 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3038 // perform a tailcall optimization here.
3039 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3042 CallingConv::ID CallerCC = CallerF->getCallingConv();
3043 bool CCMatch = CallerCC == CalleeCC;
3044 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3045 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3047 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
3048 if (IsTailCallConvention(CalleeCC) && CCMatch)
3053 // Look for obvious safe cases to perform tail call optimization that do not
3054 // require ABI changes. This is what gcc calls sibcall.
3056 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3057 // emit a special epilogue.
3058 const X86RegisterInfo *RegInfo =
3059 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3060 if (RegInfo->needsStackRealignment(MF))
3063 // Also avoid sibcall optimization if either caller or callee uses struct
3064 // return semantics.
3065 if (isCalleeStructRet || isCallerStructRet)
3068 // An stdcall caller is expected to clean up its arguments; the callee
3069 // isn't going to do that.
3070 if (!CCMatch && CallerCC == CallingConv::X86_StdCall)
3073 // Do not sibcall optimize vararg calls unless all arguments are passed via
3075 if (isVarArg && !Outs.empty()) {
3077 // Optimizing for varargs on Win64 is unlikely to be safe without
3078 // additional testing.
3079 if (IsCalleeWin64 || IsCallerWin64)
3082 SmallVector<CCValAssign, 16> ArgLocs;
3083 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3084 getTargetMachine(), ArgLocs, *DAG.getContext());
3086 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3087 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3088 if (!ArgLocs[i].isRegLoc())
3092 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3093 // stack. Therefore, if it's not used by the call it is not safe to optimize
3094 // this into a sibcall.
3095 bool Unused = false;
3096 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3103 SmallVector<CCValAssign, 16> RVLocs;
3104 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
3105 getTargetMachine(), RVLocs, *DAG.getContext());
3106 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3107 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3108 CCValAssign &VA = RVLocs[i];
3109 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
3114 // If the calling conventions do not match, then we'd better make sure the
3115 // results are returned in the same way as what the caller expects.
3117 SmallVector<CCValAssign, 16> RVLocs1;
3118 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
3119 getTargetMachine(), RVLocs1, *DAG.getContext());
3120 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3122 SmallVector<CCValAssign, 16> RVLocs2;
3123 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
3124 getTargetMachine(), RVLocs2, *DAG.getContext());
3125 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3127 if (RVLocs1.size() != RVLocs2.size())
3129 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3130 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3132 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3134 if (RVLocs1[i].isRegLoc()) {
3135 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3138 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3144 // If the callee takes no arguments then go on to check the results of the
3146 if (!Outs.empty()) {
3147 // Check if stack adjustment is needed. For now, do not do this if any
3148 // argument is passed on the stack.
3149 SmallVector<CCValAssign, 16> ArgLocs;
3150 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3151 getTargetMachine(), ArgLocs, *DAG.getContext());
3153 // Allocate shadow area for Win64
3155 CCInfo.AllocateStack(32, 8);
3157 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3158 if (CCInfo.getNextStackOffset()) {
3159 MachineFunction &MF = DAG.getMachineFunction();
3160 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3163 // Check if the arguments are already laid out in the right way as
3164 // the caller's fixed stack objects.
3165 MachineFrameInfo *MFI = MF.getFrameInfo();
3166 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3167 const X86InstrInfo *TII =
3168 ((const X86TargetMachine&)getTargetMachine()).getInstrInfo();
3169 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3170 CCValAssign &VA = ArgLocs[i];
3171 SDValue Arg = OutVals[i];
3172 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3173 if (VA.getLocInfo() == CCValAssign::Indirect)
3175 if (!VA.isRegLoc()) {
3176 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3183 // If the tailcall address may be in a register, then make sure it's
3184 // possible to register allocate for it. In 32-bit, the call address can
3185 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3186 // callee-saved registers are restored. These happen to be the same
3187 // registers used to pass 'inreg' arguments so watch out for those.
3188 if (!Subtarget->is64Bit() &&
3189 ((!isa<GlobalAddressSDNode>(Callee) &&
3190 !isa<ExternalSymbolSDNode>(Callee)) ||
3191 getTargetMachine().getRelocationModel() == Reloc::PIC_)) {
3192 unsigned NumInRegs = 0;
3193 // In PIC we need an extra register to formulate the address computation
3195 unsigned MaxInRegs =
3196 (getTargetMachine().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3198 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3199 CCValAssign &VA = ArgLocs[i];
3202 unsigned Reg = VA.getLocReg();
3205 case X86::EAX: case X86::EDX: case X86::ECX:
3206 if (++NumInRegs == MaxInRegs)
3218 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3219 const TargetLibraryInfo *libInfo) const {
3220 return X86::createFastISel(funcInfo, libInfo);
3223 //===----------------------------------------------------------------------===//
3224 // Other Lowering Hooks
3225 //===----------------------------------------------------------------------===//
3227 static bool MayFoldLoad(SDValue Op) {
3228 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3231 static bool MayFoldIntoStore(SDValue Op) {
3232 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3235 static bool isTargetShuffle(unsigned Opcode) {
3237 default: return false;
3238 case X86ISD::PSHUFD:
3239 case X86ISD::PSHUFHW:
3240 case X86ISD::PSHUFLW:
3242 case X86ISD::PALIGNR:
3243 case X86ISD::MOVLHPS:
3244 case X86ISD::MOVLHPD:
3245 case X86ISD::MOVHLPS:
3246 case X86ISD::MOVLPS:
3247 case X86ISD::MOVLPD:
3248 case X86ISD::MOVSHDUP:
3249 case X86ISD::MOVSLDUP:
3250 case X86ISD::MOVDDUP:
3253 case X86ISD::UNPCKL:
3254 case X86ISD::UNPCKH:
3255 case X86ISD::VPERMILP:
3256 case X86ISD::VPERM2X128:
3257 case X86ISD::VPERMI:
3262 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3263 SDValue V1, SelectionDAG &DAG) {
3265 default: llvm_unreachable("Unknown x86 shuffle node");
3266 case X86ISD::MOVSHDUP:
3267 case X86ISD::MOVSLDUP:
3268 case X86ISD::MOVDDUP:
3269 return DAG.getNode(Opc, dl, VT, V1);
3273 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3274 SDValue V1, unsigned TargetMask,
3275 SelectionDAG &DAG) {
3277 default: llvm_unreachable("Unknown x86 shuffle node");
3278 case X86ISD::PSHUFD:
3279 case X86ISD::PSHUFHW:
3280 case X86ISD::PSHUFLW:
3281 case X86ISD::VPERMILP:
3282 case X86ISD::VPERMI:
3283 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3287 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3288 SDValue V1, SDValue V2, unsigned TargetMask,
3289 SelectionDAG &DAG) {
3291 default: llvm_unreachable("Unknown x86 shuffle node");
3292 case X86ISD::PALIGNR:
3294 case X86ISD::VPERM2X128:
3295 return DAG.getNode(Opc, dl, VT, V1, V2,
3296 DAG.getConstant(TargetMask, MVT::i8));
3300 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3301 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3303 default: llvm_unreachable("Unknown x86 shuffle node");
3304 case X86ISD::MOVLHPS:
3305 case X86ISD::MOVLHPD:
3306 case X86ISD::MOVHLPS:
3307 case X86ISD::MOVLPS:
3308 case X86ISD::MOVLPD:
3311 case X86ISD::UNPCKL:
3312 case X86ISD::UNPCKH:
3313 return DAG.getNode(Opc, dl, VT, V1, V2);
3317 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3318 MachineFunction &MF = DAG.getMachineFunction();
3319 const X86RegisterInfo *RegInfo =
3320 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3321 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3322 int ReturnAddrIndex = FuncInfo->getRAIndex();
3324 if (ReturnAddrIndex == 0) {
3325 // Set up a frame object for the return address.
3326 unsigned SlotSize = RegInfo->getSlotSize();
3327 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3330 FuncInfo->setRAIndex(ReturnAddrIndex);
3333 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3336 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3337 bool hasSymbolicDisplacement) {
3338 // Offset should fit into 32 bit immediate field.
3339 if (!isInt<32>(Offset))
3342 // If we don't have a symbolic displacement - we don't have any extra
3344 if (!hasSymbolicDisplacement)
3347 // FIXME: Some tweaks might be needed for medium code model.
3348 if (M != CodeModel::Small && M != CodeModel::Kernel)
3351 // For small code model we assume that latest object is 16MB before end of 31
3352 // bits boundary. We may also accept pretty large negative constants knowing
3353 // that all objects are in the positive half of address space.
3354 if (M == CodeModel::Small && Offset < 16*1024*1024)
3357 // For kernel code model we know that all object resist in the negative half
3358 // of 32bits address space. We may not accept negative offsets, since they may
3359 // be just off and we may accept pretty large positive ones.
3360 if (M == CodeModel::Kernel && Offset > 0)
3366 /// isCalleePop - Determines whether the callee is required to pop its
3367 /// own arguments. Callee pop is necessary to support tail calls.
3368 bool X86::isCalleePop(CallingConv::ID CallingConv,
3369 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3373 switch (CallingConv) {
3376 case CallingConv::X86_StdCall:
3378 case CallingConv::X86_FastCall:
3380 case CallingConv::X86_ThisCall:
3382 case CallingConv::Fast:
3384 case CallingConv::GHC:
3386 case CallingConv::HiPE:
3391 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3392 /// specific condition code, returning the condition code and the LHS/RHS of the
3393 /// comparison to make.
3394 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3395 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3397 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3398 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3399 // X > -1 -> X == 0, jump !sign.
3400 RHS = DAG.getConstant(0, RHS.getValueType());
3401 return X86::COND_NS;
3403 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3404 // X < 0 -> X == 0, jump on sign.
3407 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3409 RHS = DAG.getConstant(0, RHS.getValueType());
3410 return X86::COND_LE;
3414 switch (SetCCOpcode) {
3415 default: llvm_unreachable("Invalid integer condition!");
3416 case ISD::SETEQ: return X86::COND_E;
3417 case ISD::SETGT: return X86::COND_G;
3418 case ISD::SETGE: return X86::COND_GE;
3419 case ISD::SETLT: return X86::COND_L;
3420 case ISD::SETLE: return X86::COND_LE;
3421 case ISD::SETNE: return X86::COND_NE;
3422 case ISD::SETULT: return X86::COND_B;
3423 case ISD::SETUGT: return X86::COND_A;
3424 case ISD::SETULE: return X86::COND_BE;
3425 case ISD::SETUGE: return X86::COND_AE;
3429 // First determine if it is required or is profitable to flip the operands.
3431 // If LHS is a foldable load, but RHS is not, flip the condition.
3432 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3433 !ISD::isNON_EXTLoad(RHS.getNode())) {
3434 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3435 std::swap(LHS, RHS);
3438 switch (SetCCOpcode) {
3444 std::swap(LHS, RHS);
3448 // On a floating point condition, the flags are set as follows:
3450 // 0 | 0 | 0 | X > Y
3451 // 0 | 0 | 1 | X < Y
3452 // 1 | 0 | 0 | X == Y
3453 // 1 | 1 | 1 | unordered
3454 switch (SetCCOpcode) {
3455 default: llvm_unreachable("Condcode should be pre-legalized away");
3457 case ISD::SETEQ: return X86::COND_E;
3458 case ISD::SETOLT: // flipped
3460 case ISD::SETGT: return X86::COND_A;
3461 case ISD::SETOLE: // flipped
3463 case ISD::SETGE: return X86::COND_AE;
3464 case ISD::SETUGT: // flipped
3466 case ISD::SETLT: return X86::COND_B;
3467 case ISD::SETUGE: // flipped
3469 case ISD::SETLE: return X86::COND_BE;
3471 case ISD::SETNE: return X86::COND_NE;
3472 case ISD::SETUO: return X86::COND_P;
3473 case ISD::SETO: return X86::COND_NP;
3475 case ISD::SETUNE: return X86::COND_INVALID;
3479 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3480 /// code. Current x86 isa includes the following FP cmov instructions:
3481 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3482 static bool hasFPCMov(unsigned X86CC) {
3498 /// isFPImmLegal - Returns true if the target can instruction select the
3499 /// specified FP immediate natively. If false, the legalizer will
3500 /// materialize the FP immediate as a load from a constant pool.
3501 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3502 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3503 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3509 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3510 /// the specified range (L, H].
3511 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3512 return (Val < 0) || (Val >= Low && Val < Hi);
3515 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3516 /// specified value.
3517 static bool isUndefOrEqual(int Val, int CmpVal) {
3518 return (Val < 0 || Val == CmpVal);
3521 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3522 /// from position Pos and ending in Pos+Size, falls within the specified
3523 /// sequential range (L, L+Pos]. or is undef.
3524 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3525 unsigned Pos, unsigned Size, int Low) {
3526 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3527 if (!isUndefOrEqual(Mask[i], Low))
3532 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3533 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3534 /// the second operand.
3535 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3536 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3537 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3538 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3539 return (Mask[0] < 2 && Mask[1] < 2);
3543 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3544 /// is suitable for input to PSHUFHW.
3545 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3546 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3549 // Lower quadword copied in order or undef.
3550 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3553 // Upper quadword shuffled.
3554 for (unsigned i = 4; i != 8; ++i)
3555 if (!isUndefOrInRange(Mask[i], 4, 8))
3558 if (VT == MVT::v16i16) {
3559 // Lower quadword copied in order or undef.
3560 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3563 // Upper quadword shuffled.
3564 for (unsigned i = 12; i != 16; ++i)
3565 if (!isUndefOrInRange(Mask[i], 12, 16))
3572 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3573 /// is suitable for input to PSHUFLW.
3574 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3575 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3578 // Upper quadword copied in order.
3579 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3582 // Lower quadword shuffled.
3583 for (unsigned i = 0; i != 4; ++i)
3584 if (!isUndefOrInRange(Mask[i], 0, 4))
3587 if (VT == MVT::v16i16) {
3588 // Upper quadword copied in order.
3589 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3592 // Lower quadword shuffled.
3593 for (unsigned i = 8; i != 12; ++i)
3594 if (!isUndefOrInRange(Mask[i], 8, 12))
3601 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3602 /// is suitable for input to PALIGNR.
3603 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
3604 const X86Subtarget *Subtarget) {
3605 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3606 (VT.is256BitVector() && !Subtarget->hasInt256()))
3609 unsigned NumElts = VT.getVectorNumElements();
3610 unsigned NumLanes = VT.getSizeInBits()/128;
3611 unsigned NumLaneElts = NumElts/NumLanes;
3613 // Do not handle 64-bit element shuffles with palignr.
3614 if (NumLaneElts == 2)
3617 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3619 for (i = 0; i != NumLaneElts; ++i) {
3624 // Lane is all undef, go to next lane
3625 if (i == NumLaneElts)
3628 int Start = Mask[i+l];
3630 // Make sure its in this lane in one of the sources
3631 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3632 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3635 // If not lane 0, then we must match lane 0
3636 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3639 // Correct second source to be contiguous with first source
3640 if (Start >= (int)NumElts)
3641 Start -= NumElts - NumLaneElts;
3643 // Make sure we're shifting in the right direction.
3644 if (Start <= (int)(i+l))
3649 // Check the rest of the elements to see if they are consecutive.
3650 for (++i; i != NumLaneElts; ++i) {
3651 int Idx = Mask[i+l];
3653 // Make sure its in this lane
3654 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3655 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3658 // If not lane 0, then we must match lane 0
3659 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3662 if (Idx >= (int)NumElts)
3663 Idx -= NumElts - NumLaneElts;
3665 if (!isUndefOrEqual(Idx, Start+i))
3674 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3675 /// the two vector operands have swapped position.
3676 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3677 unsigned NumElems) {
3678 for (unsigned i = 0; i != NumElems; ++i) {
3682 else if (idx < (int)NumElems)
3683 Mask[i] = idx + NumElems;
3685 Mask[i] = idx - NumElems;
3689 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3690 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3691 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3692 /// reverse of what x86 shuffles want.
3693 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool HasFp256,
3694 bool Commuted = false) {
3695 if (!HasFp256 && VT.is256BitVector())
3698 unsigned NumElems = VT.getVectorNumElements();
3699 unsigned NumLanes = VT.getSizeInBits()/128;
3700 unsigned NumLaneElems = NumElems/NumLanes;
3702 if (NumLaneElems != 2 && NumLaneElems != 4)
3705 // VSHUFPSY divides the resulting vector into 4 chunks.
3706 // The sources are also splitted into 4 chunks, and each destination
3707 // chunk must come from a different source chunk.
3709 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3710 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3712 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3713 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3715 // VSHUFPDY divides the resulting vector into 4 chunks.
3716 // The sources are also splitted into 4 chunks, and each destination
3717 // chunk must come from a different source chunk.
3719 // SRC1 => X3 X2 X1 X0
3720 // SRC2 => Y3 Y2 Y1 Y0
3722 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3724 unsigned HalfLaneElems = NumLaneElems/2;
3725 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3726 for (unsigned i = 0; i != NumLaneElems; ++i) {
3727 int Idx = Mask[i+l];
3728 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3729 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3731 // For VSHUFPSY, the mask of the second half must be the same as the
3732 // first but with the appropriate offsets. This works in the same way as
3733 // VPERMILPS works with masks.
3734 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3736 if (!isUndefOrEqual(Idx, Mask[i]+l))
3744 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3745 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3746 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
3747 if (!VT.is128BitVector())
3750 unsigned NumElems = VT.getVectorNumElements();
3755 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3756 return isUndefOrEqual(Mask[0], 6) &&
3757 isUndefOrEqual(Mask[1], 7) &&
3758 isUndefOrEqual(Mask[2], 2) &&
3759 isUndefOrEqual(Mask[3], 3);
3762 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3763 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3765 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
3766 if (!VT.is128BitVector())
3769 unsigned NumElems = VT.getVectorNumElements();
3774 return isUndefOrEqual(Mask[0], 2) &&
3775 isUndefOrEqual(Mask[1], 3) &&
3776 isUndefOrEqual(Mask[2], 2) &&
3777 isUndefOrEqual(Mask[3], 3);
3780 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3781 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3782 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
3783 if (!VT.is128BitVector())
3786 unsigned NumElems = VT.getVectorNumElements();
3788 if (NumElems != 2 && NumElems != 4)
3791 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3792 if (!isUndefOrEqual(Mask[i], i + NumElems))
3795 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3796 if (!isUndefOrEqual(Mask[i], i))
3802 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3803 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3804 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
3805 if (!VT.is128BitVector())
3808 unsigned NumElems = VT.getVectorNumElements();
3810 if (NumElems != 2 && NumElems != 4)
3813 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3814 if (!isUndefOrEqual(Mask[i], i))
3817 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3818 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3825 // Some special combinations that can be optimized.
3828 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3829 SelectionDAG &DAG) {
3830 MVT VT = SVOp->getValueType(0).getSimpleVT();
3833 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3836 ArrayRef<int> Mask = SVOp->getMask();
3838 // These are the special masks that may be optimized.
3839 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3840 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3841 bool MatchEvenMask = true;
3842 bool MatchOddMask = true;
3843 for (int i=0; i<8; ++i) {
3844 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
3845 MatchEvenMask = false;
3846 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
3847 MatchOddMask = false;
3850 if (!MatchEvenMask && !MatchOddMask)
3853 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
3855 SDValue Op0 = SVOp->getOperand(0);
3856 SDValue Op1 = SVOp->getOperand(1);
3858 if (MatchEvenMask) {
3859 // Shift the second operand right to 32 bits.
3860 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
3861 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
3863 // Shift the first operand left to 32 bits.
3864 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
3865 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
3867 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
3868 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
3871 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3872 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3873 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
3874 bool HasInt256, bool V2IsSplat = false) {
3876 if (VT.is512BitVector())
3878 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3879 "Unsupported vector type for unpckh");
3881 unsigned NumElts = VT.getVectorNumElements();
3882 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
3883 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3886 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3887 // independently on 128-bit lanes.
3888 unsigned NumLanes = VT.getSizeInBits()/128;
3889 unsigned NumLaneElts = NumElts/NumLanes;
3891 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
3892 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
3893 int BitI = Mask[l+i];
3894 int BitI1 = Mask[l+i+1];
3895 if (!isUndefOrEqual(BitI, j))
3898 if (!isUndefOrEqual(BitI1, NumElts))
3901 if (!isUndefOrEqual(BitI1, j + NumElts))
3910 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3911 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3912 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
3913 bool HasInt256, bool V2IsSplat = false) {
3914 unsigned NumElts = VT.getVectorNumElements();
3916 if (VT.is512BitVector())
3918 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3919 "Unsupported vector type for unpckh");
3921 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
3922 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3925 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3926 // independently on 128-bit lanes.
3927 unsigned NumLanes = VT.getSizeInBits()/128;
3928 unsigned NumLaneElts = NumElts/NumLanes;
3930 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
3931 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
3932 int BitI = Mask[l+i];
3933 int BitI1 = Mask[l+i+1];
3934 if (!isUndefOrEqual(BitI, j))
3937 if (isUndefOrEqual(BitI1, NumElts))
3940 if (!isUndefOrEqual(BitI1, j+NumElts))
3948 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3949 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3951 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3952 unsigned NumElts = VT.getVectorNumElements();
3953 bool Is256BitVec = VT.is256BitVector();
3955 if (VT.is512BitVector())
3957 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3958 "Unsupported vector type for unpckh");
3960 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
3961 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3964 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3965 // FIXME: Need a better way to get rid of this, there's no latency difference
3966 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3967 // the former later. We should also remove the "_undef" special mask.
3968 if (NumElts == 4 && Is256BitVec)
3971 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3972 // independently on 128-bit lanes.
3973 unsigned NumLanes = VT.getSizeInBits()/128;
3974 unsigned NumLaneElts = NumElts/NumLanes;
3976 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
3977 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
3978 int BitI = Mask[l+i];
3979 int BitI1 = Mask[l+i+1];
3981 if (!isUndefOrEqual(BitI, j))
3983 if (!isUndefOrEqual(BitI1, j))
3991 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3992 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3994 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3995 unsigned NumElts = VT.getVectorNumElements();
3997 if (VT.is512BitVector())
4000 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4001 "Unsupported vector type for unpckh");
4003 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4004 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4007 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4008 // independently on 128-bit lanes.
4009 unsigned NumLanes = VT.getSizeInBits()/128;
4010 unsigned NumLaneElts = NumElts/NumLanes;
4012 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4013 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4014 int BitI = Mask[l+i];
4015 int BitI1 = Mask[l+i+1];
4016 if (!isUndefOrEqual(BitI, j))
4018 if (!isUndefOrEqual(BitI1, j))
4025 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4026 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4027 /// MOVSD, and MOVD, i.e. setting the lowest element.
4028 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4029 if (VT.getVectorElementType().getSizeInBits() < 32)
4031 if (!VT.is128BitVector())
4034 unsigned NumElts = VT.getVectorNumElements();
4036 if (!isUndefOrEqual(Mask[0], NumElts))
4039 for (unsigned i = 1; i != NumElts; ++i)
4040 if (!isUndefOrEqual(Mask[i], i))
4046 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4047 /// as permutations between 128-bit chunks or halves. As an example: this
4049 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4050 /// The first half comes from the second half of V1 and the second half from the
4051 /// the second half of V2.
4052 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasFp256) {
4053 if (!HasFp256 || !VT.is256BitVector())
4056 // The shuffle result is divided into half A and half B. In total the two
4057 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4058 // B must come from C, D, E or F.
4059 unsigned HalfSize = VT.getVectorNumElements()/2;
4060 bool MatchA = false, MatchB = false;
4062 // Check if A comes from one of C, D, E, F.
4063 for (unsigned Half = 0; Half != 4; ++Half) {
4064 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4070 // Check if B comes from one of C, D, E, F.
4071 for (unsigned Half = 0; Half != 4; ++Half) {
4072 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4078 return MatchA && MatchB;
4081 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4082 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4083 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4084 MVT VT = SVOp->getValueType(0).getSimpleVT();
4086 unsigned HalfSize = VT.getVectorNumElements()/2;
4088 unsigned FstHalf = 0, SndHalf = 0;
4089 for (unsigned i = 0; i < HalfSize; ++i) {
4090 if (SVOp->getMaskElt(i) > 0) {
4091 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4095 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4096 if (SVOp->getMaskElt(i) > 0) {
4097 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4102 return (FstHalf | (SndHalf << 4));
4105 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4106 static bool isPermImmMask(ArrayRef<int> Mask, EVT VT, unsigned& Imm8) {
4107 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4111 unsigned NumElts = VT.getVectorNumElements();
4113 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4114 for (unsigned i = 0; i != NumElts; ++i) {
4117 Imm8 |= Mask[i] << (i*2);
4122 unsigned LaneSize = 4;
4123 SmallVector<int, 4> MaskVal(LaneSize, -1);
4125 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4126 for (unsigned i = 0; i != LaneSize; ++i) {
4127 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4131 if (MaskVal[i] < 0) {
4132 MaskVal[i] = Mask[i+l] - l;
4133 Imm8 |= MaskVal[i] << (i*2);
4136 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4143 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4144 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4145 /// Note that VPERMIL mask matching is different depending whether theunderlying
4146 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4147 /// to the same elements of the low, but to the higher half of the source.
4148 /// In VPERMILPD the two lanes could be shuffled independently of each other
4149 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4150 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasFp256) {
4154 unsigned NumElts = VT.getVectorNumElements();
4155 // Only match 256-bit with 32/64-bit types
4156 if (!VT.is256BitVector() || (NumElts != 4 && NumElts != 8))
4159 unsigned NumLanes = VT.getSizeInBits()/128;
4160 unsigned LaneSize = NumElts/NumLanes;
4161 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4162 for (unsigned i = 0; i != LaneSize; ++i) {
4163 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4165 if (NumElts != 8 || l == 0)
4167 // VPERMILPS handling
4170 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
4178 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4179 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4180 /// element of vector 2 and the other elements to come from vector 1 in order.
4181 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4182 bool V2IsSplat = false, bool V2IsUndef = false) {
4183 if (!VT.is128BitVector())
4186 unsigned NumOps = VT.getVectorNumElements();
4187 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4190 if (!isUndefOrEqual(Mask[0], 0))
4193 for (unsigned i = 1; i != NumOps; ++i)
4194 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4195 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4196 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4202 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4203 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4204 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4205 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4206 const X86Subtarget *Subtarget) {
4207 if (!Subtarget->hasSSE3())
4210 unsigned NumElems = VT.getVectorNumElements();
4212 if ((VT.is128BitVector() && NumElems != 4) ||
4213 (VT.is256BitVector() && NumElems != 8) ||
4214 (VT.is512BitVector() && NumElems != 16))
4217 // "i+1" is the value the indexed mask element must have
4218 for (unsigned i = 0; i != NumElems; i += 2)
4219 if (!isUndefOrEqual(Mask[i], i+1) ||
4220 !isUndefOrEqual(Mask[i+1], i+1))
4226 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4227 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4228 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4229 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4230 const X86Subtarget *Subtarget) {
4231 if (!Subtarget->hasSSE3())
4234 unsigned NumElems = VT.getVectorNumElements();
4236 if ((VT.is128BitVector() && NumElems != 4) ||
4237 (VT.is256BitVector() && NumElems != 8) ||
4238 (VT.is512BitVector() && NumElems != 16))
4241 // "i" is the value the indexed mask element must have
4242 for (unsigned i = 0; i != NumElems; i += 2)
4243 if (!isUndefOrEqual(Mask[i], i) ||
4244 !isUndefOrEqual(Mask[i+1], i))
4250 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4251 /// specifies a shuffle of elements that is suitable for input to 256-bit
4252 /// version of MOVDDUP.
4253 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4254 if (!HasFp256 || !VT.is256BitVector())
4257 unsigned NumElts = VT.getVectorNumElements();
4261 for (unsigned i = 0; i != NumElts/2; ++i)
4262 if (!isUndefOrEqual(Mask[i], 0))
4264 for (unsigned i = NumElts/2; i != NumElts; ++i)
4265 if (!isUndefOrEqual(Mask[i], NumElts/2))
4270 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4271 /// specifies a shuffle of elements that is suitable for input to 128-bit
4272 /// version of MOVDDUP.
4273 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4274 if (!VT.is128BitVector())
4277 unsigned e = VT.getVectorNumElements() / 2;
4278 for (unsigned i = 0; i != e; ++i)
4279 if (!isUndefOrEqual(Mask[i], i))
4281 for (unsigned i = 0; i != e; ++i)
4282 if (!isUndefOrEqual(Mask[e+i], i))
4287 /// isVEXTRACTIndex - Return true if the specified
4288 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4289 /// suitable for instruction that extract 128 or 256 bit vectors
4290 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4291 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4292 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4295 // The index should be aligned on a vecWidth-bit boundary.
4297 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4299 MVT VT = N->getValueType(0).getSimpleVT();
4300 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4301 bool Result = (Index * ElSize) % vecWidth == 0;
4306 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4307 /// operand specifies a subvector insert that is suitable for input to
4308 /// insertion of 128 or 256-bit subvectors
4309 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4310 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4311 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4313 // The index should be aligned on a vecWidth-bit boundary.
4315 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4317 MVT VT = N->getValueType(0).getSimpleVT();
4318 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4319 bool Result = (Index * ElSize) % vecWidth == 0;
4324 bool X86::isVINSERT128Index(SDNode *N) {
4325 return isVINSERTIndex(N, 128);
4328 bool X86::isVINSERT256Index(SDNode *N) {
4329 return isVINSERTIndex(N, 256);
4332 bool X86::isVEXTRACT128Index(SDNode *N) {
4333 return isVEXTRACTIndex(N, 128);
4336 bool X86::isVEXTRACT256Index(SDNode *N) {
4337 return isVEXTRACTIndex(N, 256);
4340 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4341 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4342 /// Handles 128-bit and 256-bit.
4343 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4344 MVT VT = N->getValueType(0).getSimpleVT();
4346 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4347 "Unsupported vector type for PSHUF/SHUFP");
4349 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4350 // independently on 128-bit lanes.
4351 unsigned NumElts = VT.getVectorNumElements();
4352 unsigned NumLanes = VT.getSizeInBits()/128;
4353 unsigned NumLaneElts = NumElts/NumLanes;
4355 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
4356 "Only supports 2 or 4 elements per lane");
4358 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
4360 for (unsigned i = 0; i != NumElts; ++i) {
4361 int Elt = N->getMaskElt(i);
4362 if (Elt < 0) continue;
4363 Elt &= NumLaneElts - 1;
4364 unsigned ShAmt = (i << Shift) % 8;
4365 Mask |= Elt << ShAmt;
4371 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4372 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4373 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4374 MVT VT = N->getValueType(0).getSimpleVT();
4376 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4377 "Unsupported vector type for PSHUFHW");
4379 unsigned NumElts = VT.getVectorNumElements();
4382 for (unsigned l = 0; l != NumElts; l += 8) {
4383 // 8 nodes per lane, but we only care about the last 4.
4384 for (unsigned i = 0; i < 4; ++i) {
4385 int Elt = N->getMaskElt(l+i+4);
4386 if (Elt < 0) continue;
4387 Elt &= 0x3; // only 2-bits.
4388 Mask |= Elt << (i * 2);
4395 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4396 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4397 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4398 MVT VT = N->getValueType(0).getSimpleVT();
4400 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4401 "Unsupported vector type for PSHUFHW");
4403 unsigned NumElts = VT.getVectorNumElements();
4406 for (unsigned l = 0; l != NumElts; l += 8) {
4407 // 8 nodes per lane, but we only care about the first 4.
4408 for (unsigned i = 0; i < 4; ++i) {
4409 int Elt = N->getMaskElt(l+i);
4410 if (Elt < 0) continue;
4411 Elt &= 0x3; // only 2-bits
4412 Mask |= Elt << (i * 2);
4419 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4420 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4421 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4422 MVT VT = SVOp->getValueType(0).getSimpleVT();
4423 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
4425 unsigned NumElts = VT.getVectorNumElements();
4426 unsigned NumLanes = VT.getSizeInBits()/128;
4427 unsigned NumLaneElts = NumElts/NumLanes;
4431 for (i = 0; i != NumElts; ++i) {
4432 Val = SVOp->getMaskElt(i);
4436 if (Val >= (int)NumElts)
4437 Val -= NumElts - NumLaneElts;
4439 assert(Val - i > 0 && "PALIGNR imm should be positive");
4440 return (Val - i) * EltSize;
4443 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4444 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4445 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4446 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4449 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4451 MVT VecVT = N->getOperand(0).getValueType().getSimpleVT();
4452 MVT ElVT = VecVT.getVectorElementType();
4454 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4455 return Index / NumElemsPerChunk;
4458 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4459 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4460 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4461 llvm_unreachable("Illegal insert subvector for VINSERT");
4464 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4466 MVT VecVT = N->getValueType(0).getSimpleVT();
4467 MVT ElVT = VecVT.getVectorElementType();
4469 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4470 return Index / NumElemsPerChunk;
4473 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4474 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4475 /// and VINSERTI128 instructions.
4476 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4477 return getExtractVEXTRACTImmediate(N, 128);
4480 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4481 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4482 /// and VINSERTI64x4 instructions.
4483 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4484 return getExtractVEXTRACTImmediate(N, 256);
4487 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4488 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4489 /// and VINSERTI128 instructions.
4490 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4491 return getInsertVINSERTImmediate(N, 128);
4494 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4495 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4496 /// and VINSERTI64x4 instructions.
4497 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4498 return getInsertVINSERTImmediate(N, 256);
4501 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4503 bool X86::isZeroNode(SDValue Elt) {
4504 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Elt))
4505 return CN->isNullValue();
4506 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4507 return CFP->getValueAPF().isPosZero();
4511 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4512 /// their permute mask.
4513 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4514 SelectionDAG &DAG) {
4515 MVT VT = SVOp->getValueType(0).getSimpleVT();
4516 unsigned NumElems = VT.getVectorNumElements();
4517 SmallVector<int, 8> MaskVec;
4519 for (unsigned i = 0; i != NumElems; ++i) {
4520 int Idx = SVOp->getMaskElt(i);
4522 if (Idx < (int)NumElems)
4527 MaskVec.push_back(Idx);
4529 return DAG.getVectorShuffle(VT, SDLoc(SVOp), SVOp->getOperand(1),
4530 SVOp->getOperand(0), &MaskVec[0]);
4533 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4534 /// match movhlps. The lower half elements should come from upper half of
4535 /// V1 (and in order), and the upper half elements should come from the upper
4536 /// half of V2 (and in order).
4537 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4538 if (!VT.is128BitVector())
4540 if (VT.getVectorNumElements() != 4)
4542 for (unsigned i = 0, e = 2; i != e; ++i)
4543 if (!isUndefOrEqual(Mask[i], i+2))
4545 for (unsigned i = 2; i != 4; ++i)
4546 if (!isUndefOrEqual(Mask[i], i+4))
4551 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4552 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4554 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4555 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4557 N = N->getOperand(0).getNode();
4558 if (!ISD::isNON_EXTLoad(N))
4561 *LD = cast<LoadSDNode>(N);
4565 // Test whether the given value is a vector value which will be legalized
4567 static bool WillBeConstantPoolLoad(SDNode *N) {
4568 if (N->getOpcode() != ISD::BUILD_VECTOR)
4571 // Check for any non-constant elements.
4572 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4573 switch (N->getOperand(i).getNode()->getOpcode()) {
4575 case ISD::ConstantFP:
4582 // Vectors of all-zeros and all-ones are materialized with special
4583 // instructions rather than being loaded.
4584 return !ISD::isBuildVectorAllZeros(N) &&
4585 !ISD::isBuildVectorAllOnes(N);
4588 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4589 /// match movlp{s|d}. The lower half elements should come from lower half of
4590 /// V1 (and in order), and the upper half elements should come from the upper
4591 /// half of V2 (and in order). And since V1 will become the source of the
4592 /// MOVLP, it must be either a vector load or a scalar load to vector.
4593 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4594 ArrayRef<int> Mask, MVT VT) {
4595 if (!VT.is128BitVector())
4598 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4600 // Is V2 is a vector load, don't do this transformation. We will try to use
4601 // load folding shufps op.
4602 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4605 unsigned NumElems = VT.getVectorNumElements();
4607 if (NumElems != 2 && NumElems != 4)
4609 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4610 if (!isUndefOrEqual(Mask[i], i))
4612 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4613 if (!isUndefOrEqual(Mask[i], i+NumElems))
4618 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4620 static bool isSplatVector(SDNode *N) {
4621 if (N->getOpcode() != ISD::BUILD_VECTOR)
4624 SDValue SplatValue = N->getOperand(0);
4625 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4626 if (N->getOperand(i) != SplatValue)
4631 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4632 /// to an zero vector.
4633 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4634 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4635 SDValue V1 = N->getOperand(0);
4636 SDValue V2 = N->getOperand(1);
4637 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4638 for (unsigned i = 0; i != NumElems; ++i) {
4639 int Idx = N->getMaskElt(i);
4640 if (Idx >= (int)NumElems) {
4641 unsigned Opc = V2.getOpcode();
4642 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4644 if (Opc != ISD::BUILD_VECTOR ||
4645 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4647 } else if (Idx >= 0) {
4648 unsigned Opc = V1.getOpcode();
4649 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4651 if (Opc != ISD::BUILD_VECTOR ||
4652 !X86::isZeroNode(V1.getOperand(Idx)))
4659 /// getZeroVector - Returns a vector of specified type with all zero elements.
4661 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4662 SelectionDAG &DAG, SDLoc dl) {
4663 assert(VT.isVector() && "Expected a vector type");
4665 // Always build SSE zero vectors as <4 x i32> bitcasted
4666 // to their dest type. This ensures they get CSE'd.
4668 if (VT.is128BitVector()) { // SSE
4669 if (Subtarget->hasSSE2()) { // SSE2
4670 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4671 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4673 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4674 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4676 } else if (VT.is256BitVector()) { // AVX
4677 if (Subtarget->hasInt256()) { // AVX2
4678 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4679 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4680 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4681 array_lengthof(Ops));
4683 // 256-bit logic and arithmetic instructions in AVX are all
4684 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4685 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4686 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4687 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops,
4688 array_lengthof(Ops));
4691 llvm_unreachable("Unexpected vector type");
4693 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4696 /// getOnesVector - Returns a vector of specified type with all bits set.
4697 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4698 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4699 /// Then bitcast to their original type, ensuring they get CSE'd.
4700 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4702 assert(VT.isVector() && "Expected a vector type");
4704 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4706 if (VT.is256BitVector()) {
4707 if (HasInt256) { // AVX2
4708 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4709 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4710 array_lengthof(Ops));
4712 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4713 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4715 } else if (VT.is128BitVector()) {
4716 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4718 llvm_unreachable("Unexpected vector type");
4720 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4723 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4724 /// that point to V2 points to its first element.
4725 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4726 for (unsigned i = 0; i != NumElems; ++i) {
4727 if (Mask[i] > (int)NumElems) {
4733 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4734 /// operation of specified width.
4735 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4737 unsigned NumElems = VT.getVectorNumElements();
4738 SmallVector<int, 8> Mask;
4739 Mask.push_back(NumElems);
4740 for (unsigned i = 1; i != NumElems; ++i)
4742 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4745 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4746 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4748 unsigned NumElems = VT.getVectorNumElements();
4749 SmallVector<int, 8> Mask;
4750 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4752 Mask.push_back(i + NumElems);
4754 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4757 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4758 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4760 unsigned NumElems = VT.getVectorNumElements();
4761 SmallVector<int, 8> Mask;
4762 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4763 Mask.push_back(i + Half);
4764 Mask.push_back(i + NumElems + Half);
4766 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4769 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4770 // a generic shuffle instruction because the target has no such instructions.
4771 // Generate shuffles which repeat i16 and i8 several times until they can be
4772 // represented by v4f32 and then be manipulated by target suported shuffles.
4773 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4774 EVT VT = V.getValueType();
4775 int NumElems = VT.getVectorNumElements();
4778 while (NumElems > 4) {
4779 if (EltNo < NumElems/2) {
4780 V = getUnpackl(DAG, dl, VT, V, V);
4782 V = getUnpackh(DAG, dl, VT, V, V);
4783 EltNo -= NumElems/2;
4790 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4791 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4792 EVT VT = V.getValueType();
4795 if (VT.is128BitVector()) {
4796 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4797 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4798 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4800 } else if (VT.is256BitVector()) {
4801 // To use VPERMILPS to splat scalars, the second half of indicies must
4802 // refer to the higher part, which is a duplication of the lower one,
4803 // because VPERMILPS can only handle in-lane permutations.
4804 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4805 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4807 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4808 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4811 llvm_unreachable("Vector size not supported");
4813 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4816 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4817 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4818 EVT SrcVT = SV->getValueType(0);
4819 SDValue V1 = SV->getOperand(0);
4822 int EltNo = SV->getSplatIndex();
4823 int NumElems = SrcVT.getVectorNumElements();
4824 bool Is256BitVec = SrcVT.is256BitVector();
4826 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
4827 "Unknown how to promote splat for type");
4829 // Extract the 128-bit part containing the splat element and update
4830 // the splat element index when it refers to the higher register.
4832 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4833 if (EltNo >= NumElems/2)
4834 EltNo -= NumElems/2;
4837 // All i16 and i8 vector types can't be used directly by a generic shuffle
4838 // instruction because the target has no such instruction. Generate shuffles
4839 // which repeat i16 and i8 several times until they fit in i32, and then can
4840 // be manipulated by target suported shuffles.
4841 EVT EltVT = SrcVT.getVectorElementType();
4842 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4843 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4845 // Recreate the 256-bit vector and place the same 128-bit vector
4846 // into the low and high part. This is necessary because we want
4847 // to use VPERM* to shuffle the vectors
4849 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4852 return getLegalSplat(DAG, V1, EltNo);
4855 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4856 /// vector of zero or undef vector. This produces a shuffle where the low
4857 /// element of V2 is swizzled into the zero/undef vector, landing at element
4858 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4859 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4861 const X86Subtarget *Subtarget,
4862 SelectionDAG &DAG) {
4863 EVT VT = V2.getValueType();
4865 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4866 unsigned NumElems = VT.getVectorNumElements();
4867 SmallVector<int, 16> MaskVec;
4868 for (unsigned i = 0; i != NumElems; ++i)
4869 // If this is the insertion idx, put the low elt of V2 here.
4870 MaskVec.push_back(i == Idx ? NumElems : i);
4871 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4874 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4875 /// target specific opcode. Returns true if the Mask could be calculated.
4876 /// Sets IsUnary to true if only uses one source.
4877 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4878 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4879 unsigned NumElems = VT.getVectorNumElements();
4883 switch(N->getOpcode()) {
4885 ImmN = N->getOperand(N->getNumOperands()-1);
4886 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4888 case X86ISD::UNPCKH:
4889 DecodeUNPCKHMask(VT, Mask);
4891 case X86ISD::UNPCKL:
4892 DecodeUNPCKLMask(VT, Mask);
4894 case X86ISD::MOVHLPS:
4895 DecodeMOVHLPSMask(NumElems, Mask);
4897 case X86ISD::MOVLHPS:
4898 DecodeMOVLHPSMask(NumElems, Mask);
4900 case X86ISD::PALIGNR:
4901 ImmN = N->getOperand(N->getNumOperands()-1);
4902 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4904 case X86ISD::PSHUFD:
4905 case X86ISD::VPERMILP:
4906 ImmN = N->getOperand(N->getNumOperands()-1);
4907 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4910 case X86ISD::PSHUFHW:
4911 ImmN = N->getOperand(N->getNumOperands()-1);
4912 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4915 case X86ISD::PSHUFLW:
4916 ImmN = N->getOperand(N->getNumOperands()-1);
4917 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4920 case X86ISD::VPERMI:
4921 ImmN = N->getOperand(N->getNumOperands()-1);
4922 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4926 case X86ISD::MOVSD: {
4927 // The index 0 always comes from the first element of the second source,
4928 // this is why MOVSS and MOVSD are used in the first place. The other
4929 // elements come from the other positions of the first source vector
4930 Mask.push_back(NumElems);
4931 for (unsigned i = 1; i != NumElems; ++i) {
4936 case X86ISD::VPERM2X128:
4937 ImmN = N->getOperand(N->getNumOperands()-1);
4938 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4939 if (Mask.empty()) return false;
4941 case X86ISD::MOVDDUP:
4942 case X86ISD::MOVLHPD:
4943 case X86ISD::MOVLPD:
4944 case X86ISD::MOVLPS:
4945 case X86ISD::MOVSHDUP:
4946 case X86ISD::MOVSLDUP:
4947 // Not yet implemented
4949 default: llvm_unreachable("unknown target shuffle node");
4955 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4956 /// element of the result of the vector shuffle.
4957 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4960 return SDValue(); // Limit search depth.
4962 SDValue V = SDValue(N, 0);
4963 EVT VT = V.getValueType();
4964 unsigned Opcode = V.getOpcode();
4966 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4967 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4968 int Elt = SV->getMaskElt(Index);
4971 return DAG.getUNDEF(VT.getVectorElementType());
4973 unsigned NumElems = VT.getVectorNumElements();
4974 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4975 : SV->getOperand(1);
4976 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4979 // Recurse into target specific vector shuffles to find scalars.
4980 if (isTargetShuffle(Opcode)) {
4981 MVT ShufVT = V.getValueType().getSimpleVT();
4982 unsigned NumElems = ShufVT.getVectorNumElements();
4983 SmallVector<int, 16> ShuffleMask;
4986 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4989 int Elt = ShuffleMask[Index];
4991 return DAG.getUNDEF(ShufVT.getVectorElementType());
4993 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4995 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4999 // Actual nodes that may contain scalar elements
5000 if (Opcode == ISD::BITCAST) {
5001 V = V.getOperand(0);
5002 EVT SrcVT = V.getValueType();
5003 unsigned NumElems = VT.getVectorNumElements();
5005 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5009 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5010 return (Index == 0) ? V.getOperand(0)
5011 : DAG.getUNDEF(VT.getVectorElementType());
5013 if (V.getOpcode() == ISD::BUILD_VECTOR)
5014 return V.getOperand(Index);
5019 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5020 /// shuffle operation which come from a consecutively from a zero. The
5021 /// search can start in two different directions, from left or right.
5022 /// We count undefs as zeros until PreferredNum is reached.
5023 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5024 unsigned NumElems, bool ZerosFromLeft,
5026 unsigned PreferredNum = -1U) {
5027 unsigned NumZeros = 0;
5028 for (unsigned i = 0; i != NumElems; ++i) {
5029 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5030 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5034 if (X86::isZeroNode(Elt))
5036 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5037 NumZeros = std::min(NumZeros + 1, PreferredNum);
5045 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5046 /// correspond consecutively to elements from one of the vector operands,
5047 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5049 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5050 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5051 unsigned NumElems, unsigned &OpNum) {
5052 bool SeenV1 = false;
5053 bool SeenV2 = false;
5055 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5056 int Idx = SVOp->getMaskElt(i);
5057 // Ignore undef indicies
5061 if (Idx < (int)NumElems)
5066 // Only accept consecutive elements from the same vector
5067 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5071 OpNum = SeenV1 ? 0 : 1;
5075 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5076 /// logical left shift of a vector.
5077 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5078 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5080 SVOp->getValueType(0).getSimpleVT().getVectorNumElements();
5081 unsigned NumZeros = getNumOfConsecutiveZeros(
5082 SVOp, NumElems, false /* check zeros from right */, DAG,
5083 SVOp->getMaskElt(0));
5089 // Considering the elements in the mask that are not consecutive zeros,
5090 // check if they consecutively come from only one of the source vectors.
5092 // V1 = {X, A, B, C} 0
5094 // vector_shuffle V1, V2 <1, 2, 3, X>
5096 if (!isShuffleMaskConsecutive(SVOp,
5097 0, // Mask Start Index
5098 NumElems-NumZeros, // Mask End Index(exclusive)
5099 NumZeros, // Where to start looking in the src vector
5100 NumElems, // Number of elements in vector
5101 OpSrc)) // Which source operand ?
5106 ShVal = SVOp->getOperand(OpSrc);
5110 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5111 /// logical left shift of a vector.
5112 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5113 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5115 SVOp->getValueType(0).getSimpleVT().getVectorNumElements();
5116 unsigned NumZeros = getNumOfConsecutiveZeros(
5117 SVOp, NumElems, true /* check zeros from left */, DAG,
5118 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5124 // Considering the elements in the mask that are not consecutive zeros,
5125 // check if they consecutively come from only one of the source vectors.
5127 // 0 { A, B, X, X } = V2
5129 // vector_shuffle V1, V2 <X, X, 4, 5>
5131 if (!isShuffleMaskConsecutive(SVOp,
5132 NumZeros, // Mask Start Index
5133 NumElems, // Mask End Index(exclusive)
5134 0, // Where to start looking in the src vector
5135 NumElems, // Number of elements in vector
5136 OpSrc)) // Which source operand ?
5141 ShVal = SVOp->getOperand(OpSrc);
5145 /// isVectorShift - Returns true if the shuffle can be implemented as a
5146 /// logical left or right shift of a vector.
5147 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5148 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5149 // Although the logic below support any bitwidth size, there are no
5150 // shift instructions which handle more than 128-bit vectors.
5151 if (!SVOp->getValueType(0).getSimpleVT().is128BitVector())
5154 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5155 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5161 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5163 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5164 unsigned NumNonZero, unsigned NumZero,
5166 const X86Subtarget* Subtarget,
5167 const TargetLowering &TLI) {
5174 for (unsigned i = 0; i < 16; ++i) {
5175 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5176 if (ThisIsNonZero && First) {
5178 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5180 V = DAG.getUNDEF(MVT::v8i16);
5185 SDValue ThisElt(0, 0), LastElt(0, 0);
5186 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5187 if (LastIsNonZero) {
5188 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5189 MVT::i16, Op.getOperand(i-1));
5191 if (ThisIsNonZero) {
5192 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5193 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5194 ThisElt, DAG.getConstant(8, MVT::i8));
5196 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5200 if (ThisElt.getNode())
5201 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5202 DAG.getIntPtrConstant(i/2));
5206 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5209 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5211 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5212 unsigned NumNonZero, unsigned NumZero,
5214 const X86Subtarget* Subtarget,
5215 const TargetLowering &TLI) {
5222 for (unsigned i = 0; i < 8; ++i) {
5223 bool isNonZero = (NonZeros & (1 << i)) != 0;
5227 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5229 V = DAG.getUNDEF(MVT::v8i16);
5232 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5233 MVT::v8i16, V, Op.getOperand(i),
5234 DAG.getIntPtrConstant(i));
5241 /// getVShift - Return a vector logical shift node.
5243 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5244 unsigned NumBits, SelectionDAG &DAG,
5245 const TargetLowering &TLI, SDLoc dl) {
5246 assert(VT.is128BitVector() && "Unknown type for VShift");
5247 EVT ShVT = MVT::v2i64;
5248 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5249 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5250 return DAG.getNode(ISD::BITCAST, dl, VT,
5251 DAG.getNode(Opc, dl, ShVT, SrcOp,
5252 DAG.getConstant(NumBits,
5253 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5257 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, SDLoc dl,
5258 SelectionDAG &DAG) const {
5260 // Check if the scalar load can be widened into a vector load. And if
5261 // the address is "base + cst" see if the cst can be "absorbed" into
5262 // the shuffle mask.
5263 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5264 SDValue Ptr = LD->getBasePtr();
5265 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5267 EVT PVT = LD->getValueType(0);
5268 if (PVT != MVT::i32 && PVT != MVT::f32)
5273 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5274 FI = FINode->getIndex();
5276 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5277 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5278 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5279 Offset = Ptr.getConstantOperandVal(1);
5280 Ptr = Ptr.getOperand(0);
5285 // FIXME: 256-bit vector instructions don't require a strict alignment,
5286 // improve this code to support it better.
5287 unsigned RequiredAlign = VT.getSizeInBits()/8;
5288 SDValue Chain = LD->getChain();
5289 // Make sure the stack object alignment is at least 16 or 32.
5290 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5291 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5292 if (MFI->isFixedObjectIndex(FI)) {
5293 // Can't change the alignment. FIXME: It's possible to compute
5294 // the exact stack offset and reference FI + adjust offset instead.
5295 // If someone *really* cares about this. That's the way to implement it.
5298 MFI->setObjectAlignment(FI, RequiredAlign);
5302 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5303 // Ptr + (Offset & ~15).
5306 if ((Offset % RequiredAlign) & 3)
5308 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5310 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5311 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5313 int EltNo = (Offset - StartOffset) >> 2;
5314 unsigned NumElems = VT.getVectorNumElements();
5316 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5317 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5318 LD->getPointerInfo().getWithOffset(StartOffset),
5319 false, false, false, 0);
5321 SmallVector<int, 8> Mask;
5322 for (unsigned i = 0; i != NumElems; ++i)
5323 Mask.push_back(EltNo);
5325 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5331 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5332 /// vector of type 'VT', see if the elements can be replaced by a single large
5333 /// load which has the same value as a build_vector whose operands are 'elts'.
5335 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5337 /// FIXME: we'd also like to handle the case where the last elements are zero
5338 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5339 /// There's even a handy isZeroNode for that purpose.
5340 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5341 SDLoc &DL, SelectionDAG &DAG) {
5342 EVT EltVT = VT.getVectorElementType();
5343 unsigned NumElems = Elts.size();
5345 LoadSDNode *LDBase = NULL;
5346 unsigned LastLoadedElt = -1U;
5348 // For each element in the initializer, see if we've found a load or an undef.
5349 // If we don't find an initial load element, or later load elements are
5350 // non-consecutive, bail out.
5351 for (unsigned i = 0; i < NumElems; ++i) {
5352 SDValue Elt = Elts[i];
5354 if (!Elt.getNode() ||
5355 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5358 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5360 LDBase = cast<LoadSDNode>(Elt.getNode());
5364 if (Elt.getOpcode() == ISD::UNDEF)
5367 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5368 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5373 // If we have found an entire vector of loads and undefs, then return a large
5374 // load of the entire vector width starting at the base pointer. If we found
5375 // consecutive loads for the low half, generate a vzext_load node.
5376 if (LastLoadedElt == NumElems - 1) {
5377 SDValue NewLd = SDValue();
5378 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5379 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5380 LDBase->getPointerInfo(),
5381 LDBase->isVolatile(), LDBase->isNonTemporal(),
5382 LDBase->isInvariant(), 0);
5383 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5384 LDBase->getPointerInfo(),
5385 LDBase->isVolatile(), LDBase->isNonTemporal(),
5386 LDBase->isInvariant(), LDBase->getAlignment());
5388 if (LDBase->hasAnyUseOfValue(1)) {
5389 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5391 SDValue(NewLd.getNode(), 1));
5392 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5393 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5394 SDValue(NewLd.getNode(), 1));
5399 if (NumElems == 4 && LastLoadedElt == 1 &&
5400 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5401 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5402 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5404 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops,
5405 array_lengthof(Ops), MVT::i64,
5406 LDBase->getPointerInfo(),
5407 LDBase->getAlignment(),
5408 false/*isVolatile*/, true/*ReadMem*/,
5411 // Make sure the newly-created LOAD is in the same position as LDBase in
5412 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5413 // update uses of LDBase's output chain to use the TokenFactor.
5414 if (LDBase->hasAnyUseOfValue(1)) {
5415 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5416 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5417 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5418 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5419 SDValue(ResNode.getNode(), 1));
5422 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5427 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5428 /// to generate a splat value for the following cases:
5429 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5430 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5431 /// a scalar load, or a constant.
5432 /// The VBROADCAST node is returned when a pattern is found,
5433 /// or SDValue() otherwise.
5435 X86TargetLowering::LowerVectorBroadcast(SDValue Op, SelectionDAG &DAG) const {
5436 if (!Subtarget->hasFp256())
5439 MVT VT = Op.getValueType().getSimpleVT();
5442 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5443 "Unsupported vector type for broadcast.");
5448 switch (Op.getOpcode()) {
5450 // Unknown pattern found.
5453 case ISD::BUILD_VECTOR: {
5454 // The BUILD_VECTOR node must be a splat.
5455 if (!isSplatVector(Op.getNode()))
5458 Ld = Op.getOperand(0);
5459 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5460 Ld.getOpcode() == ISD::ConstantFP);
5462 // The suspected load node has several users. Make sure that all
5463 // of its users are from the BUILD_VECTOR node.
5464 // Constants may have multiple users.
5465 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5470 case ISD::VECTOR_SHUFFLE: {
5471 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5473 // Shuffles must have a splat mask where the first element is
5475 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5478 SDValue Sc = Op.getOperand(0);
5479 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5480 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5482 if (!Subtarget->hasInt256())
5485 // Use the register form of the broadcast instruction available on AVX2.
5486 if (VT.getSizeInBits() >= 256)
5487 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5488 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5491 Ld = Sc.getOperand(0);
5492 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5493 Ld.getOpcode() == ISD::ConstantFP);
5495 // The scalar_to_vector node and the suspected
5496 // load node must have exactly one user.
5497 // Constants may have multiple users.
5499 // AVX-512 has register version of the broadcast
5500 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5501 Ld.getValueType().getSizeInBits() >= 32;
5502 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5509 bool IsGE256 = (VT.getSizeInBits() >= 256);
5511 // Handle the broadcasting a single constant scalar from the constant pool
5512 // into a vector. On Sandybridge it is still better to load a constant vector
5513 // from the constant pool and not to broadcast it from a scalar.
5514 if (ConstSplatVal && Subtarget->hasInt256()) {
5515 EVT CVT = Ld.getValueType();
5516 assert(!CVT.isVector() && "Must not broadcast a vector type");
5517 unsigned ScalarSize = CVT.getSizeInBits();
5519 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
5520 const Constant *C = 0;
5521 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5522 C = CI->getConstantIntValue();
5523 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5524 C = CF->getConstantFPValue();
5526 assert(C && "Invalid constant type");
5528 SDValue CP = DAG.getConstantPool(C, getPointerTy());
5529 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5530 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5531 MachinePointerInfo::getConstantPool(),
5532 false, false, false, Alignment);
5534 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5538 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5539 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5541 // Handle AVX2 in-register broadcasts.
5542 if (!IsLoad && Subtarget->hasInt256() &&
5543 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5544 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5546 // The scalar source must be a normal load.
5550 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
5551 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5553 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5554 // double since there is no vbroadcastsd xmm
5555 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5556 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5557 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5560 // Unsupported broadcast.
5565 X86TargetLowering::buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) const {
5566 EVT VT = Op.getValueType();
5568 // Skip if insert_vec_elt is not supported.
5569 if (!isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5573 unsigned NumElems = Op.getNumOperands();
5577 SmallVector<unsigned, 4> InsertIndices;
5578 SmallVector<int, 8> Mask(NumElems, -1);
5580 for (unsigned i = 0; i != NumElems; ++i) {
5581 unsigned Opc = Op.getOperand(i).getOpcode();
5583 if (Opc == ISD::UNDEF)
5586 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5587 // Quit if more than 1 elements need inserting.
5588 if (InsertIndices.size() > 1)
5591 InsertIndices.push_back(i);
5595 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5596 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5598 // Quit if extracted from vector of different type.
5599 if (ExtractedFromVec.getValueType() != VT)
5602 // Quit if non-constant index.
5603 if (!isa<ConstantSDNode>(ExtIdx))
5606 if (VecIn1.getNode() == 0)
5607 VecIn1 = ExtractedFromVec;
5608 else if (VecIn1 != ExtractedFromVec) {
5609 if (VecIn2.getNode() == 0)
5610 VecIn2 = ExtractedFromVec;
5611 else if (VecIn2 != ExtractedFromVec)
5612 // Quit if more than 2 vectors to shuffle
5616 unsigned Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5618 if (ExtractedFromVec == VecIn1)
5620 else if (ExtractedFromVec == VecIn2)
5621 Mask[i] = Idx + NumElems;
5624 if (VecIn1.getNode() == 0)
5627 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5628 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5629 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5630 unsigned Idx = InsertIndices[i];
5631 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5632 DAG.getIntPtrConstant(Idx));
5638 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5640 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5642 EVT VT = Op.getValueType();
5643 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5644 "Unexpected type in LowerBUILD_VECTORvXi1!");
5647 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5648 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5649 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5650 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5651 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5652 Ops, VT.getVectorNumElements());
5655 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5656 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
5657 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5658 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5659 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5660 Ops, VT.getVectorNumElements());
5663 bool AllContants = true;
5664 uint64_t Immediate = 0;
5665 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5666 SDValue In = Op.getOperand(idx);
5667 if (In.getOpcode() == ISD::UNDEF)
5669 if (!isa<ConstantSDNode>(In)) {
5670 AllContants = false;
5673 if (cast<ConstantSDNode>(In)->getZExtValue())
5674 Immediate |= (1ULL << idx);
5678 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
5679 DAG.getConstant(Immediate, MVT::i16));
5680 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
5681 DAG.getIntPtrConstant(0));
5684 if (!isSplatVector(Op.getNode()))
5685 llvm_unreachable("Unsupported predicate operation");
5687 SDValue In = Op.getOperand(0);
5688 SDValue EFLAGS, X86CC;
5689 if (In.getOpcode() == ISD::SETCC) {
5690 SDValue Op0 = In.getOperand(0);
5691 SDValue Op1 = In.getOperand(1);
5692 ISD::CondCode CC = cast<CondCodeSDNode>(In.getOperand(2))->get();
5693 bool isFP = Op1.getValueType().isFloatingPoint();
5694 unsigned X86CCVal = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5696 assert(X86CCVal != X86::COND_INVALID && "Unsupported predicate operation");
5698 X86CC = DAG.getConstant(X86CCVal, MVT::i8);
5699 EFLAGS = EmitCmp(Op0, Op1, X86CCVal, DAG);
5700 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
5701 } else if (In.getOpcode() == X86ISD::SETCC) {
5702 X86CC = In.getOperand(0);
5703 EFLAGS = In.getOperand(1);
5712 // res = allOnes ### CMOVNE -1, %res
5715 MVT InVT = In.getValueType().getSimpleVT();
5716 SDValue Bit1 = DAG.getNode(ISD::AND, dl, InVT, In, DAG.getConstant(1, InVT));
5717 EFLAGS = EmitTest(Bit1, X86::COND_NE, DAG);
5718 X86CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5721 if (VT == MVT::v16i1) {
5722 SDValue Cst1 = DAG.getConstant(-1, MVT::i16);
5723 SDValue Cst0 = DAG.getConstant(0, MVT::i16);
5724 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i16,
5725 Cst0, Cst1, X86CC, EFLAGS);
5726 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5729 if (VT == MVT::v8i1) {
5730 SDValue Cst1 = DAG.getConstant(-1, MVT::i32);
5731 SDValue Cst0 = DAG.getConstant(0, MVT::i32);
5732 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i32,
5733 Cst0, Cst1, X86CC, EFLAGS);
5734 CmovOp = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CmovOp);
5735 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5737 llvm_unreachable("Unsupported predicate operation");
5741 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5744 MVT VT = Op.getValueType().getSimpleVT();
5745 MVT ExtVT = VT.getVectorElementType();
5746 unsigned NumElems = Op.getNumOperands();
5748 // Generate vectors for predicate vectors.
5749 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5750 return LowerBUILD_VECTORvXi1(Op, DAG);
5752 // Vectors containing all zeros can be matched by pxor and xorps later
5753 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5754 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5755 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5756 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5759 return getZeroVector(VT, Subtarget, DAG, dl);
5762 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5763 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5764 // vpcmpeqd on 256-bit vectors.
5765 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5766 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5769 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5772 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
5773 if (Broadcast.getNode())
5776 unsigned EVTBits = ExtVT.getSizeInBits();
5778 unsigned NumZero = 0;
5779 unsigned NumNonZero = 0;
5780 unsigned NonZeros = 0;
5781 bool IsAllConstants = true;
5782 SmallSet<SDValue, 8> Values;
5783 for (unsigned i = 0; i < NumElems; ++i) {
5784 SDValue Elt = Op.getOperand(i);
5785 if (Elt.getOpcode() == ISD::UNDEF)
5788 if (Elt.getOpcode() != ISD::Constant &&
5789 Elt.getOpcode() != ISD::ConstantFP)
5790 IsAllConstants = false;
5791 if (X86::isZeroNode(Elt))
5794 NonZeros |= (1 << i);
5799 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5800 if (NumNonZero == 0)
5801 return DAG.getUNDEF(VT);
5803 // Special case for single non-zero, non-undef, element.
5804 if (NumNonZero == 1) {
5805 unsigned Idx = countTrailingZeros(NonZeros);
5806 SDValue Item = Op.getOperand(Idx);
5808 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5809 // the value are obviously zero, truncate the value to i32 and do the
5810 // insertion that way. Only do this if the value is non-constant or if the
5811 // value is a constant being inserted into element 0. It is cheaper to do
5812 // a constant pool load than it is to do a movd + shuffle.
5813 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5814 (!IsAllConstants || Idx == 0)) {
5815 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5817 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5818 EVT VecVT = MVT::v4i32;
5819 unsigned VecElts = 4;
5821 // Truncate the value (which may itself be a constant) to i32, and
5822 // convert it to a vector with movd (S2V+shuffle to zero extend).
5823 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5824 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5825 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5827 // Now we have our 32-bit value zero extended in the low element of
5828 // a vector. If Idx != 0, swizzle it into place.
5830 SmallVector<int, 4> Mask;
5831 Mask.push_back(Idx);
5832 for (unsigned i = 1; i != VecElts; ++i)
5834 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5837 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5841 // If we have a constant or non-constant insertion into the low element of
5842 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5843 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5844 // depending on what the source datatype is.
5847 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5849 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5850 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5851 if (VT.is256BitVector()) {
5852 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5853 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5854 Item, DAG.getIntPtrConstant(0));
5856 assert(VT.is128BitVector() && "Expected an SSE value type!");
5857 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5858 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5859 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5862 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5863 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5864 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5865 if (VT.is256BitVector()) {
5866 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5867 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5869 assert(VT.is128BitVector() && "Expected an SSE value type!");
5870 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5872 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5876 // Is it a vector logical left shift?
5877 if (NumElems == 2 && Idx == 1 &&
5878 X86::isZeroNode(Op.getOperand(0)) &&
5879 !X86::isZeroNode(Op.getOperand(1))) {
5880 unsigned NumBits = VT.getSizeInBits();
5881 return getVShift(true, VT,
5882 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5883 VT, Op.getOperand(1)),
5884 NumBits/2, DAG, *this, dl);
5887 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5890 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5891 // is a non-constant being inserted into an element other than the low one,
5892 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5893 // movd/movss) to move this into the low element, then shuffle it into
5895 if (EVTBits == 32) {
5896 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5898 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5899 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5900 SmallVector<int, 8> MaskVec;
5901 for (unsigned i = 0; i != NumElems; ++i)
5902 MaskVec.push_back(i == Idx ? 0 : 1);
5903 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5907 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5908 if (Values.size() == 1) {
5909 if (EVTBits == 32) {
5910 // Instead of a shuffle like this:
5911 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5912 // Check if it's possible to issue this instead.
5913 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5914 unsigned Idx = countTrailingZeros(NonZeros);
5915 SDValue Item = Op.getOperand(Idx);
5916 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5917 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5922 // A vector full of immediates; various special cases are already
5923 // handled, so this is best done with a single constant-pool load.
5927 // For AVX-length vectors, build the individual 128-bit pieces and use
5928 // shuffles to put them in place.
5929 if (VT.is256BitVector()) {
5930 SmallVector<SDValue, 32> V;
5931 for (unsigned i = 0; i != NumElems; ++i)
5932 V.push_back(Op.getOperand(i));
5934 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5936 // Build both the lower and upper subvector.
5937 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5938 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5941 // Recreate the wider vector with the lower and upper part.
5942 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5945 // Let legalizer expand 2-wide build_vectors.
5946 if (EVTBits == 64) {
5947 if (NumNonZero == 1) {
5948 // One half is zero or undef.
5949 unsigned Idx = countTrailingZeros(NonZeros);
5950 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5951 Op.getOperand(Idx));
5952 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5957 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5958 if (EVTBits == 8 && NumElems == 16) {
5959 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5961 if (V.getNode()) return V;
5964 if (EVTBits == 16 && NumElems == 8) {
5965 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5967 if (V.getNode()) return V;
5970 // If element VT is == 32 bits, turn it into a number of shuffles.
5971 SmallVector<SDValue, 8> V(NumElems);
5972 if (NumElems == 4 && NumZero > 0) {
5973 for (unsigned i = 0; i < 4; ++i) {
5974 bool isZero = !(NonZeros & (1 << i));
5976 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5978 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5981 for (unsigned i = 0; i < 2; ++i) {
5982 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5985 V[i] = V[i*2]; // Must be a zero vector.
5988 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5991 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5994 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5999 bool Reverse1 = (NonZeros & 0x3) == 2;
6000 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6004 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6005 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6007 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6010 if (Values.size() > 1 && VT.is128BitVector()) {
6011 // Check for a build vector of consecutive loads.
6012 for (unsigned i = 0; i < NumElems; ++i)
6013 V[i] = Op.getOperand(i);
6015 // Check for elements which are consecutive loads.
6016 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
6020 // Check for a build vector from mostly shuffle plus few inserting.
6021 SDValue Sh = buildFromShuffleMostly(Op, DAG);
6025 // For SSE 4.1, use insertps to put the high elements into the low element.
6026 if (getSubtarget()->hasSSE41()) {
6028 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6029 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6031 Result = DAG.getUNDEF(VT);
6033 for (unsigned i = 1; i < NumElems; ++i) {
6034 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6035 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6036 Op.getOperand(i), DAG.getIntPtrConstant(i));
6041 // Otherwise, expand into a number of unpckl*, start by extending each of
6042 // our (non-undef) elements to the full vector width with the element in the
6043 // bottom slot of the vector (which generates no code for SSE).
6044 for (unsigned i = 0; i < NumElems; ++i) {
6045 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6046 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6048 V[i] = DAG.getUNDEF(VT);
6051 // Next, we iteratively mix elements, e.g. for v4f32:
6052 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6053 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6054 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6055 unsigned EltStride = NumElems >> 1;
6056 while (EltStride != 0) {
6057 for (unsigned i = 0; i < EltStride; ++i) {
6058 // If V[i+EltStride] is undef and this is the first round of mixing,
6059 // then it is safe to just drop this shuffle: V[i] is already in the
6060 // right place, the one element (since it's the first round) being
6061 // inserted as undef can be dropped. This isn't safe for successive
6062 // rounds because they will permute elements within both vectors.
6063 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6064 EltStride == NumElems/2)
6067 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6076 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6077 // to create 256-bit vectors from two other 128-bit ones.
6078 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6080 MVT ResVT = Op.getValueType().getSimpleVT();
6082 assert((ResVT.is256BitVector() ||
6083 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6085 SDValue V1 = Op.getOperand(0);
6086 SDValue V2 = Op.getOperand(1);
6087 unsigned NumElems = ResVT.getVectorNumElements();
6088 if(ResVT.is256BitVector())
6089 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6091 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6094 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6095 assert(Op.getNumOperands() == 2);
6097 // AVX/AVX-512 can use the vinsertf128 instruction to create 256-bit vectors
6098 // from two other 128-bit ones.
6099 return LowerAVXCONCAT_VECTORS(Op, DAG);
6102 // Try to lower a shuffle node into a simple blend instruction.
6104 LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
6105 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6106 SDValue V1 = SVOp->getOperand(0);
6107 SDValue V2 = SVOp->getOperand(1);
6109 MVT VT = SVOp->getValueType(0).getSimpleVT();
6110 MVT EltVT = VT.getVectorElementType();
6111 unsigned NumElems = VT.getVectorNumElements();
6113 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
6115 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
6118 // Check the mask for BLEND and build the value.
6119 unsigned MaskValue = 0;
6120 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
6121 unsigned NumLanes = (NumElems-1)/8 + 1;
6122 unsigned NumElemsInLane = NumElems / NumLanes;
6124 // Blend for v16i16 should be symetric for the both lanes.
6125 for (unsigned i = 0; i < NumElemsInLane; ++i) {
6127 int SndLaneEltIdx = (NumLanes == 2) ?
6128 SVOp->getMaskElt(i + NumElemsInLane) : -1;
6129 int EltIdx = SVOp->getMaskElt(i);
6131 if ((EltIdx < 0 || EltIdx == (int)i) &&
6132 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
6135 if (((unsigned)EltIdx == (i + NumElems)) &&
6136 (SndLaneEltIdx < 0 ||
6137 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
6138 MaskValue |= (1<<i);
6143 // Convert i32 vectors to floating point if it is not AVX2.
6144 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
6146 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
6147 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
6149 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
6150 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
6153 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
6154 DAG.getConstant(MaskValue, MVT::i32));
6155 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
6158 // v8i16 shuffles - Prefer shuffles in the following order:
6159 // 1. [all] pshuflw, pshufhw, optional move
6160 // 2. [ssse3] 1 x pshufb
6161 // 3. [ssse3] 2 x pshufb + 1 x por
6162 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
6164 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
6165 SelectionDAG &DAG) {
6166 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6167 SDValue V1 = SVOp->getOperand(0);
6168 SDValue V2 = SVOp->getOperand(1);
6170 SmallVector<int, 8> MaskVals;
6172 // Determine if more than 1 of the words in each of the low and high quadwords
6173 // of the result come from the same quadword of one of the two inputs. Undef
6174 // mask values count as coming from any quadword, for better codegen.
6175 unsigned LoQuad[] = { 0, 0, 0, 0 };
6176 unsigned HiQuad[] = { 0, 0, 0, 0 };
6177 std::bitset<4> InputQuads;
6178 for (unsigned i = 0; i < 8; ++i) {
6179 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
6180 int EltIdx = SVOp->getMaskElt(i);
6181 MaskVals.push_back(EltIdx);
6190 InputQuads.set(EltIdx / 4);
6193 int BestLoQuad = -1;
6194 unsigned MaxQuad = 1;
6195 for (unsigned i = 0; i < 4; ++i) {
6196 if (LoQuad[i] > MaxQuad) {
6198 MaxQuad = LoQuad[i];
6202 int BestHiQuad = -1;
6204 for (unsigned i = 0; i < 4; ++i) {
6205 if (HiQuad[i] > MaxQuad) {
6207 MaxQuad = HiQuad[i];
6211 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
6212 // of the two input vectors, shuffle them into one input vector so only a
6213 // single pshufb instruction is necessary. If There are more than 2 input
6214 // quads, disable the next transformation since it does not help SSSE3.
6215 bool V1Used = InputQuads[0] || InputQuads[1];
6216 bool V2Used = InputQuads[2] || InputQuads[3];
6217 if (Subtarget->hasSSSE3()) {
6218 if (InputQuads.count() == 2 && V1Used && V2Used) {
6219 BestLoQuad = InputQuads[0] ? 0 : 1;
6220 BestHiQuad = InputQuads[2] ? 2 : 3;
6222 if (InputQuads.count() > 2) {
6228 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
6229 // the shuffle mask. If a quad is scored as -1, that means that it contains
6230 // words from all 4 input quadwords.
6232 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
6234 BestLoQuad < 0 ? 0 : BestLoQuad,
6235 BestHiQuad < 0 ? 1 : BestHiQuad
6237 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
6238 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
6239 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
6240 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
6242 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
6243 // source words for the shuffle, to aid later transformations.
6244 bool AllWordsInNewV = true;
6245 bool InOrder[2] = { true, true };
6246 for (unsigned i = 0; i != 8; ++i) {
6247 int idx = MaskVals[i];
6249 InOrder[i/4] = false;
6250 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
6252 AllWordsInNewV = false;
6256 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
6257 if (AllWordsInNewV) {
6258 for (int i = 0; i != 8; ++i) {
6259 int idx = MaskVals[i];
6262 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
6263 if ((idx != i) && idx < 4)
6265 if ((idx != i) && idx > 3)
6274 // If we've eliminated the use of V2, and the new mask is a pshuflw or
6275 // pshufhw, that's as cheap as it gets. Return the new shuffle.
6276 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
6277 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
6278 unsigned TargetMask = 0;
6279 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
6280 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
6281 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6282 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
6283 getShufflePSHUFLWImmediate(SVOp);
6284 V1 = NewV.getOperand(0);
6285 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
6289 // Promote splats to a larger type which usually leads to more efficient code.
6290 // FIXME: Is this true if pshufb is available?
6291 if (SVOp->isSplat())
6292 return PromoteSplat(SVOp, DAG);
6294 // If we have SSSE3, and all words of the result are from 1 input vector,
6295 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
6296 // is present, fall back to case 4.
6297 if (Subtarget->hasSSSE3()) {
6298 SmallVector<SDValue,16> pshufbMask;
6300 // If we have elements from both input vectors, set the high bit of the
6301 // shuffle mask element to zero out elements that come from V2 in the V1
6302 // mask, and elements that come from V1 in the V2 mask, so that the two
6303 // results can be OR'd together.
6304 bool TwoInputs = V1Used && V2Used;
6305 for (unsigned i = 0; i != 8; ++i) {
6306 int EltIdx = MaskVals[i] * 2;
6307 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
6308 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
6309 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6310 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6312 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
6313 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6314 DAG.getNode(ISD::BUILD_VECTOR, dl,
6315 MVT::v16i8, &pshufbMask[0], 16));
6317 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6319 // Calculate the shuffle mask for the second input, shuffle it, and
6320 // OR it with the first shuffled input.
6322 for (unsigned i = 0; i != 8; ++i) {
6323 int EltIdx = MaskVals[i] * 2;
6324 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6325 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
6326 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6327 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6329 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
6330 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6331 DAG.getNode(ISD::BUILD_VECTOR, dl,
6332 MVT::v16i8, &pshufbMask[0], 16));
6333 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6334 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6337 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
6338 // and update MaskVals with new element order.
6339 std::bitset<8> InOrder;
6340 if (BestLoQuad >= 0) {
6341 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
6342 for (int i = 0; i != 4; ++i) {
6343 int idx = MaskVals[i];
6346 } else if ((idx / 4) == BestLoQuad) {
6351 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6354 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6355 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6356 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
6358 getShufflePSHUFLWImmediate(SVOp), DAG);
6362 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
6363 // and update MaskVals with the new element order.
6364 if (BestHiQuad >= 0) {
6365 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
6366 for (unsigned i = 4; i != 8; ++i) {
6367 int idx = MaskVals[i];
6370 } else if ((idx / 4) == BestHiQuad) {
6371 MaskV[i] = (idx & 3) + 4;
6375 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6378 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6379 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6380 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
6382 getShufflePSHUFHWImmediate(SVOp), DAG);
6386 // In case BestHi & BestLo were both -1, which means each quadword has a word
6387 // from each of the four input quadwords, calculate the InOrder bitvector now
6388 // before falling through to the insert/extract cleanup.
6389 if (BestLoQuad == -1 && BestHiQuad == -1) {
6391 for (int i = 0; i != 8; ++i)
6392 if (MaskVals[i] < 0 || MaskVals[i] == i)
6396 // The other elements are put in the right place using pextrw and pinsrw.
6397 for (unsigned i = 0; i != 8; ++i) {
6400 int EltIdx = MaskVals[i];
6403 SDValue ExtOp = (EltIdx < 8) ?
6404 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
6405 DAG.getIntPtrConstant(EltIdx)) :
6406 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
6407 DAG.getIntPtrConstant(EltIdx - 8));
6408 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
6409 DAG.getIntPtrConstant(i));
6414 // v16i8 shuffles - Prefer shuffles in the following order:
6415 // 1. [ssse3] 1 x pshufb
6416 // 2. [ssse3] 2 x pshufb + 1 x por
6417 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
6419 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
6421 const X86TargetLowering &TLI) {
6422 SDValue V1 = SVOp->getOperand(0);
6423 SDValue V2 = SVOp->getOperand(1);
6425 ArrayRef<int> MaskVals = SVOp->getMask();
6427 // Promote splats to a larger type which usually leads to more efficient code.
6428 // FIXME: Is this true if pshufb is available?
6429 if (SVOp->isSplat())
6430 return PromoteSplat(SVOp, DAG);
6432 // If we have SSSE3, case 1 is generated when all result bytes come from
6433 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
6434 // present, fall back to case 3.
6436 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
6437 if (TLI.getSubtarget()->hasSSSE3()) {
6438 SmallVector<SDValue,16> pshufbMask;
6440 // If all result elements are from one input vector, then only translate
6441 // undef mask values to 0x80 (zero out result) in the pshufb mask.
6443 // Otherwise, we have elements from both input vectors, and must zero out
6444 // elements that come from V2 in the first mask, and V1 in the second mask
6445 // so that we can OR them together.
6446 for (unsigned i = 0; i != 16; ++i) {
6447 int EltIdx = MaskVals[i];
6448 if (EltIdx < 0 || EltIdx >= 16)
6450 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6452 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6453 DAG.getNode(ISD::BUILD_VECTOR, dl,
6454 MVT::v16i8, &pshufbMask[0], 16));
6456 // As PSHUFB will zero elements with negative indices, it's safe to ignore
6457 // the 2nd operand if it's undefined or zero.
6458 if (V2.getOpcode() == ISD::UNDEF ||
6459 ISD::isBuildVectorAllZeros(V2.getNode()))
6462 // Calculate the shuffle mask for the second input, shuffle it, and
6463 // OR it with the first shuffled input.
6465 for (unsigned i = 0; i != 16; ++i) {
6466 int EltIdx = MaskVals[i];
6467 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6468 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6470 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6471 DAG.getNode(ISD::BUILD_VECTOR, dl,
6472 MVT::v16i8, &pshufbMask[0], 16));
6473 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6476 // No SSSE3 - Calculate in place words and then fix all out of place words
6477 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
6478 // the 16 different words that comprise the two doublequadword input vectors.
6479 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6480 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
6482 for (int i = 0; i != 8; ++i) {
6483 int Elt0 = MaskVals[i*2];
6484 int Elt1 = MaskVals[i*2+1];
6486 // This word of the result is all undef, skip it.
6487 if (Elt0 < 0 && Elt1 < 0)
6490 // This word of the result is already in the correct place, skip it.
6491 if ((Elt0 == i*2) && (Elt1 == i*2+1))
6494 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
6495 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
6498 // If Elt0 and Elt1 are defined, are consecutive, and can be load
6499 // using a single extract together, load it and store it.
6500 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
6501 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6502 DAG.getIntPtrConstant(Elt1 / 2));
6503 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6504 DAG.getIntPtrConstant(i));
6508 // If Elt1 is defined, extract it from the appropriate source. If the
6509 // source byte is not also odd, shift the extracted word left 8 bits
6510 // otherwise clear the bottom 8 bits if we need to do an or.
6512 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6513 DAG.getIntPtrConstant(Elt1 / 2));
6514 if ((Elt1 & 1) == 0)
6515 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
6517 TLI.getShiftAmountTy(InsElt.getValueType())));
6519 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
6520 DAG.getConstant(0xFF00, MVT::i16));
6522 // If Elt0 is defined, extract it from the appropriate source. If the
6523 // source byte is not also even, shift the extracted word right 8 bits. If
6524 // Elt1 was also defined, OR the extracted values together before
6525 // inserting them in the result.
6527 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
6528 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
6529 if ((Elt0 & 1) != 0)
6530 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
6532 TLI.getShiftAmountTy(InsElt0.getValueType())));
6534 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
6535 DAG.getConstant(0x00FF, MVT::i16));
6536 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
6539 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6540 DAG.getIntPtrConstant(i));
6542 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
6545 // v32i8 shuffles - Translate to VPSHUFB if possible.
6547 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
6548 const X86Subtarget *Subtarget,
6549 SelectionDAG &DAG) {
6550 MVT VT = SVOp->getValueType(0).getSimpleVT();
6551 SDValue V1 = SVOp->getOperand(0);
6552 SDValue V2 = SVOp->getOperand(1);
6554 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
6556 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6557 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
6558 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
6560 // VPSHUFB may be generated if
6561 // (1) one of input vector is undefined or zeroinitializer.
6562 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
6563 // And (2) the mask indexes don't cross the 128-bit lane.
6564 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
6565 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
6568 if (V1IsAllZero && !V2IsAllZero) {
6569 CommuteVectorShuffleMask(MaskVals, 32);
6572 SmallVector<SDValue, 32> pshufbMask;
6573 for (unsigned i = 0; i != 32; i++) {
6574 int EltIdx = MaskVals[i];
6575 if (EltIdx < 0 || EltIdx >= 32)
6578 if ((EltIdx >= 16 && i < 16) || (EltIdx < 16 && i >= 16))
6579 // Cross lane is not allowed.
6583 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6585 return DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, V1,
6586 DAG.getNode(ISD::BUILD_VECTOR, dl,
6587 MVT::v32i8, &pshufbMask[0], 32));
6590 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
6591 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
6592 /// done when every pair / quad of shuffle mask elements point to elements in
6593 /// the right sequence. e.g.
6594 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
6596 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
6597 SelectionDAG &DAG) {
6598 MVT VT = SVOp->getValueType(0).getSimpleVT();
6600 unsigned NumElems = VT.getVectorNumElements();
6603 switch (VT.SimpleTy) {
6604 default: llvm_unreachable("Unexpected!");
6605 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
6606 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
6607 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
6608 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
6609 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
6610 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
6613 SmallVector<int, 8> MaskVec;
6614 for (unsigned i = 0; i != NumElems; i += Scale) {
6616 for (unsigned j = 0; j != Scale; ++j) {
6617 int EltIdx = SVOp->getMaskElt(i+j);
6621 StartIdx = (EltIdx / Scale);
6622 if (EltIdx != (int)(StartIdx*Scale + j))
6625 MaskVec.push_back(StartIdx);
6628 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
6629 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
6630 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
6633 /// getVZextMovL - Return a zero-extending vector move low node.
6635 static SDValue getVZextMovL(MVT VT, EVT OpVT,
6636 SDValue SrcOp, SelectionDAG &DAG,
6637 const X86Subtarget *Subtarget, SDLoc dl) {
6638 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
6639 LoadSDNode *LD = NULL;
6640 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
6641 LD = dyn_cast<LoadSDNode>(SrcOp);
6643 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
6645 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
6646 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
6647 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6648 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
6649 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
6651 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
6652 return DAG.getNode(ISD::BITCAST, dl, VT,
6653 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6654 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6662 return DAG.getNode(ISD::BITCAST, dl, VT,
6663 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6664 DAG.getNode(ISD::BITCAST, dl,
6668 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
6669 /// which could not be matched by any known target speficic shuffle
6671 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6673 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
6674 if (NewOp.getNode())
6677 MVT VT = SVOp->getValueType(0).getSimpleVT();
6679 unsigned NumElems = VT.getVectorNumElements();
6680 unsigned NumLaneElems = NumElems / 2;
6683 MVT EltVT = VT.getVectorElementType();
6684 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6687 SmallVector<int, 16> Mask;
6688 for (unsigned l = 0; l < 2; ++l) {
6689 // Build a shuffle mask for the output, discovering on the fly which
6690 // input vectors to use as shuffle operands (recorded in InputUsed).
6691 // If building a suitable shuffle vector proves too hard, then bail
6692 // out with UseBuildVector set.
6693 bool UseBuildVector = false;
6694 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6695 unsigned LaneStart = l * NumLaneElems;
6696 for (unsigned i = 0; i != NumLaneElems; ++i) {
6697 // The mask element. This indexes into the input.
6698 int Idx = SVOp->getMaskElt(i+LaneStart);
6700 // the mask element does not index into any input vector.
6705 // The input vector this mask element indexes into.
6706 int Input = Idx / NumLaneElems;
6708 // Turn the index into an offset from the start of the input vector.
6709 Idx -= Input * NumLaneElems;
6711 // Find or create a shuffle vector operand to hold this input.
6713 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6714 if (InputUsed[OpNo] == Input)
6715 // This input vector is already an operand.
6717 if (InputUsed[OpNo] < 0) {
6718 // Create a new operand for this input vector.
6719 InputUsed[OpNo] = Input;
6724 if (OpNo >= array_lengthof(InputUsed)) {
6725 // More than two input vectors used! Give up on trying to create a
6726 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6727 UseBuildVector = true;
6731 // Add the mask index for the new shuffle vector.
6732 Mask.push_back(Idx + OpNo * NumLaneElems);
6735 if (UseBuildVector) {
6736 SmallVector<SDValue, 16> SVOps;
6737 for (unsigned i = 0; i != NumLaneElems; ++i) {
6738 // The mask element. This indexes into the input.
6739 int Idx = SVOp->getMaskElt(i+LaneStart);
6741 SVOps.push_back(DAG.getUNDEF(EltVT));
6745 // The input vector this mask element indexes into.
6746 int Input = Idx / NumElems;
6748 // Turn the index into an offset from the start of the input vector.
6749 Idx -= Input * NumElems;
6751 // Extract the vector element by hand.
6752 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6753 SVOp->getOperand(Input),
6754 DAG.getIntPtrConstant(Idx)));
6757 // Construct the output using a BUILD_VECTOR.
6758 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6760 } else if (InputUsed[0] < 0) {
6761 // No input vectors were used! The result is undefined.
6762 Output[l] = DAG.getUNDEF(NVT);
6764 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6765 (InputUsed[0] % 2) * NumLaneElems,
6767 // If only one input was used, use an undefined vector for the other.
6768 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6769 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6770 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6771 // At least one input vector was used. Create a new shuffle vector.
6772 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6778 // Concatenate the result back
6779 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6782 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6783 /// 4 elements, and match them with several different shuffle types.
6785 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6786 SDValue V1 = SVOp->getOperand(0);
6787 SDValue V2 = SVOp->getOperand(1);
6789 MVT VT = SVOp->getValueType(0).getSimpleVT();
6791 assert(VT.is128BitVector() && "Unsupported vector size");
6793 std::pair<int, int> Locs[4];
6794 int Mask1[] = { -1, -1, -1, -1 };
6795 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6799 for (unsigned i = 0; i != 4; ++i) {
6800 int Idx = PermMask[i];
6802 Locs[i] = std::make_pair(-1, -1);
6804 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6806 Locs[i] = std::make_pair(0, NumLo);
6810 Locs[i] = std::make_pair(1, NumHi);
6812 Mask1[2+NumHi] = Idx;
6818 if (NumLo <= 2 && NumHi <= 2) {
6819 // If no more than two elements come from either vector. This can be
6820 // implemented with two shuffles. First shuffle gather the elements.
6821 // The second shuffle, which takes the first shuffle as both of its
6822 // vector operands, put the elements into the right order.
6823 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6825 int Mask2[] = { -1, -1, -1, -1 };
6827 for (unsigned i = 0; i != 4; ++i)
6828 if (Locs[i].first != -1) {
6829 unsigned Idx = (i < 2) ? 0 : 4;
6830 Idx += Locs[i].first * 2 + Locs[i].second;
6834 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6837 if (NumLo == 3 || NumHi == 3) {
6838 // Otherwise, we must have three elements from one vector, call it X, and
6839 // one element from the other, call it Y. First, use a shufps to build an
6840 // intermediate vector with the one element from Y and the element from X
6841 // that will be in the same half in the final destination (the indexes don't
6842 // matter). Then, use a shufps to build the final vector, taking the half
6843 // containing the element from Y from the intermediate, and the other half
6846 // Normalize it so the 3 elements come from V1.
6847 CommuteVectorShuffleMask(PermMask, 4);
6851 // Find the element from V2.
6853 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6854 int Val = PermMask[HiIndex];
6861 Mask1[0] = PermMask[HiIndex];
6863 Mask1[2] = PermMask[HiIndex^1];
6865 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6868 Mask1[0] = PermMask[0];
6869 Mask1[1] = PermMask[1];
6870 Mask1[2] = HiIndex & 1 ? 6 : 4;
6871 Mask1[3] = HiIndex & 1 ? 4 : 6;
6872 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6875 Mask1[0] = HiIndex & 1 ? 2 : 0;
6876 Mask1[1] = HiIndex & 1 ? 0 : 2;
6877 Mask1[2] = PermMask[2];
6878 Mask1[3] = PermMask[3];
6883 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6886 // Break it into (shuffle shuffle_hi, shuffle_lo).
6887 int LoMask[] = { -1, -1, -1, -1 };
6888 int HiMask[] = { -1, -1, -1, -1 };
6890 int *MaskPtr = LoMask;
6891 unsigned MaskIdx = 0;
6894 for (unsigned i = 0; i != 4; ++i) {
6901 int Idx = PermMask[i];
6903 Locs[i] = std::make_pair(-1, -1);
6904 } else if (Idx < 4) {
6905 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6906 MaskPtr[LoIdx] = Idx;
6909 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6910 MaskPtr[HiIdx] = Idx;
6915 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6916 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6917 int MaskOps[] = { -1, -1, -1, -1 };
6918 for (unsigned i = 0; i != 4; ++i)
6919 if (Locs[i].first != -1)
6920 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6921 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6924 static bool MayFoldVectorLoad(SDValue V) {
6925 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6926 V = V.getOperand(0);
6928 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6929 V = V.getOperand(0);
6930 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6931 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6932 // BUILD_VECTOR (load), undef
6933 V = V.getOperand(0);
6935 return MayFoldLoad(V);
6939 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
6940 EVT VT = Op.getValueType();
6942 // Canonizalize to v2f64.
6943 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6944 return DAG.getNode(ISD::BITCAST, dl, VT,
6945 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6950 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
6952 SDValue V1 = Op.getOperand(0);
6953 SDValue V2 = Op.getOperand(1);
6954 EVT VT = Op.getValueType();
6956 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6958 if (HasSSE2 && VT == MVT::v2f64)
6959 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6961 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6962 return DAG.getNode(ISD::BITCAST, dl, VT,
6963 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6964 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6965 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6969 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
6970 SDValue V1 = Op.getOperand(0);
6971 SDValue V2 = Op.getOperand(1);
6972 EVT VT = Op.getValueType();
6974 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6975 "unsupported shuffle type");
6977 if (V2.getOpcode() == ISD::UNDEF)
6981 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6985 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6986 SDValue V1 = Op.getOperand(0);
6987 SDValue V2 = Op.getOperand(1);
6988 EVT VT = Op.getValueType();
6989 unsigned NumElems = VT.getVectorNumElements();
6991 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6992 // operand of these instructions is only memory, so check if there's a
6993 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6995 bool CanFoldLoad = false;
6997 // Trivial case, when V2 comes from a load.
6998 if (MayFoldVectorLoad(V2))
7001 // When V1 is a load, it can be folded later into a store in isel, example:
7002 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
7004 // (MOVLPSmr addr:$src1, VR128:$src2)
7005 // So, recognize this potential and also use MOVLPS or MOVLPD
7006 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
7009 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7011 if (HasSSE2 && NumElems == 2)
7012 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
7015 // If we don't care about the second element, proceed to use movss.
7016 if (SVOp->getMaskElt(1) != -1)
7017 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
7020 // movl and movlp will both match v2i64, but v2i64 is never matched by
7021 // movl earlier because we make it strict to avoid messing with the movlp load
7022 // folding logic (see the code above getMOVLP call). Match it here then,
7023 // this is horrible, but will stay like this until we move all shuffle
7024 // matching to x86 specific nodes. Note that for the 1st condition all
7025 // types are matched with movsd.
7027 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
7028 // as to remove this logic from here, as much as possible
7029 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
7030 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7031 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7034 assert(VT != MVT::v4i32 && "unsupported shuffle type");
7036 // Invert the operand order and use SHUFPS to match it.
7037 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
7038 getShuffleSHUFImmediate(SVOp), DAG);
7041 // Reduce a vector shuffle to zext.
7043 X86TargetLowering::LowerVectorIntExtend(SDValue Op, SelectionDAG &DAG) const {
7044 // PMOVZX is only available from SSE41.
7045 if (!Subtarget->hasSSE41())
7048 EVT VT = Op.getValueType();
7050 // Only AVX2 support 256-bit vector integer extending.
7051 if (!Subtarget->hasInt256() && VT.is256BitVector())
7054 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7056 SDValue V1 = Op.getOperand(0);
7057 SDValue V2 = Op.getOperand(1);
7058 unsigned NumElems = VT.getVectorNumElements();
7060 // Extending is an unary operation and the element type of the source vector
7061 // won't be equal to or larger than i64.
7062 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
7063 VT.getVectorElementType() == MVT::i64)
7066 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
7067 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
7068 while ((1U << Shift) < NumElems) {
7069 if (SVOp->getMaskElt(1U << Shift) == 1)
7072 // The maximal ratio is 8, i.e. from i8 to i64.
7077 // Check the shuffle mask.
7078 unsigned Mask = (1U << Shift) - 1;
7079 for (unsigned i = 0; i != NumElems; ++i) {
7080 int EltIdx = SVOp->getMaskElt(i);
7081 if ((i & Mask) != 0 && EltIdx != -1)
7083 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
7087 LLVMContext *Context = DAG.getContext();
7088 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
7089 EVT NeVT = EVT::getIntegerVT(*Context, NBits);
7090 EVT NVT = EVT::getVectorVT(*Context, NeVT, NumElems >> Shift);
7092 if (!isTypeLegal(NVT))
7095 // Simplify the operand as it's prepared to be fed into shuffle.
7096 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
7097 if (V1.getOpcode() == ISD::BITCAST &&
7098 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
7099 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
7101 .getOperand(0).getValueType().getSizeInBits() == SignificantBits) {
7102 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
7103 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
7104 ConstantSDNode *CIdx =
7105 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
7106 // If it's foldable, i.e. normal load with single use, we will let code
7107 // selection to fold it. Otherwise, we will short the conversion sequence.
7108 if (CIdx && CIdx->getZExtValue() == 0 &&
7109 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
7110 if (V.getValueSizeInBits() > V1.getValueSizeInBits()) {
7111 // The "ext_vec_elt" node is wider than the result node.
7112 // In this case we should extract subvector from V.
7113 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
7114 unsigned Ratio = V.getValueSizeInBits() / V1.getValueSizeInBits();
7115 EVT FullVT = V.getValueType();
7116 EVT SubVecVT = EVT::getVectorVT(*Context,
7117 FullVT.getVectorElementType(),
7118 FullVT.getVectorNumElements()/Ratio);
7119 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
7120 DAG.getIntPtrConstant(0));
7122 V1 = DAG.getNode(ISD::BITCAST, DL, V1.getValueType(), V);
7126 return DAG.getNode(ISD::BITCAST, DL, VT,
7127 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
7131 X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const {
7132 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7133 MVT VT = Op.getValueType().getSimpleVT();
7135 SDValue V1 = Op.getOperand(0);
7136 SDValue V2 = Op.getOperand(1);
7138 if (isZeroShuffle(SVOp))
7139 return getZeroVector(VT, Subtarget, DAG, dl);
7141 // Handle splat operations
7142 if (SVOp->isSplat()) {
7143 // Use vbroadcast whenever the splat comes from a foldable load
7144 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
7145 if (Broadcast.getNode())
7149 // Check integer expanding shuffles.
7150 SDValue NewOp = LowerVectorIntExtend(Op, DAG);
7151 if (NewOp.getNode())
7154 // If the shuffle can be profitably rewritten as a narrower shuffle, then
7156 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
7157 VT == MVT::v16i16 || VT == MVT::v32i8) {
7158 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7159 if (NewOp.getNode())
7160 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
7161 } else if ((VT == MVT::v4i32 ||
7162 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
7163 // FIXME: Figure out a cleaner way to do this.
7164 // Try to make use of movq to zero out the top part.
7165 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
7166 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7167 if (NewOp.getNode()) {
7168 MVT NewVT = NewOp.getValueType().getSimpleVT();
7169 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
7170 NewVT, true, false))
7171 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
7172 DAG, Subtarget, dl);
7174 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
7175 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7176 if (NewOp.getNode()) {
7177 MVT NewVT = NewOp.getValueType().getSimpleVT();
7178 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
7179 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
7180 DAG, Subtarget, dl);
7188 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
7189 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7190 SDValue V1 = Op.getOperand(0);
7191 SDValue V2 = Op.getOperand(1);
7192 MVT VT = Op.getValueType().getSimpleVT();
7194 unsigned NumElems = VT.getVectorNumElements();
7195 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
7196 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
7197 bool V1IsSplat = false;
7198 bool V2IsSplat = false;
7199 bool HasSSE2 = Subtarget->hasSSE2();
7200 bool HasFp256 = Subtarget->hasFp256();
7201 bool HasInt256 = Subtarget->hasInt256();
7202 MachineFunction &MF = DAG.getMachineFunction();
7203 bool OptForSize = MF.getFunction()->getAttributes().
7204 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
7206 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
7208 if (V1IsUndef && V2IsUndef)
7209 return DAG.getUNDEF(VT);
7211 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
7213 // Vector shuffle lowering takes 3 steps:
7215 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
7216 // narrowing and commutation of operands should be handled.
7217 // 2) Matching of shuffles with known shuffle masks to x86 target specific
7219 // 3) Rewriting of unmatched masks into new generic shuffle operations,
7220 // so the shuffle can be broken into other shuffles and the legalizer can
7221 // try the lowering again.
7223 // The general idea is that no vector_shuffle operation should be left to
7224 // be matched during isel, all of them must be converted to a target specific
7227 // Normalize the input vectors. Here splats, zeroed vectors, profitable
7228 // narrowing and commutation of operands should be handled. The actual code
7229 // doesn't include all of those, work in progress...
7230 SDValue NewOp = NormalizeVectorShuffle(Op, DAG);
7231 if (NewOp.getNode())
7234 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
7236 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
7237 // unpckh_undef). Only use pshufd if speed is more important than size.
7238 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7239 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7240 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7241 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7243 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
7244 V2IsUndef && MayFoldVectorLoad(V1))
7245 return getMOVDDup(Op, dl, V1, DAG);
7247 if (isMOVHLPS_v_undef_Mask(M, VT))
7248 return getMOVHighToLow(Op, dl, DAG);
7250 // Use to match splats
7251 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
7252 (VT == MVT::v2f64 || VT == MVT::v2i64))
7253 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7255 if (isPSHUFDMask(M, VT)) {
7256 // The actual implementation will match the mask in the if above and then
7257 // during isel it can match several different instructions, not only pshufd
7258 // as its name says, sad but true, emulate the behavior for now...
7259 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
7260 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
7262 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
7264 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
7265 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
7267 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
7268 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
7271 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
7275 if (isPALIGNRMask(M, VT, Subtarget))
7276 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
7277 getShufflePALIGNRImmediate(SVOp),
7280 // Check if this can be converted into a logical shift.
7281 bool isLeft = false;
7284 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
7285 if (isShift && ShVal.hasOneUse()) {
7286 // If the shifted value has multiple uses, it may be cheaper to use
7287 // v_set0 + movlhps or movhlps, etc.
7288 MVT EltVT = VT.getVectorElementType();
7289 ShAmt *= EltVT.getSizeInBits();
7290 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7293 if (isMOVLMask(M, VT)) {
7294 if (ISD::isBuildVectorAllZeros(V1.getNode()))
7295 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
7296 if (!isMOVLPMask(M, VT)) {
7297 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
7298 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7300 if (VT == MVT::v4i32 || VT == MVT::v4f32)
7301 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7305 // FIXME: fold these into legal mask.
7306 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
7307 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
7309 if (isMOVHLPSMask(M, VT))
7310 return getMOVHighToLow(Op, dl, DAG);
7312 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
7313 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
7315 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
7316 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
7318 if (isMOVLPMask(M, VT))
7319 return getMOVLP(Op, dl, DAG, HasSSE2);
7321 if (ShouldXformToMOVHLPS(M, VT) ||
7322 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
7323 return CommuteVectorShuffle(SVOp, DAG);
7326 // No better options. Use a vshldq / vsrldq.
7327 MVT EltVT = VT.getVectorElementType();
7328 ShAmt *= EltVT.getSizeInBits();
7329 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7332 bool Commuted = false;
7333 // FIXME: This should also accept a bitcast of a splat? Be careful, not
7334 // 1,1,1,1 -> v8i16 though.
7335 V1IsSplat = isSplatVector(V1.getNode());
7336 V2IsSplat = isSplatVector(V2.getNode());
7338 // Canonicalize the splat or undef, if present, to be on the RHS.
7339 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
7340 CommuteVectorShuffleMask(M, NumElems);
7342 std::swap(V1IsSplat, V2IsSplat);
7346 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
7347 // Shuffling low element of v1 into undef, just return v1.
7350 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
7351 // the instruction selector will not match, so get a canonical MOVL with
7352 // swapped operands to undo the commute.
7353 return getMOVL(DAG, dl, VT, V2, V1);
7356 if (isUNPCKLMask(M, VT, HasInt256))
7357 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7359 if (isUNPCKHMask(M, VT, HasInt256))
7360 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7363 // Normalize mask so all entries that point to V2 points to its first
7364 // element then try to match unpck{h|l} again. If match, return a
7365 // new vector_shuffle with the corrected mask.p
7366 SmallVector<int, 8> NewMask(M.begin(), M.end());
7367 NormalizeMask(NewMask, NumElems);
7368 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
7369 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7370 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
7371 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7375 // Commute is back and try unpck* again.
7376 // FIXME: this seems wrong.
7377 CommuteVectorShuffleMask(M, NumElems);
7379 std::swap(V1IsSplat, V2IsSplat);
7382 if (isUNPCKLMask(M, VT, HasInt256))
7383 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7385 if (isUNPCKHMask(M, VT, HasInt256))
7386 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7389 // Normalize the node to match x86 shuffle ops if needed
7390 if (!V2IsUndef && (isSHUFPMask(M, VT, HasFp256, /* Commuted */ true)))
7391 return CommuteVectorShuffle(SVOp, DAG);
7393 // The checks below are all present in isShuffleMaskLegal, but they are
7394 // inlined here right now to enable us to directly emit target specific
7395 // nodes, and remove one by one until they don't return Op anymore.
7397 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
7398 SVOp->getSplatIndex() == 0 && V2IsUndef) {
7399 if (VT == MVT::v2f64 || VT == MVT::v2i64)
7400 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7403 if (isPSHUFHWMask(M, VT, HasInt256))
7404 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
7405 getShufflePSHUFHWImmediate(SVOp),
7408 if (isPSHUFLWMask(M, VT, HasInt256))
7409 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
7410 getShufflePSHUFLWImmediate(SVOp),
7413 if (isSHUFPMask(M, VT, HasFp256))
7414 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
7415 getShuffleSHUFImmediate(SVOp), DAG);
7417 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7418 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7419 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7420 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7422 //===--------------------------------------------------------------------===//
7423 // Generate target specific nodes for 128 or 256-bit shuffles only
7424 // supported in the AVX instruction set.
7427 // Handle VMOVDDUPY permutations
7428 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
7429 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
7431 // Handle VPERMILPS/D* permutations
7432 if (isVPERMILPMask(M, VT, HasFp256)) {
7433 if (HasInt256 && VT == MVT::v8i32)
7434 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
7435 getShuffleSHUFImmediate(SVOp), DAG);
7436 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
7437 getShuffleSHUFImmediate(SVOp), DAG);
7440 // Handle VPERM2F128/VPERM2I128 permutations
7441 if (isVPERM2X128Mask(M, VT, HasFp256))
7442 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
7443 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
7445 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
7446 if (BlendOp.getNode())
7450 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
7451 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
7453 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
7454 VT.is512BitVector()) {
7455 EVT MaskEltVT = EVT::getIntegerVT(*DAG.getContext(),
7456 VT.getVectorElementType().getSizeInBits());
7458 EVT::getVectorVT(*DAG.getContext(),MaskEltVT, NumElems);
7459 SmallVector<SDValue, 16> permclMask;
7460 for (unsigned i = 0; i != NumElems; ++i) {
7461 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
7464 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT,
7465 &permclMask[0], NumElems);
7467 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
7468 return DAG.getNode(X86ISD::VPERMV, dl, VT,
7469 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
7470 return DAG.getNode(X86ISD::VPERMV3, dl, VT,
7471 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1, V2);
7474 //===--------------------------------------------------------------------===//
7475 // Since no target specific shuffle was selected for this generic one,
7476 // lower it into other known shuffles. FIXME: this isn't true yet, but
7477 // this is the plan.
7480 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
7481 if (VT == MVT::v8i16) {
7482 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
7483 if (NewOp.getNode())
7487 if (VT == MVT::v16i8) {
7488 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
7489 if (NewOp.getNode())
7493 if (VT == MVT::v32i8) {
7494 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
7495 if (NewOp.getNode())
7499 // Handle all 128-bit wide vectors with 4 elements, and match them with
7500 // several different shuffle types.
7501 if (NumElems == 4 && VT.is128BitVector())
7502 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
7504 // Handle general 256-bit shuffles
7505 if (VT.is256BitVector())
7506 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
7511 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7512 MVT VT = Op.getValueType().getSimpleVT();
7515 if (!Op.getOperand(0).getValueType().getSimpleVT().is128BitVector())
7518 if (VT.getSizeInBits() == 8) {
7519 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
7520 Op.getOperand(0), Op.getOperand(1));
7521 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7522 DAG.getValueType(VT));
7523 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7526 if (VT.getSizeInBits() == 16) {
7527 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7528 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
7530 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7531 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7532 DAG.getNode(ISD::BITCAST, dl,
7536 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
7537 Op.getOperand(0), Op.getOperand(1));
7538 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7539 DAG.getValueType(VT));
7540 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7543 if (VT == MVT::f32) {
7544 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
7545 // the result back to FR32 register. It's only worth matching if the
7546 // result has a single use which is a store or a bitcast to i32. And in
7547 // the case of a store, it's not worth it if the index is a constant 0,
7548 // because a MOVSSmr can be used instead, which is smaller and faster.
7549 if (!Op.hasOneUse())
7551 SDNode *User = *Op.getNode()->use_begin();
7552 if ((User->getOpcode() != ISD::STORE ||
7553 (isa<ConstantSDNode>(Op.getOperand(1)) &&
7554 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
7555 (User->getOpcode() != ISD::BITCAST ||
7556 User->getValueType(0) != MVT::i32))
7558 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7559 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
7562 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
7565 if (VT == MVT::i32 || VT == MVT::i64) {
7566 // ExtractPS/pextrq works with constant index.
7567 if (isa<ConstantSDNode>(Op.getOperand(1)))
7574 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7575 SelectionDAG &DAG) const {
7577 if (!isa<ConstantSDNode>(Op.getOperand(1)))
7580 SDValue Vec = Op.getOperand(0);
7581 MVT VecVT = Vec.getValueType().getSimpleVT();
7583 // If this is a 256-bit vector result, first extract the 128-bit vector and
7584 // then extract the element from the 128-bit vector.
7585 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
7586 SDValue Idx = Op.getOperand(1);
7587 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7589 // Get the 128-bit vector.
7590 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
7591 EVT EltVT = VecVT.getVectorElementType();
7593 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
7595 //if (IdxVal >= NumElems/2)
7596 // IdxVal -= NumElems/2;
7597 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
7598 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
7599 DAG.getConstant(IdxVal, MVT::i32));
7602 assert(VecVT.is128BitVector() && "Unexpected vector length");
7604 if (Subtarget->hasSSE41()) {
7605 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
7610 MVT VT = Op.getValueType().getSimpleVT();
7611 // TODO: handle v16i8.
7612 if (VT.getSizeInBits() == 16) {
7613 SDValue Vec = Op.getOperand(0);
7614 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7616 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7617 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7618 DAG.getNode(ISD::BITCAST, dl,
7621 // Transform it so it match pextrw which produces a 32-bit result.
7622 MVT EltVT = MVT::i32;
7623 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
7624 Op.getOperand(0), Op.getOperand(1));
7625 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
7626 DAG.getValueType(VT));
7627 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7630 if (VT.getSizeInBits() == 32) {
7631 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7635 // SHUFPS the element to the lowest double word, then movss.
7636 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
7637 MVT VVT = Op.getOperand(0).getValueType().getSimpleVT();
7638 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7639 DAG.getUNDEF(VVT), Mask);
7640 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7641 DAG.getIntPtrConstant(0));
7644 if (VT.getSizeInBits() == 64) {
7645 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
7646 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
7647 // to match extract_elt for f64.
7648 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7652 // UNPCKHPD the element to the lowest double word, then movsd.
7653 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
7654 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
7655 int Mask[2] = { 1, -1 };
7656 MVT VVT = Op.getOperand(0).getValueType().getSimpleVT();
7657 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7658 DAG.getUNDEF(VVT), Mask);
7659 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7660 DAG.getIntPtrConstant(0));
7666 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7667 MVT VT = Op.getValueType().getSimpleVT();
7668 MVT EltVT = VT.getVectorElementType();
7671 SDValue N0 = Op.getOperand(0);
7672 SDValue N1 = Op.getOperand(1);
7673 SDValue N2 = Op.getOperand(2);
7675 if (!VT.is128BitVector())
7678 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
7679 isa<ConstantSDNode>(N2)) {
7681 if (VT == MVT::v8i16)
7682 Opc = X86ISD::PINSRW;
7683 else if (VT == MVT::v16i8)
7684 Opc = X86ISD::PINSRB;
7686 Opc = X86ISD::PINSRB;
7688 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
7690 if (N1.getValueType() != MVT::i32)
7691 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7692 if (N2.getValueType() != MVT::i32)
7693 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7694 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7697 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
7698 // Bits [7:6] of the constant are the source select. This will always be
7699 // zero here. The DAG Combiner may combine an extract_elt index into these
7700 // bits. For example (insert (extract, 3), 2) could be matched by putting
7701 // the '3' into bits [7:6] of X86ISD::INSERTPS.
7702 // Bits [5:4] of the constant are the destination select. This is the
7703 // value of the incoming immediate.
7704 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
7705 // combine either bitwise AND or insert of float 0.0 to set these bits.
7706 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
7707 // Create this as a scalar to vector..
7708 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7709 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7712 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
7713 // PINSR* works with constant index.
7720 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7721 MVT VT = Op.getValueType().getSimpleVT();
7722 MVT EltVT = VT.getVectorElementType();
7725 SDValue N0 = Op.getOperand(0);
7726 SDValue N1 = Op.getOperand(1);
7727 SDValue N2 = Op.getOperand(2);
7729 // If this is a 256-bit vector result, first extract the 128-bit vector,
7730 // insert the element into the extracted half and then place it back.
7731 if (VT.is256BitVector() || VT.is512BitVector()) {
7732 if (!isa<ConstantSDNode>(N2))
7735 // Get the desired 128-bit vector half.
7736 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7737 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
7739 // Insert the element into the desired half.
7740 unsigned NumEltsIn128 = 128/EltVT.getSizeInBits();
7741 unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128;
7743 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
7744 DAG.getConstant(IdxIn128, MVT::i32));
7746 // Insert the changed part back to the 256-bit vector
7747 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
7750 if (Subtarget->hasSSE41())
7751 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7753 if (EltVT == MVT::i8)
7756 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7757 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7758 // as its second argument.
7759 if (N1.getValueType() != MVT::i32)
7760 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7761 if (N2.getValueType() != MVT::i32)
7762 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7763 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7768 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
7769 LLVMContext *Context = DAG.getContext();
7771 MVT OpVT = Op.getValueType().getSimpleVT();
7773 // If this is a 256-bit vector result, first insert into a 128-bit
7774 // vector and then insert into the 256-bit vector.
7775 if (!OpVT.is128BitVector()) {
7776 // Insert into a 128-bit vector.
7777 unsigned SizeFactor = OpVT.getSizeInBits()/128;
7778 EVT VT128 = EVT::getVectorVT(*Context,
7779 OpVT.getVectorElementType(),
7780 OpVT.getVectorNumElements() / SizeFactor);
7782 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7784 // Insert the 128-bit vector.
7785 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
7788 if (OpVT == MVT::v1i64 &&
7789 Op.getOperand(0).getValueType() == MVT::i64)
7790 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7792 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7793 assert(OpVT.is128BitVector() && "Expected an SSE type!");
7794 return DAG.getNode(ISD::BITCAST, dl, OpVT,
7795 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7798 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7799 // a simple subregister reference or explicit instructions to grab
7800 // upper bits of a vector.
7801 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7802 SelectionDAG &DAG) {
7804 SDValue In = Op.getOperand(0);
7805 SDValue Idx = Op.getOperand(1);
7806 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7807 EVT ResVT = Op.getValueType();
7808 EVT InVT = In.getValueType();
7810 if (Subtarget->hasFp256()) {
7811 if (ResVT.is128BitVector() &&
7812 (InVT.is256BitVector() || InVT.is512BitVector()) &&
7813 isa<ConstantSDNode>(Idx)) {
7814 return Extract128BitVector(In, IdxVal, DAG, dl);
7816 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
7817 isa<ConstantSDNode>(Idx)) {
7818 return Extract256BitVector(In, IdxVal, DAG, dl);
7824 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7825 // simple superregister reference or explicit instructions to insert
7826 // the upper bits of a vector.
7827 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7828 SelectionDAG &DAG) {
7829 if (Subtarget->hasFp256()) {
7830 SDLoc dl(Op.getNode());
7831 SDValue Vec = Op.getNode()->getOperand(0);
7832 SDValue SubVec = Op.getNode()->getOperand(1);
7833 SDValue Idx = Op.getNode()->getOperand(2);
7835 if ((Op.getNode()->getValueType(0).is256BitVector() ||
7836 Op.getNode()->getValueType(0).is512BitVector()) &&
7837 SubVec.getNode()->getValueType(0).is128BitVector() &&
7838 isa<ConstantSDNode>(Idx)) {
7839 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7840 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
7843 if (Op.getNode()->getValueType(0).is512BitVector() &&
7844 SubVec.getNode()->getValueType(0).is256BitVector() &&
7845 isa<ConstantSDNode>(Idx)) {
7846 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7847 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
7853 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7854 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7855 // one of the above mentioned nodes. It has to be wrapped because otherwise
7856 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7857 // be used to form addressing mode. These wrapped nodes will be selected
7860 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7861 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7863 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7865 unsigned char OpFlag = 0;
7866 unsigned WrapperKind = X86ISD::Wrapper;
7867 CodeModel::Model M = getTargetMachine().getCodeModel();
7869 if (Subtarget->isPICStyleRIPRel() &&
7870 (M == CodeModel::Small || M == CodeModel::Kernel))
7871 WrapperKind = X86ISD::WrapperRIP;
7872 else if (Subtarget->isPICStyleGOT())
7873 OpFlag = X86II::MO_GOTOFF;
7874 else if (Subtarget->isPICStyleStubPIC())
7875 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7877 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7879 CP->getOffset(), OpFlag);
7881 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7882 // With PIC, the address is actually $g + Offset.
7884 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7885 DAG.getNode(X86ISD::GlobalBaseReg,
7886 SDLoc(), getPointerTy()),
7893 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7894 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7896 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7898 unsigned char OpFlag = 0;
7899 unsigned WrapperKind = X86ISD::Wrapper;
7900 CodeModel::Model M = getTargetMachine().getCodeModel();
7902 if (Subtarget->isPICStyleRIPRel() &&
7903 (M == CodeModel::Small || M == CodeModel::Kernel))
7904 WrapperKind = X86ISD::WrapperRIP;
7905 else if (Subtarget->isPICStyleGOT())
7906 OpFlag = X86II::MO_GOTOFF;
7907 else if (Subtarget->isPICStyleStubPIC())
7908 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7910 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7913 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7915 // With PIC, the address is actually $g + Offset.
7917 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7918 DAG.getNode(X86ISD::GlobalBaseReg,
7919 SDLoc(), getPointerTy()),
7926 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7927 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7929 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7931 unsigned char OpFlag = 0;
7932 unsigned WrapperKind = X86ISD::Wrapper;
7933 CodeModel::Model M = getTargetMachine().getCodeModel();
7935 if (Subtarget->isPICStyleRIPRel() &&
7936 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7937 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7938 OpFlag = X86II::MO_GOTPCREL;
7939 WrapperKind = X86ISD::WrapperRIP;
7940 } else if (Subtarget->isPICStyleGOT()) {
7941 OpFlag = X86II::MO_GOT;
7942 } else if (Subtarget->isPICStyleStubPIC()) {
7943 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7944 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7945 OpFlag = X86II::MO_DARWIN_NONLAZY;
7948 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7951 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7953 // With PIC, the address is actually $g + Offset.
7954 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7955 !Subtarget->is64Bit()) {
7956 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7957 DAG.getNode(X86ISD::GlobalBaseReg,
7958 SDLoc(), getPointerTy()),
7962 // For symbols that require a load from a stub to get the address, emit the
7964 if (isGlobalStubReference(OpFlag))
7965 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7966 MachinePointerInfo::getGOT(), false, false, false, 0);
7972 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7973 // Create the TargetBlockAddressAddress node.
7974 unsigned char OpFlags =
7975 Subtarget->ClassifyBlockAddressReference();
7976 CodeModel::Model M = getTargetMachine().getCodeModel();
7977 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7978 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
7980 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
7983 if (Subtarget->isPICStyleRIPRel() &&
7984 (M == CodeModel::Small || M == CodeModel::Kernel))
7985 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7987 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7989 // With PIC, the address is actually $g + Offset.
7990 if (isGlobalRelativeToPICBase(OpFlags)) {
7991 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7992 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8000 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
8001 int64_t Offset, SelectionDAG &DAG) const {
8002 // Create the TargetGlobalAddress node, folding in the constant
8003 // offset if it is legal.
8004 unsigned char OpFlags =
8005 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
8006 CodeModel::Model M = getTargetMachine().getCodeModel();
8008 if (OpFlags == X86II::MO_NO_FLAG &&
8009 X86::isOffsetSuitableForCodeModel(Offset, M)) {
8010 // A direct static reference to a global.
8011 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
8014 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
8017 if (Subtarget->isPICStyleRIPRel() &&
8018 (M == CodeModel::Small || M == CodeModel::Kernel))
8019 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8021 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8023 // With PIC, the address is actually $g + Offset.
8024 if (isGlobalRelativeToPICBase(OpFlags)) {
8025 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8026 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8030 // For globals that require a load from a stub to get the address, emit the
8032 if (isGlobalStubReference(OpFlags))
8033 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
8034 MachinePointerInfo::getGOT(), false, false, false, 0);
8036 // If there was a non-zero offset that we didn't fold, create an explicit
8039 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
8040 DAG.getConstant(Offset, getPointerTy()));
8046 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
8047 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
8048 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
8049 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
8053 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
8054 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
8055 unsigned char OperandFlags, bool LocalDynamic = false) {
8056 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8057 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8059 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8060 GA->getValueType(0),
8064 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
8068 SDValue Ops[] = { Chain, TGA, *InFlag };
8069 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8071 SDValue Ops[] = { Chain, TGA };
8072 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8075 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
8076 MFI->setAdjustsStack(true);
8078 SDValue Flag = Chain.getValue(1);
8079 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
8082 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
8084 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8087 SDLoc dl(GA); // ? function entry point might be better
8088 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8089 DAG.getNode(X86ISD::GlobalBaseReg,
8090 SDLoc(), PtrVT), InFlag);
8091 InFlag = Chain.getValue(1);
8093 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
8096 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
8098 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8100 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
8101 X86::RAX, X86II::MO_TLSGD);
8104 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
8110 // Get the start address of the TLS block for this module.
8111 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
8112 .getInfo<X86MachineFunctionInfo>();
8113 MFI->incNumLocalDynamicTLSAccesses();
8117 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
8118 X86II::MO_TLSLD, /*LocalDynamic=*/true);
8121 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8122 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
8123 InFlag = Chain.getValue(1);
8124 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
8125 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
8128 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
8132 unsigned char OperandFlags = X86II::MO_DTPOFF;
8133 unsigned WrapperKind = X86ISD::Wrapper;
8134 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8135 GA->getValueType(0),
8136 GA->getOffset(), OperandFlags);
8137 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8139 // Add x@dtpoff with the base.
8140 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
8143 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
8144 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8145 const EVT PtrVT, TLSModel::Model model,
8146 bool is64Bit, bool isPIC) {
8149 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
8150 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
8151 is64Bit ? 257 : 256));
8153 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
8154 DAG.getIntPtrConstant(0),
8155 MachinePointerInfo(Ptr),
8156 false, false, false, 0);
8158 unsigned char OperandFlags = 0;
8159 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
8161 unsigned WrapperKind = X86ISD::Wrapper;
8162 if (model == TLSModel::LocalExec) {
8163 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
8164 } else if (model == TLSModel::InitialExec) {
8166 OperandFlags = X86II::MO_GOTTPOFF;
8167 WrapperKind = X86ISD::WrapperRIP;
8169 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
8172 llvm_unreachable("Unexpected model");
8175 // emit "addl x@ntpoff,%eax" (local exec)
8176 // or "addl x@indntpoff,%eax" (initial exec)
8177 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
8178 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8179 GA->getValueType(0),
8180 GA->getOffset(), OperandFlags);
8181 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8183 if (model == TLSModel::InitialExec) {
8184 if (isPIC && !is64Bit) {
8185 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
8186 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
8190 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
8191 MachinePointerInfo::getGOT(), false, false, false,
8195 // The address of the thread local variable is the add of the thread
8196 // pointer with the offset of the variable.
8197 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
8201 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
8203 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
8204 const GlobalValue *GV = GA->getGlobal();
8206 if (Subtarget->isTargetELF()) {
8207 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
8210 case TLSModel::GeneralDynamic:
8211 if (Subtarget->is64Bit())
8212 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
8213 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
8214 case TLSModel::LocalDynamic:
8215 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
8216 Subtarget->is64Bit());
8217 case TLSModel::InitialExec:
8218 case TLSModel::LocalExec:
8219 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
8220 Subtarget->is64Bit(),
8221 getTargetMachine().getRelocationModel() == Reloc::PIC_);
8223 llvm_unreachable("Unknown TLS model.");
8226 if (Subtarget->isTargetDarwin()) {
8227 // Darwin only has one model of TLS. Lower to that.
8228 unsigned char OpFlag = 0;
8229 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
8230 X86ISD::WrapperRIP : X86ISD::Wrapper;
8232 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8234 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
8235 !Subtarget->is64Bit();
8237 OpFlag = X86II::MO_TLVP_PIC_BASE;
8239 OpFlag = X86II::MO_TLVP;
8241 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
8242 GA->getValueType(0),
8243 GA->getOffset(), OpFlag);
8244 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8246 // With PIC32, the address is actually $g + Offset.
8248 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8249 DAG.getNode(X86ISD::GlobalBaseReg,
8250 SDLoc(), getPointerTy()),
8253 // Lowering the machine isd will make sure everything is in the right
8255 SDValue Chain = DAG.getEntryNode();
8256 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8257 SDValue Args[] = { Chain, Offset };
8258 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
8260 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
8261 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8262 MFI->setAdjustsStack(true);
8264 // And our return value (tls address) is in the standard call return value
8266 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
8267 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
8271 if (Subtarget->isTargetWindows() || Subtarget->isTargetMingw()) {
8272 // Just use the implicit TLS architecture
8273 // Need to generate someting similar to:
8274 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
8276 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
8277 // mov rcx, qword [rdx+rcx*8]
8278 // mov eax, .tls$:tlsvar
8279 // [rax+rcx] contains the address
8280 // Windows 64bit: gs:0x58
8281 // Windows 32bit: fs:__tls_array
8283 // If GV is an alias then use the aliasee for determining
8284 // thread-localness.
8285 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
8286 GV = GA->resolveAliasedGlobal(false);
8288 SDValue Chain = DAG.getEntryNode();
8290 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
8291 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
8292 // use its literal value of 0x2C.
8293 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
8294 ? Type::getInt8PtrTy(*DAG.getContext(),
8296 : Type::getInt32PtrTy(*DAG.getContext(),
8299 SDValue TlsArray = Subtarget->is64Bit() ? DAG.getIntPtrConstant(0x58) :
8300 (Subtarget->isTargetMingw() ? DAG.getIntPtrConstant(0x2C) :
8301 DAG.getExternalSymbol("_tls_array", getPointerTy()));
8303 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
8304 MachinePointerInfo(Ptr),
8305 false, false, false, 0);
8307 // Load the _tls_index variable
8308 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
8309 if (Subtarget->is64Bit())
8310 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
8311 IDX, MachinePointerInfo(), MVT::i32,
8314 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
8315 false, false, false, 0);
8317 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
8319 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
8321 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
8322 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
8323 false, false, false, 0);
8325 // Get the offset of start of .tls section
8326 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8327 GA->getValueType(0),
8328 GA->getOffset(), X86II::MO_SECREL);
8329 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
8331 // The address of the thread local variable is the add of the thread
8332 // pointer with the offset of the variable.
8333 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
8336 llvm_unreachable("TLS not implemented for this target.");
8339 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
8340 /// and take a 2 x i32 value to shift plus a shift amount.
8341 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
8342 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
8343 EVT VT = Op.getValueType();
8344 unsigned VTBits = VT.getSizeInBits();
8346 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
8347 SDValue ShOpLo = Op.getOperand(0);
8348 SDValue ShOpHi = Op.getOperand(1);
8349 SDValue ShAmt = Op.getOperand(2);
8350 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
8351 DAG.getConstant(VTBits - 1, MVT::i8))
8352 : DAG.getConstant(0, VT);
8355 if (Op.getOpcode() == ISD::SHL_PARTS) {
8356 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
8357 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
8359 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
8360 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
8363 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
8364 DAG.getConstant(VTBits, MVT::i8));
8365 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8366 AndNode, DAG.getConstant(0, MVT::i8));
8369 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8370 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
8371 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
8373 if (Op.getOpcode() == ISD::SHL_PARTS) {
8374 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8375 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8377 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8378 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8381 SDValue Ops[2] = { Lo, Hi };
8382 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
8385 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
8386 SelectionDAG &DAG) const {
8387 EVT SrcVT = Op.getOperand(0).getValueType();
8389 if (SrcVT.isVector())
8392 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
8393 "Unknown SINT_TO_FP to lower!");
8395 // These are really Legal; return the operand so the caller accepts it as
8397 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
8399 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
8400 Subtarget->is64Bit()) {
8405 unsigned Size = SrcVT.getSizeInBits()/8;
8406 MachineFunction &MF = DAG.getMachineFunction();
8407 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
8408 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8409 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8411 MachinePointerInfo::getFixedStack(SSFI),
8413 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
8416 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
8418 SelectionDAG &DAG) const {
8422 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
8424 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
8426 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
8428 unsigned ByteSize = SrcVT.getSizeInBits()/8;
8430 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
8431 MachineMemOperand *MMO;
8433 int SSFI = FI->getIndex();
8435 DAG.getMachineFunction()
8436 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8437 MachineMemOperand::MOLoad, ByteSize, ByteSize);
8439 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
8440 StackSlot = StackSlot.getOperand(1);
8442 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
8443 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
8445 Tys, Ops, array_lengthof(Ops),
8449 Chain = Result.getValue(1);
8450 SDValue InFlag = Result.getValue(2);
8452 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
8453 // shouldn't be necessary except that RFP cannot be live across
8454 // multiple blocks. When stackifier is fixed, they can be uncoupled.
8455 MachineFunction &MF = DAG.getMachineFunction();
8456 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
8457 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
8458 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8459 Tys = DAG.getVTList(MVT::Other);
8461 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
8463 MachineMemOperand *MMO =
8464 DAG.getMachineFunction()
8465 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8466 MachineMemOperand::MOStore, SSFISize, SSFISize);
8468 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
8469 Ops, array_lengthof(Ops),
8470 Op.getValueType(), MMO);
8471 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
8472 MachinePointerInfo::getFixedStack(SSFI),
8473 false, false, false, 0);
8479 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
8480 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
8481 SelectionDAG &DAG) const {
8482 // This algorithm is not obvious. Here it is what we're trying to output:
8485 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
8486 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
8490 pshufd $0x4e, %xmm0, %xmm1
8496 LLVMContext *Context = DAG.getContext();
8498 // Build some magic constants.
8499 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
8500 Constant *C0 = ConstantDataVector::get(*Context, CV0);
8501 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
8503 SmallVector<Constant*,2> CV1;
8505 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8506 APInt(64, 0x4330000000000000ULL))));
8508 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8509 APInt(64, 0x4530000000000000ULL))));
8510 Constant *C1 = ConstantVector::get(CV1);
8511 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
8513 // Load the 64-bit value into an XMM register.
8514 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
8516 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
8517 MachinePointerInfo::getConstantPool(),
8518 false, false, false, 16);
8519 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
8520 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
8523 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
8524 MachinePointerInfo::getConstantPool(),
8525 false, false, false, 16);
8526 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
8527 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
8530 if (Subtarget->hasSSE3()) {
8531 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
8532 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
8534 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
8535 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
8537 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
8538 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
8542 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
8543 DAG.getIntPtrConstant(0));
8546 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
8547 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
8548 SelectionDAG &DAG) const {
8550 // FP constant to bias correct the final result.
8551 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
8554 // Load the 32-bit value into an XMM register.
8555 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
8558 // Zero out the upper parts of the register.
8559 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
8561 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8562 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
8563 DAG.getIntPtrConstant(0));
8565 // Or the load with the bias.
8566 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
8567 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8568 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8570 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8571 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8572 MVT::v2f64, Bias)));
8573 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8574 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
8575 DAG.getIntPtrConstant(0));
8577 // Subtract the bias.
8578 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
8580 // Handle final rounding.
8581 EVT DestVT = Op.getValueType();
8583 if (DestVT.bitsLT(MVT::f64))
8584 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
8585 DAG.getIntPtrConstant(0));
8586 if (DestVT.bitsGT(MVT::f64))
8587 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
8589 // Handle final rounding.
8593 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
8594 SelectionDAG &DAG) const {
8595 SDValue N0 = Op.getOperand(0);
8596 EVT SVT = N0.getValueType();
8599 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
8600 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
8601 "Custom UINT_TO_FP is not supported!");
8603 EVT NVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
8604 SVT.getVectorNumElements());
8605 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
8606 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
8609 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
8610 SelectionDAG &DAG) const {
8611 SDValue N0 = Op.getOperand(0);
8614 if (Op.getValueType().isVector())
8615 return lowerUINT_TO_FP_vec(Op, DAG);
8617 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
8618 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
8619 // the optimization here.
8620 if (DAG.SignBitIsZero(N0))
8621 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
8623 EVT SrcVT = N0.getValueType();
8624 EVT DstVT = Op.getValueType();
8625 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
8626 return LowerUINT_TO_FP_i64(Op, DAG);
8627 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
8628 return LowerUINT_TO_FP_i32(Op, DAG);
8629 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
8632 // Make a 64-bit buffer, and use it to build an FILD.
8633 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
8634 if (SrcVT == MVT::i32) {
8635 SDValue WordOff = DAG.getConstant(4, getPointerTy());
8636 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
8637 getPointerTy(), StackSlot, WordOff);
8638 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8639 StackSlot, MachinePointerInfo(),
8641 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
8642 OffsetSlot, MachinePointerInfo(),
8644 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
8648 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
8649 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8650 StackSlot, MachinePointerInfo(),
8652 // For i64 source, we need to add the appropriate power of 2 if the input
8653 // was negative. This is the same as the optimization in
8654 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
8655 // we must be careful to do the computation in x87 extended precision, not
8656 // in SSE. (The generic code can't know it's OK to do this, or how to.)
8657 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
8658 MachineMemOperand *MMO =
8659 DAG.getMachineFunction()
8660 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8661 MachineMemOperand::MOLoad, 8, 8);
8663 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
8664 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
8665 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
8666 array_lengthof(Ops), MVT::i64, MMO);
8668 APInt FF(32, 0x5F800000ULL);
8670 // Check whether the sign bit is set.
8671 SDValue SignSet = DAG.getSetCC(dl,
8672 getSetCCResultType(*DAG.getContext(), MVT::i64),
8673 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
8676 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
8677 SDValue FudgePtr = DAG.getConstantPool(
8678 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
8681 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
8682 SDValue Zero = DAG.getIntPtrConstant(0);
8683 SDValue Four = DAG.getIntPtrConstant(4);
8684 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
8686 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
8688 // Load the value out, extending it from f32 to f80.
8689 // FIXME: Avoid the extend by constructing the right constant pool?
8690 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
8691 FudgePtr, MachinePointerInfo::getConstantPool(),
8692 MVT::f32, false, false, 4);
8693 // Extend everything to 80 bits to force it to be done on x87.
8694 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
8695 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
8698 std::pair<SDValue,SDValue>
8699 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
8700 bool IsSigned, bool IsReplace) const {
8703 EVT DstTy = Op.getValueType();
8705 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
8706 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
8710 assert(DstTy.getSimpleVT() <= MVT::i64 &&
8711 DstTy.getSimpleVT() >= MVT::i16 &&
8712 "Unknown FP_TO_INT to lower!");
8714 // These are really Legal.
8715 if (DstTy == MVT::i32 &&
8716 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8717 return std::make_pair(SDValue(), SDValue());
8718 if (Subtarget->is64Bit() &&
8719 DstTy == MVT::i64 &&
8720 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8721 return std::make_pair(SDValue(), SDValue());
8723 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
8724 // stack slot, or into the FTOL runtime function.
8725 MachineFunction &MF = DAG.getMachineFunction();
8726 unsigned MemSize = DstTy.getSizeInBits()/8;
8727 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8728 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8731 if (!IsSigned && isIntegerTypeFTOL(DstTy))
8732 Opc = X86ISD::WIN_FTOL;
8734 switch (DstTy.getSimpleVT().SimpleTy) {
8735 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
8736 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
8737 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
8738 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
8741 SDValue Chain = DAG.getEntryNode();
8742 SDValue Value = Op.getOperand(0);
8743 EVT TheVT = Op.getOperand(0).getValueType();
8744 // FIXME This causes a redundant load/store if the SSE-class value is already
8745 // in memory, such as if it is on the callstack.
8746 if (isScalarFPTypeInSSEReg(TheVT)) {
8747 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
8748 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
8749 MachinePointerInfo::getFixedStack(SSFI),
8751 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
8753 Chain, StackSlot, DAG.getValueType(TheVT)
8756 MachineMemOperand *MMO =
8757 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8758 MachineMemOperand::MOLoad, MemSize, MemSize);
8759 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops,
8760 array_lengthof(Ops), DstTy, MMO);
8761 Chain = Value.getValue(1);
8762 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8763 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8766 MachineMemOperand *MMO =
8767 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8768 MachineMemOperand::MOStore, MemSize, MemSize);
8770 if (Opc != X86ISD::WIN_FTOL) {
8771 // Build the FP_TO_INT*_IN_MEM
8772 SDValue Ops[] = { Chain, Value, StackSlot };
8773 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
8774 Ops, array_lengthof(Ops), DstTy,
8776 return std::make_pair(FIST, StackSlot);
8778 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
8779 DAG.getVTList(MVT::Other, MVT::Glue),
8781 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
8782 MVT::i32, ftol.getValue(1));
8783 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
8784 MVT::i32, eax.getValue(2));
8785 SDValue Ops[] = { eax, edx };
8786 SDValue pair = IsReplace
8787 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, array_lengthof(Ops))
8788 : DAG.getMergeValues(Ops, array_lengthof(Ops), DL);
8789 return std::make_pair(pair, SDValue());
8793 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
8794 const X86Subtarget *Subtarget) {
8795 MVT VT = Op->getValueType(0).getSimpleVT();
8796 SDValue In = Op->getOperand(0);
8797 MVT InVT = In.getValueType().getSimpleVT();
8800 // Optimize vectors in AVX mode:
8803 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
8804 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
8805 // Concat upper and lower parts.
8808 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
8809 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
8810 // Concat upper and lower parts.
8813 if (((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
8814 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
8817 if (Subtarget->hasInt256())
8818 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, In);
8820 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
8821 SDValue Undef = DAG.getUNDEF(InVT);
8822 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
8823 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8824 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8826 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
8827 VT.getVectorNumElements()/2);
8829 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
8830 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
8832 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
8835 SDValue X86TargetLowering::LowerANY_EXTEND(SDValue Op,
8836 SelectionDAG &DAG) const {
8837 if (Subtarget->hasFp256()) {
8838 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8845 SDValue X86TargetLowering::LowerZERO_EXTEND(SDValue Op,
8846 SelectionDAG &DAG) const {
8848 MVT VT = Op.getValueType().getSimpleVT();
8849 SDValue In = Op.getOperand(0);
8850 MVT SVT = In.getValueType().getSimpleVT();
8852 if (Subtarget->hasFp256()) {
8853 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8858 if (!VT.is256BitVector() || !SVT.is128BitVector() ||
8859 VT.getVectorNumElements() != SVT.getVectorNumElements())
8862 assert(Subtarget->hasFp256() && "256-bit vector is observed without AVX!");
8864 // AVX2 has better support of integer extending.
8865 if (Subtarget->hasInt256())
8866 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
8868 SDValue Lo = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32, In);
8869 static const int Mask[] = {4, 5, 6, 7, -1, -1, -1, -1};
8870 SDValue Hi = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32,
8871 DAG.getVectorShuffle(MVT::v8i16, DL, In,
8872 DAG.getUNDEF(MVT::v8i16),
8875 return DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i32, Lo, Hi);
8878 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
8880 MVT VT = Op.getValueType().getSimpleVT();
8881 SDValue In = Op.getOperand(0);
8882 MVT SVT = In.getValueType().getSimpleVT();
8884 if ((VT == MVT::v4i32) && (SVT == MVT::v4i64)) {
8885 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
8886 if (Subtarget->hasInt256()) {
8887 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
8888 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
8889 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
8891 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
8892 DAG.getIntPtrConstant(0));
8895 // On AVX, v4i64 -> v4i32 becomes a sequence that uses PSHUFD and MOVLHPS.
8896 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
8897 DAG.getIntPtrConstant(0));
8898 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
8899 DAG.getIntPtrConstant(2));
8901 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
8902 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
8905 static const int ShufMask1[] = {0, 2, 0, 0};
8906 SDValue Undef = DAG.getUNDEF(VT);
8907 OpLo = DAG.getVectorShuffle(VT, DL, OpLo, Undef, ShufMask1);
8908 OpHi = DAG.getVectorShuffle(VT, DL, OpHi, Undef, ShufMask1);
8910 // The MOVLHPS mask:
8911 static const int ShufMask2[] = {0, 1, 4, 5};
8912 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask2);
8915 if ((VT == MVT::v8i16) && (SVT == MVT::v8i32)) {
8916 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
8917 if (Subtarget->hasInt256()) {
8918 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
8920 SmallVector<SDValue,32> pshufbMask;
8921 for (unsigned i = 0; i < 2; ++i) {
8922 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
8923 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
8924 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
8925 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
8926 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
8927 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
8928 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
8929 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
8930 for (unsigned j = 0; j < 8; ++j)
8931 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
8933 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8,
8934 &pshufbMask[0], 32);
8935 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
8936 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
8938 static const int ShufMask[] = {0, 2, -1, -1};
8939 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
8941 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
8942 DAG.getIntPtrConstant(0));
8943 return DAG.getNode(ISD::BITCAST, DL, VT, In);
8946 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
8947 DAG.getIntPtrConstant(0));
8949 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
8950 DAG.getIntPtrConstant(4));
8952 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
8953 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
8956 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
8957 -1, -1, -1, -1, -1, -1, -1, -1};
8959 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
8960 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
8961 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
8963 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
8964 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
8966 // The MOVLHPS Mask:
8967 static const int ShufMask2[] = {0, 1, 4, 5};
8968 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
8969 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
8972 // Handle truncation of V256 to V128 using shuffles.
8973 if (!VT.is128BitVector() || !SVT.is256BitVector())
8976 assert(VT.getVectorNumElements() != SVT.getVectorNumElements() &&
8978 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
8980 unsigned NumElems = VT.getVectorNumElements();
8981 EVT NVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
8984 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
8985 // Prepare truncation shuffle mask
8986 for (unsigned i = 0; i != NumElems; ++i)
8988 SDValue V = DAG.getVectorShuffle(NVT, DL,
8989 DAG.getNode(ISD::BITCAST, DL, NVT, In),
8990 DAG.getUNDEF(NVT), &MaskVec[0]);
8991 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
8992 DAG.getIntPtrConstant(0));
8995 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
8996 SelectionDAG &DAG) const {
8997 MVT VT = Op.getValueType().getSimpleVT();
8998 if (VT.isVector()) {
8999 if (VT == MVT::v8i16)
9000 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT,
9001 DAG.getNode(ISD::FP_TO_SINT, SDLoc(Op),
9002 MVT::v8i32, Op.getOperand(0)));
9006 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9007 /*IsSigned=*/ true, /*IsReplace=*/ false);
9008 SDValue FIST = Vals.first, StackSlot = Vals.second;
9009 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
9010 if (FIST.getNode() == 0) return Op;
9012 if (StackSlot.getNode())
9014 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9015 FIST, StackSlot, MachinePointerInfo(),
9016 false, false, false, 0);
9018 // The node is the result.
9022 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
9023 SelectionDAG &DAG) const {
9024 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9025 /*IsSigned=*/ false, /*IsReplace=*/ false);
9026 SDValue FIST = Vals.first, StackSlot = Vals.second;
9027 assert(FIST.getNode() && "Unexpected failure");
9029 if (StackSlot.getNode())
9031 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9032 FIST, StackSlot, MachinePointerInfo(),
9033 false, false, false, 0);
9035 // The node is the result.
9039 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
9041 MVT VT = Op.getValueType().getSimpleVT();
9042 SDValue In = Op.getOperand(0);
9043 MVT SVT = In.getValueType().getSimpleVT();
9045 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
9047 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
9048 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
9049 In, DAG.getUNDEF(SVT)));
9052 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
9053 LLVMContext *Context = DAG.getContext();
9055 MVT VT = Op.getValueType().getSimpleVT();
9057 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9058 if (VT.isVector()) {
9059 EltVT = VT.getVectorElementType();
9060 NumElts = VT.getVectorNumElements();
9063 if (EltVT == MVT::f64)
9064 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9065 APInt(64, ~(1ULL << 63))));
9067 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9068 APInt(32, ~(1U << 31))));
9069 C = ConstantVector::getSplat(NumElts, C);
9070 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
9071 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9072 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9073 MachinePointerInfo::getConstantPool(),
9074 false, false, false, Alignment);
9075 if (VT.isVector()) {
9076 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9077 return DAG.getNode(ISD::BITCAST, dl, VT,
9078 DAG.getNode(ISD::AND, dl, ANDVT,
9079 DAG.getNode(ISD::BITCAST, dl, ANDVT,
9081 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
9083 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
9086 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
9087 LLVMContext *Context = DAG.getContext();
9089 MVT VT = Op.getValueType().getSimpleVT();
9091 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9092 if (VT.isVector()) {
9093 EltVT = VT.getVectorElementType();
9094 NumElts = VT.getVectorNumElements();
9097 if (EltVT == MVT::f64)
9098 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9099 APInt(64, 1ULL << 63)));
9101 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9102 APInt(32, 1U << 31)));
9103 C = ConstantVector::getSplat(NumElts, C);
9104 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
9105 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9106 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9107 MachinePointerInfo::getConstantPool(),
9108 false, false, false, Alignment);
9109 if (VT.isVector()) {
9110 MVT XORVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9111 return DAG.getNode(ISD::BITCAST, dl, VT,
9112 DAG.getNode(ISD::XOR, dl, XORVT,
9113 DAG.getNode(ISD::BITCAST, dl, XORVT,
9115 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
9118 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
9121 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
9122 LLVMContext *Context = DAG.getContext();
9123 SDValue Op0 = Op.getOperand(0);
9124 SDValue Op1 = Op.getOperand(1);
9126 MVT VT = Op.getValueType().getSimpleVT();
9127 MVT SrcVT = Op1.getValueType().getSimpleVT();
9129 // If second operand is smaller, extend it first.
9130 if (SrcVT.bitsLT(VT)) {
9131 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
9134 // And if it is bigger, shrink it first.
9135 if (SrcVT.bitsGT(VT)) {
9136 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
9140 // At this point the operands and the result should have the same
9141 // type, and that won't be f80 since that is not custom lowered.
9143 // First get the sign bit of second operand.
9144 SmallVector<Constant*,4> CV;
9145 if (SrcVT == MVT::f64) {
9146 const fltSemantics &Sem = APFloat::IEEEdouble;
9147 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
9148 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9150 const fltSemantics &Sem = APFloat::IEEEsingle;
9151 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
9152 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9153 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9154 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9156 Constant *C = ConstantVector::get(CV);
9157 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9158 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
9159 MachinePointerInfo::getConstantPool(),
9160 false, false, false, 16);
9161 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
9163 // Shift sign bit right or left if the two operands have different types.
9164 if (SrcVT.bitsGT(VT)) {
9165 // Op0 is MVT::f32, Op1 is MVT::f64.
9166 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
9167 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
9168 DAG.getConstant(32, MVT::i32));
9169 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
9170 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
9171 DAG.getIntPtrConstant(0));
9174 // Clear first operand sign bit.
9176 if (VT == MVT::f64) {
9177 const fltSemantics &Sem = APFloat::IEEEdouble;
9178 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9179 APInt(64, ~(1ULL << 63)))));
9180 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9182 const fltSemantics &Sem = APFloat::IEEEsingle;
9183 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9184 APInt(32, ~(1U << 31)))));
9185 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9186 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9187 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9189 C = ConstantVector::get(CV);
9190 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9191 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9192 MachinePointerInfo::getConstantPool(),
9193 false, false, false, 16);
9194 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
9196 // Or the value with the sign bit.
9197 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
9200 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
9201 SDValue N0 = Op.getOperand(0);
9203 MVT VT = Op.getValueType().getSimpleVT();
9205 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
9206 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
9207 DAG.getConstant(1, VT));
9208 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
9211 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
9213 SDValue X86TargetLowering::LowerVectorAllZeroTest(SDValue Op,
9214 SelectionDAG &DAG) const {
9215 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
9217 if (!Subtarget->hasSSE41())
9220 if (!Op->hasOneUse())
9223 SDNode *N = Op.getNode();
9226 SmallVector<SDValue, 8> Opnds;
9227 DenseMap<SDValue, unsigned> VecInMap;
9228 EVT VT = MVT::Other;
9230 // Recognize a special case where a vector is casted into wide integer to
9232 Opnds.push_back(N->getOperand(0));
9233 Opnds.push_back(N->getOperand(1));
9235 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
9236 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
9237 // BFS traverse all OR'd operands.
9238 if (I->getOpcode() == ISD::OR) {
9239 Opnds.push_back(I->getOperand(0));
9240 Opnds.push_back(I->getOperand(1));
9241 // Re-evaluate the number of nodes to be traversed.
9242 e += 2; // 2 more nodes (LHS and RHS) are pushed.
9246 // Quit if a non-EXTRACT_VECTOR_ELT
9247 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9250 // Quit if without a constant index.
9251 SDValue Idx = I->getOperand(1);
9252 if (!isa<ConstantSDNode>(Idx))
9255 SDValue ExtractedFromVec = I->getOperand(0);
9256 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
9257 if (M == VecInMap.end()) {
9258 VT = ExtractedFromVec.getValueType();
9259 // Quit if not 128/256-bit vector.
9260 if (!VT.is128BitVector() && !VT.is256BitVector())
9262 // Quit if not the same type.
9263 if (VecInMap.begin() != VecInMap.end() &&
9264 VT != VecInMap.begin()->first.getValueType())
9266 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
9268 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
9271 assert((VT.is128BitVector() || VT.is256BitVector()) &&
9272 "Not extracted from 128-/256-bit vector.");
9274 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
9275 SmallVector<SDValue, 8> VecIns;
9277 for (DenseMap<SDValue, unsigned>::const_iterator
9278 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
9279 // Quit if not all elements are used.
9280 if (I->second != FullMask)
9282 VecIns.push_back(I->first);
9285 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9287 // Cast all vectors into TestVT for PTEST.
9288 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
9289 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
9291 // If more than one full vectors are evaluated, OR them first before PTEST.
9292 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
9293 // Each iteration will OR 2 nodes and append the result until there is only
9294 // 1 node left, i.e. the final OR'd value of all vectors.
9295 SDValue LHS = VecIns[Slot];
9296 SDValue RHS = VecIns[Slot + 1];
9297 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
9300 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
9301 VecIns.back(), VecIns.back());
9304 /// Emit nodes that will be selected as "test Op0,Op0", or something
9306 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
9307 SelectionDAG &DAG) const {
9310 // CF and OF aren't always set the way we want. Determine which
9311 // of these we need.
9312 bool NeedCF = false;
9313 bool NeedOF = false;
9316 case X86::COND_A: case X86::COND_AE:
9317 case X86::COND_B: case X86::COND_BE:
9320 case X86::COND_G: case X86::COND_GE:
9321 case X86::COND_L: case X86::COND_LE:
9322 case X86::COND_O: case X86::COND_NO:
9327 // See if we can use the EFLAGS value from the operand instead of
9328 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
9329 // we prove that the arithmetic won't overflow, we can't use OF or CF.
9330 if (Op.getResNo() != 0 || NeedOF || NeedCF)
9331 // Emit a CMP with 0, which is the TEST pattern.
9332 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9333 DAG.getConstant(0, Op.getValueType()));
9335 unsigned Opcode = 0;
9336 unsigned NumOperands = 0;
9338 // Truncate operations may prevent the merge of the SETCC instruction
9339 // and the arithmetic intruction before it. Attempt to truncate the operands
9340 // of the arithmetic instruction and use a reduced bit-width instruction.
9341 bool NeedTruncation = false;
9342 SDValue ArithOp = Op;
9343 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
9344 SDValue Arith = Op->getOperand(0);
9345 // Both the trunc and the arithmetic op need to have one user each.
9346 if (Arith->hasOneUse())
9347 switch (Arith.getOpcode()) {
9354 NeedTruncation = true;
9360 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
9361 // which may be the result of a CAST. We use the variable 'Op', which is the
9362 // non-casted variable when we check for possible users.
9363 switch (ArithOp.getOpcode()) {
9365 // Due to an isel shortcoming, be conservative if this add is likely to be
9366 // selected as part of a load-modify-store instruction. When the root node
9367 // in a match is a store, isel doesn't know how to remap non-chain non-flag
9368 // uses of other nodes in the match, such as the ADD in this case. This
9369 // leads to the ADD being left around and reselected, with the result being
9370 // two adds in the output. Alas, even if none our users are stores, that
9371 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
9372 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
9373 // climbing the DAG back to the root, and it doesn't seem to be worth the
9375 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9376 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9377 if (UI->getOpcode() != ISD::CopyToReg &&
9378 UI->getOpcode() != ISD::SETCC &&
9379 UI->getOpcode() != ISD::STORE)
9382 if (ConstantSDNode *C =
9383 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
9384 // An add of one will be selected as an INC.
9385 if (C->getAPIntValue() == 1) {
9386 Opcode = X86ISD::INC;
9391 // An add of negative one (subtract of one) will be selected as a DEC.
9392 if (C->getAPIntValue().isAllOnesValue()) {
9393 Opcode = X86ISD::DEC;
9399 // Otherwise use a regular EFLAGS-setting add.
9400 Opcode = X86ISD::ADD;
9404 // If the primary and result isn't used, don't bother using X86ISD::AND,
9405 // because a TEST instruction will be better.
9406 bool NonFlagUse = false;
9407 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9408 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
9410 unsigned UOpNo = UI.getOperandNo();
9411 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
9412 // Look pass truncate.
9413 UOpNo = User->use_begin().getOperandNo();
9414 User = *User->use_begin();
9417 if (User->getOpcode() != ISD::BRCOND &&
9418 User->getOpcode() != ISD::SETCC &&
9419 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) {
9432 // Due to the ISEL shortcoming noted above, be conservative if this op is
9433 // likely to be selected as part of a load-modify-store instruction.
9434 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9435 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9436 if (UI->getOpcode() == ISD::STORE)
9439 // Otherwise use a regular EFLAGS-setting instruction.
9440 switch (ArithOp.getOpcode()) {
9441 default: llvm_unreachable("unexpected operator!");
9442 case ISD::SUB: Opcode = X86ISD::SUB; break;
9443 case ISD::XOR: Opcode = X86ISD::XOR; break;
9444 case ISD::AND: Opcode = X86ISD::AND; break;
9446 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
9447 SDValue EFLAGS = LowerVectorAllZeroTest(Op, DAG);
9448 if (EFLAGS.getNode())
9451 Opcode = X86ISD::OR;
9465 return SDValue(Op.getNode(), 1);
9471 // If we found that truncation is beneficial, perform the truncation and
9473 if (NeedTruncation) {
9474 EVT VT = Op.getValueType();
9475 SDValue WideVal = Op->getOperand(0);
9476 EVT WideVT = WideVal.getValueType();
9477 unsigned ConvertedOp = 0;
9478 // Use a target machine opcode to prevent further DAGCombine
9479 // optimizations that may separate the arithmetic operations
9480 // from the setcc node.
9481 switch (WideVal.getOpcode()) {
9483 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
9484 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
9485 case ISD::AND: ConvertedOp = X86ISD::AND; break;
9486 case ISD::OR: ConvertedOp = X86ISD::OR; break;
9487 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
9491 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9492 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
9493 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
9494 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
9495 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
9501 // Emit a CMP with 0, which is the TEST pattern.
9502 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9503 DAG.getConstant(0, Op.getValueType()));
9505 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
9506 SmallVector<SDValue, 4> Ops;
9507 for (unsigned i = 0; i != NumOperands; ++i)
9508 Ops.push_back(Op.getOperand(i));
9510 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
9511 DAG.ReplaceAllUsesWith(Op, New);
9512 return SDValue(New.getNode(), 1);
9515 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
9517 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
9518 SelectionDAG &DAG) const {
9519 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
9520 if (C->getAPIntValue() == 0)
9521 return EmitTest(Op0, X86CC, DAG);
9524 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
9525 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
9526 // Use SUB instead of CMP to enable CSE between SUB and CMP.
9527 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
9528 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
9530 return SDValue(Sub.getNode(), 1);
9532 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
9535 /// Convert a comparison if required by the subtarget.
9536 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
9537 SelectionDAG &DAG) const {
9538 // If the subtarget does not support the FUCOMI instruction, floating-point
9539 // comparisons have to be converted.
9540 if (Subtarget->hasCMov() ||
9541 Cmp.getOpcode() != X86ISD::CMP ||
9542 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
9543 !Cmp.getOperand(1).getValueType().isFloatingPoint())
9546 // The instruction selector will select an FUCOM instruction instead of
9547 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
9548 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
9549 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
9551 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
9552 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
9553 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
9554 DAG.getConstant(8, MVT::i8));
9555 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
9556 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
9559 static bool isAllOnes(SDValue V) {
9560 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
9561 return C && C->isAllOnesValue();
9564 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
9565 /// if it's possible.
9566 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
9567 SDLoc dl, SelectionDAG &DAG) const {
9568 SDValue Op0 = And.getOperand(0);
9569 SDValue Op1 = And.getOperand(1);
9570 if (Op0.getOpcode() == ISD::TRUNCATE)
9571 Op0 = Op0.getOperand(0);
9572 if (Op1.getOpcode() == ISD::TRUNCATE)
9573 Op1 = Op1.getOperand(0);
9576 if (Op1.getOpcode() == ISD::SHL)
9577 std::swap(Op0, Op1);
9578 if (Op0.getOpcode() == ISD::SHL) {
9579 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
9580 if (And00C->getZExtValue() == 1) {
9581 // If we looked past a truncate, check that it's only truncating away
9583 unsigned BitWidth = Op0.getValueSizeInBits();
9584 unsigned AndBitWidth = And.getValueSizeInBits();
9585 if (BitWidth > AndBitWidth) {
9587 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
9588 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
9592 RHS = Op0.getOperand(1);
9594 } else if (Op1.getOpcode() == ISD::Constant) {
9595 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
9596 uint64_t AndRHSVal = AndRHS->getZExtValue();
9597 SDValue AndLHS = Op0;
9599 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
9600 LHS = AndLHS.getOperand(0);
9601 RHS = AndLHS.getOperand(1);
9604 // Use BT if the immediate can't be encoded in a TEST instruction.
9605 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
9607 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
9611 if (LHS.getNode()) {
9612 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
9613 // instruction. Since the shift amount is in-range-or-undefined, we know
9614 // that doing a bittest on the i32 value is ok. We extend to i32 because
9615 // the encoding for the i16 version is larger than the i32 version.
9616 // Also promote i16 to i32 for performance / code size reason.
9617 if (LHS.getValueType() == MVT::i8 ||
9618 LHS.getValueType() == MVT::i16)
9619 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
9621 // If the operand types disagree, extend the shift amount to match. Since
9622 // BT ignores high bits (like shifts) we can use anyextend.
9623 if (LHS.getValueType() != RHS.getValueType())
9624 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
9626 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
9627 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
9628 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9629 DAG.getConstant(Cond, MVT::i8), BT);
9635 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
9637 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
9642 // SSE Condition code mapping:
9651 switch (SetCCOpcode) {
9652 default: llvm_unreachable("Unexpected SETCC condition");
9654 case ISD::SETEQ: SSECC = 0; break;
9656 case ISD::SETGT: Swap = true; // Fallthrough
9658 case ISD::SETOLT: SSECC = 1; break;
9660 case ISD::SETGE: Swap = true; // Fallthrough
9662 case ISD::SETOLE: SSECC = 2; break;
9663 case ISD::SETUO: SSECC = 3; break;
9665 case ISD::SETNE: SSECC = 4; break;
9666 case ISD::SETULE: Swap = true; // Fallthrough
9667 case ISD::SETUGE: SSECC = 5; break;
9668 case ISD::SETULT: Swap = true; // Fallthrough
9669 case ISD::SETUGT: SSECC = 6; break;
9670 case ISD::SETO: SSECC = 7; break;
9672 case ISD::SETONE: SSECC = 8; break;
9675 std::swap(Op0, Op1);
9680 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
9681 // ones, and then concatenate the result back.
9682 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
9683 MVT VT = Op.getValueType().getSimpleVT();
9685 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
9686 "Unsupported value type for operation");
9688 unsigned NumElems = VT.getVectorNumElements();
9690 SDValue CC = Op.getOperand(2);
9692 // Extract the LHS vectors
9693 SDValue LHS = Op.getOperand(0);
9694 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
9695 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
9697 // Extract the RHS vectors
9698 SDValue RHS = Op.getOperand(1);
9699 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
9700 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
9702 // Issue the operation on the smaller types and concatenate the result back
9703 MVT EltVT = VT.getVectorElementType();
9704 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9705 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9706 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
9707 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
9710 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
9712 SDValue Op0 = Op.getOperand(0);
9713 SDValue Op1 = Op.getOperand(1);
9714 SDValue CC = Op.getOperand(2);
9715 MVT VT = Op.getValueType().getSimpleVT();
9717 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 32 &&
9718 Op.getValueType().getScalarType() == MVT::i1 &&
9719 "Cannot set masked compare for this operation");
9721 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9724 bool Unsigned = false;
9726 switch (SetCCOpcode) {
9727 default: llvm_unreachable("Unexpected SETCC condition");
9728 case ISD::SETNE: SSECC = 4; break;
9729 case ISD::SETEQ: SSECC = 0; break;
9730 case ISD::SETUGT: Unsigned = true;
9731 case ISD::SETGT: SSECC = 6; break; // NLE
9732 case ISD::SETULT: Unsigned = true;
9733 case ISD::SETLT: SSECC = 1; break;
9734 case ISD::SETUGE: Unsigned = true;
9735 case ISD::SETGE: SSECC = 5; break; // NLT
9736 case ISD::SETULE: Unsigned = true;
9737 case ISD::SETLE: SSECC = 2; break;
9739 unsigned Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
9740 return DAG.getNode(Opc, dl, VT, Op0, Op1,
9741 DAG.getConstant(SSECC, MVT::i8));
9745 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
9746 SelectionDAG &DAG) {
9748 SDValue Op0 = Op.getOperand(0);
9749 SDValue Op1 = Op.getOperand(1);
9750 SDValue CC = Op.getOperand(2);
9751 MVT VT = Op.getValueType().getSimpleVT();
9752 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9753 bool isFP = Op.getOperand(1).getValueType().getSimpleVT().isFloatingPoint();
9758 MVT EltVT = Op0.getValueType().getVectorElementType().getSimpleVT();
9759 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
9762 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
9763 unsigned Opc = X86ISD::CMPP;
9764 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
9765 assert(VT.getVectorNumElements() <= 16);
9768 // In the two special cases we can't handle, emit two comparisons.
9771 unsigned CombineOpc;
9772 if (SetCCOpcode == ISD::SETUEQ) {
9773 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
9775 assert(SetCCOpcode == ISD::SETONE);
9776 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
9779 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
9780 DAG.getConstant(CC0, MVT::i8));
9781 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
9782 DAG.getConstant(CC1, MVT::i8));
9783 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
9785 // Handle all other FP comparisons here.
9786 return DAG.getNode(Opc, dl, VT, Op0, Op1,
9787 DAG.getConstant(SSECC, MVT::i8));
9790 // Break 256-bit integer vector compare into smaller ones.
9791 if (VT.is256BitVector() && !Subtarget->hasInt256())
9792 return Lower256IntVSETCC(Op, DAG);
9794 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
9795 EVT OpVT = Op1.getValueType();
9796 if (Subtarget->hasAVX512()) {
9797 if (Op1.getValueType().is512BitVector() ||
9798 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
9799 return LowerIntVSETCC_AVX512(Op, DAG);
9801 // In AVX-512 architecture setcc returns mask with i1 elements,
9802 // But there is no compare instruction for i8 and i16 elements.
9803 // We are not talking about 512-bit operands in this case, these
9804 // types are illegal.
9806 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
9807 OpVT.getVectorElementType().getSizeInBits() >= 8))
9808 return DAG.getNode(ISD::TRUNCATE, dl, VT,
9809 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
9812 // We are handling one of the integer comparisons here. Since SSE only has
9813 // GT and EQ comparisons for integer, swapping operands and multiple
9814 // operations may be required for some comparisons.
9816 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
9818 switch (SetCCOpcode) {
9819 default: llvm_unreachable("Unexpected SETCC condition");
9820 case ISD::SETNE: Invert = true;
9821 case ISD::SETEQ: Opc = MaskResult? X86ISD::PCMPEQM: X86ISD::PCMPEQ; break;
9822 case ISD::SETLT: Swap = true;
9823 case ISD::SETGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT; break;
9824 case ISD::SETGE: Swap = true;
9825 case ISD::SETLE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
9826 Invert = true; break;
9827 case ISD::SETULT: Swap = true;
9828 case ISD::SETUGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
9829 FlipSigns = true; break;
9830 case ISD::SETUGE: Swap = true;
9831 case ISD::SETULE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
9832 FlipSigns = true; Invert = true; break;
9835 // Special case: Use min/max operations for SETULE/SETUGE
9836 MVT VET = VT.getVectorElementType();
9838 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
9839 || (Subtarget->hasSSE2() && (VET == MVT::i8));
9842 switch (SetCCOpcode) {
9844 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
9845 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
9848 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
9852 std::swap(Op0, Op1);
9854 // Check that the operation in question is available (most are plain SSE2,
9855 // but PCMPGTQ and PCMPEQQ have different requirements).
9856 if (VT == MVT::v2i64) {
9857 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
9858 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
9860 // First cast everything to the right type.
9861 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
9862 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
9864 // Since SSE has no unsigned integer comparisons, we need to flip the sign
9865 // bits of the inputs before performing those operations. The lower
9866 // compare is always unsigned.
9869 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
9871 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
9872 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
9873 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
9874 Sign, Zero, Sign, Zero);
9876 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
9877 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
9879 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
9880 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
9881 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
9883 // Create masks for only the low parts/high parts of the 64 bit integers.
9884 static const int MaskHi[] = { 1, 1, 3, 3 };
9885 static const int MaskLo[] = { 0, 0, 2, 2 };
9886 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
9887 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
9888 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
9890 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
9891 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
9894 Result = DAG.getNOT(dl, Result, MVT::v4i32);
9896 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
9899 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
9900 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
9901 // pcmpeqd + pshufd + pand.
9902 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
9904 // First cast everything to the right type.
9905 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
9906 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
9909 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
9911 // Make sure the lower and upper halves are both all-ones.
9912 static const int Mask[] = { 1, 0, 3, 2 };
9913 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
9914 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
9917 Result = DAG.getNOT(dl, Result, MVT::v4i32);
9919 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
9923 // Since SSE has no unsigned integer comparisons, we need to flip the sign
9924 // bits of the inputs before performing those operations.
9926 EVT EltVT = VT.getVectorElementType();
9927 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
9928 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
9929 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
9932 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
9934 // If the logical-not of the result is required, perform that now.
9936 Result = DAG.getNOT(dl, Result, VT);
9939 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
9944 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
9946 MVT VT = Op.getValueType().getSimpleVT();
9948 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
9950 assert(VT == MVT::i8 && "SetCC type must be 8-bit integer");
9951 SDValue Op0 = Op.getOperand(0);
9952 SDValue Op1 = Op.getOperand(1);
9954 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
9956 // Optimize to BT if possible.
9957 // Lower (X & (1 << N)) == 0 to BT(X, N).
9958 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
9959 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
9960 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
9961 Op1.getOpcode() == ISD::Constant &&
9962 cast<ConstantSDNode>(Op1)->isNullValue() &&
9963 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
9964 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
9965 if (NewSetCC.getNode())
9969 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
9971 if (Op1.getOpcode() == ISD::Constant &&
9972 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
9973 cast<ConstantSDNode>(Op1)->isNullValue()) &&
9974 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
9976 // If the input is a setcc, then reuse the input setcc or use a new one with
9977 // the inverted condition.
9978 if (Op0.getOpcode() == X86ISD::SETCC) {
9979 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
9980 bool Invert = (CC == ISD::SETNE) ^
9981 cast<ConstantSDNode>(Op1)->isNullValue();
9982 if (!Invert) return Op0;
9984 CCode = X86::GetOppositeBranchCondition(CCode);
9985 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9986 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
9990 bool isFP = Op1.getValueType().getSimpleVT().isFloatingPoint();
9991 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
9992 if (X86CC == X86::COND_INVALID)
9995 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
9996 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
9997 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9998 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
10001 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
10002 static bool isX86LogicalCmp(SDValue Op) {
10003 unsigned Opc = Op.getNode()->getOpcode();
10004 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
10005 Opc == X86ISD::SAHF)
10007 if (Op.getResNo() == 1 &&
10008 (Opc == X86ISD::ADD ||
10009 Opc == X86ISD::SUB ||
10010 Opc == X86ISD::ADC ||
10011 Opc == X86ISD::SBB ||
10012 Opc == X86ISD::SMUL ||
10013 Opc == X86ISD::UMUL ||
10014 Opc == X86ISD::INC ||
10015 Opc == X86ISD::DEC ||
10016 Opc == X86ISD::OR ||
10017 Opc == X86ISD::XOR ||
10018 Opc == X86ISD::AND))
10021 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
10027 static bool isZero(SDValue V) {
10028 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
10029 return C && C->isNullValue();
10032 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
10033 if (V.getOpcode() != ISD::TRUNCATE)
10036 SDValue VOp0 = V.getOperand(0);
10037 unsigned InBits = VOp0.getValueSizeInBits();
10038 unsigned Bits = V.getValueSizeInBits();
10039 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
10042 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
10043 bool addTest = true;
10044 SDValue Cond = Op.getOperand(0);
10045 SDValue Op1 = Op.getOperand(1);
10046 SDValue Op2 = Op.getOperand(2);
10048 EVT VT = Op1.getValueType();
10051 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
10052 // are available. Otherwise fp cmovs get lowered into a less efficient branch
10053 // sequence later on.
10054 if (Cond.getOpcode() == ISD::SETCC &&
10055 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
10056 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
10057 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
10058 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
10059 int SSECC = translateX86FSETCC(
10060 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
10063 unsigned Opcode = VT == MVT::f32 ? X86ISD::FSETCCss : X86ISD::FSETCCsd;
10064 SDValue Cmp = DAG.getNode(Opcode, DL, VT, CondOp0, CondOp1,
10065 DAG.getConstant(SSECC, MVT::i8));
10066 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
10067 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
10068 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
10072 if (Cond.getOpcode() == ISD::SETCC) {
10073 SDValue NewCond = LowerSETCC(Cond, DAG);
10074 if (NewCond.getNode())
10078 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
10079 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
10080 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
10081 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
10082 if (Cond.getOpcode() == X86ISD::SETCC &&
10083 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
10084 isZero(Cond.getOperand(1).getOperand(1))) {
10085 SDValue Cmp = Cond.getOperand(1);
10087 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
10089 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
10090 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
10091 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
10093 SDValue CmpOp0 = Cmp.getOperand(0);
10094 // Apply further optimizations for special cases
10095 // (select (x != 0), -1, 0) -> neg & sbb
10096 // (select (x == 0), 0, -1) -> neg & sbb
10097 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
10098 if (YC->isNullValue() &&
10099 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
10100 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
10101 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
10102 DAG.getConstant(0, CmpOp0.getValueType()),
10104 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10105 DAG.getConstant(X86::COND_B, MVT::i8),
10106 SDValue(Neg.getNode(), 1));
10110 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
10111 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
10112 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10114 SDValue Res = // Res = 0 or -1.
10115 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10116 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
10118 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
10119 Res = DAG.getNOT(DL, Res, Res.getValueType());
10121 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
10122 if (N2C == 0 || !N2C->isNullValue())
10123 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
10128 // Look past (and (setcc_carry (cmp ...)), 1).
10129 if (Cond.getOpcode() == ISD::AND &&
10130 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10131 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10132 if (C && C->getAPIntValue() == 1)
10133 Cond = Cond.getOperand(0);
10136 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10137 // setting operand in place of the X86ISD::SETCC.
10138 unsigned CondOpcode = Cond.getOpcode();
10139 if (CondOpcode == X86ISD::SETCC ||
10140 CondOpcode == X86ISD::SETCC_CARRY) {
10141 CC = Cond.getOperand(0);
10143 SDValue Cmp = Cond.getOperand(1);
10144 unsigned Opc = Cmp.getOpcode();
10145 MVT VT = Op.getValueType().getSimpleVT();
10147 bool IllegalFPCMov = false;
10148 if (VT.isFloatingPoint() && !VT.isVector() &&
10149 !isScalarFPTypeInSSEReg(VT)) // FPStack?
10150 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
10152 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
10153 Opc == X86ISD::BT) { // FIXME
10157 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10158 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10159 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10160 Cond.getOperand(0).getValueType() != MVT::i8)) {
10161 SDValue LHS = Cond.getOperand(0);
10162 SDValue RHS = Cond.getOperand(1);
10163 unsigned X86Opcode;
10166 switch (CondOpcode) {
10167 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10168 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10169 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10170 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10171 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10172 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10173 default: llvm_unreachable("unexpected overflowing operator");
10175 if (CondOpcode == ISD::UMULO)
10176 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10179 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10181 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
10183 if (CondOpcode == ISD::UMULO)
10184 Cond = X86Op.getValue(2);
10186 Cond = X86Op.getValue(1);
10188 CC = DAG.getConstant(X86Cond, MVT::i8);
10193 // Look pass the truncate if the high bits are known zero.
10194 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10195 Cond = Cond.getOperand(0);
10197 // We know the result of AND is compared against zero. Try to match
10199 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10200 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
10201 if (NewSetCC.getNode()) {
10202 CC = NewSetCC.getOperand(0);
10203 Cond = NewSetCC.getOperand(1);
10210 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10211 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10214 // a < b ? -1 : 0 -> RES = ~setcc_carry
10215 // a < b ? 0 : -1 -> RES = setcc_carry
10216 // a >= b ? -1 : 0 -> RES = setcc_carry
10217 // a >= b ? 0 : -1 -> RES = ~setcc_carry
10218 if (Cond.getOpcode() == X86ISD::SUB) {
10219 Cond = ConvertCmpIfNecessary(Cond, DAG);
10220 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
10222 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
10223 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
10224 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10225 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
10226 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
10227 return DAG.getNOT(DL, Res, Res.getValueType());
10232 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
10233 // widen the cmov and push the truncate through. This avoids introducing a new
10234 // branch during isel and doesn't add any extensions.
10235 if (Op.getValueType() == MVT::i8 &&
10236 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
10237 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
10238 if (T1.getValueType() == T2.getValueType() &&
10239 // Blacklist CopyFromReg to avoid partial register stalls.
10240 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
10241 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
10242 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
10243 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
10247 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
10248 // condition is true.
10249 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
10250 SDValue Ops[] = { Op2, Op1, CC, Cond };
10251 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
10254 SDValue X86TargetLowering::LowerSIGN_EXTEND_AVX512(SDValue Op,
10255 SelectionDAG &DAG) const {
10256 EVT VT = Op->getValueType(0);
10257 SDValue In = Op->getOperand(0);
10258 EVT InVT = In.getValueType();
10261 if (InVT.getVectorElementType().getSizeInBits() >=8 &&
10262 VT.getVectorElementType().getSizeInBits() >= 32)
10263 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
10265 if (InVT.getVectorElementType() == MVT::i1) {
10266 unsigned int NumElts = InVT.getVectorNumElements();
10267 assert ((NumElts == 8 || NumElts == 16) &&
10268 "Unsupported SIGN_EXTEND operation");
10269 if (VT.getVectorElementType().getSizeInBits() >= 32) {
10271 ConstantInt::get(*DAG.getContext(),
10272 (NumElts == 8)? APInt(64, ~0ULL): APInt(32, ~0U));
10273 SDValue CP = DAG.getConstantPool(C, getPointerTy());
10274 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
10275 SDValue Ld = DAG.getLoad(VT.getScalarType(), dl, DAG.getEntryNode(), CP,
10276 MachinePointerInfo::getConstantPool(),
10277 false, false, false, Alignment);
10278 return DAG.getNode(X86ISD::VBROADCASTM, dl, VT, In, Ld);
10284 SDValue X86TargetLowering::LowerSIGN_EXTEND(SDValue Op,
10285 SelectionDAG &DAG) const {
10286 MVT VT = Op->getValueType(0).getSimpleVT();
10287 SDValue In = Op->getOperand(0);
10288 MVT InVT = In.getValueType().getSimpleVT();
10291 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
10292 return LowerSIGN_EXTEND_AVX512(Op, DAG);
10294 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
10295 (VT != MVT::v8i32 || InVT != MVT::v8i16))
10298 if (Subtarget->hasInt256())
10299 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, In);
10301 // Optimize vectors in AVX mode
10302 // Sign extend v8i16 to v8i32 and
10305 // Divide input vector into two parts
10306 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
10307 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
10308 // concat the vectors to original VT
10310 unsigned NumElems = InVT.getVectorNumElements();
10311 SDValue Undef = DAG.getUNDEF(InVT);
10313 SmallVector<int,8> ShufMask1(NumElems, -1);
10314 for (unsigned i = 0; i != NumElems/2; ++i)
10317 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
10319 SmallVector<int,8> ShufMask2(NumElems, -1);
10320 for (unsigned i = 0; i != NumElems/2; ++i)
10321 ShufMask2[i] = i + NumElems/2;
10323 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
10325 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
10326 VT.getVectorNumElements()/2);
10328 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
10329 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
10331 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
10334 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
10335 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
10336 // from the AND / OR.
10337 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
10338 Opc = Op.getOpcode();
10339 if (Opc != ISD::OR && Opc != ISD::AND)
10341 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10342 Op.getOperand(0).hasOneUse() &&
10343 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
10344 Op.getOperand(1).hasOneUse());
10347 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
10348 // 1 and that the SETCC node has a single use.
10349 static bool isXor1OfSetCC(SDValue Op) {
10350 if (Op.getOpcode() != ISD::XOR)
10352 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
10353 if (N1C && N1C->getAPIntValue() == 1) {
10354 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10355 Op.getOperand(0).hasOneUse();
10360 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
10361 bool addTest = true;
10362 SDValue Chain = Op.getOperand(0);
10363 SDValue Cond = Op.getOperand(1);
10364 SDValue Dest = Op.getOperand(2);
10367 bool Inverted = false;
10369 if (Cond.getOpcode() == ISD::SETCC) {
10370 // Check for setcc([su]{add,sub,mul}o == 0).
10371 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
10372 isa<ConstantSDNode>(Cond.getOperand(1)) &&
10373 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
10374 Cond.getOperand(0).getResNo() == 1 &&
10375 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
10376 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
10377 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
10378 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
10379 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
10380 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
10382 Cond = Cond.getOperand(0);
10384 SDValue NewCond = LowerSETCC(Cond, DAG);
10385 if (NewCond.getNode())
10390 // FIXME: LowerXALUO doesn't handle these!!
10391 else if (Cond.getOpcode() == X86ISD::ADD ||
10392 Cond.getOpcode() == X86ISD::SUB ||
10393 Cond.getOpcode() == X86ISD::SMUL ||
10394 Cond.getOpcode() == X86ISD::UMUL)
10395 Cond = LowerXALUO(Cond, DAG);
10398 // Look pass (and (setcc_carry (cmp ...)), 1).
10399 if (Cond.getOpcode() == ISD::AND &&
10400 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10401 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10402 if (C && C->getAPIntValue() == 1)
10403 Cond = Cond.getOperand(0);
10406 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10407 // setting operand in place of the X86ISD::SETCC.
10408 unsigned CondOpcode = Cond.getOpcode();
10409 if (CondOpcode == X86ISD::SETCC ||
10410 CondOpcode == X86ISD::SETCC_CARRY) {
10411 CC = Cond.getOperand(0);
10413 SDValue Cmp = Cond.getOperand(1);
10414 unsigned Opc = Cmp.getOpcode();
10415 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
10416 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
10420 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
10424 // These can only come from an arithmetic instruction with overflow,
10425 // e.g. SADDO, UADDO.
10426 Cond = Cond.getNode()->getOperand(1);
10432 CondOpcode = Cond.getOpcode();
10433 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10434 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10435 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10436 Cond.getOperand(0).getValueType() != MVT::i8)) {
10437 SDValue LHS = Cond.getOperand(0);
10438 SDValue RHS = Cond.getOperand(1);
10439 unsigned X86Opcode;
10442 switch (CondOpcode) {
10443 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10444 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10445 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10446 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10447 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10448 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10449 default: llvm_unreachable("unexpected overflowing operator");
10452 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
10453 if (CondOpcode == ISD::UMULO)
10454 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10457 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10459 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
10461 if (CondOpcode == ISD::UMULO)
10462 Cond = X86Op.getValue(2);
10464 Cond = X86Op.getValue(1);
10466 CC = DAG.getConstant(X86Cond, MVT::i8);
10470 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
10471 SDValue Cmp = Cond.getOperand(0).getOperand(1);
10472 if (CondOpc == ISD::OR) {
10473 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
10474 // two branches instead of an explicit OR instruction with a
10476 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10477 isX86LogicalCmp(Cmp)) {
10478 CC = Cond.getOperand(0).getOperand(0);
10479 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10480 Chain, Dest, CC, Cmp);
10481 CC = Cond.getOperand(1).getOperand(0);
10485 } else { // ISD::AND
10486 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
10487 // two branches instead of an explicit AND instruction with a
10488 // separate test. However, we only do this if this block doesn't
10489 // have a fall-through edge, because this requires an explicit
10490 // jmp when the condition is false.
10491 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10492 isX86LogicalCmp(Cmp) &&
10493 Op.getNode()->hasOneUse()) {
10494 X86::CondCode CCode =
10495 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10496 CCode = X86::GetOppositeBranchCondition(CCode);
10497 CC = DAG.getConstant(CCode, MVT::i8);
10498 SDNode *User = *Op.getNode()->use_begin();
10499 // Look for an unconditional branch following this conditional branch.
10500 // We need this because we need to reverse the successors in order
10501 // to implement FCMP_OEQ.
10502 if (User->getOpcode() == ISD::BR) {
10503 SDValue FalseBB = User->getOperand(1);
10505 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10506 assert(NewBR == User);
10510 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10511 Chain, Dest, CC, Cmp);
10512 X86::CondCode CCode =
10513 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
10514 CCode = X86::GetOppositeBranchCondition(CCode);
10515 CC = DAG.getConstant(CCode, MVT::i8);
10521 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
10522 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
10523 // It should be transformed during dag combiner except when the condition
10524 // is set by a arithmetics with overflow node.
10525 X86::CondCode CCode =
10526 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10527 CCode = X86::GetOppositeBranchCondition(CCode);
10528 CC = DAG.getConstant(CCode, MVT::i8);
10529 Cond = Cond.getOperand(0).getOperand(1);
10531 } else if (Cond.getOpcode() == ISD::SETCC &&
10532 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
10533 // For FCMP_OEQ, we can emit
10534 // two branches instead of an explicit AND instruction with a
10535 // separate test. However, we only do this if this block doesn't
10536 // have a fall-through edge, because this requires an explicit
10537 // jmp when the condition is false.
10538 if (Op.getNode()->hasOneUse()) {
10539 SDNode *User = *Op.getNode()->use_begin();
10540 // Look for an unconditional branch following this conditional branch.
10541 // We need this because we need to reverse the successors in order
10542 // to implement FCMP_OEQ.
10543 if (User->getOpcode() == ISD::BR) {
10544 SDValue FalseBB = User->getOperand(1);
10546 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10547 assert(NewBR == User);
10551 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10552 Cond.getOperand(0), Cond.getOperand(1));
10553 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10554 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10555 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10556 Chain, Dest, CC, Cmp);
10557 CC = DAG.getConstant(X86::COND_P, MVT::i8);
10562 } else if (Cond.getOpcode() == ISD::SETCC &&
10563 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
10564 // For FCMP_UNE, we can emit
10565 // two branches instead of an explicit AND instruction with a
10566 // separate test. However, we only do this if this block doesn't
10567 // have a fall-through edge, because this requires an explicit
10568 // jmp when the condition is false.
10569 if (Op.getNode()->hasOneUse()) {
10570 SDNode *User = *Op.getNode()->use_begin();
10571 // Look for an unconditional branch following this conditional branch.
10572 // We need this because we need to reverse the successors in order
10573 // to implement FCMP_UNE.
10574 if (User->getOpcode() == ISD::BR) {
10575 SDValue FalseBB = User->getOperand(1);
10577 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10578 assert(NewBR == User);
10581 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10582 Cond.getOperand(0), Cond.getOperand(1));
10583 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10584 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10585 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10586 Chain, Dest, CC, Cmp);
10587 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
10597 // Look pass the truncate if the high bits are known zero.
10598 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10599 Cond = Cond.getOperand(0);
10601 // We know the result of AND is compared against zero. Try to match
10603 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10604 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
10605 if (NewSetCC.getNode()) {
10606 CC = NewSetCC.getOperand(0);
10607 Cond = NewSetCC.getOperand(1);
10614 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10615 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10617 Cond = ConvertCmpIfNecessary(Cond, DAG);
10618 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10619 Chain, Dest, CC, Cond);
10622 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
10623 // Calls to _alloca is needed to probe the stack when allocating more than 4k
10624 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
10625 // that the guard pages used by the OS virtual memory manager are allocated in
10626 // correct sequence.
10628 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
10629 SelectionDAG &DAG) const {
10630 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
10631 getTargetMachine().Options.EnableSegmentedStacks) &&
10632 "This should be used only on Windows targets or when segmented stacks "
10634 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
10638 SDValue Chain = Op.getOperand(0);
10639 SDValue Size = Op.getOperand(1);
10640 // FIXME: Ensure alignment here
10642 bool Is64Bit = Subtarget->is64Bit();
10643 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
10645 if (getTargetMachine().Options.EnableSegmentedStacks) {
10646 MachineFunction &MF = DAG.getMachineFunction();
10647 MachineRegisterInfo &MRI = MF.getRegInfo();
10650 // The 64 bit implementation of segmented stacks needs to clobber both r10
10651 // r11. This makes it impossible to use it along with nested parameters.
10652 const Function *F = MF.getFunction();
10654 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
10656 if (I->hasNestAttr())
10657 report_fatal_error("Cannot use segmented stacks with functions that "
10658 "have nested arguments.");
10661 const TargetRegisterClass *AddrRegClass =
10662 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
10663 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
10664 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
10665 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
10666 DAG.getRegister(Vreg, SPTy));
10667 SDValue Ops1[2] = { Value, Chain };
10668 return DAG.getMergeValues(Ops1, 2, dl);
10671 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
10673 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
10674 Flag = Chain.getValue(1);
10675 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10677 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
10678 Flag = Chain.getValue(1);
10680 const X86RegisterInfo *RegInfo =
10681 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
10682 Chain = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
10685 SDValue Ops1[2] = { Chain.getValue(0), Chain };
10686 return DAG.getMergeValues(Ops1, 2, dl);
10690 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
10691 MachineFunction &MF = DAG.getMachineFunction();
10692 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
10694 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10697 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
10698 // vastart just stores the address of the VarArgsFrameIndex slot into the
10699 // memory location argument.
10700 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10702 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
10703 MachinePointerInfo(SV), false, false, 0);
10707 // gp_offset (0 - 6 * 8)
10708 // fp_offset (48 - 48 + 8 * 16)
10709 // overflow_arg_area (point to parameters coming in memory).
10711 SmallVector<SDValue, 8> MemOps;
10712 SDValue FIN = Op.getOperand(1);
10714 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
10715 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
10717 FIN, MachinePointerInfo(SV), false, false, 0);
10718 MemOps.push_back(Store);
10721 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10722 FIN, DAG.getIntPtrConstant(4));
10723 Store = DAG.getStore(Op.getOperand(0), DL,
10724 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
10726 FIN, MachinePointerInfo(SV, 4), false, false, 0);
10727 MemOps.push_back(Store);
10729 // Store ptr to overflow_arg_area
10730 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10731 FIN, DAG.getIntPtrConstant(4));
10732 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10734 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
10735 MachinePointerInfo(SV, 8),
10737 MemOps.push_back(Store);
10739 // Store ptr to reg_save_area.
10740 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10741 FIN, DAG.getIntPtrConstant(8));
10742 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
10744 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
10745 MachinePointerInfo(SV, 16), false, false, 0);
10746 MemOps.push_back(Store);
10747 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
10748 &MemOps[0], MemOps.size());
10751 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
10752 assert(Subtarget->is64Bit() &&
10753 "LowerVAARG only handles 64-bit va_arg!");
10754 assert((Subtarget->isTargetLinux() ||
10755 Subtarget->isTargetDarwin()) &&
10756 "Unhandled target in LowerVAARG");
10757 assert(Op.getNode()->getNumOperands() == 4);
10758 SDValue Chain = Op.getOperand(0);
10759 SDValue SrcPtr = Op.getOperand(1);
10760 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10761 unsigned Align = Op.getConstantOperandVal(3);
10764 EVT ArgVT = Op.getNode()->getValueType(0);
10765 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
10766 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
10769 // Decide which area this value should be read from.
10770 // TODO: Implement the AMD64 ABI in its entirety. This simple
10771 // selection mechanism works only for the basic types.
10772 if (ArgVT == MVT::f80) {
10773 llvm_unreachable("va_arg for f80 not yet implemented");
10774 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
10775 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
10776 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
10777 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
10779 llvm_unreachable("Unhandled argument type in LowerVAARG");
10782 if (ArgMode == 2) {
10783 // Sanity Check: Make sure using fp_offset makes sense.
10784 assert(!getTargetMachine().Options.UseSoftFloat &&
10785 !(DAG.getMachineFunction()
10786 .getFunction()->getAttributes()
10787 .hasAttribute(AttributeSet::FunctionIndex,
10788 Attribute::NoImplicitFloat)) &&
10789 Subtarget->hasSSE1());
10792 // Insert VAARG_64 node into the DAG
10793 // VAARG_64 returns two values: Variable Argument Address, Chain
10794 SmallVector<SDValue, 11> InstOps;
10795 InstOps.push_back(Chain);
10796 InstOps.push_back(SrcPtr);
10797 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
10798 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
10799 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
10800 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
10801 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
10802 VTs, &InstOps[0], InstOps.size(),
10804 MachinePointerInfo(SV),
10806 /*Volatile=*/false,
10808 /*WriteMem=*/true);
10809 Chain = VAARG.getValue(1);
10811 // Load the next argument and return it
10812 return DAG.getLoad(ArgVT, dl,
10815 MachinePointerInfo(),
10816 false, false, false, 0);
10819 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
10820 SelectionDAG &DAG) {
10821 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
10822 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
10823 SDValue Chain = Op.getOperand(0);
10824 SDValue DstPtr = Op.getOperand(1);
10825 SDValue SrcPtr = Op.getOperand(2);
10826 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
10827 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
10830 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
10831 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
10833 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
10836 // getTargetVShiftNode - Handle vector element shifts where the shift amount
10837 // may or may not be a constant. Takes immediate version of shift as input.
10838 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, EVT VT,
10839 SDValue SrcOp, SDValue ShAmt,
10840 SelectionDAG &DAG) {
10841 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
10843 if (isa<ConstantSDNode>(ShAmt)) {
10844 // Constant may be a TargetConstant. Use a regular constant.
10845 uint32_t ShiftAmt = cast<ConstantSDNode>(ShAmt)->getZExtValue();
10847 default: llvm_unreachable("Unknown target vector shift node");
10848 case X86ISD::VSHLI:
10849 case X86ISD::VSRLI:
10850 case X86ISD::VSRAI:
10851 return DAG.getNode(Opc, dl, VT, SrcOp,
10852 DAG.getConstant(ShiftAmt, MVT::i32));
10856 // Change opcode to non-immediate version
10858 default: llvm_unreachable("Unknown target vector shift node");
10859 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
10860 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
10861 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
10864 // Need to build a vector containing shift amount
10865 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
10868 ShOps[1] = DAG.getConstant(0, MVT::i32);
10869 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
10870 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
10872 // The return type has to be a 128-bit type with the same element
10873 // type as the input type.
10874 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10875 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
10877 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
10878 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
10881 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
10883 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
10885 default: return SDValue(); // Don't custom lower most intrinsics.
10886 // Comparison intrinsics.
10887 case Intrinsic::x86_sse_comieq_ss:
10888 case Intrinsic::x86_sse_comilt_ss:
10889 case Intrinsic::x86_sse_comile_ss:
10890 case Intrinsic::x86_sse_comigt_ss:
10891 case Intrinsic::x86_sse_comige_ss:
10892 case Intrinsic::x86_sse_comineq_ss:
10893 case Intrinsic::x86_sse_ucomieq_ss:
10894 case Intrinsic::x86_sse_ucomilt_ss:
10895 case Intrinsic::x86_sse_ucomile_ss:
10896 case Intrinsic::x86_sse_ucomigt_ss:
10897 case Intrinsic::x86_sse_ucomige_ss:
10898 case Intrinsic::x86_sse_ucomineq_ss:
10899 case Intrinsic::x86_sse2_comieq_sd:
10900 case Intrinsic::x86_sse2_comilt_sd:
10901 case Intrinsic::x86_sse2_comile_sd:
10902 case Intrinsic::x86_sse2_comigt_sd:
10903 case Intrinsic::x86_sse2_comige_sd:
10904 case Intrinsic::x86_sse2_comineq_sd:
10905 case Intrinsic::x86_sse2_ucomieq_sd:
10906 case Intrinsic::x86_sse2_ucomilt_sd:
10907 case Intrinsic::x86_sse2_ucomile_sd:
10908 case Intrinsic::x86_sse2_ucomigt_sd:
10909 case Intrinsic::x86_sse2_ucomige_sd:
10910 case Intrinsic::x86_sse2_ucomineq_sd: {
10914 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10915 case Intrinsic::x86_sse_comieq_ss:
10916 case Intrinsic::x86_sse2_comieq_sd:
10917 Opc = X86ISD::COMI;
10920 case Intrinsic::x86_sse_comilt_ss:
10921 case Intrinsic::x86_sse2_comilt_sd:
10922 Opc = X86ISD::COMI;
10925 case Intrinsic::x86_sse_comile_ss:
10926 case Intrinsic::x86_sse2_comile_sd:
10927 Opc = X86ISD::COMI;
10930 case Intrinsic::x86_sse_comigt_ss:
10931 case Intrinsic::x86_sse2_comigt_sd:
10932 Opc = X86ISD::COMI;
10935 case Intrinsic::x86_sse_comige_ss:
10936 case Intrinsic::x86_sse2_comige_sd:
10937 Opc = X86ISD::COMI;
10940 case Intrinsic::x86_sse_comineq_ss:
10941 case Intrinsic::x86_sse2_comineq_sd:
10942 Opc = X86ISD::COMI;
10945 case Intrinsic::x86_sse_ucomieq_ss:
10946 case Intrinsic::x86_sse2_ucomieq_sd:
10947 Opc = X86ISD::UCOMI;
10950 case Intrinsic::x86_sse_ucomilt_ss:
10951 case Intrinsic::x86_sse2_ucomilt_sd:
10952 Opc = X86ISD::UCOMI;
10955 case Intrinsic::x86_sse_ucomile_ss:
10956 case Intrinsic::x86_sse2_ucomile_sd:
10957 Opc = X86ISD::UCOMI;
10960 case Intrinsic::x86_sse_ucomigt_ss:
10961 case Intrinsic::x86_sse2_ucomigt_sd:
10962 Opc = X86ISD::UCOMI;
10965 case Intrinsic::x86_sse_ucomige_ss:
10966 case Intrinsic::x86_sse2_ucomige_sd:
10967 Opc = X86ISD::UCOMI;
10970 case Intrinsic::x86_sse_ucomineq_ss:
10971 case Intrinsic::x86_sse2_ucomineq_sd:
10972 Opc = X86ISD::UCOMI;
10977 SDValue LHS = Op.getOperand(1);
10978 SDValue RHS = Op.getOperand(2);
10979 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
10980 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
10981 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
10982 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10983 DAG.getConstant(X86CC, MVT::i8), Cond);
10984 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
10987 // Arithmetic intrinsics.
10988 case Intrinsic::x86_sse2_pmulu_dq:
10989 case Intrinsic::x86_avx2_pmulu_dq:
10990 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
10991 Op.getOperand(1), Op.getOperand(2));
10993 // SSE2/AVX2 sub with unsigned saturation intrinsics
10994 case Intrinsic::x86_sse2_psubus_b:
10995 case Intrinsic::x86_sse2_psubus_w:
10996 case Intrinsic::x86_avx2_psubus_b:
10997 case Intrinsic::x86_avx2_psubus_w:
10998 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
10999 Op.getOperand(1), Op.getOperand(2));
11001 // SSE3/AVX horizontal add/sub intrinsics
11002 case Intrinsic::x86_sse3_hadd_ps:
11003 case Intrinsic::x86_sse3_hadd_pd:
11004 case Intrinsic::x86_avx_hadd_ps_256:
11005 case Intrinsic::x86_avx_hadd_pd_256:
11006 case Intrinsic::x86_sse3_hsub_ps:
11007 case Intrinsic::x86_sse3_hsub_pd:
11008 case Intrinsic::x86_avx_hsub_ps_256:
11009 case Intrinsic::x86_avx_hsub_pd_256:
11010 case Intrinsic::x86_ssse3_phadd_w_128:
11011 case Intrinsic::x86_ssse3_phadd_d_128:
11012 case Intrinsic::x86_avx2_phadd_w:
11013 case Intrinsic::x86_avx2_phadd_d:
11014 case Intrinsic::x86_ssse3_phsub_w_128:
11015 case Intrinsic::x86_ssse3_phsub_d_128:
11016 case Intrinsic::x86_avx2_phsub_w:
11017 case Intrinsic::x86_avx2_phsub_d: {
11020 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11021 case Intrinsic::x86_sse3_hadd_ps:
11022 case Intrinsic::x86_sse3_hadd_pd:
11023 case Intrinsic::x86_avx_hadd_ps_256:
11024 case Intrinsic::x86_avx_hadd_pd_256:
11025 Opcode = X86ISD::FHADD;
11027 case Intrinsic::x86_sse3_hsub_ps:
11028 case Intrinsic::x86_sse3_hsub_pd:
11029 case Intrinsic::x86_avx_hsub_ps_256:
11030 case Intrinsic::x86_avx_hsub_pd_256:
11031 Opcode = X86ISD::FHSUB;
11033 case Intrinsic::x86_ssse3_phadd_w_128:
11034 case Intrinsic::x86_ssse3_phadd_d_128:
11035 case Intrinsic::x86_avx2_phadd_w:
11036 case Intrinsic::x86_avx2_phadd_d:
11037 Opcode = X86ISD::HADD;
11039 case Intrinsic::x86_ssse3_phsub_w_128:
11040 case Intrinsic::x86_ssse3_phsub_d_128:
11041 case Intrinsic::x86_avx2_phsub_w:
11042 case Intrinsic::x86_avx2_phsub_d:
11043 Opcode = X86ISD::HSUB;
11046 return DAG.getNode(Opcode, dl, Op.getValueType(),
11047 Op.getOperand(1), Op.getOperand(2));
11050 // SSE2/SSE41/AVX2 integer max/min intrinsics.
11051 case Intrinsic::x86_sse2_pmaxu_b:
11052 case Intrinsic::x86_sse41_pmaxuw:
11053 case Intrinsic::x86_sse41_pmaxud:
11054 case Intrinsic::x86_avx2_pmaxu_b:
11055 case Intrinsic::x86_avx2_pmaxu_w:
11056 case Intrinsic::x86_avx2_pmaxu_d:
11057 case Intrinsic::x86_sse2_pminu_b:
11058 case Intrinsic::x86_sse41_pminuw:
11059 case Intrinsic::x86_sse41_pminud:
11060 case Intrinsic::x86_avx2_pminu_b:
11061 case Intrinsic::x86_avx2_pminu_w:
11062 case Intrinsic::x86_avx2_pminu_d:
11063 case Intrinsic::x86_sse41_pmaxsb:
11064 case Intrinsic::x86_sse2_pmaxs_w:
11065 case Intrinsic::x86_sse41_pmaxsd:
11066 case Intrinsic::x86_avx2_pmaxs_b:
11067 case Intrinsic::x86_avx2_pmaxs_w:
11068 case Intrinsic::x86_avx2_pmaxs_d:
11069 case Intrinsic::x86_sse41_pminsb:
11070 case Intrinsic::x86_sse2_pmins_w:
11071 case Intrinsic::x86_sse41_pminsd:
11072 case Intrinsic::x86_avx2_pmins_b:
11073 case Intrinsic::x86_avx2_pmins_w:
11074 case Intrinsic::x86_avx2_pmins_d: {
11077 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11078 case Intrinsic::x86_sse2_pmaxu_b:
11079 case Intrinsic::x86_sse41_pmaxuw:
11080 case Intrinsic::x86_sse41_pmaxud:
11081 case Intrinsic::x86_avx2_pmaxu_b:
11082 case Intrinsic::x86_avx2_pmaxu_w:
11083 case Intrinsic::x86_avx2_pmaxu_d:
11084 Opcode = X86ISD::UMAX;
11086 case Intrinsic::x86_sse2_pminu_b:
11087 case Intrinsic::x86_sse41_pminuw:
11088 case Intrinsic::x86_sse41_pminud:
11089 case Intrinsic::x86_avx2_pminu_b:
11090 case Intrinsic::x86_avx2_pminu_w:
11091 case Intrinsic::x86_avx2_pminu_d:
11092 Opcode = X86ISD::UMIN;
11094 case Intrinsic::x86_sse41_pmaxsb:
11095 case Intrinsic::x86_sse2_pmaxs_w:
11096 case Intrinsic::x86_sse41_pmaxsd:
11097 case Intrinsic::x86_avx2_pmaxs_b:
11098 case Intrinsic::x86_avx2_pmaxs_w:
11099 case Intrinsic::x86_avx2_pmaxs_d:
11100 Opcode = X86ISD::SMAX;
11102 case Intrinsic::x86_sse41_pminsb:
11103 case Intrinsic::x86_sse2_pmins_w:
11104 case Intrinsic::x86_sse41_pminsd:
11105 case Intrinsic::x86_avx2_pmins_b:
11106 case Intrinsic::x86_avx2_pmins_w:
11107 case Intrinsic::x86_avx2_pmins_d:
11108 Opcode = X86ISD::SMIN;
11111 return DAG.getNode(Opcode, dl, Op.getValueType(),
11112 Op.getOperand(1), Op.getOperand(2));
11115 // SSE/SSE2/AVX floating point max/min intrinsics.
11116 case Intrinsic::x86_sse_max_ps:
11117 case Intrinsic::x86_sse2_max_pd:
11118 case Intrinsic::x86_avx_max_ps_256:
11119 case Intrinsic::x86_avx_max_pd_256:
11120 case Intrinsic::x86_sse_min_ps:
11121 case Intrinsic::x86_sse2_min_pd:
11122 case Intrinsic::x86_avx_min_ps_256:
11123 case Intrinsic::x86_avx_min_pd_256: {
11126 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11127 case Intrinsic::x86_sse_max_ps:
11128 case Intrinsic::x86_sse2_max_pd:
11129 case Intrinsic::x86_avx_max_ps_256:
11130 case Intrinsic::x86_avx_max_pd_256:
11131 Opcode = X86ISD::FMAX;
11133 case Intrinsic::x86_sse_min_ps:
11134 case Intrinsic::x86_sse2_min_pd:
11135 case Intrinsic::x86_avx_min_ps_256:
11136 case Intrinsic::x86_avx_min_pd_256:
11137 Opcode = X86ISD::FMIN;
11140 return DAG.getNode(Opcode, dl, Op.getValueType(),
11141 Op.getOperand(1), Op.getOperand(2));
11144 // AVX2 variable shift intrinsics
11145 case Intrinsic::x86_avx2_psllv_d:
11146 case Intrinsic::x86_avx2_psllv_q:
11147 case Intrinsic::x86_avx2_psllv_d_256:
11148 case Intrinsic::x86_avx2_psllv_q_256:
11149 case Intrinsic::x86_avx2_psrlv_d:
11150 case Intrinsic::x86_avx2_psrlv_q:
11151 case Intrinsic::x86_avx2_psrlv_d_256:
11152 case Intrinsic::x86_avx2_psrlv_q_256:
11153 case Intrinsic::x86_avx2_psrav_d:
11154 case Intrinsic::x86_avx2_psrav_d_256: {
11157 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11158 case Intrinsic::x86_avx2_psllv_d:
11159 case Intrinsic::x86_avx2_psllv_q:
11160 case Intrinsic::x86_avx2_psllv_d_256:
11161 case Intrinsic::x86_avx2_psllv_q_256:
11164 case Intrinsic::x86_avx2_psrlv_d:
11165 case Intrinsic::x86_avx2_psrlv_q:
11166 case Intrinsic::x86_avx2_psrlv_d_256:
11167 case Intrinsic::x86_avx2_psrlv_q_256:
11170 case Intrinsic::x86_avx2_psrav_d:
11171 case Intrinsic::x86_avx2_psrav_d_256:
11175 return DAG.getNode(Opcode, dl, Op.getValueType(),
11176 Op.getOperand(1), Op.getOperand(2));
11179 case Intrinsic::x86_ssse3_pshuf_b_128:
11180 case Intrinsic::x86_avx2_pshuf_b:
11181 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
11182 Op.getOperand(1), Op.getOperand(2));
11184 case Intrinsic::x86_ssse3_psign_b_128:
11185 case Intrinsic::x86_ssse3_psign_w_128:
11186 case Intrinsic::x86_ssse3_psign_d_128:
11187 case Intrinsic::x86_avx2_psign_b:
11188 case Intrinsic::x86_avx2_psign_w:
11189 case Intrinsic::x86_avx2_psign_d:
11190 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
11191 Op.getOperand(1), Op.getOperand(2));
11193 case Intrinsic::x86_sse41_insertps:
11194 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
11195 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11197 case Intrinsic::x86_avx_vperm2f128_ps_256:
11198 case Intrinsic::x86_avx_vperm2f128_pd_256:
11199 case Intrinsic::x86_avx_vperm2f128_si_256:
11200 case Intrinsic::x86_avx2_vperm2i128:
11201 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
11202 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11204 case Intrinsic::x86_avx2_permd:
11205 case Intrinsic::x86_avx2_permps:
11206 // Operands intentionally swapped. Mask is last operand to intrinsic,
11207 // but second operand for node/intruction.
11208 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
11209 Op.getOperand(2), Op.getOperand(1));
11211 case Intrinsic::x86_sse_sqrt_ps:
11212 case Intrinsic::x86_sse2_sqrt_pd:
11213 case Intrinsic::x86_avx_sqrt_ps_256:
11214 case Intrinsic::x86_avx_sqrt_pd_256:
11215 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
11217 // ptest and testp intrinsics. The intrinsic these come from are designed to
11218 // return an integer value, not just an instruction so lower it to the ptest
11219 // or testp pattern and a setcc for the result.
11220 case Intrinsic::x86_sse41_ptestz:
11221 case Intrinsic::x86_sse41_ptestc:
11222 case Intrinsic::x86_sse41_ptestnzc:
11223 case Intrinsic::x86_avx_ptestz_256:
11224 case Intrinsic::x86_avx_ptestc_256:
11225 case Intrinsic::x86_avx_ptestnzc_256:
11226 case Intrinsic::x86_avx_vtestz_ps:
11227 case Intrinsic::x86_avx_vtestc_ps:
11228 case Intrinsic::x86_avx_vtestnzc_ps:
11229 case Intrinsic::x86_avx_vtestz_pd:
11230 case Intrinsic::x86_avx_vtestc_pd:
11231 case Intrinsic::x86_avx_vtestnzc_pd:
11232 case Intrinsic::x86_avx_vtestz_ps_256:
11233 case Intrinsic::x86_avx_vtestc_ps_256:
11234 case Intrinsic::x86_avx_vtestnzc_ps_256:
11235 case Intrinsic::x86_avx_vtestz_pd_256:
11236 case Intrinsic::x86_avx_vtestc_pd_256:
11237 case Intrinsic::x86_avx_vtestnzc_pd_256: {
11238 bool IsTestPacked = false;
11241 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
11242 case Intrinsic::x86_avx_vtestz_ps:
11243 case Intrinsic::x86_avx_vtestz_pd:
11244 case Intrinsic::x86_avx_vtestz_ps_256:
11245 case Intrinsic::x86_avx_vtestz_pd_256:
11246 IsTestPacked = true; // Fallthrough
11247 case Intrinsic::x86_sse41_ptestz:
11248 case Intrinsic::x86_avx_ptestz_256:
11250 X86CC = X86::COND_E;
11252 case Intrinsic::x86_avx_vtestc_ps:
11253 case Intrinsic::x86_avx_vtestc_pd:
11254 case Intrinsic::x86_avx_vtestc_ps_256:
11255 case Intrinsic::x86_avx_vtestc_pd_256:
11256 IsTestPacked = true; // Fallthrough
11257 case Intrinsic::x86_sse41_ptestc:
11258 case Intrinsic::x86_avx_ptestc_256:
11260 X86CC = X86::COND_B;
11262 case Intrinsic::x86_avx_vtestnzc_ps:
11263 case Intrinsic::x86_avx_vtestnzc_pd:
11264 case Intrinsic::x86_avx_vtestnzc_ps_256:
11265 case Intrinsic::x86_avx_vtestnzc_pd_256:
11266 IsTestPacked = true; // Fallthrough
11267 case Intrinsic::x86_sse41_ptestnzc:
11268 case Intrinsic::x86_avx_ptestnzc_256:
11270 X86CC = X86::COND_A;
11274 SDValue LHS = Op.getOperand(1);
11275 SDValue RHS = Op.getOperand(2);
11276 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
11277 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
11278 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11279 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
11280 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11283 // SSE/AVX shift intrinsics
11284 case Intrinsic::x86_sse2_psll_w:
11285 case Intrinsic::x86_sse2_psll_d:
11286 case Intrinsic::x86_sse2_psll_q:
11287 case Intrinsic::x86_avx2_psll_w:
11288 case Intrinsic::x86_avx2_psll_d:
11289 case Intrinsic::x86_avx2_psll_q:
11290 case Intrinsic::x86_sse2_psrl_w:
11291 case Intrinsic::x86_sse2_psrl_d:
11292 case Intrinsic::x86_sse2_psrl_q:
11293 case Intrinsic::x86_avx2_psrl_w:
11294 case Intrinsic::x86_avx2_psrl_d:
11295 case Intrinsic::x86_avx2_psrl_q:
11296 case Intrinsic::x86_sse2_psra_w:
11297 case Intrinsic::x86_sse2_psra_d:
11298 case Intrinsic::x86_avx2_psra_w:
11299 case Intrinsic::x86_avx2_psra_d: {
11302 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11303 case Intrinsic::x86_sse2_psll_w:
11304 case Intrinsic::x86_sse2_psll_d:
11305 case Intrinsic::x86_sse2_psll_q:
11306 case Intrinsic::x86_avx2_psll_w:
11307 case Intrinsic::x86_avx2_psll_d:
11308 case Intrinsic::x86_avx2_psll_q:
11309 Opcode = X86ISD::VSHL;
11311 case Intrinsic::x86_sse2_psrl_w:
11312 case Intrinsic::x86_sse2_psrl_d:
11313 case Intrinsic::x86_sse2_psrl_q:
11314 case Intrinsic::x86_avx2_psrl_w:
11315 case Intrinsic::x86_avx2_psrl_d:
11316 case Intrinsic::x86_avx2_psrl_q:
11317 Opcode = X86ISD::VSRL;
11319 case Intrinsic::x86_sse2_psra_w:
11320 case Intrinsic::x86_sse2_psra_d:
11321 case Intrinsic::x86_avx2_psra_w:
11322 case Intrinsic::x86_avx2_psra_d:
11323 Opcode = X86ISD::VSRA;
11326 return DAG.getNode(Opcode, dl, Op.getValueType(),
11327 Op.getOperand(1), Op.getOperand(2));
11330 // SSE/AVX immediate shift intrinsics
11331 case Intrinsic::x86_sse2_pslli_w:
11332 case Intrinsic::x86_sse2_pslli_d:
11333 case Intrinsic::x86_sse2_pslli_q:
11334 case Intrinsic::x86_avx2_pslli_w:
11335 case Intrinsic::x86_avx2_pslli_d:
11336 case Intrinsic::x86_avx2_pslli_q:
11337 case Intrinsic::x86_sse2_psrli_w:
11338 case Intrinsic::x86_sse2_psrli_d:
11339 case Intrinsic::x86_sse2_psrli_q:
11340 case Intrinsic::x86_avx2_psrli_w:
11341 case Intrinsic::x86_avx2_psrli_d:
11342 case Intrinsic::x86_avx2_psrli_q:
11343 case Intrinsic::x86_sse2_psrai_w:
11344 case Intrinsic::x86_sse2_psrai_d:
11345 case Intrinsic::x86_avx2_psrai_w:
11346 case Intrinsic::x86_avx2_psrai_d: {
11349 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11350 case Intrinsic::x86_sse2_pslli_w:
11351 case Intrinsic::x86_sse2_pslli_d:
11352 case Intrinsic::x86_sse2_pslli_q:
11353 case Intrinsic::x86_avx2_pslli_w:
11354 case Intrinsic::x86_avx2_pslli_d:
11355 case Intrinsic::x86_avx2_pslli_q:
11356 Opcode = X86ISD::VSHLI;
11358 case Intrinsic::x86_sse2_psrli_w:
11359 case Intrinsic::x86_sse2_psrli_d:
11360 case Intrinsic::x86_sse2_psrli_q:
11361 case Intrinsic::x86_avx2_psrli_w:
11362 case Intrinsic::x86_avx2_psrli_d:
11363 case Intrinsic::x86_avx2_psrli_q:
11364 Opcode = X86ISD::VSRLI;
11366 case Intrinsic::x86_sse2_psrai_w:
11367 case Intrinsic::x86_sse2_psrai_d:
11368 case Intrinsic::x86_avx2_psrai_w:
11369 case Intrinsic::x86_avx2_psrai_d:
11370 Opcode = X86ISD::VSRAI;
11373 return getTargetVShiftNode(Opcode, dl, Op.getValueType(),
11374 Op.getOperand(1), Op.getOperand(2), DAG);
11377 case Intrinsic::x86_sse42_pcmpistria128:
11378 case Intrinsic::x86_sse42_pcmpestria128:
11379 case Intrinsic::x86_sse42_pcmpistric128:
11380 case Intrinsic::x86_sse42_pcmpestric128:
11381 case Intrinsic::x86_sse42_pcmpistrio128:
11382 case Intrinsic::x86_sse42_pcmpestrio128:
11383 case Intrinsic::x86_sse42_pcmpistris128:
11384 case Intrinsic::x86_sse42_pcmpestris128:
11385 case Intrinsic::x86_sse42_pcmpistriz128:
11386 case Intrinsic::x86_sse42_pcmpestriz128: {
11390 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11391 case Intrinsic::x86_sse42_pcmpistria128:
11392 Opcode = X86ISD::PCMPISTRI;
11393 X86CC = X86::COND_A;
11395 case Intrinsic::x86_sse42_pcmpestria128:
11396 Opcode = X86ISD::PCMPESTRI;
11397 X86CC = X86::COND_A;
11399 case Intrinsic::x86_sse42_pcmpistric128:
11400 Opcode = X86ISD::PCMPISTRI;
11401 X86CC = X86::COND_B;
11403 case Intrinsic::x86_sse42_pcmpestric128:
11404 Opcode = X86ISD::PCMPESTRI;
11405 X86CC = X86::COND_B;
11407 case Intrinsic::x86_sse42_pcmpistrio128:
11408 Opcode = X86ISD::PCMPISTRI;
11409 X86CC = X86::COND_O;
11411 case Intrinsic::x86_sse42_pcmpestrio128:
11412 Opcode = X86ISD::PCMPESTRI;
11413 X86CC = X86::COND_O;
11415 case Intrinsic::x86_sse42_pcmpistris128:
11416 Opcode = X86ISD::PCMPISTRI;
11417 X86CC = X86::COND_S;
11419 case Intrinsic::x86_sse42_pcmpestris128:
11420 Opcode = X86ISD::PCMPESTRI;
11421 X86CC = X86::COND_S;
11423 case Intrinsic::x86_sse42_pcmpistriz128:
11424 Opcode = X86ISD::PCMPISTRI;
11425 X86CC = X86::COND_E;
11427 case Intrinsic::x86_sse42_pcmpestriz128:
11428 Opcode = X86ISD::PCMPESTRI;
11429 X86CC = X86::COND_E;
11432 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11433 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11434 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11435 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11436 DAG.getConstant(X86CC, MVT::i8),
11437 SDValue(PCMP.getNode(), 1));
11438 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11441 case Intrinsic::x86_sse42_pcmpistri128:
11442 case Intrinsic::x86_sse42_pcmpestri128: {
11444 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
11445 Opcode = X86ISD::PCMPISTRI;
11447 Opcode = X86ISD::PCMPESTRI;
11449 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11450 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11451 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11453 case Intrinsic::x86_fma_vfmadd_ps:
11454 case Intrinsic::x86_fma_vfmadd_pd:
11455 case Intrinsic::x86_fma_vfmsub_ps:
11456 case Intrinsic::x86_fma_vfmsub_pd:
11457 case Intrinsic::x86_fma_vfnmadd_ps:
11458 case Intrinsic::x86_fma_vfnmadd_pd:
11459 case Intrinsic::x86_fma_vfnmsub_ps:
11460 case Intrinsic::x86_fma_vfnmsub_pd:
11461 case Intrinsic::x86_fma_vfmaddsub_ps:
11462 case Intrinsic::x86_fma_vfmaddsub_pd:
11463 case Intrinsic::x86_fma_vfmsubadd_ps:
11464 case Intrinsic::x86_fma_vfmsubadd_pd:
11465 case Intrinsic::x86_fma_vfmadd_ps_256:
11466 case Intrinsic::x86_fma_vfmadd_pd_256:
11467 case Intrinsic::x86_fma_vfmsub_ps_256:
11468 case Intrinsic::x86_fma_vfmsub_pd_256:
11469 case Intrinsic::x86_fma_vfnmadd_ps_256:
11470 case Intrinsic::x86_fma_vfnmadd_pd_256:
11471 case Intrinsic::x86_fma_vfnmsub_ps_256:
11472 case Intrinsic::x86_fma_vfnmsub_pd_256:
11473 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11474 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11475 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11476 case Intrinsic::x86_fma_vfmsubadd_pd_256: {
11479 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11480 case Intrinsic::x86_fma_vfmadd_ps:
11481 case Intrinsic::x86_fma_vfmadd_pd:
11482 case Intrinsic::x86_fma_vfmadd_ps_256:
11483 case Intrinsic::x86_fma_vfmadd_pd_256:
11484 Opc = X86ISD::FMADD;
11486 case Intrinsic::x86_fma_vfmsub_ps:
11487 case Intrinsic::x86_fma_vfmsub_pd:
11488 case Intrinsic::x86_fma_vfmsub_ps_256:
11489 case Intrinsic::x86_fma_vfmsub_pd_256:
11490 Opc = X86ISD::FMSUB;
11492 case Intrinsic::x86_fma_vfnmadd_ps:
11493 case Intrinsic::x86_fma_vfnmadd_pd:
11494 case Intrinsic::x86_fma_vfnmadd_ps_256:
11495 case Intrinsic::x86_fma_vfnmadd_pd_256:
11496 Opc = X86ISD::FNMADD;
11498 case Intrinsic::x86_fma_vfnmsub_ps:
11499 case Intrinsic::x86_fma_vfnmsub_pd:
11500 case Intrinsic::x86_fma_vfnmsub_ps_256:
11501 case Intrinsic::x86_fma_vfnmsub_pd_256:
11502 Opc = X86ISD::FNMSUB;
11504 case Intrinsic::x86_fma_vfmaddsub_ps:
11505 case Intrinsic::x86_fma_vfmaddsub_pd:
11506 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11507 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11508 Opc = X86ISD::FMADDSUB;
11510 case Intrinsic::x86_fma_vfmsubadd_ps:
11511 case Intrinsic::x86_fma_vfmsubadd_pd:
11512 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11513 case Intrinsic::x86_fma_vfmsubadd_pd_256:
11514 Opc = X86ISD::FMSUBADD;
11518 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
11519 Op.getOperand(2), Op.getOperand(3));
11524 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) {
11526 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11528 default: return SDValue(); // Don't custom lower most intrinsics.
11530 // RDRAND/RDSEED intrinsics.
11531 case Intrinsic::x86_rdrand_16:
11532 case Intrinsic::x86_rdrand_32:
11533 case Intrinsic::x86_rdrand_64:
11534 case Intrinsic::x86_rdseed_16:
11535 case Intrinsic::x86_rdseed_32:
11536 case Intrinsic::x86_rdseed_64: {
11537 unsigned Opcode = (IntNo == Intrinsic::x86_rdseed_16 ||
11538 IntNo == Intrinsic::x86_rdseed_32 ||
11539 IntNo == Intrinsic::x86_rdseed_64) ? X86ISD::RDSEED :
11541 // Emit the node with the right value type.
11542 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
11543 SDValue Result = DAG.getNode(Opcode, dl, VTs, Op.getOperand(0));
11545 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
11546 // Otherwise return the value from Rand, which is always 0, casted to i32.
11547 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
11548 DAG.getConstant(1, Op->getValueType(1)),
11549 DAG.getConstant(X86::COND_B, MVT::i32),
11550 SDValue(Result.getNode(), 1) };
11551 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
11552 DAG.getVTList(Op->getValueType(1), MVT::Glue),
11553 Ops, array_lengthof(Ops));
11555 // Return { result, isValid, chain }.
11556 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
11557 SDValue(Result.getNode(), 2));
11560 // XTEST intrinsics.
11561 case Intrinsic::x86_xtest: {
11562 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
11563 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
11564 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11565 DAG.getConstant(X86::COND_NE, MVT::i8),
11567 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
11568 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
11569 Ret, SDValue(InTrans.getNode(), 1));
11574 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
11575 SelectionDAG &DAG) const {
11576 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11577 MFI->setReturnAddressIsTaken(true);
11579 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11581 EVT PtrVT = getPointerTy();
11584 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
11585 const X86RegisterInfo *RegInfo =
11586 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11587 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
11588 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
11589 DAG.getNode(ISD::ADD, dl, PtrVT,
11590 FrameAddr, Offset),
11591 MachinePointerInfo(), false, false, false, 0);
11594 // Just load the return address.
11595 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
11596 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
11597 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
11600 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
11601 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11602 MFI->setFrameAddressIsTaken(true);
11604 EVT VT = Op.getValueType();
11605 SDLoc dl(Op); // FIXME probably not meaningful
11606 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11607 const X86RegisterInfo *RegInfo =
11608 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11609 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
11610 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
11611 (FrameReg == X86::EBP && VT == MVT::i32)) &&
11612 "Invalid Frame Register!");
11613 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
11615 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
11616 MachinePointerInfo(),
11617 false, false, false, 0);
11621 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
11622 SelectionDAG &DAG) const {
11623 const X86RegisterInfo *RegInfo =
11624 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11625 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
11628 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
11629 SDValue Chain = Op.getOperand(0);
11630 SDValue Offset = Op.getOperand(1);
11631 SDValue Handler = Op.getOperand(2);
11634 EVT PtrVT = getPointerTy();
11635 const X86RegisterInfo *RegInfo =
11636 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11637 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
11638 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
11639 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
11640 "Invalid Frame Register!");
11641 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
11642 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
11644 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
11645 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
11646 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
11647 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
11649 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
11651 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
11652 DAG.getRegister(StoreAddrReg, PtrVT));
11655 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
11656 SelectionDAG &DAG) const {
11658 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
11659 DAG.getVTList(MVT::i32, MVT::Other),
11660 Op.getOperand(0), Op.getOperand(1));
11663 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
11664 SelectionDAG &DAG) const {
11666 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
11667 Op.getOperand(0), Op.getOperand(1));
11670 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
11671 return Op.getOperand(0);
11674 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
11675 SelectionDAG &DAG) const {
11676 SDValue Root = Op.getOperand(0);
11677 SDValue Trmp = Op.getOperand(1); // trampoline
11678 SDValue FPtr = Op.getOperand(2); // nested function
11679 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
11682 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
11683 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
11685 if (Subtarget->is64Bit()) {
11686 SDValue OutChains[6];
11688 // Large code-model.
11689 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
11690 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
11692 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
11693 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
11695 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
11697 // Load the pointer to the nested function into R11.
11698 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
11699 SDValue Addr = Trmp;
11700 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
11701 Addr, MachinePointerInfo(TrmpAddr),
11704 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11705 DAG.getConstant(2, MVT::i64));
11706 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
11707 MachinePointerInfo(TrmpAddr, 2),
11710 // Load the 'nest' parameter value into R10.
11711 // R10 is specified in X86CallingConv.td
11712 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
11713 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11714 DAG.getConstant(10, MVT::i64));
11715 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
11716 Addr, MachinePointerInfo(TrmpAddr, 10),
11719 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11720 DAG.getConstant(12, MVT::i64));
11721 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
11722 MachinePointerInfo(TrmpAddr, 12),
11725 // Jump to the nested function.
11726 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
11727 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11728 DAG.getConstant(20, MVT::i64));
11729 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
11730 Addr, MachinePointerInfo(TrmpAddr, 20),
11733 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
11734 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11735 DAG.getConstant(22, MVT::i64));
11736 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
11737 MachinePointerInfo(TrmpAddr, 22),
11740 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
11742 const Function *Func =
11743 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
11744 CallingConv::ID CC = Func->getCallingConv();
11749 llvm_unreachable("Unsupported calling convention");
11750 case CallingConv::C:
11751 case CallingConv::X86_StdCall: {
11752 // Pass 'nest' parameter in ECX.
11753 // Must be kept in sync with X86CallingConv.td
11754 NestReg = X86::ECX;
11756 // Check that ECX wasn't needed by an 'inreg' parameter.
11757 FunctionType *FTy = Func->getFunctionType();
11758 const AttributeSet &Attrs = Func->getAttributes();
11760 if (!Attrs.isEmpty() && !Func->isVarArg()) {
11761 unsigned InRegCount = 0;
11764 for (FunctionType::param_iterator I = FTy->param_begin(),
11765 E = FTy->param_end(); I != E; ++I, ++Idx)
11766 if (Attrs.hasAttribute(Idx, Attribute::InReg))
11767 // FIXME: should only count parameters that are lowered to integers.
11768 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
11770 if (InRegCount > 2) {
11771 report_fatal_error("Nest register in use - reduce number of inreg"
11777 case CallingConv::X86_FastCall:
11778 case CallingConv::X86_ThisCall:
11779 case CallingConv::Fast:
11780 // Pass 'nest' parameter in EAX.
11781 // Must be kept in sync with X86CallingConv.td
11782 NestReg = X86::EAX;
11786 SDValue OutChains[4];
11787 SDValue Addr, Disp;
11789 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11790 DAG.getConstant(10, MVT::i32));
11791 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
11793 // This is storing the opcode for MOV32ri.
11794 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
11795 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
11796 OutChains[0] = DAG.getStore(Root, dl,
11797 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
11798 Trmp, MachinePointerInfo(TrmpAddr),
11801 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11802 DAG.getConstant(1, MVT::i32));
11803 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
11804 MachinePointerInfo(TrmpAddr, 1),
11807 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
11808 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11809 DAG.getConstant(5, MVT::i32));
11810 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
11811 MachinePointerInfo(TrmpAddr, 5),
11814 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11815 DAG.getConstant(6, MVT::i32));
11816 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
11817 MachinePointerInfo(TrmpAddr, 6),
11820 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
11824 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
11825 SelectionDAG &DAG) const {
11827 The rounding mode is in bits 11:10 of FPSR, and has the following
11829 00 Round to nearest
11834 FLT_ROUNDS, on the other hand, expects the following:
11841 To perform the conversion, we do:
11842 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
11845 MachineFunction &MF = DAG.getMachineFunction();
11846 const TargetMachine &TM = MF.getTarget();
11847 const TargetFrameLowering &TFI = *TM.getFrameLowering();
11848 unsigned StackAlignment = TFI.getStackAlignment();
11849 EVT VT = Op.getValueType();
11852 // Save FP Control Word to stack slot
11853 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
11854 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11856 MachineMemOperand *MMO =
11857 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11858 MachineMemOperand::MOStore, 2, 2);
11860 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
11861 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
11862 DAG.getVTList(MVT::Other),
11863 Ops, array_lengthof(Ops), MVT::i16,
11866 // Load FP Control Word from stack slot
11867 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
11868 MachinePointerInfo(), false, false, false, 0);
11870 // Transform as necessary
11872 DAG.getNode(ISD::SRL, DL, MVT::i16,
11873 DAG.getNode(ISD::AND, DL, MVT::i16,
11874 CWD, DAG.getConstant(0x800, MVT::i16)),
11875 DAG.getConstant(11, MVT::i8));
11877 DAG.getNode(ISD::SRL, DL, MVT::i16,
11878 DAG.getNode(ISD::AND, DL, MVT::i16,
11879 CWD, DAG.getConstant(0x400, MVT::i16)),
11880 DAG.getConstant(9, MVT::i8));
11883 DAG.getNode(ISD::AND, DL, MVT::i16,
11884 DAG.getNode(ISD::ADD, DL, MVT::i16,
11885 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
11886 DAG.getConstant(1, MVT::i16)),
11887 DAG.getConstant(3, MVT::i16));
11889 return DAG.getNode((VT.getSizeInBits() < 16 ?
11890 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
11893 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
11894 EVT VT = Op.getValueType();
11896 unsigned NumBits = VT.getSizeInBits();
11899 Op = Op.getOperand(0);
11900 if (VT == MVT::i8) {
11901 // Zero extend to i32 since there is not an i8 bsr.
11903 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
11906 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
11907 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
11908 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
11910 // If src is zero (i.e. bsr sets ZF), returns NumBits.
11913 DAG.getConstant(NumBits+NumBits-1, OpVT),
11914 DAG.getConstant(X86::COND_E, MVT::i8),
11917 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
11919 // Finally xor with NumBits-1.
11920 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
11923 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
11927 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
11928 EVT VT = Op.getValueType();
11930 unsigned NumBits = VT.getSizeInBits();
11933 Op = Op.getOperand(0);
11934 if (VT == MVT::i8) {
11935 // Zero extend to i32 since there is not an i8 bsr.
11937 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
11940 // Issue a bsr (scan bits in reverse).
11941 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
11942 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
11944 // And xor with NumBits-1.
11945 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
11948 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
11952 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
11953 EVT VT = Op.getValueType();
11954 unsigned NumBits = VT.getSizeInBits();
11956 Op = Op.getOperand(0);
11958 // Issue a bsf (scan bits forward) which also sets EFLAGS.
11959 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
11960 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
11962 // If src is zero (i.e. bsf sets ZF), returns NumBits.
11965 DAG.getConstant(NumBits, VT),
11966 DAG.getConstant(X86::COND_E, MVT::i8),
11969 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
11972 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
11973 // ones, and then concatenate the result back.
11974 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
11975 EVT VT = Op.getValueType();
11977 assert(VT.is256BitVector() && VT.isInteger() &&
11978 "Unsupported value type for operation");
11980 unsigned NumElems = VT.getVectorNumElements();
11983 // Extract the LHS vectors
11984 SDValue LHS = Op.getOperand(0);
11985 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
11986 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
11988 // Extract the RHS vectors
11989 SDValue RHS = Op.getOperand(1);
11990 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
11991 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
11993 MVT EltVT = VT.getVectorElementType().getSimpleVT();
11994 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
11996 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
11997 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
11998 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
12001 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
12002 assert(Op.getValueType().is256BitVector() &&
12003 Op.getValueType().isInteger() &&
12004 "Only handle AVX 256-bit vector integer operation");
12005 return Lower256IntArith(Op, DAG);
12008 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
12009 assert(Op.getValueType().is256BitVector() &&
12010 Op.getValueType().isInteger() &&
12011 "Only handle AVX 256-bit vector integer operation");
12012 return Lower256IntArith(Op, DAG);
12015 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
12016 SelectionDAG &DAG) {
12018 EVT VT = Op.getValueType();
12020 // Decompose 256-bit ops into smaller 128-bit ops.
12021 if (VT.is256BitVector() && !Subtarget->hasInt256())
12022 return Lower256IntArith(Op, DAG);
12024 SDValue A = Op.getOperand(0);
12025 SDValue B = Op.getOperand(1);
12027 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
12028 if (VT == MVT::v4i32) {
12029 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
12030 "Should not custom lower when pmuldq is available!");
12032 // Extract the odd parts.
12033 static const int UnpackMask[] = { 1, -1, 3, -1 };
12034 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
12035 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
12037 // Multiply the even parts.
12038 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
12039 // Now multiply odd parts.
12040 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
12042 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
12043 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
12045 // Merge the two vectors back together with a shuffle. This expands into 2
12047 static const int ShufMask[] = { 0, 4, 2, 6 };
12048 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
12051 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
12052 "Only know how to lower V2I64/V4I64 multiply");
12054 // Ahi = psrlqi(a, 32);
12055 // Bhi = psrlqi(b, 32);
12057 // AloBlo = pmuludq(a, b);
12058 // AloBhi = pmuludq(a, Bhi);
12059 // AhiBlo = pmuludq(Ahi, b);
12061 // AloBhi = psllqi(AloBhi, 32);
12062 // AhiBlo = psllqi(AhiBlo, 32);
12063 // return AloBlo + AloBhi + AhiBlo;
12065 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
12067 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
12068 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
12070 // Bit cast to 32-bit vectors for MULUDQ
12071 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
12072 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
12073 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
12074 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
12075 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
12077 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
12078 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
12079 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
12081 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
12082 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
12084 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
12085 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
12088 SDValue X86TargetLowering::LowerSDIV(SDValue Op, SelectionDAG &DAG) const {
12089 EVT VT = Op.getValueType();
12090 EVT EltTy = VT.getVectorElementType();
12091 unsigned NumElts = VT.getVectorNumElements();
12092 SDValue N0 = Op.getOperand(0);
12095 // Lower sdiv X, pow2-const.
12096 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(Op.getOperand(1));
12100 APInt SplatValue, SplatUndef;
12101 unsigned SplatBitSize;
12103 if (!C->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
12105 EltTy.getSizeInBits() < SplatBitSize)
12108 if ((SplatValue != 0) &&
12109 (SplatValue.isPowerOf2() || (-SplatValue).isPowerOf2())) {
12110 unsigned lg2 = SplatValue.countTrailingZeros();
12111 // Splat the sign bit.
12112 SDValue Sz = DAG.getConstant(EltTy.getSizeInBits()-1, MVT::i32);
12113 SDValue SGN = getTargetVShiftNode(X86ISD::VSRAI, dl, VT, N0, Sz, DAG);
12114 // Add (N0 < 0) ? abs2 - 1 : 0;
12115 SDValue Amt = DAG.getConstant(EltTy.getSizeInBits() - lg2, MVT::i32);
12116 SDValue SRL = getTargetVShiftNode(X86ISD::VSRLI, dl, VT, SGN, Amt, DAG);
12117 SDValue ADD = DAG.getNode(ISD::ADD, dl, VT, N0, SRL);
12118 SDValue Lg2Amt = DAG.getConstant(lg2, MVT::i32);
12119 SDValue SRA = getTargetVShiftNode(X86ISD::VSRAI, dl, VT, ADD, Lg2Amt, DAG);
12121 // If we're dividing by a positive value, we're done. Otherwise, we must
12122 // negate the result.
12123 if (SplatValue.isNonNegative())
12126 SmallVector<SDValue, 16> V(NumElts, DAG.getConstant(0, EltTy));
12127 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], NumElts);
12128 return DAG.getNode(ISD::SUB, dl, VT, Zero, SRA);
12133 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
12134 const X86Subtarget *Subtarget) {
12135 EVT VT = Op.getValueType();
12137 SDValue R = Op.getOperand(0);
12138 SDValue Amt = Op.getOperand(1);
12140 // Optimize shl/srl/sra with constant shift amount.
12141 if (isSplatVector(Amt.getNode())) {
12142 SDValue SclrAmt = Amt->getOperand(0);
12143 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
12144 uint64_t ShiftAmt = C->getZExtValue();
12146 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
12147 (Subtarget->hasInt256() &&
12148 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
12149 if (Op.getOpcode() == ISD::SHL)
12150 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
12151 DAG.getConstant(ShiftAmt, MVT::i32));
12152 if (Op.getOpcode() == ISD::SRL)
12153 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
12154 DAG.getConstant(ShiftAmt, MVT::i32));
12155 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
12156 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
12157 DAG.getConstant(ShiftAmt, MVT::i32));
12160 if (VT == MVT::v16i8) {
12161 if (Op.getOpcode() == ISD::SHL) {
12162 // Make a large shift.
12163 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
12164 DAG.getConstant(ShiftAmt, MVT::i32));
12165 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12166 // Zero out the rightmost bits.
12167 SmallVector<SDValue, 16> V(16,
12168 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12170 return DAG.getNode(ISD::AND, dl, VT, SHL,
12171 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12173 if (Op.getOpcode() == ISD::SRL) {
12174 // Make a large shift.
12175 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
12176 DAG.getConstant(ShiftAmt, MVT::i32));
12177 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12178 // Zero out the leftmost bits.
12179 SmallVector<SDValue, 16> V(16,
12180 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12182 return DAG.getNode(ISD::AND, dl, VT, SRL,
12183 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12185 if (Op.getOpcode() == ISD::SRA) {
12186 if (ShiftAmt == 7) {
12187 // R s>> 7 === R s< 0
12188 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12189 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12192 // R s>> a === ((R u>> a) ^ m) - m
12193 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12194 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
12196 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
12197 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12198 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12201 llvm_unreachable("Unknown shift opcode.");
12204 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
12205 if (Op.getOpcode() == ISD::SHL) {
12206 // Make a large shift.
12207 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
12208 DAG.getConstant(ShiftAmt, MVT::i32));
12209 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12210 // Zero out the rightmost bits.
12211 SmallVector<SDValue, 32> V(32,
12212 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12214 return DAG.getNode(ISD::AND, dl, VT, SHL,
12215 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12217 if (Op.getOpcode() == ISD::SRL) {
12218 // Make a large shift.
12219 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
12220 DAG.getConstant(ShiftAmt, MVT::i32));
12221 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12222 // Zero out the leftmost bits.
12223 SmallVector<SDValue, 32> V(32,
12224 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12226 return DAG.getNode(ISD::AND, dl, VT, SRL,
12227 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12229 if (Op.getOpcode() == ISD::SRA) {
12230 if (ShiftAmt == 7) {
12231 // R s>> 7 === R s< 0
12232 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12233 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12236 // R s>> a === ((R u>> a) ^ m) - m
12237 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12238 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
12240 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
12241 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12242 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12245 llvm_unreachable("Unknown shift opcode.");
12250 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
12251 if (!Subtarget->is64Bit() &&
12252 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
12253 Amt.getOpcode() == ISD::BITCAST &&
12254 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
12255 Amt = Amt.getOperand(0);
12256 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
12257 VT.getVectorNumElements();
12258 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
12259 uint64_t ShiftAmt = 0;
12260 for (unsigned i = 0; i != Ratio; ++i) {
12261 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
12265 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
12267 // Check remaining shift amounts.
12268 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
12269 uint64_t ShAmt = 0;
12270 for (unsigned j = 0; j != Ratio; ++j) {
12271 ConstantSDNode *C =
12272 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
12276 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
12278 if (ShAmt != ShiftAmt)
12281 switch (Op.getOpcode()) {
12283 llvm_unreachable("Unknown shift opcode!");
12285 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
12286 DAG.getConstant(ShiftAmt, MVT::i32));
12288 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
12289 DAG.getConstant(ShiftAmt, MVT::i32));
12291 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
12292 DAG.getConstant(ShiftAmt, MVT::i32));
12299 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
12300 const X86Subtarget* Subtarget) {
12301 EVT VT = Op.getValueType();
12303 SDValue R = Op.getOperand(0);
12304 SDValue Amt = Op.getOperand(1);
12306 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
12307 VT == MVT::v4i32 || VT == MVT::v8i16 ||
12308 (Subtarget->hasInt256() &&
12309 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
12310 VT == MVT::v8i32 || VT == MVT::v16i16))) {
12312 EVT EltVT = VT.getVectorElementType();
12314 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
12315 unsigned NumElts = VT.getVectorNumElements();
12317 for (i = 0; i != NumElts; ++i) {
12318 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
12322 for (j = i; j != NumElts; ++j) {
12323 SDValue Arg = Amt.getOperand(j);
12324 if (Arg.getOpcode() == ISD::UNDEF) continue;
12325 if (Arg != Amt.getOperand(i))
12328 if (i != NumElts && j == NumElts)
12329 BaseShAmt = Amt.getOperand(i);
12331 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
12332 Amt = Amt.getOperand(0);
12333 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
12334 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
12335 SDValue InVec = Amt.getOperand(0);
12336 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
12337 unsigned NumElts = InVec.getValueType().getVectorNumElements();
12339 for (; i != NumElts; ++i) {
12340 SDValue Arg = InVec.getOperand(i);
12341 if (Arg.getOpcode() == ISD::UNDEF) continue;
12345 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
12346 if (ConstantSDNode *C =
12347 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
12348 unsigned SplatIdx =
12349 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
12350 if (C->getZExtValue() == SplatIdx)
12351 BaseShAmt = InVec.getOperand(1);
12354 if (BaseShAmt.getNode() == 0)
12355 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
12356 DAG.getIntPtrConstant(0));
12360 if (BaseShAmt.getNode()) {
12361 if (EltVT.bitsGT(MVT::i32))
12362 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
12363 else if (EltVT.bitsLT(MVT::i32))
12364 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
12366 switch (Op.getOpcode()) {
12368 llvm_unreachable("Unknown shift opcode!");
12370 switch (VT.getSimpleVT().SimpleTy) {
12371 default: return SDValue();
12378 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
12381 switch (VT.getSimpleVT().SimpleTy) {
12382 default: return SDValue();
12387 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
12390 switch (VT.getSimpleVT().SimpleTy) {
12391 default: return SDValue();
12398 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
12404 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
12405 if (!Subtarget->is64Bit() &&
12406 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
12407 Amt.getOpcode() == ISD::BITCAST &&
12408 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
12409 Amt = Amt.getOperand(0);
12410 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
12411 VT.getVectorNumElements();
12412 std::vector<SDValue> Vals(Ratio);
12413 for (unsigned i = 0; i != Ratio; ++i)
12414 Vals[i] = Amt.getOperand(i);
12415 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
12416 for (unsigned j = 0; j != Ratio; ++j)
12417 if (Vals[j] != Amt.getOperand(i + j))
12420 switch (Op.getOpcode()) {
12422 llvm_unreachable("Unknown shift opcode!");
12424 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
12426 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
12428 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
12435 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
12437 EVT VT = Op.getValueType();
12439 SDValue R = Op.getOperand(0);
12440 SDValue Amt = Op.getOperand(1);
12443 if (!Subtarget->hasSSE2())
12446 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
12450 V = LowerScalarVariableShift(Op, DAG, Subtarget);
12454 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
12455 if (Subtarget->hasInt256()) {
12456 if (Op.getOpcode() == ISD::SRL &&
12457 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
12458 VT == MVT::v4i64 || VT == MVT::v8i32))
12460 if (Op.getOpcode() == ISD::SHL &&
12461 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
12462 VT == MVT::v4i64 || VT == MVT::v8i32))
12464 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
12468 // Lower SHL with variable shift amount.
12469 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
12470 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
12472 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
12473 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
12474 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
12475 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
12477 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
12478 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
12481 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
12482 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
12484 // Turn 'a' into a mask suitable for VSELECT
12485 SDValue VSelM = DAG.getConstant(0x80, VT);
12486 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12487 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12489 SDValue CM1 = DAG.getConstant(0x0f, VT);
12490 SDValue CM2 = DAG.getConstant(0x3f, VT);
12492 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
12493 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
12494 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
12495 DAG.getConstant(4, MVT::i32), DAG);
12496 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
12497 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
12500 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
12501 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12502 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12504 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
12505 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
12506 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
12507 DAG.getConstant(2, MVT::i32), DAG);
12508 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
12509 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
12512 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
12513 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12514 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12516 // return VSELECT(r, r+r, a);
12517 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
12518 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
12522 // Decompose 256-bit shifts into smaller 128-bit shifts.
12523 if (VT.is256BitVector()) {
12524 unsigned NumElems = VT.getVectorNumElements();
12525 MVT EltVT = VT.getVectorElementType().getSimpleVT();
12526 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12528 // Extract the two vectors
12529 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
12530 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
12532 // Recreate the shift amount vectors
12533 SDValue Amt1, Amt2;
12534 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
12535 // Constant shift amount
12536 SmallVector<SDValue, 4> Amt1Csts;
12537 SmallVector<SDValue, 4> Amt2Csts;
12538 for (unsigned i = 0; i != NumElems/2; ++i)
12539 Amt1Csts.push_back(Amt->getOperand(i));
12540 for (unsigned i = NumElems/2; i != NumElems; ++i)
12541 Amt2Csts.push_back(Amt->getOperand(i));
12543 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
12544 &Amt1Csts[0], NumElems/2);
12545 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
12546 &Amt2Csts[0], NumElems/2);
12548 // Variable shift amount
12549 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
12550 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
12553 // Issue new vector shifts for the smaller types
12554 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
12555 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
12557 // Concatenate the result back
12558 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
12564 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
12565 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
12566 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
12567 // looks for this combo and may remove the "setcc" instruction if the "setcc"
12568 // has only one use.
12569 SDNode *N = Op.getNode();
12570 SDValue LHS = N->getOperand(0);
12571 SDValue RHS = N->getOperand(1);
12572 unsigned BaseOp = 0;
12575 switch (Op.getOpcode()) {
12576 default: llvm_unreachable("Unknown ovf instruction!");
12578 // A subtract of one will be selected as a INC. Note that INC doesn't
12579 // set CF, so we can't do this for UADDO.
12580 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
12582 BaseOp = X86ISD::INC;
12583 Cond = X86::COND_O;
12586 BaseOp = X86ISD::ADD;
12587 Cond = X86::COND_O;
12590 BaseOp = X86ISD::ADD;
12591 Cond = X86::COND_B;
12594 // A subtract of one will be selected as a DEC. Note that DEC doesn't
12595 // set CF, so we can't do this for USUBO.
12596 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
12598 BaseOp = X86ISD::DEC;
12599 Cond = X86::COND_O;
12602 BaseOp = X86ISD::SUB;
12603 Cond = X86::COND_O;
12606 BaseOp = X86ISD::SUB;
12607 Cond = X86::COND_B;
12610 BaseOp = X86ISD::SMUL;
12611 Cond = X86::COND_O;
12613 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
12614 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
12616 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
12619 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12620 DAG.getConstant(X86::COND_O, MVT::i32),
12621 SDValue(Sum.getNode(), 2));
12623 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
12627 // Also sets EFLAGS.
12628 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
12629 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
12632 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
12633 DAG.getConstant(Cond, MVT::i32),
12634 SDValue(Sum.getNode(), 1));
12636 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
12639 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
12640 SelectionDAG &DAG) const {
12642 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
12643 EVT VT = Op.getValueType();
12645 if (!Subtarget->hasSSE2() || !VT.isVector())
12648 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
12649 ExtraVT.getScalarType().getSizeInBits();
12650 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
12652 switch (VT.getSimpleVT().SimpleTy) {
12653 default: return SDValue();
12656 if (!Subtarget->hasFp256())
12658 if (!Subtarget->hasInt256()) {
12659 // needs to be split
12660 unsigned NumElems = VT.getVectorNumElements();
12662 // Extract the LHS vectors
12663 SDValue LHS = Op.getOperand(0);
12664 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12665 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12667 MVT EltVT = VT.getVectorElementType().getSimpleVT();
12668 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12670 EVT ExtraEltVT = ExtraVT.getVectorElementType();
12671 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
12672 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
12674 SDValue Extra = DAG.getValueType(ExtraVT);
12676 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
12677 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
12679 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
12684 // (sext (vzext x)) -> (vsext x)
12685 SDValue Op0 = Op.getOperand(0);
12686 SDValue Op00 = Op0.getOperand(0);
12688 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
12689 if (Op0.getOpcode() == ISD::BITCAST &&
12690 Op00.getOpcode() == ISD::VECTOR_SHUFFLE)
12691 Tmp1 = LowerVectorIntExtend(Op00, DAG);
12692 if (Tmp1.getNode()) {
12693 SDValue Tmp1Op0 = Tmp1.getOperand(0);
12694 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
12695 "This optimization is invalid without a VZEXT.");
12696 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
12699 // If the above didn't work, then just use Shift-Left + Shift-Right.
12700 Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT, Op0, ShAmt, DAG);
12701 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
12706 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
12707 SelectionDAG &DAG) {
12709 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
12710 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
12711 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
12712 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
12714 // The only fence that needs an instruction is a sequentially-consistent
12715 // cross-thread fence.
12716 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
12717 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
12718 // no-sse2). There isn't any reason to disable it if the target processor
12720 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
12721 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
12723 SDValue Chain = Op.getOperand(0);
12724 SDValue Zero = DAG.getConstant(0, MVT::i32);
12726 DAG.getRegister(X86::ESP, MVT::i32), // Base
12727 DAG.getTargetConstant(1, MVT::i8), // Scale
12728 DAG.getRegister(0, MVT::i32), // Index
12729 DAG.getTargetConstant(0, MVT::i32), // Disp
12730 DAG.getRegister(0, MVT::i32), // Segment.
12734 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
12735 return SDValue(Res, 0);
12738 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
12739 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
12742 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
12743 SelectionDAG &DAG) {
12744 EVT T = Op.getValueType();
12748 switch(T.getSimpleVT().SimpleTy) {
12749 default: llvm_unreachable("Invalid value type!");
12750 case MVT::i8: Reg = X86::AL; size = 1; break;
12751 case MVT::i16: Reg = X86::AX; size = 2; break;
12752 case MVT::i32: Reg = X86::EAX; size = 4; break;
12754 assert(Subtarget->is64Bit() && "Node not type legal!");
12755 Reg = X86::RAX; size = 8;
12758 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
12759 Op.getOperand(2), SDValue());
12760 SDValue Ops[] = { cpIn.getValue(0),
12763 DAG.getTargetConstant(size, MVT::i8),
12764 cpIn.getValue(1) };
12765 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
12766 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
12767 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
12768 Ops, array_lengthof(Ops), T, MMO);
12770 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
12774 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
12775 SelectionDAG &DAG) {
12776 assert(Subtarget->is64Bit() && "Result not type legalized?");
12777 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
12778 SDValue TheChain = Op.getOperand(0);
12780 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
12781 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
12782 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
12784 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
12785 DAG.getConstant(32, MVT::i8));
12787 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
12790 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
12793 SDValue X86TargetLowering::LowerBITCAST(SDValue Op, SelectionDAG &DAG) const {
12794 EVT SrcVT = Op.getOperand(0).getValueType();
12795 EVT DstVT = Op.getValueType();
12796 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
12797 Subtarget->hasMMX() && "Unexpected custom BITCAST");
12798 assert((DstVT == MVT::i64 ||
12799 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
12800 "Unexpected custom BITCAST");
12801 // i64 <=> MMX conversions are Legal.
12802 if (SrcVT==MVT::i64 && DstVT.isVector())
12804 if (DstVT==MVT::i64 && SrcVT.isVector())
12806 // MMX <=> MMX conversions are Legal.
12807 if (SrcVT.isVector() && DstVT.isVector())
12809 // All other conversions need to be expanded.
12813 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
12814 SDNode *Node = Op.getNode();
12816 EVT T = Node->getValueType(0);
12817 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
12818 DAG.getConstant(0, T), Node->getOperand(2));
12819 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
12820 cast<AtomicSDNode>(Node)->getMemoryVT(),
12821 Node->getOperand(0),
12822 Node->getOperand(1), negOp,
12823 cast<AtomicSDNode>(Node)->getSrcValue(),
12824 cast<AtomicSDNode>(Node)->getAlignment(),
12825 cast<AtomicSDNode>(Node)->getOrdering(),
12826 cast<AtomicSDNode>(Node)->getSynchScope());
12829 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
12830 SDNode *Node = Op.getNode();
12832 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
12834 // Convert seq_cst store -> xchg
12835 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
12836 // FIXME: On 32-bit, store -> fist or movq would be more efficient
12837 // (The only way to get a 16-byte store is cmpxchg16b)
12838 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
12839 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
12840 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
12841 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
12842 cast<AtomicSDNode>(Node)->getMemoryVT(),
12843 Node->getOperand(0),
12844 Node->getOperand(1), Node->getOperand(2),
12845 cast<AtomicSDNode>(Node)->getMemOperand(),
12846 cast<AtomicSDNode>(Node)->getOrdering(),
12847 cast<AtomicSDNode>(Node)->getSynchScope());
12848 return Swap.getValue(1);
12850 // Other atomic stores have a simple pattern.
12854 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
12855 EVT VT = Op.getNode()->getValueType(0);
12857 // Let legalize expand this if it isn't a legal type yet.
12858 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
12861 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
12864 bool ExtraOp = false;
12865 switch (Op.getOpcode()) {
12866 default: llvm_unreachable("Invalid code");
12867 case ISD::ADDC: Opc = X86ISD::ADD; break;
12868 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
12869 case ISD::SUBC: Opc = X86ISD::SUB; break;
12870 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
12874 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
12876 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
12877 Op.getOperand(1), Op.getOperand(2));
12880 SDValue X86TargetLowering::LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const {
12881 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
12883 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
12884 // which returns the values as { float, float } (in XMM0) or
12885 // { double, double } (which is returned in XMM0, XMM1).
12887 SDValue Arg = Op.getOperand(0);
12888 EVT ArgVT = Arg.getValueType();
12889 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
12892 ArgListEntry Entry;
12896 Entry.isSExt = false;
12897 Entry.isZExt = false;
12898 Args.push_back(Entry);
12900 bool isF64 = ArgVT == MVT::f64;
12901 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
12902 // the small struct {f32, f32} is returned in (eax, edx). For f64,
12903 // the results are returned via SRet in memory.
12904 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
12905 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
12907 Type *RetTy = isF64
12908 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
12909 : (Type*)VectorType::get(ArgTy, 4);
12911 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy,
12912 false, false, false, false, 0,
12913 CallingConv::C, /*isTaillCall=*/false,
12914 /*doesNotRet=*/false, /*isReturnValueUsed*/true,
12915 Callee, Args, DAG, dl);
12916 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
12919 // Returned in xmm0 and xmm1.
12920 return CallResult.first;
12922 // Returned in bits 0:31 and 32:64 xmm0.
12923 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
12924 CallResult.first, DAG.getIntPtrConstant(0));
12925 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
12926 CallResult.first, DAG.getIntPtrConstant(1));
12927 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
12928 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
12931 /// LowerOperation - Provide custom lowering hooks for some operations.
12933 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
12934 switch (Op.getOpcode()) {
12935 default: llvm_unreachable("Should not custom lower this!");
12936 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
12937 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
12938 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG);
12939 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
12940 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
12941 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
12942 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
12943 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
12944 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
12945 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
12946 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
12947 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
12948 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
12949 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
12950 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
12951 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
12952 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
12953 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
12954 case ISD::SHL_PARTS:
12955 case ISD::SRA_PARTS:
12956 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
12957 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
12958 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
12959 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
12960 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, DAG);
12961 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
12962 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, DAG);
12963 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
12964 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
12965 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
12966 case ISD::FABS: return LowerFABS(Op, DAG);
12967 case ISD::FNEG: return LowerFNEG(Op, DAG);
12968 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
12969 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
12970 case ISD::SETCC: return LowerSETCC(Op, DAG);
12971 case ISD::SELECT: return LowerSELECT(Op, DAG);
12972 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
12973 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
12974 case ISD::VASTART: return LowerVASTART(Op, DAG);
12975 case ISD::VAARG: return LowerVAARG(Op, DAG);
12976 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
12977 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
12978 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
12979 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
12980 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
12981 case ISD::FRAME_TO_ARGS_OFFSET:
12982 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
12983 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
12984 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
12985 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
12986 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
12987 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
12988 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
12989 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
12990 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
12991 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
12992 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
12993 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
12996 case ISD::SHL: return LowerShift(Op, DAG);
13002 case ISD::UMULO: return LowerXALUO(Op, DAG);
13003 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
13004 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
13008 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
13009 case ISD::ADD: return LowerADD(Op, DAG);
13010 case ISD::SUB: return LowerSUB(Op, DAG);
13011 case ISD::SDIV: return LowerSDIV(Op, DAG);
13012 case ISD::FSINCOS: return LowerFSINCOS(Op, DAG);
13016 static void ReplaceATOMIC_LOAD(SDNode *Node,
13017 SmallVectorImpl<SDValue> &Results,
13018 SelectionDAG &DAG) {
13020 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13022 // Convert wide load -> cmpxchg8b/cmpxchg16b
13023 // FIXME: On 32-bit, load -> fild or movq would be more efficient
13024 // (The only way to get a 16-byte load is cmpxchg16b)
13025 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
13026 SDValue Zero = DAG.getConstant(0, VT);
13027 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
13028 Node->getOperand(0),
13029 Node->getOperand(1), Zero, Zero,
13030 cast<AtomicSDNode>(Node)->getMemOperand(),
13031 cast<AtomicSDNode>(Node)->getOrdering(),
13032 cast<AtomicSDNode>(Node)->getSynchScope());
13033 Results.push_back(Swap.getValue(0));
13034 Results.push_back(Swap.getValue(1));
13038 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
13039 SelectionDAG &DAG, unsigned NewOp) {
13041 assert (Node->getValueType(0) == MVT::i64 &&
13042 "Only know how to expand i64 atomics");
13044 SDValue Chain = Node->getOperand(0);
13045 SDValue In1 = Node->getOperand(1);
13046 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13047 Node->getOperand(2), DAG.getIntPtrConstant(0));
13048 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13049 Node->getOperand(2), DAG.getIntPtrConstant(1));
13050 SDValue Ops[] = { Chain, In1, In2L, In2H };
13051 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
13053 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, array_lengthof(Ops), MVT::i64,
13054 cast<MemSDNode>(Node)->getMemOperand());
13055 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
13056 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
13057 Results.push_back(Result.getValue(2));
13060 /// ReplaceNodeResults - Replace a node with an illegal result type
13061 /// with a new node built out of custom code.
13062 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
13063 SmallVectorImpl<SDValue>&Results,
13064 SelectionDAG &DAG) const {
13066 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13067 switch (N->getOpcode()) {
13069 llvm_unreachable("Do not know how to custom type legalize this operation!");
13070 case ISD::SIGN_EXTEND_INREG:
13075 // We don't want to expand or promote these.
13077 case ISD::FP_TO_SINT:
13078 case ISD::FP_TO_UINT: {
13079 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
13081 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
13084 std::pair<SDValue,SDValue> Vals =
13085 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
13086 SDValue FIST = Vals.first, StackSlot = Vals.second;
13087 if (FIST.getNode() != 0) {
13088 EVT VT = N->getValueType(0);
13089 // Return a load from the stack slot.
13090 if (StackSlot.getNode() != 0)
13091 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
13092 MachinePointerInfo(),
13093 false, false, false, 0));
13095 Results.push_back(FIST);
13099 case ISD::UINT_TO_FP: {
13100 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
13101 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
13102 N->getValueType(0) != MVT::v2f32)
13104 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
13106 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13108 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
13109 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
13110 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
13111 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
13112 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
13113 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
13116 case ISD::FP_ROUND: {
13117 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
13119 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
13120 Results.push_back(V);
13123 case ISD::READCYCLECOUNTER: {
13124 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13125 SDValue TheChain = N->getOperand(0);
13126 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13127 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
13129 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
13131 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
13132 SDValue Ops[] = { eax, edx };
13133 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops,
13134 array_lengthof(Ops)));
13135 Results.push_back(edx.getValue(1));
13138 case ISD::ATOMIC_CMP_SWAP: {
13139 EVT T = N->getValueType(0);
13140 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
13141 bool Regs64bit = T == MVT::i128;
13142 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
13143 SDValue cpInL, cpInH;
13144 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13145 DAG.getConstant(0, HalfT));
13146 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13147 DAG.getConstant(1, HalfT));
13148 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
13149 Regs64bit ? X86::RAX : X86::EAX,
13151 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
13152 Regs64bit ? X86::RDX : X86::EDX,
13153 cpInH, cpInL.getValue(1));
13154 SDValue swapInL, swapInH;
13155 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13156 DAG.getConstant(0, HalfT));
13157 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13158 DAG.getConstant(1, HalfT));
13159 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
13160 Regs64bit ? X86::RBX : X86::EBX,
13161 swapInL, cpInH.getValue(1));
13162 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
13163 Regs64bit ? X86::RCX : X86::ECX,
13164 swapInH, swapInL.getValue(1));
13165 SDValue Ops[] = { swapInH.getValue(0),
13167 swapInH.getValue(1) };
13168 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13169 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
13170 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
13171 X86ISD::LCMPXCHG8_DAG;
13172 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
13173 Ops, array_lengthof(Ops), T, MMO);
13174 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
13175 Regs64bit ? X86::RAX : X86::EAX,
13176 HalfT, Result.getValue(1));
13177 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
13178 Regs64bit ? X86::RDX : X86::EDX,
13179 HalfT, cpOutL.getValue(2));
13180 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
13181 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
13182 Results.push_back(cpOutH.getValue(1));
13185 case ISD::ATOMIC_LOAD_ADD:
13186 case ISD::ATOMIC_LOAD_AND:
13187 case ISD::ATOMIC_LOAD_NAND:
13188 case ISD::ATOMIC_LOAD_OR:
13189 case ISD::ATOMIC_LOAD_SUB:
13190 case ISD::ATOMIC_LOAD_XOR:
13191 case ISD::ATOMIC_LOAD_MAX:
13192 case ISD::ATOMIC_LOAD_MIN:
13193 case ISD::ATOMIC_LOAD_UMAX:
13194 case ISD::ATOMIC_LOAD_UMIN:
13195 case ISD::ATOMIC_SWAP: {
13197 switch (N->getOpcode()) {
13198 default: llvm_unreachable("Unexpected opcode");
13199 case ISD::ATOMIC_LOAD_ADD:
13200 Opc = X86ISD::ATOMADD64_DAG;
13202 case ISD::ATOMIC_LOAD_AND:
13203 Opc = X86ISD::ATOMAND64_DAG;
13205 case ISD::ATOMIC_LOAD_NAND:
13206 Opc = X86ISD::ATOMNAND64_DAG;
13208 case ISD::ATOMIC_LOAD_OR:
13209 Opc = X86ISD::ATOMOR64_DAG;
13211 case ISD::ATOMIC_LOAD_SUB:
13212 Opc = X86ISD::ATOMSUB64_DAG;
13214 case ISD::ATOMIC_LOAD_XOR:
13215 Opc = X86ISD::ATOMXOR64_DAG;
13217 case ISD::ATOMIC_LOAD_MAX:
13218 Opc = X86ISD::ATOMMAX64_DAG;
13220 case ISD::ATOMIC_LOAD_MIN:
13221 Opc = X86ISD::ATOMMIN64_DAG;
13223 case ISD::ATOMIC_LOAD_UMAX:
13224 Opc = X86ISD::ATOMUMAX64_DAG;
13226 case ISD::ATOMIC_LOAD_UMIN:
13227 Opc = X86ISD::ATOMUMIN64_DAG;
13229 case ISD::ATOMIC_SWAP:
13230 Opc = X86ISD::ATOMSWAP64_DAG;
13233 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc);
13236 case ISD::ATOMIC_LOAD:
13237 ReplaceATOMIC_LOAD(N, Results, DAG);
13241 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
13243 default: return NULL;
13244 case X86ISD::BSF: return "X86ISD::BSF";
13245 case X86ISD::BSR: return "X86ISD::BSR";
13246 case X86ISD::SHLD: return "X86ISD::SHLD";
13247 case X86ISD::SHRD: return "X86ISD::SHRD";
13248 case X86ISD::FAND: return "X86ISD::FAND";
13249 case X86ISD::FANDN: return "X86ISD::FANDN";
13250 case X86ISD::FOR: return "X86ISD::FOR";
13251 case X86ISD::FXOR: return "X86ISD::FXOR";
13252 case X86ISD::FSRL: return "X86ISD::FSRL";
13253 case X86ISD::FILD: return "X86ISD::FILD";
13254 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
13255 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
13256 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
13257 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
13258 case X86ISD::FLD: return "X86ISD::FLD";
13259 case X86ISD::FST: return "X86ISD::FST";
13260 case X86ISD::CALL: return "X86ISD::CALL";
13261 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
13262 case X86ISD::BT: return "X86ISD::BT";
13263 case X86ISD::CMP: return "X86ISD::CMP";
13264 case X86ISD::COMI: return "X86ISD::COMI";
13265 case X86ISD::UCOMI: return "X86ISD::UCOMI";
13266 case X86ISD::CMPM: return "X86ISD::CMPM";
13267 case X86ISD::CMPMU: return "X86ISD::CMPMU";
13268 case X86ISD::SETCC: return "X86ISD::SETCC";
13269 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
13270 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
13271 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
13272 case X86ISD::CMOV: return "X86ISD::CMOV";
13273 case X86ISD::BRCOND: return "X86ISD::BRCOND";
13274 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
13275 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
13276 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
13277 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
13278 case X86ISD::Wrapper: return "X86ISD::Wrapper";
13279 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
13280 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
13281 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
13282 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
13283 case X86ISD::PINSRB: return "X86ISD::PINSRB";
13284 case X86ISD::PINSRW: return "X86ISD::PINSRW";
13285 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
13286 case X86ISD::ANDNP: return "X86ISD::ANDNP";
13287 case X86ISD::PSIGN: return "X86ISD::PSIGN";
13288 case X86ISD::BLENDV: return "X86ISD::BLENDV";
13289 case X86ISD::BLENDI: return "X86ISD::BLENDI";
13290 case X86ISD::SUBUS: return "X86ISD::SUBUS";
13291 case X86ISD::HADD: return "X86ISD::HADD";
13292 case X86ISD::HSUB: return "X86ISD::HSUB";
13293 case X86ISD::FHADD: return "X86ISD::FHADD";
13294 case X86ISD::FHSUB: return "X86ISD::FHSUB";
13295 case X86ISD::UMAX: return "X86ISD::UMAX";
13296 case X86ISD::UMIN: return "X86ISD::UMIN";
13297 case X86ISD::SMAX: return "X86ISD::SMAX";
13298 case X86ISD::SMIN: return "X86ISD::SMIN";
13299 case X86ISD::FMAX: return "X86ISD::FMAX";
13300 case X86ISD::FMIN: return "X86ISD::FMIN";
13301 case X86ISD::FMAXC: return "X86ISD::FMAXC";
13302 case X86ISD::FMINC: return "X86ISD::FMINC";
13303 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
13304 case X86ISD::FRCP: return "X86ISD::FRCP";
13305 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
13306 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
13307 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
13308 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
13309 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
13310 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
13311 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
13312 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
13313 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
13314 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
13315 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
13316 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
13317 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
13318 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
13319 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
13320 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
13321 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
13322 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
13323 case X86ISD::VSEXT_MOVL: return "X86ISD::VSEXT_MOVL";
13324 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
13325 case X86ISD::VZEXT: return "X86ISD::VZEXT";
13326 case X86ISD::VSEXT: return "X86ISD::VSEXT";
13327 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
13328 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
13329 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
13330 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
13331 case X86ISD::VSHL: return "X86ISD::VSHL";
13332 case X86ISD::VSRL: return "X86ISD::VSRL";
13333 case X86ISD::VSRA: return "X86ISD::VSRA";
13334 case X86ISD::VSHLI: return "X86ISD::VSHLI";
13335 case X86ISD::VSRLI: return "X86ISD::VSRLI";
13336 case X86ISD::VSRAI: return "X86ISD::VSRAI";
13337 case X86ISD::CMPP: return "X86ISD::CMPP";
13338 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
13339 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
13340 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
13341 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
13342 case X86ISD::ADD: return "X86ISD::ADD";
13343 case X86ISD::SUB: return "X86ISD::SUB";
13344 case X86ISD::ADC: return "X86ISD::ADC";
13345 case X86ISD::SBB: return "X86ISD::SBB";
13346 case X86ISD::SMUL: return "X86ISD::SMUL";
13347 case X86ISD::UMUL: return "X86ISD::UMUL";
13348 case X86ISD::INC: return "X86ISD::INC";
13349 case X86ISD::DEC: return "X86ISD::DEC";
13350 case X86ISD::OR: return "X86ISD::OR";
13351 case X86ISD::XOR: return "X86ISD::XOR";
13352 case X86ISD::AND: return "X86ISD::AND";
13353 case X86ISD::BLSI: return "X86ISD::BLSI";
13354 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
13355 case X86ISD::BLSR: return "X86ISD::BLSR";
13356 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
13357 case X86ISD::PTEST: return "X86ISD::PTEST";
13358 case X86ISD::TESTP: return "X86ISD::TESTP";
13359 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
13360 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
13361 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
13362 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
13363 case X86ISD::SHUFP: return "X86ISD::SHUFP";
13364 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
13365 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
13366 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
13367 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
13368 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
13369 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
13370 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
13371 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
13372 case X86ISD::MOVSD: return "X86ISD::MOVSD";
13373 case X86ISD::MOVSS: return "X86ISD::MOVSS";
13374 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
13375 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
13376 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
13377 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
13378 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
13379 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
13380 case X86ISD::VPERMV: return "X86ISD::VPERMV";
13381 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
13382 case X86ISD::VPERMI: return "X86ISD::VPERMI";
13383 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
13384 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
13385 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
13386 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
13387 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
13388 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
13389 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
13390 case X86ISD::SAHF: return "X86ISD::SAHF";
13391 case X86ISD::RDRAND: return "X86ISD::RDRAND";
13392 case X86ISD::RDSEED: return "X86ISD::RDSEED";
13393 case X86ISD::FMADD: return "X86ISD::FMADD";
13394 case X86ISD::FMSUB: return "X86ISD::FMSUB";
13395 case X86ISD::FNMADD: return "X86ISD::FNMADD";
13396 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
13397 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
13398 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
13399 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
13400 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
13401 case X86ISD::XTEST: return "X86ISD::XTEST";
13405 // isLegalAddressingMode - Return true if the addressing mode represented
13406 // by AM is legal for this target, for a load/store of the specified type.
13407 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
13409 // X86 supports extremely general addressing modes.
13410 CodeModel::Model M = getTargetMachine().getCodeModel();
13411 Reloc::Model R = getTargetMachine().getRelocationModel();
13413 // X86 allows a sign-extended 32-bit immediate field as a displacement.
13414 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
13419 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
13421 // If a reference to this global requires an extra load, we can't fold it.
13422 if (isGlobalStubReference(GVFlags))
13425 // If BaseGV requires a register for the PIC base, we cannot also have a
13426 // BaseReg specified.
13427 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
13430 // If lower 4G is not available, then we must use rip-relative addressing.
13431 if ((M != CodeModel::Small || R != Reloc::Static) &&
13432 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
13436 switch (AM.Scale) {
13442 // These scales always work.
13447 // These scales are formed with basereg+scalereg. Only accept if there is
13452 default: // Other stuff never works.
13459 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
13460 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
13462 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
13463 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
13464 return NumBits1 > NumBits2;
13467 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
13468 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
13471 if (!isTypeLegal(EVT::getEVT(Ty1)))
13474 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
13476 // Assuming the caller doesn't have a zeroext or signext return parameter,
13477 // truncation all the way down to i1 is valid.
13481 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
13482 return isInt<32>(Imm);
13485 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
13486 // Can also use sub to handle negated immediates.
13487 return isInt<32>(Imm);
13490 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
13491 if (!VT1.isInteger() || !VT2.isInteger())
13493 unsigned NumBits1 = VT1.getSizeInBits();
13494 unsigned NumBits2 = VT2.getSizeInBits();
13495 return NumBits1 > NumBits2;
13498 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
13499 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
13500 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
13503 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
13504 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
13505 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
13508 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
13509 EVT VT1 = Val.getValueType();
13510 if (isZExtFree(VT1, VT2))
13513 if (Val.getOpcode() != ISD::LOAD)
13516 if (!VT1.isSimple() || !VT1.isInteger() ||
13517 !VT2.isSimple() || !VT2.isInteger())
13520 switch (VT1.getSimpleVT().SimpleTy) {
13525 // X86 has 8, 16, and 32-bit zero-extending loads.
13533 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
13534 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
13537 VT = VT.getScalarType();
13539 if (!VT.isSimple())
13542 switch (VT.getSimpleVT().SimpleTy) {
13553 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
13554 // i16 instructions are longer (0x66 prefix) and potentially slower.
13555 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
13558 /// isShuffleMaskLegal - Targets can use this to indicate that they only
13559 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
13560 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
13561 /// are assumed to be legal.
13563 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
13565 if (!VT.isSimple())
13568 MVT SVT = VT.getSimpleVT();
13570 // Very little shuffling can be done for 64-bit vectors right now.
13571 if (VT.getSizeInBits() == 64)
13574 // FIXME: pshufb, blends, shifts.
13575 return (SVT.getVectorNumElements() == 2 ||
13576 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
13577 isMOVLMask(M, SVT) ||
13578 isSHUFPMask(M, SVT, Subtarget->hasFp256()) ||
13579 isPSHUFDMask(M, SVT) ||
13580 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
13581 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
13582 isPALIGNRMask(M, SVT, Subtarget) ||
13583 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
13584 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
13585 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
13586 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()));
13590 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
13592 if (!VT.isSimple())
13595 MVT SVT = VT.getSimpleVT();
13596 unsigned NumElts = SVT.getVectorNumElements();
13597 // FIXME: This collection of masks seems suspect.
13600 if (NumElts == 4 && SVT.is128BitVector()) {
13601 return (isMOVLMask(Mask, SVT) ||
13602 isCommutedMOVLMask(Mask, SVT, true) ||
13603 isSHUFPMask(Mask, SVT, Subtarget->hasFp256()) ||
13604 isSHUFPMask(Mask, SVT, Subtarget->hasFp256(), /* Commuted */ true));
13609 //===----------------------------------------------------------------------===//
13610 // X86 Scheduler Hooks
13611 //===----------------------------------------------------------------------===//
13613 /// Utility function to emit xbegin specifying the start of an RTM region.
13614 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
13615 const TargetInstrInfo *TII) {
13616 DebugLoc DL = MI->getDebugLoc();
13618 const BasicBlock *BB = MBB->getBasicBlock();
13619 MachineFunction::iterator I = MBB;
13622 // For the v = xbegin(), we generate
13633 MachineBasicBlock *thisMBB = MBB;
13634 MachineFunction *MF = MBB->getParent();
13635 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
13636 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
13637 MF->insert(I, mainMBB);
13638 MF->insert(I, sinkMBB);
13640 // Transfer the remainder of BB and its successor edges to sinkMBB.
13641 sinkMBB->splice(sinkMBB->begin(), MBB,
13642 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
13643 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
13647 // # fallthrough to mainMBB
13648 // # abortion to sinkMBB
13649 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
13650 thisMBB->addSuccessor(mainMBB);
13651 thisMBB->addSuccessor(sinkMBB);
13655 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
13656 mainMBB->addSuccessor(sinkMBB);
13659 // EAX is live into the sinkMBB
13660 sinkMBB->addLiveIn(X86::EAX);
13661 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
13662 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
13665 MI->eraseFromParent();
13669 // Get CMPXCHG opcode for the specified data type.
13670 static unsigned getCmpXChgOpcode(EVT VT) {
13671 switch (VT.getSimpleVT().SimpleTy) {
13672 case MVT::i8: return X86::LCMPXCHG8;
13673 case MVT::i16: return X86::LCMPXCHG16;
13674 case MVT::i32: return X86::LCMPXCHG32;
13675 case MVT::i64: return X86::LCMPXCHG64;
13679 llvm_unreachable("Invalid operand size!");
13682 // Get LOAD opcode for the specified data type.
13683 static unsigned getLoadOpcode(EVT VT) {
13684 switch (VT.getSimpleVT().SimpleTy) {
13685 case MVT::i8: return X86::MOV8rm;
13686 case MVT::i16: return X86::MOV16rm;
13687 case MVT::i32: return X86::MOV32rm;
13688 case MVT::i64: return X86::MOV64rm;
13692 llvm_unreachable("Invalid operand size!");
13695 // Get opcode of the non-atomic one from the specified atomic instruction.
13696 static unsigned getNonAtomicOpcode(unsigned Opc) {
13698 case X86::ATOMAND8: return X86::AND8rr;
13699 case X86::ATOMAND16: return X86::AND16rr;
13700 case X86::ATOMAND32: return X86::AND32rr;
13701 case X86::ATOMAND64: return X86::AND64rr;
13702 case X86::ATOMOR8: return X86::OR8rr;
13703 case X86::ATOMOR16: return X86::OR16rr;
13704 case X86::ATOMOR32: return X86::OR32rr;
13705 case X86::ATOMOR64: return X86::OR64rr;
13706 case X86::ATOMXOR8: return X86::XOR8rr;
13707 case X86::ATOMXOR16: return X86::XOR16rr;
13708 case X86::ATOMXOR32: return X86::XOR32rr;
13709 case X86::ATOMXOR64: return X86::XOR64rr;
13711 llvm_unreachable("Unhandled atomic-load-op opcode!");
13714 // Get opcode of the non-atomic one from the specified atomic instruction with
13716 static unsigned getNonAtomicOpcodeWithExtraOpc(unsigned Opc,
13717 unsigned &ExtraOpc) {
13719 case X86::ATOMNAND8: ExtraOpc = X86::NOT8r; return X86::AND8rr;
13720 case X86::ATOMNAND16: ExtraOpc = X86::NOT16r; return X86::AND16rr;
13721 case X86::ATOMNAND32: ExtraOpc = X86::NOT32r; return X86::AND32rr;
13722 case X86::ATOMNAND64: ExtraOpc = X86::NOT64r; return X86::AND64rr;
13723 case X86::ATOMMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVL32rr;
13724 case X86::ATOMMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVL16rr;
13725 case X86::ATOMMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVL32rr;
13726 case X86::ATOMMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVL64rr;
13727 case X86::ATOMMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVG32rr;
13728 case X86::ATOMMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVG16rr;
13729 case X86::ATOMMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVG32rr;
13730 case X86::ATOMMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVG64rr;
13731 case X86::ATOMUMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVB32rr;
13732 case X86::ATOMUMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVB16rr;
13733 case X86::ATOMUMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVB32rr;
13734 case X86::ATOMUMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVB64rr;
13735 case X86::ATOMUMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVA32rr;
13736 case X86::ATOMUMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVA16rr;
13737 case X86::ATOMUMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVA32rr;
13738 case X86::ATOMUMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVA64rr;
13740 llvm_unreachable("Unhandled atomic-load-op opcode!");
13743 // Get opcode of the non-atomic one from the specified atomic instruction for
13744 // 64-bit data type on 32-bit target.
13745 static unsigned getNonAtomic6432Opcode(unsigned Opc, unsigned &HiOpc) {
13747 case X86::ATOMAND6432: HiOpc = X86::AND32rr; return X86::AND32rr;
13748 case X86::ATOMOR6432: HiOpc = X86::OR32rr; return X86::OR32rr;
13749 case X86::ATOMXOR6432: HiOpc = X86::XOR32rr; return X86::XOR32rr;
13750 case X86::ATOMADD6432: HiOpc = X86::ADC32rr; return X86::ADD32rr;
13751 case X86::ATOMSUB6432: HiOpc = X86::SBB32rr; return X86::SUB32rr;
13752 case X86::ATOMSWAP6432: HiOpc = X86::MOV32rr; return X86::MOV32rr;
13753 case X86::ATOMMAX6432: HiOpc = X86::SETLr; return X86::SETLr;
13754 case X86::ATOMMIN6432: HiOpc = X86::SETGr; return X86::SETGr;
13755 case X86::ATOMUMAX6432: HiOpc = X86::SETBr; return X86::SETBr;
13756 case X86::ATOMUMIN6432: HiOpc = X86::SETAr; return X86::SETAr;
13758 llvm_unreachable("Unhandled atomic-load-op opcode!");
13761 // Get opcode of the non-atomic one from the specified atomic instruction for
13762 // 64-bit data type on 32-bit target with extra opcode.
13763 static unsigned getNonAtomic6432OpcodeWithExtraOpc(unsigned Opc,
13765 unsigned &ExtraOpc) {
13767 case X86::ATOMNAND6432:
13768 ExtraOpc = X86::NOT32r;
13769 HiOpc = X86::AND32rr;
13770 return X86::AND32rr;
13772 llvm_unreachable("Unhandled atomic-load-op opcode!");
13775 // Get pseudo CMOV opcode from the specified data type.
13776 static unsigned getPseudoCMOVOpc(EVT VT) {
13777 switch (VT.getSimpleVT().SimpleTy) {
13778 case MVT::i8: return X86::CMOV_GR8;
13779 case MVT::i16: return X86::CMOV_GR16;
13780 case MVT::i32: return X86::CMOV_GR32;
13784 llvm_unreachable("Unknown CMOV opcode!");
13787 // EmitAtomicLoadArith - emit the code sequence for pseudo atomic instructions.
13788 // They will be translated into a spin-loop or compare-exchange loop from
13791 // dst = atomic-fetch-op MI.addr, MI.val
13797 // t1 = LOAD MI.addr
13799 // t4 = phi(t1, t3 / loop)
13800 // t2 = OP MI.val, t4
13802 // LCMPXCHG [MI.addr], t2, [EAX is implicitly used & defined]
13808 MachineBasicBlock *
13809 X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
13810 MachineBasicBlock *MBB) const {
13811 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13812 DebugLoc DL = MI->getDebugLoc();
13814 MachineFunction *MF = MBB->getParent();
13815 MachineRegisterInfo &MRI = MF->getRegInfo();
13817 const BasicBlock *BB = MBB->getBasicBlock();
13818 MachineFunction::iterator I = MBB;
13821 assert(MI->getNumOperands() <= X86::AddrNumOperands + 4 &&
13822 "Unexpected number of operands");
13824 assert(MI->hasOneMemOperand() &&
13825 "Expected atomic-load-op to have one memoperand");
13827 // Memory Reference
13828 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
13829 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
13831 unsigned DstReg, SrcReg;
13832 unsigned MemOpndSlot;
13834 unsigned CurOp = 0;
13836 DstReg = MI->getOperand(CurOp++).getReg();
13837 MemOpndSlot = CurOp;
13838 CurOp += X86::AddrNumOperands;
13839 SrcReg = MI->getOperand(CurOp++).getReg();
13841 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
13842 MVT::SimpleValueType VT = *RC->vt_begin();
13843 unsigned t1 = MRI.createVirtualRegister(RC);
13844 unsigned t2 = MRI.createVirtualRegister(RC);
13845 unsigned t3 = MRI.createVirtualRegister(RC);
13846 unsigned t4 = MRI.createVirtualRegister(RC);
13847 unsigned PhyReg = getX86SubSuperRegister(X86::EAX, VT);
13849 unsigned LCMPXCHGOpc = getCmpXChgOpcode(VT);
13850 unsigned LOADOpc = getLoadOpcode(VT);
13852 // For the atomic load-arith operator, we generate
13855 // t1 = LOAD [MI.addr]
13857 // t4 = phi(t1 / thisMBB, t3 / mainMBB)
13858 // t1 = OP MI.val, EAX
13860 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
13866 MachineBasicBlock *thisMBB = MBB;
13867 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
13868 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
13869 MF->insert(I, mainMBB);
13870 MF->insert(I, sinkMBB);
13872 MachineInstrBuilder MIB;
13874 // Transfer the remainder of BB and its successor edges to sinkMBB.
13875 sinkMBB->splice(sinkMBB->begin(), MBB,
13876 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
13877 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
13880 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1);
13881 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
13882 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
13884 NewMO.setIsKill(false);
13885 MIB.addOperand(NewMO);
13887 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
13888 unsigned flags = (*MMOI)->getFlags();
13889 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
13890 MachineMemOperand *MMO =
13891 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
13892 (*MMOI)->getSize(),
13893 (*MMOI)->getBaseAlignment(),
13894 (*MMOI)->getTBAAInfo(),
13895 (*MMOI)->getRanges());
13896 MIB.addMemOperand(MMO);
13899 thisMBB->addSuccessor(mainMBB);
13902 MachineBasicBlock *origMainMBB = mainMBB;
13905 MachineInstr *Phi = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4)
13906 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
13908 unsigned Opc = MI->getOpcode();
13911 llvm_unreachable("Unhandled atomic-load-op opcode!");
13912 case X86::ATOMAND8:
13913 case X86::ATOMAND16:
13914 case X86::ATOMAND32:
13915 case X86::ATOMAND64:
13917 case X86::ATOMOR16:
13918 case X86::ATOMOR32:
13919 case X86::ATOMOR64:
13920 case X86::ATOMXOR8:
13921 case X86::ATOMXOR16:
13922 case X86::ATOMXOR32:
13923 case X86::ATOMXOR64: {
13924 unsigned ARITHOpc = getNonAtomicOpcode(Opc);
13925 BuildMI(mainMBB, DL, TII->get(ARITHOpc), t2).addReg(SrcReg)
13929 case X86::ATOMNAND8:
13930 case X86::ATOMNAND16:
13931 case X86::ATOMNAND32:
13932 case X86::ATOMNAND64: {
13933 unsigned Tmp = MRI.createVirtualRegister(RC);
13935 unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc(Opc, NOTOpc);
13936 BuildMI(mainMBB, DL, TII->get(ANDOpc), Tmp).addReg(SrcReg)
13938 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2).addReg(Tmp);
13941 case X86::ATOMMAX8:
13942 case X86::ATOMMAX16:
13943 case X86::ATOMMAX32:
13944 case X86::ATOMMAX64:
13945 case X86::ATOMMIN8:
13946 case X86::ATOMMIN16:
13947 case X86::ATOMMIN32:
13948 case X86::ATOMMIN64:
13949 case X86::ATOMUMAX8:
13950 case X86::ATOMUMAX16:
13951 case X86::ATOMUMAX32:
13952 case X86::ATOMUMAX64:
13953 case X86::ATOMUMIN8:
13954 case X86::ATOMUMIN16:
13955 case X86::ATOMUMIN32:
13956 case X86::ATOMUMIN64: {
13958 unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc(Opc, CMPOpc);
13960 BuildMI(mainMBB, DL, TII->get(CMPOpc))
13964 if (Subtarget->hasCMov()) {
13965 if (VT != MVT::i8) {
13967 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t2)
13971 // Promote i8 to i32 to use CMOV32
13972 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
13973 const TargetRegisterClass *RC32 =
13974 TRI->getSubClassWithSubReg(getRegClassFor(MVT::i32), X86::sub_8bit);
13975 unsigned SrcReg32 = MRI.createVirtualRegister(RC32);
13976 unsigned AccReg32 = MRI.createVirtualRegister(RC32);
13977 unsigned Tmp = MRI.createVirtualRegister(RC32);
13979 unsigned Undef = MRI.createVirtualRegister(RC32);
13980 BuildMI(mainMBB, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Undef);
13982 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), SrcReg32)
13985 .addImm(X86::sub_8bit);
13986 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), AccReg32)
13989 .addImm(X86::sub_8bit);
13991 BuildMI(mainMBB, DL, TII->get(CMOVOpc), Tmp)
13995 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t2)
13996 .addReg(Tmp, 0, X86::sub_8bit);
13999 // Use pseudo select and lower them.
14000 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) &&
14001 "Invalid atomic-load-op transformation!");
14002 unsigned SelOpc = getPseudoCMOVOpc(VT);
14003 X86::CondCode CC = X86::getCondFromCMovOpc(CMOVOpc);
14004 assert(CC != X86::COND_INVALID && "Invalid atomic-load-op transformation!");
14005 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t2)
14006 .addReg(SrcReg).addReg(t4)
14008 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14009 // Replace the original PHI node as mainMBB is changed after CMOV
14011 BuildMI(*origMainMBB, Phi, DL, TII->get(X86::PHI), t4)
14012 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14013 Phi->eraseFromParent();
14019 // Copy PhyReg back from virtual register.
14020 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), PhyReg)
14023 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14024 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14025 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14027 NewMO.setIsKill(false);
14028 MIB.addOperand(NewMO);
14031 MIB.setMemRefs(MMOBegin, MMOEnd);
14033 // Copy PhyReg back to virtual register.
14034 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3)
14037 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14039 mainMBB->addSuccessor(origMainMBB);
14040 mainMBB->addSuccessor(sinkMBB);
14043 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14044 TII->get(TargetOpcode::COPY), DstReg)
14047 MI->eraseFromParent();
14051 // EmitAtomicLoadArith6432 - emit the code sequence for pseudo atomic
14052 // instructions. They will be translated into a spin-loop or compare-exchange
14056 // dst = atomic-fetch-op MI.addr, MI.val
14062 // t1L = LOAD [MI.addr + 0]
14063 // t1H = LOAD [MI.addr + 4]
14065 // t4L = phi(t1L, t3L / loop)
14066 // t4H = phi(t1H, t3H / loop)
14067 // t2L = OP MI.val.lo, t4L
14068 // t2H = OP MI.val.hi, t4H
14073 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14081 MachineBasicBlock *
14082 X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI,
14083 MachineBasicBlock *MBB) const {
14084 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14085 DebugLoc DL = MI->getDebugLoc();
14087 MachineFunction *MF = MBB->getParent();
14088 MachineRegisterInfo &MRI = MF->getRegInfo();
14090 const BasicBlock *BB = MBB->getBasicBlock();
14091 MachineFunction::iterator I = MBB;
14094 assert(MI->getNumOperands() <= X86::AddrNumOperands + 7 &&
14095 "Unexpected number of operands");
14097 assert(MI->hasOneMemOperand() &&
14098 "Expected atomic-load-op32 to have one memoperand");
14100 // Memory Reference
14101 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14102 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14104 unsigned DstLoReg, DstHiReg;
14105 unsigned SrcLoReg, SrcHiReg;
14106 unsigned MemOpndSlot;
14108 unsigned CurOp = 0;
14110 DstLoReg = MI->getOperand(CurOp++).getReg();
14111 DstHiReg = MI->getOperand(CurOp++).getReg();
14112 MemOpndSlot = CurOp;
14113 CurOp += X86::AddrNumOperands;
14114 SrcLoReg = MI->getOperand(CurOp++).getReg();
14115 SrcHiReg = MI->getOperand(CurOp++).getReg();
14117 const TargetRegisterClass *RC = &X86::GR32RegClass;
14118 const TargetRegisterClass *RC8 = &X86::GR8RegClass;
14120 unsigned t1L = MRI.createVirtualRegister(RC);
14121 unsigned t1H = MRI.createVirtualRegister(RC);
14122 unsigned t2L = MRI.createVirtualRegister(RC);
14123 unsigned t2H = MRI.createVirtualRegister(RC);
14124 unsigned t3L = MRI.createVirtualRegister(RC);
14125 unsigned t3H = MRI.createVirtualRegister(RC);
14126 unsigned t4L = MRI.createVirtualRegister(RC);
14127 unsigned t4H = MRI.createVirtualRegister(RC);
14129 unsigned LCMPXCHGOpc = X86::LCMPXCHG8B;
14130 unsigned LOADOpc = X86::MOV32rm;
14132 // For the atomic load-arith operator, we generate
14135 // t1L = LOAD [MI.addr + 0]
14136 // t1H = LOAD [MI.addr + 4]
14138 // t4L = phi(t1L / thisMBB, t3L / mainMBB)
14139 // t4H = phi(t1H / thisMBB, t3H / mainMBB)
14140 // t2L = OP MI.val.lo, t4L
14141 // t2H = OP MI.val.hi, t4H
14144 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14152 MachineBasicBlock *thisMBB = MBB;
14153 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14154 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14155 MF->insert(I, mainMBB);
14156 MF->insert(I, sinkMBB);
14158 MachineInstrBuilder MIB;
14160 // Transfer the remainder of BB and its successor edges to sinkMBB.
14161 sinkMBB->splice(sinkMBB->begin(), MBB,
14162 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14163 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14167 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1L);
14168 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14169 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14171 NewMO.setIsKill(false);
14172 MIB.addOperand(NewMO);
14174 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14175 unsigned flags = (*MMOI)->getFlags();
14176 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14177 MachineMemOperand *MMO =
14178 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14179 (*MMOI)->getSize(),
14180 (*MMOI)->getBaseAlignment(),
14181 (*MMOI)->getTBAAInfo(),
14182 (*MMOI)->getRanges());
14183 MIB.addMemOperand(MMO);
14185 MachineInstr *LowMI = MIB;
14188 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1H);
14189 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14190 if (i == X86::AddrDisp) {
14191 MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32)
14193 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14195 NewMO.setIsKill(false);
14196 MIB.addOperand(NewMO);
14199 MIB.setMemRefs(LowMI->memoperands_begin(), LowMI->memoperands_end());
14201 thisMBB->addSuccessor(mainMBB);
14204 MachineBasicBlock *origMainMBB = mainMBB;
14207 MachineInstr *PhiL = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4L)
14208 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14209 MachineInstr *PhiH = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4H)
14210 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
14212 unsigned Opc = MI->getOpcode();
14215 llvm_unreachable("Unhandled atomic-load-op6432 opcode!");
14216 case X86::ATOMAND6432:
14217 case X86::ATOMOR6432:
14218 case X86::ATOMXOR6432:
14219 case X86::ATOMADD6432:
14220 case X86::ATOMSUB6432: {
14222 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14223 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(t4L)
14225 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(t4H)
14229 case X86::ATOMNAND6432: {
14230 unsigned HiOpc, NOTOpc;
14231 unsigned LoOpc = getNonAtomic6432OpcodeWithExtraOpc(Opc, HiOpc, NOTOpc);
14232 unsigned TmpL = MRI.createVirtualRegister(RC);
14233 unsigned TmpH = MRI.createVirtualRegister(RC);
14234 BuildMI(mainMBB, DL, TII->get(LoOpc), TmpL).addReg(SrcLoReg)
14236 BuildMI(mainMBB, DL, TII->get(HiOpc), TmpH).addReg(SrcHiReg)
14238 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2L).addReg(TmpL);
14239 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2H).addReg(TmpH);
14242 case X86::ATOMMAX6432:
14243 case X86::ATOMMIN6432:
14244 case X86::ATOMUMAX6432:
14245 case X86::ATOMUMIN6432: {
14247 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14248 unsigned cL = MRI.createVirtualRegister(RC8);
14249 unsigned cH = MRI.createVirtualRegister(RC8);
14250 unsigned cL32 = MRI.createVirtualRegister(RC);
14251 unsigned cH32 = MRI.createVirtualRegister(RC);
14252 unsigned cc = MRI.createVirtualRegister(RC);
14253 // cl := cmp src_lo, lo
14254 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14255 .addReg(SrcLoReg).addReg(t4L);
14256 BuildMI(mainMBB, DL, TII->get(LoOpc), cL);
14257 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cL32).addReg(cL);
14258 // ch := cmp src_hi, hi
14259 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14260 .addReg(SrcHiReg).addReg(t4H);
14261 BuildMI(mainMBB, DL, TII->get(HiOpc), cH);
14262 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cH32).addReg(cH);
14263 // cc := if (src_hi == hi) ? cl : ch;
14264 if (Subtarget->hasCMov()) {
14265 BuildMI(mainMBB, DL, TII->get(X86::CMOVE32rr), cc)
14266 .addReg(cH32).addReg(cL32);
14268 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), cc)
14269 .addReg(cH32).addReg(cL32)
14270 .addImm(X86::COND_E);
14271 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14273 BuildMI(mainMBB, DL, TII->get(X86::TEST32rr)).addReg(cc).addReg(cc);
14274 if (Subtarget->hasCMov()) {
14275 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2L)
14276 .addReg(SrcLoReg).addReg(t4L);
14277 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2H)
14278 .addReg(SrcHiReg).addReg(t4H);
14280 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2L)
14281 .addReg(SrcLoReg).addReg(t4L)
14282 .addImm(X86::COND_NE);
14283 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14284 // As the lowered CMOV won't clobber EFLAGS, we could reuse it for the
14285 // 2nd CMOV lowering.
14286 mainMBB->addLiveIn(X86::EFLAGS);
14287 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2H)
14288 .addReg(SrcHiReg).addReg(t4H)
14289 .addImm(X86::COND_NE);
14290 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14291 // Replace the original PHI node as mainMBB is changed after CMOV
14293 BuildMI(*origMainMBB, PhiL, DL, TII->get(X86::PHI), t4L)
14294 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14295 BuildMI(*origMainMBB, PhiH, DL, TII->get(X86::PHI), t4H)
14296 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
14297 PhiL->eraseFromParent();
14298 PhiH->eraseFromParent();
14302 case X86::ATOMSWAP6432: {
14304 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14305 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(SrcLoReg);
14306 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(SrcHiReg);
14311 // Copy EDX:EAX back from HiReg:LoReg
14312 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(t4L);
14313 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(t4H);
14314 // Copy ECX:EBX from t1H:t1L
14315 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t2L);
14316 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t2H);
14318 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14319 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14320 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14322 NewMO.setIsKill(false);
14323 MIB.addOperand(NewMO);
14325 MIB.setMemRefs(MMOBegin, MMOEnd);
14327 // Copy EDX:EAX back to t3H:t3L
14328 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3L).addReg(X86::EAX);
14329 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3H).addReg(X86::EDX);
14331 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14333 mainMBB->addSuccessor(origMainMBB);
14334 mainMBB->addSuccessor(sinkMBB);
14337 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14338 TII->get(TargetOpcode::COPY), DstLoReg)
14340 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14341 TII->get(TargetOpcode::COPY), DstHiReg)
14344 MI->eraseFromParent();
14348 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
14349 // or XMM0_V32I8 in AVX all of this code can be replaced with that
14350 // in the .td file.
14351 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
14352 const TargetInstrInfo *TII) {
14354 switch (MI->getOpcode()) {
14355 default: llvm_unreachable("illegal opcode!");
14356 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
14357 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
14358 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
14359 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
14360 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
14361 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
14362 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
14363 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
14366 DebugLoc dl = MI->getDebugLoc();
14367 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
14369 unsigned NumArgs = MI->getNumOperands();
14370 for (unsigned i = 1; i < NumArgs; ++i) {
14371 MachineOperand &Op = MI->getOperand(i);
14372 if (!(Op.isReg() && Op.isImplicit()))
14373 MIB.addOperand(Op);
14375 if (MI->hasOneMemOperand())
14376 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
14378 BuildMI(*BB, MI, dl,
14379 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14380 .addReg(X86::XMM0);
14382 MI->eraseFromParent();
14386 // FIXME: Custom handling because TableGen doesn't support multiple implicit
14387 // defs in an instruction pattern
14388 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
14389 const TargetInstrInfo *TII) {
14391 switch (MI->getOpcode()) {
14392 default: llvm_unreachable("illegal opcode!");
14393 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
14394 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
14395 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
14396 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
14397 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
14398 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
14399 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
14400 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
14403 DebugLoc dl = MI->getDebugLoc();
14404 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
14406 unsigned NumArgs = MI->getNumOperands(); // remove the results
14407 for (unsigned i = 1; i < NumArgs; ++i) {
14408 MachineOperand &Op = MI->getOperand(i);
14409 if (!(Op.isReg() && Op.isImplicit()))
14410 MIB.addOperand(Op);
14412 if (MI->hasOneMemOperand())
14413 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
14415 BuildMI(*BB, MI, dl,
14416 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14419 MI->eraseFromParent();
14423 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
14424 const TargetInstrInfo *TII,
14425 const X86Subtarget* Subtarget) {
14426 DebugLoc dl = MI->getDebugLoc();
14428 // Address into RAX/EAX, other two args into ECX, EDX.
14429 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
14430 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
14431 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
14432 for (int i = 0; i < X86::AddrNumOperands; ++i)
14433 MIB.addOperand(MI->getOperand(i));
14435 unsigned ValOps = X86::AddrNumOperands;
14436 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
14437 .addReg(MI->getOperand(ValOps).getReg());
14438 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
14439 .addReg(MI->getOperand(ValOps+1).getReg());
14441 // The instruction doesn't actually take any operands though.
14442 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
14444 MI->eraseFromParent(); // The pseudo is gone now.
14448 MachineBasicBlock *
14449 X86TargetLowering::EmitVAARG64WithCustomInserter(
14451 MachineBasicBlock *MBB) const {
14452 // Emit va_arg instruction on X86-64.
14454 // Operands to this pseudo-instruction:
14455 // 0 ) Output : destination address (reg)
14456 // 1-5) Input : va_list address (addr, i64mem)
14457 // 6 ) ArgSize : Size (in bytes) of vararg type
14458 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
14459 // 8 ) Align : Alignment of type
14460 // 9 ) EFLAGS (implicit-def)
14462 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
14463 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
14465 unsigned DestReg = MI->getOperand(0).getReg();
14466 MachineOperand &Base = MI->getOperand(1);
14467 MachineOperand &Scale = MI->getOperand(2);
14468 MachineOperand &Index = MI->getOperand(3);
14469 MachineOperand &Disp = MI->getOperand(4);
14470 MachineOperand &Segment = MI->getOperand(5);
14471 unsigned ArgSize = MI->getOperand(6).getImm();
14472 unsigned ArgMode = MI->getOperand(7).getImm();
14473 unsigned Align = MI->getOperand(8).getImm();
14475 // Memory Reference
14476 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
14477 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14478 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14480 // Machine Information
14481 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14482 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
14483 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
14484 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
14485 DebugLoc DL = MI->getDebugLoc();
14487 // struct va_list {
14490 // i64 overflow_area (address)
14491 // i64 reg_save_area (address)
14493 // sizeof(va_list) = 24
14494 // alignment(va_list) = 8
14496 unsigned TotalNumIntRegs = 6;
14497 unsigned TotalNumXMMRegs = 8;
14498 bool UseGPOffset = (ArgMode == 1);
14499 bool UseFPOffset = (ArgMode == 2);
14500 unsigned MaxOffset = TotalNumIntRegs * 8 +
14501 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
14503 /* Align ArgSize to a multiple of 8 */
14504 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
14505 bool NeedsAlign = (Align > 8);
14507 MachineBasicBlock *thisMBB = MBB;
14508 MachineBasicBlock *overflowMBB;
14509 MachineBasicBlock *offsetMBB;
14510 MachineBasicBlock *endMBB;
14512 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
14513 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
14514 unsigned OffsetReg = 0;
14516 if (!UseGPOffset && !UseFPOffset) {
14517 // If we only pull from the overflow region, we don't create a branch.
14518 // We don't need to alter control flow.
14519 OffsetDestReg = 0; // unused
14520 OverflowDestReg = DestReg;
14523 overflowMBB = thisMBB;
14526 // First emit code to check if gp_offset (or fp_offset) is below the bound.
14527 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
14528 // If not, pull from overflow_area. (branch to overflowMBB)
14533 // offsetMBB overflowMBB
14538 // Registers for the PHI in endMBB
14539 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
14540 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
14542 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
14543 MachineFunction *MF = MBB->getParent();
14544 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14545 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14546 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14548 MachineFunction::iterator MBBIter = MBB;
14551 // Insert the new basic blocks
14552 MF->insert(MBBIter, offsetMBB);
14553 MF->insert(MBBIter, overflowMBB);
14554 MF->insert(MBBIter, endMBB);
14556 // Transfer the remainder of MBB and its successor edges to endMBB.
14557 endMBB->splice(endMBB->begin(), thisMBB,
14558 llvm::next(MachineBasicBlock::iterator(MI)),
14560 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
14562 // Make offsetMBB and overflowMBB successors of thisMBB
14563 thisMBB->addSuccessor(offsetMBB);
14564 thisMBB->addSuccessor(overflowMBB);
14566 // endMBB is a successor of both offsetMBB and overflowMBB
14567 offsetMBB->addSuccessor(endMBB);
14568 overflowMBB->addSuccessor(endMBB);
14570 // Load the offset value into a register
14571 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
14572 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
14576 .addDisp(Disp, UseFPOffset ? 4 : 0)
14577 .addOperand(Segment)
14578 .setMemRefs(MMOBegin, MMOEnd);
14580 // Check if there is enough room left to pull this argument.
14581 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
14583 .addImm(MaxOffset + 8 - ArgSizeA8);
14585 // Branch to "overflowMBB" if offset >= max
14586 // Fall through to "offsetMBB" otherwise
14587 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
14588 .addMBB(overflowMBB);
14591 // In offsetMBB, emit code to use the reg_save_area.
14593 assert(OffsetReg != 0);
14595 // Read the reg_save_area address.
14596 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
14597 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
14602 .addOperand(Segment)
14603 .setMemRefs(MMOBegin, MMOEnd);
14605 // Zero-extend the offset
14606 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
14607 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
14610 .addImm(X86::sub_32bit);
14612 // Add the offset to the reg_save_area to get the final address.
14613 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
14614 .addReg(OffsetReg64)
14615 .addReg(RegSaveReg);
14617 // Compute the offset for the next argument
14618 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
14619 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
14621 .addImm(UseFPOffset ? 16 : 8);
14623 // Store it back into the va_list.
14624 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
14628 .addDisp(Disp, UseFPOffset ? 4 : 0)
14629 .addOperand(Segment)
14630 .addReg(NextOffsetReg)
14631 .setMemRefs(MMOBegin, MMOEnd);
14634 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
14639 // Emit code to use overflow area
14642 // Load the overflow_area address into a register.
14643 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
14644 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
14649 .addOperand(Segment)
14650 .setMemRefs(MMOBegin, MMOEnd);
14652 // If we need to align it, do so. Otherwise, just copy the address
14653 // to OverflowDestReg.
14655 // Align the overflow address
14656 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
14657 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
14659 // aligned_addr = (addr + (align-1)) & ~(align-1)
14660 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
14661 .addReg(OverflowAddrReg)
14664 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
14666 .addImm(~(uint64_t)(Align-1));
14668 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
14669 .addReg(OverflowAddrReg);
14672 // Compute the next overflow address after this argument.
14673 // (the overflow address should be kept 8-byte aligned)
14674 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
14675 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
14676 .addReg(OverflowDestReg)
14677 .addImm(ArgSizeA8);
14679 // Store the new overflow address.
14680 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
14685 .addOperand(Segment)
14686 .addReg(NextAddrReg)
14687 .setMemRefs(MMOBegin, MMOEnd);
14689 // If we branched, emit the PHI to the front of endMBB.
14691 BuildMI(*endMBB, endMBB->begin(), DL,
14692 TII->get(X86::PHI), DestReg)
14693 .addReg(OffsetDestReg).addMBB(offsetMBB)
14694 .addReg(OverflowDestReg).addMBB(overflowMBB);
14697 // Erase the pseudo instruction
14698 MI->eraseFromParent();
14703 MachineBasicBlock *
14704 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
14706 MachineBasicBlock *MBB) const {
14707 // Emit code to save XMM registers to the stack. The ABI says that the
14708 // number of registers to save is given in %al, so it's theoretically
14709 // possible to do an indirect jump trick to avoid saving all of them,
14710 // however this code takes a simpler approach and just executes all
14711 // of the stores if %al is non-zero. It's less code, and it's probably
14712 // easier on the hardware branch predictor, and stores aren't all that
14713 // expensive anyway.
14715 // Create the new basic blocks. One block contains all the XMM stores,
14716 // and one block is the final destination regardless of whether any
14717 // stores were performed.
14718 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
14719 MachineFunction *F = MBB->getParent();
14720 MachineFunction::iterator MBBIter = MBB;
14722 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
14723 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
14724 F->insert(MBBIter, XMMSaveMBB);
14725 F->insert(MBBIter, EndMBB);
14727 // Transfer the remainder of MBB and its successor edges to EndMBB.
14728 EndMBB->splice(EndMBB->begin(), MBB,
14729 llvm::next(MachineBasicBlock::iterator(MI)),
14731 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
14733 // The original block will now fall through to the XMM save block.
14734 MBB->addSuccessor(XMMSaveMBB);
14735 // The XMMSaveMBB will fall through to the end block.
14736 XMMSaveMBB->addSuccessor(EndMBB);
14738 // Now add the instructions.
14739 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14740 DebugLoc DL = MI->getDebugLoc();
14742 unsigned CountReg = MI->getOperand(0).getReg();
14743 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
14744 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
14746 if (!Subtarget->isTargetWin64()) {
14747 // If %al is 0, branch around the XMM save block.
14748 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
14749 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
14750 MBB->addSuccessor(EndMBB);
14753 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
14754 // In the XMM save block, save all the XMM argument registers.
14755 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
14756 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
14757 MachineMemOperand *MMO =
14758 F->getMachineMemOperand(
14759 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
14760 MachineMemOperand::MOStore,
14761 /*Size=*/16, /*Align=*/16);
14762 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
14763 .addFrameIndex(RegSaveFrameIndex)
14764 .addImm(/*Scale=*/1)
14765 .addReg(/*IndexReg=*/0)
14766 .addImm(/*Disp=*/Offset)
14767 .addReg(/*Segment=*/0)
14768 .addReg(MI->getOperand(i).getReg())
14769 .addMemOperand(MMO);
14772 MI->eraseFromParent(); // The pseudo instruction is gone now.
14777 // The EFLAGS operand of SelectItr might be missing a kill marker
14778 // because there were multiple uses of EFLAGS, and ISel didn't know
14779 // which to mark. Figure out whether SelectItr should have had a
14780 // kill marker, and set it if it should. Returns the correct kill
14782 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
14783 MachineBasicBlock* BB,
14784 const TargetRegisterInfo* TRI) {
14785 // Scan forward through BB for a use/def of EFLAGS.
14786 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
14787 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
14788 const MachineInstr& mi = *miI;
14789 if (mi.readsRegister(X86::EFLAGS))
14791 if (mi.definesRegister(X86::EFLAGS))
14792 break; // Should have kill-flag - update below.
14795 // If we hit the end of the block, check whether EFLAGS is live into a
14797 if (miI == BB->end()) {
14798 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
14799 sEnd = BB->succ_end();
14800 sItr != sEnd; ++sItr) {
14801 MachineBasicBlock* succ = *sItr;
14802 if (succ->isLiveIn(X86::EFLAGS))
14807 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
14808 // out. SelectMI should have a kill flag on EFLAGS.
14809 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
14813 MachineBasicBlock *
14814 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
14815 MachineBasicBlock *BB) const {
14816 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14817 DebugLoc DL = MI->getDebugLoc();
14819 // To "insert" a SELECT_CC instruction, we actually have to insert the
14820 // diamond control-flow pattern. The incoming instruction knows the
14821 // destination vreg to set, the condition code register to branch on, the
14822 // true/false values to select between, and a branch opcode to use.
14823 const BasicBlock *LLVM_BB = BB->getBasicBlock();
14824 MachineFunction::iterator It = BB;
14830 // cmpTY ccX, r1, r2
14832 // fallthrough --> copy0MBB
14833 MachineBasicBlock *thisMBB = BB;
14834 MachineFunction *F = BB->getParent();
14835 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
14836 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
14837 F->insert(It, copy0MBB);
14838 F->insert(It, sinkMBB);
14840 // If the EFLAGS register isn't dead in the terminator, then claim that it's
14841 // live into the sink and copy blocks.
14842 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
14843 if (!MI->killsRegister(X86::EFLAGS) &&
14844 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
14845 copy0MBB->addLiveIn(X86::EFLAGS);
14846 sinkMBB->addLiveIn(X86::EFLAGS);
14849 // Transfer the remainder of BB and its successor edges to sinkMBB.
14850 sinkMBB->splice(sinkMBB->begin(), BB,
14851 llvm::next(MachineBasicBlock::iterator(MI)),
14853 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
14855 // Add the true and fallthrough blocks as its successors.
14856 BB->addSuccessor(copy0MBB);
14857 BB->addSuccessor(sinkMBB);
14859 // Create the conditional branch instruction.
14861 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
14862 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
14865 // %FalseValue = ...
14866 // # fallthrough to sinkMBB
14867 copy0MBB->addSuccessor(sinkMBB);
14870 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
14872 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14873 TII->get(X86::PHI), MI->getOperand(0).getReg())
14874 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
14875 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
14877 MI->eraseFromParent(); // The pseudo instruction is gone now.
14881 MachineBasicBlock *
14882 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
14883 bool Is64Bit) const {
14884 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14885 DebugLoc DL = MI->getDebugLoc();
14886 MachineFunction *MF = BB->getParent();
14887 const BasicBlock *LLVM_BB = BB->getBasicBlock();
14889 assert(getTargetMachine().Options.EnableSegmentedStacks);
14891 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
14892 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
14895 // ... [Till the alloca]
14896 // If stacklet is not large enough, jump to mallocMBB
14899 // Allocate by subtracting from RSP
14900 // Jump to continueMBB
14903 // Allocate by call to runtime
14907 // [rest of original BB]
14910 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14911 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14912 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14914 MachineRegisterInfo &MRI = MF->getRegInfo();
14915 const TargetRegisterClass *AddrRegClass =
14916 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
14918 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
14919 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
14920 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
14921 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
14922 sizeVReg = MI->getOperand(1).getReg(),
14923 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
14925 MachineFunction::iterator MBBIter = BB;
14928 MF->insert(MBBIter, bumpMBB);
14929 MF->insert(MBBIter, mallocMBB);
14930 MF->insert(MBBIter, continueMBB);
14932 continueMBB->splice(continueMBB->begin(), BB, llvm::next
14933 (MachineBasicBlock::iterator(MI)), BB->end());
14934 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
14936 // Add code to the main basic block to check if the stack limit has been hit,
14937 // and if so, jump to mallocMBB otherwise to bumpMBB.
14938 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
14939 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
14940 .addReg(tmpSPVReg).addReg(sizeVReg);
14941 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
14942 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
14943 .addReg(SPLimitVReg);
14944 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
14946 // bumpMBB simply decreases the stack pointer, since we know the current
14947 // stacklet has enough space.
14948 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
14949 .addReg(SPLimitVReg);
14950 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
14951 .addReg(SPLimitVReg);
14952 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
14954 // Calls into a routine in libgcc to allocate more space from the heap.
14955 const uint32_t *RegMask =
14956 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
14958 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
14960 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
14961 .addExternalSymbol("__morestack_allocate_stack_space")
14962 .addRegMask(RegMask)
14963 .addReg(X86::RDI, RegState::Implicit)
14964 .addReg(X86::RAX, RegState::ImplicitDefine);
14966 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
14968 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
14969 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
14970 .addExternalSymbol("__morestack_allocate_stack_space")
14971 .addRegMask(RegMask)
14972 .addReg(X86::EAX, RegState::ImplicitDefine);
14976 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
14979 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
14980 .addReg(Is64Bit ? X86::RAX : X86::EAX);
14981 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
14983 // Set up the CFG correctly.
14984 BB->addSuccessor(bumpMBB);
14985 BB->addSuccessor(mallocMBB);
14986 mallocMBB->addSuccessor(continueMBB);
14987 bumpMBB->addSuccessor(continueMBB);
14989 // Take care of the PHI nodes.
14990 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
14991 MI->getOperand(0).getReg())
14992 .addReg(mallocPtrVReg).addMBB(mallocMBB)
14993 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
14995 // Delete the original pseudo instruction.
14996 MI->eraseFromParent();
14999 return continueMBB;
15002 MachineBasicBlock *
15003 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
15004 MachineBasicBlock *BB) const {
15005 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15006 DebugLoc DL = MI->getDebugLoc();
15008 assert(!Subtarget->isTargetEnvMacho());
15010 // The lowering is pretty easy: we're just emitting the call to _alloca. The
15011 // non-trivial part is impdef of ESP.
15013 if (Subtarget->isTargetWin64()) {
15014 if (Subtarget->isTargetCygMing()) {
15015 // ___chkstk(Mingw64):
15016 // Clobbers R10, R11, RAX and EFLAGS.
15018 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15019 .addExternalSymbol("___chkstk")
15020 .addReg(X86::RAX, RegState::Implicit)
15021 .addReg(X86::RSP, RegState::Implicit)
15022 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
15023 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
15024 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15026 // __chkstk(MSVCRT): does not update stack pointer.
15027 // Clobbers R10, R11 and EFLAGS.
15028 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15029 .addExternalSymbol("__chkstk")
15030 .addReg(X86::RAX, RegState::Implicit)
15031 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15032 // RAX has the offset to be subtracted from RSP.
15033 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
15038 const char *StackProbeSymbol =
15039 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
15041 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
15042 .addExternalSymbol(StackProbeSymbol)
15043 .addReg(X86::EAX, RegState::Implicit)
15044 .addReg(X86::ESP, RegState::Implicit)
15045 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
15046 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
15047 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15050 MI->eraseFromParent(); // The pseudo instruction is gone now.
15054 MachineBasicBlock *
15055 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
15056 MachineBasicBlock *BB) const {
15057 // This is pretty easy. We're taking the value that we received from
15058 // our load from the relocation, sticking it in either RDI (x86-64)
15059 // or EAX and doing an indirect call. The return value will then
15060 // be in the normal return register.
15061 const X86InstrInfo *TII
15062 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
15063 DebugLoc DL = MI->getDebugLoc();
15064 MachineFunction *F = BB->getParent();
15066 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
15067 assert(MI->getOperand(3).isGlobal() && "This should be a global");
15069 // Get a register mask for the lowered call.
15070 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
15071 // proper register mask.
15072 const uint32_t *RegMask =
15073 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15074 if (Subtarget->is64Bit()) {
15075 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15076 TII->get(X86::MOV64rm), X86::RDI)
15078 .addImm(0).addReg(0)
15079 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15080 MI->getOperand(3).getTargetFlags())
15082 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
15083 addDirectMem(MIB, X86::RDI);
15084 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
15085 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
15086 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15087 TII->get(X86::MOV32rm), X86::EAX)
15089 .addImm(0).addReg(0)
15090 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15091 MI->getOperand(3).getTargetFlags())
15093 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15094 addDirectMem(MIB, X86::EAX);
15095 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15097 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15098 TII->get(X86::MOV32rm), X86::EAX)
15099 .addReg(TII->getGlobalBaseReg(F))
15100 .addImm(0).addReg(0)
15101 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15102 MI->getOperand(3).getTargetFlags())
15104 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15105 addDirectMem(MIB, X86::EAX);
15106 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15109 MI->eraseFromParent(); // The pseudo instruction is gone now.
15113 MachineBasicBlock *
15114 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
15115 MachineBasicBlock *MBB) const {
15116 DebugLoc DL = MI->getDebugLoc();
15117 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15119 MachineFunction *MF = MBB->getParent();
15120 MachineRegisterInfo &MRI = MF->getRegInfo();
15122 const BasicBlock *BB = MBB->getBasicBlock();
15123 MachineFunction::iterator I = MBB;
15126 // Memory Reference
15127 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15128 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15131 unsigned MemOpndSlot = 0;
15133 unsigned CurOp = 0;
15135 DstReg = MI->getOperand(CurOp++).getReg();
15136 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
15137 assert(RC->hasType(MVT::i32) && "Invalid destination!");
15138 unsigned mainDstReg = MRI.createVirtualRegister(RC);
15139 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
15141 MemOpndSlot = CurOp;
15143 MVT PVT = getPointerTy();
15144 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15145 "Invalid Pointer Size!");
15147 // For v = setjmp(buf), we generate
15150 // buf[LabelOffset] = restoreMBB
15151 // SjLjSetup restoreMBB
15157 // v = phi(main, restore)
15162 MachineBasicBlock *thisMBB = MBB;
15163 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
15164 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
15165 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
15166 MF->insert(I, mainMBB);
15167 MF->insert(I, sinkMBB);
15168 MF->push_back(restoreMBB);
15170 MachineInstrBuilder MIB;
15172 // Transfer the remainder of BB and its successor edges to sinkMBB.
15173 sinkMBB->splice(sinkMBB->begin(), MBB,
15174 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
15175 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
15178 unsigned PtrStoreOpc = 0;
15179 unsigned LabelReg = 0;
15180 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15181 Reloc::Model RM = getTargetMachine().getRelocationModel();
15182 bool UseImmLabel = (getTargetMachine().getCodeModel() == CodeModel::Small) &&
15183 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
15185 // Prepare IP either in reg or imm.
15186 if (!UseImmLabel) {
15187 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
15188 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
15189 LabelReg = MRI.createVirtualRegister(PtrRC);
15190 if (Subtarget->is64Bit()) {
15191 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
15195 .addMBB(restoreMBB)
15198 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
15199 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
15200 .addReg(XII->getGlobalBaseReg(MF))
15203 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
15207 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
15209 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
15210 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15211 if (i == X86::AddrDisp)
15212 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
15214 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
15217 MIB.addReg(LabelReg);
15219 MIB.addMBB(restoreMBB);
15220 MIB.setMemRefs(MMOBegin, MMOEnd);
15222 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
15223 .addMBB(restoreMBB);
15225 const X86RegisterInfo *RegInfo =
15226 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15227 MIB.addRegMask(RegInfo->getNoPreservedMask());
15228 thisMBB->addSuccessor(mainMBB);
15229 thisMBB->addSuccessor(restoreMBB);
15233 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
15234 mainMBB->addSuccessor(sinkMBB);
15237 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15238 TII->get(X86::PHI), DstReg)
15239 .addReg(mainDstReg).addMBB(mainMBB)
15240 .addReg(restoreDstReg).addMBB(restoreMBB);
15243 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
15244 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
15245 restoreMBB->addSuccessor(sinkMBB);
15247 MI->eraseFromParent();
15251 MachineBasicBlock *
15252 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
15253 MachineBasicBlock *MBB) const {
15254 DebugLoc DL = MI->getDebugLoc();
15255 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15257 MachineFunction *MF = MBB->getParent();
15258 MachineRegisterInfo &MRI = MF->getRegInfo();
15260 // Memory Reference
15261 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15262 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15264 MVT PVT = getPointerTy();
15265 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15266 "Invalid Pointer Size!");
15268 const TargetRegisterClass *RC =
15269 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
15270 unsigned Tmp = MRI.createVirtualRegister(RC);
15271 // Since FP is only updated here but NOT referenced, it's treated as GPR.
15272 const X86RegisterInfo *RegInfo =
15273 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15274 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
15275 unsigned SP = RegInfo->getStackRegister();
15277 MachineInstrBuilder MIB;
15279 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15280 const int64_t SPOffset = 2 * PVT.getStoreSize();
15282 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
15283 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
15286 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
15287 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
15288 MIB.addOperand(MI->getOperand(i));
15289 MIB.setMemRefs(MMOBegin, MMOEnd);
15291 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
15292 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15293 if (i == X86::AddrDisp)
15294 MIB.addDisp(MI->getOperand(i), LabelOffset);
15296 MIB.addOperand(MI->getOperand(i));
15298 MIB.setMemRefs(MMOBegin, MMOEnd);
15300 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
15301 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15302 if (i == X86::AddrDisp)
15303 MIB.addDisp(MI->getOperand(i), SPOffset);
15305 MIB.addOperand(MI->getOperand(i));
15307 MIB.setMemRefs(MMOBegin, MMOEnd);
15309 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
15311 MI->eraseFromParent();
15315 MachineBasicBlock *
15316 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
15317 MachineBasicBlock *BB) const {
15318 switch (MI->getOpcode()) {
15319 default: llvm_unreachable("Unexpected instr type to insert");
15320 case X86::TAILJMPd64:
15321 case X86::TAILJMPr64:
15322 case X86::TAILJMPm64:
15323 llvm_unreachable("TAILJMP64 would not be touched here.");
15324 case X86::TCRETURNdi64:
15325 case X86::TCRETURNri64:
15326 case X86::TCRETURNmi64:
15328 case X86::WIN_ALLOCA:
15329 return EmitLoweredWinAlloca(MI, BB);
15330 case X86::SEG_ALLOCA_32:
15331 return EmitLoweredSegAlloca(MI, BB, false);
15332 case X86::SEG_ALLOCA_64:
15333 return EmitLoweredSegAlloca(MI, BB, true);
15334 case X86::TLSCall_32:
15335 case X86::TLSCall_64:
15336 return EmitLoweredTLSCall(MI, BB);
15337 case X86::CMOV_GR8:
15338 case X86::CMOV_FR32:
15339 case X86::CMOV_FR64:
15340 case X86::CMOV_V4F32:
15341 case X86::CMOV_V2F64:
15342 case X86::CMOV_V2I64:
15343 case X86::CMOV_V8F32:
15344 case X86::CMOV_V4F64:
15345 case X86::CMOV_V4I64:
15346 case X86::CMOV_GR16:
15347 case X86::CMOV_GR32:
15348 case X86::CMOV_RFP32:
15349 case X86::CMOV_RFP64:
15350 case X86::CMOV_RFP80:
15351 return EmitLoweredSelect(MI, BB);
15353 case X86::FP32_TO_INT16_IN_MEM:
15354 case X86::FP32_TO_INT32_IN_MEM:
15355 case X86::FP32_TO_INT64_IN_MEM:
15356 case X86::FP64_TO_INT16_IN_MEM:
15357 case X86::FP64_TO_INT32_IN_MEM:
15358 case X86::FP64_TO_INT64_IN_MEM:
15359 case X86::FP80_TO_INT16_IN_MEM:
15360 case X86::FP80_TO_INT32_IN_MEM:
15361 case X86::FP80_TO_INT64_IN_MEM: {
15362 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15363 DebugLoc DL = MI->getDebugLoc();
15365 // Change the floating point control register to use "round towards zero"
15366 // mode when truncating to an integer value.
15367 MachineFunction *F = BB->getParent();
15368 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
15369 addFrameReference(BuildMI(*BB, MI, DL,
15370 TII->get(X86::FNSTCW16m)), CWFrameIdx);
15372 // Load the old value of the high byte of the control word...
15374 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
15375 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
15378 // Set the high part to be round to zero...
15379 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
15382 // Reload the modified control word now...
15383 addFrameReference(BuildMI(*BB, MI, DL,
15384 TII->get(X86::FLDCW16m)), CWFrameIdx);
15386 // Restore the memory image of control word to original value
15387 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
15390 // Get the X86 opcode to use.
15392 switch (MI->getOpcode()) {
15393 default: llvm_unreachable("illegal opcode!");
15394 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
15395 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
15396 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
15397 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
15398 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
15399 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
15400 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
15401 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
15402 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
15406 MachineOperand &Op = MI->getOperand(0);
15408 AM.BaseType = X86AddressMode::RegBase;
15409 AM.Base.Reg = Op.getReg();
15411 AM.BaseType = X86AddressMode::FrameIndexBase;
15412 AM.Base.FrameIndex = Op.getIndex();
15414 Op = MI->getOperand(1);
15416 AM.Scale = Op.getImm();
15417 Op = MI->getOperand(2);
15419 AM.IndexReg = Op.getImm();
15420 Op = MI->getOperand(3);
15421 if (Op.isGlobal()) {
15422 AM.GV = Op.getGlobal();
15424 AM.Disp = Op.getImm();
15426 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
15427 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
15429 // Reload the original control word now.
15430 addFrameReference(BuildMI(*BB, MI, DL,
15431 TII->get(X86::FLDCW16m)), CWFrameIdx);
15433 MI->eraseFromParent(); // The pseudo instruction is gone now.
15436 // String/text processing lowering.
15437 case X86::PCMPISTRM128REG:
15438 case X86::VPCMPISTRM128REG:
15439 case X86::PCMPISTRM128MEM:
15440 case X86::VPCMPISTRM128MEM:
15441 case X86::PCMPESTRM128REG:
15442 case X86::VPCMPESTRM128REG:
15443 case X86::PCMPESTRM128MEM:
15444 case X86::VPCMPESTRM128MEM:
15445 assert(Subtarget->hasSSE42() &&
15446 "Target must have SSE4.2 or AVX features enabled");
15447 return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo());
15449 // String/text processing lowering.
15450 case X86::PCMPISTRIREG:
15451 case X86::VPCMPISTRIREG:
15452 case X86::PCMPISTRIMEM:
15453 case X86::VPCMPISTRIMEM:
15454 case X86::PCMPESTRIREG:
15455 case X86::VPCMPESTRIREG:
15456 case X86::PCMPESTRIMEM:
15457 case X86::VPCMPESTRIMEM:
15458 assert(Subtarget->hasSSE42() &&
15459 "Target must have SSE4.2 or AVX features enabled");
15460 return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo());
15462 // Thread synchronization.
15464 return EmitMonitor(MI, BB, getTargetMachine().getInstrInfo(), Subtarget);
15468 return EmitXBegin(MI, BB, getTargetMachine().getInstrInfo());
15470 // Atomic Lowering.
15471 case X86::ATOMAND8:
15472 case X86::ATOMAND16:
15473 case X86::ATOMAND32:
15474 case X86::ATOMAND64:
15477 case X86::ATOMOR16:
15478 case X86::ATOMOR32:
15479 case X86::ATOMOR64:
15481 case X86::ATOMXOR16:
15482 case X86::ATOMXOR8:
15483 case X86::ATOMXOR32:
15484 case X86::ATOMXOR64:
15486 case X86::ATOMNAND8:
15487 case X86::ATOMNAND16:
15488 case X86::ATOMNAND32:
15489 case X86::ATOMNAND64:
15491 case X86::ATOMMAX8:
15492 case X86::ATOMMAX16:
15493 case X86::ATOMMAX32:
15494 case X86::ATOMMAX64:
15496 case X86::ATOMMIN8:
15497 case X86::ATOMMIN16:
15498 case X86::ATOMMIN32:
15499 case X86::ATOMMIN64:
15501 case X86::ATOMUMAX8:
15502 case X86::ATOMUMAX16:
15503 case X86::ATOMUMAX32:
15504 case X86::ATOMUMAX64:
15506 case X86::ATOMUMIN8:
15507 case X86::ATOMUMIN16:
15508 case X86::ATOMUMIN32:
15509 case X86::ATOMUMIN64:
15510 return EmitAtomicLoadArith(MI, BB);
15512 // This group does 64-bit operations on a 32-bit host.
15513 case X86::ATOMAND6432:
15514 case X86::ATOMOR6432:
15515 case X86::ATOMXOR6432:
15516 case X86::ATOMNAND6432:
15517 case X86::ATOMADD6432:
15518 case X86::ATOMSUB6432:
15519 case X86::ATOMMAX6432:
15520 case X86::ATOMMIN6432:
15521 case X86::ATOMUMAX6432:
15522 case X86::ATOMUMIN6432:
15523 case X86::ATOMSWAP6432:
15524 return EmitAtomicLoadArith6432(MI, BB);
15526 case X86::VASTART_SAVE_XMM_REGS:
15527 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
15529 case X86::VAARG_64:
15530 return EmitVAARG64WithCustomInserter(MI, BB);
15532 case X86::EH_SjLj_SetJmp32:
15533 case X86::EH_SjLj_SetJmp64:
15534 return emitEHSjLjSetJmp(MI, BB);
15536 case X86::EH_SjLj_LongJmp32:
15537 case X86::EH_SjLj_LongJmp64:
15538 return emitEHSjLjLongJmp(MI, BB);
15542 //===----------------------------------------------------------------------===//
15543 // X86 Optimization Hooks
15544 //===----------------------------------------------------------------------===//
15546 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
15549 const SelectionDAG &DAG,
15550 unsigned Depth) const {
15551 unsigned BitWidth = KnownZero.getBitWidth();
15552 unsigned Opc = Op.getOpcode();
15553 assert((Opc >= ISD::BUILTIN_OP_END ||
15554 Opc == ISD::INTRINSIC_WO_CHAIN ||
15555 Opc == ISD::INTRINSIC_W_CHAIN ||
15556 Opc == ISD::INTRINSIC_VOID) &&
15557 "Should use MaskedValueIsZero if you don't know whether Op"
15558 " is a target node!");
15560 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
15574 // These nodes' second result is a boolean.
15575 if (Op.getResNo() == 0)
15578 case X86ISD::SETCC:
15579 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
15581 case ISD::INTRINSIC_WO_CHAIN: {
15582 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15583 unsigned NumLoBits = 0;
15586 case Intrinsic::x86_sse_movmsk_ps:
15587 case Intrinsic::x86_avx_movmsk_ps_256:
15588 case Intrinsic::x86_sse2_movmsk_pd:
15589 case Intrinsic::x86_avx_movmsk_pd_256:
15590 case Intrinsic::x86_mmx_pmovmskb:
15591 case Intrinsic::x86_sse2_pmovmskb_128:
15592 case Intrinsic::x86_avx2_pmovmskb: {
15593 // High bits of movmskp{s|d}, pmovmskb are known zero.
15595 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15596 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
15597 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
15598 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
15599 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
15600 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
15601 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
15602 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
15604 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
15613 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
15614 unsigned Depth) const {
15615 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
15616 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
15617 return Op.getValueType().getScalarType().getSizeInBits();
15623 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
15624 /// node is a GlobalAddress + offset.
15625 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
15626 const GlobalValue* &GA,
15627 int64_t &Offset) const {
15628 if (N->getOpcode() == X86ISD::Wrapper) {
15629 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
15630 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
15631 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
15635 return TargetLowering::isGAPlusOffset(N, GA, Offset);
15638 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
15639 /// same as extracting the high 128-bit part of 256-bit vector and then
15640 /// inserting the result into the low part of a new 256-bit vector
15641 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
15642 EVT VT = SVOp->getValueType(0);
15643 unsigned NumElems = VT.getVectorNumElements();
15645 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
15646 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
15647 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
15648 SVOp->getMaskElt(j) >= 0)
15654 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
15655 /// same as extracting the low 128-bit part of 256-bit vector and then
15656 /// inserting the result into the high part of a new 256-bit vector
15657 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
15658 EVT VT = SVOp->getValueType(0);
15659 unsigned NumElems = VT.getVectorNumElements();
15661 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
15662 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
15663 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
15664 SVOp->getMaskElt(j) >= 0)
15670 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
15671 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
15672 TargetLowering::DAGCombinerInfo &DCI,
15673 const X86Subtarget* Subtarget) {
15675 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
15676 SDValue V1 = SVOp->getOperand(0);
15677 SDValue V2 = SVOp->getOperand(1);
15678 EVT VT = SVOp->getValueType(0);
15679 unsigned NumElems = VT.getVectorNumElements();
15681 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
15682 V2.getOpcode() == ISD::CONCAT_VECTORS) {
15686 // V UNDEF BUILD_VECTOR UNDEF
15688 // CONCAT_VECTOR CONCAT_VECTOR
15691 // RESULT: V + zero extended
15693 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
15694 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
15695 V1.getOperand(1).getOpcode() != ISD::UNDEF)
15698 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
15701 // To match the shuffle mask, the first half of the mask should
15702 // be exactly the first vector, and all the rest a splat with the
15703 // first element of the second one.
15704 for (unsigned i = 0; i != NumElems/2; ++i)
15705 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
15706 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
15709 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
15710 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
15711 if (Ld->hasNUsesOfValue(1, 0)) {
15712 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
15713 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
15715 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
15716 array_lengthof(Ops),
15718 Ld->getPointerInfo(),
15719 Ld->getAlignment(),
15720 false/*isVolatile*/, true/*ReadMem*/,
15721 false/*WriteMem*/);
15723 // Make sure the newly-created LOAD is in the same position as Ld in
15724 // terms of dependency. We create a TokenFactor for Ld and ResNode,
15725 // and update uses of Ld's output chain to use the TokenFactor.
15726 if (Ld->hasAnyUseOfValue(1)) {
15727 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
15728 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
15729 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
15730 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
15731 SDValue(ResNode.getNode(), 1));
15734 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
15738 // Emit a zeroed vector and insert the desired subvector on its
15740 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
15741 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
15742 return DCI.CombineTo(N, InsV);
15745 //===--------------------------------------------------------------------===//
15746 // Combine some shuffles into subvector extracts and inserts:
15749 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
15750 if (isShuffleHigh128VectorInsertLow(SVOp)) {
15751 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
15752 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
15753 return DCI.CombineTo(N, InsV);
15756 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
15757 if (isShuffleLow128VectorInsertHigh(SVOp)) {
15758 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
15759 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
15760 return DCI.CombineTo(N, InsV);
15766 /// PerformShuffleCombine - Performs several different shuffle combines.
15767 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
15768 TargetLowering::DAGCombinerInfo &DCI,
15769 const X86Subtarget *Subtarget) {
15771 EVT VT = N->getValueType(0);
15773 // Don't create instructions with illegal types after legalize types has run.
15774 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15775 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
15778 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
15779 if (Subtarget->hasFp256() && VT.is256BitVector() &&
15780 N->getOpcode() == ISD::VECTOR_SHUFFLE)
15781 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
15783 // Only handle 128 wide vector from here on.
15784 if (!VT.is128BitVector())
15787 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
15788 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
15789 // consecutive, non-overlapping, and in the right order.
15790 SmallVector<SDValue, 16> Elts;
15791 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
15792 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
15794 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
15797 /// PerformTruncateCombine - Converts truncate operation to
15798 /// a sequence of vector shuffle operations.
15799 /// It is possible when we truncate 256-bit vector to 128-bit vector
15800 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
15801 TargetLowering::DAGCombinerInfo &DCI,
15802 const X86Subtarget *Subtarget) {
15806 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
15807 /// specific shuffle of a load can be folded into a single element load.
15808 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
15809 /// shuffles have been customed lowered so we need to handle those here.
15810 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
15811 TargetLowering::DAGCombinerInfo &DCI) {
15812 if (DCI.isBeforeLegalizeOps())
15815 SDValue InVec = N->getOperand(0);
15816 SDValue EltNo = N->getOperand(1);
15818 if (!isa<ConstantSDNode>(EltNo))
15821 EVT VT = InVec.getValueType();
15823 bool HasShuffleIntoBitcast = false;
15824 if (InVec.getOpcode() == ISD::BITCAST) {
15825 // Don't duplicate a load with other uses.
15826 if (!InVec.hasOneUse())
15828 EVT BCVT = InVec.getOperand(0).getValueType();
15829 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
15831 InVec = InVec.getOperand(0);
15832 HasShuffleIntoBitcast = true;
15835 if (!isTargetShuffle(InVec.getOpcode()))
15838 // Don't duplicate a load with other uses.
15839 if (!InVec.hasOneUse())
15842 SmallVector<int, 16> ShuffleMask;
15844 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
15848 // Select the input vector, guarding against out of range extract vector.
15849 unsigned NumElems = VT.getVectorNumElements();
15850 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
15851 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
15852 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
15853 : InVec.getOperand(1);
15855 // If inputs to shuffle are the same for both ops, then allow 2 uses
15856 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
15858 if (LdNode.getOpcode() == ISD::BITCAST) {
15859 // Don't duplicate a load with other uses.
15860 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
15863 AllowedUses = 1; // only allow 1 load use if we have a bitcast
15864 LdNode = LdNode.getOperand(0);
15867 if (!ISD::isNormalLoad(LdNode.getNode()))
15870 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
15872 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
15875 if (HasShuffleIntoBitcast) {
15876 // If there's a bitcast before the shuffle, check if the load type and
15877 // alignment is valid.
15878 unsigned Align = LN0->getAlignment();
15879 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15880 unsigned NewAlign = TLI.getDataLayout()->
15881 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
15883 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
15887 // All checks match so transform back to vector_shuffle so that DAG combiner
15888 // can finish the job
15891 // Create shuffle node taking into account the case that its a unary shuffle
15892 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
15893 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
15894 InVec.getOperand(0), Shuffle,
15896 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
15897 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
15901 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
15902 /// generation and convert it from being a bunch of shuffles and extracts
15903 /// to a simple store and scalar loads to extract the elements.
15904 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
15905 TargetLowering::DAGCombinerInfo &DCI) {
15906 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
15907 if (NewOp.getNode())
15910 SDValue InputVector = N->getOperand(0);
15911 // Detect whether we are trying to convert from mmx to i32 and the bitcast
15912 // from mmx to v2i32 has a single usage.
15913 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
15914 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
15915 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
15916 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
15917 N->getValueType(0),
15918 InputVector.getNode()->getOperand(0));
15920 // Only operate on vectors of 4 elements, where the alternative shuffling
15921 // gets to be more expensive.
15922 if (InputVector.getValueType() != MVT::v4i32)
15925 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
15926 // single use which is a sign-extend or zero-extend, and all elements are
15928 SmallVector<SDNode *, 4> Uses;
15929 unsigned ExtractedElements = 0;
15930 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
15931 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
15932 if (UI.getUse().getResNo() != InputVector.getResNo())
15935 SDNode *Extract = *UI;
15936 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
15939 if (Extract->getValueType(0) != MVT::i32)
15941 if (!Extract->hasOneUse())
15943 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
15944 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
15946 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
15949 // Record which element was extracted.
15950 ExtractedElements |=
15951 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
15953 Uses.push_back(Extract);
15956 // If not all the elements were used, this may not be worthwhile.
15957 if (ExtractedElements != 15)
15960 // Ok, we've now decided to do the transformation.
15961 SDLoc dl(InputVector);
15963 // Store the value to a temporary stack slot.
15964 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
15965 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
15966 MachinePointerInfo(), false, false, 0);
15968 // Replace each use (extract) with a load of the appropriate element.
15969 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
15970 UE = Uses.end(); UI != UE; ++UI) {
15971 SDNode *Extract = *UI;
15973 // cOMpute the element's address.
15974 SDValue Idx = Extract->getOperand(1);
15976 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
15977 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
15978 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15979 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
15981 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
15982 StackPtr, OffsetVal);
15984 // Load the scalar.
15985 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
15986 ScalarAddr, MachinePointerInfo(),
15987 false, false, false, 0);
15989 // Replace the exact with the load.
15990 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
15993 // The replacement was made in place; don't return anything.
15997 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
15998 static unsigned matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS,
15999 SDValue RHS, SelectionDAG &DAG,
16000 const X86Subtarget *Subtarget) {
16001 if (!VT.isVector())
16004 switch (VT.getSimpleVT().SimpleTy) {
16009 if (!Subtarget->hasAVX2())
16014 if (!Subtarget->hasSSE2())
16018 // SSE2 has only a small subset of the operations.
16019 bool hasUnsigned = Subtarget->hasSSE41() ||
16020 (Subtarget->hasSSE2() && VT == MVT::v16i8);
16021 bool hasSigned = Subtarget->hasSSE41() ||
16022 (Subtarget->hasSSE2() && VT == MVT::v8i16);
16024 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16026 // Check for x CC y ? x : y.
16027 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16028 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16033 return hasUnsigned ? X86ISD::UMIN : 0;
16036 return hasUnsigned ? X86ISD::UMAX : 0;
16039 return hasSigned ? X86ISD::SMIN : 0;
16042 return hasSigned ? X86ISD::SMAX : 0;
16044 // Check for x CC y ? y : x -- a min/max with reversed arms.
16045 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16046 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16051 return hasUnsigned ? X86ISD::UMAX : 0;
16054 return hasUnsigned ? X86ISD::UMIN : 0;
16057 return hasSigned ? X86ISD::SMAX : 0;
16060 return hasSigned ? X86ISD::SMIN : 0;
16067 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
16069 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
16070 TargetLowering::DAGCombinerInfo &DCI,
16071 const X86Subtarget *Subtarget) {
16073 SDValue Cond = N->getOperand(0);
16074 // Get the LHS/RHS of the select.
16075 SDValue LHS = N->getOperand(1);
16076 SDValue RHS = N->getOperand(2);
16077 EVT VT = LHS.getValueType();
16079 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
16080 // instructions match the semantics of the common C idiom x<y?x:y but not
16081 // x<=y?x:y, because of how they handle negative zero (which can be
16082 // ignored in unsafe-math mode).
16083 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
16084 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
16085 (Subtarget->hasSSE2() ||
16086 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
16087 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16089 unsigned Opcode = 0;
16090 // Check for x CC y ? x : y.
16091 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16092 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16096 // Converting this to a min would handle NaNs incorrectly, and swapping
16097 // the operands would cause it to handle comparisons between positive
16098 // and negative zero incorrectly.
16099 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16100 if (!DAG.getTarget().Options.UnsafeFPMath &&
16101 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16103 std::swap(LHS, RHS);
16105 Opcode = X86ISD::FMIN;
16108 // Converting this to a min would handle comparisons between positive
16109 // and negative zero incorrectly.
16110 if (!DAG.getTarget().Options.UnsafeFPMath &&
16111 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16113 Opcode = X86ISD::FMIN;
16116 // Converting this to a min would handle both negative zeros and NaNs
16117 // incorrectly, but we can swap the operands to fix both.
16118 std::swap(LHS, RHS);
16122 Opcode = X86ISD::FMIN;
16126 // Converting this to a max would handle comparisons between positive
16127 // and negative zero incorrectly.
16128 if (!DAG.getTarget().Options.UnsafeFPMath &&
16129 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16131 Opcode = X86ISD::FMAX;
16134 // Converting this to a max would handle NaNs incorrectly, and swapping
16135 // the operands would cause it to handle comparisons between positive
16136 // and negative zero incorrectly.
16137 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16138 if (!DAG.getTarget().Options.UnsafeFPMath &&
16139 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16141 std::swap(LHS, RHS);
16143 Opcode = X86ISD::FMAX;
16146 // Converting this to a max would handle both negative zeros and NaNs
16147 // incorrectly, but we can swap the operands to fix both.
16148 std::swap(LHS, RHS);
16152 Opcode = X86ISD::FMAX;
16155 // Check for x CC y ? y : x -- a min/max with reversed arms.
16156 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16157 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16161 // Converting this to a min would handle comparisons between positive
16162 // and negative zero incorrectly, and swapping the operands would
16163 // cause it to handle NaNs incorrectly.
16164 if (!DAG.getTarget().Options.UnsafeFPMath &&
16165 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
16166 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16168 std::swap(LHS, RHS);
16170 Opcode = X86ISD::FMIN;
16173 // Converting this to a min would handle NaNs incorrectly.
16174 if (!DAG.getTarget().Options.UnsafeFPMath &&
16175 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
16177 Opcode = X86ISD::FMIN;
16180 // Converting this to a min would handle both negative zeros and NaNs
16181 // incorrectly, but we can swap the operands to fix both.
16182 std::swap(LHS, RHS);
16186 Opcode = X86ISD::FMIN;
16190 // Converting this to a max would handle NaNs incorrectly.
16191 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16193 Opcode = X86ISD::FMAX;
16196 // Converting this to a max would handle comparisons between positive
16197 // and negative zero incorrectly, and swapping the operands would
16198 // cause it to handle NaNs incorrectly.
16199 if (!DAG.getTarget().Options.UnsafeFPMath &&
16200 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
16201 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16203 std::swap(LHS, RHS);
16205 Opcode = X86ISD::FMAX;
16208 // Converting this to a max would handle both negative zeros and NaNs
16209 // incorrectly, but we can swap the operands to fix both.
16210 std::swap(LHS, RHS);
16214 Opcode = X86ISD::FMAX;
16220 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
16223 // If this is a select between two integer constants, try to do some
16225 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
16226 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
16227 // Don't do this for crazy integer types.
16228 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
16229 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
16230 // so that TrueC (the true value) is larger than FalseC.
16231 bool NeedsCondInvert = false;
16233 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
16234 // Efficiently invertible.
16235 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
16236 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
16237 isa<ConstantSDNode>(Cond.getOperand(1))))) {
16238 NeedsCondInvert = true;
16239 std::swap(TrueC, FalseC);
16242 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
16243 if (FalseC->getAPIntValue() == 0 &&
16244 TrueC->getAPIntValue().isPowerOf2()) {
16245 if (NeedsCondInvert) // Invert the condition if needed.
16246 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16247 DAG.getConstant(1, Cond.getValueType()));
16249 // Zero extend the condition if needed.
16250 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
16252 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
16253 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
16254 DAG.getConstant(ShAmt, MVT::i8));
16257 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
16258 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
16259 if (NeedsCondInvert) // Invert the condition if needed.
16260 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16261 DAG.getConstant(1, Cond.getValueType()));
16263 // Zero extend the condition if needed.
16264 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
16265 FalseC->getValueType(0), Cond);
16266 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16267 SDValue(FalseC, 0));
16270 // Optimize cases that will turn into an LEA instruction. This requires
16271 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
16272 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
16273 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
16274 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
16276 bool isFastMultiplier = false;
16278 switch ((unsigned char)Diff) {
16280 case 1: // result = add base, cond
16281 case 2: // result = lea base( , cond*2)
16282 case 3: // result = lea base(cond, cond*2)
16283 case 4: // result = lea base( , cond*4)
16284 case 5: // result = lea base(cond, cond*4)
16285 case 8: // result = lea base( , cond*8)
16286 case 9: // result = lea base(cond, cond*8)
16287 isFastMultiplier = true;
16292 if (isFastMultiplier) {
16293 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
16294 if (NeedsCondInvert) // Invert the condition if needed.
16295 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16296 DAG.getConstant(1, Cond.getValueType()));
16298 // Zero extend the condition if needed.
16299 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
16301 // Scale the condition by the difference.
16303 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
16304 DAG.getConstant(Diff, Cond.getValueType()));
16306 // Add the base if non-zero.
16307 if (FalseC->getAPIntValue() != 0)
16308 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16309 SDValue(FalseC, 0));
16316 // Canonicalize max and min:
16317 // (x > y) ? x : y -> (x >= y) ? x : y
16318 // (x < y) ? x : y -> (x <= y) ? x : y
16319 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
16320 // the need for an extra compare
16321 // against zero. e.g.
16322 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
16324 // testl %edi, %edi
16326 // cmovgl %edi, %eax
16330 // cmovsl %eax, %edi
16331 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
16332 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16333 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16334 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16339 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
16340 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
16341 Cond.getOperand(0), Cond.getOperand(1), NewCC);
16342 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
16347 // Match VSELECTs into subs with unsigned saturation.
16348 if (!DCI.isBeforeLegalize() &&
16349 N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
16350 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
16351 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
16352 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
16353 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16355 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
16356 // left side invert the predicate to simplify logic below.
16358 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
16360 CC = ISD::getSetCCInverse(CC, true);
16361 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
16365 if (Other.getNode() && Other->getNumOperands() == 2 &&
16366 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
16367 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
16368 SDValue CondRHS = Cond->getOperand(1);
16370 // Look for a general sub with unsigned saturation first.
16371 // x >= y ? x-y : 0 --> subus x, y
16372 // x > y ? x-y : 0 --> subus x, y
16373 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
16374 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
16375 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
16377 // If the RHS is a constant we have to reverse the const canonicalization.
16378 // x > C-1 ? x+-C : 0 --> subus x, C
16379 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
16380 isSplatVector(CondRHS.getNode()) && isSplatVector(OpRHS.getNode())) {
16381 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
16382 if (CondRHS.getConstantOperandVal(0) == -A-1)
16383 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS,
16384 DAG.getConstant(-A, VT));
16387 // Another special case: If C was a sign bit, the sub has been
16388 // canonicalized into a xor.
16389 // FIXME: Would it be better to use ComputeMaskedBits to determine whether
16390 // it's safe to decanonicalize the xor?
16391 // x s< 0 ? x^C : 0 --> subus x, C
16392 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
16393 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
16394 isSplatVector(OpRHS.getNode())) {
16395 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
16397 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
16402 // Try to match a min/max vector operation.
16403 if (!DCI.isBeforeLegalize() &&
16404 N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC)
16405 if (unsigned Op = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget))
16406 return DAG.getNode(Op, DL, N->getValueType(0), LHS, RHS);
16408 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
16409 if (!DCI.isBeforeLegalize() && N->getOpcode() == ISD::VSELECT &&
16410 Cond.getOpcode() == ISD::SETCC) {
16412 assert(Cond.getValueType().isVector() &&
16413 "vector select expects a vector selector!");
16415 EVT IntVT = Cond.getValueType();
16416 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
16417 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
16419 if (!TValIsAllOnes && !FValIsAllZeros) {
16420 // Try invert the condition if true value is not all 1s and false value
16422 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
16423 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
16425 if (TValIsAllZeros || FValIsAllOnes) {
16426 SDValue CC = Cond.getOperand(2);
16427 ISD::CondCode NewCC =
16428 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
16429 Cond.getOperand(0).getValueType().isInteger());
16430 Cond = DAG.getSetCC(DL, IntVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
16431 std::swap(LHS, RHS);
16432 TValIsAllOnes = FValIsAllOnes;
16433 FValIsAllZeros = TValIsAllZeros;
16437 if (TValIsAllOnes || FValIsAllZeros) {
16440 if (TValIsAllOnes && FValIsAllZeros)
16442 else if (TValIsAllOnes)
16443 Ret = DAG.getNode(ISD::OR, DL, IntVT, Cond,
16444 DAG.getNode(ISD::BITCAST, DL, IntVT, RHS));
16445 else if (FValIsAllZeros)
16446 Ret = DAG.getNode(ISD::AND, DL, IntVT, Cond,
16447 DAG.getNode(ISD::BITCAST, DL, IntVT, LHS));
16449 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
16453 // If we know that this node is legal then we know that it is going to be
16454 // matched by one of the SSE/AVX BLEND instructions. These instructions only
16455 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
16456 // to simplify previous instructions.
16457 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16458 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
16459 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
16460 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
16462 // Don't optimize vector selects that map to mask-registers.
16466 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
16467 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
16469 APInt KnownZero, KnownOne;
16470 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
16471 DCI.isBeforeLegalizeOps());
16472 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
16473 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
16474 DCI.CommitTargetLoweringOpt(TLO);
16480 // Check whether a boolean test is testing a boolean value generated by
16481 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
16484 // Simplify the following patterns:
16485 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
16486 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
16487 // to (Op EFLAGS Cond)
16489 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
16490 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
16491 // to (Op EFLAGS !Cond)
16493 // where Op could be BRCOND or CMOV.
16495 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
16496 // Quit if not CMP and SUB with its value result used.
16497 if (Cmp.getOpcode() != X86ISD::CMP &&
16498 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
16501 // Quit if not used as a boolean value.
16502 if (CC != X86::COND_E && CC != X86::COND_NE)
16505 // Check CMP operands. One of them should be 0 or 1 and the other should be
16506 // an SetCC or extended from it.
16507 SDValue Op1 = Cmp.getOperand(0);
16508 SDValue Op2 = Cmp.getOperand(1);
16511 const ConstantSDNode* C = 0;
16512 bool needOppositeCond = (CC == X86::COND_E);
16513 bool checkAgainstTrue = false; // Is it a comparison against 1?
16515 if ((C = dyn_cast<ConstantSDNode>(Op1)))
16517 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
16519 else // Quit if all operands are not constants.
16522 if (C->getZExtValue() == 1) {
16523 needOppositeCond = !needOppositeCond;
16524 checkAgainstTrue = true;
16525 } else if (C->getZExtValue() != 0)
16526 // Quit if the constant is neither 0 or 1.
16529 bool truncatedToBoolWithAnd = false;
16530 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
16531 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
16532 SetCC.getOpcode() == ISD::TRUNCATE ||
16533 SetCC.getOpcode() == ISD::AND) {
16534 if (SetCC.getOpcode() == ISD::AND) {
16536 ConstantSDNode *CS;
16537 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
16538 CS->getZExtValue() == 1)
16540 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
16541 CS->getZExtValue() == 1)
16545 SetCC = SetCC.getOperand(OpIdx);
16546 truncatedToBoolWithAnd = true;
16548 SetCC = SetCC.getOperand(0);
16551 switch (SetCC.getOpcode()) {
16552 case X86ISD::SETCC_CARRY:
16553 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
16554 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
16555 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
16556 // truncated to i1 using 'and'.
16557 if (checkAgainstTrue && !truncatedToBoolWithAnd)
16559 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
16560 "Invalid use of SETCC_CARRY!");
16562 case X86ISD::SETCC:
16563 // Set the condition code or opposite one if necessary.
16564 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
16565 if (needOppositeCond)
16566 CC = X86::GetOppositeBranchCondition(CC);
16567 return SetCC.getOperand(1);
16568 case X86ISD::CMOV: {
16569 // Check whether false/true value has canonical one, i.e. 0 or 1.
16570 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
16571 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
16572 // Quit if true value is not a constant.
16575 // Quit if false value is not a constant.
16577 SDValue Op = SetCC.getOperand(0);
16578 // Skip 'zext' or 'trunc' node.
16579 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
16580 Op.getOpcode() == ISD::TRUNCATE)
16581 Op = Op.getOperand(0);
16582 // A special case for rdrand/rdseed, where 0 is set if false cond is
16584 if ((Op.getOpcode() != X86ISD::RDRAND &&
16585 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
16588 // Quit if false value is not the constant 0 or 1.
16589 bool FValIsFalse = true;
16590 if (FVal && FVal->getZExtValue() != 0) {
16591 if (FVal->getZExtValue() != 1)
16593 // If FVal is 1, opposite cond is needed.
16594 needOppositeCond = !needOppositeCond;
16595 FValIsFalse = false;
16597 // Quit if TVal is not the constant opposite of FVal.
16598 if (FValIsFalse && TVal->getZExtValue() != 1)
16600 if (!FValIsFalse && TVal->getZExtValue() != 0)
16602 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
16603 if (needOppositeCond)
16604 CC = X86::GetOppositeBranchCondition(CC);
16605 return SetCC.getOperand(3);
16612 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
16613 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
16614 TargetLowering::DAGCombinerInfo &DCI,
16615 const X86Subtarget *Subtarget) {
16618 // If the flag operand isn't dead, don't touch this CMOV.
16619 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
16622 SDValue FalseOp = N->getOperand(0);
16623 SDValue TrueOp = N->getOperand(1);
16624 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
16625 SDValue Cond = N->getOperand(3);
16627 if (CC == X86::COND_E || CC == X86::COND_NE) {
16628 switch (Cond.getOpcode()) {
16632 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
16633 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
16634 return (CC == X86::COND_E) ? FalseOp : TrueOp;
16640 Flags = checkBoolTestSetCCCombine(Cond, CC);
16641 if (Flags.getNode() &&
16642 // Extra check as FCMOV only supports a subset of X86 cond.
16643 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
16644 SDValue Ops[] = { FalseOp, TrueOp,
16645 DAG.getConstant(CC, MVT::i8), Flags };
16646 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
16647 Ops, array_lengthof(Ops));
16650 // If this is a select between two integer constants, try to do some
16651 // optimizations. Note that the operands are ordered the opposite of SELECT
16653 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
16654 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
16655 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
16656 // larger than FalseC (the false value).
16657 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
16658 CC = X86::GetOppositeBranchCondition(CC);
16659 std::swap(TrueC, FalseC);
16660 std::swap(TrueOp, FalseOp);
16663 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
16664 // This is efficient for any integer data type (including i8/i16) and
16666 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
16667 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16668 DAG.getConstant(CC, MVT::i8), Cond);
16670 // Zero extend the condition if needed.
16671 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
16673 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
16674 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
16675 DAG.getConstant(ShAmt, MVT::i8));
16676 if (N->getNumValues() == 2) // Dead flag value?
16677 return DCI.CombineTo(N, Cond, SDValue());
16681 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
16682 // for any integer data type, including i8/i16.
16683 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
16684 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16685 DAG.getConstant(CC, MVT::i8), Cond);
16687 // Zero extend the condition if needed.
16688 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
16689 FalseC->getValueType(0), Cond);
16690 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16691 SDValue(FalseC, 0));
16693 if (N->getNumValues() == 2) // Dead flag value?
16694 return DCI.CombineTo(N, Cond, SDValue());
16698 // Optimize cases that will turn into an LEA instruction. This requires
16699 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
16700 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
16701 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
16702 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
16704 bool isFastMultiplier = false;
16706 switch ((unsigned char)Diff) {
16708 case 1: // result = add base, cond
16709 case 2: // result = lea base( , cond*2)
16710 case 3: // result = lea base(cond, cond*2)
16711 case 4: // result = lea base( , cond*4)
16712 case 5: // result = lea base(cond, cond*4)
16713 case 8: // result = lea base( , cond*8)
16714 case 9: // result = lea base(cond, cond*8)
16715 isFastMultiplier = true;
16720 if (isFastMultiplier) {
16721 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
16722 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16723 DAG.getConstant(CC, MVT::i8), Cond);
16724 // Zero extend the condition if needed.
16725 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
16727 // Scale the condition by the difference.
16729 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
16730 DAG.getConstant(Diff, Cond.getValueType()));
16732 // Add the base if non-zero.
16733 if (FalseC->getAPIntValue() != 0)
16734 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16735 SDValue(FalseC, 0));
16736 if (N->getNumValues() == 2) // Dead flag value?
16737 return DCI.CombineTo(N, Cond, SDValue());
16744 // Handle these cases:
16745 // (select (x != c), e, c) -> select (x != c), e, x),
16746 // (select (x == c), c, e) -> select (x == c), x, e)
16747 // where the c is an integer constant, and the "select" is the combination
16748 // of CMOV and CMP.
16750 // The rationale for this change is that the conditional-move from a constant
16751 // needs two instructions, however, conditional-move from a register needs
16752 // only one instruction.
16754 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
16755 // some instruction-combining opportunities. This opt needs to be
16756 // postponed as late as possible.
16758 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
16759 // the DCI.xxxx conditions are provided to postpone the optimization as
16760 // late as possible.
16762 ConstantSDNode *CmpAgainst = 0;
16763 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
16764 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
16765 !isa<ConstantSDNode>(Cond.getOperand(0))) {
16767 if (CC == X86::COND_NE &&
16768 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
16769 CC = X86::GetOppositeBranchCondition(CC);
16770 std::swap(TrueOp, FalseOp);
16773 if (CC == X86::COND_E &&
16774 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
16775 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
16776 DAG.getConstant(CC, MVT::i8), Cond };
16777 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops,
16778 array_lengthof(Ops));
16786 /// PerformMulCombine - Optimize a single multiply with constant into two
16787 /// in order to implement it with two cheaper instructions, e.g.
16788 /// LEA + SHL, LEA + LEA.
16789 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
16790 TargetLowering::DAGCombinerInfo &DCI) {
16791 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
16794 EVT VT = N->getValueType(0);
16795 if (VT != MVT::i64)
16798 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
16801 uint64_t MulAmt = C->getZExtValue();
16802 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
16805 uint64_t MulAmt1 = 0;
16806 uint64_t MulAmt2 = 0;
16807 if ((MulAmt % 9) == 0) {
16809 MulAmt2 = MulAmt / 9;
16810 } else if ((MulAmt % 5) == 0) {
16812 MulAmt2 = MulAmt / 5;
16813 } else if ((MulAmt % 3) == 0) {
16815 MulAmt2 = MulAmt / 3;
16818 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
16821 if (isPowerOf2_64(MulAmt2) &&
16822 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
16823 // If second multiplifer is pow2, issue it first. We want the multiply by
16824 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
16826 std::swap(MulAmt1, MulAmt2);
16829 if (isPowerOf2_64(MulAmt1))
16830 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
16831 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
16833 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
16834 DAG.getConstant(MulAmt1, VT));
16836 if (isPowerOf2_64(MulAmt2))
16837 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
16838 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
16840 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
16841 DAG.getConstant(MulAmt2, VT));
16843 // Do not add new nodes to DAG combiner worklist.
16844 DCI.CombineTo(N, NewMul, false);
16849 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
16850 SDValue N0 = N->getOperand(0);
16851 SDValue N1 = N->getOperand(1);
16852 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
16853 EVT VT = N0.getValueType();
16855 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
16856 // since the result of setcc_c is all zero's or all ones.
16857 if (VT.isInteger() && !VT.isVector() &&
16858 N1C && N0.getOpcode() == ISD::AND &&
16859 N0.getOperand(1).getOpcode() == ISD::Constant) {
16860 SDValue N00 = N0.getOperand(0);
16861 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
16862 ((N00.getOpcode() == ISD::ANY_EXTEND ||
16863 N00.getOpcode() == ISD::ZERO_EXTEND) &&
16864 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
16865 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
16866 APInt ShAmt = N1C->getAPIntValue();
16867 Mask = Mask.shl(ShAmt);
16869 return DAG.getNode(ISD::AND, SDLoc(N), VT,
16870 N00, DAG.getConstant(Mask, VT));
16874 // Hardware support for vector shifts is sparse which makes us scalarize the
16875 // vector operations in many cases. Also, on sandybridge ADD is faster than
16877 // (shl V, 1) -> add V,V
16878 if (isSplatVector(N1.getNode())) {
16879 assert(N0.getValueType().isVector() && "Invalid vector shift type");
16880 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
16881 // We shift all of the values by one. In many cases we do not have
16882 // hardware support for this operation. This is better expressed as an ADD
16884 if (N1C && (1 == N1C->getZExtValue())) {
16885 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
16892 /// \brief Returns a vector of 0s if the node in input is a vector logical
16893 /// shift by a constant amount which is known to be bigger than or equal
16894 /// to the vector element size in bits.
16895 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
16896 const X86Subtarget *Subtarget) {
16897 EVT VT = N->getValueType(0);
16899 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
16900 (!Subtarget->hasInt256() ||
16901 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
16904 SDValue Amt = N->getOperand(1);
16906 if (isSplatVector(Amt.getNode())) {
16907 SDValue SclrAmt = Amt->getOperand(0);
16908 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
16909 APInt ShiftAmt = C->getAPIntValue();
16910 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
16912 // SSE2/AVX2 logical shifts always return a vector of 0s
16913 // if the shift amount is bigger than or equal to
16914 // the element size. The constant shift amount will be
16915 // encoded as a 8-bit immediate.
16916 if (ShiftAmt.trunc(8).uge(MaxAmount))
16917 return getZeroVector(VT, Subtarget, DAG, DL);
16924 /// PerformShiftCombine - Combine shifts.
16925 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
16926 TargetLowering::DAGCombinerInfo &DCI,
16927 const X86Subtarget *Subtarget) {
16928 if (N->getOpcode() == ISD::SHL) {
16929 SDValue V = PerformSHLCombine(N, DAG);
16930 if (V.getNode()) return V;
16933 if (N->getOpcode() != ISD::SRA) {
16934 // Try to fold this logical shift into a zero vector.
16935 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
16936 if (V.getNode()) return V;
16942 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
16943 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
16944 // and friends. Likewise for OR -> CMPNEQSS.
16945 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
16946 TargetLowering::DAGCombinerInfo &DCI,
16947 const X86Subtarget *Subtarget) {
16950 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
16951 // we're requiring SSE2 for both.
16952 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
16953 SDValue N0 = N->getOperand(0);
16954 SDValue N1 = N->getOperand(1);
16955 SDValue CMP0 = N0->getOperand(1);
16956 SDValue CMP1 = N1->getOperand(1);
16959 // The SETCCs should both refer to the same CMP.
16960 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
16963 SDValue CMP00 = CMP0->getOperand(0);
16964 SDValue CMP01 = CMP0->getOperand(1);
16965 EVT VT = CMP00.getValueType();
16967 if (VT == MVT::f32 || VT == MVT::f64) {
16968 bool ExpectingFlags = false;
16969 // Check for any users that want flags:
16970 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
16971 !ExpectingFlags && UI != UE; ++UI)
16972 switch (UI->getOpcode()) {
16977 ExpectingFlags = true;
16979 case ISD::CopyToReg:
16980 case ISD::SIGN_EXTEND:
16981 case ISD::ZERO_EXTEND:
16982 case ISD::ANY_EXTEND:
16986 if (!ExpectingFlags) {
16987 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
16988 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
16990 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
16991 X86::CondCode tmp = cc0;
16996 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
16997 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
16998 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
16999 X86ISD::NodeType NTOperator = is64BitFP ?
17000 X86ISD::FSETCCsd : X86ISD::FSETCCss;
17001 // FIXME: need symbolic constants for these magic numbers.
17002 // See X86ATTInstPrinter.cpp:printSSECC().
17003 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
17004 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
17005 DAG.getConstant(x86cc, MVT::i8));
17006 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
17008 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
17009 DAG.getConstant(1, MVT::i32));
17010 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
17011 return OneBitOfTruth;
17019 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
17020 /// so it can be folded inside ANDNP.
17021 static bool CanFoldXORWithAllOnes(const SDNode *N) {
17022 EVT VT = N->getValueType(0);
17024 // Match direct AllOnes for 128 and 256-bit vectors
17025 if (ISD::isBuildVectorAllOnes(N))
17028 // Look through a bit convert.
17029 if (N->getOpcode() == ISD::BITCAST)
17030 N = N->getOperand(0).getNode();
17032 // Sometimes the operand may come from a insert_subvector building a 256-bit
17034 if (VT.is256BitVector() &&
17035 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
17036 SDValue V1 = N->getOperand(0);
17037 SDValue V2 = N->getOperand(1);
17039 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
17040 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
17041 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
17042 ISD::isBuildVectorAllOnes(V2.getNode()))
17049 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
17050 // register. In most cases we actually compare or select YMM-sized registers
17051 // and mixing the two types creates horrible code. This method optimizes
17052 // some of the transition sequences.
17053 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
17054 TargetLowering::DAGCombinerInfo &DCI,
17055 const X86Subtarget *Subtarget) {
17056 EVT VT = N->getValueType(0);
17057 if (!VT.is256BitVector())
17060 assert((N->getOpcode() == ISD::ANY_EXTEND ||
17061 N->getOpcode() == ISD::ZERO_EXTEND ||
17062 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
17064 SDValue Narrow = N->getOperand(0);
17065 EVT NarrowVT = Narrow->getValueType(0);
17066 if (!NarrowVT.is128BitVector())
17069 if (Narrow->getOpcode() != ISD::XOR &&
17070 Narrow->getOpcode() != ISD::AND &&
17071 Narrow->getOpcode() != ISD::OR)
17074 SDValue N0 = Narrow->getOperand(0);
17075 SDValue N1 = Narrow->getOperand(1);
17078 // The Left side has to be a trunc.
17079 if (N0.getOpcode() != ISD::TRUNCATE)
17082 // The type of the truncated inputs.
17083 EVT WideVT = N0->getOperand(0)->getValueType(0);
17087 // The right side has to be a 'trunc' or a constant vector.
17088 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
17089 bool RHSConst = (isSplatVector(N1.getNode()) &&
17090 isa<ConstantSDNode>(N1->getOperand(0)));
17091 if (!RHSTrunc && !RHSConst)
17094 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17096 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
17099 // Set N0 and N1 to hold the inputs to the new wide operation.
17100 N0 = N0->getOperand(0);
17102 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
17103 N1->getOperand(0));
17104 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
17105 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, &C[0], C.size());
17106 } else if (RHSTrunc) {
17107 N1 = N1->getOperand(0);
17110 // Generate the wide operation.
17111 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
17112 unsigned Opcode = N->getOpcode();
17114 case ISD::ANY_EXTEND:
17116 case ISD::ZERO_EXTEND: {
17117 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
17118 APInt Mask = APInt::getAllOnesValue(InBits);
17119 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
17120 return DAG.getNode(ISD::AND, DL, VT,
17121 Op, DAG.getConstant(Mask, VT));
17123 case ISD::SIGN_EXTEND:
17124 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
17125 Op, DAG.getValueType(NarrowVT));
17127 llvm_unreachable("Unexpected opcode");
17131 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
17132 TargetLowering::DAGCombinerInfo &DCI,
17133 const X86Subtarget *Subtarget) {
17134 EVT VT = N->getValueType(0);
17135 if (DCI.isBeforeLegalizeOps())
17138 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
17142 // Create BLSI, and BLSR instructions
17143 // BLSI is X & (-X)
17144 // BLSR is X & (X-1)
17145 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
17146 SDValue N0 = N->getOperand(0);
17147 SDValue N1 = N->getOperand(1);
17150 // Check LHS for neg
17151 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
17152 isZero(N0.getOperand(0)))
17153 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
17155 // Check RHS for neg
17156 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
17157 isZero(N1.getOperand(0)))
17158 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
17160 // Check LHS for X-1
17161 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
17162 isAllOnes(N0.getOperand(1)))
17163 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
17165 // Check RHS for X-1
17166 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
17167 isAllOnes(N1.getOperand(1)))
17168 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
17173 // Want to form ANDNP nodes:
17174 // 1) In the hopes of then easily combining them with OR and AND nodes
17175 // to form PBLEND/PSIGN.
17176 // 2) To match ANDN packed intrinsics
17177 if (VT != MVT::v2i64 && VT != MVT::v4i64)
17180 SDValue N0 = N->getOperand(0);
17181 SDValue N1 = N->getOperand(1);
17184 // Check LHS for vnot
17185 if (N0.getOpcode() == ISD::XOR &&
17186 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
17187 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
17188 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
17190 // Check RHS for vnot
17191 if (N1.getOpcode() == ISD::XOR &&
17192 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
17193 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
17194 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
17199 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
17200 TargetLowering::DAGCombinerInfo &DCI,
17201 const X86Subtarget *Subtarget) {
17202 EVT VT = N->getValueType(0);
17203 if (DCI.isBeforeLegalizeOps())
17206 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
17210 SDValue N0 = N->getOperand(0);
17211 SDValue N1 = N->getOperand(1);
17213 // look for psign/blend
17214 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
17215 if (!Subtarget->hasSSSE3() ||
17216 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
17219 // Canonicalize pandn to RHS
17220 if (N0.getOpcode() == X86ISD::ANDNP)
17222 // or (and (m, y), (pandn m, x))
17223 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
17224 SDValue Mask = N1.getOperand(0);
17225 SDValue X = N1.getOperand(1);
17227 if (N0.getOperand(0) == Mask)
17228 Y = N0.getOperand(1);
17229 if (N0.getOperand(1) == Mask)
17230 Y = N0.getOperand(0);
17232 // Check to see if the mask appeared in both the AND and ANDNP and
17236 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
17237 // Look through mask bitcast.
17238 if (Mask.getOpcode() == ISD::BITCAST)
17239 Mask = Mask.getOperand(0);
17240 if (X.getOpcode() == ISD::BITCAST)
17241 X = X.getOperand(0);
17242 if (Y.getOpcode() == ISD::BITCAST)
17243 Y = Y.getOperand(0);
17245 EVT MaskVT = Mask.getValueType();
17247 // Validate that the Mask operand is a vector sra node.
17248 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
17249 // there is no psrai.b
17250 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
17251 unsigned SraAmt = ~0;
17252 if (Mask.getOpcode() == ISD::SRA) {
17253 SDValue Amt = Mask.getOperand(1);
17254 if (isSplatVector(Amt.getNode())) {
17255 SDValue SclrAmt = Amt->getOperand(0);
17256 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt))
17257 SraAmt = C->getZExtValue();
17259 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
17260 SDValue SraC = Mask.getOperand(1);
17261 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
17263 if ((SraAmt + 1) != EltBits)
17268 // Now we know we at least have a plendvb with the mask val. See if
17269 // we can form a psignb/w/d.
17270 // psign = x.type == y.type == mask.type && y = sub(0, x);
17271 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
17272 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
17273 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
17274 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
17275 "Unsupported VT for PSIGN");
17276 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
17277 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
17279 // PBLENDVB only available on SSE 4.1
17280 if (!Subtarget->hasSSE41())
17283 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
17285 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
17286 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
17287 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
17288 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
17289 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
17293 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
17296 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
17297 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
17299 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
17301 if (!N0.hasOneUse() || !N1.hasOneUse())
17304 SDValue ShAmt0 = N0.getOperand(1);
17305 if (ShAmt0.getValueType() != MVT::i8)
17307 SDValue ShAmt1 = N1.getOperand(1);
17308 if (ShAmt1.getValueType() != MVT::i8)
17310 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
17311 ShAmt0 = ShAmt0.getOperand(0);
17312 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
17313 ShAmt1 = ShAmt1.getOperand(0);
17316 unsigned Opc = X86ISD::SHLD;
17317 SDValue Op0 = N0.getOperand(0);
17318 SDValue Op1 = N1.getOperand(0);
17319 if (ShAmt0.getOpcode() == ISD::SUB) {
17320 Opc = X86ISD::SHRD;
17321 std::swap(Op0, Op1);
17322 std::swap(ShAmt0, ShAmt1);
17325 unsigned Bits = VT.getSizeInBits();
17326 if (ShAmt1.getOpcode() == ISD::SUB) {
17327 SDValue Sum = ShAmt1.getOperand(0);
17328 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
17329 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
17330 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
17331 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
17332 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
17333 return DAG.getNode(Opc, DL, VT,
17335 DAG.getNode(ISD::TRUNCATE, DL,
17338 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
17339 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
17341 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
17342 return DAG.getNode(Opc, DL, VT,
17343 N0.getOperand(0), N1.getOperand(0),
17344 DAG.getNode(ISD::TRUNCATE, DL,
17351 // Generate NEG and CMOV for integer abs.
17352 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
17353 EVT VT = N->getValueType(0);
17355 // Since X86 does not have CMOV for 8-bit integer, we don't convert
17356 // 8-bit integer abs to NEG and CMOV.
17357 if (VT.isInteger() && VT.getSizeInBits() == 8)
17360 SDValue N0 = N->getOperand(0);
17361 SDValue N1 = N->getOperand(1);
17364 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
17365 // and change it to SUB and CMOV.
17366 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
17367 N0.getOpcode() == ISD::ADD &&
17368 N0.getOperand(1) == N1 &&
17369 N1.getOpcode() == ISD::SRA &&
17370 N1.getOperand(0) == N0.getOperand(0))
17371 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
17372 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
17373 // Generate SUB & CMOV.
17374 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
17375 DAG.getConstant(0, VT), N0.getOperand(0));
17377 SDValue Ops[] = { N0.getOperand(0), Neg,
17378 DAG.getConstant(X86::COND_GE, MVT::i8),
17379 SDValue(Neg.getNode(), 1) };
17380 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
17381 Ops, array_lengthof(Ops));
17386 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
17387 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
17388 TargetLowering::DAGCombinerInfo &DCI,
17389 const X86Subtarget *Subtarget) {
17390 EVT VT = N->getValueType(0);
17391 if (DCI.isBeforeLegalizeOps())
17394 if (Subtarget->hasCMov()) {
17395 SDValue RV = performIntegerAbsCombine(N, DAG);
17400 // Try forming BMI if it is available.
17401 if (!Subtarget->hasBMI())
17404 if (VT != MVT::i32 && VT != MVT::i64)
17407 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
17409 // Create BLSMSK instructions by finding X ^ (X-1)
17410 SDValue N0 = N->getOperand(0);
17411 SDValue N1 = N->getOperand(1);
17414 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
17415 isAllOnes(N0.getOperand(1)))
17416 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
17418 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
17419 isAllOnes(N1.getOperand(1)))
17420 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
17425 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
17426 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
17427 TargetLowering::DAGCombinerInfo &DCI,
17428 const X86Subtarget *Subtarget) {
17429 LoadSDNode *Ld = cast<LoadSDNode>(N);
17430 EVT RegVT = Ld->getValueType(0);
17431 EVT MemVT = Ld->getMemoryVT();
17433 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17434 unsigned RegSz = RegVT.getSizeInBits();
17436 // On Sandybridge unaligned 256bit loads are inefficient.
17437 ISD::LoadExtType Ext = Ld->getExtensionType();
17438 unsigned Alignment = Ld->getAlignment();
17439 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
17440 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
17441 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
17442 unsigned NumElems = RegVT.getVectorNumElements();
17446 SDValue Ptr = Ld->getBasePtr();
17447 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
17449 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
17451 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
17452 Ld->getPointerInfo(), Ld->isVolatile(),
17453 Ld->isNonTemporal(), Ld->isInvariant(),
17455 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
17456 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
17457 Ld->getPointerInfo(), Ld->isVolatile(),
17458 Ld->isNonTemporal(), Ld->isInvariant(),
17459 std::min(16U, Alignment));
17460 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
17462 Load2.getValue(1));
17464 SDValue NewVec = DAG.getUNDEF(RegVT);
17465 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
17466 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
17467 return DCI.CombineTo(N, NewVec, TF, true);
17470 // If this is a vector EXT Load then attempt to optimize it using a
17471 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
17472 // expansion is still better than scalar code.
17473 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll
17474 // emit a shuffle and a arithmetic shift.
17475 // TODO: It is possible to support ZExt by zeroing the undef values
17476 // during the shuffle phase or after the shuffle.
17477 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() &&
17478 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) {
17479 assert(MemVT != RegVT && "Cannot extend to the same type");
17480 assert(MemVT.isVector() && "Must load a vector from memory");
17482 unsigned NumElems = RegVT.getVectorNumElements();
17483 unsigned MemSz = MemVT.getSizeInBits();
17484 assert(RegSz > MemSz && "Register size must be greater than the mem size");
17486 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())
17489 // All sizes must be a power of two.
17490 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
17493 // Attempt to load the original value using scalar loads.
17494 // Find the largest scalar type that divides the total loaded size.
17495 MVT SclrLoadTy = MVT::i8;
17496 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
17497 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
17498 MVT Tp = (MVT::SimpleValueType)tp;
17499 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
17504 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
17505 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
17507 SclrLoadTy = MVT::f64;
17509 // Calculate the number of scalar loads that we need to perform
17510 // in order to load our vector from memory.
17511 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
17512 if (Ext == ISD::SEXTLOAD && NumLoads > 1)
17515 unsigned loadRegZize = RegSz;
17516 if (Ext == ISD::SEXTLOAD && RegSz == 256)
17519 // Represent our vector as a sequence of elements which are the
17520 // largest scalar that we can load.
17521 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
17522 loadRegZize/SclrLoadTy.getSizeInBits());
17524 // Represent the data using the same element type that is stored in
17525 // memory. In practice, we ''widen'' MemVT.
17527 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
17528 loadRegZize/MemVT.getScalarType().getSizeInBits());
17530 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
17531 "Invalid vector type");
17533 // We can't shuffle using an illegal type.
17534 if (!TLI.isTypeLegal(WideVecVT))
17537 SmallVector<SDValue, 8> Chains;
17538 SDValue Ptr = Ld->getBasePtr();
17539 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
17540 TLI.getPointerTy());
17541 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
17543 for (unsigned i = 0; i < NumLoads; ++i) {
17544 // Perform a single load.
17545 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
17546 Ptr, Ld->getPointerInfo(),
17547 Ld->isVolatile(), Ld->isNonTemporal(),
17548 Ld->isInvariant(), Ld->getAlignment());
17549 Chains.push_back(ScalarLoad.getValue(1));
17550 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
17551 // another round of DAGCombining.
17553 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
17555 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
17556 ScalarLoad, DAG.getIntPtrConstant(i));
17558 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
17561 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
17564 // Bitcast the loaded value to a vector of the original element type, in
17565 // the size of the target vector type.
17566 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
17567 unsigned SizeRatio = RegSz/MemSz;
17569 if (Ext == ISD::SEXTLOAD) {
17570 // If we have SSE4.1 we can directly emit a VSEXT node.
17571 if (Subtarget->hasSSE41()) {
17572 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
17573 return DCI.CombineTo(N, Sext, TF, true);
17576 // Otherwise we'll shuffle the small elements in the high bits of the
17577 // larger type and perform an arithmetic shift. If the shift is not legal
17578 // it's better to scalarize.
17579 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
17582 // Redistribute the loaded elements into the different locations.
17583 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
17584 for (unsigned i = 0; i != NumElems; ++i)
17585 ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
17587 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
17588 DAG.getUNDEF(WideVecVT),
17591 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
17593 // Build the arithmetic shift.
17594 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
17595 MemVT.getVectorElementType().getSizeInBits();
17596 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
17597 DAG.getConstant(Amt, RegVT));
17599 return DCI.CombineTo(N, Shuff, TF, true);
17602 // Redistribute the loaded elements into the different locations.
17603 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
17604 for (unsigned i = 0; i != NumElems; ++i)
17605 ShuffleVec[i*SizeRatio] = i;
17607 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
17608 DAG.getUNDEF(WideVecVT),
17611 // Bitcast to the requested type.
17612 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
17613 // Replace the original load with the new sequence
17614 // and return the new chain.
17615 return DCI.CombineTo(N, Shuff, TF, true);
17621 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
17622 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
17623 const X86Subtarget *Subtarget) {
17624 StoreSDNode *St = cast<StoreSDNode>(N);
17625 EVT VT = St->getValue().getValueType();
17626 EVT StVT = St->getMemoryVT();
17628 SDValue StoredVal = St->getOperand(1);
17629 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17631 // If we are saving a concatenation of two XMM registers, perform two stores.
17632 // On Sandy Bridge, 256-bit memory operations are executed by two
17633 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
17634 // memory operation.
17635 unsigned Alignment = St->getAlignment();
17636 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
17637 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
17638 StVT == VT && !IsAligned) {
17639 unsigned NumElems = VT.getVectorNumElements();
17643 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
17644 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
17646 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
17647 SDValue Ptr0 = St->getBasePtr();
17648 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
17650 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
17651 St->getPointerInfo(), St->isVolatile(),
17652 St->isNonTemporal(), Alignment);
17653 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
17654 St->getPointerInfo(), St->isVolatile(),
17655 St->isNonTemporal(),
17656 std::min(16U, Alignment));
17657 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
17660 // Optimize trunc store (of multiple scalars) to shuffle and store.
17661 // First, pack all of the elements in one place. Next, store to memory
17662 // in fewer chunks.
17663 if (St->isTruncatingStore() && VT.isVector()) {
17664 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17665 unsigned NumElems = VT.getVectorNumElements();
17666 assert(StVT != VT && "Cannot truncate to the same type");
17667 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
17668 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
17670 // From, To sizes and ElemCount must be pow of two
17671 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
17672 // We are going to use the original vector elt for storing.
17673 // Accumulated smaller vector elements must be a multiple of the store size.
17674 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
17676 unsigned SizeRatio = FromSz / ToSz;
17678 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
17680 // Create a type on which we perform the shuffle
17681 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
17682 StVT.getScalarType(), NumElems*SizeRatio);
17684 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
17686 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
17687 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
17688 for (unsigned i = 0; i != NumElems; ++i)
17689 ShuffleVec[i] = i * SizeRatio;
17691 // Can't shuffle using an illegal type.
17692 if (!TLI.isTypeLegal(WideVecVT))
17695 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
17696 DAG.getUNDEF(WideVecVT),
17698 // At this point all of the data is stored at the bottom of the
17699 // register. We now need to save it to mem.
17701 // Find the largest store unit
17702 MVT StoreType = MVT::i8;
17703 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
17704 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
17705 MVT Tp = (MVT::SimpleValueType)tp;
17706 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
17710 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
17711 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
17712 (64 <= NumElems * ToSz))
17713 StoreType = MVT::f64;
17715 // Bitcast the original vector into a vector of store-size units
17716 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
17717 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
17718 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
17719 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
17720 SmallVector<SDValue, 8> Chains;
17721 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
17722 TLI.getPointerTy());
17723 SDValue Ptr = St->getBasePtr();
17725 // Perform one or more big stores into memory.
17726 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
17727 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
17728 StoreType, ShuffWide,
17729 DAG.getIntPtrConstant(i));
17730 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
17731 St->getPointerInfo(), St->isVolatile(),
17732 St->isNonTemporal(), St->getAlignment());
17733 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
17734 Chains.push_back(Ch);
17737 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
17741 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
17742 // the FP state in cases where an emms may be missing.
17743 // A preferable solution to the general problem is to figure out the right
17744 // places to insert EMMS. This qualifies as a quick hack.
17746 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
17747 if (VT.getSizeInBits() != 64)
17750 const Function *F = DAG.getMachineFunction().getFunction();
17751 bool NoImplicitFloatOps = F->getAttributes().
17752 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
17753 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
17754 && Subtarget->hasSSE2();
17755 if ((VT.isVector() ||
17756 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
17757 isa<LoadSDNode>(St->getValue()) &&
17758 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
17759 St->getChain().hasOneUse() && !St->isVolatile()) {
17760 SDNode* LdVal = St->getValue().getNode();
17761 LoadSDNode *Ld = 0;
17762 int TokenFactorIndex = -1;
17763 SmallVector<SDValue, 8> Ops;
17764 SDNode* ChainVal = St->getChain().getNode();
17765 // Must be a store of a load. We currently handle two cases: the load
17766 // is a direct child, and it's under an intervening TokenFactor. It is
17767 // possible to dig deeper under nested TokenFactors.
17768 if (ChainVal == LdVal)
17769 Ld = cast<LoadSDNode>(St->getChain());
17770 else if (St->getValue().hasOneUse() &&
17771 ChainVal->getOpcode() == ISD::TokenFactor) {
17772 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
17773 if (ChainVal->getOperand(i).getNode() == LdVal) {
17774 TokenFactorIndex = i;
17775 Ld = cast<LoadSDNode>(St->getValue());
17777 Ops.push_back(ChainVal->getOperand(i));
17781 if (!Ld || !ISD::isNormalLoad(Ld))
17784 // If this is not the MMX case, i.e. we are just turning i64 load/store
17785 // into f64 load/store, avoid the transformation if there are multiple
17786 // uses of the loaded value.
17787 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
17792 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
17793 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
17795 if (Subtarget->is64Bit() || F64IsLegal) {
17796 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
17797 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
17798 Ld->getPointerInfo(), Ld->isVolatile(),
17799 Ld->isNonTemporal(), Ld->isInvariant(),
17800 Ld->getAlignment());
17801 SDValue NewChain = NewLd.getValue(1);
17802 if (TokenFactorIndex != -1) {
17803 Ops.push_back(NewChain);
17804 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
17807 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
17808 St->getPointerInfo(),
17809 St->isVolatile(), St->isNonTemporal(),
17810 St->getAlignment());
17813 // Otherwise, lower to two pairs of 32-bit loads / stores.
17814 SDValue LoAddr = Ld->getBasePtr();
17815 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
17816 DAG.getConstant(4, MVT::i32));
17818 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
17819 Ld->getPointerInfo(),
17820 Ld->isVolatile(), Ld->isNonTemporal(),
17821 Ld->isInvariant(), Ld->getAlignment());
17822 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
17823 Ld->getPointerInfo().getWithOffset(4),
17824 Ld->isVolatile(), Ld->isNonTemporal(),
17826 MinAlign(Ld->getAlignment(), 4));
17828 SDValue NewChain = LoLd.getValue(1);
17829 if (TokenFactorIndex != -1) {
17830 Ops.push_back(LoLd);
17831 Ops.push_back(HiLd);
17832 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
17836 LoAddr = St->getBasePtr();
17837 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
17838 DAG.getConstant(4, MVT::i32));
17840 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
17841 St->getPointerInfo(),
17842 St->isVolatile(), St->isNonTemporal(),
17843 St->getAlignment());
17844 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
17845 St->getPointerInfo().getWithOffset(4),
17847 St->isNonTemporal(),
17848 MinAlign(St->getAlignment(), 4));
17849 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
17854 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
17855 /// and return the operands for the horizontal operation in LHS and RHS. A
17856 /// horizontal operation performs the binary operation on successive elements
17857 /// of its first operand, then on successive elements of its second operand,
17858 /// returning the resulting values in a vector. For example, if
17859 /// A = < float a0, float a1, float a2, float a3 >
17861 /// B = < float b0, float b1, float b2, float b3 >
17862 /// then the result of doing a horizontal operation on A and B is
17863 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
17864 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
17865 /// A horizontal-op B, for some already available A and B, and if so then LHS is
17866 /// set to A, RHS to B, and the routine returns 'true'.
17867 /// Note that the binary operation should have the property that if one of the
17868 /// operands is UNDEF then the result is UNDEF.
17869 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
17870 // Look for the following pattern: if
17871 // A = < float a0, float a1, float a2, float a3 >
17872 // B = < float b0, float b1, float b2, float b3 >
17874 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
17875 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
17876 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
17877 // which is A horizontal-op B.
17879 // At least one of the operands should be a vector shuffle.
17880 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
17881 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
17884 MVT VT = LHS.getValueType().getSimpleVT();
17886 assert((VT.is128BitVector() || VT.is256BitVector()) &&
17887 "Unsupported vector type for horizontal add/sub");
17889 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
17890 // operate independently on 128-bit lanes.
17891 unsigned NumElts = VT.getVectorNumElements();
17892 unsigned NumLanes = VT.getSizeInBits()/128;
17893 unsigned NumLaneElts = NumElts / NumLanes;
17894 assert((NumLaneElts % 2 == 0) &&
17895 "Vector type should have an even number of elements in each lane");
17896 unsigned HalfLaneElts = NumLaneElts/2;
17898 // View LHS in the form
17899 // LHS = VECTOR_SHUFFLE A, B, LMask
17900 // If LHS is not a shuffle then pretend it is the shuffle
17901 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
17902 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
17905 SmallVector<int, 16> LMask(NumElts);
17906 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
17907 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
17908 A = LHS.getOperand(0);
17909 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
17910 B = LHS.getOperand(1);
17911 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
17912 std::copy(Mask.begin(), Mask.end(), LMask.begin());
17914 if (LHS.getOpcode() != ISD::UNDEF)
17916 for (unsigned i = 0; i != NumElts; ++i)
17920 // Likewise, view RHS in the form
17921 // RHS = VECTOR_SHUFFLE C, D, RMask
17923 SmallVector<int, 16> RMask(NumElts);
17924 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
17925 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
17926 C = RHS.getOperand(0);
17927 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
17928 D = RHS.getOperand(1);
17929 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
17930 std::copy(Mask.begin(), Mask.end(), RMask.begin());
17932 if (RHS.getOpcode() != ISD::UNDEF)
17934 for (unsigned i = 0; i != NumElts; ++i)
17938 // Check that the shuffles are both shuffling the same vectors.
17939 if (!(A == C && B == D) && !(A == D && B == C))
17942 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
17943 if (!A.getNode() && !B.getNode())
17946 // If A and B occur in reverse order in RHS, then "swap" them (which means
17947 // rewriting the mask).
17949 CommuteVectorShuffleMask(RMask, NumElts);
17951 // At this point LHS and RHS are equivalent to
17952 // LHS = VECTOR_SHUFFLE A, B, LMask
17953 // RHS = VECTOR_SHUFFLE A, B, RMask
17954 // Check that the masks correspond to performing a horizontal operation.
17955 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
17956 for (unsigned i = 0; i != NumLaneElts; ++i) {
17957 int LIdx = LMask[i+l], RIdx = RMask[i+l];
17959 // Ignore any UNDEF components.
17960 if (LIdx < 0 || RIdx < 0 ||
17961 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
17962 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
17965 // Check that successive elements are being operated on. If not, this is
17966 // not a horizontal operation.
17967 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
17968 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
17969 if (!(LIdx == Index && RIdx == Index + 1) &&
17970 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
17975 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
17976 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
17980 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
17981 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
17982 const X86Subtarget *Subtarget) {
17983 EVT VT = N->getValueType(0);
17984 SDValue LHS = N->getOperand(0);
17985 SDValue RHS = N->getOperand(1);
17987 // Try to synthesize horizontal adds from adds of shuffles.
17988 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
17989 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
17990 isHorizontalBinOp(LHS, RHS, true))
17991 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
17995 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
17996 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
17997 const X86Subtarget *Subtarget) {
17998 EVT VT = N->getValueType(0);
17999 SDValue LHS = N->getOperand(0);
18000 SDValue RHS = N->getOperand(1);
18002 // Try to synthesize horizontal subs from subs of shuffles.
18003 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18004 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18005 isHorizontalBinOp(LHS, RHS, false))
18006 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
18010 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
18011 /// X86ISD::FXOR nodes.
18012 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
18013 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
18014 // F[X]OR(0.0, x) -> x
18015 // F[X]OR(x, 0.0) -> x
18016 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18017 if (C->getValueAPF().isPosZero())
18018 return N->getOperand(1);
18019 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18020 if (C->getValueAPF().isPosZero())
18021 return N->getOperand(0);
18025 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
18026 /// X86ISD::FMAX nodes.
18027 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
18028 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
18030 // Only perform optimizations if UnsafeMath is used.
18031 if (!DAG.getTarget().Options.UnsafeFPMath)
18034 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
18035 // into FMINC and FMAXC, which are Commutative operations.
18036 unsigned NewOp = 0;
18037 switch (N->getOpcode()) {
18038 default: llvm_unreachable("unknown opcode");
18039 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
18040 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
18043 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
18044 N->getOperand(0), N->getOperand(1));
18047 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
18048 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
18049 // FAND(0.0, x) -> 0.0
18050 // FAND(x, 0.0) -> 0.0
18051 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18052 if (C->getValueAPF().isPosZero())
18053 return N->getOperand(0);
18054 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18055 if (C->getValueAPF().isPosZero())
18056 return N->getOperand(1);
18060 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
18061 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
18062 // FANDN(x, 0.0) -> 0.0
18063 // FANDN(0.0, x) -> x
18064 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18065 if (C->getValueAPF().isPosZero())
18066 return N->getOperand(1);
18067 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18068 if (C->getValueAPF().isPosZero())
18069 return N->getOperand(1);
18073 static SDValue PerformBTCombine(SDNode *N,
18075 TargetLowering::DAGCombinerInfo &DCI) {
18076 // BT ignores high bits in the bit index operand.
18077 SDValue Op1 = N->getOperand(1);
18078 if (Op1.hasOneUse()) {
18079 unsigned BitWidth = Op1.getValueSizeInBits();
18080 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
18081 APInt KnownZero, KnownOne;
18082 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
18083 !DCI.isBeforeLegalizeOps());
18084 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18085 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
18086 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
18087 DCI.CommitTargetLoweringOpt(TLO);
18092 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
18093 SDValue Op = N->getOperand(0);
18094 if (Op.getOpcode() == ISD::BITCAST)
18095 Op = Op.getOperand(0);
18096 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
18097 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
18098 VT.getVectorElementType().getSizeInBits() ==
18099 OpVT.getVectorElementType().getSizeInBits()) {
18100 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
18105 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
18106 const X86Subtarget *Subtarget) {
18107 EVT VT = N->getValueType(0);
18108 if (!VT.isVector())
18111 SDValue N0 = N->getOperand(0);
18112 SDValue N1 = N->getOperand(1);
18113 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
18116 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
18117 // both SSE and AVX2 since there is no sign-extended shift right
18118 // operation on a vector with 64-bit elements.
18119 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
18120 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
18121 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
18122 N0.getOpcode() == ISD::SIGN_EXTEND)) {
18123 SDValue N00 = N0.getOperand(0);
18125 // EXTLOAD has a better solution on AVX2,
18126 // it may be replaced with X86ISD::VSEXT node.
18127 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
18128 if (!ISD::isNormalLoad(N00.getNode()))
18131 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
18132 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
18134 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
18140 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
18141 TargetLowering::DAGCombinerInfo &DCI,
18142 const X86Subtarget *Subtarget) {
18143 if (!DCI.isBeforeLegalizeOps())
18146 if (!Subtarget->hasFp256())
18149 EVT VT = N->getValueType(0);
18150 if (VT.isVector() && VT.getSizeInBits() == 256) {
18151 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
18159 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
18160 const X86Subtarget* Subtarget) {
18162 EVT VT = N->getValueType(0);
18164 // Let legalize expand this if it isn't a legal type yet.
18165 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18168 EVT ScalarVT = VT.getScalarType();
18169 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
18170 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
18173 SDValue A = N->getOperand(0);
18174 SDValue B = N->getOperand(1);
18175 SDValue C = N->getOperand(2);
18177 bool NegA = (A.getOpcode() == ISD::FNEG);
18178 bool NegB = (B.getOpcode() == ISD::FNEG);
18179 bool NegC = (C.getOpcode() == ISD::FNEG);
18181 // Negative multiplication when NegA xor NegB
18182 bool NegMul = (NegA != NegB);
18184 A = A.getOperand(0);
18186 B = B.getOperand(0);
18188 C = C.getOperand(0);
18192 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
18194 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
18196 return DAG.getNode(Opcode, dl, VT, A, B, C);
18199 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
18200 TargetLowering::DAGCombinerInfo &DCI,
18201 const X86Subtarget *Subtarget) {
18202 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
18203 // (and (i32 x86isd::setcc_carry), 1)
18204 // This eliminates the zext. This transformation is necessary because
18205 // ISD::SETCC is always legalized to i8.
18207 SDValue N0 = N->getOperand(0);
18208 EVT VT = N->getValueType(0);
18210 if (N0.getOpcode() == ISD::AND &&
18212 N0.getOperand(0).hasOneUse()) {
18213 SDValue N00 = N0.getOperand(0);
18214 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
18215 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
18216 if (!C || C->getZExtValue() != 1)
18218 return DAG.getNode(ISD::AND, dl, VT,
18219 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
18220 N00.getOperand(0), N00.getOperand(1)),
18221 DAG.getConstant(1, VT));
18225 if (VT.is256BitVector()) {
18226 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
18234 // Optimize x == -y --> x+y == 0
18235 // x != -y --> x+y != 0
18236 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
18237 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
18238 SDValue LHS = N->getOperand(0);
18239 SDValue RHS = N->getOperand(1);
18241 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
18242 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
18243 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
18244 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
18245 LHS.getValueType(), RHS, LHS.getOperand(1));
18246 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
18247 addV, DAG.getConstant(0, addV.getValueType()), CC);
18249 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
18250 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
18251 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
18252 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
18253 RHS.getValueType(), LHS, RHS.getOperand(1));
18254 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
18255 addV, DAG.getConstant(0, addV.getValueType()), CC);
18260 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
18261 // as "sbb reg,reg", since it can be extended without zext and produces
18262 // an all-ones bit which is more useful than 0/1 in some cases.
18263 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG) {
18264 return DAG.getNode(ISD::AND, DL, MVT::i8,
18265 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
18266 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
18267 DAG.getConstant(1, MVT::i8));
18270 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
18271 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
18272 TargetLowering::DAGCombinerInfo &DCI,
18273 const X86Subtarget *Subtarget) {
18275 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
18276 SDValue EFLAGS = N->getOperand(1);
18278 if (CC == X86::COND_A) {
18279 // Try to convert COND_A into COND_B in an attempt to facilitate
18280 // materializing "setb reg".
18282 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
18283 // cannot take an immediate as its first operand.
18285 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
18286 EFLAGS.getValueType().isInteger() &&
18287 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
18288 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
18289 EFLAGS.getNode()->getVTList(),
18290 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
18291 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
18292 return MaterializeSETB(DL, NewEFLAGS, DAG);
18296 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
18297 // a zext and produces an all-ones bit which is more useful than 0/1 in some
18299 if (CC == X86::COND_B)
18300 return MaterializeSETB(DL, EFLAGS, DAG);
18304 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
18305 if (Flags.getNode()) {
18306 SDValue Cond = DAG.getConstant(CC, MVT::i8);
18307 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
18313 // Optimize branch condition evaluation.
18315 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
18316 TargetLowering::DAGCombinerInfo &DCI,
18317 const X86Subtarget *Subtarget) {
18319 SDValue Chain = N->getOperand(0);
18320 SDValue Dest = N->getOperand(1);
18321 SDValue EFLAGS = N->getOperand(3);
18322 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
18326 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
18327 if (Flags.getNode()) {
18328 SDValue Cond = DAG.getConstant(CC, MVT::i8);
18329 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
18336 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
18337 const X86TargetLowering *XTLI) {
18338 SDValue Op0 = N->getOperand(0);
18339 EVT InVT = Op0->getValueType(0);
18341 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
18342 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
18344 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
18345 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
18346 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
18349 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
18350 // a 32-bit target where SSE doesn't support i64->FP operations.
18351 if (Op0.getOpcode() == ISD::LOAD) {
18352 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
18353 EVT VT = Ld->getValueType(0);
18354 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
18355 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
18356 !XTLI->getSubtarget()->is64Bit() &&
18357 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
18358 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
18359 Ld->getChain(), Op0, DAG);
18360 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
18367 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
18368 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
18369 X86TargetLowering::DAGCombinerInfo &DCI) {
18370 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
18371 // the result is either zero or one (depending on the input carry bit).
18372 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
18373 if (X86::isZeroNode(N->getOperand(0)) &&
18374 X86::isZeroNode(N->getOperand(1)) &&
18375 // We don't have a good way to replace an EFLAGS use, so only do this when
18377 SDValue(N, 1).use_empty()) {
18379 EVT VT = N->getValueType(0);
18380 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
18381 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
18382 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
18383 DAG.getConstant(X86::COND_B,MVT::i8),
18385 DAG.getConstant(1, VT));
18386 return DCI.CombineTo(N, Res1, CarryOut);
18392 // fold (add Y, (sete X, 0)) -> adc 0, Y
18393 // (add Y, (setne X, 0)) -> sbb -1, Y
18394 // (sub (sete X, 0), Y) -> sbb 0, Y
18395 // (sub (setne X, 0), Y) -> adc -1, Y
18396 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
18399 // Look through ZExts.
18400 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
18401 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
18404 SDValue SetCC = Ext.getOperand(0);
18405 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
18408 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
18409 if (CC != X86::COND_E && CC != X86::COND_NE)
18412 SDValue Cmp = SetCC.getOperand(1);
18413 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
18414 !X86::isZeroNode(Cmp.getOperand(1)) ||
18415 !Cmp.getOperand(0).getValueType().isInteger())
18418 SDValue CmpOp0 = Cmp.getOperand(0);
18419 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
18420 DAG.getConstant(1, CmpOp0.getValueType()));
18422 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
18423 if (CC == X86::COND_NE)
18424 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
18425 DL, OtherVal.getValueType(), OtherVal,
18426 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
18427 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
18428 DL, OtherVal.getValueType(), OtherVal,
18429 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
18432 /// PerformADDCombine - Do target-specific dag combines on integer adds.
18433 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
18434 const X86Subtarget *Subtarget) {
18435 EVT VT = N->getValueType(0);
18436 SDValue Op0 = N->getOperand(0);
18437 SDValue Op1 = N->getOperand(1);
18439 // Try to synthesize horizontal adds from adds of shuffles.
18440 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
18441 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
18442 isHorizontalBinOp(Op0, Op1, true))
18443 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
18445 return OptimizeConditionalInDecrement(N, DAG);
18448 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
18449 const X86Subtarget *Subtarget) {
18450 SDValue Op0 = N->getOperand(0);
18451 SDValue Op1 = N->getOperand(1);
18453 // X86 can't encode an immediate LHS of a sub. See if we can push the
18454 // negation into a preceding instruction.
18455 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
18456 // If the RHS of the sub is a XOR with one use and a constant, invert the
18457 // immediate. Then add one to the LHS of the sub so we can turn
18458 // X-Y -> X+~Y+1, saving one register.
18459 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
18460 isa<ConstantSDNode>(Op1.getOperand(1))) {
18461 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
18462 EVT VT = Op0.getValueType();
18463 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
18465 DAG.getConstant(~XorC, VT));
18466 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
18467 DAG.getConstant(C->getAPIntValue()+1, VT));
18471 // Try to synthesize horizontal adds from adds of shuffles.
18472 EVT VT = N->getValueType(0);
18473 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
18474 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
18475 isHorizontalBinOp(Op0, Op1, true))
18476 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
18478 return OptimizeConditionalInDecrement(N, DAG);
18481 /// performVZEXTCombine - Performs build vector combines
18482 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
18483 TargetLowering::DAGCombinerInfo &DCI,
18484 const X86Subtarget *Subtarget) {
18485 // (vzext (bitcast (vzext (x)) -> (vzext x)
18486 SDValue In = N->getOperand(0);
18487 while (In.getOpcode() == ISD::BITCAST)
18488 In = In.getOperand(0);
18490 if (In.getOpcode() != X86ISD::VZEXT)
18493 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
18497 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
18498 DAGCombinerInfo &DCI) const {
18499 SelectionDAG &DAG = DCI.DAG;
18500 switch (N->getOpcode()) {
18502 case ISD::EXTRACT_VECTOR_ELT:
18503 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
18505 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
18506 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
18507 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
18508 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
18509 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
18510 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
18513 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
18514 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
18515 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
18516 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
18517 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
18518 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
18519 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
18520 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
18521 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
18523 case X86ISD::FOR: return PerformFORCombine(N, DAG);
18525 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
18526 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
18527 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
18528 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
18529 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
18530 case ISD::ANY_EXTEND:
18531 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
18532 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
18533 case ISD::SIGN_EXTEND_INREG: return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
18534 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
18535 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
18536 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
18537 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
18538 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
18539 case X86ISD::SHUFP: // Handle all target specific shuffles
18540 case X86ISD::PALIGNR:
18541 case X86ISD::UNPCKH:
18542 case X86ISD::UNPCKL:
18543 case X86ISD::MOVHLPS:
18544 case X86ISD::MOVLHPS:
18545 case X86ISD::PSHUFD:
18546 case X86ISD::PSHUFHW:
18547 case X86ISD::PSHUFLW:
18548 case X86ISD::MOVSS:
18549 case X86ISD::MOVSD:
18550 case X86ISD::VPERMILP:
18551 case X86ISD::VPERM2X128:
18552 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
18553 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
18559 /// isTypeDesirableForOp - Return true if the target has native support for
18560 /// the specified value type and it is 'desirable' to use the type for the
18561 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
18562 /// instruction encodings are longer and some i16 instructions are slow.
18563 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
18564 if (!isTypeLegal(VT))
18566 if (VT != MVT::i16)
18573 case ISD::SIGN_EXTEND:
18574 case ISD::ZERO_EXTEND:
18575 case ISD::ANY_EXTEND:
18588 /// IsDesirableToPromoteOp - This method query the target whether it is
18589 /// beneficial for dag combiner to promote the specified node. If true, it
18590 /// should return the desired promotion type by reference.
18591 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
18592 EVT VT = Op.getValueType();
18593 if (VT != MVT::i16)
18596 bool Promote = false;
18597 bool Commute = false;
18598 switch (Op.getOpcode()) {
18601 LoadSDNode *LD = cast<LoadSDNode>(Op);
18602 // If the non-extending load has a single use and it's not live out, then it
18603 // might be folded.
18604 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
18605 Op.hasOneUse()*/) {
18606 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
18607 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
18608 // The only case where we'd want to promote LOAD (rather then it being
18609 // promoted as an operand is when it's only use is liveout.
18610 if (UI->getOpcode() != ISD::CopyToReg)
18617 case ISD::SIGN_EXTEND:
18618 case ISD::ZERO_EXTEND:
18619 case ISD::ANY_EXTEND:
18624 SDValue N0 = Op.getOperand(0);
18625 // Look out for (store (shl (load), x)).
18626 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
18639 SDValue N0 = Op.getOperand(0);
18640 SDValue N1 = Op.getOperand(1);
18641 if (!Commute && MayFoldLoad(N1))
18643 // Avoid disabling potential load folding opportunities.
18644 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
18646 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
18656 //===----------------------------------------------------------------------===//
18657 // X86 Inline Assembly Support
18658 //===----------------------------------------------------------------------===//
18661 // Helper to match a string separated by whitespace.
18662 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
18663 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
18665 for (unsigned i = 0, e = args.size(); i != e; ++i) {
18666 StringRef piece(*args[i]);
18667 if (!s.startswith(piece)) // Check if the piece matches.
18670 s = s.substr(piece.size());
18671 StringRef::size_type pos = s.find_first_not_of(" \t");
18672 if (pos == 0) // We matched a prefix.
18680 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
18683 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
18684 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
18686 std::string AsmStr = IA->getAsmString();
18688 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
18689 if (!Ty || Ty->getBitWidth() % 16 != 0)
18692 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
18693 SmallVector<StringRef, 4> AsmPieces;
18694 SplitString(AsmStr, AsmPieces, ";\n");
18696 switch (AsmPieces.size()) {
18697 default: return false;
18699 // FIXME: this should verify that we are targeting a 486 or better. If not,
18700 // we will turn this bswap into something that will be lowered to logical
18701 // ops instead of emitting the bswap asm. For now, we don't support 486 or
18702 // lower so don't worry about this.
18704 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
18705 matchAsm(AsmPieces[0], "bswapl", "$0") ||
18706 matchAsm(AsmPieces[0], "bswapq", "$0") ||
18707 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
18708 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
18709 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
18710 // No need to check constraints, nothing other than the equivalent of
18711 // "=r,0" would be valid here.
18712 return IntrinsicLowering::LowerToByteSwap(CI);
18715 // rorw $$8, ${0:w} --> llvm.bswap.i16
18716 if (CI->getType()->isIntegerTy(16) &&
18717 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
18718 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
18719 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
18721 const std::string &ConstraintsStr = IA->getConstraintString();
18722 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
18723 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
18724 if (AsmPieces.size() == 4 &&
18725 AsmPieces[0] == "~{cc}" &&
18726 AsmPieces[1] == "~{dirflag}" &&
18727 AsmPieces[2] == "~{flags}" &&
18728 AsmPieces[3] == "~{fpsr}")
18729 return IntrinsicLowering::LowerToByteSwap(CI);
18733 if (CI->getType()->isIntegerTy(32) &&
18734 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
18735 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
18736 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
18737 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
18739 const std::string &ConstraintsStr = IA->getConstraintString();
18740 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
18741 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
18742 if (AsmPieces.size() == 4 &&
18743 AsmPieces[0] == "~{cc}" &&
18744 AsmPieces[1] == "~{dirflag}" &&
18745 AsmPieces[2] == "~{flags}" &&
18746 AsmPieces[3] == "~{fpsr}")
18747 return IntrinsicLowering::LowerToByteSwap(CI);
18750 if (CI->getType()->isIntegerTy(64)) {
18751 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
18752 if (Constraints.size() >= 2 &&
18753 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
18754 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
18755 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
18756 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
18757 matchAsm(AsmPieces[1], "bswap", "%edx") &&
18758 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
18759 return IntrinsicLowering::LowerToByteSwap(CI);
18767 /// getConstraintType - Given a constraint letter, return the type of
18768 /// constraint it is for this target.
18769 X86TargetLowering::ConstraintType
18770 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
18771 if (Constraint.size() == 1) {
18772 switch (Constraint[0]) {
18783 return C_RegisterClass;
18807 return TargetLowering::getConstraintType(Constraint);
18810 /// Examine constraint type and operand type and determine a weight value.
18811 /// This object must already have been set up with the operand type
18812 /// and the current alternative constraint selected.
18813 TargetLowering::ConstraintWeight
18814 X86TargetLowering::getSingleConstraintMatchWeight(
18815 AsmOperandInfo &info, const char *constraint) const {
18816 ConstraintWeight weight = CW_Invalid;
18817 Value *CallOperandVal = info.CallOperandVal;
18818 // If we don't have a value, we can't do a match,
18819 // but allow it at the lowest weight.
18820 if (CallOperandVal == NULL)
18822 Type *type = CallOperandVal->getType();
18823 // Look at the constraint type.
18824 switch (*constraint) {
18826 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
18837 if (CallOperandVal->getType()->isIntegerTy())
18838 weight = CW_SpecificReg;
18843 if (type->isFloatingPointTy())
18844 weight = CW_SpecificReg;
18847 if (type->isX86_MMXTy() && Subtarget->hasMMX())
18848 weight = CW_SpecificReg;
18852 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
18853 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
18854 weight = CW_Register;
18857 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
18858 if (C->getZExtValue() <= 31)
18859 weight = CW_Constant;
18863 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18864 if (C->getZExtValue() <= 63)
18865 weight = CW_Constant;
18869 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18870 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
18871 weight = CW_Constant;
18875 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18876 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
18877 weight = CW_Constant;
18881 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18882 if (C->getZExtValue() <= 3)
18883 weight = CW_Constant;
18887 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18888 if (C->getZExtValue() <= 0xff)
18889 weight = CW_Constant;
18894 if (dyn_cast<ConstantFP>(CallOperandVal)) {
18895 weight = CW_Constant;
18899 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18900 if ((C->getSExtValue() >= -0x80000000LL) &&
18901 (C->getSExtValue() <= 0x7fffffffLL))
18902 weight = CW_Constant;
18906 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18907 if (C->getZExtValue() <= 0xffffffff)
18908 weight = CW_Constant;
18915 /// LowerXConstraint - try to replace an X constraint, which matches anything,
18916 /// with another that has more specific requirements based on the type of the
18917 /// corresponding operand.
18918 const char *X86TargetLowering::
18919 LowerXConstraint(EVT ConstraintVT) const {
18920 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
18921 // 'f' like normal targets.
18922 if (ConstraintVT.isFloatingPoint()) {
18923 if (Subtarget->hasSSE2())
18925 if (Subtarget->hasSSE1())
18929 return TargetLowering::LowerXConstraint(ConstraintVT);
18932 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
18933 /// vector. If it is invalid, don't add anything to Ops.
18934 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
18935 std::string &Constraint,
18936 std::vector<SDValue>&Ops,
18937 SelectionDAG &DAG) const {
18938 SDValue Result(0, 0);
18940 // Only support length 1 constraints for now.
18941 if (Constraint.length() > 1) return;
18943 char ConstraintLetter = Constraint[0];
18944 switch (ConstraintLetter) {
18947 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
18948 if (C->getZExtValue() <= 31) {
18949 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
18955 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
18956 if (C->getZExtValue() <= 63) {
18957 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
18963 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
18964 if (isInt<8>(C->getSExtValue())) {
18965 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
18971 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
18972 if (C->getZExtValue() <= 255) {
18973 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
18979 // 32-bit signed value
18980 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
18981 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
18982 C->getSExtValue())) {
18983 // Widen to 64 bits here to get it sign extended.
18984 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
18987 // FIXME gcc accepts some relocatable values here too, but only in certain
18988 // memory models; it's complicated.
18993 // 32-bit unsigned value
18994 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
18995 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
18996 C->getZExtValue())) {
18997 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19001 // FIXME gcc accepts some relocatable values here too, but only in certain
19002 // memory models; it's complicated.
19006 // Literal immediates are always ok.
19007 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
19008 // Widen to 64 bits here to get it sign extended.
19009 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
19013 // In any sort of PIC mode addresses need to be computed at runtime by
19014 // adding in a register or some sort of table lookup. These can't
19015 // be used as immediates.
19016 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
19019 // If we are in non-pic codegen mode, we allow the address of a global (with
19020 // an optional displacement) to be used with 'i'.
19021 GlobalAddressSDNode *GA = 0;
19022 int64_t Offset = 0;
19024 // Match either (GA), (GA+C), (GA+C1+C2), etc.
19026 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
19027 Offset += GA->getOffset();
19029 } else if (Op.getOpcode() == ISD::ADD) {
19030 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
19031 Offset += C->getZExtValue();
19032 Op = Op.getOperand(0);
19035 } else if (Op.getOpcode() == ISD::SUB) {
19036 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
19037 Offset += -C->getZExtValue();
19038 Op = Op.getOperand(0);
19043 // Otherwise, this isn't something we can handle, reject it.
19047 const GlobalValue *GV = GA->getGlobal();
19048 // If we require an extra load to get this address, as in PIC mode, we
19049 // can't accept it.
19050 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
19051 getTargetMachine())))
19054 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
19055 GA->getValueType(0), Offset);
19060 if (Result.getNode()) {
19061 Ops.push_back(Result);
19064 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
19067 std::pair<unsigned, const TargetRegisterClass*>
19068 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
19070 // First, see if this is a constraint that directly corresponds to an LLVM
19072 if (Constraint.size() == 1) {
19073 // GCC Constraint Letters
19074 switch (Constraint[0]) {
19076 // TODO: Slight differences here in allocation order and leaving
19077 // RIP in the class. Do they matter any more here than they do
19078 // in the normal allocation?
19079 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
19080 if (Subtarget->is64Bit()) {
19081 if (VT == MVT::i32 || VT == MVT::f32)
19082 return std::make_pair(0U, &X86::GR32RegClass);
19083 if (VT == MVT::i16)
19084 return std::make_pair(0U, &X86::GR16RegClass);
19085 if (VT == MVT::i8 || VT == MVT::i1)
19086 return std::make_pair(0U, &X86::GR8RegClass);
19087 if (VT == MVT::i64 || VT == MVT::f64)
19088 return std::make_pair(0U, &X86::GR64RegClass);
19091 // 32-bit fallthrough
19092 case 'Q': // Q_REGS
19093 if (VT == MVT::i32 || VT == MVT::f32)
19094 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
19095 if (VT == MVT::i16)
19096 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
19097 if (VT == MVT::i8 || VT == MVT::i1)
19098 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
19099 if (VT == MVT::i64)
19100 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
19102 case 'r': // GENERAL_REGS
19103 case 'l': // INDEX_REGS
19104 if (VT == MVT::i8 || VT == MVT::i1)
19105 return std::make_pair(0U, &X86::GR8RegClass);
19106 if (VT == MVT::i16)
19107 return std::make_pair(0U, &X86::GR16RegClass);
19108 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
19109 return std::make_pair(0U, &X86::GR32RegClass);
19110 return std::make_pair(0U, &X86::GR64RegClass);
19111 case 'R': // LEGACY_REGS
19112 if (VT == MVT::i8 || VT == MVT::i1)
19113 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
19114 if (VT == MVT::i16)
19115 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
19116 if (VT == MVT::i32 || !Subtarget->is64Bit())
19117 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
19118 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
19119 case 'f': // FP Stack registers.
19120 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
19121 // value to the correct fpstack register class.
19122 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
19123 return std::make_pair(0U, &X86::RFP32RegClass);
19124 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
19125 return std::make_pair(0U, &X86::RFP64RegClass);
19126 return std::make_pair(0U, &X86::RFP80RegClass);
19127 case 'y': // MMX_REGS if MMX allowed.
19128 if (!Subtarget->hasMMX()) break;
19129 return std::make_pair(0U, &X86::VR64RegClass);
19130 case 'Y': // SSE_REGS if SSE2 allowed
19131 if (!Subtarget->hasSSE2()) break;
19133 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
19134 if (!Subtarget->hasSSE1()) break;
19136 switch (VT.SimpleTy) {
19138 // Scalar SSE types.
19141 return std::make_pair(0U, &X86::FR32RegClass);
19144 return std::make_pair(0U, &X86::FR64RegClass);
19152 return std::make_pair(0U, &X86::VR128RegClass);
19160 return std::make_pair(0U, &X86::VR256RegClass);
19165 return std::make_pair(0U, &X86::VR512RegClass);
19171 // Use the default implementation in TargetLowering to convert the register
19172 // constraint into a member of a register class.
19173 std::pair<unsigned, const TargetRegisterClass*> Res;
19174 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
19176 // Not found as a standard register?
19177 if (Res.second == 0) {
19178 // Map st(0) -> st(7) -> ST0
19179 if (Constraint.size() == 7 && Constraint[0] == '{' &&
19180 tolower(Constraint[1]) == 's' &&
19181 tolower(Constraint[2]) == 't' &&
19182 Constraint[3] == '(' &&
19183 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
19184 Constraint[5] == ')' &&
19185 Constraint[6] == '}') {
19187 Res.first = X86::ST0+Constraint[4]-'0';
19188 Res.second = &X86::RFP80RegClass;
19192 // GCC allows "st(0)" to be called just plain "st".
19193 if (StringRef("{st}").equals_lower(Constraint)) {
19194 Res.first = X86::ST0;
19195 Res.second = &X86::RFP80RegClass;
19200 if (StringRef("{flags}").equals_lower(Constraint)) {
19201 Res.first = X86::EFLAGS;
19202 Res.second = &X86::CCRRegClass;
19206 // 'A' means EAX + EDX.
19207 if (Constraint == "A") {
19208 Res.first = X86::EAX;
19209 Res.second = &X86::GR32_ADRegClass;
19215 // Otherwise, check to see if this is a register class of the wrong value
19216 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
19217 // turn into {ax},{dx}.
19218 if (Res.second->hasType(VT))
19219 return Res; // Correct type already, nothing to do.
19221 // All of the single-register GCC register classes map their values onto
19222 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
19223 // really want an 8-bit or 32-bit register, map to the appropriate register
19224 // class and return the appropriate register.
19225 if (Res.second == &X86::GR16RegClass) {
19226 if (VT == MVT::i8 || VT == MVT::i1) {
19227 unsigned DestReg = 0;
19228 switch (Res.first) {
19230 case X86::AX: DestReg = X86::AL; break;
19231 case X86::DX: DestReg = X86::DL; break;
19232 case X86::CX: DestReg = X86::CL; break;
19233 case X86::BX: DestReg = X86::BL; break;
19236 Res.first = DestReg;
19237 Res.second = &X86::GR8RegClass;
19239 } else if (VT == MVT::i32 || VT == MVT::f32) {
19240 unsigned DestReg = 0;
19241 switch (Res.first) {
19243 case X86::AX: DestReg = X86::EAX; break;
19244 case X86::DX: DestReg = X86::EDX; break;
19245 case X86::CX: DestReg = X86::ECX; break;
19246 case X86::BX: DestReg = X86::EBX; break;
19247 case X86::SI: DestReg = X86::ESI; break;
19248 case X86::DI: DestReg = X86::EDI; break;
19249 case X86::BP: DestReg = X86::EBP; break;
19250 case X86::SP: DestReg = X86::ESP; break;
19253 Res.first = DestReg;
19254 Res.second = &X86::GR32RegClass;
19256 } else if (VT == MVT::i64 || VT == MVT::f64) {
19257 unsigned DestReg = 0;
19258 switch (Res.first) {
19260 case X86::AX: DestReg = X86::RAX; break;
19261 case X86::DX: DestReg = X86::RDX; break;
19262 case X86::CX: DestReg = X86::RCX; break;
19263 case X86::BX: DestReg = X86::RBX; break;
19264 case X86::SI: DestReg = X86::RSI; break;
19265 case X86::DI: DestReg = X86::RDI; break;
19266 case X86::BP: DestReg = X86::RBP; break;
19267 case X86::SP: DestReg = X86::RSP; break;
19270 Res.first = DestReg;
19271 Res.second = &X86::GR64RegClass;
19274 } else if (Res.second == &X86::FR32RegClass ||
19275 Res.second == &X86::FR64RegClass ||
19276 Res.second == &X86::VR128RegClass ||
19277 Res.second == &X86::VR256RegClass ||
19278 Res.second == &X86::FR32XRegClass ||
19279 Res.second == &X86::FR64XRegClass ||
19280 Res.second == &X86::VR128XRegClass ||
19281 Res.second == &X86::VR256XRegClass ||
19282 Res.second == &X86::VR512RegClass) {
19283 // Handle references to XMM physical registers that got mapped into the
19284 // wrong class. This can happen with constraints like {xmm0} where the
19285 // target independent register mapper will just pick the first match it can
19286 // find, ignoring the required type.
19288 if (VT == MVT::f32 || VT == MVT::i32)
19289 Res.second = &X86::FR32RegClass;
19290 else if (VT == MVT::f64 || VT == MVT::i64)
19291 Res.second = &X86::FR64RegClass;
19292 else if (X86::VR128RegClass.hasType(VT))
19293 Res.second = &X86::VR128RegClass;
19294 else if (X86::VR256RegClass.hasType(VT))
19295 Res.second = &X86::VR256RegClass;
19296 else if (X86::VR512RegClass.hasType(VT))
19297 Res.second = &X86::VR512RegClass;