1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
18 #include "X86InstrBuilder.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/SmallSet.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/ADT/StringExtras.h"
45 #include "llvm/ADT/VariadicFunction.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
54 STATISTIC(NumTailCalls, "Number of tail calls");
56 // Forward declarations.
57 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
60 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
61 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
62 /// simple subregister reference. Idx is an index in the 128 bits we
63 /// want. It need not be aligned to a 128-bit bounday. That makes
64 /// lowering EXTRACT_VECTOR_ELT operations easier.
65 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
66 SelectionDAG &DAG, DebugLoc dl) {
67 EVT VT = Vec.getValueType();
68 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
69 EVT ElVT = VT.getVectorElementType();
70 unsigned Factor = VT.getSizeInBits()/128;
71 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
72 VT.getVectorNumElements()/Factor);
74 // Extract from UNDEF is UNDEF.
75 if (Vec.getOpcode() == ISD::UNDEF)
76 return DAG.getUNDEF(ResultVT);
78 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
79 // we can match to VEXTRACTF128.
80 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
82 // This is the index of the first element of the 128-bit chunk
84 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
87 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
88 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
94 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
95 /// sets things up to match to an AVX VINSERTF128 instruction or a
96 /// simple superregister reference. Idx is an index in the 128 bits
97 /// we want. It need not be aligned to a 128-bit bounday. That makes
98 /// lowering INSERT_VECTOR_ELT operations easier.
99 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
100 unsigned IdxVal, SelectionDAG &DAG,
102 // Inserting UNDEF is Result
103 if (Vec.getOpcode() == ISD::UNDEF)
106 EVT VT = Vec.getValueType();
107 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
109 EVT ElVT = VT.getVectorElementType();
110 EVT ResultVT = Result.getValueType();
112 // Insert the relevant 128 bits.
113 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
115 // This is the index of the first element of the 128-bit chunk
117 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
120 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
121 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
125 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
126 /// instructions. This is used because creating CONCAT_VECTOR nodes of
127 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
128 /// large BUILD_VECTORS.
129 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
130 unsigned NumElems, SelectionDAG &DAG,
132 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
133 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
136 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
137 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
138 bool is64Bit = Subtarget->is64Bit();
140 if (Subtarget->isTargetEnvMacho()) {
142 return new X86_64MachoTargetObjectFile();
143 return new TargetLoweringObjectFileMachO();
146 if (Subtarget->isTargetLinux())
147 return new X86LinuxTargetObjectFile();
148 if (Subtarget->isTargetELF())
149 return new TargetLoweringObjectFileELF();
150 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
151 return new TargetLoweringObjectFileCOFF();
152 llvm_unreachable("unknown subtarget type");
155 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
156 : TargetLowering(TM, createTLOF(TM)) {
157 Subtarget = &TM.getSubtarget<X86Subtarget>();
158 X86ScalarSSEf64 = Subtarget->hasSSE2();
159 X86ScalarSSEf32 = Subtarget->hasSSE1();
160 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
162 RegInfo = TM.getRegisterInfo();
163 TD = getTargetData();
165 // Set up the TargetLowering object.
166 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
168 // X86 is weird, it always uses i8 for shift amounts and setcc results.
169 setBooleanContents(ZeroOrOneBooleanContent);
170 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
171 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
173 // For 64-bit since we have so many registers use the ILP scheduler, for
174 // 32-bit code use the register pressure specific scheduling.
175 // For Atom, always use ILP scheduling.
176 if (Subtarget->isAtom())
177 setSchedulingPreference(Sched::ILP);
178 else if (Subtarget->is64Bit())
179 setSchedulingPreference(Sched::ILP);
181 setSchedulingPreference(Sched::RegPressure);
182 setStackPointerRegisterToSaveRestore(X86StackPtr);
184 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
185 // Setup Windows compiler runtime calls.
186 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
187 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
188 setLibcallName(RTLIB::SREM_I64, "_allrem");
189 setLibcallName(RTLIB::UREM_I64, "_aullrem");
190 setLibcallName(RTLIB::MUL_I64, "_allmul");
191 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
192 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
193 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
194 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
195 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
197 // The _ftol2 runtime function has an unusual calling conv, which
198 // is modeled by a special pseudo-instruction.
199 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
200 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
201 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
202 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
205 if (Subtarget->isTargetDarwin()) {
206 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
207 setUseUnderscoreSetJmp(false);
208 setUseUnderscoreLongJmp(false);
209 } else if (Subtarget->isTargetMingw()) {
210 // MS runtime is weird: it exports _setjmp, but longjmp!
211 setUseUnderscoreSetJmp(true);
212 setUseUnderscoreLongJmp(false);
214 setUseUnderscoreSetJmp(true);
215 setUseUnderscoreLongJmp(true);
218 // Set up the register classes.
219 addRegisterClass(MVT::i8, &X86::GR8RegClass);
220 addRegisterClass(MVT::i16, &X86::GR16RegClass);
221 addRegisterClass(MVT::i32, &X86::GR32RegClass);
222 if (Subtarget->is64Bit())
223 addRegisterClass(MVT::i64, &X86::GR64RegClass);
225 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
227 // We don't accept any truncstore of integer registers.
228 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
229 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
230 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
231 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
232 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
233 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
235 // SETOEQ and SETUNE require checking two conditions.
236 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
237 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
238 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
239 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
240 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
241 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
243 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
245 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
246 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
247 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
249 if (Subtarget->is64Bit()) {
250 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
251 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
252 } else if (!TM.Options.UseSoftFloat) {
253 // We have an algorithm for SSE2->double, and we turn this into a
254 // 64-bit FILD followed by conditional FADD for other targets.
255 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
256 // We have an algorithm for SSE2, and we turn this into a 64-bit
257 // FILD for other targets.
258 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
261 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
263 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
264 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
266 if (!TM.Options.UseSoftFloat) {
267 // SSE has no i16 to fp conversion, only i32
268 if (X86ScalarSSEf32) {
269 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
270 // f32 and f64 cases are Legal, f80 case is not
271 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
273 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
274 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
277 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
278 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
281 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
282 // are Legal, f80 is custom lowered.
283 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
284 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
286 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
288 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
289 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
291 if (X86ScalarSSEf32) {
292 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
293 // f32 and f64 cases are Legal, f80 case is not
294 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
296 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
297 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
300 // Handle FP_TO_UINT by promoting the destination to a larger signed
302 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
303 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
304 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
306 if (Subtarget->is64Bit()) {
307 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
308 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
309 } else if (!TM.Options.UseSoftFloat) {
310 // Since AVX is a superset of SSE3, only check for SSE here.
311 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
312 // Expand FP_TO_UINT into a select.
313 // FIXME: We would like to use a Custom expander here eventually to do
314 // the optimal thing for SSE vs. the default expansion in the legalizer.
315 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
317 // With SSE3 we can use fisttpll to convert to a signed i64; without
318 // SSE, we're stuck with a fistpll.
319 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
322 if (isTargetFTOL()) {
323 // Use the _ftol2 runtime function, which has a pseudo-instruction
324 // to handle its weird calling convention.
325 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
328 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
329 if (!X86ScalarSSEf64) {
330 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
331 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
332 if (Subtarget->is64Bit()) {
333 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
334 // Without SSE, i64->f64 goes through memory.
335 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
339 // Scalar integer divide and remainder are lowered to use operations that
340 // produce two results, to match the available instructions. This exposes
341 // the two-result form to trivial CSE, which is able to combine x/y and x%y
342 // into a single instruction.
344 // Scalar integer multiply-high is also lowered to use two-result
345 // operations, to match the available instructions. However, plain multiply
346 // (low) operations are left as Legal, as there are single-result
347 // instructions for this in x86. Using the two-result multiply instructions
348 // when both high and low results are needed must be arranged by dagcombine.
349 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
351 setOperationAction(ISD::MULHS, VT, Expand);
352 setOperationAction(ISD::MULHU, VT, Expand);
353 setOperationAction(ISD::SDIV, VT, Expand);
354 setOperationAction(ISD::UDIV, VT, Expand);
355 setOperationAction(ISD::SREM, VT, Expand);
356 setOperationAction(ISD::UREM, VT, Expand);
358 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
359 setOperationAction(ISD::ADDC, VT, Custom);
360 setOperationAction(ISD::ADDE, VT, Custom);
361 setOperationAction(ISD::SUBC, VT, Custom);
362 setOperationAction(ISD::SUBE, VT, Custom);
365 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
366 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
367 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
368 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
369 if (Subtarget->is64Bit())
370 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
373 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
374 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
375 setOperationAction(ISD::FREM , MVT::f32 , Expand);
376 setOperationAction(ISD::FREM , MVT::f64 , Expand);
377 setOperationAction(ISD::FREM , MVT::f80 , Expand);
378 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
380 // Promote the i8 variants and force them on up to i32 which has a shorter
382 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
383 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
384 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
385 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
386 if (Subtarget->hasBMI()) {
387 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
388 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
389 if (Subtarget->is64Bit())
390 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
392 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
393 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
394 if (Subtarget->is64Bit())
395 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
398 if (Subtarget->hasLZCNT()) {
399 // When promoting the i8 variants, force them to i32 for a shorter
401 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
402 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
403 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
404 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
405 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
406 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
407 if (Subtarget->is64Bit())
408 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
410 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
411 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
412 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
413 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
414 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
415 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
416 if (Subtarget->is64Bit()) {
417 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
418 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
422 if (Subtarget->hasPOPCNT()) {
423 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
425 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
426 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
427 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
428 if (Subtarget->is64Bit())
429 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
432 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
433 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
435 // These should be promoted to a larger select which is supported.
436 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
437 // X86 wants to expand cmov itself.
438 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
439 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
440 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
441 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
442 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
443 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
444 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
445 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
446 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
447 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
448 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
449 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
450 if (Subtarget->is64Bit()) {
451 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
452 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
454 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
457 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
458 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
459 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
460 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
461 if (Subtarget->is64Bit())
462 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
463 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
464 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
465 if (Subtarget->is64Bit()) {
466 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
467 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
468 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
469 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
470 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
472 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
473 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
474 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
475 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
476 if (Subtarget->is64Bit()) {
477 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
478 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
479 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
482 if (Subtarget->hasSSE1())
483 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
485 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
486 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
488 // On X86 and X86-64, atomic operations are lowered to locked instructions.
489 // Locked instructions, in turn, have implicit fence semantics (all memory
490 // operations are flushed before issuing the locked instruction, and they
491 // are not buffered), so we can fold away the common pattern of
492 // fence-atomic-fence.
493 setShouldFoldAtomicFences(true);
495 // Expand certain atomics
496 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
498 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
499 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
500 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
503 if (!Subtarget->is64Bit()) {
504 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
505 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
506 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
507 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
508 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
509 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
510 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
511 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
514 if (Subtarget->hasCmpxchg16b()) {
515 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
518 // FIXME - use subtarget debug flags
519 if (!Subtarget->isTargetDarwin() &&
520 !Subtarget->isTargetELF() &&
521 !Subtarget->isTargetCygMing()) {
522 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
525 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
526 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
527 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
528 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
529 if (Subtarget->is64Bit()) {
530 setExceptionPointerRegister(X86::RAX);
531 setExceptionSelectorRegister(X86::RDX);
533 setExceptionPointerRegister(X86::EAX);
534 setExceptionSelectorRegister(X86::EDX);
536 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
537 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
539 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
540 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
542 setOperationAction(ISD::TRAP, MVT::Other, Legal);
544 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
545 setOperationAction(ISD::VASTART , MVT::Other, Custom);
546 setOperationAction(ISD::VAEND , MVT::Other, Expand);
547 if (Subtarget->is64Bit()) {
548 setOperationAction(ISD::VAARG , MVT::Other, Custom);
549 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
551 setOperationAction(ISD::VAARG , MVT::Other, Expand);
552 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
555 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
556 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
558 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
559 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
560 MVT::i64 : MVT::i32, Custom);
561 else if (TM.Options.EnableSegmentedStacks)
562 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
563 MVT::i64 : MVT::i32, Custom);
565 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
566 MVT::i64 : MVT::i32, Expand);
568 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
569 // f32 and f64 use SSE.
570 // Set up the FP register classes.
571 addRegisterClass(MVT::f32, &X86::FR32RegClass);
572 addRegisterClass(MVT::f64, &X86::FR64RegClass);
574 // Use ANDPD to simulate FABS.
575 setOperationAction(ISD::FABS , MVT::f64, Custom);
576 setOperationAction(ISD::FABS , MVT::f32, Custom);
578 // Use XORP to simulate FNEG.
579 setOperationAction(ISD::FNEG , MVT::f64, Custom);
580 setOperationAction(ISD::FNEG , MVT::f32, Custom);
582 // Use ANDPD and ORPD to simulate FCOPYSIGN.
583 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
584 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
586 // Lower this to FGETSIGNx86 plus an AND.
587 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
588 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
590 // We don't support sin/cos/fmod
591 setOperationAction(ISD::FSIN , MVT::f64, Expand);
592 setOperationAction(ISD::FCOS , MVT::f64, Expand);
593 setOperationAction(ISD::FSIN , MVT::f32, Expand);
594 setOperationAction(ISD::FCOS , MVT::f32, Expand);
596 // Expand FP immediates into loads from the stack, except for the special
598 addLegalFPImmediate(APFloat(+0.0)); // xorpd
599 addLegalFPImmediate(APFloat(+0.0f)); // xorps
600 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
601 // Use SSE for f32, x87 for f64.
602 // Set up the FP register classes.
603 addRegisterClass(MVT::f32, &X86::FR32RegClass);
604 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
606 // Use ANDPS to simulate FABS.
607 setOperationAction(ISD::FABS , MVT::f32, Custom);
609 // Use XORP to simulate FNEG.
610 setOperationAction(ISD::FNEG , MVT::f32, Custom);
612 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
614 // Use ANDPS and ORPS to simulate FCOPYSIGN.
615 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
616 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
618 // We don't support sin/cos/fmod
619 setOperationAction(ISD::FSIN , MVT::f32, Expand);
620 setOperationAction(ISD::FCOS , MVT::f32, Expand);
622 // Special cases we handle for FP constants.
623 addLegalFPImmediate(APFloat(+0.0f)); // xorps
624 addLegalFPImmediate(APFloat(+0.0)); // FLD0
625 addLegalFPImmediate(APFloat(+1.0)); // FLD1
626 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
627 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
629 if (!TM.Options.UnsafeFPMath) {
630 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
631 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
633 } else if (!TM.Options.UseSoftFloat) {
634 // f32 and f64 in x87.
635 // Set up the FP register classes.
636 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
637 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
639 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
640 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
641 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
642 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
644 if (!TM.Options.UnsafeFPMath) {
645 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
646 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
648 addLegalFPImmediate(APFloat(+0.0)); // FLD0
649 addLegalFPImmediate(APFloat(+1.0)); // FLD1
650 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
651 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
652 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
653 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
654 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
655 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
658 // We don't support FMA.
659 setOperationAction(ISD::FMA, MVT::f64, Expand);
660 setOperationAction(ISD::FMA, MVT::f32, Expand);
662 // Long double always uses X87.
663 if (!TM.Options.UseSoftFloat) {
664 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
665 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
666 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
668 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
669 addLegalFPImmediate(TmpFlt); // FLD0
671 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
674 APFloat TmpFlt2(+1.0);
675 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
677 addLegalFPImmediate(TmpFlt2); // FLD1
678 TmpFlt2.changeSign();
679 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
682 if (!TM.Options.UnsafeFPMath) {
683 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
684 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
687 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
688 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
689 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
690 setOperationAction(ISD::FRINT, MVT::f80, Expand);
691 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
692 setOperationAction(ISD::FMA, MVT::f80, Expand);
695 // Always use a library call for pow.
696 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
697 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
698 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
700 setOperationAction(ISD::FLOG, MVT::f80, Expand);
701 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
702 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
703 setOperationAction(ISD::FEXP, MVT::f80, Expand);
704 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
706 // First set operation action for all vector types to either promote
707 // (for widening) or expand (for scalarization). Then we will selectively
708 // turn on ones that can be effectively codegen'd.
709 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
710 VT <= MVT::LAST_VECTOR_VALUETYPE; ++VT) {
711 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
721 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
723 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
724 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
725 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
726 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
727 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
728 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
729 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
730 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
731 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
732 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
733 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
734 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
735 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
736 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
737 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
738 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
740 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
741 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
742 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
743 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
744 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
745 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
746 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
747 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
748 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
749 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
750 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
751 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
752 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
753 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
754 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
755 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
756 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
757 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
758 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
759 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
760 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
761 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
762 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
763 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
764 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
765 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
766 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
767 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
768 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
769 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
770 setTruncStoreAction((MVT::SimpleValueType)VT,
771 (MVT::SimpleValueType)InnerVT, Expand);
772 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
773 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
774 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
777 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
778 // with -msoft-float, disable use of MMX as well.
779 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
780 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
781 // No operations on x86mmx supported, everything uses intrinsics.
784 // MMX-sized vectors (other than x86mmx) are expected to be expanded
785 // into smaller operations.
786 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
787 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
788 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
789 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
790 setOperationAction(ISD::AND, MVT::v8i8, Expand);
791 setOperationAction(ISD::AND, MVT::v4i16, Expand);
792 setOperationAction(ISD::AND, MVT::v2i32, Expand);
793 setOperationAction(ISD::AND, MVT::v1i64, Expand);
794 setOperationAction(ISD::OR, MVT::v8i8, Expand);
795 setOperationAction(ISD::OR, MVT::v4i16, Expand);
796 setOperationAction(ISD::OR, MVT::v2i32, Expand);
797 setOperationAction(ISD::OR, MVT::v1i64, Expand);
798 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
799 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
800 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
801 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
802 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
803 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
804 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
805 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
806 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
807 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
808 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
809 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
810 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
811 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
812 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
813 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
814 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
816 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
817 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
819 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
820 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
821 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
822 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
823 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
824 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
825 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
826 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
827 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
828 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
829 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
830 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
833 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
834 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
836 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
837 // registers cannot be used even for integer operations.
838 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
839 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
840 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
841 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
843 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
844 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
845 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
846 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
847 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
848 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
849 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
850 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
851 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
852 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
853 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
854 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
855 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
856 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
857 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
858 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
860 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
861 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
862 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
863 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
865 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
866 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
867 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
868 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
869 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
871 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
872 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
873 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
874 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
875 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
877 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
878 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
879 EVT VT = (MVT::SimpleValueType)i;
880 // Do not attempt to custom lower non-power-of-2 vectors
881 if (!isPowerOf2_32(VT.getVectorNumElements()))
883 // Do not attempt to custom lower non-128-bit vectors
884 if (!VT.is128BitVector())
886 setOperationAction(ISD::BUILD_VECTOR,
887 VT.getSimpleVT().SimpleTy, Custom);
888 setOperationAction(ISD::VECTOR_SHUFFLE,
889 VT.getSimpleVT().SimpleTy, Custom);
890 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
891 VT.getSimpleVT().SimpleTy, Custom);
894 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
895 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
896 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
897 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
898 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
899 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
901 if (Subtarget->is64Bit()) {
902 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
903 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
906 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
907 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
908 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
911 // Do not attempt to promote non-128-bit vectors
912 if (!VT.is128BitVector())
915 setOperationAction(ISD::AND, SVT, Promote);
916 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
917 setOperationAction(ISD::OR, SVT, Promote);
918 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
919 setOperationAction(ISD::XOR, SVT, Promote);
920 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
921 setOperationAction(ISD::LOAD, SVT, Promote);
922 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
923 setOperationAction(ISD::SELECT, SVT, Promote);
924 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
927 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
929 // Custom lower v2i64 and v2f64 selects.
930 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
931 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
932 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
933 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
935 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
936 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
939 if (Subtarget->hasSSE41()) {
940 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
941 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
942 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
943 setOperationAction(ISD::FRINT, MVT::f32, Legal);
944 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
945 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
946 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
947 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
948 setOperationAction(ISD::FRINT, MVT::f64, Legal);
949 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
951 // FIXME: Do we need to handle scalar-to-vector here?
952 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
954 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
955 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
956 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
957 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
958 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
960 // i8 and i16 vectors are custom , because the source register and source
961 // source memory operand types are not the same width. f32 vectors are
962 // custom since the immediate controlling the insert encodes additional
964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
966 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
967 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
969 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
970 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
971 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
972 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
974 // FIXME: these should be Legal but thats only for the case where
975 // the index is constant. For now custom expand to deal with that.
976 if (Subtarget->is64Bit()) {
977 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
978 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
982 if (Subtarget->hasSSE2()) {
983 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
984 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
986 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
987 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
989 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
990 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
992 if (Subtarget->hasAVX2()) {
993 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
994 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
996 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
997 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
999 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
1001 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1002 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1004 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1005 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1007 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1011 if (Subtarget->hasSSE42())
1012 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1014 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) {
1015 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1016 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1017 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1018 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1019 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1020 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1022 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1023 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1024 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1026 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1027 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1028 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1029 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1030 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1031 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1033 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1034 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1035 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1036 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1037 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1038 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1040 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1041 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1042 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1044 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
1045 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
1046 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
1047 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
1048 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
1049 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
1051 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1052 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1054 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1055 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1057 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1058 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1060 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1061 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1062 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1063 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1065 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1066 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1067 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1069 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1070 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1071 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1072 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1074 if (Subtarget->hasAVX2()) {
1075 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1076 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1077 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1078 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1080 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1081 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1082 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1083 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1085 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1086 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1087 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1088 // Don't lower v32i8 because there is no 128-bit byte mul
1090 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1092 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1093 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1095 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1096 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1098 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1100 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1101 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1102 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1103 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1105 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1106 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1107 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1108 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1110 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1111 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1112 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1113 // Don't lower v32i8 because there is no 128-bit byte mul
1115 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1116 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1118 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1119 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1121 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1124 // Custom lower several nodes for 256-bit types.
1125 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1126 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1127 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1130 // Extract subvector is special because the value type
1131 // (result) is 128-bit but the source is 256-bit wide.
1132 if (VT.is128BitVector())
1133 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1135 // Do not attempt to custom lower other non-256-bit vectors
1136 if (!VT.is256BitVector())
1139 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1140 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1141 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1143 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1144 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1147 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1148 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1149 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1152 // Do not attempt to promote non-256-bit vectors
1153 if (!VT.is256BitVector())
1156 setOperationAction(ISD::AND, SVT, Promote);
1157 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1158 setOperationAction(ISD::OR, SVT, Promote);
1159 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1160 setOperationAction(ISD::XOR, SVT, Promote);
1161 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1162 setOperationAction(ISD::LOAD, SVT, Promote);
1163 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1164 setOperationAction(ISD::SELECT, SVT, Promote);
1165 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1169 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1170 // of this type with custom code.
1171 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1172 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1173 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1177 // We want to custom lower some of our intrinsics.
1178 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1179 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1182 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1183 // handle type legalization for these operations here.
1185 // FIXME: We really should do custom legalization for addition and
1186 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1187 // than generic legalization for 64-bit multiplication-with-overflow, though.
1188 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1189 // Add/Sub/Mul with overflow operations are custom lowered.
1191 setOperationAction(ISD::SADDO, VT, Custom);
1192 setOperationAction(ISD::UADDO, VT, Custom);
1193 setOperationAction(ISD::SSUBO, VT, Custom);
1194 setOperationAction(ISD::USUBO, VT, Custom);
1195 setOperationAction(ISD::SMULO, VT, Custom);
1196 setOperationAction(ISD::UMULO, VT, Custom);
1199 // There are no 8-bit 3-address imul/mul instructions
1200 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1201 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1203 if (!Subtarget->is64Bit()) {
1204 // These libcalls are not available in 32-bit.
1205 setLibcallName(RTLIB::SHL_I128, 0);
1206 setLibcallName(RTLIB::SRL_I128, 0);
1207 setLibcallName(RTLIB::SRA_I128, 0);
1210 // We have target-specific dag combine patterns for the following nodes:
1211 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1212 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1213 setTargetDAGCombine(ISD::VSELECT);
1214 setTargetDAGCombine(ISD::SELECT);
1215 setTargetDAGCombine(ISD::SHL);
1216 setTargetDAGCombine(ISD::SRA);
1217 setTargetDAGCombine(ISD::SRL);
1218 setTargetDAGCombine(ISD::OR);
1219 setTargetDAGCombine(ISD::AND);
1220 setTargetDAGCombine(ISD::ADD);
1221 setTargetDAGCombine(ISD::FADD);
1222 setTargetDAGCombine(ISD::FSUB);
1223 setTargetDAGCombine(ISD::SUB);
1224 setTargetDAGCombine(ISD::LOAD);
1225 setTargetDAGCombine(ISD::STORE);
1226 setTargetDAGCombine(ISD::ZERO_EXTEND);
1227 setTargetDAGCombine(ISD::ANY_EXTEND);
1228 setTargetDAGCombine(ISD::SIGN_EXTEND);
1229 setTargetDAGCombine(ISD::TRUNCATE);
1230 setTargetDAGCombine(ISD::UINT_TO_FP);
1231 setTargetDAGCombine(ISD::SINT_TO_FP);
1232 setTargetDAGCombine(ISD::SETCC);
1233 setTargetDAGCombine(ISD::FP_TO_SINT);
1234 if (Subtarget->is64Bit())
1235 setTargetDAGCombine(ISD::MUL);
1236 setTargetDAGCombine(ISD::XOR);
1238 computeRegisterProperties();
1240 // On Darwin, -Os means optimize for size without hurting performance,
1241 // do not reduce the limit.
1242 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1243 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1244 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1245 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1246 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1247 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1248 setPrefLoopAlignment(4); // 2^4 bytes.
1249 benefitFromCodePlacementOpt = true;
1251 // Predictable cmov don't hurt on atom because it's in-order.
1252 predictableSelectIsExpensive = !Subtarget->isAtom();
1254 setPrefFunctionAlignment(4); // 2^4 bytes.
1258 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1259 if (!VT.isVector()) return MVT::i8;
1260 return VT.changeVectorElementTypeToInteger();
1264 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1265 /// the desired ByVal argument alignment.
1266 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1269 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1270 if (VTy->getBitWidth() == 128)
1272 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1273 unsigned EltAlign = 0;
1274 getMaxByValAlign(ATy->getElementType(), EltAlign);
1275 if (EltAlign > MaxAlign)
1276 MaxAlign = EltAlign;
1277 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1278 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1279 unsigned EltAlign = 0;
1280 getMaxByValAlign(STy->getElementType(i), EltAlign);
1281 if (EltAlign > MaxAlign)
1282 MaxAlign = EltAlign;
1289 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1290 /// function arguments in the caller parameter area. For X86, aggregates
1291 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1292 /// are at 4-byte boundaries.
1293 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1294 if (Subtarget->is64Bit()) {
1295 // Max of 8 and alignment of type.
1296 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1303 if (Subtarget->hasSSE1())
1304 getMaxByValAlign(Ty, Align);
1308 /// getOptimalMemOpType - Returns the target specific optimal type for load
1309 /// and store operations as a result of memset, memcpy, and memmove
1310 /// lowering. If DstAlign is zero that means it's safe to destination
1311 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1312 /// means there isn't a need to check it against alignment requirement,
1313 /// probably because the source does not need to be loaded. If
1314 /// 'IsZeroVal' is true, that means it's safe to return a
1315 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1316 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1317 /// constant so it does not need to be loaded.
1318 /// It returns EVT::Other if the type should be determined using generic
1319 /// target-independent logic.
1321 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1322 unsigned DstAlign, unsigned SrcAlign,
1325 MachineFunction &MF) const {
1326 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1327 // linux. This is because the stack realignment code can't handle certain
1328 // cases like PR2962. This should be removed when PR2962 is fixed.
1329 const Function *F = MF.getFunction();
1331 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1333 (Subtarget->isUnalignedMemAccessFast() ||
1334 ((DstAlign == 0 || DstAlign >= 16) &&
1335 (SrcAlign == 0 || SrcAlign >= 16))) &&
1336 Subtarget->getStackAlignment() >= 16) {
1337 if (Subtarget->getStackAlignment() >= 32) {
1338 if (Subtarget->hasAVX2())
1340 if (Subtarget->hasAVX())
1343 if (Subtarget->hasSSE2())
1345 if (Subtarget->hasSSE1())
1347 } else if (!MemcpyStrSrc && Size >= 8 &&
1348 !Subtarget->is64Bit() &&
1349 Subtarget->getStackAlignment() >= 8 &&
1350 Subtarget->hasSSE2()) {
1351 // Do not use f64 to lower memcpy if source is string constant. It's
1352 // better to use i32 to avoid the loads.
1356 if (Subtarget->is64Bit() && Size >= 8)
1361 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1362 /// current function. The returned value is a member of the
1363 /// MachineJumpTableInfo::JTEntryKind enum.
1364 unsigned X86TargetLowering::getJumpTableEncoding() const {
1365 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1367 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1368 Subtarget->isPICStyleGOT())
1369 return MachineJumpTableInfo::EK_Custom32;
1371 // Otherwise, use the normal jump table encoding heuristics.
1372 return TargetLowering::getJumpTableEncoding();
1376 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1377 const MachineBasicBlock *MBB,
1378 unsigned uid,MCContext &Ctx) const{
1379 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1380 Subtarget->isPICStyleGOT());
1381 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1383 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1384 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1387 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1389 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1390 SelectionDAG &DAG) const {
1391 if (!Subtarget->is64Bit())
1392 // This doesn't have DebugLoc associated with it, but is not really the
1393 // same as a Register.
1394 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1398 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1399 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1401 const MCExpr *X86TargetLowering::
1402 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1403 MCContext &Ctx) const {
1404 // X86-64 uses RIP relative addressing based on the jump table label.
1405 if (Subtarget->isPICStyleRIPRel())
1406 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1408 // Otherwise, the reference is relative to the PIC base.
1409 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1412 // FIXME: Why this routine is here? Move to RegInfo!
1413 std::pair<const TargetRegisterClass*, uint8_t>
1414 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1415 const TargetRegisterClass *RRC = 0;
1417 switch (VT.getSimpleVT().SimpleTy) {
1419 return TargetLowering::findRepresentativeClass(VT);
1420 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1421 RRC = Subtarget->is64Bit() ?
1422 (const TargetRegisterClass*)&X86::GR64RegClass :
1423 (const TargetRegisterClass*)&X86::GR32RegClass;
1426 RRC = &X86::VR64RegClass;
1428 case MVT::f32: case MVT::f64:
1429 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1430 case MVT::v4f32: case MVT::v2f64:
1431 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1433 RRC = &X86::VR128RegClass;
1436 return std::make_pair(RRC, Cost);
1439 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1440 unsigned &Offset) const {
1441 if (!Subtarget->isTargetLinux())
1444 if (Subtarget->is64Bit()) {
1445 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1447 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1460 //===----------------------------------------------------------------------===//
1461 // Return Value Calling Convention Implementation
1462 //===----------------------------------------------------------------------===//
1464 #include "X86GenCallingConv.inc"
1467 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1468 MachineFunction &MF, bool isVarArg,
1469 const SmallVectorImpl<ISD::OutputArg> &Outs,
1470 LLVMContext &Context) const {
1471 SmallVector<CCValAssign, 16> RVLocs;
1472 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1474 return CCInfo.CheckReturn(Outs, RetCC_X86);
1478 X86TargetLowering::LowerReturn(SDValue Chain,
1479 CallingConv::ID CallConv, bool isVarArg,
1480 const SmallVectorImpl<ISD::OutputArg> &Outs,
1481 const SmallVectorImpl<SDValue> &OutVals,
1482 DebugLoc dl, SelectionDAG &DAG) const {
1483 MachineFunction &MF = DAG.getMachineFunction();
1484 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1486 SmallVector<CCValAssign, 16> RVLocs;
1487 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1488 RVLocs, *DAG.getContext());
1489 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1491 // Add the regs to the liveout set for the function.
1492 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1493 for (unsigned i = 0; i != RVLocs.size(); ++i)
1494 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1495 MRI.addLiveOut(RVLocs[i].getLocReg());
1499 SmallVector<SDValue, 6> RetOps;
1500 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1501 // Operand #1 = Bytes To Pop
1502 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1505 // Copy the result values into the output registers.
1506 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1507 CCValAssign &VA = RVLocs[i];
1508 assert(VA.isRegLoc() && "Can only return in registers!");
1509 SDValue ValToCopy = OutVals[i];
1510 EVT ValVT = ValToCopy.getValueType();
1512 // Promote values to the appropriate types
1513 if (VA.getLocInfo() == CCValAssign::SExt)
1514 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1515 else if (VA.getLocInfo() == CCValAssign::ZExt)
1516 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1517 else if (VA.getLocInfo() == CCValAssign::AExt)
1518 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1519 else if (VA.getLocInfo() == CCValAssign::BCvt)
1520 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1522 // If this is x86-64, and we disabled SSE, we can't return FP values,
1523 // or SSE or MMX vectors.
1524 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1525 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1526 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1527 report_fatal_error("SSE register return with SSE disabled");
1529 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1530 // llvm-gcc has never done it right and no one has noticed, so this
1531 // should be OK for now.
1532 if (ValVT == MVT::f64 &&
1533 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1534 report_fatal_error("SSE2 register return with SSE2 disabled");
1536 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1537 // the RET instruction and handled by the FP Stackifier.
1538 if (VA.getLocReg() == X86::ST0 ||
1539 VA.getLocReg() == X86::ST1) {
1540 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1541 // change the value to the FP stack register class.
1542 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1543 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1544 RetOps.push_back(ValToCopy);
1545 // Don't emit a copytoreg.
1549 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1550 // which is returned in RAX / RDX.
1551 if (Subtarget->is64Bit()) {
1552 if (ValVT == MVT::x86mmx) {
1553 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1554 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1555 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1557 // If we don't have SSE2 available, convert to v4f32 so the generated
1558 // register is legal.
1559 if (!Subtarget->hasSSE2())
1560 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1565 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1566 Flag = Chain.getValue(1);
1569 // The x86-64 ABI for returning structs by value requires that we copy
1570 // the sret argument into %rax for the return. We saved the argument into
1571 // a virtual register in the entry block, so now we copy the value out
1573 if (Subtarget->is64Bit() &&
1574 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1575 MachineFunction &MF = DAG.getMachineFunction();
1576 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1577 unsigned Reg = FuncInfo->getSRetReturnReg();
1579 "SRetReturnReg should have been set in LowerFormalArguments().");
1580 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1582 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1583 Flag = Chain.getValue(1);
1585 // RAX now acts like a return value.
1586 MRI.addLiveOut(X86::RAX);
1589 RetOps[0] = Chain; // Update chain.
1591 // Add the flag if we have it.
1593 RetOps.push_back(Flag);
1595 return DAG.getNode(X86ISD::RET_FLAG, dl,
1596 MVT::Other, &RetOps[0], RetOps.size());
1599 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1600 if (N->getNumValues() != 1)
1602 if (!N->hasNUsesOfValue(1, 0))
1605 SDValue TCChain = Chain;
1606 SDNode *Copy = *N->use_begin();
1607 if (Copy->getOpcode() == ISD::CopyToReg) {
1608 // If the copy has a glue operand, we conservatively assume it isn't safe to
1609 // perform a tail call.
1610 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1612 TCChain = Copy->getOperand(0);
1613 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1616 bool HasRet = false;
1617 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1619 if (UI->getOpcode() != X86ISD::RET_FLAG)
1632 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1633 ISD::NodeType ExtendKind) const {
1635 // TODO: Is this also valid on 32-bit?
1636 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1637 ReturnMVT = MVT::i8;
1639 ReturnMVT = MVT::i32;
1641 EVT MinVT = getRegisterType(Context, ReturnMVT);
1642 return VT.bitsLT(MinVT) ? MinVT : VT;
1645 /// LowerCallResult - Lower the result values of a call into the
1646 /// appropriate copies out of appropriate physical registers.
1649 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1650 CallingConv::ID CallConv, bool isVarArg,
1651 const SmallVectorImpl<ISD::InputArg> &Ins,
1652 DebugLoc dl, SelectionDAG &DAG,
1653 SmallVectorImpl<SDValue> &InVals) const {
1655 // Assign locations to each value returned by this call.
1656 SmallVector<CCValAssign, 16> RVLocs;
1657 bool Is64Bit = Subtarget->is64Bit();
1658 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1659 getTargetMachine(), RVLocs, *DAG.getContext());
1660 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1662 // Copy all of the result registers out of their specified physreg.
1663 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1664 CCValAssign &VA = RVLocs[i];
1665 EVT CopyVT = VA.getValVT();
1667 // If this is x86-64, and we disabled SSE, we can't return FP values
1668 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1669 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1670 report_fatal_error("SSE register return with SSE disabled");
1675 // If this is a call to a function that returns an fp value on the floating
1676 // point stack, we must guarantee the the value is popped from the stack, so
1677 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1678 // if the return value is not used. We use the FpPOP_RETVAL instruction
1680 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1681 // If we prefer to use the value in xmm registers, copy it out as f80 and
1682 // use a truncate to move it from fp stack reg to xmm reg.
1683 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1684 SDValue Ops[] = { Chain, InFlag };
1685 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1686 MVT::Other, MVT::Glue, Ops, 2), 1);
1687 Val = Chain.getValue(0);
1689 // Round the f80 to the right size, which also moves it to the appropriate
1691 if (CopyVT != VA.getValVT())
1692 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1693 // This truncation won't change the value.
1694 DAG.getIntPtrConstant(1));
1696 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1697 CopyVT, InFlag).getValue(1);
1698 Val = Chain.getValue(0);
1700 InFlag = Chain.getValue(2);
1701 InVals.push_back(Val);
1708 //===----------------------------------------------------------------------===//
1709 // C & StdCall & Fast Calling Convention implementation
1710 //===----------------------------------------------------------------------===//
1711 // StdCall calling convention seems to be standard for many Windows' API
1712 // routines and around. It differs from C calling convention just a little:
1713 // callee should clean up the stack, not caller. Symbols should be also
1714 // decorated in some fancy way :) It doesn't support any vector arguments.
1715 // For info on fast calling convention see Fast Calling Convention (tail call)
1716 // implementation LowerX86_32FastCCCallTo.
1718 /// CallIsStructReturn - Determines whether a call uses struct return
1720 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1724 return Outs[0].Flags.isSRet();
1727 /// ArgsAreStructReturn - Determines whether a function uses struct
1728 /// return semantics.
1730 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1734 return Ins[0].Flags.isSRet();
1737 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1738 /// by "Src" to address "Dst" with size and alignment information specified by
1739 /// the specific parameter attribute. The copy will be passed as a byval
1740 /// function parameter.
1742 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1743 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1745 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1747 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1748 /*isVolatile*/false, /*AlwaysInline=*/true,
1749 MachinePointerInfo(), MachinePointerInfo());
1752 /// IsTailCallConvention - Return true if the calling convention is one that
1753 /// supports tail call optimization.
1754 static bool IsTailCallConvention(CallingConv::ID CC) {
1755 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1758 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1759 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
1763 CallingConv::ID CalleeCC = CS.getCallingConv();
1764 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1770 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1771 /// a tailcall target by changing its ABI.
1772 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1773 bool GuaranteedTailCallOpt) {
1774 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1778 X86TargetLowering::LowerMemArgument(SDValue Chain,
1779 CallingConv::ID CallConv,
1780 const SmallVectorImpl<ISD::InputArg> &Ins,
1781 DebugLoc dl, SelectionDAG &DAG,
1782 const CCValAssign &VA,
1783 MachineFrameInfo *MFI,
1785 // Create the nodes corresponding to a load from this parameter slot.
1786 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1787 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1788 getTargetMachine().Options.GuaranteedTailCallOpt);
1789 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1792 // If value is passed by pointer we have address passed instead of the value
1794 if (VA.getLocInfo() == CCValAssign::Indirect)
1795 ValVT = VA.getLocVT();
1797 ValVT = VA.getValVT();
1799 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1800 // changed with more analysis.
1801 // In case of tail call optimization mark all arguments mutable. Since they
1802 // could be overwritten by lowering of arguments in case of a tail call.
1803 if (Flags.isByVal()) {
1804 unsigned Bytes = Flags.getByValSize();
1805 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1806 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1807 return DAG.getFrameIndex(FI, getPointerTy());
1809 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1810 VA.getLocMemOffset(), isImmutable);
1811 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1812 return DAG.getLoad(ValVT, dl, Chain, FIN,
1813 MachinePointerInfo::getFixedStack(FI),
1814 false, false, false, 0);
1819 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1820 CallingConv::ID CallConv,
1822 const SmallVectorImpl<ISD::InputArg> &Ins,
1825 SmallVectorImpl<SDValue> &InVals)
1827 MachineFunction &MF = DAG.getMachineFunction();
1828 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1830 const Function* Fn = MF.getFunction();
1831 if (Fn->hasExternalLinkage() &&
1832 Subtarget->isTargetCygMing() &&
1833 Fn->getName() == "main")
1834 FuncInfo->setForceFramePointer(true);
1836 MachineFrameInfo *MFI = MF.getFrameInfo();
1837 bool Is64Bit = Subtarget->is64Bit();
1838 bool IsWindows = Subtarget->isTargetWindows();
1839 bool IsWin64 = Subtarget->isTargetWin64();
1841 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1842 "Var args not supported with calling convention fastcc or ghc");
1844 // Assign locations to all of the incoming arguments.
1845 SmallVector<CCValAssign, 16> ArgLocs;
1846 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1847 ArgLocs, *DAG.getContext());
1849 // Allocate shadow area for Win64
1851 CCInfo.AllocateStack(32, 8);
1854 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1856 unsigned LastVal = ~0U;
1858 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1859 CCValAssign &VA = ArgLocs[i];
1860 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1862 assert(VA.getValNo() != LastVal &&
1863 "Don't support value assigned to multiple locs yet");
1865 LastVal = VA.getValNo();
1867 if (VA.isRegLoc()) {
1868 EVT RegVT = VA.getLocVT();
1869 const TargetRegisterClass *RC;
1870 if (RegVT == MVT::i32)
1871 RC = &X86::GR32RegClass;
1872 else if (Is64Bit && RegVT == MVT::i64)
1873 RC = &X86::GR64RegClass;
1874 else if (RegVT == MVT::f32)
1875 RC = &X86::FR32RegClass;
1876 else if (RegVT == MVT::f64)
1877 RC = &X86::FR64RegClass;
1878 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1879 RC = &X86::VR256RegClass;
1880 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1881 RC = &X86::VR128RegClass;
1882 else if (RegVT == MVT::x86mmx)
1883 RC = &X86::VR64RegClass;
1885 llvm_unreachable("Unknown argument type!");
1887 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1888 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1890 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1891 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1893 if (VA.getLocInfo() == CCValAssign::SExt)
1894 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1895 DAG.getValueType(VA.getValVT()));
1896 else if (VA.getLocInfo() == CCValAssign::ZExt)
1897 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1898 DAG.getValueType(VA.getValVT()));
1899 else if (VA.getLocInfo() == CCValAssign::BCvt)
1900 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1902 if (VA.isExtInLoc()) {
1903 // Handle MMX values passed in XMM regs.
1904 if (RegVT.isVector()) {
1905 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1908 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1911 assert(VA.isMemLoc());
1912 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1915 // If value is passed via pointer - do a load.
1916 if (VA.getLocInfo() == CCValAssign::Indirect)
1917 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1918 MachinePointerInfo(), false, false, false, 0);
1920 InVals.push_back(ArgValue);
1923 // The x86-64 ABI for returning structs by value requires that we copy
1924 // the sret argument into %rax for the return. Save the argument into
1925 // a virtual register so that we can access it from the return points.
1926 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1927 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1928 unsigned Reg = FuncInfo->getSRetReturnReg();
1930 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1931 FuncInfo->setSRetReturnReg(Reg);
1933 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1934 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1937 unsigned StackSize = CCInfo.getNextStackOffset();
1938 // Align stack specially for tail calls.
1939 if (FuncIsMadeTailCallSafe(CallConv,
1940 MF.getTarget().Options.GuaranteedTailCallOpt))
1941 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1943 // If the function takes variable number of arguments, make a frame index for
1944 // the start of the first vararg value... for expansion of llvm.va_start.
1946 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1947 CallConv != CallingConv::X86_ThisCall)) {
1948 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1951 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1953 // FIXME: We should really autogenerate these arrays
1954 static const uint16_t GPR64ArgRegsWin64[] = {
1955 X86::RCX, X86::RDX, X86::R8, X86::R9
1957 static const uint16_t GPR64ArgRegs64Bit[] = {
1958 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1960 static const uint16_t XMMArgRegs64Bit[] = {
1961 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1962 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1964 const uint16_t *GPR64ArgRegs;
1965 unsigned NumXMMRegs = 0;
1968 // The XMM registers which might contain var arg parameters are shadowed
1969 // in their paired GPR. So we only need to save the GPR to their home
1971 TotalNumIntRegs = 4;
1972 GPR64ArgRegs = GPR64ArgRegsWin64;
1974 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1975 GPR64ArgRegs = GPR64ArgRegs64Bit;
1977 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
1980 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1983 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1984 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1985 "SSE register cannot be used when SSE is disabled!");
1986 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
1987 NoImplicitFloatOps) &&
1988 "SSE register cannot be used when SSE is disabled!");
1989 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
1990 !Subtarget->hasSSE1())
1991 // Kernel mode asks for SSE to be disabled, so don't push them
1993 TotalNumXMMRegs = 0;
1996 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1997 // Get to the caller-allocated home save location. Add 8 to account
1998 // for the return address.
1999 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2000 FuncInfo->setRegSaveFrameIndex(
2001 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2002 // Fixup to set vararg frame on shadow area (4 x i64).
2004 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2006 // For X86-64, if there are vararg parameters that are passed via
2007 // registers, then we must store them to their spots on the stack so
2008 // they may be loaded by deferencing the result of va_next.
2009 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2010 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2011 FuncInfo->setRegSaveFrameIndex(
2012 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2016 // Store the integer parameter registers.
2017 SmallVector<SDValue, 8> MemOps;
2018 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2020 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2021 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2022 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2023 DAG.getIntPtrConstant(Offset));
2024 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2025 &X86::GR64RegClass);
2026 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2028 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2029 MachinePointerInfo::getFixedStack(
2030 FuncInfo->getRegSaveFrameIndex(), Offset),
2032 MemOps.push_back(Store);
2036 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2037 // Now store the XMM (fp + vector) parameter registers.
2038 SmallVector<SDValue, 11> SaveXMMOps;
2039 SaveXMMOps.push_back(Chain);
2041 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2042 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2043 SaveXMMOps.push_back(ALVal);
2045 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2046 FuncInfo->getRegSaveFrameIndex()));
2047 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2048 FuncInfo->getVarArgsFPOffset()));
2050 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2051 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2052 &X86::VR128RegClass);
2053 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2054 SaveXMMOps.push_back(Val);
2056 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2058 &SaveXMMOps[0], SaveXMMOps.size()));
2061 if (!MemOps.empty())
2062 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2063 &MemOps[0], MemOps.size());
2067 // Some CCs need callee pop.
2068 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2069 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2070 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2072 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2073 // If this is an sret function, the return should pop the hidden pointer.
2074 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2075 ArgsAreStructReturn(Ins))
2076 FuncInfo->setBytesToPopOnReturn(4);
2080 // RegSaveFrameIndex is X86-64 only.
2081 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2082 if (CallConv == CallingConv::X86_FastCall ||
2083 CallConv == CallingConv::X86_ThisCall)
2084 // fastcc functions can't have varargs.
2085 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2088 FuncInfo->setArgumentStackSize(StackSize);
2094 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2095 SDValue StackPtr, SDValue Arg,
2096 DebugLoc dl, SelectionDAG &DAG,
2097 const CCValAssign &VA,
2098 ISD::ArgFlagsTy Flags) const {
2099 unsigned LocMemOffset = VA.getLocMemOffset();
2100 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2101 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2102 if (Flags.isByVal())
2103 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2105 return DAG.getStore(Chain, dl, Arg, PtrOff,
2106 MachinePointerInfo::getStack(LocMemOffset),
2110 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2111 /// optimization is performed and it is required.
2113 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2114 SDValue &OutRetAddr, SDValue Chain,
2115 bool IsTailCall, bool Is64Bit,
2116 int FPDiff, DebugLoc dl) const {
2117 // Adjust the Return address stack slot.
2118 EVT VT = getPointerTy();
2119 OutRetAddr = getReturnAddressFrameIndex(DAG);
2121 // Load the "old" Return address.
2122 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2123 false, false, false, 0);
2124 return SDValue(OutRetAddr.getNode(), 1);
2127 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2128 /// optimization is performed and it is required (FPDiff!=0).
2130 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2131 SDValue Chain, SDValue RetAddrFrIdx,
2132 bool Is64Bit, int FPDiff, DebugLoc dl) {
2133 // Store the return address to the appropriate stack slot.
2134 if (!FPDiff) return Chain;
2135 // Calculate the new stack slot for the return address.
2136 int SlotSize = Is64Bit ? 8 : 4;
2137 int NewReturnAddrFI =
2138 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2139 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2140 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
2141 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2142 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2148 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2149 SmallVectorImpl<SDValue> &InVals) const {
2150 SelectionDAG &DAG = CLI.DAG;
2151 DebugLoc &dl = CLI.DL;
2152 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2153 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2154 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2155 SDValue Chain = CLI.Chain;
2156 SDValue Callee = CLI.Callee;
2157 CallingConv::ID CallConv = CLI.CallConv;
2158 bool &isTailCall = CLI.IsTailCall;
2159 bool isVarArg = CLI.IsVarArg;
2161 MachineFunction &MF = DAG.getMachineFunction();
2162 bool Is64Bit = Subtarget->is64Bit();
2163 bool IsWin64 = Subtarget->isTargetWin64();
2164 bool IsWindows = Subtarget->isTargetWindows();
2165 bool IsStructRet = CallIsStructReturn(Outs);
2166 bool IsSibcall = false;
2168 if (MF.getTarget().Options.DisableTailCalls)
2172 // Check if it's really possible to do a tail call.
2173 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2174 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2175 Outs, OutVals, Ins, DAG);
2177 // Sibcalls are automatically detected tailcalls which do not require
2179 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2186 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2187 "Var args not supported with calling convention fastcc or ghc");
2189 // Analyze operands of the call, assigning locations to each operand.
2190 SmallVector<CCValAssign, 16> ArgLocs;
2191 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2192 ArgLocs, *DAG.getContext());
2194 // Allocate shadow area for Win64
2196 CCInfo.AllocateStack(32, 8);
2199 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2201 // Get a count of how many bytes are to be pushed on the stack.
2202 unsigned NumBytes = CCInfo.getNextStackOffset();
2204 // This is a sibcall. The memory operands are available in caller's
2205 // own caller's stack.
2207 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2208 IsTailCallConvention(CallConv))
2209 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2212 if (isTailCall && !IsSibcall) {
2213 // Lower arguments at fp - stackoffset + fpdiff.
2214 unsigned NumBytesCallerPushed =
2215 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2216 FPDiff = NumBytesCallerPushed - NumBytes;
2218 // Set the delta of movement of the returnaddr stackslot.
2219 // But only set if delta is greater than previous delta.
2220 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2221 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2225 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2227 SDValue RetAddrFrIdx;
2228 // Load return address for tail calls.
2229 if (isTailCall && FPDiff)
2230 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2231 Is64Bit, FPDiff, dl);
2233 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2234 SmallVector<SDValue, 8> MemOpChains;
2237 // Walk the register/memloc assignments, inserting copies/loads. In the case
2238 // of tail call optimization arguments are handle later.
2239 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2240 CCValAssign &VA = ArgLocs[i];
2241 EVT RegVT = VA.getLocVT();
2242 SDValue Arg = OutVals[i];
2243 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2244 bool isByVal = Flags.isByVal();
2246 // Promote the value if needed.
2247 switch (VA.getLocInfo()) {
2248 default: llvm_unreachable("Unknown loc info!");
2249 case CCValAssign::Full: break;
2250 case CCValAssign::SExt:
2251 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2253 case CCValAssign::ZExt:
2254 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2256 case CCValAssign::AExt:
2257 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2258 // Special case: passing MMX values in XMM registers.
2259 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2260 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2261 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2263 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2265 case CCValAssign::BCvt:
2266 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2268 case CCValAssign::Indirect: {
2269 // Store the argument.
2270 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2271 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2272 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2273 MachinePointerInfo::getFixedStack(FI),
2280 if (VA.isRegLoc()) {
2281 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2282 if (isVarArg && IsWin64) {
2283 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2284 // shadow reg if callee is a varargs function.
2285 unsigned ShadowReg = 0;
2286 switch (VA.getLocReg()) {
2287 case X86::XMM0: ShadowReg = X86::RCX; break;
2288 case X86::XMM1: ShadowReg = X86::RDX; break;
2289 case X86::XMM2: ShadowReg = X86::R8; break;
2290 case X86::XMM3: ShadowReg = X86::R9; break;
2293 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2295 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2296 assert(VA.isMemLoc());
2297 if (StackPtr.getNode() == 0)
2298 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2299 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2300 dl, DAG, VA, Flags));
2304 if (!MemOpChains.empty())
2305 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2306 &MemOpChains[0], MemOpChains.size());
2308 if (Subtarget->isPICStyleGOT()) {
2309 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2312 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2313 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy())));
2315 // If we are tail calling and generating PIC/GOT style code load the
2316 // address of the callee into ECX. The value in ecx is used as target of
2317 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2318 // for tail calls on PIC/GOT architectures. Normally we would just put the
2319 // address of GOT into ebx and then call target@PLT. But for tail calls
2320 // ebx would be restored (since ebx is callee saved) before jumping to the
2323 // Note: The actual moving to ECX is done further down.
2324 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2325 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2326 !G->getGlobal()->hasProtectedVisibility())
2327 Callee = LowerGlobalAddress(Callee, DAG);
2328 else if (isa<ExternalSymbolSDNode>(Callee))
2329 Callee = LowerExternalSymbol(Callee, DAG);
2333 if (Is64Bit && isVarArg && !IsWin64) {
2334 // From AMD64 ABI document:
2335 // For calls that may call functions that use varargs or stdargs
2336 // (prototype-less calls or calls to functions containing ellipsis (...) in
2337 // the declaration) %al is used as hidden argument to specify the number
2338 // of SSE registers used. The contents of %al do not need to match exactly
2339 // the number of registers, but must be an ubound on the number of SSE
2340 // registers used and is in the range 0 - 8 inclusive.
2342 // Count the number of XMM registers allocated.
2343 static const uint16_t XMMArgRegs[] = {
2344 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2345 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2347 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2348 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2349 && "SSE registers cannot be used when SSE is disabled");
2351 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2352 DAG.getConstant(NumXMMRegs, MVT::i8)));
2355 // For tail calls lower the arguments to the 'real' stack slot.
2357 // Force all the incoming stack arguments to be loaded from the stack
2358 // before any new outgoing arguments are stored to the stack, because the
2359 // outgoing stack slots may alias the incoming argument stack slots, and
2360 // the alias isn't otherwise explicit. This is slightly more conservative
2361 // than necessary, because it means that each store effectively depends
2362 // on every argument instead of just those arguments it would clobber.
2363 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2365 SmallVector<SDValue, 8> MemOpChains2;
2368 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2369 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2370 CCValAssign &VA = ArgLocs[i];
2373 assert(VA.isMemLoc());
2374 SDValue Arg = OutVals[i];
2375 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2376 // Create frame index.
2377 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2378 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2379 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2380 FIN = DAG.getFrameIndex(FI, getPointerTy());
2382 if (Flags.isByVal()) {
2383 // Copy relative to framepointer.
2384 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2385 if (StackPtr.getNode() == 0)
2386 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2388 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2390 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2394 // Store relative to framepointer.
2395 MemOpChains2.push_back(
2396 DAG.getStore(ArgChain, dl, Arg, FIN,
2397 MachinePointerInfo::getFixedStack(FI),
2403 if (!MemOpChains2.empty())
2404 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2405 &MemOpChains2[0], MemOpChains2.size());
2407 // Store the return address to the appropriate stack slot.
2408 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2412 // Build a sequence of copy-to-reg nodes chained together with token chain
2413 // and flag operands which copy the outgoing args into registers.
2415 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2416 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2417 RegsToPass[i].second, InFlag);
2418 InFlag = Chain.getValue(1);
2421 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2422 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2423 // In the 64-bit large code model, we have to make all calls
2424 // through a register, since the call instruction's 32-bit
2425 // pc-relative offset may not be large enough to hold the whole
2427 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2428 // If the callee is a GlobalAddress node (quite common, every direct call
2429 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2432 // We should use extra load for direct calls to dllimported functions in
2434 const GlobalValue *GV = G->getGlobal();
2435 if (!GV->hasDLLImportLinkage()) {
2436 unsigned char OpFlags = 0;
2437 bool ExtraLoad = false;
2438 unsigned WrapperKind = ISD::DELETED_NODE;
2440 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2441 // external symbols most go through the PLT in PIC mode. If the symbol
2442 // has hidden or protected visibility, or if it is static or local, then
2443 // we don't need to use the PLT - we can directly call it.
2444 if (Subtarget->isTargetELF() &&
2445 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2446 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2447 OpFlags = X86II::MO_PLT;
2448 } else if (Subtarget->isPICStyleStubAny() &&
2449 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2450 (!Subtarget->getTargetTriple().isMacOSX() ||
2451 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2452 // PC-relative references to external symbols should go through $stub,
2453 // unless we're building with the leopard linker or later, which
2454 // automatically synthesizes these stubs.
2455 OpFlags = X86II::MO_DARWIN_STUB;
2456 } else if (Subtarget->isPICStyleRIPRel() &&
2457 isa<Function>(GV) &&
2458 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2459 // If the function is marked as non-lazy, generate an indirect call
2460 // which loads from the GOT directly. This avoids runtime overhead
2461 // at the cost of eager binding (and one extra byte of encoding).
2462 OpFlags = X86II::MO_GOTPCREL;
2463 WrapperKind = X86ISD::WrapperRIP;
2467 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2468 G->getOffset(), OpFlags);
2470 // Add a wrapper if needed.
2471 if (WrapperKind != ISD::DELETED_NODE)
2472 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2473 // Add extra indirection if needed.
2475 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2476 MachinePointerInfo::getGOT(),
2477 false, false, false, 0);
2479 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2480 unsigned char OpFlags = 0;
2482 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2483 // external symbols should go through the PLT.
2484 if (Subtarget->isTargetELF() &&
2485 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2486 OpFlags = X86II::MO_PLT;
2487 } else if (Subtarget->isPICStyleStubAny() &&
2488 (!Subtarget->getTargetTriple().isMacOSX() ||
2489 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2490 // PC-relative references to external symbols should go through $stub,
2491 // unless we're building with the leopard linker or later, which
2492 // automatically synthesizes these stubs.
2493 OpFlags = X86II::MO_DARWIN_STUB;
2496 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2500 // Returns a chain & a flag for retval copy to use.
2501 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2502 SmallVector<SDValue, 8> Ops;
2504 if (!IsSibcall && isTailCall) {
2505 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2506 DAG.getIntPtrConstant(0, true), InFlag);
2507 InFlag = Chain.getValue(1);
2510 Ops.push_back(Chain);
2511 Ops.push_back(Callee);
2514 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2516 // Add argument registers to the end of the list so that they are known live
2518 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2519 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2520 RegsToPass[i].second.getValueType()));
2522 // Add a register mask operand representing the call-preserved registers.
2523 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2524 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2525 assert(Mask && "Missing call preserved mask for calling convention");
2526 Ops.push_back(DAG.getRegisterMask(Mask));
2528 if (InFlag.getNode())
2529 Ops.push_back(InFlag);
2533 //// If this is the first return lowered for this function, add the regs
2534 //// to the liveout set for the function.
2535 // This isn't right, although it's probably harmless on x86; liveouts
2536 // should be computed from returns not tail calls. Consider a void
2537 // function making a tail call to a function returning int.
2538 return DAG.getNode(X86ISD::TC_RETURN, dl,
2539 NodeTys, &Ops[0], Ops.size());
2542 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2543 InFlag = Chain.getValue(1);
2545 // Create the CALLSEQ_END node.
2546 unsigned NumBytesForCalleeToPush;
2547 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2548 getTargetMachine().Options.GuaranteedTailCallOpt))
2549 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2550 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2552 // If this is a call to a struct-return function, the callee
2553 // pops the hidden struct pointer, so we have to push it back.
2554 // This is common for Darwin/X86, Linux & Mingw32 targets.
2555 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2556 NumBytesForCalleeToPush = 4;
2558 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2560 // Returns a flag for retval copy to use.
2562 Chain = DAG.getCALLSEQ_END(Chain,
2563 DAG.getIntPtrConstant(NumBytes, true),
2564 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2567 InFlag = Chain.getValue(1);
2570 // Handle result values, copying them out of physregs into vregs that we
2572 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2573 Ins, dl, DAG, InVals);
2577 //===----------------------------------------------------------------------===//
2578 // Fast Calling Convention (tail call) implementation
2579 //===----------------------------------------------------------------------===//
2581 // Like std call, callee cleans arguments, convention except that ECX is
2582 // reserved for storing the tail called function address. Only 2 registers are
2583 // free for argument passing (inreg). Tail call optimization is performed
2585 // * tailcallopt is enabled
2586 // * caller/callee are fastcc
2587 // On X86_64 architecture with GOT-style position independent code only local
2588 // (within module) calls are supported at the moment.
2589 // To keep the stack aligned according to platform abi the function
2590 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2591 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2592 // If a tail called function callee has more arguments than the caller the
2593 // caller needs to make sure that there is room to move the RETADDR to. This is
2594 // achieved by reserving an area the size of the argument delta right after the
2595 // original REtADDR, but before the saved framepointer or the spilled registers
2596 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2608 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2609 /// for a 16 byte align requirement.
2611 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2612 SelectionDAG& DAG) const {
2613 MachineFunction &MF = DAG.getMachineFunction();
2614 const TargetMachine &TM = MF.getTarget();
2615 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2616 unsigned StackAlignment = TFI.getStackAlignment();
2617 uint64_t AlignMask = StackAlignment - 1;
2618 int64_t Offset = StackSize;
2619 uint64_t SlotSize = TD->getPointerSize();
2620 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2621 // Number smaller than 12 so just add the difference.
2622 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2624 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2625 Offset = ((~AlignMask) & Offset) + StackAlignment +
2626 (StackAlignment-SlotSize);
2631 /// MatchingStackOffset - Return true if the given stack call argument is
2632 /// already available in the same position (relatively) of the caller's
2633 /// incoming argument stack.
2635 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2636 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2637 const X86InstrInfo *TII) {
2638 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2640 if (Arg.getOpcode() == ISD::CopyFromReg) {
2641 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2642 if (!TargetRegisterInfo::isVirtualRegister(VR))
2644 MachineInstr *Def = MRI->getVRegDef(VR);
2647 if (!Flags.isByVal()) {
2648 if (!TII->isLoadFromStackSlot(Def, FI))
2651 unsigned Opcode = Def->getOpcode();
2652 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2653 Def->getOperand(1).isFI()) {
2654 FI = Def->getOperand(1).getIndex();
2655 Bytes = Flags.getByValSize();
2659 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2660 if (Flags.isByVal())
2661 // ByVal argument is passed in as a pointer but it's now being
2662 // dereferenced. e.g.
2663 // define @foo(%struct.X* %A) {
2664 // tail call @bar(%struct.X* byval %A)
2667 SDValue Ptr = Ld->getBasePtr();
2668 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2671 FI = FINode->getIndex();
2672 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2673 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2674 FI = FINode->getIndex();
2675 Bytes = Flags.getByValSize();
2679 assert(FI != INT_MAX);
2680 if (!MFI->isFixedObjectIndex(FI))
2682 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2685 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2686 /// for tail call optimization. Targets which want to do tail call
2687 /// optimization should implement this function.
2689 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2690 CallingConv::ID CalleeCC,
2692 bool isCalleeStructRet,
2693 bool isCallerStructRet,
2694 const SmallVectorImpl<ISD::OutputArg> &Outs,
2695 const SmallVectorImpl<SDValue> &OutVals,
2696 const SmallVectorImpl<ISD::InputArg> &Ins,
2697 SelectionDAG& DAG) const {
2698 if (!IsTailCallConvention(CalleeCC) &&
2699 CalleeCC != CallingConv::C)
2702 // If -tailcallopt is specified, make fastcc functions tail-callable.
2703 const MachineFunction &MF = DAG.getMachineFunction();
2704 const Function *CallerF = DAG.getMachineFunction().getFunction();
2705 CallingConv::ID CallerCC = CallerF->getCallingConv();
2706 bool CCMatch = CallerCC == CalleeCC;
2708 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2709 if (IsTailCallConvention(CalleeCC) && CCMatch)
2714 // Look for obvious safe cases to perform tail call optimization that do not
2715 // require ABI changes. This is what gcc calls sibcall.
2717 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2718 // emit a special epilogue.
2719 if (RegInfo->needsStackRealignment(MF))
2722 // Also avoid sibcall optimization if either caller or callee uses struct
2723 // return semantics.
2724 if (isCalleeStructRet || isCallerStructRet)
2727 // An stdcall caller is expected to clean up its arguments; the callee
2728 // isn't going to do that.
2729 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2732 // Do not sibcall optimize vararg calls unless all arguments are passed via
2734 if (isVarArg && !Outs.empty()) {
2736 // Optimizing for varargs on Win64 is unlikely to be safe without
2737 // additional testing.
2738 if (Subtarget->isTargetWin64())
2741 SmallVector<CCValAssign, 16> ArgLocs;
2742 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2743 getTargetMachine(), ArgLocs, *DAG.getContext());
2745 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2746 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2747 if (!ArgLocs[i].isRegLoc())
2751 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2752 // stack. Therefore, if it's not used by the call it is not safe to optimize
2753 // this into a sibcall.
2754 bool Unused = false;
2755 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2762 SmallVector<CCValAssign, 16> RVLocs;
2763 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2764 getTargetMachine(), RVLocs, *DAG.getContext());
2765 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2766 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2767 CCValAssign &VA = RVLocs[i];
2768 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2773 // If the calling conventions do not match, then we'd better make sure the
2774 // results are returned in the same way as what the caller expects.
2776 SmallVector<CCValAssign, 16> RVLocs1;
2777 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2778 getTargetMachine(), RVLocs1, *DAG.getContext());
2779 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2781 SmallVector<CCValAssign, 16> RVLocs2;
2782 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2783 getTargetMachine(), RVLocs2, *DAG.getContext());
2784 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2786 if (RVLocs1.size() != RVLocs2.size())
2788 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2789 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2791 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2793 if (RVLocs1[i].isRegLoc()) {
2794 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2797 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2803 // If the callee takes no arguments then go on to check the results of the
2805 if (!Outs.empty()) {
2806 // Check if stack adjustment is needed. For now, do not do this if any
2807 // argument is passed on the stack.
2808 SmallVector<CCValAssign, 16> ArgLocs;
2809 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2810 getTargetMachine(), ArgLocs, *DAG.getContext());
2812 // Allocate shadow area for Win64
2813 if (Subtarget->isTargetWin64()) {
2814 CCInfo.AllocateStack(32, 8);
2817 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2818 if (CCInfo.getNextStackOffset()) {
2819 MachineFunction &MF = DAG.getMachineFunction();
2820 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2823 // Check if the arguments are already laid out in the right way as
2824 // the caller's fixed stack objects.
2825 MachineFrameInfo *MFI = MF.getFrameInfo();
2826 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2827 const X86InstrInfo *TII =
2828 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2829 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2830 CCValAssign &VA = ArgLocs[i];
2831 SDValue Arg = OutVals[i];
2832 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2833 if (VA.getLocInfo() == CCValAssign::Indirect)
2835 if (!VA.isRegLoc()) {
2836 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2843 // If the tailcall address may be in a register, then make sure it's
2844 // possible to register allocate for it. In 32-bit, the call address can
2845 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2846 // callee-saved registers are restored. These happen to be the same
2847 // registers used to pass 'inreg' arguments so watch out for those.
2848 if (!Subtarget->is64Bit() &&
2849 !isa<GlobalAddressSDNode>(Callee) &&
2850 !isa<ExternalSymbolSDNode>(Callee)) {
2851 unsigned NumInRegs = 0;
2852 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2853 CCValAssign &VA = ArgLocs[i];
2856 unsigned Reg = VA.getLocReg();
2859 case X86::EAX: case X86::EDX: case X86::ECX:
2860 if (++NumInRegs == 3)
2872 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2873 return X86::createFastISel(funcInfo);
2877 //===----------------------------------------------------------------------===//
2878 // Other Lowering Hooks
2879 //===----------------------------------------------------------------------===//
2881 static bool MayFoldLoad(SDValue Op) {
2882 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2885 static bool MayFoldIntoStore(SDValue Op) {
2886 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2889 static bool isTargetShuffle(unsigned Opcode) {
2891 default: return false;
2892 case X86ISD::PSHUFD:
2893 case X86ISD::PSHUFHW:
2894 case X86ISD::PSHUFLW:
2896 case X86ISD::PALIGN:
2897 case X86ISD::MOVLHPS:
2898 case X86ISD::MOVLHPD:
2899 case X86ISD::MOVHLPS:
2900 case X86ISD::MOVLPS:
2901 case X86ISD::MOVLPD:
2902 case X86ISD::MOVSHDUP:
2903 case X86ISD::MOVSLDUP:
2904 case X86ISD::MOVDDUP:
2907 case X86ISD::UNPCKL:
2908 case X86ISD::UNPCKH:
2909 case X86ISD::VPERMILP:
2910 case X86ISD::VPERM2X128:
2911 case X86ISD::VPERMI:
2916 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2917 SDValue V1, SelectionDAG &DAG) {
2919 default: llvm_unreachable("Unknown x86 shuffle node");
2920 case X86ISD::MOVSHDUP:
2921 case X86ISD::MOVSLDUP:
2922 case X86ISD::MOVDDUP:
2923 return DAG.getNode(Opc, dl, VT, V1);
2927 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2928 SDValue V1, unsigned TargetMask,
2929 SelectionDAG &DAG) {
2931 default: llvm_unreachable("Unknown x86 shuffle node");
2932 case X86ISD::PSHUFD:
2933 case X86ISD::PSHUFHW:
2934 case X86ISD::PSHUFLW:
2935 case X86ISD::VPERMILP:
2936 case X86ISD::VPERMI:
2937 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2941 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2942 SDValue V1, SDValue V2, unsigned TargetMask,
2943 SelectionDAG &DAG) {
2945 default: llvm_unreachable("Unknown x86 shuffle node");
2946 case X86ISD::PALIGN:
2948 case X86ISD::VPERM2X128:
2949 return DAG.getNode(Opc, dl, VT, V1, V2,
2950 DAG.getConstant(TargetMask, MVT::i8));
2954 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2955 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2957 default: llvm_unreachable("Unknown x86 shuffle node");
2958 case X86ISD::MOVLHPS:
2959 case X86ISD::MOVLHPD:
2960 case X86ISD::MOVHLPS:
2961 case X86ISD::MOVLPS:
2962 case X86ISD::MOVLPD:
2965 case X86ISD::UNPCKL:
2966 case X86ISD::UNPCKH:
2967 return DAG.getNode(Opc, dl, VT, V1, V2);
2971 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2972 MachineFunction &MF = DAG.getMachineFunction();
2973 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2974 int ReturnAddrIndex = FuncInfo->getRAIndex();
2976 if (ReturnAddrIndex == 0) {
2977 // Set up a frame object for the return address.
2978 uint64_t SlotSize = TD->getPointerSize();
2979 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2981 FuncInfo->setRAIndex(ReturnAddrIndex);
2984 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2988 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2989 bool hasSymbolicDisplacement) {
2990 // Offset should fit into 32 bit immediate field.
2991 if (!isInt<32>(Offset))
2994 // If we don't have a symbolic displacement - we don't have any extra
2996 if (!hasSymbolicDisplacement)
2999 // FIXME: Some tweaks might be needed for medium code model.
3000 if (M != CodeModel::Small && M != CodeModel::Kernel)
3003 // For small code model we assume that latest object is 16MB before end of 31
3004 // bits boundary. We may also accept pretty large negative constants knowing
3005 // that all objects are in the positive half of address space.
3006 if (M == CodeModel::Small && Offset < 16*1024*1024)
3009 // For kernel code model we know that all object resist in the negative half
3010 // of 32bits address space. We may not accept negative offsets, since they may
3011 // be just off and we may accept pretty large positive ones.
3012 if (M == CodeModel::Kernel && Offset > 0)
3018 /// isCalleePop - Determines whether the callee is required to pop its
3019 /// own arguments. Callee pop is necessary to support tail calls.
3020 bool X86::isCalleePop(CallingConv::ID CallingConv,
3021 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3025 switch (CallingConv) {
3028 case CallingConv::X86_StdCall:
3030 case CallingConv::X86_FastCall:
3032 case CallingConv::X86_ThisCall:
3034 case CallingConv::Fast:
3036 case CallingConv::GHC:
3041 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3042 /// specific condition code, returning the condition code and the LHS/RHS of the
3043 /// comparison to make.
3044 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3045 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3047 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3048 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3049 // X > -1 -> X == 0, jump !sign.
3050 RHS = DAG.getConstant(0, RHS.getValueType());
3051 return X86::COND_NS;
3053 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3054 // X < 0 -> X == 0, jump on sign.
3057 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3059 RHS = DAG.getConstant(0, RHS.getValueType());
3060 return X86::COND_LE;
3064 switch (SetCCOpcode) {
3065 default: llvm_unreachable("Invalid integer condition!");
3066 case ISD::SETEQ: return X86::COND_E;
3067 case ISD::SETGT: return X86::COND_G;
3068 case ISD::SETGE: return X86::COND_GE;
3069 case ISD::SETLT: return X86::COND_L;
3070 case ISD::SETLE: return X86::COND_LE;
3071 case ISD::SETNE: return X86::COND_NE;
3072 case ISD::SETULT: return X86::COND_B;
3073 case ISD::SETUGT: return X86::COND_A;
3074 case ISD::SETULE: return X86::COND_BE;
3075 case ISD::SETUGE: return X86::COND_AE;
3079 // First determine if it is required or is profitable to flip the operands.
3081 // If LHS is a foldable load, but RHS is not, flip the condition.
3082 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3083 !ISD::isNON_EXTLoad(RHS.getNode())) {
3084 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3085 std::swap(LHS, RHS);
3088 switch (SetCCOpcode) {
3094 std::swap(LHS, RHS);
3098 // On a floating point condition, the flags are set as follows:
3100 // 0 | 0 | 0 | X > Y
3101 // 0 | 0 | 1 | X < Y
3102 // 1 | 0 | 0 | X == Y
3103 // 1 | 1 | 1 | unordered
3104 switch (SetCCOpcode) {
3105 default: llvm_unreachable("Condcode should be pre-legalized away");
3107 case ISD::SETEQ: return X86::COND_E;
3108 case ISD::SETOLT: // flipped
3110 case ISD::SETGT: return X86::COND_A;
3111 case ISD::SETOLE: // flipped
3113 case ISD::SETGE: return X86::COND_AE;
3114 case ISD::SETUGT: // flipped
3116 case ISD::SETLT: return X86::COND_B;
3117 case ISD::SETUGE: // flipped
3119 case ISD::SETLE: return X86::COND_BE;
3121 case ISD::SETNE: return X86::COND_NE;
3122 case ISD::SETUO: return X86::COND_P;
3123 case ISD::SETO: return X86::COND_NP;
3125 case ISD::SETUNE: return X86::COND_INVALID;
3129 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3130 /// code. Current x86 isa includes the following FP cmov instructions:
3131 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3132 static bool hasFPCMov(unsigned X86CC) {
3148 /// isFPImmLegal - Returns true if the target can instruction select the
3149 /// specified FP immediate natively. If false, the legalizer will
3150 /// materialize the FP immediate as a load from a constant pool.
3151 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3152 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3153 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3159 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3160 /// the specified range (L, H].
3161 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3162 return (Val < 0) || (Val >= Low && Val < Hi);
3165 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3166 /// specified value.
3167 static bool isUndefOrEqual(int Val, int CmpVal) {
3168 if (Val < 0 || Val == CmpVal)
3173 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3174 /// from position Pos and ending in Pos+Size, falls within the specified
3175 /// sequential range (L, L+Pos]. or is undef.
3176 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3177 unsigned Pos, unsigned Size, int Low) {
3178 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3179 if (!isUndefOrEqual(Mask[i], Low))
3184 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3185 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3186 /// the second operand.
3187 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3188 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3189 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3190 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3191 return (Mask[0] < 2 && Mask[1] < 2);
3195 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3196 /// is suitable for input to PSHUFHW.
3197 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3198 if (VT != MVT::v8i16 && (!HasAVX2 || VT != MVT::v16i16))
3201 // Lower quadword copied in order or undef.
3202 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3205 // Upper quadword shuffled.
3206 for (unsigned i = 4; i != 8; ++i)
3207 if (!isUndefOrInRange(Mask[i], 4, 8))
3210 if (VT == MVT::v16i16) {
3211 // Lower quadword copied in order or undef.
3212 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3215 // Upper quadword shuffled.
3216 for (unsigned i = 12; i != 16; ++i)
3217 if (!isUndefOrInRange(Mask[i], 12, 16))
3224 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3225 /// is suitable for input to PSHUFLW.
3226 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3227 if (VT != MVT::v8i16 && (!HasAVX2 || VT != MVT::v16i16))
3230 // Upper quadword copied in order.
3231 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3234 // Lower quadword shuffled.
3235 for (unsigned i = 0; i != 4; ++i)
3236 if (!isUndefOrInRange(Mask[i], 0, 4))
3239 if (VT == MVT::v16i16) {
3240 // Upper quadword copied in order.
3241 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3244 // Lower quadword shuffled.
3245 for (unsigned i = 8; i != 12; ++i)
3246 if (!isUndefOrInRange(Mask[i], 8, 12))
3253 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3254 /// is suitable for input to PALIGNR.
3255 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
3256 const X86Subtarget *Subtarget) {
3257 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) ||
3258 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()))
3261 unsigned NumElts = VT.getVectorNumElements();
3262 unsigned NumLanes = VT.getSizeInBits()/128;
3263 unsigned NumLaneElts = NumElts/NumLanes;
3265 // Do not handle 64-bit element shuffles with palignr.
3266 if (NumLaneElts == 2)
3269 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3271 for (i = 0; i != NumLaneElts; ++i) {
3276 // Lane is all undef, go to next lane
3277 if (i == NumLaneElts)
3280 int Start = Mask[i+l];
3282 // Make sure its in this lane in one of the sources
3283 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3284 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3287 // If not lane 0, then we must match lane 0
3288 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3291 // Correct second source to be contiguous with first source
3292 if (Start >= (int)NumElts)
3293 Start -= NumElts - NumLaneElts;
3295 // Make sure we're shifting in the right direction.
3296 if (Start <= (int)(i+l))
3301 // Check the rest of the elements to see if they are consecutive.
3302 for (++i; i != NumLaneElts; ++i) {
3303 int Idx = Mask[i+l];
3305 // Make sure its in this lane
3306 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3307 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3310 // If not lane 0, then we must match lane 0
3311 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3314 if (Idx >= (int)NumElts)
3315 Idx -= NumElts - NumLaneElts;
3317 if (!isUndefOrEqual(Idx, Start+i))
3326 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3327 /// the two vector operands have swapped position.
3328 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3329 unsigned NumElems) {
3330 for (unsigned i = 0; i != NumElems; ++i) {
3334 else if (idx < (int)NumElems)
3335 Mask[i] = idx + NumElems;
3337 Mask[i] = idx - NumElems;
3341 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3342 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3343 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3344 /// reverse of what x86 shuffles want.
3345 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX,
3346 bool Commuted = false) {
3347 if (!HasAVX && VT.getSizeInBits() == 256)
3350 unsigned NumElems = VT.getVectorNumElements();
3351 unsigned NumLanes = VT.getSizeInBits()/128;
3352 unsigned NumLaneElems = NumElems/NumLanes;
3354 if (NumLaneElems != 2 && NumLaneElems != 4)
3357 // VSHUFPSY divides the resulting vector into 4 chunks.
3358 // The sources are also splitted into 4 chunks, and each destination
3359 // chunk must come from a different source chunk.
3361 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3362 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3364 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3365 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3367 // VSHUFPDY divides the resulting vector into 4 chunks.
3368 // The sources are also splitted into 4 chunks, and each destination
3369 // chunk must come from a different source chunk.
3371 // SRC1 => X3 X2 X1 X0
3372 // SRC2 => Y3 Y2 Y1 Y0
3374 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3376 unsigned HalfLaneElems = NumLaneElems/2;
3377 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3378 for (unsigned i = 0; i != NumLaneElems; ++i) {
3379 int Idx = Mask[i+l];
3380 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3381 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3383 // For VSHUFPSY, the mask of the second half must be the same as the
3384 // first but with the appropriate offsets. This works in the same way as
3385 // VPERMILPS works with masks.
3386 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3388 if (!isUndefOrEqual(Idx, Mask[i]+l))
3396 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3397 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3398 static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) {
3399 unsigned NumElems = VT.getVectorNumElements();
3401 if (VT.getSizeInBits() != 128)
3407 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3408 return isUndefOrEqual(Mask[0], 6) &&
3409 isUndefOrEqual(Mask[1], 7) &&
3410 isUndefOrEqual(Mask[2], 2) &&
3411 isUndefOrEqual(Mask[3], 3);
3414 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3415 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3417 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) {
3418 unsigned NumElems = VT.getVectorNumElements();
3420 if (VT.getSizeInBits() != 128)
3426 return isUndefOrEqual(Mask[0], 2) &&
3427 isUndefOrEqual(Mask[1], 3) &&
3428 isUndefOrEqual(Mask[2], 2) &&
3429 isUndefOrEqual(Mask[3], 3);
3432 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3433 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3434 static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) {
3435 if (VT.getSizeInBits() != 128)
3438 unsigned NumElems = VT.getVectorNumElements();
3440 if (NumElems != 2 && NumElems != 4)
3443 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3444 if (!isUndefOrEqual(Mask[i], i + NumElems))
3447 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3448 if (!isUndefOrEqual(Mask[i], i))
3454 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3455 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3456 static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) {
3457 unsigned NumElems = VT.getVectorNumElements();
3459 if ((NumElems != 2 && NumElems != 4)
3460 || VT.getSizeInBits() > 128)
3463 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3464 if (!isUndefOrEqual(Mask[i], i))
3467 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3468 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3475 // Some special combinations that can be optimized.
3478 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3479 SelectionDAG &DAG) {
3480 EVT VT = SVOp->getValueType(0);
3481 DebugLoc dl = SVOp->getDebugLoc();
3483 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3486 ArrayRef<int> Mask = SVOp->getMask();
3488 // These are the special masks that may be optimized.
3489 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3490 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3491 bool MatchEvenMask = true;
3492 bool MatchOddMask = true;
3493 for (int i=0; i<8; ++i) {
3494 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
3495 MatchEvenMask = false;
3496 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
3497 MatchOddMask = false;
3499 static const int CompactionMaskEven[] = {0, 2, -1, -1, 4, 6, -1, -1};
3500 static const int CompactionMaskOdd [] = {1, 3, -1, -1, 5, 7, -1, -1};
3502 const int *CompactionMask;
3504 CompactionMask = CompactionMaskEven;
3505 else if (MatchOddMask)
3506 CompactionMask = CompactionMaskOdd;
3510 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
3512 SDValue Op0 = DAG.getVectorShuffle(VT, dl, SVOp->getOperand(0),
3513 UndefNode, CompactionMask);
3514 SDValue Op1 = DAG.getVectorShuffle(VT, dl, SVOp->getOperand(1),
3515 UndefNode, CompactionMask);
3516 static const int UnpackMask[] = {0, 8, 1, 9, 4, 12, 5, 13};
3517 return DAG.getVectorShuffle(VT, dl, Op0, Op1, UnpackMask);
3520 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3521 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3522 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3523 bool HasAVX2, bool V2IsSplat = false) {
3524 unsigned NumElts = VT.getVectorNumElements();
3526 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3527 "Unsupported vector type for unpckh");
3529 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3530 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3533 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3534 // independently on 128-bit lanes.
3535 unsigned NumLanes = VT.getSizeInBits()/128;
3536 unsigned NumLaneElts = NumElts/NumLanes;
3538 for (unsigned l = 0; l != NumLanes; ++l) {
3539 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3540 i != (l+1)*NumLaneElts;
3543 int BitI1 = Mask[i+1];
3544 if (!isUndefOrEqual(BitI, j))
3547 if (!isUndefOrEqual(BitI1, NumElts))
3550 if (!isUndefOrEqual(BitI1, j + NumElts))
3559 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3560 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3561 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3562 bool HasAVX2, bool V2IsSplat = false) {
3563 unsigned NumElts = VT.getVectorNumElements();
3565 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3566 "Unsupported vector type for unpckh");
3568 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3569 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3572 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3573 // independently on 128-bit lanes.
3574 unsigned NumLanes = VT.getSizeInBits()/128;
3575 unsigned NumLaneElts = NumElts/NumLanes;
3577 for (unsigned l = 0; l != NumLanes; ++l) {
3578 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3579 i != (l+1)*NumLaneElts; i += 2, ++j) {
3581 int BitI1 = Mask[i+1];
3582 if (!isUndefOrEqual(BitI, j))
3585 if (isUndefOrEqual(BitI1, NumElts))
3588 if (!isUndefOrEqual(BitI1, j+NumElts))
3596 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3597 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3599 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT,
3601 unsigned NumElts = VT.getVectorNumElements();
3603 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3604 "Unsupported vector type for unpckh");
3606 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3607 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3610 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3611 // FIXME: Need a better way to get rid of this, there's no latency difference
3612 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3613 // the former later. We should also remove the "_undef" special mask.
3614 if (NumElts == 4 && VT.getSizeInBits() == 256)
3617 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3618 // independently on 128-bit lanes.
3619 unsigned NumLanes = VT.getSizeInBits()/128;
3620 unsigned NumLaneElts = NumElts/NumLanes;
3622 for (unsigned l = 0; l != NumLanes; ++l) {
3623 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3624 i != (l+1)*NumLaneElts;
3627 int BitI1 = Mask[i+1];
3629 if (!isUndefOrEqual(BitI, j))
3631 if (!isUndefOrEqual(BitI1, j))
3639 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3640 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3642 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3643 unsigned NumElts = VT.getVectorNumElements();
3645 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3646 "Unsupported vector type for unpckh");
3648 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3649 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3652 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3653 // independently on 128-bit lanes.
3654 unsigned NumLanes = VT.getSizeInBits()/128;
3655 unsigned NumLaneElts = NumElts/NumLanes;
3657 for (unsigned l = 0; l != NumLanes; ++l) {
3658 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3659 i != (l+1)*NumLaneElts; i += 2, ++j) {
3661 int BitI1 = Mask[i+1];
3662 if (!isUndefOrEqual(BitI, j))
3664 if (!isUndefOrEqual(BitI1, j))
3671 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3672 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3673 /// MOVSD, and MOVD, i.e. setting the lowest element.
3674 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
3675 if (VT.getVectorElementType().getSizeInBits() < 32)
3677 if (VT.getSizeInBits() == 256)
3680 unsigned NumElts = VT.getVectorNumElements();
3682 if (!isUndefOrEqual(Mask[0], NumElts))
3685 for (unsigned i = 1; i != NumElts; ++i)
3686 if (!isUndefOrEqual(Mask[i], i))
3692 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3693 /// as permutations between 128-bit chunks or halves. As an example: this
3695 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3696 /// The first half comes from the second half of V1 and the second half from the
3697 /// the second half of V2.
3698 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3699 if (!HasAVX || VT.getSizeInBits() != 256)
3702 // The shuffle result is divided into half A and half B. In total the two
3703 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3704 // B must come from C, D, E or F.
3705 unsigned HalfSize = VT.getVectorNumElements()/2;
3706 bool MatchA = false, MatchB = false;
3708 // Check if A comes from one of C, D, E, F.
3709 for (unsigned Half = 0; Half != 4; ++Half) {
3710 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3716 // Check if B comes from one of C, D, E, F.
3717 for (unsigned Half = 0; Half != 4; ++Half) {
3718 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3724 return MatchA && MatchB;
3727 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3728 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3729 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3730 EVT VT = SVOp->getValueType(0);
3732 unsigned HalfSize = VT.getVectorNumElements()/2;
3734 unsigned FstHalf = 0, SndHalf = 0;
3735 for (unsigned i = 0; i < HalfSize; ++i) {
3736 if (SVOp->getMaskElt(i) > 0) {
3737 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3741 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3742 if (SVOp->getMaskElt(i) > 0) {
3743 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3748 return (FstHalf | (SndHalf << 4));
3751 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3752 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3753 /// Note that VPERMIL mask matching is different depending whether theunderlying
3754 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3755 /// to the same elements of the low, but to the higher half of the source.
3756 /// In VPERMILPD the two lanes could be shuffled independently of each other
3757 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
3758 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3762 unsigned NumElts = VT.getVectorNumElements();
3763 // Only match 256-bit with 32/64-bit types
3764 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8))
3767 unsigned NumLanes = VT.getSizeInBits()/128;
3768 unsigned LaneSize = NumElts/NumLanes;
3769 for (unsigned l = 0; l != NumElts; l += LaneSize) {
3770 for (unsigned i = 0; i != LaneSize; ++i) {
3771 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
3773 if (NumElts != 8 || l == 0)
3775 // VPERMILPS handling
3778 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
3786 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
3787 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3788 /// element of vector 2 and the other elements to come from vector 1 in order.
3789 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
3790 bool V2IsSplat = false, bool V2IsUndef = false) {
3791 unsigned NumOps = VT.getVectorNumElements();
3792 if (VT.getSizeInBits() == 256)
3794 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3797 if (!isUndefOrEqual(Mask[0], 0))
3800 for (unsigned i = 1; i != NumOps; ++i)
3801 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3802 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3803 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3809 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3810 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3811 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3812 static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT,
3813 const X86Subtarget *Subtarget) {
3814 if (!Subtarget->hasSSE3())
3817 unsigned NumElems = VT.getVectorNumElements();
3819 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3820 (VT.getSizeInBits() == 256 && NumElems != 8))
3823 // "i+1" is the value the indexed mask element must have
3824 for (unsigned i = 0; i != NumElems; i += 2)
3825 if (!isUndefOrEqual(Mask[i], i+1) ||
3826 !isUndefOrEqual(Mask[i+1], i+1))
3832 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3833 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3834 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3835 static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT,
3836 const X86Subtarget *Subtarget) {
3837 if (!Subtarget->hasSSE3())
3840 unsigned NumElems = VT.getVectorNumElements();
3842 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3843 (VT.getSizeInBits() == 256 && NumElems != 8))
3846 // "i" is the value the indexed mask element must have
3847 for (unsigned i = 0; i != NumElems; i += 2)
3848 if (!isUndefOrEqual(Mask[i], i) ||
3849 !isUndefOrEqual(Mask[i+1], i))
3855 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3856 /// specifies a shuffle of elements that is suitable for input to 256-bit
3857 /// version of MOVDDUP.
3858 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3859 unsigned NumElts = VT.getVectorNumElements();
3861 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4)
3864 for (unsigned i = 0; i != NumElts/2; ++i)
3865 if (!isUndefOrEqual(Mask[i], 0))
3867 for (unsigned i = NumElts/2; i != NumElts; ++i)
3868 if (!isUndefOrEqual(Mask[i], NumElts/2))
3873 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3874 /// specifies a shuffle of elements that is suitable for input to 128-bit
3875 /// version of MOVDDUP.
3876 static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) {
3877 if (VT.getSizeInBits() != 128)
3880 unsigned e = VT.getVectorNumElements() / 2;
3881 for (unsigned i = 0; i != e; ++i)
3882 if (!isUndefOrEqual(Mask[i], i))
3884 for (unsigned i = 0; i != e; ++i)
3885 if (!isUndefOrEqual(Mask[e+i], i))
3890 /// isVEXTRACTF128Index - Return true if the specified
3891 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3892 /// suitable for input to VEXTRACTF128.
3893 bool X86::isVEXTRACTF128Index(SDNode *N) {
3894 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3897 // The index should be aligned on a 128-bit boundary.
3899 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3901 unsigned VL = N->getValueType(0).getVectorNumElements();
3902 unsigned VBits = N->getValueType(0).getSizeInBits();
3903 unsigned ElSize = VBits / VL;
3904 bool Result = (Index * ElSize) % 128 == 0;
3909 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3910 /// operand specifies a subvector insert that is suitable for input to
3912 bool X86::isVINSERTF128Index(SDNode *N) {
3913 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3916 // The index should be aligned on a 128-bit boundary.
3918 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3920 unsigned VL = N->getValueType(0).getVectorNumElements();
3921 unsigned VBits = N->getValueType(0).getSizeInBits();
3922 unsigned ElSize = VBits / VL;
3923 bool Result = (Index * ElSize) % 128 == 0;
3928 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3929 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3930 /// Handles 128-bit and 256-bit.
3931 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
3932 EVT VT = N->getValueType(0);
3934 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3935 "Unsupported vector type for PSHUF/SHUFP");
3937 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
3938 // independently on 128-bit lanes.
3939 unsigned NumElts = VT.getVectorNumElements();
3940 unsigned NumLanes = VT.getSizeInBits()/128;
3941 unsigned NumLaneElts = NumElts/NumLanes;
3943 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
3944 "Only supports 2 or 4 elements per lane");
3946 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
3948 for (unsigned i = 0; i != NumElts; ++i) {
3949 int Elt = N->getMaskElt(i);
3950 if (Elt < 0) continue;
3951 Elt &= NumLaneElts - 1;
3952 unsigned ShAmt = (i << Shift) % 8;
3953 Mask |= Elt << ShAmt;
3959 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3960 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3961 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
3962 EVT VT = N->getValueType(0);
3964 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
3965 "Unsupported vector type for PSHUFHW");
3967 unsigned NumElts = VT.getVectorNumElements();
3970 for (unsigned l = 0; l != NumElts; l += 8) {
3971 // 8 nodes per lane, but we only care about the last 4.
3972 for (unsigned i = 0; i < 4; ++i) {
3973 int Elt = N->getMaskElt(l+i+4);
3974 if (Elt < 0) continue;
3975 Elt &= 0x3; // only 2-bits.
3976 Mask |= Elt << (i * 2);
3983 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3984 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3985 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
3986 EVT VT = N->getValueType(0);
3988 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
3989 "Unsupported vector type for PSHUFHW");
3991 unsigned NumElts = VT.getVectorNumElements();
3994 for (unsigned l = 0; l != NumElts; l += 8) {
3995 // 8 nodes per lane, but we only care about the first 4.
3996 for (unsigned i = 0; i < 4; ++i) {
3997 int Elt = N->getMaskElt(l+i);
3998 if (Elt < 0) continue;
3999 Elt &= 0x3; // only 2-bits
4000 Mask |= Elt << (i * 2);
4007 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4008 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4009 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4010 EVT VT = SVOp->getValueType(0);
4011 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
4013 unsigned NumElts = VT.getVectorNumElements();
4014 unsigned NumLanes = VT.getSizeInBits()/128;
4015 unsigned NumLaneElts = NumElts/NumLanes;
4019 for (i = 0; i != NumElts; ++i) {
4020 Val = SVOp->getMaskElt(i);
4024 if (Val >= (int)NumElts)
4025 Val -= NumElts - NumLaneElts;
4027 assert(Val - i > 0 && "PALIGNR imm should be positive");
4028 return (Val - i) * EltSize;
4031 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
4032 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4034 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
4035 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4036 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
4039 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4041 EVT VecVT = N->getOperand(0).getValueType();
4042 EVT ElVT = VecVT.getVectorElementType();
4044 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4045 return Index / NumElemsPerChunk;
4048 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
4049 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4051 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
4052 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4053 llvm_unreachable("Illegal insert subvector for VINSERTF128");
4056 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4058 EVT VecVT = N->getValueType(0);
4059 EVT ElVT = VecVT.getVectorElementType();
4061 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4062 return Index / NumElemsPerChunk;
4065 /// getShuffleCLImmediate - Return the appropriate immediate to shuffle
4066 /// the specified VECTOR_SHUFFLE mask with VPERMQ and VPERMPD instructions.
4067 /// Handles 256-bit.
4068 static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) {
4069 EVT VT = N->getValueType(0);
4071 unsigned NumElts = VT.getVectorNumElements();
4073 assert((VT.is256BitVector() && NumElts == 4) &&
4074 "Unsupported vector type for VPERMQ/VPERMPD");
4077 for (unsigned i = 0; i != NumElts; ++i) {
4078 int Elt = N->getMaskElt(i);
4081 Mask |= Elt << (i*2);
4086 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4088 bool X86::isZeroNode(SDValue Elt) {
4089 return ((isa<ConstantSDNode>(Elt) &&
4090 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4091 (isa<ConstantFPSDNode>(Elt) &&
4092 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4095 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4096 /// their permute mask.
4097 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4098 SelectionDAG &DAG) {
4099 EVT VT = SVOp->getValueType(0);
4100 unsigned NumElems = VT.getVectorNumElements();
4101 SmallVector<int, 8> MaskVec;
4103 for (unsigned i = 0; i != NumElems; ++i) {
4104 int Idx = SVOp->getMaskElt(i);
4106 if (Idx < (int)NumElems)
4111 MaskVec.push_back(Idx);
4113 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4114 SVOp->getOperand(0), &MaskVec[0]);
4117 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4118 /// match movhlps. The lower half elements should come from upper half of
4119 /// V1 (and in order), and the upper half elements should come from the upper
4120 /// half of V2 (and in order).
4121 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) {
4122 if (VT.getSizeInBits() != 128)
4124 if (VT.getVectorNumElements() != 4)
4126 for (unsigned i = 0, e = 2; i != e; ++i)
4127 if (!isUndefOrEqual(Mask[i], i+2))
4129 for (unsigned i = 2; i != 4; ++i)
4130 if (!isUndefOrEqual(Mask[i], i+4))
4135 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4136 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4138 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4139 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4141 N = N->getOperand(0).getNode();
4142 if (!ISD::isNON_EXTLoad(N))
4145 *LD = cast<LoadSDNode>(N);
4149 // Test whether the given value is a vector value which will be legalized
4151 static bool WillBeConstantPoolLoad(SDNode *N) {
4152 if (N->getOpcode() != ISD::BUILD_VECTOR)
4155 // Check for any non-constant elements.
4156 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4157 switch (N->getOperand(i).getNode()->getOpcode()) {
4159 case ISD::ConstantFP:
4166 // Vectors of all-zeros and all-ones are materialized with special
4167 // instructions rather than being loaded.
4168 return !ISD::isBuildVectorAllZeros(N) &&
4169 !ISD::isBuildVectorAllOnes(N);
4172 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4173 /// match movlp{s|d}. The lower half elements should come from lower half of
4174 /// V1 (and in order), and the upper half elements should come from the upper
4175 /// half of V2 (and in order). And since V1 will become the source of the
4176 /// MOVLP, it must be either a vector load or a scalar load to vector.
4177 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4178 ArrayRef<int> Mask, EVT VT) {
4179 if (VT.getSizeInBits() != 128)
4182 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4184 // Is V2 is a vector load, don't do this transformation. We will try to use
4185 // load folding shufps op.
4186 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4189 unsigned NumElems = VT.getVectorNumElements();
4191 if (NumElems != 2 && NumElems != 4)
4193 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4194 if (!isUndefOrEqual(Mask[i], i))
4196 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4197 if (!isUndefOrEqual(Mask[i], i+NumElems))
4202 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4204 static bool isSplatVector(SDNode *N) {
4205 if (N->getOpcode() != ISD::BUILD_VECTOR)
4208 SDValue SplatValue = N->getOperand(0);
4209 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4210 if (N->getOperand(i) != SplatValue)
4215 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4216 /// to an zero vector.
4217 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4218 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4219 SDValue V1 = N->getOperand(0);
4220 SDValue V2 = N->getOperand(1);
4221 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4222 for (unsigned i = 0; i != NumElems; ++i) {
4223 int Idx = N->getMaskElt(i);
4224 if (Idx >= (int)NumElems) {
4225 unsigned Opc = V2.getOpcode();
4226 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4228 if (Opc != ISD::BUILD_VECTOR ||
4229 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4231 } else if (Idx >= 0) {
4232 unsigned Opc = V1.getOpcode();
4233 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4235 if (Opc != ISD::BUILD_VECTOR ||
4236 !X86::isZeroNode(V1.getOperand(Idx)))
4243 /// getZeroVector - Returns a vector of specified type with all zero elements.
4245 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4246 SelectionDAG &DAG, DebugLoc dl) {
4247 assert(VT.isVector() && "Expected a vector type");
4248 unsigned Size = VT.getSizeInBits();
4250 // Always build SSE zero vectors as <4 x i32> bitcasted
4251 // to their dest type. This ensures they get CSE'd.
4253 if (Size == 128) { // SSE
4254 if (Subtarget->hasSSE2()) { // SSE2
4255 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4256 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4258 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4259 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4261 } else if (Size == 256) { // AVX
4262 if (Subtarget->hasAVX2()) { // AVX2
4263 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4264 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4265 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4267 // 256-bit logic and arithmetic instructions in AVX are all
4268 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4269 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4270 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4271 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4274 llvm_unreachable("Unexpected vector type");
4276 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4279 /// getOnesVector - Returns a vector of specified type with all bits set.
4280 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4281 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4282 /// Then bitcast to their original type, ensuring they get CSE'd.
4283 static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG,
4285 assert(VT.isVector() && "Expected a vector type");
4286 unsigned Size = VT.getSizeInBits();
4288 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4291 if (HasAVX2) { // AVX2
4292 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4293 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4295 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4296 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4298 } else if (Size == 128) {
4299 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4301 llvm_unreachable("Unexpected vector type");
4303 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4306 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4307 /// that point to V2 points to its first element.
4308 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4309 for (unsigned i = 0; i != NumElems; ++i) {
4310 if (Mask[i] > (int)NumElems) {
4316 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4317 /// operation of specified width.
4318 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4320 unsigned NumElems = VT.getVectorNumElements();
4321 SmallVector<int, 8> Mask;
4322 Mask.push_back(NumElems);
4323 for (unsigned i = 1; i != NumElems; ++i)
4325 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4328 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4329 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4331 unsigned NumElems = VT.getVectorNumElements();
4332 SmallVector<int, 8> Mask;
4333 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4335 Mask.push_back(i + NumElems);
4337 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4340 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4341 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4343 unsigned NumElems = VT.getVectorNumElements();
4344 SmallVector<int, 8> Mask;
4345 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4346 Mask.push_back(i + Half);
4347 Mask.push_back(i + NumElems + Half);
4349 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4352 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4353 // a generic shuffle instruction because the target has no such instructions.
4354 // Generate shuffles which repeat i16 and i8 several times until they can be
4355 // represented by v4f32 and then be manipulated by target suported shuffles.
4356 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4357 EVT VT = V.getValueType();
4358 int NumElems = VT.getVectorNumElements();
4359 DebugLoc dl = V.getDebugLoc();
4361 while (NumElems > 4) {
4362 if (EltNo < NumElems/2) {
4363 V = getUnpackl(DAG, dl, VT, V, V);
4365 V = getUnpackh(DAG, dl, VT, V, V);
4366 EltNo -= NumElems/2;
4373 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4374 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4375 EVT VT = V.getValueType();
4376 DebugLoc dl = V.getDebugLoc();
4377 unsigned Size = VT.getSizeInBits();
4380 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4381 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4382 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4384 } else if (Size == 256) {
4385 // To use VPERMILPS to splat scalars, the second half of indicies must
4386 // refer to the higher part, which is a duplication of the lower one,
4387 // because VPERMILPS can only handle in-lane permutations.
4388 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4389 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4391 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4392 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4395 llvm_unreachable("Vector size not supported");
4397 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4400 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4401 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4402 EVT SrcVT = SV->getValueType(0);
4403 SDValue V1 = SV->getOperand(0);
4404 DebugLoc dl = SV->getDebugLoc();
4406 int EltNo = SV->getSplatIndex();
4407 int NumElems = SrcVT.getVectorNumElements();
4408 unsigned Size = SrcVT.getSizeInBits();
4410 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4411 "Unknown how to promote splat for type");
4413 // Extract the 128-bit part containing the splat element and update
4414 // the splat element index when it refers to the higher register.
4416 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4417 if (EltNo >= NumElems/2)
4418 EltNo -= NumElems/2;
4421 // All i16 and i8 vector types can't be used directly by a generic shuffle
4422 // instruction because the target has no such instruction. Generate shuffles
4423 // which repeat i16 and i8 several times until they fit in i32, and then can
4424 // be manipulated by target suported shuffles.
4425 EVT EltVT = SrcVT.getVectorElementType();
4426 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4427 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4429 // Recreate the 256-bit vector and place the same 128-bit vector
4430 // into the low and high part. This is necessary because we want
4431 // to use VPERM* to shuffle the vectors
4433 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4436 return getLegalSplat(DAG, V1, EltNo);
4439 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4440 /// vector of zero or undef vector. This produces a shuffle where the low
4441 /// element of V2 is swizzled into the zero/undef vector, landing at element
4442 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4443 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4445 const X86Subtarget *Subtarget,
4446 SelectionDAG &DAG) {
4447 EVT VT = V2.getValueType();
4449 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4450 unsigned NumElems = VT.getVectorNumElements();
4451 SmallVector<int, 16> MaskVec;
4452 for (unsigned i = 0; i != NumElems; ++i)
4453 // If this is the insertion idx, put the low elt of V2 here.
4454 MaskVec.push_back(i == Idx ? NumElems : i);
4455 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4458 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4459 /// target specific opcode. Returns true if the Mask could be calculated.
4460 /// Sets IsUnary to true if only uses one source.
4461 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4462 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4463 unsigned NumElems = VT.getVectorNumElements();
4467 switch(N->getOpcode()) {
4469 ImmN = N->getOperand(N->getNumOperands()-1);
4470 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4472 case X86ISD::UNPCKH:
4473 DecodeUNPCKHMask(VT, Mask);
4475 case X86ISD::UNPCKL:
4476 DecodeUNPCKLMask(VT, Mask);
4478 case X86ISD::MOVHLPS:
4479 DecodeMOVHLPSMask(NumElems, Mask);
4481 case X86ISD::MOVLHPS:
4482 DecodeMOVLHPSMask(NumElems, Mask);
4484 case X86ISD::PSHUFD:
4485 case X86ISD::VPERMILP:
4486 ImmN = N->getOperand(N->getNumOperands()-1);
4487 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4490 case X86ISD::PSHUFHW:
4491 ImmN = N->getOperand(N->getNumOperands()-1);
4492 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4495 case X86ISD::PSHUFLW:
4496 ImmN = N->getOperand(N->getNumOperands()-1);
4497 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4500 case X86ISD::VPERMI:
4501 ImmN = N->getOperand(N->getNumOperands()-1);
4502 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4506 case X86ISD::MOVSD: {
4507 // The index 0 always comes from the first element of the second source,
4508 // this is why MOVSS and MOVSD are used in the first place. The other
4509 // elements come from the other positions of the first source vector
4510 Mask.push_back(NumElems);
4511 for (unsigned i = 1; i != NumElems; ++i) {
4516 case X86ISD::VPERM2X128:
4517 ImmN = N->getOperand(N->getNumOperands()-1);
4518 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4519 if (Mask.empty()) return false;
4521 case X86ISD::MOVDDUP:
4522 case X86ISD::MOVLHPD:
4523 case X86ISD::MOVLPD:
4524 case X86ISD::MOVLPS:
4525 case X86ISD::MOVSHDUP:
4526 case X86ISD::MOVSLDUP:
4527 case X86ISD::PALIGN:
4528 // Not yet implemented
4530 default: llvm_unreachable("unknown target shuffle node");
4536 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4537 /// element of the result of the vector shuffle.
4538 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4541 return SDValue(); // Limit search depth.
4543 SDValue V = SDValue(N, 0);
4544 EVT VT = V.getValueType();
4545 unsigned Opcode = V.getOpcode();
4547 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4548 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4549 int Elt = SV->getMaskElt(Index);
4552 return DAG.getUNDEF(VT.getVectorElementType());
4554 unsigned NumElems = VT.getVectorNumElements();
4555 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4556 : SV->getOperand(1);
4557 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4560 // Recurse into target specific vector shuffles to find scalars.
4561 if (isTargetShuffle(Opcode)) {
4562 MVT ShufVT = V.getValueType().getSimpleVT();
4563 unsigned NumElems = ShufVT.getVectorNumElements();
4564 SmallVector<int, 16> ShuffleMask;
4568 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4571 int Elt = ShuffleMask[Index];
4573 return DAG.getUNDEF(ShufVT.getVectorElementType());
4575 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4577 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4581 // Actual nodes that may contain scalar elements
4582 if (Opcode == ISD::BITCAST) {
4583 V = V.getOperand(0);
4584 EVT SrcVT = V.getValueType();
4585 unsigned NumElems = VT.getVectorNumElements();
4587 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4591 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4592 return (Index == 0) ? V.getOperand(0)
4593 : DAG.getUNDEF(VT.getVectorElementType());
4595 if (V.getOpcode() == ISD::BUILD_VECTOR)
4596 return V.getOperand(Index);
4601 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4602 /// shuffle operation which come from a consecutively from a zero. The
4603 /// search can start in two different directions, from left or right.
4605 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems,
4606 bool ZerosFromLeft, SelectionDAG &DAG) {
4608 for (i = 0; i != NumElems; ++i) {
4609 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4610 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
4611 if (!(Elt.getNode() &&
4612 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4619 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
4620 /// correspond consecutively to elements from one of the vector operands,
4621 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4623 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
4624 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
4625 unsigned NumElems, unsigned &OpNum) {
4626 bool SeenV1 = false;
4627 bool SeenV2 = false;
4629 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
4630 int Idx = SVOp->getMaskElt(i);
4631 // Ignore undef indicies
4635 if (Idx < (int)NumElems)
4640 // Only accept consecutive elements from the same vector
4641 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4645 OpNum = SeenV1 ? 0 : 1;
4649 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4650 /// logical left shift of a vector.
4651 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4652 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4653 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4654 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4655 false /* check zeros from right */, DAG);
4661 // Considering the elements in the mask that are not consecutive zeros,
4662 // check if they consecutively come from only one of the source vectors.
4664 // V1 = {X, A, B, C} 0
4666 // vector_shuffle V1, V2 <1, 2, 3, X>
4668 if (!isShuffleMaskConsecutive(SVOp,
4669 0, // Mask Start Index
4670 NumElems-NumZeros, // Mask End Index(exclusive)
4671 NumZeros, // Where to start looking in the src vector
4672 NumElems, // Number of elements in vector
4673 OpSrc)) // Which source operand ?
4678 ShVal = SVOp->getOperand(OpSrc);
4682 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4683 /// logical left shift of a vector.
4684 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4685 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4686 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4687 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4688 true /* check zeros from left */, DAG);
4694 // Considering the elements in the mask that are not consecutive zeros,
4695 // check if they consecutively come from only one of the source vectors.
4697 // 0 { A, B, X, X } = V2
4699 // vector_shuffle V1, V2 <X, X, 4, 5>
4701 if (!isShuffleMaskConsecutive(SVOp,
4702 NumZeros, // Mask Start Index
4703 NumElems, // Mask End Index(exclusive)
4704 0, // Where to start looking in the src vector
4705 NumElems, // Number of elements in vector
4706 OpSrc)) // Which source operand ?
4711 ShVal = SVOp->getOperand(OpSrc);
4715 /// isVectorShift - Returns true if the shuffle can be implemented as a
4716 /// logical left or right shift of a vector.
4717 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4718 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4719 // Although the logic below support any bitwidth size, there are no
4720 // shift instructions which handle more than 128-bit vectors.
4721 if (SVOp->getValueType(0).getSizeInBits() > 128)
4724 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4725 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4731 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4733 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4734 unsigned NumNonZero, unsigned NumZero,
4736 const X86Subtarget* Subtarget,
4737 const TargetLowering &TLI) {
4741 DebugLoc dl = Op.getDebugLoc();
4744 for (unsigned i = 0; i < 16; ++i) {
4745 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4746 if (ThisIsNonZero && First) {
4748 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4750 V = DAG.getUNDEF(MVT::v8i16);
4755 SDValue ThisElt(0, 0), LastElt(0, 0);
4756 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4757 if (LastIsNonZero) {
4758 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4759 MVT::i16, Op.getOperand(i-1));
4761 if (ThisIsNonZero) {
4762 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4763 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4764 ThisElt, DAG.getConstant(8, MVT::i8));
4766 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4770 if (ThisElt.getNode())
4771 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4772 DAG.getIntPtrConstant(i/2));
4776 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4779 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4781 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4782 unsigned NumNonZero, unsigned NumZero,
4784 const X86Subtarget* Subtarget,
4785 const TargetLowering &TLI) {
4789 DebugLoc dl = Op.getDebugLoc();
4792 for (unsigned i = 0; i < 8; ++i) {
4793 bool isNonZero = (NonZeros & (1 << i)) != 0;
4797 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4799 V = DAG.getUNDEF(MVT::v8i16);
4802 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4803 MVT::v8i16, V, Op.getOperand(i),
4804 DAG.getIntPtrConstant(i));
4811 /// getVShift - Return a vector logical shift node.
4813 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4814 unsigned NumBits, SelectionDAG &DAG,
4815 const TargetLowering &TLI, DebugLoc dl) {
4816 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift");
4817 EVT ShVT = MVT::v2i64;
4818 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4819 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4820 return DAG.getNode(ISD::BITCAST, dl, VT,
4821 DAG.getNode(Opc, dl, ShVT, SrcOp,
4822 DAG.getConstant(NumBits,
4823 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4827 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4828 SelectionDAG &DAG) const {
4830 // Check if the scalar load can be widened into a vector load. And if
4831 // the address is "base + cst" see if the cst can be "absorbed" into
4832 // the shuffle mask.
4833 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4834 SDValue Ptr = LD->getBasePtr();
4835 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4837 EVT PVT = LD->getValueType(0);
4838 if (PVT != MVT::i32 && PVT != MVT::f32)
4843 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4844 FI = FINode->getIndex();
4846 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4847 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4848 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4849 Offset = Ptr.getConstantOperandVal(1);
4850 Ptr = Ptr.getOperand(0);
4855 // FIXME: 256-bit vector instructions don't require a strict alignment,
4856 // improve this code to support it better.
4857 unsigned RequiredAlign = VT.getSizeInBits()/8;
4858 SDValue Chain = LD->getChain();
4859 // Make sure the stack object alignment is at least 16 or 32.
4860 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4861 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4862 if (MFI->isFixedObjectIndex(FI)) {
4863 // Can't change the alignment. FIXME: It's possible to compute
4864 // the exact stack offset and reference FI + adjust offset instead.
4865 // If someone *really* cares about this. That's the way to implement it.
4868 MFI->setObjectAlignment(FI, RequiredAlign);
4872 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4873 // Ptr + (Offset & ~15).
4876 if ((Offset % RequiredAlign) & 3)
4878 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4880 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4881 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4883 int EltNo = (Offset - StartOffset) >> 2;
4884 unsigned NumElems = VT.getVectorNumElements();
4886 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4887 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4888 LD->getPointerInfo().getWithOffset(StartOffset),
4889 false, false, false, 0);
4891 SmallVector<int, 8> Mask;
4892 for (unsigned i = 0; i != NumElems; ++i)
4893 Mask.push_back(EltNo);
4895 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4901 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4902 /// vector of type 'VT', see if the elements can be replaced by a single large
4903 /// load which has the same value as a build_vector whose operands are 'elts'.
4905 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4907 /// FIXME: we'd also like to handle the case where the last elements are zero
4908 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4909 /// There's even a handy isZeroNode for that purpose.
4910 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4911 DebugLoc &DL, SelectionDAG &DAG) {
4912 EVT EltVT = VT.getVectorElementType();
4913 unsigned NumElems = Elts.size();
4915 LoadSDNode *LDBase = NULL;
4916 unsigned LastLoadedElt = -1U;
4918 // For each element in the initializer, see if we've found a load or an undef.
4919 // If we don't find an initial load element, or later load elements are
4920 // non-consecutive, bail out.
4921 for (unsigned i = 0; i < NumElems; ++i) {
4922 SDValue Elt = Elts[i];
4924 if (!Elt.getNode() ||
4925 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4928 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4930 LDBase = cast<LoadSDNode>(Elt.getNode());
4934 if (Elt.getOpcode() == ISD::UNDEF)
4937 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4938 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4943 // If we have found an entire vector of loads and undefs, then return a large
4944 // load of the entire vector width starting at the base pointer. If we found
4945 // consecutive loads for the low half, generate a vzext_load node.
4946 if (LastLoadedElt == NumElems - 1) {
4947 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4948 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4949 LDBase->getPointerInfo(),
4950 LDBase->isVolatile(), LDBase->isNonTemporal(),
4951 LDBase->isInvariant(), 0);
4952 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4953 LDBase->getPointerInfo(),
4954 LDBase->isVolatile(), LDBase->isNonTemporal(),
4955 LDBase->isInvariant(), LDBase->getAlignment());
4957 if (NumElems == 4 && LastLoadedElt == 1 &&
4958 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4959 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4960 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4962 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
4963 LDBase->getPointerInfo(),
4964 LDBase->getAlignment(),
4965 false/*isVolatile*/, true/*ReadMem*/,
4967 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4972 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
4973 /// to generate a splat value for the following cases:
4974 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
4975 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4976 /// a scalar load, or a constant.
4977 /// The VBROADCAST node is returned when a pattern is found,
4978 /// or SDValue() otherwise.
4980 X86TargetLowering::LowerVectorBroadcast(SDValue &Op, SelectionDAG &DAG) const {
4981 if (!Subtarget->hasAVX())
4984 EVT VT = Op.getValueType();
4985 DebugLoc dl = Op.getDebugLoc();
4987 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4988 "Unsupported vector type for broadcast.");
4993 switch (Op.getOpcode()) {
4995 // Unknown pattern found.
4998 case ISD::BUILD_VECTOR: {
4999 // The BUILD_VECTOR node must be a splat.
5000 if (!isSplatVector(Op.getNode()))
5003 Ld = Op.getOperand(0);
5004 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5005 Ld.getOpcode() == ISD::ConstantFP);
5007 // The suspected load node has several users. Make sure that all
5008 // of its users are from the BUILD_VECTOR node.
5009 // Constants may have multiple users.
5010 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5015 case ISD::VECTOR_SHUFFLE: {
5016 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5018 // Shuffles must have a splat mask where the first element is
5020 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5023 SDValue Sc = Op.getOperand(0);
5024 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5025 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5027 if (!Subtarget->hasAVX2())
5030 // Use the register form of the broadcast instruction available on AVX2.
5031 if (VT.is256BitVector())
5032 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5033 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5036 Ld = Sc.getOperand(0);
5037 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5038 Ld.getOpcode() == ISD::ConstantFP);
5040 // The scalar_to_vector node and the suspected
5041 // load node must have exactly one user.
5042 // Constants may have multiple users.
5043 if (!ConstSplatVal && (!Sc.hasOneUse() || !Ld.hasOneUse()))
5049 bool Is256 = VT.getSizeInBits() == 256;
5051 // Handle the broadcasting a single constant scalar from the constant pool
5052 // into a vector. On Sandybridge it is still better to load a constant vector
5053 // from the constant pool and not to broadcast it from a scalar.
5054 if (ConstSplatVal && Subtarget->hasAVX2()) {
5055 EVT CVT = Ld.getValueType();
5056 assert(!CVT.isVector() && "Must not broadcast a vector type");
5057 unsigned ScalarSize = CVT.getSizeInBits();
5059 if (ScalarSize == 32 || (Is256 && ScalarSize == 64)) {
5060 const Constant *C = 0;
5061 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5062 C = CI->getConstantIntValue();
5063 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5064 C = CF->getConstantFPValue();
5066 assert(C && "Invalid constant type");
5068 SDValue CP = DAG.getConstantPool(C, getPointerTy());
5069 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5070 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5071 MachinePointerInfo::getConstantPool(),
5072 false, false, false, Alignment);
5074 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5078 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5079 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5081 // Handle AVX2 in-register broadcasts.
5082 if (!IsLoad && Subtarget->hasAVX2() &&
5083 (ScalarSize == 32 || (Is256 && ScalarSize == 64)))
5084 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5086 // The scalar source must be a normal load.
5090 if (ScalarSize == 32 || (Is256 && ScalarSize == 64))
5091 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5093 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5094 // double since there is no vbroadcastsd xmm
5095 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) {
5096 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5097 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5100 // Unsupported broadcast.
5105 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5106 DebugLoc dl = Op.getDebugLoc();
5108 EVT VT = Op.getValueType();
5109 EVT ExtVT = VT.getVectorElementType();
5110 unsigned NumElems = Op.getNumOperands();
5112 // Vectors containing all zeros can be matched by pxor and xorps later
5113 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5114 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5115 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5116 if (VT == MVT::v4i32 || VT == MVT::v8i32)
5119 return getZeroVector(VT, Subtarget, DAG, dl);
5122 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5123 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5124 // vpcmpeqd on 256-bit vectors.
5125 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5126 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2()))
5129 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl);
5132 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
5133 if (Broadcast.getNode())
5136 unsigned EVTBits = ExtVT.getSizeInBits();
5138 unsigned NumZero = 0;
5139 unsigned NumNonZero = 0;
5140 unsigned NonZeros = 0;
5141 bool IsAllConstants = true;
5142 SmallSet<SDValue, 8> Values;
5143 for (unsigned i = 0; i < NumElems; ++i) {
5144 SDValue Elt = Op.getOperand(i);
5145 if (Elt.getOpcode() == ISD::UNDEF)
5148 if (Elt.getOpcode() != ISD::Constant &&
5149 Elt.getOpcode() != ISD::ConstantFP)
5150 IsAllConstants = false;
5151 if (X86::isZeroNode(Elt))
5154 NonZeros |= (1 << i);
5159 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5160 if (NumNonZero == 0)
5161 return DAG.getUNDEF(VT);
5163 // Special case for single non-zero, non-undef, element.
5164 if (NumNonZero == 1) {
5165 unsigned Idx = CountTrailingZeros_32(NonZeros);
5166 SDValue Item = Op.getOperand(Idx);
5168 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5169 // the value are obviously zero, truncate the value to i32 and do the
5170 // insertion that way. Only do this if the value is non-constant or if the
5171 // value is a constant being inserted into element 0. It is cheaper to do
5172 // a constant pool load than it is to do a movd + shuffle.
5173 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5174 (!IsAllConstants || Idx == 0)) {
5175 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5177 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5178 EVT VecVT = MVT::v4i32;
5179 unsigned VecElts = 4;
5181 // Truncate the value (which may itself be a constant) to i32, and
5182 // convert it to a vector with movd (S2V+shuffle to zero extend).
5183 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5184 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5185 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5187 // Now we have our 32-bit value zero extended in the low element of
5188 // a vector. If Idx != 0, swizzle it into place.
5190 SmallVector<int, 4> Mask;
5191 Mask.push_back(Idx);
5192 for (unsigned i = 1; i != VecElts; ++i)
5194 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5197 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5201 // If we have a constant or non-constant insertion into the low element of
5202 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5203 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5204 // depending on what the source datatype is.
5207 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5209 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5210 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5211 if (VT.getSizeInBits() == 256) {
5212 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5213 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5214 Item, DAG.getIntPtrConstant(0));
5216 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5217 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5218 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5219 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5222 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5223 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5224 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5225 if (VT.getSizeInBits() == 256) {
5226 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5227 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5229 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5230 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5232 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5236 // Is it a vector logical left shift?
5237 if (NumElems == 2 && Idx == 1 &&
5238 X86::isZeroNode(Op.getOperand(0)) &&
5239 !X86::isZeroNode(Op.getOperand(1))) {
5240 unsigned NumBits = VT.getSizeInBits();
5241 return getVShift(true, VT,
5242 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5243 VT, Op.getOperand(1)),
5244 NumBits/2, DAG, *this, dl);
5247 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5250 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5251 // is a non-constant being inserted into an element other than the low one,
5252 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5253 // movd/movss) to move this into the low element, then shuffle it into
5255 if (EVTBits == 32) {
5256 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5258 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5259 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5260 SmallVector<int, 8> MaskVec;
5261 for (unsigned i = 0; i != NumElems; ++i)
5262 MaskVec.push_back(i == Idx ? 0 : 1);
5263 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5267 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5268 if (Values.size() == 1) {
5269 if (EVTBits == 32) {
5270 // Instead of a shuffle like this:
5271 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5272 // Check if it's possible to issue this instead.
5273 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5274 unsigned Idx = CountTrailingZeros_32(NonZeros);
5275 SDValue Item = Op.getOperand(Idx);
5276 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5277 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5282 // A vector full of immediates; various special cases are already
5283 // handled, so this is best done with a single constant-pool load.
5287 // For AVX-length vectors, build the individual 128-bit pieces and use
5288 // shuffles to put them in place.
5289 if (VT.getSizeInBits() == 256) {
5290 SmallVector<SDValue, 32> V;
5291 for (unsigned i = 0; i != NumElems; ++i)
5292 V.push_back(Op.getOperand(i));
5294 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5296 // Build both the lower and upper subvector.
5297 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5298 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5301 // Recreate the wider vector with the lower and upper part.
5302 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5305 // Let legalizer expand 2-wide build_vectors.
5306 if (EVTBits == 64) {
5307 if (NumNonZero == 1) {
5308 // One half is zero or undef.
5309 unsigned Idx = CountTrailingZeros_32(NonZeros);
5310 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5311 Op.getOperand(Idx));
5312 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5317 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5318 if (EVTBits == 8 && NumElems == 16) {
5319 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5321 if (V.getNode()) return V;
5324 if (EVTBits == 16 && NumElems == 8) {
5325 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5327 if (V.getNode()) return V;
5330 // If element VT is == 32 bits, turn it into a number of shuffles.
5331 SmallVector<SDValue, 8> V(NumElems);
5332 if (NumElems == 4 && NumZero > 0) {
5333 for (unsigned i = 0; i < 4; ++i) {
5334 bool isZero = !(NonZeros & (1 << i));
5336 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5338 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5341 for (unsigned i = 0; i < 2; ++i) {
5342 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5345 V[i] = V[i*2]; // Must be a zero vector.
5348 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5351 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5354 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5359 bool Reverse1 = (NonZeros & 0x3) == 2;
5360 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5364 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5365 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5367 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5370 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5371 // Check for a build vector of consecutive loads.
5372 for (unsigned i = 0; i < NumElems; ++i)
5373 V[i] = Op.getOperand(i);
5375 // Check for elements which are consecutive loads.
5376 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5380 // For SSE 4.1, use insertps to put the high elements into the low element.
5381 if (getSubtarget()->hasSSE41()) {
5383 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5384 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5386 Result = DAG.getUNDEF(VT);
5388 for (unsigned i = 1; i < NumElems; ++i) {
5389 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5390 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5391 Op.getOperand(i), DAG.getIntPtrConstant(i));
5396 // Otherwise, expand into a number of unpckl*, start by extending each of
5397 // our (non-undef) elements to the full vector width with the element in the
5398 // bottom slot of the vector (which generates no code for SSE).
5399 for (unsigned i = 0; i < NumElems; ++i) {
5400 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5401 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5403 V[i] = DAG.getUNDEF(VT);
5406 // Next, we iteratively mix elements, e.g. for v4f32:
5407 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5408 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5409 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5410 unsigned EltStride = NumElems >> 1;
5411 while (EltStride != 0) {
5412 for (unsigned i = 0; i < EltStride; ++i) {
5413 // If V[i+EltStride] is undef and this is the first round of mixing,
5414 // then it is safe to just drop this shuffle: V[i] is already in the
5415 // right place, the one element (since it's the first round) being
5416 // inserted as undef can be dropped. This isn't safe for successive
5417 // rounds because they will permute elements within both vectors.
5418 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5419 EltStride == NumElems/2)
5422 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5431 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5432 // them in a MMX register. This is better than doing a stack convert.
5433 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5434 DebugLoc dl = Op.getDebugLoc();
5435 EVT ResVT = Op.getValueType();
5437 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5438 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5440 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5441 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5442 InVec = Op.getOperand(1);
5443 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5444 unsigned NumElts = ResVT.getVectorNumElements();
5445 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5446 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5447 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5449 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5450 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5451 Mask[0] = 0; Mask[1] = 2;
5452 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5454 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5457 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5458 // to create 256-bit vectors from two other 128-bit ones.
5459 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5460 DebugLoc dl = Op.getDebugLoc();
5461 EVT ResVT = Op.getValueType();
5463 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5465 SDValue V1 = Op.getOperand(0);
5466 SDValue V2 = Op.getOperand(1);
5467 unsigned NumElems = ResVT.getVectorNumElements();
5469 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
5473 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5474 EVT ResVT = Op.getValueType();
5476 assert(Op.getNumOperands() == 2);
5477 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5478 "Unsupported CONCAT_VECTORS for value type");
5480 // We support concatenate two MMX registers and place them in a MMX register.
5481 // This is better than doing a stack convert.
5482 if (ResVT.is128BitVector())
5483 return LowerMMXCONCAT_VECTORS(Op, DAG);
5485 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5486 // from two other 128-bit ones.
5487 return LowerAVXCONCAT_VECTORS(Op, DAG);
5490 // Try to lower a shuffle node into a simple blend instruction.
5491 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
5492 const X86Subtarget *Subtarget,
5493 SelectionDAG &DAG) {
5494 SDValue V1 = SVOp->getOperand(0);
5495 SDValue V2 = SVOp->getOperand(1);
5496 DebugLoc dl = SVOp->getDebugLoc();
5497 MVT VT = SVOp->getValueType(0).getSimpleVT();
5498 unsigned NumElems = VT.getVectorNumElements();
5500 if (!Subtarget->hasSSE41())
5506 switch (VT.SimpleTy) {
5507 default: return SDValue();
5509 ISDNo = X86ISD::BLENDPW;
5514 ISDNo = X86ISD::BLENDPS;
5519 ISDNo = X86ISD::BLENDPD;
5524 if (!Subtarget->hasAVX())
5526 ISDNo = X86ISD::BLENDPS;
5531 if (!Subtarget->hasAVX())
5533 ISDNo = X86ISD::BLENDPD;
5537 assert(ISDNo && "Invalid Op Number");
5539 unsigned MaskVals = 0;
5541 for (unsigned i = 0; i != NumElems; ++i) {
5542 int EltIdx = SVOp->getMaskElt(i);
5543 if (EltIdx == (int)i || EltIdx < 0)
5545 else if (EltIdx == (int)(i + NumElems))
5546 continue; // Bit is set to zero;
5551 V1 = DAG.getNode(ISD::BITCAST, dl, OpTy, V1);
5552 V2 = DAG.getNode(ISD::BITCAST, dl, OpTy, V2);
5553 SDValue Ret = DAG.getNode(ISDNo, dl, OpTy, V1, V2,
5554 DAG.getConstant(MaskVals, MVT::i32));
5555 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
5558 // v8i16 shuffles - Prefer shuffles in the following order:
5559 // 1. [all] pshuflw, pshufhw, optional move
5560 // 2. [ssse3] 1 x pshufb
5561 // 3. [ssse3] 2 x pshufb + 1 x por
5562 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5564 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5565 SelectionDAG &DAG) const {
5566 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5567 SDValue V1 = SVOp->getOperand(0);
5568 SDValue V2 = SVOp->getOperand(1);
5569 DebugLoc dl = SVOp->getDebugLoc();
5570 SmallVector<int, 8> MaskVals;
5572 // Determine if more than 1 of the words in each of the low and high quadwords
5573 // of the result come from the same quadword of one of the two inputs. Undef
5574 // mask values count as coming from any quadword, for better codegen.
5575 unsigned LoQuad[] = { 0, 0, 0, 0 };
5576 unsigned HiQuad[] = { 0, 0, 0, 0 };
5577 std::bitset<4> InputQuads;
5578 for (unsigned i = 0; i < 8; ++i) {
5579 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5580 int EltIdx = SVOp->getMaskElt(i);
5581 MaskVals.push_back(EltIdx);
5590 InputQuads.set(EltIdx / 4);
5593 int BestLoQuad = -1;
5594 unsigned MaxQuad = 1;
5595 for (unsigned i = 0; i < 4; ++i) {
5596 if (LoQuad[i] > MaxQuad) {
5598 MaxQuad = LoQuad[i];
5602 int BestHiQuad = -1;
5604 for (unsigned i = 0; i < 4; ++i) {
5605 if (HiQuad[i] > MaxQuad) {
5607 MaxQuad = HiQuad[i];
5611 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5612 // of the two input vectors, shuffle them into one input vector so only a
5613 // single pshufb instruction is necessary. If There are more than 2 input
5614 // quads, disable the next transformation since it does not help SSSE3.
5615 bool V1Used = InputQuads[0] || InputQuads[1];
5616 bool V2Used = InputQuads[2] || InputQuads[3];
5617 if (Subtarget->hasSSSE3()) {
5618 if (InputQuads.count() == 2 && V1Used && V2Used) {
5619 BestLoQuad = InputQuads[0] ? 0 : 1;
5620 BestHiQuad = InputQuads[2] ? 2 : 3;
5622 if (InputQuads.count() > 2) {
5628 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5629 // the shuffle mask. If a quad is scored as -1, that means that it contains
5630 // words from all 4 input quadwords.
5632 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5634 BestLoQuad < 0 ? 0 : BestLoQuad,
5635 BestHiQuad < 0 ? 1 : BestHiQuad
5637 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5638 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5639 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5640 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5642 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5643 // source words for the shuffle, to aid later transformations.
5644 bool AllWordsInNewV = true;
5645 bool InOrder[2] = { true, true };
5646 for (unsigned i = 0; i != 8; ++i) {
5647 int idx = MaskVals[i];
5649 InOrder[i/4] = false;
5650 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5652 AllWordsInNewV = false;
5656 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5657 if (AllWordsInNewV) {
5658 for (int i = 0; i != 8; ++i) {
5659 int idx = MaskVals[i];
5662 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5663 if ((idx != i) && idx < 4)
5665 if ((idx != i) && idx > 3)
5674 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5675 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5676 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5677 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5678 unsigned TargetMask = 0;
5679 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5680 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5681 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5682 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
5683 getShufflePSHUFLWImmediate(SVOp);
5684 V1 = NewV.getOperand(0);
5685 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5689 // If we have SSSE3, and all words of the result are from 1 input vector,
5690 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5691 // is present, fall back to case 4.
5692 if (Subtarget->hasSSSE3()) {
5693 SmallVector<SDValue,16> pshufbMask;
5695 // If we have elements from both input vectors, set the high bit of the
5696 // shuffle mask element to zero out elements that come from V2 in the V1
5697 // mask, and elements that come from V1 in the V2 mask, so that the two
5698 // results can be OR'd together.
5699 bool TwoInputs = V1Used && V2Used;
5700 for (unsigned i = 0; i != 8; ++i) {
5701 int EltIdx = MaskVals[i] * 2;
5702 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
5703 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
5704 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
5705 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
5707 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5708 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5709 DAG.getNode(ISD::BUILD_VECTOR, dl,
5710 MVT::v16i8, &pshufbMask[0], 16));
5712 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5714 // Calculate the shuffle mask for the second input, shuffle it, and
5715 // OR it with the first shuffled input.
5717 for (unsigned i = 0; i != 8; ++i) {
5718 int EltIdx = MaskVals[i] * 2;
5719 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
5720 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
5721 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
5722 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
5724 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5725 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5726 DAG.getNode(ISD::BUILD_VECTOR, dl,
5727 MVT::v16i8, &pshufbMask[0], 16));
5728 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5729 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5732 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5733 // and update MaskVals with new element order.
5734 std::bitset<8> InOrder;
5735 if (BestLoQuad >= 0) {
5736 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
5737 for (int i = 0; i != 4; ++i) {
5738 int idx = MaskVals[i];
5741 } else if ((idx / 4) == BestLoQuad) {
5746 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5749 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5750 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5751 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5753 getShufflePSHUFLWImmediate(SVOp), DAG);
5757 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5758 // and update MaskVals with the new element order.
5759 if (BestHiQuad >= 0) {
5760 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
5761 for (unsigned i = 4; i != 8; ++i) {
5762 int idx = MaskVals[i];
5765 } else if ((idx / 4) == BestHiQuad) {
5766 MaskV[i] = (idx & 3) + 4;
5770 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5773 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5774 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5775 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5777 getShufflePSHUFHWImmediate(SVOp), DAG);
5781 // In case BestHi & BestLo were both -1, which means each quadword has a word
5782 // from each of the four input quadwords, calculate the InOrder bitvector now
5783 // before falling through to the insert/extract cleanup.
5784 if (BestLoQuad == -1 && BestHiQuad == -1) {
5786 for (int i = 0; i != 8; ++i)
5787 if (MaskVals[i] < 0 || MaskVals[i] == i)
5791 // The other elements are put in the right place using pextrw and pinsrw.
5792 for (unsigned i = 0; i != 8; ++i) {
5795 int EltIdx = MaskVals[i];
5798 SDValue ExtOp = (EltIdx < 8) ?
5799 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5800 DAG.getIntPtrConstant(EltIdx)) :
5801 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5802 DAG.getIntPtrConstant(EltIdx - 8));
5803 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5804 DAG.getIntPtrConstant(i));
5809 // v16i8 shuffles - Prefer shuffles in the following order:
5810 // 1. [ssse3] 1 x pshufb
5811 // 2. [ssse3] 2 x pshufb + 1 x por
5812 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5814 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5816 const X86TargetLowering &TLI) {
5817 SDValue V1 = SVOp->getOperand(0);
5818 SDValue V2 = SVOp->getOperand(1);
5819 DebugLoc dl = SVOp->getDebugLoc();
5820 ArrayRef<int> MaskVals = SVOp->getMask();
5822 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
5824 // If we have SSSE3, case 1 is generated when all result bytes come from
5825 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5826 // present, fall back to case 3.
5828 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5829 if (TLI.getSubtarget()->hasSSSE3()) {
5830 SmallVector<SDValue,16> pshufbMask;
5832 // If all result elements are from one input vector, then only translate
5833 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5835 // Otherwise, we have elements from both input vectors, and must zero out
5836 // elements that come from V2 in the first mask, and V1 in the second mask
5837 // so that we can OR them together.
5838 for (unsigned i = 0; i != 16; ++i) {
5839 int EltIdx = MaskVals[i];
5840 if (EltIdx < 0 || EltIdx >= 16)
5842 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5844 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5845 DAG.getNode(ISD::BUILD_VECTOR, dl,
5846 MVT::v16i8, &pshufbMask[0], 16));
5850 // Calculate the shuffle mask for the second input, shuffle it, and
5851 // OR it with the first shuffled input.
5853 for (unsigned i = 0; i != 16; ++i) {
5854 int EltIdx = MaskVals[i];
5855 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
5856 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5858 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5859 DAG.getNode(ISD::BUILD_VECTOR, dl,
5860 MVT::v16i8, &pshufbMask[0], 16));
5861 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5864 // No SSSE3 - Calculate in place words and then fix all out of place words
5865 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5866 // the 16 different words that comprise the two doublequadword input vectors.
5867 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5868 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5870 for (int i = 0; i != 8; ++i) {
5871 int Elt0 = MaskVals[i*2];
5872 int Elt1 = MaskVals[i*2+1];
5874 // This word of the result is all undef, skip it.
5875 if (Elt0 < 0 && Elt1 < 0)
5878 // This word of the result is already in the correct place, skip it.
5879 if ((Elt0 == i*2) && (Elt1 == i*2+1))
5882 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5883 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5886 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5887 // using a single extract together, load it and store it.
5888 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5889 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5890 DAG.getIntPtrConstant(Elt1 / 2));
5891 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5892 DAG.getIntPtrConstant(i));
5896 // If Elt1 is defined, extract it from the appropriate source. If the
5897 // source byte is not also odd, shift the extracted word left 8 bits
5898 // otherwise clear the bottom 8 bits if we need to do an or.
5900 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5901 DAG.getIntPtrConstant(Elt1 / 2));
5902 if ((Elt1 & 1) == 0)
5903 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5905 TLI.getShiftAmountTy(InsElt.getValueType())));
5907 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5908 DAG.getConstant(0xFF00, MVT::i16));
5910 // If Elt0 is defined, extract it from the appropriate source. If the
5911 // source byte is not also even, shift the extracted word right 8 bits. If
5912 // Elt1 was also defined, OR the extracted values together before
5913 // inserting them in the result.
5915 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5916 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5917 if ((Elt0 & 1) != 0)
5918 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5920 TLI.getShiftAmountTy(InsElt0.getValueType())));
5922 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5923 DAG.getConstant(0x00FF, MVT::i16));
5924 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5927 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5928 DAG.getIntPtrConstant(i));
5930 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5933 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5934 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5935 /// done when every pair / quad of shuffle mask elements point to elements in
5936 /// the right sequence. e.g.
5937 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5939 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5940 SelectionDAG &DAG, DebugLoc dl) {
5941 MVT VT = SVOp->getValueType(0).getSimpleVT();
5942 unsigned NumElems = VT.getVectorNumElements();
5945 switch (VT.SimpleTy) {
5946 default: llvm_unreachable("Unexpected!");
5947 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
5948 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
5949 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
5950 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
5951 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
5952 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
5955 SmallVector<int, 8> MaskVec;
5956 for (unsigned i = 0; i != NumElems; i += Scale) {
5958 for (unsigned j = 0; j != Scale; ++j) {
5959 int EltIdx = SVOp->getMaskElt(i+j);
5963 StartIdx = (EltIdx / Scale);
5964 if (EltIdx != (int)(StartIdx*Scale + j))
5967 MaskVec.push_back(StartIdx);
5970 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
5971 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
5972 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5975 /// getVZextMovL - Return a zero-extending vector move low node.
5977 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5978 SDValue SrcOp, SelectionDAG &DAG,
5979 const X86Subtarget *Subtarget, DebugLoc dl) {
5980 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5981 LoadSDNode *LD = NULL;
5982 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5983 LD = dyn_cast<LoadSDNode>(SrcOp);
5985 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5987 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5988 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5989 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5990 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5991 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5993 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5994 return DAG.getNode(ISD::BITCAST, dl, VT,
5995 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5996 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6004 return DAG.getNode(ISD::BITCAST, dl, VT,
6005 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6006 DAG.getNode(ISD::BITCAST, dl,
6010 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
6011 /// which could not be matched by any known target speficic shuffle
6013 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6015 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
6016 if (NewOp.getNode())
6019 EVT VT = SVOp->getValueType(0);
6021 unsigned NumElems = VT.getVectorNumElements();
6022 unsigned NumLaneElems = NumElems / 2;
6024 DebugLoc dl = SVOp->getDebugLoc();
6025 MVT EltVT = VT.getVectorElementType().getSimpleVT();
6026 EVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6029 SmallVector<int, 16> Mask;
6030 for (unsigned l = 0; l < 2; ++l) {
6031 // Build a shuffle mask for the output, discovering on the fly which
6032 // input vectors to use as shuffle operands (recorded in InputUsed).
6033 // If building a suitable shuffle vector proves too hard, then bail
6034 // out with UseBuildVector set.
6035 bool UseBuildVector = false;
6036 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6037 unsigned LaneStart = l * NumLaneElems;
6038 for (unsigned i = 0; i != NumLaneElems; ++i) {
6039 // The mask element. This indexes into the input.
6040 int Idx = SVOp->getMaskElt(i+LaneStart);
6042 // the mask element does not index into any input vector.
6047 // The input vector this mask element indexes into.
6048 int Input = Idx / NumLaneElems;
6050 // Turn the index into an offset from the start of the input vector.
6051 Idx -= Input * NumLaneElems;
6053 // Find or create a shuffle vector operand to hold this input.
6055 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6056 if (InputUsed[OpNo] == Input)
6057 // This input vector is already an operand.
6059 if (InputUsed[OpNo] < 0) {
6060 // Create a new operand for this input vector.
6061 InputUsed[OpNo] = Input;
6066 if (OpNo >= array_lengthof(InputUsed)) {
6067 // More than two input vectors used! Give up on trying to create a
6068 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6069 UseBuildVector = true;
6073 // Add the mask index for the new shuffle vector.
6074 Mask.push_back(Idx + OpNo * NumLaneElems);
6077 if (UseBuildVector) {
6078 SmallVector<SDValue, 16> SVOps;
6079 for (unsigned i = 0; i != NumLaneElems; ++i) {
6080 // The mask element. This indexes into the input.
6081 int Idx = SVOp->getMaskElt(i+LaneStart);
6083 SVOps.push_back(DAG.getUNDEF(EltVT));
6087 // The input vector this mask element indexes into.
6088 int Input = Idx / NumElems;
6090 // Turn the index into an offset from the start of the input vector.
6091 Idx -= Input * NumElems;
6093 // Extract the vector element by hand.
6094 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6095 SVOp->getOperand(Input),
6096 DAG.getIntPtrConstant(Idx)));
6099 // Construct the output using a BUILD_VECTOR.
6100 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6102 } else if (InputUsed[0] < 0) {
6103 // No input vectors were used! The result is undefined.
6104 Output[l] = DAG.getUNDEF(NVT);
6106 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6107 (InputUsed[0] % 2) * NumLaneElems,
6109 // If only one input was used, use an undefined vector for the other.
6110 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6111 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6112 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6113 // At least one input vector was used. Create a new shuffle vector.
6114 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6120 // Concatenate the result back
6121 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6124 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6125 /// 4 elements, and match them with several different shuffle types.
6127 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6128 SDValue V1 = SVOp->getOperand(0);
6129 SDValue V2 = SVOp->getOperand(1);
6130 DebugLoc dl = SVOp->getDebugLoc();
6131 EVT VT = SVOp->getValueType(0);
6133 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
6135 std::pair<int, int> Locs[4];
6136 int Mask1[] = { -1, -1, -1, -1 };
6137 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6141 for (unsigned i = 0; i != 4; ++i) {
6142 int Idx = PermMask[i];
6144 Locs[i] = std::make_pair(-1, -1);
6146 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6148 Locs[i] = std::make_pair(0, NumLo);
6152 Locs[i] = std::make_pair(1, NumHi);
6154 Mask1[2+NumHi] = Idx;
6160 if (NumLo <= 2 && NumHi <= 2) {
6161 // If no more than two elements come from either vector. This can be
6162 // implemented with two shuffles. First shuffle gather the elements.
6163 // The second shuffle, which takes the first shuffle as both of its
6164 // vector operands, put the elements into the right order.
6165 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6167 int Mask2[] = { -1, -1, -1, -1 };
6169 for (unsigned i = 0; i != 4; ++i)
6170 if (Locs[i].first != -1) {
6171 unsigned Idx = (i < 2) ? 0 : 4;
6172 Idx += Locs[i].first * 2 + Locs[i].second;
6176 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6179 if (NumLo == 3 || NumHi == 3) {
6180 // Otherwise, we must have three elements from one vector, call it X, and
6181 // one element from the other, call it Y. First, use a shufps to build an
6182 // intermediate vector with the one element from Y and the element from X
6183 // that will be in the same half in the final destination (the indexes don't
6184 // matter). Then, use a shufps to build the final vector, taking the half
6185 // containing the element from Y from the intermediate, and the other half
6188 // Normalize it so the 3 elements come from V1.
6189 CommuteVectorShuffleMask(PermMask, 4);
6193 // Find the element from V2.
6195 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6196 int Val = PermMask[HiIndex];
6203 Mask1[0] = PermMask[HiIndex];
6205 Mask1[2] = PermMask[HiIndex^1];
6207 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6210 Mask1[0] = PermMask[0];
6211 Mask1[1] = PermMask[1];
6212 Mask1[2] = HiIndex & 1 ? 6 : 4;
6213 Mask1[3] = HiIndex & 1 ? 4 : 6;
6214 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6217 Mask1[0] = HiIndex & 1 ? 2 : 0;
6218 Mask1[1] = HiIndex & 1 ? 0 : 2;
6219 Mask1[2] = PermMask[2];
6220 Mask1[3] = PermMask[3];
6225 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6228 // Break it into (shuffle shuffle_hi, shuffle_lo).
6229 int LoMask[] = { -1, -1, -1, -1 };
6230 int HiMask[] = { -1, -1, -1, -1 };
6232 int *MaskPtr = LoMask;
6233 unsigned MaskIdx = 0;
6236 for (unsigned i = 0; i != 4; ++i) {
6243 int Idx = PermMask[i];
6245 Locs[i] = std::make_pair(-1, -1);
6246 } else if (Idx < 4) {
6247 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6248 MaskPtr[LoIdx] = Idx;
6251 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6252 MaskPtr[HiIdx] = Idx;
6257 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6258 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6259 int MaskOps[] = { -1, -1, -1, -1 };
6260 for (unsigned i = 0; i != 4; ++i)
6261 if (Locs[i].first != -1)
6262 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6263 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6266 static bool MayFoldVectorLoad(SDValue V) {
6267 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6268 V = V.getOperand(0);
6269 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6270 V = V.getOperand(0);
6271 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6272 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6273 // BUILD_VECTOR (load), undef
6274 V = V.getOperand(0);
6280 // FIXME: the version above should always be used. Since there's
6281 // a bug where several vector shuffles can't be folded because the
6282 // DAG is not updated during lowering and a node claims to have two
6283 // uses while it only has one, use this version, and let isel match
6284 // another instruction if the load really happens to have more than
6285 // one use. Remove this version after this bug get fixed.
6286 // rdar://8434668, PR8156
6287 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6288 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6289 V = V.getOperand(0);
6290 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6291 V = V.getOperand(0);
6292 if (ISD::isNormalLoad(V.getNode()))
6298 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6299 EVT VT = Op.getValueType();
6301 // Canonizalize to v2f64.
6302 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6303 return DAG.getNode(ISD::BITCAST, dl, VT,
6304 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6309 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6311 SDValue V1 = Op.getOperand(0);
6312 SDValue V2 = Op.getOperand(1);
6313 EVT VT = Op.getValueType();
6315 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6317 if (HasSSE2 && VT == MVT::v2f64)
6318 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6320 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6321 return DAG.getNode(ISD::BITCAST, dl, VT,
6322 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6323 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6324 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6328 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6329 SDValue V1 = Op.getOperand(0);
6330 SDValue V2 = Op.getOperand(1);
6331 EVT VT = Op.getValueType();
6333 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6334 "unsupported shuffle type");
6336 if (V2.getOpcode() == ISD::UNDEF)
6340 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6344 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6345 SDValue V1 = Op.getOperand(0);
6346 SDValue V2 = Op.getOperand(1);
6347 EVT VT = Op.getValueType();
6348 unsigned NumElems = VT.getVectorNumElements();
6350 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6351 // operand of these instructions is only memory, so check if there's a
6352 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6354 bool CanFoldLoad = false;
6356 // Trivial case, when V2 comes from a load.
6357 if (MayFoldVectorLoad(V2))
6360 // When V1 is a load, it can be folded later into a store in isel, example:
6361 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6363 // (MOVLPSmr addr:$src1, VR128:$src2)
6364 // So, recognize this potential and also use MOVLPS or MOVLPD
6365 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6368 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6370 if (HasSSE2 && NumElems == 2)
6371 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6374 // If we don't care about the second element, proceed to use movss.
6375 if (SVOp->getMaskElt(1) != -1)
6376 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6379 // movl and movlp will both match v2i64, but v2i64 is never matched by
6380 // movl earlier because we make it strict to avoid messing with the movlp load
6381 // folding logic (see the code above getMOVLP call). Match it here then,
6382 // this is horrible, but will stay like this until we move all shuffle
6383 // matching to x86 specific nodes. Note that for the 1st condition all
6384 // types are matched with movsd.
6386 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6387 // as to remove this logic from here, as much as possible
6388 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
6389 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6390 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6393 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6395 // Invert the operand order and use SHUFPS to match it.
6396 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6397 getShuffleSHUFImmediate(SVOp), DAG);
6401 X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const {
6402 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6403 EVT VT = Op.getValueType();
6404 DebugLoc dl = Op.getDebugLoc();
6405 SDValue V1 = Op.getOperand(0);
6406 SDValue V2 = Op.getOperand(1);
6408 if (isZeroShuffle(SVOp))
6409 return getZeroVector(VT, Subtarget, DAG, dl);
6411 // Handle splat operations
6412 if (SVOp->isSplat()) {
6413 unsigned NumElem = VT.getVectorNumElements();
6414 int Size = VT.getSizeInBits();
6416 // Use vbroadcast whenever the splat comes from a foldable load
6417 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
6418 if (Broadcast.getNode())
6421 // Handle splats by matching through known shuffle masks
6422 if ((Size == 128 && NumElem <= 4) ||
6423 (Size == 256 && NumElem < 8))
6426 // All remaning splats are promoted to target supported vector shuffles.
6427 return PromoteSplat(SVOp, DAG);
6430 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6432 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
6433 VT == MVT::v16i16 || VT == MVT::v32i8) {
6434 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6435 if (NewOp.getNode())
6436 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6437 } else if ((VT == MVT::v4i32 ||
6438 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6439 // FIXME: Figure out a cleaner way to do this.
6440 // Try to make use of movq to zero out the top part.
6441 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6442 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6443 if (NewOp.getNode()) {
6444 EVT NewVT = NewOp.getValueType();
6445 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
6446 NewVT, true, false))
6447 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
6448 DAG, Subtarget, dl);
6450 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6451 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6452 if (NewOp.getNode()) {
6453 EVT NewVT = NewOp.getValueType();
6454 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
6455 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
6456 DAG, Subtarget, dl);
6464 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6465 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6466 SDValue V1 = Op.getOperand(0);
6467 SDValue V2 = Op.getOperand(1);
6468 EVT VT = Op.getValueType();
6469 DebugLoc dl = Op.getDebugLoc();
6470 unsigned NumElems = VT.getVectorNumElements();
6471 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6472 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6473 bool V1IsSplat = false;
6474 bool V2IsSplat = false;
6475 bool HasSSE2 = Subtarget->hasSSE2();
6476 bool HasAVX = Subtarget->hasAVX();
6477 bool HasAVX2 = Subtarget->hasAVX2();
6478 MachineFunction &MF = DAG.getMachineFunction();
6479 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6481 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6483 if (V1IsUndef && V2IsUndef)
6484 return DAG.getUNDEF(VT);
6486 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6488 // Vector shuffle lowering takes 3 steps:
6490 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6491 // narrowing and commutation of operands should be handled.
6492 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6494 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6495 // so the shuffle can be broken into other shuffles and the legalizer can
6496 // try the lowering again.
6498 // The general idea is that no vector_shuffle operation should be left to
6499 // be matched during isel, all of them must be converted to a target specific
6502 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6503 // narrowing and commutation of operands should be handled. The actual code
6504 // doesn't include all of those, work in progress...
6505 SDValue NewOp = NormalizeVectorShuffle(Op, DAG);
6506 if (NewOp.getNode())
6509 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
6511 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6512 // unpckh_undef). Only use pshufd if speed is more important than size.
6513 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6514 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6515 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6516 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6518 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
6519 V2IsUndef && RelaxedMayFoldVectorLoad(V1))
6520 return getMOVDDup(Op, dl, V1, DAG);
6522 if (isMOVHLPS_v_undef_Mask(M, VT))
6523 return getMOVHighToLow(Op, dl, DAG);
6525 // Use to match splats
6526 if (HasSSE2 && isUNPCKHMask(M, VT, HasAVX2) && V2IsUndef &&
6527 (VT == MVT::v2f64 || VT == MVT::v2i64))
6528 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6530 if (isPSHUFDMask(M, VT)) {
6531 // The actual implementation will match the mask in the if above and then
6532 // during isel it can match several different instructions, not only pshufd
6533 // as its name says, sad but true, emulate the behavior for now...
6534 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6535 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6537 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
6539 if (HasAVX && (VT == MVT::v4f32 || VT == MVT::v2f64))
6540 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask, DAG);
6542 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6543 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6545 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6549 // Check if this can be converted into a logical shift.
6550 bool isLeft = false;
6553 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6554 if (isShift && ShVal.hasOneUse()) {
6555 // If the shifted value has multiple uses, it may be cheaper to use
6556 // v_set0 + movlhps or movhlps, etc.
6557 EVT EltVT = VT.getVectorElementType();
6558 ShAmt *= EltVT.getSizeInBits();
6559 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6562 if (isMOVLMask(M, VT)) {
6563 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6564 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6565 if (!isMOVLPMask(M, VT)) {
6566 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6567 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6569 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6570 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6574 // FIXME: fold these into legal mask.
6575 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasAVX2))
6576 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6578 if (isMOVHLPSMask(M, VT))
6579 return getMOVHighToLow(Op, dl, DAG);
6581 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
6582 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6584 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
6585 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6587 if (isMOVLPMask(M, VT))
6588 return getMOVLP(Op, dl, DAG, HasSSE2);
6590 if (ShouldXformToMOVHLPS(M, VT) ||
6591 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
6592 return CommuteVectorShuffle(SVOp, DAG);
6595 // No better options. Use a vshldq / vsrldq.
6596 EVT EltVT = VT.getVectorElementType();
6597 ShAmt *= EltVT.getSizeInBits();
6598 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6601 bool Commuted = false;
6602 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6603 // 1,1,1,1 -> v8i16 though.
6604 V1IsSplat = isSplatVector(V1.getNode());
6605 V2IsSplat = isSplatVector(V2.getNode());
6607 // Canonicalize the splat or undef, if present, to be on the RHS.
6608 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
6609 CommuteVectorShuffleMask(M, NumElems);
6611 std::swap(V1IsSplat, V2IsSplat);
6615 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6616 // Shuffling low element of v1 into undef, just return v1.
6619 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6620 // the instruction selector will not match, so get a canonical MOVL with
6621 // swapped operands to undo the commute.
6622 return getMOVL(DAG, dl, VT, V2, V1);
6625 if (isUNPCKLMask(M, VT, HasAVX2))
6626 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6628 if (isUNPCKHMask(M, VT, HasAVX2))
6629 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6632 // Normalize mask so all entries that point to V2 points to its first
6633 // element then try to match unpck{h|l} again. If match, return a
6634 // new vector_shuffle with the corrected mask.p
6635 SmallVector<int, 8> NewMask(M.begin(), M.end());
6636 NormalizeMask(NewMask, NumElems);
6637 if (isUNPCKLMask(NewMask, VT, HasAVX2, true))
6638 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6639 if (isUNPCKHMask(NewMask, VT, HasAVX2, true))
6640 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6644 // Commute is back and try unpck* again.
6645 // FIXME: this seems wrong.
6646 CommuteVectorShuffleMask(M, NumElems);
6648 std::swap(V1IsSplat, V2IsSplat);
6651 if (isUNPCKLMask(M, VT, HasAVX2))
6652 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6654 if (isUNPCKHMask(M, VT, HasAVX2))
6655 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6658 // Normalize the node to match x86 shuffle ops if needed
6659 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true)))
6660 return CommuteVectorShuffle(SVOp, DAG);
6662 // The checks below are all present in isShuffleMaskLegal, but they are
6663 // inlined here right now to enable us to directly emit target specific
6664 // nodes, and remove one by one until they don't return Op anymore.
6666 if (isPALIGNRMask(M, VT, Subtarget))
6667 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6668 getShufflePALIGNRImmediate(SVOp),
6671 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6672 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6673 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6674 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6677 if (isPSHUFHWMask(M, VT, HasAVX2))
6678 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6679 getShufflePSHUFHWImmediate(SVOp),
6682 if (isPSHUFLWMask(M, VT, HasAVX2))
6683 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6684 getShufflePSHUFLWImmediate(SVOp),
6687 if (isSHUFPMask(M, VT, HasAVX))
6688 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6689 getShuffleSHUFImmediate(SVOp), DAG);
6691 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6692 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6693 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6694 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6696 //===--------------------------------------------------------------------===//
6697 // Generate target specific nodes for 128 or 256-bit shuffles only
6698 // supported in the AVX instruction set.
6701 // Handle VMOVDDUPY permutations
6702 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX))
6703 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6705 // Handle VPERMILPS/D* permutations
6706 if (isVPERMILPMask(M, VT, HasAVX)) {
6707 if (HasAVX2 && VT == MVT::v8i32)
6708 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
6709 getShuffleSHUFImmediate(SVOp), DAG);
6710 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6711 getShuffleSHUFImmediate(SVOp), DAG);
6714 // Handle VPERM2F128/VPERM2I128 permutations
6715 if (isVPERM2X128Mask(M, VT, HasAVX))
6716 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
6717 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
6719 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
6720 if (BlendOp.getNode())
6723 if (V2IsUndef && HasAVX2 && (VT == MVT::v8i32 || VT == MVT::v8f32)) {
6724 SmallVector<SDValue, 8> permclMask;
6725 for (unsigned i = 0; i != 8; ++i) {
6726 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32));
6728 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32,
6730 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
6731 return DAG.getNode(X86ISD::VPERMV, dl, VT,
6732 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
6735 if (V2IsUndef && HasAVX2 && (VT == MVT::v4i64 || VT == MVT::v4f64))
6736 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1,
6737 getShuffleCLImmediate(SVOp), DAG);
6740 //===--------------------------------------------------------------------===//
6741 // Since no target specific shuffle was selected for this generic one,
6742 // lower it into other known shuffles. FIXME: this isn't true yet, but
6743 // this is the plan.
6746 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6747 if (VT == MVT::v8i16) {
6748 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6749 if (NewOp.getNode())
6753 if (VT == MVT::v16i8) {
6754 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6755 if (NewOp.getNode())
6759 // Handle all 128-bit wide vectors with 4 elements, and match them with
6760 // several different shuffle types.
6761 if (NumElems == 4 && VT.getSizeInBits() == 128)
6762 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6764 // Handle general 256-bit shuffles
6765 if (VT.is256BitVector())
6766 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6772 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6773 SelectionDAG &DAG) const {
6774 EVT VT = Op.getValueType();
6775 DebugLoc dl = Op.getDebugLoc();
6777 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6780 if (VT.getSizeInBits() == 8) {
6781 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6782 Op.getOperand(0), Op.getOperand(1));
6783 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6784 DAG.getValueType(VT));
6785 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6788 if (VT.getSizeInBits() == 16) {
6789 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6790 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6792 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6793 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6794 DAG.getNode(ISD::BITCAST, dl,
6798 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6799 Op.getOperand(0), Op.getOperand(1));
6800 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6801 DAG.getValueType(VT));
6802 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6805 if (VT == MVT::f32) {
6806 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6807 // the result back to FR32 register. It's only worth matching if the
6808 // result has a single use which is a store or a bitcast to i32. And in
6809 // the case of a store, it's not worth it if the index is a constant 0,
6810 // because a MOVSSmr can be used instead, which is smaller and faster.
6811 if (!Op.hasOneUse())
6813 SDNode *User = *Op.getNode()->use_begin();
6814 if ((User->getOpcode() != ISD::STORE ||
6815 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6816 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6817 (User->getOpcode() != ISD::BITCAST ||
6818 User->getValueType(0) != MVT::i32))
6820 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6821 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6824 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6827 if (VT == MVT::i32 || VT == MVT::i64) {
6828 // ExtractPS/pextrq works with constant index.
6829 if (isa<ConstantSDNode>(Op.getOperand(1)))
6837 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6838 SelectionDAG &DAG) const {
6839 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6842 SDValue Vec = Op.getOperand(0);
6843 EVT VecVT = Vec.getValueType();
6845 // If this is a 256-bit vector result, first extract the 128-bit vector and
6846 // then extract the element from the 128-bit vector.
6847 if (VecVT.getSizeInBits() == 256) {
6848 DebugLoc dl = Op.getNode()->getDebugLoc();
6849 unsigned NumElems = VecVT.getVectorNumElements();
6850 SDValue Idx = Op.getOperand(1);
6851 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6853 // Get the 128-bit vector.
6854 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
6856 if (IdxVal >= NumElems/2)
6857 IdxVal -= NumElems/2;
6858 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6859 DAG.getConstant(IdxVal, MVT::i32));
6862 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6864 if (Subtarget->hasSSE41()) {
6865 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6870 EVT VT = Op.getValueType();
6871 DebugLoc dl = Op.getDebugLoc();
6872 // TODO: handle v16i8.
6873 if (VT.getSizeInBits() == 16) {
6874 SDValue Vec = Op.getOperand(0);
6875 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6877 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6878 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6879 DAG.getNode(ISD::BITCAST, dl,
6882 // Transform it so it match pextrw which produces a 32-bit result.
6883 EVT EltVT = MVT::i32;
6884 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6885 Op.getOperand(0), Op.getOperand(1));
6886 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6887 DAG.getValueType(VT));
6888 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6891 if (VT.getSizeInBits() == 32) {
6892 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6896 // SHUFPS the element to the lowest double word, then movss.
6897 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6898 EVT VVT = Op.getOperand(0).getValueType();
6899 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6900 DAG.getUNDEF(VVT), Mask);
6901 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6902 DAG.getIntPtrConstant(0));
6905 if (VT.getSizeInBits() == 64) {
6906 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6907 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6908 // to match extract_elt for f64.
6909 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6913 // UNPCKHPD the element to the lowest double word, then movsd.
6914 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6915 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6916 int Mask[2] = { 1, -1 };
6917 EVT VVT = Op.getOperand(0).getValueType();
6918 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6919 DAG.getUNDEF(VVT), Mask);
6920 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6921 DAG.getIntPtrConstant(0));
6928 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6929 SelectionDAG &DAG) const {
6930 EVT VT = Op.getValueType();
6931 EVT EltVT = VT.getVectorElementType();
6932 DebugLoc dl = Op.getDebugLoc();
6934 SDValue N0 = Op.getOperand(0);
6935 SDValue N1 = Op.getOperand(1);
6936 SDValue N2 = Op.getOperand(2);
6938 if (VT.getSizeInBits() == 256)
6941 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6942 isa<ConstantSDNode>(N2)) {
6944 if (VT == MVT::v8i16)
6945 Opc = X86ISD::PINSRW;
6946 else if (VT == MVT::v16i8)
6947 Opc = X86ISD::PINSRB;
6949 Opc = X86ISD::PINSRB;
6951 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6953 if (N1.getValueType() != MVT::i32)
6954 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6955 if (N2.getValueType() != MVT::i32)
6956 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6957 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6960 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6961 // Bits [7:6] of the constant are the source select. This will always be
6962 // zero here. The DAG Combiner may combine an extract_elt index into these
6963 // bits. For example (insert (extract, 3), 2) could be matched by putting
6964 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6965 // Bits [5:4] of the constant are the destination select. This is the
6966 // value of the incoming immediate.
6967 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6968 // combine either bitwise AND or insert of float 0.0 to set these bits.
6969 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6970 // Create this as a scalar to vector..
6971 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6972 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6975 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
6976 // PINSR* works with constant index.
6983 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
6984 EVT VT = Op.getValueType();
6985 EVT EltVT = VT.getVectorElementType();
6987 DebugLoc dl = Op.getDebugLoc();
6988 SDValue N0 = Op.getOperand(0);
6989 SDValue N1 = Op.getOperand(1);
6990 SDValue N2 = Op.getOperand(2);
6992 // If this is a 256-bit vector result, first extract the 128-bit vector,
6993 // insert the element into the extracted half and then place it back.
6994 if (VT.getSizeInBits() == 256) {
6995 if (!isa<ConstantSDNode>(N2))
6998 // Get the desired 128-bit vector half.
6999 unsigned NumElems = VT.getVectorNumElements();
7000 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7001 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
7003 // Insert the element into the desired half.
7004 bool Upper = IdxVal >= NumElems/2;
7005 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
7006 DAG.getConstant(Upper ? IdxVal-NumElems/2 : IdxVal, MVT::i32));
7008 // Insert the changed part back to the 256-bit vector
7009 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
7012 if (Subtarget->hasSSE41())
7013 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7015 if (EltVT == MVT::i8)
7018 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7019 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7020 // as its second argument.
7021 if (N1.getValueType() != MVT::i32)
7022 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7023 if (N2.getValueType() != MVT::i32)
7024 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7025 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7031 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
7032 LLVMContext *Context = DAG.getContext();
7033 DebugLoc dl = Op.getDebugLoc();
7034 EVT OpVT = Op.getValueType();
7036 // If this is a 256-bit vector result, first insert into a 128-bit
7037 // vector and then insert into the 256-bit vector.
7038 if (OpVT.getSizeInBits() > 128) {
7039 // Insert into a 128-bit vector.
7040 EVT VT128 = EVT::getVectorVT(*Context,
7041 OpVT.getVectorElementType(),
7042 OpVT.getVectorNumElements() / 2);
7044 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7046 // Insert the 128-bit vector.
7047 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
7050 if (OpVT == MVT::v1i64 &&
7051 Op.getOperand(0).getValueType() == MVT::i64)
7052 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7054 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7055 assert(OpVT.getSizeInBits() == 128 && "Expected an SSE type!");
7056 return DAG.getNode(ISD::BITCAST, dl, OpVT,
7057 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7060 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7061 // a simple subregister reference or explicit instructions to grab
7062 // upper bits of a vector.
7064 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7065 if (Subtarget->hasAVX()) {
7066 DebugLoc dl = Op.getNode()->getDebugLoc();
7067 SDValue Vec = Op.getNode()->getOperand(0);
7068 SDValue Idx = Op.getNode()->getOperand(1);
7070 if (Op.getNode()->getValueType(0).getSizeInBits() == 128 &&
7071 Vec.getNode()->getValueType(0).getSizeInBits() == 256 &&
7072 isa<ConstantSDNode>(Idx)) {
7073 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7074 return Extract128BitVector(Vec, IdxVal, DAG, dl);
7080 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7081 // simple superregister reference or explicit instructions to insert
7082 // the upper bits of a vector.
7084 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7085 if (Subtarget->hasAVX()) {
7086 DebugLoc dl = Op.getNode()->getDebugLoc();
7087 SDValue Vec = Op.getNode()->getOperand(0);
7088 SDValue SubVec = Op.getNode()->getOperand(1);
7089 SDValue Idx = Op.getNode()->getOperand(2);
7091 if (Op.getNode()->getValueType(0).getSizeInBits() == 256 &&
7092 SubVec.getNode()->getValueType(0).getSizeInBits() == 128 &&
7093 isa<ConstantSDNode>(Idx)) {
7094 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7095 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
7101 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7102 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7103 // one of the above mentioned nodes. It has to be wrapped because otherwise
7104 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7105 // be used to form addressing mode. These wrapped nodes will be selected
7108 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7109 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7111 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7113 unsigned char OpFlag = 0;
7114 unsigned WrapperKind = X86ISD::Wrapper;
7115 CodeModel::Model M = getTargetMachine().getCodeModel();
7117 if (Subtarget->isPICStyleRIPRel() &&
7118 (M == CodeModel::Small || M == CodeModel::Kernel))
7119 WrapperKind = X86ISD::WrapperRIP;
7120 else if (Subtarget->isPICStyleGOT())
7121 OpFlag = X86II::MO_GOTOFF;
7122 else if (Subtarget->isPICStyleStubPIC())
7123 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7125 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7127 CP->getOffset(), OpFlag);
7128 DebugLoc DL = CP->getDebugLoc();
7129 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7130 // With PIC, the address is actually $g + Offset.
7132 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7133 DAG.getNode(X86ISD::GlobalBaseReg,
7134 DebugLoc(), getPointerTy()),
7141 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7142 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7144 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7146 unsigned char OpFlag = 0;
7147 unsigned WrapperKind = X86ISD::Wrapper;
7148 CodeModel::Model M = getTargetMachine().getCodeModel();
7150 if (Subtarget->isPICStyleRIPRel() &&
7151 (M == CodeModel::Small || M == CodeModel::Kernel))
7152 WrapperKind = X86ISD::WrapperRIP;
7153 else if (Subtarget->isPICStyleGOT())
7154 OpFlag = X86II::MO_GOTOFF;
7155 else if (Subtarget->isPICStyleStubPIC())
7156 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7158 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7160 DebugLoc DL = JT->getDebugLoc();
7161 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7163 // With PIC, the address is actually $g + Offset.
7165 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7166 DAG.getNode(X86ISD::GlobalBaseReg,
7167 DebugLoc(), getPointerTy()),
7174 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7175 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7177 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7179 unsigned char OpFlag = 0;
7180 unsigned WrapperKind = X86ISD::Wrapper;
7181 CodeModel::Model M = getTargetMachine().getCodeModel();
7183 if (Subtarget->isPICStyleRIPRel() &&
7184 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7185 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7186 OpFlag = X86II::MO_GOTPCREL;
7187 WrapperKind = X86ISD::WrapperRIP;
7188 } else if (Subtarget->isPICStyleGOT()) {
7189 OpFlag = X86II::MO_GOT;
7190 } else if (Subtarget->isPICStyleStubPIC()) {
7191 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7192 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7193 OpFlag = X86II::MO_DARWIN_NONLAZY;
7196 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7198 DebugLoc DL = Op.getDebugLoc();
7199 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7202 // With PIC, the address is actually $g + Offset.
7203 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7204 !Subtarget->is64Bit()) {
7205 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7206 DAG.getNode(X86ISD::GlobalBaseReg,
7207 DebugLoc(), getPointerTy()),
7211 // For symbols that require a load from a stub to get the address, emit the
7213 if (isGlobalStubReference(OpFlag))
7214 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7215 MachinePointerInfo::getGOT(), false, false, false, 0);
7221 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7222 // Create the TargetBlockAddressAddress node.
7223 unsigned char OpFlags =
7224 Subtarget->ClassifyBlockAddressReference();
7225 CodeModel::Model M = getTargetMachine().getCodeModel();
7226 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7227 DebugLoc dl = Op.getDebugLoc();
7228 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7229 /*isTarget=*/true, OpFlags);
7231 if (Subtarget->isPICStyleRIPRel() &&
7232 (M == CodeModel::Small || M == CodeModel::Kernel))
7233 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7235 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7237 // With PIC, the address is actually $g + Offset.
7238 if (isGlobalRelativeToPICBase(OpFlags)) {
7239 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7240 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7248 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7250 SelectionDAG &DAG) const {
7251 // Create the TargetGlobalAddress node, folding in the constant
7252 // offset if it is legal.
7253 unsigned char OpFlags =
7254 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7255 CodeModel::Model M = getTargetMachine().getCodeModel();
7257 if (OpFlags == X86II::MO_NO_FLAG &&
7258 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7259 // A direct static reference to a global.
7260 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7263 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7266 if (Subtarget->isPICStyleRIPRel() &&
7267 (M == CodeModel::Small || M == CodeModel::Kernel))
7268 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7270 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7272 // With PIC, the address is actually $g + Offset.
7273 if (isGlobalRelativeToPICBase(OpFlags)) {
7274 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7275 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7279 // For globals that require a load from a stub to get the address, emit the
7281 if (isGlobalStubReference(OpFlags))
7282 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7283 MachinePointerInfo::getGOT(), false, false, false, 0);
7285 // If there was a non-zero offset that we didn't fold, create an explicit
7288 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7289 DAG.getConstant(Offset, getPointerTy()));
7295 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7296 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7297 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7298 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7302 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7303 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7304 unsigned char OperandFlags, bool LocalDynamic = false) {
7305 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7306 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7307 DebugLoc dl = GA->getDebugLoc();
7308 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7309 GA->getValueType(0),
7313 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
7317 SDValue Ops[] = { Chain, TGA, *InFlag };
7318 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 3);
7320 SDValue Ops[] = { Chain, TGA };
7321 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 2);
7324 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7325 MFI->setAdjustsStack(true);
7327 SDValue Flag = Chain.getValue(1);
7328 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7331 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7333 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7336 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7337 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7338 DAG.getNode(X86ISD::GlobalBaseReg,
7339 DebugLoc(), PtrVT), InFlag);
7340 InFlag = Chain.getValue(1);
7342 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7345 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7347 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7349 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7350 X86::RAX, X86II::MO_TLSGD);
7353 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
7357 DebugLoc dl = GA->getDebugLoc();
7359 // Get the start address of the TLS block for this module.
7360 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
7361 .getInfo<X86MachineFunctionInfo>();
7362 MFI->incNumLocalDynamicTLSAccesses();
7366 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
7367 X86II::MO_TLSLD, /*LocalDynamic=*/true);
7370 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7371 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT), InFlag);
7372 InFlag = Chain.getValue(1);
7373 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
7374 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
7377 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
7381 unsigned char OperandFlags = X86II::MO_DTPOFF;
7382 unsigned WrapperKind = X86ISD::Wrapper;
7383 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7384 GA->getValueType(0),
7385 GA->getOffset(), OperandFlags);
7386 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7388 // Add x@dtpoff with the base.
7389 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
7392 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
7393 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7394 const EVT PtrVT, TLSModel::Model model,
7395 bool is64Bit, bool isPIC) {
7396 DebugLoc dl = GA->getDebugLoc();
7398 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7399 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7400 is64Bit ? 257 : 256));
7402 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7403 DAG.getIntPtrConstant(0),
7404 MachinePointerInfo(Ptr),
7405 false, false, false, 0);
7407 unsigned char OperandFlags = 0;
7408 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7410 unsigned WrapperKind = X86ISD::Wrapper;
7411 if (model == TLSModel::LocalExec) {
7412 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7413 } else if (model == TLSModel::InitialExec) {
7415 OperandFlags = X86II::MO_GOTTPOFF;
7416 WrapperKind = X86ISD::WrapperRIP;
7418 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
7421 llvm_unreachable("Unexpected model");
7424 // emit "addl x@ntpoff,%eax" (local exec)
7425 // or "addl x@indntpoff,%eax" (initial exec)
7426 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
7427 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7428 GA->getValueType(0),
7429 GA->getOffset(), OperandFlags);
7430 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7432 if (model == TLSModel::InitialExec) {
7433 if (isPIC && !is64Bit) {
7434 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
7435 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT),
7439 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7440 MachinePointerInfo::getGOT(), false, false, false,
7444 // The address of the thread local variable is the add of the thread
7445 // pointer with the offset of the variable.
7446 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7450 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7452 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7453 const GlobalValue *GV = GA->getGlobal();
7455 if (Subtarget->isTargetELF()) {
7456 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
7459 case TLSModel::GeneralDynamic:
7460 if (Subtarget->is64Bit())
7461 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7462 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7463 case TLSModel::LocalDynamic:
7464 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
7465 Subtarget->is64Bit());
7466 case TLSModel::InitialExec:
7467 case TLSModel::LocalExec:
7468 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7469 Subtarget->is64Bit(),
7470 getTargetMachine().getRelocationModel() == Reloc::PIC_);
7472 llvm_unreachable("Unknown TLS model.");
7475 if (Subtarget->isTargetDarwin()) {
7476 // Darwin only has one model of TLS. Lower to that.
7477 unsigned char OpFlag = 0;
7478 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7479 X86ISD::WrapperRIP : X86ISD::Wrapper;
7481 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7483 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7484 !Subtarget->is64Bit();
7486 OpFlag = X86II::MO_TLVP_PIC_BASE;
7488 OpFlag = X86II::MO_TLVP;
7489 DebugLoc DL = Op.getDebugLoc();
7490 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7491 GA->getValueType(0),
7492 GA->getOffset(), OpFlag);
7493 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7495 // With PIC32, the address is actually $g + Offset.
7497 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7498 DAG.getNode(X86ISD::GlobalBaseReg,
7499 DebugLoc(), getPointerTy()),
7502 // Lowering the machine isd will make sure everything is in the right
7504 SDValue Chain = DAG.getEntryNode();
7505 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7506 SDValue Args[] = { Chain, Offset };
7507 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7509 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7510 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7511 MFI->setAdjustsStack(true);
7513 // And our return value (tls address) is in the standard call return value
7515 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7516 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7520 if (Subtarget->isTargetWindows()) {
7521 // Just use the implicit TLS architecture
7522 // Need to generate someting similar to:
7523 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
7525 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
7526 // mov rcx, qword [rdx+rcx*8]
7527 // mov eax, .tls$:tlsvar
7528 // [rax+rcx] contains the address
7529 // Windows 64bit: gs:0x58
7530 // Windows 32bit: fs:__tls_array
7532 // If GV is an alias then use the aliasee for determining
7533 // thread-localness.
7534 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7535 GV = GA->resolveAliasedGlobal(false);
7536 DebugLoc dl = GA->getDebugLoc();
7537 SDValue Chain = DAG.getEntryNode();
7539 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
7540 // %gs:0x58 (64-bit).
7541 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
7542 ? Type::getInt8PtrTy(*DAG.getContext(),
7544 : Type::getInt32PtrTy(*DAG.getContext(),
7547 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain,
7548 Subtarget->is64Bit()
7549 ? DAG.getIntPtrConstant(0x58)
7550 : DAG.getExternalSymbol("_tls_array",
7552 MachinePointerInfo(Ptr),
7553 false, false, false, 0);
7555 // Load the _tls_index variable
7556 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
7557 if (Subtarget->is64Bit())
7558 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
7559 IDX, MachinePointerInfo(), MVT::i32,
7562 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
7563 false, false, false, 0);
7565 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
7567 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
7569 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
7570 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
7571 false, false, false, 0);
7573 // Get the offset of start of .tls section
7574 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7575 GA->getValueType(0),
7576 GA->getOffset(), X86II::MO_SECREL);
7577 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
7579 // The address of the thread local variable is the add of the thread
7580 // pointer with the offset of the variable.
7581 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
7584 llvm_unreachable("TLS not implemented for this target.");
7588 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7589 /// and take a 2 x i32 value to shift plus a shift amount.
7590 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7591 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7592 EVT VT = Op.getValueType();
7593 unsigned VTBits = VT.getSizeInBits();
7594 DebugLoc dl = Op.getDebugLoc();
7595 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7596 SDValue ShOpLo = Op.getOperand(0);
7597 SDValue ShOpHi = Op.getOperand(1);
7598 SDValue ShAmt = Op.getOperand(2);
7599 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7600 DAG.getConstant(VTBits - 1, MVT::i8))
7601 : DAG.getConstant(0, VT);
7604 if (Op.getOpcode() == ISD::SHL_PARTS) {
7605 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7606 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7608 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7609 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7612 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7613 DAG.getConstant(VTBits, MVT::i8));
7614 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7615 AndNode, DAG.getConstant(0, MVT::i8));
7618 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7619 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7620 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7622 if (Op.getOpcode() == ISD::SHL_PARTS) {
7623 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7624 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7626 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7627 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7630 SDValue Ops[2] = { Lo, Hi };
7631 return DAG.getMergeValues(Ops, 2, dl);
7634 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7635 SelectionDAG &DAG) const {
7636 EVT SrcVT = Op.getOperand(0).getValueType();
7638 if (SrcVT.isVector())
7641 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7642 "Unknown SINT_TO_FP to lower!");
7644 // These are really Legal; return the operand so the caller accepts it as
7646 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7648 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7649 Subtarget->is64Bit()) {
7653 DebugLoc dl = Op.getDebugLoc();
7654 unsigned Size = SrcVT.getSizeInBits()/8;
7655 MachineFunction &MF = DAG.getMachineFunction();
7656 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7657 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7658 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7660 MachinePointerInfo::getFixedStack(SSFI),
7662 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7665 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7667 SelectionDAG &DAG) const {
7669 DebugLoc DL = Op.getDebugLoc();
7671 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7673 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7675 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7677 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7679 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7680 MachineMemOperand *MMO;
7682 int SSFI = FI->getIndex();
7684 DAG.getMachineFunction()
7685 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7686 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7688 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7689 StackSlot = StackSlot.getOperand(1);
7691 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7692 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7694 Tys, Ops, array_lengthof(Ops),
7698 Chain = Result.getValue(1);
7699 SDValue InFlag = Result.getValue(2);
7701 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7702 // shouldn't be necessary except that RFP cannot be live across
7703 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7704 MachineFunction &MF = DAG.getMachineFunction();
7705 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7706 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7707 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7708 Tys = DAG.getVTList(MVT::Other);
7710 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7712 MachineMemOperand *MMO =
7713 DAG.getMachineFunction()
7714 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7715 MachineMemOperand::MOStore, SSFISize, SSFISize);
7717 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7718 Ops, array_lengthof(Ops),
7719 Op.getValueType(), MMO);
7720 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7721 MachinePointerInfo::getFixedStack(SSFI),
7722 false, false, false, 0);
7728 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7729 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7730 SelectionDAG &DAG) const {
7731 // This algorithm is not obvious. Here it is what we're trying to output:
7734 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
7735 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
7739 pshufd $0x4e, %xmm0, %xmm1
7744 DebugLoc dl = Op.getDebugLoc();
7745 LLVMContext *Context = DAG.getContext();
7747 // Build some magic constants.
7748 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
7749 Constant *C0 = ConstantDataVector::get(*Context, CV0);
7750 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7752 SmallVector<Constant*,2> CV1;
7754 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7756 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7757 Constant *C1 = ConstantVector::get(CV1);
7758 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7760 // Load the 64-bit value into an XMM register.
7761 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
7763 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7764 MachinePointerInfo::getConstantPool(),
7765 false, false, false, 16);
7766 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
7767 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
7770 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7771 MachinePointerInfo::getConstantPool(),
7772 false, false, false, 16);
7773 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
7774 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7777 if (Subtarget->hasSSE3()) {
7778 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
7779 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
7781 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
7782 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
7784 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
7785 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
7789 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
7790 DAG.getIntPtrConstant(0));
7793 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7794 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7795 SelectionDAG &DAG) const {
7796 DebugLoc dl = Op.getDebugLoc();
7797 // FP constant to bias correct the final result.
7798 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7801 // Load the 32-bit value into an XMM register.
7802 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7805 // Zero out the upper parts of the register.
7806 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
7808 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7809 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7810 DAG.getIntPtrConstant(0));
7812 // Or the load with the bias.
7813 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7814 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7815 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7817 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7818 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7819 MVT::v2f64, Bias)));
7820 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7821 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7822 DAG.getIntPtrConstant(0));
7824 // Subtract the bias.
7825 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7827 // Handle final rounding.
7828 EVT DestVT = Op.getValueType();
7830 if (DestVT.bitsLT(MVT::f64))
7831 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7832 DAG.getIntPtrConstant(0));
7833 if (DestVT.bitsGT(MVT::f64))
7834 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7836 // Handle final rounding.
7840 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7841 SelectionDAG &DAG) const {
7842 SDValue N0 = Op.getOperand(0);
7843 DebugLoc dl = Op.getDebugLoc();
7845 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7846 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7847 // the optimization here.
7848 if (DAG.SignBitIsZero(N0))
7849 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7851 EVT SrcVT = N0.getValueType();
7852 EVT DstVT = Op.getValueType();
7853 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7854 return LowerUINT_TO_FP_i64(Op, DAG);
7855 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7856 return LowerUINT_TO_FP_i32(Op, DAG);
7857 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
7860 // Make a 64-bit buffer, and use it to build an FILD.
7861 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7862 if (SrcVT == MVT::i32) {
7863 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7864 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7865 getPointerTy(), StackSlot, WordOff);
7866 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7867 StackSlot, MachinePointerInfo(),
7869 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7870 OffsetSlot, MachinePointerInfo(),
7872 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7876 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7877 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7878 StackSlot, MachinePointerInfo(),
7880 // For i64 source, we need to add the appropriate power of 2 if the input
7881 // was negative. This is the same as the optimization in
7882 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7883 // we must be careful to do the computation in x87 extended precision, not
7884 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7885 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7886 MachineMemOperand *MMO =
7887 DAG.getMachineFunction()
7888 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7889 MachineMemOperand::MOLoad, 8, 8);
7891 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7892 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7893 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7896 APInt FF(32, 0x5F800000ULL);
7898 // Check whether the sign bit is set.
7899 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7900 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7903 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7904 SDValue FudgePtr = DAG.getConstantPool(
7905 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7908 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7909 SDValue Zero = DAG.getIntPtrConstant(0);
7910 SDValue Four = DAG.getIntPtrConstant(4);
7911 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7913 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7915 // Load the value out, extending it from f32 to f80.
7916 // FIXME: Avoid the extend by constructing the right constant pool?
7917 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7918 FudgePtr, MachinePointerInfo::getConstantPool(),
7919 MVT::f32, false, false, 4);
7920 // Extend everything to 80 bits to force it to be done on x87.
7921 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7922 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7925 std::pair<SDValue,SDValue> X86TargetLowering::
7926 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const {
7927 DebugLoc DL = Op.getDebugLoc();
7929 EVT DstTy = Op.getValueType();
7931 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
7932 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7936 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7937 DstTy.getSimpleVT() >= MVT::i16 &&
7938 "Unknown FP_TO_INT to lower!");
7940 // These are really Legal.
7941 if (DstTy == MVT::i32 &&
7942 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7943 return std::make_pair(SDValue(), SDValue());
7944 if (Subtarget->is64Bit() &&
7945 DstTy == MVT::i64 &&
7946 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7947 return std::make_pair(SDValue(), SDValue());
7949 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
7950 // stack slot, or into the FTOL runtime function.
7951 MachineFunction &MF = DAG.getMachineFunction();
7952 unsigned MemSize = DstTy.getSizeInBits()/8;
7953 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7954 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7957 if (!IsSigned && isIntegerTypeFTOL(DstTy))
7958 Opc = X86ISD::WIN_FTOL;
7960 switch (DstTy.getSimpleVT().SimpleTy) {
7961 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7962 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7963 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7964 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7967 SDValue Chain = DAG.getEntryNode();
7968 SDValue Value = Op.getOperand(0);
7969 EVT TheVT = Op.getOperand(0).getValueType();
7970 // FIXME This causes a redundant load/store if the SSE-class value is already
7971 // in memory, such as if it is on the callstack.
7972 if (isScalarFPTypeInSSEReg(TheVT)) {
7973 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7974 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7975 MachinePointerInfo::getFixedStack(SSFI),
7977 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7979 Chain, StackSlot, DAG.getValueType(TheVT)
7982 MachineMemOperand *MMO =
7983 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7984 MachineMemOperand::MOLoad, MemSize, MemSize);
7985 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7987 Chain = Value.getValue(1);
7988 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7989 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7992 MachineMemOperand *MMO =
7993 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7994 MachineMemOperand::MOStore, MemSize, MemSize);
7996 if (Opc != X86ISD::WIN_FTOL) {
7997 // Build the FP_TO_INT*_IN_MEM
7998 SDValue Ops[] = { Chain, Value, StackSlot };
7999 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
8000 Ops, 3, DstTy, MMO);
8001 return std::make_pair(FIST, StackSlot);
8003 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
8004 DAG.getVTList(MVT::Other, MVT::Glue),
8006 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
8007 MVT::i32, ftol.getValue(1));
8008 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
8009 MVT::i32, eax.getValue(2));
8010 SDValue Ops[] = { eax, edx };
8011 SDValue pair = IsReplace
8012 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2)
8013 : DAG.getMergeValues(Ops, 2, DL);
8014 return std::make_pair(pair, SDValue());
8018 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
8019 SelectionDAG &DAG) const {
8020 if (Op.getValueType().isVector())
8023 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
8024 /*IsSigned=*/ true, /*IsReplace=*/ false);
8025 SDValue FIST = Vals.first, StackSlot = Vals.second;
8026 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
8027 if (FIST.getNode() == 0) return Op;
8029 if (StackSlot.getNode())
8031 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
8032 FIST, StackSlot, MachinePointerInfo(),
8033 false, false, false, 0);
8035 // The node is the result.
8039 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
8040 SelectionDAG &DAG) const {
8041 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
8042 /*IsSigned=*/ false, /*IsReplace=*/ false);
8043 SDValue FIST = Vals.first, StackSlot = Vals.second;
8044 assert(FIST.getNode() && "Unexpected failure");
8046 if (StackSlot.getNode())
8048 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
8049 FIST, StackSlot, MachinePointerInfo(),
8050 false, false, false, 0);
8052 // The node is the result.
8056 SDValue X86TargetLowering::LowerFABS(SDValue Op,
8057 SelectionDAG &DAG) const {
8058 LLVMContext *Context = DAG.getContext();
8059 DebugLoc dl = Op.getDebugLoc();
8060 EVT VT = Op.getValueType();
8063 EltVT = VT.getVectorElementType();
8065 if (EltVT == MVT::f64) {
8066 C = ConstantVector::getSplat(2,
8067 ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8069 C = ConstantVector::getSplat(4,
8070 ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8072 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8073 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8074 MachinePointerInfo::getConstantPool(),
8075 false, false, false, 16);
8076 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
8079 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
8080 LLVMContext *Context = DAG.getContext();
8081 DebugLoc dl = Op.getDebugLoc();
8082 EVT VT = Op.getValueType();
8084 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
8085 if (VT.isVector()) {
8086 EltVT = VT.getVectorElementType();
8087 NumElts = VT.getVectorNumElements();
8090 if (EltVT == MVT::f64)
8091 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
8093 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
8094 C = ConstantVector::getSplat(NumElts, C);
8095 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8096 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8097 MachinePointerInfo::getConstantPool(),
8098 false, false, false, 16);
8099 if (VT.isVector()) {
8100 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64;
8101 return DAG.getNode(ISD::BITCAST, dl, VT,
8102 DAG.getNode(ISD::XOR, dl, XORVT,
8103 DAG.getNode(ISD::BITCAST, dl, XORVT,
8105 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
8108 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
8111 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
8112 LLVMContext *Context = DAG.getContext();
8113 SDValue Op0 = Op.getOperand(0);
8114 SDValue Op1 = Op.getOperand(1);
8115 DebugLoc dl = Op.getDebugLoc();
8116 EVT VT = Op.getValueType();
8117 EVT SrcVT = Op1.getValueType();
8119 // If second operand is smaller, extend it first.
8120 if (SrcVT.bitsLT(VT)) {
8121 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
8124 // And if it is bigger, shrink it first.
8125 if (SrcVT.bitsGT(VT)) {
8126 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
8130 // At this point the operands and the result should have the same
8131 // type, and that won't be f80 since that is not custom lowered.
8133 // First get the sign bit of second operand.
8134 SmallVector<Constant*,4> CV;
8135 if (SrcVT == MVT::f64) {
8136 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
8137 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8139 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
8140 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8141 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8142 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8144 Constant *C = ConstantVector::get(CV);
8145 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8146 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
8147 MachinePointerInfo::getConstantPool(),
8148 false, false, false, 16);
8149 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
8151 // Shift sign bit right or left if the two operands have different types.
8152 if (SrcVT.bitsGT(VT)) {
8153 // Op0 is MVT::f32, Op1 is MVT::f64.
8154 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
8155 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
8156 DAG.getConstant(32, MVT::i32));
8157 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
8158 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
8159 DAG.getIntPtrConstant(0));
8162 // Clear first operand sign bit.
8164 if (VT == MVT::f64) {
8165 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8166 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8168 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8169 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8170 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8171 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8173 C = ConstantVector::get(CV);
8174 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8175 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8176 MachinePointerInfo::getConstantPool(),
8177 false, false, false, 16);
8178 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8180 // Or the value with the sign bit.
8181 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8184 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
8185 SDValue N0 = Op.getOperand(0);
8186 DebugLoc dl = Op.getDebugLoc();
8187 EVT VT = Op.getValueType();
8189 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8190 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8191 DAG.getConstant(1, VT));
8192 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8195 /// Emit nodes that will be selected as "test Op0,Op0", or something
8197 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8198 SelectionDAG &DAG) const {
8199 DebugLoc dl = Op.getDebugLoc();
8201 // CF and OF aren't always set the way we want. Determine which
8202 // of these we need.
8203 bool NeedCF = false;
8204 bool NeedOF = false;
8207 case X86::COND_A: case X86::COND_AE:
8208 case X86::COND_B: case X86::COND_BE:
8211 case X86::COND_G: case X86::COND_GE:
8212 case X86::COND_L: case X86::COND_LE:
8213 case X86::COND_O: case X86::COND_NO:
8218 // See if we can use the EFLAGS value from the operand instead of
8219 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8220 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8221 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8222 // Emit a CMP with 0, which is the TEST pattern.
8223 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8224 DAG.getConstant(0, Op.getValueType()));
8226 unsigned Opcode = 0;
8227 unsigned NumOperands = 0;
8228 switch (Op.getNode()->getOpcode()) {
8230 // Due to an isel shortcoming, be conservative if this add is likely to be
8231 // selected as part of a load-modify-store instruction. When the root node
8232 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8233 // uses of other nodes in the match, such as the ADD in this case. This
8234 // leads to the ADD being left around and reselected, with the result being
8235 // two adds in the output. Alas, even if none our users are stores, that
8236 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8237 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8238 // climbing the DAG back to the root, and it doesn't seem to be worth the
8240 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8241 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8242 if (UI->getOpcode() != ISD::CopyToReg &&
8243 UI->getOpcode() != ISD::SETCC &&
8244 UI->getOpcode() != ISD::STORE)
8247 if (ConstantSDNode *C =
8248 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8249 // An add of one will be selected as an INC.
8250 if (C->getAPIntValue() == 1) {
8251 Opcode = X86ISD::INC;
8256 // An add of negative one (subtract of one) will be selected as a DEC.
8257 if (C->getAPIntValue().isAllOnesValue()) {
8258 Opcode = X86ISD::DEC;
8264 // Otherwise use a regular EFLAGS-setting add.
8265 Opcode = X86ISD::ADD;
8269 // If the primary and result isn't used, don't bother using X86ISD::AND,
8270 // because a TEST instruction will be better.
8271 bool NonFlagUse = false;
8272 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8273 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8275 unsigned UOpNo = UI.getOperandNo();
8276 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8277 // Look pass truncate.
8278 UOpNo = User->use_begin().getOperandNo();
8279 User = *User->use_begin();
8282 if (User->getOpcode() != ISD::BRCOND &&
8283 User->getOpcode() != ISD::SETCC &&
8284 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8297 // Due to the ISEL shortcoming noted above, be conservative if this op is
8298 // likely to be selected as part of a load-modify-store instruction.
8299 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8300 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8301 if (UI->getOpcode() == ISD::STORE)
8304 // Otherwise use a regular EFLAGS-setting instruction.
8305 switch (Op.getNode()->getOpcode()) {
8306 default: llvm_unreachable("unexpected operator!");
8308 // If the only use of SUB is EFLAGS, use CMP instead.
8310 Opcode = X86ISD::CMP;
8312 Opcode = X86ISD::SUB;
8314 case ISD::OR: Opcode = X86ISD::OR; break;
8315 case ISD::XOR: Opcode = X86ISD::XOR; break;
8316 case ISD::AND: Opcode = X86ISD::AND; break;
8328 return SDValue(Op.getNode(), 1);
8335 // Emit a CMP with 0, which is the TEST pattern.
8336 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8337 DAG.getConstant(0, Op.getValueType()));
8339 if (Opcode == X86ISD::CMP) {
8340 SDValue New = DAG.getNode(Opcode, dl, MVT::i32, Op.getOperand(0),
8342 // We can't replace usage of SUB with CMP.
8343 // The SUB node will be removed later because there is no use of it.
8344 return SDValue(New.getNode(), 0);
8347 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8348 SmallVector<SDValue, 4> Ops;
8349 for (unsigned i = 0; i != NumOperands; ++i)
8350 Ops.push_back(Op.getOperand(i));
8352 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8353 DAG.ReplaceAllUsesWith(Op, New);
8354 return SDValue(New.getNode(), 1);
8357 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8359 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8360 SelectionDAG &DAG) const {
8361 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8362 if (C->getAPIntValue() == 0)
8363 return EmitTest(Op0, X86CC, DAG);
8365 DebugLoc dl = Op0.getDebugLoc();
8366 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8369 /// Convert a comparison if required by the subtarget.
8370 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
8371 SelectionDAG &DAG) const {
8372 // If the subtarget does not support the FUCOMI instruction, floating-point
8373 // comparisons have to be converted.
8374 if (Subtarget->hasCMov() ||
8375 Cmp.getOpcode() != X86ISD::CMP ||
8376 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
8377 !Cmp.getOperand(1).getValueType().isFloatingPoint())
8380 // The instruction selector will select an FUCOM instruction instead of
8381 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
8382 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
8383 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
8384 DebugLoc dl = Cmp.getDebugLoc();
8385 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
8386 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
8387 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
8388 DAG.getConstant(8, MVT::i8));
8389 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
8390 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
8393 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8394 /// if it's possible.
8395 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8396 DebugLoc dl, SelectionDAG &DAG) const {
8397 SDValue Op0 = And.getOperand(0);
8398 SDValue Op1 = And.getOperand(1);
8399 if (Op0.getOpcode() == ISD::TRUNCATE)
8400 Op0 = Op0.getOperand(0);
8401 if (Op1.getOpcode() == ISD::TRUNCATE)
8402 Op1 = Op1.getOperand(0);
8405 if (Op1.getOpcode() == ISD::SHL)
8406 std::swap(Op0, Op1);
8407 if (Op0.getOpcode() == ISD::SHL) {
8408 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8409 if (And00C->getZExtValue() == 1) {
8410 // If we looked past a truncate, check that it's only truncating away
8412 unsigned BitWidth = Op0.getValueSizeInBits();
8413 unsigned AndBitWidth = And.getValueSizeInBits();
8414 if (BitWidth > AndBitWidth) {
8416 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
8417 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8421 RHS = Op0.getOperand(1);
8423 } else if (Op1.getOpcode() == ISD::Constant) {
8424 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8425 uint64_t AndRHSVal = AndRHS->getZExtValue();
8426 SDValue AndLHS = Op0;
8428 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
8429 LHS = AndLHS.getOperand(0);
8430 RHS = AndLHS.getOperand(1);
8433 // Use BT if the immediate can't be encoded in a TEST instruction.
8434 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
8436 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
8440 if (LHS.getNode()) {
8441 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8442 // instruction. Since the shift amount is in-range-or-undefined, we know
8443 // that doing a bittest on the i32 value is ok. We extend to i32 because
8444 // the encoding for the i16 version is larger than the i32 version.
8445 // Also promote i16 to i32 for performance / code size reason.
8446 if (LHS.getValueType() == MVT::i8 ||
8447 LHS.getValueType() == MVT::i16)
8448 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8450 // If the operand types disagree, extend the shift amount to match. Since
8451 // BT ignores high bits (like shifts) we can use anyextend.
8452 if (LHS.getValueType() != RHS.getValueType())
8453 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8455 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8456 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8457 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8458 DAG.getConstant(Cond, MVT::i8), BT);
8464 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8466 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8468 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8469 SDValue Op0 = Op.getOperand(0);
8470 SDValue Op1 = Op.getOperand(1);
8471 DebugLoc dl = Op.getDebugLoc();
8472 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8474 // Optimize to BT if possible.
8475 // Lower (X & (1 << N)) == 0 to BT(X, N).
8476 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8477 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8478 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8479 Op1.getOpcode() == ISD::Constant &&
8480 cast<ConstantSDNode>(Op1)->isNullValue() &&
8481 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8482 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8483 if (NewSetCC.getNode())
8487 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8489 if (Op1.getOpcode() == ISD::Constant &&
8490 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8491 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8492 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8494 // If the input is a setcc, then reuse the input setcc or use a new one with
8495 // the inverted condition.
8496 if (Op0.getOpcode() == X86ISD::SETCC) {
8497 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8498 bool Invert = (CC == ISD::SETNE) ^
8499 cast<ConstantSDNode>(Op1)->isNullValue();
8500 if (!Invert) return Op0;
8502 CCode = X86::GetOppositeBranchCondition(CCode);
8503 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8504 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8508 bool isFP = Op1.getValueType().isFloatingPoint();
8509 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8510 if (X86CC == X86::COND_INVALID)
8513 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8514 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
8515 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8516 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8519 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8520 // ones, and then concatenate the result back.
8521 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
8522 EVT VT = Op.getValueType();
8524 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
8525 "Unsupported value type for operation");
8527 unsigned NumElems = VT.getVectorNumElements();
8528 DebugLoc dl = Op.getDebugLoc();
8529 SDValue CC = Op.getOperand(2);
8531 // Extract the LHS vectors
8532 SDValue LHS = Op.getOperand(0);
8533 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
8534 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
8536 // Extract the RHS vectors
8537 SDValue RHS = Op.getOperand(1);
8538 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
8539 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
8541 // Issue the operation on the smaller types and concatenate the result back
8542 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8543 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8544 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8545 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8546 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8550 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8552 SDValue Op0 = Op.getOperand(0);
8553 SDValue Op1 = Op.getOperand(1);
8554 SDValue CC = Op.getOperand(2);
8555 EVT VT = Op.getValueType();
8556 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8557 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8558 DebugLoc dl = Op.getDebugLoc();
8562 EVT EltVT = Op0.getValueType().getVectorElementType();
8563 assert(EltVT == MVT::f32 || EltVT == MVT::f64); (void)EltVT;
8567 // SSE Condition code mapping:
8576 switch (SetCCOpcode) {
8579 case ISD::SETEQ: SSECC = 0; break;
8581 case ISD::SETGT: Swap = true; // Fallthrough
8583 case ISD::SETOLT: SSECC = 1; break;
8585 case ISD::SETGE: Swap = true; // Fallthrough
8587 case ISD::SETOLE: SSECC = 2; break;
8588 case ISD::SETUO: SSECC = 3; break;
8590 case ISD::SETNE: SSECC = 4; break;
8591 case ISD::SETULE: Swap = true;
8592 case ISD::SETUGE: SSECC = 5; break;
8593 case ISD::SETULT: Swap = true;
8594 case ISD::SETUGT: SSECC = 6; break;
8595 case ISD::SETO: SSECC = 7; break;
8598 std::swap(Op0, Op1);
8600 // In the two special cases we can't handle, emit two comparisons.
8602 if (SetCCOpcode == ISD::SETUEQ) {
8604 UNORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8605 DAG.getConstant(3, MVT::i8));
8606 EQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8607 DAG.getConstant(0, MVT::i8));
8608 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8610 if (SetCCOpcode == ISD::SETONE) {
8612 ORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8613 DAG.getConstant(7, MVT::i8));
8614 NEQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8615 DAG.getConstant(4, MVT::i8));
8616 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8618 llvm_unreachable("Illegal FP comparison");
8620 // Handle all other FP comparisons here.
8621 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8622 DAG.getConstant(SSECC, MVT::i8));
8625 // Break 256-bit integer vector compare into smaller ones.
8626 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
8627 return Lower256IntVSETCC(Op, DAG);
8629 // We are handling one of the integer comparisons here. Since SSE only has
8630 // GT and EQ comparisons for integer, swapping operands and multiple
8631 // operations may be required for some comparisons.
8633 bool Swap = false, Invert = false, FlipSigns = false;
8635 switch (SetCCOpcode) {
8637 case ISD::SETNE: Invert = true;
8638 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
8639 case ISD::SETLT: Swap = true;
8640 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
8641 case ISD::SETGE: Swap = true;
8642 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
8643 case ISD::SETULT: Swap = true;
8644 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
8645 case ISD::SETUGE: Swap = true;
8646 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
8649 std::swap(Op0, Op1);
8651 // Check that the operation in question is available (most are plain SSE2,
8652 // but PCMPGTQ and PCMPEQQ have different requirements).
8653 if (Opc == X86ISD::PCMPGT && VT == MVT::v2i64 && !Subtarget->hasSSE42())
8655 if (Opc == X86ISD::PCMPEQ && VT == MVT::v2i64 && !Subtarget->hasSSE41())
8658 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8659 // bits of the inputs before performing those operations.
8661 EVT EltVT = VT.getVectorElementType();
8662 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8664 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8665 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8667 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8668 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8671 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8673 // If the logical-not of the result is required, perform that now.
8675 Result = DAG.getNOT(dl, Result, VT);
8680 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8681 static bool isX86LogicalCmp(SDValue Op) {
8682 unsigned Opc = Op.getNode()->getOpcode();
8683 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
8684 Opc == X86ISD::SAHF)
8686 if (Op.getResNo() == 1 &&
8687 (Opc == X86ISD::ADD ||
8688 Opc == X86ISD::SUB ||
8689 Opc == X86ISD::ADC ||
8690 Opc == X86ISD::SBB ||
8691 Opc == X86ISD::SMUL ||
8692 Opc == X86ISD::UMUL ||
8693 Opc == X86ISD::INC ||
8694 Opc == X86ISD::DEC ||
8695 Opc == X86ISD::OR ||
8696 Opc == X86ISD::XOR ||
8697 Opc == X86ISD::AND))
8700 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8706 static bool isZero(SDValue V) {
8707 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8708 return C && C->isNullValue();
8711 static bool isAllOnes(SDValue V) {
8712 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8713 return C && C->isAllOnesValue();
8716 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8717 bool addTest = true;
8718 SDValue Cond = Op.getOperand(0);
8719 SDValue Op1 = Op.getOperand(1);
8720 SDValue Op2 = Op.getOperand(2);
8721 DebugLoc DL = Op.getDebugLoc();
8724 if (Cond.getOpcode() == ISD::SETCC) {
8725 SDValue NewCond = LowerSETCC(Cond, DAG);
8726 if (NewCond.getNode())
8730 // Handle the following cases related to max and min:
8731 // (a > b) ? (a-b) : 0
8732 // (a >= b) ? (a-b) : 0
8733 // (b < a) ? (a-b) : 0
8734 // (b <= a) ? (a-b) : 0
8735 // Comparison is removed to use EFLAGS from SUB.
8736 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op2))
8737 if (Cond.getOpcode() == X86ISD::SETCC &&
8738 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8739 (Op1.getOpcode() == ISD::SUB || Op1.getOpcode() == X86ISD::SUB) &&
8740 C->getAPIntValue() == 0) {
8741 SDValue Cmp = Cond.getOperand(1);
8742 unsigned CC = cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8743 if ((DAG.isEqualTo(Op1.getOperand(0), Cmp.getOperand(0)) &&
8744 DAG.isEqualTo(Op1.getOperand(1), Cmp.getOperand(1)) &&
8745 (CC == X86::COND_G || CC == X86::COND_GE ||
8746 CC == X86::COND_A || CC == X86::COND_AE)) ||
8747 (DAG.isEqualTo(Op1.getOperand(0), Cmp.getOperand(1)) &&
8748 DAG.isEqualTo(Op1.getOperand(1), Cmp.getOperand(0)) &&
8749 (CC == X86::COND_L || CC == X86::COND_LE ||
8750 CC == X86::COND_B || CC == X86::COND_BE))) {
8752 if (Op1.getOpcode() == ISD::SUB) {
8753 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i32);
8754 SDValue New = DAG.getNode(X86ISD::SUB, DL, VTs,
8755 Op1.getOperand(0), Op1.getOperand(1));
8756 DAG.ReplaceAllUsesWith(Op1, New);
8760 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8761 unsigned NewCC = (CC == X86::COND_G || CC == X86::COND_GE ||
8762 CC == X86::COND_L ||
8763 CC == X86::COND_LE) ? X86::COND_GE : X86::COND_AE;
8764 SDValue Ops[] = { Op2, Op1, DAG.getConstant(NewCC, MVT::i8),
8765 SDValue(Op1.getNode(), 1) };
8766 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8770 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8771 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8772 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8773 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8774 if (Cond.getOpcode() == X86ISD::SETCC &&
8775 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8776 isZero(Cond.getOperand(1).getOperand(1))) {
8777 SDValue Cmp = Cond.getOperand(1);
8779 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8781 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8782 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8783 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8785 SDValue CmpOp0 = Cmp.getOperand(0);
8786 // Apply further optimizations for special cases
8787 // (select (x != 0), -1, 0) -> neg & sbb
8788 // (select (x == 0), 0, -1) -> neg & sbb
8789 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
8790 if (YC->isNullValue() &&
8791 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
8792 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
8793 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
8794 DAG.getConstant(0, CmpOp0.getValueType()),
8796 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8797 DAG.getConstant(X86::COND_B, MVT::i8),
8798 SDValue(Neg.getNode(), 1));
8802 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8803 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8804 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
8806 SDValue Res = // Res = 0 or -1.
8807 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8808 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8810 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8811 Res = DAG.getNOT(DL, Res, Res.getValueType());
8813 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8814 if (N2C == 0 || !N2C->isNullValue())
8815 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8820 // Look past (and (setcc_carry (cmp ...)), 1).
8821 if (Cond.getOpcode() == ISD::AND &&
8822 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8823 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8824 if (C && C->getAPIntValue() == 1)
8825 Cond = Cond.getOperand(0);
8828 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8829 // setting operand in place of the X86ISD::SETCC.
8830 unsigned CondOpcode = Cond.getOpcode();
8831 if (CondOpcode == X86ISD::SETCC ||
8832 CondOpcode == X86ISD::SETCC_CARRY) {
8833 CC = Cond.getOperand(0);
8835 SDValue Cmp = Cond.getOperand(1);
8836 unsigned Opc = Cmp.getOpcode();
8837 EVT VT = Op.getValueType();
8839 bool IllegalFPCMov = false;
8840 if (VT.isFloatingPoint() && !VT.isVector() &&
8841 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8842 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8844 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8845 Opc == X86ISD::BT) { // FIXME
8849 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8850 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8851 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8852 Cond.getOperand(0).getValueType() != MVT::i8)) {
8853 SDValue LHS = Cond.getOperand(0);
8854 SDValue RHS = Cond.getOperand(1);
8858 switch (CondOpcode) {
8859 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8860 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8861 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8862 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8863 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8864 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8865 default: llvm_unreachable("unexpected overflowing operator");
8867 if (CondOpcode == ISD::UMULO)
8868 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8871 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8873 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
8875 if (CondOpcode == ISD::UMULO)
8876 Cond = X86Op.getValue(2);
8878 Cond = X86Op.getValue(1);
8880 CC = DAG.getConstant(X86Cond, MVT::i8);
8885 // Look pass the truncate.
8886 if (Cond.getOpcode() == ISD::TRUNCATE)
8887 Cond = Cond.getOperand(0);
8889 // We know the result of AND is compared against zero. Try to match
8891 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8892 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8893 if (NewSetCC.getNode()) {
8894 CC = NewSetCC.getOperand(0);
8895 Cond = NewSetCC.getOperand(1);
8902 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8903 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8906 // a < b ? -1 : 0 -> RES = ~setcc_carry
8907 // a < b ? 0 : -1 -> RES = setcc_carry
8908 // a >= b ? -1 : 0 -> RES = setcc_carry
8909 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8910 if (Cond.getOpcode() == X86ISD::CMP) {
8911 Cond = ConvertCmpIfNecessary(Cond, DAG);
8912 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8914 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8915 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8916 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8917 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8918 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8919 return DAG.getNOT(DL, Res, Res.getValueType());
8924 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8925 // condition is true.
8926 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8927 SDValue Ops[] = { Op2, Op1, CC, Cond };
8928 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8931 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8932 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8933 // from the AND / OR.
8934 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8935 Opc = Op.getOpcode();
8936 if (Opc != ISD::OR && Opc != ISD::AND)
8938 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8939 Op.getOperand(0).hasOneUse() &&
8940 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8941 Op.getOperand(1).hasOneUse());
8944 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8945 // 1 and that the SETCC node has a single use.
8946 static bool isXor1OfSetCC(SDValue Op) {
8947 if (Op.getOpcode() != ISD::XOR)
8949 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8950 if (N1C && N1C->getAPIntValue() == 1) {
8951 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8952 Op.getOperand(0).hasOneUse();
8957 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8958 bool addTest = true;
8959 SDValue Chain = Op.getOperand(0);
8960 SDValue Cond = Op.getOperand(1);
8961 SDValue Dest = Op.getOperand(2);
8962 DebugLoc dl = Op.getDebugLoc();
8964 bool Inverted = false;
8966 if (Cond.getOpcode() == ISD::SETCC) {
8967 // Check for setcc([su]{add,sub,mul}o == 0).
8968 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
8969 isa<ConstantSDNode>(Cond.getOperand(1)) &&
8970 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
8971 Cond.getOperand(0).getResNo() == 1 &&
8972 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
8973 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
8974 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
8975 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
8976 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
8977 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
8979 Cond = Cond.getOperand(0);
8981 SDValue NewCond = LowerSETCC(Cond, DAG);
8982 if (NewCond.getNode())
8987 // FIXME: LowerXALUO doesn't handle these!!
8988 else if (Cond.getOpcode() == X86ISD::ADD ||
8989 Cond.getOpcode() == X86ISD::SUB ||
8990 Cond.getOpcode() == X86ISD::SMUL ||
8991 Cond.getOpcode() == X86ISD::UMUL)
8992 Cond = LowerXALUO(Cond, DAG);
8995 // Look pass (and (setcc_carry (cmp ...)), 1).
8996 if (Cond.getOpcode() == ISD::AND &&
8997 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8998 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8999 if (C && C->getAPIntValue() == 1)
9000 Cond = Cond.getOperand(0);
9003 // If condition flag is set by a X86ISD::CMP, then use it as the condition
9004 // setting operand in place of the X86ISD::SETCC.
9005 unsigned CondOpcode = Cond.getOpcode();
9006 if (CondOpcode == X86ISD::SETCC ||
9007 CondOpcode == X86ISD::SETCC_CARRY) {
9008 CC = Cond.getOperand(0);
9010 SDValue Cmp = Cond.getOperand(1);
9011 unsigned Opc = Cmp.getOpcode();
9012 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
9013 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
9017 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
9021 // These can only come from an arithmetic instruction with overflow,
9022 // e.g. SADDO, UADDO.
9023 Cond = Cond.getNode()->getOperand(1);
9029 CondOpcode = Cond.getOpcode();
9030 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
9031 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
9032 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
9033 Cond.getOperand(0).getValueType() != MVT::i8)) {
9034 SDValue LHS = Cond.getOperand(0);
9035 SDValue RHS = Cond.getOperand(1);
9039 switch (CondOpcode) {
9040 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
9041 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
9042 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
9043 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
9044 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
9045 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
9046 default: llvm_unreachable("unexpected overflowing operator");
9049 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
9050 if (CondOpcode == ISD::UMULO)
9051 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
9054 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
9056 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
9058 if (CondOpcode == ISD::UMULO)
9059 Cond = X86Op.getValue(2);
9061 Cond = X86Op.getValue(1);
9063 CC = DAG.getConstant(X86Cond, MVT::i8);
9067 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
9068 SDValue Cmp = Cond.getOperand(0).getOperand(1);
9069 if (CondOpc == ISD::OR) {
9070 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
9071 // two branches instead of an explicit OR instruction with a
9073 if (Cmp == Cond.getOperand(1).getOperand(1) &&
9074 isX86LogicalCmp(Cmp)) {
9075 CC = Cond.getOperand(0).getOperand(0);
9076 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9077 Chain, Dest, CC, Cmp);
9078 CC = Cond.getOperand(1).getOperand(0);
9082 } else { // ISD::AND
9083 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
9084 // two branches instead of an explicit AND instruction with a
9085 // separate test. However, we only do this if this block doesn't
9086 // have a fall-through edge, because this requires an explicit
9087 // jmp when the condition is false.
9088 if (Cmp == Cond.getOperand(1).getOperand(1) &&
9089 isX86LogicalCmp(Cmp) &&
9090 Op.getNode()->hasOneUse()) {
9091 X86::CondCode CCode =
9092 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
9093 CCode = X86::GetOppositeBranchCondition(CCode);
9094 CC = DAG.getConstant(CCode, MVT::i8);
9095 SDNode *User = *Op.getNode()->use_begin();
9096 // Look for an unconditional branch following this conditional branch.
9097 // We need this because we need to reverse the successors in order
9098 // to implement FCMP_OEQ.
9099 if (User->getOpcode() == ISD::BR) {
9100 SDValue FalseBB = User->getOperand(1);
9102 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9103 assert(NewBR == User);
9107 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9108 Chain, Dest, CC, Cmp);
9109 X86::CondCode CCode =
9110 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
9111 CCode = X86::GetOppositeBranchCondition(CCode);
9112 CC = DAG.getConstant(CCode, MVT::i8);
9118 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
9119 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
9120 // It should be transformed during dag combiner except when the condition
9121 // is set by a arithmetics with overflow node.
9122 X86::CondCode CCode =
9123 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
9124 CCode = X86::GetOppositeBranchCondition(CCode);
9125 CC = DAG.getConstant(CCode, MVT::i8);
9126 Cond = Cond.getOperand(0).getOperand(1);
9128 } else if (Cond.getOpcode() == ISD::SETCC &&
9129 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
9130 // For FCMP_OEQ, we can emit
9131 // two branches instead of an explicit AND instruction with a
9132 // separate test. However, we only do this if this block doesn't
9133 // have a fall-through edge, because this requires an explicit
9134 // jmp when the condition is false.
9135 if (Op.getNode()->hasOneUse()) {
9136 SDNode *User = *Op.getNode()->use_begin();
9137 // Look for an unconditional branch following this conditional branch.
9138 // We need this because we need to reverse the successors in order
9139 // to implement FCMP_OEQ.
9140 if (User->getOpcode() == ISD::BR) {
9141 SDValue FalseBB = User->getOperand(1);
9143 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9144 assert(NewBR == User);
9148 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
9149 Cond.getOperand(0), Cond.getOperand(1));
9150 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9151 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9152 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9153 Chain, Dest, CC, Cmp);
9154 CC = DAG.getConstant(X86::COND_P, MVT::i8);
9159 } else if (Cond.getOpcode() == ISD::SETCC &&
9160 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
9161 // For FCMP_UNE, we can emit
9162 // two branches instead of an explicit AND instruction with a
9163 // separate test. However, we only do this if this block doesn't
9164 // have a fall-through edge, because this requires an explicit
9165 // jmp when the condition is false.
9166 if (Op.getNode()->hasOneUse()) {
9167 SDNode *User = *Op.getNode()->use_begin();
9168 // Look for an unconditional branch following this conditional branch.
9169 // We need this because we need to reverse the successors in order
9170 // to implement FCMP_UNE.
9171 if (User->getOpcode() == ISD::BR) {
9172 SDValue FalseBB = User->getOperand(1);
9174 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9175 assert(NewBR == User);
9178 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
9179 Cond.getOperand(0), Cond.getOperand(1));
9180 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9181 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9182 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9183 Chain, Dest, CC, Cmp);
9184 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
9194 // Look pass the truncate.
9195 if (Cond.getOpcode() == ISD::TRUNCATE)
9196 Cond = Cond.getOperand(0);
9198 // We know the result of AND is compared against zero. Try to match
9200 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
9201 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
9202 if (NewSetCC.getNode()) {
9203 CC = NewSetCC.getOperand(0);
9204 Cond = NewSetCC.getOperand(1);
9211 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9212 Cond = EmitTest(Cond, X86::COND_NE, DAG);
9214 Cond = ConvertCmpIfNecessary(Cond, DAG);
9215 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9216 Chain, Dest, CC, Cond);
9220 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
9221 // Calls to _alloca is needed to probe the stack when allocating more than 4k
9222 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
9223 // that the guard pages used by the OS virtual memory manager are allocated in
9224 // correct sequence.
9226 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
9227 SelectionDAG &DAG) const {
9228 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
9229 getTargetMachine().Options.EnableSegmentedStacks) &&
9230 "This should be used only on Windows targets or when segmented stacks "
9232 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
9233 DebugLoc dl = Op.getDebugLoc();
9236 SDValue Chain = Op.getOperand(0);
9237 SDValue Size = Op.getOperand(1);
9238 // FIXME: Ensure alignment here
9240 bool Is64Bit = Subtarget->is64Bit();
9241 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
9243 if (getTargetMachine().Options.EnableSegmentedStacks) {
9244 MachineFunction &MF = DAG.getMachineFunction();
9245 MachineRegisterInfo &MRI = MF.getRegInfo();
9248 // The 64 bit implementation of segmented stacks needs to clobber both r10
9249 // r11. This makes it impossible to use it along with nested parameters.
9250 const Function *F = MF.getFunction();
9252 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
9254 if (I->hasNestAttr())
9255 report_fatal_error("Cannot use segmented stacks with functions that "
9256 "have nested arguments.");
9259 const TargetRegisterClass *AddrRegClass =
9260 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
9261 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
9262 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
9263 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
9264 DAG.getRegister(Vreg, SPTy));
9265 SDValue Ops1[2] = { Value, Chain };
9266 return DAG.getMergeValues(Ops1, 2, dl);
9269 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
9271 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
9272 Flag = Chain.getValue(1);
9273 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
9275 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
9276 Flag = Chain.getValue(1);
9278 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
9280 SDValue Ops1[2] = { Chain.getValue(0), Chain };
9281 return DAG.getMergeValues(Ops1, 2, dl);
9285 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
9286 MachineFunction &MF = DAG.getMachineFunction();
9287 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
9289 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9290 DebugLoc DL = Op.getDebugLoc();
9292 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
9293 // vastart just stores the address of the VarArgsFrameIndex slot into the
9294 // memory location argument.
9295 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9297 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
9298 MachinePointerInfo(SV), false, false, 0);
9302 // gp_offset (0 - 6 * 8)
9303 // fp_offset (48 - 48 + 8 * 16)
9304 // overflow_arg_area (point to parameters coming in memory).
9306 SmallVector<SDValue, 8> MemOps;
9307 SDValue FIN = Op.getOperand(1);
9309 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
9310 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
9312 FIN, MachinePointerInfo(SV), false, false, 0);
9313 MemOps.push_back(Store);
9316 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9317 FIN, DAG.getIntPtrConstant(4));
9318 Store = DAG.getStore(Op.getOperand(0), DL,
9319 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
9321 FIN, MachinePointerInfo(SV, 4), false, false, 0);
9322 MemOps.push_back(Store);
9324 // Store ptr to overflow_arg_area
9325 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9326 FIN, DAG.getIntPtrConstant(4));
9327 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9329 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
9330 MachinePointerInfo(SV, 8),
9332 MemOps.push_back(Store);
9334 // Store ptr to reg_save_area.
9335 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9336 FIN, DAG.getIntPtrConstant(8));
9337 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
9339 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
9340 MachinePointerInfo(SV, 16), false, false, 0);
9341 MemOps.push_back(Store);
9342 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9343 &MemOps[0], MemOps.size());
9346 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9347 assert(Subtarget->is64Bit() &&
9348 "LowerVAARG only handles 64-bit va_arg!");
9349 assert((Subtarget->isTargetLinux() ||
9350 Subtarget->isTargetDarwin()) &&
9351 "Unhandled target in LowerVAARG");
9352 assert(Op.getNode()->getNumOperands() == 4);
9353 SDValue Chain = Op.getOperand(0);
9354 SDValue SrcPtr = Op.getOperand(1);
9355 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9356 unsigned Align = Op.getConstantOperandVal(3);
9357 DebugLoc dl = Op.getDebugLoc();
9359 EVT ArgVT = Op.getNode()->getValueType(0);
9360 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9361 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
9364 // Decide which area this value should be read from.
9365 // TODO: Implement the AMD64 ABI in its entirety. This simple
9366 // selection mechanism works only for the basic types.
9367 if (ArgVT == MVT::f80) {
9368 llvm_unreachable("va_arg for f80 not yet implemented");
9369 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9370 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9371 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9372 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9374 llvm_unreachable("Unhandled argument type in LowerVAARG");
9378 // Sanity Check: Make sure using fp_offset makes sense.
9379 assert(!getTargetMachine().Options.UseSoftFloat &&
9380 !(DAG.getMachineFunction()
9381 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9382 Subtarget->hasSSE1());
9385 // Insert VAARG_64 node into the DAG
9386 // VAARG_64 returns two values: Variable Argument Address, Chain
9387 SmallVector<SDValue, 11> InstOps;
9388 InstOps.push_back(Chain);
9389 InstOps.push_back(SrcPtr);
9390 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9391 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9392 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9393 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9394 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9395 VTs, &InstOps[0], InstOps.size(),
9397 MachinePointerInfo(SV),
9402 Chain = VAARG.getValue(1);
9404 // Load the next argument and return it
9405 return DAG.getLoad(ArgVT, dl,
9408 MachinePointerInfo(),
9409 false, false, false, 0);
9412 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9413 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9414 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9415 SDValue Chain = Op.getOperand(0);
9416 SDValue DstPtr = Op.getOperand(1);
9417 SDValue SrcPtr = Op.getOperand(2);
9418 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9419 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9420 DebugLoc DL = Op.getDebugLoc();
9422 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9423 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9425 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9428 // getTargetVShiftNOde - Handle vector element shifts where the shift amount
9429 // may or may not be a constant. Takes immediate version of shift as input.
9430 static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
9431 SDValue SrcOp, SDValue ShAmt,
9432 SelectionDAG &DAG) {
9433 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
9435 if (isa<ConstantSDNode>(ShAmt)) {
9437 default: llvm_unreachable("Unknown target vector shift node");
9441 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9445 // Change opcode to non-immediate version
9447 default: llvm_unreachable("Unknown target vector shift node");
9448 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
9449 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
9450 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
9453 // Need to build a vector containing shift amount
9454 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
9457 ShOps[1] = DAG.getConstant(0, MVT::i32);
9458 ShOps[2] = DAG.getUNDEF(MVT::i32);
9459 ShOps[3] = DAG.getUNDEF(MVT::i32);
9460 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
9462 // The return type has to be a 128-bit type with the same element
9463 // type as the input type.
9464 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9465 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
9467 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
9468 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9472 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9473 DebugLoc dl = Op.getDebugLoc();
9474 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9476 default: return SDValue(); // Don't custom lower most intrinsics.
9477 // Comparison intrinsics.
9478 case Intrinsic::x86_sse_comieq_ss:
9479 case Intrinsic::x86_sse_comilt_ss:
9480 case Intrinsic::x86_sse_comile_ss:
9481 case Intrinsic::x86_sse_comigt_ss:
9482 case Intrinsic::x86_sse_comige_ss:
9483 case Intrinsic::x86_sse_comineq_ss:
9484 case Intrinsic::x86_sse_ucomieq_ss:
9485 case Intrinsic::x86_sse_ucomilt_ss:
9486 case Intrinsic::x86_sse_ucomile_ss:
9487 case Intrinsic::x86_sse_ucomigt_ss:
9488 case Intrinsic::x86_sse_ucomige_ss:
9489 case Intrinsic::x86_sse_ucomineq_ss:
9490 case Intrinsic::x86_sse2_comieq_sd:
9491 case Intrinsic::x86_sse2_comilt_sd:
9492 case Intrinsic::x86_sse2_comile_sd:
9493 case Intrinsic::x86_sse2_comigt_sd:
9494 case Intrinsic::x86_sse2_comige_sd:
9495 case Intrinsic::x86_sse2_comineq_sd:
9496 case Intrinsic::x86_sse2_ucomieq_sd:
9497 case Intrinsic::x86_sse2_ucomilt_sd:
9498 case Intrinsic::x86_sse2_ucomile_sd:
9499 case Intrinsic::x86_sse2_ucomigt_sd:
9500 case Intrinsic::x86_sse2_ucomige_sd:
9501 case Intrinsic::x86_sse2_ucomineq_sd: {
9503 ISD::CondCode CC = ISD::SETCC_INVALID;
9505 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9506 case Intrinsic::x86_sse_comieq_ss:
9507 case Intrinsic::x86_sse2_comieq_sd:
9511 case Intrinsic::x86_sse_comilt_ss:
9512 case Intrinsic::x86_sse2_comilt_sd:
9516 case Intrinsic::x86_sse_comile_ss:
9517 case Intrinsic::x86_sse2_comile_sd:
9521 case Intrinsic::x86_sse_comigt_ss:
9522 case Intrinsic::x86_sse2_comigt_sd:
9526 case Intrinsic::x86_sse_comige_ss:
9527 case Intrinsic::x86_sse2_comige_sd:
9531 case Intrinsic::x86_sse_comineq_ss:
9532 case Intrinsic::x86_sse2_comineq_sd:
9536 case Intrinsic::x86_sse_ucomieq_ss:
9537 case Intrinsic::x86_sse2_ucomieq_sd:
9538 Opc = X86ISD::UCOMI;
9541 case Intrinsic::x86_sse_ucomilt_ss:
9542 case Intrinsic::x86_sse2_ucomilt_sd:
9543 Opc = X86ISD::UCOMI;
9546 case Intrinsic::x86_sse_ucomile_ss:
9547 case Intrinsic::x86_sse2_ucomile_sd:
9548 Opc = X86ISD::UCOMI;
9551 case Intrinsic::x86_sse_ucomigt_ss:
9552 case Intrinsic::x86_sse2_ucomigt_sd:
9553 Opc = X86ISD::UCOMI;
9556 case Intrinsic::x86_sse_ucomige_ss:
9557 case Intrinsic::x86_sse2_ucomige_sd:
9558 Opc = X86ISD::UCOMI;
9561 case Intrinsic::x86_sse_ucomineq_ss:
9562 case Intrinsic::x86_sse2_ucomineq_sd:
9563 Opc = X86ISD::UCOMI;
9568 SDValue LHS = Op.getOperand(1);
9569 SDValue RHS = Op.getOperand(2);
9570 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9571 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9572 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9573 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9574 DAG.getConstant(X86CC, MVT::i8), Cond);
9575 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9577 // Arithmetic intrinsics.
9578 case Intrinsic::x86_sse2_pmulu_dq:
9579 case Intrinsic::x86_avx2_pmulu_dq:
9580 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
9581 Op.getOperand(1), Op.getOperand(2));
9582 case Intrinsic::x86_sse3_hadd_ps:
9583 case Intrinsic::x86_sse3_hadd_pd:
9584 case Intrinsic::x86_avx_hadd_ps_256:
9585 case Intrinsic::x86_avx_hadd_pd_256:
9586 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(),
9587 Op.getOperand(1), Op.getOperand(2));
9588 case Intrinsic::x86_sse3_hsub_ps:
9589 case Intrinsic::x86_sse3_hsub_pd:
9590 case Intrinsic::x86_avx_hsub_ps_256:
9591 case Intrinsic::x86_avx_hsub_pd_256:
9592 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(),
9593 Op.getOperand(1), Op.getOperand(2));
9594 case Intrinsic::x86_ssse3_phadd_w_128:
9595 case Intrinsic::x86_ssse3_phadd_d_128:
9596 case Intrinsic::x86_avx2_phadd_w:
9597 case Intrinsic::x86_avx2_phadd_d:
9598 return DAG.getNode(X86ISD::HADD, dl, Op.getValueType(),
9599 Op.getOperand(1), Op.getOperand(2));
9600 case Intrinsic::x86_ssse3_phsub_w_128:
9601 case Intrinsic::x86_ssse3_phsub_d_128:
9602 case Intrinsic::x86_avx2_phsub_w:
9603 case Intrinsic::x86_avx2_phsub_d:
9604 return DAG.getNode(X86ISD::HSUB, dl, Op.getValueType(),
9605 Op.getOperand(1), Op.getOperand(2));
9606 case Intrinsic::x86_avx2_psllv_d:
9607 case Intrinsic::x86_avx2_psllv_q:
9608 case Intrinsic::x86_avx2_psllv_d_256:
9609 case Intrinsic::x86_avx2_psllv_q_256:
9610 return DAG.getNode(ISD::SHL, dl, Op.getValueType(),
9611 Op.getOperand(1), Op.getOperand(2));
9612 case Intrinsic::x86_avx2_psrlv_d:
9613 case Intrinsic::x86_avx2_psrlv_q:
9614 case Intrinsic::x86_avx2_psrlv_d_256:
9615 case Intrinsic::x86_avx2_psrlv_q_256:
9616 return DAG.getNode(ISD::SRL, dl, Op.getValueType(),
9617 Op.getOperand(1), Op.getOperand(2));
9618 case Intrinsic::x86_avx2_psrav_d:
9619 case Intrinsic::x86_avx2_psrav_d_256:
9620 return DAG.getNode(ISD::SRA, dl, Op.getValueType(),
9621 Op.getOperand(1), Op.getOperand(2));
9622 case Intrinsic::x86_ssse3_pshuf_b_128:
9623 case Intrinsic::x86_avx2_pshuf_b:
9624 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
9625 Op.getOperand(1), Op.getOperand(2));
9626 case Intrinsic::x86_ssse3_psign_b_128:
9627 case Intrinsic::x86_ssse3_psign_w_128:
9628 case Intrinsic::x86_ssse3_psign_d_128:
9629 case Intrinsic::x86_avx2_psign_b:
9630 case Intrinsic::x86_avx2_psign_w:
9631 case Intrinsic::x86_avx2_psign_d:
9632 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
9633 Op.getOperand(1), Op.getOperand(2));
9634 case Intrinsic::x86_sse41_insertps:
9635 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
9636 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9637 case Intrinsic::x86_avx_vperm2f128_ps_256:
9638 case Intrinsic::x86_avx_vperm2f128_pd_256:
9639 case Intrinsic::x86_avx_vperm2f128_si_256:
9640 case Intrinsic::x86_avx2_vperm2i128:
9641 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
9642 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9643 case Intrinsic::x86_avx2_permd:
9644 case Intrinsic::x86_avx2_permps:
9645 // Operands intentionally swapped. Mask is last operand to intrinsic,
9646 // but second operand for node/intruction.
9647 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
9648 Op.getOperand(2), Op.getOperand(1));
9650 // ptest and testp intrinsics. The intrinsic these come from are designed to
9651 // return an integer value, not just an instruction so lower it to the ptest
9652 // or testp pattern and a setcc for the result.
9653 case Intrinsic::x86_sse41_ptestz:
9654 case Intrinsic::x86_sse41_ptestc:
9655 case Intrinsic::x86_sse41_ptestnzc:
9656 case Intrinsic::x86_avx_ptestz_256:
9657 case Intrinsic::x86_avx_ptestc_256:
9658 case Intrinsic::x86_avx_ptestnzc_256:
9659 case Intrinsic::x86_avx_vtestz_ps:
9660 case Intrinsic::x86_avx_vtestc_ps:
9661 case Intrinsic::x86_avx_vtestnzc_ps:
9662 case Intrinsic::x86_avx_vtestz_pd:
9663 case Intrinsic::x86_avx_vtestc_pd:
9664 case Intrinsic::x86_avx_vtestnzc_pd:
9665 case Intrinsic::x86_avx_vtestz_ps_256:
9666 case Intrinsic::x86_avx_vtestc_ps_256:
9667 case Intrinsic::x86_avx_vtestnzc_ps_256:
9668 case Intrinsic::x86_avx_vtestz_pd_256:
9669 case Intrinsic::x86_avx_vtestc_pd_256:
9670 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9671 bool IsTestPacked = false;
9674 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9675 case Intrinsic::x86_avx_vtestz_ps:
9676 case Intrinsic::x86_avx_vtestz_pd:
9677 case Intrinsic::x86_avx_vtestz_ps_256:
9678 case Intrinsic::x86_avx_vtestz_pd_256:
9679 IsTestPacked = true; // Fallthrough
9680 case Intrinsic::x86_sse41_ptestz:
9681 case Intrinsic::x86_avx_ptestz_256:
9683 X86CC = X86::COND_E;
9685 case Intrinsic::x86_avx_vtestc_ps:
9686 case Intrinsic::x86_avx_vtestc_pd:
9687 case Intrinsic::x86_avx_vtestc_ps_256:
9688 case Intrinsic::x86_avx_vtestc_pd_256:
9689 IsTestPacked = true; // Fallthrough
9690 case Intrinsic::x86_sse41_ptestc:
9691 case Intrinsic::x86_avx_ptestc_256:
9693 X86CC = X86::COND_B;
9695 case Intrinsic::x86_avx_vtestnzc_ps:
9696 case Intrinsic::x86_avx_vtestnzc_pd:
9697 case Intrinsic::x86_avx_vtestnzc_ps_256:
9698 case Intrinsic::x86_avx_vtestnzc_pd_256:
9699 IsTestPacked = true; // Fallthrough
9700 case Intrinsic::x86_sse41_ptestnzc:
9701 case Intrinsic::x86_avx_ptestnzc_256:
9703 X86CC = X86::COND_A;
9707 SDValue LHS = Op.getOperand(1);
9708 SDValue RHS = Op.getOperand(2);
9709 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9710 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9711 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9712 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9713 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9716 // SSE/AVX shift intrinsics
9717 case Intrinsic::x86_sse2_psll_w:
9718 case Intrinsic::x86_sse2_psll_d:
9719 case Intrinsic::x86_sse2_psll_q:
9720 case Intrinsic::x86_avx2_psll_w:
9721 case Intrinsic::x86_avx2_psll_d:
9722 case Intrinsic::x86_avx2_psll_q:
9723 return DAG.getNode(X86ISD::VSHL, dl, Op.getValueType(),
9724 Op.getOperand(1), Op.getOperand(2));
9725 case Intrinsic::x86_sse2_psrl_w:
9726 case Intrinsic::x86_sse2_psrl_d:
9727 case Intrinsic::x86_sse2_psrl_q:
9728 case Intrinsic::x86_avx2_psrl_w:
9729 case Intrinsic::x86_avx2_psrl_d:
9730 case Intrinsic::x86_avx2_psrl_q:
9731 return DAG.getNode(X86ISD::VSRL, dl, Op.getValueType(),
9732 Op.getOperand(1), Op.getOperand(2));
9733 case Intrinsic::x86_sse2_psra_w:
9734 case Intrinsic::x86_sse2_psra_d:
9735 case Intrinsic::x86_avx2_psra_w:
9736 case Intrinsic::x86_avx2_psra_d:
9737 return DAG.getNode(X86ISD::VSRA, dl, Op.getValueType(),
9738 Op.getOperand(1), Op.getOperand(2));
9739 case Intrinsic::x86_sse2_pslli_w:
9740 case Intrinsic::x86_sse2_pslli_d:
9741 case Intrinsic::x86_sse2_pslli_q:
9742 case Intrinsic::x86_avx2_pslli_w:
9743 case Intrinsic::x86_avx2_pslli_d:
9744 case Intrinsic::x86_avx2_pslli_q:
9745 return getTargetVShiftNode(X86ISD::VSHLI, dl, Op.getValueType(),
9746 Op.getOperand(1), Op.getOperand(2), DAG);
9747 case Intrinsic::x86_sse2_psrli_w:
9748 case Intrinsic::x86_sse2_psrli_d:
9749 case Intrinsic::x86_sse2_psrli_q:
9750 case Intrinsic::x86_avx2_psrli_w:
9751 case Intrinsic::x86_avx2_psrli_d:
9752 case Intrinsic::x86_avx2_psrli_q:
9753 return getTargetVShiftNode(X86ISD::VSRLI, dl, Op.getValueType(),
9754 Op.getOperand(1), Op.getOperand(2), DAG);
9755 case Intrinsic::x86_sse2_psrai_w:
9756 case Intrinsic::x86_sse2_psrai_d:
9757 case Intrinsic::x86_avx2_psrai_w:
9758 case Intrinsic::x86_avx2_psrai_d:
9759 return getTargetVShiftNode(X86ISD::VSRAI, dl, Op.getValueType(),
9760 Op.getOperand(1), Op.getOperand(2), DAG);
9761 // Fix vector shift instructions where the last operand is a non-immediate
9763 case Intrinsic::x86_mmx_pslli_w:
9764 case Intrinsic::x86_mmx_pslli_d:
9765 case Intrinsic::x86_mmx_pslli_q:
9766 case Intrinsic::x86_mmx_psrli_w:
9767 case Intrinsic::x86_mmx_psrli_d:
9768 case Intrinsic::x86_mmx_psrli_q:
9769 case Intrinsic::x86_mmx_psrai_w:
9770 case Intrinsic::x86_mmx_psrai_d: {
9771 SDValue ShAmt = Op.getOperand(2);
9772 if (isa<ConstantSDNode>(ShAmt))
9775 unsigned NewIntNo = 0;
9777 case Intrinsic::x86_mmx_pslli_w:
9778 NewIntNo = Intrinsic::x86_mmx_psll_w;
9780 case Intrinsic::x86_mmx_pslli_d:
9781 NewIntNo = Intrinsic::x86_mmx_psll_d;
9783 case Intrinsic::x86_mmx_pslli_q:
9784 NewIntNo = Intrinsic::x86_mmx_psll_q;
9786 case Intrinsic::x86_mmx_psrli_w:
9787 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9789 case Intrinsic::x86_mmx_psrli_d:
9790 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9792 case Intrinsic::x86_mmx_psrli_q:
9793 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9795 case Intrinsic::x86_mmx_psrai_w:
9796 NewIntNo = Intrinsic::x86_mmx_psra_w;
9798 case Intrinsic::x86_mmx_psrai_d:
9799 NewIntNo = Intrinsic::x86_mmx_psra_d;
9801 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9804 // The vector shift intrinsics with scalars uses 32b shift amounts but
9805 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9807 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt,
9808 DAG.getConstant(0, MVT::i32));
9809 // FIXME this must be lowered to get rid of the invalid type.
9811 EVT VT = Op.getValueType();
9812 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9813 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9814 DAG.getConstant(NewIntNo, MVT::i32),
9815 Op.getOperand(1), ShAmt);
9821 X86TargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9822 DebugLoc dl = Op.getDebugLoc();
9823 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
9825 default: return SDValue(); // Don't custom lower most intrinsics.
9827 // RDRAND intrinsics.
9828 case Intrinsic::x86_rdrand_16:
9829 case Intrinsic::x86_rdrand_32:
9830 case Intrinsic::x86_rdrand_64: {
9831 // Emit the node with the right value type.
9832 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
9833 SDValue Result = DAG.getNode(X86ISD::RDRAND, dl, VTs, Op.getOperand(0));
9835 // If the value returned by RDRAND was valid (CF=1), return 1. Otherwise
9836 // return the value from Rand, which is always 0, casted to i32.
9837 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
9838 DAG.getConstant(1, Op->getValueType(1)),
9839 DAG.getConstant(X86::COND_B, MVT::i32),
9840 SDValue(Result.getNode(), 1) };
9841 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
9842 DAG.getVTList(Op->getValueType(1), MVT::Glue),
9845 // Return { result, isValid, chain }.
9846 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
9847 SDValue(Result.getNode(), 2));
9852 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9853 SelectionDAG &DAG) const {
9854 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9855 MFI->setReturnAddressIsTaken(true);
9857 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9858 DebugLoc dl = Op.getDebugLoc();
9861 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9863 DAG.getConstant(TD->getPointerSize(),
9864 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9865 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9866 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9868 MachinePointerInfo(), false, false, false, 0);
9871 // Just load the return address.
9872 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9873 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9874 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9877 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9878 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9879 MFI->setFrameAddressIsTaken(true);
9881 EVT VT = Op.getValueType();
9882 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9883 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9884 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9885 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9887 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9888 MachinePointerInfo(),
9889 false, false, false, 0);
9893 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9894 SelectionDAG &DAG) const {
9895 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9898 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9899 SDValue Chain = Op.getOperand(0);
9900 SDValue Offset = Op.getOperand(1);
9901 SDValue Handler = Op.getOperand(2);
9902 DebugLoc dl = Op.getDebugLoc();
9904 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9905 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9907 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9909 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9910 DAG.getIntPtrConstant(TD->getPointerSize()));
9911 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9912 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9914 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9916 return DAG.getNode(X86ISD::EH_RETURN, dl,
9918 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9921 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
9922 SelectionDAG &DAG) const {
9923 return Op.getOperand(0);
9926 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
9927 SelectionDAG &DAG) const {
9928 SDValue Root = Op.getOperand(0);
9929 SDValue Trmp = Op.getOperand(1); // trampoline
9930 SDValue FPtr = Op.getOperand(2); // nested function
9931 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9932 DebugLoc dl = Op.getDebugLoc();
9934 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9936 if (Subtarget->is64Bit()) {
9937 SDValue OutChains[6];
9939 // Large code-model.
9940 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9941 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9943 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9944 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9946 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9948 // Load the pointer to the nested function into R11.
9949 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9950 SDValue Addr = Trmp;
9951 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9952 Addr, MachinePointerInfo(TrmpAddr),
9955 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9956 DAG.getConstant(2, MVT::i64));
9957 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9958 MachinePointerInfo(TrmpAddr, 2),
9961 // Load the 'nest' parameter value into R10.
9962 // R10 is specified in X86CallingConv.td
9963 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9964 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9965 DAG.getConstant(10, MVT::i64));
9966 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9967 Addr, MachinePointerInfo(TrmpAddr, 10),
9970 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9971 DAG.getConstant(12, MVT::i64));
9972 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9973 MachinePointerInfo(TrmpAddr, 12),
9976 // Jump to the nested function.
9977 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9978 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9979 DAG.getConstant(20, MVT::i64));
9980 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9981 Addr, MachinePointerInfo(TrmpAddr, 20),
9984 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9985 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9986 DAG.getConstant(22, MVT::i64));
9987 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9988 MachinePointerInfo(TrmpAddr, 22),
9991 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
9993 const Function *Func =
9994 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
9995 CallingConv::ID CC = Func->getCallingConv();
10000 llvm_unreachable("Unsupported calling convention");
10001 case CallingConv::C:
10002 case CallingConv::X86_StdCall: {
10003 // Pass 'nest' parameter in ECX.
10004 // Must be kept in sync with X86CallingConv.td
10005 NestReg = X86::ECX;
10007 // Check that ECX wasn't needed by an 'inreg' parameter.
10008 FunctionType *FTy = Func->getFunctionType();
10009 const AttrListPtr &Attrs = Func->getAttributes();
10011 if (!Attrs.isEmpty() && !Func->isVarArg()) {
10012 unsigned InRegCount = 0;
10015 for (FunctionType::param_iterator I = FTy->param_begin(),
10016 E = FTy->param_end(); I != E; ++I, ++Idx)
10017 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
10018 // FIXME: should only count parameters that are lowered to integers.
10019 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
10021 if (InRegCount > 2) {
10022 report_fatal_error("Nest register in use - reduce number of inreg"
10028 case CallingConv::X86_FastCall:
10029 case CallingConv::X86_ThisCall:
10030 case CallingConv::Fast:
10031 // Pass 'nest' parameter in EAX.
10032 // Must be kept in sync with X86CallingConv.td
10033 NestReg = X86::EAX;
10037 SDValue OutChains[4];
10038 SDValue Addr, Disp;
10040 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10041 DAG.getConstant(10, MVT::i32));
10042 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
10044 // This is storing the opcode for MOV32ri.
10045 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
10046 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
10047 OutChains[0] = DAG.getStore(Root, dl,
10048 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
10049 Trmp, MachinePointerInfo(TrmpAddr),
10052 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10053 DAG.getConstant(1, MVT::i32));
10054 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
10055 MachinePointerInfo(TrmpAddr, 1),
10058 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
10059 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10060 DAG.getConstant(5, MVT::i32));
10061 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
10062 MachinePointerInfo(TrmpAddr, 5),
10065 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
10066 DAG.getConstant(6, MVT::i32));
10067 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
10068 MachinePointerInfo(TrmpAddr, 6),
10071 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
10075 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
10076 SelectionDAG &DAG) const {
10078 The rounding mode is in bits 11:10 of FPSR, and has the following
10080 00 Round to nearest
10085 FLT_ROUNDS, on the other hand, expects the following:
10092 To perform the conversion, we do:
10093 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
10096 MachineFunction &MF = DAG.getMachineFunction();
10097 const TargetMachine &TM = MF.getTarget();
10098 const TargetFrameLowering &TFI = *TM.getFrameLowering();
10099 unsigned StackAlignment = TFI.getStackAlignment();
10100 EVT VT = Op.getValueType();
10101 DebugLoc DL = Op.getDebugLoc();
10103 // Save FP Control Word to stack slot
10104 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
10105 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
10108 MachineMemOperand *MMO =
10109 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10110 MachineMemOperand::MOStore, 2, 2);
10112 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
10113 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
10114 DAG.getVTList(MVT::Other),
10115 Ops, 2, MVT::i16, MMO);
10117 // Load FP Control Word from stack slot
10118 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
10119 MachinePointerInfo(), false, false, false, 0);
10121 // Transform as necessary
10123 DAG.getNode(ISD::SRL, DL, MVT::i16,
10124 DAG.getNode(ISD::AND, DL, MVT::i16,
10125 CWD, DAG.getConstant(0x800, MVT::i16)),
10126 DAG.getConstant(11, MVT::i8));
10128 DAG.getNode(ISD::SRL, DL, MVT::i16,
10129 DAG.getNode(ISD::AND, DL, MVT::i16,
10130 CWD, DAG.getConstant(0x400, MVT::i16)),
10131 DAG.getConstant(9, MVT::i8));
10134 DAG.getNode(ISD::AND, DL, MVT::i16,
10135 DAG.getNode(ISD::ADD, DL, MVT::i16,
10136 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
10137 DAG.getConstant(1, MVT::i16)),
10138 DAG.getConstant(3, MVT::i16));
10141 return DAG.getNode((VT.getSizeInBits() < 16 ?
10142 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
10145 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
10146 EVT VT = Op.getValueType();
10148 unsigned NumBits = VT.getSizeInBits();
10149 DebugLoc dl = Op.getDebugLoc();
10151 Op = Op.getOperand(0);
10152 if (VT == MVT::i8) {
10153 // Zero extend to i32 since there is not an i8 bsr.
10155 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10158 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
10159 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10160 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10162 // If src is zero (i.e. bsr sets ZF), returns NumBits.
10165 DAG.getConstant(NumBits+NumBits-1, OpVT),
10166 DAG.getConstant(X86::COND_E, MVT::i8),
10169 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
10171 // Finally xor with NumBits-1.
10172 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10175 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10179 SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op,
10180 SelectionDAG &DAG) const {
10181 EVT VT = Op.getValueType();
10183 unsigned NumBits = VT.getSizeInBits();
10184 DebugLoc dl = Op.getDebugLoc();
10186 Op = Op.getOperand(0);
10187 if (VT == MVT::i8) {
10188 // Zero extend to i32 since there is not an i8 bsr.
10190 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10193 // Issue a bsr (scan bits in reverse).
10194 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10195 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10197 // And xor with NumBits-1.
10198 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10201 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10205 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
10206 EVT VT = Op.getValueType();
10207 unsigned NumBits = VT.getSizeInBits();
10208 DebugLoc dl = Op.getDebugLoc();
10209 Op = Op.getOperand(0);
10211 // Issue a bsf (scan bits forward) which also sets EFLAGS.
10212 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10213 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
10215 // If src is zero (i.e. bsf sets ZF), returns NumBits.
10218 DAG.getConstant(NumBits, VT),
10219 DAG.getConstant(X86::COND_E, MVT::i8),
10222 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
10225 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
10226 // ones, and then concatenate the result back.
10227 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
10228 EVT VT = Op.getValueType();
10230 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
10231 "Unsupported value type for operation");
10233 unsigned NumElems = VT.getVectorNumElements();
10234 DebugLoc dl = Op.getDebugLoc();
10236 // Extract the LHS vectors
10237 SDValue LHS = Op.getOperand(0);
10238 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
10239 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
10241 // Extract the RHS vectors
10242 SDValue RHS = Op.getOperand(1);
10243 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
10244 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
10246 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10247 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10249 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
10250 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
10251 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
10254 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
10255 assert(Op.getValueType().getSizeInBits() == 256 &&
10256 Op.getValueType().isInteger() &&
10257 "Only handle AVX 256-bit vector integer operation");
10258 return Lower256IntArith(Op, DAG);
10261 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
10262 assert(Op.getValueType().getSizeInBits() == 256 &&
10263 Op.getValueType().isInteger() &&
10264 "Only handle AVX 256-bit vector integer operation");
10265 return Lower256IntArith(Op, DAG);
10268 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
10269 EVT VT = Op.getValueType();
10271 // Decompose 256-bit ops into smaller 128-bit ops.
10272 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
10273 return Lower256IntArith(Op, DAG);
10275 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
10276 "Only know how to lower V2I64/V4I64 multiply");
10278 DebugLoc dl = Op.getDebugLoc();
10280 // Ahi = psrlqi(a, 32);
10281 // Bhi = psrlqi(b, 32);
10283 // AloBlo = pmuludq(a, b);
10284 // AloBhi = pmuludq(a, Bhi);
10285 // AhiBlo = pmuludq(Ahi, b);
10287 // AloBhi = psllqi(AloBhi, 32);
10288 // AhiBlo = psllqi(AhiBlo, 32);
10289 // return AloBlo + AloBhi + AhiBlo;
10291 SDValue A = Op.getOperand(0);
10292 SDValue B = Op.getOperand(1);
10294 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
10296 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
10297 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
10299 // Bit cast to 32-bit vectors for MULUDQ
10300 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
10301 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
10302 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
10303 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
10304 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
10306 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
10307 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
10308 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
10310 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
10311 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
10313 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
10314 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
10317 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
10319 EVT VT = Op.getValueType();
10320 DebugLoc dl = Op.getDebugLoc();
10321 SDValue R = Op.getOperand(0);
10322 SDValue Amt = Op.getOperand(1);
10323 LLVMContext *Context = DAG.getContext();
10325 if (!Subtarget->hasSSE2())
10328 // Optimize shl/srl/sra with constant shift amount.
10329 if (isSplatVector(Amt.getNode())) {
10330 SDValue SclrAmt = Amt->getOperand(0);
10331 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
10332 uint64_t ShiftAmt = C->getZExtValue();
10334 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
10335 (Subtarget->hasAVX2() &&
10336 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
10337 if (Op.getOpcode() == ISD::SHL)
10338 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
10339 DAG.getConstant(ShiftAmt, MVT::i32));
10340 if (Op.getOpcode() == ISD::SRL)
10341 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
10342 DAG.getConstant(ShiftAmt, MVT::i32));
10343 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
10344 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
10345 DAG.getConstant(ShiftAmt, MVT::i32));
10348 if (VT == MVT::v16i8) {
10349 if (Op.getOpcode() == ISD::SHL) {
10350 // Make a large shift.
10351 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
10352 DAG.getConstant(ShiftAmt, MVT::i32));
10353 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10354 // Zero out the rightmost bits.
10355 SmallVector<SDValue, 16> V(16,
10356 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10358 return DAG.getNode(ISD::AND, dl, VT, SHL,
10359 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10361 if (Op.getOpcode() == ISD::SRL) {
10362 // Make a large shift.
10363 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
10364 DAG.getConstant(ShiftAmt, MVT::i32));
10365 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10366 // Zero out the leftmost bits.
10367 SmallVector<SDValue, 16> V(16,
10368 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10370 return DAG.getNode(ISD::AND, dl, VT, SRL,
10371 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10373 if (Op.getOpcode() == ISD::SRA) {
10374 if (ShiftAmt == 7) {
10375 // R s>> 7 === R s< 0
10376 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10377 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10380 // R s>> a === ((R u>> a) ^ m) - m
10381 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10382 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
10384 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
10385 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10386 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10389 llvm_unreachable("Unknown shift opcode.");
10392 if (Subtarget->hasAVX2() && VT == MVT::v32i8) {
10393 if (Op.getOpcode() == ISD::SHL) {
10394 // Make a large shift.
10395 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
10396 DAG.getConstant(ShiftAmt, MVT::i32));
10397 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10398 // Zero out the rightmost bits.
10399 SmallVector<SDValue, 32> V(32,
10400 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10402 return DAG.getNode(ISD::AND, dl, VT, SHL,
10403 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10405 if (Op.getOpcode() == ISD::SRL) {
10406 // Make a large shift.
10407 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
10408 DAG.getConstant(ShiftAmt, MVT::i32));
10409 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10410 // Zero out the leftmost bits.
10411 SmallVector<SDValue, 32> V(32,
10412 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10414 return DAG.getNode(ISD::AND, dl, VT, SRL,
10415 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10417 if (Op.getOpcode() == ISD::SRA) {
10418 if (ShiftAmt == 7) {
10419 // R s>> 7 === R s< 0
10420 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10421 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10424 // R s>> a === ((R u>> a) ^ m) - m
10425 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10426 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
10428 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
10429 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10430 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10433 llvm_unreachable("Unknown shift opcode.");
10438 // Lower SHL with variable shift amount.
10439 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
10440 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1),
10441 DAG.getConstant(23, MVT::i32));
10443 const uint32_t CV[] = { 0x3f800000U, 0x3f800000U, 0x3f800000U, 0x3f800000U};
10444 Constant *C = ConstantDataVector::get(*Context, CV);
10445 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
10446 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
10447 MachinePointerInfo::getConstantPool(),
10448 false, false, false, 16);
10450 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
10451 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
10452 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
10453 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
10455 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
10456 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
10459 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1),
10460 DAG.getConstant(5, MVT::i32));
10461 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
10463 // Turn 'a' into a mask suitable for VSELECT
10464 SDValue VSelM = DAG.getConstant(0x80, VT);
10465 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10466 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10468 SDValue CM1 = DAG.getConstant(0x0f, VT);
10469 SDValue CM2 = DAG.getConstant(0x3f, VT);
10471 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
10472 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
10473 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10474 DAG.getConstant(4, MVT::i32), DAG);
10475 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10476 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10479 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10480 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10481 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10483 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
10484 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
10485 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10486 DAG.getConstant(2, MVT::i32), DAG);
10487 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10488 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10491 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10492 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10493 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10495 // return VSELECT(r, r+r, a);
10496 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
10497 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
10501 // Decompose 256-bit shifts into smaller 128-bit shifts.
10502 if (VT.getSizeInBits() == 256) {
10503 unsigned NumElems = VT.getVectorNumElements();
10504 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10505 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10507 // Extract the two vectors
10508 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
10509 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
10511 // Recreate the shift amount vectors
10512 SDValue Amt1, Amt2;
10513 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
10514 // Constant shift amount
10515 SmallVector<SDValue, 4> Amt1Csts;
10516 SmallVector<SDValue, 4> Amt2Csts;
10517 for (unsigned i = 0; i != NumElems/2; ++i)
10518 Amt1Csts.push_back(Amt->getOperand(i));
10519 for (unsigned i = NumElems/2; i != NumElems; ++i)
10520 Amt2Csts.push_back(Amt->getOperand(i));
10522 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10523 &Amt1Csts[0], NumElems/2);
10524 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10525 &Amt2Csts[0], NumElems/2);
10527 // Variable shift amount
10528 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
10529 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
10532 // Issue new vector shifts for the smaller types
10533 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
10534 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
10536 // Concatenate the result back
10537 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
10543 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
10544 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10545 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10546 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10547 // has only one use.
10548 SDNode *N = Op.getNode();
10549 SDValue LHS = N->getOperand(0);
10550 SDValue RHS = N->getOperand(1);
10551 unsigned BaseOp = 0;
10553 DebugLoc DL = Op.getDebugLoc();
10554 switch (Op.getOpcode()) {
10555 default: llvm_unreachable("Unknown ovf instruction!");
10557 // A subtract of one will be selected as a INC. Note that INC doesn't
10558 // set CF, so we can't do this for UADDO.
10559 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10561 BaseOp = X86ISD::INC;
10562 Cond = X86::COND_O;
10565 BaseOp = X86ISD::ADD;
10566 Cond = X86::COND_O;
10569 BaseOp = X86ISD::ADD;
10570 Cond = X86::COND_B;
10573 // A subtract of one will be selected as a DEC. Note that DEC doesn't
10574 // set CF, so we can't do this for USUBO.
10575 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10577 BaseOp = X86ISD::DEC;
10578 Cond = X86::COND_O;
10581 BaseOp = X86ISD::SUB;
10582 Cond = X86::COND_O;
10585 BaseOp = X86ISD::SUB;
10586 Cond = X86::COND_B;
10589 BaseOp = X86ISD::SMUL;
10590 Cond = X86::COND_O;
10592 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10593 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10595 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10598 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10599 DAG.getConstant(X86::COND_O, MVT::i32),
10600 SDValue(Sum.getNode(), 2));
10602 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10606 // Also sets EFLAGS.
10607 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10608 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10611 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10612 DAG.getConstant(Cond, MVT::i32),
10613 SDValue(Sum.getNode(), 1));
10615 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10618 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
10619 SelectionDAG &DAG) const {
10620 DebugLoc dl = Op.getDebugLoc();
10621 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
10622 EVT VT = Op.getValueType();
10624 if (!Subtarget->hasSSE2() || !VT.isVector())
10627 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10628 ExtraVT.getScalarType().getSizeInBits();
10629 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10631 switch (VT.getSimpleVT().SimpleTy) {
10632 default: return SDValue();
10635 if (!Subtarget->hasAVX())
10637 if (!Subtarget->hasAVX2()) {
10638 // needs to be split
10639 unsigned NumElems = VT.getVectorNumElements();
10641 // Extract the LHS vectors
10642 SDValue LHS = Op.getOperand(0);
10643 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
10644 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
10646 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10647 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10649 EVT ExtraEltVT = ExtraVT.getVectorElementType();
10650 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
10651 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
10653 SDValue Extra = DAG.getValueType(ExtraVT);
10655 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
10656 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
10658 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);;
10663 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT,
10664 Op.getOperand(0), ShAmt, DAG);
10665 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
10671 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10672 DebugLoc dl = Op.getDebugLoc();
10674 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10675 // There isn't any reason to disable it if the target processor supports it.
10676 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
10677 SDValue Chain = Op.getOperand(0);
10678 SDValue Zero = DAG.getConstant(0, MVT::i32);
10680 DAG.getRegister(X86::ESP, MVT::i32), // Base
10681 DAG.getTargetConstant(1, MVT::i8), // Scale
10682 DAG.getRegister(0, MVT::i32), // Index
10683 DAG.getTargetConstant(0, MVT::i32), // Disp
10684 DAG.getRegister(0, MVT::i32), // Segment.
10689 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10690 array_lengthof(Ops));
10691 return SDValue(Res, 0);
10694 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10696 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10698 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10699 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10700 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10701 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10703 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10704 if (!Op1 && !Op2 && !Op3 && Op4)
10705 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10707 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10708 if (Op1 && !Op2 && !Op3 && !Op4)
10709 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10711 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10713 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10716 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10717 SelectionDAG &DAG) const {
10718 DebugLoc dl = Op.getDebugLoc();
10719 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10720 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10721 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10722 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10724 // The only fence that needs an instruction is a sequentially-consistent
10725 // cross-thread fence.
10726 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10727 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10728 // no-sse2). There isn't any reason to disable it if the target processor
10730 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
10731 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10733 SDValue Chain = Op.getOperand(0);
10734 SDValue Zero = DAG.getConstant(0, MVT::i32);
10736 DAG.getRegister(X86::ESP, MVT::i32), // Base
10737 DAG.getTargetConstant(1, MVT::i8), // Scale
10738 DAG.getRegister(0, MVT::i32), // Index
10739 DAG.getTargetConstant(0, MVT::i32), // Disp
10740 DAG.getRegister(0, MVT::i32), // Segment.
10745 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10746 array_lengthof(Ops));
10747 return SDValue(Res, 0);
10750 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10751 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10755 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10756 EVT T = Op.getValueType();
10757 DebugLoc DL = Op.getDebugLoc();
10760 switch(T.getSimpleVT().SimpleTy) {
10761 default: llvm_unreachable("Invalid value type!");
10762 case MVT::i8: Reg = X86::AL; size = 1; break;
10763 case MVT::i16: Reg = X86::AX; size = 2; break;
10764 case MVT::i32: Reg = X86::EAX; size = 4; break;
10766 assert(Subtarget->is64Bit() && "Node not type legal!");
10767 Reg = X86::RAX; size = 8;
10770 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10771 Op.getOperand(2), SDValue());
10772 SDValue Ops[] = { cpIn.getValue(0),
10775 DAG.getTargetConstant(size, MVT::i8),
10776 cpIn.getValue(1) };
10777 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10778 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10779 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10782 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10786 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10787 SelectionDAG &DAG) const {
10788 assert(Subtarget->is64Bit() && "Result not type legalized?");
10789 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10790 SDValue TheChain = Op.getOperand(0);
10791 DebugLoc dl = Op.getDebugLoc();
10792 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10793 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10794 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10796 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10797 DAG.getConstant(32, MVT::i8));
10799 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10802 return DAG.getMergeValues(Ops, 2, dl);
10805 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10806 SelectionDAG &DAG) const {
10807 EVT SrcVT = Op.getOperand(0).getValueType();
10808 EVT DstVT = Op.getValueType();
10809 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
10810 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10811 assert((DstVT == MVT::i64 ||
10812 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10813 "Unexpected custom BITCAST");
10814 // i64 <=> MMX conversions are Legal.
10815 if (SrcVT==MVT::i64 && DstVT.isVector())
10817 if (DstVT==MVT::i64 && SrcVT.isVector())
10819 // MMX <=> MMX conversions are Legal.
10820 if (SrcVT.isVector() && DstVT.isVector())
10822 // All other conversions need to be expanded.
10826 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10827 SDNode *Node = Op.getNode();
10828 DebugLoc dl = Node->getDebugLoc();
10829 EVT T = Node->getValueType(0);
10830 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10831 DAG.getConstant(0, T), Node->getOperand(2));
10832 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10833 cast<AtomicSDNode>(Node)->getMemoryVT(),
10834 Node->getOperand(0),
10835 Node->getOperand(1), negOp,
10836 cast<AtomicSDNode>(Node)->getSrcValue(),
10837 cast<AtomicSDNode>(Node)->getAlignment(),
10838 cast<AtomicSDNode>(Node)->getOrdering(),
10839 cast<AtomicSDNode>(Node)->getSynchScope());
10842 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10843 SDNode *Node = Op.getNode();
10844 DebugLoc dl = Node->getDebugLoc();
10845 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10847 // Convert seq_cst store -> xchg
10848 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10849 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10850 // (The only way to get a 16-byte store is cmpxchg16b)
10851 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10852 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10853 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10854 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10855 cast<AtomicSDNode>(Node)->getMemoryVT(),
10856 Node->getOperand(0),
10857 Node->getOperand(1), Node->getOperand(2),
10858 cast<AtomicSDNode>(Node)->getMemOperand(),
10859 cast<AtomicSDNode>(Node)->getOrdering(),
10860 cast<AtomicSDNode>(Node)->getSynchScope());
10861 return Swap.getValue(1);
10863 // Other atomic stores have a simple pattern.
10867 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10868 EVT VT = Op.getNode()->getValueType(0);
10870 // Let legalize expand this if it isn't a legal type yet.
10871 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10874 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10877 bool ExtraOp = false;
10878 switch (Op.getOpcode()) {
10879 default: llvm_unreachable("Invalid code");
10880 case ISD::ADDC: Opc = X86ISD::ADD; break;
10881 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10882 case ISD::SUBC: Opc = X86ISD::SUB; break;
10883 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10887 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10889 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10890 Op.getOperand(1), Op.getOperand(2));
10893 /// LowerOperation - Provide custom lowering hooks for some operations.
10895 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10896 switch (Op.getOpcode()) {
10897 default: llvm_unreachable("Should not custom lower this!");
10898 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10899 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10900 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10901 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10902 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10903 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10904 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10905 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10906 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10907 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10908 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10909 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10910 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10911 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10912 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10913 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10914 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10915 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10916 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10917 case ISD::SHL_PARTS:
10918 case ISD::SRA_PARTS:
10919 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10920 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10921 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10922 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10923 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10924 case ISD::FABS: return LowerFABS(Op, DAG);
10925 case ISD::FNEG: return LowerFNEG(Op, DAG);
10926 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10927 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10928 case ISD::SETCC: return LowerSETCC(Op, DAG);
10929 case ISD::SELECT: return LowerSELECT(Op, DAG);
10930 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10931 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10932 case ISD::VASTART: return LowerVASTART(Op, DAG);
10933 case ISD::VAARG: return LowerVAARG(Op, DAG);
10934 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10935 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10936 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
10937 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10938 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10939 case ISD::FRAME_TO_ARGS_OFFSET:
10940 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10941 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10942 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10943 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
10944 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
10945 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10946 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10947 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
10948 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10949 case ISD::MUL: return LowerMUL(Op, DAG);
10952 case ISD::SHL: return LowerShift(Op, DAG);
10958 case ISD::UMULO: return LowerXALUO(Op, DAG);
10959 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10960 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10964 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10965 case ISD::ADD: return LowerADD(Op, DAG);
10966 case ISD::SUB: return LowerSUB(Op, DAG);
10970 static void ReplaceATOMIC_LOAD(SDNode *Node,
10971 SmallVectorImpl<SDValue> &Results,
10972 SelectionDAG &DAG) {
10973 DebugLoc dl = Node->getDebugLoc();
10974 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10976 // Convert wide load -> cmpxchg8b/cmpxchg16b
10977 // FIXME: On 32-bit, load -> fild or movq would be more efficient
10978 // (The only way to get a 16-byte load is cmpxchg16b)
10979 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
10980 SDValue Zero = DAG.getConstant(0, VT);
10981 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
10982 Node->getOperand(0),
10983 Node->getOperand(1), Zero, Zero,
10984 cast<AtomicSDNode>(Node)->getMemOperand(),
10985 cast<AtomicSDNode>(Node)->getOrdering(),
10986 cast<AtomicSDNode>(Node)->getSynchScope());
10987 Results.push_back(Swap.getValue(0));
10988 Results.push_back(Swap.getValue(1));
10991 void X86TargetLowering::
10992 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10993 SelectionDAG &DAG, unsigned NewOp) const {
10994 DebugLoc dl = Node->getDebugLoc();
10995 assert (Node->getValueType(0) == MVT::i64 &&
10996 "Only know how to expand i64 atomics");
10998 SDValue Chain = Node->getOperand(0);
10999 SDValue In1 = Node->getOperand(1);
11000 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
11001 Node->getOperand(2), DAG.getIntPtrConstant(0));
11002 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
11003 Node->getOperand(2), DAG.getIntPtrConstant(1));
11004 SDValue Ops[] = { Chain, In1, In2L, In2H };
11005 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
11007 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
11008 cast<MemSDNode>(Node)->getMemOperand());
11009 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
11010 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
11011 Results.push_back(Result.getValue(2));
11014 /// ReplaceNodeResults - Replace a node with an illegal result type
11015 /// with a new node built out of custom code.
11016 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
11017 SmallVectorImpl<SDValue>&Results,
11018 SelectionDAG &DAG) const {
11019 DebugLoc dl = N->getDebugLoc();
11020 switch (N->getOpcode()) {
11022 llvm_unreachable("Do not know how to custom type legalize this operation!");
11023 case ISD::SIGN_EXTEND_INREG:
11028 // We don't want to expand or promote these.
11030 case ISD::FP_TO_SINT:
11031 case ISD::FP_TO_UINT: {
11032 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
11034 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
11037 std::pair<SDValue,SDValue> Vals =
11038 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
11039 SDValue FIST = Vals.first, StackSlot = Vals.second;
11040 if (FIST.getNode() != 0) {
11041 EVT VT = N->getValueType(0);
11042 // Return a load from the stack slot.
11043 if (StackSlot.getNode() != 0)
11044 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
11045 MachinePointerInfo(),
11046 false, false, false, 0));
11048 Results.push_back(FIST);
11052 case ISD::READCYCLECOUNTER: {
11053 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11054 SDValue TheChain = N->getOperand(0);
11055 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
11056 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
11058 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
11060 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
11061 SDValue Ops[] = { eax, edx };
11062 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
11063 Results.push_back(edx.getValue(1));
11066 case ISD::ATOMIC_CMP_SWAP: {
11067 EVT T = N->getValueType(0);
11068 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
11069 bool Regs64bit = T == MVT::i128;
11070 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
11071 SDValue cpInL, cpInH;
11072 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
11073 DAG.getConstant(0, HalfT));
11074 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
11075 DAG.getConstant(1, HalfT));
11076 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
11077 Regs64bit ? X86::RAX : X86::EAX,
11079 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
11080 Regs64bit ? X86::RDX : X86::EDX,
11081 cpInH, cpInL.getValue(1));
11082 SDValue swapInL, swapInH;
11083 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
11084 DAG.getConstant(0, HalfT));
11085 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
11086 DAG.getConstant(1, HalfT));
11087 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
11088 Regs64bit ? X86::RBX : X86::EBX,
11089 swapInL, cpInH.getValue(1));
11090 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
11091 Regs64bit ? X86::RCX : X86::ECX,
11092 swapInH, swapInL.getValue(1));
11093 SDValue Ops[] = { swapInH.getValue(0),
11095 swapInH.getValue(1) };
11096 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11097 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
11098 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
11099 X86ISD::LCMPXCHG8_DAG;
11100 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
11102 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
11103 Regs64bit ? X86::RAX : X86::EAX,
11104 HalfT, Result.getValue(1));
11105 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
11106 Regs64bit ? X86::RDX : X86::EDX,
11107 HalfT, cpOutL.getValue(2));
11108 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
11109 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
11110 Results.push_back(cpOutH.getValue(1));
11113 case ISD::ATOMIC_LOAD_ADD:
11114 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
11116 case ISD::ATOMIC_LOAD_AND:
11117 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
11119 case ISD::ATOMIC_LOAD_NAND:
11120 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
11122 case ISD::ATOMIC_LOAD_OR:
11123 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
11125 case ISD::ATOMIC_LOAD_SUB:
11126 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
11128 case ISD::ATOMIC_LOAD_XOR:
11129 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
11131 case ISD::ATOMIC_SWAP:
11132 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
11134 case ISD::ATOMIC_LOAD:
11135 ReplaceATOMIC_LOAD(N, Results, DAG);
11139 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
11141 default: return NULL;
11142 case X86ISD::BSF: return "X86ISD::BSF";
11143 case X86ISD::BSR: return "X86ISD::BSR";
11144 case X86ISD::SHLD: return "X86ISD::SHLD";
11145 case X86ISD::SHRD: return "X86ISD::SHRD";
11146 case X86ISD::FAND: return "X86ISD::FAND";
11147 case X86ISD::FOR: return "X86ISD::FOR";
11148 case X86ISD::FXOR: return "X86ISD::FXOR";
11149 case X86ISD::FSRL: return "X86ISD::FSRL";
11150 case X86ISD::FILD: return "X86ISD::FILD";
11151 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
11152 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
11153 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
11154 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
11155 case X86ISD::FLD: return "X86ISD::FLD";
11156 case X86ISD::FST: return "X86ISD::FST";
11157 case X86ISD::CALL: return "X86ISD::CALL";
11158 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
11159 case X86ISD::BT: return "X86ISD::BT";
11160 case X86ISD::CMP: return "X86ISD::CMP";
11161 case X86ISD::COMI: return "X86ISD::COMI";
11162 case X86ISD::UCOMI: return "X86ISD::UCOMI";
11163 case X86ISD::SETCC: return "X86ISD::SETCC";
11164 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
11165 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
11166 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
11167 case X86ISD::CMOV: return "X86ISD::CMOV";
11168 case X86ISD::BRCOND: return "X86ISD::BRCOND";
11169 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
11170 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
11171 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
11172 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
11173 case X86ISD::Wrapper: return "X86ISD::Wrapper";
11174 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
11175 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
11176 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
11177 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
11178 case X86ISD::PINSRB: return "X86ISD::PINSRB";
11179 case X86ISD::PINSRW: return "X86ISD::PINSRW";
11180 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
11181 case X86ISD::ANDNP: return "X86ISD::ANDNP";
11182 case X86ISD::PSIGN: return "X86ISD::PSIGN";
11183 case X86ISD::BLENDV: return "X86ISD::BLENDV";
11184 case X86ISD::BLENDPW: return "X86ISD::BLENDPW";
11185 case X86ISD::BLENDPS: return "X86ISD::BLENDPS";
11186 case X86ISD::BLENDPD: return "X86ISD::BLENDPD";
11187 case X86ISD::HADD: return "X86ISD::HADD";
11188 case X86ISD::HSUB: return "X86ISD::HSUB";
11189 case X86ISD::FHADD: return "X86ISD::FHADD";
11190 case X86ISD::FHSUB: return "X86ISD::FHSUB";
11191 case X86ISD::FMAX: return "X86ISD::FMAX";
11192 case X86ISD::FMIN: return "X86ISD::FMIN";
11193 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
11194 case X86ISD::FRCP: return "X86ISD::FRCP";
11195 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
11196 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
11197 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
11198 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
11199 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
11200 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
11201 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
11202 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
11203 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
11204 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
11205 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
11206 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
11207 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
11208 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
11209 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
11210 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
11211 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
11212 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
11213 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
11214 case X86ISD::VSHL: return "X86ISD::VSHL";
11215 case X86ISD::VSRL: return "X86ISD::VSRL";
11216 case X86ISD::VSRA: return "X86ISD::VSRA";
11217 case X86ISD::VSHLI: return "X86ISD::VSHLI";
11218 case X86ISD::VSRLI: return "X86ISD::VSRLI";
11219 case X86ISD::VSRAI: return "X86ISD::VSRAI";
11220 case X86ISD::CMPP: return "X86ISD::CMPP";
11221 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
11222 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
11223 case X86ISD::ADD: return "X86ISD::ADD";
11224 case X86ISD::SUB: return "X86ISD::SUB";
11225 case X86ISD::ADC: return "X86ISD::ADC";
11226 case X86ISD::SBB: return "X86ISD::SBB";
11227 case X86ISD::SMUL: return "X86ISD::SMUL";
11228 case X86ISD::UMUL: return "X86ISD::UMUL";
11229 case X86ISD::INC: return "X86ISD::INC";
11230 case X86ISD::DEC: return "X86ISD::DEC";
11231 case X86ISD::OR: return "X86ISD::OR";
11232 case X86ISD::XOR: return "X86ISD::XOR";
11233 case X86ISD::AND: return "X86ISD::AND";
11234 case X86ISD::ANDN: return "X86ISD::ANDN";
11235 case X86ISD::BLSI: return "X86ISD::BLSI";
11236 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
11237 case X86ISD::BLSR: return "X86ISD::BLSR";
11238 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
11239 case X86ISD::PTEST: return "X86ISD::PTEST";
11240 case X86ISD::TESTP: return "X86ISD::TESTP";
11241 case X86ISD::PALIGN: return "X86ISD::PALIGN";
11242 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
11243 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
11244 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
11245 case X86ISD::SHUFP: return "X86ISD::SHUFP";
11246 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
11247 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
11248 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
11249 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
11250 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
11251 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
11252 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
11253 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
11254 case X86ISD::MOVSD: return "X86ISD::MOVSD";
11255 case X86ISD::MOVSS: return "X86ISD::MOVSS";
11256 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
11257 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
11258 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
11259 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
11260 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
11261 case X86ISD::VPERMV: return "X86ISD::VPERMV";
11262 case X86ISD::VPERMI: return "X86ISD::VPERMI";
11263 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
11264 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
11265 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
11266 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
11267 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
11268 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
11269 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
11270 case X86ISD::SAHF: return "X86ISD::SAHF";
11271 case X86ISD::RDRAND: return "X86ISD::RDRAND";
11275 // isLegalAddressingMode - Return true if the addressing mode represented
11276 // by AM is legal for this target, for a load/store of the specified type.
11277 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
11279 // X86 supports extremely general addressing modes.
11280 CodeModel::Model M = getTargetMachine().getCodeModel();
11281 Reloc::Model R = getTargetMachine().getRelocationModel();
11283 // X86 allows a sign-extended 32-bit immediate field as a displacement.
11284 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
11289 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
11291 // If a reference to this global requires an extra load, we can't fold it.
11292 if (isGlobalStubReference(GVFlags))
11295 // If BaseGV requires a register for the PIC base, we cannot also have a
11296 // BaseReg specified.
11297 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
11300 // If lower 4G is not available, then we must use rip-relative addressing.
11301 if ((M != CodeModel::Small || R != Reloc::Static) &&
11302 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
11306 switch (AM.Scale) {
11312 // These scales always work.
11317 // These scales are formed with basereg+scalereg. Only accept if there is
11322 default: // Other stuff never works.
11330 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11331 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11333 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11334 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11335 if (NumBits1 <= NumBits2)
11340 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11341 if (!VT1.isInteger() || !VT2.isInteger())
11343 unsigned NumBits1 = VT1.getSizeInBits();
11344 unsigned NumBits2 = VT2.getSizeInBits();
11345 if (NumBits1 <= NumBits2)
11350 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
11351 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11352 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
11355 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
11356 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11357 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
11360 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
11361 // i16 instructions are longer (0x66 prefix) and potentially slower.
11362 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
11365 /// isShuffleMaskLegal - Targets can use this to indicate that they only
11366 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
11367 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
11368 /// are assumed to be legal.
11370 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
11372 // Very little shuffling can be done for 64-bit vectors right now.
11373 if (VT.getSizeInBits() == 64)
11376 // FIXME: pshufb, blends, shifts.
11377 return (VT.getVectorNumElements() == 2 ||
11378 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
11379 isMOVLMask(M, VT) ||
11380 isSHUFPMask(M, VT, Subtarget->hasAVX()) ||
11381 isPSHUFDMask(M, VT) ||
11382 isPSHUFHWMask(M, VT, Subtarget->hasAVX2()) ||
11383 isPSHUFLWMask(M, VT, Subtarget->hasAVX2()) ||
11384 isPALIGNRMask(M, VT, Subtarget) ||
11385 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) ||
11386 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) ||
11387 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) ||
11388 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2()));
11392 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
11394 unsigned NumElts = VT.getVectorNumElements();
11395 // FIXME: This collection of masks seems suspect.
11398 if (NumElts == 4 && VT.getSizeInBits() == 128) {
11399 return (isMOVLMask(Mask, VT) ||
11400 isCommutedMOVLMask(Mask, VT, true) ||
11401 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) ||
11402 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true));
11407 //===----------------------------------------------------------------------===//
11408 // X86 Scheduler Hooks
11409 //===----------------------------------------------------------------------===//
11411 // private utility function
11412 MachineBasicBlock *
11413 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
11414 MachineBasicBlock *MBB,
11421 const TargetRegisterClass *RC,
11422 bool Invert) const {
11423 // For the atomic bitwise operator, we generate
11426 // ld t1 = [bitinstr.addr]
11427 // op t2 = t1, [bitinstr.val]
11428 // not t3 = t2 (if Invert)
11430 // lcs dest = [bitinstr.addr], t3 [EAX is implicit]
11432 // fallthrough -->nextMBB
11433 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11434 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11435 MachineFunction::iterator MBBIter = MBB;
11438 /// First build the CFG
11439 MachineFunction *F = MBB->getParent();
11440 MachineBasicBlock *thisMBB = MBB;
11441 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11442 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11443 F->insert(MBBIter, newMBB);
11444 F->insert(MBBIter, nextMBB);
11446 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11447 nextMBB->splice(nextMBB->begin(), thisMBB,
11448 llvm::next(MachineBasicBlock::iterator(bInstr)),
11450 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11452 // Update thisMBB to fall through to newMBB
11453 thisMBB->addSuccessor(newMBB);
11455 // newMBB jumps to itself and fall through to nextMBB
11456 newMBB->addSuccessor(nextMBB);
11457 newMBB->addSuccessor(newMBB);
11459 // Insert instructions into newMBB based on incoming instruction
11460 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11461 "unexpected number of operands");
11462 DebugLoc dl = bInstr->getDebugLoc();
11463 MachineOperand& destOper = bInstr->getOperand(0);
11464 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11465 int numArgs = bInstr->getNumOperands() - 1;
11466 for (int i=0; i < numArgs; ++i)
11467 argOpers[i] = &bInstr->getOperand(i+1);
11469 // x86 address has 4 operands: base, index, scale, and displacement
11470 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11471 int valArgIndx = lastAddrIndx + 1;
11473 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11474 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
11475 for (int i=0; i <= lastAddrIndx; ++i)
11476 (*MIB).addOperand(*argOpers[i]);
11478 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11479 assert((argOpers[valArgIndx]->isReg() ||
11480 argOpers[valArgIndx]->isImm()) &&
11481 "invalid operand");
11482 if (argOpers[valArgIndx]->isReg())
11483 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
11485 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
11487 (*MIB).addOperand(*argOpers[valArgIndx]);
11489 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11491 MIB = BuildMI(newMBB, dl, TII->get(notOpc), t3).addReg(t2);
11496 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
11499 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
11500 for (int i=0; i <= lastAddrIndx; ++i)
11501 (*MIB).addOperand(*argOpers[i]);
11503 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11504 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11505 bInstr->memoperands_end());
11507 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11508 MIB.addReg(EAXreg);
11511 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11513 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11517 // private utility function: 64 bit atomics on 32 bit host.
11518 MachineBasicBlock *
11519 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
11520 MachineBasicBlock *MBB,
11525 bool Invert) const {
11526 // For the atomic bitwise operator, we generate
11527 // thisMBB (instructions are in pairs, except cmpxchg8b)
11528 // ld t1,t2 = [bitinstr.addr]
11530 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
11531 // op t5, t6 <- out1, out2, [bitinstr.val]
11532 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
11533 // neg t7, t8 < t5, t6 (if Invert)
11534 // mov ECX, EBX <- t5, t6
11535 // mov EAX, EDX <- t1, t2
11536 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
11537 // mov t3, t4 <- EAX, EDX
11539 // result in out1, out2
11540 // fallthrough -->nextMBB
11542 const TargetRegisterClass *RC = &X86::GR32RegClass;
11543 const unsigned LoadOpc = X86::MOV32rm;
11544 const unsigned NotOpc = X86::NOT32r;
11545 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11546 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11547 MachineFunction::iterator MBBIter = MBB;
11550 /// First build the CFG
11551 MachineFunction *F = MBB->getParent();
11552 MachineBasicBlock *thisMBB = MBB;
11553 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11554 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11555 F->insert(MBBIter, newMBB);
11556 F->insert(MBBIter, nextMBB);
11558 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11559 nextMBB->splice(nextMBB->begin(), thisMBB,
11560 llvm::next(MachineBasicBlock::iterator(bInstr)),
11562 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11564 // Update thisMBB to fall through to newMBB
11565 thisMBB->addSuccessor(newMBB);
11567 // newMBB jumps to itself and fall through to nextMBB
11568 newMBB->addSuccessor(nextMBB);
11569 newMBB->addSuccessor(newMBB);
11571 DebugLoc dl = bInstr->getDebugLoc();
11572 // Insert instructions into newMBB based on incoming instruction
11573 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
11574 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
11575 "unexpected number of operands");
11576 MachineOperand& dest1Oper = bInstr->getOperand(0);
11577 MachineOperand& dest2Oper = bInstr->getOperand(1);
11578 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11579 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
11580 argOpers[i] = &bInstr->getOperand(i+2);
11582 // We use some of the operands multiple times, so conservatively just
11583 // clear any kill flags that might be present.
11584 if (argOpers[i]->isReg() && argOpers[i]->isUse())
11585 argOpers[i]->setIsKill(false);
11588 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11589 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11591 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11592 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11593 for (int i=0; i <= lastAddrIndx; ++i)
11594 (*MIB).addOperand(*argOpers[i]);
11595 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11596 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11597 // add 4 to displacement.
11598 for (int i=0; i <= lastAddrIndx-2; ++i)
11599 (*MIB).addOperand(*argOpers[i]);
11600 MachineOperand newOp3 = *(argOpers[3]);
11601 if (newOp3.isImm())
11602 newOp3.setImm(newOp3.getImm()+4);
11604 newOp3.setOffset(newOp3.getOffset()+4);
11605 (*MIB).addOperand(newOp3);
11606 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11608 // t3/4 are defined later, at the bottom of the loop
11609 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11610 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11611 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11612 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11613 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11614 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11616 // The subsequent operations should be using the destination registers of
11617 // the PHI instructions.
11618 t1 = dest1Oper.getReg();
11619 t2 = dest2Oper.getReg();
11621 int valArgIndx = lastAddrIndx + 1;
11622 assert((argOpers[valArgIndx]->isReg() ||
11623 argOpers[valArgIndx]->isImm()) &&
11624 "invalid operand");
11625 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11626 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11627 if (argOpers[valArgIndx]->isReg())
11628 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11630 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11631 if (regOpcL != X86::MOV32rr)
11633 (*MIB).addOperand(*argOpers[valArgIndx]);
11634 assert(argOpers[valArgIndx + 1]->isReg() ==
11635 argOpers[valArgIndx]->isReg());
11636 assert(argOpers[valArgIndx + 1]->isImm() ==
11637 argOpers[valArgIndx]->isImm());
11638 if (argOpers[valArgIndx + 1]->isReg())
11639 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11641 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11642 if (regOpcH != X86::MOV32rr)
11644 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11648 t7 = F->getRegInfo().createVirtualRegister(RC);
11649 t8 = F->getRegInfo().createVirtualRegister(RC);
11650 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t7).addReg(t5);
11651 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t8).addReg(t6);
11657 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11659 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11662 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11664 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11667 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11668 for (int i=0; i <= lastAddrIndx; ++i)
11669 (*MIB).addOperand(*argOpers[i]);
11671 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11672 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11673 bInstr->memoperands_end());
11675 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11676 MIB.addReg(X86::EAX);
11677 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11678 MIB.addReg(X86::EDX);
11681 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11683 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11687 // private utility function
11688 MachineBasicBlock *
11689 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11690 MachineBasicBlock *MBB,
11691 unsigned cmovOpc) const {
11692 // For the atomic min/max operator, we generate
11695 // ld t1 = [min/max.addr]
11696 // mov t2 = [min/max.val]
11698 // cmov[cond] t2 = t1
11700 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11702 // fallthrough -->nextMBB
11704 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11705 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11706 MachineFunction::iterator MBBIter = MBB;
11709 /// First build the CFG
11710 MachineFunction *F = MBB->getParent();
11711 MachineBasicBlock *thisMBB = MBB;
11712 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11713 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11714 F->insert(MBBIter, newMBB);
11715 F->insert(MBBIter, nextMBB);
11717 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11718 nextMBB->splice(nextMBB->begin(), thisMBB,
11719 llvm::next(MachineBasicBlock::iterator(mInstr)),
11721 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11723 // Update thisMBB to fall through to newMBB
11724 thisMBB->addSuccessor(newMBB);
11726 // newMBB jumps to newMBB and fall through to nextMBB
11727 newMBB->addSuccessor(nextMBB);
11728 newMBB->addSuccessor(newMBB);
11730 DebugLoc dl = mInstr->getDebugLoc();
11731 // Insert instructions into newMBB based on incoming instruction
11732 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11733 "unexpected number of operands");
11734 MachineOperand& destOper = mInstr->getOperand(0);
11735 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11736 int numArgs = mInstr->getNumOperands() - 1;
11737 for (int i=0; i < numArgs; ++i)
11738 argOpers[i] = &mInstr->getOperand(i+1);
11740 // x86 address has 4 operands: base, index, scale, and displacement
11741 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11742 int valArgIndx = lastAddrIndx + 1;
11744 unsigned t1 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11745 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11746 for (int i=0; i <= lastAddrIndx; ++i)
11747 (*MIB).addOperand(*argOpers[i]);
11749 // We only support register and immediate values
11750 assert((argOpers[valArgIndx]->isReg() ||
11751 argOpers[valArgIndx]->isImm()) &&
11752 "invalid operand");
11754 unsigned t2 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11755 if (argOpers[valArgIndx]->isReg())
11756 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11758 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11759 (*MIB).addOperand(*argOpers[valArgIndx]);
11761 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11764 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11769 unsigned t3 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11770 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11774 // Cmp and exchange if none has modified the memory location
11775 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11776 for (int i=0; i <= lastAddrIndx; ++i)
11777 (*MIB).addOperand(*argOpers[i]);
11779 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11780 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11781 mInstr->memoperands_end());
11783 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11784 MIB.addReg(X86::EAX);
11787 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11789 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11793 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11794 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11795 // in the .td file.
11796 MachineBasicBlock *
11797 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11798 unsigned numArgs, bool memArg) const {
11799 assert(Subtarget->hasSSE42() &&
11800 "Target must have SSE4.2 or AVX features enabled");
11802 DebugLoc dl = MI->getDebugLoc();
11803 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11805 if (!Subtarget->hasAVX()) {
11807 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11809 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11812 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11814 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11817 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11818 for (unsigned i = 0; i < numArgs; ++i) {
11819 MachineOperand &Op = MI->getOperand(i+1);
11820 if (!(Op.isReg() && Op.isImplicit()))
11821 MIB.addOperand(Op);
11823 BuildMI(*BB, MI, dl,
11824 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr),
11825 MI->getOperand(0).getReg())
11826 .addReg(X86::XMM0);
11828 MI->eraseFromParent();
11832 MachineBasicBlock *
11833 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11834 DebugLoc dl = MI->getDebugLoc();
11835 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11837 // Address into RAX/EAX, other two args into ECX, EDX.
11838 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11839 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11840 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11841 for (int i = 0; i < X86::AddrNumOperands; ++i)
11842 MIB.addOperand(MI->getOperand(i));
11844 unsigned ValOps = X86::AddrNumOperands;
11845 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11846 .addReg(MI->getOperand(ValOps).getReg());
11847 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11848 .addReg(MI->getOperand(ValOps+1).getReg());
11850 // The instruction doesn't actually take any operands though.
11851 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11853 MI->eraseFromParent(); // The pseudo is gone now.
11857 MachineBasicBlock *
11858 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
11859 DebugLoc dl = MI->getDebugLoc();
11860 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11862 // First arg in ECX, the second in EAX.
11863 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11864 .addReg(MI->getOperand(0).getReg());
11865 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11866 .addReg(MI->getOperand(1).getReg());
11868 // The instruction doesn't actually take any operands though.
11869 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11871 MI->eraseFromParent(); // The pseudo is gone now.
11875 MachineBasicBlock *
11876 X86TargetLowering::EmitVAARG64WithCustomInserter(
11878 MachineBasicBlock *MBB) const {
11879 // Emit va_arg instruction on X86-64.
11881 // Operands to this pseudo-instruction:
11882 // 0 ) Output : destination address (reg)
11883 // 1-5) Input : va_list address (addr, i64mem)
11884 // 6 ) ArgSize : Size (in bytes) of vararg type
11885 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11886 // 8 ) Align : Alignment of type
11887 // 9 ) EFLAGS (implicit-def)
11889 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11890 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11892 unsigned DestReg = MI->getOperand(0).getReg();
11893 MachineOperand &Base = MI->getOperand(1);
11894 MachineOperand &Scale = MI->getOperand(2);
11895 MachineOperand &Index = MI->getOperand(3);
11896 MachineOperand &Disp = MI->getOperand(4);
11897 MachineOperand &Segment = MI->getOperand(5);
11898 unsigned ArgSize = MI->getOperand(6).getImm();
11899 unsigned ArgMode = MI->getOperand(7).getImm();
11900 unsigned Align = MI->getOperand(8).getImm();
11902 // Memory Reference
11903 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11904 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11905 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11907 // Machine Information
11908 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11909 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11910 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11911 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11912 DebugLoc DL = MI->getDebugLoc();
11914 // struct va_list {
11917 // i64 overflow_area (address)
11918 // i64 reg_save_area (address)
11920 // sizeof(va_list) = 24
11921 // alignment(va_list) = 8
11923 unsigned TotalNumIntRegs = 6;
11924 unsigned TotalNumXMMRegs = 8;
11925 bool UseGPOffset = (ArgMode == 1);
11926 bool UseFPOffset = (ArgMode == 2);
11927 unsigned MaxOffset = TotalNumIntRegs * 8 +
11928 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11930 /* Align ArgSize to a multiple of 8 */
11931 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11932 bool NeedsAlign = (Align > 8);
11934 MachineBasicBlock *thisMBB = MBB;
11935 MachineBasicBlock *overflowMBB;
11936 MachineBasicBlock *offsetMBB;
11937 MachineBasicBlock *endMBB;
11939 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11940 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11941 unsigned OffsetReg = 0;
11943 if (!UseGPOffset && !UseFPOffset) {
11944 // If we only pull from the overflow region, we don't create a branch.
11945 // We don't need to alter control flow.
11946 OffsetDestReg = 0; // unused
11947 OverflowDestReg = DestReg;
11950 overflowMBB = thisMBB;
11953 // First emit code to check if gp_offset (or fp_offset) is below the bound.
11954 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
11955 // If not, pull from overflow_area. (branch to overflowMBB)
11960 // offsetMBB overflowMBB
11965 // Registers for the PHI in endMBB
11966 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
11967 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
11969 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11970 MachineFunction *MF = MBB->getParent();
11971 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11972 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11973 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11975 MachineFunction::iterator MBBIter = MBB;
11978 // Insert the new basic blocks
11979 MF->insert(MBBIter, offsetMBB);
11980 MF->insert(MBBIter, overflowMBB);
11981 MF->insert(MBBIter, endMBB);
11983 // Transfer the remainder of MBB and its successor edges to endMBB.
11984 endMBB->splice(endMBB->begin(), thisMBB,
11985 llvm::next(MachineBasicBlock::iterator(MI)),
11987 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11989 // Make offsetMBB and overflowMBB successors of thisMBB
11990 thisMBB->addSuccessor(offsetMBB);
11991 thisMBB->addSuccessor(overflowMBB);
11993 // endMBB is a successor of both offsetMBB and overflowMBB
11994 offsetMBB->addSuccessor(endMBB);
11995 overflowMBB->addSuccessor(endMBB);
11997 // Load the offset value into a register
11998 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11999 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
12003 .addDisp(Disp, UseFPOffset ? 4 : 0)
12004 .addOperand(Segment)
12005 .setMemRefs(MMOBegin, MMOEnd);
12007 // Check if there is enough room left to pull this argument.
12008 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
12010 .addImm(MaxOffset + 8 - ArgSizeA8);
12012 // Branch to "overflowMBB" if offset >= max
12013 // Fall through to "offsetMBB" otherwise
12014 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
12015 .addMBB(overflowMBB);
12018 // In offsetMBB, emit code to use the reg_save_area.
12020 assert(OffsetReg != 0);
12022 // Read the reg_save_area address.
12023 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
12024 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
12029 .addOperand(Segment)
12030 .setMemRefs(MMOBegin, MMOEnd);
12032 // Zero-extend the offset
12033 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
12034 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
12037 .addImm(X86::sub_32bit);
12039 // Add the offset to the reg_save_area to get the final address.
12040 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
12041 .addReg(OffsetReg64)
12042 .addReg(RegSaveReg);
12044 // Compute the offset for the next argument
12045 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
12046 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
12048 .addImm(UseFPOffset ? 16 : 8);
12050 // Store it back into the va_list.
12051 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
12055 .addDisp(Disp, UseFPOffset ? 4 : 0)
12056 .addOperand(Segment)
12057 .addReg(NextOffsetReg)
12058 .setMemRefs(MMOBegin, MMOEnd);
12061 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
12066 // Emit code to use overflow area
12069 // Load the overflow_area address into a register.
12070 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
12071 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
12076 .addOperand(Segment)
12077 .setMemRefs(MMOBegin, MMOEnd);
12079 // If we need to align it, do so. Otherwise, just copy the address
12080 // to OverflowDestReg.
12082 // Align the overflow address
12083 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
12084 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
12086 // aligned_addr = (addr + (align-1)) & ~(align-1)
12087 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
12088 .addReg(OverflowAddrReg)
12091 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
12093 .addImm(~(uint64_t)(Align-1));
12095 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
12096 .addReg(OverflowAddrReg);
12099 // Compute the next overflow address after this argument.
12100 // (the overflow address should be kept 8-byte aligned)
12101 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
12102 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
12103 .addReg(OverflowDestReg)
12104 .addImm(ArgSizeA8);
12106 // Store the new overflow address.
12107 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
12112 .addOperand(Segment)
12113 .addReg(NextAddrReg)
12114 .setMemRefs(MMOBegin, MMOEnd);
12116 // If we branched, emit the PHI to the front of endMBB.
12118 BuildMI(*endMBB, endMBB->begin(), DL,
12119 TII->get(X86::PHI), DestReg)
12120 .addReg(OffsetDestReg).addMBB(offsetMBB)
12121 .addReg(OverflowDestReg).addMBB(overflowMBB);
12124 // Erase the pseudo instruction
12125 MI->eraseFromParent();
12130 MachineBasicBlock *
12131 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
12133 MachineBasicBlock *MBB) const {
12134 // Emit code to save XMM registers to the stack. The ABI says that the
12135 // number of registers to save is given in %al, so it's theoretically
12136 // possible to do an indirect jump trick to avoid saving all of them,
12137 // however this code takes a simpler approach and just executes all
12138 // of the stores if %al is non-zero. It's less code, and it's probably
12139 // easier on the hardware branch predictor, and stores aren't all that
12140 // expensive anyway.
12142 // Create the new basic blocks. One block contains all the XMM stores,
12143 // and one block is the final destination regardless of whether any
12144 // stores were performed.
12145 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
12146 MachineFunction *F = MBB->getParent();
12147 MachineFunction::iterator MBBIter = MBB;
12149 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
12150 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
12151 F->insert(MBBIter, XMMSaveMBB);
12152 F->insert(MBBIter, EndMBB);
12154 // Transfer the remainder of MBB and its successor edges to EndMBB.
12155 EndMBB->splice(EndMBB->begin(), MBB,
12156 llvm::next(MachineBasicBlock::iterator(MI)),
12158 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
12160 // The original block will now fall through to the XMM save block.
12161 MBB->addSuccessor(XMMSaveMBB);
12162 // The XMMSaveMBB will fall through to the end block.
12163 XMMSaveMBB->addSuccessor(EndMBB);
12165 // Now add the instructions.
12166 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12167 DebugLoc DL = MI->getDebugLoc();
12169 unsigned CountReg = MI->getOperand(0).getReg();
12170 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
12171 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
12173 if (!Subtarget->isTargetWin64()) {
12174 // If %al is 0, branch around the XMM save block.
12175 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
12176 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
12177 MBB->addSuccessor(EndMBB);
12180 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
12181 // In the XMM save block, save all the XMM argument registers.
12182 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
12183 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
12184 MachineMemOperand *MMO =
12185 F->getMachineMemOperand(
12186 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
12187 MachineMemOperand::MOStore,
12188 /*Size=*/16, /*Align=*/16);
12189 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
12190 .addFrameIndex(RegSaveFrameIndex)
12191 .addImm(/*Scale=*/1)
12192 .addReg(/*IndexReg=*/0)
12193 .addImm(/*Disp=*/Offset)
12194 .addReg(/*Segment=*/0)
12195 .addReg(MI->getOperand(i).getReg())
12196 .addMemOperand(MMO);
12199 MI->eraseFromParent(); // The pseudo instruction is gone now.
12204 // The EFLAGS operand of SelectItr might be missing a kill marker
12205 // because there were multiple uses of EFLAGS, and ISel didn't know
12206 // which to mark. Figure out whether SelectItr should have had a
12207 // kill marker, and set it if it should. Returns the correct kill
12209 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
12210 MachineBasicBlock* BB,
12211 const TargetRegisterInfo* TRI) {
12212 // Scan forward through BB for a use/def of EFLAGS.
12213 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
12214 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
12215 const MachineInstr& mi = *miI;
12216 if (mi.readsRegister(X86::EFLAGS))
12218 if (mi.definesRegister(X86::EFLAGS))
12219 break; // Should have kill-flag - update below.
12222 // If we hit the end of the block, check whether EFLAGS is live into a
12224 if (miI == BB->end()) {
12225 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
12226 sEnd = BB->succ_end();
12227 sItr != sEnd; ++sItr) {
12228 MachineBasicBlock* succ = *sItr;
12229 if (succ->isLiveIn(X86::EFLAGS))
12234 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
12235 // out. SelectMI should have a kill flag on EFLAGS.
12236 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
12240 MachineBasicBlock *
12241 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
12242 MachineBasicBlock *BB) const {
12243 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12244 DebugLoc DL = MI->getDebugLoc();
12246 // To "insert" a SELECT_CC instruction, we actually have to insert the
12247 // diamond control-flow pattern. The incoming instruction knows the
12248 // destination vreg to set, the condition code register to branch on, the
12249 // true/false values to select between, and a branch opcode to use.
12250 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12251 MachineFunction::iterator It = BB;
12257 // cmpTY ccX, r1, r2
12259 // fallthrough --> copy0MBB
12260 MachineBasicBlock *thisMBB = BB;
12261 MachineFunction *F = BB->getParent();
12262 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
12263 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
12264 F->insert(It, copy0MBB);
12265 F->insert(It, sinkMBB);
12267 // If the EFLAGS register isn't dead in the terminator, then claim that it's
12268 // live into the sink and copy blocks.
12269 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12270 if (!MI->killsRegister(X86::EFLAGS) &&
12271 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
12272 copy0MBB->addLiveIn(X86::EFLAGS);
12273 sinkMBB->addLiveIn(X86::EFLAGS);
12276 // Transfer the remainder of BB and its successor edges to sinkMBB.
12277 sinkMBB->splice(sinkMBB->begin(), BB,
12278 llvm::next(MachineBasicBlock::iterator(MI)),
12280 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
12282 // Add the true and fallthrough blocks as its successors.
12283 BB->addSuccessor(copy0MBB);
12284 BB->addSuccessor(sinkMBB);
12286 // Create the conditional branch instruction.
12288 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
12289 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
12292 // %FalseValue = ...
12293 // # fallthrough to sinkMBB
12294 copy0MBB->addSuccessor(sinkMBB);
12297 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
12299 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12300 TII->get(X86::PHI), MI->getOperand(0).getReg())
12301 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
12302 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
12304 MI->eraseFromParent(); // The pseudo instruction is gone now.
12308 MachineBasicBlock *
12309 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
12310 bool Is64Bit) const {
12311 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12312 DebugLoc DL = MI->getDebugLoc();
12313 MachineFunction *MF = BB->getParent();
12314 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12316 assert(getTargetMachine().Options.EnableSegmentedStacks);
12318 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
12319 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
12322 // ... [Till the alloca]
12323 // If stacklet is not large enough, jump to mallocMBB
12326 // Allocate by subtracting from RSP
12327 // Jump to continueMBB
12330 // Allocate by call to runtime
12334 // [rest of original BB]
12337 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12338 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12339 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12341 MachineRegisterInfo &MRI = MF->getRegInfo();
12342 const TargetRegisterClass *AddrRegClass =
12343 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
12345 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12346 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12347 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
12348 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
12349 sizeVReg = MI->getOperand(1).getReg(),
12350 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
12352 MachineFunction::iterator MBBIter = BB;
12355 MF->insert(MBBIter, bumpMBB);
12356 MF->insert(MBBIter, mallocMBB);
12357 MF->insert(MBBIter, continueMBB);
12359 continueMBB->splice(continueMBB->begin(), BB, llvm::next
12360 (MachineBasicBlock::iterator(MI)), BB->end());
12361 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
12363 // Add code to the main basic block to check if the stack limit has been hit,
12364 // and if so, jump to mallocMBB otherwise to bumpMBB.
12365 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
12366 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
12367 .addReg(tmpSPVReg).addReg(sizeVReg);
12368 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
12369 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
12370 .addReg(SPLimitVReg);
12371 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
12373 // bumpMBB simply decreases the stack pointer, since we know the current
12374 // stacklet has enough space.
12375 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
12376 .addReg(SPLimitVReg);
12377 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
12378 .addReg(SPLimitVReg);
12379 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12381 // Calls into a routine in libgcc to allocate more space from the heap.
12382 const uint32_t *RegMask =
12383 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12385 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
12387 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
12388 .addExternalSymbol("__morestack_allocate_stack_space")
12389 .addRegMask(RegMask)
12390 .addReg(X86::RDI, RegState::Implicit)
12391 .addReg(X86::RAX, RegState::ImplicitDefine);
12393 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
12395 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
12396 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
12397 .addExternalSymbol("__morestack_allocate_stack_space")
12398 .addRegMask(RegMask)
12399 .addReg(X86::EAX, RegState::ImplicitDefine);
12403 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
12406 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
12407 .addReg(Is64Bit ? X86::RAX : X86::EAX);
12408 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12410 // Set up the CFG correctly.
12411 BB->addSuccessor(bumpMBB);
12412 BB->addSuccessor(mallocMBB);
12413 mallocMBB->addSuccessor(continueMBB);
12414 bumpMBB->addSuccessor(continueMBB);
12416 // Take care of the PHI nodes.
12417 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
12418 MI->getOperand(0).getReg())
12419 .addReg(mallocPtrVReg).addMBB(mallocMBB)
12420 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
12422 // Delete the original pseudo instruction.
12423 MI->eraseFromParent();
12426 return continueMBB;
12429 MachineBasicBlock *
12430 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
12431 MachineBasicBlock *BB) const {
12432 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12433 DebugLoc DL = MI->getDebugLoc();
12435 assert(!Subtarget->isTargetEnvMacho());
12437 // The lowering is pretty easy: we're just emitting the call to _alloca. The
12438 // non-trivial part is impdef of ESP.
12440 if (Subtarget->isTargetWin64()) {
12441 if (Subtarget->isTargetCygMing()) {
12442 // ___chkstk(Mingw64):
12443 // Clobbers R10, R11, RAX and EFLAGS.
12445 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12446 .addExternalSymbol("___chkstk")
12447 .addReg(X86::RAX, RegState::Implicit)
12448 .addReg(X86::RSP, RegState::Implicit)
12449 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
12450 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
12451 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12453 // __chkstk(MSVCRT): does not update stack pointer.
12454 // Clobbers R10, R11 and EFLAGS.
12455 // FIXME: RAX(allocated size) might be reused and not killed.
12456 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12457 .addExternalSymbol("__chkstk")
12458 .addReg(X86::RAX, RegState::Implicit)
12459 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12460 // RAX has the offset to subtracted from RSP.
12461 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
12466 const char *StackProbeSymbol =
12467 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
12469 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
12470 .addExternalSymbol(StackProbeSymbol)
12471 .addReg(X86::EAX, RegState::Implicit)
12472 .addReg(X86::ESP, RegState::Implicit)
12473 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
12474 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
12475 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12478 MI->eraseFromParent(); // The pseudo instruction is gone now.
12482 MachineBasicBlock *
12483 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
12484 MachineBasicBlock *BB) const {
12485 // This is pretty easy. We're taking the value that we received from
12486 // our load from the relocation, sticking it in either RDI (x86-64)
12487 // or EAX and doing an indirect call. The return value will then
12488 // be in the normal return register.
12489 const X86InstrInfo *TII
12490 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
12491 DebugLoc DL = MI->getDebugLoc();
12492 MachineFunction *F = BB->getParent();
12494 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
12495 assert(MI->getOperand(3).isGlobal() && "This should be a global");
12497 // Get a register mask for the lowered call.
12498 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
12499 // proper register mask.
12500 const uint32_t *RegMask =
12501 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12502 if (Subtarget->is64Bit()) {
12503 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12504 TII->get(X86::MOV64rm), X86::RDI)
12506 .addImm(0).addReg(0)
12507 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12508 MI->getOperand(3).getTargetFlags())
12510 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
12511 addDirectMem(MIB, X86::RDI);
12512 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
12513 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
12514 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12515 TII->get(X86::MOV32rm), X86::EAX)
12517 .addImm(0).addReg(0)
12518 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12519 MI->getOperand(3).getTargetFlags())
12521 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12522 addDirectMem(MIB, X86::EAX);
12523 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12525 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12526 TII->get(X86::MOV32rm), X86::EAX)
12527 .addReg(TII->getGlobalBaseReg(F))
12528 .addImm(0).addReg(0)
12529 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12530 MI->getOperand(3).getTargetFlags())
12532 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12533 addDirectMem(MIB, X86::EAX);
12534 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12537 MI->eraseFromParent(); // The pseudo instruction is gone now.
12541 MachineBasicBlock *
12542 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
12543 MachineBasicBlock *BB) const {
12544 switch (MI->getOpcode()) {
12545 default: llvm_unreachable("Unexpected instr type to insert");
12546 case X86::TAILJMPd64:
12547 case X86::TAILJMPr64:
12548 case X86::TAILJMPm64:
12549 llvm_unreachable("TAILJMP64 would not be touched here.");
12550 case X86::TCRETURNdi64:
12551 case X86::TCRETURNri64:
12552 case X86::TCRETURNmi64:
12554 case X86::WIN_ALLOCA:
12555 return EmitLoweredWinAlloca(MI, BB);
12556 case X86::SEG_ALLOCA_32:
12557 return EmitLoweredSegAlloca(MI, BB, false);
12558 case X86::SEG_ALLOCA_64:
12559 return EmitLoweredSegAlloca(MI, BB, true);
12560 case X86::TLSCall_32:
12561 case X86::TLSCall_64:
12562 return EmitLoweredTLSCall(MI, BB);
12563 case X86::CMOV_GR8:
12564 case X86::CMOV_FR32:
12565 case X86::CMOV_FR64:
12566 case X86::CMOV_V4F32:
12567 case X86::CMOV_V2F64:
12568 case X86::CMOV_V2I64:
12569 case X86::CMOV_V8F32:
12570 case X86::CMOV_V4F64:
12571 case X86::CMOV_V4I64:
12572 case X86::CMOV_GR16:
12573 case X86::CMOV_GR32:
12574 case X86::CMOV_RFP32:
12575 case X86::CMOV_RFP64:
12576 case X86::CMOV_RFP80:
12577 return EmitLoweredSelect(MI, BB);
12579 case X86::FP32_TO_INT16_IN_MEM:
12580 case X86::FP32_TO_INT32_IN_MEM:
12581 case X86::FP32_TO_INT64_IN_MEM:
12582 case X86::FP64_TO_INT16_IN_MEM:
12583 case X86::FP64_TO_INT32_IN_MEM:
12584 case X86::FP64_TO_INT64_IN_MEM:
12585 case X86::FP80_TO_INT16_IN_MEM:
12586 case X86::FP80_TO_INT32_IN_MEM:
12587 case X86::FP80_TO_INT64_IN_MEM: {
12588 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12589 DebugLoc DL = MI->getDebugLoc();
12591 // Change the floating point control register to use "round towards zero"
12592 // mode when truncating to an integer value.
12593 MachineFunction *F = BB->getParent();
12594 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
12595 addFrameReference(BuildMI(*BB, MI, DL,
12596 TII->get(X86::FNSTCW16m)), CWFrameIdx);
12598 // Load the old value of the high byte of the control word...
12600 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
12601 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
12604 // Set the high part to be round to zero...
12605 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
12608 // Reload the modified control word now...
12609 addFrameReference(BuildMI(*BB, MI, DL,
12610 TII->get(X86::FLDCW16m)), CWFrameIdx);
12612 // Restore the memory image of control word to original value
12613 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
12616 // Get the X86 opcode to use.
12618 switch (MI->getOpcode()) {
12619 default: llvm_unreachable("illegal opcode!");
12620 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12621 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12622 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12623 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12624 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12625 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12626 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12627 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12628 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12632 MachineOperand &Op = MI->getOperand(0);
12634 AM.BaseType = X86AddressMode::RegBase;
12635 AM.Base.Reg = Op.getReg();
12637 AM.BaseType = X86AddressMode::FrameIndexBase;
12638 AM.Base.FrameIndex = Op.getIndex();
12640 Op = MI->getOperand(1);
12642 AM.Scale = Op.getImm();
12643 Op = MI->getOperand(2);
12645 AM.IndexReg = Op.getImm();
12646 Op = MI->getOperand(3);
12647 if (Op.isGlobal()) {
12648 AM.GV = Op.getGlobal();
12650 AM.Disp = Op.getImm();
12652 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12653 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
12655 // Reload the original control word now.
12656 addFrameReference(BuildMI(*BB, MI, DL,
12657 TII->get(X86::FLDCW16m)), CWFrameIdx);
12659 MI->eraseFromParent(); // The pseudo instruction is gone now.
12662 // String/text processing lowering.
12663 case X86::PCMPISTRM128REG:
12664 case X86::VPCMPISTRM128REG:
12665 return EmitPCMP(MI, BB, 3, false /* in-mem */);
12666 case X86::PCMPISTRM128MEM:
12667 case X86::VPCMPISTRM128MEM:
12668 return EmitPCMP(MI, BB, 3, true /* in-mem */);
12669 case X86::PCMPESTRM128REG:
12670 case X86::VPCMPESTRM128REG:
12671 return EmitPCMP(MI, BB, 5, false /* in mem */);
12672 case X86::PCMPESTRM128MEM:
12673 case X86::VPCMPESTRM128MEM:
12674 return EmitPCMP(MI, BB, 5, true /* in mem */);
12676 // Thread synchronization.
12678 return EmitMonitor(MI, BB);
12680 return EmitMwait(MI, BB);
12682 // Atomic Lowering.
12683 case X86::ATOMAND32:
12684 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12685 X86::AND32ri, X86::MOV32rm,
12687 X86::NOT32r, X86::EAX,
12688 &X86::GR32RegClass);
12689 case X86::ATOMOR32:
12690 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
12691 X86::OR32ri, X86::MOV32rm,
12693 X86::NOT32r, X86::EAX,
12694 &X86::GR32RegClass);
12695 case X86::ATOMXOR32:
12696 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
12697 X86::XOR32ri, X86::MOV32rm,
12699 X86::NOT32r, X86::EAX,
12700 &X86::GR32RegClass);
12701 case X86::ATOMNAND32:
12702 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12703 X86::AND32ri, X86::MOV32rm,
12705 X86::NOT32r, X86::EAX,
12706 &X86::GR32RegClass, true);
12707 case X86::ATOMMIN32:
12708 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
12709 case X86::ATOMMAX32:
12710 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
12711 case X86::ATOMUMIN32:
12712 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
12713 case X86::ATOMUMAX32:
12714 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
12716 case X86::ATOMAND16:
12717 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12718 X86::AND16ri, X86::MOV16rm,
12720 X86::NOT16r, X86::AX,
12721 &X86::GR16RegClass);
12722 case X86::ATOMOR16:
12723 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
12724 X86::OR16ri, X86::MOV16rm,
12726 X86::NOT16r, X86::AX,
12727 &X86::GR16RegClass);
12728 case X86::ATOMXOR16:
12729 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
12730 X86::XOR16ri, X86::MOV16rm,
12732 X86::NOT16r, X86::AX,
12733 &X86::GR16RegClass);
12734 case X86::ATOMNAND16:
12735 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12736 X86::AND16ri, X86::MOV16rm,
12738 X86::NOT16r, X86::AX,
12739 &X86::GR16RegClass, true);
12740 case X86::ATOMMIN16:
12741 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
12742 case X86::ATOMMAX16:
12743 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
12744 case X86::ATOMUMIN16:
12745 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
12746 case X86::ATOMUMAX16:
12747 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
12749 case X86::ATOMAND8:
12750 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12751 X86::AND8ri, X86::MOV8rm,
12753 X86::NOT8r, X86::AL,
12754 &X86::GR8RegClass);
12756 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
12757 X86::OR8ri, X86::MOV8rm,
12759 X86::NOT8r, X86::AL,
12760 &X86::GR8RegClass);
12761 case X86::ATOMXOR8:
12762 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
12763 X86::XOR8ri, X86::MOV8rm,
12765 X86::NOT8r, X86::AL,
12766 &X86::GR8RegClass);
12767 case X86::ATOMNAND8:
12768 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12769 X86::AND8ri, X86::MOV8rm,
12771 X86::NOT8r, X86::AL,
12772 &X86::GR8RegClass, true);
12773 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
12774 // This group is for 64-bit host.
12775 case X86::ATOMAND64:
12776 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12777 X86::AND64ri32, X86::MOV64rm,
12779 X86::NOT64r, X86::RAX,
12780 &X86::GR64RegClass);
12781 case X86::ATOMOR64:
12782 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
12783 X86::OR64ri32, X86::MOV64rm,
12785 X86::NOT64r, X86::RAX,
12786 &X86::GR64RegClass);
12787 case X86::ATOMXOR64:
12788 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
12789 X86::XOR64ri32, X86::MOV64rm,
12791 X86::NOT64r, X86::RAX,
12792 &X86::GR64RegClass);
12793 case X86::ATOMNAND64:
12794 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12795 X86::AND64ri32, X86::MOV64rm,
12797 X86::NOT64r, X86::RAX,
12798 &X86::GR64RegClass, true);
12799 case X86::ATOMMIN64:
12800 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12801 case X86::ATOMMAX64:
12802 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12803 case X86::ATOMUMIN64:
12804 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12805 case X86::ATOMUMAX64:
12806 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12808 // This group does 64-bit operations on a 32-bit host.
12809 case X86::ATOMAND6432:
12810 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12811 X86::AND32rr, X86::AND32rr,
12812 X86::AND32ri, X86::AND32ri,
12814 case X86::ATOMOR6432:
12815 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12816 X86::OR32rr, X86::OR32rr,
12817 X86::OR32ri, X86::OR32ri,
12819 case X86::ATOMXOR6432:
12820 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12821 X86::XOR32rr, X86::XOR32rr,
12822 X86::XOR32ri, X86::XOR32ri,
12824 case X86::ATOMNAND6432:
12825 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12826 X86::AND32rr, X86::AND32rr,
12827 X86::AND32ri, X86::AND32ri,
12829 case X86::ATOMADD6432:
12830 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12831 X86::ADD32rr, X86::ADC32rr,
12832 X86::ADD32ri, X86::ADC32ri,
12834 case X86::ATOMSUB6432:
12835 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12836 X86::SUB32rr, X86::SBB32rr,
12837 X86::SUB32ri, X86::SBB32ri,
12839 case X86::ATOMSWAP6432:
12840 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12841 X86::MOV32rr, X86::MOV32rr,
12842 X86::MOV32ri, X86::MOV32ri,
12844 case X86::VASTART_SAVE_XMM_REGS:
12845 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12847 case X86::VAARG_64:
12848 return EmitVAARG64WithCustomInserter(MI, BB);
12852 //===----------------------------------------------------------------------===//
12853 // X86 Optimization Hooks
12854 //===----------------------------------------------------------------------===//
12856 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12859 const SelectionDAG &DAG,
12860 unsigned Depth) const {
12861 unsigned BitWidth = KnownZero.getBitWidth();
12862 unsigned Opc = Op.getOpcode();
12863 assert((Opc >= ISD::BUILTIN_OP_END ||
12864 Opc == ISD::INTRINSIC_WO_CHAIN ||
12865 Opc == ISD::INTRINSIC_W_CHAIN ||
12866 Opc == ISD::INTRINSIC_VOID) &&
12867 "Should use MaskedValueIsZero if you don't know whether Op"
12868 " is a target node!");
12870 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
12884 // These nodes' second result is a boolean.
12885 if (Op.getResNo() == 0)
12888 case X86ISD::SETCC:
12889 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
12891 case ISD::INTRINSIC_WO_CHAIN: {
12892 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12893 unsigned NumLoBits = 0;
12896 case Intrinsic::x86_sse_movmsk_ps:
12897 case Intrinsic::x86_avx_movmsk_ps_256:
12898 case Intrinsic::x86_sse2_movmsk_pd:
12899 case Intrinsic::x86_avx_movmsk_pd_256:
12900 case Intrinsic::x86_mmx_pmovmskb:
12901 case Intrinsic::x86_sse2_pmovmskb_128:
12902 case Intrinsic::x86_avx2_pmovmskb: {
12903 // High bits of movmskp{s|d}, pmovmskb are known zero.
12905 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12906 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
12907 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
12908 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
12909 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
12910 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
12911 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
12912 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
12914 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
12923 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12924 unsigned Depth) const {
12925 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12926 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12927 return Op.getValueType().getScalarType().getSizeInBits();
12933 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12934 /// node is a GlobalAddress + offset.
12935 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12936 const GlobalValue* &GA,
12937 int64_t &Offset) const {
12938 if (N->getOpcode() == X86ISD::Wrapper) {
12939 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12940 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12941 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12945 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12948 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12949 /// same as extracting the high 128-bit part of 256-bit vector and then
12950 /// inserting the result into the low part of a new 256-bit vector
12951 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12952 EVT VT = SVOp->getValueType(0);
12953 unsigned NumElems = VT.getVectorNumElements();
12955 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12956 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
12957 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12958 SVOp->getMaskElt(j) >= 0)
12964 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
12965 /// same as extracting the low 128-bit part of 256-bit vector and then
12966 /// inserting the result into the high part of a new 256-bit vector
12967 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
12968 EVT VT = SVOp->getValueType(0);
12969 unsigned NumElems = VT.getVectorNumElements();
12971 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12972 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
12973 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12974 SVOp->getMaskElt(j) >= 0)
12980 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
12981 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
12982 TargetLowering::DAGCombinerInfo &DCI,
12983 const X86Subtarget* Subtarget) {
12984 DebugLoc dl = N->getDebugLoc();
12985 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
12986 SDValue V1 = SVOp->getOperand(0);
12987 SDValue V2 = SVOp->getOperand(1);
12988 EVT VT = SVOp->getValueType(0);
12989 unsigned NumElems = VT.getVectorNumElements();
12991 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
12992 V2.getOpcode() == ISD::CONCAT_VECTORS) {
12996 // V UNDEF BUILD_VECTOR UNDEF
12998 // CONCAT_VECTOR CONCAT_VECTOR
13001 // RESULT: V + zero extended
13003 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
13004 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
13005 V1.getOperand(1).getOpcode() != ISD::UNDEF)
13008 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
13011 // To match the shuffle mask, the first half of the mask should
13012 // be exactly the first vector, and all the rest a splat with the
13013 // first element of the second one.
13014 for (unsigned i = 0; i != NumElems/2; ++i)
13015 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
13016 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
13019 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
13020 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
13021 if (Ld->hasNUsesOfValue(1, 0)) {
13022 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
13023 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
13025 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
13027 Ld->getPointerInfo(),
13028 Ld->getAlignment(),
13029 false/*isVolatile*/, true/*ReadMem*/,
13030 false/*WriteMem*/);
13031 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
13035 // Emit a zeroed vector and insert the desired subvector on its
13037 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
13038 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
13039 return DCI.CombineTo(N, InsV);
13042 //===--------------------------------------------------------------------===//
13043 // Combine some shuffles into subvector extracts and inserts:
13046 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
13047 if (isShuffleHigh128VectorInsertLow(SVOp)) {
13048 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
13049 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
13050 return DCI.CombineTo(N, InsV);
13053 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
13054 if (isShuffleLow128VectorInsertHigh(SVOp)) {
13055 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
13056 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
13057 return DCI.CombineTo(N, InsV);
13063 /// PerformShuffleCombine - Performs several different shuffle combines.
13064 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
13065 TargetLowering::DAGCombinerInfo &DCI,
13066 const X86Subtarget *Subtarget) {
13067 DebugLoc dl = N->getDebugLoc();
13068 EVT VT = N->getValueType(0);
13070 // Don't create instructions with illegal types after legalize types has run.
13071 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13072 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
13075 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
13076 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
13077 N->getOpcode() == ISD::VECTOR_SHUFFLE)
13078 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
13080 // Only handle 128 wide vector from here on.
13081 if (VT.getSizeInBits() != 128)
13084 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
13085 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
13086 // consecutive, non-overlapping, and in the right order.
13087 SmallVector<SDValue, 16> Elts;
13088 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
13089 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
13091 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
13095 /// DCI, PerformTruncateCombine - Converts truncate operation to
13096 /// a sequence of vector shuffle operations.
13097 /// It is possible when we truncate 256-bit vector to 128-bit vector
13099 SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
13100 DAGCombinerInfo &DCI) const {
13101 if (!DCI.isBeforeLegalizeOps())
13104 if (!Subtarget->hasAVX())
13107 EVT VT = N->getValueType(0);
13108 SDValue Op = N->getOperand(0);
13109 EVT OpVT = Op.getValueType();
13110 DebugLoc dl = N->getDebugLoc();
13112 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) {
13114 if (Subtarget->hasAVX2()) {
13115 // AVX2: v4i64 -> v4i32
13118 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13120 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v8i32, Op);
13121 Op = DAG.getVectorShuffle(MVT::v8i32, dl, Op, DAG.getUNDEF(MVT::v8i32),
13124 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Op,
13125 DAG.getIntPtrConstant(0));
13128 // AVX: v4i64 -> v4i32
13129 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13130 DAG.getIntPtrConstant(0));
13132 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13133 DAG.getIntPtrConstant(2));
13135 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13136 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13139 static const int ShufMask1[] = {0, 2, 0, 0};
13141 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, DAG.getUNDEF(VT), ShufMask1);
13142 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, DAG.getUNDEF(VT), ShufMask1);
13145 static const int ShufMask2[] = {0, 1, 4, 5};
13147 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2);
13150 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) {
13152 if (Subtarget->hasAVX2()) {
13153 // AVX2: v8i32 -> v8i16
13155 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v32i8, Op);
13158 SmallVector<SDValue,32> pshufbMask;
13159 for (unsigned i = 0; i < 2; ++i) {
13160 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13161 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13162 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13163 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13164 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13165 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13166 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13167 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13168 for (unsigned j = 0; j < 8; ++j)
13169 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13171 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v32i8,
13172 &pshufbMask[0], 32);
13173 Op = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, Op, BV);
13175 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i64, Op);
13177 static const int ShufMask[] = {0, 2, -1, -1};
13178 Op = DAG.getVectorShuffle(MVT::v4i64, dl, Op, DAG.getUNDEF(MVT::v4i64),
13181 Op = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13182 DAG.getIntPtrConstant(0));
13184 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
13187 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13188 DAG.getIntPtrConstant(0));
13190 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13191 DAG.getIntPtrConstant(4));
13193 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo);
13194 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi);
13197 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13198 -1, -1, -1, -1, -1, -1, -1, -1};
13200 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo, DAG.getUNDEF(MVT::v16i8),
13202 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi, DAG.getUNDEF(MVT::v16i8),
13205 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13206 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13209 static const int ShufMask2[] = {0, 1, 4, 5};
13211 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2);
13212 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res);
13218 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
13219 /// specific shuffle of a load can be folded into a single element load.
13220 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
13221 /// shuffles have been customed lowered so we need to handle those here.
13222 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
13223 TargetLowering::DAGCombinerInfo &DCI) {
13224 if (DCI.isBeforeLegalizeOps())
13227 SDValue InVec = N->getOperand(0);
13228 SDValue EltNo = N->getOperand(1);
13230 if (!isa<ConstantSDNode>(EltNo))
13233 EVT VT = InVec.getValueType();
13235 bool HasShuffleIntoBitcast = false;
13236 if (InVec.getOpcode() == ISD::BITCAST) {
13237 // Don't duplicate a load with other uses.
13238 if (!InVec.hasOneUse())
13240 EVT BCVT = InVec.getOperand(0).getValueType();
13241 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
13243 InVec = InVec.getOperand(0);
13244 HasShuffleIntoBitcast = true;
13247 if (!isTargetShuffle(InVec.getOpcode()))
13250 // Don't duplicate a load with other uses.
13251 if (!InVec.hasOneUse())
13254 SmallVector<int, 16> ShuffleMask;
13256 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
13260 // Select the input vector, guarding against out of range extract vector.
13261 unsigned NumElems = VT.getVectorNumElements();
13262 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
13263 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
13264 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
13265 : InVec.getOperand(1);
13267 // If inputs to shuffle are the same for both ops, then allow 2 uses
13268 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
13270 if (LdNode.getOpcode() == ISD::BITCAST) {
13271 // Don't duplicate a load with other uses.
13272 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
13275 AllowedUses = 1; // only allow 1 load use if we have a bitcast
13276 LdNode = LdNode.getOperand(0);
13279 if (!ISD::isNormalLoad(LdNode.getNode()))
13282 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
13284 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
13287 if (HasShuffleIntoBitcast) {
13288 // If there's a bitcast before the shuffle, check if the load type and
13289 // alignment is valid.
13290 unsigned Align = LN0->getAlignment();
13291 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13292 unsigned NewAlign = TLI.getTargetData()->
13293 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
13295 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
13299 // All checks match so transform back to vector_shuffle so that DAG combiner
13300 // can finish the job
13301 DebugLoc dl = N->getDebugLoc();
13303 // Create shuffle node taking into account the case that its a unary shuffle
13304 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
13305 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
13306 InVec.getOperand(0), Shuffle,
13308 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
13309 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
13313 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
13314 /// generation and convert it from being a bunch of shuffles and extracts
13315 /// to a simple store and scalar loads to extract the elements.
13316 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
13317 TargetLowering::DAGCombinerInfo &DCI) {
13318 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
13319 if (NewOp.getNode())
13322 SDValue InputVector = N->getOperand(0);
13324 // Only operate on vectors of 4 elements, where the alternative shuffling
13325 // gets to be more expensive.
13326 if (InputVector.getValueType() != MVT::v4i32)
13329 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
13330 // single use which is a sign-extend or zero-extend, and all elements are
13332 SmallVector<SDNode *, 4> Uses;
13333 unsigned ExtractedElements = 0;
13334 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
13335 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
13336 if (UI.getUse().getResNo() != InputVector.getResNo())
13339 SDNode *Extract = *UI;
13340 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13343 if (Extract->getValueType(0) != MVT::i32)
13345 if (!Extract->hasOneUse())
13347 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
13348 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
13350 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
13353 // Record which element was extracted.
13354 ExtractedElements |=
13355 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
13357 Uses.push_back(Extract);
13360 // If not all the elements were used, this may not be worthwhile.
13361 if (ExtractedElements != 15)
13364 // Ok, we've now decided to do the transformation.
13365 DebugLoc dl = InputVector.getDebugLoc();
13367 // Store the value to a temporary stack slot.
13368 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
13369 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
13370 MachinePointerInfo(), false, false, 0);
13372 // Replace each use (extract) with a load of the appropriate element.
13373 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
13374 UE = Uses.end(); UI != UE; ++UI) {
13375 SDNode *Extract = *UI;
13377 // cOMpute the element's address.
13378 SDValue Idx = Extract->getOperand(1);
13380 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
13381 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
13382 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13383 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
13385 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
13386 StackPtr, OffsetVal);
13388 // Load the scalar.
13389 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
13390 ScalarAddr, MachinePointerInfo(),
13391 false, false, false, 0);
13393 // Replace the exact with the load.
13394 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
13397 // The replacement was made in place; don't return anything.
13401 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
13403 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
13404 TargetLowering::DAGCombinerInfo &DCI,
13405 const X86Subtarget *Subtarget) {
13406 DebugLoc DL = N->getDebugLoc();
13407 SDValue Cond = N->getOperand(0);
13408 // Get the LHS/RHS of the select.
13409 SDValue LHS = N->getOperand(1);
13410 SDValue RHS = N->getOperand(2);
13411 EVT VT = LHS.getValueType();
13413 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
13414 // instructions match the semantics of the common C idiom x<y?x:y but not
13415 // x<=y?x:y, because of how they handle negative zero (which can be
13416 // ignored in unsafe-math mode).
13417 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
13418 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
13419 (Subtarget->hasSSE2() ||
13420 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
13421 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13423 unsigned Opcode = 0;
13424 // Check for x CC y ? x : y.
13425 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13426 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13430 // Converting this to a min would handle NaNs incorrectly, and swapping
13431 // the operands would cause it to handle comparisons between positive
13432 // and negative zero incorrectly.
13433 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13434 if (!DAG.getTarget().Options.UnsafeFPMath &&
13435 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13437 std::swap(LHS, RHS);
13439 Opcode = X86ISD::FMIN;
13442 // Converting this to a min would handle comparisons between positive
13443 // and negative zero incorrectly.
13444 if (!DAG.getTarget().Options.UnsafeFPMath &&
13445 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13447 Opcode = X86ISD::FMIN;
13450 // Converting this to a min would handle both negative zeros and NaNs
13451 // incorrectly, but we can swap the operands to fix both.
13452 std::swap(LHS, RHS);
13456 Opcode = X86ISD::FMIN;
13460 // Converting this to a max would handle comparisons between positive
13461 // and negative zero incorrectly.
13462 if (!DAG.getTarget().Options.UnsafeFPMath &&
13463 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13465 Opcode = X86ISD::FMAX;
13468 // Converting this to a max would handle NaNs incorrectly, and swapping
13469 // the operands would cause it to handle comparisons between positive
13470 // and negative zero incorrectly.
13471 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13472 if (!DAG.getTarget().Options.UnsafeFPMath &&
13473 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13475 std::swap(LHS, RHS);
13477 Opcode = X86ISD::FMAX;
13480 // Converting this to a max would handle both negative zeros and NaNs
13481 // incorrectly, but we can swap the operands to fix both.
13482 std::swap(LHS, RHS);
13486 Opcode = X86ISD::FMAX;
13489 // Check for x CC y ? y : x -- a min/max with reversed arms.
13490 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
13491 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
13495 // Converting this to a min would handle comparisons between positive
13496 // and negative zero incorrectly, and swapping the operands would
13497 // cause it to handle NaNs incorrectly.
13498 if (!DAG.getTarget().Options.UnsafeFPMath &&
13499 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
13500 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13502 std::swap(LHS, RHS);
13504 Opcode = X86ISD::FMIN;
13507 // Converting this to a min would handle NaNs incorrectly.
13508 if (!DAG.getTarget().Options.UnsafeFPMath &&
13509 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
13511 Opcode = X86ISD::FMIN;
13514 // Converting this to a min would handle both negative zeros and NaNs
13515 // incorrectly, but we can swap the operands to fix both.
13516 std::swap(LHS, RHS);
13520 Opcode = X86ISD::FMIN;
13524 // Converting this to a max would handle NaNs incorrectly.
13525 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13527 Opcode = X86ISD::FMAX;
13530 // Converting this to a max would handle comparisons between positive
13531 // and negative zero incorrectly, and swapping the operands would
13532 // cause it to handle NaNs incorrectly.
13533 if (!DAG.getTarget().Options.UnsafeFPMath &&
13534 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
13535 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13537 std::swap(LHS, RHS);
13539 Opcode = X86ISD::FMAX;
13542 // Converting this to a max would handle both negative zeros and NaNs
13543 // incorrectly, but we can swap the operands to fix both.
13544 std::swap(LHS, RHS);
13548 Opcode = X86ISD::FMAX;
13554 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
13557 // If this is a select between two integer constants, try to do some
13559 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
13560 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
13561 // Don't do this for crazy integer types.
13562 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
13563 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
13564 // so that TrueC (the true value) is larger than FalseC.
13565 bool NeedsCondInvert = false;
13567 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
13568 // Efficiently invertible.
13569 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
13570 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
13571 isa<ConstantSDNode>(Cond.getOperand(1))))) {
13572 NeedsCondInvert = true;
13573 std::swap(TrueC, FalseC);
13576 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
13577 if (FalseC->getAPIntValue() == 0 &&
13578 TrueC->getAPIntValue().isPowerOf2()) {
13579 if (NeedsCondInvert) // Invert the condition if needed.
13580 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13581 DAG.getConstant(1, Cond.getValueType()));
13583 // Zero extend the condition if needed.
13584 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
13586 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13587 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
13588 DAG.getConstant(ShAmt, MVT::i8));
13591 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
13592 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13593 if (NeedsCondInvert) // Invert the condition if needed.
13594 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13595 DAG.getConstant(1, Cond.getValueType()));
13597 // Zero extend the condition if needed.
13598 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13599 FalseC->getValueType(0), Cond);
13600 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13601 SDValue(FalseC, 0));
13604 // Optimize cases that will turn into an LEA instruction. This requires
13605 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13606 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13607 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13608 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13610 bool isFastMultiplier = false;
13612 switch ((unsigned char)Diff) {
13614 case 1: // result = add base, cond
13615 case 2: // result = lea base( , cond*2)
13616 case 3: // result = lea base(cond, cond*2)
13617 case 4: // result = lea base( , cond*4)
13618 case 5: // result = lea base(cond, cond*4)
13619 case 8: // result = lea base( , cond*8)
13620 case 9: // result = lea base(cond, cond*8)
13621 isFastMultiplier = true;
13626 if (isFastMultiplier) {
13627 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13628 if (NeedsCondInvert) // Invert the condition if needed.
13629 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13630 DAG.getConstant(1, Cond.getValueType()));
13632 // Zero extend the condition if needed.
13633 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13635 // Scale the condition by the difference.
13637 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13638 DAG.getConstant(Diff, Cond.getValueType()));
13640 // Add the base if non-zero.
13641 if (FalseC->getAPIntValue() != 0)
13642 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13643 SDValue(FalseC, 0));
13650 // Canonicalize max and min:
13651 // (x > y) ? x : y -> (x >= y) ? x : y
13652 // (x < y) ? x : y -> (x <= y) ? x : y
13653 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
13654 // the need for an extra compare
13655 // against zero. e.g.
13656 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
13658 // testl %edi, %edi
13660 // cmovgl %edi, %eax
13664 // cmovsl %eax, %edi
13665 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
13666 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13667 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13668 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13673 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
13674 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(),
13675 Cond.getOperand(0), Cond.getOperand(1), NewCC);
13676 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
13681 // If we know that this node is legal then we know that it is going to be
13682 // matched by one of the SSE/AVX BLEND instructions. These instructions only
13683 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
13684 // to simplify previous instructions.
13685 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13686 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
13687 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
13688 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
13690 // Don't optimize vector selects that map to mask-registers.
13694 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
13695 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
13697 APInt KnownZero, KnownOne;
13698 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
13699 DCI.isBeforeLegalizeOps());
13700 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
13701 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
13702 DCI.CommitTargetLoweringOpt(TLO);
13708 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
13709 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
13710 TargetLowering::DAGCombinerInfo &DCI) {
13711 DebugLoc DL = N->getDebugLoc();
13713 // If the flag operand isn't dead, don't touch this CMOV.
13714 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
13717 SDValue FalseOp = N->getOperand(0);
13718 SDValue TrueOp = N->getOperand(1);
13719 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
13720 SDValue Cond = N->getOperand(3);
13721 if (CC == X86::COND_E || CC == X86::COND_NE) {
13722 switch (Cond.getOpcode()) {
13726 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
13727 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
13728 return (CC == X86::COND_E) ? FalseOp : TrueOp;
13732 // If this is a select between two integer constants, try to do some
13733 // optimizations. Note that the operands are ordered the opposite of SELECT
13735 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
13736 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
13737 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
13738 // larger than FalseC (the false value).
13739 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
13740 CC = X86::GetOppositeBranchCondition(CC);
13741 std::swap(TrueC, FalseC);
13744 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
13745 // This is efficient for any integer data type (including i8/i16) and
13747 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
13748 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13749 DAG.getConstant(CC, MVT::i8), Cond);
13751 // Zero extend the condition if needed.
13752 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
13754 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13755 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
13756 DAG.getConstant(ShAmt, MVT::i8));
13757 if (N->getNumValues() == 2) // Dead flag value?
13758 return DCI.CombineTo(N, Cond, SDValue());
13762 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
13763 // for any integer data type, including i8/i16.
13764 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13765 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13766 DAG.getConstant(CC, MVT::i8), Cond);
13768 // Zero extend the condition if needed.
13769 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13770 FalseC->getValueType(0), Cond);
13771 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13772 SDValue(FalseC, 0));
13774 if (N->getNumValues() == 2) // Dead flag value?
13775 return DCI.CombineTo(N, Cond, SDValue());
13779 // Optimize cases that will turn into an LEA instruction. This requires
13780 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13781 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13782 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13783 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13785 bool isFastMultiplier = false;
13787 switch ((unsigned char)Diff) {
13789 case 1: // result = add base, cond
13790 case 2: // result = lea base( , cond*2)
13791 case 3: // result = lea base(cond, cond*2)
13792 case 4: // result = lea base( , cond*4)
13793 case 5: // result = lea base(cond, cond*4)
13794 case 8: // result = lea base( , cond*8)
13795 case 9: // result = lea base(cond, cond*8)
13796 isFastMultiplier = true;
13801 if (isFastMultiplier) {
13802 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13803 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13804 DAG.getConstant(CC, MVT::i8), Cond);
13805 // Zero extend the condition if needed.
13806 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13808 // Scale the condition by the difference.
13810 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13811 DAG.getConstant(Diff, Cond.getValueType()));
13813 // Add the base if non-zero.
13814 if (FalseC->getAPIntValue() != 0)
13815 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13816 SDValue(FalseC, 0));
13817 if (N->getNumValues() == 2) // Dead flag value?
13818 return DCI.CombineTo(N, Cond, SDValue());
13828 /// PerformMulCombine - Optimize a single multiply with constant into two
13829 /// in order to implement it with two cheaper instructions, e.g.
13830 /// LEA + SHL, LEA + LEA.
13831 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
13832 TargetLowering::DAGCombinerInfo &DCI) {
13833 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
13836 EVT VT = N->getValueType(0);
13837 if (VT != MVT::i64)
13840 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
13843 uint64_t MulAmt = C->getZExtValue();
13844 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
13847 uint64_t MulAmt1 = 0;
13848 uint64_t MulAmt2 = 0;
13849 if ((MulAmt % 9) == 0) {
13851 MulAmt2 = MulAmt / 9;
13852 } else if ((MulAmt % 5) == 0) {
13854 MulAmt2 = MulAmt / 5;
13855 } else if ((MulAmt % 3) == 0) {
13857 MulAmt2 = MulAmt / 3;
13860 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
13861 DebugLoc DL = N->getDebugLoc();
13863 if (isPowerOf2_64(MulAmt2) &&
13864 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
13865 // If second multiplifer is pow2, issue it first. We want the multiply by
13866 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
13868 std::swap(MulAmt1, MulAmt2);
13871 if (isPowerOf2_64(MulAmt1))
13872 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
13873 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
13875 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
13876 DAG.getConstant(MulAmt1, VT));
13878 if (isPowerOf2_64(MulAmt2))
13879 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
13880 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
13882 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
13883 DAG.getConstant(MulAmt2, VT));
13885 // Do not add new nodes to DAG combiner worklist.
13886 DCI.CombineTo(N, NewMul, false);
13891 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
13892 SDValue N0 = N->getOperand(0);
13893 SDValue N1 = N->getOperand(1);
13894 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
13895 EVT VT = N0.getValueType();
13897 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
13898 // since the result of setcc_c is all zero's or all ones.
13899 if (VT.isInteger() && !VT.isVector() &&
13900 N1C && N0.getOpcode() == ISD::AND &&
13901 N0.getOperand(1).getOpcode() == ISD::Constant) {
13902 SDValue N00 = N0.getOperand(0);
13903 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
13904 ((N00.getOpcode() == ISD::ANY_EXTEND ||
13905 N00.getOpcode() == ISD::ZERO_EXTEND) &&
13906 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
13907 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
13908 APInt ShAmt = N1C->getAPIntValue();
13909 Mask = Mask.shl(ShAmt);
13911 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
13912 N00, DAG.getConstant(Mask, VT));
13917 // Hardware support for vector shifts is sparse which makes us scalarize the
13918 // vector operations in many cases. Also, on sandybridge ADD is faster than
13920 // (shl V, 1) -> add V,V
13921 if (isSplatVector(N1.getNode())) {
13922 assert(N0.getValueType().isVector() && "Invalid vector shift type");
13923 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
13924 // We shift all of the values by one. In many cases we do not have
13925 // hardware support for this operation. This is better expressed as an ADD
13927 if (N1C && (1 == N1C->getZExtValue())) {
13928 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
13935 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
13937 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
13938 TargetLowering::DAGCombinerInfo &DCI,
13939 const X86Subtarget *Subtarget) {
13940 EVT VT = N->getValueType(0);
13941 if (N->getOpcode() == ISD::SHL) {
13942 SDValue V = PerformSHLCombine(N, DAG);
13943 if (V.getNode()) return V;
13946 // On X86 with SSE2 support, we can transform this to a vector shift if
13947 // all elements are shifted by the same amount. We can't do this in legalize
13948 // because the a constant vector is typically transformed to a constant pool
13949 // so we have no knowledge of the shift amount.
13950 if (!Subtarget->hasSSE2())
13953 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
13954 (!Subtarget->hasAVX2() ||
13955 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
13958 SDValue ShAmtOp = N->getOperand(1);
13959 EVT EltVT = VT.getVectorElementType();
13960 DebugLoc DL = N->getDebugLoc();
13961 SDValue BaseShAmt = SDValue();
13962 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
13963 unsigned NumElts = VT.getVectorNumElements();
13965 for (; i != NumElts; ++i) {
13966 SDValue Arg = ShAmtOp.getOperand(i);
13967 if (Arg.getOpcode() == ISD::UNDEF) continue;
13971 // Handle the case where the build_vector is all undef
13972 // FIXME: Should DAG allow this?
13976 for (; i != NumElts; ++i) {
13977 SDValue Arg = ShAmtOp.getOperand(i);
13978 if (Arg.getOpcode() == ISD::UNDEF) continue;
13979 if (Arg != BaseShAmt) {
13983 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
13984 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
13985 SDValue InVec = ShAmtOp.getOperand(0);
13986 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13987 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13989 for (; i != NumElts; ++i) {
13990 SDValue Arg = InVec.getOperand(i);
13991 if (Arg.getOpcode() == ISD::UNDEF) continue;
13995 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13996 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13997 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
13998 if (C->getZExtValue() == SplatIdx)
13999 BaseShAmt = InVec.getOperand(1);
14002 if (BaseShAmt.getNode() == 0) {
14003 // Don't create instructions with illegal types after legalize
14005 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) &&
14006 !DCI.isBeforeLegalize())
14009 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
14010 DAG.getIntPtrConstant(0));
14015 // The shift amount is an i32.
14016 if (EltVT.bitsGT(MVT::i32))
14017 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
14018 else if (EltVT.bitsLT(MVT::i32))
14019 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
14021 // The shift amount is identical so we can do a vector shift.
14022 SDValue ValOp = N->getOperand(0);
14023 switch (N->getOpcode()) {
14025 llvm_unreachable("Unknown shift opcode!");
14027 switch (VT.getSimpleVT().SimpleTy) {
14028 default: return SDValue();
14035 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG);
14038 switch (VT.getSimpleVT().SimpleTy) {
14039 default: return SDValue();
14044 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG);
14047 switch (VT.getSimpleVT().SimpleTy) {
14048 default: return SDValue();
14055 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG);
14061 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
14062 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
14063 // and friends. Likewise for OR -> CMPNEQSS.
14064 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
14065 TargetLowering::DAGCombinerInfo &DCI,
14066 const X86Subtarget *Subtarget) {
14069 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
14070 // we're requiring SSE2 for both.
14071 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
14072 SDValue N0 = N->getOperand(0);
14073 SDValue N1 = N->getOperand(1);
14074 SDValue CMP0 = N0->getOperand(1);
14075 SDValue CMP1 = N1->getOperand(1);
14076 DebugLoc DL = N->getDebugLoc();
14078 // The SETCCs should both refer to the same CMP.
14079 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
14082 SDValue CMP00 = CMP0->getOperand(0);
14083 SDValue CMP01 = CMP0->getOperand(1);
14084 EVT VT = CMP00.getValueType();
14086 if (VT == MVT::f32 || VT == MVT::f64) {
14087 bool ExpectingFlags = false;
14088 // Check for any users that want flags:
14089 for (SDNode::use_iterator UI = N->use_begin(),
14091 !ExpectingFlags && UI != UE; ++UI)
14092 switch (UI->getOpcode()) {
14097 ExpectingFlags = true;
14099 case ISD::CopyToReg:
14100 case ISD::SIGN_EXTEND:
14101 case ISD::ZERO_EXTEND:
14102 case ISD::ANY_EXTEND:
14106 if (!ExpectingFlags) {
14107 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
14108 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
14110 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
14111 X86::CondCode tmp = cc0;
14116 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
14117 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
14118 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
14119 X86ISD::NodeType NTOperator = is64BitFP ?
14120 X86ISD::FSETCCsd : X86ISD::FSETCCss;
14121 // FIXME: need symbolic constants for these magic numbers.
14122 // See X86ATTInstPrinter.cpp:printSSECC().
14123 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
14124 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
14125 DAG.getConstant(x86cc, MVT::i8));
14126 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
14128 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
14129 DAG.getConstant(1, MVT::i32));
14130 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
14131 return OneBitOfTruth;
14139 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
14140 /// so it can be folded inside ANDNP.
14141 static bool CanFoldXORWithAllOnes(const SDNode *N) {
14142 EVT VT = N->getValueType(0);
14144 // Match direct AllOnes for 128 and 256-bit vectors
14145 if (ISD::isBuildVectorAllOnes(N))
14148 // Look through a bit convert.
14149 if (N->getOpcode() == ISD::BITCAST)
14150 N = N->getOperand(0).getNode();
14152 // Sometimes the operand may come from a insert_subvector building a 256-bit
14154 if (VT.getSizeInBits() == 256 &&
14155 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
14156 SDValue V1 = N->getOperand(0);
14157 SDValue V2 = N->getOperand(1);
14159 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
14160 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
14161 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
14162 ISD::isBuildVectorAllOnes(V2.getNode()))
14169 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
14170 TargetLowering::DAGCombinerInfo &DCI,
14171 const X86Subtarget *Subtarget) {
14172 if (DCI.isBeforeLegalizeOps())
14175 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
14179 EVT VT = N->getValueType(0);
14181 // Create ANDN, BLSI, and BLSR instructions
14182 // BLSI is X & (-X)
14183 // BLSR is X & (X-1)
14184 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
14185 SDValue N0 = N->getOperand(0);
14186 SDValue N1 = N->getOperand(1);
14187 DebugLoc DL = N->getDebugLoc();
14189 // Check LHS for not
14190 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1)))
14191 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1);
14192 // Check RHS for not
14193 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1)))
14194 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0);
14196 // Check LHS for neg
14197 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
14198 isZero(N0.getOperand(0)))
14199 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
14201 // Check RHS for neg
14202 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
14203 isZero(N1.getOperand(0)))
14204 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
14206 // Check LHS for X-1
14207 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14208 isAllOnes(N0.getOperand(1)))
14209 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
14211 // Check RHS for X-1
14212 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14213 isAllOnes(N1.getOperand(1)))
14214 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
14219 // Want to form ANDNP nodes:
14220 // 1) In the hopes of then easily combining them with OR and AND nodes
14221 // to form PBLEND/PSIGN.
14222 // 2) To match ANDN packed intrinsics
14223 if (VT != MVT::v2i64 && VT != MVT::v4i64)
14226 SDValue N0 = N->getOperand(0);
14227 SDValue N1 = N->getOperand(1);
14228 DebugLoc DL = N->getDebugLoc();
14230 // Check LHS for vnot
14231 if (N0.getOpcode() == ISD::XOR &&
14232 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
14233 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
14234 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
14236 // Check RHS for vnot
14237 if (N1.getOpcode() == ISD::XOR &&
14238 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
14239 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
14240 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
14245 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
14246 TargetLowering::DAGCombinerInfo &DCI,
14247 const X86Subtarget *Subtarget) {
14248 if (DCI.isBeforeLegalizeOps())
14251 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
14255 EVT VT = N->getValueType(0);
14257 SDValue N0 = N->getOperand(0);
14258 SDValue N1 = N->getOperand(1);
14260 // look for psign/blend
14261 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
14262 if (!Subtarget->hasSSSE3() ||
14263 (VT == MVT::v4i64 && !Subtarget->hasAVX2()))
14266 // Canonicalize pandn to RHS
14267 if (N0.getOpcode() == X86ISD::ANDNP)
14269 // or (and (m, y), (pandn m, x))
14270 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
14271 SDValue Mask = N1.getOperand(0);
14272 SDValue X = N1.getOperand(1);
14274 if (N0.getOperand(0) == Mask)
14275 Y = N0.getOperand(1);
14276 if (N0.getOperand(1) == Mask)
14277 Y = N0.getOperand(0);
14279 // Check to see if the mask appeared in both the AND and ANDNP and
14283 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
14284 // Look through mask bitcast.
14285 if (Mask.getOpcode() == ISD::BITCAST)
14286 Mask = Mask.getOperand(0);
14287 if (X.getOpcode() == ISD::BITCAST)
14288 X = X.getOperand(0);
14289 if (Y.getOpcode() == ISD::BITCAST)
14290 Y = Y.getOperand(0);
14292 EVT MaskVT = Mask.getValueType();
14294 // Validate that the Mask operand is a vector sra node.
14295 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
14296 // there is no psrai.b
14297 if (Mask.getOpcode() != X86ISD::VSRAI)
14300 // Check that the SRA is all signbits.
14301 SDValue SraC = Mask.getOperand(1);
14302 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
14303 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
14304 if ((SraAmt + 1) != EltBits)
14307 DebugLoc DL = N->getDebugLoc();
14309 // Now we know we at least have a plendvb with the mask val. See if
14310 // we can form a psignb/w/d.
14311 // psign = x.type == y.type == mask.type && y = sub(0, x);
14312 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
14313 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
14314 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
14315 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
14316 "Unsupported VT for PSIGN");
14317 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
14318 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14320 // PBLENDVB only available on SSE 4.1
14321 if (!Subtarget->hasSSE41())
14324 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
14326 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
14327 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
14328 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
14329 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
14330 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14334 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
14337 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
14338 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
14340 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
14342 if (!N0.hasOneUse() || !N1.hasOneUse())
14345 SDValue ShAmt0 = N0.getOperand(1);
14346 if (ShAmt0.getValueType() != MVT::i8)
14348 SDValue ShAmt1 = N1.getOperand(1);
14349 if (ShAmt1.getValueType() != MVT::i8)
14351 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
14352 ShAmt0 = ShAmt0.getOperand(0);
14353 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
14354 ShAmt1 = ShAmt1.getOperand(0);
14356 DebugLoc DL = N->getDebugLoc();
14357 unsigned Opc = X86ISD::SHLD;
14358 SDValue Op0 = N0.getOperand(0);
14359 SDValue Op1 = N1.getOperand(0);
14360 if (ShAmt0.getOpcode() == ISD::SUB) {
14361 Opc = X86ISD::SHRD;
14362 std::swap(Op0, Op1);
14363 std::swap(ShAmt0, ShAmt1);
14366 unsigned Bits = VT.getSizeInBits();
14367 if (ShAmt1.getOpcode() == ISD::SUB) {
14368 SDValue Sum = ShAmt1.getOperand(0);
14369 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
14370 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
14371 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
14372 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
14373 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
14374 return DAG.getNode(Opc, DL, VT,
14376 DAG.getNode(ISD::TRUNCATE, DL,
14379 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
14380 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
14382 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
14383 return DAG.getNode(Opc, DL, VT,
14384 N0.getOperand(0), N1.getOperand(0),
14385 DAG.getNode(ISD::TRUNCATE, DL,
14392 // Generate NEG and CMOV for integer abs.
14393 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
14394 EVT VT = N->getValueType(0);
14396 // Since X86 does not have CMOV for 8-bit integer, we don't convert
14397 // 8-bit integer abs to NEG and CMOV.
14398 if (VT.isInteger() && VT.getSizeInBits() == 8)
14401 SDValue N0 = N->getOperand(0);
14402 SDValue N1 = N->getOperand(1);
14403 DebugLoc DL = N->getDebugLoc();
14405 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
14406 // and change it to SUB and CMOV.
14407 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
14408 N0.getOpcode() == ISD::ADD &&
14409 N0.getOperand(1) == N1 &&
14410 N1.getOpcode() == ISD::SRA &&
14411 N1.getOperand(0) == N0.getOperand(0))
14412 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
14413 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
14414 // Generate SUB & CMOV.
14415 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
14416 DAG.getConstant(0, VT), N0.getOperand(0));
14418 SDValue Ops[] = { N0.getOperand(0), Neg,
14419 DAG.getConstant(X86::COND_GE, MVT::i8),
14420 SDValue(Neg.getNode(), 1) };
14421 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
14422 Ops, array_lengthof(Ops));
14427 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
14428 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
14429 TargetLowering::DAGCombinerInfo &DCI,
14430 const X86Subtarget *Subtarget) {
14431 if (DCI.isBeforeLegalizeOps())
14434 if (Subtarget->hasCMov()) {
14435 SDValue RV = performIntegerAbsCombine(N, DAG);
14440 // Try forming BMI if it is available.
14441 if (!Subtarget->hasBMI())
14444 EVT VT = N->getValueType(0);
14446 if (VT != MVT::i32 && VT != MVT::i64)
14449 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
14451 // Create BLSMSK instructions by finding X ^ (X-1)
14452 SDValue N0 = N->getOperand(0);
14453 SDValue N1 = N->getOperand(1);
14454 DebugLoc DL = N->getDebugLoc();
14456 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14457 isAllOnes(N0.getOperand(1)))
14458 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
14460 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14461 isAllOnes(N1.getOperand(1)))
14462 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
14467 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
14468 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
14469 TargetLowering::DAGCombinerInfo &DCI,
14470 const X86Subtarget *Subtarget) {
14471 LoadSDNode *Ld = cast<LoadSDNode>(N);
14472 EVT RegVT = Ld->getValueType(0);
14473 EVT MemVT = Ld->getMemoryVT();
14474 DebugLoc dl = Ld->getDebugLoc();
14475 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14477 ISD::LoadExtType Ext = Ld->getExtensionType();
14479 // If this is a vector EXT Load then attempt to optimize it using a
14480 // shuffle. We need SSE4 for the shuffles.
14481 // TODO: It is possible to support ZExt by zeroing the undef values
14482 // during the shuffle phase or after the shuffle.
14483 if (RegVT.isVector() && RegVT.isInteger() &&
14484 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
14485 assert(MemVT != RegVT && "Cannot extend to the same type");
14486 assert(MemVT.isVector() && "Must load a vector from memory");
14488 unsigned NumElems = RegVT.getVectorNumElements();
14489 unsigned RegSz = RegVT.getSizeInBits();
14490 unsigned MemSz = MemVT.getSizeInBits();
14491 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14493 // All sizes must be a power of two.
14494 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
14497 // Attempt to load the original value using scalar loads.
14498 // Find the largest scalar type that divides the total loaded size.
14499 MVT SclrLoadTy = MVT::i8;
14500 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14501 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14502 MVT Tp = (MVT::SimpleValueType)tp;
14503 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14508 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14509 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14511 SclrLoadTy = MVT::f64;
14513 // Calculate the number of scalar loads that we need to perform
14514 // in order to load our vector from memory.
14515 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14517 // Represent our vector as a sequence of elements which are the
14518 // largest scalar that we can load.
14519 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
14520 RegSz/SclrLoadTy.getSizeInBits());
14522 // Represent the data using the same element type that is stored in
14523 // memory. In practice, we ''widen'' MemVT.
14524 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14525 RegSz/MemVT.getScalarType().getSizeInBits());
14527 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14528 "Invalid vector type");
14530 // We can't shuffle using an illegal type.
14531 if (!TLI.isTypeLegal(WideVecVT))
14534 SmallVector<SDValue, 8> Chains;
14535 SDValue Ptr = Ld->getBasePtr();
14536 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
14537 TLI.getPointerTy());
14538 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14540 for (unsigned i = 0; i < NumLoads; ++i) {
14541 // Perform a single load.
14542 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
14543 Ptr, Ld->getPointerInfo(),
14544 Ld->isVolatile(), Ld->isNonTemporal(),
14545 Ld->isInvariant(), Ld->getAlignment());
14546 Chains.push_back(ScalarLoad.getValue(1));
14547 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14548 // another round of DAGCombining.
14550 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14552 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14553 ScalarLoad, DAG.getIntPtrConstant(i));
14555 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14558 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
14561 // Bitcast the loaded value to a vector of the original element type, in
14562 // the size of the target vector type.
14563 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
14564 unsigned SizeRatio = RegSz/MemSz;
14566 // Redistribute the loaded elements into the different locations.
14567 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14568 for (unsigned i = 0; i != NumElems; ++i)
14569 ShuffleVec[i*SizeRatio] = i;
14571 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14572 DAG.getUNDEF(WideVecVT),
14575 // Bitcast to the requested type.
14576 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14577 // Replace the original load with the new sequence
14578 // and return the new chain.
14579 return DCI.CombineTo(N, Shuff, TF, true);
14585 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
14586 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
14587 const X86Subtarget *Subtarget) {
14588 StoreSDNode *St = cast<StoreSDNode>(N);
14589 EVT VT = St->getValue().getValueType();
14590 EVT StVT = St->getMemoryVT();
14591 DebugLoc dl = St->getDebugLoc();
14592 SDValue StoredVal = St->getOperand(1);
14593 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14595 // If we are saving a concatenation of two XMM registers, perform two stores.
14596 // On Sandy Bridge, 256-bit memory operations are executed by two
14597 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
14598 // memory operation.
14599 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2() &&
14600 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
14601 StoredVal.getNumOperands() == 2) {
14602 SDValue Value0 = StoredVal.getOperand(0);
14603 SDValue Value1 = StoredVal.getOperand(1);
14605 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
14606 SDValue Ptr0 = St->getBasePtr();
14607 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
14609 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
14610 St->getPointerInfo(), St->isVolatile(),
14611 St->isNonTemporal(), St->getAlignment());
14612 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
14613 St->getPointerInfo(), St->isVolatile(),
14614 St->isNonTemporal(), St->getAlignment());
14615 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
14618 // Optimize trunc store (of multiple scalars) to shuffle and store.
14619 // First, pack all of the elements in one place. Next, store to memory
14620 // in fewer chunks.
14621 if (St->isTruncatingStore() && VT.isVector()) {
14622 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14623 unsigned NumElems = VT.getVectorNumElements();
14624 assert(StVT != VT && "Cannot truncate to the same type");
14625 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
14626 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
14628 // From, To sizes and ElemCount must be pow of two
14629 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
14630 // We are going to use the original vector elt for storing.
14631 // Accumulated smaller vector elements must be a multiple of the store size.
14632 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
14634 unsigned SizeRatio = FromSz / ToSz;
14636 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
14638 // Create a type on which we perform the shuffle
14639 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
14640 StVT.getScalarType(), NumElems*SizeRatio);
14642 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
14644 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
14645 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14646 for (unsigned i = 0; i != NumElems; ++i)
14647 ShuffleVec[i] = i * SizeRatio;
14649 // Can't shuffle using an illegal type.
14650 if (!TLI.isTypeLegal(WideVecVT))
14653 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
14654 DAG.getUNDEF(WideVecVT),
14656 // At this point all of the data is stored at the bottom of the
14657 // register. We now need to save it to mem.
14659 // Find the largest store unit
14660 MVT StoreType = MVT::i8;
14661 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14662 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14663 MVT Tp = (MVT::SimpleValueType)tp;
14664 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
14668 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14669 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
14670 (64 <= NumElems * ToSz))
14671 StoreType = MVT::f64;
14673 // Bitcast the original vector into a vector of store-size units
14674 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
14675 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
14676 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
14677 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
14678 SmallVector<SDValue, 8> Chains;
14679 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
14680 TLI.getPointerTy());
14681 SDValue Ptr = St->getBasePtr();
14683 // Perform one or more big stores into memory.
14684 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
14685 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
14686 StoreType, ShuffWide,
14687 DAG.getIntPtrConstant(i));
14688 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
14689 St->getPointerInfo(), St->isVolatile(),
14690 St->isNonTemporal(), St->getAlignment());
14691 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14692 Chains.push_back(Ch);
14695 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
14700 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
14701 // the FP state in cases where an emms may be missing.
14702 // A preferable solution to the general problem is to figure out the right
14703 // places to insert EMMS. This qualifies as a quick hack.
14705 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
14706 if (VT.getSizeInBits() != 64)
14709 const Function *F = DAG.getMachineFunction().getFunction();
14710 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
14711 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
14712 && Subtarget->hasSSE2();
14713 if ((VT.isVector() ||
14714 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
14715 isa<LoadSDNode>(St->getValue()) &&
14716 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
14717 St->getChain().hasOneUse() && !St->isVolatile()) {
14718 SDNode* LdVal = St->getValue().getNode();
14719 LoadSDNode *Ld = 0;
14720 int TokenFactorIndex = -1;
14721 SmallVector<SDValue, 8> Ops;
14722 SDNode* ChainVal = St->getChain().getNode();
14723 // Must be a store of a load. We currently handle two cases: the load
14724 // is a direct child, and it's under an intervening TokenFactor. It is
14725 // possible to dig deeper under nested TokenFactors.
14726 if (ChainVal == LdVal)
14727 Ld = cast<LoadSDNode>(St->getChain());
14728 else if (St->getValue().hasOneUse() &&
14729 ChainVal->getOpcode() == ISD::TokenFactor) {
14730 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
14731 if (ChainVal->getOperand(i).getNode() == LdVal) {
14732 TokenFactorIndex = i;
14733 Ld = cast<LoadSDNode>(St->getValue());
14735 Ops.push_back(ChainVal->getOperand(i));
14739 if (!Ld || !ISD::isNormalLoad(Ld))
14742 // If this is not the MMX case, i.e. we are just turning i64 load/store
14743 // into f64 load/store, avoid the transformation if there are multiple
14744 // uses of the loaded value.
14745 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
14748 DebugLoc LdDL = Ld->getDebugLoc();
14749 DebugLoc StDL = N->getDebugLoc();
14750 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
14751 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
14753 if (Subtarget->is64Bit() || F64IsLegal) {
14754 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
14755 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
14756 Ld->getPointerInfo(), Ld->isVolatile(),
14757 Ld->isNonTemporal(), Ld->isInvariant(),
14758 Ld->getAlignment());
14759 SDValue NewChain = NewLd.getValue(1);
14760 if (TokenFactorIndex != -1) {
14761 Ops.push_back(NewChain);
14762 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14765 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
14766 St->getPointerInfo(),
14767 St->isVolatile(), St->isNonTemporal(),
14768 St->getAlignment());
14771 // Otherwise, lower to two pairs of 32-bit loads / stores.
14772 SDValue LoAddr = Ld->getBasePtr();
14773 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
14774 DAG.getConstant(4, MVT::i32));
14776 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
14777 Ld->getPointerInfo(),
14778 Ld->isVolatile(), Ld->isNonTemporal(),
14779 Ld->isInvariant(), Ld->getAlignment());
14780 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
14781 Ld->getPointerInfo().getWithOffset(4),
14782 Ld->isVolatile(), Ld->isNonTemporal(),
14784 MinAlign(Ld->getAlignment(), 4));
14786 SDValue NewChain = LoLd.getValue(1);
14787 if (TokenFactorIndex != -1) {
14788 Ops.push_back(LoLd);
14789 Ops.push_back(HiLd);
14790 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14794 LoAddr = St->getBasePtr();
14795 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
14796 DAG.getConstant(4, MVT::i32));
14798 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
14799 St->getPointerInfo(),
14800 St->isVolatile(), St->isNonTemporal(),
14801 St->getAlignment());
14802 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
14803 St->getPointerInfo().getWithOffset(4),
14805 St->isNonTemporal(),
14806 MinAlign(St->getAlignment(), 4));
14807 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
14812 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
14813 /// and return the operands for the horizontal operation in LHS and RHS. A
14814 /// horizontal operation performs the binary operation on successive elements
14815 /// of its first operand, then on successive elements of its second operand,
14816 /// returning the resulting values in a vector. For example, if
14817 /// A = < float a0, float a1, float a2, float a3 >
14819 /// B = < float b0, float b1, float b2, float b3 >
14820 /// then the result of doing a horizontal operation on A and B is
14821 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
14822 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
14823 /// A horizontal-op B, for some already available A and B, and if so then LHS is
14824 /// set to A, RHS to B, and the routine returns 'true'.
14825 /// Note that the binary operation should have the property that if one of the
14826 /// operands is UNDEF then the result is UNDEF.
14827 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
14828 // Look for the following pattern: if
14829 // A = < float a0, float a1, float a2, float a3 >
14830 // B = < float b0, float b1, float b2, float b3 >
14832 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
14833 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
14834 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
14835 // which is A horizontal-op B.
14837 // At least one of the operands should be a vector shuffle.
14838 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
14839 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
14842 EVT VT = LHS.getValueType();
14844 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14845 "Unsupported vector type for horizontal add/sub");
14847 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
14848 // operate independently on 128-bit lanes.
14849 unsigned NumElts = VT.getVectorNumElements();
14850 unsigned NumLanes = VT.getSizeInBits()/128;
14851 unsigned NumLaneElts = NumElts / NumLanes;
14852 assert((NumLaneElts % 2 == 0) &&
14853 "Vector type should have an even number of elements in each lane");
14854 unsigned HalfLaneElts = NumLaneElts/2;
14856 // View LHS in the form
14857 // LHS = VECTOR_SHUFFLE A, B, LMask
14858 // If LHS is not a shuffle then pretend it is the shuffle
14859 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
14860 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
14863 SmallVector<int, 16> LMask(NumElts);
14864 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14865 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
14866 A = LHS.getOperand(0);
14867 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
14868 B = LHS.getOperand(1);
14869 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
14870 std::copy(Mask.begin(), Mask.end(), LMask.begin());
14872 if (LHS.getOpcode() != ISD::UNDEF)
14874 for (unsigned i = 0; i != NumElts; ++i)
14878 // Likewise, view RHS in the form
14879 // RHS = VECTOR_SHUFFLE C, D, RMask
14881 SmallVector<int, 16> RMask(NumElts);
14882 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14883 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
14884 C = RHS.getOperand(0);
14885 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
14886 D = RHS.getOperand(1);
14887 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
14888 std::copy(Mask.begin(), Mask.end(), RMask.begin());
14890 if (RHS.getOpcode() != ISD::UNDEF)
14892 for (unsigned i = 0; i != NumElts; ++i)
14896 // Check that the shuffles are both shuffling the same vectors.
14897 if (!(A == C && B == D) && !(A == D && B == C))
14900 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
14901 if (!A.getNode() && !B.getNode())
14904 // If A and B occur in reverse order in RHS, then "swap" them (which means
14905 // rewriting the mask).
14907 CommuteVectorShuffleMask(RMask, NumElts);
14909 // At this point LHS and RHS are equivalent to
14910 // LHS = VECTOR_SHUFFLE A, B, LMask
14911 // RHS = VECTOR_SHUFFLE A, B, RMask
14912 // Check that the masks correspond to performing a horizontal operation.
14913 for (unsigned i = 0; i != NumElts; ++i) {
14914 int LIdx = LMask[i], RIdx = RMask[i];
14916 // Ignore any UNDEF components.
14917 if (LIdx < 0 || RIdx < 0 ||
14918 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
14919 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
14922 // Check that successive elements are being operated on. If not, this is
14923 // not a horizontal operation.
14924 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
14925 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
14926 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
14927 if (!(LIdx == Index && RIdx == Index + 1) &&
14928 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
14932 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
14933 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
14937 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
14938 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
14939 const X86Subtarget *Subtarget) {
14940 EVT VT = N->getValueType(0);
14941 SDValue LHS = N->getOperand(0);
14942 SDValue RHS = N->getOperand(1);
14944 // Try to synthesize horizontal adds from adds of shuffles.
14945 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14946 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14947 isHorizontalBinOp(LHS, RHS, true))
14948 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
14952 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
14953 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
14954 const X86Subtarget *Subtarget) {
14955 EVT VT = N->getValueType(0);
14956 SDValue LHS = N->getOperand(0);
14957 SDValue RHS = N->getOperand(1);
14959 // Try to synthesize horizontal subs from subs of shuffles.
14960 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14961 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14962 isHorizontalBinOp(LHS, RHS, false))
14963 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
14967 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
14968 /// X86ISD::FXOR nodes.
14969 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
14970 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
14971 // F[X]OR(0.0, x) -> x
14972 // F[X]OR(x, 0.0) -> x
14973 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14974 if (C->getValueAPF().isPosZero())
14975 return N->getOperand(1);
14976 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14977 if (C->getValueAPF().isPosZero())
14978 return N->getOperand(0);
14982 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
14983 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
14984 // FAND(0.0, x) -> 0.0
14985 // FAND(x, 0.0) -> 0.0
14986 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14987 if (C->getValueAPF().isPosZero())
14988 return N->getOperand(0);
14989 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14990 if (C->getValueAPF().isPosZero())
14991 return N->getOperand(1);
14995 static SDValue PerformBTCombine(SDNode *N,
14997 TargetLowering::DAGCombinerInfo &DCI) {
14998 // BT ignores high bits in the bit index operand.
14999 SDValue Op1 = N->getOperand(1);
15000 if (Op1.hasOneUse()) {
15001 unsigned BitWidth = Op1.getValueSizeInBits();
15002 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
15003 APInt KnownZero, KnownOne;
15004 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
15005 !DCI.isBeforeLegalizeOps());
15006 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15007 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
15008 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
15009 DCI.CommitTargetLoweringOpt(TLO);
15014 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
15015 SDValue Op = N->getOperand(0);
15016 if (Op.getOpcode() == ISD::BITCAST)
15017 Op = Op.getOperand(0);
15018 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
15019 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
15020 VT.getVectorElementType().getSizeInBits() ==
15021 OpVT.getVectorElementType().getSizeInBits()) {
15022 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
15027 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
15028 TargetLowering::DAGCombinerInfo &DCI,
15029 const X86Subtarget *Subtarget) {
15030 if (!DCI.isBeforeLegalizeOps())
15033 if (!Subtarget->hasAVX())
15036 EVT VT = N->getValueType(0);
15037 SDValue Op = N->getOperand(0);
15038 EVT OpVT = Op.getValueType();
15039 DebugLoc dl = N->getDebugLoc();
15041 if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) ||
15042 (VT == MVT::v8i32 && OpVT == MVT::v8i16)) {
15044 if (Subtarget->hasAVX2())
15045 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, Op);
15047 // Optimize vectors in AVX mode
15048 // Sign extend v8i16 to v8i32 and
15051 // Divide input vector into two parts
15052 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15053 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15054 // concat the vectors to original VT
15056 unsigned NumElems = OpVT.getVectorNumElements();
15057 SmallVector<int,8> ShufMask1(NumElems, -1);
15058 for (unsigned i = 0; i != NumElems/2; ++i)
15061 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
15064 SmallVector<int,8> ShufMask2(NumElems, -1);
15065 for (unsigned i = 0; i != NumElems/2; ++i)
15066 ShufMask2[i] = i + NumElems/2;
15068 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
15071 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
15072 VT.getVectorNumElements()/2);
15074 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
15075 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
15077 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15082 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
15083 TargetLowering::DAGCombinerInfo &DCI,
15084 const X86Subtarget *Subtarget) {
15085 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
15086 // (and (i32 x86isd::setcc_carry), 1)
15087 // This eliminates the zext. This transformation is necessary because
15088 // ISD::SETCC is always legalized to i8.
15089 DebugLoc dl = N->getDebugLoc();
15090 SDValue N0 = N->getOperand(0);
15091 EVT VT = N->getValueType(0);
15092 EVT OpVT = N0.getValueType();
15094 if (N0.getOpcode() == ISD::AND &&
15096 N0.getOperand(0).hasOneUse()) {
15097 SDValue N00 = N0.getOperand(0);
15098 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
15100 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
15101 if (!C || C->getZExtValue() != 1)
15103 return DAG.getNode(ISD::AND, dl, VT,
15104 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
15105 N00.getOperand(0), N00.getOperand(1)),
15106 DAG.getConstant(1, VT));
15109 // Optimize vectors in AVX mode:
15112 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
15113 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
15114 // Concat upper and lower parts.
15117 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
15118 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
15119 // Concat upper and lower parts.
15121 if (!DCI.isBeforeLegalizeOps())
15124 if (!Subtarget->hasAVX())
15127 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) ||
15128 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) {
15130 if (Subtarget->hasAVX2())
15131 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, N0);
15133 SDValue ZeroVec = getZeroVector(OpVT, Subtarget, DAG, dl);
15134 SDValue OpLo = getUnpackl(DAG, dl, OpVT, N0, ZeroVec);
15135 SDValue OpHi = getUnpackh(DAG, dl, OpVT, N0, ZeroVec);
15137 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
15138 VT.getVectorNumElements()/2);
15140 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
15141 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
15143 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15149 // Optimize x == -y --> x+y == 0
15150 // x != -y --> x+y != 0
15151 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
15152 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
15153 SDValue LHS = N->getOperand(0);
15154 SDValue RHS = N->getOperand(1);
15156 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
15157 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
15158 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
15159 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
15160 LHS.getValueType(), RHS, LHS.getOperand(1));
15161 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
15162 addV, DAG.getConstant(0, addV.getValueType()), CC);
15164 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
15165 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
15166 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
15167 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
15168 RHS.getValueType(), LHS, RHS.getOperand(1));
15169 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
15170 addV, DAG.getConstant(0, addV.getValueType()), CC);
15175 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
15176 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
15177 unsigned X86CC = N->getConstantOperandVal(0);
15178 SDValue EFLAG = N->getOperand(1);
15179 DebugLoc DL = N->getDebugLoc();
15181 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
15182 // a zext and produces an all-ones bit which is more useful than 0/1 in some
15184 if (X86CC == X86::COND_B)
15185 return DAG.getNode(ISD::AND, DL, MVT::i8,
15186 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
15187 DAG.getConstant(X86CC, MVT::i8), EFLAG),
15188 DAG.getConstant(1, MVT::i8));
15193 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG) {
15194 SDValue Op0 = N->getOperand(0);
15195 EVT InVT = Op0->getValueType(0);
15197 // UINT_TO_FP(v4i8) -> SINT_TO_FP(ZEXT(v4i8 to v4i32))
15198 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
15199 DebugLoc dl = N->getDebugLoc();
15200 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15201 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
15202 // Notice that we use SINT_TO_FP because we know that the high bits
15203 // are zero and SINT_TO_FP is better supported by the hardware.
15204 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
15210 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
15211 const X86TargetLowering *XTLI) {
15212 SDValue Op0 = N->getOperand(0);
15213 EVT InVT = Op0->getValueType(0);
15215 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
15216 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
15217 DebugLoc dl = N->getDebugLoc();
15218 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15219 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
15220 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
15223 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
15224 // a 32-bit target where SSE doesn't support i64->FP operations.
15225 if (Op0.getOpcode() == ISD::LOAD) {
15226 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
15227 EVT VT = Ld->getValueType(0);
15228 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
15229 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
15230 !XTLI->getSubtarget()->is64Bit() &&
15231 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
15232 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
15233 Ld->getChain(), Op0, DAG);
15234 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
15241 static SDValue PerformFP_TO_SINTCombine(SDNode *N, SelectionDAG &DAG) {
15242 EVT VT = N->getValueType(0);
15244 // v4i8 = FP_TO_SINT() -> v4i8 = TRUNCATE (V4i32 = FP_TO_SINT()
15245 if (VT == MVT::v8i8 || VT == MVT::v4i8) {
15246 DebugLoc dl = N->getDebugLoc();
15247 MVT DstVT = VT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
15248 SDValue I = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, N->getOperand(0));
15249 return DAG.getNode(ISD::TRUNCATE, dl, VT, I);
15255 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
15256 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
15257 X86TargetLowering::DAGCombinerInfo &DCI) {
15258 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
15259 // the result is either zero or one (depending on the input carry bit).
15260 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
15261 if (X86::isZeroNode(N->getOperand(0)) &&
15262 X86::isZeroNode(N->getOperand(1)) &&
15263 // We don't have a good way to replace an EFLAGS use, so only do this when
15265 SDValue(N, 1).use_empty()) {
15266 DebugLoc DL = N->getDebugLoc();
15267 EVT VT = N->getValueType(0);
15268 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
15269 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
15270 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
15271 DAG.getConstant(X86::COND_B,MVT::i8),
15273 DAG.getConstant(1, VT));
15274 return DCI.CombineTo(N, Res1, CarryOut);
15280 // fold (add Y, (sete X, 0)) -> adc 0, Y
15281 // (add Y, (setne X, 0)) -> sbb -1, Y
15282 // (sub (sete X, 0), Y) -> sbb 0, Y
15283 // (sub (setne X, 0), Y) -> adc -1, Y
15284 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
15285 DebugLoc DL = N->getDebugLoc();
15287 // Look through ZExts.
15288 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
15289 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
15292 SDValue SetCC = Ext.getOperand(0);
15293 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
15296 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
15297 if (CC != X86::COND_E && CC != X86::COND_NE)
15300 SDValue Cmp = SetCC.getOperand(1);
15301 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
15302 !X86::isZeroNode(Cmp.getOperand(1)) ||
15303 !Cmp.getOperand(0).getValueType().isInteger())
15306 SDValue CmpOp0 = Cmp.getOperand(0);
15307 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
15308 DAG.getConstant(1, CmpOp0.getValueType()));
15310 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
15311 if (CC == X86::COND_NE)
15312 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
15313 DL, OtherVal.getValueType(), OtherVal,
15314 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
15315 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
15316 DL, OtherVal.getValueType(), OtherVal,
15317 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
15320 /// PerformADDCombine - Do target-specific dag combines on integer adds.
15321 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
15322 const X86Subtarget *Subtarget) {
15323 EVT VT = N->getValueType(0);
15324 SDValue Op0 = N->getOperand(0);
15325 SDValue Op1 = N->getOperand(1);
15327 // Try to synthesize horizontal adds from adds of shuffles.
15328 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
15329 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
15330 isHorizontalBinOp(Op0, Op1, true))
15331 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
15333 return OptimizeConditionalInDecrement(N, DAG);
15336 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
15337 const X86Subtarget *Subtarget) {
15338 SDValue Op0 = N->getOperand(0);
15339 SDValue Op1 = N->getOperand(1);
15341 // X86 can't encode an immediate LHS of a sub. See if we can push the
15342 // negation into a preceding instruction.
15343 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
15344 // If the RHS of the sub is a XOR with one use and a constant, invert the
15345 // immediate. Then add one to the LHS of the sub so we can turn
15346 // X-Y -> X+~Y+1, saving one register.
15347 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
15348 isa<ConstantSDNode>(Op1.getOperand(1))) {
15349 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
15350 EVT VT = Op0.getValueType();
15351 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
15353 DAG.getConstant(~XorC, VT));
15354 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
15355 DAG.getConstant(C->getAPIntValue()+1, VT));
15359 // Try to synthesize horizontal adds from adds of shuffles.
15360 EVT VT = N->getValueType(0);
15361 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
15362 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
15363 isHorizontalBinOp(Op0, Op1, true))
15364 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
15366 return OptimizeConditionalInDecrement(N, DAG);
15369 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
15370 DAGCombinerInfo &DCI) const {
15371 SelectionDAG &DAG = DCI.DAG;
15372 switch (N->getOpcode()) {
15374 case ISD::EXTRACT_VECTOR_ELT:
15375 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
15377 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
15378 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
15379 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
15380 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
15381 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
15382 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
15385 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
15386 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
15387 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
15388 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
15389 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
15390 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
15391 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG);
15392 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
15393 case ISD::FP_TO_SINT: return PerformFP_TO_SINTCombine(N, DAG);
15394 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
15395 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
15397 case X86ISD::FOR: return PerformFORCombine(N, DAG);
15398 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
15399 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
15400 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
15401 case ISD::ANY_EXTEND:
15402 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
15403 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
15404 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI);
15405 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
15406 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
15407 case X86ISD::SHUFP: // Handle all target specific shuffles
15408 case X86ISD::PALIGN:
15409 case X86ISD::UNPCKH:
15410 case X86ISD::UNPCKL:
15411 case X86ISD::MOVHLPS:
15412 case X86ISD::MOVLHPS:
15413 case X86ISD::PSHUFD:
15414 case X86ISD::PSHUFHW:
15415 case X86ISD::PSHUFLW:
15416 case X86ISD::MOVSS:
15417 case X86ISD::MOVSD:
15418 case X86ISD::VPERMILP:
15419 case X86ISD::VPERM2X128:
15420 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
15426 /// isTypeDesirableForOp - Return true if the target has native support for
15427 /// the specified value type and it is 'desirable' to use the type for the
15428 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
15429 /// instruction encodings are longer and some i16 instructions are slow.
15430 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
15431 if (!isTypeLegal(VT))
15433 if (VT != MVT::i16)
15440 case ISD::SIGN_EXTEND:
15441 case ISD::ZERO_EXTEND:
15442 case ISD::ANY_EXTEND:
15455 /// IsDesirableToPromoteOp - This method query the target whether it is
15456 /// beneficial for dag combiner to promote the specified node. If true, it
15457 /// should return the desired promotion type by reference.
15458 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
15459 EVT VT = Op.getValueType();
15460 if (VT != MVT::i16)
15463 bool Promote = false;
15464 bool Commute = false;
15465 switch (Op.getOpcode()) {
15468 LoadSDNode *LD = cast<LoadSDNode>(Op);
15469 // If the non-extending load has a single use and it's not live out, then it
15470 // might be folded.
15471 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
15472 Op.hasOneUse()*/) {
15473 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
15474 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
15475 // The only case where we'd want to promote LOAD (rather then it being
15476 // promoted as an operand is when it's only use is liveout.
15477 if (UI->getOpcode() != ISD::CopyToReg)
15484 case ISD::SIGN_EXTEND:
15485 case ISD::ZERO_EXTEND:
15486 case ISD::ANY_EXTEND:
15491 SDValue N0 = Op.getOperand(0);
15492 // Look out for (store (shl (load), x)).
15493 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
15506 SDValue N0 = Op.getOperand(0);
15507 SDValue N1 = Op.getOperand(1);
15508 if (!Commute && MayFoldLoad(N1))
15510 // Avoid disabling potential load folding opportunities.
15511 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
15513 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
15523 //===----------------------------------------------------------------------===//
15524 // X86 Inline Assembly Support
15525 //===----------------------------------------------------------------------===//
15528 // Helper to match a string separated by whitespace.
15529 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
15530 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
15532 for (unsigned i = 0, e = args.size(); i != e; ++i) {
15533 StringRef piece(*args[i]);
15534 if (!s.startswith(piece)) // Check if the piece matches.
15537 s = s.substr(piece.size());
15538 StringRef::size_type pos = s.find_first_not_of(" \t");
15539 if (pos == 0) // We matched a prefix.
15547 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
15550 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
15551 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
15553 std::string AsmStr = IA->getAsmString();
15555 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
15556 if (!Ty || Ty->getBitWidth() % 16 != 0)
15559 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
15560 SmallVector<StringRef, 4> AsmPieces;
15561 SplitString(AsmStr, AsmPieces, ";\n");
15563 switch (AsmPieces.size()) {
15564 default: return false;
15566 // FIXME: this should verify that we are targeting a 486 or better. If not,
15567 // we will turn this bswap into something that will be lowered to logical
15568 // ops instead of emitting the bswap asm. For now, we don't support 486 or
15569 // lower so don't worry about this.
15571 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
15572 matchAsm(AsmPieces[0], "bswapl", "$0") ||
15573 matchAsm(AsmPieces[0], "bswapq", "$0") ||
15574 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
15575 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
15576 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
15577 // No need to check constraints, nothing other than the equivalent of
15578 // "=r,0" would be valid here.
15579 return IntrinsicLowering::LowerToByteSwap(CI);
15582 // rorw $$8, ${0:w} --> llvm.bswap.i16
15583 if (CI->getType()->isIntegerTy(16) &&
15584 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15585 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
15586 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
15588 const std::string &ConstraintsStr = IA->getConstraintString();
15589 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15590 std::sort(AsmPieces.begin(), AsmPieces.end());
15591 if (AsmPieces.size() == 4 &&
15592 AsmPieces[0] == "~{cc}" &&
15593 AsmPieces[1] == "~{dirflag}" &&
15594 AsmPieces[2] == "~{flags}" &&
15595 AsmPieces[3] == "~{fpsr}")
15596 return IntrinsicLowering::LowerToByteSwap(CI);
15600 if (CI->getType()->isIntegerTy(32) &&
15601 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15602 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
15603 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
15604 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
15606 const std::string &ConstraintsStr = IA->getConstraintString();
15607 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15608 std::sort(AsmPieces.begin(), AsmPieces.end());
15609 if (AsmPieces.size() == 4 &&
15610 AsmPieces[0] == "~{cc}" &&
15611 AsmPieces[1] == "~{dirflag}" &&
15612 AsmPieces[2] == "~{flags}" &&
15613 AsmPieces[3] == "~{fpsr}")
15614 return IntrinsicLowering::LowerToByteSwap(CI);
15617 if (CI->getType()->isIntegerTy(64)) {
15618 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
15619 if (Constraints.size() >= 2 &&
15620 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
15621 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
15622 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
15623 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
15624 matchAsm(AsmPieces[1], "bswap", "%edx") &&
15625 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
15626 return IntrinsicLowering::LowerToByteSwap(CI);
15636 /// getConstraintType - Given a constraint letter, return the type of
15637 /// constraint it is for this target.
15638 X86TargetLowering::ConstraintType
15639 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
15640 if (Constraint.size() == 1) {
15641 switch (Constraint[0]) {
15652 return C_RegisterClass;
15676 return TargetLowering::getConstraintType(Constraint);
15679 /// Examine constraint type and operand type and determine a weight value.
15680 /// This object must already have been set up with the operand type
15681 /// and the current alternative constraint selected.
15682 TargetLowering::ConstraintWeight
15683 X86TargetLowering::getSingleConstraintMatchWeight(
15684 AsmOperandInfo &info, const char *constraint) const {
15685 ConstraintWeight weight = CW_Invalid;
15686 Value *CallOperandVal = info.CallOperandVal;
15687 // If we don't have a value, we can't do a match,
15688 // but allow it at the lowest weight.
15689 if (CallOperandVal == NULL)
15691 Type *type = CallOperandVal->getType();
15692 // Look at the constraint type.
15693 switch (*constraint) {
15695 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
15706 if (CallOperandVal->getType()->isIntegerTy())
15707 weight = CW_SpecificReg;
15712 if (type->isFloatingPointTy())
15713 weight = CW_SpecificReg;
15716 if (type->isX86_MMXTy() && Subtarget->hasMMX())
15717 weight = CW_SpecificReg;
15721 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
15722 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX()))
15723 weight = CW_Register;
15726 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
15727 if (C->getZExtValue() <= 31)
15728 weight = CW_Constant;
15732 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15733 if (C->getZExtValue() <= 63)
15734 weight = CW_Constant;
15738 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15739 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
15740 weight = CW_Constant;
15744 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15745 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
15746 weight = CW_Constant;
15750 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15751 if (C->getZExtValue() <= 3)
15752 weight = CW_Constant;
15756 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15757 if (C->getZExtValue() <= 0xff)
15758 weight = CW_Constant;
15763 if (dyn_cast<ConstantFP>(CallOperandVal)) {
15764 weight = CW_Constant;
15768 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15769 if ((C->getSExtValue() >= -0x80000000LL) &&
15770 (C->getSExtValue() <= 0x7fffffffLL))
15771 weight = CW_Constant;
15775 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15776 if (C->getZExtValue() <= 0xffffffff)
15777 weight = CW_Constant;
15784 /// LowerXConstraint - try to replace an X constraint, which matches anything,
15785 /// with another that has more specific requirements based on the type of the
15786 /// corresponding operand.
15787 const char *X86TargetLowering::
15788 LowerXConstraint(EVT ConstraintVT) const {
15789 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
15790 // 'f' like normal targets.
15791 if (ConstraintVT.isFloatingPoint()) {
15792 if (Subtarget->hasSSE2())
15794 if (Subtarget->hasSSE1())
15798 return TargetLowering::LowerXConstraint(ConstraintVT);
15801 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
15802 /// vector. If it is invalid, don't add anything to Ops.
15803 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
15804 std::string &Constraint,
15805 std::vector<SDValue>&Ops,
15806 SelectionDAG &DAG) const {
15807 SDValue Result(0, 0);
15809 // Only support length 1 constraints for now.
15810 if (Constraint.length() > 1) return;
15812 char ConstraintLetter = Constraint[0];
15813 switch (ConstraintLetter) {
15816 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15817 if (C->getZExtValue() <= 31) {
15818 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15824 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15825 if (C->getZExtValue() <= 63) {
15826 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15832 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15833 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
15834 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15840 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15841 if (C->getZExtValue() <= 255) {
15842 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15848 // 32-bit signed value
15849 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15850 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15851 C->getSExtValue())) {
15852 // Widen to 64 bits here to get it sign extended.
15853 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
15856 // FIXME gcc accepts some relocatable values here too, but only in certain
15857 // memory models; it's complicated.
15862 // 32-bit unsigned value
15863 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15864 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15865 C->getZExtValue())) {
15866 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15870 // FIXME gcc accepts some relocatable values here too, but only in certain
15871 // memory models; it's complicated.
15875 // Literal immediates are always ok.
15876 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
15877 // Widen to 64 bits here to get it sign extended.
15878 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
15882 // In any sort of PIC mode addresses need to be computed at runtime by
15883 // adding in a register or some sort of table lookup. These can't
15884 // be used as immediates.
15885 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
15888 // If we are in non-pic codegen mode, we allow the address of a global (with
15889 // an optional displacement) to be used with 'i'.
15890 GlobalAddressSDNode *GA = 0;
15891 int64_t Offset = 0;
15893 // Match either (GA), (GA+C), (GA+C1+C2), etc.
15895 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
15896 Offset += GA->getOffset();
15898 } else if (Op.getOpcode() == ISD::ADD) {
15899 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15900 Offset += C->getZExtValue();
15901 Op = Op.getOperand(0);
15904 } else if (Op.getOpcode() == ISD::SUB) {
15905 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15906 Offset += -C->getZExtValue();
15907 Op = Op.getOperand(0);
15912 // Otherwise, this isn't something we can handle, reject it.
15916 const GlobalValue *GV = GA->getGlobal();
15917 // If we require an extra load to get this address, as in PIC mode, we
15918 // can't accept it.
15919 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
15920 getTargetMachine())))
15923 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
15924 GA->getValueType(0), Offset);
15929 if (Result.getNode()) {
15930 Ops.push_back(Result);
15933 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
15936 std::pair<unsigned, const TargetRegisterClass*>
15937 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
15939 // First, see if this is a constraint that directly corresponds to an LLVM
15941 if (Constraint.size() == 1) {
15942 // GCC Constraint Letters
15943 switch (Constraint[0]) {
15945 // TODO: Slight differences here in allocation order and leaving
15946 // RIP in the class. Do they matter any more here than they do
15947 // in the normal allocation?
15948 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
15949 if (Subtarget->is64Bit()) {
15950 if (VT == MVT::i32 || VT == MVT::f32)
15951 return std::make_pair(0U, &X86::GR32RegClass);
15952 if (VT == MVT::i16)
15953 return std::make_pair(0U, &X86::GR16RegClass);
15954 if (VT == MVT::i8 || VT == MVT::i1)
15955 return std::make_pair(0U, &X86::GR8RegClass);
15956 if (VT == MVT::i64 || VT == MVT::f64)
15957 return std::make_pair(0U, &X86::GR64RegClass);
15960 // 32-bit fallthrough
15961 case 'Q': // Q_REGS
15962 if (VT == MVT::i32 || VT == MVT::f32)
15963 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
15964 if (VT == MVT::i16)
15965 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
15966 if (VT == MVT::i8 || VT == MVT::i1)
15967 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
15968 if (VT == MVT::i64)
15969 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
15971 case 'r': // GENERAL_REGS
15972 case 'l': // INDEX_REGS
15973 if (VT == MVT::i8 || VT == MVT::i1)
15974 return std::make_pair(0U, &X86::GR8RegClass);
15975 if (VT == MVT::i16)
15976 return std::make_pair(0U, &X86::GR16RegClass);
15977 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
15978 return std::make_pair(0U, &X86::GR32RegClass);
15979 return std::make_pair(0U, &X86::GR64RegClass);
15980 case 'R': // LEGACY_REGS
15981 if (VT == MVT::i8 || VT == MVT::i1)
15982 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
15983 if (VT == MVT::i16)
15984 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
15985 if (VT == MVT::i32 || !Subtarget->is64Bit())
15986 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
15987 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
15988 case 'f': // FP Stack registers.
15989 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
15990 // value to the correct fpstack register class.
15991 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
15992 return std::make_pair(0U, &X86::RFP32RegClass);
15993 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
15994 return std::make_pair(0U, &X86::RFP64RegClass);
15995 return std::make_pair(0U, &X86::RFP80RegClass);
15996 case 'y': // MMX_REGS if MMX allowed.
15997 if (!Subtarget->hasMMX()) break;
15998 return std::make_pair(0U, &X86::VR64RegClass);
15999 case 'Y': // SSE_REGS if SSE2 allowed
16000 if (!Subtarget->hasSSE2()) break;
16002 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
16003 if (!Subtarget->hasSSE1()) break;
16005 switch (VT.getSimpleVT().SimpleTy) {
16007 // Scalar SSE types.
16010 return std::make_pair(0U, &X86::FR32RegClass);
16013 return std::make_pair(0U, &X86::FR64RegClass);
16021 return std::make_pair(0U, &X86::VR128RegClass);
16029 return std::make_pair(0U, &X86::VR256RegClass);
16035 // Use the default implementation in TargetLowering to convert the register
16036 // constraint into a member of a register class.
16037 std::pair<unsigned, const TargetRegisterClass*> Res;
16038 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
16040 // Not found as a standard register?
16041 if (Res.second == 0) {
16042 // Map st(0) -> st(7) -> ST0
16043 if (Constraint.size() == 7 && Constraint[0] == '{' &&
16044 tolower(Constraint[1]) == 's' &&
16045 tolower(Constraint[2]) == 't' &&
16046 Constraint[3] == '(' &&
16047 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
16048 Constraint[5] == ')' &&
16049 Constraint[6] == '}') {
16051 Res.first = X86::ST0+Constraint[4]-'0';
16052 Res.second = &X86::RFP80RegClass;
16056 // GCC allows "st(0)" to be called just plain "st".
16057 if (StringRef("{st}").equals_lower(Constraint)) {
16058 Res.first = X86::ST0;
16059 Res.second = &X86::RFP80RegClass;
16064 if (StringRef("{flags}").equals_lower(Constraint)) {
16065 Res.first = X86::EFLAGS;
16066 Res.second = &X86::CCRRegClass;
16070 // 'A' means EAX + EDX.
16071 if (Constraint == "A") {
16072 Res.first = X86::EAX;
16073 Res.second = &X86::GR32_ADRegClass;
16079 // Otherwise, check to see if this is a register class of the wrong value
16080 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
16081 // turn into {ax},{dx}.
16082 if (Res.second->hasType(VT))
16083 return Res; // Correct type already, nothing to do.
16085 // All of the single-register GCC register classes map their values onto
16086 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
16087 // really want an 8-bit or 32-bit register, map to the appropriate register
16088 // class and return the appropriate register.
16089 if (Res.second == &X86::GR16RegClass) {
16090 if (VT == MVT::i8) {
16091 unsigned DestReg = 0;
16092 switch (Res.first) {
16094 case X86::AX: DestReg = X86::AL; break;
16095 case X86::DX: DestReg = X86::DL; break;
16096 case X86::CX: DestReg = X86::CL; break;
16097 case X86::BX: DestReg = X86::BL; break;
16100 Res.first = DestReg;
16101 Res.second = &X86::GR8RegClass;
16103 } else if (VT == MVT::i32) {
16104 unsigned DestReg = 0;
16105 switch (Res.first) {
16107 case X86::AX: DestReg = X86::EAX; break;
16108 case X86::DX: DestReg = X86::EDX; break;
16109 case X86::CX: DestReg = X86::ECX; break;
16110 case X86::BX: DestReg = X86::EBX; break;
16111 case X86::SI: DestReg = X86::ESI; break;
16112 case X86::DI: DestReg = X86::EDI; break;
16113 case X86::BP: DestReg = X86::EBP; break;
16114 case X86::SP: DestReg = X86::ESP; break;
16117 Res.first = DestReg;
16118 Res.second = &X86::GR32RegClass;
16120 } else if (VT == MVT::i64) {
16121 unsigned DestReg = 0;
16122 switch (Res.first) {
16124 case X86::AX: DestReg = X86::RAX; break;
16125 case X86::DX: DestReg = X86::RDX; break;
16126 case X86::CX: DestReg = X86::RCX; break;
16127 case X86::BX: DestReg = X86::RBX; break;
16128 case X86::SI: DestReg = X86::RSI; break;
16129 case X86::DI: DestReg = X86::RDI; break;
16130 case X86::BP: DestReg = X86::RBP; break;
16131 case X86::SP: DestReg = X86::RSP; break;
16134 Res.first = DestReg;
16135 Res.second = &X86::GR64RegClass;
16138 } else if (Res.second == &X86::FR32RegClass ||
16139 Res.second == &X86::FR64RegClass ||
16140 Res.second == &X86::VR128RegClass) {
16141 // Handle references to XMM physical registers that got mapped into the
16142 // wrong class. This can happen with constraints like {xmm0} where the
16143 // target independent register mapper will just pick the first match it can
16144 // find, ignoring the required type.
16146 if (VT == MVT::f32 || VT == MVT::i32)
16147 Res.second = &X86::FR32RegClass;
16148 else if (VT == MVT::f64 || VT == MVT::i64)
16149 Res.second = &X86::FR64RegClass;
16150 else if (X86::VR128RegClass.hasType(VT))
16151 Res.second = &X86::VR128RegClass;
16152 else if (X86::VR256RegClass.hasType(VT))
16153 Res.second = &X86::VR256RegClass;