1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/Analysis/EHPersonalities.h"
29 #include "llvm/CodeGen/IntrinsicLowering.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/WinEHFuncInfo.h"
37 #include "llvm/IR/CallSite.h"
38 #include "llvm/IR/CallingConv.h"
39 #include "llvm/IR/Constants.h"
40 #include "llvm/IR/DerivedTypes.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/GlobalAlias.h"
43 #include "llvm/IR/GlobalVariable.h"
44 #include "llvm/IR/Instructions.h"
45 #include "llvm/IR/Intrinsics.h"
46 #include "llvm/MC/MCAsmInfo.h"
47 #include "llvm/MC/MCContext.h"
48 #include "llvm/MC/MCExpr.h"
49 #include "llvm/MC/MCSymbol.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/Debug.h"
52 #include "llvm/Support/ErrorHandling.h"
53 #include "llvm/Support/MathExtras.h"
54 #include "llvm/Target/TargetOptions.h"
55 #include "X86IntrinsicsInfo.h"
61 #define DEBUG_TYPE "x86-isel"
63 STATISTIC(NumTailCalls, "Number of tail calls");
65 static cl::opt<bool> ExperimentalVectorWideningLegalization(
66 "x86-experimental-vector-widening-legalization", cl::init(false),
67 cl::desc("Enable an experimental vector type legalization through widening "
68 "rather than promotion."),
71 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
72 const X86Subtarget &STI)
73 : TargetLowering(TM), Subtarget(&STI) {
74 X86ScalarSSEf64 = Subtarget->hasSSE2();
75 X86ScalarSSEf32 = Subtarget->hasSSE1();
76 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
78 // Set up the TargetLowering object.
80 // X86 is weird. It always uses i8 for shift amounts and setcc results.
81 setBooleanContents(ZeroOrOneBooleanContent);
82 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
83 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
85 // For 64-bit, since we have so many registers, use the ILP scheduler.
86 // For 32-bit, use the register pressure specific scheduling.
87 // For Atom, always use ILP scheduling.
88 if (Subtarget->isAtom())
89 setSchedulingPreference(Sched::ILP);
90 else if (Subtarget->is64Bit())
91 setSchedulingPreference(Sched::ILP);
93 setSchedulingPreference(Sched::RegPressure);
94 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
95 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
97 // Bypass expensive divides on Atom when compiling with O2.
98 if (TM.getOptLevel() >= CodeGenOpt::Default) {
99 if (Subtarget->hasSlowDivide32())
100 addBypassSlowDiv(32, 8);
101 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
102 addBypassSlowDiv(64, 16);
105 if (Subtarget->isTargetKnownWindowsMSVC()) {
106 // Setup Windows compiler runtime calls.
107 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
108 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
109 setLibcallName(RTLIB::SREM_I64, "_allrem");
110 setLibcallName(RTLIB::UREM_I64, "_aullrem");
111 setLibcallName(RTLIB::MUL_I64, "_allmul");
112 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
113 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
114 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
115 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
116 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
119 if (Subtarget->isTargetDarwin()) {
120 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
121 setUseUnderscoreSetJmp(false);
122 setUseUnderscoreLongJmp(false);
123 } else if (Subtarget->isTargetWindowsGNU()) {
124 // MS runtime is weird: it exports _setjmp, but longjmp!
125 setUseUnderscoreSetJmp(true);
126 setUseUnderscoreLongJmp(false);
128 setUseUnderscoreSetJmp(true);
129 setUseUnderscoreLongJmp(true);
132 // Set up the register classes.
133 addRegisterClass(MVT::i8, &X86::GR8RegClass);
134 addRegisterClass(MVT::i16, &X86::GR16RegClass);
135 addRegisterClass(MVT::i32, &X86::GR32RegClass);
136 if (Subtarget->is64Bit())
137 addRegisterClass(MVT::i64, &X86::GR64RegClass);
139 for (MVT VT : MVT::integer_valuetypes())
140 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
142 // We don't accept any truncstore of integer registers.
143 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
144 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
145 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
146 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
147 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
148 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
150 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
152 // SETOEQ and SETUNE require checking two conditions.
153 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
154 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
155 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
156 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
157 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
158 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
160 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
162 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
163 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
164 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
166 if (Subtarget->is64Bit()) {
167 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512())
168 // f32/f64 are legal, f80 is custom.
169 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
171 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
172 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
173 } else if (!Subtarget->useSoftFloat()) {
174 // We have an algorithm for SSE2->double, and we turn this into a
175 // 64-bit FILD followed by conditional FADD for other targets.
176 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
177 // We have an algorithm for SSE2, and we turn this into a 64-bit
178 // FILD or VCVTUSI2SS/SD for other targets.
179 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
182 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
184 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
185 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
187 if (!Subtarget->useSoftFloat()) {
188 // SSE has no i16 to fp conversion, only i32
189 if (X86ScalarSSEf32) {
190 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
191 // f32 and f64 cases are Legal, f80 case is not
192 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
194 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
195 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
199 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
202 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
204 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
205 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
207 if (!Subtarget->useSoftFloat()) {
208 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
209 // are Legal, f80 is custom lowered.
210 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
211 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
213 if (X86ScalarSSEf32) {
214 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
215 // f32 and f64 cases are Legal, f80 case is not
216 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
218 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
219 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
222 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
223 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Expand);
224 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Expand);
227 // Handle FP_TO_UINT by promoting the destination to a larger signed
229 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
230 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
231 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
233 if (Subtarget->is64Bit()) {
234 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
235 // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
236 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
237 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
239 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
240 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
242 } else if (!Subtarget->useSoftFloat()) {
243 // Since AVX is a superset of SSE3, only check for SSE here.
244 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
245 // Expand FP_TO_UINT into a select.
246 // FIXME: We would like to use a Custom expander here eventually to do
247 // the optimal thing for SSE vs. the default expansion in the legalizer.
248 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
250 // With AVX512 we can use vcvts[ds]2usi for f32/f64->i32, f80 is custom.
251 // With SSE3 we can use fisttpll to convert to a signed i64; without
252 // SSE, we're stuck with a fistpll.
253 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
255 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
258 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
259 if (!X86ScalarSSEf64) {
260 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
261 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
262 if (Subtarget->is64Bit()) {
263 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
264 // Without SSE, i64->f64 goes through memory.
265 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
269 // Scalar integer divide and remainder are lowered to use operations that
270 // produce two results, to match the available instructions. This exposes
271 // the two-result form to trivial CSE, which is able to combine x/y and x%y
272 // into a single instruction.
274 // Scalar integer multiply-high is also lowered to use two-result
275 // operations, to match the available instructions. However, plain multiply
276 // (low) operations are left as Legal, as there are single-result
277 // instructions for this in x86. Using the two-result multiply instructions
278 // when both high and low results are needed must be arranged by dagcombine.
279 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
280 setOperationAction(ISD::MULHS, VT, Expand);
281 setOperationAction(ISD::MULHU, VT, Expand);
282 setOperationAction(ISD::SDIV, VT, Expand);
283 setOperationAction(ISD::UDIV, VT, Expand);
284 setOperationAction(ISD::SREM, VT, Expand);
285 setOperationAction(ISD::UREM, VT, Expand);
287 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
288 setOperationAction(ISD::ADDC, VT, Custom);
289 setOperationAction(ISD::ADDE, VT, Custom);
290 setOperationAction(ISD::SUBC, VT, Custom);
291 setOperationAction(ISD::SUBE, VT, Custom);
294 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
295 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
296 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
297 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
298 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
299 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
300 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
301 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
302 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
303 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
304 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
305 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
306 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
307 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
308 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
309 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
310 if (Subtarget->is64Bit())
311 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
312 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
313 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
314 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
315 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
317 if (Subtarget->is32Bit() && Subtarget->isTargetKnownWindowsMSVC()) {
318 // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
319 // is. We should promote the value to 64-bits to solve this.
320 // This is what the CRT headers do - `fmodf` is an inline header
321 // function casting to f64 and calling `fmod`.
322 setOperationAction(ISD::FREM , MVT::f32 , Promote);
324 setOperationAction(ISD::FREM , MVT::f32 , Expand);
327 setOperationAction(ISD::FREM , MVT::f64 , Expand);
328 setOperationAction(ISD::FREM , MVT::f80 , Expand);
329 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
331 // Promote the i8 variants and force them on up to i32 which has a shorter
333 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
334 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
335 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
336 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
337 if (Subtarget->hasBMI()) {
338 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
339 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
340 if (Subtarget->is64Bit())
341 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
343 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
344 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
345 if (Subtarget->is64Bit())
346 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
349 if (Subtarget->hasLZCNT()) {
350 // When promoting the i8 variants, force them to i32 for a shorter
352 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
353 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
355 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
356 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
357 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
358 if (Subtarget->is64Bit())
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
361 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
362 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
363 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
364 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
365 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
366 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
367 if (Subtarget->is64Bit()) {
368 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
369 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
373 // Special handling for half-precision floating point conversions.
374 // If we don't have F16C support, then lower half float conversions
375 // into library calls.
376 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
377 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
378 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
381 // There's never any support for operations beyond MVT::f32.
382 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
383 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
384 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
385 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
387 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
388 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
389 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
390 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
391 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
392 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
394 if (Subtarget->hasPOPCNT()) {
395 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
397 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
398 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
399 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
400 if (Subtarget->is64Bit())
401 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
404 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
406 if (!Subtarget->hasMOVBE())
407 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
409 // These should be promoted to a larger select which is supported.
410 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
411 // X86 wants to expand cmov itself.
412 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
413 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
414 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
415 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
416 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
417 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
418 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
419 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
420 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
421 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
422 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
423 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
424 setOperationAction(ISD::SETCCE , MVT::i8 , Custom);
425 setOperationAction(ISD::SETCCE , MVT::i16 , Custom);
426 setOperationAction(ISD::SETCCE , MVT::i32 , Custom);
427 if (Subtarget->is64Bit()) {
428 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
429 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
430 setOperationAction(ISD::SETCCE , MVT::i64 , Custom);
432 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
433 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
434 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
435 // support continuation, user-level threading, and etc.. As a result, no
436 // other SjLj exception interfaces are implemented and please don't build
437 // your own exception handling based on them.
438 // LLVM/Clang supports zero-cost DWARF exception handling.
439 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
440 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
443 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
444 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
445 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
446 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
447 if (Subtarget->is64Bit())
448 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
449 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
450 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
451 if (Subtarget->is64Bit()) {
452 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
453 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
454 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
455 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
456 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
458 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
459 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
460 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
461 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
462 if (Subtarget->is64Bit()) {
463 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
464 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
465 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
468 if (Subtarget->hasSSE1())
469 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
471 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
473 // Expand certain atomics
474 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
475 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
476 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
477 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
480 if (Subtarget->hasCmpxchg16b()) {
481 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
484 // FIXME - use subtarget debug flags
485 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
486 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
487 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
490 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
491 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
493 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
494 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
496 setOperationAction(ISD::TRAP, MVT::Other, Legal);
497 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
499 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
500 setOperationAction(ISD::VASTART , MVT::Other, Custom);
501 setOperationAction(ISD::VAEND , MVT::Other, Expand);
502 if (Subtarget->is64Bit()) {
503 setOperationAction(ISD::VAARG , MVT::Other, Custom);
504 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
506 // TargetInfo::CharPtrBuiltinVaList
507 setOperationAction(ISD::VAARG , MVT::Other, Expand);
508 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
511 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
512 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
514 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
516 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
517 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
518 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
520 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
521 // f32 and f64 use SSE.
522 // Set up the FP register classes.
523 addRegisterClass(MVT::f32, &X86::FR32RegClass);
524 addRegisterClass(MVT::f64, &X86::FR64RegClass);
526 // Use ANDPD to simulate FABS.
527 setOperationAction(ISD::FABS , MVT::f64, Custom);
528 setOperationAction(ISD::FABS , MVT::f32, Custom);
530 // Use XORP to simulate FNEG.
531 setOperationAction(ISD::FNEG , MVT::f64, Custom);
532 setOperationAction(ISD::FNEG , MVT::f32, Custom);
534 // Use ANDPD and ORPD to simulate FCOPYSIGN.
535 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
536 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
538 // Lower this to FGETSIGNx86 plus an AND.
539 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
540 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
542 // We don't support sin/cos/fmod
543 setOperationAction(ISD::FSIN , MVT::f64, Expand);
544 setOperationAction(ISD::FCOS , MVT::f64, Expand);
545 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
546 setOperationAction(ISD::FSIN , MVT::f32, Expand);
547 setOperationAction(ISD::FCOS , MVT::f32, Expand);
548 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
550 // Expand FP immediates into loads from the stack, except for the special
552 addLegalFPImmediate(APFloat(+0.0)); // xorpd
553 addLegalFPImmediate(APFloat(+0.0f)); // xorps
554 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
555 // Use SSE for f32, x87 for f64.
556 // Set up the FP register classes.
557 addRegisterClass(MVT::f32, &X86::FR32RegClass);
558 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
560 // Use ANDPS to simulate FABS.
561 setOperationAction(ISD::FABS , MVT::f32, Custom);
563 // Use XORP to simulate FNEG.
564 setOperationAction(ISD::FNEG , MVT::f32, Custom);
566 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
568 // Use ANDPS and ORPS to simulate FCOPYSIGN.
569 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
570 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
572 // We don't support sin/cos/fmod
573 setOperationAction(ISD::FSIN , MVT::f32, Expand);
574 setOperationAction(ISD::FCOS , MVT::f32, Expand);
575 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
577 // Special cases we handle for FP constants.
578 addLegalFPImmediate(APFloat(+0.0f)); // xorps
579 addLegalFPImmediate(APFloat(+0.0)); // FLD0
580 addLegalFPImmediate(APFloat(+1.0)); // FLD1
581 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
582 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
584 if (!TM.Options.UnsafeFPMath) {
585 setOperationAction(ISD::FSIN , MVT::f64, Expand);
586 setOperationAction(ISD::FCOS , MVT::f64, Expand);
587 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
589 } else if (!Subtarget->useSoftFloat()) {
590 // f32 and f64 in x87.
591 // Set up the FP register classes.
592 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
593 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
595 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
596 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
597 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
598 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
600 if (!TM.Options.UnsafeFPMath) {
601 setOperationAction(ISD::FSIN , MVT::f64, Expand);
602 setOperationAction(ISD::FSIN , MVT::f32, Expand);
603 setOperationAction(ISD::FCOS , MVT::f64, Expand);
604 setOperationAction(ISD::FCOS , MVT::f32, Expand);
605 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
606 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
608 addLegalFPImmediate(APFloat(+0.0)); // FLD0
609 addLegalFPImmediate(APFloat(+1.0)); // FLD1
610 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
611 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
612 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
613 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
614 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
615 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
618 // We don't support FMA.
619 setOperationAction(ISD::FMA, MVT::f64, Expand);
620 setOperationAction(ISD::FMA, MVT::f32, Expand);
622 // Long double always uses X87.
623 if (!Subtarget->useSoftFloat()) {
624 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
625 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
626 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
628 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
629 addLegalFPImmediate(TmpFlt); // FLD0
631 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
634 APFloat TmpFlt2(+1.0);
635 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
637 addLegalFPImmediate(TmpFlt2); // FLD1
638 TmpFlt2.changeSign();
639 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
642 if (!TM.Options.UnsafeFPMath) {
643 setOperationAction(ISD::FSIN , MVT::f80, Expand);
644 setOperationAction(ISD::FCOS , MVT::f80, Expand);
645 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
648 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
649 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
650 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
651 setOperationAction(ISD::FRINT, MVT::f80, Expand);
652 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
653 setOperationAction(ISD::FMA, MVT::f80, Expand);
656 // Always use a library call for pow.
657 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
658 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
659 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
661 setOperationAction(ISD::FLOG, MVT::f80, Expand);
662 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
663 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
664 setOperationAction(ISD::FEXP, MVT::f80, Expand);
665 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
666 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
667 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
669 // First set operation action for all vector types to either promote
670 // (for widening) or expand (for scalarization). Then we will selectively
671 // turn on ones that can be effectively codegen'd.
672 for (MVT VT : MVT::vector_valuetypes()) {
673 setOperationAction(ISD::ADD , VT, Expand);
674 setOperationAction(ISD::SUB , VT, Expand);
675 setOperationAction(ISD::FADD, VT, Expand);
676 setOperationAction(ISD::FNEG, VT, Expand);
677 setOperationAction(ISD::FSUB, VT, Expand);
678 setOperationAction(ISD::MUL , VT, Expand);
679 setOperationAction(ISD::FMUL, VT, Expand);
680 setOperationAction(ISD::SDIV, VT, Expand);
681 setOperationAction(ISD::UDIV, VT, Expand);
682 setOperationAction(ISD::FDIV, VT, Expand);
683 setOperationAction(ISD::SREM, VT, Expand);
684 setOperationAction(ISD::UREM, VT, Expand);
685 setOperationAction(ISD::LOAD, VT, Expand);
686 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
687 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
688 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
689 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
690 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
691 setOperationAction(ISD::FABS, VT, Expand);
692 setOperationAction(ISD::FSIN, VT, Expand);
693 setOperationAction(ISD::FSINCOS, VT, Expand);
694 setOperationAction(ISD::FCOS, VT, Expand);
695 setOperationAction(ISD::FSINCOS, VT, Expand);
696 setOperationAction(ISD::FREM, VT, Expand);
697 setOperationAction(ISD::FMA, VT, Expand);
698 setOperationAction(ISD::FPOWI, VT, Expand);
699 setOperationAction(ISD::FSQRT, VT, Expand);
700 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
701 setOperationAction(ISD::FFLOOR, VT, Expand);
702 setOperationAction(ISD::FCEIL, VT, Expand);
703 setOperationAction(ISD::FTRUNC, VT, Expand);
704 setOperationAction(ISD::FRINT, VT, Expand);
705 setOperationAction(ISD::FNEARBYINT, VT, Expand);
706 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
707 setOperationAction(ISD::MULHS, VT, Expand);
708 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
709 setOperationAction(ISD::MULHU, VT, Expand);
710 setOperationAction(ISD::SDIVREM, VT, Expand);
711 setOperationAction(ISD::UDIVREM, VT, Expand);
712 setOperationAction(ISD::FPOW, VT, Expand);
713 setOperationAction(ISD::CTPOP, VT, Expand);
714 setOperationAction(ISD::CTTZ, VT, Expand);
715 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
716 setOperationAction(ISD::CTLZ, VT, Expand);
717 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
718 setOperationAction(ISD::SHL, VT, Expand);
719 setOperationAction(ISD::SRA, VT, Expand);
720 setOperationAction(ISD::SRL, VT, Expand);
721 setOperationAction(ISD::ROTL, VT, Expand);
722 setOperationAction(ISD::ROTR, VT, Expand);
723 setOperationAction(ISD::BSWAP, VT, Expand);
724 setOperationAction(ISD::SETCC, VT, Expand);
725 setOperationAction(ISD::FLOG, VT, Expand);
726 setOperationAction(ISD::FLOG2, VT, Expand);
727 setOperationAction(ISD::FLOG10, VT, Expand);
728 setOperationAction(ISD::FEXP, VT, Expand);
729 setOperationAction(ISD::FEXP2, VT, Expand);
730 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
731 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
732 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
733 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
734 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
735 setOperationAction(ISD::TRUNCATE, VT, Expand);
736 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
737 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
738 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
739 setOperationAction(ISD::VSELECT, VT, Expand);
740 setOperationAction(ISD::SELECT_CC, VT, Expand);
741 for (MVT InnerVT : MVT::vector_valuetypes()) {
742 setTruncStoreAction(InnerVT, VT, Expand);
744 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
745 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
747 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
748 // types, we have to deal with them whether we ask for Expansion or not.
749 // Setting Expand causes its own optimisation problems though, so leave
751 if (VT.getVectorElementType() == MVT::i1)
752 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
754 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
755 // split/scalarized right now.
756 if (VT.getVectorElementType() == MVT::f16)
757 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
761 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
762 // with -msoft-float, disable use of MMX as well.
763 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
764 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
765 // No operations on x86mmx supported, everything uses intrinsics.
768 // MMX-sized vectors (other than x86mmx) are expected to be expanded
769 // into smaller operations.
770 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
771 setOperationAction(ISD::MULHS, MMXTy, Expand);
772 setOperationAction(ISD::AND, MMXTy, Expand);
773 setOperationAction(ISD::OR, MMXTy, Expand);
774 setOperationAction(ISD::XOR, MMXTy, Expand);
775 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
776 setOperationAction(ISD::SELECT, MMXTy, Expand);
777 setOperationAction(ISD::BITCAST, MMXTy, Expand);
779 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
781 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
782 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
784 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
785 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
786 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
787 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
788 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
789 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
790 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
791 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
792 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
793 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
794 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
795 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
796 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
797 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
800 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
801 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
803 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
804 // registers cannot be used even for integer operations.
805 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
806 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
807 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
808 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
810 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
811 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
812 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
813 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
814 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
815 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
816 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
817 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
818 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
819 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
820 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
821 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
822 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
823 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
824 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
825 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
826 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
827 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
828 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
829 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
830 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
831 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
832 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
834 setOperationAction(ISD::SMAX, MVT::v8i16, Legal);
835 setOperationAction(ISD::UMAX, MVT::v16i8, Legal);
836 setOperationAction(ISD::SMIN, MVT::v8i16, Legal);
837 setOperationAction(ISD::UMIN, MVT::v16i8, Legal);
839 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
840 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
841 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
842 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
844 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
845 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
846 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
847 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
848 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
850 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
851 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
852 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
853 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
855 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
856 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
857 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
858 // ISD::CTTZ v2i64 - scalarization is faster.
859 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
860 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
861 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
862 // ISD::CTTZ_ZERO_UNDEF v2i64 - scalarization is faster.
864 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
865 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
866 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
867 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
868 setOperationAction(ISD::VSELECT, VT, Custom);
869 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
872 // We support custom legalizing of sext and anyext loads for specific
873 // memory vector types which we can load as a scalar (or sequence of
874 // scalars) and extend in-register to a legal 128-bit vector type. For sext
875 // loads these must work with a single scalar load.
876 for (MVT VT : MVT::integer_vector_valuetypes()) {
877 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
878 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
879 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
880 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
881 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
882 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
883 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
884 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
885 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
888 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
889 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
890 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
891 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
892 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
893 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
894 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
895 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
897 if (Subtarget->is64Bit()) {
898 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
899 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
902 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
903 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
904 setOperationAction(ISD::AND, VT, Promote);
905 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
906 setOperationAction(ISD::OR, VT, Promote);
907 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
908 setOperationAction(ISD::XOR, VT, Promote);
909 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
910 setOperationAction(ISD::LOAD, VT, Promote);
911 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
912 setOperationAction(ISD::SELECT, VT, Promote);
913 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
916 // Custom lower v2i64 and v2f64 selects.
917 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
918 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
919 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
920 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
922 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
923 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
925 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
927 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
928 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
929 // As there is no 64-bit GPR available, we need build a special custom
930 // sequence to convert from v2i32 to v2f32.
931 if (!Subtarget->is64Bit())
932 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
934 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
935 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
937 for (MVT VT : MVT::fp_vector_valuetypes())
938 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
940 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
941 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
942 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
945 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
946 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
947 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
948 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
949 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
950 setOperationAction(ISD::FRINT, RoundedTy, Legal);
951 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
954 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
955 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
956 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
957 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
958 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
959 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
960 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
961 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
963 // FIXME: Do we need to handle scalar-to-vector here?
964 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
966 // We directly match byte blends in the backend as they match the VSELECT
968 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
970 // SSE41 brings specific instructions for doing vector sign extend even in
971 // cases where we don't have SRA.
972 for (MVT VT : MVT::integer_vector_valuetypes()) {
973 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
974 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
975 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
978 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
979 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
980 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
981 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
982 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
983 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
984 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
986 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
987 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
988 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
989 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
990 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
991 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
993 // i8 and i16 vectors are custom because the source register and source
994 // source memory operand types are not the same width. f32 vectors are
995 // custom since the immediate controlling the insert encodes additional
997 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
998 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
999 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1000 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1002 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1003 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1004 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1005 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1007 // FIXME: these should be Legal, but that's only for the case where
1008 // the index is constant. For now custom expand to deal with that.
1009 if (Subtarget->is64Bit()) {
1010 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1011 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1015 if (Subtarget->hasSSE2()) {
1016 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1017 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1018 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1020 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1021 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1023 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1024 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1026 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1027 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1029 // In the customized shift lowering, the legal cases in AVX2 will be
1031 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1032 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1034 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1035 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1037 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1038 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1041 if (Subtarget->hasXOP()) {
1042 setOperationAction(ISD::ROTL, MVT::v16i8, Custom);
1043 setOperationAction(ISD::ROTL, MVT::v8i16, Custom);
1044 setOperationAction(ISD::ROTL, MVT::v4i32, Custom);
1045 setOperationAction(ISD::ROTL, MVT::v2i64, Custom);
1046 setOperationAction(ISD::ROTL, MVT::v32i8, Custom);
1047 setOperationAction(ISD::ROTL, MVT::v16i16, Custom);
1048 setOperationAction(ISD::ROTL, MVT::v8i32, Custom);
1049 setOperationAction(ISD::ROTL, MVT::v4i64, Custom);
1052 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1053 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1054 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1055 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1056 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1057 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1058 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1060 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1061 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1062 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1064 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1065 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1066 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1067 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1068 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1069 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1070 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1071 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1072 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1073 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1074 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1075 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1077 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1078 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1079 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1080 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1081 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1082 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1083 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1084 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1085 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1086 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1087 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1088 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1090 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1091 // even though v8i16 is a legal type.
1092 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1093 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1094 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1096 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1097 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1098 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1100 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1101 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1103 for (MVT VT : MVT::fp_vector_valuetypes())
1104 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1107 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1109 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1110 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1112 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1113 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1115 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1116 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1117 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1118 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1120 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1121 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1122 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1124 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1125 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1126 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1127 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1128 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1129 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1130 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1131 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1132 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1133 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1134 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1135 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1137 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1138 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1139 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1140 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1142 setOperationAction(ISD::CTTZ, MVT::v32i8, Custom);
1143 setOperationAction(ISD::CTTZ, MVT::v16i16, Custom);
1144 setOperationAction(ISD::CTTZ, MVT::v8i32, Custom);
1145 setOperationAction(ISD::CTTZ, MVT::v4i64, Custom);
1146 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v32i8, Custom);
1147 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i16, Custom);
1148 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1149 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1151 if (Subtarget->hasAnyFMA()) {
1152 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1153 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1154 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1155 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1156 setOperationAction(ISD::FMA, MVT::f32, Legal);
1157 setOperationAction(ISD::FMA, MVT::f64, Legal);
1160 if (Subtarget->hasInt256()) {
1161 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1162 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1163 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1164 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1166 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1167 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1168 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1169 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1171 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1172 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1173 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1174 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1176 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1177 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1178 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1179 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1181 setOperationAction(ISD::SMAX, MVT::v32i8, Legal);
1182 setOperationAction(ISD::SMAX, MVT::v16i16, Legal);
1183 setOperationAction(ISD::SMAX, MVT::v8i32, Legal);
1184 setOperationAction(ISD::UMAX, MVT::v32i8, Legal);
1185 setOperationAction(ISD::UMAX, MVT::v16i16, Legal);
1186 setOperationAction(ISD::UMAX, MVT::v8i32, Legal);
1187 setOperationAction(ISD::SMIN, MVT::v32i8, Legal);
1188 setOperationAction(ISD::SMIN, MVT::v16i16, Legal);
1189 setOperationAction(ISD::SMIN, MVT::v8i32, Legal);
1190 setOperationAction(ISD::UMIN, MVT::v32i8, Legal);
1191 setOperationAction(ISD::UMIN, MVT::v16i16, Legal);
1192 setOperationAction(ISD::UMIN, MVT::v8i32, Legal);
1194 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1195 // when we have a 256bit-wide blend with immediate.
1196 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1198 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1199 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1200 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1201 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1202 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1203 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1204 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1206 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1207 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1208 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1209 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1210 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1211 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1213 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1214 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1215 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1216 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1218 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1219 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1220 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1221 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1223 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1224 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1225 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1226 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1228 setOperationAction(ISD::SMAX, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SMAX, MVT::v16i16, Custom);
1230 setOperationAction(ISD::SMAX, MVT::v8i32, Custom);
1231 setOperationAction(ISD::UMAX, MVT::v32i8, Custom);
1232 setOperationAction(ISD::UMAX, MVT::v16i16, Custom);
1233 setOperationAction(ISD::UMAX, MVT::v8i32, Custom);
1234 setOperationAction(ISD::SMIN, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SMIN, MVT::v16i16, Custom);
1236 setOperationAction(ISD::SMIN, MVT::v8i32, Custom);
1237 setOperationAction(ISD::UMIN, MVT::v32i8, Custom);
1238 setOperationAction(ISD::UMIN, MVT::v16i16, Custom);
1239 setOperationAction(ISD::UMIN, MVT::v8i32, Custom);
1242 // In the customized shift lowering, the legal cases in AVX2 will be
1244 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1245 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1247 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1248 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1250 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1251 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1253 // Custom lower several nodes for 256-bit types.
1254 for (MVT VT : MVT::vector_valuetypes()) {
1255 if (VT.getScalarSizeInBits() >= 32) {
1256 setOperationAction(ISD::MLOAD, VT, Legal);
1257 setOperationAction(ISD::MSTORE, VT, Legal);
1259 // Extract subvector is special because the value type
1260 // (result) is 128-bit but the source is 256-bit wide.
1261 if (VT.is128BitVector()) {
1262 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1264 // Do not attempt to custom lower other non-256-bit vectors
1265 if (!VT.is256BitVector())
1268 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1269 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1270 setOperationAction(ISD::VSELECT, VT, Custom);
1271 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1272 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1273 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1274 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1275 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1278 if (Subtarget->hasInt256())
1279 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1281 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1282 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
1283 setOperationAction(ISD::AND, VT, Promote);
1284 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1285 setOperationAction(ISD::OR, VT, Promote);
1286 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1287 setOperationAction(ISD::XOR, VT, Promote);
1288 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1289 setOperationAction(ISD::LOAD, VT, Promote);
1290 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1291 setOperationAction(ISD::SELECT, VT, Promote);
1292 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1296 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1297 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1298 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1299 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1300 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1302 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1303 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1304 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1306 for (MVT VT : MVT::fp_vector_valuetypes())
1307 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1309 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1310 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1311 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1312 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1313 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1314 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1315 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1316 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1317 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1318 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1319 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1320 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1322 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1323 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1324 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
1325 setOperationAction(ISD::XOR, MVT::i1, Legal);
1326 setOperationAction(ISD::OR, MVT::i1, Legal);
1327 setOperationAction(ISD::AND, MVT::i1, Legal);
1328 setOperationAction(ISD::SUB, MVT::i1, Custom);
1329 setOperationAction(ISD::ADD, MVT::i1, Custom);
1330 setOperationAction(ISD::MUL, MVT::i1, Custom);
1331 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1332 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1333 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1334 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1335 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1337 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1338 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1339 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1340 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1341 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1342 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1344 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1345 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1346 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1347 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1348 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1349 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1350 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1351 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1353 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1354 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1355 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1356 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1357 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1358 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1359 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1360 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1361 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1362 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1363 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1364 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1365 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1366 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1367 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1368 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1370 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1371 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1372 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1373 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1374 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1375 if (Subtarget->hasVLX()){
1376 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1377 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1378 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
1379 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
1380 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
1382 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
1383 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1384 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
1385 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
1386 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
1388 setOperationAction(ISD::MLOAD, MVT::v8i32, Custom);
1389 setOperationAction(ISD::MLOAD, MVT::v8f32, Custom);
1390 setOperationAction(ISD::MSTORE, MVT::v8i32, Custom);
1391 setOperationAction(ISD::MSTORE, MVT::v8f32, Custom);
1393 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1394 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1395 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1396 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i1, Custom);
1397 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i1, Custom);
1398 if (Subtarget->hasDQI()) {
1399 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1400 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1402 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1403 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1404 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1405 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1406 if (Subtarget->hasVLX()) {
1407 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Legal);
1408 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
1409 setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Legal);
1410 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
1411 setOperationAction(ISD::FP_TO_SINT, MVT::v4i64, Legal);
1412 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
1413 setOperationAction(ISD::FP_TO_UINT, MVT::v4i64, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
1417 if (Subtarget->hasVLX()) {
1418 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1421 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1422 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1423 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1424 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1425 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1427 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1432 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1433 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1437 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1438 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1439 if (Subtarget->hasDQI()) {
1440 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1441 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1443 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1444 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1445 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1446 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1447 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1448 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1449 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1450 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1451 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1452 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1454 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1455 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1456 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1457 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1458 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Custom);
1460 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1461 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1463 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1465 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1466 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1467 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v16i1, Custom);
1468 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1469 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1470 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1471 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1472 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1473 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1474 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1475 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1476 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1478 setOperationAction(ISD::SMAX, MVT::v16i32, Legal);
1479 setOperationAction(ISD::SMAX, MVT::v8i64, Legal);
1480 setOperationAction(ISD::UMAX, MVT::v16i32, Legal);
1481 setOperationAction(ISD::UMAX, MVT::v8i64, Legal);
1482 setOperationAction(ISD::SMIN, MVT::v16i32, Legal);
1483 setOperationAction(ISD::SMIN, MVT::v8i64, Legal);
1484 setOperationAction(ISD::UMIN, MVT::v16i32, Legal);
1485 setOperationAction(ISD::UMIN, MVT::v8i64, Legal);
1487 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1488 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1490 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1491 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1493 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1495 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1496 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1498 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1499 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1501 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1502 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1504 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1505 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1506 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1507 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1508 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1509 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1511 if (Subtarget->hasCDI()) {
1512 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1513 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i64, Legal);
1515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i32, Legal);
1517 setOperationAction(ISD::CTLZ, MVT::v8i16, Custom);
1518 setOperationAction(ISD::CTLZ, MVT::v16i8, Custom);
1519 setOperationAction(ISD::CTLZ, MVT::v16i16, Custom);
1520 setOperationAction(ISD::CTLZ, MVT::v32i8, Custom);
1521 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i16, Custom);
1522 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i8, Custom);
1523 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i16, Custom);
1524 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i8, Custom);
1526 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i64, Custom);
1527 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i32, Custom);
1529 if (Subtarget->hasVLX()) {
1530 setOperationAction(ISD::CTLZ, MVT::v4i64, Legal);
1531 setOperationAction(ISD::CTLZ, MVT::v8i32, Legal);
1532 setOperationAction(ISD::CTLZ, MVT::v2i64, Legal);
1533 setOperationAction(ISD::CTLZ, MVT::v4i32, Legal);
1534 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Legal);
1535 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Legal);
1536 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Legal);
1537 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Legal);
1539 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1540 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1541 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
1542 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
1544 setOperationAction(ISD::CTLZ, MVT::v4i64, Custom);
1545 setOperationAction(ISD::CTLZ, MVT::v8i32, Custom);
1546 setOperationAction(ISD::CTLZ, MVT::v2i64, Custom);
1547 setOperationAction(ISD::CTLZ, MVT::v4i32, Custom);
1548 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Custom);
1549 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Custom);
1550 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Custom);
1551 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Custom);
1553 } // Subtarget->hasCDI()
1555 if (Subtarget->hasDQI()) {
1556 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1557 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1558 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1560 // Custom lower several nodes.
1561 for (MVT VT : MVT::vector_valuetypes()) {
1562 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1564 setOperationAction(ISD::AND, VT, Legal);
1565 setOperationAction(ISD::OR, VT, Legal);
1566 setOperationAction(ISD::XOR, VT, Legal);
1568 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1569 setOperationAction(ISD::MGATHER, VT, Custom);
1570 setOperationAction(ISD::MSCATTER, VT, Custom);
1572 // Extract subvector is special because the value type
1573 // (result) is 256/128-bit but the source is 512-bit wide.
1574 if (VT.is128BitVector() || VT.is256BitVector()) {
1575 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1577 if (VT.getVectorElementType() == MVT::i1)
1578 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1580 // Do not attempt to custom lower other non-512-bit vectors
1581 if (!VT.is512BitVector())
1584 if (EltSize >= 32) {
1585 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1586 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1587 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1588 setOperationAction(ISD::VSELECT, VT, Legal);
1589 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1590 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1591 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1592 setOperationAction(ISD::MLOAD, VT, Legal);
1593 setOperationAction(ISD::MSTORE, VT, Legal);
1596 for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32 }) {
1597 setOperationAction(ISD::SELECT, VT, Promote);
1598 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1602 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1603 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1604 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1606 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1607 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1609 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1610 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1611 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1612 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1613 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1614 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1615 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1616 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1617 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1618 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1619 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1620 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1621 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1622 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i16, Custom);
1623 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i8, Custom);
1624 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1625 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1626 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i16, Custom);
1627 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i8, Custom);
1628 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v32i16, Custom);
1629 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v64i8, Custom);
1630 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1631 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1632 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1633 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1634 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1635 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1636 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
1637 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i8, Custom);
1638 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1639 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1640 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1641 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1642 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i16, Custom);
1643 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i8, Custom);
1644 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1645 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1646 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1647 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1648 setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);
1649 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i1, Custom);
1650 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i1, Custom);
1652 setOperationAction(ISD::SMAX, MVT::v64i8, Legal);
1653 setOperationAction(ISD::SMAX, MVT::v32i16, Legal);
1654 setOperationAction(ISD::UMAX, MVT::v64i8, Legal);
1655 setOperationAction(ISD::UMAX, MVT::v32i16, Legal);
1656 setOperationAction(ISD::SMIN, MVT::v64i8, Legal);
1657 setOperationAction(ISD::SMIN, MVT::v32i16, Legal);
1658 setOperationAction(ISD::UMIN, MVT::v64i8, Legal);
1659 setOperationAction(ISD::UMIN, MVT::v32i16, Legal);
1661 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1662 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
1663 if (Subtarget->hasVLX())
1664 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
1666 if (Subtarget->hasCDI()) {
1667 setOperationAction(ISD::CTLZ, MVT::v32i16, Custom);
1668 setOperationAction(ISD::CTLZ, MVT::v64i8, Custom);
1669 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i16, Custom);
1670 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v64i8, Custom);
1673 for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1674 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1675 setOperationAction(ISD::VSELECT, VT, Legal);
1679 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1680 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1681 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1683 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1684 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1685 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1686 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1687 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1688 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1689 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1690 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1691 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1692 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1693 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i1, Custom);
1694 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i1, Custom);
1696 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1697 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1698 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1699 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1700 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1701 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1702 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1703 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1705 setOperationAction(ISD::SMAX, MVT::v2i64, Legal);
1706 setOperationAction(ISD::SMAX, MVT::v4i64, Legal);
1707 setOperationAction(ISD::UMAX, MVT::v2i64, Legal);
1708 setOperationAction(ISD::UMAX, MVT::v4i64, Legal);
1709 setOperationAction(ISD::SMIN, MVT::v2i64, Legal);
1710 setOperationAction(ISD::SMIN, MVT::v4i64, Legal);
1711 setOperationAction(ISD::UMIN, MVT::v2i64, Legal);
1712 setOperationAction(ISD::UMIN, MVT::v4i64, Legal);
1715 // We want to custom lower some of our intrinsics.
1716 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1717 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1718 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1719 if (!Subtarget->is64Bit()) {
1720 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1721 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
1724 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1725 // handle type legalization for these operations here.
1727 // FIXME: We really should do custom legalization for addition and
1728 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1729 // than generic legalization for 64-bit multiplication-with-overflow, though.
1730 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
1731 if (VT == MVT::i64 && !Subtarget->is64Bit())
1733 // Add/Sub/Mul with overflow operations are custom lowered.
1734 setOperationAction(ISD::SADDO, VT, Custom);
1735 setOperationAction(ISD::UADDO, VT, Custom);
1736 setOperationAction(ISD::SSUBO, VT, Custom);
1737 setOperationAction(ISD::USUBO, VT, Custom);
1738 setOperationAction(ISD::SMULO, VT, Custom);
1739 setOperationAction(ISD::UMULO, VT, Custom);
1742 if (!Subtarget->is64Bit()) {
1743 // These libcalls are not available in 32-bit.
1744 setLibcallName(RTLIB::SHL_I128, nullptr);
1745 setLibcallName(RTLIB::SRL_I128, nullptr);
1746 setLibcallName(RTLIB::SRA_I128, nullptr);
1749 // Combine sin / cos into one node or libcall if possible.
1750 if (Subtarget->hasSinCos()) {
1751 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1752 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1753 if (Subtarget->isTargetDarwin()) {
1754 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1755 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1756 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1757 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1761 if (Subtarget->isTargetWin64()) {
1762 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1763 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1764 setOperationAction(ISD::SREM, MVT::i128, Custom);
1765 setOperationAction(ISD::UREM, MVT::i128, Custom);
1766 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1767 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1770 // We have target-specific dag combine patterns for the following nodes:
1771 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1772 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1773 setTargetDAGCombine(ISD::BITCAST);
1774 setTargetDAGCombine(ISD::VSELECT);
1775 setTargetDAGCombine(ISD::SELECT);
1776 setTargetDAGCombine(ISD::SHL);
1777 setTargetDAGCombine(ISD::SRA);
1778 setTargetDAGCombine(ISD::SRL);
1779 setTargetDAGCombine(ISD::OR);
1780 setTargetDAGCombine(ISD::AND);
1781 setTargetDAGCombine(ISD::ADD);
1782 setTargetDAGCombine(ISD::FADD);
1783 setTargetDAGCombine(ISD::FSUB);
1784 setTargetDAGCombine(ISD::FNEG);
1785 setTargetDAGCombine(ISD::FMA);
1786 setTargetDAGCombine(ISD::SUB);
1787 setTargetDAGCombine(ISD::LOAD);
1788 setTargetDAGCombine(ISD::MLOAD);
1789 setTargetDAGCombine(ISD::STORE);
1790 setTargetDAGCombine(ISD::MSTORE);
1791 setTargetDAGCombine(ISD::TRUNCATE);
1792 setTargetDAGCombine(ISD::ZERO_EXTEND);
1793 setTargetDAGCombine(ISD::ANY_EXTEND);
1794 setTargetDAGCombine(ISD::SIGN_EXTEND);
1795 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1796 setTargetDAGCombine(ISD::SINT_TO_FP);
1797 setTargetDAGCombine(ISD::UINT_TO_FP);
1798 setTargetDAGCombine(ISD::SETCC);
1799 setTargetDAGCombine(ISD::BUILD_VECTOR);
1800 setTargetDAGCombine(ISD::MUL);
1801 setTargetDAGCombine(ISD::XOR);
1803 computeRegisterProperties(Subtarget->getRegisterInfo());
1805 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1806 MaxStoresPerMemsetOptSize = 8;
1807 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1808 MaxStoresPerMemcpyOptSize = 4;
1809 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1810 MaxStoresPerMemmoveOptSize = 4;
1811 setPrefLoopAlignment(4); // 2^4 bytes.
1813 // A predictable cmov does not hurt on an in-order CPU.
1814 // FIXME: Use a CPU attribute to trigger this, not a CPU model.
1815 PredictableSelectIsExpensive = !Subtarget->isAtom();
1816 EnableExtLdPromotion = true;
1817 setPrefFunctionAlignment(4); // 2^4 bytes.
1819 verifyIntrinsicTables();
1822 // This has so far only been implemented for 64-bit MachO.
1823 bool X86TargetLowering::useLoadStackGuardNode() const {
1824 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1827 TargetLoweringBase::LegalizeTypeAction
1828 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1829 if (ExperimentalVectorWideningLegalization &&
1830 VT.getVectorNumElements() != 1 &&
1831 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1832 return TypeWidenVector;
1834 return TargetLoweringBase::getPreferredVectorAction(VT);
1837 EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1840 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1842 if (VT.isSimple()) {
1843 MVT VVT = VT.getSimpleVT();
1844 const unsigned NumElts = VVT.getVectorNumElements();
1845 const MVT EltVT = VVT.getVectorElementType();
1846 if (VVT.is512BitVector()) {
1847 if (Subtarget->hasAVX512())
1848 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1849 EltVT == MVT::f32 || EltVT == MVT::f64)
1851 case 8: return MVT::v8i1;
1852 case 16: return MVT::v16i1;
1854 if (Subtarget->hasBWI())
1855 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1857 case 32: return MVT::v32i1;
1858 case 64: return MVT::v64i1;
1862 if (VVT.is256BitVector() || VVT.is128BitVector()) {
1863 if (Subtarget->hasVLX())
1864 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1865 EltVT == MVT::f32 || EltVT == MVT::f64)
1867 case 2: return MVT::v2i1;
1868 case 4: return MVT::v4i1;
1869 case 8: return MVT::v8i1;
1871 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1872 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1874 case 8: return MVT::v8i1;
1875 case 16: return MVT::v16i1;
1876 case 32: return MVT::v32i1;
1881 return VT.changeVectorElementTypeToInteger();
1884 /// Helper for getByValTypeAlignment to determine
1885 /// the desired ByVal argument alignment.
1886 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1889 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1890 if (VTy->getBitWidth() == 128)
1892 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1893 unsigned EltAlign = 0;
1894 getMaxByValAlign(ATy->getElementType(), EltAlign);
1895 if (EltAlign > MaxAlign)
1896 MaxAlign = EltAlign;
1897 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1898 for (auto *EltTy : STy->elements()) {
1899 unsigned EltAlign = 0;
1900 getMaxByValAlign(EltTy, EltAlign);
1901 if (EltAlign > MaxAlign)
1902 MaxAlign = EltAlign;
1909 /// Return the desired alignment for ByVal aggregate
1910 /// function arguments in the caller parameter area. For X86, aggregates
1911 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1912 /// are at 4-byte boundaries.
1913 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,
1914 const DataLayout &DL) const {
1915 if (Subtarget->is64Bit()) {
1916 // Max of 8 and alignment of type.
1917 unsigned TyAlign = DL.getABITypeAlignment(Ty);
1924 if (Subtarget->hasSSE1())
1925 getMaxByValAlign(Ty, Align);
1929 /// Returns the target specific optimal type for load
1930 /// and store operations as a result of memset, memcpy, and memmove
1931 /// lowering. If DstAlign is zero that means it's safe to destination
1932 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1933 /// means there isn't a need to check it against alignment requirement,
1934 /// probably because the source does not need to be loaded. If 'IsMemset' is
1935 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1936 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1937 /// source is constant so it does not need to be loaded.
1938 /// It returns EVT::Other if the type should be determined using generic
1939 /// target-independent logic.
1941 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1942 unsigned DstAlign, unsigned SrcAlign,
1943 bool IsMemset, bool ZeroMemset,
1945 MachineFunction &MF) const {
1946 const Function *F = MF.getFunction();
1947 if ((!IsMemset || ZeroMemset) &&
1948 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1950 (!Subtarget->isUnalignedMem16Slow() ||
1951 ((DstAlign == 0 || DstAlign >= 16) &&
1952 (SrcAlign == 0 || SrcAlign >= 16)))) {
1954 // FIXME: Check if unaligned 32-byte accesses are slow.
1955 if (Subtarget->hasInt256())
1957 if (Subtarget->hasFp256())
1960 if (Subtarget->hasSSE2())
1962 if (Subtarget->hasSSE1())
1964 } else if (!MemcpyStrSrc && Size >= 8 &&
1965 !Subtarget->is64Bit() &&
1966 Subtarget->hasSSE2()) {
1967 // Do not use f64 to lower memcpy if source is string constant. It's
1968 // better to use i32 to avoid the loads.
1972 // This is a compromise. If we reach here, unaligned accesses may be slow on
1973 // this target. However, creating smaller, aligned accesses could be even
1974 // slower and would certainly be a lot more code.
1975 if (Subtarget->is64Bit() && Size >= 8)
1980 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1982 return X86ScalarSSEf32;
1983 else if (VT == MVT::f64)
1984 return X86ScalarSSEf64;
1989 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1994 switch (VT.getSizeInBits()) {
1996 // 8-byte and under are always assumed to be fast.
2000 *Fast = !Subtarget->isUnalignedMem16Slow();
2003 *Fast = !Subtarget->isUnalignedMem32Slow();
2005 // TODO: What about AVX-512 (512-bit) accesses?
2008 // Misaligned accesses of any size are always allowed.
2012 /// Return the entry encoding for a jump table in the
2013 /// current function. The returned value is a member of the
2014 /// MachineJumpTableInfo::JTEntryKind enum.
2015 unsigned X86TargetLowering::getJumpTableEncoding() const {
2016 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
2018 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2019 Subtarget->isPICStyleGOT())
2020 return MachineJumpTableInfo::EK_Custom32;
2022 // Otherwise, use the normal jump table encoding heuristics.
2023 return TargetLowering::getJumpTableEncoding();
2026 bool X86TargetLowering::useSoftFloat() const {
2027 return Subtarget->useSoftFloat();
2031 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
2032 const MachineBasicBlock *MBB,
2033 unsigned uid,MCContext &Ctx) const{
2034 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
2035 Subtarget->isPICStyleGOT());
2036 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2038 return MCSymbolRefExpr::create(MBB->getSymbol(),
2039 MCSymbolRefExpr::VK_GOTOFF, Ctx);
2042 /// Returns relocation base for the given PIC jumptable.
2043 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
2044 SelectionDAG &DAG) const {
2045 if (!Subtarget->is64Bit())
2046 // This doesn't have SDLoc associated with it, but is not really the
2047 // same as a Register.
2048 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2049 getPointerTy(DAG.getDataLayout()));
2053 /// This returns the relocation base for the given PIC jumptable,
2054 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2055 const MCExpr *X86TargetLowering::
2056 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
2057 MCContext &Ctx) const {
2058 // X86-64 uses RIP relative addressing based on the jump table label.
2059 if (Subtarget->isPICStyleRIPRel())
2060 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2062 // Otherwise, the reference is relative to the PIC base.
2063 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2066 std::pair<const TargetRegisterClass *, uint8_t>
2067 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2069 const TargetRegisterClass *RRC = nullptr;
2071 switch (VT.SimpleTy) {
2073 return TargetLowering::findRepresentativeClass(TRI, VT);
2074 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2075 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2078 RRC = &X86::VR64RegClass;
2080 case MVT::f32: case MVT::f64:
2081 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2082 case MVT::v4f32: case MVT::v2f64:
2083 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
2085 RRC = &X86::VR128RegClass;
2088 return std::make_pair(RRC, Cost);
2091 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
2092 unsigned &Offset) const {
2093 if (!Subtarget->isTargetLinux())
2096 if (Subtarget->is64Bit()) {
2097 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
2099 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2111 Value *X86TargetLowering::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
2112 if (!Subtarget->isTargetAndroid())
2113 return TargetLowering::getSafeStackPointerLocation(IRB);
2115 // Android provides a fixed TLS slot for the SafeStack pointer. See the
2116 // definition of TLS_SLOT_SAFESTACK in
2117 // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2118 unsigned AddressSpace, Offset;
2119 if (Subtarget->is64Bit()) {
2120 // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2122 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2132 return ConstantExpr::getIntToPtr(
2133 ConstantInt::get(Type::getInt32Ty(IRB.getContext()), Offset),
2134 Type::getInt8PtrTy(IRB.getContext())->getPointerTo(AddressSpace));
2137 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
2138 unsigned DestAS) const {
2139 assert(SrcAS != DestAS && "Expected different address spaces!");
2141 return SrcAS < 256 && DestAS < 256;
2144 //===----------------------------------------------------------------------===//
2145 // Return Value Calling Convention Implementation
2146 //===----------------------------------------------------------------------===//
2148 #include "X86GenCallingConv.inc"
2150 bool X86TargetLowering::CanLowerReturn(
2151 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2152 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2153 SmallVector<CCValAssign, 16> RVLocs;
2154 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2155 return CCInfo.CheckReturn(Outs, RetCC_X86);
2158 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2159 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2164 X86TargetLowering::LowerReturn(SDValue Chain,
2165 CallingConv::ID CallConv, bool isVarArg,
2166 const SmallVectorImpl<ISD::OutputArg> &Outs,
2167 const SmallVectorImpl<SDValue> &OutVals,
2168 SDLoc dl, SelectionDAG &DAG) const {
2169 MachineFunction &MF = DAG.getMachineFunction();
2170 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2172 SmallVector<CCValAssign, 16> RVLocs;
2173 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2174 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2177 SmallVector<SDValue, 6> RetOps;
2178 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2179 // Operand #1 = Bytes To Pop
2180 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2183 // Copy the result values into the output registers.
2184 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2185 CCValAssign &VA = RVLocs[i];
2186 assert(VA.isRegLoc() && "Can only return in registers!");
2187 SDValue ValToCopy = OutVals[i];
2188 EVT ValVT = ValToCopy.getValueType();
2190 // Promote values to the appropriate types.
2191 if (VA.getLocInfo() == CCValAssign::SExt)
2192 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2193 else if (VA.getLocInfo() == CCValAssign::ZExt)
2194 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2195 else if (VA.getLocInfo() == CCValAssign::AExt) {
2196 if (ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1)
2197 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2199 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2201 else if (VA.getLocInfo() == CCValAssign::BCvt)
2202 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2204 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2205 "Unexpected FP-extend for return value.");
2207 // If this is x86-64, and we disabled SSE, we can't return FP values,
2208 // or SSE or MMX vectors.
2209 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2210 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2211 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2212 report_fatal_error("SSE register return with SSE disabled");
2214 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2215 // llvm-gcc has never done it right and no one has noticed, so this
2216 // should be OK for now.
2217 if (ValVT == MVT::f64 &&
2218 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2219 report_fatal_error("SSE2 register return with SSE2 disabled");
2221 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2222 // the RET instruction and handled by the FP Stackifier.
2223 if (VA.getLocReg() == X86::FP0 ||
2224 VA.getLocReg() == X86::FP1) {
2225 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2226 // change the value to the FP stack register class.
2227 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2228 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2229 RetOps.push_back(ValToCopy);
2230 // Don't emit a copytoreg.
2234 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2235 // which is returned in RAX / RDX.
2236 if (Subtarget->is64Bit()) {
2237 if (ValVT == MVT::x86mmx) {
2238 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2239 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2240 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2242 // If we don't have SSE2 available, convert to v4f32 so the generated
2243 // register is legal.
2244 if (!Subtarget->hasSSE2())
2245 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2250 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2251 Flag = Chain.getValue(1);
2252 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2255 // All x86 ABIs require that for returning structs by value we copy
2256 // the sret argument into %rax/%eax (depending on ABI) for the return.
2257 // We saved the argument into a virtual register in the entry block,
2258 // so now we copy the value out and into %rax/%eax.
2260 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2261 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2262 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2263 // either case FuncInfo->setSRetReturnReg() will have been called.
2264 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2265 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg,
2266 getPointerTy(MF.getDataLayout()));
2269 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2270 X86::RAX : X86::EAX;
2271 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2272 Flag = Chain.getValue(1);
2274 // RAX/EAX now acts like a return value.
2276 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2279 RetOps[0] = Chain; // Update chain.
2281 // Add the flag if we have it.
2283 RetOps.push_back(Flag);
2285 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2288 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2289 if (N->getNumValues() != 1)
2291 if (!N->hasNUsesOfValue(1, 0))
2294 SDValue TCChain = Chain;
2295 SDNode *Copy = *N->use_begin();
2296 if (Copy->getOpcode() == ISD::CopyToReg) {
2297 // If the copy has a glue operand, we conservatively assume it isn't safe to
2298 // perform a tail call.
2299 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2301 TCChain = Copy->getOperand(0);
2302 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2305 bool HasRet = false;
2306 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2308 if (UI->getOpcode() != X86ISD::RET_FLAG)
2310 // If we are returning more than one value, we can definitely
2311 // not make a tail call see PR19530
2312 if (UI->getNumOperands() > 4)
2314 if (UI->getNumOperands() == 4 &&
2315 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2328 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2329 ISD::NodeType ExtendKind) const {
2331 // TODO: Is this also valid on 32-bit?
2332 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2333 ReturnMVT = MVT::i8;
2335 ReturnMVT = MVT::i32;
2337 EVT MinVT = getRegisterType(Context, ReturnMVT);
2338 return VT.bitsLT(MinVT) ? MinVT : VT;
2341 /// Lower the result values of a call into the
2342 /// appropriate copies out of appropriate physical registers.
2345 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2346 CallingConv::ID CallConv, bool isVarArg,
2347 const SmallVectorImpl<ISD::InputArg> &Ins,
2348 SDLoc dl, SelectionDAG &DAG,
2349 SmallVectorImpl<SDValue> &InVals) const {
2351 // Assign locations to each value returned by this call.
2352 SmallVector<CCValAssign, 16> RVLocs;
2353 bool Is64Bit = Subtarget->is64Bit();
2354 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2356 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2358 // Copy all of the result registers out of their specified physreg.
2359 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2360 CCValAssign &VA = RVLocs[i];
2361 EVT CopyVT = VA.getLocVT();
2363 // If this is x86-64, and we disabled SSE, we can't return FP values
2364 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2365 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2366 report_fatal_error("SSE register return with SSE disabled");
2369 // If we prefer to use the value in xmm registers, copy it out as f80 and
2370 // use a truncate to move it from fp stack reg to xmm reg.
2371 bool RoundAfterCopy = false;
2372 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2373 isScalarFPTypeInSSEReg(VA.getValVT())) {
2375 RoundAfterCopy = (CopyVT != VA.getLocVT());
2378 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2379 CopyVT, InFlag).getValue(1);
2380 SDValue Val = Chain.getValue(0);
2383 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2384 // This truncation won't change the value.
2385 DAG.getIntPtrConstant(1, dl));
2387 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2388 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2390 InFlag = Chain.getValue(2);
2391 InVals.push_back(Val);
2397 //===----------------------------------------------------------------------===//
2398 // C & StdCall & Fast Calling Convention implementation
2399 //===----------------------------------------------------------------------===//
2400 // StdCall calling convention seems to be standard for many Windows' API
2401 // routines and around. It differs from C calling convention just a little:
2402 // callee should clean up the stack, not caller. Symbols should be also
2403 // decorated in some fancy way :) It doesn't support any vector arguments.
2404 // For info on fast calling convention see Fast Calling Convention (tail call)
2405 // implementation LowerX86_32FastCCCallTo.
2407 /// CallIsStructReturn - Determines whether a call uses struct return
2409 enum StructReturnType {
2414 static StructReturnType
2415 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2417 return NotStructReturn;
2419 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2420 if (!Flags.isSRet())
2421 return NotStructReturn;
2422 if (Flags.isInReg())
2423 return RegStructReturn;
2424 return StackStructReturn;
2427 /// Determines whether a function uses struct return semantics.
2428 static StructReturnType
2429 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2431 return NotStructReturn;
2433 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2434 if (!Flags.isSRet())
2435 return NotStructReturn;
2436 if (Flags.isInReg())
2437 return RegStructReturn;
2438 return StackStructReturn;
2441 /// Make a copy of an aggregate at address specified by "Src" to address
2442 /// "Dst" with size and alignment information specified by the specific
2443 /// parameter attribute. The copy will be passed as a byval function parameter.
2445 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2446 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2448 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2450 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2451 /*isVolatile*/false, /*AlwaysInline=*/true,
2452 /*isTailCall*/false,
2453 MachinePointerInfo(), MachinePointerInfo());
2456 /// Return true if the calling convention is one that we can guarantee TCO for.
2457 static bool canGuaranteeTCO(CallingConv::ID CC) {
2458 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2459 CC == CallingConv::HiPE || CC == CallingConv::HHVM);
2462 /// Return true if we might ever do TCO for calls with this calling convention.
2463 static bool mayTailCallThisCC(CallingConv::ID CC) {
2465 // C calling conventions:
2466 case CallingConv::C:
2467 case CallingConv::X86_64_Win64:
2468 case CallingConv::X86_64_SysV:
2469 // Callee pop conventions:
2470 case CallingConv::X86_ThisCall:
2471 case CallingConv::X86_StdCall:
2472 case CallingConv::X86_VectorCall:
2473 case CallingConv::X86_FastCall:
2476 return canGuaranteeTCO(CC);
2480 /// Return true if the function is being made into a tailcall target by
2481 /// changing its ABI.
2482 static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
2483 return GuaranteedTailCallOpt && canGuaranteeTCO(CC);
2486 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2488 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2489 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2493 CallingConv::ID CalleeCC = CS.getCallingConv();
2494 if (!mayTailCallThisCC(CalleeCC))
2501 X86TargetLowering::LowerMemArgument(SDValue Chain,
2502 CallingConv::ID CallConv,
2503 const SmallVectorImpl<ISD::InputArg> &Ins,
2504 SDLoc dl, SelectionDAG &DAG,
2505 const CCValAssign &VA,
2506 MachineFrameInfo *MFI,
2508 // Create the nodes corresponding to a load from this parameter slot.
2509 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2510 bool AlwaysUseMutable = shouldGuaranteeTCO(
2511 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2512 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2515 // If value is passed by pointer we have address passed instead of the value
2517 bool ExtendedInMem = VA.isExtInLoc() &&
2518 VA.getValVT().getScalarType() == MVT::i1;
2520 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2521 ValVT = VA.getLocVT();
2523 ValVT = VA.getValVT();
2525 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2526 // changed with more analysis.
2527 // In case of tail call optimization mark all arguments mutable. Since they
2528 // could be overwritten by lowering of arguments in case of a tail call.
2529 if (Flags.isByVal()) {
2530 unsigned Bytes = Flags.getByValSize();
2531 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2532 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2533 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2535 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2536 VA.getLocMemOffset(), isImmutable);
2537 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2538 SDValue Val = DAG.getLoad(
2539 ValVT, dl, Chain, FIN,
2540 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
2542 return ExtendedInMem ?
2543 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2547 // FIXME: Get this from tablegen.
2548 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2549 const X86Subtarget *Subtarget) {
2550 assert(Subtarget->is64Bit());
2552 if (Subtarget->isCallingConvWin64(CallConv)) {
2553 static const MCPhysReg GPR64ArgRegsWin64[] = {
2554 X86::RCX, X86::RDX, X86::R8, X86::R9
2556 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2559 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2560 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2562 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2565 // FIXME: Get this from tablegen.
2566 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2567 CallingConv::ID CallConv,
2568 const X86Subtarget *Subtarget) {
2569 assert(Subtarget->is64Bit());
2570 if (Subtarget->isCallingConvWin64(CallConv)) {
2571 // The XMM registers which might contain var arg parameters are shadowed
2572 // in their paired GPR. So we only need to save the GPR to their home
2574 // TODO: __vectorcall will change this.
2578 const Function *Fn = MF.getFunction();
2579 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2580 bool isSoftFloat = Subtarget->useSoftFloat();
2581 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2582 "SSE register cannot be used when SSE is disabled!");
2583 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2584 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2588 static const MCPhysReg XMMArgRegs64Bit[] = {
2589 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2590 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2592 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2595 SDValue X86TargetLowering::LowerFormalArguments(
2596 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2597 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
2598 SmallVectorImpl<SDValue> &InVals) const {
2599 MachineFunction &MF = DAG.getMachineFunction();
2600 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2601 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2603 const Function* Fn = MF.getFunction();
2604 if (Fn->hasExternalLinkage() &&
2605 Subtarget->isTargetCygMing() &&
2606 Fn->getName() == "main")
2607 FuncInfo->setForceFramePointer(true);
2609 MachineFrameInfo *MFI = MF.getFrameInfo();
2610 bool Is64Bit = Subtarget->is64Bit();
2611 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2613 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&
2614 "Var args not supported with calling convention fastcc, ghc or hipe");
2616 // Assign locations to all of the incoming arguments.
2617 SmallVector<CCValAssign, 16> ArgLocs;
2618 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2620 // Allocate shadow area for Win64
2622 CCInfo.AllocateStack(32, 8);
2624 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2626 unsigned LastVal = ~0U;
2628 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2629 CCValAssign &VA = ArgLocs[i];
2630 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2632 assert(VA.getValNo() != LastVal &&
2633 "Don't support value assigned to multiple locs yet");
2635 LastVal = VA.getValNo();
2637 if (VA.isRegLoc()) {
2638 EVT RegVT = VA.getLocVT();
2639 const TargetRegisterClass *RC;
2640 if (RegVT == MVT::i32)
2641 RC = &X86::GR32RegClass;
2642 else if (Is64Bit && RegVT == MVT::i64)
2643 RC = &X86::GR64RegClass;
2644 else if (RegVT == MVT::f32)
2645 RC = &X86::FR32RegClass;
2646 else if (RegVT == MVT::f64)
2647 RC = &X86::FR64RegClass;
2648 else if (RegVT.is512BitVector())
2649 RC = &X86::VR512RegClass;
2650 else if (RegVT.is256BitVector())
2651 RC = &X86::VR256RegClass;
2652 else if (RegVT.is128BitVector())
2653 RC = &X86::VR128RegClass;
2654 else if (RegVT == MVT::x86mmx)
2655 RC = &X86::VR64RegClass;
2656 else if (RegVT == MVT::i1)
2657 RC = &X86::VK1RegClass;
2658 else if (RegVT == MVT::v8i1)
2659 RC = &X86::VK8RegClass;
2660 else if (RegVT == MVT::v16i1)
2661 RC = &X86::VK16RegClass;
2662 else if (RegVT == MVT::v32i1)
2663 RC = &X86::VK32RegClass;
2664 else if (RegVT == MVT::v64i1)
2665 RC = &X86::VK64RegClass;
2667 llvm_unreachable("Unknown argument type!");
2669 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2670 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2672 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2673 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2675 if (VA.getLocInfo() == CCValAssign::SExt)
2676 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2677 DAG.getValueType(VA.getValVT()));
2678 else if (VA.getLocInfo() == CCValAssign::ZExt)
2679 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2680 DAG.getValueType(VA.getValVT()));
2681 else if (VA.getLocInfo() == CCValAssign::BCvt)
2682 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2684 if (VA.isExtInLoc()) {
2685 // Handle MMX values passed in XMM regs.
2686 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2687 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2689 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2692 assert(VA.isMemLoc());
2693 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2696 // If value is passed via pointer - do a load.
2697 if (VA.getLocInfo() == CCValAssign::Indirect)
2698 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2699 MachinePointerInfo(), false, false, false, 0);
2701 InVals.push_back(ArgValue);
2704 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2705 // All x86 ABIs require that for returning structs by value we copy the
2706 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2707 // the argument into a virtual register so that we can access it from the
2709 if (Ins[i].Flags.isSRet()) {
2710 unsigned Reg = FuncInfo->getSRetReturnReg();
2712 MVT PtrTy = getPointerTy(DAG.getDataLayout());
2713 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2714 FuncInfo->setSRetReturnReg(Reg);
2716 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2717 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2722 unsigned StackSize = CCInfo.getNextStackOffset();
2723 // Align stack specially for tail calls.
2724 if (shouldGuaranteeTCO(CallConv,
2725 MF.getTarget().Options.GuaranteedTailCallOpt))
2726 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2728 // If the function takes variable number of arguments, make a frame index for
2729 // the start of the first vararg value... for expansion of llvm.va_start. We
2730 // can skip this if there are no va_start calls.
2731 if (MFI->hasVAStart() &&
2732 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2733 CallConv != CallingConv::X86_ThisCall))) {
2734 FuncInfo->setVarArgsFrameIndex(
2735 MFI->CreateFixedObject(1, StackSize, true));
2738 // Figure out if XMM registers are in use.
2739 assert(!(Subtarget->useSoftFloat() &&
2740 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2741 "SSE register cannot be used when SSE is disabled!");
2743 // 64-bit calling conventions support varargs and register parameters, so we
2744 // have to do extra work to spill them in the prologue.
2745 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2746 // Find the first unallocated argument registers.
2747 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2748 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2749 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2750 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2751 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2752 "SSE register cannot be used when SSE is disabled!");
2754 // Gather all the live in physical registers.
2755 SmallVector<SDValue, 6> LiveGPRs;
2756 SmallVector<SDValue, 8> LiveXMMRegs;
2758 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2759 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2761 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2763 if (!ArgXMMs.empty()) {
2764 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2765 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2766 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2767 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2768 LiveXMMRegs.push_back(
2769 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2774 // Get to the caller-allocated home save location. Add 8 to account
2775 // for the return address.
2776 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2777 FuncInfo->setRegSaveFrameIndex(
2778 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2779 // Fixup to set vararg frame on shadow area (4 x i64).
2781 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2783 // For X86-64, if there are vararg parameters that are passed via
2784 // registers, then we must store them to their spots on the stack so
2785 // they may be loaded by deferencing the result of va_next.
2786 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2787 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2788 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2789 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2792 // Store the integer parameter registers.
2793 SmallVector<SDValue, 8> MemOps;
2794 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2795 getPointerTy(DAG.getDataLayout()));
2796 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2797 for (SDValue Val : LiveGPRs) {
2798 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2799 RSFIN, DAG.getIntPtrConstant(Offset, dl));
2801 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2802 MachinePointerInfo::getFixedStack(
2803 DAG.getMachineFunction(),
2804 FuncInfo->getRegSaveFrameIndex(), Offset),
2806 MemOps.push_back(Store);
2810 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2811 // Now store the XMM (fp + vector) parameter registers.
2812 SmallVector<SDValue, 12> SaveXMMOps;
2813 SaveXMMOps.push_back(Chain);
2814 SaveXMMOps.push_back(ALVal);
2815 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2816 FuncInfo->getRegSaveFrameIndex(), dl));
2817 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2818 FuncInfo->getVarArgsFPOffset(), dl));
2819 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2821 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2822 MVT::Other, SaveXMMOps));
2825 if (!MemOps.empty())
2826 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2829 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2830 // Find the largest legal vector type.
2831 MVT VecVT = MVT::Other;
2832 // FIXME: Only some x86_32 calling conventions support AVX512.
2833 if (Subtarget->hasAVX512() &&
2834 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2835 CallConv == CallingConv::Intel_OCL_BI)))
2836 VecVT = MVT::v16f32;
2837 else if (Subtarget->hasAVX())
2839 else if (Subtarget->hasSSE2())
2842 // We forward some GPRs and some vector types.
2843 SmallVector<MVT, 2> RegParmTypes;
2844 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2845 RegParmTypes.push_back(IntVT);
2846 if (VecVT != MVT::Other)
2847 RegParmTypes.push_back(VecVT);
2849 // Compute the set of forwarded registers. The rest are scratch.
2850 SmallVectorImpl<ForwardedRegister> &Forwards =
2851 FuncInfo->getForwardedMustTailRegParms();
2852 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2854 // Conservatively forward AL on x86_64, since it might be used for varargs.
2855 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2856 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2857 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2860 // Copy all forwards from physical to virtual registers.
2861 for (ForwardedRegister &F : Forwards) {
2862 // FIXME: Can we use a less constrained schedule?
2863 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2864 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2865 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2869 // Some CCs need callee pop.
2870 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2871 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2872 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2874 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2875 // If this is an sret function, the return should pop the hidden pointer.
2876 if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
2877 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2878 argsAreStructReturn(Ins) == StackStructReturn)
2879 FuncInfo->setBytesToPopOnReturn(4);
2883 // RegSaveFrameIndex is X86-64 only.
2884 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2885 if (CallConv == CallingConv::X86_FastCall ||
2886 CallConv == CallingConv::X86_ThisCall)
2887 // fastcc functions can't have varargs.
2888 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2891 FuncInfo->setArgumentStackSize(StackSize);
2893 if (WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo()) {
2894 EHPersonality Personality = classifyEHPersonality(Fn->getPersonalityFn());
2895 if (Personality == EHPersonality::CoreCLR) {
2897 // TODO: Add a mechanism to frame lowering that will allow us to indicate
2898 // that we'd prefer this slot be allocated towards the bottom of the frame
2899 // (i.e. near the stack pointer after allocating the frame). Every
2900 // funclet needs a copy of this slot in its (mostly empty) frame, and the
2901 // offset from the bottom of this and each funclet's frame must be the
2902 // same, so the size of funclets' (mostly empty) frames is dictated by
2903 // how far this slot is from the bottom (since they allocate just enough
2904 // space to accomodate holding this slot at the correct offset).
2905 int PSPSymFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2906 EHInfo->PSPSymFrameIdx = PSPSymFI;
2914 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2915 SDValue StackPtr, SDValue Arg,
2916 SDLoc dl, SelectionDAG &DAG,
2917 const CCValAssign &VA,
2918 ISD::ArgFlagsTy Flags) const {
2919 unsigned LocMemOffset = VA.getLocMemOffset();
2920 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2921 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2923 if (Flags.isByVal())
2924 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2926 return DAG.getStore(
2927 Chain, dl, Arg, PtrOff,
2928 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset),
2932 /// Emit a load of return address if tail call
2933 /// optimization is performed and it is required.
2935 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2936 SDValue &OutRetAddr, SDValue Chain,
2937 bool IsTailCall, bool Is64Bit,
2938 int FPDiff, SDLoc dl) const {
2939 // Adjust the Return address stack slot.
2940 EVT VT = getPointerTy(DAG.getDataLayout());
2941 OutRetAddr = getReturnAddressFrameIndex(DAG);
2943 // Load the "old" Return address.
2944 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2945 false, false, false, 0);
2946 return SDValue(OutRetAddr.getNode(), 1);
2949 /// Emit a store of the return address if tail call
2950 /// optimization is performed and it is required (FPDiff!=0).
2951 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2952 SDValue Chain, SDValue RetAddrFrIdx,
2953 EVT PtrVT, unsigned SlotSize,
2954 int FPDiff, SDLoc dl) {
2955 // Store the return address to the appropriate stack slot.
2956 if (!FPDiff) return Chain;
2957 // Calculate the new stack slot for the return address.
2958 int NewReturnAddrFI =
2959 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2961 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2962 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2963 MachinePointerInfo::getFixedStack(
2964 DAG.getMachineFunction(), NewReturnAddrFI),
2969 /// Returns a vector_shuffle mask for an movs{s|d}, movd
2970 /// operation of specified width.
2971 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
2973 unsigned NumElems = VT.getVectorNumElements();
2974 SmallVector<int, 8> Mask;
2975 Mask.push_back(NumElems);
2976 for (unsigned i = 1; i != NumElems; ++i)
2978 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2982 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2983 SmallVectorImpl<SDValue> &InVals) const {
2984 SelectionDAG &DAG = CLI.DAG;
2986 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2987 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2988 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2989 SDValue Chain = CLI.Chain;
2990 SDValue Callee = CLI.Callee;
2991 CallingConv::ID CallConv = CLI.CallConv;
2992 bool &isTailCall = CLI.IsTailCall;
2993 bool isVarArg = CLI.IsVarArg;
2995 MachineFunction &MF = DAG.getMachineFunction();
2996 bool Is64Bit = Subtarget->is64Bit();
2997 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2998 StructReturnType SR = callIsStructReturn(Outs);
2999 bool IsSibcall = false;
3000 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
3001 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
3003 if (Attr.getValueAsString() == "true")
3006 if (Subtarget->isPICStyleGOT() &&
3007 !MF.getTarget().Options.GuaranteedTailCallOpt) {
3008 // If we are using a GOT, disable tail calls to external symbols with
3009 // default visibility. Tail calling such a symbol requires using a GOT
3010 // relocation, which forces early binding of the symbol. This breaks code
3011 // that require lazy function symbol resolution. Using musttail or
3012 // GuaranteedTailCallOpt will override this.
3013 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3014 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
3015 G->getGlobal()->hasDefaultVisibility()))
3019 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
3021 // Force this to be a tail call. The verifier rules are enough to ensure
3022 // that we can lower this successfully without moving the return address
3025 } else if (isTailCall) {
3026 // Check if it's really possible to do a tail call.
3027 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
3028 isVarArg, SR != NotStructReturn,
3029 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
3030 Outs, OutVals, Ins, DAG);
3032 // Sibcalls are automatically detected tailcalls which do not require
3034 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
3041 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&
3042 "Var args not supported with calling convention fastcc, ghc or hipe");
3044 // Analyze operands of the call, assigning locations to each operand.
3045 SmallVector<CCValAssign, 16> ArgLocs;
3046 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
3048 // Allocate shadow area for Win64
3050 CCInfo.AllocateStack(32, 8);
3052 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3054 // Get a count of how many bytes are to be pushed on the stack.
3055 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
3057 // This is a sibcall. The memory operands are available in caller's
3058 // own caller's stack.
3060 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
3061 canGuaranteeTCO(CallConv))
3062 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
3065 if (isTailCall && !IsSibcall && !IsMustTail) {
3066 // Lower arguments at fp - stackoffset + fpdiff.
3067 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
3069 FPDiff = NumBytesCallerPushed - NumBytes;
3071 // Set the delta of movement of the returnaddr stackslot.
3072 // But only set if delta is greater than previous delta.
3073 if (FPDiff < X86Info->getTCReturnAddrDelta())
3074 X86Info->setTCReturnAddrDelta(FPDiff);
3077 unsigned NumBytesToPush = NumBytes;
3078 unsigned NumBytesToPop = NumBytes;
3080 // If we have an inalloca argument, all stack space has already been allocated
3081 // for us and be right at the top of the stack. We don't support multiple
3082 // arguments passed in memory when using inalloca.
3083 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
3085 if (!ArgLocs.back().isMemLoc())
3086 report_fatal_error("cannot use inalloca attribute on a register "
3088 if (ArgLocs.back().getLocMemOffset() != 0)
3089 report_fatal_error("any parameter with the inalloca attribute must be "
3090 "the only memory argument");
3094 Chain = DAG.getCALLSEQ_START(
3095 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
3097 SDValue RetAddrFrIdx;
3098 // Load return address for tail calls.
3099 if (isTailCall && FPDiff)
3100 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
3101 Is64Bit, FPDiff, dl);
3103 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3104 SmallVector<SDValue, 8> MemOpChains;
3107 // Walk the register/memloc assignments, inserting copies/loads. In the case
3108 // of tail call optimization arguments are handle later.
3109 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3110 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3111 // Skip inalloca arguments, they have already been written.
3112 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3113 if (Flags.isInAlloca())
3116 CCValAssign &VA = ArgLocs[i];
3117 EVT RegVT = VA.getLocVT();
3118 SDValue Arg = OutVals[i];
3119 bool isByVal = Flags.isByVal();
3121 // Promote the value if needed.
3122 switch (VA.getLocInfo()) {
3123 default: llvm_unreachable("Unknown loc info!");
3124 case CCValAssign::Full: break;
3125 case CCValAssign::SExt:
3126 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3128 case CCValAssign::ZExt:
3129 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
3131 case CCValAssign::AExt:
3132 if (Arg.getValueType().isVector() &&
3133 Arg.getValueType().getVectorElementType() == MVT::i1)
3134 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3135 else if (RegVT.is128BitVector()) {
3136 // Special case: passing MMX values in XMM registers.
3137 Arg = DAG.getBitcast(MVT::i64, Arg);
3138 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
3139 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
3141 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
3143 case CCValAssign::BCvt:
3144 Arg = DAG.getBitcast(RegVT, Arg);
3146 case CCValAssign::Indirect: {
3147 // Store the argument.
3148 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
3149 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
3150 Chain = DAG.getStore(
3151 Chain, dl, Arg, SpillSlot,
3152 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3159 if (VA.isRegLoc()) {
3160 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3161 if (isVarArg && IsWin64) {
3162 // Win64 ABI requires argument XMM reg to be copied to the corresponding
3163 // shadow reg if callee is a varargs function.
3164 unsigned ShadowReg = 0;
3165 switch (VA.getLocReg()) {
3166 case X86::XMM0: ShadowReg = X86::RCX; break;
3167 case X86::XMM1: ShadowReg = X86::RDX; break;
3168 case X86::XMM2: ShadowReg = X86::R8; break;
3169 case X86::XMM3: ShadowReg = X86::R9; break;
3172 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
3174 } else if (!IsSibcall && (!isTailCall || isByVal)) {
3175 assert(VA.isMemLoc());
3176 if (!StackPtr.getNode())
3177 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3178 getPointerTy(DAG.getDataLayout()));
3179 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3180 dl, DAG, VA, Flags));
3184 if (!MemOpChains.empty())
3185 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3187 if (Subtarget->isPICStyleGOT()) {
3188 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3191 RegsToPass.push_back(std::make_pair(
3192 unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
3193 getPointerTy(DAG.getDataLayout()))));
3195 // If we are tail calling and generating PIC/GOT style code load the
3196 // address of the callee into ECX. The value in ecx is used as target of
3197 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3198 // for tail calls on PIC/GOT architectures. Normally we would just put the
3199 // address of GOT into ebx and then call target@PLT. But for tail calls
3200 // ebx would be restored (since ebx is callee saved) before jumping to the
3203 // Note: The actual moving to ECX is done further down.
3204 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3205 if (G && !G->getGlobal()->hasLocalLinkage() &&
3206 G->getGlobal()->hasDefaultVisibility())
3207 Callee = LowerGlobalAddress(Callee, DAG);
3208 else if (isa<ExternalSymbolSDNode>(Callee))
3209 Callee = LowerExternalSymbol(Callee, DAG);
3213 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3214 // From AMD64 ABI document:
3215 // For calls that may call functions that use varargs or stdargs
3216 // (prototype-less calls or calls to functions containing ellipsis (...) in
3217 // the declaration) %al is used as hidden argument to specify the number
3218 // of SSE registers used. The contents of %al do not need to match exactly
3219 // the number of registers, but must be an ubound on the number of SSE
3220 // registers used and is in the range 0 - 8 inclusive.
3222 // Count the number of XMM registers allocated.
3223 static const MCPhysReg XMMArgRegs[] = {
3224 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3225 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3227 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3228 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3229 && "SSE registers cannot be used when SSE is disabled");
3231 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3232 DAG.getConstant(NumXMMRegs, dl,
3236 if (isVarArg && IsMustTail) {
3237 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3238 for (const auto &F : Forwards) {
3239 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3240 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3244 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3245 // don't need this because the eligibility check rejects calls that require
3246 // shuffling arguments passed in memory.
3247 if (!IsSibcall && isTailCall) {
3248 // Force all the incoming stack arguments to be loaded from the stack
3249 // before any new outgoing arguments are stored to the stack, because the
3250 // outgoing stack slots may alias the incoming argument stack slots, and
3251 // the alias isn't otherwise explicit. This is slightly more conservative
3252 // than necessary, because it means that each store effectively depends
3253 // on every argument instead of just those arguments it would clobber.
3254 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3256 SmallVector<SDValue, 8> MemOpChains2;
3259 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3260 CCValAssign &VA = ArgLocs[i];
3263 assert(VA.isMemLoc());
3264 SDValue Arg = OutVals[i];
3265 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3266 // Skip inalloca arguments. They don't require any work.
3267 if (Flags.isInAlloca())
3269 // Create frame index.
3270 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3271 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3272 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3273 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3275 if (Flags.isByVal()) {
3276 // Copy relative to framepointer.
3277 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3278 if (!StackPtr.getNode())
3279 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3280 getPointerTy(DAG.getDataLayout()));
3281 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3284 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3288 // Store relative to framepointer.
3289 MemOpChains2.push_back(DAG.getStore(
3290 ArgChain, dl, Arg, FIN,
3291 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3296 if (!MemOpChains2.empty())
3297 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3299 // Store the return address to the appropriate stack slot.
3300 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3301 getPointerTy(DAG.getDataLayout()),
3302 RegInfo->getSlotSize(), FPDiff, dl);
3305 // Build a sequence of copy-to-reg nodes chained together with token chain
3306 // and flag operands which copy the outgoing args into registers.
3308 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3309 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3310 RegsToPass[i].second, InFlag);
3311 InFlag = Chain.getValue(1);
3314 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3315 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3316 // In the 64-bit large code model, we have to make all calls
3317 // through a register, since the call instruction's 32-bit
3318 // pc-relative offset may not be large enough to hold the whole
3320 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3321 // If the callee is a GlobalAddress node (quite common, every direct call
3322 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3324 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3326 // We should use extra load for direct calls to dllimported functions in
3328 const GlobalValue *GV = G->getGlobal();
3329 if (!GV->hasDLLImportStorageClass()) {
3330 unsigned char OpFlags = 0;
3331 bool ExtraLoad = false;
3332 unsigned WrapperKind = ISD::DELETED_NODE;
3334 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3335 // external symbols most go through the PLT in PIC mode. If the symbol
3336 // has hidden or protected visibility, or if it is static or local, then
3337 // we don't need to use the PLT - we can directly call it.
3338 if (Subtarget->isTargetELF() &&
3339 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3340 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3341 OpFlags = X86II::MO_PLT;
3342 } else if (Subtarget->isPICStyleStubAny() &&
3343 !GV->isStrongDefinitionForLinker() &&
3344 (!Subtarget->getTargetTriple().isMacOSX() ||
3345 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3346 // PC-relative references to external symbols should go through $stub,
3347 // unless we're building with the leopard linker or later, which
3348 // automatically synthesizes these stubs.
3349 OpFlags = X86II::MO_DARWIN_STUB;
3350 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3351 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3352 // If the function is marked as non-lazy, generate an indirect call
3353 // which loads from the GOT directly. This avoids runtime overhead
3354 // at the cost of eager binding (and one extra byte of encoding).
3355 OpFlags = X86II::MO_GOTPCREL;
3356 WrapperKind = X86ISD::WrapperRIP;
3360 Callee = DAG.getTargetGlobalAddress(
3361 GV, dl, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
3363 // Add a wrapper if needed.
3364 if (WrapperKind != ISD::DELETED_NODE)
3365 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3366 getPointerTy(DAG.getDataLayout()), Callee);
3367 // Add extra indirection if needed.
3369 Callee = DAG.getLoad(
3370 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3371 MachinePointerInfo::getGOT(DAG.getMachineFunction()), false, false,
3374 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3375 unsigned char OpFlags = 0;
3377 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3378 // external symbols should go through the PLT.
3379 if (Subtarget->isTargetELF() &&
3380 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3381 OpFlags = X86II::MO_PLT;
3382 } else if (Subtarget->isPICStyleStubAny() &&
3383 (!Subtarget->getTargetTriple().isMacOSX() ||
3384 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3385 // PC-relative references to external symbols should go through $stub,
3386 // unless we're building with the leopard linker or later, which
3387 // automatically synthesizes these stubs.
3388 OpFlags = X86II::MO_DARWIN_STUB;
3391 Callee = DAG.getTargetExternalSymbol(
3392 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
3393 } else if (Subtarget->isTarget64BitILP32() &&
3394 Callee->getValueType(0) == MVT::i32) {
3395 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3396 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3399 // Returns a chain & a flag for retval copy to use.
3400 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3401 SmallVector<SDValue, 8> Ops;
3403 if (!IsSibcall && isTailCall) {
3404 Chain = DAG.getCALLSEQ_END(Chain,
3405 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3406 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3407 InFlag = Chain.getValue(1);
3410 Ops.push_back(Chain);
3411 Ops.push_back(Callee);
3414 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3416 // Add argument registers to the end of the list so that they are known live
3418 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3419 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3420 RegsToPass[i].second.getValueType()));
3422 // Add a register mask operand representing the call-preserved registers.
3423 const uint32_t *Mask = RegInfo->getCallPreservedMask(MF, CallConv);
3424 assert(Mask && "Missing call preserved mask for calling convention");
3426 // If this is an invoke in a 32-bit function using a funclet-based
3427 // personality, assume the function clobbers all registers. If an exception
3428 // is thrown, the runtime will not restore CSRs.
3429 // FIXME: Model this more precisely so that we can register allocate across
3430 // the normal edge and spill and fill across the exceptional edge.
3431 if (!Is64Bit && CLI.CS && CLI.CS->isInvoke()) {
3432 const Function *CallerFn = MF.getFunction();
3433 EHPersonality Pers =
3434 CallerFn->hasPersonalityFn()
3435 ? classifyEHPersonality(CallerFn->getPersonalityFn())
3436 : EHPersonality::Unknown;
3437 if (isFuncletEHPersonality(Pers))
3438 Mask = RegInfo->getNoPreservedMask();
3441 Ops.push_back(DAG.getRegisterMask(Mask));
3443 if (InFlag.getNode())
3444 Ops.push_back(InFlag);
3448 //// If this is the first return lowered for this function, add the regs
3449 //// to the liveout set for the function.
3450 // This isn't right, although it's probably harmless on x86; liveouts
3451 // should be computed from returns not tail calls. Consider a void
3452 // function making a tail call to a function returning int.
3453 MF.getFrameInfo()->setHasTailCall();
3454 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3457 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3458 InFlag = Chain.getValue(1);
3460 // Create the CALLSEQ_END node.
3461 unsigned NumBytesForCalleeToPop;
3462 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3463 DAG.getTarget().Options.GuaranteedTailCallOpt))
3464 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3465 else if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
3466 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3467 SR == StackStructReturn)
3468 // If this is a call to a struct-return function, the callee
3469 // pops the hidden struct pointer, so we have to push it back.
3470 // This is common for Darwin/X86, Linux & Mingw32 targets.
3471 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3472 NumBytesForCalleeToPop = 4;
3474 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3476 // Returns a flag for retval copy to use.
3478 Chain = DAG.getCALLSEQ_END(Chain,
3479 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3480 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3483 InFlag = Chain.getValue(1);
3486 // Handle result values, copying them out of physregs into vregs that we
3488 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3489 Ins, dl, DAG, InVals);
3492 //===----------------------------------------------------------------------===//
3493 // Fast Calling Convention (tail call) implementation
3494 //===----------------------------------------------------------------------===//
3496 // Like std call, callee cleans arguments, convention except that ECX is
3497 // reserved for storing the tail called function address. Only 2 registers are
3498 // free for argument passing (inreg). Tail call optimization is performed
3500 // * tailcallopt is enabled
3501 // * caller/callee are fastcc
3502 // On X86_64 architecture with GOT-style position independent code only local
3503 // (within module) calls are supported at the moment.
3504 // To keep the stack aligned according to platform abi the function
3505 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3506 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3507 // If a tail called function callee has more arguments than the caller the
3508 // caller needs to make sure that there is room to move the RETADDR to. This is
3509 // achieved by reserving an area the size of the argument delta right after the
3510 // original RETADDR, but before the saved framepointer or the spilled registers
3511 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3523 /// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
3526 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3527 SelectionDAG& DAG) const {
3528 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3529 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3530 unsigned StackAlignment = TFI.getStackAlignment();
3531 uint64_t AlignMask = StackAlignment - 1;
3532 int64_t Offset = StackSize;
3533 unsigned SlotSize = RegInfo->getSlotSize();
3534 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3535 // Number smaller than 12 so just add the difference.
3536 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3538 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3539 Offset = ((~AlignMask) & Offset) + StackAlignment +
3540 (StackAlignment-SlotSize);
3545 /// Return true if the given stack call argument is already available in the
3546 /// same position (relatively) of the caller's incoming argument stack.
3548 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3549 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3550 const X86InstrInfo *TII) {
3551 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3553 if (Arg.getOpcode() == ISD::CopyFromReg) {
3554 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3555 if (!TargetRegisterInfo::isVirtualRegister(VR))
3557 MachineInstr *Def = MRI->getVRegDef(VR);
3560 if (!Flags.isByVal()) {
3561 if (!TII->isLoadFromStackSlot(Def, FI))
3564 unsigned Opcode = Def->getOpcode();
3565 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3566 Opcode == X86::LEA64_32r) &&
3567 Def->getOperand(1).isFI()) {
3568 FI = Def->getOperand(1).getIndex();
3569 Bytes = Flags.getByValSize();
3573 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3574 if (Flags.isByVal())
3575 // ByVal argument is passed in as a pointer but it's now being
3576 // dereferenced. e.g.
3577 // define @foo(%struct.X* %A) {
3578 // tail call @bar(%struct.X* byval %A)
3581 SDValue Ptr = Ld->getBasePtr();
3582 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3585 FI = FINode->getIndex();
3586 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3587 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3588 FI = FINode->getIndex();
3589 Bytes = Flags.getByValSize();
3593 assert(FI != INT_MAX);
3594 if (!MFI->isFixedObjectIndex(FI))
3596 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3599 /// Check whether the call is eligible for tail call optimization. Targets
3600 /// that want to do tail call optimization should implement this function.
3601 bool X86TargetLowering::IsEligibleForTailCallOptimization(
3602 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
3603 bool isCalleeStructRet, bool isCallerStructRet, Type *RetTy,
3604 const SmallVectorImpl<ISD::OutputArg> &Outs,
3605 const SmallVectorImpl<SDValue> &OutVals,
3606 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
3607 if (!mayTailCallThisCC(CalleeCC))
3610 // If -tailcallopt is specified, make fastcc functions tail-callable.
3611 MachineFunction &MF = DAG.getMachineFunction();
3612 const Function *CallerF = MF.getFunction();
3614 // If the function return type is x86_fp80 and the callee return type is not,
3615 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3616 // perform a tailcall optimization here.
3617 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3620 CallingConv::ID CallerCC = CallerF->getCallingConv();
3621 bool CCMatch = CallerCC == CalleeCC;
3622 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3623 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3625 // Win64 functions have extra shadow space for argument homing. Don't do the
3626 // sibcall if the caller and callee have mismatched expectations for this
3628 if (IsCalleeWin64 != IsCallerWin64)
3631 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3632 if (canGuaranteeTCO(CalleeCC) && CCMatch)
3637 // Look for obvious safe cases to perform tail call optimization that do not
3638 // require ABI changes. This is what gcc calls sibcall.
3640 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3641 // emit a special epilogue.
3642 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3643 if (RegInfo->needsStackRealignment(MF))
3646 // Also avoid sibcall optimization if either caller or callee uses struct
3647 // return semantics.
3648 if (isCalleeStructRet || isCallerStructRet)
3651 // Do not sibcall optimize vararg calls unless all arguments are passed via
3653 if (isVarArg && !Outs.empty()) {
3654 // Optimizing for varargs on Win64 is unlikely to be safe without
3655 // additional testing.
3656 if (IsCalleeWin64 || IsCallerWin64)
3659 SmallVector<CCValAssign, 16> ArgLocs;
3660 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3663 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3664 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3665 if (!ArgLocs[i].isRegLoc())
3669 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3670 // stack. Therefore, if it's not used by the call it is not safe to optimize
3671 // this into a sibcall.
3672 bool Unused = false;
3673 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3680 SmallVector<CCValAssign, 16> RVLocs;
3681 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3683 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3684 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3685 CCValAssign &VA = RVLocs[i];
3686 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3691 // If the calling conventions do not match, then we'd better make sure the
3692 // results are returned in the same way as what the caller expects.
3694 SmallVector<CCValAssign, 16> RVLocs1;
3695 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3697 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3699 SmallVector<CCValAssign, 16> RVLocs2;
3700 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3702 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3704 if (RVLocs1.size() != RVLocs2.size())
3706 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3707 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3709 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3711 if (RVLocs1[i].isRegLoc()) {
3712 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3715 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3721 unsigned StackArgsSize = 0;
3723 // If the callee takes no arguments then go on to check the results of the
3725 if (!Outs.empty()) {
3726 // Check if stack adjustment is needed. For now, do not do this if any
3727 // argument is passed on the stack.
3728 SmallVector<CCValAssign, 16> ArgLocs;
3729 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3732 // Allocate shadow area for Win64
3734 CCInfo.AllocateStack(32, 8);
3736 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3737 StackArgsSize = CCInfo.getNextStackOffset();
3739 if (CCInfo.getNextStackOffset()) {
3740 // Check if the arguments are already laid out in the right way as
3741 // the caller's fixed stack objects.
3742 MachineFrameInfo *MFI = MF.getFrameInfo();
3743 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3744 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3745 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3746 CCValAssign &VA = ArgLocs[i];
3747 SDValue Arg = OutVals[i];
3748 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3749 if (VA.getLocInfo() == CCValAssign::Indirect)
3751 if (!VA.isRegLoc()) {
3752 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3759 // If the tailcall address may be in a register, then make sure it's
3760 // possible to register allocate for it. In 32-bit, the call address can
3761 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3762 // callee-saved registers are restored. These happen to be the same
3763 // registers used to pass 'inreg' arguments so watch out for those.
3764 if (!Subtarget->is64Bit() &&
3765 ((!isa<GlobalAddressSDNode>(Callee) &&
3766 !isa<ExternalSymbolSDNode>(Callee)) ||
3767 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3768 unsigned NumInRegs = 0;
3769 // In PIC we need an extra register to formulate the address computation
3771 unsigned MaxInRegs =
3772 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3774 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3775 CCValAssign &VA = ArgLocs[i];
3778 unsigned Reg = VA.getLocReg();
3781 case X86::EAX: case X86::EDX: case X86::ECX:
3782 if (++NumInRegs == MaxInRegs)
3790 bool CalleeWillPop =
3791 X86::isCalleePop(CalleeCC, Subtarget->is64Bit(), isVarArg,
3792 MF.getTarget().Options.GuaranteedTailCallOpt);
3794 if (unsigned BytesToPop =
3795 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) {
3796 // If we have bytes to pop, the callee must pop them.
3797 bool CalleePopMatches = CalleeWillPop && BytesToPop == StackArgsSize;
3798 if (!CalleePopMatches)
3800 } else if (CalleeWillPop && StackArgsSize > 0) {
3801 // If we don't have bytes to pop, make sure the callee doesn't pop any.
3809 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3810 const TargetLibraryInfo *libInfo) const {
3811 return X86::createFastISel(funcInfo, libInfo);
3814 //===----------------------------------------------------------------------===//
3815 // Other Lowering Hooks
3816 //===----------------------------------------------------------------------===//
3818 static bool MayFoldLoad(SDValue Op) {
3819 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3822 static bool MayFoldIntoStore(SDValue Op) {
3823 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3826 static bool isTargetShuffle(unsigned Opcode) {
3828 default: return false;
3829 case X86ISD::BLENDI:
3830 case X86ISD::PSHUFB:
3831 case X86ISD::PSHUFD:
3832 case X86ISD::PSHUFHW:
3833 case X86ISD::PSHUFLW:
3835 case X86ISD::PALIGNR:
3836 case X86ISD::MOVLHPS:
3837 case X86ISD::MOVLHPD:
3838 case X86ISD::MOVHLPS:
3839 case X86ISD::MOVLPS:
3840 case X86ISD::MOVLPD:
3841 case X86ISD::MOVSHDUP:
3842 case X86ISD::MOVSLDUP:
3843 case X86ISD::MOVDDUP:
3846 case X86ISD::UNPCKL:
3847 case X86ISD::UNPCKH:
3848 case X86ISD::VPERMILPI:
3849 case X86ISD::VPERM2X128:
3850 case X86ISD::VPERMI:
3851 case X86ISD::VPERMV:
3852 case X86ISD::VPERMV3:
3857 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, MVT VT,
3858 SDValue V1, unsigned TargetMask,
3859 SelectionDAG &DAG) {
3861 default: llvm_unreachable("Unknown x86 shuffle node");
3862 case X86ISD::PSHUFD:
3863 case X86ISD::PSHUFHW:
3864 case X86ISD::PSHUFLW:
3865 case X86ISD::VPERMILPI:
3866 case X86ISD::VPERMI:
3867 return DAG.getNode(Opc, dl, VT, V1,
3868 DAG.getConstant(TargetMask, dl, MVT::i8));
3872 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, MVT VT,
3873 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3875 default: llvm_unreachable("Unknown x86 shuffle node");
3876 case X86ISD::MOVLHPS:
3877 case X86ISD::MOVLHPD:
3878 case X86ISD::MOVHLPS:
3879 case X86ISD::MOVLPS:
3880 case X86ISD::MOVLPD:
3883 case X86ISD::UNPCKL:
3884 case X86ISD::UNPCKH:
3885 return DAG.getNode(Opc, dl, VT, V1, V2);
3889 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3890 MachineFunction &MF = DAG.getMachineFunction();
3891 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3892 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3893 int ReturnAddrIndex = FuncInfo->getRAIndex();
3895 if (ReturnAddrIndex == 0) {
3896 // Set up a frame object for the return address.
3897 unsigned SlotSize = RegInfo->getSlotSize();
3898 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3901 FuncInfo->setRAIndex(ReturnAddrIndex);
3904 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
3907 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3908 bool hasSymbolicDisplacement) {
3909 // Offset should fit into 32 bit immediate field.
3910 if (!isInt<32>(Offset))
3913 // If we don't have a symbolic displacement - we don't have any extra
3915 if (!hasSymbolicDisplacement)
3918 // FIXME: Some tweaks might be needed for medium code model.
3919 if (M != CodeModel::Small && M != CodeModel::Kernel)
3922 // For small code model we assume that latest object is 16MB before end of 31
3923 // bits boundary. We may also accept pretty large negative constants knowing
3924 // that all objects are in the positive half of address space.
3925 if (M == CodeModel::Small && Offset < 16*1024*1024)
3928 // For kernel code model we know that all object resist in the negative half
3929 // of 32bits address space. We may not accept negative offsets, since they may
3930 // be just off and we may accept pretty large positive ones.
3931 if (M == CodeModel::Kernel && Offset >= 0)
3937 /// Determines whether the callee is required to pop its own arguments.
3938 /// Callee pop is necessary to support tail calls.
3939 bool X86::isCalleePop(CallingConv::ID CallingConv,
3940 bool is64Bit, bool IsVarArg, bool GuaranteeTCO) {
3941 // If GuaranteeTCO is true, we force some calls to be callee pop so that we
3942 // can guarantee TCO.
3943 if (!IsVarArg && shouldGuaranteeTCO(CallingConv, GuaranteeTCO))
3946 switch (CallingConv) {
3949 case CallingConv::X86_StdCall:
3950 case CallingConv::X86_FastCall:
3951 case CallingConv::X86_ThisCall:
3952 case CallingConv::X86_VectorCall:
3957 /// \brief Return true if the condition is an unsigned comparison operation.
3958 static bool isX86CCUnsigned(unsigned X86CC) {
3960 default: llvm_unreachable("Invalid integer condition!");
3961 case X86::COND_E: return true;
3962 case X86::COND_G: return false;
3963 case X86::COND_GE: return false;
3964 case X86::COND_L: return false;
3965 case X86::COND_LE: return false;
3966 case X86::COND_NE: return true;
3967 case X86::COND_B: return true;
3968 case X86::COND_A: return true;
3969 case X86::COND_BE: return true;
3970 case X86::COND_AE: return true;
3974 static X86::CondCode TranslateIntegerX86CC(ISD::CondCode SetCCOpcode) {
3975 switch (SetCCOpcode) {
3976 default: llvm_unreachable("Invalid integer condition!");
3977 case ISD::SETEQ: return X86::COND_E;
3978 case ISD::SETGT: return X86::COND_G;
3979 case ISD::SETGE: return X86::COND_GE;
3980 case ISD::SETLT: return X86::COND_L;
3981 case ISD::SETLE: return X86::COND_LE;
3982 case ISD::SETNE: return X86::COND_NE;
3983 case ISD::SETULT: return X86::COND_B;
3984 case ISD::SETUGT: return X86::COND_A;
3985 case ISD::SETULE: return X86::COND_BE;
3986 case ISD::SETUGE: return X86::COND_AE;
3990 /// Do a one-to-one translation of a ISD::CondCode to the X86-specific
3991 /// condition code, returning the condition code and the LHS/RHS of the
3992 /// comparison to make.
3993 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3994 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3996 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3997 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3998 // X > -1 -> X == 0, jump !sign.
3999 RHS = DAG.getConstant(0, DL, RHS.getValueType());
4000 return X86::COND_NS;
4002 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
4003 // X < 0 -> X == 0, jump on sign.
4006 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
4008 RHS = DAG.getConstant(0, DL, RHS.getValueType());
4009 return X86::COND_LE;
4013 return TranslateIntegerX86CC(SetCCOpcode);
4016 // First determine if it is required or is profitable to flip the operands.
4018 // If LHS is a foldable load, but RHS is not, flip the condition.
4019 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
4020 !ISD::isNON_EXTLoad(RHS.getNode())) {
4021 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
4022 std::swap(LHS, RHS);
4025 switch (SetCCOpcode) {
4031 std::swap(LHS, RHS);
4035 // On a floating point condition, the flags are set as follows:
4037 // 0 | 0 | 0 | X > Y
4038 // 0 | 0 | 1 | X < Y
4039 // 1 | 0 | 0 | X == Y
4040 // 1 | 1 | 1 | unordered
4041 switch (SetCCOpcode) {
4042 default: llvm_unreachable("Condcode should be pre-legalized away");
4044 case ISD::SETEQ: return X86::COND_E;
4045 case ISD::SETOLT: // flipped
4047 case ISD::SETGT: return X86::COND_A;
4048 case ISD::SETOLE: // flipped
4050 case ISD::SETGE: return X86::COND_AE;
4051 case ISD::SETUGT: // flipped
4053 case ISD::SETLT: return X86::COND_B;
4054 case ISD::SETUGE: // flipped
4056 case ISD::SETLE: return X86::COND_BE;
4058 case ISD::SETNE: return X86::COND_NE;
4059 case ISD::SETUO: return X86::COND_P;
4060 case ISD::SETO: return X86::COND_NP;
4062 case ISD::SETUNE: return X86::COND_INVALID;
4066 /// Is there a floating point cmov for the specific X86 condition code?
4067 /// Current x86 isa includes the following FP cmov instructions:
4068 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
4069 static bool hasFPCMov(unsigned X86CC) {
4085 /// Returns true if the target can instruction select the
4086 /// specified FP immediate natively. If false, the legalizer will
4087 /// materialize the FP immediate as a load from a constant pool.
4088 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4089 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
4090 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
4096 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
4097 ISD::LoadExtType ExtTy,
4099 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
4100 // relocation target a movq or addq instruction: don't let the load shrink.
4101 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
4102 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
4103 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
4104 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
4108 /// \brief Returns true if it is beneficial to convert a load of a constant
4109 /// to just the constant itself.
4110 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
4112 assert(Ty->isIntegerTy());
4114 unsigned BitSize = Ty->getPrimitiveSizeInBits();
4115 if (BitSize == 0 || BitSize > 64)
4120 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
4121 unsigned Index) const {
4122 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
4125 return (Index == 0 || Index == ResVT.getVectorNumElements());
4128 bool X86TargetLowering::isCheapToSpeculateCttz() const {
4129 // Speculate cttz only if we can directly use TZCNT.
4130 return Subtarget->hasBMI();
4133 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
4134 // Speculate ctlz only if we can directly use LZCNT.
4135 return Subtarget->hasLZCNT();
4138 /// Return true if every element in Mask, beginning
4139 /// from position Pos and ending in Pos+Size is undef.
4140 static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
4141 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
4147 /// Return true if Val is undef or if its value falls within the
4148 /// specified range (L, H].
4149 static bool isUndefOrInRange(int Val, int Low, int Hi) {
4150 return (Val < 0) || (Val >= Low && Val < Hi);
4153 /// Val is either less than zero (undef) or equal to the specified value.
4154 static bool isUndefOrEqual(int Val, int CmpVal) {
4155 return (Val < 0 || Val == CmpVal);
4158 /// Return true if every element in Mask, beginning
4159 /// from position Pos and ending in Pos+Size, falls within the specified
4160 /// sequential range (Low, Low+Size]. or is undef.
4161 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
4162 unsigned Pos, unsigned Size, int Low) {
4163 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
4164 if (!isUndefOrEqual(Mask[i], Low))
4169 /// Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector
4170 /// extract that is suitable for instruction that extract 128 or 256 bit vectors
4171 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4172 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4173 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4176 // The index should be aligned on a vecWidth-bit boundary.
4178 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4180 MVT VT = N->getSimpleValueType(0);
4181 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4182 bool Result = (Index * ElSize) % vecWidth == 0;
4187 /// Return true if the specified INSERT_SUBVECTOR
4188 /// operand specifies a subvector insert that is suitable for input to
4189 /// insertion of 128 or 256-bit subvectors
4190 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4191 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4192 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4194 // The index should be aligned on a vecWidth-bit boundary.
4196 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4198 MVT VT = N->getSimpleValueType(0);
4199 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4200 bool Result = (Index * ElSize) % vecWidth == 0;
4205 bool X86::isVINSERT128Index(SDNode *N) {
4206 return isVINSERTIndex(N, 128);
4209 bool X86::isVINSERT256Index(SDNode *N) {
4210 return isVINSERTIndex(N, 256);
4213 bool X86::isVEXTRACT128Index(SDNode *N) {
4214 return isVEXTRACTIndex(N, 128);
4217 bool X86::isVEXTRACT256Index(SDNode *N) {
4218 return isVEXTRACTIndex(N, 256);
4221 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4222 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4223 assert(isa<ConstantSDNode>(N->getOperand(1).getNode()) &&
4224 "Illegal extract subvector for VEXTRACT");
4227 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4229 MVT VecVT = N->getOperand(0).getSimpleValueType();
4230 MVT ElVT = VecVT.getVectorElementType();
4232 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4233 return Index / NumElemsPerChunk;
4236 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4237 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4238 assert(isa<ConstantSDNode>(N->getOperand(2).getNode()) &&
4239 "Illegal insert subvector for VINSERT");
4242 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4244 MVT VecVT = N->getSimpleValueType(0);
4245 MVT ElVT = VecVT.getVectorElementType();
4247 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4248 return Index / NumElemsPerChunk;
4251 /// Return the appropriate immediate to extract the specified
4252 /// EXTRACT_SUBVECTOR index with VEXTRACTF128 and VINSERTI128 instructions.
4253 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4254 return getExtractVEXTRACTImmediate(N, 128);
4257 /// Return the appropriate immediate to extract the specified
4258 /// EXTRACT_SUBVECTOR index with VEXTRACTF64x4 and VINSERTI64x4 instructions.
4259 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4260 return getExtractVEXTRACTImmediate(N, 256);
4263 /// Return the appropriate immediate to insert at the specified
4264 /// INSERT_SUBVECTOR index with VINSERTF128 and VINSERTI128 instructions.
4265 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4266 return getInsertVINSERTImmediate(N, 128);
4269 /// Return the appropriate immediate to insert at the specified
4270 /// INSERT_SUBVECTOR index with VINSERTF46x4 and VINSERTI64x4 instructions.
4271 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4272 return getInsertVINSERTImmediate(N, 256);
4275 /// Returns true if Elt is a constant zero or a floating point constant +0.0.
4276 bool X86::isZeroNode(SDValue Elt) {
4277 return isNullConstant(Elt) || isNullFPConstant(Elt);
4280 // Build a vector of constants
4281 // Use an UNDEF node if MaskElt == -1.
4282 // Spilt 64-bit constants in the 32-bit mode.
4283 static SDValue getConstVector(ArrayRef<int> Values, MVT VT,
4285 SDLoc dl, bool IsMask = false) {
4287 SmallVector<SDValue, 32> Ops;
4290 MVT ConstVecVT = VT;
4291 unsigned NumElts = VT.getVectorNumElements();
4292 bool In64BitMode = DAG.getTargetLoweringInfo().isTypeLegal(MVT::i64);
4293 if (!In64BitMode && VT.getVectorElementType() == MVT::i64) {
4294 ConstVecVT = MVT::getVectorVT(MVT::i32, NumElts * 2);
4298 MVT EltVT = ConstVecVT.getVectorElementType();
4299 for (unsigned i = 0; i < NumElts; ++i) {
4300 bool IsUndef = Values[i] < 0 && IsMask;
4301 SDValue OpNode = IsUndef ? DAG.getUNDEF(EltVT) :
4302 DAG.getConstant(Values[i], dl, EltVT);
4303 Ops.push_back(OpNode);
4305 Ops.push_back(IsUndef ? DAG.getUNDEF(EltVT) :
4306 DAG.getConstant(0, dl, EltVT));
4308 SDValue ConstsNode = DAG.getNode(ISD::BUILD_VECTOR, dl, ConstVecVT, Ops);
4310 ConstsNode = DAG.getBitcast(VT, ConstsNode);
4314 /// Returns a vector of specified type with all zero elements.
4315 static SDValue getZeroVector(MVT VT, const X86Subtarget *Subtarget,
4316 SelectionDAG &DAG, SDLoc dl) {
4317 assert(VT.isVector() && "Expected a vector type");
4319 // Always build SSE zero vectors as <4 x i32> bitcasted
4320 // to their dest type. This ensures they get CSE'd.
4322 if (VT.is128BitVector()) { // SSE
4323 if (Subtarget->hasSSE2()) { // SSE2
4324 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4325 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4327 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4328 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4330 } else if (VT.is256BitVector()) { // AVX
4331 if (Subtarget->hasInt256()) { // AVX2
4332 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4333 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4334 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4336 // 256-bit logic and arithmetic instructions in AVX are all
4337 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4338 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4339 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4340 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4342 } else if (VT.is512BitVector()) { // AVX-512
4343 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4344 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4345 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4346 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4347 } else if (VT.getVectorElementType() == MVT::i1) {
4349 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4350 && "Unexpected vector type");
4351 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4352 && "Unexpected vector type");
4353 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4354 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4355 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4357 llvm_unreachable("Unexpected vector type");
4359 return DAG.getBitcast(VT, Vec);
4362 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4363 SelectionDAG &DAG, SDLoc dl,
4364 unsigned vectorWidth) {
4365 assert((vectorWidth == 128 || vectorWidth == 256) &&
4366 "Unsupported vector width");
4367 EVT VT = Vec.getValueType();
4368 EVT ElVT = VT.getVectorElementType();
4369 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4370 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4371 VT.getVectorNumElements()/Factor);
4373 // Extract from UNDEF is UNDEF.
4374 if (Vec.getOpcode() == ISD::UNDEF)
4375 return DAG.getUNDEF(ResultVT);
4377 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4378 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4379 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
4381 // This is the index of the first element of the vectorWidth-bit chunk
4382 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
4383 IdxVal &= ~(ElemsPerChunk - 1);
4385 // If the input is a buildvector just emit a smaller one.
4386 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4387 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4388 makeArrayRef(Vec->op_begin() + IdxVal, ElemsPerChunk));
4390 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
4391 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4394 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4395 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4396 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4397 /// instructions or a simple subregister reference. Idx is an index in the
4398 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4399 /// lowering EXTRACT_VECTOR_ELT operations easier.
4400 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4401 SelectionDAG &DAG, SDLoc dl) {
4402 assert((Vec.getValueType().is256BitVector() ||
4403 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4404 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4407 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4408 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4409 SelectionDAG &DAG, SDLoc dl) {
4410 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4411 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4414 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4415 unsigned IdxVal, SelectionDAG &DAG,
4416 SDLoc dl, unsigned vectorWidth) {
4417 assert((vectorWidth == 128 || vectorWidth == 256) &&
4418 "Unsupported vector width");
4419 // Inserting UNDEF is Result
4420 if (Vec.getOpcode() == ISD::UNDEF)
4422 EVT VT = Vec.getValueType();
4423 EVT ElVT = VT.getVectorElementType();
4424 EVT ResultVT = Result.getValueType();
4426 // Insert the relevant vectorWidth bits.
4427 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4428 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
4430 // This is the index of the first element of the vectorWidth-bit chunk
4431 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
4432 IdxVal &= ~(ElemsPerChunk - 1);
4434 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
4435 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4438 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4439 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4440 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4441 /// simple superregister reference. Idx is an index in the 128 bits
4442 /// we want. It need not be aligned to a 128-bit boundary. That makes
4443 /// lowering INSERT_VECTOR_ELT operations easier.
4444 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4445 SelectionDAG &DAG, SDLoc dl) {
4446 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4448 // For insertion into the zero index (low half) of a 256-bit vector, it is
4449 // more efficient to generate a blend with immediate instead of an insert*128.
4450 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4451 // extend the subvector to the size of the result vector. Make sure that
4452 // we are not recursing on that node by checking for undef here.
4453 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4454 Result.getOpcode() != ISD::UNDEF) {
4455 EVT ResultVT = Result.getValueType();
4456 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4457 SDValue Undef = DAG.getUNDEF(ResultVT);
4458 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4461 // The blend instruction, and therefore its mask, depend on the data type.
4462 MVT ScalarType = ResultVT.getVectorElementType().getSimpleVT();
4463 if (ScalarType.isFloatingPoint()) {
4464 // Choose either vblendps (float) or vblendpd (double).
4465 unsigned ScalarSize = ScalarType.getSizeInBits();
4466 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4467 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4468 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4469 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4472 const X86Subtarget &Subtarget =
4473 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4475 // AVX2 is needed for 256-bit integer blend support.
4476 // Integers must be cast to 32-bit because there is only vpblendd;
4477 // vpblendw can't be used for this because it has a handicapped mask.
4479 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4480 // is still more efficient than using the wrong domain vinsertf128 that
4481 // will be created by InsertSubVector().
4482 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4484 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4485 Vec256 = DAG.getBitcast(CastVT, Vec256);
4486 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4487 return DAG.getBitcast(ResultVT, Vec256);
4490 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4493 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4494 SelectionDAG &DAG, SDLoc dl) {
4495 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4496 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4499 /// Insert i1-subvector to i1-vector.
4500 static SDValue Insert1BitVector(SDValue Op, SelectionDAG &DAG) {
4503 SDValue Vec = Op.getOperand(0);
4504 SDValue SubVec = Op.getOperand(1);
4505 SDValue Idx = Op.getOperand(2);
4507 if (!isa<ConstantSDNode>(Idx))
4510 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
4511 if (IdxVal == 0 && Vec.isUndef()) // the operation is legal
4514 MVT OpVT = Op.getSimpleValueType();
4515 MVT SubVecVT = SubVec.getSimpleValueType();
4516 unsigned NumElems = OpVT.getVectorNumElements();
4517 unsigned SubVecNumElems = SubVecVT.getVectorNumElements();
4519 assert(IdxVal + SubVecNumElems <= NumElems &&
4520 IdxVal % SubVecVT.getSizeInBits() == 0 &&
4521 "Unexpected index value in INSERT_SUBVECTOR");
4523 // There are 3 possible cases:
4524 // 1. Subvector should be inserted in the lower part (IdxVal == 0)
4525 // 2. Subvector should be inserted in the upper part
4526 // (IdxVal + SubVecNumElems == NumElems)
4527 // 3. Subvector should be inserted in the middle (for example v2i1
4528 // to v16i1, index 2)
4530 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
4531 SDValue Undef = DAG.getUNDEF(OpVT);
4532 SDValue WideSubVec =
4533 DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef, SubVec, ZeroIdx);
4535 return DAG.getNode(X86ISD::VSHLI, dl, OpVT, WideSubVec,
4536 DAG.getConstant(IdxVal, dl, MVT::i8));
4538 if (ISD::isBuildVectorAllZeros(Vec.getNode())) {
4539 unsigned ShiftLeft = NumElems - SubVecNumElems;
4540 unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal;
4541 WideSubVec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, WideSubVec,
4542 DAG.getConstant(ShiftLeft, dl, MVT::i8));
4543 return ShiftRight ? DAG.getNode(X86ISD::VSRLI, dl, OpVT, WideSubVec,
4544 DAG.getConstant(ShiftRight, dl, MVT::i8)) : WideSubVec;
4548 // Zero lower bits of the Vec
4549 SDValue ShiftBits = DAG.getConstant(SubVecNumElems, dl, MVT::i8);
4550 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
4551 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
4552 // Merge them together
4553 return DAG.getNode(ISD::OR, dl, OpVT, Vec, WideSubVec);
4556 // Simple case when we put subvector in the upper part
4557 if (IdxVal + SubVecNumElems == NumElems) {
4558 // Zero upper bits of the Vec
4559 WideSubVec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec,
4560 DAG.getConstant(IdxVal, dl, MVT::i8));
4561 SDValue ShiftBits = DAG.getConstant(SubVecNumElems, dl, MVT::i8);
4562 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
4563 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
4564 return DAG.getNode(ISD::OR, dl, OpVT, Vec, WideSubVec);
4566 // Subvector should be inserted in the middle - use shuffle
4567 SmallVector<int, 64> Mask;
4568 for (unsigned i = 0; i < NumElems; ++i)
4569 Mask.push_back(i >= IdxVal && i < IdxVal + SubVecNumElems ?
4571 return DAG.getVectorShuffle(OpVT, dl, WideSubVec, Vec, Mask);
4574 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4575 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4576 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4577 /// large BUILD_VECTORS.
4578 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4579 unsigned NumElems, SelectionDAG &DAG,
4581 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4582 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4585 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4586 unsigned NumElems, SelectionDAG &DAG,
4588 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4589 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4592 /// Returns a vector of specified type with all bits set.
4593 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4594 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4595 /// Then bitcast to their original type, ensuring they get CSE'd.
4596 static SDValue getOnesVector(EVT VT, const X86Subtarget *Subtarget,
4597 SelectionDAG &DAG, SDLoc dl) {
4598 assert(VT.isVector() && "Expected a vector type");
4600 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4602 if (VT.is512BitVector()) {
4603 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4604 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4605 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4606 } else if (VT.is256BitVector()) {
4607 if (Subtarget->hasInt256()) { // AVX2
4608 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4609 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4611 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4612 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4614 } else if (VT.is128BitVector()) {
4615 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4617 llvm_unreachable("Unexpected vector type");
4619 return DAG.getBitcast(VT, Vec);
4622 /// Returns a vector_shuffle node for an unpackl operation.
4623 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4625 unsigned NumElems = VT.getVectorNumElements();
4626 SmallVector<int, 8> Mask;
4627 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4629 Mask.push_back(i + NumElems);
4631 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4634 /// Returns a vector_shuffle node for an unpackh operation.
4635 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4637 unsigned NumElems = VT.getVectorNumElements();
4638 SmallVector<int, 8> Mask;
4639 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4640 Mask.push_back(i + Half);
4641 Mask.push_back(i + NumElems + Half);
4643 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4646 /// Return a vector_shuffle of the specified vector of zero or undef vector.
4647 /// This produces a shuffle where the low element of V2 is swizzled into the
4648 /// zero/undef vector, landing at element Idx.
4649 /// This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4650 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4652 const X86Subtarget *Subtarget,
4653 SelectionDAG &DAG) {
4654 MVT VT = V2.getSimpleValueType();
4656 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4657 unsigned NumElems = VT.getVectorNumElements();
4658 SmallVector<int, 16> MaskVec;
4659 for (unsigned i = 0; i != NumElems; ++i)
4660 // If this is the insertion idx, put the low elt of V2 here.
4661 MaskVec.push_back(i == Idx ? NumElems : i);
4662 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4665 /// Calculates the shuffle mask corresponding to the target-specific opcode.
4666 /// Returns true if the Mask could be calculated. Sets IsUnary to true if only
4667 /// uses one source. Note that this will set IsUnary for shuffles which use a
4668 /// single input multiple times, and in those cases it will
4669 /// adjust the mask to only have indices within that single input.
4670 /// FIXME: Add support for Decode*Mask functions that return SM_SentinelZero.
4671 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4672 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4673 unsigned NumElems = VT.getVectorNumElements();
4677 bool IsFakeUnary = false;
4678 switch(N->getOpcode()) {
4679 case X86ISD::BLENDI:
4680 ImmN = N->getOperand(N->getNumOperands()-1);
4681 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4684 ImmN = N->getOperand(N->getNumOperands()-1);
4685 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4686 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4688 case X86ISD::UNPCKH:
4689 DecodeUNPCKHMask(VT, Mask);
4690 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4692 case X86ISD::UNPCKL:
4693 DecodeUNPCKLMask(VT, Mask);
4694 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4696 case X86ISD::MOVHLPS:
4697 DecodeMOVHLPSMask(NumElems, Mask);
4698 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4700 case X86ISD::MOVLHPS:
4701 DecodeMOVLHPSMask(NumElems, Mask);
4702 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4704 case X86ISD::PALIGNR:
4705 ImmN = N->getOperand(N->getNumOperands()-1);
4706 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4708 case X86ISD::PSHUFD:
4709 case X86ISD::VPERMILPI:
4710 ImmN = N->getOperand(N->getNumOperands()-1);
4711 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4714 case X86ISD::PSHUFHW:
4715 ImmN = N->getOperand(N->getNumOperands()-1);
4716 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4719 case X86ISD::PSHUFLW:
4720 ImmN = N->getOperand(N->getNumOperands()-1);
4721 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4724 case X86ISD::PSHUFB: {
4726 SDValue MaskNode = N->getOperand(1);
4727 while (MaskNode->getOpcode() == ISD::BITCAST)
4728 MaskNode = MaskNode->getOperand(0);
4730 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4731 // If we have a build-vector, then things are easy.
4732 MVT VT = MaskNode.getSimpleValueType();
4733 assert(VT.isVector() &&
4734 "Can't produce a non-vector with a build_vector!");
4735 if (!VT.isInteger())
4738 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4740 SmallVector<uint64_t, 32> RawMask;
4741 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4742 SDValue Op = MaskNode->getOperand(i);
4743 if (Op->getOpcode() == ISD::UNDEF) {
4744 RawMask.push_back((uint64_t)SM_SentinelUndef);
4747 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4750 APInt MaskElement = CN->getAPIntValue();
4752 // We now have to decode the element which could be any integer size and
4753 // extract each byte of it.
4754 for (int j = 0; j < NumBytesPerElement; ++j) {
4755 // Note that this is x86 and so always little endian: the low byte is
4756 // the first byte of the mask.
4757 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4758 MaskElement = MaskElement.lshr(8);
4761 DecodePSHUFBMask(RawMask, Mask);
4765 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4769 SDValue Ptr = MaskLoad->getBasePtr();
4770 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4771 Ptr->getOpcode() == X86ISD::WrapperRIP)
4772 Ptr = Ptr->getOperand(0);
4774 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4775 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4778 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4779 DecodePSHUFBMask(C, Mask);
4787 case X86ISD::VPERMI:
4788 ImmN = N->getOperand(N->getNumOperands()-1);
4789 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4794 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4796 case X86ISD::VPERM2X128:
4797 ImmN = N->getOperand(N->getNumOperands()-1);
4798 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4799 if (Mask.empty()) return false;
4800 // Mask only contains negative index if an element is zero.
4801 if (std::any_of(Mask.begin(), Mask.end(),
4802 [](int M){ return M == SM_SentinelZero; }))
4805 case X86ISD::MOVSLDUP:
4806 DecodeMOVSLDUPMask(VT, Mask);
4809 case X86ISD::MOVSHDUP:
4810 DecodeMOVSHDUPMask(VT, Mask);
4813 case X86ISD::MOVDDUP:
4814 DecodeMOVDDUPMask(VT, Mask);
4817 case X86ISD::MOVLHPD:
4818 case X86ISD::MOVLPD:
4819 case X86ISD::MOVLPS:
4820 // Not yet implemented
4822 case X86ISD::VPERMV: {
4824 SDValue MaskNode = N->getOperand(0);
4825 while (MaskNode->getOpcode() == ISD::BITCAST)
4826 MaskNode = MaskNode->getOperand(0);
4828 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements());
4829 SmallVector<uint64_t, 32> RawMask;
4830 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4831 // If we have a build-vector, then things are easy.
4832 assert(MaskNode.getSimpleValueType().isInteger() &&
4833 MaskNode.getSimpleValueType().getVectorNumElements() ==
4834 VT.getVectorNumElements());
4836 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4837 SDValue Op = MaskNode->getOperand(i);
4838 if (Op->getOpcode() == ISD::UNDEF)
4839 RawMask.push_back((uint64_t)SM_SentinelUndef);
4840 else if (isa<ConstantSDNode>(Op)) {
4841 APInt MaskElement = cast<ConstantSDNode>(Op)->getAPIntValue();
4842 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4846 DecodeVPERMVMask(RawMask, Mask);
4849 if (MaskNode->getOpcode() == X86ISD::VBROADCAST) {
4850 unsigned NumEltsInMask = MaskNode->getNumOperands();
4851 MaskNode = MaskNode->getOperand(0);
4852 auto *CN = dyn_cast<ConstantSDNode>(MaskNode);
4854 APInt MaskEltValue = CN->getAPIntValue();
4855 for (unsigned i = 0; i < NumEltsInMask; ++i)
4856 RawMask.push_back(MaskEltValue.getLoBits(MaskLoBits).getZExtValue());
4857 DecodeVPERMVMask(RawMask, Mask);
4860 // It may be a scalar load
4863 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4867 SDValue Ptr = MaskLoad->getBasePtr();
4868 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4869 Ptr->getOpcode() == X86ISD::WrapperRIP)
4870 Ptr = Ptr->getOperand(0);
4872 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4873 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4876 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4878 DecodeVPERMVMask(C, VT, Mask);
4885 case X86ISD::VPERMV3: {
4887 SDValue MaskNode = N->getOperand(1);
4888 while (MaskNode->getOpcode() == ISD::BITCAST)
4889 MaskNode = MaskNode->getOperand(1);
4891 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4892 // If we have a build-vector, then things are easy.
4893 assert(MaskNode.getSimpleValueType().isInteger() &&
4894 MaskNode.getSimpleValueType().getVectorNumElements() ==
4895 VT.getVectorNumElements());
4897 SmallVector<uint64_t, 32> RawMask;
4898 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements()*2);
4900 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4901 SDValue Op = MaskNode->getOperand(i);
4902 if (Op->getOpcode() == ISD::UNDEF)
4903 RawMask.push_back((uint64_t)SM_SentinelUndef);
4905 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4908 APInt MaskElement = CN->getAPIntValue();
4909 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4912 DecodeVPERMV3Mask(RawMask, Mask);
4916 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4920 SDValue Ptr = MaskLoad->getBasePtr();
4921 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4922 Ptr->getOpcode() == X86ISD::WrapperRIP)
4923 Ptr = Ptr->getOperand(0);
4925 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4926 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4929 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4931 DecodeVPERMV3Mask(C, VT, Mask);
4938 default: llvm_unreachable("unknown target shuffle node");
4941 // If we have a fake unary shuffle, the shuffle mask is spread across two
4942 // inputs that are actually the same node. Re-map the mask to always point
4943 // into the first input.
4946 if (M >= (int)Mask.size())
4952 /// Returns the scalar element that will make up the ith
4953 /// element of the result of the vector shuffle.
4954 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4957 return SDValue(); // Limit search depth.
4959 SDValue V = SDValue(N, 0);
4960 EVT VT = V.getValueType();
4961 unsigned Opcode = V.getOpcode();
4963 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4964 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4965 int Elt = SV->getMaskElt(Index);
4968 return DAG.getUNDEF(VT.getVectorElementType());
4970 unsigned NumElems = VT.getVectorNumElements();
4971 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4972 : SV->getOperand(1);
4973 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4976 // Recurse into target specific vector shuffles to find scalars.
4977 if (isTargetShuffle(Opcode)) {
4978 MVT ShufVT = V.getSimpleValueType();
4979 unsigned NumElems = ShufVT.getVectorNumElements();
4980 SmallVector<int, 16> ShuffleMask;
4983 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4986 int Elt = ShuffleMask[Index];
4988 return DAG.getUNDEF(ShufVT.getVectorElementType());
4990 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4992 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4996 // Actual nodes that may contain scalar elements
4997 if (Opcode == ISD::BITCAST) {
4998 V = V.getOperand(0);
4999 EVT SrcVT = V.getValueType();
5000 unsigned NumElems = VT.getVectorNumElements();
5002 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5006 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5007 return (Index == 0) ? V.getOperand(0)
5008 : DAG.getUNDEF(VT.getVectorElementType());
5010 if (V.getOpcode() == ISD::BUILD_VECTOR)
5011 return V.getOperand(Index);
5016 /// Custom lower build_vector of v16i8.
5017 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5018 unsigned NumNonZero, unsigned NumZero,
5020 const X86Subtarget* Subtarget,
5021 const TargetLowering &TLI) {
5029 // SSE4.1 - use PINSRB to insert each byte directly.
5030 if (Subtarget->hasSSE41()) {
5031 for (unsigned i = 0; i < 16; ++i) {
5032 bool isNonZero = (NonZeros & (1 << i)) != 0;
5036 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
5038 V = DAG.getUNDEF(MVT::v16i8);
5041 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5042 MVT::v16i8, V, Op.getOperand(i),
5043 DAG.getIntPtrConstant(i, dl));
5050 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
5051 for (unsigned i = 0; i < 16; ++i) {
5052 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5053 if (ThisIsNonZero && First) {
5055 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5057 V = DAG.getUNDEF(MVT::v8i16);
5062 SDValue ThisElt, LastElt;
5063 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5064 if (LastIsNonZero) {
5065 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5066 MVT::i16, Op.getOperand(i-1));
5068 if (ThisIsNonZero) {
5069 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5070 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5071 ThisElt, DAG.getConstant(8, dl, MVT::i8));
5073 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5077 if (ThisElt.getNode())
5078 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5079 DAG.getIntPtrConstant(i/2, dl));
5083 return DAG.getBitcast(MVT::v16i8, V);
5086 /// Custom lower build_vector of v8i16.
5087 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5088 unsigned NumNonZero, unsigned NumZero,
5090 const X86Subtarget* Subtarget,
5091 const TargetLowering &TLI) {
5098 for (unsigned i = 0; i < 8; ++i) {
5099 bool isNonZero = (NonZeros & (1 << i)) != 0;
5103 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5105 V = DAG.getUNDEF(MVT::v8i16);
5108 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5109 MVT::v8i16, V, Op.getOperand(i),
5110 DAG.getIntPtrConstant(i, dl));
5117 /// Custom lower build_vector of v4i32 or v4f32.
5118 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5119 const X86Subtarget *Subtarget,
5120 const TargetLowering &TLI) {
5121 // Find all zeroable elements.
5122 std::bitset<4> Zeroable;
5123 for (int i=0; i < 4; ++i) {
5124 SDValue Elt = Op->getOperand(i);
5125 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5127 assert(Zeroable.size() - Zeroable.count() > 1 &&
5128 "We expect at least two non-zero elements!");
5130 // We only know how to deal with build_vector nodes where elements are either
5131 // zeroable or extract_vector_elt with constant index.
5132 SDValue FirstNonZero;
5133 unsigned FirstNonZeroIdx;
5134 for (unsigned i=0; i < 4; ++i) {
5137 SDValue Elt = Op->getOperand(i);
5138 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5139 !isa<ConstantSDNode>(Elt.getOperand(1)))
5141 // Make sure that this node is extracting from a 128-bit vector.
5142 MVT VT = Elt.getOperand(0).getSimpleValueType();
5143 if (!VT.is128BitVector())
5145 if (!FirstNonZero.getNode()) {
5147 FirstNonZeroIdx = i;
5151 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5152 SDValue V1 = FirstNonZero.getOperand(0);
5153 MVT VT = V1.getSimpleValueType();
5155 // See if this build_vector can be lowered as a blend with zero.
5157 unsigned EltMaskIdx, EltIdx;
5159 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5160 if (Zeroable[EltIdx]) {
5161 // The zero vector will be on the right hand side.
5162 Mask[EltIdx] = EltIdx+4;
5166 Elt = Op->getOperand(EltIdx);
5167 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5168 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5169 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5171 Mask[EltIdx] = EltIdx;
5175 // Let the shuffle legalizer deal with blend operations.
5176 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5177 if (V1.getSimpleValueType() != VT)
5178 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5179 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5182 // See if we can lower this build_vector to a INSERTPS.
5183 if (!Subtarget->hasSSE41())
5186 SDValue V2 = Elt.getOperand(0);
5187 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5190 bool CanFold = true;
5191 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5195 SDValue Current = Op->getOperand(i);
5196 SDValue SrcVector = Current->getOperand(0);
5199 CanFold = SrcVector == V1 &&
5200 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5206 assert(V1.getNode() && "Expected at least two non-zero elements!");
5207 if (V1.getSimpleValueType() != MVT::v4f32)
5208 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5209 if (V2.getSimpleValueType() != MVT::v4f32)
5210 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5212 // Ok, we can emit an INSERTPS instruction.
5213 unsigned ZMask = Zeroable.to_ulong();
5215 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5216 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5218 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
5219 DAG.getIntPtrConstant(InsertPSMask, DL));
5220 return DAG.getBitcast(VT, Result);
5223 /// Return a vector logical shift node.
5224 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5225 unsigned NumBits, SelectionDAG &DAG,
5226 const TargetLowering &TLI, SDLoc dl) {
5227 assert(VT.is128BitVector() && "Unknown type for VShift");
5228 MVT ShVT = MVT::v2i64;
5229 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5230 SrcOp = DAG.getBitcast(ShVT, SrcOp);
5231 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(DAG.getDataLayout(), VT);
5232 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
5233 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
5234 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
5238 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5240 // Check if the scalar load can be widened into a vector load. And if
5241 // the address is "base + cst" see if the cst can be "absorbed" into
5242 // the shuffle mask.
5243 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5244 SDValue Ptr = LD->getBasePtr();
5245 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5247 EVT PVT = LD->getValueType(0);
5248 if (PVT != MVT::i32 && PVT != MVT::f32)
5253 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5254 FI = FINode->getIndex();
5256 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5257 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5258 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5259 Offset = Ptr.getConstantOperandVal(1);
5260 Ptr = Ptr.getOperand(0);
5265 // FIXME: 256-bit vector instructions don't require a strict alignment,
5266 // improve this code to support it better.
5267 unsigned RequiredAlign = VT.getSizeInBits()/8;
5268 SDValue Chain = LD->getChain();
5269 // Make sure the stack object alignment is at least 16 or 32.
5270 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5271 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5272 if (MFI->isFixedObjectIndex(FI)) {
5273 // Can't change the alignment. FIXME: It's possible to compute
5274 // the exact stack offset and reference FI + adjust offset instead.
5275 // If someone *really* cares about this. That's the way to implement it.
5278 MFI->setObjectAlignment(FI, RequiredAlign);
5282 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5283 // Ptr + (Offset & ~15).
5286 if ((Offset % RequiredAlign) & 3)
5288 int64_t StartOffset = Offset & ~int64_t(RequiredAlign - 1);
5291 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5292 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
5295 int EltNo = (Offset - StartOffset) >> 2;
5296 unsigned NumElems = VT.getVectorNumElements();
5298 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5299 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5300 LD->getPointerInfo().getWithOffset(StartOffset),
5301 false, false, false, 0);
5303 SmallVector<int, 8> Mask(NumElems, EltNo);
5305 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5311 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
5312 /// elements can be replaced by a single large load which has the same value as
5313 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
5315 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5317 /// FIXME: we'd also like to handle the case where the last elements are zero
5318 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5319 /// There's even a handy isZeroNode for that purpose.
5320 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
5321 SDLoc &DL, SelectionDAG &DAG,
5322 bool isAfterLegalize) {
5323 unsigned NumElems = Elts.size();
5325 LoadSDNode *LDBase = nullptr;
5326 unsigned LastLoadedElt = -1U;
5328 // For each element in the initializer, see if we've found a load or an undef.
5329 // If we don't find an initial load element, or later load elements are
5330 // non-consecutive, bail out.
5331 for (unsigned i = 0; i < NumElems; ++i) {
5332 SDValue Elt = Elts[i];
5333 // Look through a bitcast.
5334 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
5335 Elt = Elt.getOperand(0);
5336 if (!Elt.getNode() ||
5337 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5340 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5342 LDBase = cast<LoadSDNode>(Elt.getNode());
5346 if (Elt.getOpcode() == ISD::UNDEF)
5349 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5350 EVT LdVT = Elt.getValueType();
5351 // Each loaded element must be the correct fractional portion of the
5352 // requested vector load.
5353 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
5355 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
5360 // If we have found an entire vector of loads and undefs, then return a large
5361 // load of the entire vector width starting at the base pointer. If we found
5362 // consecutive loads for the low half, generate a vzext_load node.
5363 if (LastLoadedElt == NumElems - 1) {
5364 assert(LDBase && "Did not find base load for merging consecutive loads");
5365 EVT EltVT = LDBase->getValueType(0);
5366 // Ensure that the input vector size for the merged loads matches the
5367 // cumulative size of the input elements.
5368 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
5371 if (isAfterLegalize &&
5372 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5375 SDValue NewLd = SDValue();
5377 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5378 LDBase->getPointerInfo(), LDBase->isVolatile(),
5379 LDBase->isNonTemporal(), LDBase->isInvariant(),
5380 LDBase->getAlignment());
5382 if (LDBase->hasAnyUseOfValue(1)) {
5383 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5385 SDValue(NewLd.getNode(), 1));
5386 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5387 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5388 SDValue(NewLd.getNode(), 1));
5394 //TODO: The code below fires only for for loading the low v2i32 / v2f32
5395 //of a v4i32 / v4f32. It's probably worth generalizing.
5396 EVT EltVT = VT.getVectorElementType();
5397 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
5398 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5399 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5400 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5402 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5403 LDBase->getPointerInfo(),
5404 LDBase->getAlignment(),
5405 false/*isVolatile*/, true/*ReadMem*/,
5408 // Make sure the newly-created LOAD is in the same position as LDBase in
5409 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5410 // update uses of LDBase's output chain to use the TokenFactor.
5411 if (LDBase->hasAnyUseOfValue(1)) {
5412 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5413 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5414 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5415 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5416 SDValue(ResNode.getNode(), 1));
5419 return DAG.getBitcast(VT, ResNode);
5424 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5425 /// to generate a splat value for the following cases:
5426 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5427 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5428 /// a scalar load, or a constant.
5429 /// The VBROADCAST node is returned when a pattern is found,
5430 /// or SDValue() otherwise.
5431 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5432 SelectionDAG &DAG) {
5433 // VBROADCAST requires AVX.
5434 // TODO: Splats could be generated for non-AVX CPUs using SSE
5435 // instructions, but there's less potential gain for only 128-bit vectors.
5436 if (!Subtarget->hasAVX())
5439 MVT VT = Op.getSimpleValueType();
5442 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5443 "Unsupported vector type for broadcast.");
5448 switch (Op.getOpcode()) {
5450 // Unknown pattern found.
5453 case ISD::BUILD_VECTOR: {
5454 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5455 BitVector UndefElements;
5456 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5458 // We need a splat of a single value to use broadcast, and it doesn't
5459 // make any sense if the value is only in one element of the vector.
5460 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5464 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5465 Ld.getOpcode() == ISD::ConstantFP);
5467 // Make sure that all of the users of a non-constant load are from the
5468 // BUILD_VECTOR node.
5469 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5474 case ISD::VECTOR_SHUFFLE: {
5475 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5477 // Shuffles must have a splat mask where the first element is
5479 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5482 SDValue Sc = Op.getOperand(0);
5483 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5484 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5486 if (!Subtarget->hasInt256())
5489 // Use the register form of the broadcast instruction available on AVX2.
5490 if (VT.getSizeInBits() >= 256)
5491 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5492 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5495 Ld = Sc.getOperand(0);
5496 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5497 Ld.getOpcode() == ISD::ConstantFP);
5499 // The scalar_to_vector node and the suspected
5500 // load node must have exactly one user.
5501 // Constants may have multiple users.
5503 // AVX-512 has register version of the broadcast
5504 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5505 Ld.getValueType().getSizeInBits() >= 32;
5506 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5513 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5514 bool IsGE256 = (VT.getSizeInBits() >= 256);
5516 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5517 // instruction to save 8 or more bytes of constant pool data.
5518 // TODO: If multiple splats are generated to load the same constant,
5519 // it may be detrimental to overall size. There needs to be a way to detect
5520 // that condition to know if this is truly a size win.
5521 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
5523 // Handle broadcasting a single constant scalar from the constant pool
5525 // On Sandybridge (no AVX2), it is still better to load a constant vector
5526 // from the constant pool and not to broadcast it from a scalar.
5527 // But override that restriction when optimizing for size.
5528 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5529 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5530 EVT CVT = Ld.getValueType();
5531 assert(!CVT.isVector() && "Must not broadcast a vector type");
5533 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5534 // For size optimization, also splat v2f64 and v2i64, and for size opt
5535 // with AVX2, also splat i8 and i16.
5536 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5537 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5538 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5539 const Constant *C = nullptr;
5540 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5541 C = CI->getConstantIntValue();
5542 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5543 C = CF->getConstantFPValue();
5545 assert(C && "Invalid constant type");
5547 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5549 DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
5550 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5552 CVT, dl, DAG.getEntryNode(), CP,
5553 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
5554 false, false, Alignment);
5556 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5560 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5562 // Handle AVX2 in-register broadcasts.
5563 if (!IsLoad && Subtarget->hasInt256() &&
5564 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5565 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5567 // The scalar source must be a normal load.
5571 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5572 (Subtarget->hasVLX() && ScalarSize == 64))
5573 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5575 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5576 // double since there is no vbroadcastsd xmm
5577 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5578 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5579 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5582 // Unsupported broadcast.
5586 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5587 /// underlying vector and index.
5589 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5591 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5593 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5594 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5597 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5599 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5601 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5602 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5605 // In this case the vector is the extract_subvector expression and the index
5606 // is 2, as specified by the shuffle.
5607 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5608 SDValue ShuffleVec = SVOp->getOperand(0);
5609 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5610 assert(ShuffleVecVT.getVectorElementType() ==
5611 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5613 int ShuffleIdx = SVOp->getMaskElt(Idx);
5614 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5615 ExtractedFromVec = ShuffleVec;
5621 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5622 MVT VT = Op.getSimpleValueType();
5624 // Skip if insert_vec_elt is not supported.
5625 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5626 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5630 unsigned NumElems = Op.getNumOperands();
5634 SmallVector<unsigned, 4> InsertIndices;
5635 SmallVector<int, 8> Mask(NumElems, -1);
5637 for (unsigned i = 0; i != NumElems; ++i) {
5638 unsigned Opc = Op.getOperand(i).getOpcode();
5640 if (Opc == ISD::UNDEF)
5643 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5644 // Quit if more than 1 elements need inserting.
5645 if (InsertIndices.size() > 1)
5648 InsertIndices.push_back(i);
5652 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5653 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5654 // Quit if non-constant index.
5655 if (!isa<ConstantSDNode>(ExtIdx))
5657 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5659 // Quit if extracted from vector of different type.
5660 if (ExtractedFromVec.getValueType() != VT)
5663 if (!VecIn1.getNode())
5664 VecIn1 = ExtractedFromVec;
5665 else if (VecIn1 != ExtractedFromVec) {
5666 if (!VecIn2.getNode())
5667 VecIn2 = ExtractedFromVec;
5668 else if (VecIn2 != ExtractedFromVec)
5669 // Quit if more than 2 vectors to shuffle
5673 if (ExtractedFromVec == VecIn1)
5675 else if (ExtractedFromVec == VecIn2)
5676 Mask[i] = Idx + NumElems;
5679 if (!VecIn1.getNode())
5682 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5683 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5684 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5685 unsigned Idx = InsertIndices[i];
5686 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5687 DAG.getIntPtrConstant(Idx, DL));
5693 static SDValue ConvertI1VectorToInteger(SDValue Op, SelectionDAG &DAG) {
5694 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5695 Op.getScalarValueSizeInBits() == 1 &&
5696 "Can not convert non-constant vector");
5697 uint64_t Immediate = 0;
5698 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5699 SDValue In = Op.getOperand(idx);
5700 if (In.getOpcode() != ISD::UNDEF)
5701 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5705 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5706 return DAG.getConstant(Immediate, dl, VT);
5708 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5710 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5712 MVT VT = Op.getSimpleValueType();
5713 assert((VT.getVectorElementType() == MVT::i1) &&
5714 "Unexpected type in LowerBUILD_VECTORvXi1!");
5717 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5718 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5719 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5720 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5723 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5724 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5725 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5726 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5729 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5730 SDValue Imm = ConvertI1VectorToInteger(Op, DAG);
5731 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5732 return DAG.getBitcast(VT, Imm);
5733 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5734 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5735 DAG.getIntPtrConstant(0, dl));
5738 // Vector has one or more non-const elements
5739 uint64_t Immediate = 0;
5740 SmallVector<unsigned, 16> NonConstIdx;
5741 bool IsSplat = true;
5742 bool HasConstElts = false;
5744 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5745 SDValue In = Op.getOperand(idx);
5746 if (In.getOpcode() == ISD::UNDEF)
5748 if (!isa<ConstantSDNode>(In))
5749 NonConstIdx.push_back(idx);
5751 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5752 HasConstElts = true;
5756 else if (In != Op.getOperand(SplatIdx))
5760 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5762 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5763 DAG.getConstant(1, dl, VT),
5764 DAG.getConstant(0, dl, VT));
5766 // insert elements one by one
5770 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5771 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5773 else if (HasConstElts)
5774 Imm = DAG.getConstant(0, dl, VT);
5776 Imm = DAG.getUNDEF(VT);
5777 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5778 DstVec = DAG.getBitcast(VT, Imm);
5780 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5781 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5782 DAG.getIntPtrConstant(0, dl));
5785 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5786 unsigned InsertIdx = NonConstIdx[i];
5787 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5788 Op.getOperand(InsertIdx),
5789 DAG.getIntPtrConstant(InsertIdx, dl));
5794 /// \brief Return true if \p N implements a horizontal binop and return the
5795 /// operands for the horizontal binop into V0 and V1.
5797 /// This is a helper function of LowerToHorizontalOp().
5798 /// This function checks that the build_vector \p N in input implements a
5799 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5800 /// operation to match.
5801 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5802 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5803 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5806 /// This function only analyzes elements of \p N whose indices are
5807 /// in range [BaseIdx, LastIdx).
5808 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5810 unsigned BaseIdx, unsigned LastIdx,
5811 SDValue &V0, SDValue &V1) {
5812 EVT VT = N->getValueType(0);
5814 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5815 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5816 "Invalid Vector in input!");
5818 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5819 bool CanFold = true;
5820 unsigned ExpectedVExtractIdx = BaseIdx;
5821 unsigned NumElts = LastIdx - BaseIdx;
5822 V0 = DAG.getUNDEF(VT);
5823 V1 = DAG.getUNDEF(VT);
5825 // Check if N implements a horizontal binop.
5826 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5827 SDValue Op = N->getOperand(i + BaseIdx);
5830 if (Op->getOpcode() == ISD::UNDEF) {
5831 // Update the expected vector extract index.
5832 if (i * 2 == NumElts)
5833 ExpectedVExtractIdx = BaseIdx;
5834 ExpectedVExtractIdx += 2;
5838 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5843 SDValue Op0 = Op.getOperand(0);
5844 SDValue Op1 = Op.getOperand(1);
5846 // Try to match the following pattern:
5847 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5848 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5849 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5850 Op0.getOperand(0) == Op1.getOperand(0) &&
5851 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5852 isa<ConstantSDNode>(Op1.getOperand(1)));
5856 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5857 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5859 if (i * 2 < NumElts) {
5860 if (V0.getOpcode() == ISD::UNDEF) {
5861 V0 = Op0.getOperand(0);
5862 if (V0.getValueType() != VT)
5866 if (V1.getOpcode() == ISD::UNDEF) {
5867 V1 = Op0.getOperand(0);
5868 if (V1.getValueType() != VT)
5871 if (i * 2 == NumElts)
5872 ExpectedVExtractIdx = BaseIdx;
5875 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5876 if (I0 == ExpectedVExtractIdx)
5877 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5878 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5879 // Try to match the following dag sequence:
5880 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5881 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5885 ExpectedVExtractIdx += 2;
5891 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5892 /// a concat_vector.
5894 /// This is a helper function of LowerToHorizontalOp().
5895 /// This function expects two 256-bit vectors called V0 and V1.
5896 /// At first, each vector is split into two separate 128-bit vectors.
5897 /// Then, the resulting 128-bit vectors are used to implement two
5898 /// horizontal binary operations.
5900 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5902 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5903 /// the two new horizontal binop.
5904 /// When Mode is set, the first horizontal binop dag node would take as input
5905 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5906 /// horizontal binop dag node would take as input the lower 128-bit of V1
5907 /// and the upper 128-bit of V1.
5909 /// HADD V0_LO, V0_HI
5910 /// HADD V1_LO, V1_HI
5912 /// Otherwise, the first horizontal binop dag node takes as input the lower
5913 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5914 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
5916 /// HADD V0_LO, V1_LO
5917 /// HADD V0_HI, V1_HI
5919 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5920 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5921 /// the upper 128-bits of the result.
5922 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5923 SDLoc DL, SelectionDAG &DAG,
5924 unsigned X86Opcode, bool Mode,
5925 bool isUndefLO, bool isUndefHI) {
5926 EVT VT = V0.getValueType();
5927 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5928 "Invalid nodes in input!");
5930 unsigned NumElts = VT.getVectorNumElements();
5931 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5932 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5933 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5934 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5935 EVT NewVT = V0_LO.getValueType();
5937 SDValue LO = DAG.getUNDEF(NewVT);
5938 SDValue HI = DAG.getUNDEF(NewVT);
5941 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5942 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5943 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5944 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5945 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5947 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5948 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5949 V1_LO->getOpcode() != ISD::UNDEF))
5950 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5952 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5953 V1_HI->getOpcode() != ISD::UNDEF))
5954 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5957 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5960 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5962 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5963 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5964 MVT VT = BV->getSimpleValueType(0);
5965 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5966 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5970 unsigned NumElts = VT.getVectorNumElements();
5971 SDValue InVec0 = DAG.getUNDEF(VT);
5972 SDValue InVec1 = DAG.getUNDEF(VT);
5974 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5975 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5977 // Odd-numbered elements in the input build vector are obtained from
5978 // adding two integer/float elements.
5979 // Even-numbered elements in the input build vector are obtained from
5980 // subtracting two integer/float elements.
5981 unsigned ExpectedOpcode = ISD::FSUB;
5982 unsigned NextExpectedOpcode = ISD::FADD;
5983 bool AddFound = false;
5984 bool SubFound = false;
5986 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5987 SDValue Op = BV->getOperand(i);
5989 // Skip 'undef' values.
5990 unsigned Opcode = Op.getOpcode();
5991 if (Opcode == ISD::UNDEF) {
5992 std::swap(ExpectedOpcode, NextExpectedOpcode);
5996 // Early exit if we found an unexpected opcode.
5997 if (Opcode != ExpectedOpcode)
6000 SDValue Op0 = Op.getOperand(0);
6001 SDValue Op1 = Op.getOperand(1);
6003 // Try to match the following pattern:
6004 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6005 // Early exit if we cannot match that sequence.
6006 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6007 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6008 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6009 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6010 Op0.getOperand(1) != Op1.getOperand(1))
6013 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6017 // We found a valid add/sub node. Update the information accordingly.
6023 // Update InVec0 and InVec1.
6024 if (InVec0.getOpcode() == ISD::UNDEF) {
6025 InVec0 = Op0.getOperand(0);
6026 if (InVec0.getSimpleValueType() != VT)
6029 if (InVec1.getOpcode() == ISD::UNDEF) {
6030 InVec1 = Op1.getOperand(0);
6031 if (InVec1.getSimpleValueType() != VT)
6035 // Make sure that operands in input to each add/sub node always
6036 // come from a same pair of vectors.
6037 if (InVec0 != Op0.getOperand(0)) {
6038 if (ExpectedOpcode == ISD::FSUB)
6041 // FADD is commutable. Try to commute the operands
6042 // and then test again.
6043 std::swap(Op0, Op1);
6044 if (InVec0 != Op0.getOperand(0))
6048 if (InVec1 != Op1.getOperand(0))
6051 // Update the pair of expected opcodes.
6052 std::swap(ExpectedOpcode, NextExpectedOpcode);
6055 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6056 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6057 InVec1.getOpcode() != ISD::UNDEF)
6058 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6063 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
6064 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
6065 const X86Subtarget *Subtarget,
6066 SelectionDAG &DAG) {
6067 MVT VT = BV->getSimpleValueType(0);
6068 unsigned NumElts = VT.getVectorNumElements();
6069 unsigned NumUndefsLO = 0;
6070 unsigned NumUndefsHI = 0;
6071 unsigned Half = NumElts/2;
6073 // Count the number of UNDEF operands in the build_vector in input.
6074 for (unsigned i = 0, e = Half; i != e; ++i)
6075 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6078 for (unsigned i = Half, e = NumElts; i != e; ++i)
6079 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6082 // Early exit if this is either a build_vector of all UNDEFs or all the
6083 // operands but one are UNDEF.
6084 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6088 SDValue InVec0, InVec1;
6089 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6090 // Try to match an SSE3 float HADD/HSUB.
6091 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6092 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6094 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6095 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6096 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6097 // Try to match an SSSE3 integer HADD/HSUB.
6098 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6099 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6101 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6102 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6105 if (!Subtarget->hasAVX())
6108 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6109 // Try to match an AVX horizontal add/sub of packed single/double
6110 // precision floating point values from 256-bit vectors.
6111 SDValue InVec2, InVec3;
6112 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6113 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6114 ((InVec0.getOpcode() == ISD::UNDEF ||
6115 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6116 ((InVec1.getOpcode() == ISD::UNDEF ||
6117 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6118 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6120 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6121 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6122 ((InVec0.getOpcode() == ISD::UNDEF ||
6123 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6124 ((InVec1.getOpcode() == ISD::UNDEF ||
6125 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6126 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6127 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6128 // Try to match an AVX2 horizontal add/sub of signed integers.
6129 SDValue InVec2, InVec3;
6131 bool CanFold = true;
6133 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6134 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6135 ((InVec0.getOpcode() == ISD::UNDEF ||
6136 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6137 ((InVec1.getOpcode() == ISD::UNDEF ||
6138 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6139 X86Opcode = X86ISD::HADD;
6140 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6141 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6142 ((InVec0.getOpcode() == ISD::UNDEF ||
6143 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6144 ((InVec1.getOpcode() == ISD::UNDEF ||
6145 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6146 X86Opcode = X86ISD::HSUB;
6151 // Fold this build_vector into a single horizontal add/sub.
6152 // Do this only if the target has AVX2.
6153 if (Subtarget->hasAVX2())
6154 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6156 // Do not try to expand this build_vector into a pair of horizontal
6157 // add/sub if we can emit a pair of scalar add/sub.
6158 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6161 // Convert this build_vector into a pair of horizontal binop followed by
6163 bool isUndefLO = NumUndefsLO == Half;
6164 bool isUndefHI = NumUndefsHI == Half;
6165 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6166 isUndefLO, isUndefHI);
6170 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6171 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6173 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6174 X86Opcode = X86ISD::HADD;
6175 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6176 X86Opcode = X86ISD::HSUB;
6177 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6178 X86Opcode = X86ISD::FHADD;
6179 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6180 X86Opcode = X86ISD::FHSUB;
6184 // Don't try to expand this build_vector into a pair of horizontal add/sub
6185 // if we can simply emit a pair of scalar add/sub.
6186 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6189 // Convert this build_vector into two horizontal add/sub followed by
6191 bool isUndefLO = NumUndefsLO == Half;
6192 bool isUndefHI = NumUndefsHI == Half;
6193 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6194 isUndefLO, isUndefHI);
6201 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6204 MVT VT = Op.getSimpleValueType();
6205 MVT ExtVT = VT.getVectorElementType();
6206 unsigned NumElems = Op.getNumOperands();
6208 // Generate vectors for predicate vectors.
6209 if (VT.getVectorElementType() == MVT::i1 && Subtarget->hasAVX512())
6210 return LowerBUILD_VECTORvXi1(Op, DAG);
6212 // Vectors containing all zeros can be matched by pxor and xorps later
6213 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6214 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6215 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6216 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6219 return getZeroVector(VT, Subtarget, DAG, dl);
6222 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6223 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6224 // vpcmpeqd on 256-bit vectors.
6225 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6226 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6229 if (!VT.is512BitVector())
6230 return getOnesVector(VT, Subtarget, DAG, dl);
6233 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
6234 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
6236 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
6237 return HorizontalOp;
6238 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
6241 unsigned EVTBits = ExtVT.getSizeInBits();
6243 unsigned NumZero = 0;
6244 unsigned NumNonZero = 0;
6245 uint64_t NonZeros = 0;
6246 bool IsAllConstants = true;
6247 SmallSet<SDValue, 8> Values;
6248 for (unsigned i = 0; i < NumElems; ++i) {
6249 SDValue Elt = Op.getOperand(i);
6250 if (Elt.getOpcode() == ISD::UNDEF)
6253 if (Elt.getOpcode() != ISD::Constant &&
6254 Elt.getOpcode() != ISD::ConstantFP)
6255 IsAllConstants = false;
6256 if (X86::isZeroNode(Elt))
6259 assert(i < sizeof(NonZeros) * 8); // Make sure the shift is within range.
6260 NonZeros |= ((uint64_t)1 << i);
6265 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6266 if (NumNonZero == 0)
6267 return DAG.getUNDEF(VT);
6269 // Special case for single non-zero, non-undef, element.
6270 if (NumNonZero == 1) {
6271 unsigned Idx = countTrailingZeros(NonZeros);
6272 SDValue Item = Op.getOperand(Idx);
6274 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6275 // the value are obviously zero, truncate the value to i32 and do the
6276 // insertion that way. Only do this if the value is non-constant or if the
6277 // value is a constant being inserted into element 0. It is cheaper to do
6278 // a constant pool load than it is to do a movd + shuffle.
6279 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6280 (!IsAllConstants || Idx == 0)) {
6281 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6283 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6284 MVT VecVT = MVT::v4i32;
6286 // Truncate the value (which may itself be a constant) to i32, and
6287 // convert it to a vector with movd (S2V+shuffle to zero extend).
6288 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6289 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6290 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
6291 Item, Idx * 2, true, Subtarget, DAG));
6295 // If we have a constant or non-constant insertion into the low element of
6296 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6297 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6298 // depending on what the source datatype is.
6301 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6303 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6304 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6305 if (VT.is512BitVector()) {
6306 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6307 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6308 Item, DAG.getIntPtrConstant(0, dl));
6310 assert((VT.is128BitVector() || VT.is256BitVector()) &&
6311 "Expected an SSE value type!");
6312 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6313 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6314 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6317 // We can't directly insert an i8 or i16 into a vector, so zero extend
6319 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6320 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6321 if (VT.is256BitVector()) {
6322 if (Subtarget->hasAVX()) {
6323 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
6324 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6326 // Without AVX, we need to extend to a 128-bit vector and then
6327 // insert into the 256-bit vector.
6328 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6329 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6330 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6333 assert(VT.is128BitVector() && "Expected an SSE value type!");
6334 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6335 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6337 return DAG.getBitcast(VT, Item);
6341 // Is it a vector logical left shift?
6342 if (NumElems == 2 && Idx == 1 &&
6343 X86::isZeroNode(Op.getOperand(0)) &&
6344 !X86::isZeroNode(Op.getOperand(1))) {
6345 unsigned NumBits = VT.getSizeInBits();
6346 return getVShift(true, VT,
6347 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6348 VT, Op.getOperand(1)),
6349 NumBits/2, DAG, *this, dl);
6352 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6355 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6356 // is a non-constant being inserted into an element other than the low one,
6357 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6358 // movd/movss) to move this into the low element, then shuffle it into
6360 if (EVTBits == 32) {
6361 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6362 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6366 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6367 if (Values.size() == 1) {
6368 if (EVTBits == 32) {
6369 // Instead of a shuffle like this:
6370 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6371 // Check if it's possible to issue this instead.
6372 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6373 unsigned Idx = countTrailingZeros(NonZeros);
6374 SDValue Item = Op.getOperand(Idx);
6375 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6376 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6381 // A vector full of immediates; various special cases are already
6382 // handled, so this is best done with a single constant-pool load.
6386 // For AVX-length vectors, see if we can use a vector load to get all of the
6387 // elements, otherwise build the individual 128-bit pieces and use
6388 // shuffles to put them in place.
6389 if (VT.is256BitVector() || VT.is512BitVector()) {
6390 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
6392 // Check for a build vector of consecutive loads.
6393 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6396 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6398 // Build both the lower and upper subvector.
6399 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6400 makeArrayRef(&V[0], NumElems/2));
6401 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6402 makeArrayRef(&V[NumElems / 2], NumElems/2));
6404 // Recreate the wider vector with the lower and upper part.
6405 if (VT.is256BitVector())
6406 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6407 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6410 // Let legalizer expand 2-wide build_vectors.
6411 if (EVTBits == 64) {
6412 if (NumNonZero == 1) {
6413 // One half is zero or undef.
6414 unsigned Idx = countTrailingZeros(NonZeros);
6415 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6416 Op.getOperand(Idx));
6417 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6422 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6423 if (EVTBits == 8 && NumElems == 16)
6424 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros, NumNonZero, NumZero,
6425 DAG, Subtarget, *this))
6428 if (EVTBits == 16 && NumElems == 8)
6429 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros, NumNonZero, NumZero,
6430 DAG, Subtarget, *this))
6433 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6434 if (EVTBits == 32 && NumElems == 4)
6435 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
6438 // If element VT is == 32 bits, turn it into a number of shuffles.
6439 SmallVector<SDValue, 8> V(NumElems);
6440 if (NumElems == 4 && NumZero > 0) {
6441 for (unsigned i = 0; i < 4; ++i) {
6442 bool isZero = !(NonZeros & (1ULL << i));
6444 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6446 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6449 for (unsigned i = 0; i < 2; ++i) {
6450 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6453 V[i] = V[i*2]; // Must be a zero vector.
6456 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6459 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6462 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6467 bool Reverse1 = (NonZeros & 0x3) == 2;
6468 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6472 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6473 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6475 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6478 if (Values.size() > 1 && VT.is128BitVector()) {
6479 // Check for a build vector of consecutive loads.
6480 for (unsigned i = 0; i < NumElems; ++i)
6481 V[i] = Op.getOperand(i);
6483 // Check for elements which are consecutive loads.
6484 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6487 // Check for a build vector from mostly shuffle plus few inserting.
6488 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6491 // For SSE 4.1, use insertps to put the high elements into the low element.
6492 if (Subtarget->hasSSE41()) {
6494 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6495 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6497 Result = DAG.getUNDEF(VT);
6499 for (unsigned i = 1; i < NumElems; ++i) {
6500 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6501 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6502 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6507 // Otherwise, expand into a number of unpckl*, start by extending each of
6508 // our (non-undef) elements to the full vector width with the element in the
6509 // bottom slot of the vector (which generates no code for SSE).
6510 for (unsigned i = 0; i < NumElems; ++i) {
6511 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6512 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6514 V[i] = DAG.getUNDEF(VT);
6517 // Next, we iteratively mix elements, e.g. for v4f32:
6518 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6519 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6520 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6521 unsigned EltStride = NumElems >> 1;
6522 while (EltStride != 0) {
6523 for (unsigned i = 0; i < EltStride; ++i) {
6524 // If V[i+EltStride] is undef and this is the first round of mixing,
6525 // then it is safe to just drop this shuffle: V[i] is already in the
6526 // right place, the one element (since it's the first round) being
6527 // inserted as undef can be dropped. This isn't safe for successive
6528 // rounds because they will permute elements within both vectors.
6529 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6530 EltStride == NumElems/2)
6533 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6542 // 256-bit AVX can use the vinsertf128 instruction
6543 // to create 256-bit vectors from two other 128-bit ones.
6544 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6546 MVT ResVT = Op.getSimpleValueType();
6548 assert((ResVT.is256BitVector() ||
6549 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6551 SDValue V1 = Op.getOperand(0);
6552 SDValue V2 = Op.getOperand(1);
6553 unsigned NumElems = ResVT.getVectorNumElements();
6554 if (ResVT.is256BitVector())
6555 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6557 if (Op.getNumOperands() == 4) {
6558 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(),
6559 ResVT.getVectorNumElements()/2);
6560 SDValue V3 = Op.getOperand(2);
6561 SDValue V4 = Op.getOperand(3);
6562 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6563 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6565 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6568 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6569 const X86Subtarget *Subtarget,
6570 SelectionDAG & DAG) {
6572 MVT ResVT = Op.getSimpleValueType();
6573 unsigned NumOfOperands = Op.getNumOperands();
6575 assert(isPowerOf2_32(NumOfOperands) &&
6576 "Unexpected number of operands in CONCAT_VECTORS");
6578 SDValue Undef = DAG.getUNDEF(ResVT);
6579 if (NumOfOperands > 2) {
6580 // Specialize the cases when all, or all but one, of the operands are undef.
6581 unsigned NumOfDefinedOps = 0;
6583 for (unsigned i = 0; i < NumOfOperands; i++)
6584 if (!Op.getOperand(i).isUndef()) {
6588 if (NumOfDefinedOps == 0)
6590 if (NumOfDefinedOps == 1) {
6591 unsigned SubVecNumElts =
6592 Op.getOperand(OpIdx).getValueType().getVectorNumElements();
6593 SDValue IdxVal = DAG.getIntPtrConstant(SubVecNumElts * OpIdx, dl);
6594 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef,
6595 Op.getOperand(OpIdx), IdxVal);
6598 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(),
6599 ResVT.getVectorNumElements()/2);
6600 SmallVector<SDValue, 2> Ops;
6601 for (unsigned i = 0; i < NumOfOperands/2; i++)
6602 Ops.push_back(Op.getOperand(i));
6603 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6605 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6606 Ops.push_back(Op.getOperand(i));
6607 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6608 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6612 SDValue V1 = Op.getOperand(0);
6613 SDValue V2 = Op.getOperand(1);
6614 unsigned NumElems = ResVT.getVectorNumElements();
6615 assert(V1.getValueType() == V2.getValueType() &&
6616 V1.getValueType().getVectorNumElements() == NumElems/2 &&
6617 "Unexpected operands in CONCAT_VECTORS");
6619 if (ResVT.getSizeInBits() >= 16)
6620 return Op; // The operation is legal with KUNPCK
6622 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6623 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6624 SDValue ZeroVec = getZeroVector(ResVT, Subtarget, DAG, dl);
6625 if (IsZeroV1 && IsZeroV2)
6628 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6630 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6632 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ZeroVec, V1, ZeroIdx);
6634 SDValue IdxVal = DAG.getIntPtrConstant(NumElems/2, dl);
6636 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, IdxVal);
6639 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ZeroVec, V2, IdxVal);
6641 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6642 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, V1, V2, IdxVal);
6645 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6646 const X86Subtarget *Subtarget,
6647 SelectionDAG &DAG) {
6648 MVT VT = Op.getSimpleValueType();
6649 if (VT.getVectorElementType() == MVT::i1)
6650 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6652 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6653 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6654 Op.getNumOperands() == 4)));
6656 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6657 // from two other 128-bit ones.
6659 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6660 return LowerAVXCONCAT_VECTORS(Op, DAG);
6663 //===----------------------------------------------------------------------===//
6664 // Vector shuffle lowering
6666 // This is an experimental code path for lowering vector shuffles on x86. It is
6667 // designed to handle arbitrary vector shuffles and blends, gracefully
6668 // degrading performance as necessary. It works hard to recognize idiomatic
6669 // shuffles and lower them to optimal instruction patterns without leaving
6670 // a framework that allows reasonably efficient handling of all vector shuffle
6672 //===----------------------------------------------------------------------===//
6674 /// \brief Tiny helper function to identify a no-op mask.
6676 /// This is a somewhat boring predicate function. It checks whether the mask
6677 /// array input, which is assumed to be a single-input shuffle mask of the kind
6678 /// used by the X86 shuffle instructions (not a fully general
6679 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6680 /// in-place shuffle are 'no-op's.
6681 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6682 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6683 if (Mask[i] != -1 && Mask[i] != i)
6688 /// \brief Helper function to classify a mask as a single-input mask.
6690 /// This isn't a generic single-input test because in the vector shuffle
6691 /// lowering we canonicalize single inputs to be the first input operand. This
6692 /// means we can more quickly test for a single input by only checking whether
6693 /// an input from the second operand exists. We also assume that the size of
6694 /// mask corresponds to the size of the input vectors which isn't true in the
6695 /// fully general case.
6696 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6698 if (M >= (int)Mask.size())
6703 /// \brief Test whether there are elements crossing 128-bit lanes in this
6706 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6707 /// and we routinely test for these.
6708 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6709 int LaneSize = 128 / VT.getScalarSizeInBits();
6710 int Size = Mask.size();
6711 for (int i = 0; i < Size; ++i)
6712 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6717 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6719 /// This checks a shuffle mask to see if it is performing the same
6720 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6721 /// that it is also not lane-crossing. It may however involve a blend from the
6722 /// same lane of a second vector.
6724 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6725 /// non-trivial to compute in the face of undef lanes. The representation is
6726 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6727 /// entries from both V1 and V2 inputs to the wider mask.
6729 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6730 SmallVectorImpl<int> &RepeatedMask) {
6731 int LaneSize = 128 / VT.getScalarSizeInBits();
6732 RepeatedMask.resize(LaneSize, -1);
6733 int Size = Mask.size();
6734 for (int i = 0; i < Size; ++i) {
6737 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6738 // This entry crosses lanes, so there is no way to model this shuffle.
6741 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6742 if (RepeatedMask[i % LaneSize] == -1)
6743 // This is the first non-undef entry in this slot of a 128-bit lane.
6744 RepeatedMask[i % LaneSize] =
6745 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6746 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6747 // Found a mismatch with the repeated mask.
6753 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6756 /// This is a fast way to test a shuffle mask against a fixed pattern:
6758 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6760 /// It returns true if the mask is exactly as wide as the argument list, and
6761 /// each element of the mask is either -1 (signifying undef) or the value given
6762 /// in the argument.
6763 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6764 ArrayRef<int> ExpectedMask) {
6765 if (Mask.size() != ExpectedMask.size())
6768 int Size = Mask.size();
6770 // If the values are build vectors, we can look through them to find
6771 // equivalent inputs that make the shuffles equivalent.
6772 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6773 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6775 for (int i = 0; i < Size; ++i)
6776 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6777 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6778 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6779 if (!MaskBV || !ExpectedBV ||
6780 MaskBV->getOperand(Mask[i] % Size) !=
6781 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6788 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6790 /// This helper function produces an 8-bit shuffle immediate corresponding to
6791 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6792 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6795 /// NB: We rely heavily on "undef" masks preserving the input lane.
6796 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6797 SelectionDAG &DAG) {
6798 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6799 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6800 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6801 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6802 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6805 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6806 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6807 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6808 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6809 return DAG.getConstant(Imm, DL, MVT::i8);
6812 /// \brief Compute whether each element of a shuffle is zeroable.
6814 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6815 /// Either it is an undef element in the shuffle mask, the element of the input
6816 /// referenced is undef, or the element of the input referenced is known to be
6817 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6818 /// as many lanes with this technique as possible to simplify the remaining
6820 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6821 SDValue V1, SDValue V2) {
6822 SmallBitVector Zeroable(Mask.size(), false);
6824 while (V1.getOpcode() == ISD::BITCAST)
6825 V1 = V1->getOperand(0);
6826 while (V2.getOpcode() == ISD::BITCAST)
6827 V2 = V2->getOperand(0);
6829 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6830 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6832 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6834 // Handle the easy cases.
6835 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6840 // If this is an index into a build_vector node (which has the same number
6841 // of elements), dig out the input value and use it.
6842 SDValue V = M < Size ? V1 : V2;
6843 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6846 SDValue Input = V.getOperand(M % Size);
6847 // The UNDEF opcode check really should be dead code here, but not quite
6848 // worth asserting on (it isn't invalid, just unexpected).
6849 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6856 // X86 has dedicated unpack instructions that can handle specific blend
6857 // operations: UNPCKH and UNPCKL.
6858 static SDValue lowerVectorShuffleWithUNPCK(SDLoc DL, MVT VT, ArrayRef<int> Mask,
6859 SDValue V1, SDValue V2,
6860 SelectionDAG &DAG) {
6861 int NumElts = VT.getVectorNumElements();
6862 int NumEltsInLane = 128 / VT.getScalarSizeInBits();
6863 SmallVector<int, 8> Unpckl;
6864 SmallVector<int, 8> Unpckh;
6866 for (int i = 0; i < NumElts; ++i) {
6867 unsigned LaneStart = (i / NumEltsInLane) * NumEltsInLane;
6868 int LoPos = (i % NumEltsInLane) / 2 + LaneStart + NumElts * (i % 2);
6869 int HiPos = LoPos + NumEltsInLane / 2;
6870 Unpckl.push_back(LoPos);
6871 Unpckh.push_back(HiPos);
6874 if (isShuffleEquivalent(V1, V2, Mask, Unpckl))
6875 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
6876 if (isShuffleEquivalent(V1, V2, Mask, Unpckh))
6877 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
6879 // Commute and try again.
6880 ShuffleVectorSDNode::commuteMask(Unpckl);
6881 if (isShuffleEquivalent(V1, V2, Mask, Unpckl))
6882 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V2, V1);
6884 ShuffleVectorSDNode::commuteMask(Unpckh);
6885 if (isShuffleEquivalent(V1, V2, Mask, Unpckh))
6886 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V2, V1);
6891 /// \brief Try to emit a bitmask instruction for a shuffle.
6893 /// This handles cases where we can model a blend exactly as a bitmask due to
6894 /// one of the inputs being zeroable.
6895 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6896 SDValue V2, ArrayRef<int> Mask,
6897 SelectionDAG &DAG) {
6898 MVT EltVT = VT.getVectorElementType();
6899 int NumEltBits = EltVT.getSizeInBits();
6900 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6901 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6902 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6904 if (EltVT.isFloatingPoint()) {
6905 Zero = DAG.getBitcast(EltVT, Zero);
6906 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6908 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6909 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6911 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6914 if (Mask[i] % Size != i)
6915 return SDValue(); // Not a blend.
6917 V = Mask[i] < Size ? V1 : V2;
6918 else if (V != (Mask[i] < Size ? V1 : V2))
6919 return SDValue(); // Can only let one input through the mask.
6921 VMaskOps[i] = AllOnes;
6924 return SDValue(); // No non-zeroable elements!
6926 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6927 V = DAG.getNode(VT.isFloatingPoint()
6928 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6933 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6935 /// This is used as a fallback approach when first class blend instructions are
6936 /// unavailable. Currently it is only suitable for integer vectors, but could
6937 /// be generalized for floating point vectors if desirable.
6938 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6939 SDValue V2, ArrayRef<int> Mask,
6940 SelectionDAG &DAG) {
6941 assert(VT.isInteger() && "Only supports integer vector types!");
6942 MVT EltVT = VT.getVectorElementType();
6943 int NumEltBits = EltVT.getSizeInBits();
6944 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6945 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6947 SmallVector<SDValue, 16> MaskOps;
6948 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6949 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6950 return SDValue(); // Shuffled input!
6951 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6954 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6955 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6956 // We have to cast V2 around.
6957 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6958 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6959 DAG.getBitcast(MaskVT, V1Mask),
6960 DAG.getBitcast(MaskVT, V2)));
6961 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6964 /// \brief Try to emit a blend instruction for a shuffle.
6966 /// This doesn't do any checks for the availability of instructions for blending
6967 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6968 /// be matched in the backend with the type given. What it does check for is
6969 /// that the shuffle mask is a blend, or convertible into a blend with zero.
6970 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6971 SDValue V2, ArrayRef<int> Original,
6972 const X86Subtarget *Subtarget,
6973 SelectionDAG &DAG) {
6974 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6975 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6976 SmallVector<int, 8> Mask(Original.begin(), Original.end());
6977 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6978 bool ForceV1Zero = false, ForceV2Zero = false;
6980 // Attempt to generate the binary blend mask. If an input is zero then
6981 // we can use any lane.
6982 // TODO: generalize the zero matching to any scalar like isShuffleEquivalent.
6983 unsigned BlendMask = 0;
6984 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6990 if (M == i + Size) {
6991 BlendMask |= 1u << i;
7002 BlendMask |= 1u << i;
7007 return SDValue(); // Shuffled input!
7010 // Create a REAL zero vector - ISD::isBuildVectorAllZeros allows UNDEFs.
7012 V1 = getZeroVector(VT, Subtarget, DAG, DL);
7014 V2 = getZeroVector(VT, Subtarget, DAG, DL);
7016 auto ScaleBlendMask = [](unsigned BlendMask, int Size, int Scale) {
7017 unsigned ScaledMask = 0;
7018 for (int i = 0; i != Size; ++i)
7019 if (BlendMask & (1u << i))
7020 for (int j = 0; j != Scale; ++j)
7021 ScaledMask |= 1u << (i * Scale + j);
7025 switch (VT.SimpleTy) {
7030 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7031 DAG.getConstant(BlendMask, DL, MVT::i8));
7035 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7039 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7040 // that instruction.
7041 if (Subtarget->hasAVX2()) {
7042 // Scale the blend by the number of 32-bit dwords per element.
7043 int Scale = VT.getScalarSizeInBits() / 32;
7044 BlendMask = ScaleBlendMask(BlendMask, Mask.size(), Scale);
7045 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7046 V1 = DAG.getBitcast(BlendVT, V1);
7047 V2 = DAG.getBitcast(BlendVT, V2);
7048 return DAG.getBitcast(
7049 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7050 DAG.getConstant(BlendMask, DL, MVT::i8)));
7054 // For integer shuffles we need to expand the mask and cast the inputs to
7055 // v8i16s prior to blending.
7056 int Scale = 8 / VT.getVectorNumElements();
7057 BlendMask = ScaleBlendMask(BlendMask, Mask.size(), Scale);
7058 V1 = DAG.getBitcast(MVT::v8i16, V1);
7059 V2 = DAG.getBitcast(MVT::v8i16, V2);
7060 return DAG.getBitcast(VT,
7061 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7062 DAG.getConstant(BlendMask, DL, MVT::i8)));
7066 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7067 SmallVector<int, 8> RepeatedMask;
7068 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7069 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7070 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7072 for (int i = 0; i < 8; ++i)
7073 if (RepeatedMask[i] >= 16)
7074 BlendMask |= 1u << i;
7075 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7076 DAG.getConstant(BlendMask, DL, MVT::i8));
7082 assert((VT.is128BitVector() || Subtarget->hasAVX2()) &&
7083 "256-bit byte-blends require AVX2 support!");
7085 // Attempt to lower to a bitmask if we can. VPAND is faster than VPBLENDVB.
7086 if (SDValue Masked = lowerVectorShuffleAsBitMask(DL, VT, V1, V2, Mask, DAG))
7089 // Scale the blend by the number of bytes per element.
7090 int Scale = VT.getScalarSizeInBits() / 8;
7092 // This form of blend is always done on bytes. Compute the byte vector
7094 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
7096 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7097 // mix of LLVM's code generator and the x86 backend. We tell the code
7098 // generator that boolean values in the elements of an x86 vector register
7099 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7100 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7101 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7102 // of the element (the remaining are ignored) and 0 in that high bit would
7103 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7104 // the LLVM model for boolean values in vector elements gets the relevant
7105 // bit set, it is set backwards and over constrained relative to x86's
7107 SmallVector<SDValue, 32> VSELECTMask;
7108 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7109 for (int j = 0; j < Scale; ++j)
7110 VSELECTMask.push_back(
7111 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7112 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
7115 V1 = DAG.getBitcast(BlendVT, V1);
7116 V2 = DAG.getBitcast(BlendVT, V2);
7117 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
7118 DAG.getNode(ISD::BUILD_VECTOR, DL,
7119 BlendVT, VSELECTMask),
7124 llvm_unreachable("Not a supported integer vector type!");
7128 /// \brief Try to lower as a blend of elements from two inputs followed by
7129 /// a single-input permutation.
7131 /// This matches the pattern where we can blend elements from two inputs and
7132 /// then reduce the shuffle to a single-input permutation.
7133 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
7136 SelectionDAG &DAG) {
7137 // We build up the blend mask while checking whether a blend is a viable way
7138 // to reduce the shuffle.
7139 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7140 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
7142 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7146 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
7148 if (BlendMask[Mask[i] % Size] == -1)
7149 BlendMask[Mask[i] % Size] = Mask[i];
7150 else if (BlendMask[Mask[i] % Size] != Mask[i])
7151 return SDValue(); // Can't blend in the needed input!
7153 PermuteMask[i] = Mask[i] % Size;
7156 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7157 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
7160 /// \brief Generic routine to decompose a shuffle and blend into indepndent
7161 /// blends and permutes.
7163 /// This matches the extremely common pattern for handling combined
7164 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7165 /// operations. It will try to pick the best arrangement of shuffles and
7167 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7171 SelectionDAG &DAG) {
7172 // Shuffle the input elements into the desired positions in V1 and V2 and
7173 // blend them together.
7174 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7175 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7176 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7177 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7178 if (Mask[i] >= 0 && Mask[i] < Size) {
7179 V1Mask[i] = Mask[i];
7181 } else if (Mask[i] >= Size) {
7182 V2Mask[i] = Mask[i] - Size;
7183 BlendMask[i] = i + Size;
7186 // Try to lower with the simpler initial blend strategy unless one of the
7187 // input shuffles would be a no-op. We prefer to shuffle inputs as the
7188 // shuffle may be able to fold with a load or other benefit. However, when
7189 // we'll have to do 2x as many shuffles in order to achieve this, blending
7190 // first is a better strategy.
7191 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
7192 if (SDValue BlendPerm =
7193 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
7196 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7197 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7198 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7201 /// \brief Try to lower a vector shuffle as a byte rotation.
7203 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7204 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7205 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7206 /// try to generically lower a vector shuffle through such an pattern. It
7207 /// does not check for the profitability of lowering either as PALIGNR or
7208 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7209 /// This matches shuffle vectors that look like:
7211 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7213 /// Essentially it concatenates V1 and V2, shifts right by some number of
7214 /// elements, and takes the low elements as the result. Note that while this is
7215 /// specified as a *right shift* because x86 is little-endian, it is a *left
7216 /// rotate* of the vector lanes.
7217 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7220 const X86Subtarget *Subtarget,
7221 SelectionDAG &DAG) {
7222 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7224 int NumElts = Mask.size();
7225 int NumLanes = VT.getSizeInBits() / 128;
7226 int NumLaneElts = NumElts / NumLanes;
7228 // We need to detect various ways of spelling a rotation:
7229 // [11, 12, 13, 14, 15, 0, 1, 2]
7230 // [-1, 12, 13, 14, -1, -1, 1, -1]
7231 // [-1, -1, -1, -1, -1, -1, 1, 2]
7232 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7233 // [-1, 4, 5, 6, -1, -1, 9, -1]
7234 // [-1, 4, 5, 6, -1, -1, -1, -1]
7237 for (int l = 0; l < NumElts; l += NumLaneElts) {
7238 for (int i = 0; i < NumLaneElts; ++i) {
7239 if (Mask[l + i] == -1)
7241 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
7243 // Get the mod-Size index and lane correct it.
7244 int LaneIdx = (Mask[l + i] % NumElts) - l;
7245 // Make sure it was in this lane.
7246 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
7249 // Determine where a rotated vector would have started.
7250 int StartIdx = i - LaneIdx;
7252 // The identity rotation isn't interesting, stop.
7255 // If we found the tail of a vector the rotation must be the missing
7256 // front. If we found the head of a vector, it must be how much of the
7258 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
7261 Rotation = CandidateRotation;
7262 else if (Rotation != CandidateRotation)
7263 // The rotations don't match, so we can't match this mask.
7266 // Compute which value this mask is pointing at.
7267 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
7269 // Compute which of the two target values this index should be assigned
7270 // to. This reflects whether the high elements are remaining or the low
7271 // elements are remaining.
7272 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7274 // Either set up this value if we've not encountered it before, or check
7275 // that it remains consistent.
7278 else if (TargetV != MaskV)
7279 // This may be a rotation, but it pulls from the inputs in some
7280 // unsupported interleaving.
7285 // Check that we successfully analyzed the mask, and normalize the results.
7286 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7287 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7293 // The actual rotate instruction rotates bytes, so we need to scale the
7294 // rotation based on how many bytes are in the vector lane.
7295 int Scale = 16 / NumLaneElts;
7297 // SSSE3 targets can use the palignr instruction.
7298 if (Subtarget->hasSSSE3()) {
7299 // Cast the inputs to i8 vector of correct length to match PALIGNR.
7300 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
7301 Lo = DAG.getBitcast(AlignVT, Lo);
7302 Hi = DAG.getBitcast(AlignVT, Hi);
7304 return DAG.getBitcast(
7305 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Lo, Hi,
7306 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
7309 assert(VT.is128BitVector() &&
7310 "Rotate-based lowering only supports 128-bit lowering!");
7311 assert(Mask.size() <= 16 &&
7312 "Can shuffle at most 16 bytes in a 128-bit vector!");
7314 // Default SSE2 implementation
7315 int LoByteShift = 16 - Rotation * Scale;
7316 int HiByteShift = Rotation * Scale;
7318 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7319 Lo = DAG.getBitcast(MVT::v2i64, Lo);
7320 Hi = DAG.getBitcast(MVT::v2i64, Hi);
7322 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7323 DAG.getConstant(LoByteShift, DL, MVT::i8));
7324 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7325 DAG.getConstant(HiByteShift, DL, MVT::i8));
7326 return DAG.getBitcast(VT,
7327 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7330 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
7332 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
7333 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
7334 /// matches elements from one of the input vectors shuffled to the left or
7335 /// right with zeroable elements 'shifted in'. It handles both the strictly
7336 /// bit-wise element shifts and the byte shift across an entire 128-bit double
7339 /// PSHL : (little-endian) left bit shift.
7340 /// [ zz, 0, zz, 2 ]
7341 /// [ -1, 4, zz, -1 ]
7342 /// PSRL : (little-endian) right bit shift.
7344 /// [ -1, -1, 7, zz]
7345 /// PSLLDQ : (little-endian) left byte shift
7346 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
7347 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
7348 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
7349 /// PSRLDQ : (little-endian) right byte shift
7350 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
7351 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
7352 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
7353 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
7354 SDValue V2, ArrayRef<int> Mask,
7355 SelectionDAG &DAG) {
7356 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7358 int Size = Mask.size();
7359 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7361 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
7362 for (int i = 0; i < Size; i += Scale)
7363 for (int j = 0; j < Shift; ++j)
7364 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
7370 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
7371 for (int i = 0; i != Size; i += Scale) {
7372 unsigned Pos = Left ? i + Shift : i;
7373 unsigned Low = Left ? i : i + Shift;
7374 unsigned Len = Scale - Shift;
7375 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
7376 Low + (V == V1 ? 0 : Size)))
7380 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
7381 bool ByteShift = ShiftEltBits > 64;
7382 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
7383 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
7384 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
7386 // Normalize the scale for byte shifts to still produce an i64 element
7388 Scale = ByteShift ? Scale / 2 : Scale;
7390 // We need to round trip through the appropriate type for the shift.
7391 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
7392 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
7393 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
7394 "Illegal integer vector type");
7395 V = DAG.getBitcast(ShiftVT, V);
7397 V = DAG.getNode(OpCode, DL, ShiftVT, V,
7398 DAG.getConstant(ShiftAmt, DL, MVT::i8));
7399 return DAG.getBitcast(VT, V);
7402 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
7403 // keep doubling the size of the integer elements up to that. We can
7404 // then shift the elements of the integer vector by whole multiples of
7405 // their width within the elements of the larger integer vector. Test each
7406 // multiple to see if we can find a match with the moved element indices
7407 // and that the shifted in elements are all zeroable.
7408 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
7409 for (int Shift = 1; Shift != Scale; ++Shift)
7410 for (bool Left : {true, false})
7411 if (CheckZeros(Shift, Scale, Left))
7412 for (SDValue V : {V1, V2})
7413 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
7420 /// \brief Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ.
7421 static SDValue lowerVectorShuffleWithSSE4A(SDLoc DL, MVT VT, SDValue V1,
7422 SDValue V2, ArrayRef<int> Mask,
7423 SelectionDAG &DAG) {
7424 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7425 assert(!Zeroable.all() && "Fully zeroable shuffle mask");
7427 int Size = Mask.size();
7428 int HalfSize = Size / 2;
7429 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7431 // Upper half must be undefined.
7432 if (!isUndefInRange(Mask, HalfSize, HalfSize))
7435 // EXTRQ: Extract Len elements from lower half of source, starting at Idx.
7436 // Remainder of lower half result is zero and upper half is all undef.
7437 auto LowerAsEXTRQ = [&]() {
7438 // Determine the extraction length from the part of the
7439 // lower half that isn't zeroable.
7441 for (; Len > 0; --Len)
7442 if (!Zeroable[Len - 1])
7444 assert(Len > 0 && "Zeroable shuffle mask");
7446 // Attempt to match first Len sequential elements from the lower half.
7449 for (int i = 0; i != Len; ++i) {
7453 SDValue &V = (M < Size ? V1 : V2);
7456 // The extracted elements must start at a valid index and all mask
7457 // elements must be in the lower half.
7458 if (i > M || M >= HalfSize)
7461 if (Idx < 0 || (Src == V && Idx == (M - i))) {
7472 assert((Idx + Len) <= HalfSize && "Illegal extraction mask");
7473 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7474 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7475 return DAG.getNode(X86ISD::EXTRQI, DL, VT, Src,
7476 DAG.getConstant(BitLen, DL, MVT::i8),
7477 DAG.getConstant(BitIdx, DL, MVT::i8));
7480 if (SDValue ExtrQ = LowerAsEXTRQ())
7483 // INSERTQ: Extract lowest Len elements from lower half of second source and
7484 // insert over first source, starting at Idx.
7485 // { A[0], .., A[Idx-1], B[0], .., B[Len-1], A[Idx+Len], .., UNDEF, ... }
7486 auto LowerAsInsertQ = [&]() {
7487 for (int Idx = 0; Idx != HalfSize; ++Idx) {
7490 // Attempt to match first source from mask before insertion point.
7491 if (isUndefInRange(Mask, 0, Idx)) {
7493 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, 0)) {
7495 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, Size)) {
7501 // Extend the extraction length looking to match both the insertion of
7502 // the second source and the remaining elements of the first.
7503 for (int Hi = Idx + 1; Hi <= HalfSize; ++Hi) {
7508 if (isSequentialOrUndefInRange(Mask, Idx, Len, 0)) {
7510 } else if (isSequentialOrUndefInRange(Mask, Idx, Len, Size)) {
7516 // Match the remaining elements of the lower half.
7517 if (isUndefInRange(Mask, Hi, HalfSize - Hi)) {
7519 } else if ((!Base || (Base == V1)) &&
7520 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi, Hi)) {
7522 } else if ((!Base || (Base == V2)) &&
7523 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi,
7530 // We may not have a base (first source) - this can safely be undefined.
7532 Base = DAG.getUNDEF(VT);
7534 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7535 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7536 return DAG.getNode(X86ISD::INSERTQI, DL, VT, Base, Insert,
7537 DAG.getConstant(BitLen, DL, MVT::i8),
7538 DAG.getConstant(BitIdx, DL, MVT::i8));
7545 if (SDValue InsertQ = LowerAsInsertQ())
7551 /// \brief Lower a vector shuffle as a zero or any extension.
7553 /// Given a specific number of elements, element bit width, and extension
7554 /// stride, produce either a zero or any extension based on the available
7555 /// features of the subtarget. The extended elements are consecutive and
7556 /// begin and can start from an offseted element index in the input; to
7557 /// avoid excess shuffling the offset must either being in the bottom lane
7558 /// or at the start of a higher lane. All extended elements must be from
7560 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7561 SDLoc DL, MVT VT, int Scale, int Offset, bool AnyExt, SDValue InputV,
7562 ArrayRef<int> Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7563 assert(Scale > 1 && "Need a scale to extend.");
7564 int EltBits = VT.getScalarSizeInBits();
7565 int NumElements = VT.getVectorNumElements();
7566 int NumEltsPerLane = 128 / EltBits;
7567 int OffsetLane = Offset / NumEltsPerLane;
7568 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7569 "Only 8, 16, and 32 bit elements can be extended.");
7570 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7571 assert(0 <= Offset && "Extension offset must be positive.");
7572 assert((Offset < NumEltsPerLane || Offset % NumEltsPerLane == 0) &&
7573 "Extension offset must be in the first lane or start an upper lane.");
7575 // Check that an index is in same lane as the base offset.
7576 auto SafeOffset = [&](int Idx) {
7577 return OffsetLane == (Idx / NumEltsPerLane);
7580 // Shift along an input so that the offset base moves to the first element.
7581 auto ShuffleOffset = [&](SDValue V) {
7585 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7586 for (int i = 0; i * Scale < NumElements; ++i) {
7587 int SrcIdx = i + Offset;
7588 ShMask[i] = SafeOffset(SrcIdx) ? SrcIdx : -1;
7590 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), ShMask);
7593 // Found a valid zext mask! Try various lowering strategies based on the
7594 // input type and available ISA extensions.
7595 if (Subtarget->hasSSE41()) {
7596 // Not worth offseting 128-bit vectors if scale == 2, a pattern using
7597 // PUNPCK will catch this in a later shuffle match.
7598 if (Offset && Scale == 2 && VT.is128BitVector())
7600 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7601 NumElements / Scale);
7602 InputV = DAG.getNode(X86ISD::VZEXT, DL, ExtVT, ShuffleOffset(InputV));
7603 return DAG.getBitcast(VT, InputV);
7606 assert(VT.is128BitVector() && "Only 128-bit vectors can be extended.");
7608 // For any extends we can cheat for larger element sizes and use shuffle
7609 // instructions that can fold with a load and/or copy.
7610 if (AnyExt && EltBits == 32) {
7611 int PSHUFDMask[4] = {Offset, -1, SafeOffset(Offset + 1) ? Offset + 1 : -1,
7613 return DAG.getBitcast(
7614 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7615 DAG.getBitcast(MVT::v4i32, InputV),
7616 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
7618 if (AnyExt && EltBits == 16 && Scale > 2) {
7619 int PSHUFDMask[4] = {Offset / 2, -1,
7620 SafeOffset(Offset + 1) ? (Offset + 1) / 2 : -1, -1};
7621 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7622 DAG.getBitcast(MVT::v4i32, InputV),
7623 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
7624 int PSHUFWMask[4] = {1, -1, -1, -1};
7625 unsigned OddEvenOp = (Offset & 1 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW);
7626 return DAG.getBitcast(
7627 VT, DAG.getNode(OddEvenOp, DL, MVT::v8i16,
7628 DAG.getBitcast(MVT::v8i16, InputV),
7629 getV4X86ShuffleImm8ForMask(PSHUFWMask, DL, DAG)));
7632 // The SSE4A EXTRQ instruction can efficiently extend the first 2 lanes
7634 if ((Scale * EltBits) == 64 && EltBits < 32 && Subtarget->hasSSE4A()) {
7635 assert(NumElements == (int)Mask.size() && "Unexpected shuffle mask size!");
7636 assert(VT.is128BitVector() && "Unexpected vector width!");
7638 int LoIdx = Offset * EltBits;
7639 SDValue Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7640 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7641 DAG.getConstant(EltBits, DL, MVT::i8),
7642 DAG.getConstant(LoIdx, DL, MVT::i8)));
7644 if (isUndefInRange(Mask, NumElements / 2, NumElements / 2) ||
7645 !SafeOffset(Offset + 1))
7646 return DAG.getNode(ISD::BITCAST, DL, VT, Lo);
7648 int HiIdx = (Offset + 1) * EltBits;
7649 SDValue Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7650 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7651 DAG.getConstant(EltBits, DL, MVT::i8),
7652 DAG.getConstant(HiIdx, DL, MVT::i8)));
7653 return DAG.getNode(ISD::BITCAST, DL, VT,
7654 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));
7657 // If this would require more than 2 unpack instructions to expand, use
7658 // pshufb when available. We can only use more than 2 unpack instructions
7659 // when zero extending i8 elements which also makes it easier to use pshufb.
7660 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7661 assert(NumElements == 16 && "Unexpected byte vector width!");
7662 SDValue PSHUFBMask[16];
7663 for (int i = 0; i < 16; ++i) {
7664 int Idx = Offset + (i / Scale);
7665 PSHUFBMask[i] = DAG.getConstant(
7666 (i % Scale == 0 && SafeOffset(Idx)) ? Idx : 0x80, DL, MVT::i8);
7668 InputV = DAG.getBitcast(MVT::v16i8, InputV);
7669 return DAG.getBitcast(VT,
7670 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7671 DAG.getNode(ISD::BUILD_VECTOR, DL,
7672 MVT::v16i8, PSHUFBMask)));
7675 // If we are extending from an offset, ensure we start on a boundary that
7676 // we can unpack from.
7677 int AlignToUnpack = Offset % (NumElements / Scale);
7678 if (AlignToUnpack) {
7679 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7680 for (int i = AlignToUnpack; i < NumElements; ++i)
7681 ShMask[i - AlignToUnpack] = i;
7682 InputV = DAG.getVectorShuffle(VT, DL, InputV, DAG.getUNDEF(VT), ShMask);
7683 Offset -= AlignToUnpack;
7686 // Otherwise emit a sequence of unpacks.
7688 unsigned UnpackLoHi = X86ISD::UNPCKL;
7689 if (Offset >= (NumElements / 2)) {
7690 UnpackLoHi = X86ISD::UNPCKH;
7691 Offset -= (NumElements / 2);
7694 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7695 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7696 : getZeroVector(InputVT, Subtarget, DAG, DL);
7697 InputV = DAG.getBitcast(InputVT, InputV);
7698 InputV = DAG.getNode(UnpackLoHi, DL, InputVT, InputV, Ext);
7702 } while (Scale > 1);
7703 return DAG.getBitcast(VT, InputV);
7706 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
7708 /// This routine will try to do everything in its power to cleverly lower
7709 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7710 /// check for the profitability of this lowering, it tries to aggressively
7711 /// match this pattern. It will use all of the micro-architectural details it
7712 /// can to emit an efficient lowering. It handles both blends with all-zero
7713 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7714 /// masking out later).
7716 /// The reason we have dedicated lowering for zext-style shuffles is that they
7717 /// are both incredibly common and often quite performance sensitive.
7718 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7719 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7720 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7721 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7723 int Bits = VT.getSizeInBits();
7724 int NumLanes = Bits / 128;
7725 int NumElements = VT.getVectorNumElements();
7726 int NumEltsPerLane = NumElements / NumLanes;
7727 assert(VT.getScalarSizeInBits() <= 32 &&
7728 "Exceeds 32-bit integer zero extension limit");
7729 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7731 // Define a helper function to check a particular ext-scale and lower to it if
7733 auto Lower = [&](int Scale) -> SDValue {
7738 for (int i = 0; i < NumElements; ++i) {
7741 continue; // Valid anywhere but doesn't tell us anything.
7742 if (i % Scale != 0) {
7743 // Each of the extended elements need to be zeroable.
7747 // We no longer are in the anyext case.
7752 // Each of the base elements needs to be consecutive indices into the
7753 // same input vector.
7754 SDValue V = M < NumElements ? V1 : V2;
7755 M = M % NumElements;
7758 Offset = M - (i / Scale);
7759 } else if (InputV != V)
7760 return SDValue(); // Flip-flopping inputs.
7762 // Offset must start in the lowest 128-bit lane or at the start of an
7764 // FIXME: Is it ever worth allowing a negative base offset?
7765 if (!((0 <= Offset && Offset < NumEltsPerLane) ||
7766 (Offset % NumEltsPerLane) == 0))
7769 // If we are offsetting, all referenced entries must come from the same
7771 if (Offset && (Offset / NumEltsPerLane) != (M / NumEltsPerLane))
7774 if ((M % NumElements) != (Offset + (i / Scale)))
7775 return SDValue(); // Non-consecutive strided elements.
7779 // If we fail to find an input, we have a zero-shuffle which should always
7780 // have already been handled.
7781 // FIXME: Maybe handle this here in case during blending we end up with one?
7785 // If we are offsetting, don't extend if we only match a single input, we
7786 // can always do better by using a basic PSHUF or PUNPCK.
7787 if (Offset != 0 && Matches < 2)
7790 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7791 DL, VT, Scale, Offset, AnyExt, InputV, Mask, Subtarget, DAG);
7794 // The widest scale possible for extending is to a 64-bit integer.
7795 assert(Bits % 64 == 0 &&
7796 "The number of bits in a vector must be divisible by 64 on x86!");
7797 int NumExtElements = Bits / 64;
7799 // Each iteration, try extending the elements half as much, but into twice as
7801 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7802 assert(NumElements % NumExtElements == 0 &&
7803 "The input vector size must be divisible by the extended size.");
7804 if (SDValue V = Lower(NumElements / NumExtElements))
7808 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7812 // Returns one of the source operands if the shuffle can be reduced to a
7813 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7814 auto CanZExtLowHalf = [&]() {
7815 for (int i = NumElements / 2; i != NumElements; ++i)
7818 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7820 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7825 if (SDValue V = CanZExtLowHalf()) {
7826 V = DAG.getBitcast(MVT::v2i64, V);
7827 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7828 return DAG.getBitcast(VT, V);
7831 // No viable ext lowering found.
7835 /// \brief Try to get a scalar value for a specific element of a vector.
7837 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7838 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7839 SelectionDAG &DAG) {
7840 MVT VT = V.getSimpleValueType();
7841 MVT EltVT = VT.getVectorElementType();
7842 while (V.getOpcode() == ISD::BITCAST)
7843 V = V.getOperand(0);
7844 // If the bitcasts shift the element size, we can't extract an equivalent
7846 MVT NewVT = V.getSimpleValueType();
7847 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7850 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7851 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7852 // Ensure the scalar operand is the same size as the destination.
7853 // FIXME: Add support for scalar truncation where possible.
7854 SDValue S = V.getOperand(Idx);
7855 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7856 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7862 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7864 /// This is particularly important because the set of instructions varies
7865 /// significantly based on whether the operand is a load or not.
7866 static bool isShuffleFoldableLoad(SDValue V) {
7867 while (V.getOpcode() == ISD::BITCAST)
7868 V = V.getOperand(0);
7870 return ISD::isNON_EXTLoad(V.getNode());
7873 /// \brief Try to lower insertion of a single element into a zero vector.
7875 /// This is a common pattern that we have especially efficient patterns to lower
7876 /// across all subtarget feature sets.
7877 static SDValue lowerVectorShuffleAsElementInsertion(
7878 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7879 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7880 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7882 MVT EltVT = VT.getVectorElementType();
7884 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7885 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7887 bool IsV1Zeroable = true;
7888 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7889 if (i != V2Index && !Zeroable[i]) {
7890 IsV1Zeroable = false;
7894 // Check for a single input from a SCALAR_TO_VECTOR node.
7895 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7896 // all the smarts here sunk into that routine. However, the current
7897 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7898 // vector shuffle lowering is dead.
7899 SDValue V2S = getScalarValueForVectorElement(V2, Mask[V2Index] - Mask.size(),
7901 if (V2S && DAG.getTargetLoweringInfo().isTypeLegal(V2S.getValueType())) {
7902 // We need to zext the scalar if it is smaller than an i32.
7903 V2S = DAG.getBitcast(EltVT, V2S);
7904 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7905 // Using zext to expand a narrow element won't work for non-zero
7910 // Zero-extend directly to i32.
7912 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7914 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7915 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7916 EltVT == MVT::i16) {
7917 // Either not inserting from the low element of the input or the input
7918 // element size is too small to use VZEXT_MOVL to clear the high bits.
7922 if (!IsV1Zeroable) {
7923 // If V1 can't be treated as a zero vector we have fewer options to lower
7924 // this. We can't support integer vectors or non-zero targets cheaply, and
7925 // the V1 elements can't be permuted in any way.
7926 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7927 if (!VT.isFloatingPoint() || V2Index != 0)
7929 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7930 V1Mask[V2Index] = -1;
7931 if (!isNoopShuffleMask(V1Mask))
7933 // This is essentially a special case blend operation, but if we have
7934 // general purpose blend operations, they are always faster. Bail and let
7935 // the rest of the lowering handle these as blends.
7936 if (Subtarget->hasSSE41())
7939 // Otherwise, use MOVSD or MOVSS.
7940 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7941 "Only two types of floating point element types to handle!");
7942 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7946 // This lowering only works for the low element with floating point vectors.
7947 if (VT.isFloatingPoint() && V2Index != 0)
7950 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7952 V2 = DAG.getBitcast(VT, V2);
7955 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7956 // the desired position. Otherwise it is more efficient to do a vector
7957 // shift left. We know that we can do a vector shift left because all
7958 // the inputs are zero.
7959 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7960 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7961 V2Shuffle[V2Index] = 0;
7962 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7964 V2 = DAG.getBitcast(MVT::v2i64, V2);
7966 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7967 DAG.getConstant(V2Index * EltVT.getSizeInBits() / 8, DL,
7968 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(
7969 DAG.getDataLayout(), VT)));
7970 V2 = DAG.getBitcast(VT, V2);
7976 /// \brief Try to lower broadcast of a single - truncated - integer element,
7977 /// coming from a scalar_to_vector/build_vector node \p V0 with larger elements.
7979 /// This assumes we have AVX2.
7980 static SDValue lowerVectorShuffleAsTruncBroadcast(SDLoc DL, MVT VT, SDValue V0,
7982 const X86Subtarget *Subtarget,
7983 SelectionDAG &DAG) {
7984 assert(Subtarget->hasAVX2() &&
7985 "We can only lower integer broadcasts with AVX2!");
7987 EVT EltVT = VT.getVectorElementType();
7988 EVT V0VT = V0.getValueType();
7990 assert(VT.isInteger() && "Unexpected non-integer trunc broadcast!");
7991 assert(V0VT.isVector() && "Unexpected non-vector vector-sized value!");
7993 EVT V0EltVT = V0VT.getVectorElementType();
7994 if (!V0EltVT.isInteger())
7997 const unsigned EltSize = EltVT.getSizeInBits();
7998 const unsigned V0EltSize = V0EltVT.getSizeInBits();
8000 // This is only a truncation if the original element type is larger.
8001 if (V0EltSize <= EltSize)
8004 assert(((V0EltSize % EltSize) == 0) &&
8005 "Scalar type sizes must all be powers of 2 on x86!");
8007 const unsigned V0Opc = V0.getOpcode();
8008 const unsigned Scale = V0EltSize / EltSize;
8009 const unsigned V0BroadcastIdx = BroadcastIdx / Scale;
8011 if ((V0Opc != ISD::SCALAR_TO_VECTOR || V0BroadcastIdx != 0) &&
8012 V0Opc != ISD::BUILD_VECTOR)
8015 SDValue Scalar = V0.getOperand(V0BroadcastIdx);
8017 // If we're extracting non-least-significant bits, shift so we can truncate.
8018 // Hopefully, we can fold away the trunc/srl/load into the broadcast.
8019 // Even if we can't (and !isShuffleFoldableLoad(Scalar)), prefer
8020 // vpbroadcast+vmovd+shr to vpshufb(m)+vmovd.
8021 if (const int OffsetIdx = BroadcastIdx % Scale)
8022 Scalar = DAG.getNode(ISD::SRL, DL, Scalar.getValueType(), Scalar,
8023 DAG.getConstant(OffsetIdx * EltSize, DL, Scalar.getValueType()));
8025 return DAG.getNode(X86ISD::VBROADCAST, DL, VT,
8026 DAG.getNode(ISD::TRUNCATE, DL, EltVT, Scalar));
8029 /// \brief Try to lower broadcast of a single element.
8031 /// For convenience, this code also bundles all of the subtarget feature set
8032 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8033 /// a convenient way to factor it out.
8034 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
8036 const X86Subtarget *Subtarget,
8037 SelectionDAG &DAG) {
8038 if (!Subtarget->hasAVX())
8040 if (VT.isInteger() && !Subtarget->hasAVX2())
8043 // Check that the mask is a broadcast.
8044 int BroadcastIdx = -1;
8046 if (M >= 0 && BroadcastIdx == -1)
8048 else if (M >= 0 && M != BroadcastIdx)
8051 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8052 "a sorted mask where the broadcast "
8055 // Go up the chain of (vector) values to find a scalar load that we can
8056 // combine with the broadcast.
8058 switch (V.getOpcode()) {
8059 case ISD::CONCAT_VECTORS: {
8060 int OperandSize = Mask.size() / V.getNumOperands();
8061 V = V.getOperand(BroadcastIdx / OperandSize);
8062 BroadcastIdx %= OperandSize;
8066 case ISD::INSERT_SUBVECTOR: {
8067 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8068 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8072 int BeginIdx = (int)ConstantIdx->getZExtValue();
8074 BeginIdx + (int)VInner.getSimpleValueType().getVectorNumElements();
8075 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8076 BroadcastIdx -= BeginIdx;
8087 // Check if this is a broadcast of a scalar. We special case lowering
8088 // for scalars so that we can more effectively fold with loads.
8089 // First, look through bitcast: if the original value has a larger element
8090 // type than the shuffle, the broadcast element is in essence truncated.
8091 // Make that explicit to ease folding.
8092 if (V.getOpcode() == ISD::BITCAST && VT.isInteger())
8093 if (SDValue TruncBroadcast = lowerVectorShuffleAsTruncBroadcast(
8094 DL, VT, V.getOperand(0), BroadcastIdx, Subtarget, DAG))
8095 return TruncBroadcast;
8097 // Also check the simpler case, where we can directly reuse the scalar.
8098 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8099 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8100 V = V.getOperand(BroadcastIdx);
8102 // If the scalar isn't a load, we can't broadcast from it in AVX1.
8103 // Only AVX2 has register broadcasts.
8104 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8106 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8107 // We can't broadcast from a vector register without AVX2, and we can only
8108 // broadcast from the zero-element of a vector register.
8112 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8115 // Check for whether we can use INSERTPS to perform the shuffle. We only use
8116 // INSERTPS when the V1 elements are already in the correct locations
8117 // because otherwise we can just always use two SHUFPS instructions which
8118 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
8119 // perform INSERTPS if a single V1 element is out of place and all V2
8120 // elements are zeroable.
8121 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
8123 SelectionDAG &DAG) {
8124 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8125 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8126 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8127 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8129 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8132 int V1DstIndex = -1;
8133 int V2DstIndex = -1;
8134 bool V1UsedInPlace = false;
8136 for (int i = 0; i < 4; ++i) {
8137 // Synthesize a zero mask from the zeroable elements (includes undefs).
8143 // Flag if we use any V1 inputs in place.
8145 V1UsedInPlace = true;
8149 // We can only insert a single non-zeroable element.
8150 if (V1DstIndex != -1 || V2DstIndex != -1)
8154 // V1 input out of place for insertion.
8157 // V2 input for insertion.
8162 // Don't bother if we have no (non-zeroable) element for insertion.
8163 if (V1DstIndex == -1 && V2DstIndex == -1)
8166 // Determine element insertion src/dst indices. The src index is from the
8167 // start of the inserted vector, not the start of the concatenated vector.
8168 unsigned V2SrcIndex = 0;
8169 if (V1DstIndex != -1) {
8170 // If we have a V1 input out of place, we use V1 as the V2 element insertion
8171 // and don't use the original V2 at all.
8172 V2SrcIndex = Mask[V1DstIndex];
8173 V2DstIndex = V1DstIndex;
8176 V2SrcIndex = Mask[V2DstIndex] - 4;
8179 // If no V1 inputs are used in place, then the result is created only from
8180 // the zero mask and the V2 insertion - so remove V1 dependency.
8182 V1 = DAG.getUNDEF(MVT::v4f32);
8184 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
8185 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8187 // Insert the V2 element into the desired position.
8189 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8190 DAG.getConstant(InsertPSMask, DL, MVT::i8));
8193 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
8194 /// UNPCK instruction.
8196 /// This specifically targets cases where we end up with alternating between
8197 /// the two inputs, and so can permute them into something that feeds a single
8198 /// UNPCK instruction. Note that this routine only targets integer vectors
8199 /// because for floating point vectors we have a generalized SHUFPS lowering
8200 /// strategy that handles everything that doesn't *exactly* match an unpack,
8201 /// making this clever lowering unnecessary.
8202 static SDValue lowerVectorShuffleAsPermuteAndUnpack(SDLoc DL, MVT VT,
8203 SDValue V1, SDValue V2,
8205 SelectionDAG &DAG) {
8206 assert(!VT.isFloatingPoint() &&
8207 "This routine only supports integer vectors.");
8208 assert(!isSingleInputShuffleMask(Mask) &&
8209 "This routine should only be used when blending two inputs.");
8210 assert(Mask.size() >= 2 && "Single element masks are invalid.");
8212 int Size = Mask.size();
8214 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
8215 return M >= 0 && M % Size < Size / 2;
8217 int NumHiInputs = std::count_if(
8218 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
8220 bool UnpackLo = NumLoInputs >= NumHiInputs;
8222 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
8223 SmallVector<int, 32> V1Mask(Mask.size(), -1);
8224 SmallVector<int, 32> V2Mask(Mask.size(), -1);
8226 for (int i = 0; i < Size; ++i) {
8230 // Each element of the unpack contains Scale elements from this mask.
8231 int UnpackIdx = i / Scale;
8233 // We only handle the case where V1 feeds the first slots of the unpack.
8234 // We rely on canonicalization to ensure this is the case.
8235 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
8238 // Setup the mask for this input. The indexing is tricky as we have to
8239 // handle the unpack stride.
8240 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
8241 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
8245 // If we will have to shuffle both inputs to use the unpack, check whether
8246 // we can just unpack first and shuffle the result. If so, skip this unpack.
8247 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
8248 !isNoopShuffleMask(V2Mask))
8251 // Shuffle the inputs into place.
8252 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
8253 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
8255 // Cast the inputs to the type we will use to unpack them.
8256 V1 = DAG.getBitcast(UnpackVT, V1);
8257 V2 = DAG.getBitcast(UnpackVT, V2);
8259 // Unpack the inputs and cast the result back to the desired type.
8260 return DAG.getBitcast(
8261 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8265 // We try each unpack from the largest to the smallest to try and find one
8266 // that fits this mask.
8267 int OrigNumElements = VT.getVectorNumElements();
8268 int OrigScalarSize = VT.getScalarSizeInBits();
8269 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
8270 int Scale = ScalarSize / OrigScalarSize;
8271 int NumElements = OrigNumElements / Scale;
8272 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
8273 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
8277 // If none of the unpack-rooted lowerings worked (or were profitable) try an
8279 if (NumLoInputs == 0 || NumHiInputs == 0) {
8280 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
8281 "We have to have *some* inputs!");
8282 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
8284 // FIXME: We could consider the total complexity of the permute of each
8285 // possible unpacking. Or at the least we should consider how many
8286 // half-crossings are created.
8287 // FIXME: We could consider commuting the unpacks.
8289 SmallVector<int, 32> PermMask;
8290 PermMask.assign(Size, -1);
8291 for (int i = 0; i < Size; ++i) {
8295 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
8298 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
8300 return DAG.getVectorShuffle(
8301 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
8303 DAG.getUNDEF(VT), PermMask);
8309 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8311 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8312 /// support for floating point shuffles but not integer shuffles. These
8313 /// instructions will incur a domain crossing penalty on some chips though so
8314 /// it is better to avoid lowering through this for integer vectors where
8316 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8317 const X86Subtarget *Subtarget,
8318 SelectionDAG &DAG) {
8320 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8321 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8322 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8323 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8324 ArrayRef<int> Mask = SVOp->getMask();
8325 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8327 if (isSingleInputShuffleMask(Mask)) {
8328 // Use low duplicate instructions for masks that match their pattern.
8329 if (Subtarget->hasSSE3())
8330 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
8331 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
8333 // Straight shuffle of a single input vector. Simulate this by using the
8334 // single input as both of the "inputs" to this instruction..
8335 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8337 if (Subtarget->hasAVX()) {
8338 // If we have AVX, we can use VPERMILPS which will allow folding a load
8339 // into the shuffle.
8340 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8341 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8344 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
8345 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8347 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8348 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8350 // If we have a single input, insert that into V1 if we can do so cheaply.
8351 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8352 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8353 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
8355 // Try inverting the insertion since for v2 masks it is easy to do and we
8356 // can't reliably sort the mask one way or the other.
8357 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8358 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8359 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8360 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
8364 // Try to use one of the special instruction patterns to handle two common
8365 // blend patterns if a zero-blend above didn't work.
8366 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
8367 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8368 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8369 // We can either use a special instruction to load over the low double or
8370 // to move just the low double.
8372 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8374 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8376 if (Subtarget->hasSSE41())
8377 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8381 // Use dedicated unpack instructions for masks that match their pattern.
8383 lowerVectorShuffleWithUNPCK(DL, MVT::v2f64, Mask, V1, V2, DAG))
8386 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8387 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
8388 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8391 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8393 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8394 /// the integer unit to minimize domain crossing penalties. However, for blends
8395 /// it falls back to the floating point shuffle operation with appropriate bit
8397 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8398 const X86Subtarget *Subtarget,
8399 SelectionDAG &DAG) {
8401 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8402 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8403 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8404 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8405 ArrayRef<int> Mask = SVOp->getMask();
8406 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8408 if (isSingleInputShuffleMask(Mask)) {
8409 // Check for being able to broadcast a single element.
8410 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
8411 Mask, Subtarget, DAG))
8414 // Straight shuffle of a single input vector. For everything from SSE2
8415 // onward this has a single fast instruction with no scary immediates.
8416 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8417 V1 = DAG.getBitcast(MVT::v4i32, V1);
8418 int WidenedMask[4] = {
8419 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8420 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8421 return DAG.getBitcast(
8423 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8424 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
8426 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
8427 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
8428 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
8429 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
8431 // If we have a blend of two PACKUS operations an the blend aligns with the
8432 // low and half halves, we can just merge the PACKUS operations. This is
8433 // particularly important as it lets us merge shuffles that this routine itself
8435 auto GetPackNode = [](SDValue V) {
8436 while (V.getOpcode() == ISD::BITCAST)
8437 V = V.getOperand(0);
8439 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
8441 if (SDValue V1Pack = GetPackNode(V1))
8442 if (SDValue V2Pack = GetPackNode(V2))
8443 return DAG.getBitcast(MVT::v2i64,
8444 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
8445 Mask[0] == 0 ? V1Pack.getOperand(0)
8446 : V1Pack.getOperand(1),
8447 Mask[1] == 2 ? V2Pack.getOperand(0)
8448 : V2Pack.getOperand(1)));
8450 // Try to use shift instructions.
8452 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
8455 // When loading a scalar and then shuffling it into a vector we can often do
8456 // the insertion cheaply.
8457 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8458 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8460 // Try inverting the insertion since for v2 masks it is easy to do and we
8461 // can't reliably sort the mask one way or the other.
8462 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
8463 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8464 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
8467 // We have different paths for blend lowering, but they all must use the
8468 // *exact* same predicate.
8469 bool IsBlendSupported = Subtarget->hasSSE41();
8470 if (IsBlendSupported)
8471 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8475 // Use dedicated unpack instructions for masks that match their pattern.
8477 lowerVectorShuffleWithUNPCK(DL, MVT::v2i64, Mask, V1, V2, DAG))
8480 // Try to use byte rotation instructions.
8481 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8482 if (Subtarget->hasSSSE3())
8483 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8484 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8487 // If we have direct support for blends, we should lower by decomposing into
8488 // a permute. That will be faster than the domain cross.
8489 if (IsBlendSupported)
8490 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
8493 // We implement this with SHUFPD which is pretty lame because it will likely
8494 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8495 // However, all the alternatives are still more cycles and newer chips don't
8496 // have this problem. It would be really nice if x86 had better shuffles here.
8497 V1 = DAG.getBitcast(MVT::v2f64, V1);
8498 V2 = DAG.getBitcast(MVT::v2f64, V2);
8499 return DAG.getBitcast(MVT::v2i64,
8500 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8503 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
8505 /// This is used to disable more specialized lowerings when the shufps lowering
8506 /// will happen to be efficient.
8507 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
8508 // This routine only handles 128-bit shufps.
8509 assert(Mask.size() == 4 && "Unsupported mask size!");
8511 // To lower with a single SHUFPS we need to have the low half and high half
8512 // each requiring a single input.
8513 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
8515 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
8521 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8523 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8524 /// It makes no assumptions about whether this is the *best* lowering, it simply
8526 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8527 ArrayRef<int> Mask, SDValue V1,
8528 SDValue V2, SelectionDAG &DAG) {
8529 SDValue LowV = V1, HighV = V2;
8530 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8533 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8535 if (NumV2Elements == 1) {
8537 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8540 // Compute the index adjacent to V2Index and in the same half by toggling
8542 int V2AdjIndex = V2Index ^ 1;
8544 if (Mask[V2AdjIndex] == -1) {
8545 // Handles all the cases where we have a single V2 element and an undef.
8546 // This will only ever happen in the high lanes because we commute the
8547 // vector otherwise.
8549 std::swap(LowV, HighV);
8550 NewMask[V2Index] -= 4;
8552 // Handle the case where the V2 element ends up adjacent to a V1 element.
8553 // To make this work, blend them together as the first step.
8554 int V1Index = V2AdjIndex;
8555 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8556 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8557 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8559 // Now proceed to reconstruct the final blend as we have the necessary
8560 // high or low half formed.
8567 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8568 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8570 } else if (NumV2Elements == 2) {
8571 if (Mask[0] < 4 && Mask[1] < 4) {
8572 // Handle the easy case where we have V1 in the low lanes and V2 in the
8576 } else if (Mask[2] < 4 && Mask[3] < 4) {
8577 // We also handle the reversed case because this utility may get called
8578 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8579 // arrange things in the right direction.
8585 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8586 // trying to place elements directly, just blend them and set up the final
8587 // shuffle to place them.
8589 // The first two blend mask elements are for V1, the second two are for
8591 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8592 Mask[2] < 4 ? Mask[2] : Mask[3],
8593 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8594 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8595 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8596 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8598 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8601 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8602 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8603 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8604 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8607 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8608 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
8611 /// \brief Lower 4-lane 32-bit floating point shuffles.
8613 /// Uses instructions exclusively from the floating point unit to minimize
8614 /// domain crossing penalties, as these are sufficient to implement all v4f32
8616 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8617 const X86Subtarget *Subtarget,
8618 SelectionDAG &DAG) {
8620 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8621 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8622 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8623 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8624 ArrayRef<int> Mask = SVOp->getMask();
8625 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8628 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8630 if (NumV2Elements == 0) {
8631 // Check for being able to broadcast a single element.
8632 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
8633 Mask, Subtarget, DAG))
8636 // Use even/odd duplicate instructions for masks that match their pattern.
8637 if (Subtarget->hasSSE3()) {
8638 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
8639 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
8640 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
8641 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
8644 if (Subtarget->hasAVX()) {
8645 // If we have AVX, we can use VPERMILPS which will allow folding a load
8646 // into the shuffle.
8647 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8648 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8651 // Otherwise, use a straight shuffle of a single input vector. We pass the
8652 // input vector to both operands to simulate this with a SHUFPS.
8653 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8654 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8657 // There are special ways we can lower some single-element blends. However, we
8658 // have custom ways we can lower more complex single-element blends below that
8659 // we defer to if both this and BLENDPS fail to match, so restrict this to
8660 // when the V2 input is targeting element 0 of the mask -- that is the fast
8662 if (NumV2Elements == 1 && Mask[0] >= 4)
8663 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
8664 Mask, Subtarget, DAG))
8667 if (Subtarget->hasSSE41()) {
8668 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8672 // Use INSERTPS if we can complete the shuffle efficiently.
8673 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8676 if (!isSingleSHUFPSMask(Mask))
8677 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
8678 DL, MVT::v4f32, V1, V2, Mask, DAG))
8682 // Use dedicated unpack instructions for masks that match their pattern.
8684 lowerVectorShuffleWithUNPCK(DL, MVT::v4f32, Mask, V1, V2, DAG))
8687 // Otherwise fall back to a SHUFPS lowering strategy.
8688 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8691 /// \brief Lower 4-lane i32 vector shuffles.
8693 /// We try to handle these with integer-domain shuffles where we can, but for
8694 /// blends we use the floating point domain blend instructions.
8695 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8696 const X86Subtarget *Subtarget,
8697 SelectionDAG &DAG) {
8699 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8700 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8701 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8702 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8703 ArrayRef<int> Mask = SVOp->getMask();
8704 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8706 // Whenever we can lower this as a zext, that instruction is strictly faster
8707 // than any alternative. It also allows us to fold memory operands into the
8708 // shuffle in many cases.
8709 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8710 Mask, Subtarget, DAG))
8714 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8716 if (NumV2Elements == 0) {
8717 // Check for being able to broadcast a single element.
8718 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
8719 Mask, Subtarget, DAG))
8722 // Straight shuffle of a single input vector. For everything from SSE2
8723 // onward this has a single fast instruction with no scary immediates.
8724 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8725 // but we aren't actually going to use the UNPCK instruction because doing
8726 // so prevents folding a load into this instruction or making a copy.
8727 const int UnpackLoMask[] = {0, 0, 1, 1};
8728 const int UnpackHiMask[] = {2, 2, 3, 3};
8729 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
8730 Mask = UnpackLoMask;
8731 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
8732 Mask = UnpackHiMask;
8734 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8735 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8738 // Try to use shift instructions.
8740 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
8743 // There are special ways we can lower some single-element blends.
8744 if (NumV2Elements == 1)
8745 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
8746 Mask, Subtarget, DAG))
8749 // We have different paths for blend lowering, but they all must use the
8750 // *exact* same predicate.
8751 bool IsBlendSupported = Subtarget->hasSSE41();
8752 if (IsBlendSupported)
8753 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8757 if (SDValue Masked =
8758 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
8761 // Use dedicated unpack instructions for masks that match their pattern.
8763 lowerVectorShuffleWithUNPCK(DL, MVT::v4i32, Mask, V1, V2, DAG))
8766 // Try to use byte rotation instructions.
8767 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8768 if (Subtarget->hasSSSE3())
8769 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8770 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8773 // If we have direct support for blends, we should lower by decomposing into
8774 // a permute. That will be faster than the domain cross.
8775 if (IsBlendSupported)
8776 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
8779 // Try to lower by permuting the inputs into an unpack instruction.
8780 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v4i32, V1,
8784 // We implement this with SHUFPS because it can blend from two vectors.
8785 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8786 // up the inputs, bypassing domain shift penalties that we would encur if we
8787 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8789 return DAG.getBitcast(
8791 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
8792 DAG.getBitcast(MVT::v4f32, V2), Mask));
8795 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8796 /// shuffle lowering, and the most complex part.
8798 /// The lowering strategy is to try to form pairs of input lanes which are
8799 /// targeted at the same half of the final vector, and then use a dword shuffle
8800 /// to place them onto the right half, and finally unpack the paired lanes into
8801 /// their final position.
8803 /// The exact breakdown of how to form these dword pairs and align them on the
8804 /// correct sides is really tricky. See the comments within the function for
8805 /// more of the details.
8807 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8808 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8809 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8810 /// vector, form the analogous 128-bit 8-element Mask.
8811 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8812 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8813 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8814 assert(VT.getVectorElementType() == MVT::i16 && "Bad input type!");
8815 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8817 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8818 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8819 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8821 SmallVector<int, 4> LoInputs;
8822 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8823 [](int M) { return M >= 0; });
8824 std::sort(LoInputs.begin(), LoInputs.end());
8825 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8826 SmallVector<int, 4> HiInputs;
8827 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8828 [](int M) { return M >= 0; });
8829 std::sort(HiInputs.begin(), HiInputs.end());
8830 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8832 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8833 int NumHToL = LoInputs.size() - NumLToL;
8835 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8836 int NumHToH = HiInputs.size() - NumLToH;
8837 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8838 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8839 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8840 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8842 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8843 // such inputs we can swap two of the dwords across the half mark and end up
8844 // with <=2 inputs to each half in each half. Once there, we can fall through
8845 // to the generic code below. For example:
8847 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8848 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8850 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8851 // and an existing 2-into-2 on the other half. In this case we may have to
8852 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8853 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8854 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8855 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8856 // half than the one we target for fixing) will be fixed when we re-enter this
8857 // path. We will also combine away any sequence of PSHUFD instructions that
8858 // result into a single instruction. Here is an example of the tricky case:
8860 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8861 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8863 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8865 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8866 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8868 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8869 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8871 // The result is fine to be handled by the generic logic.
8872 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8873 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8874 int AOffset, int BOffset) {
8875 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8876 "Must call this with A having 3 or 1 inputs from the A half.");
8877 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8878 "Must call this with B having 1 or 3 inputs from the B half.");
8879 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8880 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8882 bool ThreeAInputs = AToAInputs.size() == 3;
8884 // Compute the index of dword with only one word among the three inputs in
8885 // a half by taking the sum of the half with three inputs and subtracting
8886 // the sum of the actual three inputs. The difference is the remaining
8889 int &TripleDWord = ThreeAInputs ? ADWord : BDWord;
8890 int &OneInputDWord = ThreeAInputs ? BDWord : ADWord;
8891 int TripleInputOffset = ThreeAInputs ? AOffset : BOffset;
8892 ArrayRef<int> TripleInputs = ThreeAInputs ? AToAInputs : BToAInputs;
8893 int OneInput = ThreeAInputs ? BToAInputs[0] : AToAInputs[0];
8894 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8895 int TripleNonInputIdx =
8896 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8897 TripleDWord = TripleNonInputIdx / 2;
8899 // We use xor with one to compute the adjacent DWord to whichever one the
8901 OneInputDWord = (OneInput / 2) ^ 1;
8903 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8904 // and BToA inputs. If there is also such a problem with the BToB and AToB
8905 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8906 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8907 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8908 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8909 // Compute how many inputs will be flipped by swapping these DWords. We
8911 // to balance this to ensure we don't form a 3-1 shuffle in the other
8913 int NumFlippedAToBInputs =
8914 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8915 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8916 int NumFlippedBToBInputs =
8917 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8918 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8919 if ((NumFlippedAToBInputs == 1 &&
8920 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8921 (NumFlippedBToBInputs == 1 &&
8922 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8923 // We choose whether to fix the A half or B half based on whether that
8924 // half has zero flipped inputs. At zero, we may not be able to fix it
8925 // with that half. We also bias towards fixing the B half because that
8926 // will more commonly be the high half, and we have to bias one way.
8927 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8928 ArrayRef<int> Inputs) {
8929 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8930 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8931 PinnedIdx ^ 1) != Inputs.end();
8932 // Determine whether the free index is in the flipped dword or the
8933 // unflipped dword based on where the pinned index is. We use this bit
8934 // in an xor to conditionally select the adjacent dword.
8935 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8936 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8937 FixFreeIdx) != Inputs.end();
8938 if (IsFixIdxInput == IsFixFreeIdxInput)
8940 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8941 FixFreeIdx) != Inputs.end();
8942 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8943 "We need to be changing the number of flipped inputs!");
8944 int PSHUFHalfMask[] = {0, 1, 2, 3};
8945 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8946 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8948 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8951 if (M != -1 && M == FixIdx)
8953 else if (M != -1 && M == FixFreeIdx)
8956 if (NumFlippedBToBInputs != 0) {
8958 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8959 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8961 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8962 int APinnedIdx = ThreeAInputs ? TripleNonInputIdx : OneInput;
8963 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8968 int PSHUFDMask[] = {0, 1, 2, 3};
8969 PSHUFDMask[ADWord] = BDWord;
8970 PSHUFDMask[BDWord] = ADWord;
8973 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8974 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8976 // Adjust the mask to match the new locations of A and B.
8978 if (M != -1 && M/2 == ADWord)
8979 M = 2 * BDWord + M % 2;
8980 else if (M != -1 && M/2 == BDWord)
8981 M = 2 * ADWord + M % 2;
8983 // Recurse back into this routine to re-compute state now that this isn't
8984 // a 3 and 1 problem.
8985 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8988 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8989 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8990 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8991 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8993 // At this point there are at most two inputs to the low and high halves from
8994 // each half. That means the inputs can always be grouped into dwords and
8995 // those dwords can then be moved to the correct half with a dword shuffle.
8996 // We use at most one low and one high word shuffle to collect these paired
8997 // inputs into dwords, and finally a dword shuffle to place them.
8998 int PSHUFLMask[4] = {-1, -1, -1, -1};
8999 int PSHUFHMask[4] = {-1, -1, -1, -1};
9000 int PSHUFDMask[4] = {-1, -1, -1, -1};
9002 // First fix the masks for all the inputs that are staying in their
9003 // original halves. This will then dictate the targets of the cross-half
9005 auto fixInPlaceInputs =
9006 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
9007 MutableArrayRef<int> SourceHalfMask,
9008 MutableArrayRef<int> HalfMask, int HalfOffset) {
9009 if (InPlaceInputs.empty())
9011 if (InPlaceInputs.size() == 1) {
9012 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
9013 InPlaceInputs[0] - HalfOffset;
9014 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
9017 if (IncomingInputs.empty()) {
9018 // Just fix all of the in place inputs.
9019 for (int Input : InPlaceInputs) {
9020 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
9021 PSHUFDMask[Input / 2] = Input / 2;
9026 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
9027 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
9028 InPlaceInputs[0] - HalfOffset;
9029 // Put the second input next to the first so that they are packed into
9030 // a dword. We find the adjacent index by toggling the low bit.
9031 int AdjIndex = InPlaceInputs[0] ^ 1;
9032 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
9033 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
9034 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
9036 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
9037 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
9039 // Now gather the cross-half inputs and place them into a free dword of
9040 // their target half.
9041 // FIXME: This operation could almost certainly be simplified dramatically to
9042 // look more like the 3-1 fixing operation.
9043 auto moveInputsToRightHalf = [&PSHUFDMask](
9044 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
9045 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
9046 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
9048 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
9049 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
9051 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
9053 int LowWord = Word & ~1;
9054 int HighWord = Word | 1;
9055 return isWordClobbered(SourceHalfMask, LowWord) ||
9056 isWordClobbered(SourceHalfMask, HighWord);
9059 if (IncomingInputs.empty())
9062 if (ExistingInputs.empty()) {
9063 // Map any dwords with inputs from them into the right half.
9064 for (int Input : IncomingInputs) {
9065 // If the source half mask maps over the inputs, turn those into
9066 // swaps and use the swapped lane.
9067 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
9068 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
9069 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
9070 Input - SourceOffset;
9071 // We have to swap the uses in our half mask in one sweep.
9072 for (int &M : HalfMask)
9073 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
9075 else if (M == Input)
9076 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
9078 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
9079 Input - SourceOffset &&
9080 "Previous placement doesn't match!");
9082 // Note that this correctly re-maps both when we do a swap and when
9083 // we observe the other side of the swap above. We rely on that to
9084 // avoid swapping the members of the input list directly.
9085 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
9088 // Map the input's dword into the correct half.
9089 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
9090 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
9092 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
9094 "Previous placement doesn't match!");
9097 // And just directly shift any other-half mask elements to be same-half
9098 // as we will have mirrored the dword containing the element into the
9099 // same position within that half.
9100 for (int &M : HalfMask)
9101 if (M >= SourceOffset && M < SourceOffset + 4) {
9102 M = M - SourceOffset + DestOffset;
9103 assert(M >= 0 && "This should never wrap below zero!");
9108 // Ensure we have the input in a viable dword of its current half. This
9109 // is particularly tricky because the original position may be clobbered
9110 // by inputs being moved and *staying* in that half.
9111 if (IncomingInputs.size() == 1) {
9112 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
9113 int InputFixed = std::find(std::begin(SourceHalfMask),
9114 std::end(SourceHalfMask), -1) -
9115 std::begin(SourceHalfMask) + SourceOffset;
9116 SourceHalfMask[InputFixed - SourceOffset] =
9117 IncomingInputs[0] - SourceOffset;
9118 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
9120 IncomingInputs[0] = InputFixed;
9122 } else if (IncomingInputs.size() == 2) {
9123 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
9124 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
9125 // We have two non-adjacent or clobbered inputs we need to extract from
9126 // the source half. To do this, we need to map them into some adjacent
9127 // dword slot in the source mask.
9128 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
9129 IncomingInputs[1] - SourceOffset};
9131 // If there is a free slot in the source half mask adjacent to one of
9132 // the inputs, place the other input in it. We use (Index XOR 1) to
9133 // compute an adjacent index.
9134 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
9135 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
9136 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
9137 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9138 InputsFixed[1] = InputsFixed[0] ^ 1;
9139 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
9140 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
9141 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
9142 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
9143 InputsFixed[0] = InputsFixed[1] ^ 1;
9144 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
9145 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
9146 // The two inputs are in the same DWord but it is clobbered and the
9147 // adjacent DWord isn't used at all. Move both inputs to the free
9149 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
9150 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
9151 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
9152 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
9154 // The only way we hit this point is if there is no clobbering
9155 // (because there are no off-half inputs to this half) and there is no
9156 // free slot adjacent to one of the inputs. In this case, we have to
9157 // swap an input with a non-input.
9158 for (int i = 0; i < 4; ++i)
9159 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
9160 "We can't handle any clobbers here!");
9161 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
9162 "Cannot have adjacent inputs here!");
9164 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9165 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
9167 // We also have to update the final source mask in this case because
9168 // it may need to undo the above swap.
9169 for (int &M : FinalSourceHalfMask)
9170 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
9171 M = InputsFixed[1] + SourceOffset;
9172 else if (M == InputsFixed[1] + SourceOffset)
9173 M = (InputsFixed[0] ^ 1) + SourceOffset;
9175 InputsFixed[1] = InputsFixed[0] ^ 1;
9178 // Point everything at the fixed inputs.
9179 for (int &M : HalfMask)
9180 if (M == IncomingInputs[0])
9181 M = InputsFixed[0] + SourceOffset;
9182 else if (M == IncomingInputs[1])
9183 M = InputsFixed[1] + SourceOffset;
9185 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
9186 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
9189 llvm_unreachable("Unhandled input size!");
9192 // Now hoist the DWord down to the right half.
9193 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
9194 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
9195 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
9196 for (int &M : HalfMask)
9197 for (int Input : IncomingInputs)
9199 M = FreeDWord * 2 + Input % 2;
9201 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
9202 /*SourceOffset*/ 4, /*DestOffset*/ 0);
9203 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
9204 /*SourceOffset*/ 0, /*DestOffset*/ 4);
9206 // Now enact all the shuffles we've computed to move the inputs into their
9208 if (!isNoopShuffleMask(PSHUFLMask))
9209 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9210 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
9211 if (!isNoopShuffleMask(PSHUFHMask))
9212 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9213 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
9214 if (!isNoopShuffleMask(PSHUFDMask))
9217 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
9218 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9220 // At this point, each half should contain all its inputs, and we can then
9221 // just shuffle them into their final position.
9222 assert(std::count_if(LoMask.begin(), LoMask.end(),
9223 [](int M) { return M >= 4; }) == 0 &&
9224 "Failed to lift all the high half inputs to the low mask!");
9225 assert(std::count_if(HiMask.begin(), HiMask.end(),
9226 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9227 "Failed to lift all the low half inputs to the high mask!");
9229 // Do a half shuffle for the low mask.
9230 if (!isNoopShuffleMask(LoMask))
9231 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9232 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
9234 // Do a half shuffle with the high mask after shifting its values down.
9235 for (int &M : HiMask)
9238 if (!isNoopShuffleMask(HiMask))
9239 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9240 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
9245 /// \brief Helper to form a PSHUFB-based shuffle+blend.
9246 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
9247 SDValue V2, ArrayRef<int> Mask,
9248 SelectionDAG &DAG, bool &V1InUse,
9250 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
9256 int Size = Mask.size();
9257 int Scale = 16 / Size;
9258 for (int i = 0; i < 16; ++i) {
9259 if (Mask[i / Scale] == -1) {
9260 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9262 const int ZeroMask = 0x80;
9263 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
9265 int V2Idx = Mask[i / Scale] < Size
9267 : (Mask[i / Scale] - Size) * Scale + i % Scale;
9268 if (Zeroable[i / Scale])
9269 V1Idx = V2Idx = ZeroMask;
9270 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
9271 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
9272 V1InUse |= (ZeroMask != V1Idx);
9273 V2InUse |= (ZeroMask != V2Idx);
9278 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9279 DAG.getBitcast(MVT::v16i8, V1),
9280 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9282 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9283 DAG.getBitcast(MVT::v16i8, V2),
9284 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9286 // If we need shuffled inputs from both, blend the two.
9288 if (V1InUse && V2InUse)
9289 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9291 V = V1InUse ? V1 : V2;
9293 // Cast the result back to the correct type.
9294 return DAG.getBitcast(VT, V);
9297 /// \brief Generic lowering of 8-lane i16 shuffles.
9299 /// This handles both single-input shuffles and combined shuffle/blends with
9300 /// two inputs. The single input shuffles are immediately delegated to
9301 /// a dedicated lowering routine.
9303 /// The blends are lowered in one of three fundamental ways. If there are few
9304 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9305 /// of the input is significantly cheaper when lowered as an interleaving of
9306 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9307 /// halves of the inputs separately (making them have relatively few inputs)
9308 /// and then concatenate them.
9309 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9310 const X86Subtarget *Subtarget,
9311 SelectionDAG &DAG) {
9313 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9314 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9315 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9316 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9317 ArrayRef<int> OrigMask = SVOp->getMask();
9318 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9319 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9320 MutableArrayRef<int> Mask(MaskStorage);
9322 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9324 // Whenever we can lower this as a zext, that instruction is strictly faster
9325 // than any alternative.
9326 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9327 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9330 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9332 auto isV2 = [](int M) { return M >= 8; };
9334 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9336 if (NumV2Inputs == 0) {
9337 // Check for being able to broadcast a single element.
9338 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
9339 Mask, Subtarget, DAG))
9342 // Try to use shift instructions.
9344 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
9347 // Use dedicated unpack instructions for masks that match their pattern.
9349 lowerVectorShuffleWithUNPCK(DL, MVT::v8i16, Mask, V1, V2, DAG))
9352 // Try to use byte rotation instructions.
9353 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
9354 Mask, Subtarget, DAG))
9357 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
9361 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
9362 "All single-input shuffles should be canonicalized to be V1-input "
9365 // Try to use shift instructions.
9367 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
9370 // See if we can use SSE4A Extraction / Insertion.
9371 if (Subtarget->hasSSE4A())
9372 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v8i16, V1, V2, Mask, DAG))
9375 // There are special ways we can lower some single-element blends.
9376 if (NumV2Inputs == 1)
9377 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
9378 Mask, Subtarget, DAG))
9381 // We have different paths for blend lowering, but they all must use the
9382 // *exact* same predicate.
9383 bool IsBlendSupported = Subtarget->hasSSE41();
9384 if (IsBlendSupported)
9385 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9389 if (SDValue Masked =
9390 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
9393 // Use dedicated unpack instructions for masks that match their pattern.
9395 lowerVectorShuffleWithUNPCK(DL, MVT::v8i16, Mask, V1, V2, DAG))
9398 // Try to use byte rotation instructions.
9399 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9400 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9403 if (SDValue BitBlend =
9404 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
9407 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v8i16, V1,
9411 // If we can't directly blend but can use PSHUFB, that will be better as it
9412 // can both shuffle and set up the inefficient blend.
9413 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
9414 bool V1InUse, V2InUse;
9415 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
9419 // We can always bit-blend if we have to so the fallback strategy is to
9420 // decompose into single-input permutes and blends.
9421 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
9425 /// \brief Check whether a compaction lowering can be done by dropping even
9426 /// elements and compute how many times even elements must be dropped.
9428 /// This handles shuffles which take every Nth element where N is a power of
9429 /// two. Example shuffle masks:
9431 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9432 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9433 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9434 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9435 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9436 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9438 /// Any of these lanes can of course be undef.
9440 /// This routine only supports N <= 3.
9441 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9444 /// \returns N above, or the number of times even elements must be dropped if
9445 /// there is such a number. Otherwise returns zero.
9446 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9447 // Figure out whether we're looping over two inputs or just one.
9448 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9450 // The modulus for the shuffle vector entries is based on whether this is
9451 // a single input or not.
9452 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9453 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9454 "We should only be called with masks with a power-of-2 size!");
9456 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9458 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9459 // and 2^3 simultaneously. This is because we may have ambiguity with
9460 // partially undef inputs.
9461 bool ViableForN[3] = {true, true, true};
9463 for (int i = 0, e = Mask.size(); i < e; ++i) {
9464 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9469 bool IsAnyViable = false;
9470 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9471 if (ViableForN[j]) {
9474 // The shuffle mask must be equal to (i * 2^N) % M.
9475 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9478 ViableForN[j] = false;
9480 // Early exit if we exhaust the possible powers of two.
9485 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9489 // Return 0 as there is no viable power of two.
9493 /// \brief Generic lowering of v16i8 shuffles.
9495 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9496 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9497 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9498 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9500 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9501 const X86Subtarget *Subtarget,
9502 SelectionDAG &DAG) {
9504 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9505 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9506 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9507 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9508 ArrayRef<int> Mask = SVOp->getMask();
9509 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9511 // Try to use shift instructions.
9513 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
9516 // Try to use byte rotation instructions.
9517 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9518 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9521 // Try to use a zext lowering.
9522 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9523 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9526 // See if we can use SSE4A Extraction / Insertion.
9527 if (Subtarget->hasSSE4A())
9528 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v16i8, V1, V2, Mask, DAG))
9532 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9534 // For single-input shuffles, there are some nicer lowering tricks we can use.
9535 if (NumV2Elements == 0) {
9536 // Check for being able to broadcast a single element.
9537 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
9538 Mask, Subtarget, DAG))
9541 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9542 // Notably, this handles splat and partial-splat shuffles more efficiently.
9543 // However, it only makes sense if the pre-duplication shuffle simplifies
9544 // things significantly. Currently, this means we need to be able to
9545 // express the pre-duplication shuffle as an i16 shuffle.
9547 // FIXME: We should check for other patterns which can be widened into an
9548 // i16 shuffle as well.
9549 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9550 for (int i = 0; i < 16; i += 2)
9551 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9556 auto tryToWidenViaDuplication = [&]() -> SDValue {
9557 if (!canWidenViaDuplication(Mask))
9559 SmallVector<int, 4> LoInputs;
9560 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9561 [](int M) { return M >= 0 && M < 8; });
9562 std::sort(LoInputs.begin(), LoInputs.end());
9563 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9565 SmallVector<int, 4> HiInputs;
9566 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9567 [](int M) { return M >= 8; });
9568 std::sort(HiInputs.begin(), HiInputs.end());
9569 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9572 bool TargetLo = LoInputs.size() >= HiInputs.size();
9573 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9574 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9576 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9577 SmallDenseMap<int, int, 8> LaneMap;
9578 for (int I : InPlaceInputs) {
9579 PreDupI16Shuffle[I/2] = I/2;
9582 int j = TargetLo ? 0 : 4, je = j + 4;
9583 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9584 // Check if j is already a shuffle of this input. This happens when
9585 // there are two adjacent bytes after we move the low one.
9586 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9587 // If we haven't yet mapped the input, search for a slot into which
9589 while (j < je && PreDupI16Shuffle[j] != -1)
9593 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9596 // Map this input with the i16 shuffle.
9597 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9600 // Update the lane map based on the mapping we ended up with.
9601 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9603 V1 = DAG.getBitcast(
9605 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9606 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9608 // Unpack the bytes to form the i16s that will be shuffled into place.
9609 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9610 MVT::v16i8, V1, V1);
9612 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9613 for (int i = 0; i < 16; ++i)
9614 if (Mask[i] != -1) {
9615 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9616 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9617 if (PostDupI16Shuffle[i / 2] == -1)
9618 PostDupI16Shuffle[i / 2] = MappedMask;
9620 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9621 "Conflicting entrties in the original shuffle!");
9623 return DAG.getBitcast(
9625 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9626 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9628 if (SDValue V = tryToWidenViaDuplication())
9632 if (SDValue Masked =
9633 lowerVectorShuffleAsBitMask(DL, MVT::v16i8, V1, V2, Mask, DAG))
9636 // Use dedicated unpack instructions for masks that match their pattern.
9638 lowerVectorShuffleWithUNPCK(DL, MVT::v16i8, Mask, V1, V2, DAG))
9641 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9642 // with PSHUFB. It is important to do this before we attempt to generate any
9643 // blends but after all of the single-input lowerings. If the single input
9644 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9645 // want to preserve that and we can DAG combine any longer sequences into
9646 // a PSHUFB in the end. But once we start blending from multiple inputs,
9647 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9648 // and there are *very* few patterns that would actually be faster than the
9649 // PSHUFB approach because of its ability to zero lanes.
9651 // FIXME: The only exceptions to the above are blends which are exact
9652 // interleavings with direct instructions supporting them. We currently don't
9653 // handle those well here.
9654 if (Subtarget->hasSSSE3()) {
9655 bool V1InUse = false;
9656 bool V2InUse = false;
9658 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
9659 DAG, V1InUse, V2InUse);
9661 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
9662 // do so. This avoids using them to handle blends-with-zero which is
9663 // important as a single pshufb is significantly faster for that.
9664 if (V1InUse && V2InUse) {
9665 if (Subtarget->hasSSE41())
9666 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
9667 Mask, Subtarget, DAG))
9670 // We can use an unpack to do the blending rather than an or in some
9671 // cases. Even though the or may be (very minorly) more efficient, we
9672 // preference this lowering because there are common cases where part of
9673 // the complexity of the shuffles goes away when we do the final blend as
9675 // FIXME: It might be worth trying to detect if the unpack-feeding
9676 // shuffles will both be pshufb, in which case we shouldn't bother with
9678 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(
9679 DL, MVT::v16i8, V1, V2, Mask, DAG))
9686 // There are special ways we can lower some single-element blends.
9687 if (NumV2Elements == 1)
9688 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
9689 Mask, Subtarget, DAG))
9692 if (SDValue BitBlend =
9693 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
9696 // Check whether a compaction lowering can be done. This handles shuffles
9697 // which take every Nth element for some even N. See the helper function for
9700 // We special case these as they can be particularly efficiently handled with
9701 // the PACKUSB instruction on x86 and they show up in common patterns of
9702 // rearranging bytes to truncate wide elements.
9703 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9704 // NumEvenDrops is the power of two stride of the elements. Another way of
9705 // thinking about it is that we need to drop the even elements this many
9706 // times to get the original input.
9707 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9709 // First we need to zero all the dropped bytes.
9710 assert(NumEvenDrops <= 3 &&
9711 "No support for dropping even elements more than 3 times.");
9712 // We use the mask type to pick which bytes are preserved based on how many
9713 // elements are dropped.
9714 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9715 SDValue ByteClearMask = DAG.getBitcast(
9716 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
9717 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9719 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9721 // Now pack things back together.
9722 V1 = DAG.getBitcast(MVT::v8i16, V1);
9723 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
9724 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9725 for (int i = 1; i < NumEvenDrops; ++i) {
9726 Result = DAG.getBitcast(MVT::v8i16, Result);
9727 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9733 // Handle multi-input cases by blending single-input shuffles.
9734 if (NumV2Elements > 0)
9735 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
9738 // The fallback path for single-input shuffles widens this into two v8i16
9739 // vectors with unpacks, shuffles those, and then pulls them back together
9743 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9744 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9745 for (int i = 0; i < 16; ++i)
9747 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
9749 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9751 SDValue VLoHalf, VHiHalf;
9752 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9753 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9755 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
9756 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9757 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
9758 [](int M) { return M >= 0 && M % 2 == 1; })) {
9759 // Use a mask to drop the high bytes.
9760 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
9761 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
9762 DAG.getConstant(0x00FF, DL, MVT::v8i16));
9764 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
9765 VHiHalf = DAG.getUNDEF(MVT::v8i16);
9767 // Squash the masks to point directly into VLoHalf.
9768 for (int &M : LoBlendMask)
9771 for (int &M : HiBlendMask)
9775 // Otherwise just unpack the low half of V into VLoHalf and the high half into
9776 // VHiHalf so that we can blend them as i16s.
9777 VLoHalf = DAG.getBitcast(
9778 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9779 VHiHalf = DAG.getBitcast(
9780 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9783 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
9784 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
9786 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9789 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9791 /// This routine breaks down the specific type of 128-bit shuffle and
9792 /// dispatches to the lowering routines accordingly.
9793 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9794 MVT VT, const X86Subtarget *Subtarget,
9795 SelectionDAG &DAG) {
9796 switch (VT.SimpleTy) {
9798 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9800 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9802 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9804 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9806 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9808 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9811 llvm_unreachable("Unimplemented!");
9815 /// \brief Helper function to test whether a shuffle mask could be
9816 /// simplified by widening the elements being shuffled.
9818 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9819 /// leaves it in an unspecified state.
9821 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9822 /// shuffle masks. The latter have the special property of a '-2' representing
9823 /// a zero-ed lane of a vector.
9824 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9825 SmallVectorImpl<int> &WidenedMask) {
9826 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9827 // If both elements are undef, its trivial.
9828 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9829 WidenedMask.push_back(SM_SentinelUndef);
9833 // Check for an undef mask and a mask value properly aligned to fit with
9834 // a pair of values. If we find such a case, use the non-undef mask's value.
9835 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9836 WidenedMask.push_back(Mask[i + 1] / 2);
9839 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9840 WidenedMask.push_back(Mask[i] / 2);
9844 // When zeroing, we need to spread the zeroing across both lanes to widen.
9845 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9846 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9847 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9848 WidenedMask.push_back(SM_SentinelZero);
9854 // Finally check if the two mask values are adjacent and aligned with
9856 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9857 WidenedMask.push_back(Mask[i] / 2);
9861 // Otherwise we can't safely widen the elements used in this shuffle.
9864 assert(WidenedMask.size() == Mask.size() / 2 &&
9865 "Incorrect size of mask after widening the elements!");
9870 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9872 /// This routine just extracts two subvectors, shuffles them independently, and
9873 /// then concatenates them back together. This should work effectively with all
9874 /// AVX vector shuffle types.
9875 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9876 SDValue V2, ArrayRef<int> Mask,
9877 SelectionDAG &DAG) {
9878 assert(VT.getSizeInBits() >= 256 &&
9879 "Only for 256-bit or wider vector shuffles!");
9880 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9881 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9883 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9884 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9886 int NumElements = VT.getVectorNumElements();
9887 int SplitNumElements = NumElements / 2;
9888 MVT ScalarVT = VT.getVectorElementType();
9889 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9891 // Rather than splitting build-vectors, just build two narrower build
9892 // vectors. This helps shuffling with splats and zeros.
9893 auto SplitVector = [&](SDValue V) {
9894 while (V.getOpcode() == ISD::BITCAST)
9895 V = V->getOperand(0);
9897 MVT OrigVT = V.getSimpleValueType();
9898 int OrigNumElements = OrigVT.getVectorNumElements();
9899 int OrigSplitNumElements = OrigNumElements / 2;
9900 MVT OrigScalarVT = OrigVT.getVectorElementType();
9901 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9905 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9907 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9908 DAG.getIntPtrConstant(0, DL));
9909 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9910 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9913 SmallVector<SDValue, 16> LoOps, HiOps;
9914 for (int i = 0; i < OrigSplitNumElements; ++i) {
9915 LoOps.push_back(BV->getOperand(i));
9916 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9918 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9919 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9921 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
9922 DAG.getBitcast(SplitVT, HiV));
9925 SDValue LoV1, HiV1, LoV2, HiV2;
9926 std::tie(LoV1, HiV1) = SplitVector(V1);
9927 std::tie(LoV2, HiV2) = SplitVector(V2);
9929 // Now create two 4-way blends of these half-width vectors.
9930 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9931 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9932 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9933 for (int i = 0; i < SplitNumElements; ++i) {
9934 int M = HalfMask[i];
9935 if (M >= NumElements) {
9936 if (M >= NumElements + SplitNumElements)
9940 V2BlendMask.push_back(M - NumElements);
9941 V1BlendMask.push_back(-1);
9942 BlendMask.push_back(SplitNumElements + i);
9943 } else if (M >= 0) {
9944 if (M >= SplitNumElements)
9948 V2BlendMask.push_back(-1);
9949 V1BlendMask.push_back(M);
9950 BlendMask.push_back(i);
9952 V2BlendMask.push_back(-1);
9953 V1BlendMask.push_back(-1);
9954 BlendMask.push_back(-1);
9958 // Because the lowering happens after all combining takes place, we need to
9959 // manually combine these blend masks as much as possible so that we create
9960 // a minimal number of high-level vector shuffle nodes.
9962 // First try just blending the halves of V1 or V2.
9963 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9964 return DAG.getUNDEF(SplitVT);
9965 if (!UseLoV2 && !UseHiV2)
9966 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9967 if (!UseLoV1 && !UseHiV1)
9968 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9970 SDValue V1Blend, V2Blend;
9971 if (UseLoV1 && UseHiV1) {
9973 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9975 // We only use half of V1 so map the usage down into the final blend mask.
9976 V1Blend = UseLoV1 ? LoV1 : HiV1;
9977 for (int i = 0; i < SplitNumElements; ++i)
9978 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9979 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9981 if (UseLoV2 && UseHiV2) {
9983 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9985 // We only use half of V2 so map the usage down into the final blend mask.
9986 V2Blend = UseLoV2 ? LoV2 : HiV2;
9987 for (int i = 0; i < SplitNumElements; ++i)
9988 if (BlendMask[i] >= SplitNumElements)
9989 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9991 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9993 SDValue Lo = HalfBlend(LoMask);
9994 SDValue Hi = HalfBlend(HiMask);
9995 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9998 /// \brief Either split a vector in halves or decompose the shuffles and the
10001 /// This is provided as a good fallback for many lowerings of non-single-input
10002 /// shuffles with more than one 128-bit lane. In those cases, we want to select
10003 /// between splitting the shuffle into 128-bit components and stitching those
10004 /// back together vs. extracting the single-input shuffles and blending those
10006 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
10007 SDValue V2, ArrayRef<int> Mask,
10008 SelectionDAG &DAG) {
10009 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
10010 "lower single-input shuffles as it "
10011 "could then recurse on itself.");
10012 int Size = Mask.size();
10014 // If this can be modeled as a broadcast of two elements followed by a blend,
10015 // prefer that lowering. This is especially important because broadcasts can
10016 // often fold with memory operands.
10017 auto DoBothBroadcast = [&] {
10018 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
10021 if (V2BroadcastIdx == -1)
10022 V2BroadcastIdx = M - Size;
10023 else if (M - Size != V2BroadcastIdx)
10025 } else if (M >= 0) {
10026 if (V1BroadcastIdx == -1)
10027 V1BroadcastIdx = M;
10028 else if (M != V1BroadcastIdx)
10033 if (DoBothBroadcast())
10034 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
10037 // If the inputs all stem from a single 128-bit lane of each input, then we
10038 // split them rather than blending because the split will decompose to
10039 // unusually few instructions.
10040 int LaneCount = VT.getSizeInBits() / 128;
10041 int LaneSize = Size / LaneCount;
10042 SmallBitVector LaneInputs[2];
10043 LaneInputs[0].resize(LaneCount, false);
10044 LaneInputs[1].resize(LaneCount, false);
10045 for (int i = 0; i < Size; ++i)
10047 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
10048 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
10049 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10051 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
10052 // that the decomposed single-input shuffles don't end up here.
10053 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10056 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
10057 /// a permutation and blend of those lanes.
10059 /// This essentially blends the out-of-lane inputs to each lane into the lane
10060 /// from a permuted copy of the vector. This lowering strategy results in four
10061 /// instructions in the worst case for a single-input cross lane shuffle which
10062 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
10063 /// of. Special cases for each particular shuffle pattern should be handled
10064 /// prior to trying this lowering.
10065 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
10066 SDValue V1, SDValue V2,
10067 ArrayRef<int> Mask,
10068 SelectionDAG &DAG) {
10069 // FIXME: This should probably be generalized for 512-bit vectors as well.
10070 assert(VT.is256BitVector() && "Only for 256-bit vector shuffles!");
10071 int LaneSize = Mask.size() / 2;
10073 // If there are only inputs from one 128-bit lane, splitting will in fact be
10074 // less expensive. The flags track whether the given lane contains an element
10075 // that crosses to another lane.
10076 bool LaneCrossing[2] = {false, false};
10077 for (int i = 0, Size = Mask.size(); i < Size; ++i)
10078 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
10079 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
10080 if (!LaneCrossing[0] || !LaneCrossing[1])
10081 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10083 if (isSingleInputShuffleMask(Mask)) {
10084 SmallVector<int, 32> FlippedBlendMask;
10085 for (int i = 0, Size = Mask.size(); i < Size; ++i)
10086 FlippedBlendMask.push_back(
10087 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
10089 : Mask[i] % LaneSize +
10090 (i / LaneSize) * LaneSize + Size));
10092 // Flip the vector, and blend the results which should now be in-lane. The
10093 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
10094 // 5 for the high source. The value 3 selects the high half of source 2 and
10095 // the value 2 selects the low half of source 2. We only use source 2 to
10096 // allow folding it into a memory operand.
10097 unsigned PERMMask = 3 | 2 << 4;
10098 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
10099 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
10100 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
10103 // This now reduces to two single-input shuffles of V1 and V2 which at worst
10104 // will be handled by the above logic and a blend of the results, much like
10105 // other patterns in AVX.
10106 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10109 /// \brief Handle lowering 2-lane 128-bit shuffles.
10110 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
10111 SDValue V2, ArrayRef<int> Mask,
10112 const X86Subtarget *Subtarget,
10113 SelectionDAG &DAG) {
10114 // TODO: If minimizing size and one of the inputs is a zero vector and the
10115 // the zero vector has only one use, we could use a VPERM2X128 to save the
10116 // instruction bytes needed to explicitly generate the zero vector.
10118 // Blends are faster and handle all the non-lane-crossing cases.
10119 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
10123 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
10124 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
10126 // If either input operand is a zero vector, use VPERM2X128 because its mask
10127 // allows us to replace the zero input with an implicit zero.
10128 if (!IsV1Zero && !IsV2Zero) {
10129 // Check for patterns which can be matched with a single insert of a 128-bit
10131 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
10132 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
10133 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
10134 VT.getVectorNumElements() / 2);
10135 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10136 DAG.getIntPtrConstant(0, DL));
10137 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
10138 OnlyUsesV1 ? V1 : V2,
10139 DAG.getIntPtrConstant(0, DL));
10140 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10144 // Otherwise form a 128-bit permutation. After accounting for undefs,
10145 // convert the 64-bit shuffle mask selection values into 128-bit
10146 // selection bits by dividing the indexes by 2 and shifting into positions
10147 // defined by a vperm2*128 instruction's immediate control byte.
10149 // The immediate permute control byte looks like this:
10150 // [1:0] - select 128 bits from sources for low half of destination
10152 // [3] - zero low half of destination
10153 // [5:4] - select 128 bits from sources for high half of destination
10155 // [7] - zero high half of destination
10157 int MaskLO = Mask[0];
10158 if (MaskLO == SM_SentinelUndef)
10159 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
10161 int MaskHI = Mask[2];
10162 if (MaskHI == SM_SentinelUndef)
10163 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
10165 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
10167 // If either input is a zero vector, replace it with an undef input.
10168 // Shuffle mask values < 4 are selecting elements of V1.
10169 // Shuffle mask values >= 4 are selecting elements of V2.
10170 // Adjust each half of the permute mask by clearing the half that was
10171 // selecting the zero vector and setting the zero mask bit.
10173 V1 = DAG.getUNDEF(VT);
10175 PermMask = (PermMask & 0xf0) | 0x08;
10177 PermMask = (PermMask & 0x0f) | 0x80;
10180 V2 = DAG.getUNDEF(VT);
10182 PermMask = (PermMask & 0xf0) | 0x08;
10184 PermMask = (PermMask & 0x0f) | 0x80;
10187 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
10188 DAG.getConstant(PermMask, DL, MVT::i8));
10191 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10192 /// shuffling each lane.
10194 /// This will only succeed when the result of fixing the 128-bit lanes results
10195 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10196 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10197 /// the lane crosses early and then use simpler shuffles within each lane.
10199 /// FIXME: It might be worthwhile at some point to support this without
10200 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10201 /// in x86 only floating point has interesting non-repeating shuffles, and even
10202 /// those are still *marginally* more expensive.
10203 static SDValue lowerVectorShuffleByMerging128BitLanes(
10204 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10205 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10206 assert(!isSingleInputShuffleMask(Mask) &&
10207 "This is only useful with multiple inputs.");
10209 int Size = Mask.size();
10210 int LaneSize = 128 / VT.getScalarSizeInBits();
10211 int NumLanes = Size / LaneSize;
10212 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10214 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10215 // check whether the in-128-bit lane shuffles share a repeating pattern.
10216 SmallVector<int, 4> Lanes;
10217 Lanes.resize(NumLanes, -1);
10218 SmallVector<int, 4> InLaneMask;
10219 InLaneMask.resize(LaneSize, -1);
10220 for (int i = 0; i < Size; ++i) {
10224 int j = i / LaneSize;
10226 if (Lanes[j] < 0) {
10227 // First entry we've seen for this lane.
10228 Lanes[j] = Mask[i] / LaneSize;
10229 } else if (Lanes[j] != Mask[i] / LaneSize) {
10230 // This doesn't match the lane selected previously!
10234 // Check that within each lane we have a consistent shuffle mask.
10235 int k = i % LaneSize;
10236 if (InLaneMask[k] < 0) {
10237 InLaneMask[k] = Mask[i] % LaneSize;
10238 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10239 // This doesn't fit a repeating in-lane mask.
10244 // First shuffle the lanes into place.
10245 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10246 VT.getSizeInBits() / 64);
10247 SmallVector<int, 8> LaneMask;
10248 LaneMask.resize(NumLanes * 2, -1);
10249 for (int i = 0; i < NumLanes; ++i)
10250 if (Lanes[i] >= 0) {
10251 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10252 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10255 V1 = DAG.getBitcast(LaneVT, V1);
10256 V2 = DAG.getBitcast(LaneVT, V2);
10257 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10259 // Cast it back to the type we actually want.
10260 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
10262 // Now do a simple shuffle that isn't lane crossing.
10263 SmallVector<int, 8> NewMask;
10264 NewMask.resize(Size, -1);
10265 for (int i = 0; i < Size; ++i)
10267 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10268 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10269 "Must not introduce lane crosses at this point!");
10271 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10274 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10277 /// This returns true if the elements from a particular input are already in the
10278 /// slot required by the given mask and require no permutation.
10279 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10280 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10281 int Size = Mask.size();
10282 for (int i = 0; i < Size; ++i)
10283 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10289 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
10290 ArrayRef<int> Mask, SDValue V1,
10291 SDValue V2, SelectionDAG &DAG) {
10293 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
10294 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
10295 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
10296 int NumElts = VT.getVectorNumElements();
10297 bool ShufpdMask = true;
10298 bool CommutableMask = true;
10299 unsigned Immediate = 0;
10300 for (int i = 0; i < NumElts; ++i) {
10303 int Val = (i & 6) + NumElts * (i & 1);
10304 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
10305 if (Mask[i] < Val || Mask[i] > Val + 1)
10306 ShufpdMask = false;
10307 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
10308 CommutableMask = false;
10309 Immediate |= (Mask[i] % 2) << i;
10312 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
10313 DAG.getConstant(Immediate, DL, MVT::i8));
10314 if (CommutableMask)
10315 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
10316 DAG.getConstant(Immediate, DL, MVT::i8));
10320 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10322 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10323 /// isn't available.
10324 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10325 const X86Subtarget *Subtarget,
10326 SelectionDAG &DAG) {
10328 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10329 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10330 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10331 ArrayRef<int> Mask = SVOp->getMask();
10332 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10334 SmallVector<int, 4> WidenedMask;
10335 if (canWidenShuffleElements(Mask, WidenedMask))
10336 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10339 if (isSingleInputShuffleMask(Mask)) {
10340 // Check for being able to broadcast a single element.
10341 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
10342 Mask, Subtarget, DAG))
10345 // Use low duplicate instructions for masks that match their pattern.
10346 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
10347 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
10349 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10350 // Non-half-crossing single input shuffles can be lowerid with an
10351 // interleaved permutation.
10352 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10353 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10354 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10355 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
10358 // With AVX2 we have direct support for this permutation.
10359 if (Subtarget->hasAVX2())
10360 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10361 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10363 // Otherwise, fall back.
10364 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10368 // Use dedicated unpack instructions for masks that match their pattern.
10370 lowerVectorShuffleWithUNPCK(DL, MVT::v4f64, Mask, V1, V2, DAG))
10373 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10377 // Check if the blend happens to exactly fit that of SHUFPD.
10379 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
10382 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10383 // shuffle. However, if we have AVX2 and either inputs are already in place,
10384 // we will be able to shuffle even across lanes the other input in a single
10385 // instruction so skip this pattern.
10386 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10387 isShuffleMaskInputInPlace(1, Mask))))
10388 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10389 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10392 // If we have AVX2 then we always want to lower with a blend because an v4 we
10393 // can fully permute the elements.
10394 if (Subtarget->hasAVX2())
10395 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10398 // Otherwise fall back on generic lowering.
10399 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10402 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10404 /// This routine is only called when we have AVX2 and thus a reasonable
10405 /// instruction set for v4i64 shuffling..
10406 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10407 const X86Subtarget *Subtarget,
10408 SelectionDAG &DAG) {
10410 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10411 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10412 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10413 ArrayRef<int> Mask = SVOp->getMask();
10414 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10415 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10417 SmallVector<int, 4> WidenedMask;
10418 if (canWidenShuffleElements(Mask, WidenedMask))
10419 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10422 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10426 // Check for being able to broadcast a single element.
10427 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
10428 Mask, Subtarget, DAG))
10431 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10432 // use lower latency instructions that will operate on both 128-bit lanes.
10433 SmallVector<int, 2> RepeatedMask;
10434 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10435 if (isSingleInputShuffleMask(Mask)) {
10436 int PSHUFDMask[] = {-1, -1, -1, -1};
10437 for (int i = 0; i < 2; ++i)
10438 if (RepeatedMask[i] >= 0) {
10439 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10440 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10442 return DAG.getBitcast(
10444 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10445 DAG.getBitcast(MVT::v8i32, V1),
10446 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
10450 // AVX2 provides a direct instruction for permuting a single input across
10452 if (isSingleInputShuffleMask(Mask))
10453 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10454 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10456 // Try to use shift instructions.
10457 if (SDValue Shift =
10458 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
10461 // Use dedicated unpack instructions for masks that match their pattern.
10463 lowerVectorShuffleWithUNPCK(DL, MVT::v4i64, Mask, V1, V2, DAG))
10466 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10467 // shuffle. However, if we have AVX2 and either inputs are already in place,
10468 // we will be able to shuffle even across lanes the other input in a single
10469 // instruction so skip this pattern.
10470 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10471 isShuffleMaskInputInPlace(1, Mask))))
10472 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10473 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10476 // Otherwise fall back on generic blend lowering.
10477 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10481 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10483 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10484 /// isn't available.
10485 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10486 const X86Subtarget *Subtarget,
10487 SelectionDAG &DAG) {
10489 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10490 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10491 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10492 ArrayRef<int> Mask = SVOp->getMask();
10493 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10495 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10499 // Check for being able to broadcast a single element.
10500 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
10501 Mask, Subtarget, DAG))
10504 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10505 // options to efficiently lower the shuffle.
10506 SmallVector<int, 4> RepeatedMask;
10507 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10508 assert(RepeatedMask.size() == 4 &&
10509 "Repeated masks must be half the mask width!");
10511 // Use even/odd duplicate instructions for masks that match their pattern.
10512 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
10513 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
10514 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
10515 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
10517 if (isSingleInputShuffleMask(Mask))
10518 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10519 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10521 // Use dedicated unpack instructions for masks that match their pattern.
10523 lowerVectorShuffleWithUNPCK(DL, MVT::v8f32, Mask, V1, V2, DAG))
10526 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10527 // have already handled any direct blends. We also need to squash the
10528 // repeated mask into a simulated v4f32 mask.
10529 for (int i = 0; i < 4; ++i)
10530 if (RepeatedMask[i] >= 8)
10531 RepeatedMask[i] -= 4;
10532 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10535 // If we have a single input shuffle with different shuffle patterns in the
10536 // two 128-bit lanes use the variable mask to VPERMILPS.
10537 if (isSingleInputShuffleMask(Mask)) {
10538 SDValue VPermMask[8];
10539 for (int i = 0; i < 8; ++i)
10540 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10541 : DAG.getConstant(Mask[i], DL, MVT::i32);
10542 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10543 return DAG.getNode(
10544 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10545 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10547 if (Subtarget->hasAVX2())
10548 return DAG.getNode(
10549 X86ISD::VPERMV, DL, MVT::v8f32,
10550 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10552 // Otherwise, fall back.
10553 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10557 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10559 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10560 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10563 // If we have AVX2 then we always want to lower with a blend because at v8 we
10564 // can fully permute the elements.
10565 if (Subtarget->hasAVX2())
10566 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10569 // Otherwise fall back on generic lowering.
10570 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10573 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10575 /// This routine is only called when we have AVX2 and thus a reasonable
10576 /// instruction set for v8i32 shuffling..
10577 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10578 const X86Subtarget *Subtarget,
10579 SelectionDAG &DAG) {
10581 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10582 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10583 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10584 ArrayRef<int> Mask = SVOp->getMask();
10585 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10586 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10588 // Whenever we can lower this as a zext, that instruction is strictly faster
10589 // than any alternative. It also allows us to fold memory operands into the
10590 // shuffle in many cases.
10591 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
10592 Mask, Subtarget, DAG))
10595 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10599 // Check for being able to broadcast a single element.
10600 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
10601 Mask, Subtarget, DAG))
10604 // If the shuffle mask is repeated in each 128-bit lane we can use more
10605 // efficient instructions that mirror the shuffles across the two 128-bit
10607 SmallVector<int, 4> RepeatedMask;
10608 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10609 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10610 if (isSingleInputShuffleMask(Mask))
10611 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10612 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10614 // Use dedicated unpack instructions for masks that match their pattern.
10616 lowerVectorShuffleWithUNPCK(DL, MVT::v8i32, Mask, V1, V2, DAG))
10620 // Try to use shift instructions.
10621 if (SDValue Shift =
10622 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
10625 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10626 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10629 // If the shuffle patterns aren't repeated but it is a single input, directly
10630 // generate a cross-lane VPERMD instruction.
10631 if (isSingleInputShuffleMask(Mask)) {
10632 SDValue VPermMask[8];
10633 for (int i = 0; i < 8; ++i)
10634 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10635 : DAG.getConstant(Mask[i], DL, MVT::i32);
10636 return DAG.getNode(
10637 X86ISD::VPERMV, DL, MVT::v8i32,
10638 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10641 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10643 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10644 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10647 // Otherwise fall back on generic blend lowering.
10648 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10652 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10654 /// This routine is only called when we have AVX2 and thus a reasonable
10655 /// instruction set for v16i16 shuffling..
10656 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10657 const X86Subtarget *Subtarget,
10658 SelectionDAG &DAG) {
10660 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10661 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10662 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10663 ArrayRef<int> Mask = SVOp->getMask();
10664 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10665 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10667 // Whenever we can lower this as a zext, that instruction is strictly faster
10668 // than any alternative. It also allows us to fold memory operands into the
10669 // shuffle in many cases.
10670 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
10671 Mask, Subtarget, DAG))
10674 // Check for being able to broadcast a single element.
10675 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
10676 Mask, Subtarget, DAG))
10679 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10683 // Use dedicated unpack instructions for masks that match their pattern.
10685 lowerVectorShuffleWithUNPCK(DL, MVT::v16i16, Mask, V1, V2, DAG))
10688 // Try to use shift instructions.
10689 if (SDValue Shift =
10690 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
10693 // Try to use byte rotation instructions.
10694 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10695 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10698 if (isSingleInputShuffleMask(Mask)) {
10699 // There are no generalized cross-lane shuffle operations available on i16
10701 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10702 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10705 SmallVector<int, 8> RepeatedMask;
10706 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
10707 // As this is a single-input shuffle, the repeated mask should be
10708 // a strictly valid v8i16 mask that we can pass through to the v8i16
10709 // lowering to handle even the v16 case.
10710 return lowerV8I16GeneralSingleInputVectorShuffle(
10711 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
10714 SDValue PSHUFBMask[32];
10715 for (int i = 0; i < 16; ++i) {
10716 if (Mask[i] == -1) {
10717 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10721 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10722 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10723 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
10724 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
10726 return DAG.getBitcast(MVT::v16i16,
10727 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
10728 DAG.getBitcast(MVT::v32i8, V1),
10729 DAG.getNode(ISD::BUILD_VECTOR, DL,
10730 MVT::v32i8, PSHUFBMask)));
10733 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10735 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10736 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10739 // Otherwise fall back on generic lowering.
10740 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10743 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10745 /// This routine is only called when we have AVX2 and thus a reasonable
10746 /// instruction set for v32i8 shuffling..
10747 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10748 const X86Subtarget *Subtarget,
10749 SelectionDAG &DAG) {
10751 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10752 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10753 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10754 ArrayRef<int> Mask = SVOp->getMask();
10755 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10756 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10758 // Whenever we can lower this as a zext, that instruction is strictly faster
10759 // than any alternative. It also allows us to fold memory operands into the
10760 // shuffle in many cases.
10761 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
10762 Mask, Subtarget, DAG))
10765 // Check for being able to broadcast a single element.
10766 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
10767 Mask, Subtarget, DAG))
10770 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10774 // Use dedicated unpack instructions for masks that match their pattern.
10776 lowerVectorShuffleWithUNPCK(DL, MVT::v32i8, Mask, V1, V2, DAG))
10779 // Try to use shift instructions.
10780 if (SDValue Shift =
10781 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10784 // Try to use byte rotation instructions.
10785 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10786 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10789 if (isSingleInputShuffleMask(Mask)) {
10790 // There are no generalized cross-lane shuffle operations available on i8
10792 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10793 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10796 SDValue PSHUFBMask[32];
10797 for (int i = 0; i < 32; ++i)
10800 ? DAG.getUNDEF(MVT::i8)
10801 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10804 return DAG.getNode(
10805 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10806 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10809 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10811 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10812 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10815 // Otherwise fall back on generic lowering.
10816 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10819 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10821 /// This routine either breaks down the specific type of a 256-bit x86 vector
10822 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10823 /// together based on the available instructions.
10824 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10825 MVT VT, const X86Subtarget *Subtarget,
10826 SelectionDAG &DAG) {
10828 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10829 ArrayRef<int> Mask = SVOp->getMask();
10831 // If we have a single input to the zero element, insert that into V1 if we
10832 // can do so cheaply.
10833 int NumElts = VT.getVectorNumElements();
10834 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10835 return M >= NumElts;
10838 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10839 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10840 DL, VT, V1, V2, Mask, Subtarget, DAG))
10843 // There is a really nice hard cut-over between AVX1 and AVX2 that means we
10844 // can check for those subtargets here and avoid much of the subtarget
10845 // querying in the per-vector-type lowering routines. With AVX1 we have
10846 // essentially *zero* ability to manipulate a 256-bit vector with integer
10847 // types. Since we'll use floating point types there eventually, just
10848 // immediately cast everything to a float and operate entirely in that domain.
10849 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10850 int ElementBits = VT.getScalarSizeInBits();
10851 if (ElementBits < 32)
10852 // No floating point type available, decompose into 128-bit vectors.
10853 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10855 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10856 VT.getVectorNumElements());
10857 V1 = DAG.getBitcast(FpVT, V1);
10858 V2 = DAG.getBitcast(FpVT, V2);
10859 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10862 switch (VT.SimpleTy) {
10864 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10866 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10868 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10870 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10872 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10874 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10877 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10881 /// \brief Try to lower a vector shuffle as a 128-bit shuffles.
10882 static SDValue lowerV4X128VectorShuffle(SDLoc DL, MVT VT,
10883 ArrayRef<int> Mask,
10884 SDValue V1, SDValue V2,
10885 SelectionDAG &DAG) {
10886 assert(VT.getScalarSizeInBits() == 64 &&
10887 "Unexpected element type size for 128bit shuffle.");
10889 // To handle 256 bit vector requires VLX and most probably
10890 // function lowerV2X128VectorShuffle() is better solution.
10891 assert(VT.is512BitVector() && "Unexpected vector size for 128bit shuffle.");
10893 SmallVector<int, 4> WidenedMask;
10894 if (!canWidenShuffleElements(Mask, WidenedMask))
10897 // Form a 128-bit permutation.
10898 // Convert the 64-bit shuffle mask selection values into 128-bit selection
10899 // bits defined by a vshuf64x2 instruction's immediate control byte.
10900 unsigned PermMask = 0, Imm = 0;
10901 unsigned ControlBitsNum = WidenedMask.size() / 2;
10903 for (int i = 0, Size = WidenedMask.size(); i < Size; ++i) {
10904 if (WidenedMask[i] == SM_SentinelZero)
10907 // Use first element in place of undef mask.
10908 Imm = (WidenedMask[i] == SM_SentinelUndef) ? 0 : WidenedMask[i];
10909 PermMask |= (Imm % WidenedMask.size()) << (i * ControlBitsNum);
10912 return DAG.getNode(X86ISD::SHUF128, DL, VT, V1, V2,
10913 DAG.getConstant(PermMask, DL, MVT::i8));
10916 static SDValue lowerVectorShuffleWithPERMV(SDLoc DL, MVT VT,
10917 ArrayRef<int> Mask, SDValue V1,
10918 SDValue V2, SelectionDAG &DAG) {
10920 assert(VT.getScalarSizeInBits() >= 16 && "Unexpected data type for PERMV");
10922 MVT MaskEltVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
10923 MVT MaskVecVT = MVT::getVectorVT(MaskEltVT, VT.getVectorNumElements());
10925 SDValue MaskNode = getConstVector(Mask, MaskVecVT, DAG, DL, true);
10926 if (isSingleInputShuffleMask(Mask))
10927 return DAG.getNode(X86ISD::VPERMV, DL, VT, MaskNode, V1);
10929 return DAG.getNode(X86ISD::VPERMV3, DL, VT, V1, MaskNode, V2);
10932 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10933 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10934 const X86Subtarget *Subtarget,
10935 SelectionDAG &DAG) {
10937 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10938 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10939 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10940 ArrayRef<int> Mask = SVOp->getMask();
10941 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10943 if (SDValue Shuf128 =
10944 lowerV4X128VectorShuffle(DL, MVT::v8f64, Mask, V1, V2, DAG))
10947 if (SDValue Unpck =
10948 lowerVectorShuffleWithUNPCK(DL, MVT::v8f64, Mask, V1, V2, DAG))
10951 return lowerVectorShuffleWithPERMV(DL, MVT::v8f64, Mask, V1, V2, DAG);
10954 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10955 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10956 const X86Subtarget *Subtarget,
10957 SelectionDAG &DAG) {
10959 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10960 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10961 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10962 ArrayRef<int> Mask = SVOp->getMask();
10963 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10965 if (SDValue Unpck =
10966 lowerVectorShuffleWithUNPCK(DL, MVT::v16f32, Mask, V1, V2, DAG))
10969 return lowerVectorShuffleWithPERMV(DL, MVT::v16f32, Mask, V1, V2, DAG);
10972 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10973 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10974 const X86Subtarget *Subtarget,
10975 SelectionDAG &DAG) {
10977 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10978 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10979 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10980 ArrayRef<int> Mask = SVOp->getMask();
10981 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10983 if (SDValue Shuf128 =
10984 lowerV4X128VectorShuffle(DL, MVT::v8i64, Mask, V1, V2, DAG))
10987 if (SDValue Unpck =
10988 lowerVectorShuffleWithUNPCK(DL, MVT::v8i64, Mask, V1, V2, DAG))
10991 return lowerVectorShuffleWithPERMV(DL, MVT::v8i64, Mask, V1, V2, DAG);
10994 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10995 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10996 const X86Subtarget *Subtarget,
10997 SelectionDAG &DAG) {
10999 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
11000 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
11001 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11002 ArrayRef<int> Mask = SVOp->getMask();
11003 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
11005 if (SDValue Unpck =
11006 lowerVectorShuffleWithUNPCK(DL, MVT::v16i32, Mask, V1, V2, DAG))
11009 return lowerVectorShuffleWithPERMV(DL, MVT::v16i32, Mask, V1, V2, DAG);
11012 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
11013 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11014 const X86Subtarget *Subtarget,
11015 SelectionDAG &DAG) {
11017 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
11018 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
11019 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11020 ArrayRef<int> Mask = SVOp->getMask();
11021 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
11022 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
11024 return lowerVectorShuffleWithPERMV(DL, MVT::v32i16, Mask, V1, V2, DAG);
11027 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
11028 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11029 const X86Subtarget *Subtarget,
11030 SelectionDAG &DAG) {
11032 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
11033 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
11034 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11035 ArrayRef<int> Mask = SVOp->getMask();
11036 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
11037 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
11039 // FIXME: Implement direct support for this type!
11040 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
11043 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
11045 /// This routine either breaks down the specific type of a 512-bit x86 vector
11046 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
11047 /// together based on the available instructions.
11048 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11049 MVT VT, const X86Subtarget *Subtarget,
11050 SelectionDAG &DAG) {
11052 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11053 ArrayRef<int> Mask = SVOp->getMask();
11054 assert(Subtarget->hasAVX512() &&
11055 "Cannot lower 512-bit vectors w/ basic ISA!");
11057 // Check for being able to broadcast a single element.
11058 if (SDValue Broadcast =
11059 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
11062 // Dispatch to each element type for lowering. If we don't have supprot for
11063 // specific element type shuffles at 512 bits, immediately split them and
11064 // lower them. Each lowering routine of a given type is allowed to assume that
11065 // the requisite ISA extensions for that element type are available.
11066 switch (VT.SimpleTy) {
11068 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
11070 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
11072 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
11074 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
11076 if (Subtarget->hasBWI())
11077 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
11080 if (Subtarget->hasBWI())
11081 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
11085 llvm_unreachable("Not a valid 512-bit x86 vector type!");
11088 // Otherwise fall back on splitting.
11089 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
11092 // Lower vXi1 vector shuffles.
11093 // There is no a dedicated instruction on AVX-512 that shuffles the masks.
11094 // The only way to shuffle bits is to sign-extend the mask vector to SIMD
11095 // vector, shuffle and then truncate it back.
11096 static SDValue lower1BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11097 MVT VT, const X86Subtarget *Subtarget,
11098 SelectionDAG &DAG) {
11100 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11101 ArrayRef<int> Mask = SVOp->getMask();
11102 assert(Subtarget->hasAVX512() &&
11103 "Cannot lower 512-bit vectors w/o basic ISA!");
11105 switch (VT.SimpleTy) {
11107 llvm_unreachable("Expected a vector of i1 elements");
11109 ExtVT = MVT::v2i64;
11112 ExtVT = MVT::v4i32;
11115 ExtVT = MVT::v8i64; // Take 512-bit type, more shuffles on KNL
11118 ExtVT = MVT::v16i32;
11121 ExtVT = MVT::v32i16;
11124 ExtVT = MVT::v64i8;
11128 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11129 V1 = getZeroVector(ExtVT, Subtarget, DAG, DL);
11130 else if (ISD::isBuildVectorAllOnes(V1.getNode()))
11131 V1 = getOnesVector(ExtVT, Subtarget, DAG, DL);
11133 V1 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V1);
11136 V2 = DAG.getUNDEF(ExtVT);
11137 else if (ISD::isBuildVectorAllZeros(V2.getNode()))
11138 V2 = getZeroVector(ExtVT, Subtarget, DAG, DL);
11139 else if (ISD::isBuildVectorAllOnes(V2.getNode()))
11140 V2 = getOnesVector(ExtVT, Subtarget, DAG, DL);
11142 V2 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V2);
11143 return DAG.getNode(ISD::TRUNCATE, DL, VT,
11144 DAG.getVectorShuffle(ExtVT, DL, V1, V2, Mask));
11146 /// \brief Top-level lowering for x86 vector shuffles.
11148 /// This handles decomposition, canonicalization, and lowering of all x86
11149 /// vector shuffles. Most of the specific lowering strategies are encapsulated
11150 /// above in helper routines. The canonicalization attempts to widen shuffles
11151 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
11152 /// s.t. only one of the two inputs needs to be tested, etc.
11153 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11154 SelectionDAG &DAG) {
11155 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11156 ArrayRef<int> Mask = SVOp->getMask();
11157 SDValue V1 = Op.getOperand(0);
11158 SDValue V2 = Op.getOperand(1);
11159 MVT VT = Op.getSimpleValueType();
11160 int NumElements = VT.getVectorNumElements();
11162 bool Is1BitVector = (VT.getVectorElementType() == MVT::i1);
11164 assert((VT.getSizeInBits() != 64 || Is1BitVector) &&
11165 "Can't lower MMX shuffles");
11167 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11168 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11169 if (V1IsUndef && V2IsUndef)
11170 return DAG.getUNDEF(VT);
11172 // When we create a shuffle node we put the UNDEF node to second operand,
11173 // but in some cases the first operand may be transformed to UNDEF.
11174 // In this case we should just commute the node.
11176 return DAG.getCommutedVectorShuffle(*SVOp);
11178 // Check for non-undef masks pointing at an undef vector and make the masks
11179 // undef as well. This makes it easier to match the shuffle based solely on
11183 if (M >= NumElements) {
11184 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
11185 for (int &M : NewMask)
11186 if (M >= NumElements)
11188 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
11191 // We actually see shuffles that are entirely re-arrangements of a set of
11192 // zero inputs. This mostly happens while decomposing complex shuffles into
11193 // simple ones. Directly lower these as a buildvector of zeros.
11194 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
11195 if (Zeroable.all())
11196 return getZeroVector(VT, Subtarget, DAG, dl);
11198 // Try to collapse shuffles into using a vector type with fewer elements but
11199 // wider element types. We cap this to not form integers or floating point
11200 // elements wider than 64 bits, but it might be interesting to form i128
11201 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
11202 SmallVector<int, 16> WidenedMask;
11203 if (VT.getScalarSizeInBits() < 64 && !Is1BitVector &&
11204 canWidenShuffleElements(Mask, WidenedMask)) {
11205 MVT NewEltVT = VT.isFloatingPoint()
11206 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
11207 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
11208 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
11209 // Make sure that the new vector type is legal. For example, v2f64 isn't
11211 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
11212 V1 = DAG.getBitcast(NewVT, V1);
11213 V2 = DAG.getBitcast(NewVT, V2);
11214 return DAG.getBitcast(
11215 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
11219 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
11220 for (int M : SVOp->getMask())
11222 ++NumUndefElements;
11223 else if (M < NumElements)
11228 // Commute the shuffle as needed such that more elements come from V1 than
11229 // V2. This allows us to match the shuffle pattern strictly on how many
11230 // elements come from V1 without handling the symmetric cases.
11231 if (NumV2Elements > NumV1Elements)
11232 return DAG.getCommutedVectorShuffle(*SVOp);
11234 // When the number of V1 and V2 elements are the same, try to minimize the
11235 // number of uses of V2 in the low half of the vector. When that is tied,
11236 // ensure that the sum of indices for V1 is equal to or lower than the sum
11237 // indices for V2. When those are equal, try to ensure that the number of odd
11238 // indices for V1 is lower than the number of odd indices for V2.
11239 if (NumV1Elements == NumV2Elements) {
11240 int LowV1Elements = 0, LowV2Elements = 0;
11241 for (int M : SVOp->getMask().slice(0, NumElements / 2))
11242 if (M >= NumElements)
11246 if (LowV2Elements > LowV1Elements) {
11247 return DAG.getCommutedVectorShuffle(*SVOp);
11248 } else if (LowV2Elements == LowV1Elements) {
11249 int SumV1Indices = 0, SumV2Indices = 0;
11250 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11251 if (SVOp->getMask()[i] >= NumElements)
11253 else if (SVOp->getMask()[i] >= 0)
11255 if (SumV2Indices < SumV1Indices) {
11256 return DAG.getCommutedVectorShuffle(*SVOp);
11257 } else if (SumV2Indices == SumV1Indices) {
11258 int NumV1OddIndices = 0, NumV2OddIndices = 0;
11259 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11260 if (SVOp->getMask()[i] >= NumElements)
11261 NumV2OddIndices += i % 2;
11262 else if (SVOp->getMask()[i] >= 0)
11263 NumV1OddIndices += i % 2;
11264 if (NumV2OddIndices < NumV1OddIndices)
11265 return DAG.getCommutedVectorShuffle(*SVOp);
11270 // For each vector width, delegate to a specialized lowering routine.
11271 if (VT.is128BitVector())
11272 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11274 if (VT.is256BitVector())
11275 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11277 if (VT.is512BitVector())
11278 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11281 return lower1BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11282 llvm_unreachable("Unimplemented!");
11285 // This function assumes its argument is a BUILD_VECTOR of constants or
11286 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11288 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11289 unsigned &MaskValue) {
11291 unsigned NumElems = BuildVector->getNumOperands();
11293 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11294 // We don't handle the >2 lanes case right now.
11295 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11299 unsigned NumElemsInLane = NumElems / NumLanes;
11301 // Blend for v16i16 should be symmetric for the both lanes.
11302 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11303 SDValue EltCond = BuildVector->getOperand(i);
11304 SDValue SndLaneEltCond =
11305 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11307 int Lane1Cond = -1, Lane2Cond = -1;
11308 if (isa<ConstantSDNode>(EltCond))
11309 Lane1Cond = !isNullConstant(EltCond);
11310 if (isa<ConstantSDNode>(SndLaneEltCond))
11311 Lane2Cond = !isNullConstant(SndLaneEltCond);
11313 unsigned LaneMask = 0;
11314 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11315 // Lane1Cond != 0, means we want the first argument.
11316 // Lane1Cond == 0, means we want the second argument.
11317 // The encoding of this argument is 0 for the first argument, 1
11318 // for the second. Therefore, invert the condition.
11319 LaneMask = !Lane1Cond << i;
11320 else if (Lane1Cond < 0)
11321 LaneMask = !Lane2Cond << i;
11325 MaskValue |= LaneMask;
11327 MaskValue |= LaneMask << NumElemsInLane;
11332 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
11333 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
11334 const X86Subtarget *Subtarget,
11335 SelectionDAG &DAG) {
11336 SDValue Cond = Op.getOperand(0);
11337 SDValue LHS = Op.getOperand(1);
11338 SDValue RHS = Op.getOperand(2);
11340 MVT VT = Op.getSimpleValueType();
11342 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11344 auto *CondBV = cast<BuildVectorSDNode>(Cond);
11346 // Only non-legal VSELECTs reach this lowering, convert those into generic
11347 // shuffles and re-use the shuffle lowering path for blends.
11348 SmallVector<int, 32> Mask;
11349 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
11350 SDValue CondElt = CondBV->getOperand(i);
11352 isa<ConstantSDNode>(CondElt) ? i + (isNullConstant(CondElt) ? Size : 0)
11355 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
11358 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11359 // A vselect where all conditions and data are constants can be optimized into
11360 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11361 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11362 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11363 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11366 // Try to lower this to a blend-style vector shuffle. This can handle all
11367 // constant condition cases.
11368 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
11371 // Variable blends are only legal from SSE4.1 onward.
11372 if (!Subtarget->hasSSE41())
11375 // Only some types will be legal on some subtargets. If we can emit a legal
11376 // VSELECT-matching blend, return Op, and but if we need to expand, return
11378 switch (Op.getSimpleValueType().SimpleTy) {
11380 // Most of the vector types have blends past SSE4.1.
11384 // The byte blends for AVX vectors were introduced only in AVX2.
11385 if (Subtarget->hasAVX2())
11392 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
11393 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11396 // FIXME: We should custom lower this by fixing the condition and using i8
11402 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11403 MVT VT = Op.getSimpleValueType();
11406 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11409 if (VT.getSizeInBits() == 8) {
11410 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11411 Op.getOperand(0), Op.getOperand(1));
11412 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11413 DAG.getValueType(VT));
11414 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11417 if (VT.getSizeInBits() == 16) {
11418 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11419 if (isNullConstant(Op.getOperand(1)))
11420 return DAG.getNode(
11421 ISD::TRUNCATE, dl, MVT::i16,
11422 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11423 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11424 Op.getOperand(1)));
11425 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11426 Op.getOperand(0), Op.getOperand(1));
11427 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11428 DAG.getValueType(VT));
11429 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11432 if (VT == MVT::f32) {
11433 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11434 // the result back to FR32 register. It's only worth matching if the
11435 // result has a single use which is a store or a bitcast to i32. And in
11436 // the case of a store, it's not worth it if the index is a constant 0,
11437 // because a MOVSSmr can be used instead, which is smaller and faster.
11438 if (!Op.hasOneUse())
11440 SDNode *User = *Op.getNode()->use_begin();
11441 if ((User->getOpcode() != ISD::STORE ||
11442 isNullConstant(Op.getOperand(1))) &&
11443 (User->getOpcode() != ISD::BITCAST ||
11444 User->getValueType(0) != MVT::i32))
11446 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11447 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11449 return DAG.getBitcast(MVT::f32, Extract);
11452 if (VT == MVT::i32 || VT == MVT::i64) {
11453 // ExtractPS/pextrq works with constant index.
11454 if (isa<ConstantSDNode>(Op.getOperand(1)))
11460 /// Extract one bit from mask vector, like v16i1 or v8i1.
11461 /// AVX-512 feature.
11463 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11464 SDValue Vec = Op.getOperand(0);
11466 MVT VecVT = Vec.getSimpleValueType();
11467 SDValue Idx = Op.getOperand(1);
11468 MVT EltVT = Op.getSimpleValueType();
11470 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11471 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
11472 "Unexpected vector type in ExtractBitFromMaskVector");
11474 // variable index can't be handled in mask registers,
11475 // extend vector to VR512
11476 if (!isa<ConstantSDNode>(Idx)) {
11477 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11478 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11479 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11480 ExtVT.getVectorElementType(), Ext, Idx);
11481 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11484 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11485 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11486 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
11487 rc = getRegClassFor(MVT::v16i1);
11488 unsigned MaxSift = rc->getSize()*8 - 1;
11489 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11490 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
11491 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11492 DAG.getConstant(MaxSift, dl, MVT::i8));
11493 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11494 DAG.getIntPtrConstant(0, dl));
11498 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11499 SelectionDAG &DAG) const {
11501 SDValue Vec = Op.getOperand(0);
11502 MVT VecVT = Vec.getSimpleValueType();
11503 SDValue Idx = Op.getOperand(1);
11505 if (Op.getSimpleValueType() == MVT::i1)
11506 return ExtractBitFromMaskVector(Op, DAG);
11508 if (!isa<ConstantSDNode>(Idx)) {
11509 if (VecVT.is512BitVector() ||
11510 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11511 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11514 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11515 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11516 MaskEltVT.getSizeInBits());
11518 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11519 auto PtrVT = getPointerTy(DAG.getDataLayout());
11520 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11521 getZeroVector(MaskVT, Subtarget, DAG, dl), Idx,
11522 DAG.getConstant(0, dl, PtrVT));
11523 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11524 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Perm,
11525 DAG.getConstant(0, dl, PtrVT));
11530 // If this is a 256-bit vector result, first extract the 128-bit vector and
11531 // then extract the element from the 128-bit vector.
11532 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11534 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11535 // Get the 128-bit vector.
11536 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11537 MVT EltVT = VecVT.getVectorElementType();
11539 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11540 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
11542 // Find IdxVal modulo ElemsPerChunk. Since ElemsPerChunk is a power of 2
11543 // this can be done with a mask.
11544 IdxVal &= ElemsPerChunk - 1;
11545 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11546 DAG.getConstant(IdxVal, dl, MVT::i32));
11549 assert(VecVT.is128BitVector() && "Unexpected vector length");
11551 if (Subtarget->hasSSE41())
11552 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG))
11555 MVT VT = Op.getSimpleValueType();
11556 // TODO: handle v16i8.
11557 if (VT.getSizeInBits() == 16) {
11558 SDValue Vec = Op.getOperand(0);
11559 if (isNullConstant(Op.getOperand(1)))
11560 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11561 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11562 DAG.getBitcast(MVT::v4i32, Vec),
11563 Op.getOperand(1)));
11564 // Transform it so it match pextrw which produces a 32-bit result.
11565 MVT EltVT = MVT::i32;
11566 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11567 Op.getOperand(0), Op.getOperand(1));
11568 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11569 DAG.getValueType(VT));
11570 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11573 if (VT.getSizeInBits() == 32) {
11574 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11578 // SHUFPS the element to the lowest double word, then movss.
11579 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11580 MVT VVT = Op.getOperand(0).getSimpleValueType();
11581 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11582 DAG.getUNDEF(VVT), Mask);
11583 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11584 DAG.getIntPtrConstant(0, dl));
11587 if (VT.getSizeInBits() == 64) {
11588 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11589 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11590 // to match extract_elt for f64.
11591 if (isNullConstant(Op.getOperand(1)))
11594 // UNPCKHPD the element to the lowest double word, then movsd.
11595 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11596 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11597 int Mask[2] = { 1, -1 };
11598 MVT VVT = Op.getOperand(0).getSimpleValueType();
11599 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11600 DAG.getUNDEF(VVT), Mask);
11601 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11602 DAG.getIntPtrConstant(0, dl));
11608 /// Insert one bit to mask vector, like v16i1 or v8i1.
11609 /// AVX-512 feature.
11611 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11613 SDValue Vec = Op.getOperand(0);
11614 SDValue Elt = Op.getOperand(1);
11615 SDValue Idx = Op.getOperand(2);
11616 MVT VecVT = Vec.getSimpleValueType();
11618 if (!isa<ConstantSDNode>(Idx)) {
11619 // Non constant index. Extend source and destination,
11620 // insert element and then truncate the result.
11621 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11622 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11623 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11624 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11625 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11626 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11629 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11630 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11632 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11633 DAG.getConstant(IdxVal, dl, MVT::i8));
11634 if (Vec.getOpcode() == ISD::UNDEF)
11636 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11639 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11640 SelectionDAG &DAG) const {
11641 MVT VT = Op.getSimpleValueType();
11642 MVT EltVT = VT.getVectorElementType();
11644 if (EltVT == MVT::i1)
11645 return InsertBitToMaskVector(Op, DAG);
11648 SDValue N0 = Op.getOperand(0);
11649 SDValue N1 = Op.getOperand(1);
11650 SDValue N2 = Op.getOperand(2);
11651 if (!isa<ConstantSDNode>(N2))
11653 auto *N2C = cast<ConstantSDNode>(N2);
11654 unsigned IdxVal = N2C->getZExtValue();
11656 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11657 // into that, and then insert the subvector back into the result.
11658 if (VT.is256BitVector() || VT.is512BitVector()) {
11659 // With a 256-bit vector, we can insert into the zero element efficiently
11660 // using a blend if we have AVX or AVX2 and the right data type.
11661 if (VT.is256BitVector() && IdxVal == 0) {
11662 // TODO: It is worthwhile to cast integer to floating point and back
11663 // and incur a domain crossing penalty if that's what we'll end up
11664 // doing anyway after extracting to a 128-bit vector.
11665 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
11666 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
11667 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
11668 N2 = DAG.getIntPtrConstant(1, dl);
11669 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
11673 // Get the desired 128-bit vector chunk.
11674 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11676 // Insert the element into the desired chunk.
11677 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11678 assert(isPowerOf2_32(NumEltsIn128));
11679 // Since NumEltsIn128 is a power of 2 we can use mask instead of modulo.
11680 unsigned IdxIn128 = IdxVal & (NumEltsIn128 - 1);
11682 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11683 DAG.getConstant(IdxIn128, dl, MVT::i32));
11685 // Insert the changed part back into the bigger vector
11686 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11688 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11690 if (Subtarget->hasSSE41()) {
11691 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11693 if (VT == MVT::v8i16) {
11694 Opc = X86ISD::PINSRW;
11696 assert(VT == MVT::v16i8);
11697 Opc = X86ISD::PINSRB;
11700 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11702 if (N1.getValueType() != MVT::i32)
11703 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11704 if (N2.getValueType() != MVT::i32)
11705 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11706 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11709 if (EltVT == MVT::f32) {
11710 // Bits [7:6] of the constant are the source select. This will always be
11711 // zero here. The DAG Combiner may combine an extract_elt index into
11712 // these bits. For example (insert (extract, 3), 2) could be matched by
11713 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
11714 // Bits [5:4] of the constant are the destination select. This is the
11715 // value of the incoming immediate.
11716 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11717 // combine either bitwise AND or insert of float 0.0 to set these bits.
11719 bool MinSize = DAG.getMachineFunction().getFunction()->optForMinSize();
11720 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
11721 // If this is an insertion of 32-bits into the low 32-bits of
11722 // a vector, we prefer to generate a blend with immediate rather
11723 // than an insertps. Blends are simpler operations in hardware and so
11724 // will always have equal or better performance than insertps.
11725 // But if optimizing for size and there's a load folding opportunity,
11726 // generate insertps because blendps does not have a 32-bit memory
11728 N2 = DAG.getIntPtrConstant(1, dl);
11729 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11730 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
11732 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
11733 // Create this as a scalar to vector..
11734 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11735 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11738 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11739 // PINSR* works with constant index.
11744 if (EltVT == MVT::i8)
11747 if (EltVT.getSizeInBits() == 16) {
11748 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11749 // as its second argument.
11750 if (N1.getValueType() != MVT::i32)
11751 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11752 if (N2.getValueType() != MVT::i32)
11753 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11754 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11759 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11761 MVT OpVT = Op.getSimpleValueType();
11763 // If this is a 256-bit vector result, first insert into a 128-bit
11764 // vector and then insert into the 256-bit vector.
11765 if (!OpVT.is128BitVector()) {
11766 // Insert into a 128-bit vector.
11767 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11768 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11769 OpVT.getVectorNumElements() / SizeFactor);
11771 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11773 // Insert the 128-bit vector.
11774 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11777 if (OpVT == MVT::v1i64 &&
11778 Op.getOperand(0).getValueType() == MVT::i64)
11779 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11781 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11782 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11783 return DAG.getBitcast(
11784 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
11787 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11788 // a simple subregister reference or explicit instructions to grab
11789 // upper bits of a vector.
11790 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11791 SelectionDAG &DAG) {
11793 SDValue In = Op.getOperand(0);
11794 SDValue Idx = Op.getOperand(1);
11795 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11796 MVT ResVT = Op.getSimpleValueType();
11797 MVT InVT = In.getSimpleValueType();
11799 if (Subtarget->hasFp256()) {
11800 if (ResVT.is128BitVector() &&
11801 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11802 isa<ConstantSDNode>(Idx)) {
11803 return Extract128BitVector(In, IdxVal, DAG, dl);
11805 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11806 isa<ConstantSDNode>(Idx)) {
11807 return Extract256BitVector(In, IdxVal, DAG, dl);
11813 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11814 // simple superregister reference or explicit instructions to insert
11815 // the upper bits of a vector.
11816 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11817 SelectionDAG &DAG) {
11818 if (!Subtarget->hasAVX())
11822 SDValue Vec = Op.getOperand(0);
11823 SDValue SubVec = Op.getOperand(1);
11824 SDValue Idx = Op.getOperand(2);
11826 if (!isa<ConstantSDNode>(Idx))
11829 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11830 MVT OpVT = Op.getSimpleValueType();
11831 MVT SubVecVT = SubVec.getSimpleValueType();
11833 // Fold two 16-byte subvector loads into one 32-byte load:
11834 // (insert_subvector (insert_subvector undef, (load addr), 0),
11835 // (load addr + 16), Elts/2)
11837 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
11838 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
11839 OpVT.is256BitVector() && SubVecVT.is128BitVector()) {
11840 auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2));
11841 if (Idx2 && Idx2->getZExtValue() == 0) {
11842 SDValue SubVec2 = Vec.getOperand(1);
11843 // If needed, look through a bitcast to get to the load.
11844 if (SubVec2.getNode() && SubVec2.getOpcode() == ISD::BITCAST)
11845 SubVec2 = SubVec2.getOperand(0);
11847 if (auto *FirstLd = dyn_cast<LoadSDNode>(SubVec2)) {
11849 unsigned Alignment = FirstLd->getAlignment();
11850 unsigned AS = FirstLd->getAddressSpace();
11851 const X86TargetLowering *TLI = Subtarget->getTargetLowering();
11852 if (TLI->allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(),
11853 OpVT, AS, Alignment, &Fast) && Fast) {
11854 SDValue Ops[] = { SubVec2, SubVec };
11855 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))
11862 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
11863 SubVecVT.is128BitVector())
11864 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11866 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
11867 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11869 if (OpVT.getVectorElementType() == MVT::i1)
11870 return Insert1BitVector(Op, DAG);
11875 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11876 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11877 // one of the above mentioned nodes. It has to be wrapped because otherwise
11878 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11879 // be used to form addressing mode. These wrapped nodes will be selected
11882 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11883 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11885 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11886 // global base reg.
11887 unsigned char OpFlag = 0;
11888 unsigned WrapperKind = X86ISD::Wrapper;
11889 CodeModel::Model M = DAG.getTarget().getCodeModel();
11891 if (Subtarget->isPICStyleRIPRel() &&
11892 (M == CodeModel::Small || M == CodeModel::Kernel))
11893 WrapperKind = X86ISD::WrapperRIP;
11894 else if (Subtarget->isPICStyleGOT())
11895 OpFlag = X86II::MO_GOTOFF;
11896 else if (Subtarget->isPICStyleStubPIC())
11897 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11899 auto PtrVT = getPointerTy(DAG.getDataLayout());
11900 SDValue Result = DAG.getTargetConstantPool(
11901 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(), OpFlag);
11903 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11904 // With PIC, the address is actually $g + Offset.
11907 DAG.getNode(ISD::ADD, DL, PtrVT,
11908 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11914 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11915 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11917 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11918 // global base reg.
11919 unsigned char OpFlag = 0;
11920 unsigned WrapperKind = X86ISD::Wrapper;
11921 CodeModel::Model M = DAG.getTarget().getCodeModel();
11923 if (Subtarget->isPICStyleRIPRel() &&
11924 (M == CodeModel::Small || M == CodeModel::Kernel))
11925 WrapperKind = X86ISD::WrapperRIP;
11926 else if (Subtarget->isPICStyleGOT())
11927 OpFlag = X86II::MO_GOTOFF;
11928 else if (Subtarget->isPICStyleStubPIC())
11929 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11931 auto PtrVT = getPointerTy(DAG.getDataLayout());
11932 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
11934 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11936 // With PIC, the address is actually $g + Offset.
11939 DAG.getNode(ISD::ADD, DL, PtrVT,
11940 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11946 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11947 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11949 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11950 // global base reg.
11951 unsigned char OpFlag = 0;
11952 unsigned WrapperKind = X86ISD::Wrapper;
11953 CodeModel::Model M = DAG.getTarget().getCodeModel();
11955 if (Subtarget->isPICStyleRIPRel() &&
11956 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11957 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11958 OpFlag = X86II::MO_GOTPCREL;
11959 WrapperKind = X86ISD::WrapperRIP;
11960 } else if (Subtarget->isPICStyleGOT()) {
11961 OpFlag = X86II::MO_GOT;
11962 } else if (Subtarget->isPICStyleStubPIC()) {
11963 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11964 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11965 OpFlag = X86II::MO_DARWIN_NONLAZY;
11968 auto PtrVT = getPointerTy(DAG.getDataLayout());
11969 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
11972 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11974 // With PIC, the address is actually $g + Offset.
11975 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11976 !Subtarget->is64Bit()) {
11978 DAG.getNode(ISD::ADD, DL, PtrVT,
11979 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11982 // For symbols that require a load from a stub to get the address, emit the
11984 if (isGlobalStubReference(OpFlag))
11985 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
11986 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11987 false, false, false, 0);
11993 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11994 // Create the TargetBlockAddressAddress node.
11995 unsigned char OpFlags =
11996 Subtarget->ClassifyBlockAddressReference();
11997 CodeModel::Model M = DAG.getTarget().getCodeModel();
11998 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11999 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
12001 auto PtrVT = getPointerTy(DAG.getDataLayout());
12002 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
12004 if (Subtarget->isPICStyleRIPRel() &&
12005 (M == CodeModel::Small || M == CodeModel::Kernel))
12006 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
12008 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
12010 // With PIC, the address is actually $g + Offset.
12011 if (isGlobalRelativeToPICBase(OpFlags)) {
12012 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
12013 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
12020 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
12021 int64_t Offset, SelectionDAG &DAG) const {
12022 // Create the TargetGlobalAddress node, folding in the constant
12023 // offset if it is legal.
12024 unsigned char OpFlags =
12025 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
12026 CodeModel::Model M = DAG.getTarget().getCodeModel();
12027 auto PtrVT = getPointerTy(DAG.getDataLayout());
12029 if (OpFlags == X86II::MO_NO_FLAG &&
12030 X86::isOffsetSuitableForCodeModel(Offset, M)) {
12031 // A direct static reference to a global.
12032 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
12035 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, OpFlags);
12038 if (Subtarget->isPICStyleRIPRel() &&
12039 (M == CodeModel::Small || M == CodeModel::Kernel))
12040 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
12042 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
12044 // With PIC, the address is actually $g + Offset.
12045 if (isGlobalRelativeToPICBase(OpFlags)) {
12046 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
12047 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
12050 // For globals that require a load from a stub to get the address, emit the
12052 if (isGlobalStubReference(OpFlags))
12053 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
12054 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12055 false, false, false, 0);
12057 // If there was a non-zero offset that we didn't fold, create an explicit
12058 // addition for it.
12060 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result,
12061 DAG.getConstant(Offset, dl, PtrVT));
12067 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12068 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12069 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12070 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12074 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12075 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12076 unsigned char OperandFlags, bool LocalDynamic = false) {
12077 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12078 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12080 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12081 GA->getValueType(0),
12085 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12089 SDValue Ops[] = { Chain, TGA, *InFlag };
12090 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12092 SDValue Ops[] = { Chain, TGA };
12093 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12096 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12097 MFI->setAdjustsStack(true);
12098 MFI->setHasCalls(true);
12100 SDValue Flag = Chain.getValue(1);
12101 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12104 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12106 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12109 SDLoc dl(GA); // ? function entry point might be better
12110 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12111 DAG.getNode(X86ISD::GlobalBaseReg,
12112 SDLoc(), PtrVT), InFlag);
12113 InFlag = Chain.getValue(1);
12115 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12118 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12120 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12122 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12123 X86::RAX, X86II::MO_TLSGD);
12126 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12132 // Get the start address of the TLS block for this module.
12133 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12134 .getInfo<X86MachineFunctionInfo>();
12135 MFI->incNumLocalDynamicTLSAccesses();
12139 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12140 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12143 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12144 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12145 InFlag = Chain.getValue(1);
12146 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12147 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12150 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12154 unsigned char OperandFlags = X86II::MO_DTPOFF;
12155 unsigned WrapperKind = X86ISD::Wrapper;
12156 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12157 GA->getValueType(0),
12158 GA->getOffset(), OperandFlags);
12159 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12161 // Add x@dtpoff with the base.
12162 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12165 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12166 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12167 const EVT PtrVT, TLSModel::Model model,
12168 bool is64Bit, bool isPIC) {
12171 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12172 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12173 is64Bit ? 257 : 256));
12175 SDValue ThreadPointer =
12176 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
12177 MachinePointerInfo(Ptr), false, false, false, 0);
12179 unsigned char OperandFlags = 0;
12180 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12182 unsigned WrapperKind = X86ISD::Wrapper;
12183 if (model == TLSModel::LocalExec) {
12184 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12185 } else if (model == TLSModel::InitialExec) {
12187 OperandFlags = X86II::MO_GOTTPOFF;
12188 WrapperKind = X86ISD::WrapperRIP;
12190 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12193 llvm_unreachable("Unexpected model");
12196 // emit "addl x@ntpoff,%eax" (local exec)
12197 // or "addl x@indntpoff,%eax" (initial exec)
12198 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12200 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12201 GA->getOffset(), OperandFlags);
12202 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12204 if (model == TLSModel::InitialExec) {
12205 if (isPIC && !is64Bit) {
12206 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12207 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12211 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12212 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12213 false, false, false, 0);
12216 // The address of the thread local variable is the add of the thread
12217 // pointer with the offset of the variable.
12218 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12222 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12224 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12225 const GlobalValue *GV = GA->getGlobal();
12226 auto PtrVT = getPointerTy(DAG.getDataLayout());
12228 if (Subtarget->isTargetELF()) {
12229 if (DAG.getTarget().Options.EmulatedTLS)
12230 return LowerToTLSEmulatedModel(GA, DAG);
12231 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12233 case TLSModel::GeneralDynamic:
12234 if (Subtarget->is64Bit())
12235 return LowerToTLSGeneralDynamicModel64(GA, DAG, PtrVT);
12236 return LowerToTLSGeneralDynamicModel32(GA, DAG, PtrVT);
12237 case TLSModel::LocalDynamic:
12238 return LowerToTLSLocalDynamicModel(GA, DAG, PtrVT,
12239 Subtarget->is64Bit());
12240 case TLSModel::InitialExec:
12241 case TLSModel::LocalExec:
12242 return LowerToTLSExecModel(GA, DAG, PtrVT, model, Subtarget->is64Bit(),
12243 DAG.getTarget().getRelocationModel() ==
12246 llvm_unreachable("Unknown TLS model.");
12249 if (Subtarget->isTargetDarwin()) {
12250 // Darwin only has one model of TLS. Lower to that.
12251 unsigned char OpFlag = 0;
12252 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12253 X86ISD::WrapperRIP : X86ISD::Wrapper;
12255 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12256 // global base reg.
12257 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12258 !Subtarget->is64Bit();
12260 OpFlag = X86II::MO_TLVP_PIC_BASE;
12262 OpFlag = X86II::MO_TLVP;
12264 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12265 GA->getValueType(0),
12266 GA->getOffset(), OpFlag);
12267 SDValue Offset = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12269 // With PIC32, the address is actually $g + Offset.
12271 Offset = DAG.getNode(ISD::ADD, DL, PtrVT,
12272 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12275 // Lowering the machine isd will make sure everything is in the right
12277 SDValue Chain = DAG.getEntryNode();
12278 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12279 SDValue Args[] = { Chain, Offset };
12280 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12282 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12283 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12284 MFI->setAdjustsStack(true);
12286 // And our return value (tls address) is in the standard call return value
12288 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12289 return DAG.getCopyFromReg(Chain, DL, Reg, PtrVT, Chain.getValue(1));
12292 if (Subtarget->isTargetKnownWindowsMSVC() ||
12293 Subtarget->isTargetWindowsGNU()) {
12294 // Just use the implicit TLS architecture
12295 // Need to generate someting similar to:
12296 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12298 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12299 // mov rcx, qword [rdx+rcx*8]
12300 // mov eax, .tls$:tlsvar
12301 // [rax+rcx] contains the address
12302 // Windows 64bit: gs:0x58
12303 // Windows 32bit: fs:__tls_array
12306 SDValue Chain = DAG.getEntryNode();
12308 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12309 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12310 // use its literal value of 0x2C.
12311 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12312 ? Type::getInt8PtrTy(*DAG.getContext(),
12314 : Type::getInt32PtrTy(*DAG.getContext(),
12317 SDValue TlsArray = Subtarget->is64Bit()
12318 ? DAG.getIntPtrConstant(0x58, dl)
12319 : (Subtarget->isTargetWindowsGNU()
12320 ? DAG.getIntPtrConstant(0x2C, dl)
12321 : DAG.getExternalSymbol("_tls_array", PtrVT));
12323 SDValue ThreadPointer =
12324 DAG.getLoad(PtrVT, dl, Chain, TlsArray, MachinePointerInfo(Ptr), false,
12328 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
12329 res = ThreadPointer;
12331 // Load the _tls_index variable
12332 SDValue IDX = DAG.getExternalSymbol("_tls_index", PtrVT);
12333 if (Subtarget->is64Bit())
12334 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, IDX,
12335 MachinePointerInfo(), MVT::i32, false, false,
12338 IDX = DAG.getLoad(PtrVT, dl, Chain, IDX, MachinePointerInfo(), false,
12341 auto &DL = DAG.getDataLayout();
12343 DAG.getConstant(Log2_64_Ceil(DL.getPointerSize()), dl, PtrVT);
12344 IDX = DAG.getNode(ISD::SHL, dl, PtrVT, IDX, Scale);
12346 res = DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, IDX);
12349 res = DAG.getLoad(PtrVT, dl, Chain, res, MachinePointerInfo(), false, false,
12352 // Get the offset of start of .tls section
12353 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12354 GA->getValueType(0),
12355 GA->getOffset(), X86II::MO_SECREL);
12356 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
12358 // The address of the thread local variable is the add of the thread
12359 // pointer with the offset of the variable.
12360 return DAG.getNode(ISD::ADD, dl, PtrVT, res, Offset);
12363 llvm_unreachable("TLS not implemented for this target.");
12366 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12367 /// and take a 2 x i32 value to shift plus a shift amount.
12368 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12369 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12370 MVT VT = Op.getSimpleValueType();
12371 unsigned VTBits = VT.getSizeInBits();
12373 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12374 SDValue ShOpLo = Op.getOperand(0);
12375 SDValue ShOpHi = Op.getOperand(1);
12376 SDValue ShAmt = Op.getOperand(2);
12377 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12378 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12380 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12381 DAG.getConstant(VTBits - 1, dl, MVT::i8));
12382 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12383 DAG.getConstant(VTBits - 1, dl, MVT::i8))
12384 : DAG.getConstant(0, dl, VT);
12386 SDValue Tmp2, Tmp3;
12387 if (Op.getOpcode() == ISD::SHL_PARTS) {
12388 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12389 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12391 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12392 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12395 // If the shift amount is larger or equal than the width of a part we can't
12396 // rely on the results of shld/shrd. Insert a test and select the appropriate
12397 // values for large shift amounts.
12398 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12399 DAG.getConstant(VTBits, dl, MVT::i8));
12400 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12401 AndNode, DAG.getConstant(0, dl, MVT::i8));
12404 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
12405 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12406 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12408 if (Op.getOpcode() == ISD::SHL_PARTS) {
12409 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12410 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12412 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12413 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12416 SDValue Ops[2] = { Lo, Hi };
12417 return DAG.getMergeValues(Ops, dl);
12420 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12421 SelectionDAG &DAG) const {
12422 SDValue Src = Op.getOperand(0);
12423 MVT SrcVT = Src.getSimpleValueType();
12424 MVT VT = Op.getSimpleValueType();
12427 if (SrcVT.isVector()) {
12428 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
12429 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
12430 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
12431 DAG.getUNDEF(SrcVT)));
12433 if (SrcVT.getVectorElementType() == MVT::i1) {
12434 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
12435 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12436 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
12441 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12442 "Unknown SINT_TO_FP to lower!");
12444 // These are really Legal; return the operand so the caller accepts it as
12446 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12448 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12449 Subtarget->is64Bit()) {
12453 unsigned Size = SrcVT.getSizeInBits()/8;
12454 MachineFunction &MF = DAG.getMachineFunction();
12455 auto PtrVT = getPointerTy(MF.getDataLayout());
12456 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12457 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12458 SDValue Chain = DAG.getStore(
12459 DAG.getEntryNode(), dl, Op.getOperand(0), StackSlot,
12460 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI), false,
12462 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12465 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12467 SelectionDAG &DAG) const {
12471 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12473 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12475 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12477 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12479 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12480 MachineMemOperand *MMO;
12482 int SSFI = FI->getIndex();
12483 MMO = DAG.getMachineFunction().getMachineMemOperand(
12484 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12485 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12487 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12488 StackSlot = StackSlot.getOperand(1);
12490 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12491 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12493 Tys, Ops, SrcVT, MMO);
12496 Chain = Result.getValue(1);
12497 SDValue InFlag = Result.getValue(2);
12499 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12500 // shouldn't be necessary except that RFP cannot be live across
12501 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12502 MachineFunction &MF = DAG.getMachineFunction();
12503 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12504 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12505 auto PtrVT = getPointerTy(MF.getDataLayout());
12506 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12507 Tys = DAG.getVTList(MVT::Other);
12509 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12511 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12512 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12513 MachineMemOperand::MOStore, SSFISize, SSFISize);
12515 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12516 Ops, Op.getValueType(), MMO);
12517 Result = DAG.getLoad(
12518 Op.getValueType(), DL, Chain, StackSlot,
12519 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12520 false, false, false, 0);
12526 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12527 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12528 SelectionDAG &DAG) const {
12529 // This algorithm is not obvious. Here it is what we're trying to output:
12532 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12533 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12535 haddpd %xmm0, %xmm0
12537 pshufd $0x4e, %xmm0, %xmm1
12543 LLVMContext *Context = DAG.getContext();
12545 // Build some magic constants.
12546 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12547 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12548 auto PtrVT = getPointerTy(DAG.getDataLayout());
12549 SDValue CPIdx0 = DAG.getConstantPool(C0, PtrVT, 16);
12551 SmallVector<Constant*,2> CV1;
12553 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12554 APInt(64, 0x4330000000000000ULL))));
12556 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12557 APInt(64, 0x4530000000000000ULL))));
12558 Constant *C1 = ConstantVector::get(CV1);
12559 SDValue CPIdx1 = DAG.getConstantPool(C1, PtrVT, 16);
12561 // Load the 64-bit value into an XMM register.
12562 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12565 DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12566 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12567 false, false, false, 16);
12569 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
12572 DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12573 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12574 false, false, false, 16);
12575 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
12576 // TODO: Are there any fast-math-flags to propagate here?
12577 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12580 if (Subtarget->hasSSE3()) {
12581 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12582 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12584 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
12585 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12587 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12588 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
12591 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12592 DAG.getIntPtrConstant(0, dl));
12595 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12596 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12597 SelectionDAG &DAG) const {
12599 // FP constant to bias correct the final result.
12600 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
12603 // Load the 32-bit value into an XMM register.
12604 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12607 // Zero out the upper parts of the register.
12608 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12610 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12611 DAG.getBitcast(MVT::v2f64, Load),
12612 DAG.getIntPtrConstant(0, dl));
12614 // Or the load with the bias.
12615 SDValue Or = DAG.getNode(
12616 ISD::OR, dl, MVT::v2i64,
12617 DAG.getBitcast(MVT::v2i64,
12618 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
12619 DAG.getBitcast(MVT::v2i64,
12620 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
12622 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12623 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
12625 // Subtract the bias.
12626 // TODO: Are there any fast-math-flags to propagate here?
12627 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12629 // Handle final rounding.
12630 MVT DestVT = Op.getSimpleValueType();
12632 if (DestVT.bitsLT(MVT::f64))
12633 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12634 DAG.getIntPtrConstant(0, dl));
12635 if (DestVT.bitsGT(MVT::f64))
12636 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12638 // Handle final rounding.
12642 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
12643 const X86Subtarget &Subtarget) {
12644 // The algorithm is the following:
12645 // #ifdef __SSE4_1__
12646 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12647 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12648 // (uint4) 0x53000000, 0xaa);
12650 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12651 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12653 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12654 // return (float4) lo + fhi;
12656 // We shouldn't use it when unsafe-fp-math is enabled though: we might later
12657 // reassociate the two FADDs, and if we do that, the algorithm fails
12658 // spectacularly (PR24512).
12659 // FIXME: If we ever have some kind of Machine FMF, this should be marked
12660 // as non-fast and always be enabled. Why isn't SDAG FMF enough? Because
12661 // there's also the MachineCombiner reassociations happening on Machine IR.
12662 if (DAG.getTarget().Options.UnsafeFPMath)
12666 SDValue V = Op->getOperand(0);
12667 MVT VecIntVT = V.getSimpleValueType();
12668 bool Is128 = VecIntVT == MVT::v4i32;
12669 MVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
12670 // If we convert to something else than the supported type, e.g., to v4f64,
12672 if (VecFloatVT != Op->getSimpleValueType(0))
12675 unsigned NumElts = VecIntVT.getVectorNumElements();
12676 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
12677 "Unsupported custom type");
12678 assert(NumElts <= 8 && "The size of the constant array must be fixed");
12680 // In the #idef/#else code, we have in common:
12681 // - The vector of constants:
12687 // Create the splat vector for 0x4b000000.
12688 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
12689 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
12690 CstLow, CstLow, CstLow, CstLow};
12691 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12692 makeArrayRef(&CstLowArray[0], NumElts));
12693 // Create the splat vector for 0x53000000.
12694 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
12695 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
12696 CstHigh, CstHigh, CstHigh, CstHigh};
12697 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12698 makeArrayRef(&CstHighArray[0], NumElts));
12700 // Create the right shift.
12701 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
12702 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
12703 CstShift, CstShift, CstShift, CstShift};
12704 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12705 makeArrayRef(&CstShiftArray[0], NumElts));
12706 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
12709 if (Subtarget.hasSSE41()) {
12710 MVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
12711 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12712 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
12713 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
12714 // Low will be bitcasted right away, so do not bother bitcasting back to its
12716 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
12717 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12718 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12719 // (uint4) 0x53000000, 0xaa);
12720 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
12721 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
12722 // High will be bitcasted right away, so do not bother bitcasting back to
12723 // its original type.
12724 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
12725 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12727 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
12728 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
12729 CstMask, CstMask, CstMask);
12730 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12731 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
12732 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
12734 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12735 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
12738 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
12739 SDValue CstFAdd = DAG.getConstantFP(
12740 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
12741 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
12742 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
12743 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
12744 makeArrayRef(&CstFAddArray[0], NumElts));
12746 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12747 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
12748 // TODO: Are there any fast-math-flags to propagate here?
12750 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
12751 // return (float4) lo + fhi;
12752 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
12753 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
12756 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12757 SelectionDAG &DAG) const {
12758 SDValue N0 = Op.getOperand(0);
12759 MVT SVT = N0.getSimpleValueType();
12762 switch (SVT.SimpleTy) {
12764 llvm_unreachable("Custom UINT_TO_FP is not supported!");
12769 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12770 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12771 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12775 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
12778 assert(Subtarget->hasAVX512());
12779 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
12780 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
12784 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12785 SelectionDAG &DAG) const {
12786 SDValue N0 = Op.getOperand(0);
12788 auto PtrVT = getPointerTy(DAG.getDataLayout());
12790 if (Op.getSimpleValueType().isVector())
12791 return lowerUINT_TO_FP_vec(Op, DAG);
12793 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12794 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12795 // the optimization here.
12796 if (DAG.SignBitIsZero(N0))
12797 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12799 MVT SrcVT = N0.getSimpleValueType();
12800 MVT DstVT = Op.getSimpleValueType();
12802 if (Subtarget->hasAVX512() && isScalarFPTypeInSSEReg(DstVT) &&
12803 (SrcVT == MVT::i32 || (SrcVT == MVT::i64 && Subtarget->is64Bit()))) {
12804 // Conversions from unsigned i32 to f32/f64 are legal,
12805 // using VCVTUSI2SS/SD. Same for i64 in 64-bit mode.
12809 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12810 return LowerUINT_TO_FP_i64(Op, DAG);
12811 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12812 return LowerUINT_TO_FP_i32(Op, DAG);
12813 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12816 // Make a 64-bit buffer, and use it to build an FILD.
12817 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12818 if (SrcVT == MVT::i32) {
12819 SDValue WordOff = DAG.getConstant(4, dl, PtrVT);
12820 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, WordOff);
12821 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12822 StackSlot, MachinePointerInfo(),
12824 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
12825 OffsetSlot, MachinePointerInfo(),
12827 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12831 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12832 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12833 StackSlot, MachinePointerInfo(),
12835 // For i64 source, we need to add the appropriate power of 2 if the input
12836 // was negative. This is the same as the optimization in
12837 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12838 // we must be careful to do the computation in x87 extended precision, not
12839 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12840 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12841 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12842 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12843 MachineMemOperand::MOLoad, 8, 8);
12845 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12846 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12847 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12850 APInt FF(32, 0x5F800000ULL);
12852 // Check whether the sign bit is set.
12853 SDValue SignSet = DAG.getSetCC(
12854 dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64),
12855 Op.getOperand(0), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
12857 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12858 SDValue FudgePtr = DAG.getConstantPool(
12859 ConstantInt::get(*DAG.getContext(), FF.zext(64)), PtrVT);
12861 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12862 SDValue Zero = DAG.getIntPtrConstant(0, dl);
12863 SDValue Four = DAG.getIntPtrConstant(4, dl);
12864 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12866 FudgePtr = DAG.getNode(ISD::ADD, dl, PtrVT, FudgePtr, Offset);
12868 // Load the value out, extending it from f32 to f80.
12869 // FIXME: Avoid the extend by constructing the right constant pool?
12870 SDValue Fudge = DAG.getExtLoad(
12871 ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), FudgePtr,
12872 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
12873 false, false, false, 4);
12874 // Extend everything to 80 bits to force it to be done on x87.
12875 // TODO: Are there any fast-math-flags to propagate here?
12876 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12877 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
12878 DAG.getIntPtrConstant(0, dl));
12881 // If the given FP_TO_SINT (IsSigned) or FP_TO_UINT (!IsSigned) operation
12882 // is legal, or has an fp128 or f16 source (which needs to be promoted to f32),
12883 // just return an <SDValue(), SDValue()> pair.
12884 // Otherwise it is assumed to be a conversion from one of f32, f64 or f80
12885 // to i16, i32 or i64, and we lower it to a legal sequence.
12886 // If lowered to the final integer result we return a <result, SDValue()> pair.
12887 // Otherwise we lower it to a sequence ending with a FIST, return a
12888 // <FIST, StackSlot> pair, and the caller is responsible for loading
12889 // the final integer result from StackSlot.
12890 std::pair<SDValue,SDValue>
12891 X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12892 bool IsSigned, bool IsReplace) const {
12895 EVT DstTy = Op.getValueType();
12896 EVT TheVT = Op.getOperand(0).getValueType();
12897 auto PtrVT = getPointerTy(DAG.getDataLayout());
12899 if (TheVT != MVT::f32 && TheVT != MVT::f64 && TheVT != MVT::f80) {
12900 // f16 must be promoted before using the lowering in this routine.
12901 // fp128 does not use this lowering.
12902 return std::make_pair(SDValue(), SDValue());
12905 // If using FIST to compute an unsigned i64, we'll need some fixup
12906 // to handle values above the maximum signed i64. A FIST is always
12907 // used for the 32-bit subtarget, but also for f80 on a 64-bit target.
12908 bool UnsignedFixup = !IsSigned &&
12909 DstTy == MVT::i64 &&
12910 (!Subtarget->is64Bit() ||
12911 !isScalarFPTypeInSSEReg(TheVT));
12913 if (!IsSigned && DstTy != MVT::i64 && !Subtarget->hasAVX512()) {
12914 // Replace the fp-to-uint32 operation with an fp-to-sint64 FIST.
12915 // The low 32 bits of the fist result will have the correct uint32 result.
12916 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12920 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12921 DstTy.getSimpleVT() >= MVT::i16 &&
12922 "Unknown FP_TO_INT to lower!");
12924 // These are really Legal.
12925 if (DstTy == MVT::i32 &&
12926 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12927 return std::make_pair(SDValue(), SDValue());
12928 if (Subtarget->is64Bit() &&
12929 DstTy == MVT::i64 &&
12930 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12931 return std::make_pair(SDValue(), SDValue());
12933 // We lower FP->int64 into FISTP64 followed by a load from a temporary
12935 MachineFunction &MF = DAG.getMachineFunction();
12936 unsigned MemSize = DstTy.getSizeInBits()/8;
12937 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12938 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12941 switch (DstTy.getSimpleVT().SimpleTy) {
12942 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12943 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12944 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12945 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12948 SDValue Chain = DAG.getEntryNode();
12949 SDValue Value = Op.getOperand(0);
12950 SDValue Adjust; // 0x0 or 0x80000000, for result sign bit adjustment.
12952 if (UnsignedFixup) {
12954 // Conversion to unsigned i64 is implemented with a select,
12955 // depending on whether the source value fits in the range
12956 // of a signed i64. Let Thresh be the FP equivalent of
12957 // 0x8000000000000000ULL.
12959 // Adjust i32 = (Value < Thresh) ? 0 : 0x80000000;
12960 // FistSrc = (Value < Thresh) ? Value : (Value - Thresh);
12961 // Fist-to-mem64 FistSrc
12962 // Add 0 or 0x800...0ULL to the 64-bit result, which is equivalent
12963 // to XOR'ing the high 32 bits with Adjust.
12965 // Being a power of 2, Thresh is exactly representable in all FP formats.
12966 // For X87 we'd like to use the smallest FP type for this constant, but
12967 // for DAG type consistency we have to match the FP operand type.
12969 APFloat Thresh(APFloat::IEEEsingle, APInt(32, 0x5f000000));
12970 LLVM_ATTRIBUTE_UNUSED APFloat::opStatus Status = APFloat::opOK;
12971 bool LosesInfo = false;
12972 if (TheVT == MVT::f64)
12973 // The rounding mode is irrelevant as the conversion should be exact.
12974 Status = Thresh.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
12976 else if (TheVT == MVT::f80)
12977 Status = Thresh.convert(APFloat::x87DoubleExtended,
12978 APFloat::rmNearestTiesToEven, &LosesInfo);
12980 assert(Status == APFloat::opOK && !LosesInfo &&
12981 "FP conversion should have been exact");
12983 SDValue ThreshVal = DAG.getConstantFP(Thresh, DL, TheVT);
12985 SDValue Cmp = DAG.getSetCC(DL,
12986 getSetCCResultType(DAG.getDataLayout(),
12987 *DAG.getContext(), TheVT),
12988 Value, ThreshVal, ISD::SETLT);
12989 Adjust = DAG.getSelect(DL, MVT::i32, Cmp,
12990 DAG.getConstant(0, DL, MVT::i32),
12991 DAG.getConstant(0x80000000, DL, MVT::i32));
12992 SDValue Sub = DAG.getNode(ISD::FSUB, DL, TheVT, Value, ThreshVal);
12993 Cmp = DAG.getSetCC(DL, getSetCCResultType(DAG.getDataLayout(),
12994 *DAG.getContext(), TheVT),
12995 Value, ThreshVal, ISD::SETLT);
12996 Value = DAG.getSelect(DL, TheVT, Cmp, Value, Sub);
12999 // FIXME This causes a redundant load/store if the SSE-class value is already
13000 // in memory, such as if it is on the callstack.
13001 if (isScalarFPTypeInSSEReg(TheVT)) {
13002 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
13003 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
13004 MachinePointerInfo::getFixedStack(MF, SSFI), false,
13006 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
13008 Chain, StackSlot, DAG.getValueType(TheVT)
13011 MachineMemOperand *MMO =
13012 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
13013 MachineMemOperand::MOLoad, MemSize, MemSize);
13014 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
13015 Chain = Value.getValue(1);
13016 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13017 StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
13020 MachineMemOperand *MMO =
13021 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
13022 MachineMemOperand::MOStore, MemSize, MemSize);
13024 if (UnsignedFixup) {
13026 // Insert the FIST, load its result as two i32's,
13027 // and XOR the high i32 with Adjust.
13029 SDValue FistOps[] = { Chain, Value, StackSlot };
13030 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13031 FistOps, DstTy, MMO);
13033 SDValue Low32 = DAG.getLoad(MVT::i32, DL, FIST, StackSlot,
13034 MachinePointerInfo(),
13035 false, false, false, 0);
13036 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackSlot,
13037 DAG.getConstant(4, DL, PtrVT));
13039 SDValue High32 = DAG.getLoad(MVT::i32, DL, FIST, HighAddr,
13040 MachinePointerInfo(),
13041 false, false, false, 0);
13042 High32 = DAG.getNode(ISD::XOR, DL, MVT::i32, High32, Adjust);
13044 if (Subtarget->is64Bit()) {
13045 // Join High32 and Low32 into a 64-bit result.
13046 // (High32 << 32) | Low32
13047 Low32 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Low32);
13048 High32 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, High32);
13049 High32 = DAG.getNode(ISD::SHL, DL, MVT::i64, High32,
13050 DAG.getConstant(32, DL, MVT::i8));
13051 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i64, High32, Low32);
13052 return std::make_pair(Result, SDValue());
13055 SDValue ResultOps[] = { Low32, High32 };
13057 SDValue pair = IsReplace
13058 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResultOps)
13059 : DAG.getMergeValues(ResultOps, DL);
13060 return std::make_pair(pair, SDValue());
13062 // Build the FP_TO_INT*_IN_MEM
13063 SDValue Ops[] = { Chain, Value, StackSlot };
13064 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13066 return std::make_pair(FIST, StackSlot);
13070 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13071 const X86Subtarget *Subtarget) {
13072 MVT VT = Op->getSimpleValueType(0);
13073 SDValue In = Op->getOperand(0);
13074 MVT InVT = In.getSimpleValueType();
13077 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
13078 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
13080 // Optimize vectors in AVX mode:
13083 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13084 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13085 // Concat upper and lower parts.
13088 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13089 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13090 // Concat upper and lower parts.
13093 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13094 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13095 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13098 if (Subtarget->hasInt256())
13099 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13101 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13102 SDValue Undef = DAG.getUNDEF(InVT);
13103 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13104 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13105 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13107 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13108 VT.getVectorNumElements()/2);
13110 OpLo = DAG.getBitcast(HVT, OpLo);
13111 OpHi = DAG.getBitcast(HVT, OpHi);
13113 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13116 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13117 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
13118 MVT VT = Op->getSimpleValueType(0);
13119 SDValue In = Op->getOperand(0);
13120 MVT InVT = In.getSimpleValueType();
13122 unsigned int NumElts = VT.getVectorNumElements();
13123 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
13126 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13127 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13129 assert(InVT.getVectorElementType() == MVT::i1);
13130 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
13132 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
13134 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
13136 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
13137 if (VT.is512BitVector())
13139 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
13142 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13143 SelectionDAG &DAG) {
13144 if (Subtarget->hasFp256())
13145 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13151 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13152 SelectionDAG &DAG) {
13154 MVT VT = Op.getSimpleValueType();
13155 SDValue In = Op.getOperand(0);
13156 MVT SVT = In.getSimpleValueType();
13158 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13159 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
13161 if (Subtarget->hasFp256())
13162 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13165 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13166 VT.getVectorNumElements() != SVT.getVectorNumElements());
13170 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13172 MVT VT = Op.getSimpleValueType();
13173 SDValue In = Op.getOperand(0);
13174 MVT InVT = In.getSimpleValueType();
13176 if (VT == MVT::i1) {
13177 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13178 "Invalid scalar TRUNCATE operation");
13179 if (InVT.getSizeInBits() >= 32)
13181 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13182 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13184 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13185 "Invalid TRUNCATE operation");
13187 // move vector to mask - truncate solution for SKX
13188 if (VT.getVectorElementType() == MVT::i1) {
13189 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
13190 Subtarget->hasBWI())
13191 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13192 if ((InVT.is256BitVector() || InVT.is128BitVector())
13193 && InVT.getScalarSizeInBits() <= 16 &&
13194 Subtarget->hasBWI() && Subtarget->hasVLX())
13195 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13196 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
13197 Subtarget->hasDQI())
13198 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
13199 if ((InVT.is256BitVector() || InVT.is128BitVector())
13200 && InVT.getScalarSizeInBits() >= 32 &&
13201 Subtarget->hasDQI() && Subtarget->hasVLX())
13202 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
13205 if (VT.getVectorElementType() == MVT::i1) {
13206 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13207 unsigned NumElts = InVT.getVectorNumElements();
13208 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13209 if (InVT.getSizeInBits() < 512) {
13210 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13211 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13216 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
13217 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13218 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13221 // vpmovqb/w/d, vpmovdb/w, vpmovwb
13222 if (Subtarget->hasAVX512()) {
13223 // word to byte only under BWI
13224 if (InVT == MVT::v16i16 && !Subtarget->hasBWI()) // v16i16 -> v16i8
13225 return DAG.getNode(X86ISD::VTRUNC, DL, VT,
13226 DAG.getNode(X86ISD::VSEXT, DL, MVT::v16i32, In));
13227 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13229 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13230 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13231 if (Subtarget->hasInt256()) {
13232 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13233 In = DAG.getBitcast(MVT::v8i32, In);
13234 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13236 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13237 DAG.getIntPtrConstant(0, DL));
13240 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13241 DAG.getIntPtrConstant(0, DL));
13242 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13243 DAG.getIntPtrConstant(2, DL));
13244 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13245 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13246 static const int ShufMask[] = {0, 2, 4, 6};
13247 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13250 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13251 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13252 if (Subtarget->hasInt256()) {
13253 In = DAG.getBitcast(MVT::v32i8, In);
13255 SmallVector<SDValue,32> pshufbMask;
13256 for (unsigned i = 0; i < 2; ++i) {
13257 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
13258 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
13259 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
13260 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
13261 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
13262 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
13263 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
13264 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
13265 for (unsigned j = 0; j < 8; ++j)
13266 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
13268 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13269 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13270 In = DAG.getBitcast(MVT::v4i64, In);
13272 static const int ShufMask[] = {0, 2, -1, -1};
13273 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13275 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13276 DAG.getIntPtrConstant(0, DL));
13277 return DAG.getBitcast(VT, In);
13280 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13281 DAG.getIntPtrConstant(0, DL));
13283 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13284 DAG.getIntPtrConstant(4, DL));
13286 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
13287 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
13289 // The PSHUFB mask:
13290 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13291 -1, -1, -1, -1, -1, -1, -1, -1};
13293 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13294 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13295 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13297 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13298 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13300 // The MOVLHPS Mask:
13301 static const int ShufMask2[] = {0, 1, 4, 5};
13302 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13303 return DAG.getBitcast(MVT::v8i16, res);
13306 // Handle truncation of V256 to V128 using shuffles.
13307 if (!VT.is128BitVector() || !InVT.is256BitVector())
13310 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13312 unsigned NumElems = VT.getVectorNumElements();
13313 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13315 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13316 // Prepare truncation shuffle mask
13317 for (unsigned i = 0; i != NumElems; ++i)
13318 MaskVec[i] = i * 2;
13319 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
13320 DAG.getUNDEF(NVT), &MaskVec[0]);
13321 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13322 DAG.getIntPtrConstant(0, DL));
13325 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13326 SelectionDAG &DAG) const {
13327 assert(!Op.getSimpleValueType().isVector());
13329 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13330 /*IsSigned=*/ true, /*IsReplace=*/ false);
13331 SDValue FIST = Vals.first, StackSlot = Vals.second;
13332 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13333 if (!FIST.getNode())
13336 if (StackSlot.getNode())
13337 // Load the result.
13338 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13339 FIST, StackSlot, MachinePointerInfo(),
13340 false, false, false, 0);
13342 // The node is the result.
13346 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13347 SelectionDAG &DAG) const {
13348 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13349 /*IsSigned=*/ false, /*IsReplace=*/ false);
13350 SDValue FIST = Vals.first, StackSlot = Vals.second;
13351 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13352 if (!FIST.getNode())
13355 if (StackSlot.getNode())
13356 // Load the result.
13357 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13358 FIST, StackSlot, MachinePointerInfo(),
13359 false, false, false, 0);
13361 // The node is the result.
13365 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13367 MVT VT = Op.getSimpleValueType();
13368 SDValue In = Op.getOperand(0);
13369 MVT SVT = In.getSimpleValueType();
13371 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13373 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13374 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13375 In, DAG.getUNDEF(SVT)));
13378 /// The only differences between FABS and FNEG are the mask and the logic op.
13379 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
13380 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13381 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13382 "Wrong opcode for lowering FABS or FNEG.");
13384 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13386 // If this is a FABS and it has an FNEG user, bail out to fold the combination
13387 // into an FNABS. We'll lower the FABS after that if it is still in use.
13389 for (SDNode *User : Op->uses())
13390 if (User->getOpcode() == ISD::FNEG)
13394 MVT VT = Op.getSimpleValueType();
13396 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13397 // decide if we should generate a 16-byte constant mask when we only need 4 or
13398 // 8 bytes for the scalar case.
13404 if (VT.isVector()) {
13406 EltVT = VT.getVectorElementType();
13407 NumElts = VT.getVectorNumElements();
13409 // There are no scalar bitwise logical SSE/AVX instructions, so we
13410 // generate a 16-byte vector constant and logic op even for the scalar case.
13411 // Using a 16-byte mask allows folding the load of the mask with
13412 // the logic op, so it can save (~4 bytes) on code size.
13413 LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13415 NumElts = (VT == MVT::f64) ? 2 : 4;
13418 unsigned EltBits = EltVT.getSizeInBits();
13419 LLVMContext *Context = DAG.getContext();
13420 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13422 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13423 Constant *C = ConstantInt::get(*Context, MaskElt);
13424 C = ConstantVector::getSplat(NumElts, C);
13425 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13426 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
13427 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13429 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13430 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13431 false, false, false, Alignment);
13433 SDValue Op0 = Op.getOperand(0);
13434 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13436 IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
13437 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
13440 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13442 // For the scalar case extend to a 128-bit vector, perform the logic op,
13443 // and extract the scalar result back out.
13444 Operand = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Operand);
13445 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13446 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, LogicNode,
13447 DAG.getIntPtrConstant(0, dl));
13450 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13451 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13452 LLVMContext *Context = DAG.getContext();
13453 SDValue Op0 = Op.getOperand(0);
13454 SDValue Op1 = Op.getOperand(1);
13456 MVT VT = Op.getSimpleValueType();
13457 MVT SrcVT = Op1.getSimpleValueType();
13459 // If second operand is smaller, extend it first.
13460 if (SrcVT.bitsLT(VT)) {
13461 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13464 // And if it is bigger, shrink it first.
13465 if (SrcVT.bitsGT(VT)) {
13466 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
13470 // At this point the operands and the result should have the same
13471 // type, and that won't be f80 since that is not custom lowered.
13473 const fltSemantics &Sem =
13474 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
13475 const unsigned SizeInBits = VT.getSizeInBits();
13477 SmallVector<Constant *, 4> CV(
13478 VT == MVT::f64 ? 2 : 4,
13479 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
13481 // First, clear all bits but the sign bit from the second operand (sign).
13482 CV[0] = ConstantFP::get(*Context,
13483 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
13484 Constant *C = ConstantVector::get(CV);
13485 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
13486 SDValue CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13488 // Perform all logic operations as 16-byte vectors because there are no
13489 // scalar FP logic instructions in SSE. This allows load folding of the
13490 // constants into the logic instructions.
13491 MVT LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13493 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13494 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13495 false, false, false, 16);
13496 Op1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op1);
13497 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op1, Mask1);
13499 // Next, clear the sign bit from the first operand (magnitude).
13500 // If it's a constant, we can clear it here.
13501 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
13502 APFloat APF = Op0CN->getValueAPF();
13503 // If the magnitude is a positive zero, the sign bit alone is enough.
13504 if (APF.isPosZero())
13505 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, SignBit,
13506 DAG.getIntPtrConstant(0, dl));
13508 CV[0] = ConstantFP::get(*Context, APF);
13510 CV[0] = ConstantFP::get(
13512 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
13514 C = ConstantVector::get(CV);
13515 CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13517 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13518 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13519 false, false, false, 16);
13520 // If the magnitude operand wasn't a constant, we need to AND out the sign.
13521 if (!isa<ConstantFPSDNode>(Op0)) {
13522 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op0);
13523 Val = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op0, Val);
13525 // OR the magnitude value with the sign bit.
13526 Val = DAG.getNode(X86ISD::FOR, dl, LogicVT, Val, SignBit);
13527 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, Val,
13528 DAG.getIntPtrConstant(0, dl));
13531 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13532 SDValue N0 = Op.getOperand(0);
13534 MVT VT = Op.getSimpleValueType();
13536 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13537 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13538 DAG.getConstant(1, dl, VT));
13539 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
13542 // Check whether an OR'd tree is PTEST-able.
13543 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13544 SelectionDAG &DAG) {
13545 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13547 if (!Subtarget->hasSSE41())
13550 if (!Op->hasOneUse())
13553 SDNode *N = Op.getNode();
13556 SmallVector<SDValue, 8> Opnds;
13557 DenseMap<SDValue, unsigned> VecInMap;
13558 SmallVector<SDValue, 8> VecIns;
13559 EVT VT = MVT::Other;
13561 // Recognize a special case where a vector is casted into wide integer to
13563 Opnds.push_back(N->getOperand(0));
13564 Opnds.push_back(N->getOperand(1));
13566 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13567 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13568 // BFS traverse all OR'd operands.
13569 if (I->getOpcode() == ISD::OR) {
13570 Opnds.push_back(I->getOperand(0));
13571 Opnds.push_back(I->getOperand(1));
13572 // Re-evaluate the number of nodes to be traversed.
13573 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13577 // Quit if a non-EXTRACT_VECTOR_ELT
13578 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13581 // Quit if without a constant index.
13582 SDValue Idx = I->getOperand(1);
13583 if (!isa<ConstantSDNode>(Idx))
13586 SDValue ExtractedFromVec = I->getOperand(0);
13587 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13588 if (M == VecInMap.end()) {
13589 VT = ExtractedFromVec.getValueType();
13590 // Quit if not 128/256-bit vector.
13591 if (!VT.is128BitVector() && !VT.is256BitVector())
13593 // Quit if not the same type.
13594 if (VecInMap.begin() != VecInMap.end() &&
13595 VT != VecInMap.begin()->first.getValueType())
13597 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13598 VecIns.push_back(ExtractedFromVec);
13600 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13603 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13604 "Not extracted from 128-/256-bit vector.");
13606 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13608 for (DenseMap<SDValue, unsigned>::const_iterator
13609 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13610 // Quit if not all elements are used.
13611 if (I->second != FullMask)
13615 MVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13617 // Cast all vectors into TestVT for PTEST.
13618 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13619 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
13621 // If more than one full vectors are evaluated, OR them first before PTEST.
13622 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13623 // Each iteration will OR 2 nodes and append the result until there is only
13624 // 1 node left, i.e. the final OR'd value of all vectors.
13625 SDValue LHS = VecIns[Slot];
13626 SDValue RHS = VecIns[Slot + 1];
13627 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13630 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13631 VecIns.back(), VecIns.back());
13634 /// \brief return true if \c Op has a use that doesn't just read flags.
13635 static bool hasNonFlagsUse(SDValue Op) {
13636 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13638 SDNode *User = *UI;
13639 unsigned UOpNo = UI.getOperandNo();
13640 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13641 // Look pass truncate.
13642 UOpNo = User->use_begin().getOperandNo();
13643 User = *User->use_begin();
13646 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13647 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13653 /// Emit nodes that will be selected as "test Op0,Op0", or something
13655 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13656 SelectionDAG &DAG) const {
13657 if (Op.getValueType() == MVT::i1) {
13658 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
13659 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
13660 DAG.getConstant(0, dl, MVT::i8));
13662 // CF and OF aren't always set the way we want. Determine which
13663 // of these we need.
13664 bool NeedCF = false;
13665 bool NeedOF = false;
13668 case X86::COND_A: case X86::COND_AE:
13669 case X86::COND_B: case X86::COND_BE:
13672 case X86::COND_G: case X86::COND_GE:
13673 case X86::COND_L: case X86::COND_LE:
13674 case X86::COND_O: case X86::COND_NO: {
13675 // Check if we really need to set the
13676 // Overflow flag. If NoSignedWrap is present
13677 // that is not actually needed.
13678 switch (Op->getOpcode()) {
13683 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
13684 if (BinNode->Flags.hasNoSignedWrap())
13694 // See if we can use the EFLAGS value from the operand instead of
13695 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13696 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13697 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13698 // Emit a CMP with 0, which is the TEST pattern.
13699 //if (Op.getValueType() == MVT::i1)
13700 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13701 // DAG.getConstant(0, MVT::i1));
13702 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13703 DAG.getConstant(0, dl, Op.getValueType()));
13705 unsigned Opcode = 0;
13706 unsigned NumOperands = 0;
13708 // Truncate operations may prevent the merge of the SETCC instruction
13709 // and the arithmetic instruction before it. Attempt to truncate the operands
13710 // of the arithmetic instruction and use a reduced bit-width instruction.
13711 bool NeedTruncation = false;
13712 SDValue ArithOp = Op;
13713 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13714 SDValue Arith = Op->getOperand(0);
13715 // Both the trunc and the arithmetic op need to have one user each.
13716 if (Arith->hasOneUse())
13717 switch (Arith.getOpcode()) {
13724 NeedTruncation = true;
13730 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13731 // which may be the result of a CAST. We use the variable 'Op', which is the
13732 // non-casted variable when we check for possible users.
13733 switch (ArithOp.getOpcode()) {
13735 // Due to an isel shortcoming, be conservative if this add is likely to be
13736 // selected as part of a load-modify-store instruction. When the root node
13737 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13738 // uses of other nodes in the match, such as the ADD in this case. This
13739 // leads to the ADD being left around and reselected, with the result being
13740 // two adds in the output. Alas, even if none our users are stores, that
13741 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13742 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13743 // climbing the DAG back to the root, and it doesn't seem to be worth the
13745 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13746 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13747 if (UI->getOpcode() != ISD::CopyToReg &&
13748 UI->getOpcode() != ISD::SETCC &&
13749 UI->getOpcode() != ISD::STORE)
13752 if (ConstantSDNode *C =
13753 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13754 // An add of one will be selected as an INC.
13755 if (C->isOne() && !Subtarget->slowIncDec()) {
13756 Opcode = X86ISD::INC;
13761 // An add of negative one (subtract of one) will be selected as a DEC.
13762 if (C->isAllOnesValue() && !Subtarget->slowIncDec()) {
13763 Opcode = X86ISD::DEC;
13769 // Otherwise use a regular EFLAGS-setting add.
13770 Opcode = X86ISD::ADD;
13775 // If we have a constant logical shift that's only used in a comparison
13776 // against zero turn it into an equivalent AND. This allows turning it into
13777 // a TEST instruction later.
13778 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13779 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13780 EVT VT = Op.getValueType();
13781 unsigned BitWidth = VT.getSizeInBits();
13782 unsigned ShAmt = Op->getConstantOperandVal(1);
13783 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13785 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13786 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13787 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13788 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13790 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13791 DAG.getConstant(Mask, dl, VT));
13792 DAG.ReplaceAllUsesWith(Op, New);
13798 // If the primary and result isn't used, don't bother using X86ISD::AND,
13799 // because a TEST instruction will be better.
13800 if (!hasNonFlagsUse(Op))
13806 // Due to the ISEL shortcoming noted above, be conservative if this op is
13807 // likely to be selected as part of a load-modify-store instruction.
13808 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13809 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13810 if (UI->getOpcode() == ISD::STORE)
13813 // Otherwise use a regular EFLAGS-setting instruction.
13814 switch (ArithOp.getOpcode()) {
13815 default: llvm_unreachable("unexpected operator!");
13816 case ISD::SUB: Opcode = X86ISD::SUB; break;
13817 case ISD::XOR: Opcode = X86ISD::XOR; break;
13818 case ISD::AND: Opcode = X86ISD::AND; break;
13820 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13821 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13822 if (EFLAGS.getNode())
13825 Opcode = X86ISD::OR;
13839 return SDValue(Op.getNode(), 1);
13845 // If we found that truncation is beneficial, perform the truncation and
13847 if (NeedTruncation) {
13848 EVT VT = Op.getValueType();
13849 SDValue WideVal = Op->getOperand(0);
13850 EVT WideVT = WideVal.getValueType();
13851 unsigned ConvertedOp = 0;
13852 // Use a target machine opcode to prevent further DAGCombine
13853 // optimizations that may separate the arithmetic operations
13854 // from the setcc node.
13855 switch (WideVal.getOpcode()) {
13857 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13858 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13859 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13860 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13861 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13865 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13866 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13867 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13868 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13869 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13875 // Emit a CMP with 0, which is the TEST pattern.
13876 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13877 DAG.getConstant(0, dl, Op.getValueType()));
13879 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13880 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
13882 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13883 DAG.ReplaceAllUsesWith(Op, New);
13884 return SDValue(New.getNode(), 1);
13887 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13889 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13890 SDLoc dl, SelectionDAG &DAG) const {
13891 if (isNullConstant(Op1))
13892 return EmitTest(Op0, X86CC, dl, DAG);
13894 assert(!(isa<ConstantSDNode>(Op1) && Op0.getValueType() == MVT::i1) &&
13895 "Unexpected comparison operation for MVT::i1 operands");
13897 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13898 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13899 // Do the comparison at i32 if it's smaller, besides the Atom case.
13900 // This avoids subregister aliasing issues. Keep the smaller reference
13901 // if we're optimizing for size, however, as that'll allow better folding
13902 // of memory operations.
13903 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13904 !DAG.getMachineFunction().getFunction()->optForMinSize() &&
13905 !Subtarget->isAtom()) {
13906 unsigned ExtendOp =
13907 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13908 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13909 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13911 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13912 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13913 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13915 return SDValue(Sub.getNode(), 1);
13917 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13920 /// Convert a comparison if required by the subtarget.
13921 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13922 SelectionDAG &DAG) const {
13923 // If the subtarget does not support the FUCOMI instruction, floating-point
13924 // comparisons have to be converted.
13925 if (Subtarget->hasCMov() ||
13926 Cmp.getOpcode() != X86ISD::CMP ||
13927 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13928 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13931 // The instruction selector will select an FUCOM instruction instead of
13932 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13933 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13934 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13936 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13937 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13938 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13939 DAG.getConstant(8, dl, MVT::i8));
13940 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13942 // Some 64-bit targets lack SAHF support, but they do support FCOMI.
13943 assert(Subtarget->hasLAHFSAHF() && "Target doesn't support SAHF or FCOMI?");
13944 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13947 /// The minimum architected relative accuracy is 2^-12. We need one
13948 /// Newton-Raphson step to have a good float result (24 bits of precision).
13949 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
13950 DAGCombinerInfo &DCI,
13951 unsigned &RefinementSteps,
13952 bool &UseOneConstNR) const {
13953 EVT VT = Op.getValueType();
13954 const char *RecipOp;
13956 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
13957 // TODO: Add support for AVX512 (v16f32).
13958 // It is likely not profitable to do this for f64 because a double-precision
13959 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
13960 // instructions: convert to single, rsqrtss, convert back to double, refine
13961 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
13962 // along with FMA, this could be a throughput win.
13963 if (VT == MVT::f32 && Subtarget->hasSSE1())
13965 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13966 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13967 RecipOp = "vec-sqrtf";
13971 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13972 if (!Recips.isEnabled(RecipOp))
13975 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13976 UseOneConstNR = false;
13977 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
13980 /// The minimum architected relative accuracy is 2^-12. We need one
13981 /// Newton-Raphson step to have a good float result (24 bits of precision).
13982 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
13983 DAGCombinerInfo &DCI,
13984 unsigned &RefinementSteps) const {
13985 EVT VT = Op.getValueType();
13986 const char *RecipOp;
13988 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
13989 // TODO: Add support for AVX512 (v16f32).
13990 // It is likely not profitable to do this for f64 because a double-precision
13991 // reciprocal estimate with refinement on x86 prior to FMA requires
13992 // 15 instructions: convert to single, rcpss, convert back to double, refine
13993 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
13994 // along with FMA, this could be a throughput win.
13995 if (VT == MVT::f32 && Subtarget->hasSSE1())
13997 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13998 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13999 RecipOp = "vec-divf";
14003 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
14004 if (!Recips.isEnabled(RecipOp))
14007 RefinementSteps = Recips.getRefinementSteps(RecipOp);
14008 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
14011 /// If we have at least two divisions that use the same divisor, convert to
14012 /// multplication by a reciprocal. This may need to be adjusted for a given
14013 /// CPU if a division's cost is not at least twice the cost of a multiplication.
14014 /// This is because we still need one division to calculate the reciprocal and
14015 /// then we need two multiplies by that reciprocal as replacements for the
14016 /// original divisions.
14017 unsigned X86TargetLowering::combineRepeatedFPDivisors() const {
14021 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14022 /// if it's possible.
14023 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14024 SDLoc dl, SelectionDAG &DAG) const {
14025 SDValue Op0 = And.getOperand(0);
14026 SDValue Op1 = And.getOperand(1);
14027 if (Op0.getOpcode() == ISD::TRUNCATE)
14028 Op0 = Op0.getOperand(0);
14029 if (Op1.getOpcode() == ISD::TRUNCATE)
14030 Op1 = Op1.getOperand(0);
14033 if (Op1.getOpcode() == ISD::SHL)
14034 std::swap(Op0, Op1);
14035 if (Op0.getOpcode() == ISD::SHL) {
14036 if (isOneConstant(Op0.getOperand(0))) {
14037 // If we looked past a truncate, check that it's only truncating away
14039 unsigned BitWidth = Op0.getValueSizeInBits();
14040 unsigned AndBitWidth = And.getValueSizeInBits();
14041 if (BitWidth > AndBitWidth) {
14043 DAG.computeKnownBits(Op0, Zeros, Ones);
14044 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
14048 RHS = Op0.getOperand(1);
14050 } else if (Op1.getOpcode() == ISD::Constant) {
14051 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
14052 uint64_t AndRHSVal = AndRHS->getZExtValue();
14053 SDValue AndLHS = Op0;
14055 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
14056 LHS = AndLHS.getOperand(0);
14057 RHS = AndLHS.getOperand(1);
14060 // Use BT if the immediate can't be encoded in a TEST instruction.
14061 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
14063 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
14067 if (LHS.getNode()) {
14068 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
14069 // instruction. Since the shift amount is in-range-or-undefined, we know
14070 // that doing a bittest on the i32 value is ok. We extend to i32 because
14071 // the encoding for the i16 version is larger than the i32 version.
14072 // Also promote i16 to i32 for performance / code size reason.
14073 if (LHS.getValueType() == MVT::i8 ||
14074 LHS.getValueType() == MVT::i16)
14075 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
14077 // If the operand types disagree, extend the shift amount to match. Since
14078 // BT ignores high bits (like shifts) we can use anyextend.
14079 if (LHS.getValueType() != RHS.getValueType())
14080 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
14082 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
14083 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
14084 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14085 DAG.getConstant(Cond, dl, MVT::i8), BT);
14091 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
14093 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14098 // SSE Condition code mapping:
14107 switch (SetCCOpcode) {
14108 default: llvm_unreachable("Unexpected SETCC condition");
14110 case ISD::SETEQ: SSECC = 0; break;
14112 case ISD::SETGT: Swap = true; // Fallthrough
14114 case ISD::SETOLT: SSECC = 1; break;
14116 case ISD::SETGE: Swap = true; // Fallthrough
14118 case ISD::SETOLE: SSECC = 2; break;
14119 case ISD::SETUO: SSECC = 3; break;
14121 case ISD::SETNE: SSECC = 4; break;
14122 case ISD::SETULE: Swap = true; // Fallthrough
14123 case ISD::SETUGE: SSECC = 5; break;
14124 case ISD::SETULT: Swap = true; // Fallthrough
14125 case ISD::SETUGT: SSECC = 6; break;
14126 case ISD::SETO: SSECC = 7; break;
14128 case ISD::SETONE: SSECC = 8; break;
14131 std::swap(Op0, Op1);
14136 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14137 // ones, and then concatenate the result back.
14138 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14139 MVT VT = Op.getSimpleValueType();
14141 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14142 "Unsupported value type for operation");
14144 unsigned NumElems = VT.getVectorNumElements();
14146 SDValue CC = Op.getOperand(2);
14148 // Extract the LHS vectors
14149 SDValue LHS = Op.getOperand(0);
14150 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14151 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14153 // Extract the RHS vectors
14154 SDValue RHS = Op.getOperand(1);
14155 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14156 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14158 // Issue the operation on the smaller types and concatenate the result back
14159 MVT EltVT = VT.getVectorElementType();
14160 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14161 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14162 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14163 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14166 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
14167 SDValue Op0 = Op.getOperand(0);
14168 SDValue Op1 = Op.getOperand(1);
14169 SDValue CC = Op.getOperand(2);
14170 MVT VT = Op.getSimpleValueType();
14173 assert(Op0.getSimpleValueType().getVectorElementType() == MVT::i1 &&
14174 "Unexpected type for boolean compare operation");
14175 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14176 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
14177 DAG.getConstant(-1, dl, VT));
14178 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
14179 DAG.getConstant(-1, dl, VT));
14180 switch (SetCCOpcode) {
14181 default: llvm_unreachable("Unexpected SETCC condition");
14183 // (x == y) -> ~(x ^ y)
14184 return DAG.getNode(ISD::XOR, dl, VT,
14185 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
14186 DAG.getConstant(-1, dl, VT));
14188 // (x != y) -> (x ^ y)
14189 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
14192 // (x > y) -> (x & ~y)
14193 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
14196 // (x < y) -> (~x & y)
14197 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
14200 // (x <= y) -> (~x | y)
14201 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
14204 // (x >=y) -> (x | ~y)
14205 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
14209 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14210 const X86Subtarget *Subtarget) {
14211 SDValue Op0 = Op.getOperand(0);
14212 SDValue Op1 = Op.getOperand(1);
14213 SDValue CC = Op.getOperand(2);
14214 MVT VT = Op.getSimpleValueType();
14217 assert(Op0.getSimpleValueType().getVectorElementType().getSizeInBits() >= 8 &&
14218 Op.getSimpleValueType().getVectorElementType() == MVT::i1 &&
14219 "Cannot set masked compare for this operation");
14221 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14223 bool Unsigned = false;
14226 switch (SetCCOpcode) {
14227 default: llvm_unreachable("Unexpected SETCC condition");
14228 case ISD::SETNE: SSECC = 4; break;
14229 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14230 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14231 case ISD::SETLT: Swap = true; //fall-through
14232 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14233 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14234 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14235 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14236 case ISD::SETULE: Unsigned = true; //fall-through
14237 case ISD::SETLE: SSECC = 2; break;
14241 std::swap(Op0, Op1);
14243 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14244 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14245 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14246 DAG.getConstant(SSECC, dl, MVT::i8));
14249 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14250 /// operand \p Op1. If non-trivial (for example because it's not constant)
14251 /// return an empty value.
14252 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14254 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14258 MVT VT = Op1.getSimpleValueType();
14259 MVT EVT = VT.getVectorElementType();
14260 unsigned n = VT.getVectorNumElements();
14261 SmallVector<SDValue, 8> ULTOp1;
14263 for (unsigned i = 0; i < n; ++i) {
14264 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14265 if (!Elt || Elt->isOpaque() || Elt->getSimpleValueType(0) != EVT)
14268 // Avoid underflow.
14269 APInt Val = Elt->getAPIntValue();
14273 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
14276 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14279 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14280 SelectionDAG &DAG) {
14281 SDValue Op0 = Op.getOperand(0);
14282 SDValue Op1 = Op.getOperand(1);
14283 SDValue CC = Op.getOperand(2);
14284 MVT VT = Op.getSimpleValueType();
14285 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14286 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14291 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14292 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14295 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14296 unsigned Opc = X86ISD::CMPP;
14297 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14298 assert(VT.getVectorNumElements() <= 16);
14299 Opc = X86ISD::CMPM;
14301 // In the two special cases we can't handle, emit two comparisons.
14304 unsigned CombineOpc;
14305 if (SetCCOpcode == ISD::SETUEQ) {
14306 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14308 assert(SetCCOpcode == ISD::SETONE);
14309 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14312 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14313 DAG.getConstant(CC0, dl, MVT::i8));
14314 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14315 DAG.getConstant(CC1, dl, MVT::i8));
14316 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14318 // Handle all other FP comparisons here.
14319 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14320 DAG.getConstant(SSECC, dl, MVT::i8));
14323 MVT VTOp0 = Op0.getSimpleValueType();
14324 assert(VTOp0 == Op1.getSimpleValueType() &&
14325 "Expected operands with same type!");
14326 assert(VT.getVectorNumElements() == VTOp0.getVectorNumElements() &&
14327 "Invalid number of packed elements for source and destination!");
14329 if (VT.is128BitVector() && VTOp0.is256BitVector()) {
14330 // On non-AVX512 targets, a vector of MVT::i1 is promoted by the type
14331 // legalizer to a wider vector type. In the case of 'vsetcc' nodes, the
14332 // legalizer firstly checks if the first operand in input to the setcc has
14333 // a legal type. If so, then it promotes the return type to that same type.
14334 // Otherwise, the return type is promoted to the 'next legal type' which,
14335 // for a vector of MVT::i1 is always a 128-bit integer vector type.
14337 // We reach this code only if the following two conditions are met:
14338 // 1. Both return type and operand type have been promoted to wider types
14339 // by the type legalizer.
14340 // 2. The original operand type has been promoted to a 256-bit vector.
14342 // Note that condition 2. only applies for AVX targets.
14343 SDValue NewOp = DAG.getSetCC(dl, VTOp0, Op0, Op1, SetCCOpcode);
14344 return DAG.getZExtOrTrunc(NewOp, dl, VT);
14347 // The non-AVX512 code below works under the assumption that source and
14348 // destination types are the same.
14349 assert((Subtarget->hasAVX512() || (VT == VTOp0)) &&
14350 "Value types for source and destination must be the same!");
14352 // Break 256-bit integer vector compare into smaller ones.
14353 if (VT.is256BitVector() && !Subtarget->hasInt256())
14354 return Lower256IntVSETCC(Op, DAG);
14356 MVT OpVT = Op1.getSimpleValueType();
14357 if (OpVT.getVectorElementType() == MVT::i1)
14358 return LowerBoolVSETCC_AVX512(Op, DAG);
14360 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14361 if (Subtarget->hasAVX512()) {
14362 if (Op1.getSimpleValueType().is512BitVector() ||
14363 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14364 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14365 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14367 // In AVX-512 architecture setcc returns mask with i1 elements,
14368 // But there is no compare instruction for i8 and i16 elements in KNL.
14369 // We are not talking about 512-bit operands in this case, these
14370 // types are illegal.
14372 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14373 OpVT.getVectorElementType().getSizeInBits() >= 8))
14374 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14375 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14378 // Lower using XOP integer comparisons.
14379 if ((VT == MVT::v16i8 || VT == MVT::v8i16 ||
14380 VT == MVT::v4i32 || VT == MVT::v2i64) && Subtarget->hasXOP()) {
14381 // Translate compare code to XOP PCOM compare mode.
14382 unsigned CmpMode = 0;
14383 switch (SetCCOpcode) {
14384 default: llvm_unreachable("Unexpected SETCC condition");
14386 case ISD::SETLT: CmpMode = 0x00; break;
14388 case ISD::SETLE: CmpMode = 0x01; break;
14390 case ISD::SETGT: CmpMode = 0x02; break;
14392 case ISD::SETGE: CmpMode = 0x03; break;
14393 case ISD::SETEQ: CmpMode = 0x04; break;
14394 case ISD::SETNE: CmpMode = 0x05; break;
14397 // Are we comparing unsigned or signed integers?
14398 unsigned Opc = ISD::isUnsignedIntSetCC(SetCCOpcode)
14399 ? X86ISD::VPCOMU : X86ISD::VPCOM;
14401 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14402 DAG.getConstant(CmpMode, dl, MVT::i8));
14405 // We are handling one of the integer comparisons here. Since SSE only has
14406 // GT and EQ comparisons for integer, swapping operands and multiple
14407 // operations may be required for some comparisons.
14409 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14410 bool Subus = false;
14412 switch (SetCCOpcode) {
14413 default: llvm_unreachable("Unexpected SETCC condition");
14414 case ISD::SETNE: Invert = true;
14415 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14416 case ISD::SETLT: Swap = true;
14417 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14418 case ISD::SETGE: Swap = true;
14419 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14420 Invert = true; break;
14421 case ISD::SETULT: Swap = true;
14422 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14423 FlipSigns = true; break;
14424 case ISD::SETUGE: Swap = true;
14425 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14426 FlipSigns = true; Invert = true; break;
14429 // Special case: Use min/max operations for SETULE/SETUGE
14430 MVT VET = VT.getVectorElementType();
14432 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14433 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14436 switch (SetCCOpcode) {
14438 case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break;
14439 case ISD::SETUGE: Opc = ISD::UMAX; MinMax = true; break;
14442 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14445 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14446 if (!MinMax && hasSubus) {
14447 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14449 // t = psubus Op0, Op1
14450 // pcmpeq t, <0..0>
14451 switch (SetCCOpcode) {
14453 case ISD::SETULT: {
14454 // If the comparison is against a constant we can turn this into a
14455 // setule. With psubus, setule does not require a swap. This is
14456 // beneficial because the constant in the register is no longer
14457 // destructed as the destination so it can be hoisted out of a loop.
14458 // Only do this pre-AVX since vpcmp* is no longer destructive.
14459 if (Subtarget->hasAVX())
14461 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14462 if (ULEOp1.getNode()) {
14464 Subus = true; Invert = false; Swap = false;
14468 // Psubus is better than flip-sign because it requires no inversion.
14469 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14470 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14474 Opc = X86ISD::SUBUS;
14480 std::swap(Op0, Op1);
14482 // Check that the operation in question is available (most are plain SSE2,
14483 // but PCMPGTQ and PCMPEQQ have different requirements).
14484 if (VT == MVT::v2i64) {
14485 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14486 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14488 // First cast everything to the right type.
14489 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14490 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14492 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14493 // bits of the inputs before performing those operations. The lower
14494 // compare is always unsigned.
14497 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
14499 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
14500 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
14501 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14502 Sign, Zero, Sign, Zero);
14504 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14505 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14507 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14508 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14509 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14511 // Create masks for only the low parts/high parts of the 64 bit integers.
14512 static const int MaskHi[] = { 1, 1, 3, 3 };
14513 static const int MaskLo[] = { 0, 0, 2, 2 };
14514 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14515 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14516 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14518 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14519 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14522 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14524 return DAG.getBitcast(VT, Result);
14527 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14528 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14529 // pcmpeqd + pshufd + pand.
14530 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14532 // First cast everything to the right type.
14533 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14534 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14537 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14539 // Make sure the lower and upper halves are both all-ones.
14540 static const int Mask[] = { 1, 0, 3, 2 };
14541 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14542 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14545 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14547 return DAG.getBitcast(VT, Result);
14551 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14552 // bits of the inputs before performing those operations.
14554 MVT EltVT = VT.getVectorElementType();
14555 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
14557 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14558 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14561 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14563 // If the logical-not of the result is required, perform that now.
14565 Result = DAG.getNOT(dl, Result, VT);
14568 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14571 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14572 getZeroVector(VT, Subtarget, DAG, dl));
14577 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14579 MVT VT = Op.getSimpleValueType();
14581 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14583 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14584 && "SetCC type must be 8-bit or 1-bit integer");
14585 SDValue Op0 = Op.getOperand(0);
14586 SDValue Op1 = Op.getOperand(1);
14588 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14590 // Optimize to BT if possible.
14591 // Lower (X & (1 << N)) == 0 to BT(X, N).
14592 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14593 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14594 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14595 isNullConstant(Op1) &&
14596 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14597 if (SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG)) {
14599 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
14604 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14606 if ((isOneConstant(Op1) || isNullConstant(Op1)) &&
14607 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14609 // If the input is a setcc, then reuse the input setcc or use a new one with
14610 // the inverted condition.
14611 if (Op0.getOpcode() == X86ISD::SETCC) {
14612 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14613 bool Invert = (CC == ISD::SETNE) ^ isNullConstant(Op1);
14617 CCode = X86::GetOppositeBranchCondition(CCode);
14618 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14619 DAG.getConstant(CCode, dl, MVT::i8),
14620 Op0.getOperand(1));
14622 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14626 if ((Op0.getValueType() == MVT::i1) && isOneConstant(Op1) &&
14627 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14629 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14630 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
14633 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14634 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
14635 if (X86CC == X86::COND_INVALID)
14638 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14639 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14640 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14641 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
14643 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14647 SDValue X86TargetLowering::LowerSETCCE(SDValue Op, SelectionDAG &DAG) const {
14648 SDValue LHS = Op.getOperand(0);
14649 SDValue RHS = Op.getOperand(1);
14650 SDValue Carry = Op.getOperand(2);
14651 SDValue Cond = Op.getOperand(3);
14654 assert(LHS.getSimpleValueType().isInteger() && "SETCCE is integer only.");
14655 X86::CondCode CC = TranslateIntegerX86CC(cast<CondCodeSDNode>(Cond)->get());
14657 assert(Carry.getOpcode() != ISD::CARRY_FALSE);
14658 SDVTList VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14659 SDValue Cmp = DAG.getNode(X86ISD::SBB, DL, VTs, LHS, RHS, Carry);
14660 return DAG.getNode(X86ISD::SETCC, DL, Op.getValueType(),
14661 DAG.getConstant(CC, DL, MVT::i8), Cmp.getValue(1));
14664 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14665 static bool isX86LogicalCmp(SDValue Op) {
14666 unsigned Opc = Op.getNode()->getOpcode();
14667 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14668 Opc == X86ISD::SAHF)
14670 if (Op.getResNo() == 1 &&
14671 (Opc == X86ISD::ADD ||
14672 Opc == X86ISD::SUB ||
14673 Opc == X86ISD::ADC ||
14674 Opc == X86ISD::SBB ||
14675 Opc == X86ISD::SMUL ||
14676 Opc == X86ISD::UMUL ||
14677 Opc == X86ISD::INC ||
14678 Opc == X86ISD::DEC ||
14679 Opc == X86ISD::OR ||
14680 Opc == X86ISD::XOR ||
14681 Opc == X86ISD::AND))
14684 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14690 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14691 if (V.getOpcode() != ISD::TRUNCATE)
14694 SDValue VOp0 = V.getOperand(0);
14695 unsigned InBits = VOp0.getValueSizeInBits();
14696 unsigned Bits = V.getValueSizeInBits();
14697 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14700 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14701 bool addTest = true;
14702 SDValue Cond = Op.getOperand(0);
14703 SDValue Op1 = Op.getOperand(1);
14704 SDValue Op2 = Op.getOperand(2);
14706 MVT VT = Op1.getSimpleValueType();
14709 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14710 // are available or VBLENDV if AVX is available.
14711 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
14712 if (Cond.getOpcode() == ISD::SETCC &&
14713 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14714 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14715 VT == Cond.getOperand(0).getSimpleValueType() && Cond->hasOneUse()) {
14716 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14717 int SSECC = translateX86FSETCC(
14718 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14721 if (Subtarget->hasAVX512()) {
14722 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14723 DAG.getConstant(SSECC, DL, MVT::i8));
14724 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14727 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14728 DAG.getConstant(SSECC, DL, MVT::i8));
14730 // If we have AVX, we can use a variable vector select (VBLENDV) instead
14731 // of 3 logic instructions for size savings and potentially speed.
14732 // Unfortunately, there is no scalar form of VBLENDV.
14734 // If either operand is a constant, don't try this. We can expect to
14735 // optimize away at least one of the logic instructions later in that
14736 // case, so that sequence would be faster than a variable blend.
14738 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
14739 // uses XMM0 as the selection register. That may need just as many
14740 // instructions as the AND/ANDN/OR sequence due to register moves, so
14743 if (Subtarget->hasAVX() &&
14744 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
14746 // Convert to vectors, do a VSELECT, and convert back to scalar.
14747 // All of the conversions should be optimized away.
14749 MVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
14750 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
14751 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
14752 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
14754 MVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
14755 VCmp = DAG.getBitcast(VCmpVT, VCmp);
14757 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
14759 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
14760 VSel, DAG.getIntPtrConstant(0, DL));
14762 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14763 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14764 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14768 if (VT.isVector() && VT.getVectorElementType() == MVT::i1) {
14770 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
14771 Op1Scalar = ConvertI1VectorToInteger(Op1, DAG);
14772 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
14773 Op1Scalar = Op1.getOperand(0);
14775 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
14776 Op2Scalar = ConvertI1VectorToInteger(Op2, DAG);
14777 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
14778 Op2Scalar = Op2.getOperand(0);
14779 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
14780 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
14781 Op1Scalar.getValueType(),
14782 Cond, Op1Scalar, Op2Scalar);
14783 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
14784 return DAG.getBitcast(VT, newSelect);
14785 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
14786 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
14787 DAG.getIntPtrConstant(0, DL));
14791 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
14792 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
14793 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14794 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
14795 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14796 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
14797 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
14799 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
14802 if (Cond.getOpcode() == ISD::SETCC) {
14803 SDValue NewCond = LowerSETCC(Cond, DAG);
14804 if (NewCond.getNode())
14808 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14809 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14810 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14811 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14812 if (Cond.getOpcode() == X86ISD::SETCC &&
14813 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14814 isNullConstant(Cond.getOperand(1).getOperand(1))) {
14815 SDValue Cmp = Cond.getOperand(1);
14817 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14819 if ((isAllOnesConstant(Op1) || isAllOnesConstant(Op2)) &&
14820 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14821 SDValue Y = isAllOnesConstant(Op2) ? Op1 : Op2;
14823 SDValue CmpOp0 = Cmp.getOperand(0);
14824 // Apply further optimizations for special cases
14825 // (select (x != 0), -1, 0) -> neg & sbb
14826 // (select (x == 0), 0, -1) -> neg & sbb
14827 if (isNullConstant(Y) &&
14828 (isAllOnesConstant(Op1) == (CondCode == X86::COND_NE))) {
14829 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14830 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14831 DAG.getConstant(0, DL,
14832 CmpOp0.getValueType()),
14834 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14835 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14836 SDValue(Neg.getNode(), 1));
14840 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14841 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
14842 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14844 SDValue Res = // Res = 0 or -1.
14845 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14846 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
14848 if (isAllOnesConstant(Op1) != (CondCode == X86::COND_E))
14849 Res = DAG.getNOT(DL, Res, Res.getValueType());
14851 if (!isNullConstant(Op2))
14852 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14857 // Look past (and (setcc_carry (cmp ...)), 1).
14858 if (Cond.getOpcode() == ISD::AND &&
14859 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY &&
14860 isOneConstant(Cond.getOperand(1)))
14861 Cond = Cond.getOperand(0);
14863 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14864 // setting operand in place of the X86ISD::SETCC.
14865 unsigned CondOpcode = Cond.getOpcode();
14866 if (CondOpcode == X86ISD::SETCC ||
14867 CondOpcode == X86ISD::SETCC_CARRY) {
14868 CC = Cond.getOperand(0);
14870 SDValue Cmp = Cond.getOperand(1);
14871 unsigned Opc = Cmp.getOpcode();
14872 MVT VT = Op.getSimpleValueType();
14874 bool IllegalFPCMov = false;
14875 if (VT.isFloatingPoint() && !VT.isVector() &&
14876 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14877 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14879 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14880 Opc == X86ISD::BT) { // FIXME
14884 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14885 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14886 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14887 Cond.getOperand(0).getValueType() != MVT::i8)) {
14888 SDValue LHS = Cond.getOperand(0);
14889 SDValue RHS = Cond.getOperand(1);
14890 unsigned X86Opcode;
14893 switch (CondOpcode) {
14894 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14895 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14896 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14897 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14898 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14899 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14900 default: llvm_unreachable("unexpected overflowing operator");
14902 if (CondOpcode == ISD::UMULO)
14903 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14906 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14908 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14910 if (CondOpcode == ISD::UMULO)
14911 Cond = X86Op.getValue(2);
14913 Cond = X86Op.getValue(1);
14915 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
14920 // Look past the truncate if the high bits are known zero.
14921 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14922 Cond = Cond.getOperand(0);
14924 // We know the result of AND is compared against zero. Try to match
14926 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14927 if (SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG)) {
14928 CC = NewSetCC.getOperand(0);
14929 Cond = NewSetCC.getOperand(1);
14936 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
14937 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14940 // a < b ? -1 : 0 -> RES = ~setcc_carry
14941 // a < b ? 0 : -1 -> RES = setcc_carry
14942 // a >= b ? -1 : 0 -> RES = setcc_carry
14943 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14944 if (Cond.getOpcode() == X86ISD::SUB) {
14945 Cond = ConvertCmpIfNecessary(Cond, DAG);
14946 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14948 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14949 (isAllOnesConstant(Op1) || isAllOnesConstant(Op2)) &&
14950 (isNullConstant(Op1) || isNullConstant(Op2))) {
14951 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14952 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14954 if (isAllOnesConstant(Op1) != (CondCode == X86::COND_B))
14955 return DAG.getNOT(DL, Res, Res.getValueType());
14960 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14961 // widen the cmov and push the truncate through. This avoids introducing a new
14962 // branch during isel and doesn't add any extensions.
14963 if (Op.getValueType() == MVT::i8 &&
14964 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14965 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14966 if (T1.getValueType() == T2.getValueType() &&
14967 // Blacklist CopyFromReg to avoid partial register stalls.
14968 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14969 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14970 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14971 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14975 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14976 // condition is true.
14977 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14978 SDValue Ops[] = { Op2, Op1, CC, Cond };
14979 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14982 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
14983 const X86Subtarget *Subtarget,
14984 SelectionDAG &DAG) {
14985 MVT VT = Op->getSimpleValueType(0);
14986 SDValue In = Op->getOperand(0);
14987 MVT InVT = In.getSimpleValueType();
14988 MVT VTElt = VT.getVectorElementType();
14989 MVT InVTElt = InVT.getVectorElementType();
14993 if ((InVTElt == MVT::i1) &&
14994 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
14995 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
14997 ((Subtarget->hasBWI() && VT.is512BitVector() &&
14998 VTElt.getSizeInBits() <= 16)) ||
15000 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15001 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15003 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15004 VTElt.getSizeInBits() >= 32))))
15005 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15007 unsigned int NumElts = VT.getVectorNumElements();
15009 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
15012 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15013 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15014 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15015 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15018 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15019 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
15021 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
15024 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
15026 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
15027 if (VT.is512BitVector())
15029 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
15032 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
15033 const X86Subtarget *Subtarget,
15034 SelectionDAG &DAG) {
15035 SDValue In = Op->getOperand(0);
15036 MVT VT = Op->getSimpleValueType(0);
15037 MVT InVT = In.getSimpleValueType();
15038 assert(VT.getSizeInBits() == InVT.getSizeInBits());
15040 MVT InSVT = InVT.getVectorElementType();
15041 assert(VT.getVectorElementType().getSizeInBits() > InSVT.getSizeInBits());
15043 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
15045 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
15050 // SSE41 targets can use the pmovsx* instructions directly.
15051 if (Subtarget->hasSSE41())
15052 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15054 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
15058 // As SRAI is only available on i16/i32 types, we expand only up to i32
15059 // and handle i64 separately.
15060 while (CurrVT != VT && CurrVT.getVectorElementType() != MVT::i32) {
15061 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
15062 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
15063 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
15064 Curr = DAG.getBitcast(CurrVT, Curr);
15067 SDValue SignExt = Curr;
15068 if (CurrVT != InVT) {
15069 unsigned SignExtShift =
15070 CurrVT.getVectorElementType().getSizeInBits() - InSVT.getSizeInBits();
15071 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
15072 DAG.getConstant(SignExtShift, dl, MVT::i8));
15078 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
15079 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
15080 DAG.getConstant(31, dl, MVT::i8));
15081 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
15082 return DAG.getBitcast(VT, Ext);
15088 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15089 SelectionDAG &DAG) {
15090 MVT VT = Op->getSimpleValueType(0);
15091 SDValue In = Op->getOperand(0);
15092 MVT InVT = In.getSimpleValueType();
15095 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15096 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15098 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15099 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15100 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15103 if (Subtarget->hasInt256())
15104 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15106 // Optimize vectors in AVX mode
15107 // Sign extend v8i16 to v8i32 and
15110 // Divide input vector into two parts
15111 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15112 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15113 // concat the vectors to original VT
15115 unsigned NumElems = InVT.getVectorNumElements();
15116 SDValue Undef = DAG.getUNDEF(InVT);
15118 SmallVector<int,8> ShufMask1(NumElems, -1);
15119 for (unsigned i = 0; i != NumElems/2; ++i)
15122 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15124 SmallVector<int,8> ShufMask2(NumElems, -1);
15125 for (unsigned i = 0; i != NumElems/2; ++i)
15126 ShufMask2[i] = i + NumElems/2;
15128 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15130 MVT HalfVT = MVT::getVectorVT(VT.getVectorElementType(),
15131 VT.getVectorNumElements()/2);
15133 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15134 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15136 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15139 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15140 // may emit an illegal shuffle but the expansion is still better than scalar
15141 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15142 // we'll emit a shuffle and a arithmetic shift.
15143 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
15144 // TODO: It is possible to support ZExt by zeroing the undef values during
15145 // the shuffle phase or after the shuffle.
15146 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15147 SelectionDAG &DAG) {
15148 MVT RegVT = Op.getSimpleValueType();
15149 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15150 assert(RegVT.isInteger() &&
15151 "We only custom lower integer vector sext loads.");
15153 // Nothing useful we can do without SSE2 shuffles.
15154 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15156 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15158 EVT MemVT = Ld->getMemoryVT();
15159 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15160 unsigned RegSz = RegVT.getSizeInBits();
15162 ISD::LoadExtType Ext = Ld->getExtensionType();
15164 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15165 && "Only anyext and sext are currently implemented.");
15166 assert(MemVT != RegVT && "Cannot extend to the same type");
15167 assert(MemVT.isVector() && "Must load a vector from memory");
15169 unsigned NumElems = RegVT.getVectorNumElements();
15170 unsigned MemSz = MemVT.getSizeInBits();
15171 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15173 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15174 // The only way in which we have a legal 256-bit vector result but not the
15175 // integer 256-bit operations needed to directly lower a sextload is if we
15176 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15177 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15178 // correctly legalized. We do this late to allow the canonical form of
15179 // sextload to persist throughout the rest of the DAG combiner -- it wants
15180 // to fold together any extensions it can, and so will fuse a sign_extend
15181 // of an sextload into a sextload targeting a wider value.
15183 if (MemSz == 128) {
15184 // Just switch this to a normal load.
15185 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15186 "it must be a legal 128-bit vector "
15188 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15189 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15190 Ld->isInvariant(), Ld->getAlignment());
15192 assert(MemSz < 128 &&
15193 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15194 // Do an sext load to a 128-bit vector type. We want to use the same
15195 // number of elements, but elements half as wide. This will end up being
15196 // recursively lowered by this routine, but will succeed as we definitely
15197 // have all the necessary features if we're using AVX1.
15199 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15200 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15202 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15203 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15204 Ld->isNonTemporal(), Ld->isInvariant(),
15205 Ld->getAlignment());
15208 // Replace chain users with the new chain.
15209 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15210 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15212 // Finally, do a normal sign-extend to the desired register.
15213 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15216 // All sizes must be a power of two.
15217 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15218 "Non-power-of-two elements are not custom lowered!");
15220 // Attempt to load the original value using scalar loads.
15221 // Find the largest scalar type that divides the total loaded size.
15222 MVT SclrLoadTy = MVT::i8;
15223 for (MVT Tp : MVT::integer_valuetypes()) {
15224 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15229 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15230 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15232 SclrLoadTy = MVT::f64;
15234 // Calculate the number of scalar loads that we need to perform
15235 // in order to load our vector from memory.
15236 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15238 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15239 "Can only lower sext loads with a single scalar load!");
15241 unsigned loadRegZize = RegSz;
15242 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
15245 // Represent our vector as a sequence of elements which are the
15246 // largest scalar that we can load.
15247 EVT LoadUnitVecVT = EVT::getVectorVT(
15248 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15250 // Represent the data using the same element type that is stored in
15251 // memory. In practice, we ''widen'' MemVT.
15253 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15254 loadRegZize / MemVT.getScalarSizeInBits());
15256 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15257 "Invalid vector type");
15259 // We can't shuffle using an illegal type.
15260 assert(TLI.isTypeLegal(WideVecVT) &&
15261 "We only lower types that form legal widened vector types");
15263 SmallVector<SDValue, 8> Chains;
15264 SDValue Ptr = Ld->getBasePtr();
15265 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl,
15266 TLI.getPointerTy(DAG.getDataLayout()));
15267 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15269 for (unsigned i = 0; i < NumLoads; ++i) {
15270 // Perform a single load.
15271 SDValue ScalarLoad =
15272 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15273 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15274 Ld->getAlignment());
15275 Chains.push_back(ScalarLoad.getValue(1));
15276 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15277 // another round of DAGCombining.
15279 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15281 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15282 ScalarLoad, DAG.getIntPtrConstant(i, dl));
15284 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15287 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15289 // Bitcast the loaded value to a vector of the original element type, in
15290 // the size of the target vector type.
15291 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
15292 unsigned SizeRatio = RegSz / MemSz;
15294 if (Ext == ISD::SEXTLOAD) {
15295 // If we have SSE4.1, we can directly emit a VSEXT node.
15296 if (Subtarget->hasSSE41()) {
15297 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15298 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15302 // Otherwise we'll use SIGN_EXTEND_VECTOR_INREG to sign extend the lowest
15304 assert(TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND_VECTOR_INREG, RegVT) &&
15305 "We can't implement a sext load without SIGN_EXTEND_VECTOR_INREG!");
15307 SDValue Shuff = DAG.getSignExtendVectorInReg(SlicedVec, dl, RegVT);
15308 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15312 // Redistribute the loaded elements into the different locations.
15313 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15314 for (unsigned i = 0; i != NumElems; ++i)
15315 ShuffleVec[i * SizeRatio] = i;
15317 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15318 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15320 // Bitcast to the requested type.
15321 Shuff = DAG.getBitcast(RegVT, Shuff);
15322 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15326 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15327 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15328 // from the AND / OR.
15329 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15330 Opc = Op.getOpcode();
15331 if (Opc != ISD::OR && Opc != ISD::AND)
15333 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15334 Op.getOperand(0).hasOneUse() &&
15335 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15336 Op.getOperand(1).hasOneUse());
15339 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15340 // 1 and that the SETCC node has a single use.
15341 static bool isXor1OfSetCC(SDValue Op) {
15342 if (Op.getOpcode() != ISD::XOR)
15344 if (isOneConstant(Op.getOperand(1)))
15345 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15346 Op.getOperand(0).hasOneUse();
15350 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15351 bool addTest = true;
15352 SDValue Chain = Op.getOperand(0);
15353 SDValue Cond = Op.getOperand(1);
15354 SDValue Dest = Op.getOperand(2);
15357 bool Inverted = false;
15359 if (Cond.getOpcode() == ISD::SETCC) {
15360 // Check for setcc([su]{add,sub,mul}o == 0).
15361 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15362 isNullConstant(Cond.getOperand(1)) &&
15363 Cond.getOperand(0).getResNo() == 1 &&
15364 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15365 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15366 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15367 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15368 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15369 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15371 Cond = Cond.getOperand(0);
15373 SDValue NewCond = LowerSETCC(Cond, DAG);
15374 if (NewCond.getNode())
15379 // FIXME: LowerXALUO doesn't handle these!!
15380 else if (Cond.getOpcode() == X86ISD::ADD ||
15381 Cond.getOpcode() == X86ISD::SUB ||
15382 Cond.getOpcode() == X86ISD::SMUL ||
15383 Cond.getOpcode() == X86ISD::UMUL)
15384 Cond = LowerXALUO(Cond, DAG);
15387 // Look pass (and (setcc_carry (cmp ...)), 1).
15388 if (Cond.getOpcode() == ISD::AND &&
15389 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY &&
15390 isOneConstant(Cond.getOperand(1)))
15391 Cond = Cond.getOperand(0);
15393 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15394 // setting operand in place of the X86ISD::SETCC.
15395 unsigned CondOpcode = Cond.getOpcode();
15396 if (CondOpcode == X86ISD::SETCC ||
15397 CondOpcode == X86ISD::SETCC_CARRY) {
15398 CC = Cond.getOperand(0);
15400 SDValue Cmp = Cond.getOperand(1);
15401 unsigned Opc = Cmp.getOpcode();
15402 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15403 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15407 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15411 // These can only come from an arithmetic instruction with overflow,
15412 // e.g. SADDO, UADDO.
15413 Cond = Cond.getNode()->getOperand(1);
15419 CondOpcode = Cond.getOpcode();
15420 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15421 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15422 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15423 Cond.getOperand(0).getValueType() != MVT::i8)) {
15424 SDValue LHS = Cond.getOperand(0);
15425 SDValue RHS = Cond.getOperand(1);
15426 unsigned X86Opcode;
15429 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15430 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15432 switch (CondOpcode) {
15433 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15435 if (isOneConstant(RHS)) {
15436 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15439 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15440 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15442 if (isOneConstant(RHS)) {
15443 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15446 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15447 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15448 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15449 default: llvm_unreachable("unexpected overflowing operator");
15452 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15453 if (CondOpcode == ISD::UMULO)
15454 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15457 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15459 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15461 if (CondOpcode == ISD::UMULO)
15462 Cond = X86Op.getValue(2);
15464 Cond = X86Op.getValue(1);
15466 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15470 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15471 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15472 if (CondOpc == ISD::OR) {
15473 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15474 // two branches instead of an explicit OR instruction with a
15476 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15477 isX86LogicalCmp(Cmp)) {
15478 CC = Cond.getOperand(0).getOperand(0);
15479 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15480 Chain, Dest, CC, Cmp);
15481 CC = Cond.getOperand(1).getOperand(0);
15485 } else { // ISD::AND
15486 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15487 // two branches instead of an explicit AND instruction with a
15488 // separate test. However, we only do this if this block doesn't
15489 // have a fall-through edge, because this requires an explicit
15490 // jmp when the condition is false.
15491 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15492 isX86LogicalCmp(Cmp) &&
15493 Op.getNode()->hasOneUse()) {
15494 X86::CondCode CCode =
15495 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15496 CCode = X86::GetOppositeBranchCondition(CCode);
15497 CC = DAG.getConstant(CCode, dl, MVT::i8);
15498 SDNode *User = *Op.getNode()->use_begin();
15499 // Look for an unconditional branch following this conditional branch.
15500 // We need this because we need to reverse the successors in order
15501 // to implement FCMP_OEQ.
15502 if (User->getOpcode() == ISD::BR) {
15503 SDValue FalseBB = User->getOperand(1);
15505 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15506 assert(NewBR == User);
15510 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15511 Chain, Dest, CC, Cmp);
15512 X86::CondCode CCode =
15513 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15514 CCode = X86::GetOppositeBranchCondition(CCode);
15515 CC = DAG.getConstant(CCode, dl, MVT::i8);
15521 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15522 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15523 // It should be transformed during dag combiner except when the condition
15524 // is set by a arithmetics with overflow node.
15525 X86::CondCode CCode =
15526 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15527 CCode = X86::GetOppositeBranchCondition(CCode);
15528 CC = DAG.getConstant(CCode, dl, MVT::i8);
15529 Cond = Cond.getOperand(0).getOperand(1);
15531 } else if (Cond.getOpcode() == ISD::SETCC &&
15532 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15533 // For FCMP_OEQ, we can emit
15534 // two branches instead of an explicit AND instruction with a
15535 // separate test. However, we only do this if this block doesn't
15536 // have a fall-through edge, because this requires an explicit
15537 // jmp when the condition is false.
15538 if (Op.getNode()->hasOneUse()) {
15539 SDNode *User = *Op.getNode()->use_begin();
15540 // Look for an unconditional branch following this conditional branch.
15541 // We need this because we need to reverse the successors in order
15542 // to implement FCMP_OEQ.
15543 if (User->getOpcode() == ISD::BR) {
15544 SDValue FalseBB = User->getOperand(1);
15546 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15547 assert(NewBR == User);
15551 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15552 Cond.getOperand(0), Cond.getOperand(1));
15553 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15554 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15555 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15556 Chain, Dest, CC, Cmp);
15557 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
15562 } else if (Cond.getOpcode() == ISD::SETCC &&
15563 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15564 // For FCMP_UNE, we can emit
15565 // two branches instead of an explicit AND instruction with a
15566 // separate test. However, we only do this if this block doesn't
15567 // have a fall-through edge, because this requires an explicit
15568 // jmp when the condition is false.
15569 if (Op.getNode()->hasOneUse()) {
15570 SDNode *User = *Op.getNode()->use_begin();
15571 // Look for an unconditional branch following this conditional branch.
15572 // We need this because we need to reverse the successors in order
15573 // to implement FCMP_UNE.
15574 if (User->getOpcode() == ISD::BR) {
15575 SDValue FalseBB = User->getOperand(1);
15577 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15578 assert(NewBR == User);
15581 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15582 Cond.getOperand(0), Cond.getOperand(1));
15583 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15584 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15585 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15586 Chain, Dest, CC, Cmp);
15587 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
15597 // Look pass the truncate if the high bits are known zero.
15598 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15599 Cond = Cond.getOperand(0);
15601 // We know the result of AND is compared against zero. Try to match
15603 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15604 if (SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG)) {
15605 CC = NewSetCC.getOperand(0);
15606 Cond = NewSetCC.getOperand(1);
15613 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15614 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15615 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15617 Cond = ConvertCmpIfNecessary(Cond, DAG);
15618 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15619 Chain, Dest, CC, Cond);
15622 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15623 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15624 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15625 // that the guard pages used by the OS virtual memory manager are allocated in
15626 // correct sequence.
15628 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15629 SelectionDAG &DAG) const {
15630 MachineFunction &MF = DAG.getMachineFunction();
15631 bool SplitStack = MF.shouldSplitStack();
15632 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
15637 SDNode *Node = Op.getNode();
15638 SDValue Chain = Op.getOperand(0);
15639 SDValue Size = Op.getOperand(1);
15640 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15641 EVT VT = Node->getValueType(0);
15643 // Chain the dynamic stack allocation so that it doesn't modify the stack
15644 // pointer when other instructions are using the stack.
15645 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true), dl);
15647 bool Is64Bit = Subtarget->is64Bit();
15648 MVT SPTy = getPointerTy(DAG.getDataLayout());
15652 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15653 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15654 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15655 " not tell us which reg is the stack pointer!");
15656 EVT VT = Node->getValueType(0);
15657 SDValue Tmp3 = Node->getOperand(2);
15659 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15660 Chain = SP.getValue(1);
15661 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15662 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15663 unsigned StackAlign = TFI.getStackAlignment();
15664 Result = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15665 if (Align > StackAlign)
15666 Result = DAG.getNode(ISD::AND, dl, VT, Result,
15667 DAG.getConstant(-(uint64_t)Align, dl, VT));
15668 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Result); // Output chain
15669 } else if (SplitStack) {
15670 MachineRegisterInfo &MRI = MF.getRegInfo();
15673 // The 64 bit implementation of segmented stacks needs to clobber both r10
15674 // r11. This makes it impossible to use it along with nested parameters.
15675 const Function *F = MF.getFunction();
15677 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15679 if (I->hasNestAttr())
15680 report_fatal_error("Cannot use segmented stacks with functions that "
15681 "have nested arguments.");
15684 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
15685 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15686 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15687 Result = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15688 DAG.getRegister(Vreg, SPTy));
15691 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15693 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15694 Flag = Chain.getValue(1);
15695 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15697 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15699 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15700 unsigned SPReg = RegInfo->getStackRegister();
15701 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15702 Chain = SP.getValue(1);
15705 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15706 DAG.getConstant(-(uint64_t)Align, dl, VT));
15707 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15713 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
15714 DAG.getIntPtrConstant(0, dl, true), SDValue(), dl);
15716 SDValue Ops[2] = {Result, Chain};
15717 return DAG.getMergeValues(Ops, dl);
15720 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15721 MachineFunction &MF = DAG.getMachineFunction();
15722 auto PtrVT = getPointerTy(MF.getDataLayout());
15723 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15725 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15728 if (!Subtarget->is64Bit() ||
15729 Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv())) {
15730 // vastart just stores the address of the VarArgsFrameIndex slot into the
15731 // memory location argument.
15732 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15733 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15734 MachinePointerInfo(SV), false, false, 0);
15738 // gp_offset (0 - 6 * 8)
15739 // fp_offset (48 - 48 + 8 * 16)
15740 // overflow_arg_area (point to parameters coming in memory).
15742 SmallVector<SDValue, 8> MemOps;
15743 SDValue FIN = Op.getOperand(1);
15745 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15746 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15748 FIN, MachinePointerInfo(SV), false, false, 0);
15749 MemOps.push_back(Store);
15752 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15753 Store = DAG.getStore(Op.getOperand(0), DL,
15754 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
15756 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15757 MemOps.push_back(Store);
15759 // Store ptr to overflow_arg_area
15760 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15761 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15762 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15763 MachinePointerInfo(SV, 8),
15765 MemOps.push_back(Store);
15767 // Store ptr to reg_save_area.
15768 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(
15769 Subtarget->isTarget64BitLP64() ? 8 : 4, DL));
15770 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT);
15771 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, MachinePointerInfo(
15772 SV, Subtarget->isTarget64BitLP64() ? 16 : 12), false, false, 0);
15773 MemOps.push_back(Store);
15774 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15777 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15778 assert(Subtarget->is64Bit() &&
15779 "LowerVAARG only handles 64-bit va_arg!");
15780 assert(Op.getNode()->getNumOperands() == 4);
15782 MachineFunction &MF = DAG.getMachineFunction();
15783 if (Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv()))
15784 // The Win64 ABI uses char* instead of a structure.
15785 return DAG.expandVAArg(Op.getNode());
15787 SDValue Chain = Op.getOperand(0);
15788 SDValue SrcPtr = Op.getOperand(1);
15789 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15790 unsigned Align = Op.getConstantOperandVal(3);
15793 EVT ArgVT = Op.getNode()->getValueType(0);
15794 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15795 uint32_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
15798 // Decide which area this value should be read from.
15799 // TODO: Implement the AMD64 ABI in its entirety. This simple
15800 // selection mechanism works only for the basic types.
15801 if (ArgVT == MVT::f80) {
15802 llvm_unreachable("va_arg for f80 not yet implemented");
15803 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15804 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15805 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15806 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15808 llvm_unreachable("Unhandled argument type in LowerVAARG");
15811 if (ArgMode == 2) {
15812 // Sanity Check: Make sure using fp_offset makes sense.
15813 assert(!Subtarget->useSoftFloat() &&
15814 !(MF.getFunction()->hasFnAttribute(Attribute::NoImplicitFloat)) &&
15815 Subtarget->hasSSE1());
15818 // Insert VAARG_64 node into the DAG
15819 // VAARG_64 returns two values: Variable Argument Address, Chain
15820 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
15821 DAG.getConstant(ArgMode, dl, MVT::i8),
15822 DAG.getConstant(Align, dl, MVT::i32)};
15823 SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
15824 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15825 VTs, InstOps, MVT::i64,
15826 MachinePointerInfo(SV),
15828 /*Volatile=*/false,
15830 /*WriteMem=*/true);
15831 Chain = VAARG.getValue(1);
15833 // Load the next argument and return it
15834 return DAG.getLoad(ArgVT, dl,
15837 MachinePointerInfo(),
15838 false, false, false, 0);
15841 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15842 SelectionDAG &DAG) {
15843 // X86-64 va_list is a struct { i32, i32, i8*, i8* }, except on Windows,
15844 // where a va_list is still an i8*.
15845 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15846 if (Subtarget->isCallingConvWin64(
15847 DAG.getMachineFunction().getFunction()->getCallingConv()))
15848 // Probably a Win64 va_copy.
15849 return DAG.expandVACopy(Op.getNode());
15851 SDValue Chain = Op.getOperand(0);
15852 SDValue DstPtr = Op.getOperand(1);
15853 SDValue SrcPtr = Op.getOperand(2);
15854 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15855 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15858 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15859 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
15861 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15864 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15865 // amount is a constant. Takes immediate version of shift as input.
15866 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15867 SDValue SrcOp, uint64_t ShiftAmt,
15868 SelectionDAG &DAG) {
15869 MVT ElementType = VT.getVectorElementType();
15871 // Fold this packed shift into its first operand if ShiftAmt is 0.
15875 // Check for ShiftAmt >= element width
15876 if (ShiftAmt >= ElementType.getSizeInBits()) {
15877 if (Opc == X86ISD::VSRAI)
15878 ShiftAmt = ElementType.getSizeInBits() - 1;
15880 return DAG.getConstant(0, dl, VT);
15883 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15884 && "Unknown target vector shift-by-constant node");
15886 // Fold this packed vector shift into a build vector if SrcOp is a
15887 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15888 if (VT == SrcOp.getSimpleValueType() &&
15889 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15890 SmallVector<SDValue, 8> Elts;
15891 unsigned NumElts = SrcOp->getNumOperands();
15892 ConstantSDNode *ND;
15895 default: llvm_unreachable(nullptr);
15896 case X86ISD::VSHLI:
15897 for (unsigned i=0; i!=NumElts; ++i) {
15898 SDValue CurrentOp = SrcOp->getOperand(i);
15899 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15900 Elts.push_back(CurrentOp);
15903 ND = cast<ConstantSDNode>(CurrentOp);
15904 const APInt &C = ND->getAPIntValue();
15905 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
15908 case X86ISD::VSRLI:
15909 for (unsigned i=0; i!=NumElts; ++i) {
15910 SDValue CurrentOp = SrcOp->getOperand(i);
15911 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15912 Elts.push_back(CurrentOp);
15915 ND = cast<ConstantSDNode>(CurrentOp);
15916 const APInt &C = ND->getAPIntValue();
15917 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
15920 case X86ISD::VSRAI:
15921 for (unsigned i=0; i!=NumElts; ++i) {
15922 SDValue CurrentOp = SrcOp->getOperand(i);
15923 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15924 Elts.push_back(CurrentOp);
15927 ND = cast<ConstantSDNode>(CurrentOp);
15928 const APInt &C = ND->getAPIntValue();
15929 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
15934 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15937 return DAG.getNode(Opc, dl, VT, SrcOp,
15938 DAG.getConstant(ShiftAmt, dl, MVT::i8));
15941 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15942 // may or may not be a constant. Takes immediate version of shift as input.
15943 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15944 SDValue SrcOp, SDValue ShAmt,
15945 SelectionDAG &DAG) {
15946 MVT SVT = ShAmt.getSimpleValueType();
15947 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
15949 // Catch shift-by-constant.
15950 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15951 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15952 CShAmt->getZExtValue(), DAG);
15954 // Change opcode to non-immediate version
15956 default: llvm_unreachable("Unknown target vector shift node");
15957 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15958 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15959 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15962 const X86Subtarget &Subtarget =
15963 static_cast<const X86Subtarget &>(DAG.getSubtarget());
15964 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
15965 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
15966 // Let the shuffle legalizer expand this shift amount node.
15967 SDValue Op0 = ShAmt.getOperand(0);
15968 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
15969 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
15971 // Need to build a vector containing shift amount.
15972 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
15973 SmallVector<SDValue, 4> ShOps;
15974 ShOps.push_back(ShAmt);
15975 if (SVT == MVT::i32) {
15976 ShOps.push_back(DAG.getConstant(0, dl, SVT));
15977 ShOps.push_back(DAG.getUNDEF(SVT));
15979 ShOps.push_back(DAG.getUNDEF(SVT));
15981 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
15982 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
15985 // The return type has to be a 128-bit type with the same element
15986 // type as the input type.
15987 MVT EltVT = VT.getVectorElementType();
15988 MVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15990 ShAmt = DAG.getBitcast(ShVT, ShAmt);
15991 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15994 /// \brief Return Mask with the necessary casting or extending
15995 /// for \p Mask according to \p MaskVT when lowering masking intrinsics
15996 static SDValue getMaskNode(SDValue Mask, MVT MaskVT,
15997 const X86Subtarget *Subtarget,
15998 SelectionDAG &DAG, SDLoc dl) {
16000 if (MaskVT.bitsGT(Mask.getSimpleValueType())) {
16001 // Mask should be extended
16002 Mask = DAG.getNode(ISD::ANY_EXTEND, dl,
16003 MVT::getIntegerVT(MaskVT.getSizeInBits()), Mask);
16006 if (Mask.getSimpleValueType() == MVT::i64 && Subtarget->is32Bit()) {
16007 if (MaskVT == MVT::v64i1) {
16008 assert(Subtarget->hasBWI() && "Expected AVX512BW target!");
16009 // In case 32bit mode, bitcast i64 is illegal, extend/split it.
16011 Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Mask,
16012 DAG.getConstant(0, dl, MVT::i32));
16013 Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Mask,
16014 DAG.getConstant(1, dl, MVT::i32));
16016 Lo = DAG.getBitcast(MVT::v32i1, Lo);
16017 Hi = DAG.getBitcast(MVT::v32i1, Hi);
16019 return DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v64i1, Lo, Hi);
16021 // MaskVT require < 64bit. Truncate mask (should succeed in any case),
16023 MVT TruncVT = MVT::getIntegerVT(MaskVT.getSizeInBits());
16024 return DAG.getBitcast(MaskVT,
16025 DAG.getNode(ISD::TRUNCATE, dl, TruncVT, Mask));
16029 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16030 Mask.getSimpleValueType().getSizeInBits());
16031 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16032 // are extracted by EXTRACT_SUBVECTOR.
16033 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16034 DAG.getBitcast(BitcastVT, Mask),
16035 DAG.getIntPtrConstant(0, dl));
16039 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16040 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16041 /// necessary casting or extending for \p Mask when lowering masking intrinsics
16042 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16043 SDValue PreservedSrc,
16044 const X86Subtarget *Subtarget,
16045 SelectionDAG &DAG) {
16046 MVT VT = Op.getSimpleValueType();
16047 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16048 unsigned OpcodeSelect = ISD::VSELECT;
16051 if (isAllOnesConstant(Mask))
16054 SDValue VMask = getMaskNode(Mask, MaskVT, Subtarget, DAG, dl);
16056 switch (Op.getOpcode()) {
16058 case X86ISD::PCMPEQM:
16059 case X86ISD::PCMPGTM:
16061 case X86ISD::CMPMU:
16062 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16063 case X86ISD::VFPCLASS:
16064 case X86ISD::VFPCLASSS:
16065 return DAG.getNode(ISD::OR, dl, VT, Op, VMask);
16066 case X86ISD::VTRUNC:
16067 case X86ISD::VTRUNCS:
16068 case X86ISD::VTRUNCUS:
16069 // We can't use ISD::VSELECT here because it is not always "Legal"
16070 // for the destination type. For example vpmovqb require only AVX512
16071 // and vselect that can operate on byte element type require BWI
16072 OpcodeSelect = X86ISD::SELECT;
16075 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16076 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16077 return DAG.getNode(OpcodeSelect, dl, VT, VMask, Op, PreservedSrc);
16080 /// \brief Creates an SDNode for a predicated scalar operation.
16081 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
16082 /// The mask is coming as MVT::i8 and it should be truncated
16083 /// to MVT::i1 while lowering masking intrinsics.
16084 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
16085 /// "X86select" instead of "vselect". We just can't create the "vselect" node
16086 /// for a scalar instruction.
16087 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
16088 SDValue PreservedSrc,
16089 const X86Subtarget *Subtarget,
16090 SelectionDAG &DAG) {
16091 if (isAllOnesConstant(Mask))
16094 MVT VT = Op.getSimpleValueType();
16096 // The mask should be of type MVT::i1
16097 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
16099 if (Op.getOpcode() == X86ISD::FSETCC)
16100 return DAG.getNode(ISD::AND, dl, VT, Op, IMask);
16101 if (Op.getOpcode() == X86ISD::VFPCLASS ||
16102 Op.getOpcode() == X86ISD::VFPCLASSS)
16103 return DAG.getNode(ISD::OR, dl, VT, Op, IMask);
16105 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16106 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16107 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
16110 static int getSEHRegistrationNodeSize(const Function *Fn) {
16111 if (!Fn->hasPersonalityFn())
16112 report_fatal_error(
16113 "querying registration node size for function without personality");
16114 // The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See
16115 // WinEHStatePass for the full struct definition.
16116 switch (classifyEHPersonality(Fn->getPersonalityFn())) {
16117 case EHPersonality::MSVC_X86SEH: return 24;
16118 case EHPersonality::MSVC_CXX: return 16;
16121 report_fatal_error("can only recover FP for MSVC EH personality functions");
16124 /// When the 32-bit MSVC runtime transfers control to us, either to an outlined
16125 /// function or when returning to a parent frame after catching an exception, we
16126 /// recover the parent frame pointer by doing arithmetic on the incoming EBP.
16127 /// Here's the math:
16128 /// RegNodeBase = EntryEBP - RegNodeSize
16129 /// ParentFP = RegNodeBase - RegNodeFrameOffset
16130 /// Subtracting RegNodeSize takes us to the offset of the registration node, and
16131 /// subtracting the offset (negative on x86) takes us back to the parent FP.
16132 static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,
16133 SDValue EntryEBP) {
16134 MachineFunction &MF = DAG.getMachineFunction();
16137 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16138 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
16140 // It's possible that the parent function no longer has a personality function
16141 // if the exceptional code was optimized away, in which case we just return
16142 // the incoming EBP.
16143 if (!Fn->hasPersonalityFn())
16146 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16148 // Get an MCSymbol that will ultimately resolve to the frame offset of the EH
16150 MCSymbol *OffsetSym =
16151 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
16152 GlobalValue::getRealLinkageName(Fn->getName()));
16153 SDValue OffsetSymVal = DAG.getMCSymbol(OffsetSym, PtrVT);
16154 SDValue RegNodeFrameOffset =
16155 DAG.getNode(ISD::LOCAL_RECOVER, dl, PtrVT, OffsetSymVal);
16157 // RegNodeBase = EntryEBP - RegNodeSize
16158 // ParentFP = RegNodeBase - RegNodeFrameOffset
16159 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
16160 DAG.getConstant(RegNodeSize, dl, PtrVT));
16161 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, RegNodeFrameOffset);
16164 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16165 SelectionDAG &DAG) {
16167 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16168 MVT VT = Op.getSimpleValueType();
16169 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16171 switch(IntrData->Type) {
16172 case INTR_TYPE_1OP:
16173 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16174 case INTR_TYPE_2OP:
16175 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16177 case INTR_TYPE_2OP_IMM8:
16178 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16179 DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(2)));
16180 case INTR_TYPE_3OP:
16181 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16182 Op.getOperand(2), Op.getOperand(3));
16183 case INTR_TYPE_4OP:
16184 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16185 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4));
16186 case INTR_TYPE_1OP_MASK_RM: {
16187 SDValue Src = Op.getOperand(1);
16188 SDValue PassThru = Op.getOperand(2);
16189 SDValue Mask = Op.getOperand(3);
16190 SDValue RoundingMode;
16191 // We allways add rounding mode to the Node.
16192 // If the rounding mode is not specified, we add the
16193 // "current direction" mode.
16194 if (Op.getNumOperands() == 4)
16196 DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16198 RoundingMode = Op.getOperand(4);
16199 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16200 if (IntrWithRoundingModeOpcode != 0)
16201 if (cast<ConstantSDNode>(RoundingMode)->getZExtValue() !=
16202 X86::STATIC_ROUNDING::CUR_DIRECTION)
16203 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16204 dl, Op.getValueType(), Src, RoundingMode),
16205 Mask, PassThru, Subtarget, DAG);
16206 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16208 Mask, PassThru, Subtarget, DAG);
16210 case INTR_TYPE_1OP_MASK: {
16211 SDValue Src = Op.getOperand(1);
16212 SDValue PassThru = Op.getOperand(2);
16213 SDValue Mask = Op.getOperand(3);
16214 // We add rounding mode to the Node when
16215 // - RM Opcode is specified and
16216 // - RM is not "current direction".
16217 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16218 if (IntrWithRoundingModeOpcode != 0) {
16219 SDValue Rnd = Op.getOperand(4);
16220 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16221 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16222 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16223 dl, Op.getValueType(),
16225 Mask, PassThru, Subtarget, DAG);
16228 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
16229 Mask, PassThru, Subtarget, DAG);
16231 case INTR_TYPE_SCALAR_MASK: {
16232 SDValue Src1 = Op.getOperand(1);
16233 SDValue Src2 = Op.getOperand(2);
16234 SDValue passThru = Op.getOperand(3);
16235 SDValue Mask = Op.getOperand(4);
16236 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2),
16237 Mask, passThru, Subtarget, DAG);
16239 case INTR_TYPE_SCALAR_MASK_RM: {
16240 SDValue Src1 = Op.getOperand(1);
16241 SDValue Src2 = Op.getOperand(2);
16242 SDValue Src0 = Op.getOperand(3);
16243 SDValue Mask = Op.getOperand(4);
16244 // There are 2 kinds of intrinsics in this group:
16245 // (1) With suppress-all-exceptions (sae) or rounding mode- 6 operands
16246 // (2) With rounding mode and sae - 7 operands.
16247 if (Op.getNumOperands() == 6) {
16248 SDValue Sae = Op.getOperand(5);
16249 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
16250 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
16252 Mask, Src0, Subtarget, DAG);
16254 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
16255 SDValue RoundingMode = Op.getOperand(5);
16256 SDValue Sae = Op.getOperand(6);
16257 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16258 RoundingMode, Sae),
16259 Mask, Src0, Subtarget, DAG);
16261 case INTR_TYPE_2OP_MASK:
16262 case INTR_TYPE_2OP_IMM8_MASK: {
16263 SDValue Src1 = Op.getOperand(1);
16264 SDValue Src2 = Op.getOperand(2);
16265 SDValue PassThru = Op.getOperand(3);
16266 SDValue Mask = Op.getOperand(4);
16268 if (IntrData->Type == INTR_TYPE_2OP_IMM8_MASK)
16269 Src2 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src2);
16271 // We specify 2 possible opcodes for intrinsics with rounding modes.
16272 // First, we check if the intrinsic may have non-default rounding mode,
16273 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16274 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16275 if (IntrWithRoundingModeOpcode != 0) {
16276 SDValue Rnd = Op.getOperand(5);
16277 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16278 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16279 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16280 dl, Op.getValueType(),
16282 Mask, PassThru, Subtarget, DAG);
16285 // TODO: Intrinsics should have fast-math-flags to propagate.
16286 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,Src1,Src2),
16287 Mask, PassThru, Subtarget, DAG);
16289 case INTR_TYPE_2OP_MASK_RM: {
16290 SDValue Src1 = Op.getOperand(1);
16291 SDValue Src2 = Op.getOperand(2);
16292 SDValue PassThru = Op.getOperand(3);
16293 SDValue Mask = Op.getOperand(4);
16294 // We specify 2 possible modes for intrinsics, with/without rounding
16296 // First, we check if the intrinsic have rounding mode (6 operands),
16297 // if not, we set rounding mode to "current".
16299 if (Op.getNumOperands() == 6)
16300 Rnd = Op.getOperand(5);
16302 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16303 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16305 Mask, PassThru, Subtarget, DAG);
16307 case INTR_TYPE_3OP_SCALAR_MASK_RM: {
16308 SDValue Src1 = Op.getOperand(1);
16309 SDValue Src2 = Op.getOperand(2);
16310 SDValue Src3 = Op.getOperand(3);
16311 SDValue PassThru = Op.getOperand(4);
16312 SDValue Mask = Op.getOperand(5);
16313 SDValue Sae = Op.getOperand(6);
16315 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1,
16317 Mask, PassThru, Subtarget, DAG);
16319 case INTR_TYPE_3OP_MASK_RM: {
16320 SDValue Src1 = Op.getOperand(1);
16321 SDValue Src2 = Op.getOperand(2);
16322 SDValue Imm = Op.getOperand(3);
16323 SDValue PassThru = Op.getOperand(4);
16324 SDValue Mask = Op.getOperand(5);
16325 // We specify 2 possible modes for intrinsics, with/without rounding
16327 // First, we check if the intrinsic have rounding mode (7 operands),
16328 // if not, we set rounding mode to "current".
16330 if (Op.getNumOperands() == 7)
16331 Rnd = Op.getOperand(6);
16333 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16334 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16335 Src1, Src2, Imm, Rnd),
16336 Mask, PassThru, Subtarget, DAG);
16338 case INTR_TYPE_3OP_IMM8_MASK:
16339 case INTR_TYPE_3OP_MASK:
16340 case INSERT_SUBVEC: {
16341 SDValue Src1 = Op.getOperand(1);
16342 SDValue Src2 = Op.getOperand(2);
16343 SDValue Src3 = Op.getOperand(3);
16344 SDValue PassThru = Op.getOperand(4);
16345 SDValue Mask = Op.getOperand(5);
16347 if (IntrData->Type == INTR_TYPE_3OP_IMM8_MASK)
16348 Src3 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src3);
16349 else if (IntrData->Type == INSERT_SUBVEC) {
16350 // imm should be adapted to ISD::INSERT_SUBVECTOR behavior
16351 assert(isa<ConstantSDNode>(Src3) && "Expected a ConstantSDNode here!");
16352 unsigned Imm = cast<ConstantSDNode>(Src3)->getZExtValue();
16353 Imm *= Src2.getSimpleValueType().getVectorNumElements();
16354 Src3 = DAG.getTargetConstant(Imm, dl, MVT::i32);
16357 // We specify 2 possible opcodes for intrinsics with rounding modes.
16358 // First, we check if the intrinsic may have non-default rounding mode,
16359 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16360 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16361 if (IntrWithRoundingModeOpcode != 0) {
16362 SDValue Rnd = Op.getOperand(6);
16363 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16364 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16365 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16366 dl, Op.getValueType(),
16367 Src1, Src2, Src3, Rnd),
16368 Mask, PassThru, Subtarget, DAG);
16371 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16373 Mask, PassThru, Subtarget, DAG);
16375 case VPERM_3OP_MASKZ:
16376 case VPERM_3OP_MASK:{
16377 // Src2 is the PassThru
16378 SDValue Src1 = Op.getOperand(1);
16379 SDValue Src2 = Op.getOperand(2);
16380 SDValue Src3 = Op.getOperand(3);
16381 SDValue Mask = Op.getOperand(4);
16382 MVT VT = Op.getSimpleValueType();
16383 SDValue PassThru = SDValue();
16385 // set PassThru element
16386 if (IntrData->Type == VPERM_3OP_MASKZ)
16387 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16389 PassThru = DAG.getBitcast(VT, Src2);
16391 // Swap Src1 and Src2 in the node creation
16392 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
16393 dl, Op.getValueType(),
16395 Mask, PassThru, Subtarget, DAG);
16399 case FMA_OP_MASK: {
16400 SDValue Src1 = Op.getOperand(1);
16401 SDValue Src2 = Op.getOperand(2);
16402 SDValue Src3 = Op.getOperand(3);
16403 SDValue Mask = Op.getOperand(4);
16404 MVT VT = Op.getSimpleValueType();
16405 SDValue PassThru = SDValue();
16407 // set PassThru element
16408 if (IntrData->Type == FMA_OP_MASKZ)
16409 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16410 else if (IntrData->Type == FMA_OP_MASK3)
16415 // We specify 2 possible opcodes for intrinsics with rounding modes.
16416 // First, we check if the intrinsic may have non-default rounding mode,
16417 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16418 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16419 if (IntrWithRoundingModeOpcode != 0) {
16420 SDValue Rnd = Op.getOperand(5);
16421 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16422 X86::STATIC_ROUNDING::CUR_DIRECTION)
16423 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16424 dl, Op.getValueType(),
16425 Src1, Src2, Src3, Rnd),
16426 Mask, PassThru, Subtarget, DAG);
16428 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
16429 dl, Op.getValueType(),
16431 Mask, PassThru, Subtarget, DAG);
16433 case TERLOG_OP_MASK:
16434 case TERLOG_OP_MASKZ: {
16435 SDValue Src1 = Op.getOperand(1);
16436 SDValue Src2 = Op.getOperand(2);
16437 SDValue Src3 = Op.getOperand(3);
16438 SDValue Src4 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(4));
16439 SDValue Mask = Op.getOperand(5);
16440 MVT VT = Op.getSimpleValueType();
16441 SDValue PassThru = Src1;
16442 // Set PassThru element.
16443 if (IntrData->Type == TERLOG_OP_MASKZ)
16444 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16446 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16447 Src1, Src2, Src3, Src4),
16448 Mask, PassThru, Subtarget, DAG);
16451 // FPclass intrinsics with mask
16452 SDValue Src1 = Op.getOperand(1);
16453 MVT VT = Src1.getSimpleValueType();
16454 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16455 SDValue Imm = Op.getOperand(2);
16456 SDValue Mask = Op.getOperand(3);
16457 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16458 Mask.getSimpleValueType().getSizeInBits());
16459 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MaskVT, Src1, Imm);
16460 SDValue FPclassMask = getVectorMaskingNode(FPclass, Mask,
16461 DAG.getTargetConstant(0, dl, MaskVT),
16463 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16464 DAG.getUNDEF(BitcastVT), FPclassMask,
16465 DAG.getIntPtrConstant(0, dl));
16466 return DAG.getBitcast(Op.getValueType(), Res);
16469 SDValue Src1 = Op.getOperand(1);
16470 SDValue Imm = Op.getOperand(2);
16471 SDValue Mask = Op.getOperand(3);
16472 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Imm);
16473 SDValue FPclassMask = getScalarMaskingNode(FPclass, Mask,
16474 DAG.getTargetConstant(0, dl, MVT::i1), Subtarget, DAG);
16475 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i8, FPclassMask);
16478 case CMP_MASK_CC: {
16479 // Comparison intrinsics with masks.
16480 // Example of transformation:
16481 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16482 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16484 // (v8i1 (insert_subvector undef,
16485 // (v2i1 (and (PCMPEQM %a, %b),
16486 // (extract_subvector
16487 // (v8i1 (bitcast %mask)), 0))), 0))))
16488 MVT VT = Op.getOperand(1).getSimpleValueType();
16489 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16490 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16491 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16492 Mask.getSimpleValueType().getSizeInBits());
16494 if (IntrData->Type == CMP_MASK_CC) {
16495 SDValue CC = Op.getOperand(3);
16496 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
16497 // We specify 2 possible opcodes for intrinsics with rounding modes.
16498 // First, we check if the intrinsic may have non-default rounding mode,
16499 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16500 if (IntrData->Opc1 != 0) {
16501 SDValue Rnd = Op.getOperand(5);
16502 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16503 X86::STATIC_ROUNDING::CUR_DIRECTION)
16504 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
16505 Op.getOperand(2), CC, Rnd);
16507 //default rounding mode
16509 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16510 Op.getOperand(2), CC);
16513 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16514 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16517 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16518 DAG.getTargetConstant(0, dl,
16521 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16522 DAG.getUNDEF(BitcastVT), CmpMask,
16523 DAG.getIntPtrConstant(0, dl));
16524 return DAG.getBitcast(Op.getValueType(), Res);
16526 case CMP_MASK_SCALAR_CC: {
16527 SDValue Src1 = Op.getOperand(1);
16528 SDValue Src2 = Op.getOperand(2);
16529 SDValue CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(3));
16530 SDValue Mask = Op.getOperand(4);
16533 if (IntrData->Opc1 != 0) {
16534 SDValue Rnd = Op.getOperand(5);
16535 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16536 X86::STATIC_ROUNDING::CUR_DIRECTION)
16537 Cmp = DAG.getNode(IntrData->Opc1, dl, MVT::i1, Src1, Src2, CC, Rnd);
16539 //default rounding mode
16541 Cmp = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Src2, CC);
16543 SDValue CmpMask = getScalarMaskingNode(Cmp, Mask,
16544 DAG.getTargetConstant(0, dl,
16548 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i8,
16549 DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i8, CmpMask),
16550 DAG.getValueType(MVT::i1));
16552 case COMI: { // Comparison intrinsics
16553 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16554 SDValue LHS = Op.getOperand(1);
16555 SDValue RHS = Op.getOperand(2);
16556 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
16557 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16558 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16559 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16560 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
16561 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16563 case COMI_RM: { // Comparison intrinsics with Sae
16564 SDValue LHS = Op.getOperand(1);
16565 SDValue RHS = Op.getOperand(2);
16566 SDValue CC = Op.getOperand(3);
16567 SDValue Sae = Op.getOperand(4);
16568 auto ComiType = TranslateX86ConstCondToX86CC(CC);
16569 // choose between ordered and unordered (comi/ucomi)
16570 unsigned comiOp = std::get<0>(ComiType) ? IntrData->Opc0 : IntrData->Opc1;
16572 if (cast<ConstantSDNode>(Sae)->getZExtValue() !=
16573 X86::STATIC_ROUNDING::CUR_DIRECTION)
16574 Cond = DAG.getNode(comiOp, dl, MVT::i32, LHS, RHS, Sae);
16576 Cond = DAG.getNode(comiOp, dl, MVT::i32, LHS, RHS);
16577 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16578 DAG.getConstant(std::get<1>(ComiType), dl, MVT::i8), Cond);
16579 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16582 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16583 Op.getOperand(1), Op.getOperand(2), DAG);
16585 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
16586 Op.getSimpleValueType(),
16588 Op.getOperand(2), DAG),
16589 Op.getOperand(4), Op.getOperand(3), Subtarget,
16591 case COMPRESS_EXPAND_IN_REG: {
16592 SDValue Mask = Op.getOperand(3);
16593 SDValue DataToCompress = Op.getOperand(1);
16594 SDValue PassThru = Op.getOperand(2);
16595 if (isAllOnesConstant(Mask)) // return data as is
16596 return Op.getOperand(1);
16598 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16600 Mask, PassThru, Subtarget, DAG);
16603 SDValue Mask = Op.getOperand(1);
16604 MVT MaskVT = MVT::getVectorVT(MVT::i1, Mask.getSimpleValueType().getSizeInBits());
16605 Mask = DAG.getBitcast(MaskVT, Mask);
16606 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Mask);
16609 SDValue Mask = Op.getOperand(3);
16610 MVT VT = Op.getSimpleValueType();
16611 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16612 SDValue VMask = getMaskNode(Mask, MaskVT, Subtarget, DAG, dl);
16613 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
16617 MVT VT = Op.getSimpleValueType();
16618 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getSizeInBits()/2);
16620 SDValue Src1 = getMaskNode(Op.getOperand(1), MaskVT, Subtarget, DAG, dl);
16621 SDValue Src2 = getMaskNode(Op.getOperand(2), MaskVT, Subtarget, DAG, dl);
16622 // Arguments should be swapped.
16623 SDValue Res = DAG.getNode(IntrData->Opc0, dl,
16624 MVT::getVectorVT(MVT::i1, VT.getSizeInBits()),
16626 return DAG.getBitcast(VT, Res);
16634 default: return SDValue(); // Don't custom lower most intrinsics.
16636 case Intrinsic::x86_avx2_permd:
16637 case Intrinsic::x86_avx2_permps:
16638 // Operands intentionally swapped. Mask is last operand to intrinsic,
16639 // but second operand for node/instruction.
16640 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16641 Op.getOperand(2), Op.getOperand(1));
16643 // ptest and testp intrinsics. The intrinsic these come from are designed to
16644 // return an integer value, not just an instruction so lower it to the ptest
16645 // or testp pattern and a setcc for the result.
16646 case Intrinsic::x86_sse41_ptestz:
16647 case Intrinsic::x86_sse41_ptestc:
16648 case Intrinsic::x86_sse41_ptestnzc:
16649 case Intrinsic::x86_avx_ptestz_256:
16650 case Intrinsic::x86_avx_ptestc_256:
16651 case Intrinsic::x86_avx_ptestnzc_256:
16652 case Intrinsic::x86_avx_vtestz_ps:
16653 case Intrinsic::x86_avx_vtestc_ps:
16654 case Intrinsic::x86_avx_vtestnzc_ps:
16655 case Intrinsic::x86_avx_vtestz_pd:
16656 case Intrinsic::x86_avx_vtestc_pd:
16657 case Intrinsic::x86_avx_vtestnzc_pd:
16658 case Intrinsic::x86_avx_vtestz_ps_256:
16659 case Intrinsic::x86_avx_vtestc_ps_256:
16660 case Intrinsic::x86_avx_vtestnzc_ps_256:
16661 case Intrinsic::x86_avx_vtestz_pd_256:
16662 case Intrinsic::x86_avx_vtestc_pd_256:
16663 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16664 bool IsTestPacked = false;
16667 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16668 case Intrinsic::x86_avx_vtestz_ps:
16669 case Intrinsic::x86_avx_vtestz_pd:
16670 case Intrinsic::x86_avx_vtestz_ps_256:
16671 case Intrinsic::x86_avx_vtestz_pd_256:
16672 IsTestPacked = true; // Fallthrough
16673 case Intrinsic::x86_sse41_ptestz:
16674 case Intrinsic::x86_avx_ptestz_256:
16676 X86CC = X86::COND_E;
16678 case Intrinsic::x86_avx_vtestc_ps:
16679 case Intrinsic::x86_avx_vtestc_pd:
16680 case Intrinsic::x86_avx_vtestc_ps_256:
16681 case Intrinsic::x86_avx_vtestc_pd_256:
16682 IsTestPacked = true; // Fallthrough
16683 case Intrinsic::x86_sse41_ptestc:
16684 case Intrinsic::x86_avx_ptestc_256:
16686 X86CC = X86::COND_B;
16688 case Intrinsic::x86_avx_vtestnzc_ps:
16689 case Intrinsic::x86_avx_vtestnzc_pd:
16690 case Intrinsic::x86_avx_vtestnzc_ps_256:
16691 case Intrinsic::x86_avx_vtestnzc_pd_256:
16692 IsTestPacked = true; // Fallthrough
16693 case Intrinsic::x86_sse41_ptestnzc:
16694 case Intrinsic::x86_avx_ptestnzc_256:
16696 X86CC = X86::COND_A;
16700 SDValue LHS = Op.getOperand(1);
16701 SDValue RHS = Op.getOperand(2);
16702 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16703 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16704 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16705 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16706 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16708 case Intrinsic::x86_avx512_kortestz_w:
16709 case Intrinsic::x86_avx512_kortestc_w: {
16710 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16711 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
16712 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
16713 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16714 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16715 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16716 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16719 case Intrinsic::x86_sse42_pcmpistria128:
16720 case Intrinsic::x86_sse42_pcmpestria128:
16721 case Intrinsic::x86_sse42_pcmpistric128:
16722 case Intrinsic::x86_sse42_pcmpestric128:
16723 case Intrinsic::x86_sse42_pcmpistrio128:
16724 case Intrinsic::x86_sse42_pcmpestrio128:
16725 case Intrinsic::x86_sse42_pcmpistris128:
16726 case Intrinsic::x86_sse42_pcmpestris128:
16727 case Intrinsic::x86_sse42_pcmpistriz128:
16728 case Intrinsic::x86_sse42_pcmpestriz128: {
16732 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16733 case Intrinsic::x86_sse42_pcmpistria128:
16734 Opcode = X86ISD::PCMPISTRI;
16735 X86CC = X86::COND_A;
16737 case Intrinsic::x86_sse42_pcmpestria128:
16738 Opcode = X86ISD::PCMPESTRI;
16739 X86CC = X86::COND_A;
16741 case Intrinsic::x86_sse42_pcmpistric128:
16742 Opcode = X86ISD::PCMPISTRI;
16743 X86CC = X86::COND_B;
16745 case Intrinsic::x86_sse42_pcmpestric128:
16746 Opcode = X86ISD::PCMPESTRI;
16747 X86CC = X86::COND_B;
16749 case Intrinsic::x86_sse42_pcmpistrio128:
16750 Opcode = X86ISD::PCMPISTRI;
16751 X86CC = X86::COND_O;
16753 case Intrinsic::x86_sse42_pcmpestrio128:
16754 Opcode = X86ISD::PCMPESTRI;
16755 X86CC = X86::COND_O;
16757 case Intrinsic::x86_sse42_pcmpistris128:
16758 Opcode = X86ISD::PCMPISTRI;
16759 X86CC = X86::COND_S;
16761 case Intrinsic::x86_sse42_pcmpestris128:
16762 Opcode = X86ISD::PCMPESTRI;
16763 X86CC = X86::COND_S;
16765 case Intrinsic::x86_sse42_pcmpistriz128:
16766 Opcode = X86ISD::PCMPISTRI;
16767 X86CC = X86::COND_E;
16769 case Intrinsic::x86_sse42_pcmpestriz128:
16770 Opcode = X86ISD::PCMPESTRI;
16771 X86CC = X86::COND_E;
16774 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16775 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16776 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16777 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16778 DAG.getConstant(X86CC, dl, MVT::i8),
16779 SDValue(PCMP.getNode(), 1));
16780 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16783 case Intrinsic::x86_sse42_pcmpistri128:
16784 case Intrinsic::x86_sse42_pcmpestri128: {
16786 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16787 Opcode = X86ISD::PCMPISTRI;
16789 Opcode = X86ISD::PCMPESTRI;
16791 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16792 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16793 return DAG.getNode(Opcode, dl, VTs, NewOps);
16796 case Intrinsic::x86_seh_lsda: {
16797 // Compute the symbol for the LSDA. We know it'll get emitted later.
16798 MachineFunction &MF = DAG.getMachineFunction();
16799 SDValue Op1 = Op.getOperand(1);
16800 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
16801 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
16802 GlobalValue::getRealLinkageName(Fn->getName()));
16804 // Generate a simple absolute symbol reference. This intrinsic is only
16805 // supported on 32-bit Windows, which isn't PIC.
16806 SDValue Result = DAG.getMCSymbol(LSDASym, VT);
16807 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
16810 case Intrinsic::x86_seh_recoverfp: {
16811 SDValue FnOp = Op.getOperand(1);
16812 SDValue IncomingFPOp = Op.getOperand(2);
16813 GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(FnOp);
16814 auto *Fn = dyn_cast_or_null<Function>(GSD ? GSD->getGlobal() : nullptr);
16816 report_fatal_error(
16817 "llvm.x86.seh.recoverfp must take a function as the first argument");
16818 return recoverFramePointer(DAG, Fn, IncomingFPOp);
16821 case Intrinsic::localaddress: {
16822 // Returns one of the stack, base, or frame pointer registers, depending on
16823 // which is used to reference local variables.
16824 MachineFunction &MF = DAG.getMachineFunction();
16825 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16827 if (RegInfo->hasBasePointer(MF))
16828 Reg = RegInfo->getBaseRegister();
16829 else // This function handles the SP or FP case.
16830 Reg = RegInfo->getPtrSizedFrameRegister(MF);
16831 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
16836 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16837 SDValue Src, SDValue Mask, SDValue Base,
16838 SDValue Index, SDValue ScaleOp, SDValue Chain,
16839 const X86Subtarget * Subtarget) {
16841 auto *C = cast<ConstantSDNode>(ScaleOp);
16842 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16843 MVT MaskVT = MVT::getVectorVT(MVT::i1,
16844 Index.getSimpleValueType().getVectorNumElements());
16846 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16848 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16850 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16851 Mask.getSimpleValueType().getSizeInBits());
16853 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16854 // are extracted by EXTRACT_SUBVECTOR.
16855 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16856 DAG.getBitcast(BitcastVT, Mask),
16857 DAG.getIntPtrConstant(0, dl));
16859 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16860 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16861 SDValue Segment = DAG.getRegister(0, MVT::i32);
16862 if (Src.getOpcode() == ISD::UNDEF)
16863 Src = getZeroVector(Op.getSimpleValueType(), Subtarget, DAG, dl);
16864 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16865 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16866 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16867 return DAG.getMergeValues(RetOps, dl);
16870 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16871 SDValue Src, SDValue Mask, SDValue Base,
16872 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16874 auto *C = cast<ConstantSDNode>(ScaleOp);
16875 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16876 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16877 SDValue Segment = DAG.getRegister(0, MVT::i32);
16878 MVT MaskVT = MVT::getVectorVT(MVT::i1,
16879 Index.getSimpleValueType().getVectorNumElements());
16881 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16883 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16885 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16886 Mask.getSimpleValueType().getSizeInBits());
16888 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16889 // are extracted by EXTRACT_SUBVECTOR.
16890 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16891 DAG.getBitcast(BitcastVT, Mask),
16892 DAG.getIntPtrConstant(0, dl));
16894 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16895 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16896 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16897 return SDValue(Res, 1);
16900 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16901 SDValue Mask, SDValue Base, SDValue Index,
16902 SDValue ScaleOp, SDValue Chain) {
16904 auto *C = cast<ConstantSDNode>(ScaleOp);
16905 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16906 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16907 SDValue Segment = DAG.getRegister(0, MVT::i32);
16909 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16911 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16913 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16915 MaskInReg = DAG.getBitcast(MaskVT, Mask);
16916 //SDVTList VTs = DAG.getVTList(MVT::Other);
16917 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16918 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16919 return SDValue(Res, 0);
16922 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16923 // read performance monitor counters (x86_rdpmc).
16924 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16925 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16926 SmallVectorImpl<SDValue> &Results) {
16927 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16928 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16931 // The ECX register is used to select the index of the performance counter
16933 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16935 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16937 // Reads the content of a 64-bit performance counter and returns it in the
16938 // registers EDX:EAX.
16939 if (Subtarget->is64Bit()) {
16940 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16941 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16944 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16945 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16948 Chain = HI.getValue(1);
16950 if (Subtarget->is64Bit()) {
16951 // The EAX register is loaded with the low-order 32 bits. The EDX register
16952 // is loaded with the supported high-order bits of the counter.
16953 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16954 DAG.getConstant(32, DL, MVT::i8));
16955 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16956 Results.push_back(Chain);
16960 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16961 SDValue Ops[] = { LO, HI };
16962 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16963 Results.push_back(Pair);
16964 Results.push_back(Chain);
16967 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16968 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16969 // also used to custom lower READCYCLECOUNTER nodes.
16970 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16971 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16972 SmallVectorImpl<SDValue> &Results) {
16973 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16974 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16977 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16978 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16979 // and the EAX register is loaded with the low-order 32 bits.
16980 if (Subtarget->is64Bit()) {
16981 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16982 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16985 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16986 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16989 SDValue Chain = HI.getValue(1);
16991 if (Opcode == X86ISD::RDTSCP_DAG) {
16992 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16994 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16995 // the ECX register. Add 'ecx' explicitly to the chain.
16996 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16998 // Explicitly store the content of ECX at the location passed in input
16999 // to the 'rdtscp' intrinsic.
17000 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
17001 MachinePointerInfo(), false, false, 0);
17004 if (Subtarget->is64Bit()) {
17005 // The EDX register is loaded with the high-order 32 bits of the MSR, and
17006 // the EAX register is loaded with the low-order 32 bits.
17007 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17008 DAG.getConstant(32, DL, MVT::i8));
17009 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17010 Results.push_back(Chain);
17014 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17015 SDValue Ops[] = { LO, HI };
17016 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17017 Results.push_back(Pair);
17018 Results.push_back(Chain);
17021 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17022 SelectionDAG &DAG) {
17023 SmallVector<SDValue, 2> Results;
17025 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17027 return DAG.getMergeValues(Results, DL);
17030 static SDValue LowerSEHRESTOREFRAME(SDValue Op, const X86Subtarget *Subtarget,
17031 SelectionDAG &DAG) {
17032 MachineFunction &MF = DAG.getMachineFunction();
17033 const Function *Fn = MF.getFunction();
17035 SDValue Chain = Op.getOperand(0);
17037 assert(Subtarget->getFrameLowering()->hasFP(MF) &&
17038 "using llvm.x86.seh.restoreframe requires a frame pointer");
17040 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17041 MVT VT = TLI.getPointerTy(DAG.getDataLayout());
17043 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17044 unsigned FrameReg =
17045 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17046 unsigned SPReg = RegInfo->getStackRegister();
17047 unsigned SlotSize = RegInfo->getSlotSize();
17049 // Get incoming EBP.
17050 SDValue IncomingEBP =
17051 DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
17053 // SP is saved in the first field of every registration node, so load
17054 // [EBP-RegNodeSize] into SP.
17055 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
17056 SDValue SPAddr = DAG.getNode(ISD::ADD, dl, VT, IncomingEBP,
17057 DAG.getConstant(-RegNodeSize, dl, VT));
17059 DAG.getLoad(VT, dl, Chain, SPAddr, MachinePointerInfo(), false, false,
17060 false, VT.getScalarSizeInBits() / 8);
17061 Chain = DAG.getCopyToReg(Chain, dl, SPReg, NewSP);
17063 if (!RegInfo->needsStackRealignment(MF)) {
17064 // Adjust EBP to point back to the original frame position.
17065 SDValue NewFP = recoverFramePointer(DAG, Fn, IncomingEBP);
17066 Chain = DAG.getCopyToReg(Chain, dl, FrameReg, NewFP);
17068 assert(RegInfo->hasBasePointer(MF) &&
17069 "functions with Win32 EH must use frame or base pointer register");
17071 // Reload the base pointer (ESI) with the adjusted incoming EBP.
17072 SDValue NewBP = recoverFramePointer(DAG, Fn, IncomingEBP);
17073 Chain = DAG.getCopyToReg(Chain, dl, RegInfo->getBaseRegister(), NewBP);
17075 // Reload the spilled EBP value, now that the stack and base pointers are
17077 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
17078 X86FI->setHasSEHFramePtrSave(true);
17079 int FI = MF.getFrameInfo()->CreateSpillStackObject(SlotSize, SlotSize);
17080 X86FI->setSEHFramePtrSaveIndex(FI);
17081 SDValue NewFP = DAG.getLoad(VT, dl, Chain, DAG.getFrameIndex(FI, VT),
17082 MachinePointerInfo(), false, false, false,
17083 VT.getScalarSizeInBits() / 8);
17084 Chain = DAG.getCopyToReg(NewFP, dl, FrameReg, NewFP);
17090 static SDValue MarkEHRegistrationNode(SDValue Op, SelectionDAG &DAG) {
17091 MachineFunction &MF = DAG.getMachineFunction();
17092 SDValue Chain = Op.getOperand(0);
17093 SDValue RegNode = Op.getOperand(2);
17094 WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo();
17096 report_fatal_error("EH registrations only live in functions using WinEH");
17098 // Cast the operand to an alloca, and remember the frame index.
17099 auto *FINode = dyn_cast<FrameIndexSDNode>(RegNode);
17101 report_fatal_error("llvm.x86.seh.ehregnode expects a static alloca");
17102 EHInfo->EHRegNodeFrameIndex = FINode->getIndex();
17104 // Return the chain operand without making any DAG nodes.
17108 /// \brief Lower intrinsics for TRUNCATE_TO_MEM case
17109 /// return truncate Store/MaskedStore Node
17110 static SDValue LowerINTRINSIC_TRUNCATE_TO_MEM(const SDValue & Op,
17114 SDValue Mask = Op.getOperand(4);
17115 SDValue DataToTruncate = Op.getOperand(3);
17116 SDValue Addr = Op.getOperand(2);
17117 SDValue Chain = Op.getOperand(0);
17119 MVT VT = DataToTruncate.getSimpleValueType();
17120 MVT SVT = MVT::getVectorVT(ElementType, VT.getVectorNumElements());
17122 if (isAllOnesConstant(Mask)) // return just a truncate store
17123 return DAG.getTruncStore(Chain, dl, DataToTruncate, Addr,
17124 MachinePointerInfo(), SVT, false, false,
17125 SVT.getScalarSizeInBits()/8);
17127 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
17128 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
17129 Mask.getSimpleValueType().getSizeInBits());
17130 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
17131 // are extracted by EXTRACT_SUBVECTOR.
17132 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17133 DAG.getBitcast(BitcastVT, Mask),
17134 DAG.getIntPtrConstant(0, dl));
17136 MachineMemOperand *MMO = DAG.getMachineFunction().
17137 getMachineMemOperand(MachinePointerInfo(),
17138 MachineMemOperand::MOStore, SVT.getStoreSize(),
17139 SVT.getScalarSizeInBits()/8);
17141 return DAG.getMaskedStore(Chain, dl, DataToTruncate, Addr,
17142 VMask, SVT, MMO, true);
17145 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17146 SelectionDAG &DAG) {
17147 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17149 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17151 if (IntNo == llvm::Intrinsic::x86_seh_restoreframe)
17152 return LowerSEHRESTOREFRAME(Op, Subtarget, DAG);
17153 else if (IntNo == llvm::Intrinsic::x86_seh_ehregnode)
17154 return MarkEHRegistrationNode(Op, DAG);
17159 switch(IntrData->Type) {
17160 default: llvm_unreachable("Unknown Intrinsic Type");
17163 // Emit the node with the right value type.
17164 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17165 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17167 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17168 // Otherwise return the value from Rand, which is always 0, casted to i32.
17169 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17170 DAG.getConstant(1, dl, Op->getValueType(1)),
17171 DAG.getConstant(X86::COND_B, dl, MVT::i32),
17172 SDValue(Result.getNode(), 1) };
17173 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17174 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17177 // Return { result, isValid, chain }.
17178 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17179 SDValue(Result.getNode(), 2));
17182 //gather(v1, mask, index, base, scale);
17183 SDValue Chain = Op.getOperand(0);
17184 SDValue Src = Op.getOperand(2);
17185 SDValue Base = Op.getOperand(3);
17186 SDValue Index = Op.getOperand(4);
17187 SDValue Mask = Op.getOperand(5);
17188 SDValue Scale = Op.getOperand(6);
17189 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
17193 //scatter(base, mask, index, v1, scale);
17194 SDValue Chain = Op.getOperand(0);
17195 SDValue Base = Op.getOperand(2);
17196 SDValue Mask = Op.getOperand(3);
17197 SDValue Index = Op.getOperand(4);
17198 SDValue Src = Op.getOperand(5);
17199 SDValue Scale = Op.getOperand(6);
17200 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
17204 SDValue Hint = Op.getOperand(6);
17205 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
17206 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
17207 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17208 SDValue Chain = Op.getOperand(0);
17209 SDValue Mask = Op.getOperand(2);
17210 SDValue Index = Op.getOperand(3);
17211 SDValue Base = Op.getOperand(4);
17212 SDValue Scale = Op.getOperand(5);
17213 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17215 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17217 SmallVector<SDValue, 2> Results;
17218 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
17220 return DAG.getMergeValues(Results, dl);
17222 // Read Performance Monitoring Counters.
17224 SmallVector<SDValue, 2> Results;
17225 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17226 return DAG.getMergeValues(Results, dl);
17228 // XTEST intrinsics.
17230 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17231 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17232 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17233 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
17235 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17236 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17237 Ret, SDValue(InTrans.getNode(), 1));
17241 SmallVector<SDValue, 2> Results;
17242 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17243 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17244 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17245 DAG.getConstant(-1, dl, MVT::i8));
17246 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17247 Op.getOperand(4), GenCF.getValue(1));
17248 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17249 Op.getOperand(5), MachinePointerInfo(),
17251 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17252 DAG.getConstant(X86::COND_B, dl, MVT::i8),
17254 Results.push_back(SetCC);
17255 Results.push_back(Store);
17256 return DAG.getMergeValues(Results, dl);
17258 case COMPRESS_TO_MEM: {
17260 SDValue Mask = Op.getOperand(4);
17261 SDValue DataToCompress = Op.getOperand(3);
17262 SDValue Addr = Op.getOperand(2);
17263 SDValue Chain = Op.getOperand(0);
17265 MVT VT = DataToCompress.getSimpleValueType();
17266 if (isAllOnesConstant(Mask)) // return just a store
17267 return DAG.getStore(Chain, dl, DataToCompress, Addr,
17268 MachinePointerInfo(), false, false,
17269 VT.getScalarSizeInBits()/8);
17271 SDValue Compressed =
17272 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToCompress),
17273 Mask, DAG.getUNDEF(VT), Subtarget, DAG);
17274 return DAG.getStore(Chain, dl, Compressed, Addr,
17275 MachinePointerInfo(), false, false,
17276 VT.getScalarSizeInBits()/8);
17278 case TRUNCATE_TO_MEM_VI8:
17279 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i8);
17280 case TRUNCATE_TO_MEM_VI16:
17281 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i16);
17282 case TRUNCATE_TO_MEM_VI32:
17283 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i32);
17284 case EXPAND_FROM_MEM: {
17286 SDValue Mask = Op.getOperand(4);
17287 SDValue PassThru = Op.getOperand(3);
17288 SDValue Addr = Op.getOperand(2);
17289 SDValue Chain = Op.getOperand(0);
17290 MVT VT = Op.getSimpleValueType();
17292 if (isAllOnesConstant(Mask)) // return just a load
17293 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
17294 false, VT.getScalarSizeInBits()/8);
17296 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
17297 false, false, false,
17298 VT.getScalarSizeInBits()/8);
17300 SDValue Results[] = {
17301 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToExpand),
17302 Mask, PassThru, Subtarget, DAG), Chain};
17303 return DAG.getMergeValues(Results, dl);
17308 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17309 SelectionDAG &DAG) const {
17310 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17311 MFI->setReturnAddressIsTaken(true);
17313 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17316 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17318 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17321 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17322 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17323 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
17324 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17325 DAG.getNode(ISD::ADD, dl, PtrVT,
17326 FrameAddr, Offset),
17327 MachinePointerInfo(), false, false, false, 0);
17330 // Just load the return address.
17331 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17332 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17333 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17336 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17337 MachineFunction &MF = DAG.getMachineFunction();
17338 MachineFrameInfo *MFI = MF.getFrameInfo();
17339 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
17340 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17341 EVT VT = Op.getValueType();
17343 MFI->setFrameAddressIsTaken(true);
17345 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
17346 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
17347 // is not possible to crawl up the stack without looking at the unwind codes
17349 int FrameAddrIndex = FuncInfo->getFAIndex();
17350 if (!FrameAddrIndex) {
17351 // Set up a frame object for the return address.
17352 unsigned SlotSize = RegInfo->getSlotSize();
17353 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
17354 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
17355 FuncInfo->setFAIndex(FrameAddrIndex);
17357 return DAG.getFrameIndex(FrameAddrIndex, VT);
17360 unsigned FrameReg =
17361 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17362 SDLoc dl(Op); // FIXME probably not meaningful
17363 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17364 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17365 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17366 "Invalid Frame Register!");
17367 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17369 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17370 MachinePointerInfo(),
17371 false, false, false, 0);
17375 // FIXME? Maybe this could be a TableGen attribute on some registers and
17376 // this table could be generated automatically from RegInfo.
17377 unsigned X86TargetLowering::getRegisterByName(const char* RegName, EVT VT,
17378 SelectionDAG &DAG) const {
17379 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17380 const MachineFunction &MF = DAG.getMachineFunction();
17382 unsigned Reg = StringSwitch<unsigned>(RegName)
17383 .Case("esp", X86::ESP)
17384 .Case("rsp", X86::RSP)
17385 .Case("ebp", X86::EBP)
17386 .Case("rbp", X86::RBP)
17389 if (Reg == X86::EBP || Reg == X86::RBP) {
17390 if (!TFI.hasFP(MF))
17391 report_fatal_error("register " + StringRef(RegName) +
17392 " is allocatable: function has no frame pointer");
17395 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17396 unsigned FrameReg =
17397 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17398 assert((FrameReg == X86::EBP || FrameReg == X86::RBP) &&
17399 "Invalid Frame Register!");
17407 report_fatal_error("Invalid register name global variable");
17410 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17411 SelectionDAG &DAG) const {
17412 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17413 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
17416 unsigned X86TargetLowering::getExceptionPointerRegister(
17417 const Constant *PersonalityFn) const {
17418 if (classifyEHPersonality(PersonalityFn) == EHPersonality::CoreCLR)
17419 return Subtarget->isTarget64BitLP64() ? X86::RDX : X86::EDX;
17421 return Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX;
17424 unsigned X86TargetLowering::getExceptionSelectorRegister(
17425 const Constant *PersonalityFn) const {
17426 // Funclet personalities don't use selectors (the runtime does the selection).
17427 assert(!isFuncletEHPersonality(classifyEHPersonality(PersonalityFn)));
17428 return Subtarget->isTarget64BitLP64() ? X86::RDX : X86::EDX;
17431 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17432 SDValue Chain = Op.getOperand(0);
17433 SDValue Offset = Op.getOperand(1);
17434 SDValue Handler = Op.getOperand(2);
17437 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17438 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17439 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17440 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17441 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17442 "Invalid Frame Register!");
17443 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17444 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17446 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17447 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
17449 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17450 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17452 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17454 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17455 DAG.getRegister(StoreAddrReg, PtrVT));
17458 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17459 SelectionDAG &DAG) const {
17461 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17462 DAG.getVTList(MVT::i32, MVT::Other),
17463 Op.getOperand(0), Op.getOperand(1));
17466 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17467 SelectionDAG &DAG) const {
17469 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17470 Op.getOperand(0), Op.getOperand(1));
17473 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17474 return Op.getOperand(0);
17477 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17478 SelectionDAG &DAG) const {
17479 SDValue Root = Op.getOperand(0);
17480 SDValue Trmp = Op.getOperand(1); // trampoline
17481 SDValue FPtr = Op.getOperand(2); // nested function
17482 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17485 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17486 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
17488 if (Subtarget->is64Bit()) {
17489 SDValue OutChains[6];
17491 // Large code-model.
17492 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17493 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17495 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17496 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17498 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17500 // Load the pointer to the nested function into R11.
17501 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17502 SDValue Addr = Trmp;
17503 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17504 Addr, MachinePointerInfo(TrmpAddr),
17507 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17508 DAG.getConstant(2, dl, MVT::i64));
17509 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17510 MachinePointerInfo(TrmpAddr, 2),
17513 // Load the 'nest' parameter value into R10.
17514 // R10 is specified in X86CallingConv.td
17515 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17516 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17517 DAG.getConstant(10, dl, MVT::i64));
17518 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17519 Addr, MachinePointerInfo(TrmpAddr, 10),
17522 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17523 DAG.getConstant(12, dl, MVT::i64));
17524 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17525 MachinePointerInfo(TrmpAddr, 12),
17528 // Jump to the nested function.
17529 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17530 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17531 DAG.getConstant(20, dl, MVT::i64));
17532 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17533 Addr, MachinePointerInfo(TrmpAddr, 20),
17536 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17537 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17538 DAG.getConstant(22, dl, MVT::i64));
17539 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
17540 Addr, MachinePointerInfo(TrmpAddr, 22),
17543 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17545 const Function *Func =
17546 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17547 CallingConv::ID CC = Func->getCallingConv();
17552 llvm_unreachable("Unsupported calling convention");
17553 case CallingConv::C:
17554 case CallingConv::X86_StdCall: {
17555 // Pass 'nest' parameter in ECX.
17556 // Must be kept in sync with X86CallingConv.td
17557 NestReg = X86::ECX;
17559 // Check that ECX wasn't needed by an 'inreg' parameter.
17560 FunctionType *FTy = Func->getFunctionType();
17561 const AttributeSet &Attrs = Func->getAttributes();
17563 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17564 unsigned InRegCount = 0;
17567 for (FunctionType::param_iterator I = FTy->param_begin(),
17568 E = FTy->param_end(); I != E; ++I, ++Idx)
17569 if (Attrs.hasAttribute(Idx, Attribute::InReg)) {
17570 auto &DL = DAG.getDataLayout();
17571 // FIXME: should only count parameters that are lowered to integers.
17572 InRegCount += (DL.getTypeSizeInBits(*I) + 31) / 32;
17575 if (InRegCount > 2) {
17576 report_fatal_error("Nest register in use - reduce number of inreg"
17582 case CallingConv::X86_FastCall:
17583 case CallingConv::X86_ThisCall:
17584 case CallingConv::Fast:
17585 // Pass 'nest' parameter in EAX.
17586 // Must be kept in sync with X86CallingConv.td
17587 NestReg = X86::EAX;
17591 SDValue OutChains[4];
17592 SDValue Addr, Disp;
17594 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17595 DAG.getConstant(10, dl, MVT::i32));
17596 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17598 // This is storing the opcode for MOV32ri.
17599 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17600 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17601 OutChains[0] = DAG.getStore(Root, dl,
17602 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
17603 Trmp, MachinePointerInfo(TrmpAddr),
17606 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17607 DAG.getConstant(1, dl, MVT::i32));
17608 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17609 MachinePointerInfo(TrmpAddr, 1),
17612 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17613 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17614 DAG.getConstant(5, dl, MVT::i32));
17615 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
17616 Addr, MachinePointerInfo(TrmpAddr, 5),
17619 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17620 DAG.getConstant(6, dl, MVT::i32));
17621 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17622 MachinePointerInfo(TrmpAddr, 6),
17625 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17629 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17630 SelectionDAG &DAG) const {
17632 The rounding mode is in bits 11:10 of FPSR, and has the following
17634 00 Round to nearest
17639 FLT_ROUNDS, on the other hand, expects the following:
17646 To perform the conversion, we do:
17647 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17650 MachineFunction &MF = DAG.getMachineFunction();
17651 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17652 unsigned StackAlignment = TFI.getStackAlignment();
17653 MVT VT = Op.getSimpleValueType();
17656 // Save FP Control Word to stack slot
17657 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17658 SDValue StackSlot =
17659 DAG.getFrameIndex(SSFI, getPointerTy(DAG.getDataLayout()));
17661 MachineMemOperand *MMO =
17662 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
17663 MachineMemOperand::MOStore, 2, 2);
17665 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17666 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17667 DAG.getVTList(MVT::Other),
17668 Ops, MVT::i16, MMO);
17670 // Load FP Control Word from stack slot
17671 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17672 MachinePointerInfo(), false, false, false, 0);
17674 // Transform as necessary
17676 DAG.getNode(ISD::SRL, DL, MVT::i16,
17677 DAG.getNode(ISD::AND, DL, MVT::i16,
17678 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
17679 DAG.getConstant(11, DL, MVT::i8));
17681 DAG.getNode(ISD::SRL, DL, MVT::i16,
17682 DAG.getNode(ISD::AND, DL, MVT::i16,
17683 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
17684 DAG.getConstant(9, DL, MVT::i8));
17687 DAG.getNode(ISD::AND, DL, MVT::i16,
17688 DAG.getNode(ISD::ADD, DL, MVT::i16,
17689 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17690 DAG.getConstant(1, DL, MVT::i16)),
17691 DAG.getConstant(3, DL, MVT::i16));
17693 return DAG.getNode((VT.getSizeInBits() < 16 ?
17694 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17697 /// \brief Lower a vector CTLZ using native supported vector CTLZ instruction.
17699 // 1. i32/i64 128/256-bit vector (native support require VLX) are expended
17700 // to 512-bit vector.
17701 // 2. i8/i16 vector implemented using dword LZCNT vector instruction
17702 // ( sub(trunc(lzcnt(zext32(x)))) ). In case zext32(x) is illegal,
17703 // split the vector, perform operation on it's Lo a Hi part and
17704 // concatenate the results.
17705 static SDValue LowerVectorCTLZ_AVX512(SDValue Op, SelectionDAG &DAG) {
17707 MVT VT = Op.getSimpleValueType();
17708 MVT EltVT = VT.getVectorElementType();
17709 unsigned NumElems = VT.getVectorNumElements();
17711 if (EltVT == MVT::i64 || EltVT == MVT::i32) {
17712 // Extend to 512 bit vector.
17713 assert((VT.is256BitVector() || VT.is128BitVector()) &&
17714 "Unsupported value type for operation");
17716 MVT NewVT = MVT::getVectorVT(EltVT, 512 / VT.getScalarSizeInBits());
17717 SDValue Vec512 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NewVT,
17718 DAG.getUNDEF(NewVT),
17720 DAG.getIntPtrConstant(0, dl));
17721 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Vec512);
17723 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CtlzNode,
17724 DAG.getIntPtrConstant(0, dl));
17727 assert((EltVT == MVT::i8 || EltVT == MVT::i16) &&
17728 "Unsupported element type");
17730 if (16 < NumElems) {
17731 // Split vector, it's Lo and Hi parts will be handled in next iteration.
17733 std::tie(Lo, Hi) = DAG.SplitVector(Op.getOperand(0), dl);
17734 MVT OutVT = MVT::getVectorVT(EltVT, NumElems/2);
17736 Lo = DAG.getNode(Op.getOpcode(), dl, OutVT, Lo);
17737 Hi = DAG.getNode(Op.getOpcode(), dl, OutVT, Hi);
17739 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi);
17742 MVT NewVT = MVT::getVectorVT(MVT::i32, NumElems);
17744 assert((NewVT.is256BitVector() || NewVT.is512BitVector()) &&
17745 "Unsupported value type for operation");
17747 // Use native supported vector instruction vplzcntd.
17748 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, NewVT, Op.getOperand(0));
17749 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Op);
17750 SDValue TruncNode = DAG.getNode(ISD::TRUNCATE, dl, VT, CtlzNode);
17751 SDValue Delta = DAG.getConstant(32 - EltVT.getSizeInBits(), dl, VT);
17753 return DAG.getNode(ISD::SUB, dl, VT, TruncNode, Delta);
17756 static SDValue LowerCTLZ(SDValue Op, const X86Subtarget *Subtarget,
17757 SelectionDAG &DAG) {
17758 MVT VT = Op.getSimpleValueType();
17760 unsigned NumBits = VT.getSizeInBits();
17763 if (VT.isVector() && Subtarget->hasAVX512())
17764 return LowerVectorCTLZ_AVX512(Op, DAG);
17766 Op = Op.getOperand(0);
17767 if (VT == MVT::i8) {
17768 // Zero extend to i32 since there is not an i8 bsr.
17770 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17773 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17774 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17775 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17777 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17780 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
17781 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17784 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17786 // Finally xor with NumBits-1.
17787 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17788 DAG.getConstant(NumBits - 1, dl, OpVT));
17791 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17795 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, const X86Subtarget *Subtarget,
17796 SelectionDAG &DAG) {
17797 MVT VT = Op.getSimpleValueType();
17799 unsigned NumBits = VT.getSizeInBits();
17802 if (VT.isVector() && Subtarget->hasAVX512())
17803 return LowerVectorCTLZ_AVX512(Op, DAG);
17805 Op = Op.getOperand(0);
17806 if (VT == MVT::i8) {
17807 // Zero extend to i32 since there is not an i8 bsr.
17809 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17812 // Issue a bsr (scan bits in reverse).
17813 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17814 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17816 // And xor with NumBits-1.
17817 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17818 DAG.getConstant(NumBits - 1, dl, OpVT));
17821 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17825 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17826 MVT VT = Op.getSimpleValueType();
17827 unsigned NumBits = VT.getScalarSizeInBits();
17830 if (VT.isVector()) {
17831 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17833 SDValue N0 = Op.getOperand(0);
17834 SDValue Zero = DAG.getConstant(0, dl, VT);
17836 // lsb(x) = (x & -x)
17837 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, N0,
17838 DAG.getNode(ISD::SUB, dl, VT, Zero, N0));
17840 // cttz_undef(x) = (width - 1) - ctlz(lsb)
17841 if (Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF &&
17842 TLI.isOperationLegal(ISD::CTLZ, VT)) {
17843 SDValue WidthMinusOne = DAG.getConstant(NumBits - 1, dl, VT);
17844 return DAG.getNode(ISD::SUB, dl, VT, WidthMinusOne,
17845 DAG.getNode(ISD::CTLZ, dl, VT, LSB));
17848 // cttz(x) = ctpop(lsb - 1)
17849 SDValue One = DAG.getConstant(1, dl, VT);
17850 return DAG.getNode(ISD::CTPOP, dl, VT,
17851 DAG.getNode(ISD::SUB, dl, VT, LSB, One));
17854 assert(Op.getOpcode() == ISD::CTTZ &&
17855 "Only scalar CTTZ requires custom lowering");
17857 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17858 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17859 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op.getOperand(0));
17861 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17864 DAG.getConstant(NumBits, dl, VT),
17865 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17868 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17871 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17872 // ones, and then concatenate the result back.
17873 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17874 MVT VT = Op.getSimpleValueType();
17876 assert(VT.is256BitVector() && VT.isInteger() &&
17877 "Unsupported value type for operation");
17879 unsigned NumElems = VT.getVectorNumElements();
17882 // Extract the LHS vectors
17883 SDValue LHS = Op.getOperand(0);
17884 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17885 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17887 // Extract the RHS vectors
17888 SDValue RHS = Op.getOperand(1);
17889 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17890 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17892 MVT EltVT = VT.getVectorElementType();
17893 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17895 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17896 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17897 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17900 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17901 if (Op.getValueType() == MVT::i1)
17902 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17903 Op.getOperand(0), Op.getOperand(1));
17904 assert(Op.getSimpleValueType().is256BitVector() &&
17905 Op.getSimpleValueType().isInteger() &&
17906 "Only handle AVX 256-bit vector integer operation");
17907 return Lower256IntArith(Op, DAG);
17910 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17911 if (Op.getValueType() == MVT::i1)
17912 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17913 Op.getOperand(0), Op.getOperand(1));
17914 assert(Op.getSimpleValueType().is256BitVector() &&
17915 Op.getSimpleValueType().isInteger() &&
17916 "Only handle AVX 256-bit vector integer operation");
17917 return Lower256IntArith(Op, DAG);
17920 static SDValue LowerMINMAX(SDValue Op, SelectionDAG &DAG) {
17921 assert(Op.getSimpleValueType().is256BitVector() &&
17922 Op.getSimpleValueType().isInteger() &&
17923 "Only handle AVX 256-bit vector integer operation");
17924 return Lower256IntArith(Op, DAG);
17927 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17928 SelectionDAG &DAG) {
17930 MVT VT = Op.getSimpleValueType();
17933 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
17935 // Decompose 256-bit ops into smaller 128-bit ops.
17936 if (VT.is256BitVector() && !Subtarget->hasInt256())
17937 return Lower256IntArith(Op, DAG);
17939 SDValue A = Op.getOperand(0);
17940 SDValue B = Op.getOperand(1);
17942 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
17943 // pairs, multiply and truncate.
17944 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
17945 if (Subtarget->hasInt256()) {
17946 if (VT == MVT::v32i8) {
17947 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
17948 SDValue Lo = DAG.getIntPtrConstant(0, dl);
17949 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
17950 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
17951 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
17952 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
17953 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
17954 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17955 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
17956 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
17959 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
17960 return DAG.getNode(
17961 ISD::TRUNCATE, dl, VT,
17962 DAG.getNode(ISD::MUL, dl, ExVT,
17963 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
17964 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
17967 assert(VT == MVT::v16i8 &&
17968 "Pre-AVX2 support only supports v16i8 multiplication");
17969 MVT ExVT = MVT::v8i16;
17971 // Extract the lo parts and sign extend to i16
17973 if (Subtarget->hasSSE41()) {
17974 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
17975 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
17977 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
17978 -1, 4, -1, 5, -1, 6, -1, 7};
17979 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17980 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17981 ALo = DAG.getBitcast(ExVT, ALo);
17982 BLo = DAG.getBitcast(ExVT, BLo);
17983 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
17984 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
17987 // Extract the hi parts and sign extend to i16
17989 if (Subtarget->hasSSE41()) {
17990 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
17991 -1, -1, -1, -1, -1, -1, -1, -1};
17992 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17993 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17994 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
17995 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
17997 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
17998 -1, 12, -1, 13, -1, 14, -1, 15};
17999 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
18000 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
18001 AHi = DAG.getBitcast(ExVT, AHi);
18002 BHi = DAG.getBitcast(ExVT, BHi);
18003 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
18004 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
18007 // Multiply, mask the lower 8bits of the lo/hi results and pack
18008 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
18009 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
18010 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
18011 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
18012 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
18015 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
18016 if (VT == MVT::v4i32) {
18017 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
18018 "Should not custom lower when pmuldq is available!");
18020 // Extract the odd parts.
18021 static const int UnpackMask[] = { 1, -1, 3, -1 };
18022 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
18023 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
18025 // Multiply the even parts.
18026 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
18027 // Now multiply odd parts.
18028 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
18030 Evens = DAG.getBitcast(VT, Evens);
18031 Odds = DAG.getBitcast(VT, Odds);
18033 // Merge the two vectors back together with a shuffle. This expands into 2
18035 static const int ShufMask[] = { 0, 4, 2, 6 };
18036 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
18039 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
18040 "Only know how to lower V2I64/V4I64/V8I64 multiply");
18042 // Ahi = psrlqi(a, 32);
18043 // Bhi = psrlqi(b, 32);
18045 // AloBlo = pmuludq(a, b);
18046 // AloBhi = pmuludq(a, Bhi);
18047 // AhiBlo = pmuludq(Ahi, b);
18049 // AloBhi = psllqi(AloBhi, 32);
18050 // AhiBlo = psllqi(AhiBlo, 32);
18051 // return AloBlo + AloBhi + AhiBlo;
18053 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
18054 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
18056 SDValue AhiBlo = Ahi;
18057 SDValue AloBhi = Bhi;
18058 // Bit cast to 32-bit vectors for MULUDQ
18059 MVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
18060 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
18061 A = DAG.getBitcast(MulVT, A);
18062 B = DAG.getBitcast(MulVT, B);
18063 Ahi = DAG.getBitcast(MulVT, Ahi);
18064 Bhi = DAG.getBitcast(MulVT, Bhi);
18066 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
18067 // After shifting right const values the result may be all-zero.
18068 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
18069 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
18070 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
18072 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
18073 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
18074 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
18077 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
18078 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
18081 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
18082 assert(Subtarget->isTargetWin64() && "Unexpected target");
18083 EVT VT = Op.getValueType();
18084 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
18085 "Unexpected return type for lowering");
18089 switch (Op->getOpcode()) {
18090 default: llvm_unreachable("Unexpected request for libcall!");
18091 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
18092 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
18093 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
18094 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
18095 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
18096 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
18100 SDValue InChain = DAG.getEntryNode();
18102 TargetLowering::ArgListTy Args;
18103 TargetLowering::ArgListEntry Entry;
18104 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
18105 EVT ArgVT = Op->getOperand(i).getValueType();
18106 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
18107 "Unexpected argument type for lowering");
18108 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
18109 Entry.Node = StackPtr;
18110 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
18112 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18113 Entry.Ty = PointerType::get(ArgTy,0);
18114 Entry.isSExt = false;
18115 Entry.isZExt = false;
18116 Args.push_back(Entry);
18119 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
18120 getPointerTy(DAG.getDataLayout()));
18122 TargetLowering::CallLoweringInfo CLI(DAG);
18123 CLI.setDebugLoc(dl).setChain(InChain)
18124 .setCallee(getLibcallCallingConv(LC),
18125 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
18126 Callee, std::move(Args), 0)
18127 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
18129 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
18130 return DAG.getBitcast(VT, CallInfo.first);
18133 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
18134 SelectionDAG &DAG) {
18135 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
18136 MVT VT = Op0.getSimpleValueType();
18139 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
18140 (VT == MVT::v8i32 && Subtarget->hasInt256()));
18142 // PMULxD operations multiply each even value (starting at 0) of LHS with
18143 // the related value of RHS and produce a widen result.
18144 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18145 // => <2 x i64> <ae|cg>
18147 // In other word, to have all the results, we need to perform two PMULxD:
18148 // 1. one with the even values.
18149 // 2. one with the odd values.
18150 // To achieve #2, with need to place the odd values at an even position.
18152 // Place the odd value at an even position (basically, shift all values 1
18153 // step to the left):
18154 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18155 // <a|b|c|d> => <b|undef|d|undef>
18156 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18157 // <e|f|g|h> => <f|undef|h|undef>
18158 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18160 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18162 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18163 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18165 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18166 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18167 // => <2 x i64> <ae|cg>
18168 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18169 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18170 // => <2 x i64> <bf|dh>
18171 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18173 // Shuffle it back into the right order.
18174 SDValue Highs, Lows;
18175 if (VT == MVT::v8i32) {
18176 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18177 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18178 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18179 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18181 const int HighMask[] = {1, 5, 3, 7};
18182 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18183 const int LowMask[] = {0, 4, 2, 6};
18184 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18187 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18188 // unsigned multiply.
18189 if (IsSigned && !Subtarget->hasSSE41()) {
18190 SDValue ShAmt = DAG.getConstant(
18192 DAG.getTargetLoweringInfo().getShiftAmountTy(VT, DAG.getDataLayout()));
18193 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18194 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18195 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18196 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18198 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18199 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18202 // The first result of MUL_LOHI is actually the low value, followed by the
18204 SDValue Ops[] = {Lows, Highs};
18205 return DAG.getMergeValues(Ops, dl);
18208 // Return true if the required (according to Opcode) shift-imm form is natively
18209 // supported by the Subtarget
18210 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
18212 if (VT.getScalarSizeInBits() < 16)
18215 if (VT.is512BitVector() &&
18216 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
18219 bool LShift = VT.is128BitVector() ||
18220 (VT.is256BitVector() && Subtarget->hasInt256());
18222 bool AShift = LShift && (Subtarget->hasVLX() ||
18223 (VT != MVT::v2i64 && VT != MVT::v4i64));
18224 return (Opcode == ISD::SRA) ? AShift : LShift;
18227 // The shift amount is a variable, but it is the same for all vector lanes.
18228 // These instructions are defined together with shift-immediate.
18230 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
18232 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
18235 // Return true if the required (according to Opcode) variable-shift form is
18236 // natively supported by the Subtarget
18237 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
18240 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
18243 // vXi16 supported only on AVX-512, BWI
18244 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
18247 if (VT.is512BitVector() || Subtarget->hasVLX())
18250 bool LShift = VT.is128BitVector() || VT.is256BitVector();
18251 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
18252 return (Opcode == ISD::SRA) ? AShift : LShift;
18255 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18256 const X86Subtarget *Subtarget) {
18257 MVT VT = Op.getSimpleValueType();
18259 SDValue R = Op.getOperand(0);
18260 SDValue Amt = Op.getOperand(1);
18262 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18263 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18265 auto ArithmeticShiftRight64 = [&](uint64_t ShiftAmt) {
18266 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
18267 MVT ExVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2);
18268 SDValue Ex = DAG.getBitcast(ExVT, R);
18270 if (ShiftAmt >= 32) {
18271 // Splat sign to upper i32 dst, and SRA upper i32 src to lower i32.
18273 getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex, 31, DAG);
18274 SDValue Lower = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18275 ShiftAmt - 32, DAG);
18276 if (VT == MVT::v2i64)
18277 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {5, 1, 7, 3});
18278 if (VT == MVT::v4i64)
18279 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18280 {9, 1, 11, 3, 13, 5, 15, 7});
18282 // SRA upper i32, SHL whole i64 and select lower i32.
18283 SDValue Upper = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18286 getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);
18287 Lower = DAG.getBitcast(ExVT, Lower);
18288 if (VT == MVT::v2i64)
18289 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {4, 1, 6, 3});
18290 if (VT == MVT::v4i64)
18291 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18292 {8, 1, 10, 3, 12, 5, 14, 7});
18294 return DAG.getBitcast(VT, Ex);
18297 // Optimize shl/srl/sra with constant shift amount.
18298 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18299 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18300 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18302 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18303 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18305 // i64 SRA needs to be performed as partial shifts.
18306 if ((VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18307 Op.getOpcode() == ISD::SRA && !Subtarget->hasXOP())
18308 return ArithmeticShiftRight64(ShiftAmt);
18310 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
18311 unsigned NumElts = VT.getVectorNumElements();
18312 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
18314 // Simple i8 add case
18315 if (Op.getOpcode() == ISD::SHL && ShiftAmt == 1)
18316 return DAG.getNode(ISD::ADD, dl, VT, R, R);
18318 // ashr(R, 7) === cmp_slt(R, 0)
18319 if (Op.getOpcode() == ISD::SRA && ShiftAmt == 7) {
18320 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18321 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18324 // XOP can shift v16i8 directly instead of as shift v8i16 + mask.
18325 if (VT == MVT::v16i8 && Subtarget->hasXOP())
18328 if (Op.getOpcode() == ISD::SHL) {
18329 // Make a large shift.
18330 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
18332 SHL = DAG.getBitcast(VT, SHL);
18333 // Zero out the rightmost bits.
18334 SmallVector<SDValue, 32> V(
18335 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
18336 return DAG.getNode(ISD::AND, dl, VT, SHL,
18337 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18339 if (Op.getOpcode() == ISD::SRL) {
18340 // Make a large shift.
18341 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
18343 SRL = DAG.getBitcast(VT, SRL);
18344 // Zero out the leftmost bits.
18345 SmallVector<SDValue, 32> V(
18346 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
18347 return DAG.getNode(ISD::AND, dl, VT, SRL,
18348 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18350 if (Op.getOpcode() == ISD::SRA) {
18351 // ashr(R, Amt) === sub(xor(lshr(R, Amt), Mask), Mask)
18352 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18353 SmallVector<SDValue, 32> V(NumElts,
18354 DAG.getConstant(128 >> ShiftAmt, dl,
18356 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18357 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18358 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18361 llvm_unreachable("Unknown shift opcode.");
18366 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18367 if (!Subtarget->is64Bit() && !Subtarget->hasXOP() &&
18368 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64))) {
18370 // Peek through any splat that was introduced for i64 shift vectorization.
18371 int SplatIndex = -1;
18372 if (ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt.getNode()))
18373 if (SVN->isSplat()) {
18374 SplatIndex = SVN->getSplatIndex();
18375 Amt = Amt.getOperand(0);
18376 assert(SplatIndex < (int)VT.getVectorNumElements() &&
18377 "Splat shuffle referencing second operand");
18380 if (Amt.getOpcode() != ISD::BITCAST ||
18381 Amt.getOperand(0).getOpcode() != ISD::BUILD_VECTOR)
18384 Amt = Amt.getOperand(0);
18385 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18386 VT.getVectorNumElements();
18387 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18388 uint64_t ShiftAmt = 0;
18389 unsigned BaseOp = (SplatIndex < 0 ? 0 : SplatIndex * Ratio);
18390 for (unsigned i = 0; i != Ratio; ++i) {
18391 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + BaseOp));
18395 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18398 // Check remaining shift amounts (if not a splat).
18399 if (SplatIndex < 0) {
18400 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18401 uint64_t ShAmt = 0;
18402 for (unsigned j = 0; j != Ratio; ++j) {
18403 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18407 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18409 if (ShAmt != ShiftAmt)
18414 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18415 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18417 if (Op.getOpcode() == ISD::SRA)
18418 return ArithmeticShiftRight64(ShiftAmt);
18424 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18425 const X86Subtarget* Subtarget) {
18426 MVT VT = Op.getSimpleValueType();
18428 SDValue R = Op.getOperand(0);
18429 SDValue Amt = Op.getOperand(1);
18431 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18432 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18434 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
18435 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
18437 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
18439 MVT EltVT = VT.getVectorElementType();
18441 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18442 // Check if this build_vector node is doing a splat.
18443 // If so, then set BaseShAmt equal to the splat value.
18444 BaseShAmt = BV->getSplatValue();
18445 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18446 BaseShAmt = SDValue();
18448 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18449 Amt = Amt.getOperand(0);
18451 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18452 if (SVN && SVN->isSplat()) {
18453 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18454 SDValue InVec = Amt.getOperand(0);
18455 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18456 assert((SplatIdx < InVec.getSimpleValueType().getVectorNumElements()) &&
18457 "Unexpected shuffle index found!");
18458 BaseShAmt = InVec.getOperand(SplatIdx);
18459 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18460 if (ConstantSDNode *C =
18461 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18462 if (C->getZExtValue() == SplatIdx)
18463 BaseShAmt = InVec.getOperand(1);
18468 // Avoid introducing an extract element from a shuffle.
18469 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18470 DAG.getIntPtrConstant(SplatIdx, dl));
18474 if (BaseShAmt.getNode()) {
18475 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18476 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18477 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18478 else if (EltVT.bitsLT(MVT::i32))
18479 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18481 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
18485 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18486 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
18487 Amt.getOpcode() == ISD::BITCAST &&
18488 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18489 Amt = Amt.getOperand(0);
18490 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18491 VT.getVectorNumElements();
18492 std::vector<SDValue> Vals(Ratio);
18493 for (unsigned i = 0; i != Ratio; ++i)
18494 Vals[i] = Amt.getOperand(i);
18495 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18496 for (unsigned j = 0; j != Ratio; ++j)
18497 if (Vals[j] != Amt.getOperand(i + j))
18501 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
18502 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
18507 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18508 SelectionDAG &DAG) {
18509 MVT VT = Op.getSimpleValueType();
18511 SDValue R = Op.getOperand(0);
18512 SDValue Amt = Op.getOperand(1);
18514 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18515 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18517 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
18520 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
18523 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
18526 // XOP has 128-bit variable logical/arithmetic shifts.
18527 // +ve/-ve Amt = shift left/right.
18528 if (Subtarget->hasXOP() &&
18529 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18530 VT == MVT::v8i16 || VT == MVT::v16i8)) {
18531 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) {
18532 SDValue Zero = getZeroVector(VT, Subtarget, DAG, dl);
18533 Amt = DAG.getNode(ISD::SUB, dl, VT, Zero, Amt);
18535 if (Op.getOpcode() == ISD::SHL || Op.getOpcode() == ISD::SRL)
18536 return DAG.getNode(X86ISD::VPSHL, dl, VT, R, Amt);
18537 if (Op.getOpcode() == ISD::SRA)
18538 return DAG.getNode(X86ISD::VPSHA, dl, VT, R, Amt);
18541 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
18542 // shifts per-lane and then shuffle the partial results back together.
18543 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
18544 // Splat the shift amounts so the scalar shifts above will catch it.
18545 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
18546 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
18547 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
18548 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
18549 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
18552 // i64 vector arithmetic shift can be emulated with the transform:
18553 // M = lshr(SIGN_BIT, Amt)
18554 // ashr(R, Amt) === sub(xor(lshr(R, Amt), M), M)
18555 if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget->hasInt256())) &&
18556 Op.getOpcode() == ISD::SRA) {
18557 SDValue S = DAG.getConstant(APInt::getSignBit(64), dl, VT);
18558 SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt);
18559 R = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18560 R = DAG.getNode(ISD::XOR, dl, VT, R, M);
18561 R = DAG.getNode(ISD::SUB, dl, VT, R, M);
18565 // If possible, lower this packed shift into a vector multiply instead of
18566 // expanding it into a sequence of scalar shifts.
18567 // Do this only if the vector shift count is a constant build_vector.
18568 if (Op.getOpcode() == ISD::SHL &&
18569 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18570 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18571 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18572 SmallVector<SDValue, 8> Elts;
18573 MVT SVT = VT.getVectorElementType();
18574 unsigned SVTBits = SVT.getSizeInBits();
18575 APInt One(SVTBits, 1);
18576 unsigned NumElems = VT.getVectorNumElements();
18578 for (unsigned i=0; i !=NumElems; ++i) {
18579 SDValue Op = Amt->getOperand(i);
18580 if (Op->getOpcode() == ISD::UNDEF) {
18581 Elts.push_back(Op);
18585 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18586 APInt C(SVTBits, ND->getAPIntValue().getZExtValue());
18587 uint64_t ShAmt = C.getZExtValue();
18588 if (ShAmt >= SVTBits) {
18589 Elts.push_back(DAG.getUNDEF(SVT));
18592 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
18594 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18595 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18598 // Lower SHL with variable shift amount.
18599 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18600 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
18602 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
18603 DAG.getConstant(0x3f800000U, dl, VT));
18604 Op = DAG.getBitcast(MVT::v4f32, Op);
18605 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18606 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18609 // If possible, lower this shift as a sequence of two shifts by
18610 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18612 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18614 // Could be rewritten as:
18615 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18617 // The advantage is that the two shifts from the example would be
18618 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18619 // the vector shift into four scalar shifts plus four pairs of vector
18621 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18622 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18623 unsigned TargetOpcode = X86ISD::MOVSS;
18624 bool CanBeSimplified;
18625 // The splat value for the first packed shift (the 'X' from the example).
18626 SDValue Amt1 = Amt->getOperand(0);
18627 // The splat value for the second packed shift (the 'Y' from the example).
18628 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18629 Amt->getOperand(2);
18631 // See if it is possible to replace this node with a sequence of
18632 // two shifts followed by a MOVSS/MOVSD
18633 if (VT == MVT::v4i32) {
18634 // Check if it is legal to use a MOVSS.
18635 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18636 Amt2 == Amt->getOperand(3);
18637 if (!CanBeSimplified) {
18638 // Otherwise, check if we can still simplify this node using a MOVSD.
18639 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18640 Amt->getOperand(2) == Amt->getOperand(3);
18641 TargetOpcode = X86ISD::MOVSD;
18642 Amt2 = Amt->getOperand(2);
18645 // Do similar checks for the case where the machine value type
18647 CanBeSimplified = Amt1 == Amt->getOperand(1);
18648 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18649 CanBeSimplified = Amt2 == Amt->getOperand(i);
18651 if (!CanBeSimplified) {
18652 TargetOpcode = X86ISD::MOVSD;
18653 CanBeSimplified = true;
18654 Amt2 = Amt->getOperand(4);
18655 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18656 CanBeSimplified = Amt1 == Amt->getOperand(i);
18657 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18658 CanBeSimplified = Amt2 == Amt->getOperand(j);
18662 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18663 isa<ConstantSDNode>(Amt2)) {
18664 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18665 MVT CastVT = MVT::v4i32;
18667 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
18668 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18670 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
18671 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18672 if (TargetOpcode == X86ISD::MOVSD)
18673 CastVT = MVT::v2i64;
18674 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
18675 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
18676 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18678 return DAG.getBitcast(VT, Result);
18682 // v4i32 Non Uniform Shifts.
18683 // If the shift amount is constant we can shift each lane using the SSE2
18684 // immediate shifts, else we need to zero-extend each lane to the lower i64
18685 // and shift using the SSE2 variable shifts.
18686 // The separate results can then be blended together.
18687 if (VT == MVT::v4i32) {
18688 unsigned Opc = Op.getOpcode();
18689 SDValue Amt0, Amt1, Amt2, Amt3;
18690 if (ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18691 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {0, 0, 0, 0});
18692 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {1, 1, 1, 1});
18693 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {2, 2, 2, 2});
18694 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {3, 3, 3, 3});
18696 // ISD::SHL is handled above but we include it here for completeness.
18699 llvm_unreachable("Unknown target vector shift node");
18701 Opc = X86ISD::VSHL;
18704 Opc = X86ISD::VSRL;
18707 Opc = X86ISD::VSRA;
18710 // The SSE2 shifts use the lower i64 as the same shift amount for
18711 // all lanes and the upper i64 is ignored. These shuffle masks
18712 // optimally zero-extend each lanes on SSE2/SSE41/AVX targets.
18713 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18714 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Z, {0, 4, -1, -1});
18715 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Z, {1, 5, -1, -1});
18716 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, Z, {2, 6, -1, -1});
18717 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, Z, {3, 7, -1, -1});
18720 SDValue R0 = DAG.getNode(Opc, dl, VT, R, Amt0);
18721 SDValue R1 = DAG.getNode(Opc, dl, VT, R, Amt1);
18722 SDValue R2 = DAG.getNode(Opc, dl, VT, R, Amt2);
18723 SDValue R3 = DAG.getNode(Opc, dl, VT, R, Amt3);
18724 SDValue R02 = DAG.getVectorShuffle(VT, dl, R0, R2, {0, -1, 6, -1});
18725 SDValue R13 = DAG.getVectorShuffle(VT, dl, R1, R3, {-1, 1, -1, 7});
18726 return DAG.getVectorShuffle(VT, dl, R02, R13, {0, 5, 2, 7});
18729 if (VT == MVT::v16i8 ||
18730 (VT == MVT::v32i8 && Subtarget->hasInt256() && !Subtarget->hasXOP())) {
18731 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
18732 unsigned ShiftOpcode = Op->getOpcode();
18734 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
18735 // On SSE41 targets we make use of the fact that VSELECT lowers
18736 // to PBLENDVB which selects bytes based just on the sign bit.
18737 if (Subtarget->hasSSE41()) {
18738 V0 = DAG.getBitcast(VT, V0);
18739 V1 = DAG.getBitcast(VT, V1);
18740 Sel = DAG.getBitcast(VT, Sel);
18741 return DAG.getBitcast(SelVT,
18742 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
18744 // On pre-SSE41 targets we test for the sign bit by comparing to
18745 // zero - a negative value will set all bits of the lanes to true
18746 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
18747 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
18748 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
18749 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
18752 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
18753 // We can safely do this using i16 shifts as we're only interested in
18754 // the 3 lower bits of each byte.
18755 Amt = DAG.getBitcast(ExtVT, Amt);
18756 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
18757 Amt = DAG.getBitcast(VT, Amt);
18759 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
18760 // r = VSELECT(r, shift(r, 4), a);
18762 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18763 R = SignBitSelect(VT, Amt, M, R);
18766 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18768 // r = VSELECT(r, shift(r, 2), a);
18769 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18770 R = SignBitSelect(VT, Amt, M, R);
18773 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18775 // return VSELECT(r, shift(r, 1), a);
18776 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18777 R = SignBitSelect(VT, Amt, M, R);
18781 if (Op->getOpcode() == ISD::SRA) {
18782 // For SRA we need to unpack each byte to the higher byte of a i16 vector
18783 // so we can correctly sign extend. We don't care what happens to the
18785 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
18786 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
18787 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
18788 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
18789 ALo = DAG.getBitcast(ExtVT, ALo);
18790 AHi = DAG.getBitcast(ExtVT, AHi);
18791 RLo = DAG.getBitcast(ExtVT, RLo);
18792 RHi = DAG.getBitcast(ExtVT, RHi);
18794 // r = VSELECT(r, shift(r, 4), a);
18795 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18796 DAG.getConstant(4, dl, ExtVT));
18797 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18798 DAG.getConstant(4, dl, ExtVT));
18799 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18800 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18803 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18804 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18806 // r = VSELECT(r, shift(r, 2), a);
18807 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18808 DAG.getConstant(2, dl, ExtVT));
18809 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18810 DAG.getConstant(2, dl, ExtVT));
18811 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18812 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18815 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18816 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18818 // r = VSELECT(r, shift(r, 1), a);
18819 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18820 DAG.getConstant(1, dl, ExtVT));
18821 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18822 DAG.getConstant(1, dl, ExtVT));
18823 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18824 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18826 // Logical shift the result back to the lower byte, leaving a zero upper
18828 // meaning that we can safely pack with PACKUSWB.
18830 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
18832 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
18833 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
18837 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18838 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18839 // solution better.
18840 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18841 MVT ExtVT = MVT::v8i32;
18843 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18844 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
18845 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
18846 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18847 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
18850 if (Subtarget->hasInt256() && !Subtarget->hasXOP() && VT == MVT::v16i16) {
18851 MVT ExtVT = MVT::v8i32;
18852 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18853 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
18854 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
18855 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
18856 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
18857 ALo = DAG.getBitcast(ExtVT, ALo);
18858 AHi = DAG.getBitcast(ExtVT, AHi);
18859 RLo = DAG.getBitcast(ExtVT, RLo);
18860 RHi = DAG.getBitcast(ExtVT, RHi);
18861 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
18862 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
18863 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
18864 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
18865 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
18868 if (VT == MVT::v8i16) {
18869 unsigned ShiftOpcode = Op->getOpcode();
18871 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
18872 // On SSE41 targets we make use of the fact that VSELECT lowers
18873 // to PBLENDVB which selects bytes based just on the sign bit.
18874 if (Subtarget->hasSSE41()) {
18875 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
18876 V0 = DAG.getBitcast(ExtVT, V0);
18877 V1 = DAG.getBitcast(ExtVT, V1);
18878 Sel = DAG.getBitcast(ExtVT, Sel);
18879 return DAG.getBitcast(
18880 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
18882 // On pre-SSE41 targets we splat the sign bit - a negative value will
18883 // set all bits of the lanes to true and VSELECT uses that in
18884 // its OR(AND(V0,C),AND(V1,~C)) lowering.
18886 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
18887 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
18890 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
18891 if (Subtarget->hasSSE41()) {
18892 // On SSE41 targets we need to replicate the shift mask in both
18893 // bytes for PBLENDVB.
18896 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
18897 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
18899 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
18902 // r = VSELECT(r, shift(r, 8), a);
18903 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
18904 R = SignBitSelect(Amt, M, R);
18907 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18909 // r = VSELECT(r, shift(r, 4), a);
18910 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18911 R = SignBitSelect(Amt, M, R);
18914 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18916 // r = VSELECT(r, shift(r, 2), a);
18917 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18918 R = SignBitSelect(Amt, M, R);
18921 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18923 // return VSELECT(r, shift(r, 1), a);
18924 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18925 R = SignBitSelect(Amt, M, R);
18929 // Decompose 256-bit shifts into smaller 128-bit shifts.
18930 if (VT.is256BitVector()) {
18931 unsigned NumElems = VT.getVectorNumElements();
18932 MVT EltVT = VT.getVectorElementType();
18933 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18935 // Extract the two vectors
18936 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18937 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18939 // Recreate the shift amount vectors
18940 SDValue Amt1, Amt2;
18941 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18942 // Constant shift amount
18943 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
18944 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
18945 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
18947 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18948 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18950 // Variable shift amount
18951 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18952 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18955 // Issue new vector shifts for the smaller types
18956 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18957 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18959 // Concatenate the result back
18960 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18966 static SDValue LowerRotate(SDValue Op, const X86Subtarget *Subtarget,
18967 SelectionDAG &DAG) {
18968 MVT VT = Op.getSimpleValueType();
18970 SDValue R = Op.getOperand(0);
18971 SDValue Amt = Op.getOperand(1);
18973 assert(VT.isVector() && "Custom lowering only for vector rotates!");
18974 assert(Subtarget->hasXOP() && "XOP support required for vector rotates!");
18975 assert((Op.getOpcode() == ISD::ROTL) && "Only ROTL supported");
18977 // XOP has 128-bit vector variable + immediate rotates.
18978 // +ve/-ve Amt = rotate left/right.
18980 // Split 256-bit integers.
18981 if (VT.is256BitVector())
18982 return Lower256IntArith(Op, DAG);
18984 assert(VT.is128BitVector() && "Only rotate 128-bit vectors!");
18986 // Attempt to rotate by immediate.
18987 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18988 if (auto *RotateConst = BVAmt->getConstantSplatNode()) {
18989 uint64_t RotateAmt = RotateConst->getAPIntValue().getZExtValue();
18990 assert(RotateAmt < VT.getScalarSizeInBits() && "Rotation out of range");
18991 return DAG.getNode(X86ISD::VPROTI, DL, VT, R,
18992 DAG.getConstant(RotateAmt, DL, MVT::i8));
18996 // Use general rotate by variable (per-element).
18997 return DAG.getNode(X86ISD::VPROT, DL, VT, R, Amt);
19000 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
19001 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
19002 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
19003 // looks for this combo and may remove the "setcc" instruction if the "setcc"
19004 // has only one use.
19005 SDNode *N = Op.getNode();
19006 SDValue LHS = N->getOperand(0);
19007 SDValue RHS = N->getOperand(1);
19008 unsigned BaseOp = 0;
19011 switch (Op.getOpcode()) {
19012 default: llvm_unreachable("Unknown ovf instruction!");
19014 // A subtract of one will be selected as a INC. Note that INC doesn't
19015 // set CF, so we can't do this for UADDO.
19016 if (isOneConstant(RHS)) {
19017 BaseOp = X86ISD::INC;
19018 Cond = X86::COND_O;
19021 BaseOp = X86ISD::ADD;
19022 Cond = X86::COND_O;
19025 BaseOp = X86ISD::ADD;
19026 Cond = X86::COND_B;
19029 // A subtract of one will be selected as a DEC. Note that DEC doesn't
19030 // set CF, so we can't do this for USUBO.
19031 if (isOneConstant(RHS)) {
19032 BaseOp = X86ISD::DEC;
19033 Cond = X86::COND_O;
19036 BaseOp = X86ISD::SUB;
19037 Cond = X86::COND_O;
19040 BaseOp = X86ISD::SUB;
19041 Cond = X86::COND_B;
19044 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
19045 Cond = X86::COND_O;
19047 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
19048 if (N->getValueType(0) == MVT::i8) {
19049 BaseOp = X86ISD::UMUL8;
19050 Cond = X86::COND_O;
19053 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
19055 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
19058 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
19059 DAG.getConstant(X86::COND_O, DL, MVT::i32),
19060 SDValue(Sum.getNode(), 2));
19062 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
19066 // Also sets EFLAGS.
19067 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
19068 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
19071 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
19072 DAG.getConstant(Cond, DL, MVT::i32),
19073 SDValue(Sum.getNode(), 1));
19075 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
19078 /// Returns true if the operand type is exactly twice the native width, and
19079 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
19080 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
19081 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
19082 bool X86TargetLowering::needsCmpXchgNb(Type *MemType) const {
19083 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
19086 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
19087 else if (OpWidth == 128)
19088 return Subtarget->hasCmpxchg16b();
19093 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
19094 return needsCmpXchgNb(SI->getValueOperand()->getType());
19097 // Note: this turns large loads into lock cmpxchg8b/16b.
19098 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
19099 TargetLowering::AtomicExpansionKind
19100 X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
19101 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
19102 return needsCmpXchgNb(PTy->getElementType()) ? AtomicExpansionKind::CmpXChg
19103 : AtomicExpansionKind::None;
19106 TargetLowering::AtomicExpansionKind
19107 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
19108 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
19109 Type *MemType = AI->getType();
19111 // If the operand is too big, we must see if cmpxchg8/16b is available
19112 // and default to library calls otherwise.
19113 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
19114 return needsCmpXchgNb(MemType) ? AtomicExpansionKind::CmpXChg
19115 : AtomicExpansionKind::None;
19118 AtomicRMWInst::BinOp Op = AI->getOperation();
19121 llvm_unreachable("Unknown atomic operation");
19122 case AtomicRMWInst::Xchg:
19123 case AtomicRMWInst::Add:
19124 case AtomicRMWInst::Sub:
19125 // It's better to use xadd, xsub or xchg for these in all cases.
19126 return AtomicExpansionKind::None;
19127 case AtomicRMWInst::Or:
19128 case AtomicRMWInst::And:
19129 case AtomicRMWInst::Xor:
19130 // If the atomicrmw's result isn't actually used, we can just add a "lock"
19131 // prefix to a normal instruction for these operations.
19132 return !AI->use_empty() ? AtomicExpansionKind::CmpXChg
19133 : AtomicExpansionKind::None;
19134 case AtomicRMWInst::Nand:
19135 case AtomicRMWInst::Max:
19136 case AtomicRMWInst::Min:
19137 case AtomicRMWInst::UMax:
19138 case AtomicRMWInst::UMin:
19139 // These always require a non-trivial set of data operations on x86. We must
19140 // use a cmpxchg loop.
19141 return AtomicExpansionKind::CmpXChg;
19145 static bool hasMFENCE(const X86Subtarget& Subtarget) {
19146 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
19147 // no-sse2). There isn't any reason to disable it if the target processor
19149 return Subtarget.hasSSE2() || Subtarget.is64Bit();
19153 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
19154 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
19155 Type *MemType = AI->getType();
19156 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
19157 // there is no benefit in turning such RMWs into loads, and it is actually
19158 // harmful as it introduces a mfence.
19159 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19162 auto Builder = IRBuilder<>(AI);
19163 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
19164 auto SynchScope = AI->getSynchScope();
19165 // We must restrict the ordering to avoid generating loads with Release or
19166 // ReleaseAcquire orderings.
19167 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
19168 auto Ptr = AI->getPointerOperand();
19170 // Before the load we need a fence. Here is an example lifted from
19171 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
19174 // x.store(1, relaxed);
19175 // r1 = y.fetch_add(0, release);
19177 // y.fetch_add(42, acquire);
19178 // r2 = x.load(relaxed);
19179 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
19180 // lowered to just a load without a fence. A mfence flushes the store buffer,
19181 // making the optimization clearly correct.
19182 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
19183 // otherwise, we might be able to be more aggressive on relaxed idempotent
19184 // rmw. In practice, they do not look useful, so we don't try to be
19185 // especially clever.
19186 if (SynchScope == SingleThread)
19187 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19188 // the IR level, so we must wrap it in an intrinsic.
19191 if (!hasMFENCE(*Subtarget))
19192 // FIXME: it might make sense to use a locked operation here but on a
19193 // different cache-line to prevent cache-line bouncing. In practice it
19194 // is probably a small win, and x86 processors without mfence are rare
19195 // enough that we do not bother.
19199 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
19200 Builder.CreateCall(MFence, {});
19202 // Finally we can emit the atomic load.
19203 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19204 AI->getType()->getPrimitiveSizeInBits());
19205 Loaded->setAtomic(Order, SynchScope);
19206 AI->replaceAllUsesWith(Loaded);
19207 AI->eraseFromParent();
19211 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19212 SelectionDAG &DAG) {
19214 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19215 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19216 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19217 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19219 // The only fence that needs an instruction is a sequentially-consistent
19220 // cross-thread fence.
19221 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19222 if (hasMFENCE(*Subtarget))
19223 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19225 SDValue Chain = Op.getOperand(0);
19226 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
19228 DAG.getRegister(X86::ESP, MVT::i32), // Base
19229 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
19230 DAG.getRegister(0, MVT::i32), // Index
19231 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
19232 DAG.getRegister(0, MVT::i32), // Segment.
19236 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19237 return SDValue(Res, 0);
19240 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19241 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19244 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19245 SelectionDAG &DAG) {
19246 MVT T = Op.getSimpleValueType();
19250 switch(T.SimpleTy) {
19251 default: llvm_unreachable("Invalid value type!");
19252 case MVT::i8: Reg = X86::AL; size = 1; break;
19253 case MVT::i16: Reg = X86::AX; size = 2; break;
19254 case MVT::i32: Reg = X86::EAX; size = 4; break;
19256 assert(Subtarget->is64Bit() && "Node not type legal!");
19257 Reg = X86::RAX; size = 8;
19260 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19261 Op.getOperand(2), SDValue());
19262 SDValue Ops[] = { cpIn.getValue(0),
19265 DAG.getTargetConstant(size, DL, MVT::i8),
19266 cpIn.getValue(1) };
19267 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19268 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19269 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19273 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19274 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19275 MVT::i32, cpOut.getValue(2));
19276 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19277 DAG.getConstant(X86::COND_E, DL, MVT::i8),
19280 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19281 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19282 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19286 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19287 SelectionDAG &DAG) {
19288 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19289 MVT DstVT = Op.getSimpleValueType();
19291 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19292 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19293 if (DstVT != MVT::f64)
19294 // This conversion needs to be expanded.
19297 SDValue InVec = Op->getOperand(0);
19299 unsigned NumElts = SrcVT.getVectorNumElements();
19300 MVT SVT = SrcVT.getVectorElementType();
19302 // Widen the vector in input in the case of MVT::v2i32.
19303 // Example: from MVT::v2i32 to MVT::v4i32.
19304 SmallVector<SDValue, 16> Elts;
19305 for (unsigned i = 0, e = NumElts; i != e; ++i)
19306 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19307 DAG.getIntPtrConstant(i, dl)));
19309 // Explicitly mark the extra elements as Undef.
19310 Elts.append(NumElts, DAG.getUNDEF(SVT));
19312 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19313 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19314 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
19315 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19316 DAG.getIntPtrConstant(0, dl));
19319 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19320 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19321 assert((DstVT == MVT::i64 ||
19322 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19323 "Unexpected custom BITCAST");
19324 // i64 <=> MMX conversions are Legal.
19325 if (SrcVT==MVT::i64 && DstVT.isVector())
19327 if (DstVT==MVT::i64 && SrcVT.isVector())
19329 // MMX <=> MMX conversions are Legal.
19330 if (SrcVT.isVector() && DstVT.isVector())
19332 // All other conversions need to be expanded.
19336 /// Compute the horizontal sum of bytes in V for the elements of VT.
19338 /// Requires V to be a byte vector and VT to be an integer vector type with
19339 /// wider elements than V's type. The width of the elements of VT determines
19340 /// how many bytes of V are summed horizontally to produce each element of the
19342 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
19343 const X86Subtarget *Subtarget,
19344 SelectionDAG &DAG) {
19346 MVT ByteVecVT = V.getSimpleValueType();
19347 MVT EltVT = VT.getVectorElementType();
19348 int NumElts = VT.getVectorNumElements();
19349 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
19350 "Expected value to have byte element type.");
19351 assert(EltVT != MVT::i8 &&
19352 "Horizontal byte sum only makes sense for wider elements!");
19353 unsigned VecSize = VT.getSizeInBits();
19354 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
19356 // PSADBW instruction horizontally add all bytes and leave the result in i64
19357 // chunks, thus directly computes the pop count for v2i64 and v4i64.
19358 if (EltVT == MVT::i64) {
19359 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19360 MVT SadVecVT = MVT::getVectorVT(MVT::i64, VecSize / 64);
19361 V = DAG.getNode(X86ISD::PSADBW, DL, SadVecVT, V, Zeros);
19362 return DAG.getBitcast(VT, V);
19365 if (EltVT == MVT::i32) {
19366 // We unpack the low half and high half into i32s interleaved with zeros so
19367 // that we can use PSADBW to horizontally sum them. The most useful part of
19368 // this is that it lines up the results of two PSADBW instructions to be
19369 // two v2i64 vectors which concatenated are the 4 population counts. We can
19370 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
19371 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
19372 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
19373 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
19375 // Do the horizontal sums into two v2i64s.
19376 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19377 MVT SadVecVT = MVT::getVectorVT(MVT::i64, VecSize / 64);
19378 Low = DAG.getNode(X86ISD::PSADBW, DL, SadVecVT,
19379 DAG.getBitcast(ByteVecVT, Low), Zeros);
19380 High = DAG.getNode(X86ISD::PSADBW, DL, SadVecVT,
19381 DAG.getBitcast(ByteVecVT, High), Zeros);
19383 // Merge them together.
19384 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
19385 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
19386 DAG.getBitcast(ShortVecVT, Low),
19387 DAG.getBitcast(ShortVecVT, High));
19389 return DAG.getBitcast(VT, V);
19392 // The only element type left is i16.
19393 assert(EltVT == MVT::i16 && "Unknown how to handle type");
19395 // To obtain pop count for each i16 element starting from the pop count for
19396 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
19397 // right by 8. It is important to shift as i16s as i8 vector shift isn't
19398 // directly supported.
19399 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
19400 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
19401 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19402 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
19403 DAG.getBitcast(ByteVecVT, V));
19404 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19407 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
19408 const X86Subtarget *Subtarget,
19409 SelectionDAG &DAG) {
19410 MVT VT = Op.getSimpleValueType();
19411 MVT EltVT = VT.getVectorElementType();
19412 unsigned VecSize = VT.getSizeInBits();
19414 // Implement a lookup table in register by using an algorithm based on:
19415 // http://wm.ite.pl/articles/sse-popcount.html
19417 // The general idea is that every lower byte nibble in the input vector is an
19418 // index into a in-register pre-computed pop count table. We then split up the
19419 // input vector in two new ones: (1) a vector with only the shifted-right
19420 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
19421 // masked out higher ones) for each byte. PSHUB is used separately with both
19422 // to index the in-register table. Next, both are added and the result is a
19423 // i8 vector where each element contains the pop count for input byte.
19425 // To obtain the pop count for elements != i8, we follow up with the same
19426 // approach and use additional tricks as described below.
19428 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
19429 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
19430 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
19431 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
19433 int NumByteElts = VecSize / 8;
19434 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
19435 SDValue In = DAG.getBitcast(ByteVecVT, Op);
19436 SmallVector<SDValue, 16> LUTVec;
19437 for (int i = 0; i < NumByteElts; ++i)
19438 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
19439 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
19440 SmallVector<SDValue, 16> Mask0F(NumByteElts,
19441 DAG.getConstant(0x0F, DL, MVT::i8));
19442 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
19445 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
19446 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
19447 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
19450 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
19452 // The input vector is used as the shuffle mask that index elements into the
19453 // LUT. After counting low and high nibbles, add the vector to obtain the
19454 // final pop count per i8 element.
19455 SDValue HighPopCnt =
19456 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
19457 SDValue LowPopCnt =
19458 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
19459 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
19461 if (EltVT == MVT::i8)
19464 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
19467 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
19468 const X86Subtarget *Subtarget,
19469 SelectionDAG &DAG) {
19470 MVT VT = Op.getSimpleValueType();
19471 assert(VT.is128BitVector() &&
19472 "Only 128-bit vector bitmath lowering supported.");
19474 int VecSize = VT.getSizeInBits();
19475 MVT EltVT = VT.getVectorElementType();
19476 int Len = EltVT.getSizeInBits();
19478 // This is the vectorized version of the "best" algorithm from
19479 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19480 // with a minor tweak to use a series of adds + shifts instead of vector
19481 // multiplications. Implemented for all integer vector types. We only use
19482 // this when we don't have SSSE3 which allows a LUT-based lowering that is
19483 // much faster, even faster than using native popcnt instructions.
19485 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
19486 MVT VT = V.getSimpleValueType();
19487 SmallVector<SDValue, 32> Shifters(
19488 VT.getVectorNumElements(),
19489 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
19490 return DAG.getNode(OpCode, DL, VT, V,
19491 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
19493 auto GetMask = [&](SDValue V, APInt Mask) {
19494 MVT VT = V.getSimpleValueType();
19495 SmallVector<SDValue, 32> Masks(
19496 VT.getVectorNumElements(),
19497 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
19498 return DAG.getNode(ISD::AND, DL, VT, V,
19499 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
19502 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
19503 // x86, so set the SRL type to have elements at least i16 wide. This is
19504 // correct because all of our SRLs are followed immediately by a mask anyways
19505 // that handles any bits that sneak into the high bits of the byte elements.
19506 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
19510 // v = v - ((v >> 1) & 0x55555555...)
19512 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
19513 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
19514 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
19516 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19517 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
19518 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
19519 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
19520 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
19522 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19523 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
19524 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
19525 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
19527 // At this point, V contains the byte-wise population count, and we are
19528 // merely doing a horizontal sum if necessary to get the wider element
19530 if (EltVT == MVT::i8)
19533 return LowerHorizontalByteSum(
19534 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
19538 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19539 SelectionDAG &DAG) {
19540 MVT VT = Op.getSimpleValueType();
19541 // FIXME: Need to add AVX-512 support here!
19542 assert((VT.is256BitVector() || VT.is128BitVector()) &&
19543 "Unknown CTPOP type to handle");
19544 SDLoc DL(Op.getNode());
19545 SDValue Op0 = Op.getOperand(0);
19547 if (!Subtarget->hasSSSE3()) {
19548 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
19549 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
19550 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
19553 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
19554 unsigned NumElems = VT.getVectorNumElements();
19556 // Extract each 128-bit vector, compute pop count and concat the result.
19557 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
19558 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
19560 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
19561 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
19562 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
19565 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
19568 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19569 SelectionDAG &DAG) {
19570 assert(Op.getSimpleValueType().isVector() &&
19571 "We only do custom lowering for vector population count.");
19572 return LowerVectorCTPOP(Op, Subtarget, DAG);
19575 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19576 SDNode *Node = Op.getNode();
19578 EVT T = Node->getValueType(0);
19579 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19580 DAG.getConstant(0, dl, T), Node->getOperand(2));
19581 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19582 cast<AtomicSDNode>(Node)->getMemoryVT(),
19583 Node->getOperand(0),
19584 Node->getOperand(1), negOp,
19585 cast<AtomicSDNode>(Node)->getMemOperand(),
19586 cast<AtomicSDNode>(Node)->getOrdering(),
19587 cast<AtomicSDNode>(Node)->getSynchScope());
19590 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19591 SDNode *Node = Op.getNode();
19593 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19595 // Convert seq_cst store -> xchg
19596 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19597 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19598 // (The only way to get a 16-byte store is cmpxchg16b)
19599 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19600 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19601 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19602 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19603 cast<AtomicSDNode>(Node)->getMemoryVT(),
19604 Node->getOperand(0),
19605 Node->getOperand(1), Node->getOperand(2),
19606 cast<AtomicSDNode>(Node)->getMemOperand(),
19607 cast<AtomicSDNode>(Node)->getOrdering(),
19608 cast<AtomicSDNode>(Node)->getSynchScope());
19609 return Swap.getValue(1);
19611 // Other atomic stores have a simple pattern.
19615 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19616 MVT VT = Op.getNode()->getSimpleValueType(0);
19618 // Let legalize expand this if it isn't a legal type yet.
19619 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19622 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19625 bool ExtraOp = false;
19626 switch (Op.getOpcode()) {
19627 default: llvm_unreachable("Invalid code");
19628 case ISD::ADDC: Opc = X86ISD::ADD; break;
19629 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19630 case ISD::SUBC: Opc = X86ISD::SUB; break;
19631 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19635 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19637 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19638 Op.getOperand(1), Op.getOperand(2));
19641 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19642 SelectionDAG &DAG) {
19643 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19645 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19646 // which returns the values as { float, float } (in XMM0) or
19647 // { double, double } (which is returned in XMM0, XMM1).
19649 SDValue Arg = Op.getOperand(0);
19650 EVT ArgVT = Arg.getValueType();
19651 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19653 TargetLowering::ArgListTy Args;
19654 TargetLowering::ArgListEntry Entry;
19658 Entry.isSExt = false;
19659 Entry.isZExt = false;
19660 Args.push_back(Entry);
19662 bool isF64 = ArgVT == MVT::f64;
19663 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19664 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19665 // the results are returned via SRet in memory.
19666 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19667 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19669 DAG.getExternalSymbol(LibcallName, TLI.getPointerTy(DAG.getDataLayout()));
19671 Type *RetTy = isF64
19672 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19673 : (Type*)VectorType::get(ArgTy, 4);
19675 TargetLowering::CallLoweringInfo CLI(DAG);
19676 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19677 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19679 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19682 // Returned in xmm0 and xmm1.
19683 return CallResult.first;
19685 // Returned in bits 0:31 and 32:64 xmm0.
19686 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19687 CallResult.first, DAG.getIntPtrConstant(0, dl));
19688 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19689 CallResult.first, DAG.getIntPtrConstant(1, dl));
19690 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19691 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19694 /// Widen a vector input to a vector of NVT. The
19695 /// input vector must have the same element type as NVT.
19696 static SDValue ExtendToType(SDValue InOp, MVT NVT, SelectionDAG &DAG,
19697 bool FillWithZeroes = false) {
19698 // Check if InOp already has the right width.
19699 MVT InVT = InOp.getSimpleValueType();
19703 if (InOp.isUndef())
19704 return DAG.getUNDEF(NVT);
19706 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
19707 "input and widen element type must match");
19709 unsigned InNumElts = InVT.getVectorNumElements();
19710 unsigned WidenNumElts = NVT.getVectorNumElements();
19711 assert(WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0 &&
19712 "Unexpected request for vector widening");
19714 EVT EltVT = NVT.getVectorElementType();
19717 if (ISD::isBuildVectorOfConstantSDNodes(InOp.getNode()) ||
19718 ISD::isBuildVectorOfConstantFPSDNodes(InOp.getNode())) {
19719 SmallVector<SDValue, 16> Ops;
19720 for (unsigned i = 0; i < InNumElts; ++i)
19721 Ops.push_back(InOp.getOperand(i));
19723 SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, EltVT) :
19724 DAG.getUNDEF(EltVT);
19725 for (unsigned i = 0; i < WidenNumElts - InNumElts; ++i)
19726 Ops.push_back(FillVal);
19727 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Ops);
19729 SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, NVT) :
19731 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NVT, FillVal,
19732 InOp, DAG.getIntPtrConstant(0, dl));
19735 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
19736 SelectionDAG &DAG) {
19737 assert(Subtarget->hasAVX512() &&
19738 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19740 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
19741 MVT VT = N->getValue().getSimpleValueType();
19742 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
19745 // X86 scatter kills mask register, so its type should be added to
19746 // the list of return values
19747 if (N->getNumValues() == 1) {
19748 SDValue Index = N->getIndex();
19749 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19750 !Index.getSimpleValueType().is512BitVector())
19751 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19753 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
19754 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19755 N->getOperand(3), Index };
19757 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
19758 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
19759 return SDValue(NewScatter.getNode(), 0);
19764 static SDValue LowerMLOAD(SDValue Op, const X86Subtarget *Subtarget,
19765 SelectionDAG &DAG) {
19767 MaskedLoadSDNode *N = cast<MaskedLoadSDNode>(Op.getNode());
19768 MVT VT = Op.getSimpleValueType();
19769 SDValue Mask = N->getMask();
19772 if (Subtarget->hasAVX512() && !Subtarget->hasVLX() &&
19773 !VT.is512BitVector() && Mask.getValueType() == MVT::v8i1) {
19774 // This operation is legal for targets with VLX, but without
19775 // VLX the vector should be widened to 512 bit
19776 unsigned NumEltsInWideVec = 512/VT.getScalarSizeInBits();
19777 MVT WideDataVT = MVT::getVectorVT(VT.getScalarType(), NumEltsInWideVec);
19778 MVT WideMaskVT = MVT::getVectorVT(MVT::i1, NumEltsInWideVec);
19779 SDValue Src0 = N->getSrc0();
19780 Src0 = ExtendToType(Src0, WideDataVT, DAG);
19781 Mask = ExtendToType(Mask, WideMaskVT, DAG, true);
19782 SDValue NewLoad = DAG.getMaskedLoad(WideDataVT, dl, N->getChain(),
19783 N->getBasePtr(), Mask, Src0,
19784 N->getMemoryVT(), N->getMemOperand(),
19785 N->getExtensionType());
19787 SDValue Exract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
19788 NewLoad.getValue(0),
19789 DAG.getIntPtrConstant(0, dl));
19790 SDValue RetOps[] = {Exract, NewLoad.getValue(1)};
19791 return DAG.getMergeValues(RetOps, dl);
19796 static SDValue LowerMSTORE(SDValue Op, const X86Subtarget *Subtarget,
19797 SelectionDAG &DAG) {
19798 MaskedStoreSDNode *N = cast<MaskedStoreSDNode>(Op.getNode());
19799 SDValue DataToStore = N->getValue();
19800 MVT VT = DataToStore.getSimpleValueType();
19801 SDValue Mask = N->getMask();
19804 if (Subtarget->hasAVX512() && !Subtarget->hasVLX() &&
19805 !VT.is512BitVector() && Mask.getValueType() == MVT::v8i1) {
19806 // This operation is legal for targets with VLX, but without
19807 // VLX the vector should be widened to 512 bit
19808 unsigned NumEltsInWideVec = 512/VT.getScalarSizeInBits();
19809 MVT WideDataVT = MVT::getVectorVT(VT.getScalarType(), NumEltsInWideVec);
19810 MVT WideMaskVT = MVT::getVectorVT(MVT::i1, NumEltsInWideVec);
19811 DataToStore = ExtendToType(DataToStore, WideDataVT, DAG);
19812 Mask = ExtendToType(Mask, WideMaskVT, DAG, true);
19813 return DAG.getMaskedStore(N->getChain(), dl, DataToStore, N->getBasePtr(),
19814 Mask, N->getMemoryVT(), N->getMemOperand(),
19815 N->isTruncatingStore());
19820 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
19821 SelectionDAG &DAG) {
19822 assert(Subtarget->hasAVX512() &&
19823 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19825 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
19826 MVT VT = Op.getSimpleValueType();
19827 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
19830 SDValue Index = N->getIndex();
19831 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19832 !Index.getSimpleValueType().is512BitVector()) {
19833 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19834 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19835 N->getOperand(3), Index };
19836 DAG.UpdateNodeOperands(N, Ops);
19841 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
19842 SelectionDAG &DAG) const {
19843 // TODO: Eventually, the lowering of these nodes should be informed by or
19844 // deferred to the GC strategy for the function in which they appear. For
19845 // now, however, they must be lowered to something. Since they are logically
19846 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19847 // require special handling for these nodes), lower them as literal NOOPs for
19849 SmallVector<SDValue, 2> Ops;
19851 Ops.push_back(Op.getOperand(0));
19852 if (Op->getGluedNode())
19853 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19856 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19857 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19862 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
19863 SelectionDAG &DAG) const {
19864 // TODO: Eventually, the lowering of these nodes should be informed by or
19865 // deferred to the GC strategy for the function in which they appear. For
19866 // now, however, they must be lowered to something. Since they are logically
19867 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19868 // require special handling for these nodes), lower them as literal NOOPs for
19870 SmallVector<SDValue, 2> Ops;
19872 Ops.push_back(Op.getOperand(0));
19873 if (Op->getGluedNode())
19874 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19877 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19878 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19883 /// LowerOperation - Provide custom lowering hooks for some operations.
19885 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19886 switch (Op.getOpcode()) {
19887 default: llvm_unreachable("Should not custom lower this!");
19888 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19889 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19890 return LowerCMP_SWAP(Op, Subtarget, DAG);
19891 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
19892 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19893 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19894 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19895 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
19896 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
19897 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19898 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19899 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19900 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19901 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19902 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19903 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19904 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19905 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19906 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19907 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19908 case ISD::SHL_PARTS:
19909 case ISD::SRA_PARTS:
19910 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19911 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19912 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19913 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19914 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19915 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19916 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19917 case ISD::SIGN_EXTEND_VECTOR_INREG:
19918 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
19919 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19920 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19921 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19922 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19924 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19925 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19926 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19927 case ISD::SETCC: return LowerSETCC(Op, DAG);
19928 case ISD::SETCCE: return LowerSETCCE(Op, DAG);
19929 case ISD::SELECT: return LowerSELECT(Op, DAG);
19930 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19931 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19932 case ISD::VASTART: return LowerVASTART(Op, DAG);
19933 case ISD::VAARG: return LowerVAARG(Op, DAG);
19934 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19935 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19936 case ISD::INTRINSIC_VOID:
19937 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19938 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19939 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19940 case ISD::FRAME_TO_ARGS_OFFSET:
19941 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19942 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19943 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19944 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19945 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19946 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19947 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19948 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19949 case ISD::CTLZ: return LowerCTLZ(Op, Subtarget, DAG);
19950 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, Subtarget, DAG);
19952 case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op, DAG);
19953 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19954 case ISD::UMUL_LOHI:
19955 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19956 case ISD::ROTL: return LowerRotate(Op, Subtarget, DAG);
19959 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19965 case ISD::UMULO: return LowerXALUO(Op, DAG);
19966 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19967 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19971 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19972 case ISD::ADD: return LowerADD(Op, DAG);
19973 case ISD::SUB: return LowerSUB(Op, DAG);
19977 case ISD::UMIN: return LowerMINMAX(Op, DAG);
19978 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19979 case ISD::MLOAD: return LowerMLOAD(Op, Subtarget, DAG);
19980 case ISD::MSTORE: return LowerMSTORE(Op, Subtarget, DAG);
19981 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
19982 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
19983 case ISD::GC_TRANSITION_START:
19984 return LowerGC_TRANSITION_START(Op, DAG);
19985 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
19989 /// ReplaceNodeResults - Replace a node with an illegal result type
19990 /// with a new node built out of custom code.
19991 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19992 SmallVectorImpl<SDValue>&Results,
19993 SelectionDAG &DAG) const {
19995 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19996 switch (N->getOpcode()) {
19998 llvm_unreachable("Do not know how to custom type legalize this operation!");
19999 case X86ISD::AVG: {
20000 // Legalize types for X86ISD::AVG by expanding vectors.
20001 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
20003 auto InVT = N->getValueType(0);
20004 auto InVTSize = InVT.getSizeInBits();
20005 const unsigned RegSize =
20006 (InVTSize > 128) ? ((InVTSize > 256) ? 512 : 256) : 128;
20007 assert((!Subtarget->hasAVX512() || RegSize < 512) &&
20008 "512-bit vector requires AVX512");
20009 assert((!Subtarget->hasAVX2() || RegSize < 256) &&
20010 "256-bit vector requires AVX2");
20012 auto ElemVT = InVT.getVectorElementType();
20013 auto RegVT = EVT::getVectorVT(*DAG.getContext(), ElemVT,
20014 RegSize / ElemVT.getSizeInBits());
20015 assert(RegSize % InVT.getSizeInBits() == 0);
20016 unsigned NumConcat = RegSize / InVT.getSizeInBits();
20018 SmallVector<SDValue, 16> Ops(NumConcat, DAG.getUNDEF(InVT));
20019 Ops[0] = N->getOperand(0);
20020 SDValue InVec0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Ops);
20021 Ops[0] = N->getOperand(1);
20022 SDValue InVec1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Ops);
20024 SDValue Res = DAG.getNode(X86ISD::AVG, dl, RegVT, InVec0, InVec1);
20025 Results.push_back(DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InVT, Res,
20026 DAG.getIntPtrConstant(0, dl)));
20029 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
20030 case X86ISD::FMINC:
20032 case X86ISD::FMAXC:
20033 case X86ISD::FMAX: {
20034 EVT VT = N->getValueType(0);
20035 assert(VT == MVT::v2f32 && "Unexpected type (!= v2f32) on FMIN/FMAX.");
20036 SDValue UNDEF = DAG.getUNDEF(VT);
20037 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
20038 N->getOperand(0), UNDEF);
20039 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
20040 N->getOperand(1), UNDEF);
20041 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
20044 case ISD::SIGN_EXTEND_INREG:
20049 // We don't want to expand or promote these.
20056 case ISD::UDIVREM: {
20057 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
20058 Results.push_back(V);
20061 case ISD::FP_TO_SINT:
20062 case ISD::FP_TO_UINT: {
20063 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
20065 std::pair<SDValue,SDValue> Vals =
20066 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
20067 SDValue FIST = Vals.first, StackSlot = Vals.second;
20068 if (FIST.getNode()) {
20069 EVT VT = N->getValueType(0);
20070 // Return a load from the stack slot.
20071 if (StackSlot.getNode())
20072 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
20073 MachinePointerInfo(),
20074 false, false, false, 0));
20076 Results.push_back(FIST);
20080 case ISD::UINT_TO_FP: {
20081 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
20082 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
20083 N->getValueType(0) != MVT::v2f32)
20085 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
20087 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
20089 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
20090 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
20091 DAG.getBitcast(MVT::v2i64, VBias));
20092 Or = DAG.getBitcast(MVT::v2f64, Or);
20093 // TODO: Are there any fast-math-flags to propagate here?
20094 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
20095 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
20098 case ISD::FP_ROUND: {
20099 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
20101 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
20102 Results.push_back(V);
20105 case ISD::FP_EXTEND: {
20106 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
20107 // No other ValueType for FP_EXTEND should reach this point.
20108 assert(N->getValueType(0) == MVT::v2f32 &&
20109 "Do not know how to legalize this Node");
20112 case ISD::INTRINSIC_W_CHAIN: {
20113 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
20115 default : llvm_unreachable("Do not know how to custom type "
20116 "legalize this intrinsic operation!");
20117 case Intrinsic::x86_rdtsc:
20118 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
20120 case Intrinsic::x86_rdtscp:
20121 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
20123 case Intrinsic::x86_rdpmc:
20124 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
20127 case ISD::INTRINSIC_WO_CHAIN: {
20128 if (SDValue V = LowerINTRINSIC_WO_CHAIN(SDValue(N, 0), Subtarget, DAG))
20129 Results.push_back(V);
20132 case ISD::READCYCLECOUNTER: {
20133 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
20136 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
20137 EVT T = N->getValueType(0);
20138 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
20139 bool Regs64bit = T == MVT::i128;
20140 MVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
20141 SDValue cpInL, cpInH;
20142 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
20143 DAG.getConstant(0, dl, HalfT));
20144 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
20145 DAG.getConstant(1, dl, HalfT));
20146 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
20147 Regs64bit ? X86::RAX : X86::EAX,
20149 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
20150 Regs64bit ? X86::RDX : X86::EDX,
20151 cpInH, cpInL.getValue(1));
20152 SDValue swapInL, swapInH;
20153 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
20154 DAG.getConstant(0, dl, HalfT));
20155 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
20156 DAG.getConstant(1, dl, HalfT));
20157 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
20158 Regs64bit ? X86::RBX : X86::EBX,
20159 swapInL, cpInH.getValue(1));
20160 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
20161 Regs64bit ? X86::RCX : X86::ECX,
20162 swapInH, swapInL.getValue(1));
20163 SDValue Ops[] = { swapInH.getValue(0),
20165 swapInH.getValue(1) };
20166 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
20167 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
20168 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
20169 X86ISD::LCMPXCHG8_DAG;
20170 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
20171 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
20172 Regs64bit ? X86::RAX : X86::EAX,
20173 HalfT, Result.getValue(1));
20174 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
20175 Regs64bit ? X86::RDX : X86::EDX,
20176 HalfT, cpOutL.getValue(2));
20177 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
20179 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
20180 MVT::i32, cpOutH.getValue(2));
20182 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
20183 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
20184 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
20186 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
20187 Results.push_back(Success);
20188 Results.push_back(EFLAGS.getValue(1));
20191 case ISD::ATOMIC_SWAP:
20192 case ISD::ATOMIC_LOAD_ADD:
20193 case ISD::ATOMIC_LOAD_SUB:
20194 case ISD::ATOMIC_LOAD_AND:
20195 case ISD::ATOMIC_LOAD_OR:
20196 case ISD::ATOMIC_LOAD_XOR:
20197 case ISD::ATOMIC_LOAD_NAND:
20198 case ISD::ATOMIC_LOAD_MIN:
20199 case ISD::ATOMIC_LOAD_MAX:
20200 case ISD::ATOMIC_LOAD_UMIN:
20201 case ISD::ATOMIC_LOAD_UMAX:
20202 case ISD::ATOMIC_LOAD: {
20203 // Delegate to generic TypeLegalization. Situations we can really handle
20204 // should have already been dealt with by AtomicExpandPass.cpp.
20207 case ISD::BITCAST: {
20208 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
20209 EVT DstVT = N->getValueType(0);
20210 EVT SrcVT = N->getOperand(0)->getValueType(0);
20212 if (SrcVT != MVT::f64 ||
20213 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
20216 unsigned NumElts = DstVT.getVectorNumElements();
20217 EVT SVT = DstVT.getVectorElementType();
20218 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
20219 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
20220 MVT::v2f64, N->getOperand(0));
20221 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
20223 if (ExperimentalVectorWideningLegalization) {
20224 // If we are legalizing vectors by widening, we already have the desired
20225 // legal vector type, just return it.
20226 Results.push_back(ToVecInt);
20230 SmallVector<SDValue, 8> Elts;
20231 for (unsigned i = 0, e = NumElts; i != e; ++i)
20232 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
20233 ToVecInt, DAG.getIntPtrConstant(i, dl)));
20235 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
20240 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
20241 switch ((X86ISD::NodeType)Opcode) {
20242 case X86ISD::FIRST_NUMBER: break;
20243 case X86ISD::BSF: return "X86ISD::BSF";
20244 case X86ISD::BSR: return "X86ISD::BSR";
20245 case X86ISD::SHLD: return "X86ISD::SHLD";
20246 case X86ISD::SHRD: return "X86ISD::SHRD";
20247 case X86ISD::FAND: return "X86ISD::FAND";
20248 case X86ISD::FANDN: return "X86ISD::FANDN";
20249 case X86ISD::FOR: return "X86ISD::FOR";
20250 case X86ISD::FXOR: return "X86ISD::FXOR";
20251 case X86ISD::FILD: return "X86ISD::FILD";
20252 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
20253 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
20254 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
20255 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
20256 case X86ISD::FLD: return "X86ISD::FLD";
20257 case X86ISD::FST: return "X86ISD::FST";
20258 case X86ISD::CALL: return "X86ISD::CALL";
20259 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
20260 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
20261 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
20262 case X86ISD::BT: return "X86ISD::BT";
20263 case X86ISD::CMP: return "X86ISD::CMP";
20264 case X86ISD::COMI: return "X86ISD::COMI";
20265 case X86ISD::UCOMI: return "X86ISD::UCOMI";
20266 case X86ISD::CMPM: return "X86ISD::CMPM";
20267 case X86ISD::CMPMU: return "X86ISD::CMPMU";
20268 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
20269 case X86ISD::SETCC: return "X86ISD::SETCC";
20270 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
20271 case X86ISD::FSETCC: return "X86ISD::FSETCC";
20272 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
20273 case X86ISD::CMOV: return "X86ISD::CMOV";
20274 case X86ISD::BRCOND: return "X86ISD::BRCOND";
20275 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
20276 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
20277 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
20278 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
20279 case X86ISD::Wrapper: return "X86ISD::Wrapper";
20280 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
20281 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
20282 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
20283 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
20284 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
20285 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
20286 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
20287 case X86ISD::PINSRB: return "X86ISD::PINSRB";
20288 case X86ISD::PINSRW: return "X86ISD::PINSRW";
20289 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
20290 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
20291 case X86ISD::ANDNP: return "X86ISD::ANDNP";
20292 case X86ISD::PSIGN: return "X86ISD::PSIGN";
20293 case X86ISD::BLENDI: return "X86ISD::BLENDI";
20294 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
20295 case X86ISD::ADDUS: return "X86ISD::ADDUS";
20296 case X86ISD::SUBUS: return "X86ISD::SUBUS";
20297 case X86ISD::HADD: return "X86ISD::HADD";
20298 case X86ISD::HSUB: return "X86ISD::HSUB";
20299 case X86ISD::FHADD: return "X86ISD::FHADD";
20300 case X86ISD::FHSUB: return "X86ISD::FHSUB";
20301 case X86ISD::ABS: return "X86ISD::ABS";
20302 case X86ISD::CONFLICT: return "X86ISD::CONFLICT";
20303 case X86ISD::FMAX: return "X86ISD::FMAX";
20304 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
20305 case X86ISD::FMIN: return "X86ISD::FMIN";
20306 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
20307 case X86ISD::FMAXC: return "X86ISD::FMAXC";
20308 case X86ISD::FMINC: return "X86ISD::FMINC";
20309 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
20310 case X86ISD::FRCP: return "X86ISD::FRCP";
20311 case X86ISD::EXTRQI: return "X86ISD::EXTRQI";
20312 case X86ISD::INSERTQI: return "X86ISD::INSERTQI";
20313 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
20314 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
20315 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
20316 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
20317 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
20318 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
20319 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
20320 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
20321 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
20322 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
20323 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
20324 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
20325 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
20326 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
20327 case X86ISD::VZEXT: return "X86ISD::VZEXT";
20328 case X86ISD::VSEXT: return "X86ISD::VSEXT";
20329 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
20330 case X86ISD::VTRUNCS: return "X86ISD::VTRUNCS";
20331 case X86ISD::VTRUNCUS: return "X86ISD::VTRUNCUS";
20332 case X86ISD::VINSERT: return "X86ISD::VINSERT";
20333 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
20334 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
20335 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
20336 case X86ISD::CVTUDQ2PD: return "X86ISD::CVTUDQ2PD";
20337 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
20338 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
20339 case X86ISD::VSHL: return "X86ISD::VSHL";
20340 case X86ISD::VSRL: return "X86ISD::VSRL";
20341 case X86ISD::VSRA: return "X86ISD::VSRA";
20342 case X86ISD::VSHLI: return "X86ISD::VSHLI";
20343 case X86ISD::VSRLI: return "X86ISD::VSRLI";
20344 case X86ISD::VSRAI: return "X86ISD::VSRAI";
20345 case X86ISD::CMPP: return "X86ISD::CMPP";
20346 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
20347 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
20348 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
20349 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
20350 case X86ISD::ADD: return "X86ISD::ADD";
20351 case X86ISD::SUB: return "X86ISD::SUB";
20352 case X86ISD::ADC: return "X86ISD::ADC";
20353 case X86ISD::SBB: return "X86ISD::SBB";
20354 case X86ISD::SMUL: return "X86ISD::SMUL";
20355 case X86ISD::UMUL: return "X86ISD::UMUL";
20356 case X86ISD::SMUL8: return "X86ISD::SMUL8";
20357 case X86ISD::UMUL8: return "X86ISD::UMUL8";
20358 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
20359 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
20360 case X86ISD::INC: return "X86ISD::INC";
20361 case X86ISD::DEC: return "X86ISD::DEC";
20362 case X86ISD::OR: return "X86ISD::OR";
20363 case X86ISD::XOR: return "X86ISD::XOR";
20364 case X86ISD::AND: return "X86ISD::AND";
20365 case X86ISD::BEXTR: return "X86ISD::BEXTR";
20366 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
20367 case X86ISD::PTEST: return "X86ISD::PTEST";
20368 case X86ISD::TESTP: return "X86ISD::TESTP";
20369 case X86ISD::TESTM: return "X86ISD::TESTM";
20370 case X86ISD::TESTNM: return "X86ISD::TESTNM";
20371 case X86ISD::KORTEST: return "X86ISD::KORTEST";
20372 case X86ISD::KTEST: return "X86ISD::KTEST";
20373 case X86ISD::PACKSS: return "X86ISD::PACKSS";
20374 case X86ISD::PACKUS: return "X86ISD::PACKUS";
20375 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
20376 case X86ISD::VALIGN: return "X86ISD::VALIGN";
20377 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
20378 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
20379 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
20380 case X86ISD::SHUFP: return "X86ISD::SHUFP";
20381 case X86ISD::SHUF128: return "X86ISD::SHUF128";
20382 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
20383 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
20384 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
20385 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
20386 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
20387 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
20388 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
20389 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
20390 case X86ISD::MOVSD: return "X86ISD::MOVSD";
20391 case X86ISD::MOVSS: return "X86ISD::MOVSS";
20392 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
20393 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
20394 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
20395 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
20396 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
20397 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
20398 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
20399 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
20400 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
20401 case X86ISD::VPERMV: return "X86ISD::VPERMV";
20402 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
20403 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
20404 case X86ISD::VPERMI: return "X86ISD::VPERMI";
20405 case X86ISD::VPTERNLOG: return "X86ISD::VPTERNLOG";
20406 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
20407 case X86ISD::VRANGE: return "X86ISD::VRANGE";
20408 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
20409 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
20410 case X86ISD::PSADBW: return "X86ISD::PSADBW";
20411 case X86ISD::DBPSADBW: return "X86ISD::DBPSADBW";
20412 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
20413 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
20414 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
20415 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
20416 case X86ISD::MFENCE: return "X86ISD::MFENCE";
20417 case X86ISD::SFENCE: return "X86ISD::SFENCE";
20418 case X86ISD::LFENCE: return "X86ISD::LFENCE";
20419 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
20420 case X86ISD::SAHF: return "X86ISD::SAHF";
20421 case X86ISD::RDRAND: return "X86ISD::RDRAND";
20422 case X86ISD::RDSEED: return "X86ISD::RDSEED";
20423 case X86ISD::VPMADDUBSW: return "X86ISD::VPMADDUBSW";
20424 case X86ISD::VPMADDWD: return "X86ISD::VPMADDWD";
20425 case X86ISD::VPROT: return "X86ISD::VPROT";
20426 case X86ISD::VPROTI: return "X86ISD::VPROTI";
20427 case X86ISD::VPSHA: return "X86ISD::VPSHA";
20428 case X86ISD::VPSHL: return "X86ISD::VPSHL";
20429 case X86ISD::VPCOM: return "X86ISD::VPCOM";
20430 case X86ISD::VPCOMU: return "X86ISD::VPCOMU";
20431 case X86ISD::FMADD: return "X86ISD::FMADD";
20432 case X86ISD::FMSUB: return "X86ISD::FMSUB";
20433 case X86ISD::FNMADD: return "X86ISD::FNMADD";
20434 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
20435 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
20436 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
20437 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
20438 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
20439 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
20440 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
20441 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
20442 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
20443 case X86ISD::VRNDSCALE: return "X86ISD::VRNDSCALE";
20444 case X86ISD::VREDUCE: return "X86ISD::VREDUCE";
20445 case X86ISD::VGETMANT: return "X86ISD::VGETMANT";
20446 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
20447 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
20448 case X86ISD::XTEST: return "X86ISD::XTEST";
20449 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
20450 case X86ISD::EXPAND: return "X86ISD::EXPAND";
20451 case X86ISD::SELECT: return "X86ISD::SELECT";
20452 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
20453 case X86ISD::RCP28: return "X86ISD::RCP28";
20454 case X86ISD::EXP2: return "X86ISD::EXP2";
20455 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
20456 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
20457 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
20458 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
20459 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
20460 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
20461 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
20462 case X86ISD::SCALEF: return "X86ISD::SCALEF";
20463 case X86ISD::ADDS: return "X86ISD::ADDS";
20464 case X86ISD::SUBS: return "X86ISD::SUBS";
20465 case X86ISD::AVG: return "X86ISD::AVG";
20466 case X86ISD::MULHRS: return "X86ISD::MULHRS";
20467 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
20468 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
20469 case X86ISD::FP_TO_SINT_RND: return "X86ISD::FP_TO_SINT_RND";
20470 case X86ISD::FP_TO_UINT_RND: return "X86ISD::FP_TO_UINT_RND";
20471 case X86ISD::VFPCLASS: return "X86ISD::VFPCLASS";
20472 case X86ISD::VFPCLASSS: return "X86ISD::VFPCLASSS";
20477 // isLegalAddressingMode - Return true if the addressing mode represented
20478 // by AM is legal for this target, for a load/store of the specified type.
20479 bool X86TargetLowering::isLegalAddressingMode(const DataLayout &DL,
20480 const AddrMode &AM, Type *Ty,
20481 unsigned AS) const {
20482 // X86 supports extremely general addressing modes.
20483 CodeModel::Model M = getTargetMachine().getCodeModel();
20484 Reloc::Model R = getTargetMachine().getRelocationModel();
20486 // X86 allows a sign-extended 32-bit immediate field as a displacement.
20487 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
20492 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
20494 // If a reference to this global requires an extra load, we can't fold it.
20495 if (isGlobalStubReference(GVFlags))
20498 // If BaseGV requires a register for the PIC base, we cannot also have a
20499 // BaseReg specified.
20500 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
20503 // If lower 4G is not available, then we must use rip-relative addressing.
20504 if ((M != CodeModel::Small || R != Reloc::Static) &&
20505 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
20509 switch (AM.Scale) {
20515 // These scales always work.
20520 // These scales are formed with basereg+scalereg. Only accept if there is
20525 default: // Other stuff never works.
20532 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
20533 unsigned Bits = Ty->getScalarSizeInBits();
20535 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
20536 // particularly cheaper than those without.
20540 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
20541 // variable shifts just as cheap as scalar ones.
20542 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
20545 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
20546 // fully general vector.
20550 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
20551 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20553 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
20554 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
20555 return NumBits1 > NumBits2;
20558 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
20559 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20562 if (!isTypeLegal(EVT::getEVT(Ty1)))
20565 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
20567 // Assuming the caller doesn't have a zeroext or signext return parameter,
20568 // truncation all the way down to i1 is valid.
20572 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
20573 return isInt<32>(Imm);
20576 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
20577 // Can also use sub to handle negated immediates.
20578 return isInt<32>(Imm);
20581 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
20582 if (!VT1.isInteger() || !VT2.isInteger())
20584 unsigned NumBits1 = VT1.getSizeInBits();
20585 unsigned NumBits2 = VT2.getSizeInBits();
20586 return NumBits1 > NumBits2;
20589 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
20590 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20591 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
20594 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
20595 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20596 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
20599 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
20600 EVT VT1 = Val.getValueType();
20601 if (isZExtFree(VT1, VT2))
20604 if (Val.getOpcode() != ISD::LOAD)
20607 if (!VT1.isSimple() || !VT1.isInteger() ||
20608 !VT2.isSimple() || !VT2.isInteger())
20611 switch (VT1.getSimpleVT().SimpleTy) {
20616 // X86 has 8, 16, and 32-bit zero-extending loads.
20623 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
20626 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20627 if (!Subtarget->hasAnyFMA())
20630 VT = VT.getScalarType();
20632 if (!VT.isSimple())
20635 switch (VT.getSimpleVT().SimpleTy) {
20646 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
20647 // i16 instructions are longer (0x66 prefix) and potentially slower.
20648 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
20651 /// isShuffleMaskLegal - Targets can use this to indicate that they only
20652 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
20653 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
20654 /// are assumed to be legal.
20656 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
20658 if (!VT.isSimple())
20661 // Not for i1 vectors
20662 if (VT.getSimpleVT().getScalarType() == MVT::i1)
20665 // Very little shuffling can be done for 64-bit vectors right now.
20666 if (VT.getSimpleVT().getSizeInBits() == 64)
20669 // We only care that the types being shuffled are legal. The lowering can
20670 // handle any possible shuffle mask that results.
20671 return isTypeLegal(VT.getSimpleVT());
20675 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20677 // Just delegate to the generic legality, clear masks aren't special.
20678 return isShuffleMaskLegal(Mask, VT);
20681 //===----------------------------------------------------------------------===//
20682 // X86 Scheduler Hooks
20683 //===----------------------------------------------------------------------===//
20685 /// Utility function to emit xbegin specifying the start of an RTM region.
20686 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20687 const TargetInstrInfo *TII) {
20688 DebugLoc DL = MI->getDebugLoc();
20690 const BasicBlock *BB = MBB->getBasicBlock();
20691 MachineFunction::iterator I = ++MBB->getIterator();
20693 // For the v = xbegin(), we generate
20704 MachineBasicBlock *thisMBB = MBB;
20705 MachineFunction *MF = MBB->getParent();
20706 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20707 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20708 MF->insert(I, mainMBB);
20709 MF->insert(I, sinkMBB);
20711 // Transfer the remainder of BB and its successor edges to sinkMBB.
20712 sinkMBB->splice(sinkMBB->begin(), MBB,
20713 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20714 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20718 // # fallthrough to mainMBB
20719 // # abortion to sinkMBB
20720 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20721 thisMBB->addSuccessor(mainMBB);
20722 thisMBB->addSuccessor(sinkMBB);
20726 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20727 mainMBB->addSuccessor(sinkMBB);
20730 // EAX is live into the sinkMBB
20731 sinkMBB->addLiveIn(X86::EAX);
20732 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20733 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20736 MI->eraseFromParent();
20740 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20741 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20742 // in the .td file.
20743 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20744 const TargetInstrInfo *TII) {
20746 switch (MI->getOpcode()) {
20747 default: llvm_unreachable("illegal opcode!");
20748 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20749 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20750 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20751 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20752 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20753 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20754 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20755 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20758 DebugLoc dl = MI->getDebugLoc();
20759 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20761 unsigned NumArgs = MI->getNumOperands();
20762 for (unsigned i = 1; i < NumArgs; ++i) {
20763 MachineOperand &Op = MI->getOperand(i);
20764 if (!(Op.isReg() && Op.isImplicit()))
20765 MIB.addOperand(Op);
20767 if (MI->hasOneMemOperand())
20768 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20770 BuildMI(*BB, MI, dl,
20771 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20772 .addReg(X86::XMM0);
20774 MI->eraseFromParent();
20778 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20779 // defs in an instruction pattern
20780 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20781 const TargetInstrInfo *TII) {
20783 switch (MI->getOpcode()) {
20784 default: llvm_unreachable("illegal opcode!");
20785 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20786 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20787 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20788 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20789 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20790 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20791 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20792 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20795 DebugLoc dl = MI->getDebugLoc();
20796 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20798 unsigned NumArgs = MI->getNumOperands(); // remove the results
20799 for (unsigned i = 1; i < NumArgs; ++i) {
20800 MachineOperand &Op = MI->getOperand(i);
20801 if (!(Op.isReg() && Op.isImplicit()))
20802 MIB.addOperand(Op);
20804 if (MI->hasOneMemOperand())
20805 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20807 BuildMI(*BB, MI, dl,
20808 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20811 MI->eraseFromParent();
20815 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20816 const X86Subtarget *Subtarget) {
20817 DebugLoc dl = MI->getDebugLoc();
20818 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20819 // Address into RAX/EAX, other two args into ECX, EDX.
20820 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20821 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20822 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20823 for (int i = 0; i < X86::AddrNumOperands; ++i)
20824 MIB.addOperand(MI->getOperand(i));
20826 unsigned ValOps = X86::AddrNumOperands;
20827 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20828 .addReg(MI->getOperand(ValOps).getReg());
20829 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20830 .addReg(MI->getOperand(ValOps+1).getReg());
20832 // The instruction doesn't actually take any operands though.
20833 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20835 MI->eraseFromParent(); // The pseudo is gone now.
20839 MachineBasicBlock *
20840 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
20841 MachineBasicBlock *MBB) const {
20842 // Emit va_arg instruction on X86-64.
20844 // Operands to this pseudo-instruction:
20845 // 0 ) Output : destination address (reg)
20846 // 1-5) Input : va_list address (addr, i64mem)
20847 // 6 ) ArgSize : Size (in bytes) of vararg type
20848 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20849 // 8 ) Align : Alignment of type
20850 // 9 ) EFLAGS (implicit-def)
20852 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20853 static_assert(X86::AddrNumOperands == 5,
20854 "VAARG_64 assumes 5 address operands");
20856 unsigned DestReg = MI->getOperand(0).getReg();
20857 MachineOperand &Base = MI->getOperand(1);
20858 MachineOperand &Scale = MI->getOperand(2);
20859 MachineOperand &Index = MI->getOperand(3);
20860 MachineOperand &Disp = MI->getOperand(4);
20861 MachineOperand &Segment = MI->getOperand(5);
20862 unsigned ArgSize = MI->getOperand(6).getImm();
20863 unsigned ArgMode = MI->getOperand(7).getImm();
20864 unsigned Align = MI->getOperand(8).getImm();
20866 // Memory Reference
20867 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20868 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20869 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20871 // Machine Information
20872 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20873 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20874 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20875 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20876 DebugLoc DL = MI->getDebugLoc();
20878 // struct va_list {
20881 // i64 overflow_area (address)
20882 // i64 reg_save_area (address)
20884 // sizeof(va_list) = 24
20885 // alignment(va_list) = 8
20887 unsigned TotalNumIntRegs = 6;
20888 unsigned TotalNumXMMRegs = 8;
20889 bool UseGPOffset = (ArgMode == 1);
20890 bool UseFPOffset = (ArgMode == 2);
20891 unsigned MaxOffset = TotalNumIntRegs * 8 +
20892 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20894 /* Align ArgSize to a multiple of 8 */
20895 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20896 bool NeedsAlign = (Align > 8);
20898 MachineBasicBlock *thisMBB = MBB;
20899 MachineBasicBlock *overflowMBB;
20900 MachineBasicBlock *offsetMBB;
20901 MachineBasicBlock *endMBB;
20903 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20904 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20905 unsigned OffsetReg = 0;
20907 if (!UseGPOffset && !UseFPOffset) {
20908 // If we only pull from the overflow region, we don't create a branch.
20909 // We don't need to alter control flow.
20910 OffsetDestReg = 0; // unused
20911 OverflowDestReg = DestReg;
20913 offsetMBB = nullptr;
20914 overflowMBB = thisMBB;
20917 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20918 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20919 // If not, pull from overflow_area. (branch to overflowMBB)
20924 // offsetMBB overflowMBB
20929 // Registers for the PHI in endMBB
20930 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20931 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20933 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20934 MachineFunction *MF = MBB->getParent();
20935 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20936 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20937 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20939 MachineFunction::iterator MBBIter = ++MBB->getIterator();
20941 // Insert the new basic blocks
20942 MF->insert(MBBIter, offsetMBB);
20943 MF->insert(MBBIter, overflowMBB);
20944 MF->insert(MBBIter, endMBB);
20946 // Transfer the remainder of MBB and its successor edges to endMBB.
20947 endMBB->splice(endMBB->begin(), thisMBB,
20948 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20949 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20951 // Make offsetMBB and overflowMBB successors of thisMBB
20952 thisMBB->addSuccessor(offsetMBB);
20953 thisMBB->addSuccessor(overflowMBB);
20955 // endMBB is a successor of both offsetMBB and overflowMBB
20956 offsetMBB->addSuccessor(endMBB);
20957 overflowMBB->addSuccessor(endMBB);
20959 // Load the offset value into a register
20960 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20961 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20965 .addDisp(Disp, UseFPOffset ? 4 : 0)
20966 .addOperand(Segment)
20967 .setMemRefs(MMOBegin, MMOEnd);
20969 // Check if there is enough room left to pull this argument.
20970 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20972 .addImm(MaxOffset + 8 - ArgSizeA8);
20974 // Branch to "overflowMBB" if offset >= max
20975 // Fall through to "offsetMBB" otherwise
20976 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20977 .addMBB(overflowMBB);
20980 // In offsetMBB, emit code to use the reg_save_area.
20982 assert(OffsetReg != 0);
20984 // Read the reg_save_area address.
20985 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20986 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20991 .addOperand(Segment)
20992 .setMemRefs(MMOBegin, MMOEnd);
20994 // Zero-extend the offset
20995 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20996 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20999 .addImm(X86::sub_32bit);
21001 // Add the offset to the reg_save_area to get the final address.
21002 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
21003 .addReg(OffsetReg64)
21004 .addReg(RegSaveReg);
21006 // Compute the offset for the next argument
21007 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
21008 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
21010 .addImm(UseFPOffset ? 16 : 8);
21012 // Store it back into the va_list.
21013 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
21017 .addDisp(Disp, UseFPOffset ? 4 : 0)
21018 .addOperand(Segment)
21019 .addReg(NextOffsetReg)
21020 .setMemRefs(MMOBegin, MMOEnd);
21023 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
21028 // Emit code to use overflow area
21031 // Load the overflow_area address into a register.
21032 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
21033 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
21038 .addOperand(Segment)
21039 .setMemRefs(MMOBegin, MMOEnd);
21041 // If we need to align it, do so. Otherwise, just copy the address
21042 // to OverflowDestReg.
21044 // Align the overflow address
21045 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
21046 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
21048 // aligned_addr = (addr + (align-1)) & ~(align-1)
21049 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
21050 .addReg(OverflowAddrReg)
21053 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
21055 .addImm(~(uint64_t)(Align-1));
21057 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
21058 .addReg(OverflowAddrReg);
21061 // Compute the next overflow address after this argument.
21062 // (the overflow address should be kept 8-byte aligned)
21063 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
21064 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
21065 .addReg(OverflowDestReg)
21066 .addImm(ArgSizeA8);
21068 // Store the new overflow address.
21069 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
21074 .addOperand(Segment)
21075 .addReg(NextAddrReg)
21076 .setMemRefs(MMOBegin, MMOEnd);
21078 // If we branched, emit the PHI to the front of endMBB.
21080 BuildMI(*endMBB, endMBB->begin(), DL,
21081 TII->get(X86::PHI), DestReg)
21082 .addReg(OffsetDestReg).addMBB(offsetMBB)
21083 .addReg(OverflowDestReg).addMBB(overflowMBB);
21086 // Erase the pseudo instruction
21087 MI->eraseFromParent();
21092 MachineBasicBlock *
21093 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
21095 MachineBasicBlock *MBB) const {
21096 // Emit code to save XMM registers to the stack. The ABI says that the
21097 // number of registers to save is given in %al, so it's theoretically
21098 // possible to do an indirect jump trick to avoid saving all of them,
21099 // however this code takes a simpler approach and just executes all
21100 // of the stores if %al is non-zero. It's less code, and it's probably
21101 // easier on the hardware branch predictor, and stores aren't all that
21102 // expensive anyway.
21104 // Create the new basic blocks. One block contains all the XMM stores,
21105 // and one block is the final destination regardless of whether any
21106 // stores were performed.
21107 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
21108 MachineFunction *F = MBB->getParent();
21109 MachineFunction::iterator MBBIter = ++MBB->getIterator();
21110 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
21111 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
21112 F->insert(MBBIter, XMMSaveMBB);
21113 F->insert(MBBIter, EndMBB);
21115 // Transfer the remainder of MBB and its successor edges to EndMBB.
21116 EndMBB->splice(EndMBB->begin(), MBB,
21117 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21118 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
21120 // The original block will now fall through to the XMM save block.
21121 MBB->addSuccessor(XMMSaveMBB);
21122 // The XMMSaveMBB will fall through to the end block.
21123 XMMSaveMBB->addSuccessor(EndMBB);
21125 // Now add the instructions.
21126 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21127 DebugLoc DL = MI->getDebugLoc();
21129 unsigned CountReg = MI->getOperand(0).getReg();
21130 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
21131 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
21133 if (!Subtarget->isCallingConvWin64(F->getFunction()->getCallingConv())) {
21134 // If %al is 0, branch around the XMM save block.
21135 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
21136 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
21137 MBB->addSuccessor(EndMBB);
21140 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
21141 // that was just emitted, but clearly shouldn't be "saved".
21142 assert((MI->getNumOperands() <= 3 ||
21143 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
21144 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
21145 && "Expected last argument to be EFLAGS");
21146 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
21147 // In the XMM save block, save all the XMM argument registers.
21148 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
21149 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
21150 MachineMemOperand *MMO = F->getMachineMemOperand(
21151 MachinePointerInfo::getFixedStack(*F, RegSaveFrameIndex, Offset),
21152 MachineMemOperand::MOStore,
21153 /*Size=*/16, /*Align=*/16);
21154 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
21155 .addFrameIndex(RegSaveFrameIndex)
21156 .addImm(/*Scale=*/1)
21157 .addReg(/*IndexReg=*/0)
21158 .addImm(/*Disp=*/Offset)
21159 .addReg(/*Segment=*/0)
21160 .addReg(MI->getOperand(i).getReg())
21161 .addMemOperand(MMO);
21164 MI->eraseFromParent(); // The pseudo instruction is gone now.
21169 // The EFLAGS operand of SelectItr might be missing a kill marker
21170 // because there were multiple uses of EFLAGS, and ISel didn't know
21171 // which to mark. Figure out whether SelectItr should have had a
21172 // kill marker, and set it if it should. Returns the correct kill
21174 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
21175 MachineBasicBlock* BB,
21176 const TargetRegisterInfo* TRI) {
21177 // Scan forward through BB for a use/def of EFLAGS.
21178 MachineBasicBlock::iterator miI(std::next(SelectItr));
21179 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
21180 const MachineInstr& mi = *miI;
21181 if (mi.readsRegister(X86::EFLAGS))
21183 if (mi.definesRegister(X86::EFLAGS))
21184 break; // Should have kill-flag - update below.
21187 // If we hit the end of the block, check whether EFLAGS is live into a
21189 if (miI == BB->end()) {
21190 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
21191 sEnd = BB->succ_end();
21192 sItr != sEnd; ++sItr) {
21193 MachineBasicBlock* succ = *sItr;
21194 if (succ->isLiveIn(X86::EFLAGS))
21199 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
21200 // out. SelectMI should have a kill flag on EFLAGS.
21201 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
21205 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
21206 // together with other CMOV pseudo-opcodes into a single basic-block with
21207 // conditional jump around it.
21208 static bool isCMOVPseudo(MachineInstr *MI) {
21209 switch (MI->getOpcode()) {
21210 case X86::CMOV_FR32:
21211 case X86::CMOV_FR64:
21212 case X86::CMOV_GR8:
21213 case X86::CMOV_GR16:
21214 case X86::CMOV_GR32:
21215 case X86::CMOV_RFP32:
21216 case X86::CMOV_RFP64:
21217 case X86::CMOV_RFP80:
21218 case X86::CMOV_V2F64:
21219 case X86::CMOV_V2I64:
21220 case X86::CMOV_V4F32:
21221 case X86::CMOV_V4F64:
21222 case X86::CMOV_V4I64:
21223 case X86::CMOV_V16F32:
21224 case X86::CMOV_V8F32:
21225 case X86::CMOV_V8F64:
21226 case X86::CMOV_V8I64:
21227 case X86::CMOV_V8I1:
21228 case X86::CMOV_V16I1:
21229 case X86::CMOV_V32I1:
21230 case X86::CMOV_V64I1:
21238 MachineBasicBlock *
21239 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
21240 MachineBasicBlock *BB) const {
21241 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21242 DebugLoc DL = MI->getDebugLoc();
21244 // To "insert" a SELECT_CC instruction, we actually have to insert the
21245 // diamond control-flow pattern. The incoming instruction knows the
21246 // destination vreg to set, the condition code register to branch on, the
21247 // true/false values to select between, and a branch opcode to use.
21248 const BasicBlock *LLVM_BB = BB->getBasicBlock();
21249 MachineFunction::iterator It = ++BB->getIterator();
21254 // cmpTY ccX, r1, r2
21256 // fallthrough --> copy0MBB
21257 MachineBasicBlock *thisMBB = BB;
21258 MachineFunction *F = BB->getParent();
21260 // This code lowers all pseudo-CMOV instructions. Generally it lowers these
21261 // as described above, by inserting a BB, and then making a PHI at the join
21262 // point to select the true and false operands of the CMOV in the PHI.
21264 // The code also handles two different cases of multiple CMOV opcodes
21268 // In this case, there are multiple CMOVs in a row, all which are based on
21269 // the same condition setting (or the exact opposite condition setting).
21270 // In this case we can lower all the CMOVs using a single inserted BB, and
21271 // then make a number of PHIs at the join point to model the CMOVs. The only
21272 // trickiness here, is that in a case like:
21274 // t2 = CMOV cond1 t1, f1
21275 // t3 = CMOV cond1 t2, f2
21277 // when rewriting this into PHIs, we have to perform some renaming on the
21278 // temps since you cannot have a PHI operand refer to a PHI result earlier
21279 // in the same block. The "simple" but wrong lowering would be:
21281 // t2 = PHI t1(BB1), f1(BB2)
21282 // t3 = PHI t2(BB1), f2(BB2)
21284 // but clearly t2 is not defined in BB1, so that is incorrect. The proper
21285 // renaming is to note that on the path through BB1, t2 is really just a
21286 // copy of t1, and do that renaming, properly generating:
21288 // t2 = PHI t1(BB1), f1(BB2)
21289 // t3 = PHI t1(BB1), f2(BB2)
21291 // Case 2, we lower cascaded CMOVs such as
21293 // (CMOV (CMOV F, T, cc1), T, cc2)
21295 // to two successives branches. For that, we look for another CMOV as the
21296 // following instruction.
21298 // Without this, we would add a PHI between the two jumps, which ends up
21299 // creating a few copies all around. For instance, for
21301 // (sitofp (zext (fcmp une)))
21303 // we would generate:
21305 // ucomiss %xmm1, %xmm0
21306 // movss <1.0f>, %xmm0
21307 // movaps %xmm0, %xmm1
21309 // xorps %xmm1, %xmm1
21312 // movaps %xmm1, %xmm0
21316 // because this custom-inserter would have generated:
21328 // A: X = ...; Y = ...
21330 // C: Z = PHI [X, A], [Y, B]
21332 // E: PHI [X, C], [Z, D]
21334 // If we lower both CMOVs in a single step, we can instead generate:
21346 // A: X = ...; Y = ...
21348 // E: PHI [X, A], [X, C], [Y, D]
21350 // Which, in our sitofp/fcmp example, gives us something like:
21352 // ucomiss %xmm1, %xmm0
21353 // movss <1.0f>, %xmm0
21356 // xorps %xmm0, %xmm0
21360 MachineInstr *CascadedCMOV = nullptr;
21361 MachineInstr *LastCMOV = MI;
21362 X86::CondCode CC = X86::CondCode(MI->getOperand(3).getImm());
21363 X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC);
21364 MachineBasicBlock::iterator NextMIIt =
21365 std::next(MachineBasicBlock::iterator(MI));
21367 // Check for case 1, where there are multiple CMOVs with the same condition
21368 // first. Of the two cases of multiple CMOV lowerings, case 1 reduces the
21369 // number of jumps the most.
21371 if (isCMOVPseudo(MI)) {
21372 // See if we have a string of CMOVS with the same condition.
21373 while (NextMIIt != BB->end() &&
21374 isCMOVPseudo(NextMIIt) &&
21375 (NextMIIt->getOperand(3).getImm() == CC ||
21376 NextMIIt->getOperand(3).getImm() == OppCC)) {
21377 LastCMOV = &*NextMIIt;
21382 // This checks for case 2, but only do this if we didn't already find
21383 // case 1, as indicated by LastCMOV == MI.
21384 if (LastCMOV == MI &&
21385 NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
21386 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
21387 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg()) {
21388 CascadedCMOV = &*NextMIIt;
21391 MachineBasicBlock *jcc1MBB = nullptr;
21393 // If we have a cascaded CMOV, we lower it to two successive branches to
21394 // the same block. EFLAGS is used by both, so mark it as live in the second.
21395 if (CascadedCMOV) {
21396 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
21397 F->insert(It, jcc1MBB);
21398 jcc1MBB->addLiveIn(X86::EFLAGS);
21401 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
21402 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
21403 F->insert(It, copy0MBB);
21404 F->insert(It, sinkMBB);
21406 // If the EFLAGS register isn't dead in the terminator, then claim that it's
21407 // live into the sink and copy blocks.
21408 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
21410 MachineInstr *LastEFLAGSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
21411 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
21412 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
21413 copy0MBB->addLiveIn(X86::EFLAGS);
21414 sinkMBB->addLiveIn(X86::EFLAGS);
21417 // Transfer the remainder of BB and its successor edges to sinkMBB.
21418 sinkMBB->splice(sinkMBB->begin(), BB,
21419 std::next(MachineBasicBlock::iterator(LastCMOV)), BB->end());
21420 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
21422 // Add the true and fallthrough blocks as its successors.
21423 if (CascadedCMOV) {
21424 // The fallthrough block may be jcc1MBB, if we have a cascaded CMOV.
21425 BB->addSuccessor(jcc1MBB);
21427 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
21428 // jump to the sinkMBB.
21429 jcc1MBB->addSuccessor(copy0MBB);
21430 jcc1MBB->addSuccessor(sinkMBB);
21432 BB->addSuccessor(copy0MBB);
21435 // The true block target of the first (or only) branch is always sinkMBB.
21436 BB->addSuccessor(sinkMBB);
21438 // Create the conditional branch instruction.
21439 unsigned Opc = X86::GetCondBranchFromCond(CC);
21440 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
21442 if (CascadedCMOV) {
21443 unsigned Opc2 = X86::GetCondBranchFromCond(
21444 (X86::CondCode)CascadedCMOV->getOperand(3).getImm());
21445 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
21449 // %FalseValue = ...
21450 // # fallthrough to sinkMBB
21451 copy0MBB->addSuccessor(sinkMBB);
21454 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
21456 MachineBasicBlock::iterator MIItBegin = MachineBasicBlock::iterator(MI);
21457 MachineBasicBlock::iterator MIItEnd =
21458 std::next(MachineBasicBlock::iterator(LastCMOV));
21459 MachineBasicBlock::iterator SinkInsertionPoint = sinkMBB->begin();
21460 DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
21461 MachineInstrBuilder MIB;
21463 // As we are creating the PHIs, we have to be careful if there is more than
21464 // one. Later CMOVs may reference the results of earlier CMOVs, but later
21465 // PHIs have to reference the individual true/false inputs from earlier PHIs.
21466 // That also means that PHI construction must work forward from earlier to
21467 // later, and that the code must maintain a mapping from earlier PHI's
21468 // destination registers, and the registers that went into the PHI.
21470 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
21471 unsigned DestReg = MIIt->getOperand(0).getReg();
21472 unsigned Op1Reg = MIIt->getOperand(1).getReg();
21473 unsigned Op2Reg = MIIt->getOperand(2).getReg();
21475 // If this CMOV we are generating is the opposite condition from
21476 // the jump we generated, then we have to swap the operands for the
21477 // PHI that is going to be generated.
21478 if (MIIt->getOperand(3).getImm() == OppCC)
21479 std::swap(Op1Reg, Op2Reg);
21481 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end())
21482 Op1Reg = RegRewriteTable[Op1Reg].first;
21484 if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end())
21485 Op2Reg = RegRewriteTable[Op2Reg].second;
21487 MIB = BuildMI(*sinkMBB, SinkInsertionPoint, DL,
21488 TII->get(X86::PHI), DestReg)
21489 .addReg(Op1Reg).addMBB(copy0MBB)
21490 .addReg(Op2Reg).addMBB(thisMBB);
21492 // Add this PHI to the rewrite table.
21493 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
21496 // If we have a cascaded CMOV, the second Jcc provides the same incoming
21497 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
21498 if (CascadedCMOV) {
21499 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
21500 // Copy the PHI result to the register defined by the second CMOV.
21501 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
21502 DL, TII->get(TargetOpcode::COPY),
21503 CascadedCMOV->getOperand(0).getReg())
21504 .addReg(MI->getOperand(0).getReg());
21505 CascadedCMOV->eraseFromParent();
21508 // Now remove the CMOV(s).
21509 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; )
21510 (MIIt++)->eraseFromParent();
21515 MachineBasicBlock *
21516 X86TargetLowering::EmitLoweredAtomicFP(MachineInstr *MI,
21517 MachineBasicBlock *BB) const {
21518 // Combine the following atomic floating-point modification pattern:
21519 // a.store(reg OP a.load(acquire), release)
21520 // Transform them into:
21521 // OPss (%gpr), %xmm
21522 // movss %xmm, (%gpr)
21523 // Or sd equivalent for 64-bit operations.
21525 switch (MI->getOpcode()) {
21526 default: llvm_unreachable("unexpected instr type for EmitLoweredAtomicFP");
21527 case X86::RELEASE_FADD32mr: MOp = X86::MOVSSmr; FOp = X86::ADDSSrm; break;
21528 case X86::RELEASE_FADD64mr: MOp = X86::MOVSDmr; FOp = X86::ADDSDrm; break;
21530 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21531 DebugLoc DL = MI->getDebugLoc();
21532 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
21533 MachineOperand MSrc = MI->getOperand(0);
21534 unsigned VSrc = MI->getOperand(5).getReg();
21535 const MachineOperand &Disp = MI->getOperand(3);
21536 MachineOperand ZeroDisp = MachineOperand::CreateImm(0);
21537 bool hasDisp = Disp.isGlobal() || Disp.isImm();
21538 if (hasDisp && MSrc.isReg())
21539 MSrc.setIsKill(false);
21540 MachineInstrBuilder MIM = BuildMI(*BB, MI, DL, TII->get(MOp))
21541 .addOperand(/*Base=*/MSrc)
21542 .addImm(/*Scale=*/1)
21543 .addReg(/*Index=*/0)
21544 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21546 MachineInstr *MIO = BuildMI(*BB, (MachineInstr *)MIM, DL, TII->get(FOp),
21547 MRI.createVirtualRegister(MRI.getRegClass(VSrc)))
21549 .addOperand(/*Base=*/MSrc)
21550 .addImm(/*Scale=*/1)
21551 .addReg(/*Index=*/0)
21552 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21553 .addReg(/*Segment=*/0);
21554 MIM.addReg(MIO->getOperand(0).getReg(), RegState::Kill);
21555 MI->eraseFromParent(); // The pseudo instruction is gone now.
21559 MachineBasicBlock *
21560 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
21561 MachineBasicBlock *BB) const {
21562 MachineFunction *MF = BB->getParent();
21563 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21564 DebugLoc DL = MI->getDebugLoc();
21565 const BasicBlock *LLVM_BB = BB->getBasicBlock();
21567 assert(MF->shouldSplitStack());
21569 const bool Is64Bit = Subtarget->is64Bit();
21570 const bool IsLP64 = Subtarget->isTarget64BitLP64();
21572 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
21573 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
21576 // ... [Till the alloca]
21577 // If stacklet is not large enough, jump to mallocMBB
21580 // Allocate by subtracting from RSP
21581 // Jump to continueMBB
21584 // Allocate by call to runtime
21588 // [rest of original BB]
21591 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21592 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21593 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21595 MachineRegisterInfo &MRI = MF->getRegInfo();
21596 const TargetRegisterClass *AddrRegClass =
21597 getRegClassFor(getPointerTy(MF->getDataLayout()));
21599 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21600 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21601 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
21602 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
21603 sizeVReg = MI->getOperand(1).getReg(),
21604 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
21606 MachineFunction::iterator MBBIter = ++BB->getIterator();
21608 MF->insert(MBBIter, bumpMBB);
21609 MF->insert(MBBIter, mallocMBB);
21610 MF->insert(MBBIter, continueMBB);
21612 continueMBB->splice(continueMBB->begin(), BB,
21613 std::next(MachineBasicBlock::iterator(MI)), BB->end());
21614 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
21616 // Add code to the main basic block to check if the stack limit has been hit,
21617 // and if so, jump to mallocMBB otherwise to bumpMBB.
21618 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
21619 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
21620 .addReg(tmpSPVReg).addReg(sizeVReg);
21621 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
21622 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
21623 .addReg(SPLimitVReg);
21624 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
21626 // bumpMBB simply decreases the stack pointer, since we know the current
21627 // stacklet has enough space.
21628 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
21629 .addReg(SPLimitVReg);
21630 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
21631 .addReg(SPLimitVReg);
21632 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21634 // Calls into a routine in libgcc to allocate more space from the heap.
21635 const uint32_t *RegMask =
21636 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
21638 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
21640 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21641 .addExternalSymbol("__morestack_allocate_stack_space")
21642 .addRegMask(RegMask)
21643 .addReg(X86::RDI, RegState::Implicit)
21644 .addReg(X86::RAX, RegState::ImplicitDefine);
21645 } else if (Is64Bit) {
21646 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
21648 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21649 .addExternalSymbol("__morestack_allocate_stack_space")
21650 .addRegMask(RegMask)
21651 .addReg(X86::EDI, RegState::Implicit)
21652 .addReg(X86::EAX, RegState::ImplicitDefine);
21654 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
21656 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
21657 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
21658 .addExternalSymbol("__morestack_allocate_stack_space")
21659 .addRegMask(RegMask)
21660 .addReg(X86::EAX, RegState::ImplicitDefine);
21664 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
21667 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
21668 .addReg(IsLP64 ? X86::RAX : X86::EAX);
21669 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21671 // Set up the CFG correctly.
21672 BB->addSuccessor(bumpMBB);
21673 BB->addSuccessor(mallocMBB);
21674 mallocMBB->addSuccessor(continueMBB);
21675 bumpMBB->addSuccessor(continueMBB);
21677 // Take care of the PHI nodes.
21678 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
21679 MI->getOperand(0).getReg())
21680 .addReg(mallocPtrVReg).addMBB(mallocMBB)
21681 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
21683 // Delete the original pseudo instruction.
21684 MI->eraseFromParent();
21687 return continueMBB;
21690 MachineBasicBlock *
21691 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
21692 MachineBasicBlock *BB) const {
21693 assert(!Subtarget->isTargetMachO());
21694 DebugLoc DL = MI->getDebugLoc();
21695 MachineInstr *ResumeMI = Subtarget->getFrameLowering()->emitStackProbe(
21696 *BB->getParent(), *BB, MI, DL, false);
21697 MachineBasicBlock *ResumeBB = ResumeMI->getParent();
21698 MI->eraseFromParent(); // The pseudo instruction is gone now.
21702 MachineBasicBlock *
21703 X86TargetLowering::EmitLoweredCatchRet(MachineInstr *MI,
21704 MachineBasicBlock *BB) const {
21705 MachineFunction *MF = BB->getParent();
21706 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21707 MachineBasicBlock *TargetMBB = MI->getOperand(0).getMBB();
21708 DebugLoc DL = MI->getDebugLoc();
21710 assert(!isAsynchronousEHPersonality(
21711 classifyEHPersonality(MF->getFunction()->getPersonalityFn())) &&
21712 "SEH does not use catchret!");
21714 // Only 32-bit EH needs to worry about manually restoring stack pointers.
21715 if (!Subtarget->is32Bit())
21718 // C++ EH creates a new target block to hold the restore code, and wires up
21719 // the new block to the return destination with a normal JMP_4.
21720 MachineBasicBlock *RestoreMBB =
21721 MF->CreateMachineBasicBlock(BB->getBasicBlock());
21722 assert(BB->succ_size() == 1);
21723 MF->insert(std::next(BB->getIterator()), RestoreMBB);
21724 RestoreMBB->transferSuccessorsAndUpdatePHIs(BB);
21725 BB->addSuccessor(RestoreMBB);
21726 MI->getOperand(0).setMBB(RestoreMBB);
21728 auto RestoreMBBI = RestoreMBB->begin();
21729 BuildMI(*RestoreMBB, RestoreMBBI, DL, TII.get(X86::EH_RESTORE));
21730 BuildMI(*RestoreMBB, RestoreMBBI, DL, TII.get(X86::JMP_4)).addMBB(TargetMBB);
21734 MachineBasicBlock *
21735 X86TargetLowering::EmitLoweredCatchPad(MachineInstr *MI,
21736 MachineBasicBlock *BB) const {
21737 MachineFunction *MF = BB->getParent();
21738 const Constant *PerFn = MF->getFunction()->getPersonalityFn();
21739 bool IsSEH = isAsynchronousEHPersonality(classifyEHPersonality(PerFn));
21740 // Only 32-bit SEH requires special handling for catchpad.
21741 if (IsSEH && Subtarget->is32Bit()) {
21742 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21743 DebugLoc DL = MI->getDebugLoc();
21744 BuildMI(*BB, MI, DL, TII.get(X86::EH_RESTORE));
21746 MI->eraseFromParent();
21750 MachineBasicBlock *
21751 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
21752 MachineBasicBlock *BB) const {
21753 // This is pretty easy. We're taking the value that we received from
21754 // our load from the relocation, sticking it in either RDI (x86-64)
21755 // or EAX and doing an indirect call. The return value will then
21756 // be in the normal return register.
21757 MachineFunction *F = BB->getParent();
21758 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21759 DebugLoc DL = MI->getDebugLoc();
21761 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
21762 assert(MI->getOperand(3).isGlobal() && "This should be a global");
21764 // Get a register mask for the lowered call.
21765 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
21766 // proper register mask.
21767 const uint32_t *RegMask =
21768 Subtarget->is64Bit() ?
21769 Subtarget->getRegisterInfo()->getDarwinTLSCallPreservedMask() :
21770 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
21771 if (Subtarget->is64Bit()) {
21772 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21773 TII->get(X86::MOV64rm), X86::RDI)
21775 .addImm(0).addReg(0)
21776 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21777 MI->getOperand(3).getTargetFlags())
21779 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
21780 addDirectMem(MIB, X86::RDI);
21781 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
21782 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
21783 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21784 TII->get(X86::MOV32rm), X86::EAX)
21786 .addImm(0).addReg(0)
21787 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21788 MI->getOperand(3).getTargetFlags())
21790 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21791 addDirectMem(MIB, X86::EAX);
21792 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21794 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21795 TII->get(X86::MOV32rm), X86::EAX)
21796 .addReg(TII->getGlobalBaseReg(F))
21797 .addImm(0).addReg(0)
21798 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21799 MI->getOperand(3).getTargetFlags())
21801 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21802 addDirectMem(MIB, X86::EAX);
21803 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21806 MI->eraseFromParent(); // The pseudo instruction is gone now.
21810 MachineBasicBlock *
21811 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
21812 MachineBasicBlock *MBB) const {
21813 DebugLoc DL = MI->getDebugLoc();
21814 MachineFunction *MF = MBB->getParent();
21815 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21816 MachineRegisterInfo &MRI = MF->getRegInfo();
21818 const BasicBlock *BB = MBB->getBasicBlock();
21819 MachineFunction::iterator I = ++MBB->getIterator();
21821 // Memory Reference
21822 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21823 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21826 unsigned MemOpndSlot = 0;
21828 unsigned CurOp = 0;
21830 DstReg = MI->getOperand(CurOp++).getReg();
21831 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
21832 assert(RC->hasType(MVT::i32) && "Invalid destination!");
21833 unsigned mainDstReg = MRI.createVirtualRegister(RC);
21834 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
21836 MemOpndSlot = CurOp;
21838 MVT PVT = getPointerTy(MF->getDataLayout());
21839 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21840 "Invalid Pointer Size!");
21842 // For v = setjmp(buf), we generate
21845 // buf[LabelOffset] = restoreMBB <-- takes address of restoreMBB
21846 // SjLjSetup restoreMBB
21852 // v = phi(main, restore)
21855 // if base pointer being used, load it from frame
21858 MachineBasicBlock *thisMBB = MBB;
21859 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
21860 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
21861 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
21862 MF->insert(I, mainMBB);
21863 MF->insert(I, sinkMBB);
21864 MF->push_back(restoreMBB);
21865 restoreMBB->setHasAddressTaken();
21867 MachineInstrBuilder MIB;
21869 // Transfer the remainder of BB and its successor edges to sinkMBB.
21870 sinkMBB->splice(sinkMBB->begin(), MBB,
21871 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21872 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
21875 unsigned PtrStoreOpc = 0;
21876 unsigned LabelReg = 0;
21877 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21878 Reloc::Model RM = MF->getTarget().getRelocationModel();
21879 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
21880 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
21882 // Prepare IP either in reg or imm.
21883 if (!UseImmLabel) {
21884 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
21885 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
21886 LabelReg = MRI.createVirtualRegister(PtrRC);
21887 if (Subtarget->is64Bit()) {
21888 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
21892 .addMBB(restoreMBB)
21895 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
21896 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
21897 .addReg(XII->getGlobalBaseReg(MF))
21900 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
21904 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
21906 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
21907 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21908 if (i == X86::AddrDisp)
21909 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
21911 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
21914 MIB.addReg(LabelReg);
21916 MIB.addMBB(restoreMBB);
21917 MIB.setMemRefs(MMOBegin, MMOEnd);
21919 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21920 .addMBB(restoreMBB);
21922 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21923 MIB.addRegMask(RegInfo->getNoPreservedMask());
21924 thisMBB->addSuccessor(mainMBB);
21925 thisMBB->addSuccessor(restoreMBB);
21929 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21930 mainMBB->addSuccessor(sinkMBB);
21933 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21934 TII->get(X86::PHI), DstReg)
21935 .addReg(mainDstReg).addMBB(mainMBB)
21936 .addReg(restoreDstReg).addMBB(restoreMBB);
21939 if (RegInfo->hasBasePointer(*MF)) {
21940 const bool Uses64BitFramePtr =
21941 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
21942 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21943 X86FI->setRestoreBasePointer(MF);
21944 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21945 unsigned BasePtr = RegInfo->getBaseRegister();
21946 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21947 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21948 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21949 .setMIFlag(MachineInstr::FrameSetup);
21951 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21952 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
21953 restoreMBB->addSuccessor(sinkMBB);
21955 MI->eraseFromParent();
21959 MachineBasicBlock *
21960 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21961 MachineBasicBlock *MBB) const {
21962 DebugLoc DL = MI->getDebugLoc();
21963 MachineFunction *MF = MBB->getParent();
21964 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21965 MachineRegisterInfo &MRI = MF->getRegInfo();
21967 // Memory Reference
21968 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21969 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21971 MVT PVT = getPointerTy(MF->getDataLayout());
21972 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21973 "Invalid Pointer Size!");
21975 const TargetRegisterClass *RC =
21976 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21977 unsigned Tmp = MRI.createVirtualRegister(RC);
21978 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21979 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21980 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21981 unsigned SP = RegInfo->getStackRegister();
21983 MachineInstrBuilder MIB;
21985 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21986 const int64_t SPOffset = 2 * PVT.getStoreSize();
21988 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21989 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21992 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21993 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21994 MIB.addOperand(MI->getOperand(i));
21995 MIB.setMemRefs(MMOBegin, MMOEnd);
21997 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21998 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21999 if (i == X86::AddrDisp)
22000 MIB.addDisp(MI->getOperand(i), LabelOffset);
22002 MIB.addOperand(MI->getOperand(i));
22004 MIB.setMemRefs(MMOBegin, MMOEnd);
22006 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
22007 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
22008 if (i == X86::AddrDisp)
22009 MIB.addDisp(MI->getOperand(i), SPOffset);
22011 MIB.addOperand(MI->getOperand(i));
22013 MIB.setMemRefs(MMOBegin, MMOEnd);
22015 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
22017 MI->eraseFromParent();
22021 // Replace 213-type (isel default) FMA3 instructions with 231-type for
22022 // accumulator loops. Writing back to the accumulator allows the coalescer
22023 // to remove extra copies in the loop.
22024 // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
22025 MachineBasicBlock *
22026 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
22027 MachineBasicBlock *MBB) const {
22028 MachineOperand &AddendOp = MI->getOperand(3);
22030 // Bail out early if the addend isn't a register - we can't switch these.
22031 if (!AddendOp.isReg())
22034 MachineFunction &MF = *MBB->getParent();
22035 MachineRegisterInfo &MRI = MF.getRegInfo();
22037 // Check whether the addend is defined by a PHI:
22038 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
22039 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
22040 if (!AddendDef.isPHI())
22043 // Look for the following pattern:
22045 // %addend = phi [%entry, 0], [%loop, %result]
22047 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
22051 // %addend = phi [%entry, 0], [%loop, %result]
22053 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
22055 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
22056 assert(AddendDef.getOperand(i).isReg());
22057 MachineOperand PHISrcOp = AddendDef.getOperand(i);
22058 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
22059 if (&PHISrcInst == MI) {
22060 // Found a matching instruction.
22061 unsigned NewFMAOpc = 0;
22062 switch (MI->getOpcode()) {
22063 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
22064 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
22065 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
22066 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
22067 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
22068 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
22069 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
22070 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
22071 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
22072 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
22073 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
22074 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
22075 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
22076 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
22077 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
22078 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
22079 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
22080 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
22081 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
22082 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
22084 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
22085 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
22086 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
22087 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
22088 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
22089 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
22090 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
22091 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
22092 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
22093 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
22094 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
22095 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
22096 default: llvm_unreachable("Unrecognized FMA variant.");
22099 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
22100 MachineInstrBuilder MIB =
22101 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
22102 .addOperand(MI->getOperand(0))
22103 .addOperand(MI->getOperand(3))
22104 .addOperand(MI->getOperand(2))
22105 .addOperand(MI->getOperand(1));
22106 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
22107 MI->eraseFromParent();
22114 MachineBasicBlock *
22115 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
22116 MachineBasicBlock *BB) const {
22117 switch (MI->getOpcode()) {
22118 default: llvm_unreachable("Unexpected instr type to insert");
22119 case X86::TAILJMPd64:
22120 case X86::TAILJMPr64:
22121 case X86::TAILJMPm64:
22122 case X86::TAILJMPd64_REX:
22123 case X86::TAILJMPr64_REX:
22124 case X86::TAILJMPm64_REX:
22125 llvm_unreachable("TAILJMP64 would not be touched here.");
22126 case X86::TCRETURNdi64:
22127 case X86::TCRETURNri64:
22128 case X86::TCRETURNmi64:
22130 case X86::WIN_ALLOCA:
22131 return EmitLoweredWinAlloca(MI, BB);
22132 case X86::CATCHRET:
22133 return EmitLoweredCatchRet(MI, BB);
22134 case X86::CATCHPAD:
22135 return EmitLoweredCatchPad(MI, BB);
22136 case X86::SEG_ALLOCA_32:
22137 case X86::SEG_ALLOCA_64:
22138 return EmitLoweredSegAlloca(MI, BB);
22139 case X86::TLSCall_32:
22140 case X86::TLSCall_64:
22141 return EmitLoweredTLSCall(MI, BB);
22142 case X86::CMOV_FR32:
22143 case X86::CMOV_FR64:
22144 case X86::CMOV_GR8:
22145 case X86::CMOV_GR16:
22146 case X86::CMOV_GR32:
22147 case X86::CMOV_RFP32:
22148 case X86::CMOV_RFP64:
22149 case X86::CMOV_RFP80:
22150 case X86::CMOV_V2F64:
22151 case X86::CMOV_V2I64:
22152 case X86::CMOV_V4F32:
22153 case X86::CMOV_V4F64:
22154 case X86::CMOV_V4I64:
22155 case X86::CMOV_V16F32:
22156 case X86::CMOV_V8F32:
22157 case X86::CMOV_V8F64:
22158 case X86::CMOV_V8I64:
22159 case X86::CMOV_V8I1:
22160 case X86::CMOV_V16I1:
22161 case X86::CMOV_V32I1:
22162 case X86::CMOV_V64I1:
22163 return EmitLoweredSelect(MI, BB);
22165 case X86::RELEASE_FADD32mr:
22166 case X86::RELEASE_FADD64mr:
22167 return EmitLoweredAtomicFP(MI, BB);
22169 case X86::FP32_TO_INT16_IN_MEM:
22170 case X86::FP32_TO_INT32_IN_MEM:
22171 case X86::FP32_TO_INT64_IN_MEM:
22172 case X86::FP64_TO_INT16_IN_MEM:
22173 case X86::FP64_TO_INT32_IN_MEM:
22174 case X86::FP64_TO_INT64_IN_MEM:
22175 case X86::FP80_TO_INT16_IN_MEM:
22176 case X86::FP80_TO_INT32_IN_MEM:
22177 case X86::FP80_TO_INT64_IN_MEM: {
22178 MachineFunction *F = BB->getParent();
22179 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
22180 DebugLoc DL = MI->getDebugLoc();
22182 // Change the floating point control register to use "round towards zero"
22183 // mode when truncating to an integer value.
22184 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
22185 addFrameReference(BuildMI(*BB, MI, DL,
22186 TII->get(X86::FNSTCW16m)), CWFrameIdx);
22188 // Load the old value of the high byte of the control word...
22190 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
22191 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
22194 // Set the high part to be round to zero...
22195 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
22198 // Reload the modified control word now...
22199 addFrameReference(BuildMI(*BB, MI, DL,
22200 TII->get(X86::FLDCW16m)), CWFrameIdx);
22202 // Restore the memory image of control word to original value
22203 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
22206 // Get the X86 opcode to use.
22208 switch (MI->getOpcode()) {
22209 default: llvm_unreachable("illegal opcode!");
22210 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
22211 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
22212 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
22213 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
22214 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
22215 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
22216 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
22217 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
22218 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
22222 MachineOperand &Op = MI->getOperand(0);
22224 AM.BaseType = X86AddressMode::RegBase;
22225 AM.Base.Reg = Op.getReg();
22227 AM.BaseType = X86AddressMode::FrameIndexBase;
22228 AM.Base.FrameIndex = Op.getIndex();
22230 Op = MI->getOperand(1);
22232 AM.Scale = Op.getImm();
22233 Op = MI->getOperand(2);
22235 AM.IndexReg = Op.getImm();
22236 Op = MI->getOperand(3);
22237 if (Op.isGlobal()) {
22238 AM.GV = Op.getGlobal();
22240 AM.Disp = Op.getImm();
22242 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
22243 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
22245 // Reload the original control word now.
22246 addFrameReference(BuildMI(*BB, MI, DL,
22247 TII->get(X86::FLDCW16m)), CWFrameIdx);
22249 MI->eraseFromParent(); // The pseudo instruction is gone now.
22252 // String/text processing lowering.
22253 case X86::PCMPISTRM128REG:
22254 case X86::VPCMPISTRM128REG:
22255 case X86::PCMPISTRM128MEM:
22256 case X86::VPCMPISTRM128MEM:
22257 case X86::PCMPESTRM128REG:
22258 case X86::VPCMPESTRM128REG:
22259 case X86::PCMPESTRM128MEM:
22260 case X86::VPCMPESTRM128MEM:
22261 assert(Subtarget->hasSSE42() &&
22262 "Target must have SSE4.2 or AVX features enabled");
22263 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
22265 // String/text processing lowering.
22266 case X86::PCMPISTRIREG:
22267 case X86::VPCMPISTRIREG:
22268 case X86::PCMPISTRIMEM:
22269 case X86::VPCMPISTRIMEM:
22270 case X86::PCMPESTRIREG:
22271 case X86::VPCMPESTRIREG:
22272 case X86::PCMPESTRIMEM:
22273 case X86::VPCMPESTRIMEM:
22274 assert(Subtarget->hasSSE42() &&
22275 "Target must have SSE4.2 or AVX features enabled");
22276 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
22278 // Thread synchronization.
22280 return EmitMonitor(MI, BB, Subtarget);
22284 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
22286 case X86::VASTART_SAVE_XMM_REGS:
22287 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
22289 case X86::VAARG_64:
22290 return EmitVAARG64WithCustomInserter(MI, BB);
22292 case X86::EH_SjLj_SetJmp32:
22293 case X86::EH_SjLj_SetJmp64:
22294 return emitEHSjLjSetJmp(MI, BB);
22296 case X86::EH_SjLj_LongJmp32:
22297 case X86::EH_SjLj_LongJmp64:
22298 return emitEHSjLjLongJmp(MI, BB);
22300 case TargetOpcode::STATEPOINT:
22301 // As an implementation detail, STATEPOINT shares the STACKMAP format at
22302 // this point in the process. We diverge later.
22303 return emitPatchPoint(MI, BB);
22305 case TargetOpcode::STACKMAP:
22306 case TargetOpcode::PATCHPOINT:
22307 return emitPatchPoint(MI, BB);
22309 case X86::VFMADDPDr213r:
22310 case X86::VFMADDPSr213r:
22311 case X86::VFMADDSDr213r:
22312 case X86::VFMADDSSr213r:
22313 case X86::VFMSUBPDr213r:
22314 case X86::VFMSUBPSr213r:
22315 case X86::VFMSUBSDr213r:
22316 case X86::VFMSUBSSr213r:
22317 case X86::VFNMADDPDr213r:
22318 case X86::VFNMADDPSr213r:
22319 case X86::VFNMADDSDr213r:
22320 case X86::VFNMADDSSr213r:
22321 case X86::VFNMSUBPDr213r:
22322 case X86::VFNMSUBPSr213r:
22323 case X86::VFNMSUBSDr213r:
22324 case X86::VFNMSUBSSr213r:
22325 case X86::VFMADDSUBPDr213r:
22326 case X86::VFMADDSUBPSr213r:
22327 case X86::VFMSUBADDPDr213r:
22328 case X86::VFMSUBADDPSr213r:
22329 case X86::VFMADDPDr213rY:
22330 case X86::VFMADDPSr213rY:
22331 case X86::VFMSUBPDr213rY:
22332 case X86::VFMSUBPSr213rY:
22333 case X86::VFNMADDPDr213rY:
22334 case X86::VFNMADDPSr213rY:
22335 case X86::VFNMSUBPDr213rY:
22336 case X86::VFNMSUBPSr213rY:
22337 case X86::VFMADDSUBPDr213rY:
22338 case X86::VFMADDSUBPSr213rY:
22339 case X86::VFMSUBADDPDr213rY:
22340 case X86::VFMSUBADDPSr213rY:
22341 return emitFMA3Instr(MI, BB);
22345 //===----------------------------------------------------------------------===//
22346 // X86 Optimization Hooks
22347 //===----------------------------------------------------------------------===//
22349 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
22352 const SelectionDAG &DAG,
22353 unsigned Depth) const {
22354 unsigned BitWidth = KnownZero.getBitWidth();
22355 unsigned Opc = Op.getOpcode();
22356 assert((Opc >= ISD::BUILTIN_OP_END ||
22357 Opc == ISD::INTRINSIC_WO_CHAIN ||
22358 Opc == ISD::INTRINSIC_W_CHAIN ||
22359 Opc == ISD::INTRINSIC_VOID) &&
22360 "Should use MaskedValueIsZero if you don't know whether Op"
22361 " is a target node!");
22363 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
22377 // These nodes' second result is a boolean.
22378 if (Op.getResNo() == 0)
22381 case X86ISD::SETCC:
22382 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
22384 case ISD::INTRINSIC_WO_CHAIN: {
22385 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
22386 unsigned NumLoBits = 0;
22389 case Intrinsic::x86_sse_movmsk_ps:
22390 case Intrinsic::x86_avx_movmsk_ps_256:
22391 case Intrinsic::x86_sse2_movmsk_pd:
22392 case Intrinsic::x86_avx_movmsk_pd_256:
22393 case Intrinsic::x86_mmx_pmovmskb:
22394 case Intrinsic::x86_sse2_pmovmskb_128:
22395 case Intrinsic::x86_avx2_pmovmskb: {
22396 // High bits of movmskp{s|d}, pmovmskb are known zero.
22398 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
22399 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
22400 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
22401 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
22402 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
22403 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
22404 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
22405 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
22407 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
22416 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
22418 const SelectionDAG &,
22419 unsigned Depth) const {
22420 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
22421 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
22422 return Op.getValueType().getScalarSizeInBits();
22428 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
22429 /// node is a GlobalAddress + offset.
22430 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
22431 const GlobalValue* &GA,
22432 int64_t &Offset) const {
22433 if (N->getOpcode() == X86ISD::Wrapper) {
22434 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
22435 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
22436 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
22440 return TargetLowering::isGAPlusOffset(N, GA, Offset);
22443 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
22444 /// same as extracting the high 128-bit part of 256-bit vector and then
22445 /// inserting the result into the low part of a new 256-bit vector
22446 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
22447 EVT VT = SVOp->getValueType(0);
22448 unsigned NumElems = VT.getVectorNumElements();
22450 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
22451 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
22452 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
22453 SVOp->getMaskElt(j) >= 0)
22459 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
22460 /// same as extracting the low 128-bit part of 256-bit vector and then
22461 /// inserting the result into the high part of a new 256-bit vector
22462 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
22463 EVT VT = SVOp->getValueType(0);
22464 unsigned NumElems = VT.getVectorNumElements();
22466 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
22467 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
22468 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
22469 SVOp->getMaskElt(j) >= 0)
22475 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
22476 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
22477 TargetLowering::DAGCombinerInfo &DCI,
22478 const X86Subtarget* Subtarget) {
22480 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22481 SDValue V1 = SVOp->getOperand(0);
22482 SDValue V2 = SVOp->getOperand(1);
22483 MVT VT = SVOp->getSimpleValueType(0);
22484 unsigned NumElems = VT.getVectorNumElements();
22486 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
22487 V2.getOpcode() == ISD::CONCAT_VECTORS) {
22491 // V UNDEF BUILD_VECTOR UNDEF
22493 // CONCAT_VECTOR CONCAT_VECTOR
22496 // RESULT: V + zero extended
22498 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
22499 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
22500 V1.getOperand(1).getOpcode() != ISD::UNDEF)
22503 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
22506 // To match the shuffle mask, the first half of the mask should
22507 // be exactly the first vector, and all the rest a splat with the
22508 // first element of the second one.
22509 for (unsigned i = 0; i != NumElems/2; ++i)
22510 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
22511 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
22514 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
22515 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
22516 if (Ld->hasNUsesOfValue(1, 0)) {
22517 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
22518 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
22520 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
22522 Ld->getPointerInfo(),
22523 Ld->getAlignment(),
22524 false/*isVolatile*/, true/*ReadMem*/,
22525 false/*WriteMem*/);
22527 // Make sure the newly-created LOAD is in the same position as Ld in
22528 // terms of dependency. We create a TokenFactor for Ld and ResNode,
22529 // and update uses of Ld's output chain to use the TokenFactor.
22530 if (Ld->hasAnyUseOfValue(1)) {
22531 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22532 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
22533 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
22534 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
22535 SDValue(ResNode.getNode(), 1));
22538 return DAG.getBitcast(VT, ResNode);
22542 // Emit a zeroed vector and insert the desired subvector on its
22544 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
22545 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
22546 return DCI.CombineTo(N, InsV);
22549 //===--------------------------------------------------------------------===//
22550 // Combine some shuffles into subvector extracts and inserts:
22553 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
22554 if (isShuffleHigh128VectorInsertLow(SVOp)) {
22555 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
22556 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
22557 return DCI.CombineTo(N, InsV);
22560 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
22561 if (isShuffleLow128VectorInsertHigh(SVOp)) {
22562 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
22563 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
22564 return DCI.CombineTo(N, InsV);
22570 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
22573 /// This is the leaf of the recursive combinine below. When we have found some
22574 /// chain of single-use x86 shuffle instructions and accumulated the combined
22575 /// shuffle mask represented by them, this will try to pattern match that mask
22576 /// into either a single instruction if there is a special purpose instruction
22577 /// for this operation, or into a PSHUFB instruction which is a fully general
22578 /// instruction but should only be used to replace chains over a certain depth.
22579 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
22580 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
22581 TargetLowering::DAGCombinerInfo &DCI,
22582 const X86Subtarget *Subtarget) {
22583 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
22585 // Find the operand that enters the chain. Note that multiple uses are OK
22586 // here, we're not going to remove the operand we find.
22587 SDValue Input = Op.getOperand(0);
22588 while (Input.getOpcode() == ISD::BITCAST)
22589 Input = Input.getOperand(0);
22591 MVT VT = Input.getSimpleValueType();
22592 MVT RootVT = Root.getSimpleValueType();
22595 if (Mask.size() == 1) {
22596 int Index = Mask[0];
22597 assert((Index >= 0 || Index == SM_SentinelUndef ||
22598 Index == SM_SentinelZero) &&
22599 "Invalid shuffle index found!");
22601 // We may end up with an accumulated mask of size 1 as a result of
22602 // widening of shuffle operands (see function canWidenShuffleElements).
22603 // If the only shuffle index is equal to SM_SentinelZero then propagate
22604 // a zero vector. Otherwise, the combine shuffle mask is a no-op shuffle
22605 // mask, and therefore the entire chain of shuffles can be folded away.
22606 if (Index == SM_SentinelZero)
22607 DCI.CombineTo(Root.getNode(), getZeroVector(RootVT, Subtarget, DAG, DL));
22609 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
22614 // Use the float domain if the operand type is a floating point type.
22615 bool FloatDomain = VT.isFloatingPoint();
22617 // For floating point shuffles, we don't have free copies in the shuffle
22618 // instructions or the ability to load as part of the instruction, so
22619 // canonicalize their shuffles to UNPCK or MOV variants.
22621 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
22622 // vectors because it can have a load folded into it that UNPCK cannot. This
22623 // doesn't preclude something switching to the shorter encoding post-RA.
22625 // FIXME: Should teach these routines about AVX vector widths.
22626 if (FloatDomain && VT.is128BitVector()) {
22627 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
22628 bool Lo = Mask.equals({0, 0});
22631 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
22632 // is no slower than UNPCKLPD but has the option to fold the input operand
22633 // into even an unaligned memory load.
22634 if (Lo && Subtarget->hasSSE3()) {
22635 Shuffle = X86ISD::MOVDDUP;
22636 ShuffleVT = MVT::v2f64;
22638 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
22639 // than the UNPCK variants.
22640 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
22641 ShuffleVT = MVT::v4f32;
22643 if (Depth == 1 && Root->getOpcode() == Shuffle)
22644 return false; // Nothing to do!
22645 Op = DAG.getBitcast(ShuffleVT, Input);
22646 DCI.AddToWorklist(Op.getNode());
22647 if (Shuffle == X86ISD::MOVDDUP)
22648 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22650 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22651 DCI.AddToWorklist(Op.getNode());
22652 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22656 if (Subtarget->hasSSE3() &&
22657 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
22658 bool Lo = Mask.equals({0, 0, 2, 2});
22659 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
22660 MVT ShuffleVT = MVT::v4f32;
22661 if (Depth == 1 && Root->getOpcode() == Shuffle)
22662 return false; // Nothing to do!
22663 Op = DAG.getBitcast(ShuffleVT, Input);
22664 DCI.AddToWorklist(Op.getNode());
22665 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22666 DCI.AddToWorklist(Op.getNode());
22667 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22671 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
22672 bool Lo = Mask.equals({0, 0, 1, 1});
22673 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22674 MVT ShuffleVT = MVT::v4f32;
22675 if (Depth == 1 && Root->getOpcode() == Shuffle)
22676 return false; // Nothing to do!
22677 Op = DAG.getBitcast(ShuffleVT, Input);
22678 DCI.AddToWorklist(Op.getNode());
22679 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22680 DCI.AddToWorklist(Op.getNode());
22681 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22687 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
22688 // variants as none of these have single-instruction variants that are
22689 // superior to the UNPCK formulation.
22690 if (!FloatDomain && VT.is128BitVector() &&
22691 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22692 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
22693 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
22695 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
22696 bool Lo = Mask[0] == 0;
22697 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22698 if (Depth == 1 && Root->getOpcode() == Shuffle)
22699 return false; // Nothing to do!
22701 switch (Mask.size()) {
22703 ShuffleVT = MVT::v8i16;
22706 ShuffleVT = MVT::v16i8;
22709 llvm_unreachable("Impossible mask size!");
22711 Op = DAG.getBitcast(ShuffleVT, Input);
22712 DCI.AddToWorklist(Op.getNode());
22713 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22714 DCI.AddToWorklist(Op.getNode());
22715 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22720 // Don't try to re-form single instruction chains under any circumstances now
22721 // that we've done encoding canonicalization for them.
22725 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
22726 // can replace them with a single PSHUFB instruction profitably. Intel's
22727 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
22728 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
22729 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
22730 SmallVector<SDValue, 16> PSHUFBMask;
22731 int NumBytes = VT.getSizeInBits() / 8;
22732 int Ratio = NumBytes / Mask.size();
22733 for (int i = 0; i < NumBytes; ++i) {
22734 if (Mask[i / Ratio] == SM_SentinelUndef) {
22735 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
22738 int M = Mask[i / Ratio] != SM_SentinelZero
22739 ? Ratio * Mask[i / Ratio] + i % Ratio
22741 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
22743 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
22744 Op = DAG.getBitcast(ByteVT, Input);
22745 DCI.AddToWorklist(Op.getNode());
22746 SDValue PSHUFBMaskOp =
22747 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
22748 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
22749 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
22750 DCI.AddToWorklist(Op.getNode());
22751 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22756 // Failed to find any combines.
22760 /// \brief Fully generic combining of x86 shuffle instructions.
22762 /// This should be the last combine run over the x86 shuffle instructions. Once
22763 /// they have been fully optimized, this will recursively consider all chains
22764 /// of single-use shuffle instructions, build a generic model of the cumulative
22765 /// shuffle operation, and check for simpler instructions which implement this
22766 /// operation. We use this primarily for two purposes:
22768 /// 1) Collapse generic shuffles to specialized single instructions when
22769 /// equivalent. In most cases, this is just an encoding size win, but
22770 /// sometimes we will collapse multiple generic shuffles into a single
22771 /// special-purpose shuffle.
22772 /// 2) Look for sequences of shuffle instructions with 3 or more total
22773 /// instructions, and replace them with the slightly more expensive SSSE3
22774 /// PSHUFB instruction if available. We do this as the last combining step
22775 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
22776 /// a suitable short sequence of other instructions. The PHUFB will either
22777 /// use a register or have to read from memory and so is slightly (but only
22778 /// slightly) more expensive than the other shuffle instructions.
22780 /// Because this is inherently a quadratic operation (for each shuffle in
22781 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
22782 /// This should never be an issue in practice as the shuffle lowering doesn't
22783 /// produce sequences of more than 8 instructions.
22785 /// FIXME: We will currently miss some cases where the redundant shuffling
22786 /// would simplify under the threshold for PSHUFB formation because of
22787 /// combine-ordering. To fix this, we should do the redundant instruction
22788 /// combining in this recursive walk.
22789 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
22790 ArrayRef<int> RootMask,
22791 int Depth, bool HasPSHUFB,
22793 TargetLowering::DAGCombinerInfo &DCI,
22794 const X86Subtarget *Subtarget) {
22795 // Bound the depth of our recursive combine because this is ultimately
22796 // quadratic in nature.
22800 // Directly rip through bitcasts to find the underlying operand.
22801 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
22802 Op = Op.getOperand(0);
22804 MVT VT = Op.getSimpleValueType();
22805 if (!VT.isVector())
22806 return false; // Bail if we hit a non-vector.
22808 assert(Root.getSimpleValueType().isVector() &&
22809 "Shuffles operate on vector types!");
22810 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
22811 "Can only combine shuffles of the same vector register size.");
22813 if (!isTargetShuffle(Op.getOpcode()))
22815 SmallVector<int, 16> OpMask;
22817 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
22818 // We only can combine unary shuffles which we can decode the mask for.
22819 if (!HaveMask || !IsUnary)
22822 assert(VT.getVectorNumElements() == OpMask.size() &&
22823 "Different mask size from vector size!");
22824 assert(((RootMask.size() > OpMask.size() &&
22825 RootMask.size() % OpMask.size() == 0) ||
22826 (OpMask.size() > RootMask.size() &&
22827 OpMask.size() % RootMask.size() == 0) ||
22828 OpMask.size() == RootMask.size()) &&
22829 "The smaller number of elements must divide the larger.");
22830 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
22831 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
22832 assert(((RootRatio == 1 && OpRatio == 1) ||
22833 (RootRatio == 1) != (OpRatio == 1)) &&
22834 "Must not have a ratio for both incoming and op masks!");
22836 SmallVector<int, 16> Mask;
22837 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
22839 // Merge this shuffle operation's mask into our accumulated mask. Note that
22840 // this shuffle's mask will be the first applied to the input, followed by the
22841 // root mask to get us all the way to the root value arrangement. The reason
22842 // for this order is that we are recursing up the operation chain.
22843 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
22844 int RootIdx = i / RootRatio;
22845 if (RootMask[RootIdx] < 0) {
22846 // This is a zero or undef lane, we're done.
22847 Mask.push_back(RootMask[RootIdx]);
22851 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
22852 int OpIdx = RootMaskedIdx / OpRatio;
22853 if (OpMask[OpIdx] < 0) {
22854 // The incoming lanes are zero or undef, it doesn't matter which ones we
22856 Mask.push_back(OpMask[OpIdx]);
22860 // Ok, we have non-zero lanes, map them through.
22861 Mask.push_back(OpMask[OpIdx] * OpRatio +
22862 RootMaskedIdx % OpRatio);
22865 // See if we can recurse into the operand to combine more things.
22866 switch (Op.getOpcode()) {
22867 case X86ISD::PSHUFB:
22869 case X86ISD::PSHUFD:
22870 case X86ISD::PSHUFHW:
22871 case X86ISD::PSHUFLW:
22872 if (Op.getOperand(0).hasOneUse() &&
22873 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22874 HasPSHUFB, DAG, DCI, Subtarget))
22878 case X86ISD::UNPCKL:
22879 case X86ISD::UNPCKH:
22880 assert(Op.getOperand(0) == Op.getOperand(1) &&
22881 "We only combine unary shuffles!");
22882 // We can't check for single use, we have to check that this shuffle is the
22884 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
22885 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22886 HasPSHUFB, DAG, DCI, Subtarget))
22891 // Minor canonicalization of the accumulated shuffle mask to make it easier
22892 // to match below. All this does is detect masks with squential pairs of
22893 // elements, and shrink them to the half-width mask. It does this in a loop
22894 // so it will reduce the size of the mask to the minimal width mask which
22895 // performs an equivalent shuffle.
22896 SmallVector<int, 16> WidenedMask;
22897 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
22898 Mask = std::move(WidenedMask);
22899 WidenedMask.clear();
22902 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
22906 /// \brief Get the PSHUF-style mask from PSHUF node.
22908 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
22909 /// PSHUF-style masks that can be reused with such instructions.
22910 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
22911 MVT VT = N.getSimpleValueType();
22912 SmallVector<int, 4> Mask;
22914 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
22918 // If we have more than 128-bits, only the low 128-bits of shuffle mask
22919 // matter. Check that the upper masks are repeats and remove them.
22920 if (VT.getSizeInBits() > 128) {
22921 int LaneElts = 128 / VT.getScalarSizeInBits();
22923 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
22924 for (int j = 0; j < LaneElts; ++j)
22925 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
22926 "Mask doesn't repeat in high 128-bit lanes!");
22928 Mask.resize(LaneElts);
22931 switch (N.getOpcode()) {
22932 case X86ISD::PSHUFD:
22934 case X86ISD::PSHUFLW:
22937 case X86ISD::PSHUFHW:
22938 Mask.erase(Mask.begin(), Mask.begin() + 4);
22939 for (int &M : Mask)
22943 llvm_unreachable("No valid shuffle instruction found!");
22947 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
22949 /// We walk up the chain and look for a combinable shuffle, skipping over
22950 /// shuffles that we could hoist this shuffle's transformation past without
22951 /// altering anything.
22953 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22955 TargetLowering::DAGCombinerInfo &DCI) {
22956 assert(N.getOpcode() == X86ISD::PSHUFD &&
22957 "Called with something other than an x86 128-bit half shuffle!");
22960 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22961 // of the shuffles in the chain so that we can form a fresh chain to replace
22963 SmallVector<SDValue, 8> Chain;
22964 SDValue V = N.getOperand(0);
22965 for (; V.hasOneUse(); V = V.getOperand(0)) {
22966 switch (V.getOpcode()) {
22968 return SDValue(); // Nothing combined!
22971 // Skip bitcasts as we always know the type for the target specific
22975 case X86ISD::PSHUFD:
22976 // Found another dword shuffle.
22979 case X86ISD::PSHUFLW:
22980 // Check that the low words (being shuffled) are the identity in the
22981 // dword shuffle, and the high words are self-contained.
22982 if (Mask[0] != 0 || Mask[1] != 1 ||
22983 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22986 Chain.push_back(V);
22989 case X86ISD::PSHUFHW:
22990 // Check that the high words (being shuffled) are the identity in the
22991 // dword shuffle, and the low words are self-contained.
22992 if (Mask[2] != 2 || Mask[3] != 3 ||
22993 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22996 Chain.push_back(V);
22999 case X86ISD::UNPCKL:
23000 case X86ISD::UNPCKH:
23001 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
23002 // shuffle into a preceding word shuffle.
23003 if (V.getSimpleValueType().getVectorElementType() != MVT::i8 &&
23004 V.getSimpleValueType().getVectorElementType() != MVT::i16)
23007 // Search for a half-shuffle which we can combine with.
23008 unsigned CombineOp =
23009 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
23010 if (V.getOperand(0) != V.getOperand(1) ||
23011 !V->isOnlyUserOf(V.getOperand(0).getNode()))
23013 Chain.push_back(V);
23014 V = V.getOperand(0);
23016 switch (V.getOpcode()) {
23018 return SDValue(); // Nothing to combine.
23020 case X86ISD::PSHUFLW:
23021 case X86ISD::PSHUFHW:
23022 if (V.getOpcode() == CombineOp)
23025 Chain.push_back(V);
23029 V = V.getOperand(0);
23033 } while (V.hasOneUse());
23036 // Break out of the loop if we break out of the switch.
23040 if (!V.hasOneUse())
23041 // We fell out of the loop without finding a viable combining instruction.
23044 // Merge this node's mask and our incoming mask.
23045 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
23046 for (int &M : Mask)
23048 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
23049 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
23051 // Rebuild the chain around this new shuffle.
23052 while (!Chain.empty()) {
23053 SDValue W = Chain.pop_back_val();
23055 if (V.getValueType() != W.getOperand(0).getValueType())
23056 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
23058 switch (W.getOpcode()) {
23060 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
23062 case X86ISD::UNPCKL:
23063 case X86ISD::UNPCKH:
23064 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
23067 case X86ISD::PSHUFD:
23068 case X86ISD::PSHUFLW:
23069 case X86ISD::PSHUFHW:
23070 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
23074 if (V.getValueType() != N.getValueType())
23075 V = DAG.getBitcast(N.getValueType(), V);
23077 // Return the new chain to replace N.
23081 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or
23084 /// We walk up the chain, skipping shuffles of the other half and looking
23085 /// through shuffles which switch halves trying to find a shuffle of the same
23086 /// pair of dwords.
23087 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
23089 TargetLowering::DAGCombinerInfo &DCI) {
23091 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
23092 "Called with something other than an x86 128-bit half shuffle!");
23094 unsigned CombineOpcode = N.getOpcode();
23096 // Walk up a single-use chain looking for a combinable shuffle.
23097 SDValue V = N.getOperand(0);
23098 for (; V.hasOneUse(); V = V.getOperand(0)) {
23099 switch (V.getOpcode()) {
23101 return false; // Nothing combined!
23104 // Skip bitcasts as we always know the type for the target specific
23108 case X86ISD::PSHUFLW:
23109 case X86ISD::PSHUFHW:
23110 if (V.getOpcode() == CombineOpcode)
23113 // Other-half shuffles are no-ops.
23116 // Break out of the loop if we break out of the switch.
23120 if (!V.hasOneUse())
23121 // We fell out of the loop without finding a viable combining instruction.
23124 // Combine away the bottom node as its shuffle will be accumulated into
23125 // a preceding shuffle.
23126 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
23128 // Record the old value.
23131 // Merge this node's mask and our incoming mask (adjusted to account for all
23132 // the pshufd instructions encountered).
23133 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
23134 for (int &M : Mask)
23136 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
23137 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
23139 // Check that the shuffles didn't cancel each other out. If not, we need to
23140 // combine to the new one.
23142 // Replace the combinable shuffle with the combined one, updating all users
23143 // so that we re-evaluate the chain here.
23144 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
23149 /// \brief Try to combine x86 target specific shuffles.
23150 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
23151 TargetLowering::DAGCombinerInfo &DCI,
23152 const X86Subtarget *Subtarget) {
23154 MVT VT = N.getSimpleValueType();
23155 SmallVector<int, 4> Mask;
23157 switch (N.getOpcode()) {
23158 case X86ISD::PSHUFD:
23159 case X86ISD::PSHUFLW:
23160 case X86ISD::PSHUFHW:
23161 Mask = getPSHUFShuffleMask(N);
23162 assert(Mask.size() == 4);
23164 case X86ISD::UNPCKL: {
23165 // Combine X86ISD::UNPCKL and ISD::VECTOR_SHUFFLE into X86ISD::UNPCKH, in
23166 // which X86ISD::UNPCKL has a ISD::UNDEF operand, and ISD::VECTOR_SHUFFLE
23167 // moves upper half elements into the lower half part. For example:
23169 // t2: v16i8 = vector_shuffle<8,9,10,11,12,13,14,15,u,u,u,u,u,u,u,u> t1,
23171 // t3: v16i8 = X86ISD::UNPCKL undef:v16i8, t2
23173 // will be combined to:
23175 // t3: v16i8 = X86ISD::UNPCKH undef:v16i8, t1
23177 // This is only for 128-bit vectors. From SSE4.1 onward this combine may not
23178 // happen due to advanced instructions.
23179 if (!VT.is128BitVector())
23182 auto Op0 = N.getOperand(0);
23183 auto Op1 = N.getOperand(1);
23184 if (Op0.getOpcode() == ISD::UNDEF &&
23185 Op1.getNode()->getOpcode() == ISD::VECTOR_SHUFFLE) {
23186 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op1.getNode())->getMask();
23188 unsigned NumElts = VT.getVectorNumElements();
23189 SmallVector<int, 8> ExpectedMask(NumElts, -1);
23190 std::iota(ExpectedMask.begin(), ExpectedMask.begin() + NumElts / 2,
23193 auto ShufOp = Op1.getOperand(0);
23194 if (isShuffleEquivalent(Op1, ShufOp, Mask, ExpectedMask))
23195 return DAG.getNode(X86ISD::UNPCKH, DL, VT, N.getOperand(0), ShufOp);
23203 // Nuke no-op shuffles that show up after combining.
23204 if (isNoopShuffleMask(Mask))
23205 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
23207 // Look for simplifications involving one or two shuffle instructions.
23208 SDValue V = N.getOperand(0);
23209 switch (N.getOpcode()) {
23212 case X86ISD::PSHUFLW:
23213 case X86ISD::PSHUFHW:
23214 assert(VT.getVectorElementType() == MVT::i16 && "Bad word shuffle type!");
23216 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
23217 return SDValue(); // We combined away this shuffle, so we're done.
23219 // See if this reduces to a PSHUFD which is no more expensive and can
23220 // combine with more operations. Note that it has to at least flip the
23221 // dwords as otherwise it would have been removed as a no-op.
23222 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
23223 int DMask[] = {0, 1, 2, 3};
23224 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
23225 DMask[DOffset + 0] = DOffset + 1;
23226 DMask[DOffset + 1] = DOffset + 0;
23227 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
23228 V = DAG.getBitcast(DVT, V);
23229 DCI.AddToWorklist(V.getNode());
23230 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
23231 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
23232 DCI.AddToWorklist(V.getNode());
23233 return DAG.getBitcast(VT, V);
23236 // Look for shuffle patterns which can be implemented as a single unpack.
23237 // FIXME: This doesn't handle the location of the PSHUFD generically, and
23238 // only works when we have a PSHUFD followed by two half-shuffles.
23239 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
23240 (V.getOpcode() == X86ISD::PSHUFLW ||
23241 V.getOpcode() == X86ISD::PSHUFHW) &&
23242 V.getOpcode() != N.getOpcode() &&
23244 SDValue D = V.getOperand(0);
23245 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
23246 D = D.getOperand(0);
23247 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
23248 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
23249 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
23250 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
23251 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
23253 for (int i = 0; i < 4; ++i) {
23254 WordMask[i + NOffset] = Mask[i] + NOffset;
23255 WordMask[i + VOffset] = VMask[i] + VOffset;
23257 // Map the word mask through the DWord mask.
23259 for (int i = 0; i < 8; ++i)
23260 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
23261 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
23262 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
23263 // We can replace all three shuffles with an unpack.
23264 V = DAG.getBitcast(VT, D.getOperand(0));
23265 DCI.AddToWorklist(V.getNode());
23266 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
23275 case X86ISD::PSHUFD:
23276 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
23285 /// \brief Try to combine a shuffle into a target-specific add-sub node.
23287 /// We combine this directly on the abstract vector shuffle nodes so it is
23288 /// easier to generically match. We also insert dummy vector shuffle nodes for
23289 /// the operands which explicitly discard the lanes which are unused by this
23290 /// operation to try to flow through the rest of the combiner the fact that
23291 /// they're unused.
23292 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
23294 EVT VT = N->getValueType(0);
23296 // We only handle target-independent shuffles.
23297 // FIXME: It would be easy and harmless to use the target shuffle mask
23298 // extraction tool to support more.
23299 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
23302 auto *SVN = cast<ShuffleVectorSDNode>(N);
23303 SmallVector<int, 8> Mask;
23304 for (int M : SVN->getMask())
23307 SDValue V1 = N->getOperand(0);
23308 SDValue V2 = N->getOperand(1);
23310 // We require the first shuffle operand to be the FSUB node, and the second to
23311 // be the FADD node.
23312 if (V1.getOpcode() == ISD::FADD && V2.getOpcode() == ISD::FSUB) {
23313 ShuffleVectorSDNode::commuteMask(Mask);
23315 } else if (V1.getOpcode() != ISD::FSUB || V2.getOpcode() != ISD::FADD)
23318 // If there are other uses of these operations we can't fold them.
23319 if (!V1->hasOneUse() || !V2->hasOneUse())
23322 // Ensure that both operations have the same operands. Note that we can
23323 // commute the FADD operands.
23324 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
23325 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
23326 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
23329 // We're looking for blends between FADD and FSUB nodes. We insist on these
23330 // nodes being lined up in a specific expected pattern.
23331 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
23332 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
23333 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
23336 // Only specific types are legal at this point, assert so we notice if and
23337 // when these change.
23338 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
23339 VT == MVT::v4f64) &&
23340 "Unknown vector type encountered!");
23342 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
23345 /// PerformShuffleCombine - Performs several different shuffle combines.
23346 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
23347 TargetLowering::DAGCombinerInfo &DCI,
23348 const X86Subtarget *Subtarget) {
23350 SDValue N0 = N->getOperand(0);
23351 SDValue N1 = N->getOperand(1);
23352 EVT VT = N->getValueType(0);
23354 // Don't create instructions with illegal types after legalize types has run.
23355 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23356 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
23359 // If we have legalized the vector types, look for blends of FADD and FSUB
23360 // nodes that we can fuse into an ADDSUB node.
23361 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
23362 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
23365 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
23366 if (TLI.isTypeLegal(VT) && Subtarget->hasFp256() && VT.is256BitVector() &&
23367 N->getOpcode() == ISD::VECTOR_SHUFFLE)
23368 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
23370 // During Type Legalization, when promoting illegal vector types,
23371 // the backend might introduce new shuffle dag nodes and bitcasts.
23373 // This code performs the following transformation:
23374 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
23375 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
23377 // We do this only if both the bitcast and the BINOP dag nodes have
23378 // one use. Also, perform this transformation only if the new binary
23379 // operation is legal. This is to avoid introducing dag nodes that
23380 // potentially need to be further expanded (or custom lowered) into a
23381 // less optimal sequence of dag nodes.
23382 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
23383 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
23384 N0.getOpcode() == ISD::BITCAST) {
23385 SDValue BC0 = N0.getOperand(0);
23386 EVT SVT = BC0.getValueType();
23387 unsigned Opcode = BC0.getOpcode();
23388 unsigned NumElts = VT.getVectorNumElements();
23390 if (BC0.hasOneUse() && SVT.isVector() &&
23391 SVT.getVectorNumElements() * 2 == NumElts &&
23392 TLI.isOperationLegal(Opcode, VT)) {
23393 bool CanFold = false;
23405 unsigned SVTNumElts = SVT.getVectorNumElements();
23406 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
23407 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
23408 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
23409 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
23410 CanFold = SVOp->getMaskElt(i) < 0;
23413 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
23414 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
23415 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
23416 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
23421 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
23422 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
23423 // consecutive, non-overlapping, and in the right order.
23424 SmallVector<SDValue, 16> Elts;
23425 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
23426 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
23428 if (SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true))
23431 if (isTargetShuffle(N->getOpcode())) {
23433 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
23434 if (Shuffle.getNode())
23437 // Try recursively combining arbitrary sequences of x86 shuffle
23438 // instructions into higher-order shuffles. We do this after combining
23439 // specific PSHUF instruction sequences into their minimal form so that we
23440 // can evaluate how many specialized shuffle instructions are involved in
23441 // a particular chain.
23442 SmallVector<int, 1> NonceMask; // Just a placeholder.
23443 NonceMask.push_back(0);
23444 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
23445 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
23447 return SDValue(); // This routine will use CombineTo to replace N.
23453 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
23454 /// specific shuffle of a load can be folded into a single element load.
23455 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
23456 /// shuffles have been custom lowered so we need to handle those here.
23457 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
23458 TargetLowering::DAGCombinerInfo &DCI) {
23459 if (DCI.isBeforeLegalizeOps())
23462 SDValue InVec = N->getOperand(0);
23463 SDValue EltNo = N->getOperand(1);
23465 if (!isa<ConstantSDNode>(EltNo))
23468 EVT OriginalVT = InVec.getValueType();
23470 if (InVec.getOpcode() == ISD::BITCAST) {
23471 // Don't duplicate a load with other uses.
23472 if (!InVec.hasOneUse())
23474 EVT BCVT = InVec.getOperand(0).getValueType();
23475 if (!BCVT.isVector() ||
23476 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
23478 InVec = InVec.getOperand(0);
23481 EVT CurrentVT = InVec.getValueType();
23483 if (!isTargetShuffle(InVec.getOpcode()))
23486 // Don't duplicate a load with other uses.
23487 if (!InVec.hasOneUse())
23490 SmallVector<int, 16> ShuffleMask;
23492 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
23493 ShuffleMask, UnaryShuffle))
23496 // Select the input vector, guarding against out of range extract vector.
23497 unsigned NumElems = CurrentVT.getVectorNumElements();
23498 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
23499 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
23500 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
23501 : InVec.getOperand(1);
23503 // If inputs to shuffle are the same for both ops, then allow 2 uses
23504 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
23505 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
23507 if (LdNode.getOpcode() == ISD::BITCAST) {
23508 // Don't duplicate a load with other uses.
23509 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
23512 AllowedUses = 1; // only allow 1 load use if we have a bitcast
23513 LdNode = LdNode.getOperand(0);
23516 if (!ISD::isNormalLoad(LdNode.getNode()))
23519 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
23521 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
23524 EVT EltVT = N->getValueType(0);
23525 // If there's a bitcast before the shuffle, check if the load type and
23526 // alignment is valid.
23527 unsigned Align = LN0->getAlignment();
23528 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23529 unsigned NewAlign = DAG.getDataLayout().getABITypeAlignment(
23530 EltVT.getTypeForEVT(*DAG.getContext()));
23532 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
23535 // All checks match so transform back to vector_shuffle so that DAG combiner
23536 // can finish the job
23539 // Create shuffle node taking into account the case that its a unary shuffle
23540 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
23541 : InVec.getOperand(1);
23542 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
23543 InVec.getOperand(0), Shuffle,
23545 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
23546 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
23550 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG,
23551 const X86Subtarget *Subtarget) {
23552 SDValue N0 = N->getOperand(0);
23553 EVT VT = N->getValueType(0);
23555 // Detect bitcasts between i32 to x86mmx low word. Since MMX types are
23556 // special and don't usually play with other vector types, it's better to
23557 // handle them early to be sure we emit efficient code by avoiding
23558 // store-load conversions.
23559 if (VT == MVT::x86mmx && N0.getOpcode() == ISD::BUILD_VECTOR &&
23560 N0.getValueType() == MVT::v2i32 &&
23561 isNullConstant(N0.getOperand(1))) {
23562 SDValue N00 = N0->getOperand(0);
23563 if (N00.getValueType() == MVT::i32)
23564 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(N00), VT, N00);
23567 // Convert a bitcasted integer logic operation that has one bitcasted
23568 // floating-point operand and one constant operand into a floating-point
23569 // logic operation. This may create a load of the constant, but that is
23570 // cheaper than materializing the constant in an integer register and
23571 // transferring it to an SSE register or transferring the SSE operand to
23572 // integer register and back.
23574 switch (N0.getOpcode()) {
23575 case ISD::AND: FPOpcode = X86ISD::FAND; break;
23576 case ISD::OR: FPOpcode = X86ISD::FOR; break;
23577 case ISD::XOR: FPOpcode = X86ISD::FXOR; break;
23578 default: return SDValue();
23580 if (((Subtarget->hasSSE1() && VT == MVT::f32) ||
23581 (Subtarget->hasSSE2() && VT == MVT::f64)) &&
23582 isa<ConstantSDNode>(N0.getOperand(1)) &&
23583 N0.getOperand(0).getOpcode() == ISD::BITCAST &&
23584 N0.getOperand(0).getOperand(0).getValueType() == VT) {
23585 SDValue N000 = N0.getOperand(0).getOperand(0);
23586 SDValue FPConst = DAG.getBitcast(VT, N0.getOperand(1));
23587 return DAG.getNode(FPOpcode, SDLoc(N0), VT, N000, FPConst);
23593 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
23594 /// generation and convert it from being a bunch of shuffles and extracts
23595 /// into a somewhat faster sequence. For i686, the best sequence is apparently
23596 /// storing the value and loading scalars back, while for x64 we should
23597 /// use 64-bit extracts and shifts.
23598 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
23599 TargetLowering::DAGCombinerInfo &DCI) {
23600 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
23603 SDValue InputVector = N->getOperand(0);
23604 SDLoc dl(InputVector);
23605 // Detect mmx to i32 conversion through a v2i32 elt extract.
23606 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
23607 N->getValueType(0) == MVT::i32 &&
23608 InputVector.getValueType() == MVT::v2i32) {
23610 // The bitcast source is a direct mmx result.
23611 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
23612 if (MMXSrc.getValueType() == MVT::x86mmx)
23613 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23614 N->getValueType(0),
23615 InputVector.getNode()->getOperand(0));
23617 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
23618 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
23619 MMXSrc.getValueType() == MVT::i64) {
23620 SDValue MMXSrcOp = MMXSrc.getOperand(0);
23621 if (MMXSrcOp.hasOneUse() && MMXSrcOp.getOpcode() == ISD::BITCAST &&
23622 MMXSrcOp.getValueType() == MVT::v1i64 &&
23623 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
23624 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23625 N->getValueType(0), MMXSrcOp.getOperand(0));
23629 EVT VT = N->getValueType(0);
23631 if (VT == MVT::i1 && isa<ConstantSDNode>(N->getOperand(1)) &&
23632 InputVector.getOpcode() == ISD::BITCAST &&
23633 isa<ConstantSDNode>(InputVector.getOperand(0))) {
23634 uint64_t ExtractedElt =
23635 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
23636 uint64_t InputValue =
23637 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
23638 uint64_t Res = (InputValue >> ExtractedElt) & 1;
23639 return DAG.getConstant(Res, dl, MVT::i1);
23641 // Only operate on vectors of 4 elements, where the alternative shuffling
23642 // gets to be more expensive.
23643 if (InputVector.getValueType() != MVT::v4i32)
23646 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
23647 // single use which is a sign-extend or zero-extend, and all elements are
23649 SmallVector<SDNode *, 4> Uses;
23650 unsigned ExtractedElements = 0;
23651 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
23652 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
23653 if (UI.getUse().getResNo() != InputVector.getResNo())
23656 SDNode *Extract = *UI;
23657 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
23660 if (Extract->getValueType(0) != MVT::i32)
23662 if (!Extract->hasOneUse())
23664 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
23665 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
23667 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
23670 // Record which element was extracted.
23671 ExtractedElements |=
23672 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
23674 Uses.push_back(Extract);
23677 // If not all the elements were used, this may not be worthwhile.
23678 if (ExtractedElements != 15)
23681 // Ok, we've now decided to do the transformation.
23682 // If 64-bit shifts are legal, use the extract-shift sequence,
23683 // otherwise bounce the vector off the cache.
23684 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23687 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
23688 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
23689 auto &DL = DAG.getDataLayout();
23690 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy(DL);
23691 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23692 DAG.getConstant(0, dl, VecIdxTy));
23693 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23694 DAG.getConstant(1, dl, VecIdxTy));
23696 SDValue ShAmt = DAG.getConstant(
23697 32, dl, DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64, DL));
23698 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
23699 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23700 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
23701 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
23702 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23703 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
23705 // Store the value to a temporary stack slot.
23706 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
23707 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
23708 MachinePointerInfo(), false, false, 0);
23710 EVT ElementType = InputVector.getValueType().getVectorElementType();
23711 unsigned EltSize = ElementType.getSizeInBits() / 8;
23713 // Replace each use (extract) with a load of the appropriate element.
23714 for (unsigned i = 0; i < 4; ++i) {
23715 uint64_t Offset = EltSize * i;
23716 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
23717 SDValue OffsetVal = DAG.getConstant(Offset, dl, PtrVT);
23719 SDValue ScalarAddr =
23720 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, OffsetVal);
23722 // Load the scalar.
23723 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
23724 ScalarAddr, MachinePointerInfo(),
23725 false, false, false, 0);
23730 // Replace the extracts
23731 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
23732 UE = Uses.end(); UI != UE; ++UI) {
23733 SDNode *Extract = *UI;
23735 SDValue Idx = Extract->getOperand(1);
23736 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
23737 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
23740 // The replacement was made in place; don't return anything.
23745 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
23746 const X86Subtarget *Subtarget) {
23748 SDValue Cond = N->getOperand(0);
23749 SDValue LHS = N->getOperand(1);
23750 SDValue RHS = N->getOperand(2);
23752 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
23753 SDValue CondSrc = Cond->getOperand(0);
23754 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
23755 Cond = CondSrc->getOperand(0);
23758 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
23761 // A vselect where all conditions and data are constants can be optimized into
23762 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
23763 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
23764 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
23767 unsigned MaskValue = 0;
23768 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
23771 MVT VT = N->getSimpleValueType(0);
23772 unsigned NumElems = VT.getVectorNumElements();
23773 SmallVector<int, 8> ShuffleMask(NumElems, -1);
23774 for (unsigned i = 0; i < NumElems; ++i) {
23775 // Be sure we emit undef where we can.
23776 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
23777 ShuffleMask[i] = -1;
23779 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
23782 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23783 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
23785 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
23788 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
23790 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
23791 TargetLowering::DAGCombinerInfo &DCI,
23792 const X86Subtarget *Subtarget) {
23794 SDValue Cond = N->getOperand(0);
23795 // Get the LHS/RHS of the select.
23796 SDValue LHS = N->getOperand(1);
23797 SDValue RHS = N->getOperand(2);
23798 EVT VT = LHS.getValueType();
23799 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23801 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
23802 // instructions match the semantics of the common C idiom x<y?x:y but not
23803 // x<=y?x:y, because of how they handle negative zero (which can be
23804 // ignored in unsafe-math mode).
23805 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
23806 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
23807 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
23808 (Subtarget->hasSSE2() ||
23809 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
23810 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23812 unsigned Opcode = 0;
23813 // Check for x CC y ? x : y.
23814 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23815 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23819 // Converting this to a min would handle NaNs incorrectly, and swapping
23820 // the operands would cause it to handle comparisons between positive
23821 // and negative zero incorrectly.
23822 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23823 if (!DAG.getTarget().Options.UnsafeFPMath &&
23824 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23826 std::swap(LHS, RHS);
23828 Opcode = X86ISD::FMIN;
23831 // Converting this to a min would handle comparisons between positive
23832 // and negative zero incorrectly.
23833 if (!DAG.getTarget().Options.UnsafeFPMath &&
23834 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23836 Opcode = X86ISD::FMIN;
23839 // Converting this to a min would handle both negative zeros and NaNs
23840 // incorrectly, but we can swap the operands to fix both.
23841 std::swap(LHS, RHS);
23845 Opcode = X86ISD::FMIN;
23849 // Converting this to a max would handle comparisons between positive
23850 // and negative zero incorrectly.
23851 if (!DAG.getTarget().Options.UnsafeFPMath &&
23852 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23854 Opcode = X86ISD::FMAX;
23857 // Converting this to a max would handle NaNs incorrectly, and swapping
23858 // the operands would cause it to handle comparisons between positive
23859 // and negative zero incorrectly.
23860 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23861 if (!DAG.getTarget().Options.UnsafeFPMath &&
23862 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23864 std::swap(LHS, RHS);
23866 Opcode = X86ISD::FMAX;
23869 // Converting this to a max would handle both negative zeros and NaNs
23870 // incorrectly, but we can swap the operands to fix both.
23871 std::swap(LHS, RHS);
23875 Opcode = X86ISD::FMAX;
23878 // Check for x CC y ? y : x -- a min/max with reversed arms.
23879 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
23880 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
23884 // Converting this to a min would handle comparisons between positive
23885 // and negative zero incorrectly, and swapping the operands would
23886 // cause it to handle NaNs incorrectly.
23887 if (!DAG.getTarget().Options.UnsafeFPMath &&
23888 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
23889 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23891 std::swap(LHS, RHS);
23893 Opcode = X86ISD::FMIN;
23896 // Converting this to a min would handle NaNs incorrectly.
23897 if (!DAG.getTarget().Options.UnsafeFPMath &&
23898 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
23900 Opcode = X86ISD::FMIN;
23903 // Converting this to a min would handle both negative zeros and NaNs
23904 // incorrectly, but we can swap the operands to fix both.
23905 std::swap(LHS, RHS);
23909 Opcode = X86ISD::FMIN;
23913 // Converting this to a max would handle NaNs incorrectly.
23914 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23916 Opcode = X86ISD::FMAX;
23919 // Converting this to a max would handle comparisons between positive
23920 // and negative zero incorrectly, and swapping the operands would
23921 // cause it to handle NaNs incorrectly.
23922 if (!DAG.getTarget().Options.UnsafeFPMath &&
23923 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
23924 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23926 std::swap(LHS, RHS);
23928 Opcode = X86ISD::FMAX;
23931 // Converting this to a max would handle both negative zeros and NaNs
23932 // incorrectly, but we can swap the operands to fix both.
23933 std::swap(LHS, RHS);
23937 Opcode = X86ISD::FMAX;
23943 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
23946 EVT CondVT = Cond.getValueType();
23947 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
23948 CondVT.getVectorElementType() == MVT::i1) {
23949 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
23950 // lowering on KNL. In this case we convert it to
23951 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
23952 // The same situation for all 128 and 256-bit vectors of i8 and i16.
23953 // Since SKX these selects have a proper lowering.
23954 EVT OpVT = LHS.getValueType();
23955 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
23956 (OpVT.getVectorElementType() == MVT::i8 ||
23957 OpVT.getVectorElementType() == MVT::i16) &&
23958 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
23959 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
23960 DCI.AddToWorklist(Cond.getNode());
23961 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
23964 // If this is a select between two integer constants, try to do some
23966 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
23967 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
23968 // Don't do this for crazy integer types.
23969 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
23970 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
23971 // so that TrueC (the true value) is larger than FalseC.
23972 bool NeedsCondInvert = false;
23974 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
23975 // Efficiently invertible.
23976 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
23977 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
23978 isa<ConstantSDNode>(Cond.getOperand(1))))) {
23979 NeedsCondInvert = true;
23980 std::swap(TrueC, FalseC);
23983 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
23984 if (FalseC->getAPIntValue() == 0 &&
23985 TrueC->getAPIntValue().isPowerOf2()) {
23986 if (NeedsCondInvert) // Invert the condition if needed.
23987 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23988 DAG.getConstant(1, DL, Cond.getValueType()));
23990 // Zero extend the condition if needed.
23991 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
23993 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23994 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
23995 DAG.getConstant(ShAmt, DL, MVT::i8));
23998 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
23999 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
24000 if (NeedsCondInvert) // Invert the condition if needed.
24001 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
24002 DAG.getConstant(1, DL, Cond.getValueType()));
24004 // Zero extend the condition if needed.
24005 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
24006 FalseC->getValueType(0), Cond);
24007 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24008 SDValue(FalseC, 0));
24011 // Optimize cases that will turn into an LEA instruction. This requires
24012 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
24013 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
24014 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
24015 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
24017 bool isFastMultiplier = false;
24019 switch ((unsigned char)Diff) {
24021 case 1: // result = add base, cond
24022 case 2: // result = lea base( , cond*2)
24023 case 3: // result = lea base(cond, cond*2)
24024 case 4: // result = lea base( , cond*4)
24025 case 5: // result = lea base(cond, cond*4)
24026 case 8: // result = lea base( , cond*8)
24027 case 9: // result = lea base(cond, cond*8)
24028 isFastMultiplier = true;
24033 if (isFastMultiplier) {
24034 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
24035 if (NeedsCondInvert) // Invert the condition if needed.
24036 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
24037 DAG.getConstant(1, DL, Cond.getValueType()));
24039 // Zero extend the condition if needed.
24040 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
24042 // Scale the condition by the difference.
24044 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
24045 DAG.getConstant(Diff, DL,
24046 Cond.getValueType()));
24048 // Add the base if non-zero.
24049 if (FalseC->getAPIntValue() != 0)
24050 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24051 SDValue(FalseC, 0));
24058 // Canonicalize max and min:
24059 // (x > y) ? x : y -> (x >= y) ? x : y
24060 // (x < y) ? x : y -> (x <= y) ? x : y
24061 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
24062 // the need for an extra compare
24063 // against zero. e.g.
24064 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
24066 // testl %edi, %edi
24068 // cmovgl %edi, %eax
24072 // cmovsl %eax, %edi
24073 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
24074 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
24075 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
24076 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
24081 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
24082 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
24083 Cond.getOperand(0), Cond.getOperand(1), NewCC);
24084 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
24089 // Early exit check
24090 if (!TLI.isTypeLegal(VT))
24093 // Match VSELECTs into subs with unsigned saturation.
24094 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
24095 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
24096 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
24097 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
24098 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
24100 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
24101 // left side invert the predicate to simplify logic below.
24103 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
24105 CC = ISD::getSetCCInverse(CC, true);
24106 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
24110 if (Other.getNode() && Other->getNumOperands() == 2 &&
24111 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
24112 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
24113 SDValue CondRHS = Cond->getOperand(1);
24115 // Look for a general sub with unsigned saturation first.
24116 // x >= y ? x-y : 0 --> subus x, y
24117 // x > y ? x-y : 0 --> subus x, y
24118 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
24119 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
24120 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
24122 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
24123 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
24124 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
24125 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
24126 // If the RHS is a constant we have to reverse the const
24127 // canonicalization.
24128 // x > C-1 ? x+-C : 0 --> subus x, C
24129 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
24130 CondRHSConst->getAPIntValue() ==
24131 (-OpRHSConst->getAPIntValue() - 1))
24132 return DAG.getNode(
24133 X86ISD::SUBUS, DL, VT, OpLHS,
24134 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
24136 // Another special case: If C was a sign bit, the sub has been
24137 // canonicalized into a xor.
24138 // FIXME: Would it be better to use computeKnownBits to determine
24139 // whether it's safe to decanonicalize the xor?
24140 // x s< 0 ? x^C : 0 --> subus x, C
24141 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
24142 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
24143 OpRHSConst->getAPIntValue().isSignBit())
24144 // Note that we have to rebuild the RHS constant here to ensure we
24145 // don't rely on particular values of undef lanes.
24146 return DAG.getNode(
24147 X86ISD::SUBUS, DL, VT, OpLHS,
24148 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
24153 // Simplify vector selection if condition value type matches vselect
24155 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
24156 assert(Cond.getValueType().isVector() &&
24157 "vector select expects a vector selector!");
24159 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
24160 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
24162 // Try invert the condition if true value is not all 1s and false value
24164 if (!TValIsAllOnes && !FValIsAllZeros &&
24165 // Check if the selector will be produced by CMPP*/PCMP*
24166 Cond.getOpcode() == ISD::SETCC &&
24167 // Check if SETCC has already been promoted
24168 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT) ==
24170 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
24171 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
24173 if (TValIsAllZeros || FValIsAllOnes) {
24174 SDValue CC = Cond.getOperand(2);
24175 ISD::CondCode NewCC =
24176 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
24177 Cond.getOperand(0).getValueType().isInteger());
24178 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
24179 std::swap(LHS, RHS);
24180 TValIsAllOnes = FValIsAllOnes;
24181 FValIsAllZeros = TValIsAllZeros;
24185 if (TValIsAllOnes || FValIsAllZeros) {
24188 if (TValIsAllOnes && FValIsAllZeros)
24190 else if (TValIsAllOnes)
24192 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
24193 else if (FValIsAllZeros)
24194 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
24195 DAG.getBitcast(CondVT, LHS));
24197 return DAG.getBitcast(VT, Ret);
24201 // We should generate an X86ISD::BLENDI from a vselect if its argument
24202 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
24203 // constants. This specific pattern gets generated when we split a
24204 // selector for a 512 bit vector in a machine without AVX512 (but with
24205 // 256-bit vectors), during legalization:
24207 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
24209 // Iff we find this pattern and the build_vectors are built from
24210 // constants, we translate the vselect into a shuffle_vector that we
24211 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
24212 if ((N->getOpcode() == ISD::VSELECT ||
24213 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
24214 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
24215 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
24216 if (Shuffle.getNode())
24220 // If this is a *dynamic* select (non-constant condition) and we can match
24221 // this node with one of the variable blend instructions, restructure the
24222 // condition so that the blends can use the high bit of each element and use
24223 // SimplifyDemandedBits to simplify the condition operand.
24224 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
24225 !DCI.isBeforeLegalize() &&
24226 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
24227 unsigned BitWidth = Cond.getValueType().getScalarSizeInBits();
24229 // Don't optimize vector selects that map to mask-registers.
24233 // We can only handle the cases where VSELECT is directly legal on the
24234 // subtarget. We custom lower VSELECT nodes with constant conditions and
24235 // this makes it hard to see whether a dynamic VSELECT will correctly
24236 // lower, so we both check the operation's status and explicitly handle the
24237 // cases where a *dynamic* blend will fail even though a constant-condition
24238 // blend could be custom lowered.
24239 // FIXME: We should find a better way to handle this class of problems.
24240 // Potentially, we should combine constant-condition vselect nodes
24241 // pre-legalization into shuffles and not mark as many types as custom
24243 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
24245 // FIXME: We don't support i16-element blends currently. We could and
24246 // should support them by making *all* the bits in the condition be set
24247 // rather than just the high bit and using an i8-element blend.
24248 if (VT.getVectorElementType() == MVT::i16)
24250 // Dynamic blending was only available from SSE4.1 onward.
24251 if (VT.is128BitVector() && !Subtarget->hasSSE41())
24253 // Byte blends are only available in AVX2
24254 if (VT == MVT::v32i8 && !Subtarget->hasAVX2())
24257 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
24258 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
24260 APInt KnownZero, KnownOne;
24261 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
24262 DCI.isBeforeLegalizeOps());
24263 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
24264 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
24266 // If we changed the computation somewhere in the DAG, this change
24267 // will affect all users of Cond.
24268 // Make sure it is fine and update all the nodes so that we do not
24269 // use the generic VSELECT anymore. Otherwise, we may perform
24270 // wrong optimizations as we messed up with the actual expectation
24271 // for the vector boolean values.
24272 if (Cond != TLO.Old) {
24273 // Check all uses of that condition operand to check whether it will be
24274 // consumed by non-BLEND instructions, which may depend on all bits are
24276 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
24278 if (I->getOpcode() != ISD::VSELECT)
24279 // TODO: Add other opcodes eventually lowered into BLEND.
24282 // Update all the users of the condition, before committing the change,
24283 // so that the VSELECT optimizations that expect the correct vector
24284 // boolean value will not be triggered.
24285 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
24287 DAG.ReplaceAllUsesOfValueWith(
24289 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
24290 Cond, I->getOperand(1), I->getOperand(2)));
24291 DCI.CommitTargetLoweringOpt(TLO);
24294 // At this point, only Cond is changed. Change the condition
24295 // just for N to keep the opportunity to optimize all other
24296 // users their own way.
24297 DAG.ReplaceAllUsesOfValueWith(
24299 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
24300 TLO.New, N->getOperand(1), N->getOperand(2)));
24308 // Check whether a boolean test is testing a boolean value generated by
24309 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
24312 // Simplify the following patterns:
24313 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
24314 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
24315 // to (Op EFLAGS Cond)
24317 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
24318 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
24319 // to (Op EFLAGS !Cond)
24321 // where Op could be BRCOND or CMOV.
24323 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
24324 // Quit if not CMP and SUB with its value result used.
24325 if (Cmp.getOpcode() != X86ISD::CMP &&
24326 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
24329 // Quit if not used as a boolean value.
24330 if (CC != X86::COND_E && CC != X86::COND_NE)
24333 // Check CMP operands. One of them should be 0 or 1 and the other should be
24334 // an SetCC or extended from it.
24335 SDValue Op1 = Cmp.getOperand(0);
24336 SDValue Op2 = Cmp.getOperand(1);
24339 const ConstantSDNode* C = nullptr;
24340 bool needOppositeCond = (CC == X86::COND_E);
24341 bool checkAgainstTrue = false; // Is it a comparison against 1?
24343 if ((C = dyn_cast<ConstantSDNode>(Op1)))
24345 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
24347 else // Quit if all operands are not constants.
24350 if (C->getZExtValue() == 1) {
24351 needOppositeCond = !needOppositeCond;
24352 checkAgainstTrue = true;
24353 } else if (C->getZExtValue() != 0)
24354 // Quit if the constant is neither 0 or 1.
24357 bool truncatedToBoolWithAnd = false;
24358 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
24359 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
24360 SetCC.getOpcode() == ISD::TRUNCATE ||
24361 SetCC.getOpcode() == ISD::AND) {
24362 if (SetCC.getOpcode() == ISD::AND) {
24364 if (isOneConstant(SetCC.getOperand(0)))
24366 if (isOneConstant(SetCC.getOperand(1)))
24370 SetCC = SetCC.getOperand(OpIdx);
24371 truncatedToBoolWithAnd = true;
24373 SetCC = SetCC.getOperand(0);
24376 switch (SetCC.getOpcode()) {
24377 case X86ISD::SETCC_CARRY:
24378 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
24379 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
24380 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
24381 // truncated to i1 using 'and'.
24382 if (checkAgainstTrue && !truncatedToBoolWithAnd)
24384 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
24385 "Invalid use of SETCC_CARRY!");
24387 case X86ISD::SETCC:
24388 // Set the condition code or opposite one if necessary.
24389 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
24390 if (needOppositeCond)
24391 CC = X86::GetOppositeBranchCondition(CC);
24392 return SetCC.getOperand(1);
24393 case X86ISD::CMOV: {
24394 // Check whether false/true value has canonical one, i.e. 0 or 1.
24395 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
24396 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
24397 // Quit if true value is not a constant.
24400 // Quit if false value is not a constant.
24402 SDValue Op = SetCC.getOperand(0);
24403 // Skip 'zext' or 'trunc' node.
24404 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
24405 Op.getOpcode() == ISD::TRUNCATE)
24406 Op = Op.getOperand(0);
24407 // A special case for rdrand/rdseed, where 0 is set if false cond is
24409 if ((Op.getOpcode() != X86ISD::RDRAND &&
24410 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
24413 // Quit if false value is not the constant 0 or 1.
24414 bool FValIsFalse = true;
24415 if (FVal && FVal->getZExtValue() != 0) {
24416 if (FVal->getZExtValue() != 1)
24418 // If FVal is 1, opposite cond is needed.
24419 needOppositeCond = !needOppositeCond;
24420 FValIsFalse = false;
24422 // Quit if TVal is not the constant opposite of FVal.
24423 if (FValIsFalse && TVal->getZExtValue() != 1)
24425 if (!FValIsFalse && TVal->getZExtValue() != 0)
24427 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
24428 if (needOppositeCond)
24429 CC = X86::GetOppositeBranchCondition(CC);
24430 return SetCC.getOperand(3);
24437 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
24439 /// (X86or (X86setcc) (X86setcc))
24440 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
24441 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
24442 X86::CondCode &CC1, SDValue &Flags,
24444 if (Cond->getOpcode() == X86ISD::CMP) {
24445 if (!isNullConstant(Cond->getOperand(1)))
24448 Cond = Cond->getOperand(0);
24453 SDValue SetCC0, SetCC1;
24454 switch (Cond->getOpcode()) {
24455 default: return false;
24462 SetCC0 = Cond->getOperand(0);
24463 SetCC1 = Cond->getOperand(1);
24467 // Make sure we have SETCC nodes, using the same flags value.
24468 if (SetCC0.getOpcode() != X86ISD::SETCC ||
24469 SetCC1.getOpcode() != X86ISD::SETCC ||
24470 SetCC0->getOperand(1) != SetCC1->getOperand(1))
24473 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
24474 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
24475 Flags = SetCC0->getOperand(1);
24479 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
24480 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
24481 TargetLowering::DAGCombinerInfo &DCI,
24482 const X86Subtarget *Subtarget) {
24485 // If the flag operand isn't dead, don't touch this CMOV.
24486 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
24489 SDValue FalseOp = N->getOperand(0);
24490 SDValue TrueOp = N->getOperand(1);
24491 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
24492 SDValue Cond = N->getOperand(3);
24494 if (CC == X86::COND_E || CC == X86::COND_NE) {
24495 switch (Cond.getOpcode()) {
24499 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
24500 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
24501 return (CC == X86::COND_E) ? FalseOp : TrueOp;
24507 Flags = checkBoolTestSetCCCombine(Cond, CC);
24508 if (Flags.getNode() &&
24509 // Extra check as FCMOV only supports a subset of X86 cond.
24510 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
24511 SDValue Ops[] = { FalseOp, TrueOp,
24512 DAG.getConstant(CC, DL, MVT::i8), Flags };
24513 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24516 // If this is a select between two integer constants, try to do some
24517 // optimizations. Note that the operands are ordered the opposite of SELECT
24519 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
24520 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
24521 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
24522 // larger than FalseC (the false value).
24523 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
24524 CC = X86::GetOppositeBranchCondition(CC);
24525 std::swap(TrueC, FalseC);
24526 std::swap(TrueOp, FalseOp);
24529 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
24530 // This is efficient for any integer data type (including i8/i16) and
24532 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
24533 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24534 DAG.getConstant(CC, DL, MVT::i8), Cond);
24536 // Zero extend the condition if needed.
24537 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
24539 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
24540 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
24541 DAG.getConstant(ShAmt, DL, MVT::i8));
24542 if (N->getNumValues() == 2) // Dead flag value?
24543 return DCI.CombineTo(N, Cond, SDValue());
24547 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
24548 // for any integer data type, including i8/i16.
24549 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
24550 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24551 DAG.getConstant(CC, DL, MVT::i8), Cond);
24553 // Zero extend the condition if needed.
24554 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
24555 FalseC->getValueType(0), Cond);
24556 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24557 SDValue(FalseC, 0));
24559 if (N->getNumValues() == 2) // Dead flag value?
24560 return DCI.CombineTo(N, Cond, SDValue());
24564 // Optimize cases that will turn into an LEA instruction. This requires
24565 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
24566 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
24567 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
24568 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
24570 bool isFastMultiplier = false;
24572 switch ((unsigned char)Diff) {
24574 case 1: // result = add base, cond
24575 case 2: // result = lea base( , cond*2)
24576 case 3: // result = lea base(cond, cond*2)
24577 case 4: // result = lea base( , cond*4)
24578 case 5: // result = lea base(cond, cond*4)
24579 case 8: // result = lea base( , cond*8)
24580 case 9: // result = lea base(cond, cond*8)
24581 isFastMultiplier = true;
24586 if (isFastMultiplier) {
24587 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
24588 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24589 DAG.getConstant(CC, DL, MVT::i8), Cond);
24590 // Zero extend the condition if needed.
24591 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
24593 // Scale the condition by the difference.
24595 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
24596 DAG.getConstant(Diff, DL, Cond.getValueType()));
24598 // Add the base if non-zero.
24599 if (FalseC->getAPIntValue() != 0)
24600 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24601 SDValue(FalseC, 0));
24602 if (N->getNumValues() == 2) // Dead flag value?
24603 return DCI.CombineTo(N, Cond, SDValue());
24610 // Handle these cases:
24611 // (select (x != c), e, c) -> select (x != c), e, x),
24612 // (select (x == c), c, e) -> select (x == c), x, e)
24613 // where the c is an integer constant, and the "select" is the combination
24614 // of CMOV and CMP.
24616 // The rationale for this change is that the conditional-move from a constant
24617 // needs two instructions, however, conditional-move from a register needs
24618 // only one instruction.
24620 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
24621 // some instruction-combining opportunities. This opt needs to be
24622 // postponed as late as possible.
24624 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
24625 // the DCI.xxxx conditions are provided to postpone the optimization as
24626 // late as possible.
24628 ConstantSDNode *CmpAgainst = nullptr;
24629 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
24630 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
24631 !isa<ConstantSDNode>(Cond.getOperand(0))) {
24633 if (CC == X86::COND_NE &&
24634 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
24635 CC = X86::GetOppositeBranchCondition(CC);
24636 std::swap(TrueOp, FalseOp);
24639 if (CC == X86::COND_E &&
24640 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
24641 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
24642 DAG.getConstant(CC, DL, MVT::i8), Cond };
24643 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
24648 // Fold and/or of setcc's to double CMOV:
24649 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
24650 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
24652 // This combine lets us generate:
24653 // cmovcc1 (jcc1 if we don't have CMOV)
24659 // cmovne (jne if we don't have CMOV)
24660 // When we can't use the CMOV instruction, it might increase branch
24662 // When we can use CMOV, or when there is no mispredict, this improves
24663 // throughput and reduces register pressure.
24665 if (CC == X86::COND_NE) {
24667 X86::CondCode CC0, CC1;
24669 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
24671 std::swap(FalseOp, TrueOp);
24672 CC0 = X86::GetOppositeBranchCondition(CC0);
24673 CC1 = X86::GetOppositeBranchCondition(CC1);
24676 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
24678 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
24679 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
24680 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24681 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
24689 /// PerformMulCombine - Optimize a single multiply with constant into two
24690 /// in order to implement it with two cheaper instructions, e.g.
24691 /// LEA + SHL, LEA + LEA.
24692 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
24693 TargetLowering::DAGCombinerInfo &DCI) {
24694 // An imul is usually smaller than the alternative sequence.
24695 if (DAG.getMachineFunction().getFunction()->optForMinSize())
24698 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
24701 EVT VT = N->getValueType(0);
24702 if (VT != MVT::i64 && VT != MVT::i32)
24705 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
24708 uint64_t MulAmt = C->getZExtValue();
24709 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
24712 uint64_t MulAmt1 = 0;
24713 uint64_t MulAmt2 = 0;
24714 if ((MulAmt % 9) == 0) {
24716 MulAmt2 = MulAmt / 9;
24717 } else if ((MulAmt % 5) == 0) {
24719 MulAmt2 = MulAmt / 5;
24720 } else if ((MulAmt % 3) == 0) {
24722 MulAmt2 = MulAmt / 3;
24725 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
24728 if (isPowerOf2_64(MulAmt2) &&
24729 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
24730 // If second multiplifer is pow2, issue it first. We want the multiply by
24731 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
24733 std::swap(MulAmt1, MulAmt2);
24736 if (isPowerOf2_64(MulAmt1))
24737 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
24738 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
24740 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
24741 DAG.getConstant(MulAmt1, DL, VT));
24743 if (isPowerOf2_64(MulAmt2))
24744 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
24745 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
24747 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
24748 DAG.getConstant(MulAmt2, DL, VT));
24750 // Do not add new nodes to DAG combiner worklist.
24751 DCI.CombineTo(N, NewMul, false);
24756 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
24757 SDValue N0 = N->getOperand(0);
24758 SDValue N1 = N->getOperand(1);
24759 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
24760 EVT VT = N0.getValueType();
24762 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
24763 // since the result of setcc_c is all zero's or all ones.
24764 if (VT.isInteger() && !VT.isVector() &&
24765 N1C && N0.getOpcode() == ISD::AND &&
24766 N0.getOperand(1).getOpcode() == ISD::Constant) {
24767 SDValue N00 = N0.getOperand(0);
24768 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
24769 APInt ShAmt = N1C->getAPIntValue();
24770 Mask = Mask.shl(ShAmt);
24771 bool MaskOK = false;
24772 // We can handle cases concerning bit-widening nodes containing setcc_c if
24773 // we carefully interrogate the mask to make sure we are semantics
24775 // The transform is not safe if the result of C1 << C2 exceeds the bitwidth
24776 // of the underlying setcc_c operation if the setcc_c was zero extended.
24777 // Consider the following example:
24778 // zext(setcc_c) -> i32 0x0000FFFF
24779 // c1 -> i32 0x0000FFFF
24780 // c2 -> i32 0x00000001
24781 // (shl (and (setcc_c), c1), c2) -> i32 0x0001FFFE
24782 // (and setcc_c, (c1 << c2)) -> i32 0x0000FFFE
24783 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24785 } else if (N00.getOpcode() == ISD::SIGN_EXTEND &&
24786 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24788 } else if ((N00.getOpcode() == ISD::ZERO_EXTEND ||
24789 N00.getOpcode() == ISD::ANY_EXTEND) &&
24790 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24791 MaskOK = Mask.isIntN(N00.getOperand(0).getValueSizeInBits());
24793 if (MaskOK && Mask != 0) {
24795 return DAG.getNode(ISD::AND, DL, VT, N00, DAG.getConstant(Mask, DL, VT));
24799 // Hardware support for vector shifts is sparse which makes us scalarize the
24800 // vector operations in many cases. Also, on sandybridge ADD is faster than
24802 // (shl V, 1) -> add V,V
24803 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
24804 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
24805 assert(N0.getValueType().isVector() && "Invalid vector shift type");
24806 // We shift all of the values by one. In many cases we do not have
24807 // hardware support for this operation. This is better expressed as an ADD
24809 if (N1SplatC->getAPIntValue() == 1)
24810 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
24816 /// \brief Returns a vector of 0s if the node in input is a vector logical
24817 /// shift by a constant amount which is known to be bigger than or equal
24818 /// to the vector element size in bits.
24819 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
24820 const X86Subtarget *Subtarget) {
24821 EVT VT = N->getValueType(0);
24823 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
24824 (!Subtarget->hasInt256() ||
24825 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
24828 SDValue Amt = N->getOperand(1);
24830 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
24831 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
24832 APInt ShiftAmt = AmtSplat->getAPIntValue();
24833 unsigned MaxAmount =
24834 VT.getSimpleVT().getVectorElementType().getSizeInBits();
24836 // SSE2/AVX2 logical shifts always return a vector of 0s
24837 // if the shift amount is bigger than or equal to
24838 // the element size. The constant shift amount will be
24839 // encoded as a 8-bit immediate.
24840 if (ShiftAmt.trunc(8).uge(MaxAmount))
24841 return getZeroVector(VT.getSimpleVT(), Subtarget, DAG, DL);
24847 /// PerformShiftCombine - Combine shifts.
24848 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
24849 TargetLowering::DAGCombinerInfo &DCI,
24850 const X86Subtarget *Subtarget) {
24851 if (N->getOpcode() == ISD::SHL)
24852 if (SDValue V = PerformSHLCombine(N, DAG))
24855 // Try to fold this logical shift into a zero vector.
24856 if (N->getOpcode() != ISD::SRA)
24857 if (SDValue V = performShiftToAllZeros(N, DAG, Subtarget))
24863 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
24864 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
24865 // and friends. Likewise for OR -> CMPNEQSS.
24866 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
24867 TargetLowering::DAGCombinerInfo &DCI,
24868 const X86Subtarget *Subtarget) {
24871 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
24872 // we're requiring SSE2 for both.
24873 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
24874 SDValue N0 = N->getOperand(0);
24875 SDValue N1 = N->getOperand(1);
24876 SDValue CMP0 = N0->getOperand(1);
24877 SDValue CMP1 = N1->getOperand(1);
24880 // The SETCCs should both refer to the same CMP.
24881 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
24884 SDValue CMP00 = CMP0->getOperand(0);
24885 SDValue CMP01 = CMP0->getOperand(1);
24886 EVT VT = CMP00.getValueType();
24888 if (VT == MVT::f32 || VT == MVT::f64) {
24889 bool ExpectingFlags = false;
24890 // Check for any users that want flags:
24891 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
24892 !ExpectingFlags && UI != UE; ++UI)
24893 switch (UI->getOpcode()) {
24898 ExpectingFlags = true;
24900 case ISD::CopyToReg:
24901 case ISD::SIGN_EXTEND:
24902 case ISD::ZERO_EXTEND:
24903 case ISD::ANY_EXTEND:
24907 if (!ExpectingFlags) {
24908 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
24909 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
24911 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
24912 X86::CondCode tmp = cc0;
24917 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
24918 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
24919 // FIXME: need symbolic constants for these magic numbers.
24920 // See X86ATTInstPrinter.cpp:printSSECC().
24921 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
24922 if (Subtarget->hasAVX512()) {
24923 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
24925 DAG.getConstant(x86cc, DL, MVT::i8));
24926 if (N->getValueType(0) != MVT::i1)
24927 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
24931 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
24932 CMP00.getValueType(), CMP00, CMP01,
24933 DAG.getConstant(x86cc, DL,
24936 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
24937 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
24939 if (is64BitFP && !Subtarget->is64Bit()) {
24940 // On a 32-bit target, we cannot bitcast the 64-bit float to a
24941 // 64-bit integer, since that's not a legal type. Since
24942 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
24943 // bits, but can do this little dance to extract the lowest 32 bits
24944 // and work with those going forward.
24945 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
24947 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
24948 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
24949 Vector32, DAG.getIntPtrConstant(0, DL));
24953 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
24954 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
24955 DAG.getConstant(1, DL, IntVT));
24956 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
24958 return OneBitOfTruth;
24966 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
24967 /// so it can be folded inside ANDNP.
24968 static bool CanFoldXORWithAllOnes(const SDNode *N) {
24969 EVT VT = N->getValueType(0);
24971 // Match direct AllOnes for 128 and 256-bit vectors
24972 if (ISD::isBuildVectorAllOnes(N))
24975 // Look through a bit convert.
24976 if (N->getOpcode() == ISD::BITCAST)
24977 N = N->getOperand(0).getNode();
24979 // Sometimes the operand may come from a insert_subvector building a 256-bit
24981 if (VT.is256BitVector() &&
24982 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24983 SDValue V1 = N->getOperand(0);
24984 SDValue V2 = N->getOperand(1);
24986 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24987 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24988 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24989 ISD::isBuildVectorAllOnes(V2.getNode()))
24996 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24997 // register. In most cases we actually compare or select YMM-sized registers
24998 // and mixing the two types creates horrible code. This method optimizes
24999 // some of the transition sequences.
25000 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
25001 TargetLowering::DAGCombinerInfo &DCI,
25002 const X86Subtarget *Subtarget) {
25003 EVT VT = N->getValueType(0);
25004 if (!VT.is256BitVector())
25007 assert((N->getOpcode() == ISD::ANY_EXTEND ||
25008 N->getOpcode() == ISD::ZERO_EXTEND ||
25009 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
25011 SDValue Narrow = N->getOperand(0);
25012 EVT NarrowVT = Narrow->getValueType(0);
25013 if (!NarrowVT.is128BitVector())
25016 if (Narrow->getOpcode() != ISD::XOR &&
25017 Narrow->getOpcode() != ISD::AND &&
25018 Narrow->getOpcode() != ISD::OR)
25021 SDValue N0 = Narrow->getOperand(0);
25022 SDValue N1 = Narrow->getOperand(1);
25025 // The Left side has to be a trunc.
25026 if (N0.getOpcode() != ISD::TRUNCATE)
25029 // The type of the truncated inputs.
25030 EVT WideVT = N0->getOperand(0)->getValueType(0);
25034 // The right side has to be a 'trunc' or a constant vector.
25035 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
25036 ConstantSDNode *RHSConstSplat = nullptr;
25037 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
25038 RHSConstSplat = RHSBV->getConstantSplatNode();
25039 if (!RHSTrunc && !RHSConstSplat)
25042 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25044 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
25047 // Set N0 and N1 to hold the inputs to the new wide operation.
25048 N0 = N0->getOperand(0);
25049 if (RHSConstSplat) {
25050 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getVectorElementType(),
25051 SDValue(RHSConstSplat, 0));
25052 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
25053 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
25054 } else if (RHSTrunc) {
25055 N1 = N1->getOperand(0);
25058 // Generate the wide operation.
25059 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
25060 unsigned Opcode = N->getOpcode();
25062 case ISD::ANY_EXTEND:
25064 case ISD::ZERO_EXTEND: {
25065 unsigned InBits = NarrowVT.getScalarSizeInBits();
25066 APInt Mask = APInt::getAllOnesValue(InBits);
25067 Mask = Mask.zext(VT.getScalarSizeInBits());
25068 return DAG.getNode(ISD::AND, DL, VT,
25069 Op, DAG.getConstant(Mask, DL, VT));
25071 case ISD::SIGN_EXTEND:
25072 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
25073 Op, DAG.getValueType(NarrowVT));
25075 llvm_unreachable("Unexpected opcode");
25079 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
25080 TargetLowering::DAGCombinerInfo &DCI,
25081 const X86Subtarget *Subtarget) {
25082 SDValue N0 = N->getOperand(0);
25083 SDValue N1 = N->getOperand(1);
25086 // A vector zext_in_reg may be represented as a shuffle,
25087 // feeding into a bitcast (this represents anyext) feeding into
25088 // an and with a mask.
25089 // We'd like to try to combine that into a shuffle with zero
25090 // plus a bitcast, removing the and.
25091 if (N0.getOpcode() != ISD::BITCAST ||
25092 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
25095 // The other side of the AND should be a splat of 2^C, where C
25096 // is the number of bits in the source type.
25097 if (N1.getOpcode() == ISD::BITCAST)
25098 N1 = N1.getOperand(0);
25099 if (N1.getOpcode() != ISD::BUILD_VECTOR)
25101 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
25103 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
25104 EVT SrcType = Shuffle->getValueType(0);
25106 // We expect a single-source shuffle
25107 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
25110 unsigned SrcSize = SrcType.getScalarSizeInBits();
25112 APInt SplatValue, SplatUndef;
25113 unsigned SplatBitSize;
25115 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
25116 SplatBitSize, HasAnyUndefs))
25119 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
25120 // Make sure the splat matches the mask we expect
25121 if (SplatBitSize > ResSize ||
25122 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
25125 // Make sure the input and output size make sense
25126 if (SrcSize >= ResSize || ResSize % SrcSize)
25129 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
25130 // The number of u's between each two values depends on the ratio between
25131 // the source and dest type.
25132 unsigned ZextRatio = ResSize / SrcSize;
25133 bool IsZext = true;
25134 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
25135 if (i % ZextRatio) {
25136 if (Shuffle->getMaskElt(i) > 0) {
25142 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
25143 // Expected element number
25153 // Ok, perform the transformation - replace the shuffle with
25154 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
25155 // (instead of undef) where the k elements come from the zero vector.
25156 SmallVector<int, 8> Mask;
25157 unsigned NumElems = SrcType.getVectorNumElements();
25158 for (unsigned i = 0; i < NumElems; ++i)
25160 Mask.push_back(NumElems);
25162 Mask.push_back(i / ZextRatio);
25164 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
25165 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
25166 return DAG.getBitcast(N0.getValueType(), NewShuffle);
25169 /// If both input operands of a logic op are being cast from floating point
25170 /// types, try to convert this into a floating point logic node to avoid
25171 /// unnecessary moves from SSE to integer registers.
25172 static SDValue convertIntLogicToFPLogic(SDNode *N, SelectionDAG &DAG,
25173 const X86Subtarget *Subtarget) {
25174 unsigned FPOpcode = ISD::DELETED_NODE;
25175 if (N->getOpcode() == ISD::AND)
25176 FPOpcode = X86ISD::FAND;
25177 else if (N->getOpcode() == ISD::OR)
25178 FPOpcode = X86ISD::FOR;
25179 else if (N->getOpcode() == ISD::XOR)
25180 FPOpcode = X86ISD::FXOR;
25182 assert(FPOpcode != ISD::DELETED_NODE &&
25183 "Unexpected input node for FP logic conversion");
25185 EVT VT = N->getValueType(0);
25186 SDValue N0 = N->getOperand(0);
25187 SDValue N1 = N->getOperand(1);
25189 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST &&
25190 ((Subtarget->hasSSE1() && VT == MVT::i32) ||
25191 (Subtarget->hasSSE2() && VT == MVT::i64))) {
25192 SDValue N00 = N0.getOperand(0);
25193 SDValue N10 = N1.getOperand(0);
25194 EVT N00Type = N00.getValueType();
25195 EVT N10Type = N10.getValueType();
25196 if (N00Type.isFloatingPoint() && N10Type.isFloatingPoint()) {
25197 SDValue FPLogic = DAG.getNode(FPOpcode, DL, N00Type, N00, N10);
25198 return DAG.getBitcast(VT, FPLogic);
25204 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
25205 TargetLowering::DAGCombinerInfo &DCI,
25206 const X86Subtarget *Subtarget) {
25207 if (DCI.isBeforeLegalizeOps())
25210 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
25213 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
25216 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25219 EVT VT = N->getValueType(0);
25220 SDValue N0 = N->getOperand(0);
25221 SDValue N1 = N->getOperand(1);
25224 // Create BEXTR instructions
25225 // BEXTR is ((X >> imm) & (2**size-1))
25226 if (VT == MVT::i32 || VT == MVT::i64) {
25227 // Check for BEXTR.
25228 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
25229 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
25230 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
25231 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25232 if (MaskNode && ShiftNode) {
25233 uint64_t Mask = MaskNode->getZExtValue();
25234 uint64_t Shift = ShiftNode->getZExtValue();
25235 if (isMask_64(Mask)) {
25236 uint64_t MaskSize = countPopulation(Mask);
25237 if (Shift + MaskSize <= VT.getSizeInBits())
25238 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
25239 DAG.getConstant(Shift | (MaskSize << 8), DL,
25248 // Want to form ANDNP nodes:
25249 // 1) In the hopes of then easily combining them with OR and AND nodes
25250 // to form PBLEND/PSIGN.
25251 // 2) To match ANDN packed intrinsics
25252 if (VT != MVT::v2i64 && VT != MVT::v4i64)
25255 // Check LHS for vnot
25256 if (N0.getOpcode() == ISD::XOR &&
25257 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
25258 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
25259 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
25261 // Check RHS for vnot
25262 if (N1.getOpcode() == ISD::XOR &&
25263 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
25264 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
25265 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
25270 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
25271 TargetLowering::DAGCombinerInfo &DCI,
25272 const X86Subtarget *Subtarget) {
25273 if (DCI.isBeforeLegalizeOps())
25276 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
25279 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25282 SDValue N0 = N->getOperand(0);
25283 SDValue N1 = N->getOperand(1);
25284 EVT VT = N->getValueType(0);
25286 // look for psign/blend
25287 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
25288 if (!Subtarget->hasSSSE3() ||
25289 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
25292 // Canonicalize pandn to RHS
25293 if (N0.getOpcode() == X86ISD::ANDNP)
25295 // or (and (m, y), (pandn m, x))
25296 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
25297 SDValue Mask = N1.getOperand(0);
25298 SDValue X = N1.getOperand(1);
25300 if (N0.getOperand(0) == Mask)
25301 Y = N0.getOperand(1);
25302 if (N0.getOperand(1) == Mask)
25303 Y = N0.getOperand(0);
25305 // Check to see if the mask appeared in both the AND and ANDNP and
25309 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
25310 // Look through mask bitcast.
25311 if (Mask.getOpcode() == ISD::BITCAST)
25312 Mask = Mask.getOperand(0);
25313 if (X.getOpcode() == ISD::BITCAST)
25314 X = X.getOperand(0);
25315 if (Y.getOpcode() == ISD::BITCAST)
25316 Y = Y.getOperand(0);
25318 EVT MaskVT = Mask.getValueType();
25320 // Validate that the Mask operand is a vector sra node.
25321 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
25322 // there is no psrai.b
25323 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
25324 unsigned SraAmt = ~0;
25325 if (Mask.getOpcode() == ISD::SRA) {
25326 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
25327 if (auto *AmtConst = AmtBV->getConstantSplatNode())
25328 SraAmt = AmtConst->getZExtValue();
25329 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
25330 SDValue SraC = Mask.getOperand(1);
25331 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
25333 if ((SraAmt + 1) != EltBits)
25338 // Now we know we at least have a plendvb with the mask val. See if
25339 // we can form a psignb/w/d.
25340 // psign = x.type == y.type == mask.type && y = sub(0, x);
25341 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
25342 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
25343 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
25344 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
25345 "Unsupported VT for PSIGN");
25346 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
25347 return DAG.getBitcast(VT, Mask);
25349 // PBLENDVB only available on SSE 4.1
25350 if (!Subtarget->hasSSE41())
25353 MVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
25355 X = DAG.getBitcast(BlendVT, X);
25356 Y = DAG.getBitcast(BlendVT, Y);
25357 Mask = DAG.getBitcast(BlendVT, Mask);
25358 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
25359 return DAG.getBitcast(VT, Mask);
25363 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
25366 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
25367 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
25369 // SHLD/SHRD instructions have lower register pressure, but on some
25370 // platforms they have higher latency than the equivalent
25371 // series of shifts/or that would otherwise be generated.
25372 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
25373 // have higher latencies and we are not optimizing for size.
25374 if (!OptForSize && Subtarget->isSHLDSlow())
25377 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
25379 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
25381 if (!N0.hasOneUse() || !N1.hasOneUse())
25384 SDValue ShAmt0 = N0.getOperand(1);
25385 if (ShAmt0.getValueType() != MVT::i8)
25387 SDValue ShAmt1 = N1.getOperand(1);
25388 if (ShAmt1.getValueType() != MVT::i8)
25390 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
25391 ShAmt0 = ShAmt0.getOperand(0);
25392 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
25393 ShAmt1 = ShAmt1.getOperand(0);
25396 unsigned Opc = X86ISD::SHLD;
25397 SDValue Op0 = N0.getOperand(0);
25398 SDValue Op1 = N1.getOperand(0);
25399 if (ShAmt0.getOpcode() == ISD::SUB) {
25400 Opc = X86ISD::SHRD;
25401 std::swap(Op0, Op1);
25402 std::swap(ShAmt0, ShAmt1);
25405 unsigned Bits = VT.getSizeInBits();
25406 if (ShAmt1.getOpcode() == ISD::SUB) {
25407 SDValue Sum = ShAmt1.getOperand(0);
25408 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
25409 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
25410 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
25411 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
25412 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
25413 return DAG.getNode(Opc, DL, VT,
25415 DAG.getNode(ISD::TRUNCATE, DL,
25418 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
25419 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
25421 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
25422 return DAG.getNode(Opc, DL, VT,
25423 N0.getOperand(0), N1.getOperand(0),
25424 DAG.getNode(ISD::TRUNCATE, DL,
25431 // Generate NEG and CMOV for integer abs.
25432 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
25433 EVT VT = N->getValueType(0);
25435 // Since X86 does not have CMOV for 8-bit integer, we don't convert
25436 // 8-bit integer abs to NEG and CMOV.
25437 if (VT.isInteger() && VT.getSizeInBits() == 8)
25440 SDValue N0 = N->getOperand(0);
25441 SDValue N1 = N->getOperand(1);
25444 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
25445 // and change it to SUB and CMOV.
25446 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
25447 N0.getOpcode() == ISD::ADD &&
25448 N0.getOperand(1) == N1 &&
25449 N1.getOpcode() == ISD::SRA &&
25450 N1.getOperand(0) == N0.getOperand(0))
25451 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
25452 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
25453 // Generate SUB & CMOV.
25454 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
25455 DAG.getConstant(0, DL, VT), N0.getOperand(0));
25457 SDValue Ops[] = { N0.getOperand(0), Neg,
25458 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
25459 SDValue(Neg.getNode(), 1) };
25460 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
25465 // Try to turn tests against the signbit in the form of:
25466 // XOR(TRUNCATE(SRL(X, size(X)-1)), 1)
25469 static SDValue foldXorTruncShiftIntoCmp(SDNode *N, SelectionDAG &DAG) {
25470 // This is only worth doing if the output type is i8.
25471 if (N->getValueType(0) != MVT::i8)
25474 SDValue N0 = N->getOperand(0);
25475 SDValue N1 = N->getOperand(1);
25477 // We should be performing an xor against a truncated shift.
25478 if (N0.getOpcode() != ISD::TRUNCATE || !N0.hasOneUse())
25481 // Make sure we are performing an xor against one.
25482 if (!isOneConstant(N1))
25485 // SetCC on x86 zero extends so only act on this if it's a logical shift.
25486 SDValue Shift = N0.getOperand(0);
25487 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse())
25490 // Make sure we are truncating from one of i16, i32 or i64.
25491 EVT ShiftTy = Shift.getValueType();
25492 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64)
25495 // Make sure the shift amount extracts the sign bit.
25496 if (!isa<ConstantSDNode>(Shift.getOperand(1)) ||
25497 Shift.getConstantOperandVal(1) != ShiftTy.getSizeInBits() - 1)
25500 // Create a greater-than comparison against -1.
25501 // N.B. Using SETGE against 0 works but we want a canonical looking
25502 // comparison, using SETGT matches up with what TranslateX86CC.
25504 SDValue ShiftOp = Shift.getOperand(0);
25505 EVT ShiftOpTy = ShiftOp.getValueType();
25506 SDValue Cond = DAG.getSetCC(DL, MVT::i8, ShiftOp,
25507 DAG.getConstant(-1, DL, ShiftOpTy), ISD::SETGT);
25511 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
25512 TargetLowering::DAGCombinerInfo &DCI,
25513 const X86Subtarget *Subtarget) {
25514 if (DCI.isBeforeLegalizeOps())
25517 if (SDValue RV = foldXorTruncShiftIntoCmp(N, DAG))
25520 if (Subtarget->hasCMov())
25521 if (SDValue RV = performIntegerAbsCombine(N, DAG))
25524 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25530 /// This function detects the AVG pattern between vectors of unsigned i8/i16,
25531 /// which is c = (a + b + 1) / 2, and replace this operation with the efficient
25532 /// X86ISD::AVG instruction.
25533 static SDValue detectAVGPattern(SDValue In, EVT VT, SelectionDAG &DAG,
25534 const X86Subtarget *Subtarget, SDLoc DL) {
25535 if (!VT.isVector() || !VT.isSimple())
25537 EVT InVT = In.getValueType();
25538 unsigned NumElems = VT.getVectorNumElements();
25540 EVT ScalarVT = VT.getVectorElementType();
25541 if (!((ScalarVT == MVT::i8 || ScalarVT == MVT::i16) &&
25542 isPowerOf2_32(NumElems)))
25545 // InScalarVT is the intermediate type in AVG pattern and it should be greater
25546 // than the original input type (i8/i16).
25547 EVT InScalarVT = InVT.getVectorElementType();
25548 if (InScalarVT.getSizeInBits() <= ScalarVT.getSizeInBits())
25551 if (Subtarget->hasAVX512()) {
25552 if (VT.getSizeInBits() > 512)
25554 } else if (Subtarget->hasAVX2()) {
25555 if (VT.getSizeInBits() > 256)
25558 if (VT.getSizeInBits() > 128)
25562 // Detect the following pattern:
25564 // %1 = zext <N x i8> %a to <N x i32>
25565 // %2 = zext <N x i8> %b to <N x i32>
25566 // %3 = add nuw nsw <N x i32> %1, <i32 1 x N>
25567 // %4 = add nuw nsw <N x i32> %3, %2
25568 // %5 = lshr <N x i32> %N, <i32 1 x N>
25569 // %6 = trunc <N x i32> %5 to <N x i8>
25571 // In AVX512, the last instruction can also be a trunc store.
25573 if (In.getOpcode() != ISD::SRL)
25576 // A lambda checking the given SDValue is a constant vector and each element
25577 // is in the range [Min, Max].
25578 auto IsConstVectorInRange = [](SDValue V, unsigned Min, unsigned Max) {
25579 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(V);
25580 if (!BV || !BV->isConstant())
25582 for (unsigned i = 0, e = V.getNumOperands(); i < e; i++) {
25583 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(i));
25586 uint64_t Val = C->getZExtValue();
25587 if (Val < Min || Val > Max)
25593 // Check if each element of the vector is left-shifted by one.
25594 auto LHS = In.getOperand(0);
25595 auto RHS = In.getOperand(1);
25596 if (!IsConstVectorInRange(RHS, 1, 1))
25598 if (LHS.getOpcode() != ISD::ADD)
25601 // Detect a pattern of a + b + 1 where the order doesn't matter.
25602 SDValue Operands[3];
25603 Operands[0] = LHS.getOperand(0);
25604 Operands[1] = LHS.getOperand(1);
25606 // Take care of the case when one of the operands is a constant vector whose
25607 // element is in the range [1, 256].
25608 if (IsConstVectorInRange(Operands[1], 1, ScalarVT == MVT::i8 ? 256 : 65536) &&
25609 Operands[0].getOpcode() == ISD::ZERO_EXTEND &&
25610 Operands[0].getOperand(0).getValueType() == VT) {
25611 // The pattern is detected. Subtract one from the constant vector, then
25612 // demote it and emit X86ISD::AVG instruction.
25613 SDValue One = DAG.getConstant(1, DL, InScalarVT);
25614 SDValue Ones = DAG.getNode(ISD::BUILD_VECTOR, DL, InVT,
25615 SmallVector<SDValue, 8>(NumElems, One));
25616 Operands[1] = DAG.getNode(ISD::SUB, DL, InVT, Operands[1], Ones);
25617 Operands[1] = DAG.getNode(ISD::TRUNCATE, DL, VT, Operands[1]);
25618 return DAG.getNode(X86ISD::AVG, DL, VT, Operands[0].getOperand(0),
25622 if (Operands[0].getOpcode() == ISD::ADD)
25623 std::swap(Operands[0], Operands[1]);
25624 else if (Operands[1].getOpcode() != ISD::ADD)
25626 Operands[2] = Operands[1].getOperand(0);
25627 Operands[1] = Operands[1].getOperand(1);
25629 // Now we have three operands of two additions. Check that one of them is a
25630 // constant vector with ones, and the other two are promoted from i8/i16.
25631 for (int i = 0; i < 3; ++i) {
25632 if (!IsConstVectorInRange(Operands[i], 1, 1))
25634 std::swap(Operands[i], Operands[2]);
25636 // Check if Operands[0] and Operands[1] are results of type promotion.
25637 for (int j = 0; j < 2; ++j)
25638 if (Operands[j].getOpcode() != ISD::ZERO_EXTEND ||
25639 Operands[j].getOperand(0).getValueType() != VT)
25642 // The pattern is detected, emit X86ISD::AVG instruction.
25643 return DAG.getNode(X86ISD::AVG, DL, VT, Operands[0].getOperand(0),
25644 Operands[1].getOperand(0));
25650 static SDValue PerformTRUNCATECombine(SDNode *N, SelectionDAG &DAG,
25651 const X86Subtarget *Subtarget) {
25652 return detectAVGPattern(N->getOperand(0), N->getValueType(0), DAG, Subtarget,
25656 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
25657 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
25658 TargetLowering::DAGCombinerInfo &DCI,
25659 const X86Subtarget *Subtarget) {
25660 LoadSDNode *Ld = cast<LoadSDNode>(N);
25661 EVT RegVT = Ld->getValueType(0);
25662 EVT MemVT = Ld->getMemoryVT();
25664 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25666 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
25667 // into two 16-byte operations.
25668 ISD::LoadExtType Ext = Ld->getExtensionType();
25670 unsigned AddressSpace = Ld->getAddressSpace();
25671 unsigned Alignment = Ld->getAlignment();
25672 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&
25673 Ext == ISD::NON_EXTLOAD &&
25674 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,
25675 AddressSpace, Alignment, &Fast) && !Fast) {
25676 unsigned NumElems = RegVT.getVectorNumElements();
25680 SDValue Ptr = Ld->getBasePtr();
25681 SDValue Increment =
25682 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25684 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
25686 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
25687 Ld->getPointerInfo(), Ld->isVolatile(),
25688 Ld->isNonTemporal(), Ld->isInvariant(),
25690 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25691 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
25692 Ld->getPointerInfo(), Ld->isVolatile(),
25693 Ld->isNonTemporal(), Ld->isInvariant(),
25694 std::min(16U, Alignment));
25695 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
25697 Load2.getValue(1));
25699 SDValue NewVec = DAG.getUNDEF(RegVT);
25700 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
25701 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
25702 return DCI.CombineTo(N, NewVec, TF, true);
25708 /// PerformMLOADCombine - Resolve extending loads
25709 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
25710 TargetLowering::DAGCombinerInfo &DCI,
25711 const X86Subtarget *Subtarget) {
25712 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
25713 if (Mld->getExtensionType() != ISD::SEXTLOAD)
25716 EVT VT = Mld->getValueType(0);
25717 unsigned NumElems = VT.getVectorNumElements();
25718 EVT LdVT = Mld->getMemoryVT();
25721 assert(LdVT != VT && "Cannot extend to the same type");
25722 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
25723 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
25724 // From, To sizes and ElemCount must be pow of two
25725 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
25726 "Unexpected size for extending masked load");
25728 unsigned SizeRatio = ToSz / FromSz;
25729 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
25731 // Create a type on which we perform the shuffle
25732 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25733 LdVT.getScalarType(), NumElems*SizeRatio);
25734 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25736 // Convert Src0 value
25737 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
25738 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
25739 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25740 for (unsigned i = 0; i != NumElems; ++i)
25741 ShuffleVec[i] = i * SizeRatio;
25743 // Can't shuffle using an illegal type.
25744 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25745 "WideVecVT should be legal");
25746 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
25747 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
25749 // Prepare the new mask
25751 SDValue Mask = Mld->getMask();
25752 if (Mask.getValueType() == VT) {
25753 // Mask and original value have the same type
25754 NewMask = DAG.getBitcast(WideVecVT, Mask);
25755 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25756 for (unsigned i = 0; i != NumElems; ++i)
25757 ShuffleVec[i] = i * SizeRatio;
25758 for (unsigned i = NumElems; i != NumElems * SizeRatio; ++i)
25759 ShuffleVec[i] = NumElems * SizeRatio;
25760 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25761 DAG.getConstant(0, dl, WideVecVT),
25765 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25766 unsigned WidenNumElts = NumElems*SizeRatio;
25767 unsigned MaskNumElts = VT.getVectorNumElements();
25768 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25771 unsigned NumConcat = WidenNumElts / MaskNumElts;
25772 SmallVector<SDValue, 16> Ops(NumConcat);
25773 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25775 for (unsigned i = 1; i != NumConcat; ++i)
25778 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25781 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
25782 Mld->getBasePtr(), NewMask, WideSrc0,
25783 Mld->getMemoryVT(), Mld->getMemOperand(),
25785 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
25786 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
25788 /// PerformMSTORECombine - Resolve truncating stores
25789 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
25790 const X86Subtarget *Subtarget) {
25791 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
25792 if (!Mst->isTruncatingStore())
25795 EVT VT = Mst->getValue().getValueType();
25796 unsigned NumElems = VT.getVectorNumElements();
25797 EVT StVT = Mst->getMemoryVT();
25800 assert(StVT != VT && "Cannot truncate to the same type");
25801 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25802 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25804 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25806 // The truncating store is legal in some cases. For example
25807 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25808 // are designated for truncate store.
25809 // In this case we don't need any further transformations.
25810 if (TLI.isTruncStoreLegal(VT, StVT))
25813 // From, To sizes and ElemCount must be pow of two
25814 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
25815 "Unexpected size for truncating masked store");
25816 // We are going to use the original vector elt for storing.
25817 // Accumulated smaller vector elements must be a multiple of the store size.
25818 assert (((NumElems * FromSz) % ToSz) == 0 &&
25819 "Unexpected ratio for truncating masked store");
25821 unsigned SizeRatio = FromSz / ToSz;
25822 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25824 // Create a type on which we perform the shuffle
25825 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25826 StVT.getScalarType(), NumElems*SizeRatio);
25828 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25830 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
25831 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25832 for (unsigned i = 0; i != NumElems; ++i)
25833 ShuffleVec[i] = i * SizeRatio;
25835 // Can't shuffle using an illegal type.
25836 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25837 "WideVecVT should be legal");
25839 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25840 DAG.getUNDEF(WideVecVT),
25844 SDValue Mask = Mst->getMask();
25845 if (Mask.getValueType() == VT) {
25846 // Mask and original value have the same type
25847 NewMask = DAG.getBitcast(WideVecVT, Mask);
25848 for (unsigned i = 0; i != NumElems; ++i)
25849 ShuffleVec[i] = i * SizeRatio;
25850 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
25851 ShuffleVec[i] = NumElems*SizeRatio;
25852 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25853 DAG.getConstant(0, dl, WideVecVT),
25857 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25858 unsigned WidenNumElts = NumElems*SizeRatio;
25859 unsigned MaskNumElts = VT.getVectorNumElements();
25860 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25863 unsigned NumConcat = WidenNumElts / MaskNumElts;
25864 SmallVector<SDValue, 16> Ops(NumConcat);
25865 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25867 for (unsigned i = 1; i != NumConcat; ++i)
25870 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25873 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal,
25874 Mst->getBasePtr(), NewMask, StVT,
25875 Mst->getMemOperand(), false);
25877 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
25878 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
25879 const X86Subtarget *Subtarget) {
25880 StoreSDNode *St = cast<StoreSDNode>(N);
25881 EVT VT = St->getValue().getValueType();
25882 EVT StVT = St->getMemoryVT();
25884 SDValue StoredVal = St->getOperand(1);
25885 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25887 // If we are saving a concatenation of two XMM registers and 32-byte stores
25888 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
25890 unsigned AddressSpace = St->getAddressSpace();
25891 unsigned Alignment = St->getAlignment();
25892 if (VT.is256BitVector() && StVT == VT &&
25893 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
25894 AddressSpace, Alignment, &Fast) && !Fast) {
25895 unsigned NumElems = VT.getVectorNumElements();
25899 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
25900 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
25903 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25904 SDValue Ptr0 = St->getBasePtr();
25905 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
25907 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
25908 St->getPointerInfo(), St->isVolatile(),
25909 St->isNonTemporal(), Alignment);
25910 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
25911 St->getPointerInfo(), St->isVolatile(),
25912 St->isNonTemporal(),
25913 std::min(16U, Alignment));
25914 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
25917 // Optimize trunc store (of multiple scalars) to shuffle and store.
25918 // First, pack all of the elements in one place. Next, store to memory
25919 // in fewer chunks.
25920 if (St->isTruncatingStore() && VT.isVector()) {
25921 // Check if we can detect an AVG pattern from the truncation. If yes,
25922 // replace the trunc store by a normal store with the result of X86ISD::AVG
25925 detectAVGPattern(St->getValue(), St->getMemoryVT(), DAG, Subtarget, dl);
25927 return DAG.getStore(St->getChain(), dl, Avg, St->getBasePtr(),
25928 St->getPointerInfo(), St->isVolatile(),
25929 St->isNonTemporal(), St->getAlignment());
25931 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25932 unsigned NumElems = VT.getVectorNumElements();
25933 assert(StVT != VT && "Cannot truncate to the same type");
25934 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25935 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25937 // The truncating store is legal in some cases. For example
25938 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25939 // are designated for truncate store.
25940 // In this case we don't need any further transformations.
25941 if (TLI.isTruncStoreLegal(VT, StVT))
25944 // From, To sizes and ElemCount must be pow of two
25945 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
25946 // We are going to use the original vector elt for storing.
25947 // Accumulated smaller vector elements must be a multiple of the store size.
25948 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
25950 unsigned SizeRatio = FromSz / ToSz;
25952 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25954 // Create a type on which we perform the shuffle
25955 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25956 StVT.getScalarType(), NumElems*SizeRatio);
25958 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25960 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
25961 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
25962 for (unsigned i = 0; i != NumElems; ++i)
25963 ShuffleVec[i] = i * SizeRatio;
25965 // Can't shuffle using an illegal type.
25966 if (!TLI.isTypeLegal(WideVecVT))
25969 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25970 DAG.getUNDEF(WideVecVT),
25972 // At this point all of the data is stored at the bottom of the
25973 // register. We now need to save it to mem.
25975 // Find the largest store unit
25976 MVT StoreType = MVT::i8;
25977 for (MVT Tp : MVT::integer_valuetypes()) {
25978 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
25982 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
25983 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
25984 (64 <= NumElems * ToSz))
25985 StoreType = MVT::f64;
25987 // Bitcast the original vector into a vector of store-size units
25988 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
25989 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
25990 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
25991 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
25992 SmallVector<SDValue, 8> Chains;
25993 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, dl,
25994 TLI.getPointerTy(DAG.getDataLayout()));
25995 SDValue Ptr = St->getBasePtr();
25997 // Perform one or more big stores into memory.
25998 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
25999 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
26000 StoreType, ShuffWide,
26001 DAG.getIntPtrConstant(i, dl));
26002 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
26003 St->getPointerInfo(), St->isVolatile(),
26004 St->isNonTemporal(), St->getAlignment());
26005 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
26006 Chains.push_back(Ch);
26009 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
26012 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
26013 // the FP state in cases where an emms may be missing.
26014 // A preferable solution to the general problem is to figure out the right
26015 // places to insert EMMS. This qualifies as a quick hack.
26017 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
26018 if (VT.getSizeInBits() != 64)
26021 const Function *F = DAG.getMachineFunction().getFunction();
26022 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
26024 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
26025 if ((VT.isVector() ||
26026 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
26027 isa<LoadSDNode>(St->getValue()) &&
26028 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
26029 St->getChain().hasOneUse() && !St->isVolatile()) {
26030 SDNode* LdVal = St->getValue().getNode();
26031 LoadSDNode *Ld = nullptr;
26032 int TokenFactorIndex = -1;
26033 SmallVector<SDValue, 8> Ops;
26034 SDNode* ChainVal = St->getChain().getNode();
26035 // Must be a store of a load. We currently handle two cases: the load
26036 // is a direct child, and it's under an intervening TokenFactor. It is
26037 // possible to dig deeper under nested TokenFactors.
26038 if (ChainVal == LdVal)
26039 Ld = cast<LoadSDNode>(St->getChain());
26040 else if (St->getValue().hasOneUse() &&
26041 ChainVal->getOpcode() == ISD::TokenFactor) {
26042 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
26043 if (ChainVal->getOperand(i).getNode() == LdVal) {
26044 TokenFactorIndex = i;
26045 Ld = cast<LoadSDNode>(St->getValue());
26047 Ops.push_back(ChainVal->getOperand(i));
26051 if (!Ld || !ISD::isNormalLoad(Ld))
26054 // If this is not the MMX case, i.e. we are just turning i64 load/store
26055 // into f64 load/store, avoid the transformation if there are multiple
26056 // uses of the loaded value.
26057 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
26062 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
26063 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
26065 if (Subtarget->is64Bit() || F64IsLegal) {
26066 MVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
26067 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
26068 Ld->getPointerInfo(), Ld->isVolatile(),
26069 Ld->isNonTemporal(), Ld->isInvariant(),
26070 Ld->getAlignment());
26071 SDValue NewChain = NewLd.getValue(1);
26072 if (TokenFactorIndex != -1) {
26073 Ops.push_back(NewChain);
26074 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
26076 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
26077 St->getPointerInfo(),
26078 St->isVolatile(), St->isNonTemporal(),
26079 St->getAlignment());
26082 // Otherwise, lower to two pairs of 32-bit loads / stores.
26083 SDValue LoAddr = Ld->getBasePtr();
26084 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
26085 DAG.getConstant(4, LdDL, MVT::i32));
26087 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
26088 Ld->getPointerInfo(),
26089 Ld->isVolatile(), Ld->isNonTemporal(),
26090 Ld->isInvariant(), Ld->getAlignment());
26091 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
26092 Ld->getPointerInfo().getWithOffset(4),
26093 Ld->isVolatile(), Ld->isNonTemporal(),
26095 MinAlign(Ld->getAlignment(), 4));
26097 SDValue NewChain = LoLd.getValue(1);
26098 if (TokenFactorIndex != -1) {
26099 Ops.push_back(LoLd);
26100 Ops.push_back(HiLd);
26101 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
26104 LoAddr = St->getBasePtr();
26105 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
26106 DAG.getConstant(4, StDL, MVT::i32));
26108 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
26109 St->getPointerInfo(),
26110 St->isVolatile(), St->isNonTemporal(),
26111 St->getAlignment());
26112 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
26113 St->getPointerInfo().getWithOffset(4),
26115 St->isNonTemporal(),
26116 MinAlign(St->getAlignment(), 4));
26117 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
26120 // This is similar to the above case, but here we handle a scalar 64-bit
26121 // integer store that is extracted from a vector on a 32-bit target.
26122 // If we have SSE2, then we can treat it like a floating-point double
26123 // to get past legalization. The execution dependencies fixup pass will
26124 // choose the optimal machine instruction for the store if this really is
26125 // an integer or v2f32 rather than an f64.
26126 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
26127 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
26128 SDValue OldExtract = St->getOperand(1);
26129 SDValue ExtOp0 = OldExtract.getOperand(0);
26130 unsigned VecSize = ExtOp0.getValueSizeInBits();
26131 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
26132 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
26133 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
26134 BitCast, OldExtract.getOperand(1));
26135 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
26136 St->getPointerInfo(), St->isVolatile(),
26137 St->isNonTemporal(), St->getAlignment());
26143 /// Return 'true' if this vector operation is "horizontal"
26144 /// and return the operands for the horizontal operation in LHS and RHS. A
26145 /// horizontal operation performs the binary operation on successive elements
26146 /// of its first operand, then on successive elements of its second operand,
26147 /// returning the resulting values in a vector. For example, if
26148 /// A = < float a0, float a1, float a2, float a3 >
26150 /// B = < float b0, float b1, float b2, float b3 >
26151 /// then the result of doing a horizontal operation on A and B is
26152 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
26153 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
26154 /// A horizontal-op B, for some already available A and B, and if so then LHS is
26155 /// set to A, RHS to B, and the routine returns 'true'.
26156 /// Note that the binary operation should have the property that if one of the
26157 /// operands is UNDEF then the result is UNDEF.
26158 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
26159 // Look for the following pattern: if
26160 // A = < float a0, float a1, float a2, float a3 >
26161 // B = < float b0, float b1, float b2, float b3 >
26163 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
26164 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
26165 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
26166 // which is A horizontal-op B.
26168 // At least one of the operands should be a vector shuffle.
26169 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
26170 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
26173 MVT VT = LHS.getSimpleValueType();
26175 assert((VT.is128BitVector() || VT.is256BitVector()) &&
26176 "Unsupported vector type for horizontal add/sub");
26178 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
26179 // operate independently on 128-bit lanes.
26180 unsigned NumElts = VT.getVectorNumElements();
26181 unsigned NumLanes = VT.getSizeInBits()/128;
26182 unsigned NumLaneElts = NumElts / NumLanes;
26183 assert((NumLaneElts % 2 == 0) &&
26184 "Vector type should have an even number of elements in each lane");
26185 unsigned HalfLaneElts = NumLaneElts/2;
26187 // View LHS in the form
26188 // LHS = VECTOR_SHUFFLE A, B, LMask
26189 // If LHS is not a shuffle then pretend it is the shuffle
26190 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
26191 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
26194 SmallVector<int, 16> LMask(NumElts);
26195 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
26196 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
26197 A = LHS.getOperand(0);
26198 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
26199 B = LHS.getOperand(1);
26200 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
26201 std::copy(Mask.begin(), Mask.end(), LMask.begin());
26203 if (LHS.getOpcode() != ISD::UNDEF)
26205 for (unsigned i = 0; i != NumElts; ++i)
26209 // Likewise, view RHS in the form
26210 // RHS = VECTOR_SHUFFLE C, D, RMask
26212 SmallVector<int, 16> RMask(NumElts);
26213 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
26214 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
26215 C = RHS.getOperand(0);
26216 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
26217 D = RHS.getOperand(1);
26218 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
26219 std::copy(Mask.begin(), Mask.end(), RMask.begin());
26221 if (RHS.getOpcode() != ISD::UNDEF)
26223 for (unsigned i = 0; i != NumElts; ++i)
26227 // Check that the shuffles are both shuffling the same vectors.
26228 if (!(A == C && B == D) && !(A == D && B == C))
26231 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
26232 if (!A.getNode() && !B.getNode())
26235 // If A and B occur in reverse order in RHS, then "swap" them (which means
26236 // rewriting the mask).
26238 ShuffleVectorSDNode::commuteMask(RMask);
26240 // At this point LHS and RHS are equivalent to
26241 // LHS = VECTOR_SHUFFLE A, B, LMask
26242 // RHS = VECTOR_SHUFFLE A, B, RMask
26243 // Check that the masks correspond to performing a horizontal operation.
26244 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
26245 for (unsigned i = 0; i != NumLaneElts; ++i) {
26246 int LIdx = LMask[i+l], RIdx = RMask[i+l];
26248 // Ignore any UNDEF components.
26249 if (LIdx < 0 || RIdx < 0 ||
26250 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
26251 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
26254 // Check that successive elements are being operated on. If not, this is
26255 // not a horizontal operation.
26256 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
26257 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
26258 if (!(LIdx == Index && RIdx == Index + 1) &&
26259 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
26264 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
26265 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
26269 /// Do target-specific dag combines on floating point adds.
26270 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
26271 const X86Subtarget *Subtarget) {
26272 EVT VT = N->getValueType(0);
26273 SDValue LHS = N->getOperand(0);
26274 SDValue RHS = N->getOperand(1);
26276 // Try to synthesize horizontal adds from adds of shuffles.
26277 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
26278 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
26279 isHorizontalBinOp(LHS, RHS, true))
26280 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
26284 /// Do target-specific dag combines on floating point subs.
26285 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
26286 const X86Subtarget *Subtarget) {
26287 EVT VT = N->getValueType(0);
26288 SDValue LHS = N->getOperand(0);
26289 SDValue RHS = N->getOperand(1);
26291 // Try to synthesize horizontal subs from subs of shuffles.
26292 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
26293 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
26294 isHorizontalBinOp(LHS, RHS, false))
26295 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
26299 /// Do target-specific dag combines on floating point negations.
26300 static SDValue PerformFNEGCombine(SDNode *N, SelectionDAG &DAG,
26301 const X86Subtarget *Subtarget) {
26302 EVT VT = N->getValueType(0);
26303 EVT SVT = VT.getScalarType();
26304 SDValue Arg = N->getOperand(0);
26307 // Let legalize expand this if it isn't a legal type yet.
26308 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
26311 // If we're negating a FMUL node on a target with FMA, then we can avoid the
26312 // use of a constant by performing (-0 - A*B) instead.
26313 // FIXME: Check rounding control flags as well once it becomes available.
26314 if (Arg.getOpcode() == ISD::FMUL && (SVT == MVT::f32 || SVT == MVT::f64) &&
26315 Arg->getFlags()->hasNoSignedZeros() && Subtarget->hasAnyFMA()) {
26316 SDValue Zero = DAG.getConstantFP(0.0, DL, VT);
26317 return DAG.getNode(X86ISD::FNMSUB, DL, VT, Arg.getOperand(0),
26318 Arg.getOperand(1), Zero);
26321 // If we're negating a FMA node, then we can adjust the
26322 // instruction to include the extra negation.
26323 if (Arg.hasOneUse()) {
26324 switch (Arg.getOpcode()) {
26325 case X86ISD::FMADD:
26326 return DAG.getNode(X86ISD::FNMSUB, DL, VT, Arg.getOperand(0),
26327 Arg.getOperand(1), Arg.getOperand(2));
26328 case X86ISD::FMSUB:
26329 return DAG.getNode(X86ISD::FNMADD, DL, VT, Arg.getOperand(0),
26330 Arg.getOperand(1), Arg.getOperand(2));
26331 case X86ISD::FNMADD:
26332 return DAG.getNode(X86ISD::FMSUB, DL, VT, Arg.getOperand(0),
26333 Arg.getOperand(1), Arg.getOperand(2));
26334 case X86ISD::FNMSUB:
26335 return DAG.getNode(X86ISD::FMADD, DL, VT, Arg.getOperand(0),
26336 Arg.getOperand(1), Arg.getOperand(2));
26342 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
26343 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG,
26344 const X86Subtarget *Subtarget) {
26345 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
26347 // F[X]OR(0.0, x) -> x
26348 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
26349 if (C->getValueAPF().isPosZero())
26350 return N->getOperand(1);
26352 // F[X]OR(x, 0.0) -> x
26353 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
26354 if (C->getValueAPF().isPosZero())
26355 return N->getOperand(0);
26357 EVT VT = N->getValueType(0);
26358 if (VT.is512BitVector() && !Subtarget->hasDQI()) {
26360 MVT IntScalar = MVT::getIntegerVT(VT.getScalarSizeInBits());
26361 MVT IntVT = MVT::getVectorVT(IntScalar, VT.getVectorNumElements());
26363 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(0));
26364 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(1));
26365 unsigned IntOpcode = (N->getOpcode() == X86ISD::FOR) ? ISD::OR : ISD::XOR;
26366 SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1);
26367 return DAG.getNode(ISD::BITCAST, dl, VT, IntOp);
26372 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
26373 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
26374 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
26376 // Only perform optimizations if UnsafeMath is used.
26377 if (!DAG.getTarget().Options.UnsafeFPMath)
26380 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
26381 // into FMINC and FMAXC, which are Commutative operations.
26382 unsigned NewOp = 0;
26383 switch (N->getOpcode()) {
26384 default: llvm_unreachable("unknown opcode");
26385 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
26386 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
26389 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
26390 N->getOperand(0), N->getOperand(1));
26393 /// Do target-specific dag combines on X86ISD::FAND nodes.
26394 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
26395 // FAND(0.0, x) -> 0.0
26396 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
26397 if (C->getValueAPF().isPosZero())
26398 return N->getOperand(0);
26400 // FAND(x, 0.0) -> 0.0
26401 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
26402 if (C->getValueAPF().isPosZero())
26403 return N->getOperand(1);
26408 /// Do target-specific dag combines on X86ISD::FANDN nodes
26409 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
26410 // FANDN(0.0, x) -> x
26411 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
26412 if (C->getValueAPF().isPosZero())
26413 return N->getOperand(1);
26415 // FANDN(x, 0.0) -> 0.0
26416 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
26417 if (C->getValueAPF().isPosZero())
26418 return N->getOperand(1);
26423 static SDValue PerformBTCombine(SDNode *N,
26425 TargetLowering::DAGCombinerInfo &DCI) {
26426 // BT ignores high bits in the bit index operand.
26427 SDValue Op1 = N->getOperand(1);
26428 if (Op1.hasOneUse()) {
26429 unsigned BitWidth = Op1.getValueSizeInBits();
26430 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
26431 APInt KnownZero, KnownOne;
26432 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
26433 !DCI.isBeforeLegalizeOps());
26434 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26435 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
26436 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
26437 DCI.CommitTargetLoweringOpt(TLO);
26442 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
26443 SDValue Op = N->getOperand(0);
26444 if (Op.getOpcode() == ISD::BITCAST)
26445 Op = Op.getOperand(0);
26446 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
26447 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
26448 VT.getVectorElementType().getSizeInBits() ==
26449 OpVT.getVectorElementType().getSizeInBits()) {
26450 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
26455 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
26456 const X86Subtarget *Subtarget) {
26457 EVT VT = N->getValueType(0);
26458 if (!VT.isVector())
26461 SDValue N0 = N->getOperand(0);
26462 SDValue N1 = N->getOperand(1);
26463 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
26466 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
26467 // both SSE and AVX2 since there is no sign-extended shift right
26468 // operation on a vector with 64-bit elements.
26469 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
26470 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
26471 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
26472 N0.getOpcode() == ISD::SIGN_EXTEND)) {
26473 SDValue N00 = N0.getOperand(0);
26475 // EXTLOAD has a better solution on AVX2,
26476 // it may be replaced with X86ISD::VSEXT node.
26477 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
26478 if (!ISD::isNormalLoad(N00.getNode()))
26481 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
26482 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
26484 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
26490 /// sext(add_nsw(x, C)) --> add(sext(x), C_sext)
26491 /// Promoting a sign extension ahead of an 'add nsw' exposes opportunities
26492 /// to combine math ops, use an LEA, or use a complex addressing mode. This can
26493 /// eliminate extend, add, and shift instructions.
26494 static SDValue promoteSextBeforeAddNSW(SDNode *Sext, SelectionDAG &DAG,
26495 const X86Subtarget *Subtarget) {
26496 // TODO: This should be valid for other integer types.
26497 EVT VT = Sext->getValueType(0);
26498 if (VT != MVT::i64)
26501 // We need an 'add nsw' feeding into the 'sext'.
26502 SDValue Add = Sext->getOperand(0);
26503 if (Add.getOpcode() != ISD::ADD || !Add->getFlags()->hasNoSignedWrap())
26506 // Having a constant operand to the 'add' ensures that we are not increasing
26507 // the instruction count because the constant is extended for free below.
26508 // A constant operand can also become the displacement field of an LEA.
26509 auto *AddOp1 = dyn_cast<ConstantSDNode>(Add.getOperand(1));
26513 // Don't make the 'add' bigger if there's no hope of combining it with some
26514 // other 'add' or 'shl' instruction.
26515 // TODO: It may be profitable to generate simpler LEA instructions in place
26516 // of single 'add' instructions, but the cost model for selecting an LEA
26517 // currently has a high threshold.
26518 bool HasLEAPotential = false;
26519 for (auto *User : Sext->uses()) {
26520 if (User->getOpcode() == ISD::ADD || User->getOpcode() == ISD::SHL) {
26521 HasLEAPotential = true;
26525 if (!HasLEAPotential)
26528 // Everything looks good, so pull the 'sext' ahead of the 'add'.
26529 int64_t AddConstant = AddOp1->getSExtValue();
26530 SDValue AddOp0 = Add.getOperand(0);
26531 SDValue NewSext = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(Sext), VT, AddOp0);
26532 SDValue NewConstant = DAG.getConstant(AddConstant, SDLoc(Add), VT);
26534 // The wider add is guaranteed to not wrap because both operands are
26537 Flags.setNoSignedWrap(true);
26538 return DAG.getNode(ISD::ADD, SDLoc(Add), VT, NewSext, NewConstant, &Flags);
26541 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
26542 TargetLowering::DAGCombinerInfo &DCI,
26543 const X86Subtarget *Subtarget) {
26544 SDValue N0 = N->getOperand(0);
26545 EVT VT = N->getValueType(0);
26546 EVT SVT = VT.getScalarType();
26547 EVT InVT = N0.getValueType();
26548 EVT InSVT = InVT.getScalarType();
26551 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
26552 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
26553 // This exposes the sext to the sdivrem lowering, so that it directly extends
26554 // from AH (which we otherwise need to do contortions to access).
26555 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
26556 InVT == MVT::i8 && VT == MVT::i32) {
26557 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
26558 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
26559 N0.getOperand(0), N0.getOperand(1));
26560 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
26561 return R.getValue(1);
26564 if (!DCI.isBeforeLegalizeOps()) {
26565 if (InVT == MVT::i1) {
26566 SDValue Zero = DAG.getConstant(0, DL, VT);
26568 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
26569 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
26574 if (VT.isVector() && Subtarget->hasSSE2()) {
26575 auto ExtendVecSize = [&DAG](SDLoc DL, SDValue N, unsigned Size) {
26576 EVT InVT = N.getValueType();
26577 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
26578 Size / InVT.getScalarSizeInBits());
26579 SmallVector<SDValue, 8> Opnds(Size / InVT.getSizeInBits(),
26580 DAG.getUNDEF(InVT));
26582 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
26585 // If target-size is less than 128-bits, extend to a type that would extend
26586 // to 128 bits, extend that and extract the original target vector.
26587 if (VT.getSizeInBits() < 128 && !(128 % VT.getSizeInBits()) &&
26588 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26589 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26590 unsigned Scale = 128 / VT.getSizeInBits();
26592 EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits());
26593 SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits());
26594 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);
26595 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SExt,
26596 DAG.getIntPtrConstant(0, DL));
26599 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
26600 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
26601 if (VT.getSizeInBits() == 128 &&
26602 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26603 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26604 SDValue ExOp = ExtendVecSize(DL, N0, 128);
26605 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
26608 // On pre-AVX2 targets, split into 128-bit nodes of
26609 // ISD::SIGN_EXTEND_VECTOR_INREG.
26610 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
26611 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26612 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26613 unsigned NumVecs = VT.getSizeInBits() / 128;
26614 unsigned NumSubElts = 128 / SVT.getSizeInBits();
26615 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
26616 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
26618 SmallVector<SDValue, 8> Opnds;
26619 for (unsigned i = 0, Offset = 0; i != NumVecs;
26620 ++i, Offset += NumSubElts) {
26621 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
26622 DAG.getIntPtrConstant(Offset, DL));
26623 SrcVec = ExtendVecSize(DL, SrcVec, 128);
26624 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
26625 Opnds.push_back(SrcVec);
26627 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
26631 if (Subtarget->hasAVX() && VT.is256BitVector())
26632 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
26635 if (SDValue NewAdd = promoteSextBeforeAddNSW(N, DAG, Subtarget))
26641 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
26642 const X86Subtarget* Subtarget) {
26644 EVT VT = N->getValueType(0);
26646 // Let legalize expand this if it isn't a legal type yet.
26647 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
26650 EVT ScalarVT = VT.getScalarType();
26651 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) || !Subtarget->hasAnyFMA())
26654 SDValue A = N->getOperand(0);
26655 SDValue B = N->getOperand(1);
26656 SDValue C = N->getOperand(2);
26658 bool NegA = (A.getOpcode() == ISD::FNEG);
26659 bool NegB = (B.getOpcode() == ISD::FNEG);
26660 bool NegC = (C.getOpcode() == ISD::FNEG);
26662 // Negative multiplication when NegA xor NegB
26663 bool NegMul = (NegA != NegB);
26665 A = A.getOperand(0);
26667 B = B.getOperand(0);
26669 C = C.getOperand(0);
26673 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
26675 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
26677 return DAG.getNode(Opcode, dl, VT, A, B, C);
26680 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
26681 TargetLowering::DAGCombinerInfo &DCI,
26682 const X86Subtarget *Subtarget) {
26683 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
26684 // (and (i32 x86isd::setcc_carry), 1)
26685 // This eliminates the zext. This transformation is necessary because
26686 // ISD::SETCC is always legalized to i8.
26688 SDValue N0 = N->getOperand(0);
26689 EVT VT = N->getValueType(0);
26691 if (N0.getOpcode() == ISD::AND &&
26693 N0.getOperand(0).hasOneUse()) {
26694 SDValue N00 = N0.getOperand(0);
26695 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
26696 if (!isOneConstant(N0.getOperand(1)))
26698 return DAG.getNode(ISD::AND, dl, VT,
26699 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
26700 N00.getOperand(0), N00.getOperand(1)),
26701 DAG.getConstant(1, dl, VT));
26705 if (N0.getOpcode() == ISD::TRUNCATE &&
26707 N0.getOperand(0).hasOneUse()) {
26708 SDValue N00 = N0.getOperand(0);
26709 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
26710 return DAG.getNode(ISD::AND, dl, VT,
26711 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
26712 N00.getOperand(0), N00.getOperand(1)),
26713 DAG.getConstant(1, dl, VT));
26717 if (VT.is256BitVector())
26718 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
26721 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
26722 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
26723 // This exposes the zext to the udivrem lowering, so that it directly extends
26724 // from AH (which we otherwise need to do contortions to access).
26725 if (N0.getOpcode() == ISD::UDIVREM &&
26726 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
26727 (VT == MVT::i32 || VT == MVT::i64)) {
26728 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
26729 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
26730 N0.getOperand(0), N0.getOperand(1));
26731 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
26732 return R.getValue(1);
26738 // Optimize x == -y --> x+y == 0
26739 // x != -y --> x+y != 0
26740 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
26741 const X86Subtarget* Subtarget) {
26742 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
26743 SDValue LHS = N->getOperand(0);
26744 SDValue RHS = N->getOperand(1);
26745 EVT VT = N->getValueType(0);
26748 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
26749 if (isNullConstant(LHS.getOperand(0)) && LHS.hasOneUse()) {
26750 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
26751 LHS.getOperand(1));
26752 return DAG.getSetCC(DL, N->getValueType(0), addV,
26753 DAG.getConstant(0, DL, addV.getValueType()), CC);
26755 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
26756 if (isNullConstant(RHS.getOperand(0)) && RHS.hasOneUse()) {
26757 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
26758 RHS.getOperand(1));
26759 return DAG.getSetCC(DL, N->getValueType(0), addV,
26760 DAG.getConstant(0, DL, addV.getValueType()), CC);
26763 if (VT.getScalarType() == MVT::i1 &&
26764 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
26766 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
26767 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
26768 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
26770 if (!IsSEXT0 || !IsVZero1) {
26771 // Swap the operands and update the condition code.
26772 std::swap(LHS, RHS);
26773 CC = ISD::getSetCCSwappedOperands(CC);
26775 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
26776 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
26777 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
26780 if (IsSEXT0 && IsVZero1) {
26781 assert(VT == LHS.getOperand(0).getValueType() &&
26782 "Uexpected operand type");
26783 if (CC == ISD::SETGT)
26784 return DAG.getConstant(0, DL, VT);
26785 if (CC == ISD::SETLE)
26786 return DAG.getConstant(1, DL, VT);
26787 if (CC == ISD::SETEQ || CC == ISD::SETGE)
26788 return DAG.getNOT(DL, LHS.getOperand(0), VT);
26790 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
26791 "Unexpected condition code!");
26792 return LHS.getOperand(0);
26799 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
26800 SDValue V0 = N->getOperand(0);
26801 SDValue V1 = N->getOperand(1);
26803 EVT VT = N->getValueType(0);
26805 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
26806 // operands and changing the mask to 1. This saves us a bunch of
26807 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
26808 // x86InstrInfo knows how to commute this back after instruction selection
26809 // if it would help register allocation.
26811 // TODO: If optimizing for size or a processor that doesn't suffer from
26812 // partial register update stalls, this should be transformed into a MOVSD
26813 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
26815 if (VT == MVT::v2f64)
26816 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
26817 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
26818 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
26819 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
26825 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
26826 // as "sbb reg,reg", since it can be extended without zext and produces
26827 // an all-ones bit which is more useful than 0/1 in some cases.
26828 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
26831 return DAG.getNode(ISD::AND, DL, VT,
26832 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
26833 DAG.getConstant(X86::COND_B, DL, MVT::i8),
26835 DAG.getConstant(1, DL, VT));
26836 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
26837 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
26838 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
26839 DAG.getConstant(X86::COND_B, DL, MVT::i8),
26843 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
26844 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
26845 TargetLowering::DAGCombinerInfo &DCI,
26846 const X86Subtarget *Subtarget) {
26848 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
26849 SDValue EFLAGS = N->getOperand(1);
26851 if (CC == X86::COND_A) {
26852 // Try to convert COND_A into COND_B in an attempt to facilitate
26853 // materializing "setb reg".
26855 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
26856 // cannot take an immediate as its first operand.
26858 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
26859 EFLAGS.getValueType().isInteger() &&
26860 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
26861 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
26862 EFLAGS.getNode()->getVTList(),
26863 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
26864 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
26865 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
26869 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
26870 // a zext and produces an all-ones bit which is more useful than 0/1 in some
26872 if (CC == X86::COND_B)
26873 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
26875 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26876 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26877 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
26883 // Optimize branch condition evaluation.
26885 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
26886 TargetLowering::DAGCombinerInfo &DCI,
26887 const X86Subtarget *Subtarget) {
26889 SDValue Chain = N->getOperand(0);
26890 SDValue Dest = N->getOperand(1);
26891 SDValue EFLAGS = N->getOperand(3);
26892 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
26894 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26895 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26896 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
26903 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
26904 SelectionDAG &DAG) {
26905 // Take advantage of vector comparisons producing 0 or -1 in each lane to
26906 // optimize away operation when it's from a constant.
26908 // The general transformation is:
26909 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
26910 // AND(VECTOR_CMP(x,y), constant2)
26911 // constant2 = UNARYOP(constant)
26913 // Early exit if this isn't a vector operation, the operand of the
26914 // unary operation isn't a bitwise AND, or if the sizes of the operations
26915 // aren't the same.
26916 EVT VT = N->getValueType(0);
26917 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
26918 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
26919 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
26922 // Now check that the other operand of the AND is a constant. We could
26923 // make the transformation for non-constant splats as well, but it's unclear
26924 // that would be a benefit as it would not eliminate any operations, just
26925 // perform one more step in scalar code before moving to the vector unit.
26926 if (BuildVectorSDNode *BV =
26927 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
26928 // Bail out if the vector isn't a constant.
26929 if (!BV->isConstant())
26932 // Everything checks out. Build up the new and improved node.
26934 EVT IntVT = BV->getValueType(0);
26935 // Create a new constant of the appropriate type for the transformed
26937 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
26938 // The AND node needs bitcasts to/from an integer vector type around it.
26939 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
26940 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
26941 N->getOperand(0)->getOperand(0), MaskConst);
26942 SDValue Res = DAG.getBitcast(VT, NewAnd);
26949 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26950 const X86Subtarget *Subtarget) {
26951 SDValue Op0 = N->getOperand(0);
26952 EVT VT = N->getValueType(0);
26953 EVT InVT = Op0.getValueType();
26954 EVT InSVT = InVT.getScalarType();
26955 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26957 // UINT_TO_FP(vXi8) -> SINT_TO_FP(ZEXT(vXi8 to vXi32))
26958 // UINT_TO_FP(vXi16) -> SINT_TO_FP(ZEXT(vXi16 to vXi32))
26959 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26961 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26962 InVT.getVectorNumElements());
26963 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
26965 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
26966 return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P);
26968 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26974 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26975 const X86Subtarget *Subtarget) {
26976 // First try to optimize away the conversion entirely when it's
26977 // conditionally from a constant. Vectors only.
26978 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
26981 // Now move on to more general possibilities.
26982 SDValue Op0 = N->getOperand(0);
26983 EVT VT = N->getValueType(0);
26984 EVT InVT = Op0.getValueType();
26985 EVT InSVT = InVT.getScalarType();
26987 // SINT_TO_FP(vXi8) -> SINT_TO_FP(SEXT(vXi8 to vXi32))
26988 // SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
26989 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26991 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26992 InVT.getVectorNumElements());
26993 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
26994 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26997 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
26998 // a 32-bit target where SSE doesn't support i64->FP operations.
26999 if (!Subtarget->useSoftFloat() && Op0.getOpcode() == ISD::LOAD) {
27000 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
27001 EVT LdVT = Ld->getValueType(0);
27003 // This transformation is not supported if the result type is f16
27004 if (VT == MVT::f16)
27007 if (!Ld->isVolatile() && !VT.isVector() &&
27008 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
27009 !Subtarget->is64Bit() && LdVT == MVT::i64) {
27010 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
27011 SDValue(N, 0), LdVT, Ld->getChain(), Op0, DAG);
27012 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
27019 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
27020 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
27021 X86TargetLowering::DAGCombinerInfo &DCI) {
27022 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
27023 // the result is either zero or one (depending on the input carry bit).
27024 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
27025 if (X86::isZeroNode(N->getOperand(0)) &&
27026 X86::isZeroNode(N->getOperand(1)) &&
27027 // We don't have a good way to replace an EFLAGS use, so only do this when
27029 SDValue(N, 1).use_empty()) {
27031 EVT VT = N->getValueType(0);
27032 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
27033 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
27034 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
27035 DAG.getConstant(X86::COND_B, DL,
27038 DAG.getConstant(1, DL, VT));
27039 return DCI.CombineTo(N, Res1, CarryOut);
27045 // fold (add Y, (sete X, 0)) -> adc 0, Y
27046 // (add Y, (setne X, 0)) -> sbb -1, Y
27047 // (sub (sete X, 0), Y) -> sbb 0, Y
27048 // (sub (setne X, 0), Y) -> adc -1, Y
27049 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
27052 // Look through ZExts.
27053 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
27054 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
27057 SDValue SetCC = Ext.getOperand(0);
27058 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
27061 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
27062 if (CC != X86::COND_E && CC != X86::COND_NE)
27065 SDValue Cmp = SetCC.getOperand(1);
27066 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
27067 !X86::isZeroNode(Cmp.getOperand(1)) ||
27068 !Cmp.getOperand(0).getValueType().isInteger())
27071 SDValue CmpOp0 = Cmp.getOperand(0);
27072 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
27073 DAG.getConstant(1, DL, CmpOp0.getValueType()));
27075 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
27076 if (CC == X86::COND_NE)
27077 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
27078 DL, OtherVal.getValueType(), OtherVal,
27079 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
27081 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
27082 DL, OtherVal.getValueType(), OtherVal,
27083 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
27086 /// PerformADDCombine - Do target-specific dag combines on integer adds.
27087 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
27088 const X86Subtarget *Subtarget) {
27089 EVT VT = N->getValueType(0);
27090 SDValue Op0 = N->getOperand(0);
27091 SDValue Op1 = N->getOperand(1);
27093 // Try to synthesize horizontal adds from adds of shuffles.
27094 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
27095 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
27096 isHorizontalBinOp(Op0, Op1, true))
27097 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
27099 return OptimizeConditionalInDecrement(N, DAG);
27102 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
27103 const X86Subtarget *Subtarget) {
27104 SDValue Op0 = N->getOperand(0);
27105 SDValue Op1 = N->getOperand(1);
27107 // X86 can't encode an immediate LHS of a sub. See if we can push the
27108 // negation into a preceding instruction.
27109 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
27110 // If the RHS of the sub is a XOR with one use and a constant, invert the
27111 // immediate. Then add one to the LHS of the sub so we can turn
27112 // X-Y -> X+~Y+1, saving one register.
27113 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
27114 isa<ConstantSDNode>(Op1.getOperand(1))) {
27115 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
27116 EVT VT = Op0.getValueType();
27117 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
27119 DAG.getConstant(~XorC, SDLoc(Op1), VT));
27120 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
27121 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
27125 // Try to synthesize horizontal adds from adds of shuffles.
27126 EVT VT = N->getValueType(0);
27127 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
27128 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
27129 isHorizontalBinOp(Op0, Op1, true))
27130 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
27132 return OptimizeConditionalInDecrement(N, DAG);
27135 /// performVZEXTCombine - Performs build vector combines
27136 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
27137 TargetLowering::DAGCombinerInfo &DCI,
27138 const X86Subtarget *Subtarget) {
27140 MVT VT = N->getSimpleValueType(0);
27141 SDValue Op = N->getOperand(0);
27142 MVT OpVT = Op.getSimpleValueType();
27143 MVT OpEltVT = OpVT.getVectorElementType();
27144 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
27146 // (vzext (bitcast (vzext (x)) -> (vzext x)
27148 while (V.getOpcode() == ISD::BITCAST)
27149 V = V.getOperand(0);
27151 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
27152 MVT InnerVT = V.getSimpleValueType();
27153 MVT InnerEltVT = InnerVT.getVectorElementType();
27155 // If the element sizes match exactly, we can just do one larger vzext. This
27156 // is always an exact type match as vzext operates on integer types.
27157 if (OpEltVT == InnerEltVT) {
27158 assert(OpVT == InnerVT && "Types must match for vzext!");
27159 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
27162 // The only other way we can combine them is if only a single element of the
27163 // inner vzext is used in the input to the outer vzext.
27164 if (InnerEltVT.getSizeInBits() < InputBits)
27167 // In this case, the inner vzext is completely dead because we're going to
27168 // only look at bits inside of the low element. Just do the outer vzext on
27169 // a bitcast of the input to the inner.
27170 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
27173 // Check if we can bypass extracting and re-inserting an element of an input
27174 // vector. Essentially:
27175 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
27176 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
27177 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
27178 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
27179 SDValue ExtractedV = V.getOperand(0);
27180 SDValue OrigV = ExtractedV.getOperand(0);
27181 if (isNullConstant(ExtractedV.getOperand(1))) {
27182 MVT OrigVT = OrigV.getSimpleValueType();
27183 // Extract a subvector if necessary...
27184 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
27185 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
27186 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
27187 OrigVT.getVectorNumElements() / Ratio);
27188 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
27189 DAG.getIntPtrConstant(0, DL));
27191 Op = DAG.getBitcast(OpVT, OrigV);
27192 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
27199 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
27200 DAGCombinerInfo &DCI) const {
27201 SelectionDAG &DAG = DCI.DAG;
27202 switch (N->getOpcode()) {
27204 case ISD::EXTRACT_VECTOR_ELT:
27205 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
27208 case X86ISD::SHRUNKBLEND:
27209 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
27210 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG, Subtarget);
27211 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
27212 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
27213 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
27214 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
27215 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
27218 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
27219 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
27220 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
27221 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
27222 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
27223 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
27224 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
27225 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
27226 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
27227 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, Subtarget);
27228 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
27229 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
27230 case ISD::FNEG: return PerformFNEGCombine(N, DAG, Subtarget);
27231 case ISD::TRUNCATE: return PerformTRUNCATECombine(N, DAG, Subtarget);
27233 case X86ISD::FOR: return PerformFORCombine(N, DAG, Subtarget);
27235 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
27236 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
27237 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
27238 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
27239 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
27240 case ISD::ANY_EXTEND:
27241 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
27242 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
27243 case ISD::SIGN_EXTEND_INREG:
27244 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
27245 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
27246 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
27247 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
27248 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
27249 case X86ISD::SHUFP: // Handle all target specific shuffles
27250 case X86ISD::PALIGNR:
27251 case X86ISD::UNPCKH:
27252 case X86ISD::UNPCKL:
27253 case X86ISD::MOVHLPS:
27254 case X86ISD::MOVLHPS:
27255 case X86ISD::PSHUFB:
27256 case X86ISD::PSHUFD:
27257 case X86ISD::PSHUFHW:
27258 case X86ISD::PSHUFLW:
27259 case X86ISD::MOVSS:
27260 case X86ISD::MOVSD:
27261 case X86ISD::VPERMILPI:
27262 case X86ISD::VPERM2X128:
27263 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
27264 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
27265 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
27271 /// isTypeDesirableForOp - Return true if the target has native support for
27272 /// the specified value type and it is 'desirable' to use the type for the
27273 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
27274 /// instruction encodings are longer and some i16 instructions are slow.
27275 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
27276 if (!isTypeLegal(VT))
27278 if (VT != MVT::i16)
27285 case ISD::SIGN_EXTEND:
27286 case ISD::ZERO_EXTEND:
27287 case ISD::ANY_EXTEND:
27300 /// IsDesirableToPromoteOp - This method query the target whether it is
27301 /// beneficial for dag combiner to promote the specified node. If true, it
27302 /// should return the desired promotion type by reference.
27303 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
27304 EVT VT = Op.getValueType();
27305 if (VT != MVT::i16)
27308 bool Promote = false;
27309 bool Commute = false;
27310 switch (Op.getOpcode()) {
27313 LoadSDNode *LD = cast<LoadSDNode>(Op);
27314 // If the non-extending load has a single use and it's not live out, then it
27315 // might be folded.
27316 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
27317 Op.hasOneUse()*/) {
27318 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
27319 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
27320 // The only case where we'd want to promote LOAD (rather then it being
27321 // promoted as an operand is when it's only use is liveout.
27322 if (UI->getOpcode() != ISD::CopyToReg)
27329 case ISD::SIGN_EXTEND:
27330 case ISD::ZERO_EXTEND:
27331 case ISD::ANY_EXTEND:
27336 SDValue N0 = Op.getOperand(0);
27337 // Look out for (store (shl (load), x)).
27338 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
27351 SDValue N0 = Op.getOperand(0);
27352 SDValue N1 = Op.getOperand(1);
27353 if (!Commute && MayFoldLoad(N1))
27355 // Avoid disabling potential load folding opportunities.
27356 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
27358 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
27368 //===----------------------------------------------------------------------===//
27369 // X86 Inline Assembly Support
27370 //===----------------------------------------------------------------------===//
27372 // Helper to match a string separated by whitespace.
27373 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
27374 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
27376 for (StringRef Piece : Pieces) {
27377 if (!S.startswith(Piece)) // Check if the piece matches.
27380 S = S.substr(Piece.size());
27381 StringRef::size_type Pos = S.find_first_not_of(" \t");
27382 if (Pos == 0) // We matched a prefix.
27391 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
27393 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
27394 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
27395 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
27396 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
27398 if (AsmPieces.size() == 3)
27400 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
27407 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
27408 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
27410 std::string AsmStr = IA->getAsmString();
27412 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
27413 if (!Ty || Ty->getBitWidth() % 16 != 0)
27416 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
27417 SmallVector<StringRef, 4> AsmPieces;
27418 SplitString(AsmStr, AsmPieces, ";\n");
27420 switch (AsmPieces.size()) {
27421 default: return false;
27423 // FIXME: this should verify that we are targeting a 486 or better. If not,
27424 // we will turn this bswap into something that will be lowered to logical
27425 // ops instead of emitting the bswap asm. For now, we don't support 486 or
27426 // lower so don't worry about this.
27428 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
27429 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
27430 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
27431 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
27432 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
27433 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
27434 // No need to check constraints, nothing other than the equivalent of
27435 // "=r,0" would be valid here.
27436 return IntrinsicLowering::LowerToByteSwap(CI);
27439 // rorw $$8, ${0:w} --> llvm.bswap.i16
27440 if (CI->getType()->isIntegerTy(16) &&
27441 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
27442 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
27443 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
27445 StringRef ConstraintsStr = IA->getConstraintString();
27446 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
27447 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
27448 if (clobbersFlagRegisters(AsmPieces))
27449 return IntrinsicLowering::LowerToByteSwap(CI);
27453 if (CI->getType()->isIntegerTy(32) &&
27454 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
27455 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
27456 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
27457 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
27459 StringRef ConstraintsStr = IA->getConstraintString();
27460 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
27461 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
27462 if (clobbersFlagRegisters(AsmPieces))
27463 return IntrinsicLowering::LowerToByteSwap(CI);
27466 if (CI->getType()->isIntegerTy(64)) {
27467 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
27468 if (Constraints.size() >= 2 &&
27469 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
27470 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
27471 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
27472 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
27473 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
27474 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
27475 return IntrinsicLowering::LowerToByteSwap(CI);
27483 /// getConstraintType - Given a constraint letter, return the type of
27484 /// constraint it is for this target.
27485 X86TargetLowering::ConstraintType
27486 X86TargetLowering::getConstraintType(StringRef Constraint) const {
27487 if (Constraint.size() == 1) {
27488 switch (Constraint[0]) {
27499 return C_RegisterClass;
27523 return TargetLowering::getConstraintType(Constraint);
27526 /// Examine constraint type and operand type and determine a weight value.
27527 /// This object must already have been set up with the operand type
27528 /// and the current alternative constraint selected.
27529 TargetLowering::ConstraintWeight
27530 X86TargetLowering::getSingleConstraintMatchWeight(
27531 AsmOperandInfo &info, const char *constraint) const {
27532 ConstraintWeight weight = CW_Invalid;
27533 Value *CallOperandVal = info.CallOperandVal;
27534 // If we don't have a value, we can't do a match,
27535 // but allow it at the lowest weight.
27536 if (!CallOperandVal)
27538 Type *type = CallOperandVal->getType();
27539 // Look at the constraint type.
27540 switch (*constraint) {
27542 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
27553 if (CallOperandVal->getType()->isIntegerTy())
27554 weight = CW_SpecificReg;
27559 if (type->isFloatingPointTy())
27560 weight = CW_SpecificReg;
27563 if (type->isX86_MMXTy() && Subtarget->hasMMX())
27564 weight = CW_SpecificReg;
27568 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
27569 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
27570 weight = CW_Register;
27573 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
27574 if (C->getZExtValue() <= 31)
27575 weight = CW_Constant;
27579 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27580 if (C->getZExtValue() <= 63)
27581 weight = CW_Constant;
27585 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27586 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
27587 weight = CW_Constant;
27591 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27592 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
27593 weight = CW_Constant;
27597 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27598 if (C->getZExtValue() <= 3)
27599 weight = CW_Constant;
27603 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27604 if (C->getZExtValue() <= 0xff)
27605 weight = CW_Constant;
27610 if (isa<ConstantFP>(CallOperandVal)) {
27611 weight = CW_Constant;
27615 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27616 if ((C->getSExtValue() >= -0x80000000LL) &&
27617 (C->getSExtValue() <= 0x7fffffffLL))
27618 weight = CW_Constant;
27622 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27623 if (C->getZExtValue() <= 0xffffffff)
27624 weight = CW_Constant;
27631 /// LowerXConstraint - try to replace an X constraint, which matches anything,
27632 /// with another that has more specific requirements based on the type of the
27633 /// corresponding operand.
27634 const char *X86TargetLowering::
27635 LowerXConstraint(EVT ConstraintVT) const {
27636 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
27637 // 'f' like normal targets.
27638 if (ConstraintVT.isFloatingPoint()) {
27639 if (Subtarget->hasSSE2())
27641 if (Subtarget->hasSSE1())
27645 return TargetLowering::LowerXConstraint(ConstraintVT);
27648 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
27649 /// vector. If it is invalid, don't add anything to Ops.
27650 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
27651 std::string &Constraint,
27652 std::vector<SDValue>&Ops,
27653 SelectionDAG &DAG) const {
27656 // Only support length 1 constraints for now.
27657 if (Constraint.length() > 1) return;
27659 char ConstraintLetter = Constraint[0];
27660 switch (ConstraintLetter) {
27663 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27664 if (C->getZExtValue() <= 31) {
27665 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27666 Op.getValueType());
27672 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27673 if (C->getZExtValue() <= 63) {
27674 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27675 Op.getValueType());
27681 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27682 if (isInt<8>(C->getSExtValue())) {
27683 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27684 Op.getValueType());
27690 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27691 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
27692 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
27693 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
27694 Op.getValueType());
27700 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27701 if (C->getZExtValue() <= 3) {
27702 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27703 Op.getValueType());
27709 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27710 if (C->getZExtValue() <= 255) {
27711 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27712 Op.getValueType());
27718 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27719 if (C->getZExtValue() <= 127) {
27720 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27721 Op.getValueType());
27727 // 32-bit signed value
27728 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27729 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
27730 C->getSExtValue())) {
27731 // Widen to 64 bits here to get it sign extended.
27732 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
27735 // FIXME gcc accepts some relocatable values here too, but only in certain
27736 // memory models; it's complicated.
27741 // 32-bit unsigned value
27742 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27743 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
27744 C->getZExtValue())) {
27745 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27746 Op.getValueType());
27750 // FIXME gcc accepts some relocatable values here too, but only in certain
27751 // memory models; it's complicated.
27755 // Literal immediates are always ok.
27756 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
27757 // Widen to 64 bits here to get it sign extended.
27758 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
27762 // In any sort of PIC mode addresses need to be computed at runtime by
27763 // adding in a register or some sort of table lookup. These can't
27764 // be used as immediates.
27765 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
27768 // If we are in non-pic codegen mode, we allow the address of a global (with
27769 // an optional displacement) to be used with 'i'.
27770 GlobalAddressSDNode *GA = nullptr;
27771 int64_t Offset = 0;
27773 // Match either (GA), (GA+C), (GA+C1+C2), etc.
27775 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
27776 Offset += GA->getOffset();
27778 } else if (Op.getOpcode() == ISD::ADD) {
27779 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
27780 Offset += C->getZExtValue();
27781 Op = Op.getOperand(0);
27784 } else if (Op.getOpcode() == ISD::SUB) {
27785 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
27786 Offset += -C->getZExtValue();
27787 Op = Op.getOperand(0);
27792 // Otherwise, this isn't something we can handle, reject it.
27796 const GlobalValue *GV = GA->getGlobal();
27797 // If we require an extra load to get this address, as in PIC mode, we
27798 // can't accept it.
27799 if (isGlobalStubReference(
27800 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
27803 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
27804 GA->getValueType(0), Offset);
27809 if (Result.getNode()) {
27810 Ops.push_back(Result);
27813 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
27816 std::pair<unsigned, const TargetRegisterClass *>
27817 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
27818 StringRef Constraint,
27820 // First, see if this is a constraint that directly corresponds to an LLVM
27822 if (Constraint.size() == 1) {
27823 // GCC Constraint Letters
27824 switch (Constraint[0]) {
27826 // TODO: Slight differences here in allocation order and leaving
27827 // RIP in the class. Do they matter any more here than they do
27828 // in the normal allocation?
27829 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
27830 if (Subtarget->is64Bit()) {
27831 if (VT == MVT::i32 || VT == MVT::f32)
27832 return std::make_pair(0U, &X86::GR32RegClass);
27833 if (VT == MVT::i16)
27834 return std::make_pair(0U, &X86::GR16RegClass);
27835 if (VT == MVT::i8 || VT == MVT::i1)
27836 return std::make_pair(0U, &X86::GR8RegClass);
27837 if (VT == MVT::i64 || VT == MVT::f64)
27838 return std::make_pair(0U, &X86::GR64RegClass);
27841 // 32-bit fallthrough
27842 case 'Q': // Q_REGS
27843 if (VT == MVT::i32 || VT == MVT::f32)
27844 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
27845 if (VT == MVT::i16)
27846 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
27847 if (VT == MVT::i8 || VT == MVT::i1)
27848 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
27849 if (VT == MVT::i64)
27850 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
27852 case 'r': // GENERAL_REGS
27853 case 'l': // INDEX_REGS
27854 if (VT == MVT::i8 || VT == MVT::i1)
27855 return std::make_pair(0U, &X86::GR8RegClass);
27856 if (VT == MVT::i16)
27857 return std::make_pair(0U, &X86::GR16RegClass);
27858 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
27859 return std::make_pair(0U, &X86::GR32RegClass);
27860 return std::make_pair(0U, &X86::GR64RegClass);
27861 case 'R': // LEGACY_REGS
27862 if (VT == MVT::i8 || VT == MVT::i1)
27863 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
27864 if (VT == MVT::i16)
27865 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
27866 if (VT == MVT::i32 || !Subtarget->is64Bit())
27867 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
27868 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
27869 case 'f': // FP Stack registers.
27870 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
27871 // value to the correct fpstack register class.
27872 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
27873 return std::make_pair(0U, &X86::RFP32RegClass);
27874 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
27875 return std::make_pair(0U, &X86::RFP64RegClass);
27876 return std::make_pair(0U, &X86::RFP80RegClass);
27877 case 'y': // MMX_REGS if MMX allowed.
27878 if (!Subtarget->hasMMX()) break;
27879 return std::make_pair(0U, &X86::VR64RegClass);
27880 case 'Y': // SSE_REGS if SSE2 allowed
27881 if (!Subtarget->hasSSE2()) break;
27883 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
27884 if (!Subtarget->hasSSE1()) break;
27886 switch (VT.SimpleTy) {
27888 // Scalar SSE types.
27891 return std::make_pair(0U, &X86::FR32RegClass);
27894 return std::make_pair(0U, &X86::FR64RegClass);
27902 return std::make_pair(0U, &X86::VR128RegClass);
27910 return std::make_pair(0U, &X86::VR256RegClass);
27915 return std::make_pair(0U, &X86::VR512RegClass);
27921 // Use the default implementation in TargetLowering to convert the register
27922 // constraint into a member of a register class.
27923 std::pair<unsigned, const TargetRegisterClass*> Res;
27924 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
27926 // Not found as a standard register?
27928 // Map st(0) -> st(7) -> ST0
27929 if (Constraint.size() == 7 && Constraint[0] == '{' &&
27930 tolower(Constraint[1]) == 's' &&
27931 tolower(Constraint[2]) == 't' &&
27932 Constraint[3] == '(' &&
27933 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
27934 Constraint[5] == ')' &&
27935 Constraint[6] == '}') {
27937 Res.first = X86::FP0+Constraint[4]-'0';
27938 Res.second = &X86::RFP80RegClass;
27942 // GCC allows "st(0)" to be called just plain "st".
27943 if (StringRef("{st}").equals_lower(Constraint)) {
27944 Res.first = X86::FP0;
27945 Res.second = &X86::RFP80RegClass;
27950 if (StringRef("{flags}").equals_lower(Constraint)) {
27951 Res.first = X86::EFLAGS;
27952 Res.second = &X86::CCRRegClass;
27956 // 'A' means EAX + EDX.
27957 if (Constraint == "A") {
27958 Res.first = X86::EAX;
27959 Res.second = &X86::GR32_ADRegClass;
27965 // Otherwise, check to see if this is a register class of the wrong value
27966 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
27967 // turn into {ax},{dx}.
27968 // MVT::Other is used to specify clobber names.
27969 if (Res.second->hasType(VT) || VT == MVT::Other)
27970 return Res; // Correct type already, nothing to do.
27972 // Get a matching integer of the correct size. i.e. "ax" with MVT::32 should
27973 // return "eax". This should even work for things like getting 64bit integer
27974 // registers when given an f64 type.
27975 const TargetRegisterClass *Class = Res.second;
27976 if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
27977 Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
27978 unsigned Size = VT.getSizeInBits();
27979 MVT::SimpleValueType SimpleTy = Size == 1 || Size == 8 ? MVT::i8
27980 : Size == 16 ? MVT::i16
27981 : Size == 32 ? MVT::i32
27982 : Size == 64 ? MVT::i64
27984 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, SimpleTy);
27986 Res.first = DestReg;
27987 Res.second = SimpleTy == MVT::i8 ? &X86::GR8RegClass
27988 : SimpleTy == MVT::i16 ? &X86::GR16RegClass
27989 : SimpleTy == MVT::i32 ? &X86::GR32RegClass
27990 : &X86::GR64RegClass;
27991 assert(Res.second->contains(Res.first) && "Register in register class");
27993 // No register found/type mismatch.
27995 Res.second = nullptr;
27997 } else if (Class == &X86::FR32RegClass || Class == &X86::FR64RegClass ||
27998 Class == &X86::VR128RegClass || Class == &X86::VR256RegClass ||
27999 Class == &X86::FR32XRegClass || Class == &X86::FR64XRegClass ||
28000 Class == &X86::VR128XRegClass || Class == &X86::VR256XRegClass ||
28001 Class == &X86::VR512RegClass) {
28002 // Handle references to XMM physical registers that got mapped into the
28003 // wrong class. This can happen with constraints like {xmm0} where the
28004 // target independent register mapper will just pick the first match it can
28005 // find, ignoring the required type.
28007 if (VT == MVT::f32 || VT == MVT::i32)
28008 Res.second = &X86::FR32RegClass;
28009 else if (VT == MVT::f64 || VT == MVT::i64)
28010 Res.second = &X86::FR64RegClass;
28011 else if (X86::VR128RegClass.hasType(VT))
28012 Res.second = &X86::VR128RegClass;
28013 else if (X86::VR256RegClass.hasType(VT))
28014 Res.second = &X86::VR256RegClass;
28015 else if (X86::VR512RegClass.hasType(VT))
28016 Res.second = &X86::VR512RegClass;
28018 // Type mismatch and not a clobber: Return an error;
28020 Res.second = nullptr;
28027 int X86TargetLowering::getScalingFactorCost(const DataLayout &DL,
28028 const AddrMode &AM, Type *Ty,
28029 unsigned AS) const {
28030 // Scaling factors are not free at all.
28031 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
28032 // will take 2 allocations in the out of order engine instead of 1
28033 // for plain addressing mode, i.e. inst (reg1).
28035 // vaddps (%rsi,%drx), %ymm0, %ymm1
28036 // Requires two allocations (one for the load, one for the computation)
28038 // vaddps (%rsi), %ymm0, %ymm1
28039 // Requires just 1 allocation, i.e., freeing allocations for other operations
28040 // and having less micro operations to execute.
28042 // For some X86 architectures, this is even worse because for instance for
28043 // stores, the complex addressing mode forces the instruction to use the
28044 // "load" ports instead of the dedicated "store" port.
28045 // E.g., on Haswell:
28046 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
28047 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
28048 if (isLegalAddressingMode(DL, AM, Ty, AS))
28049 // Scale represents reg2 * scale, thus account for 1
28050 // as soon as we use a second register.
28051 return AM.Scale != 0;
28055 bool X86TargetLowering::isIntDivCheap(EVT VT, AttributeSet Attr) const {
28056 // Integer division on x86 is expensive. However, when aggressively optimizing
28057 // for code size, we prefer to use a div instruction, as it is usually smaller
28058 // than the alternative sequence.
28059 // The exception to this is vector division. Since x86 doesn't have vector
28060 // integer division, leaving the division as-is is a loss even in terms of
28061 // size, because it will have to be scalarized, while the alternative code
28062 // sequence can be performed in vector form.
28063 bool OptSize = Attr.hasAttribute(AttributeSet::FunctionIndex,
28064 Attribute::MinSize);
28065 return OptSize && !VT.isVector();
28068 void X86TargetLowering::markInRegArguments(SelectionDAG &DAG,
28069 TargetLowering::ArgListTy& Args) const {
28070 // The MCU psABI requires some arguments to be passed in-register.
28071 // For regular calls, the inreg arguments are marked by the front-end.
28072 // However, for compiler generated library calls, we have to patch this
28074 if (!Subtarget->isTargetMCU() || !Args.size())
28077 unsigned FreeRegs = 3;
28078 for (auto &Arg : Args) {
28079 // For library functions, we do not expect any fancy types.
28080 unsigned Size = DAG.getDataLayout().getTypeSizeInBits(Arg.Ty);
28081 unsigned SizeInRegs = (Size + 31) / 32;
28082 if (SizeInRegs > 2 || SizeInRegs > FreeRegs)
28085 Arg.isInReg = true;
28086 FreeRegs -= SizeInRegs;