1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86ShuffleDecode.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/PseudoSourceValue.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/BitVector.h"
43 #include "llvm/ADT/SmallSet.h"
44 #include "llvm/ADT/Statistic.h"
45 #include "llvm/ADT/StringExtras.h"
46 #include "llvm/ADT/VectorExtras.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/Dwarf.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Support/raw_ostream.h"
54 using namespace dwarf;
56 STATISTIC(NumTailCalls, "Number of tail calls");
58 // Forward declarations.
59 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
62 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
64 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
66 if (TM.getSubtarget<X86Subtarget>().isTargetDarwin()) {
68 return new X8664_MachoTargetObjectFile();
69 return new TargetLoweringObjectFileMachO();
72 if (TM.getSubtarget<X86Subtarget>().isTargetELF() ){
74 return new X8664_ELFTargetObjectFile(TM);
75 return new X8632_ELFTargetObjectFile(TM);
77 if (TM.getSubtarget<X86Subtarget>().isTargetCOFF())
78 return new TargetLoweringObjectFileCOFF();
79 llvm_unreachable("unknown subtarget type");
82 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
83 : TargetLowering(TM, createTLOF(TM)) {
84 Subtarget = &TM.getSubtarget<X86Subtarget>();
85 X86ScalarSSEf64 = Subtarget->hasXMMInt();
86 X86ScalarSSEf32 = Subtarget->hasXMM();
87 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
89 RegInfo = TM.getRegisterInfo();
92 // Set up the TargetLowering object.
93 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
95 // X86 is weird, it always uses i8 for shift amounts and setcc results.
96 setShiftAmountType(MVT::i8);
97 setBooleanContents(ZeroOrOneBooleanContent);
98 setSchedulingPreference(Sched::RegPressure);
99 setStackPointerRegisterToSaveRestore(X86StackPtr);
101 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
102 // Setup Windows compiler runtime calls.
103 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
104 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
105 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2");
106 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2");
107 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
108 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
109 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C);
110 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C);
113 if (Subtarget->isTargetDarwin()) {
114 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
115 setUseUnderscoreSetJmp(false);
116 setUseUnderscoreLongJmp(false);
117 } else if (Subtarget->isTargetMingw()) {
118 // MS runtime is weird: it exports _setjmp, but longjmp!
119 setUseUnderscoreSetJmp(true);
120 setUseUnderscoreLongJmp(false);
122 setUseUnderscoreSetJmp(true);
123 setUseUnderscoreLongJmp(true);
126 // Set up the register classes.
127 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
128 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
129 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
130 if (Subtarget->is64Bit())
131 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
133 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
135 // We don't accept any truncstore of integer registers.
136 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
137 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
138 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
139 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
140 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
141 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
143 // SETOEQ and SETUNE require checking two conditions.
144 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
145 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
146 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
147 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
148 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
149 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
151 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
153 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
154 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
155 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
157 if (Subtarget->is64Bit()) {
158 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
159 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
160 } else if (!UseSoftFloat) {
161 // We have an algorithm for SSE2->double, and we turn this into a
162 // 64-bit FILD followed by conditional FADD for other targets.
163 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
164 // We have an algorithm for SSE2, and we turn this into a 64-bit
165 // FILD for other targets.
166 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
169 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
171 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
172 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
175 // SSE has no i16 to fp conversion, only i32
176 if (X86ScalarSSEf32) {
177 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
178 // f32 and f64 cases are Legal, f80 case is not
179 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
181 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
182 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
185 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
186 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
189 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
190 // are Legal, f80 is custom lowered.
191 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
192 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
194 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
196 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
197 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
199 if (X86ScalarSSEf32) {
200 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
201 // f32 and f64 cases are Legal, f80 case is not
202 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
204 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
205 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
208 // Handle FP_TO_UINT by promoting the destination to a larger signed
210 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
211 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
212 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
214 if (Subtarget->is64Bit()) {
215 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
216 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
217 } else if (!UseSoftFloat) {
218 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
219 // Expand FP_TO_UINT into a select.
220 // FIXME: We would like to use a Custom expander here eventually to do
221 // the optimal thing for SSE vs. the default expansion in the legalizer.
222 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
224 // With SSE3 we can use fisttpll to convert to a signed i64; without
225 // SSE, we're stuck with a fistpll.
226 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
229 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
230 if (!X86ScalarSSEf64) {
231 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
232 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
233 if (Subtarget->is64Bit()) {
234 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
235 // Without SSE, i64->f64 goes through memory.
236 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
240 // Scalar integer divide and remainder are lowered to use operations that
241 // produce two results, to match the available instructions. This exposes
242 // the two-result form to trivial CSE, which is able to combine x/y and x%y
243 // into a single instruction.
245 // Scalar integer multiply-high is also lowered to use two-result
246 // operations, to match the available instructions. However, plain multiply
247 // (low) operations are left as Legal, as there are single-result
248 // instructions for this in x86. Using the two-result multiply instructions
249 // when both high and low results are needed must be arranged by dagcombine.
250 for (unsigned i = 0, e = 4; i != e; ++i) {
252 setOperationAction(ISD::MULHS, VT, Expand);
253 setOperationAction(ISD::MULHU, VT, Expand);
254 setOperationAction(ISD::SDIV, VT, Expand);
255 setOperationAction(ISD::UDIV, VT, Expand);
256 setOperationAction(ISD::SREM, VT, Expand);
257 setOperationAction(ISD::UREM, VT, Expand);
259 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
260 setOperationAction(ISD::ADDC, VT, Custom);
261 setOperationAction(ISD::ADDE, VT, Custom);
262 setOperationAction(ISD::SUBC, VT, Custom);
263 setOperationAction(ISD::SUBE, VT, Custom);
266 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
267 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
268 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
269 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
270 if (Subtarget->is64Bit())
271 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
272 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
273 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
274 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
275 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
276 setOperationAction(ISD::FREM , MVT::f32 , Expand);
277 setOperationAction(ISD::FREM , MVT::f64 , Expand);
278 setOperationAction(ISD::FREM , MVT::f80 , Expand);
279 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
281 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
282 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
283 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
284 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
285 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
286 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
287 if (Subtarget->is64Bit()) {
288 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
289 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
292 if (Subtarget->hasPOPCNT()) {
293 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
295 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
296 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
297 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
298 if (Subtarget->is64Bit())
299 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
302 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
303 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
305 // These should be promoted to a larger select which is supported.
306 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
307 // X86 wants to expand cmov itself.
308 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
309 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
310 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
311 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
312 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
313 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
314 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
315 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
316 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
317 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
318 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
319 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
320 if (Subtarget->is64Bit()) {
321 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
322 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
324 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
327 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
328 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
329 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
330 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
331 if (Subtarget->is64Bit())
332 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
333 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
334 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
335 if (Subtarget->is64Bit()) {
336 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
337 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
338 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
339 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
340 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
342 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
343 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
344 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
345 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
346 if (Subtarget->is64Bit()) {
347 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
348 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
349 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
352 if (Subtarget->hasXMM())
353 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
355 // We may not have a libcall for MEMBARRIER so we should lower this.
356 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
358 // On X86 and X86-64, atomic operations are lowered to locked instructions.
359 // Locked instructions, in turn, have implicit fence semantics (all memory
360 // operations are flushed before issuing the locked instruction, and they
361 // are not buffered), so we can fold away the common pattern of
362 // fence-atomic-fence.
363 setShouldFoldAtomicFences(true);
365 // Expand certain atomics
366 for (unsigned i = 0, e = 4; i != e; ++i) {
368 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
369 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
372 if (!Subtarget->is64Bit()) {
373 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
374 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
375 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
376 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
377 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
378 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
379 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
382 // FIXME - use subtarget debug flags
383 if (!Subtarget->isTargetDarwin() &&
384 !Subtarget->isTargetELF() &&
385 !Subtarget->isTargetCygMing()) {
386 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
389 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
390 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
391 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
392 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
393 if (Subtarget->is64Bit()) {
394 setExceptionPointerRegister(X86::RAX);
395 setExceptionSelectorRegister(X86::RDX);
397 setExceptionPointerRegister(X86::EAX);
398 setExceptionSelectorRegister(X86::EDX);
400 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
401 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
403 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
405 setOperationAction(ISD::TRAP, MVT::Other, Legal);
407 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
408 setOperationAction(ISD::VASTART , MVT::Other, Custom);
409 setOperationAction(ISD::VAEND , MVT::Other, Expand);
410 if (Subtarget->is64Bit()) {
411 setOperationAction(ISD::VAARG , MVT::Other, Custom);
412 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
414 setOperationAction(ISD::VAARG , MVT::Other, Expand);
415 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
418 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
419 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
420 if (Subtarget->is64Bit())
421 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
422 if (Subtarget->isTargetCygMing() || Subtarget->isTargetWindows())
423 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
425 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
427 if (!UseSoftFloat && X86ScalarSSEf64) {
428 // f32 and f64 use SSE.
429 // Set up the FP register classes.
430 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
431 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
433 // Use ANDPD to simulate FABS.
434 setOperationAction(ISD::FABS , MVT::f64, Custom);
435 setOperationAction(ISD::FABS , MVT::f32, Custom);
437 // Use XORP to simulate FNEG.
438 setOperationAction(ISD::FNEG , MVT::f64, Custom);
439 setOperationAction(ISD::FNEG , MVT::f32, Custom);
441 // Use ANDPD and ORPD to simulate FCOPYSIGN.
442 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
443 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
445 // We don't support sin/cos/fmod
446 setOperationAction(ISD::FSIN , MVT::f64, Expand);
447 setOperationAction(ISD::FCOS , MVT::f64, Expand);
448 setOperationAction(ISD::FSIN , MVT::f32, Expand);
449 setOperationAction(ISD::FCOS , MVT::f32, Expand);
451 // Expand FP immediates into loads from the stack, except for the special
453 addLegalFPImmediate(APFloat(+0.0)); // xorpd
454 addLegalFPImmediate(APFloat(+0.0f)); // xorps
455 } else if (!UseSoftFloat && X86ScalarSSEf32) {
456 // Use SSE for f32, x87 for f64.
457 // Set up the FP register classes.
458 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
459 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
461 // Use ANDPS to simulate FABS.
462 setOperationAction(ISD::FABS , MVT::f32, Custom);
464 // Use XORP to simulate FNEG.
465 setOperationAction(ISD::FNEG , MVT::f32, Custom);
467 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
469 // Use ANDPS and ORPS to simulate FCOPYSIGN.
470 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
471 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
473 // We don't support sin/cos/fmod
474 setOperationAction(ISD::FSIN , MVT::f32, Expand);
475 setOperationAction(ISD::FCOS , MVT::f32, Expand);
477 // Special cases we handle for FP constants.
478 addLegalFPImmediate(APFloat(+0.0f)); // xorps
479 addLegalFPImmediate(APFloat(+0.0)); // FLD0
480 addLegalFPImmediate(APFloat(+1.0)); // FLD1
481 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
482 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
485 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
486 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
488 } else if (!UseSoftFloat) {
489 // f32 and f64 in x87.
490 // Set up the FP register classes.
491 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
492 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
494 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
495 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
496 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
497 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
500 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
501 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
503 addLegalFPImmediate(APFloat(+0.0)); // FLD0
504 addLegalFPImmediate(APFloat(+1.0)); // FLD1
505 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
506 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
507 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
508 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
509 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
510 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
513 // Long double always uses X87.
515 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
516 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
517 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
519 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
520 addLegalFPImmediate(TmpFlt); // FLD0
522 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
525 APFloat TmpFlt2(+1.0);
526 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
528 addLegalFPImmediate(TmpFlt2); // FLD1
529 TmpFlt2.changeSign();
530 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
534 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
535 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
539 // Always use a library call for pow.
540 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
541 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
542 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
544 setOperationAction(ISD::FLOG, MVT::f80, Expand);
545 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
546 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
547 setOperationAction(ISD::FEXP, MVT::f80, Expand);
548 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
550 // First set operation action for all vector types to either promote
551 // (for widening) or expand (for scalarization). Then we will selectively
552 // turn on ones that can be effectively codegen'd.
553 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
554 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
555 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
556 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
565 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
566 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
567 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
568 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
570 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
571 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
574 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
575 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
576 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
577 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
578 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
579 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
580 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
581 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
582 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
583 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
584 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
585 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
586 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
587 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
588 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
589 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
590 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
591 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
592 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
593 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
594 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
595 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
596 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
597 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
598 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
599 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
600 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
601 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
602 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
603 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
604 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
605 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
606 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
607 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
608 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
609 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
610 setTruncStoreAction((MVT::SimpleValueType)VT,
611 (MVT::SimpleValueType)InnerVT, Expand);
612 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
613 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
614 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
617 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
618 // with -msoft-float, disable use of MMX as well.
619 if (!UseSoftFloat && Subtarget->hasMMX()) {
620 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
621 // No operations on x86mmx supported, everything uses intrinsics.
624 // MMX-sized vectors (other than x86mmx) are expected to be expanded
625 // into smaller operations.
626 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
627 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
628 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
629 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
630 setOperationAction(ISD::AND, MVT::v8i8, Expand);
631 setOperationAction(ISD::AND, MVT::v4i16, Expand);
632 setOperationAction(ISD::AND, MVT::v2i32, Expand);
633 setOperationAction(ISD::AND, MVT::v1i64, Expand);
634 setOperationAction(ISD::OR, MVT::v8i8, Expand);
635 setOperationAction(ISD::OR, MVT::v4i16, Expand);
636 setOperationAction(ISD::OR, MVT::v2i32, Expand);
637 setOperationAction(ISD::OR, MVT::v1i64, Expand);
638 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
639 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
640 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
641 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
642 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
643 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
644 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
645 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
646 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
647 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
648 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
649 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
650 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
651 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
652 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
653 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
654 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
656 if (!UseSoftFloat && Subtarget->hasXMM()) {
657 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
659 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
660 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
661 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
662 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
663 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
664 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
665 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
666 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
667 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
668 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
669 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
670 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
673 if (!UseSoftFloat && Subtarget->hasXMMInt()) {
674 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
676 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
677 // registers cannot be used even for integer operations.
678 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
679 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
680 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
681 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
683 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
684 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
685 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
686 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
687 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
688 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
689 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
690 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
691 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
692 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
693 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
694 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
695 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
696 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
697 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
698 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
700 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
701 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
702 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
703 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
705 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
706 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
707 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
708 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
709 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
711 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
712 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
713 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
714 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
715 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
717 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
718 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
719 EVT VT = (MVT::SimpleValueType)i;
720 // Do not attempt to custom lower non-power-of-2 vectors
721 if (!isPowerOf2_32(VT.getVectorNumElements()))
723 // Do not attempt to custom lower non-128-bit vectors
724 if (!VT.is128BitVector())
726 setOperationAction(ISD::BUILD_VECTOR,
727 VT.getSimpleVT().SimpleTy, Custom);
728 setOperationAction(ISD::VECTOR_SHUFFLE,
729 VT.getSimpleVT().SimpleTy, Custom);
730 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
731 VT.getSimpleVT().SimpleTy, Custom);
734 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
735 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
736 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
737 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
738 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
739 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
741 if (Subtarget->is64Bit()) {
742 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
743 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
746 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
747 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
748 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
751 // Do not attempt to promote non-128-bit vectors
752 if (!VT.is128BitVector())
755 setOperationAction(ISD::AND, SVT, Promote);
756 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
757 setOperationAction(ISD::OR, SVT, Promote);
758 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
759 setOperationAction(ISD::XOR, SVT, Promote);
760 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
761 setOperationAction(ISD::LOAD, SVT, Promote);
762 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
763 setOperationAction(ISD::SELECT, SVT, Promote);
764 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
767 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
769 // Custom lower v2i64 and v2f64 selects.
770 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
771 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
772 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
773 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
775 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
776 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
779 if (Subtarget->hasSSE41()) {
780 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
781 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
782 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
783 setOperationAction(ISD::FRINT, MVT::f32, Legal);
784 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
785 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
786 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
787 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
788 setOperationAction(ISD::FRINT, MVT::f64, Legal);
789 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
791 // FIXME: Do we need to handle scalar-to-vector here?
792 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
794 // Can turn SHL into an integer multiply.
795 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
796 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
798 // i8 and i16 vectors are custom , because the source register and source
799 // source memory operand types are not the same width. f32 vectors are
800 // custom since the immediate controlling the insert encodes additional
802 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
803 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
804 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
805 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
807 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
808 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
809 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
810 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
812 if (Subtarget->is64Bit()) {
813 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
814 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
818 if (Subtarget->hasSSE42())
819 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
821 if (!UseSoftFloat && Subtarget->hasAVX()) {
822 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
823 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
824 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
825 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
826 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
828 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
829 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
830 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
831 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
832 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
833 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
834 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
835 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
836 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
837 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
838 setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
839 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
840 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
841 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
842 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
844 // Operations to consider commented out -v16i16 v32i8
845 //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
846 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
847 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
848 //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
849 //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
850 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
851 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
852 //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
853 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
854 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
855 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
856 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
857 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
858 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
860 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
861 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
862 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
863 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
865 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
866 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
867 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
868 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
869 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
871 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
872 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
873 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
874 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
875 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
876 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
879 // Not sure we want to do this since there are no 256-bit integer
882 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
883 // This includes 256-bit vectors
884 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
885 EVT VT = (MVT::SimpleValueType)i;
887 // Do not attempt to custom lower non-power-of-2 vectors
888 if (!isPowerOf2_32(VT.getVectorNumElements()))
891 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
892 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
893 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
896 if (Subtarget->is64Bit()) {
897 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
898 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
903 // Not sure we want to do this since there are no 256-bit integer
906 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
907 // Including 256-bit vectors
908 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
909 EVT VT = (MVT::SimpleValueType)i;
911 if (!VT.is256BitVector()) {
914 setOperationAction(ISD::AND, VT, Promote);
915 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
916 setOperationAction(ISD::OR, VT, Promote);
917 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
918 setOperationAction(ISD::XOR, VT, Promote);
919 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
920 setOperationAction(ISD::LOAD, VT, Promote);
921 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
922 setOperationAction(ISD::SELECT, VT, Promote);
923 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
926 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
930 // We want to custom lower some of our intrinsics.
931 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
934 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
935 // handle type legalization for these operations here.
937 // FIXME: We really should do custom legalization for addition and
938 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
939 // than generic legalization for 64-bit multiplication-with-overflow, though.
940 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
941 // Add/Sub/Mul with overflow operations are custom lowered.
943 setOperationAction(ISD::SADDO, VT, Custom);
944 setOperationAction(ISD::UADDO, VT, Custom);
945 setOperationAction(ISD::SSUBO, VT, Custom);
946 setOperationAction(ISD::USUBO, VT, Custom);
947 setOperationAction(ISD::SMULO, VT, Custom);
948 setOperationAction(ISD::UMULO, VT, Custom);
951 // There are no 8-bit 3-address imul/mul instructions
952 setOperationAction(ISD::SMULO, MVT::i8, Expand);
953 setOperationAction(ISD::UMULO, MVT::i8, Expand);
955 if (!Subtarget->is64Bit()) {
956 // These libcalls are not available in 32-bit.
957 setLibcallName(RTLIB::SHL_I128, 0);
958 setLibcallName(RTLIB::SRL_I128, 0);
959 setLibcallName(RTLIB::SRA_I128, 0);
962 // We have target-specific dag combine patterns for the following nodes:
963 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
964 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
965 setTargetDAGCombine(ISD::BUILD_VECTOR);
966 setTargetDAGCombine(ISD::SELECT);
967 setTargetDAGCombine(ISD::SHL);
968 setTargetDAGCombine(ISD::SRA);
969 setTargetDAGCombine(ISD::SRL);
970 setTargetDAGCombine(ISD::OR);
971 setTargetDAGCombine(ISD::AND);
972 setTargetDAGCombine(ISD::ADD);
973 setTargetDAGCombine(ISD::SUB);
974 setTargetDAGCombine(ISD::STORE);
975 setTargetDAGCombine(ISD::ZERO_EXTEND);
976 if (Subtarget->is64Bit())
977 setTargetDAGCombine(ISD::MUL);
979 computeRegisterProperties();
981 // FIXME: These should be based on subtarget info. Plus, the values should
982 // be smaller when we are in optimizing for size mode.
983 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
984 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
985 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
986 setPrefLoopAlignment(16);
987 benefitFromCodePlacementOpt = true;
991 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
996 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
997 /// the desired ByVal argument alignment.
998 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
1001 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1002 if (VTy->getBitWidth() == 128)
1004 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1005 unsigned EltAlign = 0;
1006 getMaxByValAlign(ATy->getElementType(), EltAlign);
1007 if (EltAlign > MaxAlign)
1008 MaxAlign = EltAlign;
1009 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
1010 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1011 unsigned EltAlign = 0;
1012 getMaxByValAlign(STy->getElementType(i), EltAlign);
1013 if (EltAlign > MaxAlign)
1014 MaxAlign = EltAlign;
1022 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1023 /// function arguments in the caller parameter area. For X86, aggregates
1024 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1025 /// are at 4-byte boundaries.
1026 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1027 if (Subtarget->is64Bit()) {
1028 // Max of 8 and alignment of type.
1029 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1036 if (Subtarget->hasXMM())
1037 getMaxByValAlign(Ty, Align);
1041 /// getOptimalMemOpType - Returns the target specific optimal type for load
1042 /// and store operations as a result of memset, memcpy, and memmove
1043 /// lowering. If DstAlign is zero that means it's safe to destination
1044 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1045 /// means there isn't a need to check it against alignment requirement,
1046 /// probably because the source does not need to be loaded. If
1047 /// 'NonScalarIntSafe' is true, that means it's safe to return a
1048 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1049 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1050 /// constant so it does not need to be loaded.
1051 /// It returns EVT::Other if the type should be determined using generic
1052 /// target-independent logic.
1054 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1055 unsigned DstAlign, unsigned SrcAlign,
1056 bool NonScalarIntSafe,
1058 MachineFunction &MF) const {
1059 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1060 // linux. This is because the stack realignment code can't handle certain
1061 // cases like PR2962. This should be removed when PR2962 is fixed.
1062 const Function *F = MF.getFunction();
1063 if (NonScalarIntSafe &&
1064 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1066 (Subtarget->isUnalignedMemAccessFast() ||
1067 ((DstAlign == 0 || DstAlign >= 16) &&
1068 (SrcAlign == 0 || SrcAlign >= 16))) &&
1069 Subtarget->getStackAlignment() >= 16) {
1070 if (Subtarget->hasSSE2())
1072 if (Subtarget->hasSSE1())
1074 } else if (!MemcpyStrSrc && Size >= 8 &&
1075 !Subtarget->is64Bit() &&
1076 Subtarget->getStackAlignment() >= 8 &&
1077 Subtarget->hasXMMInt()) {
1078 // Do not use f64 to lower memcpy if source is string constant. It's
1079 // better to use i32 to avoid the loads.
1083 if (Subtarget->is64Bit() && Size >= 8)
1088 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1089 /// current function. The returned value is a member of the
1090 /// MachineJumpTableInfo::JTEntryKind enum.
1091 unsigned X86TargetLowering::getJumpTableEncoding() const {
1092 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1094 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1095 Subtarget->isPICStyleGOT())
1096 return MachineJumpTableInfo::EK_Custom32;
1098 // Otherwise, use the normal jump table encoding heuristics.
1099 return TargetLowering::getJumpTableEncoding();
1103 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1104 const MachineBasicBlock *MBB,
1105 unsigned uid,MCContext &Ctx) const{
1106 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1107 Subtarget->isPICStyleGOT());
1108 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1110 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1111 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1114 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1116 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1117 SelectionDAG &DAG) const {
1118 if (!Subtarget->is64Bit())
1119 // This doesn't have DebugLoc associated with it, but is not really the
1120 // same as a Register.
1121 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1125 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1126 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1128 const MCExpr *X86TargetLowering::
1129 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1130 MCContext &Ctx) const {
1131 // X86-64 uses RIP relative addressing based on the jump table label.
1132 if (Subtarget->isPICStyleRIPRel())
1133 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1135 // Otherwise, the reference is relative to the PIC base.
1136 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1139 /// getFunctionAlignment - Return the Log2 alignment of this function.
1140 unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1141 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4;
1144 std::pair<const TargetRegisterClass*, uint8_t>
1145 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1146 const TargetRegisterClass *RRC = 0;
1148 switch (VT.getSimpleVT().SimpleTy) {
1150 return TargetLowering::findRepresentativeClass(VT);
1151 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1152 RRC = (Subtarget->is64Bit()
1153 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1156 RRC = X86::VR64RegisterClass;
1158 case MVT::f32: case MVT::f64:
1159 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1160 case MVT::v4f32: case MVT::v2f64:
1161 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1163 RRC = X86::VR128RegisterClass;
1166 return std::make_pair(RRC, Cost);
1170 X86TargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
1171 MachineFunction &MF) const {
1172 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
1174 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
1175 switch (RC->getID()) {
1178 case X86::GR32RegClassID:
1180 case X86::GR64RegClassID:
1182 case X86::VR128RegClassID:
1183 return Subtarget->is64Bit() ? 10 : 4;
1184 case X86::VR64RegClassID:
1189 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1190 unsigned &Offset) const {
1191 if (!Subtarget->isTargetLinux())
1194 if (Subtarget->is64Bit()) {
1195 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1197 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1210 //===----------------------------------------------------------------------===//
1211 // Return Value Calling Convention Implementation
1212 //===----------------------------------------------------------------------===//
1214 #include "X86GenCallingConv.inc"
1217 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1218 const SmallVectorImpl<ISD::OutputArg> &Outs,
1219 LLVMContext &Context) const {
1220 SmallVector<CCValAssign, 16> RVLocs;
1221 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1223 return CCInfo.CheckReturn(Outs, RetCC_X86);
1227 X86TargetLowering::LowerReturn(SDValue Chain,
1228 CallingConv::ID CallConv, bool isVarArg,
1229 const SmallVectorImpl<ISD::OutputArg> &Outs,
1230 const SmallVectorImpl<SDValue> &OutVals,
1231 DebugLoc dl, SelectionDAG &DAG) const {
1232 MachineFunction &MF = DAG.getMachineFunction();
1233 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1235 SmallVector<CCValAssign, 16> RVLocs;
1236 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1237 RVLocs, *DAG.getContext());
1238 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1240 // Add the regs to the liveout set for the function.
1241 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1242 for (unsigned i = 0; i != RVLocs.size(); ++i)
1243 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1244 MRI.addLiveOut(RVLocs[i].getLocReg());
1248 SmallVector<SDValue, 6> RetOps;
1249 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1250 // Operand #1 = Bytes To Pop
1251 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1254 // Copy the result values into the output registers.
1255 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1256 CCValAssign &VA = RVLocs[i];
1257 assert(VA.isRegLoc() && "Can only return in registers!");
1258 SDValue ValToCopy = OutVals[i];
1259 EVT ValVT = ValToCopy.getValueType();
1261 // If this is x86-64, and we disabled SSE, we can't return FP values,
1262 // or SSE or MMX vectors.
1263 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1264 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1265 (Subtarget->is64Bit() && !Subtarget->hasXMM())) {
1266 report_fatal_error("SSE register return with SSE disabled");
1268 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1269 // llvm-gcc has never done it right and no one has noticed, so this
1270 // should be OK for now.
1271 if (ValVT == MVT::f64 &&
1272 (Subtarget->is64Bit() && !Subtarget->hasXMMInt()))
1273 report_fatal_error("SSE2 register return with SSE2 disabled");
1275 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1276 // the RET instruction and handled by the FP Stackifier.
1277 if (VA.getLocReg() == X86::ST0 ||
1278 VA.getLocReg() == X86::ST1) {
1279 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1280 // change the value to the FP stack register class.
1281 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1282 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1283 RetOps.push_back(ValToCopy);
1284 // Don't emit a copytoreg.
1288 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1289 // which is returned in RAX / RDX.
1290 if (Subtarget->is64Bit()) {
1291 if (ValVT == MVT::x86mmx) {
1292 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1293 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1294 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1296 // If we don't have SSE2 available, convert to v4f32 so the generated
1297 // register is legal.
1298 if (!Subtarget->hasSSE2())
1299 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1304 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1305 Flag = Chain.getValue(1);
1308 // The x86-64 ABI for returning structs by value requires that we copy
1309 // the sret argument into %rax for the return. We saved the argument into
1310 // a virtual register in the entry block, so now we copy the value out
1312 if (Subtarget->is64Bit() &&
1313 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1314 MachineFunction &MF = DAG.getMachineFunction();
1315 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1316 unsigned Reg = FuncInfo->getSRetReturnReg();
1318 "SRetReturnReg should have been set in LowerFormalArguments().");
1319 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1321 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1322 Flag = Chain.getValue(1);
1324 // RAX now acts like a return value.
1325 MRI.addLiveOut(X86::RAX);
1328 RetOps[0] = Chain; // Update chain.
1330 // Add the flag if we have it.
1332 RetOps.push_back(Flag);
1334 return DAG.getNode(X86ISD::RET_FLAG, dl,
1335 MVT::Other, &RetOps[0], RetOps.size());
1338 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const {
1339 if (N->getNumValues() != 1)
1341 if (!N->hasNUsesOfValue(1, 0))
1344 SDNode *Copy = *N->use_begin();
1345 if (Copy->getOpcode() != ISD::CopyToReg &&
1346 Copy->getOpcode() != ISD::FP_EXTEND)
1349 bool HasRet = false;
1350 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1352 if (UI->getOpcode() != X86ISD::RET_FLAG)
1360 /// LowerCallResult - Lower the result values of a call into the
1361 /// appropriate copies out of appropriate physical registers.
1364 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1365 CallingConv::ID CallConv, bool isVarArg,
1366 const SmallVectorImpl<ISD::InputArg> &Ins,
1367 DebugLoc dl, SelectionDAG &DAG,
1368 SmallVectorImpl<SDValue> &InVals) const {
1370 // Assign locations to each value returned by this call.
1371 SmallVector<CCValAssign, 16> RVLocs;
1372 bool Is64Bit = Subtarget->is64Bit();
1373 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1374 RVLocs, *DAG.getContext());
1375 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1377 // Copy all of the result registers out of their specified physreg.
1378 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1379 CCValAssign &VA = RVLocs[i];
1380 EVT CopyVT = VA.getValVT();
1382 // If this is x86-64, and we disabled SSE, we can't return FP values
1383 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1384 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasXMM())) {
1385 report_fatal_error("SSE register return with SSE disabled");
1390 // If this is a call to a function that returns an fp value on the floating
1391 // point stack, we must guarantee the the value is popped from the stack, so
1392 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1393 // if the return value is not used. We use the FpGET_ST0 instructions
1395 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1396 // If we prefer to use the value in xmm registers, copy it out as f80 and
1397 // use a truncate to move it from fp stack reg to xmm reg.
1398 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1399 bool isST0 = VA.getLocReg() == X86::ST0;
1401 if (CopyVT == MVT::f32) Opc = isST0 ? X86::FpGET_ST0_32:X86::FpGET_ST1_32;
1402 if (CopyVT == MVT::f64) Opc = isST0 ? X86::FpGET_ST0_64:X86::FpGET_ST1_64;
1403 if (CopyVT == MVT::f80) Opc = isST0 ? X86::FpGET_ST0_80:X86::FpGET_ST1_80;
1404 SDValue Ops[] = { Chain, InFlag };
1405 Chain = SDValue(DAG.getMachineNode(Opc, dl, CopyVT, MVT::Other, MVT::Glue,
1407 Val = Chain.getValue(0);
1409 // Round the f80 to the right size, which also moves it to the appropriate
1411 if (CopyVT != VA.getValVT())
1412 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1413 // This truncation won't change the value.
1414 DAG.getIntPtrConstant(1));
1415 } else if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1416 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1417 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1418 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1419 MVT::v2i64, InFlag).getValue(1);
1420 Val = Chain.getValue(0);
1421 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1422 Val, DAG.getConstant(0, MVT::i64));
1424 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1425 MVT::i64, InFlag).getValue(1);
1426 Val = Chain.getValue(0);
1428 Val = DAG.getNode(ISD::BITCAST, dl, CopyVT, Val);
1430 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1431 CopyVT, InFlag).getValue(1);
1432 Val = Chain.getValue(0);
1434 InFlag = Chain.getValue(2);
1435 InVals.push_back(Val);
1442 //===----------------------------------------------------------------------===//
1443 // C & StdCall & Fast Calling Convention implementation
1444 //===----------------------------------------------------------------------===//
1445 // StdCall calling convention seems to be standard for many Windows' API
1446 // routines and around. It differs from C calling convention just a little:
1447 // callee should clean up the stack, not caller. Symbols should be also
1448 // decorated in some fancy way :) It doesn't support any vector arguments.
1449 // For info on fast calling convention see Fast Calling Convention (tail call)
1450 // implementation LowerX86_32FastCCCallTo.
1452 /// CallIsStructReturn - Determines whether a call uses struct return
1454 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1458 return Outs[0].Flags.isSRet();
1461 /// ArgsAreStructReturn - Determines whether a function uses struct
1462 /// return semantics.
1464 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1468 return Ins[0].Flags.isSRet();
1471 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1472 /// by "Src" to address "Dst" with size and alignment information specified by
1473 /// the specific parameter attribute. The copy will be passed as a byval
1474 /// function parameter.
1476 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1477 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1479 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1481 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1482 /*isVolatile*/false, /*AlwaysInline=*/true,
1483 MachinePointerInfo(), MachinePointerInfo());
1486 /// IsTailCallConvention - Return true if the calling convention is one that
1487 /// supports tail call optimization.
1488 static bool IsTailCallConvention(CallingConv::ID CC) {
1489 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1492 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1493 /// a tailcall target by changing its ABI.
1494 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1495 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1499 X86TargetLowering::LowerMemArgument(SDValue Chain,
1500 CallingConv::ID CallConv,
1501 const SmallVectorImpl<ISD::InputArg> &Ins,
1502 DebugLoc dl, SelectionDAG &DAG,
1503 const CCValAssign &VA,
1504 MachineFrameInfo *MFI,
1506 // Create the nodes corresponding to a load from this parameter slot.
1507 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1508 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1509 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1512 // If value is passed by pointer we have address passed instead of the value
1514 if (VA.getLocInfo() == CCValAssign::Indirect)
1515 ValVT = VA.getLocVT();
1517 ValVT = VA.getValVT();
1519 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1520 // changed with more analysis.
1521 // In case of tail call optimization mark all arguments mutable. Since they
1522 // could be overwritten by lowering of arguments in case of a tail call.
1523 if (Flags.isByVal()) {
1524 int FI = MFI->CreateFixedObject(Flags.getByValSize(),
1525 VA.getLocMemOffset(), isImmutable);
1526 return DAG.getFrameIndex(FI, getPointerTy());
1528 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1529 VA.getLocMemOffset(), isImmutable);
1530 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1531 return DAG.getLoad(ValVT, dl, Chain, FIN,
1532 MachinePointerInfo::getFixedStack(FI),
1538 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1539 CallingConv::ID CallConv,
1541 const SmallVectorImpl<ISD::InputArg> &Ins,
1544 SmallVectorImpl<SDValue> &InVals)
1546 MachineFunction &MF = DAG.getMachineFunction();
1547 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1549 const Function* Fn = MF.getFunction();
1550 if (Fn->hasExternalLinkage() &&
1551 Subtarget->isTargetCygMing() &&
1552 Fn->getName() == "main")
1553 FuncInfo->setForceFramePointer(true);
1555 MachineFrameInfo *MFI = MF.getFrameInfo();
1556 bool Is64Bit = Subtarget->is64Bit();
1557 bool IsWin64 = Subtarget->isTargetWin64();
1559 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1560 "Var args not supported with calling convention fastcc or ghc");
1562 // Assign locations to all of the incoming arguments.
1563 SmallVector<CCValAssign, 16> ArgLocs;
1564 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1565 ArgLocs, *DAG.getContext());
1566 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1568 unsigned LastVal = ~0U;
1570 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1571 CCValAssign &VA = ArgLocs[i];
1572 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1574 assert(VA.getValNo() != LastVal &&
1575 "Don't support value assigned to multiple locs yet");
1576 LastVal = VA.getValNo();
1578 if (VA.isRegLoc()) {
1579 EVT RegVT = VA.getLocVT();
1580 TargetRegisterClass *RC = NULL;
1581 if (RegVT == MVT::i32)
1582 RC = X86::GR32RegisterClass;
1583 else if (Is64Bit && RegVT == MVT::i64)
1584 RC = X86::GR64RegisterClass;
1585 else if (RegVT == MVT::f32)
1586 RC = X86::FR32RegisterClass;
1587 else if (RegVT == MVT::f64)
1588 RC = X86::FR64RegisterClass;
1589 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1590 RC = X86::VR256RegisterClass;
1591 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1592 RC = X86::VR128RegisterClass;
1593 else if (RegVT == MVT::x86mmx)
1594 RC = X86::VR64RegisterClass;
1596 llvm_unreachable("Unknown argument type!");
1598 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1599 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1601 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1602 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1604 if (VA.getLocInfo() == CCValAssign::SExt)
1605 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1606 DAG.getValueType(VA.getValVT()));
1607 else if (VA.getLocInfo() == CCValAssign::ZExt)
1608 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1609 DAG.getValueType(VA.getValVT()));
1610 else if (VA.getLocInfo() == CCValAssign::BCvt)
1611 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1613 if (VA.isExtInLoc()) {
1614 // Handle MMX values passed in XMM regs.
1615 if (RegVT.isVector()) {
1616 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1619 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1622 assert(VA.isMemLoc());
1623 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1626 // If value is passed via pointer - do a load.
1627 if (VA.getLocInfo() == CCValAssign::Indirect)
1628 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1629 MachinePointerInfo(), false, false, 0);
1631 InVals.push_back(ArgValue);
1634 // The x86-64 ABI for returning structs by value requires that we copy
1635 // the sret argument into %rax for the return. Save the argument into
1636 // a virtual register so that we can access it from the return points.
1637 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1638 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1639 unsigned Reg = FuncInfo->getSRetReturnReg();
1641 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1642 FuncInfo->setSRetReturnReg(Reg);
1644 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1645 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1648 unsigned StackSize = CCInfo.getNextStackOffset();
1649 // Align stack specially for tail calls.
1650 if (FuncIsMadeTailCallSafe(CallConv))
1651 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1653 // If the function takes variable number of arguments, make a frame index for
1654 // the start of the first vararg value... for expansion of llvm.va_start.
1656 if (!IsWin64 && (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1657 CallConv != CallingConv::X86_ThisCall))) {
1658 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1661 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1663 // FIXME: We should really autogenerate these arrays
1664 static const unsigned GPR64ArgRegsWin64[] = {
1665 X86::RCX, X86::RDX, X86::R8, X86::R9
1667 static const unsigned GPR64ArgRegs64Bit[] = {
1668 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1670 static const unsigned XMMArgRegs64Bit[] = {
1671 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1672 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1674 const unsigned *GPR64ArgRegs;
1675 unsigned NumXMMRegs = 0;
1678 // The XMM registers which might contain var arg parameters are shadowed
1679 // in their paired GPR. So we only need to save the GPR to their home
1681 TotalNumIntRegs = 4;
1682 GPR64ArgRegs = GPR64ArgRegsWin64;
1684 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1685 GPR64ArgRegs = GPR64ArgRegs64Bit;
1687 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, TotalNumXMMRegs);
1689 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1692 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1693 assert(!(NumXMMRegs && !Subtarget->hasXMM()) &&
1694 "SSE register cannot be used when SSE is disabled!");
1695 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1696 "SSE register cannot be used when SSE is disabled!");
1697 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasXMM())
1698 // Kernel mode asks for SSE to be disabled, so don't push them
1700 TotalNumXMMRegs = 0;
1703 const TargetFrameInfo &TFI = *getTargetMachine().getFrameInfo();
1704 // Get to the caller-allocated home save location. Add 8 to account
1705 // for the return address.
1706 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1707 FuncInfo->setRegSaveFrameIndex(
1708 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1709 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1711 // For X86-64, if there are vararg parameters that are passed via
1712 // registers, then we must store them to their spots on the stack so they
1713 // may be loaded by deferencing the result of va_next.
1714 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1715 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1716 FuncInfo->setRegSaveFrameIndex(
1717 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1721 // Store the integer parameter registers.
1722 SmallVector<SDValue, 8> MemOps;
1723 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1725 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1726 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1727 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1728 DAG.getIntPtrConstant(Offset));
1729 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1730 X86::GR64RegisterClass);
1731 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1733 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1734 MachinePointerInfo::getFixedStack(
1735 FuncInfo->getRegSaveFrameIndex(), Offset),
1737 MemOps.push_back(Store);
1741 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1742 // Now store the XMM (fp + vector) parameter registers.
1743 SmallVector<SDValue, 11> SaveXMMOps;
1744 SaveXMMOps.push_back(Chain);
1746 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1747 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1748 SaveXMMOps.push_back(ALVal);
1750 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1751 FuncInfo->getRegSaveFrameIndex()));
1752 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1753 FuncInfo->getVarArgsFPOffset()));
1755 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1756 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
1757 X86::VR128RegisterClass);
1758 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1759 SaveXMMOps.push_back(Val);
1761 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1763 &SaveXMMOps[0], SaveXMMOps.size()));
1766 if (!MemOps.empty())
1767 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1768 &MemOps[0], MemOps.size());
1772 // Some CCs need callee pop.
1773 if (Subtarget->IsCalleePop(isVarArg, CallConv)) {
1774 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
1776 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
1777 // If this is an sret function, the return should pop the hidden pointer.
1778 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
1779 FuncInfo->setBytesToPopOnReturn(4);
1783 // RegSaveFrameIndex is X86-64 only.
1784 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
1785 if (CallConv == CallingConv::X86_FastCall ||
1786 CallConv == CallingConv::X86_ThisCall)
1787 // fastcc functions can't have varargs.
1788 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
1795 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1796 SDValue StackPtr, SDValue Arg,
1797 DebugLoc dl, SelectionDAG &DAG,
1798 const CCValAssign &VA,
1799 ISD::ArgFlagsTy Flags) const {
1800 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
1801 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
1802 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1803 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1804 if (Flags.isByVal())
1805 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1807 return DAG.getStore(Chain, dl, Arg, PtrOff,
1808 MachinePointerInfo::getStack(LocMemOffset),
1812 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1813 /// optimization is performed and it is required.
1815 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1816 SDValue &OutRetAddr, SDValue Chain,
1817 bool IsTailCall, bool Is64Bit,
1818 int FPDiff, DebugLoc dl) const {
1819 // Adjust the Return address stack slot.
1820 EVT VT = getPointerTy();
1821 OutRetAddr = getReturnAddressFrameIndex(DAG);
1823 // Load the "old" Return address.
1824 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
1826 return SDValue(OutRetAddr.getNode(), 1);
1829 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1830 /// optimization is performed and it is required (FPDiff!=0).
1832 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1833 SDValue Chain, SDValue RetAddrFrIdx,
1834 bool Is64Bit, int FPDiff, DebugLoc dl) {
1835 // Store the return address to the appropriate stack slot.
1836 if (!FPDiff) return Chain;
1837 // Calculate the new stack slot for the return address.
1838 int SlotSize = Is64Bit ? 8 : 4;
1839 int NewReturnAddrFI =
1840 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
1841 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1842 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1843 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1844 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
1850 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1851 CallingConv::ID CallConv, bool isVarArg,
1853 const SmallVectorImpl<ISD::OutputArg> &Outs,
1854 const SmallVectorImpl<SDValue> &OutVals,
1855 const SmallVectorImpl<ISD::InputArg> &Ins,
1856 DebugLoc dl, SelectionDAG &DAG,
1857 SmallVectorImpl<SDValue> &InVals) const {
1858 MachineFunction &MF = DAG.getMachineFunction();
1859 bool Is64Bit = Subtarget->is64Bit();
1860 bool IsStructRet = CallIsStructReturn(Outs);
1861 bool IsSibcall = false;
1864 // Check if it's really possible to do a tail call.
1865 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1866 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1867 Outs, OutVals, Ins, DAG);
1869 // Sibcalls are automatically detected tailcalls which do not require
1871 if (!GuaranteedTailCallOpt && isTailCall)
1878 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1879 "Var args not supported with calling convention fastcc or ghc");
1881 // Analyze operands of the call, assigning locations to each operand.
1882 SmallVector<CCValAssign, 16> ArgLocs;
1883 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1884 ArgLocs, *DAG.getContext());
1885 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
1887 // Get a count of how many bytes are to be pushed on the stack.
1888 unsigned NumBytes = CCInfo.getNextStackOffset();
1890 // This is a sibcall. The memory operands are available in caller's
1891 // own caller's stack.
1893 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv))
1894 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1897 if (isTailCall && !IsSibcall) {
1898 // Lower arguments at fp - stackoffset + fpdiff.
1899 unsigned NumBytesCallerPushed =
1900 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1901 FPDiff = NumBytesCallerPushed - NumBytes;
1903 // Set the delta of movement of the returnaddr stackslot.
1904 // But only set if delta is greater than previous delta.
1905 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1906 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1910 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1912 SDValue RetAddrFrIdx;
1913 // Load return adress for tail calls.
1914 if (isTailCall && FPDiff)
1915 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
1916 Is64Bit, FPDiff, dl);
1918 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1919 SmallVector<SDValue, 8> MemOpChains;
1922 // Walk the register/memloc assignments, inserting copies/loads. In the case
1923 // of tail call optimization arguments are handle later.
1924 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1925 CCValAssign &VA = ArgLocs[i];
1926 EVT RegVT = VA.getLocVT();
1927 SDValue Arg = OutVals[i];
1928 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1929 bool isByVal = Flags.isByVal();
1931 // Promote the value if needed.
1932 switch (VA.getLocInfo()) {
1933 default: llvm_unreachable("Unknown loc info!");
1934 case CCValAssign::Full: break;
1935 case CCValAssign::SExt:
1936 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
1938 case CCValAssign::ZExt:
1939 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
1941 case CCValAssign::AExt:
1942 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
1943 // Special case: passing MMX values in XMM registers.
1944 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
1945 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1946 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1948 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
1950 case CCValAssign::BCvt:
1951 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
1953 case CCValAssign::Indirect: {
1954 // Store the argument.
1955 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
1956 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1957 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
1958 MachinePointerInfo::getFixedStack(FI),
1965 if (VA.isRegLoc()) {
1966 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1967 if (isVarArg && Subtarget->isTargetWin64()) {
1968 // Win64 ABI requires argument XMM reg to be copied to the corresponding
1969 // shadow reg if callee is a varargs function.
1970 unsigned ShadowReg = 0;
1971 switch (VA.getLocReg()) {
1972 case X86::XMM0: ShadowReg = X86::RCX; break;
1973 case X86::XMM1: ShadowReg = X86::RDX; break;
1974 case X86::XMM2: ShadowReg = X86::R8; break;
1975 case X86::XMM3: ShadowReg = X86::R9; break;
1978 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
1980 } else if (!IsSibcall && (!isTailCall || isByVal)) {
1981 assert(VA.isMemLoc());
1982 if (StackPtr.getNode() == 0)
1983 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
1984 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1985 dl, DAG, VA, Flags));
1989 if (!MemOpChains.empty())
1990 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1991 &MemOpChains[0], MemOpChains.size());
1993 // Build a sequence of copy-to-reg nodes chained together with token chain
1994 // and flag operands which copy the outgoing args into registers.
1996 // Tail call byval lowering might overwrite argument registers so in case of
1997 // tail call optimization the copies to registers are lowered later.
1999 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2000 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2001 RegsToPass[i].second, InFlag);
2002 InFlag = Chain.getValue(1);
2005 if (Subtarget->isPICStyleGOT()) {
2006 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2009 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2010 DAG.getNode(X86ISD::GlobalBaseReg,
2011 DebugLoc(), getPointerTy()),
2013 InFlag = Chain.getValue(1);
2015 // If we are tail calling and generating PIC/GOT style code load the
2016 // address of the callee into ECX. The value in ecx is used as target of
2017 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2018 // for tail calls on PIC/GOT architectures. Normally we would just put the
2019 // address of GOT into ebx and then call target@PLT. But for tail calls
2020 // ebx would be restored (since ebx is callee saved) before jumping to the
2023 // Note: The actual moving to ECX is done further down.
2024 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2025 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2026 !G->getGlobal()->hasProtectedVisibility())
2027 Callee = LowerGlobalAddress(Callee, DAG);
2028 else if (isa<ExternalSymbolSDNode>(Callee))
2029 Callee = LowerExternalSymbol(Callee, DAG);
2033 if (Is64Bit && isVarArg && !Subtarget->isTargetWin64()) {
2034 // From AMD64 ABI document:
2035 // For calls that may call functions that use varargs or stdargs
2036 // (prototype-less calls or calls to functions containing ellipsis (...) in
2037 // the declaration) %al is used as hidden argument to specify the number
2038 // of SSE registers used. The contents of %al do not need to match exactly
2039 // the number of registers, but must be an ubound on the number of SSE
2040 // registers used and is in the range 0 - 8 inclusive.
2042 // Count the number of XMM registers allocated.
2043 static const unsigned XMMArgRegs[] = {
2044 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2045 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2047 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2048 assert((Subtarget->hasXMM() || !NumXMMRegs)
2049 && "SSE registers cannot be used when SSE is disabled");
2051 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2052 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2053 InFlag = Chain.getValue(1);
2057 // For tail calls lower the arguments to the 'real' stack slot.
2059 // Force all the incoming stack arguments to be loaded from the stack
2060 // before any new outgoing arguments are stored to the stack, because the
2061 // outgoing stack slots may alias the incoming argument stack slots, and
2062 // the alias isn't otherwise explicit. This is slightly more conservative
2063 // than necessary, because it means that each store effectively depends
2064 // on every argument instead of just those arguments it would clobber.
2065 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2067 SmallVector<SDValue, 8> MemOpChains2;
2070 // Do not flag preceeding copytoreg stuff together with the following stuff.
2072 if (GuaranteedTailCallOpt) {
2073 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2074 CCValAssign &VA = ArgLocs[i];
2077 assert(VA.isMemLoc());
2078 SDValue Arg = OutVals[i];
2079 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2080 // Create frame index.
2081 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2082 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2083 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2084 FIN = DAG.getFrameIndex(FI, getPointerTy());
2086 if (Flags.isByVal()) {
2087 // Copy relative to framepointer.
2088 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2089 if (StackPtr.getNode() == 0)
2090 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2092 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2094 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2098 // Store relative to framepointer.
2099 MemOpChains2.push_back(
2100 DAG.getStore(ArgChain, dl, Arg, FIN,
2101 MachinePointerInfo::getFixedStack(FI),
2107 if (!MemOpChains2.empty())
2108 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2109 &MemOpChains2[0], MemOpChains2.size());
2111 // Copy arguments to their registers.
2112 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2113 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2114 RegsToPass[i].second, InFlag);
2115 InFlag = Chain.getValue(1);
2119 // Store the return address to the appropriate stack slot.
2120 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2124 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2125 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2126 // In the 64-bit large code model, we have to make all calls
2127 // through a register, since the call instruction's 32-bit
2128 // pc-relative offset may not be large enough to hold the whole
2130 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2131 // If the callee is a GlobalAddress node (quite common, every direct call
2132 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2135 // We should use extra load for direct calls to dllimported functions in
2137 const GlobalValue *GV = G->getGlobal();
2138 if (!GV->hasDLLImportLinkage()) {
2139 unsigned char OpFlags = 0;
2141 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2142 // external symbols most go through the PLT in PIC mode. If the symbol
2143 // has hidden or protected visibility, or if it is static or local, then
2144 // we don't need to use the PLT - we can directly call it.
2145 if (Subtarget->isTargetELF() &&
2146 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2147 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2148 OpFlags = X86II::MO_PLT;
2149 } else if (Subtarget->isPICStyleStubAny() &&
2150 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2151 Subtarget->getDarwinVers() < 9) {
2152 // PC-relative references to external symbols should go through $stub,
2153 // unless we're building with the leopard linker or later, which
2154 // automatically synthesizes these stubs.
2155 OpFlags = X86II::MO_DARWIN_STUB;
2158 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2159 G->getOffset(), OpFlags);
2161 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2162 unsigned char OpFlags = 0;
2164 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2165 // external symbols should go through the PLT.
2166 if (Subtarget->isTargetELF() &&
2167 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2168 OpFlags = X86II::MO_PLT;
2169 } else if (Subtarget->isPICStyleStubAny() &&
2170 Subtarget->getDarwinVers() < 9) {
2171 // PC-relative references to external symbols should go through $stub,
2172 // unless we're building with the leopard linker or later, which
2173 // automatically synthesizes these stubs.
2174 OpFlags = X86II::MO_DARWIN_STUB;
2177 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2181 // Returns a chain & a flag for retval copy to use.
2182 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2183 SmallVector<SDValue, 8> Ops;
2185 if (!IsSibcall && isTailCall) {
2186 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2187 DAG.getIntPtrConstant(0, true), InFlag);
2188 InFlag = Chain.getValue(1);
2191 Ops.push_back(Chain);
2192 Ops.push_back(Callee);
2195 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2197 // Add argument registers to the end of the list so that they are known live
2199 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2200 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2201 RegsToPass[i].second.getValueType()));
2203 // Add an implicit use GOT pointer in EBX.
2204 if (!isTailCall && Subtarget->isPICStyleGOT())
2205 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2207 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2208 if (Is64Bit && isVarArg && !Subtarget->isTargetWin64())
2209 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2211 if (InFlag.getNode())
2212 Ops.push_back(InFlag);
2216 //// If this is the first return lowered for this function, add the regs
2217 //// to the liveout set for the function.
2218 // This isn't right, although it's probably harmless on x86; liveouts
2219 // should be computed from returns not tail calls. Consider a void
2220 // function making a tail call to a function returning int.
2221 return DAG.getNode(X86ISD::TC_RETURN, dl,
2222 NodeTys, &Ops[0], Ops.size());
2225 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2226 InFlag = Chain.getValue(1);
2228 // Create the CALLSEQ_END node.
2229 unsigned NumBytesForCalleeToPush;
2230 if (Subtarget->IsCalleePop(isVarArg, CallConv))
2231 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2232 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2233 // If this is a call to a struct-return function, the callee
2234 // pops the hidden struct pointer, so we have to push it back.
2235 // This is common for Darwin/X86, Linux & Mingw32 targets.
2236 NumBytesForCalleeToPush = 4;
2238 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2240 // Returns a flag for retval copy to use.
2242 Chain = DAG.getCALLSEQ_END(Chain,
2243 DAG.getIntPtrConstant(NumBytes, true),
2244 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2247 InFlag = Chain.getValue(1);
2250 // Handle result values, copying them out of physregs into vregs that we
2252 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2253 Ins, dl, DAG, InVals);
2257 //===----------------------------------------------------------------------===//
2258 // Fast Calling Convention (tail call) implementation
2259 //===----------------------------------------------------------------------===//
2261 // Like std call, callee cleans arguments, convention except that ECX is
2262 // reserved for storing the tail called function address. Only 2 registers are
2263 // free for argument passing (inreg). Tail call optimization is performed
2265 // * tailcallopt is enabled
2266 // * caller/callee are fastcc
2267 // On X86_64 architecture with GOT-style position independent code only local
2268 // (within module) calls are supported at the moment.
2269 // To keep the stack aligned according to platform abi the function
2270 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2271 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2272 // If a tail called function callee has more arguments than the caller the
2273 // caller needs to make sure that there is room to move the RETADDR to. This is
2274 // achieved by reserving an area the size of the argument delta right after the
2275 // original REtADDR, but before the saved framepointer or the spilled registers
2276 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2288 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2289 /// for a 16 byte align requirement.
2291 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2292 SelectionDAG& DAG) const {
2293 MachineFunction &MF = DAG.getMachineFunction();
2294 const TargetMachine &TM = MF.getTarget();
2295 const TargetFrameInfo &TFI = *TM.getFrameInfo();
2296 unsigned StackAlignment = TFI.getStackAlignment();
2297 uint64_t AlignMask = StackAlignment - 1;
2298 int64_t Offset = StackSize;
2299 uint64_t SlotSize = TD->getPointerSize();
2300 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2301 // Number smaller than 12 so just add the difference.
2302 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2304 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2305 Offset = ((~AlignMask) & Offset) + StackAlignment +
2306 (StackAlignment-SlotSize);
2311 /// MatchingStackOffset - Return true if the given stack call argument is
2312 /// already available in the same position (relatively) of the caller's
2313 /// incoming argument stack.
2315 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2316 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2317 const X86InstrInfo *TII) {
2318 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2320 if (Arg.getOpcode() == ISD::CopyFromReg) {
2321 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2322 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
2324 MachineInstr *Def = MRI->getVRegDef(VR);
2327 if (!Flags.isByVal()) {
2328 if (!TII->isLoadFromStackSlot(Def, FI))
2331 unsigned Opcode = Def->getOpcode();
2332 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2333 Def->getOperand(1).isFI()) {
2334 FI = Def->getOperand(1).getIndex();
2335 Bytes = Flags.getByValSize();
2339 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2340 if (Flags.isByVal())
2341 // ByVal argument is passed in as a pointer but it's now being
2342 // dereferenced. e.g.
2343 // define @foo(%struct.X* %A) {
2344 // tail call @bar(%struct.X* byval %A)
2347 SDValue Ptr = Ld->getBasePtr();
2348 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2351 FI = FINode->getIndex();
2355 assert(FI != INT_MAX);
2356 if (!MFI->isFixedObjectIndex(FI))
2358 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2361 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2362 /// for tail call optimization. Targets which want to do tail call
2363 /// optimization should implement this function.
2365 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2366 CallingConv::ID CalleeCC,
2368 bool isCalleeStructRet,
2369 bool isCallerStructRet,
2370 const SmallVectorImpl<ISD::OutputArg> &Outs,
2371 const SmallVectorImpl<SDValue> &OutVals,
2372 const SmallVectorImpl<ISD::InputArg> &Ins,
2373 SelectionDAG& DAG) const {
2374 if (!IsTailCallConvention(CalleeCC) &&
2375 CalleeCC != CallingConv::C)
2378 // If -tailcallopt is specified, make fastcc functions tail-callable.
2379 const MachineFunction &MF = DAG.getMachineFunction();
2380 const Function *CallerF = DAG.getMachineFunction().getFunction();
2381 CallingConv::ID CallerCC = CallerF->getCallingConv();
2382 bool CCMatch = CallerCC == CalleeCC;
2384 if (GuaranteedTailCallOpt) {
2385 if (IsTailCallConvention(CalleeCC) && CCMatch)
2390 // Look for obvious safe cases to perform tail call optimization that do not
2391 // require ABI changes. This is what gcc calls sibcall.
2393 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2394 // emit a special epilogue.
2395 if (RegInfo->needsStackRealignment(MF))
2398 // Do not sibcall optimize vararg calls unless the call site is not passing
2400 if (isVarArg && !Outs.empty())
2403 // Also avoid sibcall optimization if either caller or callee uses struct
2404 // return semantics.
2405 if (isCalleeStructRet || isCallerStructRet)
2408 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack.
2409 // Therefore if it's not used by the call it is not safe to optimize this into
2411 bool Unused = false;
2412 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2419 SmallVector<CCValAssign, 16> RVLocs;
2420 CCState CCInfo(CalleeCC, false, getTargetMachine(),
2421 RVLocs, *DAG.getContext());
2422 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2423 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2424 CCValAssign &VA = RVLocs[i];
2425 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2430 // If the calling conventions do not match, then we'd better make sure the
2431 // results are returned in the same way as what the caller expects.
2433 SmallVector<CCValAssign, 16> RVLocs1;
2434 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
2435 RVLocs1, *DAG.getContext());
2436 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2438 SmallVector<CCValAssign, 16> RVLocs2;
2439 CCState CCInfo2(CallerCC, false, getTargetMachine(),
2440 RVLocs2, *DAG.getContext());
2441 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2443 if (RVLocs1.size() != RVLocs2.size())
2445 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2446 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2448 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2450 if (RVLocs1[i].isRegLoc()) {
2451 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2454 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2460 // If the callee takes no arguments then go on to check the results of the
2462 if (!Outs.empty()) {
2463 // Check if stack adjustment is needed. For now, do not do this if any
2464 // argument is passed on the stack.
2465 SmallVector<CCValAssign, 16> ArgLocs;
2466 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
2467 ArgLocs, *DAG.getContext());
2468 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2469 if (CCInfo.getNextStackOffset()) {
2470 MachineFunction &MF = DAG.getMachineFunction();
2471 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2473 if (Subtarget->isTargetWin64())
2474 // Win64 ABI has additional complications.
2477 // Check if the arguments are already laid out in the right way as
2478 // the caller's fixed stack objects.
2479 MachineFrameInfo *MFI = MF.getFrameInfo();
2480 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2481 const X86InstrInfo *TII =
2482 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2483 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2484 CCValAssign &VA = ArgLocs[i];
2485 SDValue Arg = OutVals[i];
2486 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2487 if (VA.getLocInfo() == CCValAssign::Indirect)
2489 if (!VA.isRegLoc()) {
2490 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2497 // If the tailcall address may be in a register, then make sure it's
2498 // possible to register allocate for it. In 32-bit, the call address can
2499 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2500 // callee-saved registers are restored. These happen to be the same
2501 // registers used to pass 'inreg' arguments so watch out for those.
2502 if (!Subtarget->is64Bit() &&
2503 !isa<GlobalAddressSDNode>(Callee) &&
2504 !isa<ExternalSymbolSDNode>(Callee)) {
2505 unsigned NumInRegs = 0;
2506 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2507 CCValAssign &VA = ArgLocs[i];
2510 unsigned Reg = VA.getLocReg();
2513 case X86::EAX: case X86::EDX: case X86::ECX:
2514 if (++NumInRegs == 3)
2522 // An stdcall caller is expected to clean up its arguments; the callee
2523 // isn't going to do that.
2524 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2531 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2532 return X86::createFastISel(funcInfo);
2536 //===----------------------------------------------------------------------===//
2537 // Other Lowering Hooks
2538 //===----------------------------------------------------------------------===//
2540 static bool MayFoldLoad(SDValue Op) {
2541 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2544 static bool MayFoldIntoStore(SDValue Op) {
2545 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2548 static bool isTargetShuffle(unsigned Opcode) {
2550 default: return false;
2551 case X86ISD::PSHUFD:
2552 case X86ISD::PSHUFHW:
2553 case X86ISD::PSHUFLW:
2554 case X86ISD::SHUFPD:
2555 case X86ISD::PALIGN:
2556 case X86ISD::SHUFPS:
2557 case X86ISD::MOVLHPS:
2558 case X86ISD::MOVLHPD:
2559 case X86ISD::MOVHLPS:
2560 case X86ISD::MOVLPS:
2561 case X86ISD::MOVLPD:
2562 case X86ISD::MOVSHDUP:
2563 case X86ISD::MOVSLDUP:
2564 case X86ISD::MOVDDUP:
2567 case X86ISD::UNPCKLPS:
2568 case X86ISD::UNPCKLPD:
2569 case X86ISD::PUNPCKLWD:
2570 case X86ISD::PUNPCKLBW:
2571 case X86ISD::PUNPCKLDQ:
2572 case X86ISD::PUNPCKLQDQ:
2573 case X86ISD::UNPCKHPS:
2574 case X86ISD::UNPCKHPD:
2575 case X86ISD::PUNPCKHWD:
2576 case X86ISD::PUNPCKHBW:
2577 case X86ISD::PUNPCKHDQ:
2578 case X86ISD::PUNPCKHQDQ:
2584 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2585 SDValue V1, SelectionDAG &DAG) {
2587 default: llvm_unreachable("Unknown x86 shuffle node");
2588 case X86ISD::MOVSHDUP:
2589 case X86ISD::MOVSLDUP:
2590 case X86ISD::MOVDDUP:
2591 return DAG.getNode(Opc, dl, VT, V1);
2597 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2598 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2600 default: llvm_unreachable("Unknown x86 shuffle node");
2601 case X86ISD::PSHUFD:
2602 case X86ISD::PSHUFHW:
2603 case X86ISD::PSHUFLW:
2604 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2610 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2611 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2613 default: llvm_unreachable("Unknown x86 shuffle node");
2614 case X86ISD::PALIGN:
2615 case X86ISD::SHUFPD:
2616 case X86ISD::SHUFPS:
2617 return DAG.getNode(Opc, dl, VT, V1, V2,
2618 DAG.getConstant(TargetMask, MVT::i8));
2623 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2624 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2626 default: llvm_unreachable("Unknown x86 shuffle node");
2627 case X86ISD::MOVLHPS:
2628 case X86ISD::MOVLHPD:
2629 case X86ISD::MOVHLPS:
2630 case X86ISD::MOVLPS:
2631 case X86ISD::MOVLPD:
2634 case X86ISD::UNPCKLPS:
2635 case X86ISD::UNPCKLPD:
2636 case X86ISD::PUNPCKLWD:
2637 case X86ISD::PUNPCKLBW:
2638 case X86ISD::PUNPCKLDQ:
2639 case X86ISD::PUNPCKLQDQ:
2640 case X86ISD::UNPCKHPS:
2641 case X86ISD::UNPCKHPD:
2642 case X86ISD::PUNPCKHWD:
2643 case X86ISD::PUNPCKHBW:
2644 case X86ISD::PUNPCKHDQ:
2645 case X86ISD::PUNPCKHQDQ:
2646 return DAG.getNode(Opc, dl, VT, V1, V2);
2651 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2652 MachineFunction &MF = DAG.getMachineFunction();
2653 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2654 int ReturnAddrIndex = FuncInfo->getRAIndex();
2656 if (ReturnAddrIndex == 0) {
2657 // Set up a frame object for the return address.
2658 uint64_t SlotSize = TD->getPointerSize();
2659 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2661 FuncInfo->setRAIndex(ReturnAddrIndex);
2664 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2668 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2669 bool hasSymbolicDisplacement) {
2670 // Offset should fit into 32 bit immediate field.
2671 if (!isInt<32>(Offset))
2674 // If we don't have a symbolic displacement - we don't have any extra
2676 if (!hasSymbolicDisplacement)
2679 // FIXME: Some tweaks might be needed for medium code model.
2680 if (M != CodeModel::Small && M != CodeModel::Kernel)
2683 // For small code model we assume that latest object is 16MB before end of 31
2684 // bits boundary. We may also accept pretty large negative constants knowing
2685 // that all objects are in the positive half of address space.
2686 if (M == CodeModel::Small && Offset < 16*1024*1024)
2689 // For kernel code model we know that all object resist in the negative half
2690 // of 32bits address space. We may not accept negative offsets, since they may
2691 // be just off and we may accept pretty large positive ones.
2692 if (M == CodeModel::Kernel && Offset > 0)
2698 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2699 /// specific condition code, returning the condition code and the LHS/RHS of the
2700 /// comparison to make.
2701 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2702 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2704 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2705 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2706 // X > -1 -> X == 0, jump !sign.
2707 RHS = DAG.getConstant(0, RHS.getValueType());
2708 return X86::COND_NS;
2709 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2710 // X < 0 -> X == 0, jump on sign.
2712 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2714 RHS = DAG.getConstant(0, RHS.getValueType());
2715 return X86::COND_LE;
2719 switch (SetCCOpcode) {
2720 default: llvm_unreachable("Invalid integer condition!");
2721 case ISD::SETEQ: return X86::COND_E;
2722 case ISD::SETGT: return X86::COND_G;
2723 case ISD::SETGE: return X86::COND_GE;
2724 case ISD::SETLT: return X86::COND_L;
2725 case ISD::SETLE: return X86::COND_LE;
2726 case ISD::SETNE: return X86::COND_NE;
2727 case ISD::SETULT: return X86::COND_B;
2728 case ISD::SETUGT: return X86::COND_A;
2729 case ISD::SETULE: return X86::COND_BE;
2730 case ISD::SETUGE: return X86::COND_AE;
2734 // First determine if it is required or is profitable to flip the operands.
2736 // If LHS is a foldable load, but RHS is not, flip the condition.
2737 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2738 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2739 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2740 std::swap(LHS, RHS);
2743 switch (SetCCOpcode) {
2749 std::swap(LHS, RHS);
2753 // On a floating point condition, the flags are set as follows:
2755 // 0 | 0 | 0 | X > Y
2756 // 0 | 0 | 1 | X < Y
2757 // 1 | 0 | 0 | X == Y
2758 // 1 | 1 | 1 | unordered
2759 switch (SetCCOpcode) {
2760 default: llvm_unreachable("Condcode should be pre-legalized away");
2762 case ISD::SETEQ: return X86::COND_E;
2763 case ISD::SETOLT: // flipped
2765 case ISD::SETGT: return X86::COND_A;
2766 case ISD::SETOLE: // flipped
2768 case ISD::SETGE: return X86::COND_AE;
2769 case ISD::SETUGT: // flipped
2771 case ISD::SETLT: return X86::COND_B;
2772 case ISD::SETUGE: // flipped
2774 case ISD::SETLE: return X86::COND_BE;
2776 case ISD::SETNE: return X86::COND_NE;
2777 case ISD::SETUO: return X86::COND_P;
2778 case ISD::SETO: return X86::COND_NP;
2780 case ISD::SETUNE: return X86::COND_INVALID;
2784 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2785 /// code. Current x86 isa includes the following FP cmov instructions:
2786 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2787 static bool hasFPCMov(unsigned X86CC) {
2803 /// isFPImmLegal - Returns true if the target can instruction select the
2804 /// specified FP immediate natively. If false, the legalizer will
2805 /// materialize the FP immediate as a load from a constant pool.
2806 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2807 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
2808 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
2814 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2815 /// the specified range (L, H].
2816 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2817 return (Val < 0) || (Val >= Low && Val < Hi);
2820 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2821 /// specified value.
2822 static bool isUndefOrEqual(int Val, int CmpVal) {
2823 if (Val < 0 || Val == CmpVal)
2828 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2829 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2830 /// the second operand.
2831 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2832 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
2833 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2834 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2835 return (Mask[0] < 2 && Mask[1] < 2);
2839 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2840 SmallVector<int, 8> M;
2842 return ::isPSHUFDMask(M, N->getValueType(0));
2845 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2846 /// is suitable for input to PSHUFHW.
2847 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2848 if (VT != MVT::v8i16)
2851 // Lower quadword copied in order or undef.
2852 for (int i = 0; i != 4; ++i)
2853 if (Mask[i] >= 0 && Mask[i] != i)
2856 // Upper quadword shuffled.
2857 for (int i = 4; i != 8; ++i)
2858 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2864 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2865 SmallVector<int, 8> M;
2867 return ::isPSHUFHWMask(M, N->getValueType(0));
2870 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2871 /// is suitable for input to PSHUFLW.
2872 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2873 if (VT != MVT::v8i16)
2876 // Upper quadword copied in order.
2877 for (int i = 4; i != 8; ++i)
2878 if (Mask[i] >= 0 && Mask[i] != i)
2881 // Lower quadword shuffled.
2882 for (int i = 0; i != 4; ++i)
2889 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2890 SmallVector<int, 8> M;
2892 return ::isPSHUFLWMask(M, N->getValueType(0));
2895 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
2896 /// is suitable for input to PALIGNR.
2897 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
2899 int i, e = VT.getVectorNumElements();
2901 // Do not handle v2i64 / v2f64 shuffles with palignr.
2902 if (e < 4 || !hasSSSE3)
2905 for (i = 0; i != e; ++i)
2909 // All undef, not a palignr.
2913 // Determine if it's ok to perform a palignr with only the LHS, since we
2914 // don't have access to the actual shuffle elements to see if RHS is undef.
2915 bool Unary = Mask[i] < (int)e;
2916 bool NeedsUnary = false;
2918 int s = Mask[i] - i;
2920 // Check the rest of the elements to see if they are consecutive.
2921 for (++i; i != e; ++i) {
2926 Unary = Unary && (m < (int)e);
2927 NeedsUnary = NeedsUnary || (m < s);
2929 if (NeedsUnary && !Unary)
2931 if (Unary && m != ((s+i) & (e-1)))
2933 if (!Unary && m != (s+i))
2939 bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) {
2940 SmallVector<int, 8> M;
2942 return ::isPALIGNRMask(M, N->getValueType(0), true);
2945 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2946 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2947 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2948 int NumElems = VT.getVectorNumElements();
2949 if (NumElems != 2 && NumElems != 4)
2952 int Half = NumElems / 2;
2953 for (int i = 0; i < Half; ++i)
2954 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2956 for (int i = Half; i < NumElems; ++i)
2957 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2963 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
2964 SmallVector<int, 8> M;
2966 return ::isSHUFPMask(M, N->getValueType(0));
2969 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2970 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2971 /// half elements to come from vector 1 (which would equal the dest.) and
2972 /// the upper half to come from vector 2.
2973 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2974 int NumElems = VT.getVectorNumElements();
2976 if (NumElems != 2 && NumElems != 4)
2979 int Half = NumElems / 2;
2980 for (int i = 0; i < Half; ++i)
2981 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2983 for (int i = Half; i < NumElems; ++i)
2984 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2989 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
2990 SmallVector<int, 8> M;
2992 return isCommutedSHUFPMask(M, N->getValueType(0));
2995 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2996 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2997 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
2998 if (N->getValueType(0).getVectorNumElements() != 4)
3001 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3002 return isUndefOrEqual(N->getMaskElt(0), 6) &&
3003 isUndefOrEqual(N->getMaskElt(1), 7) &&
3004 isUndefOrEqual(N->getMaskElt(2), 2) &&
3005 isUndefOrEqual(N->getMaskElt(3), 3);
3008 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3009 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3011 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
3012 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3017 return isUndefOrEqual(N->getMaskElt(0), 2) &&
3018 isUndefOrEqual(N->getMaskElt(1), 3) &&
3019 isUndefOrEqual(N->getMaskElt(2), 2) &&
3020 isUndefOrEqual(N->getMaskElt(3), 3);
3023 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3024 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3025 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
3026 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3028 if (NumElems != 2 && NumElems != 4)
3031 for (unsigned i = 0; i < NumElems/2; ++i)
3032 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
3035 for (unsigned i = NumElems/2; i < NumElems; ++i)
3036 if (!isUndefOrEqual(N->getMaskElt(i), i))
3042 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3043 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3044 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
3045 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3047 if (NumElems != 2 && NumElems != 4)
3050 for (unsigned i = 0; i < NumElems/2; ++i)
3051 if (!isUndefOrEqual(N->getMaskElt(i), i))
3054 for (unsigned i = 0; i < NumElems/2; ++i)
3055 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
3061 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3062 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3063 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3064 bool V2IsSplat = false) {
3065 int NumElts = VT.getVectorNumElements();
3066 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
3069 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
3071 int BitI1 = Mask[i+1];
3072 if (!isUndefOrEqual(BitI, j))
3075 if (!isUndefOrEqual(BitI1, NumElts))
3078 if (!isUndefOrEqual(BitI1, j + NumElts))
3085 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3086 SmallVector<int, 8> M;
3088 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
3091 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3092 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3093 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
3094 bool V2IsSplat = false) {
3095 int NumElts = VT.getVectorNumElements();
3096 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
3099 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
3101 int BitI1 = Mask[i+1];
3102 if (!isUndefOrEqual(BitI, j + NumElts/2))
3105 if (isUndefOrEqual(BitI1, NumElts))
3108 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
3115 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3116 SmallVector<int, 8> M;
3118 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
3121 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3122 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3124 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3125 int NumElems = VT.getVectorNumElements();
3126 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3129 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
3131 int BitI1 = Mask[i+1];
3132 if (!isUndefOrEqual(BitI, j))
3134 if (!isUndefOrEqual(BitI1, j))
3140 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
3141 SmallVector<int, 8> M;
3143 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
3146 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3147 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3149 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3150 int NumElems = VT.getVectorNumElements();
3151 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3154 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
3156 int BitI1 = Mask[i+1];
3157 if (!isUndefOrEqual(BitI, j))
3159 if (!isUndefOrEqual(BitI1, j))
3165 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
3166 SmallVector<int, 8> M;
3168 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
3171 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3172 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3173 /// MOVSD, and MOVD, i.e. setting the lowest element.
3174 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3175 if (VT.getVectorElementType().getSizeInBits() < 32)
3178 int NumElts = VT.getVectorNumElements();
3180 if (!isUndefOrEqual(Mask[0], NumElts))
3183 for (int i = 1; i < NumElts; ++i)
3184 if (!isUndefOrEqual(Mask[i], i))
3190 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3191 SmallVector<int, 8> M;
3193 return ::isMOVLMask(M, N->getValueType(0));
3196 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3197 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3198 /// element of vector 2 and the other elements to come from vector 1 in order.
3199 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3200 bool V2IsSplat = false, bool V2IsUndef = false) {
3201 int NumOps = VT.getVectorNumElements();
3202 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3205 if (!isUndefOrEqual(Mask[0], 0))
3208 for (int i = 1; i < NumOps; ++i)
3209 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3210 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3211 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3217 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3218 bool V2IsUndef = false) {
3219 SmallVector<int, 8> M;
3221 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
3224 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3225 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3226 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
3227 if (N->getValueType(0).getVectorNumElements() != 4)
3230 // Expect 1, 1, 3, 3
3231 for (unsigned i = 0; i < 2; ++i) {
3232 int Elt = N->getMaskElt(i);
3233 if (Elt >= 0 && Elt != 1)
3238 for (unsigned i = 2; i < 4; ++i) {
3239 int Elt = N->getMaskElt(i);
3240 if (Elt >= 0 && Elt != 3)
3245 // Don't use movshdup if it can be done with a shufps.
3246 // FIXME: verify that matching u, u, 3, 3 is what we want.
3250 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3251 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3252 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
3253 if (N->getValueType(0).getVectorNumElements() != 4)
3256 // Expect 0, 0, 2, 2
3257 for (unsigned i = 0; i < 2; ++i)
3258 if (N->getMaskElt(i) > 0)
3262 for (unsigned i = 2; i < 4; ++i) {
3263 int Elt = N->getMaskElt(i);
3264 if (Elt >= 0 && Elt != 2)
3269 // Don't use movsldup if it can be done with a shufps.
3273 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3274 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
3275 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3276 int e = N->getValueType(0).getVectorNumElements() / 2;
3278 for (int i = 0; i < e; ++i)
3279 if (!isUndefOrEqual(N->getMaskElt(i), i))
3281 for (int i = 0; i < e; ++i)
3282 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3287 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3288 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3289 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
3290 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3291 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
3293 unsigned Shift = (NumOperands == 4) ? 2 : 1;
3295 for (int i = 0; i < NumOperands; ++i) {
3296 int Val = SVOp->getMaskElt(NumOperands-i-1);
3297 if (Val < 0) Val = 0;
3298 if (Val >= NumOperands) Val -= NumOperands;
3300 if (i != NumOperands - 1)
3306 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3307 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3308 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3309 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3311 // 8 nodes, but we only care about the last 4.
3312 for (unsigned i = 7; i >= 4; --i) {
3313 int Val = SVOp->getMaskElt(i);
3322 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3323 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3324 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3325 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3327 // 8 nodes, but we only care about the first 4.
3328 for (int i = 3; i >= 0; --i) {
3329 int Val = SVOp->getMaskElt(i);
3338 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3339 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3340 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
3341 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3342 EVT VVT = N->getValueType(0);
3343 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
3347 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
3348 Val = SVOp->getMaskElt(i);
3352 return (Val - i) * EltSize;
3355 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3357 bool X86::isZeroNode(SDValue Elt) {
3358 return ((isa<ConstantSDNode>(Elt) &&
3359 cast<ConstantSDNode>(Elt)->isNullValue()) ||
3360 (isa<ConstantFPSDNode>(Elt) &&
3361 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
3364 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
3365 /// their permute mask.
3366 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
3367 SelectionDAG &DAG) {
3368 EVT VT = SVOp->getValueType(0);
3369 unsigned NumElems = VT.getVectorNumElements();
3370 SmallVector<int, 8> MaskVec;
3372 for (unsigned i = 0; i != NumElems; ++i) {
3373 int idx = SVOp->getMaskElt(i);
3375 MaskVec.push_back(idx);
3376 else if (idx < (int)NumElems)
3377 MaskVec.push_back(idx + NumElems);
3379 MaskVec.push_back(idx - NumElems);
3381 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
3382 SVOp->getOperand(0), &MaskVec[0]);
3385 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3386 /// the two vector operands have swapped position.
3387 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
3388 unsigned NumElems = VT.getVectorNumElements();
3389 for (unsigned i = 0; i != NumElems; ++i) {
3393 else if (idx < (int)NumElems)
3394 Mask[i] = idx + NumElems;
3396 Mask[i] = idx - NumElems;
3400 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
3401 /// match movhlps. The lower half elements should come from upper half of
3402 /// V1 (and in order), and the upper half elements should come from the upper
3403 /// half of V2 (and in order).
3404 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
3405 if (Op->getValueType(0).getVectorNumElements() != 4)
3407 for (unsigned i = 0, e = 2; i != e; ++i)
3408 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
3410 for (unsigned i = 2; i != 4; ++i)
3411 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
3416 /// isScalarLoadToVector - Returns true if the node is a scalar load that
3417 /// is promoted to a vector. It also returns the LoadSDNode by reference if
3419 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
3420 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
3422 N = N->getOperand(0).getNode();
3423 if (!ISD::isNON_EXTLoad(N))
3426 *LD = cast<LoadSDNode>(N);
3430 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
3431 /// match movlp{s|d}. The lower half elements should come from lower half of
3432 /// V1 (and in order), and the upper half elements should come from the upper
3433 /// half of V2 (and in order). And since V1 will become the source of the
3434 /// MOVLP, it must be either a vector load or a scalar load to vector.
3435 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
3436 ShuffleVectorSDNode *Op) {
3437 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
3439 // Is V2 is a vector load, don't do this transformation. We will try to use
3440 // load folding shufps op.
3441 if (ISD::isNON_EXTLoad(V2))
3444 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
3446 if (NumElems != 2 && NumElems != 4)
3448 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3449 if (!isUndefOrEqual(Op->getMaskElt(i), i))
3451 for (unsigned i = NumElems/2; i != NumElems; ++i)
3452 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
3457 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
3459 static bool isSplatVector(SDNode *N) {
3460 if (N->getOpcode() != ISD::BUILD_VECTOR)
3463 SDValue SplatValue = N->getOperand(0);
3464 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
3465 if (N->getOperand(i) != SplatValue)
3470 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
3471 /// to an zero vector.
3472 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
3473 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
3474 SDValue V1 = N->getOperand(0);
3475 SDValue V2 = N->getOperand(1);
3476 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3477 for (unsigned i = 0; i != NumElems; ++i) {
3478 int Idx = N->getMaskElt(i);
3479 if (Idx >= (int)NumElems) {
3480 unsigned Opc = V2.getOpcode();
3481 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
3483 if (Opc != ISD::BUILD_VECTOR ||
3484 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
3486 } else if (Idx >= 0) {
3487 unsigned Opc = V1.getOpcode();
3488 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
3490 if (Opc != ISD::BUILD_VECTOR ||
3491 !X86::isZeroNode(V1.getOperand(Idx)))
3498 /// getZeroVector - Returns a vector of specified type with all zero elements.
3500 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
3502 assert(VT.isVector() && "Expected a vector type");
3504 // Always build SSE zero vectors as <4 x i32> bitcasted
3505 // to their dest type. This ensures they get CSE'd.
3507 if (VT.getSizeInBits() == 128) { // SSE
3508 if (HasSSE2) { // SSE2
3509 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3510 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3512 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3513 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3515 } else if (VT.getSizeInBits() == 256) { // AVX
3516 // 256-bit logic and arithmetic instructions in AVX are
3517 // all floating-point, no support for integer ops. Default
3518 // to emitting fp zeroed vectors then.
3519 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3520 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
3521 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
3523 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
3526 /// getOnesVector - Returns a vector of specified type with all bits set.
3528 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3529 assert(VT.isVector() && "Expected a vector type");
3531 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3532 // type. This ensures they get CSE'd.
3533 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
3535 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3536 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
3540 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
3541 /// that point to V2 points to its first element.
3542 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3543 EVT VT = SVOp->getValueType(0);
3544 unsigned NumElems = VT.getVectorNumElements();
3546 bool Changed = false;
3547 SmallVector<int, 8> MaskVec;
3548 SVOp->getMask(MaskVec);
3550 for (unsigned i = 0; i != NumElems; ++i) {
3551 if (MaskVec[i] > (int)NumElems) {
3552 MaskVec[i] = NumElems;
3557 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
3558 SVOp->getOperand(1), &MaskVec[0]);
3559 return SDValue(SVOp, 0);
3562 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
3563 /// operation of specified width.
3564 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3566 unsigned NumElems = VT.getVectorNumElements();
3567 SmallVector<int, 8> Mask;
3568 Mask.push_back(NumElems);
3569 for (unsigned i = 1; i != NumElems; ++i)
3571 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3574 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
3575 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3577 unsigned NumElems = VT.getVectorNumElements();
3578 SmallVector<int, 8> Mask;
3579 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3581 Mask.push_back(i + NumElems);
3583 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3586 /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
3587 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3589 unsigned NumElems = VT.getVectorNumElements();
3590 unsigned Half = NumElems/2;
3591 SmallVector<int, 8> Mask;
3592 for (unsigned i = 0; i != Half; ++i) {
3593 Mask.push_back(i + Half);
3594 Mask.push_back(i + NumElems + Half);
3596 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3599 /// PromoteSplat - Promote a splat of v4i32, v8i16 or v16i8 to v4f32.
3600 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
3601 EVT PVT = MVT::v4f32;
3602 EVT VT = SV->getValueType(0);
3603 DebugLoc dl = SV->getDebugLoc();
3604 SDValue V1 = SV->getOperand(0);
3605 int NumElems = VT.getVectorNumElements();
3606 int EltNo = SV->getSplatIndex();
3608 // unpack elements to the correct location
3609 while (NumElems > 4) {
3610 if (EltNo < NumElems/2) {
3611 V1 = getUnpackl(DAG, dl, VT, V1, V1);
3613 V1 = getUnpackh(DAG, dl, VT, V1, V1);
3614 EltNo -= NumElems/2;
3619 // Perform the splat.
3620 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
3621 V1 = DAG.getNode(ISD::BITCAST, dl, PVT, V1);
3622 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3623 return DAG.getNode(ISD::BITCAST, dl, VT, V1);
3626 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3627 /// vector of zero or undef vector. This produces a shuffle where the low
3628 /// element of V2 is swizzled into the zero/undef vector, landing at element
3629 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3630 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3631 bool isZero, bool HasSSE2,
3632 SelectionDAG &DAG) {
3633 EVT VT = V2.getValueType();
3635 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3636 unsigned NumElems = VT.getVectorNumElements();
3637 SmallVector<int, 16> MaskVec;
3638 for (unsigned i = 0; i != NumElems; ++i)
3639 // If this is the insertion idx, put the low elt of V2 here.
3640 MaskVec.push_back(i == Idx ? NumElems : i);
3641 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3644 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
3645 /// element of the result of the vector shuffle.
3646 SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
3649 return SDValue(); // Limit search depth.
3651 SDValue V = SDValue(N, 0);
3652 EVT VT = V.getValueType();
3653 unsigned Opcode = V.getOpcode();
3655 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
3656 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
3657 Index = SV->getMaskElt(Index);
3660 return DAG.getUNDEF(VT.getVectorElementType());
3662 int NumElems = VT.getVectorNumElements();
3663 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1);
3664 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
3667 // Recurse into target specific vector shuffles to find scalars.
3668 if (isTargetShuffle(Opcode)) {
3669 int NumElems = VT.getVectorNumElements();
3670 SmallVector<unsigned, 16> ShuffleMask;
3674 case X86ISD::SHUFPS:
3675 case X86ISD::SHUFPD:
3676 ImmN = N->getOperand(N->getNumOperands()-1);
3677 DecodeSHUFPSMask(NumElems,
3678 cast<ConstantSDNode>(ImmN)->getZExtValue(),
3681 case X86ISD::PUNPCKHBW:
3682 case X86ISD::PUNPCKHWD:
3683 case X86ISD::PUNPCKHDQ:
3684 case X86ISD::PUNPCKHQDQ:
3685 DecodePUNPCKHMask(NumElems, ShuffleMask);
3687 case X86ISD::UNPCKHPS:
3688 case X86ISD::UNPCKHPD:
3689 DecodeUNPCKHPMask(NumElems, ShuffleMask);
3691 case X86ISD::PUNPCKLBW:
3692 case X86ISD::PUNPCKLWD:
3693 case X86ISD::PUNPCKLDQ:
3694 case X86ISD::PUNPCKLQDQ:
3695 DecodePUNPCKLMask(NumElems, ShuffleMask);
3697 case X86ISD::UNPCKLPS:
3698 case X86ISD::UNPCKLPD:
3699 DecodeUNPCKLPMask(NumElems, ShuffleMask);
3701 case X86ISD::MOVHLPS:
3702 DecodeMOVHLPSMask(NumElems, ShuffleMask);
3704 case X86ISD::MOVLHPS:
3705 DecodeMOVLHPSMask(NumElems, ShuffleMask);
3707 case X86ISD::PSHUFD:
3708 ImmN = N->getOperand(N->getNumOperands()-1);
3709 DecodePSHUFMask(NumElems,
3710 cast<ConstantSDNode>(ImmN)->getZExtValue(),
3713 case X86ISD::PSHUFHW:
3714 ImmN = N->getOperand(N->getNumOperands()-1);
3715 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
3718 case X86ISD::PSHUFLW:
3719 ImmN = N->getOperand(N->getNumOperands()-1);
3720 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
3724 case X86ISD::MOVSD: {
3725 // The index 0 always comes from the first element of the second source,
3726 // this is why MOVSS and MOVSD are used in the first place. The other
3727 // elements come from the other positions of the first source vector.
3728 unsigned OpNum = (Index == 0) ? 1 : 0;
3729 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
3733 assert("not implemented for target shuffle node");
3737 Index = ShuffleMask[Index];
3739 return DAG.getUNDEF(VT.getVectorElementType());
3741 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
3742 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
3746 // Actual nodes that may contain scalar elements
3747 if (Opcode == ISD::BITCAST) {
3748 V = V.getOperand(0);
3749 EVT SrcVT = V.getValueType();
3750 unsigned NumElems = VT.getVectorNumElements();
3752 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
3756 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
3757 return (Index == 0) ? V.getOperand(0)
3758 : DAG.getUNDEF(VT.getVectorElementType());
3760 if (V.getOpcode() == ISD::BUILD_VECTOR)
3761 return V.getOperand(Index);
3766 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
3767 /// shuffle operation which come from a consecutively from a zero. The
3768 /// search can start in two diferent directions, from left or right.
3770 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
3771 bool ZerosFromLeft, SelectionDAG &DAG) {
3774 while (i < NumElems) {
3775 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
3776 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
3777 if (!(Elt.getNode() &&
3778 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
3786 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
3787 /// MaskE correspond consecutively to elements from one of the vector operands,
3788 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
3790 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
3791 int OpIdx, int NumElems, unsigned &OpNum) {
3792 bool SeenV1 = false;
3793 bool SeenV2 = false;
3795 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
3796 int Idx = SVOp->getMaskElt(i);
3797 // Ignore undef indicies
3806 // Only accept consecutive elements from the same vector
3807 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
3811 OpNum = SeenV1 ? 0 : 1;
3815 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
3816 /// logical left shift of a vector.
3817 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3818 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3819 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
3820 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
3821 false /* check zeros from right */, DAG);
3827 // Considering the elements in the mask that are not consecutive zeros,
3828 // check if they consecutively come from only one of the source vectors.
3830 // V1 = {X, A, B, C} 0
3832 // vector_shuffle V1, V2 <1, 2, 3, X>
3834 if (!isShuffleMaskConsecutive(SVOp,
3835 0, // Mask Start Index
3836 NumElems-NumZeros-1, // Mask End Index
3837 NumZeros, // Where to start looking in the src vector
3838 NumElems, // Number of elements in vector
3839 OpSrc)) // Which source operand ?
3844 ShVal = SVOp->getOperand(OpSrc);
3848 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
3849 /// logical left shift of a vector.
3850 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3851 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3852 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
3853 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
3854 true /* check zeros from left */, DAG);
3860 // Considering the elements in the mask that are not consecutive zeros,
3861 // check if they consecutively come from only one of the source vectors.
3863 // 0 { A, B, X, X } = V2
3865 // vector_shuffle V1, V2 <X, X, 4, 5>
3867 if (!isShuffleMaskConsecutive(SVOp,
3868 NumZeros, // Mask Start Index
3869 NumElems-1, // Mask End Index
3870 0, // Where to start looking in the src vector
3871 NumElems, // Number of elements in vector
3872 OpSrc)) // Which source operand ?
3877 ShVal = SVOp->getOperand(OpSrc);
3881 /// isVectorShift - Returns true if the shuffle can be implemented as a
3882 /// logical left or right shift of a vector.
3883 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3884 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3885 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
3886 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
3892 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3894 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3895 unsigned NumNonZero, unsigned NumZero,
3897 const TargetLowering &TLI) {
3901 DebugLoc dl = Op.getDebugLoc();
3904 for (unsigned i = 0; i < 16; ++i) {
3905 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3906 if (ThisIsNonZero && First) {
3908 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3910 V = DAG.getUNDEF(MVT::v8i16);
3915 SDValue ThisElt(0, 0), LastElt(0, 0);
3916 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3917 if (LastIsNonZero) {
3918 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3919 MVT::i16, Op.getOperand(i-1));
3921 if (ThisIsNonZero) {
3922 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3923 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3924 ThisElt, DAG.getConstant(8, MVT::i8));
3926 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3930 if (ThisElt.getNode())
3931 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3932 DAG.getIntPtrConstant(i/2));
3936 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
3939 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3941 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3942 unsigned NumNonZero, unsigned NumZero,
3944 const TargetLowering &TLI) {
3948 DebugLoc dl = Op.getDebugLoc();
3951 for (unsigned i = 0; i < 8; ++i) {
3952 bool isNonZero = (NonZeros & (1 << i)) != 0;
3956 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3958 V = DAG.getUNDEF(MVT::v8i16);
3961 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3962 MVT::v8i16, V, Op.getOperand(i),
3963 DAG.getIntPtrConstant(i));
3970 /// getVShift - Return a vector logical shift node.
3972 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
3973 unsigned NumBits, SelectionDAG &DAG,
3974 const TargetLowering &TLI, DebugLoc dl) {
3975 EVT ShVT = MVT::v2i64;
3976 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3977 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
3978 return DAG.getNode(ISD::BITCAST, dl, VT,
3979 DAG.getNode(Opc, dl, ShVT, SrcOp,
3980 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3984 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
3985 SelectionDAG &DAG) const {
3987 // Check if the scalar load can be widened into a vector load. And if
3988 // the address is "base + cst" see if the cst can be "absorbed" into
3989 // the shuffle mask.
3990 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
3991 SDValue Ptr = LD->getBasePtr();
3992 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
3994 EVT PVT = LD->getValueType(0);
3995 if (PVT != MVT::i32 && PVT != MVT::f32)
4000 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4001 FI = FINode->getIndex();
4003 } else if (Ptr.getOpcode() == ISD::ADD &&
4004 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
4005 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4006 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4007 Offset = Ptr.getConstantOperandVal(1);
4008 Ptr = Ptr.getOperand(0);
4013 SDValue Chain = LD->getChain();
4014 // Make sure the stack object alignment is at least 16.
4015 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4016 if (DAG.InferPtrAlignment(Ptr) < 16) {
4017 if (MFI->isFixedObjectIndex(FI)) {
4018 // Can't change the alignment. FIXME: It's possible to compute
4019 // the exact stack offset and reference FI + adjust offset instead.
4020 // If someone *really* cares about this. That's the way to implement it.
4023 MFI->setObjectAlignment(FI, 16);
4027 // (Offset % 16) must be multiple of 4. Then address is then
4028 // Ptr + (Offset & ~15).
4031 if ((Offset % 16) & 3)
4033 int64_t StartOffset = Offset & ~15;
4035 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4036 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4038 int EltNo = (Offset - StartOffset) >> 2;
4039 int Mask[4] = { EltNo, EltNo, EltNo, EltNo };
4040 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32;
4041 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,
4042 LD->getPointerInfo().getWithOffset(StartOffset),
4044 // Canonicalize it to a v4i32 shuffle.
4045 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1);
4046 return DAG.getNode(ISD::BITCAST, dl, VT,
4047 DAG.getVectorShuffle(MVT::v4i32, dl, V1,
4048 DAG.getUNDEF(MVT::v4i32),&Mask[0]));
4054 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4055 /// vector of type 'VT', see if the elements can be replaced by a single large
4056 /// load which has the same value as a build_vector whose operands are 'elts'.
4058 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4060 /// FIXME: we'd also like to handle the case where the last elements are zero
4061 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4062 /// There's even a handy isZeroNode for that purpose.
4063 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4064 DebugLoc &DL, SelectionDAG &DAG) {
4065 EVT EltVT = VT.getVectorElementType();
4066 unsigned NumElems = Elts.size();
4068 LoadSDNode *LDBase = NULL;
4069 unsigned LastLoadedElt = -1U;
4071 // For each element in the initializer, see if we've found a load or an undef.
4072 // If we don't find an initial load element, or later load elements are
4073 // non-consecutive, bail out.
4074 for (unsigned i = 0; i < NumElems; ++i) {
4075 SDValue Elt = Elts[i];
4077 if (!Elt.getNode() ||
4078 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4081 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4083 LDBase = cast<LoadSDNode>(Elt.getNode());
4087 if (Elt.getOpcode() == ISD::UNDEF)
4090 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4091 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4096 // If we have found an entire vector of loads and undefs, then return a large
4097 // load of the entire vector width starting at the base pointer. If we found
4098 // consecutive loads for the low half, generate a vzext_load node.
4099 if (LastLoadedElt == NumElems - 1) {
4100 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4101 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4102 LDBase->getPointerInfo(),
4103 LDBase->isVolatile(), LDBase->isNonTemporal(), 0);
4104 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4105 LDBase->getPointerInfo(),
4106 LDBase->isVolatile(), LDBase->isNonTemporal(),
4107 LDBase->getAlignment());
4108 } else if (NumElems == 4 && LastLoadedElt == 1) {
4109 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4110 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4111 SDValue ResNode = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys,
4113 LDBase->getMemOperand());
4114 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4120 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
4121 DebugLoc dl = Op.getDebugLoc();
4122 // All zero's are handled with pxor in SSE2 and above, xorps in SSE1.
4123 // All one's are handled with pcmpeqd. In AVX, zero's are handled with
4124 // vpxor in 128-bit and xor{pd,ps} in 256-bit, but no 256 version of pcmpeqd
4125 // is present, so AllOnes is ignored.
4126 if (ISD::isBuildVectorAllZeros(Op.getNode()) ||
4127 (Op.getValueType().getSizeInBits() != 256 &&
4128 ISD::isBuildVectorAllOnes(Op.getNode()))) {
4129 // Canonicalize this to <4 x i32> (SSE) to
4130 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
4131 // eliminated on x86-32 hosts.
4132 if (Op.getValueType() == MVT::v4i32)
4135 if (ISD::isBuildVectorAllOnes(Op.getNode()))
4136 return getOnesVector(Op.getValueType(), DAG, dl);
4137 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
4140 EVT VT = Op.getValueType();
4141 EVT ExtVT = VT.getVectorElementType();
4142 unsigned EVTBits = ExtVT.getSizeInBits();
4144 unsigned NumElems = Op.getNumOperands();
4145 unsigned NumZero = 0;
4146 unsigned NumNonZero = 0;
4147 unsigned NonZeros = 0;
4148 bool IsAllConstants = true;
4149 SmallSet<SDValue, 8> Values;
4150 for (unsigned i = 0; i < NumElems; ++i) {
4151 SDValue Elt = Op.getOperand(i);
4152 if (Elt.getOpcode() == ISD::UNDEF)
4155 if (Elt.getOpcode() != ISD::Constant &&
4156 Elt.getOpcode() != ISD::ConstantFP)
4157 IsAllConstants = false;
4158 if (X86::isZeroNode(Elt))
4161 NonZeros |= (1 << i);
4166 // All undef vector. Return an UNDEF. All zero vectors were handled above.
4167 if (NumNonZero == 0)
4168 return DAG.getUNDEF(VT);
4170 // Special case for single non-zero, non-undef, element.
4171 if (NumNonZero == 1) {
4172 unsigned Idx = CountTrailingZeros_32(NonZeros);
4173 SDValue Item = Op.getOperand(Idx);
4175 // If this is an insertion of an i64 value on x86-32, and if the top bits of
4176 // the value are obviously zero, truncate the value to i32 and do the
4177 // insertion that way. Only do this if the value is non-constant or if the
4178 // value is a constant being inserted into element 0. It is cheaper to do
4179 // a constant pool load than it is to do a movd + shuffle.
4180 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
4181 (!IsAllConstants || Idx == 0)) {
4182 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
4184 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
4185 EVT VecVT = MVT::v4i32;
4186 unsigned VecElts = 4;
4188 // Truncate the value (which may itself be a constant) to i32, and
4189 // convert it to a vector with movd (S2V+shuffle to zero extend).
4190 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
4191 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
4192 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
4193 Subtarget->hasSSE2(), DAG);
4195 // Now we have our 32-bit value zero extended in the low element of
4196 // a vector. If Idx != 0, swizzle it into place.
4198 SmallVector<int, 4> Mask;
4199 Mask.push_back(Idx);
4200 for (unsigned i = 1; i != VecElts; ++i)
4202 Item = DAG.getVectorShuffle(VecVT, dl, Item,
4203 DAG.getUNDEF(Item.getValueType()),
4206 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item);
4210 // If we have a constant or non-constant insertion into the low element of
4211 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
4212 // the rest of the elements. This will be matched as movd/movq/movss/movsd
4213 // depending on what the source datatype is.
4216 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4217 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
4218 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
4219 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4220 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
4221 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
4223 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
4224 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
4225 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
4226 EVT MiddleVT = MVT::v4i32;
4227 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
4228 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
4229 Subtarget->hasSSE2(), DAG);
4230 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
4234 // Is it a vector logical left shift?
4235 if (NumElems == 2 && Idx == 1 &&
4236 X86::isZeroNode(Op.getOperand(0)) &&
4237 !X86::isZeroNode(Op.getOperand(1))) {
4238 unsigned NumBits = VT.getSizeInBits();
4239 return getVShift(true, VT,
4240 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4241 VT, Op.getOperand(1)),
4242 NumBits/2, DAG, *this, dl);
4245 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
4248 // Otherwise, if this is a vector with i32 or f32 elements, and the element
4249 // is a non-constant being inserted into an element other than the low one,
4250 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
4251 // movd/movss) to move this into the low element, then shuffle it into
4253 if (EVTBits == 32) {
4254 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4256 // Turn it into a shuffle of zero and zero-extended scalar to vector.
4257 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
4258 Subtarget->hasSSE2(), DAG);
4259 SmallVector<int, 8> MaskVec;
4260 for (unsigned i = 0; i < NumElems; i++)
4261 MaskVec.push_back(i == Idx ? 0 : 1);
4262 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
4266 // Splat is obviously ok. Let legalizer expand it to a shuffle.
4267 if (Values.size() == 1) {
4268 if (EVTBits == 32) {
4269 // Instead of a shuffle like this:
4270 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
4271 // Check if it's possible to issue this instead.
4272 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
4273 unsigned Idx = CountTrailingZeros_32(NonZeros);
4274 SDValue Item = Op.getOperand(Idx);
4275 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
4276 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
4281 // A vector full of immediates; various special cases are already
4282 // handled, so this is best done with a single constant-pool load.
4286 // Let legalizer expand 2-wide build_vectors.
4287 if (EVTBits == 64) {
4288 if (NumNonZero == 1) {
4289 // One half is zero or undef.
4290 unsigned Idx = CountTrailingZeros_32(NonZeros);
4291 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
4292 Op.getOperand(Idx));
4293 return getShuffleVectorZeroOrUndef(V2, Idx, true,
4294 Subtarget->hasSSE2(), DAG);
4299 // If element VT is < 32 bits, convert it to inserts into a zero vector.
4300 if (EVTBits == 8 && NumElems == 16) {
4301 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
4303 if (V.getNode()) return V;
4306 if (EVTBits == 16 && NumElems == 8) {
4307 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
4309 if (V.getNode()) return V;
4312 // If element VT is == 32 bits, turn it into a number of shuffles.
4313 SmallVector<SDValue, 8> V;
4315 if (NumElems == 4 && NumZero > 0) {
4316 for (unsigned i = 0; i < 4; ++i) {
4317 bool isZero = !(NonZeros & (1 << i));
4319 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4321 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
4324 for (unsigned i = 0; i < 2; ++i) {
4325 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
4328 V[i] = V[i*2]; // Must be a zero vector.
4331 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
4334 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
4337 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
4342 SmallVector<int, 8> MaskVec;
4343 bool Reverse = (NonZeros & 0x3) == 2;
4344 for (unsigned i = 0; i < 2; ++i)
4345 MaskVec.push_back(Reverse ? 1-i : i);
4346 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
4347 for (unsigned i = 0; i < 2; ++i)
4348 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
4349 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
4352 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
4353 // Check for a build vector of consecutive loads.
4354 for (unsigned i = 0; i < NumElems; ++i)
4355 V[i] = Op.getOperand(i);
4357 // Check for elements which are consecutive loads.
4358 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
4362 // For SSE 4.1, use insertps to put the high elements into the low element.
4363 if (getSubtarget()->hasSSE41()) {
4365 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
4366 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
4368 Result = DAG.getUNDEF(VT);
4370 for (unsigned i = 1; i < NumElems; ++i) {
4371 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
4372 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
4373 Op.getOperand(i), DAG.getIntPtrConstant(i));
4378 // Otherwise, expand into a number of unpckl*, start by extending each of
4379 // our (non-undef) elements to the full vector width with the element in the
4380 // bottom slot of the vector (which generates no code for SSE).
4381 for (unsigned i = 0; i < NumElems; ++i) {
4382 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
4383 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
4385 V[i] = DAG.getUNDEF(VT);
4388 // Next, we iteratively mix elements, e.g. for v4f32:
4389 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
4390 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
4391 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
4392 unsigned EltStride = NumElems >> 1;
4393 while (EltStride != 0) {
4394 for (unsigned i = 0; i < EltStride; ++i) {
4395 // If V[i+EltStride] is undef and this is the first round of mixing,
4396 // then it is safe to just drop this shuffle: V[i] is already in the
4397 // right place, the one element (since it's the first round) being
4398 // inserted as undef can be dropped. This isn't safe for successive
4399 // rounds because they will permute elements within both vectors.
4400 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
4401 EltStride == NumElems/2)
4404 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
4414 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
4415 // We support concatenate two MMX registers and place them in a MMX
4416 // register. This is better than doing a stack convert.
4417 DebugLoc dl = Op.getDebugLoc();
4418 EVT ResVT = Op.getValueType();
4419 assert(Op.getNumOperands() == 2);
4420 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
4421 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
4423 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
4424 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4425 InVec = Op.getOperand(1);
4426 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4427 unsigned NumElts = ResVT.getVectorNumElements();
4428 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
4429 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
4430 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
4432 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
4433 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4434 Mask[0] = 0; Mask[1] = 2;
4435 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
4437 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
4440 // v8i16 shuffles - Prefer shuffles in the following order:
4441 // 1. [all] pshuflw, pshufhw, optional move
4442 // 2. [ssse3] 1 x pshufb
4443 // 3. [ssse3] 2 x pshufb + 1 x por
4444 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
4446 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
4447 SelectionDAG &DAG) const {
4448 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4449 SDValue V1 = SVOp->getOperand(0);
4450 SDValue V2 = SVOp->getOperand(1);
4451 DebugLoc dl = SVOp->getDebugLoc();
4452 SmallVector<int, 8> MaskVals;
4454 // Determine if more than 1 of the words in each of the low and high quadwords
4455 // of the result come from the same quadword of one of the two inputs. Undef
4456 // mask values count as coming from any quadword, for better codegen.
4457 SmallVector<unsigned, 4> LoQuad(4);
4458 SmallVector<unsigned, 4> HiQuad(4);
4459 BitVector InputQuads(4);
4460 for (unsigned i = 0; i < 8; ++i) {
4461 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
4462 int EltIdx = SVOp->getMaskElt(i);
4463 MaskVals.push_back(EltIdx);
4472 InputQuads.set(EltIdx / 4);
4475 int BestLoQuad = -1;
4476 unsigned MaxQuad = 1;
4477 for (unsigned i = 0; i < 4; ++i) {
4478 if (LoQuad[i] > MaxQuad) {
4480 MaxQuad = LoQuad[i];
4484 int BestHiQuad = -1;
4486 for (unsigned i = 0; i < 4; ++i) {
4487 if (HiQuad[i] > MaxQuad) {
4489 MaxQuad = HiQuad[i];
4493 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
4494 // of the two input vectors, shuffle them into one input vector so only a
4495 // single pshufb instruction is necessary. If There are more than 2 input
4496 // quads, disable the next transformation since it does not help SSSE3.
4497 bool V1Used = InputQuads[0] || InputQuads[1];
4498 bool V2Used = InputQuads[2] || InputQuads[3];
4499 if (Subtarget->hasSSSE3()) {
4500 if (InputQuads.count() == 2 && V1Used && V2Used) {
4501 BestLoQuad = InputQuads.find_first();
4502 BestHiQuad = InputQuads.find_next(BestLoQuad);
4504 if (InputQuads.count() > 2) {
4510 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
4511 // the shuffle mask. If a quad is scored as -1, that means that it contains
4512 // words from all 4 input quadwords.
4514 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
4515 SmallVector<int, 8> MaskV;
4516 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
4517 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
4518 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
4519 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
4520 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
4521 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
4523 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
4524 // source words for the shuffle, to aid later transformations.
4525 bool AllWordsInNewV = true;
4526 bool InOrder[2] = { true, true };
4527 for (unsigned i = 0; i != 8; ++i) {
4528 int idx = MaskVals[i];
4530 InOrder[i/4] = false;
4531 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
4533 AllWordsInNewV = false;
4537 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
4538 if (AllWordsInNewV) {
4539 for (int i = 0; i != 8; ++i) {
4540 int idx = MaskVals[i];
4543 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
4544 if ((idx != i) && idx < 4)
4546 if ((idx != i) && idx > 3)
4555 // If we've eliminated the use of V2, and the new mask is a pshuflw or
4556 // pshufhw, that's as cheap as it gets. Return the new shuffle.
4557 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
4558 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
4559 unsigned TargetMask = 0;
4560 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
4561 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
4562 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()):
4563 X86::getShufflePSHUFLWImmediate(NewV.getNode());
4564 V1 = NewV.getOperand(0);
4565 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
4569 // If we have SSSE3, and all words of the result are from 1 input vector,
4570 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
4571 // is present, fall back to case 4.
4572 if (Subtarget->hasSSSE3()) {
4573 SmallVector<SDValue,16> pshufbMask;
4575 // If we have elements from both input vectors, set the high bit of the
4576 // shuffle mask element to zero out elements that come from V2 in the V1
4577 // mask, and elements that come from V1 in the V2 mask, so that the two
4578 // results can be OR'd together.
4579 bool TwoInputs = V1Used && V2Used;
4580 for (unsigned i = 0; i != 8; ++i) {
4581 int EltIdx = MaskVals[i] * 2;
4582 if (TwoInputs && (EltIdx >= 16)) {
4583 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4584 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4587 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4588 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
4590 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
4591 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4592 DAG.getNode(ISD::BUILD_VECTOR, dl,
4593 MVT::v16i8, &pshufbMask[0], 16));
4595 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
4597 // Calculate the shuffle mask for the second input, shuffle it, and
4598 // OR it with the first shuffled input.
4600 for (unsigned i = 0; i != 8; ++i) {
4601 int EltIdx = MaskVals[i] * 2;
4603 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4604 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4607 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4608 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
4610 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
4611 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4612 DAG.getNode(ISD::BUILD_VECTOR, dl,
4613 MVT::v16i8, &pshufbMask[0], 16));
4614 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4615 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
4618 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
4619 // and update MaskVals with new element order.
4620 BitVector InOrder(8);
4621 if (BestLoQuad >= 0) {
4622 SmallVector<int, 8> MaskV;
4623 for (int i = 0; i != 4; ++i) {
4624 int idx = MaskVals[i];
4626 MaskV.push_back(-1);
4628 } else if ((idx / 4) == BestLoQuad) {
4629 MaskV.push_back(idx & 3);
4632 MaskV.push_back(-1);
4635 for (unsigned i = 4; i != 8; ++i)
4637 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4640 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
4641 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
4643 X86::getShufflePSHUFLWImmediate(NewV.getNode()),
4647 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
4648 // and update MaskVals with the new element order.
4649 if (BestHiQuad >= 0) {
4650 SmallVector<int, 8> MaskV;
4651 for (unsigned i = 0; i != 4; ++i)
4653 for (unsigned i = 4; i != 8; ++i) {
4654 int idx = MaskVals[i];
4656 MaskV.push_back(-1);
4658 } else if ((idx / 4) == BestHiQuad) {
4659 MaskV.push_back((idx & 3) + 4);
4662 MaskV.push_back(-1);
4665 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4668 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
4669 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
4671 X86::getShufflePSHUFHWImmediate(NewV.getNode()),
4675 // In case BestHi & BestLo were both -1, which means each quadword has a word
4676 // from each of the four input quadwords, calculate the InOrder bitvector now
4677 // before falling through to the insert/extract cleanup.
4678 if (BestLoQuad == -1 && BestHiQuad == -1) {
4680 for (int i = 0; i != 8; ++i)
4681 if (MaskVals[i] < 0 || MaskVals[i] == i)
4685 // The other elements are put in the right place using pextrw and pinsrw.
4686 for (unsigned i = 0; i != 8; ++i) {
4689 int EltIdx = MaskVals[i];
4692 SDValue ExtOp = (EltIdx < 8)
4693 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
4694 DAG.getIntPtrConstant(EltIdx))
4695 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
4696 DAG.getIntPtrConstant(EltIdx - 8));
4697 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
4698 DAG.getIntPtrConstant(i));
4703 // v16i8 shuffles - Prefer shuffles in the following order:
4704 // 1. [ssse3] 1 x pshufb
4705 // 2. [ssse3] 2 x pshufb + 1 x por
4706 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
4708 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
4710 const X86TargetLowering &TLI) {
4711 SDValue V1 = SVOp->getOperand(0);
4712 SDValue V2 = SVOp->getOperand(1);
4713 DebugLoc dl = SVOp->getDebugLoc();
4714 SmallVector<int, 16> MaskVals;
4715 SVOp->getMask(MaskVals);
4717 // If we have SSSE3, case 1 is generated when all result bytes come from
4718 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
4719 // present, fall back to case 3.
4720 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
4723 for (unsigned i = 0; i < 16; ++i) {
4724 int EltIdx = MaskVals[i];
4733 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
4734 if (TLI.getSubtarget()->hasSSSE3()) {
4735 SmallVector<SDValue,16> pshufbMask;
4737 // If all result elements are from one input vector, then only translate
4738 // undef mask values to 0x80 (zero out result) in the pshufb mask.
4740 // Otherwise, we have elements from both input vectors, and must zero out
4741 // elements that come from V2 in the first mask, and V1 in the second mask
4742 // so that we can OR them together.
4743 bool TwoInputs = !(V1Only || V2Only);
4744 for (unsigned i = 0; i != 16; ++i) {
4745 int EltIdx = MaskVals[i];
4746 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
4747 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4750 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4752 // If all the elements are from V2, assign it to V1 and return after
4753 // building the first pshufb.
4756 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4757 DAG.getNode(ISD::BUILD_VECTOR, dl,
4758 MVT::v16i8, &pshufbMask[0], 16));
4762 // Calculate the shuffle mask for the second input, shuffle it, and
4763 // OR it with the first shuffled input.
4765 for (unsigned i = 0; i != 16; ++i) {
4766 int EltIdx = MaskVals[i];
4768 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4771 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4773 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4774 DAG.getNode(ISD::BUILD_VECTOR, dl,
4775 MVT::v16i8, &pshufbMask[0], 16));
4776 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4779 // No SSSE3 - Calculate in place words and then fix all out of place words
4780 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
4781 // the 16 different words that comprise the two doublequadword input vectors.
4782 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
4783 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
4784 SDValue NewV = V2Only ? V2 : V1;
4785 for (int i = 0; i != 8; ++i) {
4786 int Elt0 = MaskVals[i*2];
4787 int Elt1 = MaskVals[i*2+1];
4789 // This word of the result is all undef, skip it.
4790 if (Elt0 < 0 && Elt1 < 0)
4793 // This word of the result is already in the correct place, skip it.
4794 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
4796 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
4799 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
4800 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
4803 // If Elt0 and Elt1 are defined, are consecutive, and can be load
4804 // using a single extract together, load it and store it.
4805 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
4806 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4807 DAG.getIntPtrConstant(Elt1 / 2));
4808 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4809 DAG.getIntPtrConstant(i));
4813 // If Elt1 is defined, extract it from the appropriate source. If the
4814 // source byte is not also odd, shift the extracted word left 8 bits
4815 // otherwise clear the bottom 8 bits if we need to do an or.
4817 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4818 DAG.getIntPtrConstant(Elt1 / 2));
4819 if ((Elt1 & 1) == 0)
4820 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
4821 DAG.getConstant(8, TLI.getShiftAmountTy()));
4823 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
4824 DAG.getConstant(0xFF00, MVT::i16));
4826 // If Elt0 is defined, extract it from the appropriate source. If the
4827 // source byte is not also even, shift the extracted word right 8 bits. If
4828 // Elt1 was also defined, OR the extracted values together before
4829 // inserting them in the result.
4831 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
4832 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
4833 if ((Elt0 & 1) != 0)
4834 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
4835 DAG.getConstant(8, TLI.getShiftAmountTy()));
4837 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
4838 DAG.getConstant(0x00FF, MVT::i16));
4839 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
4842 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4843 DAG.getIntPtrConstant(i));
4845 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
4848 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
4849 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
4850 /// done when every pair / quad of shuffle mask elements point to elements in
4851 /// the right sequence. e.g.
4852 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
4854 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
4855 SelectionDAG &DAG, DebugLoc dl) {
4856 EVT VT = SVOp->getValueType(0);
4857 SDValue V1 = SVOp->getOperand(0);
4858 SDValue V2 = SVOp->getOperand(1);
4859 unsigned NumElems = VT.getVectorNumElements();
4860 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
4862 switch (VT.getSimpleVT().SimpleTy) {
4863 default: assert(false && "Unexpected!");
4864 case MVT::v4f32: NewVT = MVT::v2f64; break;
4865 case MVT::v4i32: NewVT = MVT::v2i64; break;
4866 case MVT::v8i16: NewVT = MVT::v4i32; break;
4867 case MVT::v16i8: NewVT = MVT::v4i32; break;
4870 int Scale = NumElems / NewWidth;
4871 SmallVector<int, 8> MaskVec;
4872 for (unsigned i = 0; i < NumElems; i += Scale) {
4874 for (int j = 0; j < Scale; ++j) {
4875 int EltIdx = SVOp->getMaskElt(i+j);
4879 StartIdx = EltIdx - (EltIdx % Scale);
4880 if (EltIdx != StartIdx + j)
4884 MaskVec.push_back(-1);
4886 MaskVec.push_back(StartIdx / Scale);
4889 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
4890 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
4891 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
4894 /// getVZextMovL - Return a zero-extending vector move low node.
4896 static SDValue getVZextMovL(EVT VT, EVT OpVT,
4897 SDValue SrcOp, SelectionDAG &DAG,
4898 const X86Subtarget *Subtarget, DebugLoc dl) {
4899 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
4900 LoadSDNode *LD = NULL;
4901 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
4902 LD = dyn_cast<LoadSDNode>(SrcOp);
4904 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
4906 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
4907 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
4908 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4909 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
4910 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
4912 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
4913 return DAG.getNode(ISD::BITCAST, dl, VT,
4914 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4915 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4923 return DAG.getNode(ISD::BITCAST, dl, VT,
4924 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4925 DAG.getNode(ISD::BITCAST, dl,
4929 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
4932 LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4933 SDValue V1 = SVOp->getOperand(0);
4934 SDValue V2 = SVOp->getOperand(1);
4935 DebugLoc dl = SVOp->getDebugLoc();
4936 EVT VT = SVOp->getValueType(0);
4938 SmallVector<std::pair<int, int>, 8> Locs;
4940 SmallVector<int, 8> Mask1(4U, -1);
4941 SmallVector<int, 8> PermMask;
4942 SVOp->getMask(PermMask);
4946 for (unsigned i = 0; i != 4; ++i) {
4947 int Idx = PermMask[i];
4949 Locs[i] = std::make_pair(-1, -1);
4951 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
4953 Locs[i] = std::make_pair(0, NumLo);
4957 Locs[i] = std::make_pair(1, NumHi);
4959 Mask1[2+NumHi] = Idx;
4965 if (NumLo <= 2 && NumHi <= 2) {
4966 // If no more than two elements come from either vector. This can be
4967 // implemented with two shuffles. First shuffle gather the elements.
4968 // The second shuffle, which takes the first shuffle as both of its
4969 // vector operands, put the elements into the right order.
4970 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4972 SmallVector<int, 8> Mask2(4U, -1);
4974 for (unsigned i = 0; i != 4; ++i) {
4975 if (Locs[i].first == -1)
4978 unsigned Idx = (i < 2) ? 0 : 4;
4979 Idx += Locs[i].first * 2 + Locs[i].second;
4984 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
4985 } else if (NumLo == 3 || NumHi == 3) {
4986 // Otherwise, we must have three elements from one vector, call it X, and
4987 // one element from the other, call it Y. First, use a shufps to build an
4988 // intermediate vector with the one element from Y and the element from X
4989 // that will be in the same half in the final destination (the indexes don't
4990 // matter). Then, use a shufps to build the final vector, taking the half
4991 // containing the element from Y from the intermediate, and the other half
4994 // Normalize it so the 3 elements come from V1.
4995 CommuteVectorShuffleMask(PermMask, VT);
4999 // Find the element from V2.
5001 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
5002 int Val = PermMask[HiIndex];
5009 Mask1[0] = PermMask[HiIndex];
5011 Mask1[2] = PermMask[HiIndex^1];
5013 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5016 Mask1[0] = PermMask[0];
5017 Mask1[1] = PermMask[1];
5018 Mask1[2] = HiIndex & 1 ? 6 : 4;
5019 Mask1[3] = HiIndex & 1 ? 4 : 6;
5020 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5022 Mask1[0] = HiIndex & 1 ? 2 : 0;
5023 Mask1[1] = HiIndex & 1 ? 0 : 2;
5024 Mask1[2] = PermMask[2];
5025 Mask1[3] = PermMask[3];
5030 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
5034 // Break it into (shuffle shuffle_hi, shuffle_lo).
5036 SmallVector<int,8> LoMask(4U, -1);
5037 SmallVector<int,8> HiMask(4U, -1);
5039 SmallVector<int,8> *MaskPtr = &LoMask;
5040 unsigned MaskIdx = 0;
5043 for (unsigned i = 0; i != 4; ++i) {
5050 int Idx = PermMask[i];
5052 Locs[i] = std::make_pair(-1, -1);
5053 } else if (Idx < 4) {
5054 Locs[i] = std::make_pair(MaskIdx, LoIdx);
5055 (*MaskPtr)[LoIdx] = Idx;
5058 Locs[i] = std::make_pair(MaskIdx, HiIdx);
5059 (*MaskPtr)[HiIdx] = Idx;
5064 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
5065 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
5066 SmallVector<int, 8> MaskOps;
5067 for (unsigned i = 0; i != 4; ++i) {
5068 if (Locs[i].first == -1) {
5069 MaskOps.push_back(-1);
5071 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
5072 MaskOps.push_back(Idx);
5075 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
5078 static bool MayFoldVectorLoad(SDValue V) {
5079 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
5080 V = V.getOperand(0);
5081 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5082 V = V.getOperand(0);
5088 // FIXME: the version above should always be used. Since there's
5089 // a bug where several vector shuffles can't be folded because the
5090 // DAG is not updated during lowering and a node claims to have two
5091 // uses while it only has one, use this version, and let isel match
5092 // another instruction if the load really happens to have more than
5093 // one use. Remove this version after this bug get fixed.
5094 // rdar://8434668, PR8156
5095 static bool RelaxedMayFoldVectorLoad(SDValue V) {
5096 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
5097 V = V.getOperand(0);
5098 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5099 V = V.getOperand(0);
5100 if (ISD::isNormalLoad(V.getNode()))
5105 /// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by
5106 /// a vector extract, and if both can be later optimized into a single load.
5107 /// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked
5108 /// here because otherwise a target specific shuffle node is going to be
5109 /// emitted for this shuffle, and the optimization not done.
5110 /// FIXME: This is probably not the best approach, but fix the problem
5111 /// until the right path is decided.
5113 bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
5114 const TargetLowering &TLI) {
5115 EVT VT = V.getValueType();
5116 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V);
5118 // Be sure that the vector shuffle is present in a pattern like this:
5119 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr)
5123 SDNode *N = *V.getNode()->use_begin();
5124 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5127 SDValue EltNo = N->getOperand(1);
5128 if (!isa<ConstantSDNode>(EltNo))
5131 // If the bit convert changed the number of elements, it is unsafe
5132 // to examine the mask.
5133 bool HasShuffleIntoBitcast = false;
5134 if (V.getOpcode() == ISD::BITCAST) {
5135 EVT SrcVT = V.getOperand(0).getValueType();
5136 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
5138 V = V.getOperand(0);
5139 HasShuffleIntoBitcast = true;
5142 // Select the input vector, guarding against out of range extract vector.
5143 unsigned NumElems = VT.getVectorNumElements();
5144 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5145 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
5146 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
5148 // Skip one more bit_convert if necessary
5149 if (V.getOpcode() == ISD::BITCAST)
5150 V = V.getOperand(0);
5152 if (ISD::isNormalLoad(V.getNode())) {
5153 // Is the original load suitable?
5154 LoadSDNode *LN0 = cast<LoadSDNode>(V);
5156 // FIXME: avoid the multi-use bug that is preventing lots of
5157 // of foldings to be detected, this is still wrong of course, but
5158 // give the temporary desired behavior, and if it happens that
5159 // the load has real more uses, during isel it will not fold, and
5160 // will generate poor code.
5161 if (!LN0 || LN0->isVolatile()) // || !LN0->hasOneUse()
5164 if (!HasShuffleIntoBitcast)
5167 // If there's a bitcast before the shuffle, check if the load type and
5168 // alignment is valid.
5169 unsigned Align = LN0->getAlignment();
5171 TLI.getTargetData()->getABITypeAlignment(
5172 VT.getTypeForEVT(*DAG.getContext()));
5174 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
5182 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
5183 EVT VT = Op.getValueType();
5185 // Canonizalize to v2f64.
5186 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
5187 return DAG.getNode(ISD::BITCAST, dl, VT,
5188 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
5193 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
5195 SDValue V1 = Op.getOperand(0);
5196 SDValue V2 = Op.getOperand(1);
5197 EVT VT = Op.getValueType();
5199 assert(VT != MVT::v2i64 && "unsupported shuffle type");
5201 if (HasSSE2 && VT == MVT::v2f64)
5202 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
5205 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V2, DAG);
5209 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
5210 SDValue V1 = Op.getOperand(0);
5211 SDValue V2 = Op.getOperand(1);
5212 EVT VT = Op.getValueType();
5214 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
5215 "unsupported shuffle type");
5217 if (V2.getOpcode() == ISD::UNDEF)
5221 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
5225 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
5226 SDValue V1 = Op.getOperand(0);
5227 SDValue V2 = Op.getOperand(1);
5228 EVT VT = Op.getValueType();
5229 unsigned NumElems = VT.getVectorNumElements();
5231 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
5232 // operand of these instructions is only memory, so check if there's a
5233 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
5235 bool CanFoldLoad = false;
5237 // Trivial case, when V2 comes from a load.
5238 if (MayFoldVectorLoad(V2))
5241 // When V1 is a load, it can be folded later into a store in isel, example:
5242 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
5244 // (MOVLPSmr addr:$src1, VR128:$src2)
5245 // So, recognize this potential and also use MOVLPS or MOVLPD
5246 if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
5250 if (HasSSE2 && NumElems == 2)
5251 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
5254 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
5257 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5258 // movl and movlp will both match v2i64, but v2i64 is never matched by
5259 // movl earlier because we make it strict to avoid messing with the movlp load
5260 // folding logic (see the code above getMOVLP call). Match it here then,
5261 // this is horrible, but will stay like this until we move all shuffle
5262 // matching to x86 specific nodes. Note that for the 1st condition all
5263 // types are matched with movsd.
5264 if ((HasSSE2 && NumElems == 2) || !X86::isMOVLMask(SVOp))
5265 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
5267 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
5270 assert(VT != MVT::v4i32 && "unsupported shuffle type");
5272 // Invert the operand order and use SHUFPS to match it.
5273 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V2, V1,
5274 X86::getShuffleSHUFImmediate(SVOp), DAG);
5277 static inline unsigned getUNPCKLOpcode(EVT VT) {
5278 switch(VT.getSimpleVT().SimpleTy) {
5279 case MVT::v4i32: return X86ISD::PUNPCKLDQ;
5280 case MVT::v2i64: return X86ISD::PUNPCKLQDQ;
5281 case MVT::v4f32: return X86ISD::UNPCKLPS;
5282 case MVT::v2f64: return X86ISD::UNPCKLPD;
5283 case MVT::v16i8: return X86ISD::PUNPCKLBW;
5284 case MVT::v8i16: return X86ISD::PUNPCKLWD;
5286 llvm_unreachable("Unknow type for unpckl");
5291 static inline unsigned getUNPCKHOpcode(EVT VT) {
5292 switch(VT.getSimpleVT().SimpleTy) {
5293 case MVT::v4i32: return X86ISD::PUNPCKHDQ;
5294 case MVT::v2i64: return X86ISD::PUNPCKHQDQ;
5295 case MVT::v4f32: return X86ISD::UNPCKHPS;
5296 case MVT::v2f64: return X86ISD::UNPCKHPD;
5297 case MVT::v16i8: return X86ISD::PUNPCKHBW;
5298 case MVT::v8i16: return X86ISD::PUNPCKHWD;
5300 llvm_unreachable("Unknow type for unpckh");
5306 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
5307 const TargetLowering &TLI,
5308 const X86Subtarget *Subtarget) {
5309 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5310 EVT VT = Op.getValueType();
5311 DebugLoc dl = Op.getDebugLoc();
5312 SDValue V1 = Op.getOperand(0);
5313 SDValue V2 = Op.getOperand(1);
5315 if (isZeroShuffle(SVOp))
5316 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
5318 // Handle splat operations
5319 if (SVOp->isSplat()) {
5320 // Special case, this is the only place now where it's
5321 // allowed to return a vector_shuffle operation without
5322 // using a target specific node, because *hopefully* it
5323 // will be optimized away by the dag combiner.
5324 if (VT.getVectorNumElements() <= 4 &&
5325 CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
5328 // Handle splats by matching through known masks
5329 if (VT.getVectorNumElements() <= 4)
5332 // Canonicalize all of the remaining to v4f32.
5333 return PromoteSplat(SVOp, DAG);
5336 // If the shuffle can be profitably rewritten as a narrower shuffle, then
5338 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
5339 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
5340 if (NewOp.getNode())
5341 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
5342 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
5343 // FIXME: Figure out a cleaner way to do this.
5344 // Try to make use of movq to zero out the top part.
5345 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
5346 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
5347 if (NewOp.getNode()) {
5348 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
5349 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
5350 DAG, Subtarget, dl);
5352 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
5353 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
5354 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
5355 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
5356 DAG, Subtarget, dl);
5363 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
5364 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5365 SDValue V1 = Op.getOperand(0);
5366 SDValue V2 = Op.getOperand(1);
5367 EVT VT = Op.getValueType();
5368 DebugLoc dl = Op.getDebugLoc();
5369 unsigned NumElems = VT.getVectorNumElements();
5370 bool isMMX = VT.getSizeInBits() == 64;
5371 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
5372 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
5373 bool V1IsSplat = false;
5374 bool V2IsSplat = false;
5375 bool HasSSE2 = Subtarget->hasSSE2() || Subtarget->hasAVX();
5376 bool HasSSE3 = Subtarget->hasSSE3() || Subtarget->hasAVX();
5377 bool HasSSSE3 = Subtarget->hasSSSE3() || Subtarget->hasAVX();
5378 MachineFunction &MF = DAG.getMachineFunction();
5379 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
5381 // Shuffle operations on MMX not supported.
5385 // Vector shuffle lowering takes 3 steps:
5387 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
5388 // narrowing and commutation of operands should be handled.
5389 // 2) Matching of shuffles with known shuffle masks to x86 target specific
5391 // 3) Rewriting of unmatched masks into new generic shuffle operations,
5392 // so the shuffle can be broken into other shuffles and the legalizer can
5393 // try the lowering again.
5395 // The general ideia is that no vector_shuffle operation should be left to
5396 // be matched during isel, all of them must be converted to a target specific
5399 // Normalize the input vectors. Here splats, zeroed vectors, profitable
5400 // narrowing and commutation of operands should be handled. The actual code
5401 // doesn't include all of those, work in progress...
5402 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
5403 if (NewOp.getNode())
5406 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
5407 // unpckh_undef). Only use pshufd if speed is more important than size.
5408 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp))
5409 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5410 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
5411 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp))
5412 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5413 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
5415 if (X86::isMOVDDUPMask(SVOp) && HasSSE3 && V2IsUndef &&
5416 RelaxedMayFoldVectorLoad(V1))
5417 return getMOVDDup(Op, dl, V1, DAG);
5419 if (X86::isMOVHLPS_v_undef_Mask(SVOp))
5420 return getMOVHighToLow(Op, dl, DAG);
5422 // Use to match splats
5423 if (HasSSE2 && X86::isUNPCKHMask(SVOp) && V2IsUndef &&
5424 (VT == MVT::v2f64 || VT == MVT::v2i64))
5425 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
5427 if (X86::isPSHUFDMask(SVOp)) {
5428 // The actual implementation will match the mask in the if above and then
5429 // during isel it can match several different instructions, not only pshufd
5430 // as its name says, sad but true, emulate the behavior for now...
5431 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
5432 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
5434 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
5436 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
5437 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
5439 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
5440 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V1,
5443 if (VT == MVT::v4f32)
5444 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V1,
5448 // Check if this can be converted into a logical shift.
5449 bool isLeft = false;
5452 bool isShift = getSubtarget()->hasSSE2() &&
5453 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
5454 if (isShift && ShVal.hasOneUse()) {
5455 // If the shifted value has multiple uses, it may be cheaper to use
5456 // v_set0 + movlhps or movhlps, etc.
5457 EVT EltVT = VT.getVectorElementType();
5458 ShAmt *= EltVT.getSizeInBits();
5459 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
5462 if (X86::isMOVLMask(SVOp)) {
5465 if (ISD::isBuildVectorAllZeros(V1.getNode()))
5466 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
5467 if (!X86::isMOVLPMask(SVOp)) {
5468 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
5469 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
5471 if (VT == MVT::v4i32 || VT == MVT::v4f32)
5472 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
5476 // FIXME: fold these into legal mask.
5477 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp))
5478 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
5480 if (X86::isMOVHLPSMask(SVOp))
5481 return getMOVHighToLow(Op, dl, DAG);
5483 if (X86::isMOVSHDUPMask(SVOp) && HasSSE3 && V2IsUndef && NumElems == 4)
5484 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
5486 if (X86::isMOVSLDUPMask(SVOp) && HasSSE3 && V2IsUndef && NumElems == 4)
5487 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
5489 if (X86::isMOVLPMask(SVOp))
5490 return getMOVLP(Op, dl, DAG, HasSSE2);
5492 if (ShouldXformToMOVHLPS(SVOp) ||
5493 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
5494 return CommuteVectorShuffle(SVOp, DAG);
5497 // No better options. Use a vshl / vsrl.
5498 EVT EltVT = VT.getVectorElementType();
5499 ShAmt *= EltVT.getSizeInBits();
5500 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
5503 bool Commuted = false;
5504 // FIXME: This should also accept a bitcast of a splat? Be careful, not
5505 // 1,1,1,1 -> v8i16 though.
5506 V1IsSplat = isSplatVector(V1.getNode());
5507 V2IsSplat = isSplatVector(V2.getNode());
5509 // Canonicalize the splat or undef, if present, to be on the RHS.
5510 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
5511 Op = CommuteVectorShuffle(SVOp, DAG);
5512 SVOp = cast<ShuffleVectorSDNode>(Op);
5513 V1 = SVOp->getOperand(0);
5514 V2 = SVOp->getOperand(1);
5515 std::swap(V1IsSplat, V2IsSplat);
5516 std::swap(V1IsUndef, V2IsUndef);
5520 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
5521 // Shuffling low element of v1 into undef, just return v1.
5524 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
5525 // the instruction selector will not match, so get a canonical MOVL with
5526 // swapped operands to undo the commute.
5527 return getMOVL(DAG, dl, VT, V2, V1);
5530 if (X86::isUNPCKLMask(SVOp))
5531 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG);
5533 if (X86::isUNPCKHMask(SVOp))
5534 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V2, DAG);
5537 // Normalize mask so all entries that point to V2 points to its first
5538 // element then try to match unpck{h|l} again. If match, return a
5539 // new vector_shuffle with the corrected mask.
5540 SDValue NewMask = NormalizeMask(SVOp, DAG);
5541 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
5542 if (NSVOp != SVOp) {
5543 if (X86::isUNPCKLMask(NSVOp, true)) {
5545 } else if (X86::isUNPCKHMask(NSVOp, true)) {
5552 // Commute is back and try unpck* again.
5553 // FIXME: this seems wrong.
5554 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
5555 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
5557 if (X86::isUNPCKLMask(NewSVOp))
5558 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG);
5560 if (X86::isUNPCKHMask(NewSVOp))
5561 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V2, V1, DAG);
5564 // Normalize the node to match x86 shuffle ops if needed
5565 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
5566 return CommuteVectorShuffle(SVOp, DAG);
5568 // The checks below are all present in isShuffleMaskLegal, but they are
5569 // inlined here right now to enable us to directly emit target specific
5570 // nodes, and remove one by one until they don't return Op anymore.
5571 SmallVector<int, 16> M;
5574 if (isPALIGNRMask(M, VT, HasSSSE3))
5575 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
5576 X86::getShufflePALIGNRImmediate(SVOp),
5579 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
5580 SVOp->getSplatIndex() == 0 && V2IsUndef) {
5581 if (VT == MVT::v2f64)
5582 return getTargetShuffleNode(X86ISD::UNPCKLPD, dl, VT, V1, V1, DAG);
5583 if (VT == MVT::v2i64)
5584 return getTargetShuffleNode(X86ISD::PUNPCKLQDQ, dl, VT, V1, V1, DAG);
5587 if (isPSHUFHWMask(M, VT))
5588 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
5589 X86::getShufflePSHUFHWImmediate(SVOp),
5592 if (isPSHUFLWMask(M, VT))
5593 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
5594 X86::getShufflePSHUFLWImmediate(SVOp),
5597 if (isSHUFPMask(M, VT)) {
5598 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
5599 if (VT == MVT::v4f32 || VT == MVT::v4i32)
5600 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V2,
5602 if (VT == MVT::v2f64 || VT == MVT::v2i64)
5603 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V2,
5607 if (X86::isUNPCKL_v_undef_Mask(SVOp))
5608 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5609 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
5610 if (X86::isUNPCKH_v_undef_Mask(SVOp))
5611 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5612 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
5614 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
5615 if (VT == MVT::v8i16) {
5616 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
5617 if (NewOp.getNode())
5621 if (VT == MVT::v16i8) {
5622 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
5623 if (NewOp.getNode())
5627 // Handle all 4 wide cases with a number of shuffles.
5629 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
5635 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
5636 SelectionDAG &DAG) const {
5637 EVT VT = Op.getValueType();
5638 DebugLoc dl = Op.getDebugLoc();
5639 if (VT.getSizeInBits() == 8) {
5640 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
5641 Op.getOperand(0), Op.getOperand(1));
5642 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
5643 DAG.getValueType(VT));
5644 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
5645 } else if (VT.getSizeInBits() == 16) {
5646 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5647 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
5649 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
5650 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
5651 DAG.getNode(ISD::BITCAST, dl,
5655 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
5656 Op.getOperand(0), Op.getOperand(1));
5657 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
5658 DAG.getValueType(VT));
5659 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
5660 } else if (VT == MVT::f32) {
5661 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
5662 // the result back to FR32 register. It's only worth matching if the
5663 // result has a single use which is a store or a bitcast to i32. And in
5664 // the case of a store, it's not worth it if the index is a constant 0,
5665 // because a MOVSSmr can be used instead, which is smaller and faster.
5666 if (!Op.hasOneUse())
5668 SDNode *User = *Op.getNode()->use_begin();
5669 if ((User->getOpcode() != ISD::STORE ||
5670 (isa<ConstantSDNode>(Op.getOperand(1)) &&
5671 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
5672 (User->getOpcode() != ISD::BITCAST ||
5673 User->getValueType(0) != MVT::i32))
5675 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
5676 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
5679 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
5680 } else if (VT == MVT::i32) {
5681 // ExtractPS works with constant index.
5682 if (isa<ConstantSDNode>(Op.getOperand(1)))
5690 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
5691 SelectionDAG &DAG) const {
5692 if (!isa<ConstantSDNode>(Op.getOperand(1)))
5695 if (Subtarget->hasSSE41()) {
5696 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
5701 EVT VT = Op.getValueType();
5702 DebugLoc dl = Op.getDebugLoc();
5703 // TODO: handle v16i8.
5704 if (VT.getSizeInBits() == 16) {
5705 SDValue Vec = Op.getOperand(0);
5706 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5708 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
5709 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
5710 DAG.getNode(ISD::BITCAST, dl,
5713 // Transform it so it match pextrw which produces a 32-bit result.
5714 EVT EltVT = MVT::i32;
5715 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
5716 Op.getOperand(0), Op.getOperand(1));
5717 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
5718 DAG.getValueType(VT));
5719 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
5720 } else if (VT.getSizeInBits() == 32) {
5721 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5725 // SHUFPS the element to the lowest double word, then movss.
5726 int Mask[4] = { Idx, -1, -1, -1 };
5727 EVT VVT = Op.getOperand(0).getValueType();
5728 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
5729 DAG.getUNDEF(VVT), Mask);
5730 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
5731 DAG.getIntPtrConstant(0));
5732 } else if (VT.getSizeInBits() == 64) {
5733 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
5734 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
5735 // to match extract_elt for f64.
5736 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5740 // UNPCKHPD the element to the lowest double word, then movsd.
5741 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
5742 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
5743 int Mask[2] = { 1, -1 };
5744 EVT VVT = Op.getOperand(0).getValueType();
5745 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
5746 DAG.getUNDEF(VVT), Mask);
5747 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
5748 DAG.getIntPtrConstant(0));
5755 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
5756 SelectionDAG &DAG) const {
5757 EVT VT = Op.getValueType();
5758 EVT EltVT = VT.getVectorElementType();
5759 DebugLoc dl = Op.getDebugLoc();
5761 SDValue N0 = Op.getOperand(0);
5762 SDValue N1 = Op.getOperand(1);
5763 SDValue N2 = Op.getOperand(2);
5765 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
5766 isa<ConstantSDNode>(N2)) {
5768 if (VT == MVT::v8i16)
5769 Opc = X86ISD::PINSRW;
5770 else if (VT == MVT::v16i8)
5771 Opc = X86ISD::PINSRB;
5773 Opc = X86ISD::PINSRB;
5775 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
5777 if (N1.getValueType() != MVT::i32)
5778 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
5779 if (N2.getValueType() != MVT::i32)
5780 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
5781 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
5782 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
5783 // Bits [7:6] of the constant are the source select. This will always be
5784 // zero here. The DAG Combiner may combine an extract_elt index into these
5785 // bits. For example (insert (extract, 3), 2) could be matched by putting
5786 // the '3' into bits [7:6] of X86ISD::INSERTPS.
5787 // Bits [5:4] of the constant are the destination select. This is the
5788 // value of the incoming immediate.
5789 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
5790 // combine either bitwise AND or insert of float 0.0 to set these bits.
5791 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
5792 // Create this as a scalar to vector..
5793 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
5794 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
5795 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
5796 // PINSR* works with constant index.
5803 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
5804 EVT VT = Op.getValueType();
5805 EVT EltVT = VT.getVectorElementType();
5807 if (Subtarget->hasSSE41())
5808 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
5810 if (EltVT == MVT::i8)
5813 DebugLoc dl = Op.getDebugLoc();
5814 SDValue N0 = Op.getOperand(0);
5815 SDValue N1 = Op.getOperand(1);
5816 SDValue N2 = Op.getOperand(2);
5818 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
5819 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
5820 // as its second argument.
5821 if (N1.getValueType() != MVT::i32)
5822 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
5823 if (N2.getValueType() != MVT::i32)
5824 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
5825 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
5831 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5832 DebugLoc dl = Op.getDebugLoc();
5834 if (Op.getValueType() == MVT::v1i64 &&
5835 Op.getOperand(0).getValueType() == MVT::i64)
5836 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
5838 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
5839 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
5840 "Expected an SSE type!");
5841 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
5842 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
5845 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
5846 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
5847 // one of the above mentioned nodes. It has to be wrapped because otherwise
5848 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
5849 // be used to form addressing mode. These wrapped nodes will be selected
5852 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
5853 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
5855 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5857 unsigned char OpFlag = 0;
5858 unsigned WrapperKind = X86ISD::Wrapper;
5859 CodeModel::Model M = getTargetMachine().getCodeModel();
5861 if (Subtarget->isPICStyleRIPRel() &&
5862 (M == CodeModel::Small || M == CodeModel::Kernel))
5863 WrapperKind = X86ISD::WrapperRIP;
5864 else if (Subtarget->isPICStyleGOT())
5865 OpFlag = X86II::MO_GOTOFF;
5866 else if (Subtarget->isPICStyleStubPIC())
5867 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5869 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
5871 CP->getOffset(), OpFlag);
5872 DebugLoc DL = CP->getDebugLoc();
5873 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5874 // With PIC, the address is actually $g + Offset.
5876 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5877 DAG.getNode(X86ISD::GlobalBaseReg,
5878 DebugLoc(), getPointerTy()),
5885 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
5886 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
5888 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5890 unsigned char OpFlag = 0;
5891 unsigned WrapperKind = X86ISD::Wrapper;
5892 CodeModel::Model M = getTargetMachine().getCodeModel();
5894 if (Subtarget->isPICStyleRIPRel() &&
5895 (M == CodeModel::Small || M == CodeModel::Kernel))
5896 WrapperKind = X86ISD::WrapperRIP;
5897 else if (Subtarget->isPICStyleGOT())
5898 OpFlag = X86II::MO_GOTOFF;
5899 else if (Subtarget->isPICStyleStubPIC())
5900 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5902 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
5904 DebugLoc DL = JT->getDebugLoc();
5905 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5907 // With PIC, the address is actually $g + Offset.
5909 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5910 DAG.getNode(X86ISD::GlobalBaseReg,
5911 DebugLoc(), getPointerTy()),
5918 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
5919 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
5921 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5923 unsigned char OpFlag = 0;
5924 unsigned WrapperKind = X86ISD::Wrapper;
5925 CodeModel::Model M = getTargetMachine().getCodeModel();
5927 if (Subtarget->isPICStyleRIPRel() &&
5928 (M == CodeModel::Small || M == CodeModel::Kernel))
5929 WrapperKind = X86ISD::WrapperRIP;
5930 else if (Subtarget->isPICStyleGOT())
5931 OpFlag = X86II::MO_GOTOFF;
5932 else if (Subtarget->isPICStyleStubPIC())
5933 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5935 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
5937 DebugLoc DL = Op.getDebugLoc();
5938 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5941 // With PIC, the address is actually $g + Offset.
5942 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
5943 !Subtarget->is64Bit()) {
5944 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5945 DAG.getNode(X86ISD::GlobalBaseReg,
5946 DebugLoc(), getPointerTy()),
5954 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
5955 // Create the TargetBlockAddressAddress node.
5956 unsigned char OpFlags =
5957 Subtarget->ClassifyBlockAddressReference();
5958 CodeModel::Model M = getTargetMachine().getCodeModel();
5959 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
5960 DebugLoc dl = Op.getDebugLoc();
5961 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
5962 /*isTarget=*/true, OpFlags);
5964 if (Subtarget->isPICStyleRIPRel() &&
5965 (M == CodeModel::Small || M == CodeModel::Kernel))
5966 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5968 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5970 // With PIC, the address is actually $g + Offset.
5971 if (isGlobalRelativeToPICBase(OpFlags)) {
5972 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5973 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5981 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
5983 SelectionDAG &DAG) const {
5984 // Create the TargetGlobalAddress node, folding in the constant
5985 // offset if it is legal.
5986 unsigned char OpFlags =
5987 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
5988 CodeModel::Model M = getTargetMachine().getCodeModel();
5990 if (OpFlags == X86II::MO_NO_FLAG &&
5991 X86::isOffsetSuitableForCodeModel(Offset, M)) {
5992 // A direct static reference to a global.
5993 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
5996 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
5999 if (Subtarget->isPICStyleRIPRel() &&
6000 (M == CodeModel::Small || M == CodeModel::Kernel))
6001 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
6003 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
6005 // With PIC, the address is actually $g + Offset.
6006 if (isGlobalRelativeToPICBase(OpFlags)) {
6007 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6008 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
6012 // For globals that require a load from a stub to get the address, emit the
6014 if (isGlobalStubReference(OpFlags))
6015 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
6016 MachinePointerInfo::getGOT(), false, false, 0);
6018 // If there was a non-zero offset that we didn't fold, create an explicit
6021 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
6022 DAG.getConstant(Offset, getPointerTy()));
6028 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
6029 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
6030 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
6031 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
6035 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
6036 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
6037 unsigned char OperandFlags) {
6038 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6039 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6040 DebugLoc dl = GA->getDebugLoc();
6041 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
6042 GA->getValueType(0),
6046 SDValue Ops[] = { Chain, TGA, *InFlag };
6047 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
6049 SDValue Ops[] = { Chain, TGA };
6050 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
6053 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
6054 MFI->setAdjustsStack(true);
6056 SDValue Flag = Chain.getValue(1);
6057 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
6060 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
6062 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
6065 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
6066 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
6067 DAG.getNode(X86ISD::GlobalBaseReg,
6068 DebugLoc(), PtrVT), InFlag);
6069 InFlag = Chain.getValue(1);
6071 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
6074 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
6076 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
6078 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
6079 X86::RAX, X86II::MO_TLSGD);
6082 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
6083 // "local exec" model.
6084 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
6085 const EVT PtrVT, TLSModel::Model model,
6087 DebugLoc dl = GA->getDebugLoc();
6089 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
6090 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
6091 is64Bit ? 257 : 256));
6093 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
6094 DAG.getIntPtrConstant(0),
6095 MachinePointerInfo(Ptr), false, false, 0);
6097 unsigned char OperandFlags = 0;
6098 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
6100 unsigned WrapperKind = X86ISD::Wrapper;
6101 if (model == TLSModel::LocalExec) {
6102 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
6103 } else if (is64Bit) {
6104 assert(model == TLSModel::InitialExec);
6105 OperandFlags = X86II::MO_GOTTPOFF;
6106 WrapperKind = X86ISD::WrapperRIP;
6108 assert(model == TLSModel::InitialExec);
6109 OperandFlags = X86II::MO_INDNTPOFF;
6112 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
6114 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
6115 GA->getValueType(0),
6116 GA->getOffset(), OperandFlags);
6117 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
6119 if (model == TLSModel::InitialExec)
6120 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
6121 MachinePointerInfo::getGOT(), false, false, 0);
6123 // The address of the thread local variable is the add of the thread
6124 // pointer with the offset of the variable.
6125 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
6129 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
6131 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
6132 const GlobalValue *GV = GA->getGlobal();
6134 if (Subtarget->isTargetELF()) {
6135 // TODO: implement the "local dynamic" model
6136 // TODO: implement the "initial exec"model for pic executables
6138 // If GV is an alias then use the aliasee for determining
6139 // thread-localness.
6140 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
6141 GV = GA->resolveAliasedGlobal(false);
6143 TLSModel::Model model
6144 = getTLSModel(GV, getTargetMachine().getRelocationModel());
6147 case TLSModel::GeneralDynamic:
6148 case TLSModel::LocalDynamic: // not implemented
6149 if (Subtarget->is64Bit())
6150 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
6151 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
6153 case TLSModel::InitialExec:
6154 case TLSModel::LocalExec:
6155 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
6156 Subtarget->is64Bit());
6158 } else if (Subtarget->isTargetDarwin()) {
6159 // Darwin only has one model of TLS. Lower to that.
6160 unsigned char OpFlag = 0;
6161 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
6162 X86ISD::WrapperRIP : X86ISD::Wrapper;
6164 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6166 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
6167 !Subtarget->is64Bit();
6169 OpFlag = X86II::MO_TLVP_PIC_BASE;
6171 OpFlag = X86II::MO_TLVP;
6172 DebugLoc DL = Op.getDebugLoc();
6173 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
6174 GA->getValueType(0),
6175 GA->getOffset(), OpFlag);
6176 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6178 // With PIC32, the address is actually $g + Offset.
6180 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
6181 DAG.getNode(X86ISD::GlobalBaseReg,
6182 DebugLoc(), getPointerTy()),
6185 // Lowering the machine isd will make sure everything is in the right
6187 SDValue Chain = DAG.getEntryNode();
6188 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6189 SDValue Args[] = { Chain, Offset };
6190 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
6192 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
6193 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6194 MFI->setAdjustsStack(true);
6196 // And our return value (tls address) is in the standard call return value
6198 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
6199 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
6203 "TLS not implemented for this target.");
6205 llvm_unreachable("Unreachable");
6210 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
6211 /// take a 2 x i32 value to shift plus a shift amount.
6212 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
6213 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
6214 EVT VT = Op.getValueType();
6215 unsigned VTBits = VT.getSizeInBits();
6216 DebugLoc dl = Op.getDebugLoc();
6217 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
6218 SDValue ShOpLo = Op.getOperand(0);
6219 SDValue ShOpHi = Op.getOperand(1);
6220 SDValue ShAmt = Op.getOperand(2);
6221 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
6222 DAG.getConstant(VTBits - 1, MVT::i8))
6223 : DAG.getConstant(0, VT);
6226 if (Op.getOpcode() == ISD::SHL_PARTS) {
6227 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
6228 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
6230 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
6231 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
6234 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
6235 DAG.getConstant(VTBits, MVT::i8));
6236 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
6237 AndNode, DAG.getConstant(0, MVT::i8));
6240 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6241 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
6242 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
6244 if (Op.getOpcode() == ISD::SHL_PARTS) {
6245 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
6246 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
6248 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
6249 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
6252 SDValue Ops[2] = { Lo, Hi };
6253 return DAG.getMergeValues(Ops, 2, dl);
6256 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
6257 SelectionDAG &DAG) const {
6258 EVT SrcVT = Op.getOperand(0).getValueType();
6260 if (SrcVT.isVector())
6263 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
6264 "Unknown SINT_TO_FP to lower!");
6266 // These are really Legal; return the operand so the caller accepts it as
6268 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
6270 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
6271 Subtarget->is64Bit()) {
6275 DebugLoc dl = Op.getDebugLoc();
6276 unsigned Size = SrcVT.getSizeInBits()/8;
6277 MachineFunction &MF = DAG.getMachineFunction();
6278 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
6279 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6280 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
6282 MachinePointerInfo::getFixedStack(SSFI),
6284 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
6287 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
6289 SelectionDAG &DAG) const {
6291 DebugLoc DL = Op.getDebugLoc();
6293 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
6295 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
6297 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
6299 unsigned ByteSize = SrcVT.getSizeInBits()/8;
6301 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
6302 MachineMemOperand *MMO =
6303 DAG.getMachineFunction()
6304 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6305 MachineMemOperand::MOLoad, ByteSize, ByteSize);
6307 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
6308 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
6310 Tys, Ops, array_lengthof(Ops),
6314 Chain = Result.getValue(1);
6315 SDValue InFlag = Result.getValue(2);
6317 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
6318 // shouldn't be necessary except that RFP cannot be live across
6319 // multiple blocks. When stackifier is fixed, they can be uncoupled.
6320 MachineFunction &MF = DAG.getMachineFunction();
6321 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
6322 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
6323 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6324 Tys = DAG.getVTList(MVT::Other);
6326 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
6328 MachineMemOperand *MMO =
6329 DAG.getMachineFunction()
6330 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6331 MachineMemOperand::MOStore, SSFISize, SSFISize);
6333 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
6334 Ops, array_lengthof(Ops),
6335 Op.getValueType(), MMO);
6336 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
6337 MachinePointerInfo::getFixedStack(SSFI),
6344 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
6345 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
6346 SelectionDAG &DAG) const {
6347 // This algorithm is not obvious. Here it is in C code, more or less:
6349 double uint64_to_double( uint32_t hi, uint32_t lo ) {
6350 static const __m128i exp = { 0x4330000045300000ULL, 0 };
6351 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
6353 // Copy ints to xmm registers.
6354 __m128i xh = _mm_cvtsi32_si128( hi );
6355 __m128i xl = _mm_cvtsi32_si128( lo );
6357 // Combine into low half of a single xmm register.
6358 __m128i x = _mm_unpacklo_epi32( xh, xl );
6362 // Merge in appropriate exponents to give the integer bits the right
6364 x = _mm_unpacklo_epi32( x, exp );
6366 // Subtract away the biases to deal with the IEEE-754 double precision
6368 d = _mm_sub_pd( (__m128d) x, bias );
6370 // All conversions up to here are exact. The correctly rounded result is
6371 // calculated using the current rounding mode using the following
6373 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
6374 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
6375 // store doesn't really need to be here (except
6376 // maybe to zero the other double)
6381 DebugLoc dl = Op.getDebugLoc();
6382 LLVMContext *Context = DAG.getContext();
6384 // Build some magic constants.
6385 std::vector<Constant*> CV0;
6386 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
6387 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
6388 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
6389 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
6390 Constant *C0 = ConstantVector::get(CV0);
6391 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
6393 std::vector<Constant*> CV1;
6395 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
6397 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
6398 Constant *C1 = ConstantVector::get(CV1);
6399 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
6401 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
6402 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6404 DAG.getIntPtrConstant(1)));
6405 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
6406 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6408 DAG.getIntPtrConstant(0)));
6409 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
6410 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
6411 MachinePointerInfo::getConstantPool(),
6413 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
6414 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck2);
6415 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
6416 MachinePointerInfo::getConstantPool(),
6418 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
6420 // Add the halves; easiest way is to swap them into another reg first.
6421 int ShufMask[2] = { 1, -1 };
6422 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
6423 DAG.getUNDEF(MVT::v2f64), ShufMask);
6424 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
6425 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
6426 DAG.getIntPtrConstant(0));
6429 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
6430 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
6431 SelectionDAG &DAG) const {
6432 DebugLoc dl = Op.getDebugLoc();
6433 // FP constant to bias correct the final result.
6434 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
6437 // Load the 32-bit value into an XMM register.
6438 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
6439 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6441 DAG.getIntPtrConstant(0)));
6443 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
6444 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
6445 DAG.getIntPtrConstant(0));
6447 // Or the load with the bias.
6448 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
6449 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
6450 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6452 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
6453 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6454 MVT::v2f64, Bias)));
6455 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
6456 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
6457 DAG.getIntPtrConstant(0));
6459 // Subtract the bias.
6460 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
6462 // Handle final rounding.
6463 EVT DestVT = Op.getValueType();
6465 if (DestVT.bitsLT(MVT::f64)) {
6466 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
6467 DAG.getIntPtrConstant(0));
6468 } else if (DestVT.bitsGT(MVT::f64)) {
6469 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
6472 // Handle final rounding.
6476 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
6477 SelectionDAG &DAG) const {
6478 SDValue N0 = Op.getOperand(0);
6479 DebugLoc dl = Op.getDebugLoc();
6481 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
6482 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
6483 // the optimization here.
6484 if (DAG.SignBitIsZero(N0))
6485 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
6487 EVT SrcVT = N0.getValueType();
6488 EVT DstVT = Op.getValueType();
6489 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
6490 return LowerUINT_TO_FP_i64(Op, DAG);
6491 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
6492 return LowerUINT_TO_FP_i32(Op, DAG);
6494 // Make a 64-bit buffer, and use it to build an FILD.
6495 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
6496 if (SrcVT == MVT::i32) {
6497 SDValue WordOff = DAG.getConstant(4, getPointerTy());
6498 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
6499 getPointerTy(), StackSlot, WordOff);
6500 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
6501 StackSlot, MachinePointerInfo(),
6503 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
6504 OffsetSlot, MachinePointerInfo(),
6506 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
6510 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
6511 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
6512 StackSlot, MachinePointerInfo(),
6514 // For i64 source, we need to add the appropriate power of 2 if the input
6515 // was negative. This is the same as the optimization in
6516 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
6517 // we must be careful to do the computation in x87 extended precision, not
6518 // in SSE. (The generic code can't know it's OK to do this, or how to.)
6519 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
6520 MachineMemOperand *MMO =
6521 DAG.getMachineFunction()
6522 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6523 MachineMemOperand::MOLoad, 8, 8);
6525 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
6526 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
6527 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
6530 APInt FF(32, 0x5F800000ULL);
6532 // Check whether the sign bit is set.
6533 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
6534 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
6537 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
6538 SDValue FudgePtr = DAG.getConstantPool(
6539 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
6542 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
6543 SDValue Zero = DAG.getIntPtrConstant(0);
6544 SDValue Four = DAG.getIntPtrConstant(4);
6545 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
6547 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
6549 // Load the value out, extending it from f32 to f80.
6550 // FIXME: Avoid the extend by constructing the right constant pool?
6551 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, MVT::f80, dl, DAG.getEntryNode(),
6552 FudgePtr, MachinePointerInfo::getConstantPool(),
6553 MVT::f32, false, false, 4);
6554 // Extend everything to 80 bits to force it to be done on x87.
6555 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
6556 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
6559 std::pair<SDValue,SDValue> X86TargetLowering::
6560 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
6561 DebugLoc DL = Op.getDebugLoc();
6563 EVT DstTy = Op.getValueType();
6566 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
6570 assert(DstTy.getSimpleVT() <= MVT::i64 &&
6571 DstTy.getSimpleVT() >= MVT::i16 &&
6572 "Unknown FP_TO_SINT to lower!");
6574 // These are really Legal.
6575 if (DstTy == MVT::i32 &&
6576 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
6577 return std::make_pair(SDValue(), SDValue());
6578 if (Subtarget->is64Bit() &&
6579 DstTy == MVT::i64 &&
6580 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
6581 return std::make_pair(SDValue(), SDValue());
6583 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
6585 MachineFunction &MF = DAG.getMachineFunction();
6586 unsigned MemSize = DstTy.getSizeInBits()/8;
6587 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
6588 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6593 switch (DstTy.getSimpleVT().SimpleTy) {
6594 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
6595 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
6596 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
6597 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
6600 SDValue Chain = DAG.getEntryNode();
6601 SDValue Value = Op.getOperand(0);
6602 EVT TheVT = Op.getOperand(0).getValueType();
6603 if (isScalarFPTypeInSSEReg(TheVT)) {
6604 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
6605 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
6606 MachinePointerInfo::getFixedStack(SSFI),
6608 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
6610 Chain, StackSlot, DAG.getValueType(TheVT)
6613 MachineMemOperand *MMO =
6614 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6615 MachineMemOperand::MOLoad, MemSize, MemSize);
6616 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
6618 Chain = Value.getValue(1);
6619 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
6620 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6623 MachineMemOperand *MMO =
6624 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6625 MachineMemOperand::MOStore, MemSize, MemSize);
6627 // Build the FP_TO_INT*_IN_MEM
6628 SDValue Ops[] = { Chain, Value, StackSlot };
6629 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
6630 Ops, 3, DstTy, MMO);
6632 return std::make_pair(FIST, StackSlot);
6635 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
6636 SelectionDAG &DAG) const {
6637 if (Op.getValueType().isVector())
6640 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
6641 SDValue FIST = Vals.first, StackSlot = Vals.second;
6642 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
6643 if (FIST.getNode() == 0) return Op;
6646 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
6647 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
6650 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
6651 SelectionDAG &DAG) const {
6652 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
6653 SDValue FIST = Vals.first, StackSlot = Vals.second;
6654 assert(FIST.getNode() && "Unexpected failure");
6657 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
6658 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
6661 SDValue X86TargetLowering::LowerFABS(SDValue Op,
6662 SelectionDAG &DAG) const {
6663 LLVMContext *Context = DAG.getContext();
6664 DebugLoc dl = Op.getDebugLoc();
6665 EVT VT = Op.getValueType();
6668 EltVT = VT.getVectorElementType();
6669 std::vector<Constant*> CV;
6670 if (EltVT == MVT::f64) {
6671 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
6675 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
6681 Constant *C = ConstantVector::get(CV);
6682 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6683 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
6684 MachinePointerInfo::getConstantPool(),
6686 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
6689 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
6690 LLVMContext *Context = DAG.getContext();
6691 DebugLoc dl = Op.getDebugLoc();
6692 EVT VT = Op.getValueType();
6695 EltVT = VT.getVectorElementType();
6696 std::vector<Constant*> CV;
6697 if (EltVT == MVT::f64) {
6698 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
6702 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
6708 Constant *C = ConstantVector::get(CV);
6709 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6710 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
6711 MachinePointerInfo::getConstantPool(),
6713 if (VT.isVector()) {
6714 return DAG.getNode(ISD::BITCAST, dl, VT,
6715 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
6716 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
6718 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Mask)));
6720 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
6724 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
6725 LLVMContext *Context = DAG.getContext();
6726 SDValue Op0 = Op.getOperand(0);
6727 SDValue Op1 = Op.getOperand(1);
6728 DebugLoc dl = Op.getDebugLoc();
6729 EVT VT = Op.getValueType();
6730 EVT SrcVT = Op1.getValueType();
6732 // If second operand is smaller, extend it first.
6733 if (SrcVT.bitsLT(VT)) {
6734 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
6737 // And if it is bigger, shrink it first.
6738 if (SrcVT.bitsGT(VT)) {
6739 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
6743 // At this point the operands and the result should have the same
6744 // type, and that won't be f80 since that is not custom lowered.
6746 // First get the sign bit of second operand.
6747 std::vector<Constant*> CV;
6748 if (SrcVT == MVT::f64) {
6749 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
6750 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
6752 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
6753 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6754 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6755 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6757 Constant *C = ConstantVector::get(CV);
6758 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6759 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
6760 MachinePointerInfo::getConstantPool(),
6762 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
6764 // Shift sign bit right or left if the two operands have different types.
6765 if (SrcVT.bitsGT(VT)) {
6766 // Op0 is MVT::f32, Op1 is MVT::f64.
6767 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
6768 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
6769 DAG.getConstant(32, MVT::i32));
6770 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
6771 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
6772 DAG.getIntPtrConstant(0));
6775 // Clear first operand sign bit.
6777 if (VT == MVT::f64) {
6778 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
6779 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
6781 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
6782 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6783 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6784 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6786 C = ConstantVector::get(CV);
6787 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6788 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
6789 MachinePointerInfo::getConstantPool(),
6791 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
6793 // Or the value with the sign bit.
6794 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
6797 /// Emit nodes that will be selected as "test Op0,Op0", or something
6799 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
6800 SelectionDAG &DAG) const {
6801 DebugLoc dl = Op.getDebugLoc();
6803 // CF and OF aren't always set the way we want. Determine which
6804 // of these we need.
6805 bool NeedCF = false;
6806 bool NeedOF = false;
6809 case X86::COND_A: case X86::COND_AE:
6810 case X86::COND_B: case X86::COND_BE:
6813 case X86::COND_G: case X86::COND_GE:
6814 case X86::COND_L: case X86::COND_LE:
6815 case X86::COND_O: case X86::COND_NO:
6820 // See if we can use the EFLAGS value from the operand instead of
6821 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
6822 // we prove that the arithmetic won't overflow, we can't use OF or CF.
6823 if (Op.getResNo() != 0 || NeedOF || NeedCF)
6824 // Emit a CMP with 0, which is the TEST pattern.
6825 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
6826 DAG.getConstant(0, Op.getValueType()));
6828 unsigned Opcode = 0;
6829 unsigned NumOperands = 0;
6830 switch (Op.getNode()->getOpcode()) {
6832 // Due to an isel shortcoming, be conservative if this add is likely to be
6833 // selected as part of a load-modify-store instruction. When the root node
6834 // in a match is a store, isel doesn't know how to remap non-chain non-flag
6835 // uses of other nodes in the match, such as the ADD in this case. This
6836 // leads to the ADD being left around and reselected, with the result being
6837 // two adds in the output. Alas, even if none our users are stores, that
6838 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
6839 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
6840 // climbing the DAG back to the root, and it doesn't seem to be worth the
6842 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6843 UE = Op.getNode()->use_end(); UI != UE; ++UI)
6844 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
6847 if (ConstantSDNode *C =
6848 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
6849 // An add of one will be selected as an INC.
6850 if (C->getAPIntValue() == 1) {
6851 Opcode = X86ISD::INC;
6856 // An add of negative one (subtract of one) will be selected as a DEC.
6857 if (C->getAPIntValue().isAllOnesValue()) {
6858 Opcode = X86ISD::DEC;
6864 // Otherwise use a regular EFLAGS-setting add.
6865 Opcode = X86ISD::ADD;
6869 // If the primary and result isn't used, don't bother using X86ISD::AND,
6870 // because a TEST instruction will be better.
6871 bool NonFlagUse = false;
6872 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6873 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
6875 unsigned UOpNo = UI.getOperandNo();
6876 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
6877 // Look pass truncate.
6878 UOpNo = User->use_begin().getOperandNo();
6879 User = *User->use_begin();
6882 if (User->getOpcode() != ISD::BRCOND &&
6883 User->getOpcode() != ISD::SETCC &&
6884 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
6897 // Due to the ISEL shortcoming noted above, be conservative if this op is
6898 // likely to be selected as part of a load-modify-store instruction.
6899 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6900 UE = Op.getNode()->use_end(); UI != UE; ++UI)
6901 if (UI->getOpcode() == ISD::STORE)
6904 // Otherwise use a regular EFLAGS-setting instruction.
6905 switch (Op.getNode()->getOpcode()) {
6906 default: llvm_unreachable("unexpected operator!");
6907 case ISD::SUB: Opcode = X86ISD::SUB; break;
6908 case ISD::OR: Opcode = X86ISD::OR; break;
6909 case ISD::XOR: Opcode = X86ISD::XOR; break;
6910 case ISD::AND: Opcode = X86ISD::AND; break;
6922 return SDValue(Op.getNode(), 1);
6929 // Emit a CMP with 0, which is the TEST pattern.
6930 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
6931 DAG.getConstant(0, Op.getValueType()));
6933 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
6934 SmallVector<SDValue, 4> Ops;
6935 for (unsigned i = 0; i != NumOperands; ++i)
6936 Ops.push_back(Op.getOperand(i));
6938 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
6939 DAG.ReplaceAllUsesWith(Op, New);
6940 return SDValue(New.getNode(), 1);
6943 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
6945 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
6946 SelectionDAG &DAG) const {
6947 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
6948 if (C->getAPIntValue() == 0)
6949 return EmitTest(Op0, X86CC, DAG);
6951 DebugLoc dl = Op0.getDebugLoc();
6952 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
6955 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
6956 /// if it's possible.
6957 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
6958 DebugLoc dl, SelectionDAG &DAG) const {
6959 SDValue Op0 = And.getOperand(0);
6960 SDValue Op1 = And.getOperand(1);
6961 if (Op0.getOpcode() == ISD::TRUNCATE)
6962 Op0 = Op0.getOperand(0);
6963 if (Op1.getOpcode() == ISD::TRUNCATE)
6964 Op1 = Op1.getOperand(0);
6967 if (Op1.getOpcode() == ISD::SHL)
6968 std::swap(Op0, Op1);
6969 if (Op0.getOpcode() == ISD::SHL) {
6970 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
6971 if (And00C->getZExtValue() == 1) {
6972 // If we looked past a truncate, check that it's only truncating away
6974 unsigned BitWidth = Op0.getValueSizeInBits();
6975 unsigned AndBitWidth = And.getValueSizeInBits();
6976 if (BitWidth > AndBitWidth) {
6977 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
6978 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
6979 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
6983 RHS = Op0.getOperand(1);
6985 } else if (Op1.getOpcode() == ISD::Constant) {
6986 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
6987 SDValue AndLHS = Op0;
6988 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
6989 LHS = AndLHS.getOperand(0);
6990 RHS = AndLHS.getOperand(1);
6994 if (LHS.getNode()) {
6995 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
6996 // instruction. Since the shift amount is in-range-or-undefined, we know
6997 // that doing a bittest on the i32 value is ok. We extend to i32 because
6998 // the encoding for the i16 version is larger than the i32 version.
6999 // Also promote i16 to i32 for performance / code size reason.
7000 if (LHS.getValueType() == MVT::i8 ||
7001 LHS.getValueType() == MVT::i16)
7002 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
7004 // If the operand types disagree, extend the shift amount to match. Since
7005 // BT ignores high bits (like shifts) we can use anyextend.
7006 if (LHS.getValueType() != RHS.getValueType())
7007 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
7009 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
7010 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
7011 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7012 DAG.getConstant(Cond, MVT::i8), BT);
7018 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
7019 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
7020 SDValue Op0 = Op.getOperand(0);
7021 SDValue Op1 = Op.getOperand(1);
7022 DebugLoc dl = Op.getDebugLoc();
7023 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
7025 // Optimize to BT if possible.
7026 // Lower (X & (1 << N)) == 0 to BT(X, N).
7027 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
7028 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
7029 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
7030 Op1.getOpcode() == ISD::Constant &&
7031 cast<ConstantSDNode>(Op1)->isNullValue() &&
7032 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
7033 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
7034 if (NewSetCC.getNode())
7038 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
7040 if (Op1.getOpcode() == ISD::Constant &&
7041 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
7042 cast<ConstantSDNode>(Op1)->isNullValue()) &&
7043 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
7045 // If the input is a setcc, then reuse the input setcc or use a new one with
7046 // the inverted condition.
7047 if (Op0.getOpcode() == X86ISD::SETCC) {
7048 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
7049 bool Invert = (CC == ISD::SETNE) ^
7050 cast<ConstantSDNode>(Op1)->isNullValue();
7051 if (!Invert) return Op0;
7053 CCode = X86::GetOppositeBranchCondition(CCode);
7054 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7055 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
7059 bool isFP = Op1.getValueType().isFloatingPoint();
7060 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
7061 if (X86CC == X86::COND_INVALID)
7064 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
7065 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7066 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
7069 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
7071 SDValue Op0 = Op.getOperand(0);
7072 SDValue Op1 = Op.getOperand(1);
7073 SDValue CC = Op.getOperand(2);
7074 EVT VT = Op.getValueType();
7075 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
7076 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
7077 DebugLoc dl = Op.getDebugLoc();
7081 EVT VT0 = Op0.getValueType();
7082 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
7083 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
7086 switch (SetCCOpcode) {
7089 case ISD::SETEQ: SSECC = 0; break;
7091 case ISD::SETGT: Swap = true; // Fallthrough
7093 case ISD::SETOLT: SSECC = 1; break;
7095 case ISD::SETGE: Swap = true; // Fallthrough
7097 case ISD::SETOLE: SSECC = 2; break;
7098 case ISD::SETUO: SSECC = 3; break;
7100 case ISD::SETNE: SSECC = 4; break;
7101 case ISD::SETULE: Swap = true;
7102 case ISD::SETUGE: SSECC = 5; break;
7103 case ISD::SETULT: Swap = true;
7104 case ISD::SETUGT: SSECC = 6; break;
7105 case ISD::SETO: SSECC = 7; break;
7108 std::swap(Op0, Op1);
7110 // In the two special cases we can't handle, emit two comparisons.
7112 if (SetCCOpcode == ISD::SETUEQ) {
7114 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
7115 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
7116 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
7118 else if (SetCCOpcode == ISD::SETONE) {
7120 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
7121 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
7122 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
7124 llvm_unreachable("Illegal FP comparison");
7126 // Handle all other FP comparisons here.
7127 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
7130 // We are handling one of the integer comparisons here. Since SSE only has
7131 // GT and EQ comparisons for integer, swapping operands and multiple
7132 // operations may be required for some comparisons.
7133 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
7134 bool Swap = false, Invert = false, FlipSigns = false;
7136 switch (VT.getSimpleVT().SimpleTy) {
7138 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
7139 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
7140 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
7141 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
7144 switch (SetCCOpcode) {
7146 case ISD::SETNE: Invert = true;
7147 case ISD::SETEQ: Opc = EQOpc; break;
7148 case ISD::SETLT: Swap = true;
7149 case ISD::SETGT: Opc = GTOpc; break;
7150 case ISD::SETGE: Swap = true;
7151 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
7152 case ISD::SETULT: Swap = true;
7153 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
7154 case ISD::SETUGE: Swap = true;
7155 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
7158 std::swap(Op0, Op1);
7160 // Since SSE has no unsigned integer comparisons, we need to flip the sign
7161 // bits of the inputs before performing those operations.
7163 EVT EltVT = VT.getVectorElementType();
7164 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
7166 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
7167 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
7169 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
7170 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
7173 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
7175 // If the logical-not of the result is required, perform that now.
7177 Result = DAG.getNOT(dl, Result, VT);
7182 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
7183 static bool isX86LogicalCmp(SDValue Op) {
7184 unsigned Opc = Op.getNode()->getOpcode();
7185 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
7187 if (Op.getResNo() == 1 &&
7188 (Opc == X86ISD::ADD ||
7189 Opc == X86ISD::SUB ||
7190 Opc == X86ISD::ADC ||
7191 Opc == X86ISD::SBB ||
7192 Opc == X86ISD::SMUL ||
7193 Opc == X86ISD::UMUL ||
7194 Opc == X86ISD::INC ||
7195 Opc == X86ISD::DEC ||
7196 Opc == X86ISD::OR ||
7197 Opc == X86ISD::XOR ||
7198 Opc == X86ISD::AND))
7201 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
7207 static bool isZero(SDValue V) {
7208 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
7209 return C && C->isNullValue();
7212 static bool isAllOnes(SDValue V) {
7213 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
7214 return C && C->isAllOnesValue();
7217 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
7218 bool addTest = true;
7219 SDValue Cond = Op.getOperand(0);
7220 SDValue Op1 = Op.getOperand(1);
7221 SDValue Op2 = Op.getOperand(2);
7222 DebugLoc DL = Op.getDebugLoc();
7225 if (Cond.getOpcode() == ISD::SETCC) {
7226 SDValue NewCond = LowerSETCC(Cond, DAG);
7227 if (NewCond.getNode())
7231 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
7232 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
7233 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
7234 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
7235 if (Cond.getOpcode() == X86ISD::SETCC &&
7236 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
7237 isZero(Cond.getOperand(1).getOperand(1))) {
7238 SDValue Cmp = Cond.getOperand(1);
7240 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
7242 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
7243 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
7244 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
7246 SDValue CmpOp0 = Cmp.getOperand(0);
7247 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
7248 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
7250 SDValue Res = // Res = 0 or -1.
7251 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
7252 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
7254 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
7255 Res = DAG.getNOT(DL, Res, Res.getValueType());
7257 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
7258 if (N2C == 0 || !N2C->isNullValue())
7259 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
7264 // Look past (and (setcc_carry (cmp ...)), 1).
7265 if (Cond.getOpcode() == ISD::AND &&
7266 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
7267 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
7268 if (C && C->getAPIntValue() == 1)
7269 Cond = Cond.getOperand(0);
7272 // If condition flag is set by a X86ISD::CMP, then use it as the condition
7273 // setting operand in place of the X86ISD::SETCC.
7274 if (Cond.getOpcode() == X86ISD::SETCC ||
7275 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
7276 CC = Cond.getOperand(0);
7278 SDValue Cmp = Cond.getOperand(1);
7279 unsigned Opc = Cmp.getOpcode();
7280 EVT VT = Op.getValueType();
7282 bool IllegalFPCMov = false;
7283 if (VT.isFloatingPoint() && !VT.isVector() &&
7284 !isScalarFPTypeInSSEReg(VT)) // FPStack?
7285 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
7287 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
7288 Opc == X86ISD::BT) { // FIXME
7295 // Look pass the truncate.
7296 if (Cond.getOpcode() == ISD::TRUNCATE)
7297 Cond = Cond.getOperand(0);
7299 // We know the result of AND is compared against zero. Try to match
7301 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
7302 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
7303 if (NewSetCC.getNode()) {
7304 CC = NewSetCC.getOperand(0);
7305 Cond = NewSetCC.getOperand(1);
7312 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7313 Cond = EmitTest(Cond, X86::COND_NE, DAG);
7316 // a < b ? -1 : 0 -> RES = ~setcc_carry
7317 // a < b ? 0 : -1 -> RES = setcc_carry
7318 // a >= b ? -1 : 0 -> RES = setcc_carry
7319 // a >= b ? 0 : -1 -> RES = ~setcc_carry
7320 if (Cond.getOpcode() == X86ISD::CMP) {
7321 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
7323 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
7324 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
7325 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
7326 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
7327 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
7328 return DAG.getNOT(DL, Res, Res.getValueType());
7333 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
7334 // condition is true.
7335 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
7336 SDValue Ops[] = { Op2, Op1, CC, Cond };
7337 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
7340 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
7341 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
7342 // from the AND / OR.
7343 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
7344 Opc = Op.getOpcode();
7345 if (Opc != ISD::OR && Opc != ISD::AND)
7347 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
7348 Op.getOperand(0).hasOneUse() &&
7349 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
7350 Op.getOperand(1).hasOneUse());
7353 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
7354 // 1 and that the SETCC node has a single use.
7355 static bool isXor1OfSetCC(SDValue Op) {
7356 if (Op.getOpcode() != ISD::XOR)
7358 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7359 if (N1C && N1C->getAPIntValue() == 1) {
7360 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
7361 Op.getOperand(0).hasOneUse();
7366 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
7367 bool addTest = true;
7368 SDValue Chain = Op.getOperand(0);
7369 SDValue Cond = Op.getOperand(1);
7370 SDValue Dest = Op.getOperand(2);
7371 DebugLoc dl = Op.getDebugLoc();
7374 if (Cond.getOpcode() == ISD::SETCC) {
7375 SDValue NewCond = LowerSETCC(Cond, DAG);
7376 if (NewCond.getNode())
7380 // FIXME: LowerXALUO doesn't handle these!!
7381 else if (Cond.getOpcode() == X86ISD::ADD ||
7382 Cond.getOpcode() == X86ISD::SUB ||
7383 Cond.getOpcode() == X86ISD::SMUL ||
7384 Cond.getOpcode() == X86ISD::UMUL)
7385 Cond = LowerXALUO(Cond, DAG);
7388 // Look pass (and (setcc_carry (cmp ...)), 1).
7389 if (Cond.getOpcode() == ISD::AND &&
7390 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
7391 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
7392 if (C && C->getAPIntValue() == 1)
7393 Cond = Cond.getOperand(0);
7396 // If condition flag is set by a X86ISD::CMP, then use it as the condition
7397 // setting operand in place of the X86ISD::SETCC.
7398 if (Cond.getOpcode() == X86ISD::SETCC ||
7399 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
7400 CC = Cond.getOperand(0);
7402 SDValue Cmp = Cond.getOperand(1);
7403 unsigned Opc = Cmp.getOpcode();
7404 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
7405 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
7409 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
7413 // These can only come from an arithmetic instruction with overflow,
7414 // e.g. SADDO, UADDO.
7415 Cond = Cond.getNode()->getOperand(1);
7422 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
7423 SDValue Cmp = Cond.getOperand(0).getOperand(1);
7424 if (CondOpc == ISD::OR) {
7425 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
7426 // two branches instead of an explicit OR instruction with a
7428 if (Cmp == Cond.getOperand(1).getOperand(1) &&
7429 isX86LogicalCmp(Cmp)) {
7430 CC = Cond.getOperand(0).getOperand(0);
7431 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
7432 Chain, Dest, CC, Cmp);
7433 CC = Cond.getOperand(1).getOperand(0);
7437 } else { // ISD::AND
7438 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
7439 // two branches instead of an explicit AND instruction with a
7440 // separate test. However, we only do this if this block doesn't
7441 // have a fall-through edge, because this requires an explicit
7442 // jmp when the condition is false.
7443 if (Cmp == Cond.getOperand(1).getOperand(1) &&
7444 isX86LogicalCmp(Cmp) &&
7445 Op.getNode()->hasOneUse()) {
7446 X86::CondCode CCode =
7447 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
7448 CCode = X86::GetOppositeBranchCondition(CCode);
7449 CC = DAG.getConstant(CCode, MVT::i8);
7450 SDNode *User = *Op.getNode()->use_begin();
7451 // Look for an unconditional branch following this conditional branch.
7452 // We need this because we need to reverse the successors in order
7453 // to implement FCMP_OEQ.
7454 if (User->getOpcode() == ISD::BR) {
7455 SDValue FalseBB = User->getOperand(1);
7457 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
7458 assert(NewBR == User);
7462 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
7463 Chain, Dest, CC, Cmp);
7464 X86::CondCode CCode =
7465 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
7466 CCode = X86::GetOppositeBranchCondition(CCode);
7467 CC = DAG.getConstant(CCode, MVT::i8);
7473 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
7474 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
7475 // It should be transformed during dag combiner except when the condition
7476 // is set by a arithmetics with overflow node.
7477 X86::CondCode CCode =
7478 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
7479 CCode = X86::GetOppositeBranchCondition(CCode);
7480 CC = DAG.getConstant(CCode, MVT::i8);
7481 Cond = Cond.getOperand(0).getOperand(1);
7487 // Look pass the truncate.
7488 if (Cond.getOpcode() == ISD::TRUNCATE)
7489 Cond = Cond.getOperand(0);
7491 // We know the result of AND is compared against zero. Try to match
7493 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
7494 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
7495 if (NewSetCC.getNode()) {
7496 CC = NewSetCC.getOperand(0);
7497 Cond = NewSetCC.getOperand(1);
7504 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7505 Cond = EmitTest(Cond, X86::COND_NE, DAG);
7507 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
7508 Chain, Dest, CC, Cond);
7512 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
7513 // Calls to _alloca is needed to probe the stack when allocating more than 4k
7514 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
7515 // that the guard pages used by the OS virtual memory manager are allocated in
7516 // correct sequence.
7518 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
7519 SelectionDAG &DAG) const {
7520 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows()) &&
7521 "This should be used only on Windows targets");
7522 DebugLoc dl = Op.getDebugLoc();
7525 SDValue Chain = Op.getOperand(0);
7526 SDValue Size = Op.getOperand(1);
7527 // FIXME: Ensure alignment here
7531 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
7533 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
7534 Flag = Chain.getValue(1);
7536 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7538 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
7539 Flag = Chain.getValue(1);
7541 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
7543 SDValue Ops1[2] = { Chain.getValue(0), Chain };
7544 return DAG.getMergeValues(Ops1, 2, dl);
7547 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
7548 MachineFunction &MF = DAG.getMachineFunction();
7549 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
7551 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
7552 DebugLoc DL = Op.getDebugLoc();
7554 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
7555 // vastart just stores the address of the VarArgsFrameIndex slot into the
7556 // memory location argument.
7557 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
7559 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
7560 MachinePointerInfo(SV), false, false, 0);
7564 // gp_offset (0 - 6 * 8)
7565 // fp_offset (48 - 48 + 8 * 16)
7566 // overflow_arg_area (point to parameters coming in memory).
7568 SmallVector<SDValue, 8> MemOps;
7569 SDValue FIN = Op.getOperand(1);
7571 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
7572 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
7574 FIN, MachinePointerInfo(SV), false, false, 0);
7575 MemOps.push_back(Store);
7578 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7579 FIN, DAG.getIntPtrConstant(4));
7580 Store = DAG.getStore(Op.getOperand(0), DL,
7581 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
7583 FIN, MachinePointerInfo(SV, 4), false, false, 0);
7584 MemOps.push_back(Store);
7586 // Store ptr to overflow_arg_area
7587 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7588 FIN, DAG.getIntPtrConstant(4));
7589 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
7591 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
7592 MachinePointerInfo(SV, 8),
7594 MemOps.push_back(Store);
7596 // Store ptr to reg_save_area.
7597 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7598 FIN, DAG.getIntPtrConstant(8));
7599 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
7601 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
7602 MachinePointerInfo(SV, 16), false, false, 0);
7603 MemOps.push_back(Store);
7604 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
7605 &MemOps[0], MemOps.size());
7608 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
7609 assert(Subtarget->is64Bit() &&
7610 "LowerVAARG only handles 64-bit va_arg!");
7611 assert((Subtarget->isTargetLinux() ||
7612 Subtarget->isTargetDarwin()) &&
7613 "Unhandled target in LowerVAARG");
7614 assert(Op.getNode()->getNumOperands() == 4);
7615 SDValue Chain = Op.getOperand(0);
7616 SDValue SrcPtr = Op.getOperand(1);
7617 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
7618 unsigned Align = Op.getConstantOperandVal(3);
7619 DebugLoc dl = Op.getDebugLoc();
7621 EVT ArgVT = Op.getNode()->getValueType(0);
7622 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
7623 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
7626 // Decide which area this value should be read from.
7627 // TODO: Implement the AMD64 ABI in its entirety. This simple
7628 // selection mechanism works only for the basic types.
7629 if (ArgVT == MVT::f80) {
7630 llvm_unreachable("va_arg for f80 not yet implemented");
7631 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
7632 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
7633 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
7634 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
7636 llvm_unreachable("Unhandled argument type in LowerVAARG");
7640 // Sanity Check: Make sure using fp_offset makes sense.
7641 assert(!UseSoftFloat &&
7642 !(DAG.getMachineFunction()
7643 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
7644 Subtarget->hasXMM());
7647 // Insert VAARG_64 node into the DAG
7648 // VAARG_64 returns two values: Variable Argument Address, Chain
7649 SmallVector<SDValue, 11> InstOps;
7650 InstOps.push_back(Chain);
7651 InstOps.push_back(SrcPtr);
7652 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
7653 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
7654 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
7655 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
7656 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
7657 VTs, &InstOps[0], InstOps.size(),
7659 MachinePointerInfo(SV),
7664 Chain = VAARG.getValue(1);
7666 // Load the next argument and return it
7667 return DAG.getLoad(ArgVT, dl,
7670 MachinePointerInfo(),
7674 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
7675 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
7676 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
7677 SDValue Chain = Op.getOperand(0);
7678 SDValue DstPtr = Op.getOperand(1);
7679 SDValue SrcPtr = Op.getOperand(2);
7680 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
7681 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
7682 DebugLoc DL = Op.getDebugLoc();
7684 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
7685 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
7687 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
7691 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
7692 DebugLoc dl = Op.getDebugLoc();
7693 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7695 default: return SDValue(); // Don't custom lower most intrinsics.
7696 // Comparison intrinsics.
7697 case Intrinsic::x86_sse_comieq_ss:
7698 case Intrinsic::x86_sse_comilt_ss:
7699 case Intrinsic::x86_sse_comile_ss:
7700 case Intrinsic::x86_sse_comigt_ss:
7701 case Intrinsic::x86_sse_comige_ss:
7702 case Intrinsic::x86_sse_comineq_ss:
7703 case Intrinsic::x86_sse_ucomieq_ss:
7704 case Intrinsic::x86_sse_ucomilt_ss:
7705 case Intrinsic::x86_sse_ucomile_ss:
7706 case Intrinsic::x86_sse_ucomigt_ss:
7707 case Intrinsic::x86_sse_ucomige_ss:
7708 case Intrinsic::x86_sse_ucomineq_ss:
7709 case Intrinsic::x86_sse2_comieq_sd:
7710 case Intrinsic::x86_sse2_comilt_sd:
7711 case Intrinsic::x86_sse2_comile_sd:
7712 case Intrinsic::x86_sse2_comigt_sd:
7713 case Intrinsic::x86_sse2_comige_sd:
7714 case Intrinsic::x86_sse2_comineq_sd:
7715 case Intrinsic::x86_sse2_ucomieq_sd:
7716 case Intrinsic::x86_sse2_ucomilt_sd:
7717 case Intrinsic::x86_sse2_ucomile_sd:
7718 case Intrinsic::x86_sse2_ucomigt_sd:
7719 case Intrinsic::x86_sse2_ucomige_sd:
7720 case Intrinsic::x86_sse2_ucomineq_sd: {
7722 ISD::CondCode CC = ISD::SETCC_INVALID;
7725 case Intrinsic::x86_sse_comieq_ss:
7726 case Intrinsic::x86_sse2_comieq_sd:
7730 case Intrinsic::x86_sse_comilt_ss:
7731 case Intrinsic::x86_sse2_comilt_sd:
7735 case Intrinsic::x86_sse_comile_ss:
7736 case Intrinsic::x86_sse2_comile_sd:
7740 case Intrinsic::x86_sse_comigt_ss:
7741 case Intrinsic::x86_sse2_comigt_sd:
7745 case Intrinsic::x86_sse_comige_ss:
7746 case Intrinsic::x86_sse2_comige_sd:
7750 case Intrinsic::x86_sse_comineq_ss:
7751 case Intrinsic::x86_sse2_comineq_sd:
7755 case Intrinsic::x86_sse_ucomieq_ss:
7756 case Intrinsic::x86_sse2_ucomieq_sd:
7757 Opc = X86ISD::UCOMI;
7760 case Intrinsic::x86_sse_ucomilt_ss:
7761 case Intrinsic::x86_sse2_ucomilt_sd:
7762 Opc = X86ISD::UCOMI;
7765 case Intrinsic::x86_sse_ucomile_ss:
7766 case Intrinsic::x86_sse2_ucomile_sd:
7767 Opc = X86ISD::UCOMI;
7770 case Intrinsic::x86_sse_ucomigt_ss:
7771 case Intrinsic::x86_sse2_ucomigt_sd:
7772 Opc = X86ISD::UCOMI;
7775 case Intrinsic::x86_sse_ucomige_ss:
7776 case Intrinsic::x86_sse2_ucomige_sd:
7777 Opc = X86ISD::UCOMI;
7780 case Intrinsic::x86_sse_ucomineq_ss:
7781 case Intrinsic::x86_sse2_ucomineq_sd:
7782 Opc = X86ISD::UCOMI;
7787 SDValue LHS = Op.getOperand(1);
7788 SDValue RHS = Op.getOperand(2);
7789 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
7790 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
7791 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
7792 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7793 DAG.getConstant(X86CC, MVT::i8), Cond);
7794 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
7796 // ptest and testp intrinsics. The intrinsic these come from are designed to
7797 // return an integer value, not just an instruction so lower it to the ptest
7798 // or testp pattern and a setcc for the result.
7799 case Intrinsic::x86_sse41_ptestz:
7800 case Intrinsic::x86_sse41_ptestc:
7801 case Intrinsic::x86_sse41_ptestnzc:
7802 case Intrinsic::x86_avx_ptestz_256:
7803 case Intrinsic::x86_avx_ptestc_256:
7804 case Intrinsic::x86_avx_ptestnzc_256:
7805 case Intrinsic::x86_avx_vtestz_ps:
7806 case Intrinsic::x86_avx_vtestc_ps:
7807 case Intrinsic::x86_avx_vtestnzc_ps:
7808 case Intrinsic::x86_avx_vtestz_pd:
7809 case Intrinsic::x86_avx_vtestc_pd:
7810 case Intrinsic::x86_avx_vtestnzc_pd:
7811 case Intrinsic::x86_avx_vtestz_ps_256:
7812 case Intrinsic::x86_avx_vtestc_ps_256:
7813 case Intrinsic::x86_avx_vtestnzc_ps_256:
7814 case Intrinsic::x86_avx_vtestz_pd_256:
7815 case Intrinsic::x86_avx_vtestc_pd_256:
7816 case Intrinsic::x86_avx_vtestnzc_pd_256: {
7817 bool IsTestPacked = false;
7820 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
7821 case Intrinsic::x86_avx_vtestz_ps:
7822 case Intrinsic::x86_avx_vtestz_pd:
7823 case Intrinsic::x86_avx_vtestz_ps_256:
7824 case Intrinsic::x86_avx_vtestz_pd_256:
7825 IsTestPacked = true; // Fallthrough
7826 case Intrinsic::x86_sse41_ptestz:
7827 case Intrinsic::x86_avx_ptestz_256:
7829 X86CC = X86::COND_E;
7831 case Intrinsic::x86_avx_vtestc_ps:
7832 case Intrinsic::x86_avx_vtestc_pd:
7833 case Intrinsic::x86_avx_vtestc_ps_256:
7834 case Intrinsic::x86_avx_vtestc_pd_256:
7835 IsTestPacked = true; // Fallthrough
7836 case Intrinsic::x86_sse41_ptestc:
7837 case Intrinsic::x86_avx_ptestc_256:
7839 X86CC = X86::COND_B;
7841 case Intrinsic::x86_avx_vtestnzc_ps:
7842 case Intrinsic::x86_avx_vtestnzc_pd:
7843 case Intrinsic::x86_avx_vtestnzc_ps_256:
7844 case Intrinsic::x86_avx_vtestnzc_pd_256:
7845 IsTestPacked = true; // Fallthrough
7846 case Intrinsic::x86_sse41_ptestnzc:
7847 case Intrinsic::x86_avx_ptestnzc_256:
7849 X86CC = X86::COND_A;
7853 SDValue LHS = Op.getOperand(1);
7854 SDValue RHS = Op.getOperand(2);
7855 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
7856 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
7857 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
7858 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
7859 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
7862 // Fix vector shift instructions where the last operand is a non-immediate
7864 case Intrinsic::x86_sse2_pslli_w:
7865 case Intrinsic::x86_sse2_pslli_d:
7866 case Intrinsic::x86_sse2_pslli_q:
7867 case Intrinsic::x86_sse2_psrli_w:
7868 case Intrinsic::x86_sse2_psrli_d:
7869 case Intrinsic::x86_sse2_psrli_q:
7870 case Intrinsic::x86_sse2_psrai_w:
7871 case Intrinsic::x86_sse2_psrai_d:
7872 case Intrinsic::x86_mmx_pslli_w:
7873 case Intrinsic::x86_mmx_pslli_d:
7874 case Intrinsic::x86_mmx_pslli_q:
7875 case Intrinsic::x86_mmx_psrli_w:
7876 case Intrinsic::x86_mmx_psrli_d:
7877 case Intrinsic::x86_mmx_psrli_q:
7878 case Intrinsic::x86_mmx_psrai_w:
7879 case Intrinsic::x86_mmx_psrai_d: {
7880 SDValue ShAmt = Op.getOperand(2);
7881 if (isa<ConstantSDNode>(ShAmt))
7884 unsigned NewIntNo = 0;
7885 EVT ShAmtVT = MVT::v4i32;
7887 case Intrinsic::x86_sse2_pslli_w:
7888 NewIntNo = Intrinsic::x86_sse2_psll_w;
7890 case Intrinsic::x86_sse2_pslli_d:
7891 NewIntNo = Intrinsic::x86_sse2_psll_d;
7893 case Intrinsic::x86_sse2_pslli_q:
7894 NewIntNo = Intrinsic::x86_sse2_psll_q;
7896 case Intrinsic::x86_sse2_psrli_w:
7897 NewIntNo = Intrinsic::x86_sse2_psrl_w;
7899 case Intrinsic::x86_sse2_psrli_d:
7900 NewIntNo = Intrinsic::x86_sse2_psrl_d;
7902 case Intrinsic::x86_sse2_psrli_q:
7903 NewIntNo = Intrinsic::x86_sse2_psrl_q;
7905 case Intrinsic::x86_sse2_psrai_w:
7906 NewIntNo = Intrinsic::x86_sse2_psra_w;
7908 case Intrinsic::x86_sse2_psrai_d:
7909 NewIntNo = Intrinsic::x86_sse2_psra_d;
7912 ShAmtVT = MVT::v2i32;
7914 case Intrinsic::x86_mmx_pslli_w:
7915 NewIntNo = Intrinsic::x86_mmx_psll_w;
7917 case Intrinsic::x86_mmx_pslli_d:
7918 NewIntNo = Intrinsic::x86_mmx_psll_d;
7920 case Intrinsic::x86_mmx_pslli_q:
7921 NewIntNo = Intrinsic::x86_mmx_psll_q;
7923 case Intrinsic::x86_mmx_psrli_w:
7924 NewIntNo = Intrinsic::x86_mmx_psrl_w;
7926 case Intrinsic::x86_mmx_psrli_d:
7927 NewIntNo = Intrinsic::x86_mmx_psrl_d;
7929 case Intrinsic::x86_mmx_psrli_q:
7930 NewIntNo = Intrinsic::x86_mmx_psrl_q;
7932 case Intrinsic::x86_mmx_psrai_w:
7933 NewIntNo = Intrinsic::x86_mmx_psra_w;
7935 case Intrinsic::x86_mmx_psrai_d:
7936 NewIntNo = Intrinsic::x86_mmx_psra_d;
7938 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
7944 // The vector shift intrinsics with scalars uses 32b shift amounts but
7945 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
7949 ShOps[1] = DAG.getConstant(0, MVT::i32);
7950 if (ShAmtVT == MVT::v4i32) {
7951 ShOps[2] = DAG.getUNDEF(MVT::i32);
7952 ShOps[3] = DAG.getUNDEF(MVT::i32);
7953 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
7955 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
7956 // FIXME this must be lowered to get rid of the invalid type.
7959 EVT VT = Op.getValueType();
7960 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
7961 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7962 DAG.getConstant(NewIntNo, MVT::i32),
7963 Op.getOperand(1), ShAmt);
7968 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
7969 SelectionDAG &DAG) const {
7970 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7971 MFI->setReturnAddressIsTaken(true);
7973 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7974 DebugLoc dl = Op.getDebugLoc();
7977 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
7979 DAG.getConstant(TD->getPointerSize(),
7980 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
7981 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7982 DAG.getNode(ISD::ADD, dl, getPointerTy(),
7984 MachinePointerInfo(), false, false, 0);
7987 // Just load the return address.
7988 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
7989 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7990 RetAddrFI, MachinePointerInfo(), false, false, 0);
7993 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
7994 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7995 MFI->setFrameAddressIsTaken(true);
7997 EVT VT = Op.getValueType();
7998 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
7999 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8000 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
8001 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
8003 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
8004 MachinePointerInfo(),
8009 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
8010 SelectionDAG &DAG) const {
8011 return DAG.getIntPtrConstant(2*TD->getPointerSize());
8014 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
8015 MachineFunction &MF = DAG.getMachineFunction();
8016 SDValue Chain = Op.getOperand(0);
8017 SDValue Offset = Op.getOperand(1);
8018 SDValue Handler = Op.getOperand(2);
8019 DebugLoc dl = Op.getDebugLoc();
8021 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
8022 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
8024 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
8026 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
8027 DAG.getIntPtrConstant(TD->getPointerSize()));
8028 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
8029 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
8031 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
8032 MF.getRegInfo().addLiveOut(StoreAddrReg);
8034 return DAG.getNode(X86ISD::EH_RETURN, dl,
8036 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
8039 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
8040 SelectionDAG &DAG) const {
8041 SDValue Root = Op.getOperand(0);
8042 SDValue Trmp = Op.getOperand(1); // trampoline
8043 SDValue FPtr = Op.getOperand(2); // nested function
8044 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
8045 DebugLoc dl = Op.getDebugLoc();
8047 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
8049 if (Subtarget->is64Bit()) {
8050 SDValue OutChains[6];
8052 // Large code-model.
8053 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
8054 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
8056 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
8057 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
8059 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
8061 // Load the pointer to the nested function into R11.
8062 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
8063 SDValue Addr = Trmp;
8064 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
8065 Addr, MachinePointerInfo(TrmpAddr),
8068 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8069 DAG.getConstant(2, MVT::i64));
8070 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
8071 MachinePointerInfo(TrmpAddr, 2),
8074 // Load the 'nest' parameter value into R10.
8075 // R10 is specified in X86CallingConv.td
8076 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
8077 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8078 DAG.getConstant(10, MVT::i64));
8079 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
8080 Addr, MachinePointerInfo(TrmpAddr, 10),
8083 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8084 DAG.getConstant(12, MVT::i64));
8085 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
8086 MachinePointerInfo(TrmpAddr, 12),
8089 // Jump to the nested function.
8090 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
8091 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8092 DAG.getConstant(20, MVT::i64));
8093 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
8094 Addr, MachinePointerInfo(TrmpAddr, 20),
8097 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
8098 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8099 DAG.getConstant(22, MVT::i64));
8100 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
8101 MachinePointerInfo(TrmpAddr, 22),
8105 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
8106 return DAG.getMergeValues(Ops, 2, dl);
8108 const Function *Func =
8109 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
8110 CallingConv::ID CC = Func->getCallingConv();
8115 llvm_unreachable("Unsupported calling convention");
8116 case CallingConv::C:
8117 case CallingConv::X86_StdCall: {
8118 // Pass 'nest' parameter in ECX.
8119 // Must be kept in sync with X86CallingConv.td
8122 // Check that ECX wasn't needed by an 'inreg' parameter.
8123 const FunctionType *FTy = Func->getFunctionType();
8124 const AttrListPtr &Attrs = Func->getAttributes();
8126 if (!Attrs.isEmpty() && !Func->isVarArg()) {
8127 unsigned InRegCount = 0;
8130 for (FunctionType::param_iterator I = FTy->param_begin(),
8131 E = FTy->param_end(); I != E; ++I, ++Idx)
8132 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
8133 // FIXME: should only count parameters that are lowered to integers.
8134 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
8136 if (InRegCount > 2) {
8137 report_fatal_error("Nest register in use - reduce number of inreg"
8143 case CallingConv::X86_FastCall:
8144 case CallingConv::X86_ThisCall:
8145 case CallingConv::Fast:
8146 // Pass 'nest' parameter in EAX.
8147 // Must be kept in sync with X86CallingConv.td
8152 SDValue OutChains[4];
8155 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8156 DAG.getConstant(10, MVT::i32));
8157 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
8159 // This is storing the opcode for MOV32ri.
8160 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
8161 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
8162 OutChains[0] = DAG.getStore(Root, dl,
8163 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
8164 Trmp, MachinePointerInfo(TrmpAddr),
8167 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8168 DAG.getConstant(1, MVT::i32));
8169 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
8170 MachinePointerInfo(TrmpAddr, 1),
8173 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
8174 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8175 DAG.getConstant(5, MVT::i32));
8176 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
8177 MachinePointerInfo(TrmpAddr, 5),
8180 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8181 DAG.getConstant(6, MVT::i32));
8182 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
8183 MachinePointerInfo(TrmpAddr, 6),
8187 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
8188 return DAG.getMergeValues(Ops, 2, dl);
8192 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
8193 SelectionDAG &DAG) const {
8195 The rounding mode is in bits 11:10 of FPSR, and has the following
8202 FLT_ROUNDS, on the other hand, expects the following:
8209 To perform the conversion, we do:
8210 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
8213 MachineFunction &MF = DAG.getMachineFunction();
8214 const TargetMachine &TM = MF.getTarget();
8215 const TargetFrameInfo &TFI = *TM.getFrameInfo();
8216 unsigned StackAlignment = TFI.getStackAlignment();
8217 EVT VT = Op.getValueType();
8218 DebugLoc DL = Op.getDebugLoc();
8220 // Save FP Control Word to stack slot
8221 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
8222 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8225 MachineMemOperand *MMO =
8226 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8227 MachineMemOperand::MOStore, 2, 2);
8229 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
8230 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
8231 DAG.getVTList(MVT::Other),
8232 Ops, 2, MVT::i16, MMO);
8234 // Load FP Control Word from stack slot
8235 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
8236 MachinePointerInfo(), false, false, 0);
8238 // Transform as necessary
8240 DAG.getNode(ISD::SRL, DL, MVT::i16,
8241 DAG.getNode(ISD::AND, DL, MVT::i16,
8242 CWD, DAG.getConstant(0x800, MVT::i16)),
8243 DAG.getConstant(11, MVT::i8));
8245 DAG.getNode(ISD::SRL, DL, MVT::i16,
8246 DAG.getNode(ISD::AND, DL, MVT::i16,
8247 CWD, DAG.getConstant(0x400, MVT::i16)),
8248 DAG.getConstant(9, MVT::i8));
8251 DAG.getNode(ISD::AND, DL, MVT::i16,
8252 DAG.getNode(ISD::ADD, DL, MVT::i16,
8253 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
8254 DAG.getConstant(1, MVT::i16)),
8255 DAG.getConstant(3, MVT::i16));
8258 return DAG.getNode((VT.getSizeInBits() < 16 ?
8259 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
8262 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
8263 EVT VT = Op.getValueType();
8265 unsigned NumBits = VT.getSizeInBits();
8266 DebugLoc dl = Op.getDebugLoc();
8268 Op = Op.getOperand(0);
8269 if (VT == MVT::i8) {
8270 // Zero extend to i32 since there is not an i8 bsr.
8272 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
8275 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
8276 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
8277 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
8279 // If src is zero (i.e. bsr sets ZF), returns NumBits.
8282 DAG.getConstant(NumBits+NumBits-1, OpVT),
8283 DAG.getConstant(X86::COND_E, MVT::i8),
8286 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
8288 // Finally xor with NumBits-1.
8289 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
8292 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
8296 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
8297 EVT VT = Op.getValueType();
8299 unsigned NumBits = VT.getSizeInBits();
8300 DebugLoc dl = Op.getDebugLoc();
8302 Op = Op.getOperand(0);
8303 if (VT == MVT::i8) {
8305 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
8308 // Issue a bsf (scan bits forward) which also sets EFLAGS.
8309 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
8310 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
8312 // If src is zero (i.e. bsf sets ZF), returns NumBits.
8315 DAG.getConstant(NumBits, OpVT),
8316 DAG.getConstant(X86::COND_E, MVT::i8),
8319 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
8322 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
8326 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const {
8327 EVT VT = Op.getValueType();
8328 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
8329 DebugLoc dl = Op.getDebugLoc();
8331 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
8332 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
8333 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
8334 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
8335 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
8337 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
8338 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
8339 // return AloBlo + AloBhi + AhiBlo;
8341 SDValue A = Op.getOperand(0);
8342 SDValue B = Op.getOperand(1);
8344 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8345 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
8346 A, DAG.getConstant(32, MVT::i32));
8347 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8348 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
8349 B, DAG.getConstant(32, MVT::i32));
8350 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8351 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
8353 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8354 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
8356 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8357 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
8359 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8360 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
8361 AloBhi, DAG.getConstant(32, MVT::i32));
8362 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8363 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
8364 AhiBlo, DAG.getConstant(32, MVT::i32));
8365 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
8366 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
8370 SDValue X86TargetLowering::LowerSHL(SDValue Op, SelectionDAG &DAG) const {
8371 EVT VT = Op.getValueType();
8372 DebugLoc dl = Op.getDebugLoc();
8373 SDValue R = Op.getOperand(0);
8375 LLVMContext *Context = DAG.getContext();
8377 assert(Subtarget->hasSSE41() && "Cannot lower SHL without SSE4.1 or later");
8379 if (VT == MVT::v4i32) {
8380 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8381 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
8382 Op.getOperand(1), DAG.getConstant(23, MVT::i32));
8384 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
8386 std::vector<Constant*> CV(4, CI);
8387 Constant *C = ConstantVector::get(CV);
8388 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8389 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8390 MachinePointerInfo::getConstantPool(),
8393 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
8394 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
8395 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
8396 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
8398 if (VT == MVT::v16i8) {
8400 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8401 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
8402 Op.getOperand(1), DAG.getConstant(5, MVT::i32));
8404 ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15));
8405 ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63));
8407 std::vector<Constant*> CVM1(16, CM1);
8408 std::vector<Constant*> CVM2(16, CM2);
8409 Constant *C = ConstantVector::get(CVM1);
8410 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8411 SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8412 MachinePointerInfo::getConstantPool(),
8415 // r = pblendv(r, psllw(r & (char16)15, 4), a);
8416 M = DAG.getNode(ISD::AND, dl, VT, R, M);
8417 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8418 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
8419 DAG.getConstant(4, MVT::i32));
8420 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op);
8422 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
8424 C = ConstantVector::get(CVM2);
8425 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8426 M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8427 MachinePointerInfo::getConstantPool(),
8430 // r = pblendv(r, psllw(r & (char16)63, 2), a);
8431 M = DAG.getNode(ISD::AND, dl, VT, R, M);
8432 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8433 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
8434 DAG.getConstant(2, MVT::i32));
8435 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op);
8437 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
8439 // return pblendv(r, r+r, a);
8440 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT,
8441 R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op);
8447 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
8448 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
8449 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
8450 // looks for this combo and may remove the "setcc" instruction if the "setcc"
8451 // has only one use.
8452 SDNode *N = Op.getNode();
8453 SDValue LHS = N->getOperand(0);
8454 SDValue RHS = N->getOperand(1);
8455 unsigned BaseOp = 0;
8457 DebugLoc DL = Op.getDebugLoc();
8458 switch (Op.getOpcode()) {
8459 default: llvm_unreachable("Unknown ovf instruction!");
8461 // A subtract of one will be selected as a INC. Note that INC doesn't
8462 // set CF, so we can't do this for UADDO.
8463 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
8464 if (C->getAPIntValue() == 1) {
8465 BaseOp = X86ISD::INC;
8469 BaseOp = X86ISD::ADD;
8473 BaseOp = X86ISD::ADD;
8477 // A subtract of one will be selected as a DEC. Note that DEC doesn't
8478 // set CF, so we can't do this for USUBO.
8479 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
8480 if (C->getAPIntValue() == 1) {
8481 BaseOp = X86ISD::DEC;
8485 BaseOp = X86ISD::SUB;
8489 BaseOp = X86ISD::SUB;
8493 BaseOp = X86ISD::SMUL;
8496 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
8497 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
8499 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
8502 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8503 DAG.getConstant(X86::COND_O, MVT::i32),
8504 SDValue(Sum.getNode(), 2));
8506 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
8511 // Also sets EFLAGS.
8512 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
8513 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
8516 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
8517 DAG.getConstant(Cond, MVT::i32),
8518 SDValue(Sum.getNode(), 1));
8520 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
8524 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
8525 DebugLoc dl = Op.getDebugLoc();
8527 if (!Subtarget->hasSSE2()) {
8528 SDValue Chain = Op.getOperand(0);
8529 SDValue Zero = DAG.getConstant(0,
8530 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
8532 DAG.getRegister(X86::ESP, MVT::i32), // Base
8533 DAG.getTargetConstant(1, MVT::i8), // Scale
8534 DAG.getRegister(0, MVT::i32), // Index
8535 DAG.getTargetConstant(0, MVT::i32), // Disp
8536 DAG.getRegister(0, MVT::i32), // Segment.
8541 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
8542 array_lengthof(Ops));
8543 return SDValue(Res, 0);
8546 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
8548 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
8550 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
8551 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
8552 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
8553 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
8555 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
8556 if (!Op1 && !Op2 && !Op3 && Op4)
8557 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
8559 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
8560 if (Op1 && !Op2 && !Op3 && !Op4)
8561 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
8563 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
8565 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
8568 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
8569 EVT T = Op.getValueType();
8570 DebugLoc DL = Op.getDebugLoc();
8573 switch(T.getSimpleVT().SimpleTy) {
8575 assert(false && "Invalid value type!");
8576 case MVT::i8: Reg = X86::AL; size = 1; break;
8577 case MVT::i16: Reg = X86::AX; size = 2; break;
8578 case MVT::i32: Reg = X86::EAX; size = 4; break;
8580 assert(Subtarget->is64Bit() && "Node not type legal!");
8581 Reg = X86::RAX; size = 8;
8584 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
8585 Op.getOperand(2), SDValue());
8586 SDValue Ops[] = { cpIn.getValue(0),
8589 DAG.getTargetConstant(size, MVT::i8),
8591 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
8592 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
8593 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
8596 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
8600 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
8601 SelectionDAG &DAG) const {
8602 assert(Subtarget->is64Bit() && "Result not type legalized?");
8603 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
8604 SDValue TheChain = Op.getOperand(0);
8605 DebugLoc dl = Op.getDebugLoc();
8606 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
8607 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
8608 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
8610 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
8611 DAG.getConstant(32, MVT::i8));
8613 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
8616 return DAG.getMergeValues(Ops, 2, dl);
8619 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
8620 SelectionDAG &DAG) const {
8621 EVT SrcVT = Op.getOperand(0).getValueType();
8622 EVT DstVT = Op.getValueType();
8623 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
8624 Subtarget->hasMMX() && "Unexpected custom BITCAST");
8625 assert((DstVT == MVT::i64 ||
8626 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
8627 "Unexpected custom BITCAST");
8628 // i64 <=> MMX conversions are Legal.
8629 if (SrcVT==MVT::i64 && DstVT.isVector())
8631 if (DstVT==MVT::i64 && SrcVT.isVector())
8633 // MMX <=> MMX conversions are Legal.
8634 if (SrcVT.isVector() && DstVT.isVector())
8636 // All other conversions need to be expanded.
8640 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
8641 SDNode *Node = Op.getNode();
8642 DebugLoc dl = Node->getDebugLoc();
8643 EVT T = Node->getValueType(0);
8644 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
8645 DAG.getConstant(0, T), Node->getOperand(2));
8646 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
8647 cast<AtomicSDNode>(Node)->getMemoryVT(),
8648 Node->getOperand(0),
8649 Node->getOperand(1), negOp,
8650 cast<AtomicSDNode>(Node)->getSrcValue(),
8651 cast<AtomicSDNode>(Node)->getAlignment());
8654 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
8655 EVT VT = Op.getNode()->getValueType(0);
8657 // Let legalize expand this if it isn't a legal type yet.
8658 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8661 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
8664 bool ExtraOp = false;
8665 switch (Op.getOpcode()) {
8666 default: assert(0 && "Invalid code");
8667 case ISD::ADDC: Opc = X86ISD::ADD; break;
8668 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
8669 case ISD::SUBC: Opc = X86ISD::SUB; break;
8670 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
8674 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
8676 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
8677 Op.getOperand(1), Op.getOperand(2));
8680 /// LowerOperation - Provide custom lowering hooks for some operations.
8682 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
8683 switch (Op.getOpcode()) {
8684 default: llvm_unreachable("Should not custom lower this!");
8685 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
8686 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
8687 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
8688 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
8689 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
8690 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
8691 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
8692 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
8693 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
8694 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
8695 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
8696 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
8697 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
8698 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
8699 case ISD::SHL_PARTS:
8700 case ISD::SRA_PARTS:
8701 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
8702 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
8703 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
8704 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
8705 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
8706 case ISD::FABS: return LowerFABS(Op, DAG);
8707 case ISD::FNEG: return LowerFNEG(Op, DAG);
8708 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
8709 case ISD::SETCC: return LowerSETCC(Op, DAG);
8710 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
8711 case ISD::SELECT: return LowerSELECT(Op, DAG);
8712 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
8713 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
8714 case ISD::VASTART: return LowerVASTART(Op, DAG);
8715 case ISD::VAARG: return LowerVAARG(Op, DAG);
8716 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
8717 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
8718 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
8719 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
8720 case ISD::FRAME_TO_ARGS_OFFSET:
8721 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
8722 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
8723 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
8724 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
8725 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
8726 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
8727 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
8728 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
8729 case ISD::SHL: return LowerSHL(Op, DAG);
8735 case ISD::UMULO: return LowerXALUO(Op, DAG);
8736 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
8737 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
8741 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
8745 void X86TargetLowering::
8746 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
8747 SelectionDAG &DAG, unsigned NewOp) const {
8748 EVT T = Node->getValueType(0);
8749 DebugLoc dl = Node->getDebugLoc();
8750 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
8752 SDValue Chain = Node->getOperand(0);
8753 SDValue In1 = Node->getOperand(1);
8754 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
8755 Node->getOperand(2), DAG.getIntPtrConstant(0));
8756 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
8757 Node->getOperand(2), DAG.getIntPtrConstant(1));
8758 SDValue Ops[] = { Chain, In1, In2L, In2H };
8759 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
8761 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
8762 cast<MemSDNode>(Node)->getMemOperand());
8763 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
8764 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
8765 Results.push_back(Result.getValue(2));
8768 /// ReplaceNodeResults - Replace a node with an illegal result type
8769 /// with a new node built out of custom code.
8770 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
8771 SmallVectorImpl<SDValue>&Results,
8772 SelectionDAG &DAG) const {
8773 DebugLoc dl = N->getDebugLoc();
8774 switch (N->getOpcode()) {
8776 assert(false && "Do not know how to custom type legalize this operation!");
8782 // We don't want to expand or promote these.
8784 case ISD::FP_TO_SINT: {
8785 std::pair<SDValue,SDValue> Vals =
8786 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
8787 SDValue FIST = Vals.first, StackSlot = Vals.second;
8788 if (FIST.getNode() != 0) {
8789 EVT VT = N->getValueType(0);
8790 // Return a load from the stack slot.
8791 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
8792 MachinePointerInfo(), false, false, 0));
8796 case ISD::READCYCLECOUNTER: {
8797 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
8798 SDValue TheChain = N->getOperand(0);
8799 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
8800 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
8802 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
8804 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
8805 SDValue Ops[] = { eax, edx };
8806 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
8807 Results.push_back(edx.getValue(1));
8810 case ISD::ATOMIC_CMP_SWAP: {
8811 EVT T = N->getValueType(0);
8812 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
8813 SDValue cpInL, cpInH;
8814 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
8815 DAG.getConstant(0, MVT::i32));
8816 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
8817 DAG.getConstant(1, MVT::i32));
8818 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
8819 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
8821 SDValue swapInL, swapInH;
8822 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
8823 DAG.getConstant(0, MVT::i32));
8824 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
8825 DAG.getConstant(1, MVT::i32));
8826 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
8828 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
8829 swapInL.getValue(1));
8830 SDValue Ops[] = { swapInH.getValue(0),
8832 swapInH.getValue(1) };
8833 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
8834 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
8835 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG8_DAG, dl, Tys,
8837 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
8838 MVT::i32, Result.getValue(1));
8839 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
8840 MVT::i32, cpOutL.getValue(2));
8841 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
8842 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
8843 Results.push_back(cpOutH.getValue(1));
8846 case ISD::ATOMIC_LOAD_ADD:
8847 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
8849 case ISD::ATOMIC_LOAD_AND:
8850 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
8852 case ISD::ATOMIC_LOAD_NAND:
8853 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
8855 case ISD::ATOMIC_LOAD_OR:
8856 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
8858 case ISD::ATOMIC_LOAD_SUB:
8859 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
8861 case ISD::ATOMIC_LOAD_XOR:
8862 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
8864 case ISD::ATOMIC_SWAP:
8865 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
8870 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
8872 default: return NULL;
8873 case X86ISD::BSF: return "X86ISD::BSF";
8874 case X86ISD::BSR: return "X86ISD::BSR";
8875 case X86ISD::SHLD: return "X86ISD::SHLD";
8876 case X86ISD::SHRD: return "X86ISD::SHRD";
8877 case X86ISD::FAND: return "X86ISD::FAND";
8878 case X86ISD::FOR: return "X86ISD::FOR";
8879 case X86ISD::FXOR: return "X86ISD::FXOR";
8880 case X86ISD::FSRL: return "X86ISD::FSRL";
8881 case X86ISD::FILD: return "X86ISD::FILD";
8882 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
8883 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
8884 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
8885 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
8886 case X86ISD::FLD: return "X86ISD::FLD";
8887 case X86ISD::FST: return "X86ISD::FST";
8888 case X86ISD::CALL: return "X86ISD::CALL";
8889 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
8890 case X86ISD::BT: return "X86ISD::BT";
8891 case X86ISD::CMP: return "X86ISD::CMP";
8892 case X86ISD::COMI: return "X86ISD::COMI";
8893 case X86ISD::UCOMI: return "X86ISD::UCOMI";
8894 case X86ISD::SETCC: return "X86ISD::SETCC";
8895 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
8896 case X86ISD::CMOV: return "X86ISD::CMOV";
8897 case X86ISD::BRCOND: return "X86ISD::BRCOND";
8898 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
8899 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
8900 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
8901 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
8902 case X86ISD::Wrapper: return "X86ISD::Wrapper";
8903 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
8904 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
8905 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
8906 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
8907 case X86ISD::PINSRB: return "X86ISD::PINSRB";
8908 case X86ISD::PINSRW: return "X86ISD::PINSRW";
8909 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
8910 case X86ISD::PANDN: return "X86ISD::PANDN";
8911 case X86ISD::PSIGNB: return "X86ISD::PSIGNB";
8912 case X86ISD::PSIGNW: return "X86ISD::PSIGNW";
8913 case X86ISD::PSIGND: return "X86ISD::PSIGND";
8914 case X86ISD::PBLENDVB: return "X86ISD::PBLENDVB";
8915 case X86ISD::FMAX: return "X86ISD::FMAX";
8916 case X86ISD::FMIN: return "X86ISD::FMIN";
8917 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
8918 case X86ISD::FRCP: return "X86ISD::FRCP";
8919 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
8920 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
8921 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
8922 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
8923 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
8924 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
8925 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
8926 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
8927 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
8928 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
8929 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
8930 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
8931 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
8932 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
8933 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
8934 case X86ISD::VSHL: return "X86ISD::VSHL";
8935 case X86ISD::VSRL: return "X86ISD::VSRL";
8936 case X86ISD::CMPPD: return "X86ISD::CMPPD";
8937 case X86ISD::CMPPS: return "X86ISD::CMPPS";
8938 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
8939 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
8940 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
8941 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
8942 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
8943 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
8944 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
8945 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
8946 case X86ISD::ADD: return "X86ISD::ADD";
8947 case X86ISD::SUB: return "X86ISD::SUB";
8948 case X86ISD::ADC: return "X86ISD::ADC";
8949 case X86ISD::SBB: return "X86ISD::SBB";
8950 case X86ISD::SMUL: return "X86ISD::SMUL";
8951 case X86ISD::UMUL: return "X86ISD::UMUL";
8952 case X86ISD::INC: return "X86ISD::INC";
8953 case X86ISD::DEC: return "X86ISD::DEC";
8954 case X86ISD::OR: return "X86ISD::OR";
8955 case X86ISD::XOR: return "X86ISD::XOR";
8956 case X86ISD::AND: return "X86ISD::AND";
8957 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
8958 case X86ISD::PTEST: return "X86ISD::PTEST";
8959 case X86ISD::TESTP: return "X86ISD::TESTP";
8960 case X86ISD::PALIGN: return "X86ISD::PALIGN";
8961 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
8962 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
8963 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD";
8964 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
8965 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD";
8966 case X86ISD::SHUFPS: return "X86ISD::SHUFPS";
8967 case X86ISD::SHUFPD: return "X86ISD::SHUFPD";
8968 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
8969 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
8970 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
8971 case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD";
8972 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
8973 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
8974 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
8975 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
8976 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
8977 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD";
8978 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD";
8979 case X86ISD::MOVSD: return "X86ISD::MOVSD";
8980 case X86ISD::MOVSS: return "X86ISD::MOVSS";
8981 case X86ISD::UNPCKLPS: return "X86ISD::UNPCKLPS";
8982 case X86ISD::UNPCKLPD: return "X86ISD::UNPCKLPD";
8983 case X86ISD::UNPCKHPS: return "X86ISD::UNPCKHPS";
8984 case X86ISD::UNPCKHPD: return "X86ISD::UNPCKHPD";
8985 case X86ISD::PUNPCKLBW: return "X86ISD::PUNPCKLBW";
8986 case X86ISD::PUNPCKLWD: return "X86ISD::PUNPCKLWD";
8987 case X86ISD::PUNPCKLDQ: return "X86ISD::PUNPCKLDQ";
8988 case X86ISD::PUNPCKLQDQ: return "X86ISD::PUNPCKLQDQ";
8989 case X86ISD::PUNPCKHBW: return "X86ISD::PUNPCKHBW";
8990 case X86ISD::PUNPCKHWD: return "X86ISD::PUNPCKHWD";
8991 case X86ISD::PUNPCKHDQ: return "X86ISD::PUNPCKHDQ";
8992 case X86ISD::PUNPCKHQDQ: return "X86ISD::PUNPCKHQDQ";
8993 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
8994 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
8995 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
8999 // isLegalAddressingMode - Return true if the addressing mode represented
9000 // by AM is legal for this target, for a load/store of the specified type.
9001 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
9002 const Type *Ty) const {
9003 // X86 supports extremely general addressing modes.
9004 CodeModel::Model M = getTargetMachine().getCodeModel();
9005 Reloc::Model R = getTargetMachine().getRelocationModel();
9007 // X86 allows a sign-extended 32-bit immediate field as a displacement.
9008 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
9013 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
9015 // If a reference to this global requires an extra load, we can't fold it.
9016 if (isGlobalStubReference(GVFlags))
9019 // If BaseGV requires a register for the PIC base, we cannot also have a
9020 // BaseReg specified.
9021 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
9024 // If lower 4G is not available, then we must use rip-relative addressing.
9025 if ((M != CodeModel::Small || R != Reloc::Static) &&
9026 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
9036 // These scales always work.
9041 // These scales are formed with basereg+scalereg. Only accept if there is
9046 default: // Other stuff never works.
9054 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
9055 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
9057 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
9058 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
9059 if (NumBits1 <= NumBits2)
9064 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
9065 if (!VT1.isInteger() || !VT2.isInteger())
9067 unsigned NumBits1 = VT1.getSizeInBits();
9068 unsigned NumBits2 = VT2.getSizeInBits();
9069 if (NumBits1 <= NumBits2)
9074 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
9075 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
9076 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
9079 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
9080 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
9081 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
9084 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
9085 // i16 instructions are longer (0x66 prefix) and potentially slower.
9086 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
9089 /// isShuffleMaskLegal - Targets can use this to indicate that they only
9090 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
9091 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
9092 /// are assumed to be legal.
9094 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
9096 // Very little shuffling can be done for 64-bit vectors right now.
9097 if (VT.getSizeInBits() == 64)
9098 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3());
9100 // FIXME: pshufb, blends, shifts.
9101 return (VT.getVectorNumElements() == 2 ||
9102 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
9103 isMOVLMask(M, VT) ||
9104 isSHUFPMask(M, VT) ||
9105 isPSHUFDMask(M, VT) ||
9106 isPSHUFHWMask(M, VT) ||
9107 isPSHUFLWMask(M, VT) ||
9108 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
9109 isUNPCKLMask(M, VT) ||
9110 isUNPCKHMask(M, VT) ||
9111 isUNPCKL_v_undef_Mask(M, VT) ||
9112 isUNPCKH_v_undef_Mask(M, VT));
9116 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
9118 unsigned NumElts = VT.getVectorNumElements();
9119 // FIXME: This collection of masks seems suspect.
9122 if (NumElts == 4 && VT.getSizeInBits() == 128) {
9123 return (isMOVLMask(Mask, VT) ||
9124 isCommutedMOVLMask(Mask, VT, true) ||
9125 isSHUFPMask(Mask, VT) ||
9126 isCommutedSHUFPMask(Mask, VT));
9131 //===----------------------------------------------------------------------===//
9132 // X86 Scheduler Hooks
9133 //===----------------------------------------------------------------------===//
9135 // private utility function
9137 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
9138 MachineBasicBlock *MBB,
9145 TargetRegisterClass *RC,
9146 bool invSrc) const {
9147 // For the atomic bitwise operator, we generate
9150 // ld t1 = [bitinstr.addr]
9151 // op t2 = t1, [bitinstr.val]
9153 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
9155 // fallthrough -->nextMBB
9156 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9157 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9158 MachineFunction::iterator MBBIter = MBB;
9161 /// First build the CFG
9162 MachineFunction *F = MBB->getParent();
9163 MachineBasicBlock *thisMBB = MBB;
9164 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
9165 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
9166 F->insert(MBBIter, newMBB);
9167 F->insert(MBBIter, nextMBB);
9169 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
9170 nextMBB->splice(nextMBB->begin(), thisMBB,
9171 llvm::next(MachineBasicBlock::iterator(bInstr)),
9173 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
9175 // Update thisMBB to fall through to newMBB
9176 thisMBB->addSuccessor(newMBB);
9178 // newMBB jumps to itself and fall through to nextMBB
9179 newMBB->addSuccessor(nextMBB);
9180 newMBB->addSuccessor(newMBB);
9182 // Insert instructions into newMBB based on incoming instruction
9183 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
9184 "unexpected number of operands");
9185 DebugLoc dl = bInstr->getDebugLoc();
9186 MachineOperand& destOper = bInstr->getOperand(0);
9187 MachineOperand* argOpers[2 + X86::AddrNumOperands];
9188 int numArgs = bInstr->getNumOperands() - 1;
9189 for (int i=0; i < numArgs; ++i)
9190 argOpers[i] = &bInstr->getOperand(i+1);
9192 // x86 address has 4 operands: base, index, scale, and displacement
9193 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
9194 int valArgIndx = lastAddrIndx + 1;
9196 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
9197 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
9198 for (int i=0; i <= lastAddrIndx; ++i)
9199 (*MIB).addOperand(*argOpers[i]);
9201 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
9203 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
9208 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
9209 assert((argOpers[valArgIndx]->isReg() ||
9210 argOpers[valArgIndx]->isImm()) &&
9212 if (argOpers[valArgIndx]->isReg())
9213 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
9215 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
9217 (*MIB).addOperand(*argOpers[valArgIndx]);
9219 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
9222 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
9223 for (int i=0; i <= lastAddrIndx; ++i)
9224 (*MIB).addOperand(*argOpers[i]);
9226 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
9227 (*MIB).setMemRefs(bInstr->memoperands_begin(),
9228 bInstr->memoperands_end());
9230 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
9234 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
9236 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
9240 // private utility function: 64 bit atomics on 32 bit host.
9242 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
9243 MachineBasicBlock *MBB,
9248 bool invSrc) const {
9249 // For the atomic bitwise operator, we generate
9250 // thisMBB (instructions are in pairs, except cmpxchg8b)
9251 // ld t1,t2 = [bitinstr.addr]
9253 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
9254 // op t5, t6 <- out1, out2, [bitinstr.val]
9255 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
9256 // mov ECX, EBX <- t5, t6
9257 // mov EAX, EDX <- t1, t2
9258 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
9259 // mov t3, t4 <- EAX, EDX
9261 // result in out1, out2
9262 // fallthrough -->nextMBB
9264 const TargetRegisterClass *RC = X86::GR32RegisterClass;
9265 const unsigned LoadOpc = X86::MOV32rm;
9266 const unsigned NotOpc = X86::NOT32r;
9267 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9268 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9269 MachineFunction::iterator MBBIter = MBB;
9272 /// First build the CFG
9273 MachineFunction *F = MBB->getParent();
9274 MachineBasicBlock *thisMBB = MBB;
9275 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
9276 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
9277 F->insert(MBBIter, newMBB);
9278 F->insert(MBBIter, nextMBB);
9280 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
9281 nextMBB->splice(nextMBB->begin(), thisMBB,
9282 llvm::next(MachineBasicBlock::iterator(bInstr)),
9284 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
9286 // Update thisMBB to fall through to newMBB
9287 thisMBB->addSuccessor(newMBB);
9289 // newMBB jumps to itself and fall through to nextMBB
9290 newMBB->addSuccessor(nextMBB);
9291 newMBB->addSuccessor(newMBB);
9293 DebugLoc dl = bInstr->getDebugLoc();
9294 // Insert instructions into newMBB based on incoming instruction
9295 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
9296 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
9297 "unexpected number of operands");
9298 MachineOperand& dest1Oper = bInstr->getOperand(0);
9299 MachineOperand& dest2Oper = bInstr->getOperand(1);
9300 MachineOperand* argOpers[2 + X86::AddrNumOperands];
9301 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
9302 argOpers[i] = &bInstr->getOperand(i+2);
9304 // We use some of the operands multiple times, so conservatively just
9305 // clear any kill flags that might be present.
9306 if (argOpers[i]->isReg() && argOpers[i]->isUse())
9307 argOpers[i]->setIsKill(false);
9310 // x86 address has 5 operands: base, index, scale, displacement, and segment.
9311 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
9313 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
9314 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
9315 for (int i=0; i <= lastAddrIndx; ++i)
9316 (*MIB).addOperand(*argOpers[i]);
9317 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
9318 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
9319 // add 4 to displacement.
9320 for (int i=0; i <= lastAddrIndx-2; ++i)
9321 (*MIB).addOperand(*argOpers[i]);
9322 MachineOperand newOp3 = *(argOpers[3]);
9324 newOp3.setImm(newOp3.getImm()+4);
9326 newOp3.setOffset(newOp3.getOffset()+4);
9327 (*MIB).addOperand(newOp3);
9328 (*MIB).addOperand(*argOpers[lastAddrIndx]);
9330 // t3/4 are defined later, at the bottom of the loop
9331 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
9332 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
9333 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
9334 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
9335 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
9336 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
9338 // The subsequent operations should be using the destination registers of
9339 //the PHI instructions.
9341 t1 = F->getRegInfo().createVirtualRegister(RC);
9342 t2 = F->getRegInfo().createVirtualRegister(RC);
9343 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
9344 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
9346 t1 = dest1Oper.getReg();
9347 t2 = dest2Oper.getReg();
9350 int valArgIndx = lastAddrIndx + 1;
9351 assert((argOpers[valArgIndx]->isReg() ||
9352 argOpers[valArgIndx]->isImm()) &&
9354 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
9355 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
9356 if (argOpers[valArgIndx]->isReg())
9357 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
9359 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
9360 if (regOpcL != X86::MOV32rr)
9362 (*MIB).addOperand(*argOpers[valArgIndx]);
9363 assert(argOpers[valArgIndx + 1]->isReg() ==
9364 argOpers[valArgIndx]->isReg());
9365 assert(argOpers[valArgIndx + 1]->isImm() ==
9366 argOpers[valArgIndx]->isImm());
9367 if (argOpers[valArgIndx + 1]->isReg())
9368 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
9370 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
9371 if (regOpcH != X86::MOV32rr)
9373 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
9375 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
9377 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
9380 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
9382 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
9385 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
9386 for (int i=0; i <= lastAddrIndx; ++i)
9387 (*MIB).addOperand(*argOpers[i]);
9389 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
9390 (*MIB).setMemRefs(bInstr->memoperands_begin(),
9391 bInstr->memoperands_end());
9393 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
9394 MIB.addReg(X86::EAX);
9395 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
9396 MIB.addReg(X86::EDX);
9399 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
9401 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
9405 // private utility function
9407 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
9408 MachineBasicBlock *MBB,
9409 unsigned cmovOpc) const {
9410 // For the atomic min/max operator, we generate
9413 // ld t1 = [min/max.addr]
9414 // mov t2 = [min/max.val]
9416 // cmov[cond] t2 = t1
9418 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
9420 // fallthrough -->nextMBB
9422 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9423 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9424 MachineFunction::iterator MBBIter = MBB;
9427 /// First build the CFG
9428 MachineFunction *F = MBB->getParent();
9429 MachineBasicBlock *thisMBB = MBB;
9430 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
9431 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
9432 F->insert(MBBIter, newMBB);
9433 F->insert(MBBIter, nextMBB);
9435 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
9436 nextMBB->splice(nextMBB->begin(), thisMBB,
9437 llvm::next(MachineBasicBlock::iterator(mInstr)),
9439 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
9441 // Update thisMBB to fall through to newMBB
9442 thisMBB->addSuccessor(newMBB);
9444 // newMBB jumps to newMBB and fall through to nextMBB
9445 newMBB->addSuccessor(nextMBB);
9446 newMBB->addSuccessor(newMBB);
9448 DebugLoc dl = mInstr->getDebugLoc();
9449 // Insert instructions into newMBB based on incoming instruction
9450 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
9451 "unexpected number of operands");
9452 MachineOperand& destOper = mInstr->getOperand(0);
9453 MachineOperand* argOpers[2 + X86::AddrNumOperands];
9454 int numArgs = mInstr->getNumOperands() - 1;
9455 for (int i=0; i < numArgs; ++i)
9456 argOpers[i] = &mInstr->getOperand(i+1);
9458 // x86 address has 4 operands: base, index, scale, and displacement
9459 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
9460 int valArgIndx = lastAddrIndx + 1;
9462 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
9463 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
9464 for (int i=0; i <= lastAddrIndx; ++i)
9465 (*MIB).addOperand(*argOpers[i]);
9467 // We only support register and immediate values
9468 assert((argOpers[valArgIndx]->isReg() ||
9469 argOpers[valArgIndx]->isImm()) &&
9472 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
9473 if (argOpers[valArgIndx]->isReg())
9474 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
9476 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
9477 (*MIB).addOperand(*argOpers[valArgIndx]);
9479 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
9482 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
9487 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
9488 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
9492 // Cmp and exchange if none has modified the memory location
9493 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
9494 for (int i=0; i <= lastAddrIndx; ++i)
9495 (*MIB).addOperand(*argOpers[i]);
9497 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
9498 (*MIB).setMemRefs(mInstr->memoperands_begin(),
9499 mInstr->memoperands_end());
9501 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
9502 MIB.addReg(X86::EAX);
9505 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
9507 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
9511 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
9512 // or XMM0_V32I8 in AVX all of this code can be replaced with that
9515 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
9516 unsigned numArgs, bool memArg) const {
9517 assert((Subtarget->hasSSE42() || Subtarget->hasAVX()) &&
9518 "Target must have SSE4.2 or AVX features enabled");
9520 DebugLoc dl = MI->getDebugLoc();
9521 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9523 if (!Subtarget->hasAVX()) {
9525 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
9527 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
9530 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
9532 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
9535 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
9536 for (unsigned i = 0; i < numArgs; ++i) {
9537 MachineOperand &Op = MI->getOperand(i+1);
9538 if (!(Op.isReg() && Op.isImplicit()))
9541 BuildMI(*BB, MI, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
9544 MI->eraseFromParent();
9549 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
9550 DebugLoc dl = MI->getDebugLoc();
9551 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9553 // Address into RAX/EAX, other two args into ECX, EDX.
9554 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
9555 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
9556 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
9557 for (int i = 0; i < X86::AddrNumOperands; ++i)
9558 MIB.addOperand(MI->getOperand(i));
9560 unsigned ValOps = X86::AddrNumOperands;
9561 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
9562 .addReg(MI->getOperand(ValOps).getReg());
9563 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
9564 .addReg(MI->getOperand(ValOps+1).getReg());
9566 // The instruction doesn't actually take any operands though.
9567 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
9569 MI->eraseFromParent(); // The pseudo is gone now.
9574 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
9575 DebugLoc dl = MI->getDebugLoc();
9576 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9578 // First arg in ECX, the second in EAX.
9579 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
9580 .addReg(MI->getOperand(0).getReg());
9581 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
9582 .addReg(MI->getOperand(1).getReg());
9584 // The instruction doesn't actually take any operands though.
9585 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
9587 MI->eraseFromParent(); // The pseudo is gone now.
9592 X86TargetLowering::EmitVAARG64WithCustomInserter(
9594 MachineBasicBlock *MBB) const {
9595 // Emit va_arg instruction on X86-64.
9597 // Operands to this pseudo-instruction:
9598 // 0 ) Output : destination address (reg)
9599 // 1-5) Input : va_list address (addr, i64mem)
9600 // 6 ) ArgSize : Size (in bytes) of vararg type
9601 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
9602 // 8 ) Align : Alignment of type
9603 // 9 ) EFLAGS (implicit-def)
9605 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
9606 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
9608 unsigned DestReg = MI->getOperand(0).getReg();
9609 MachineOperand &Base = MI->getOperand(1);
9610 MachineOperand &Scale = MI->getOperand(2);
9611 MachineOperand &Index = MI->getOperand(3);
9612 MachineOperand &Disp = MI->getOperand(4);
9613 MachineOperand &Segment = MI->getOperand(5);
9614 unsigned ArgSize = MI->getOperand(6).getImm();
9615 unsigned ArgMode = MI->getOperand(7).getImm();
9616 unsigned Align = MI->getOperand(8).getImm();
9619 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
9620 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
9621 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
9623 // Machine Information
9624 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9625 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
9626 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
9627 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
9628 DebugLoc DL = MI->getDebugLoc();
9633 // i64 overflow_area (address)
9634 // i64 reg_save_area (address)
9636 // sizeof(va_list) = 24
9637 // alignment(va_list) = 8
9639 unsigned TotalNumIntRegs = 6;
9640 unsigned TotalNumXMMRegs = 8;
9641 bool UseGPOffset = (ArgMode == 1);
9642 bool UseFPOffset = (ArgMode == 2);
9643 unsigned MaxOffset = TotalNumIntRegs * 8 +
9644 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
9646 /* Align ArgSize to a multiple of 8 */
9647 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
9648 bool NeedsAlign = (Align > 8);
9650 MachineBasicBlock *thisMBB = MBB;
9651 MachineBasicBlock *overflowMBB;
9652 MachineBasicBlock *offsetMBB;
9653 MachineBasicBlock *endMBB;
9655 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
9656 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
9657 unsigned OffsetReg = 0;
9659 if (!UseGPOffset && !UseFPOffset) {
9660 // If we only pull from the overflow region, we don't create a branch.
9661 // We don't need to alter control flow.
9662 OffsetDestReg = 0; // unused
9663 OverflowDestReg = DestReg;
9666 overflowMBB = thisMBB;
9669 // First emit code to check if gp_offset (or fp_offset) is below the bound.
9670 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
9671 // If not, pull from overflow_area. (branch to overflowMBB)
9676 // offsetMBB overflowMBB
9681 // Registers for the PHI in endMBB
9682 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
9683 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
9685 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9686 MachineFunction *MF = MBB->getParent();
9687 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
9688 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
9689 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
9691 MachineFunction::iterator MBBIter = MBB;
9694 // Insert the new basic blocks
9695 MF->insert(MBBIter, offsetMBB);
9696 MF->insert(MBBIter, overflowMBB);
9697 MF->insert(MBBIter, endMBB);
9699 // Transfer the remainder of MBB and its successor edges to endMBB.
9700 endMBB->splice(endMBB->begin(), thisMBB,
9701 llvm::next(MachineBasicBlock::iterator(MI)),
9703 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
9705 // Make offsetMBB and overflowMBB successors of thisMBB
9706 thisMBB->addSuccessor(offsetMBB);
9707 thisMBB->addSuccessor(overflowMBB);
9709 // endMBB is a successor of both offsetMBB and overflowMBB
9710 offsetMBB->addSuccessor(endMBB);
9711 overflowMBB->addSuccessor(endMBB);
9713 // Load the offset value into a register
9714 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
9715 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
9719 .addDisp(Disp, UseFPOffset ? 4 : 0)
9720 .addOperand(Segment)
9721 .setMemRefs(MMOBegin, MMOEnd);
9723 // Check if there is enough room left to pull this argument.
9724 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
9726 .addImm(MaxOffset + 8 - ArgSizeA8);
9728 // Branch to "overflowMBB" if offset >= max
9729 // Fall through to "offsetMBB" otherwise
9730 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
9731 .addMBB(overflowMBB);
9734 // In offsetMBB, emit code to use the reg_save_area.
9736 assert(OffsetReg != 0);
9738 // Read the reg_save_area address.
9739 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
9740 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
9745 .addOperand(Segment)
9746 .setMemRefs(MMOBegin, MMOEnd);
9748 // Zero-extend the offset
9749 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
9750 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
9753 .addImm(X86::sub_32bit);
9755 // Add the offset to the reg_save_area to get the final address.
9756 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
9757 .addReg(OffsetReg64)
9758 .addReg(RegSaveReg);
9760 // Compute the offset for the next argument
9761 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
9762 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
9764 .addImm(UseFPOffset ? 16 : 8);
9766 // Store it back into the va_list.
9767 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
9771 .addDisp(Disp, UseFPOffset ? 4 : 0)
9772 .addOperand(Segment)
9773 .addReg(NextOffsetReg)
9774 .setMemRefs(MMOBegin, MMOEnd);
9777 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
9782 // Emit code to use overflow area
9785 // Load the overflow_area address into a register.
9786 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
9787 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
9792 .addOperand(Segment)
9793 .setMemRefs(MMOBegin, MMOEnd);
9795 // If we need to align it, do so. Otherwise, just copy the address
9796 // to OverflowDestReg.
9798 // Align the overflow address
9799 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
9800 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
9802 // aligned_addr = (addr + (align-1)) & ~(align-1)
9803 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
9804 .addReg(OverflowAddrReg)
9807 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
9809 .addImm(~(uint64_t)(Align-1));
9811 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
9812 .addReg(OverflowAddrReg);
9815 // Compute the next overflow address after this argument.
9816 // (the overflow address should be kept 8-byte aligned)
9817 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
9818 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
9819 .addReg(OverflowDestReg)
9822 // Store the new overflow address.
9823 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
9828 .addOperand(Segment)
9829 .addReg(NextAddrReg)
9830 .setMemRefs(MMOBegin, MMOEnd);
9832 // If we branched, emit the PHI to the front of endMBB.
9834 BuildMI(*endMBB, endMBB->begin(), DL,
9835 TII->get(X86::PHI), DestReg)
9836 .addReg(OffsetDestReg).addMBB(offsetMBB)
9837 .addReg(OverflowDestReg).addMBB(overflowMBB);
9840 // Erase the pseudo instruction
9841 MI->eraseFromParent();
9847 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
9849 MachineBasicBlock *MBB) const {
9850 // Emit code to save XMM registers to the stack. The ABI says that the
9851 // number of registers to save is given in %al, so it's theoretically
9852 // possible to do an indirect jump trick to avoid saving all of them,
9853 // however this code takes a simpler approach and just executes all
9854 // of the stores if %al is non-zero. It's less code, and it's probably
9855 // easier on the hardware branch predictor, and stores aren't all that
9856 // expensive anyway.
9858 // Create the new basic blocks. One block contains all the XMM stores,
9859 // and one block is the final destination regardless of whether any
9860 // stores were performed.
9861 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9862 MachineFunction *F = MBB->getParent();
9863 MachineFunction::iterator MBBIter = MBB;
9865 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
9866 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
9867 F->insert(MBBIter, XMMSaveMBB);
9868 F->insert(MBBIter, EndMBB);
9870 // Transfer the remainder of MBB and its successor edges to EndMBB.
9871 EndMBB->splice(EndMBB->begin(), MBB,
9872 llvm::next(MachineBasicBlock::iterator(MI)),
9874 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
9876 // The original block will now fall through to the XMM save block.
9877 MBB->addSuccessor(XMMSaveMBB);
9878 // The XMMSaveMBB will fall through to the end block.
9879 XMMSaveMBB->addSuccessor(EndMBB);
9881 // Now add the instructions.
9882 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9883 DebugLoc DL = MI->getDebugLoc();
9885 unsigned CountReg = MI->getOperand(0).getReg();
9886 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
9887 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
9889 if (!Subtarget->isTargetWin64()) {
9890 // If %al is 0, branch around the XMM save block.
9891 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
9892 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
9893 MBB->addSuccessor(EndMBB);
9896 // In the XMM save block, save all the XMM argument registers.
9897 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
9898 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
9899 MachineMemOperand *MMO =
9900 F->getMachineMemOperand(
9901 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
9902 MachineMemOperand::MOStore,
9903 /*Size=*/16, /*Align=*/16);
9904 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
9905 .addFrameIndex(RegSaveFrameIndex)
9906 .addImm(/*Scale=*/1)
9907 .addReg(/*IndexReg=*/0)
9908 .addImm(/*Disp=*/Offset)
9909 .addReg(/*Segment=*/0)
9910 .addReg(MI->getOperand(i).getReg())
9911 .addMemOperand(MMO);
9914 MI->eraseFromParent(); // The pseudo instruction is gone now.
9920 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
9921 MachineBasicBlock *BB) const {
9922 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9923 DebugLoc DL = MI->getDebugLoc();
9925 // To "insert" a SELECT_CC instruction, we actually have to insert the
9926 // diamond control-flow pattern. The incoming instruction knows the
9927 // destination vreg to set, the condition code register to branch on, the
9928 // true/false values to select between, and a branch opcode to use.
9929 const BasicBlock *LLVM_BB = BB->getBasicBlock();
9930 MachineFunction::iterator It = BB;
9936 // cmpTY ccX, r1, r2
9938 // fallthrough --> copy0MBB
9939 MachineBasicBlock *thisMBB = BB;
9940 MachineFunction *F = BB->getParent();
9941 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
9942 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
9943 F->insert(It, copy0MBB);
9944 F->insert(It, sinkMBB);
9946 // If the EFLAGS register isn't dead in the terminator, then claim that it's
9947 // live into the sink and copy blocks.
9948 const MachineFunction *MF = BB->getParent();
9949 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
9950 BitVector ReservedRegs = TRI->getReservedRegs(*MF);
9952 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
9953 const MachineOperand &MO = MI->getOperand(I);
9954 if (!MO.isReg() || !MO.isUse() || MO.isKill()) continue;
9955 unsigned Reg = MO.getReg();
9956 if (Reg != X86::EFLAGS) continue;
9957 copy0MBB->addLiveIn(Reg);
9958 sinkMBB->addLiveIn(Reg);
9961 // Transfer the remainder of BB and its successor edges to sinkMBB.
9962 sinkMBB->splice(sinkMBB->begin(), BB,
9963 llvm::next(MachineBasicBlock::iterator(MI)),
9965 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
9967 // Add the true and fallthrough blocks as its successors.
9968 BB->addSuccessor(copy0MBB);
9969 BB->addSuccessor(sinkMBB);
9971 // Create the conditional branch instruction.
9973 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
9974 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
9977 // %FalseValue = ...
9978 // # fallthrough to sinkMBB
9979 copy0MBB->addSuccessor(sinkMBB);
9982 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
9984 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
9985 TII->get(X86::PHI), MI->getOperand(0).getReg())
9986 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
9987 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
9989 MI->eraseFromParent(); // The pseudo instruction is gone now.
9994 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
9995 MachineBasicBlock *BB) const {
9996 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9997 DebugLoc DL = MI->getDebugLoc();
9999 // The lowering is pretty easy: we're just emitting the call to _alloca. The
10000 // non-trivial part is impdef of ESP.
10001 // FIXME: The code should be tweaked as soon as we'll try to do codegen for
10004 const char *StackProbeSymbol =
10005 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
10007 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
10008 .addExternalSymbol(StackProbeSymbol)
10009 .addReg(X86::EAX, RegState::Implicit)
10010 .addReg(X86::ESP, RegState::Implicit)
10011 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
10012 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
10013 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
10015 MI->eraseFromParent(); // The pseudo instruction is gone now.
10019 MachineBasicBlock *
10020 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
10021 MachineBasicBlock *BB) const {
10022 // This is pretty easy. We're taking the value that we received from
10023 // our load from the relocation, sticking it in either RDI (x86-64)
10024 // or EAX and doing an indirect call. The return value will then
10025 // be in the normal return register.
10026 const X86InstrInfo *TII
10027 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
10028 DebugLoc DL = MI->getDebugLoc();
10029 MachineFunction *F = BB->getParent();
10031 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
10032 assert(MI->getOperand(3).isGlobal() && "This should be a global");
10034 if (Subtarget->is64Bit()) {
10035 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
10036 TII->get(X86::MOV64rm), X86::RDI)
10038 .addImm(0).addReg(0)
10039 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
10040 MI->getOperand(3).getTargetFlags())
10042 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
10043 addDirectMem(MIB, X86::RDI);
10044 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
10045 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
10046 TII->get(X86::MOV32rm), X86::EAX)
10048 .addImm(0).addReg(0)
10049 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
10050 MI->getOperand(3).getTargetFlags())
10052 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
10053 addDirectMem(MIB, X86::EAX);
10055 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
10056 TII->get(X86::MOV32rm), X86::EAX)
10057 .addReg(TII->getGlobalBaseReg(F))
10058 .addImm(0).addReg(0)
10059 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
10060 MI->getOperand(3).getTargetFlags())
10062 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
10063 addDirectMem(MIB, X86::EAX);
10066 MI->eraseFromParent(); // The pseudo instruction is gone now.
10070 MachineBasicBlock *
10071 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
10072 MachineBasicBlock *BB) const {
10073 switch (MI->getOpcode()) {
10074 default: assert(false && "Unexpected instr type to insert");
10075 case X86::WIN_ALLOCA:
10076 return EmitLoweredWinAlloca(MI, BB);
10077 case X86::TLSCall_32:
10078 case X86::TLSCall_64:
10079 return EmitLoweredTLSCall(MI, BB);
10080 case X86::CMOV_GR8:
10081 case X86::CMOV_FR32:
10082 case X86::CMOV_FR64:
10083 case X86::CMOV_V4F32:
10084 case X86::CMOV_V2F64:
10085 case X86::CMOV_V2I64:
10086 case X86::CMOV_GR16:
10087 case X86::CMOV_GR32:
10088 case X86::CMOV_RFP32:
10089 case X86::CMOV_RFP64:
10090 case X86::CMOV_RFP80:
10091 return EmitLoweredSelect(MI, BB);
10093 case X86::FP32_TO_INT16_IN_MEM:
10094 case X86::FP32_TO_INT32_IN_MEM:
10095 case X86::FP32_TO_INT64_IN_MEM:
10096 case X86::FP64_TO_INT16_IN_MEM:
10097 case X86::FP64_TO_INT32_IN_MEM:
10098 case X86::FP64_TO_INT64_IN_MEM:
10099 case X86::FP80_TO_INT16_IN_MEM:
10100 case X86::FP80_TO_INT32_IN_MEM:
10101 case X86::FP80_TO_INT64_IN_MEM: {
10102 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10103 DebugLoc DL = MI->getDebugLoc();
10105 // Change the floating point control register to use "round towards zero"
10106 // mode when truncating to an integer value.
10107 MachineFunction *F = BB->getParent();
10108 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
10109 addFrameReference(BuildMI(*BB, MI, DL,
10110 TII->get(X86::FNSTCW16m)), CWFrameIdx);
10112 // Load the old value of the high byte of the control word...
10114 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
10115 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
10118 // Set the high part to be round to zero...
10119 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
10122 // Reload the modified control word now...
10123 addFrameReference(BuildMI(*BB, MI, DL,
10124 TII->get(X86::FLDCW16m)), CWFrameIdx);
10126 // Restore the memory image of control word to original value
10127 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
10130 // Get the X86 opcode to use.
10132 switch (MI->getOpcode()) {
10133 default: llvm_unreachable("illegal opcode!");
10134 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
10135 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
10136 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
10137 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
10138 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
10139 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
10140 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
10141 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
10142 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
10146 MachineOperand &Op = MI->getOperand(0);
10148 AM.BaseType = X86AddressMode::RegBase;
10149 AM.Base.Reg = Op.getReg();
10151 AM.BaseType = X86AddressMode::FrameIndexBase;
10152 AM.Base.FrameIndex = Op.getIndex();
10154 Op = MI->getOperand(1);
10156 AM.Scale = Op.getImm();
10157 Op = MI->getOperand(2);
10159 AM.IndexReg = Op.getImm();
10160 Op = MI->getOperand(3);
10161 if (Op.isGlobal()) {
10162 AM.GV = Op.getGlobal();
10164 AM.Disp = Op.getImm();
10166 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
10167 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
10169 // Reload the original control word now.
10170 addFrameReference(BuildMI(*BB, MI, DL,
10171 TII->get(X86::FLDCW16m)), CWFrameIdx);
10173 MI->eraseFromParent(); // The pseudo instruction is gone now.
10176 // String/text processing lowering.
10177 case X86::PCMPISTRM128REG:
10178 case X86::VPCMPISTRM128REG:
10179 return EmitPCMP(MI, BB, 3, false /* in-mem */);
10180 case X86::PCMPISTRM128MEM:
10181 case X86::VPCMPISTRM128MEM:
10182 return EmitPCMP(MI, BB, 3, true /* in-mem */);
10183 case X86::PCMPESTRM128REG:
10184 case X86::VPCMPESTRM128REG:
10185 return EmitPCMP(MI, BB, 5, false /* in mem */);
10186 case X86::PCMPESTRM128MEM:
10187 case X86::VPCMPESTRM128MEM:
10188 return EmitPCMP(MI, BB, 5, true /* in mem */);
10190 // Thread synchronization.
10192 return EmitMonitor(MI, BB);
10194 return EmitMwait(MI, BB);
10196 // Atomic Lowering.
10197 case X86::ATOMAND32:
10198 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
10199 X86::AND32ri, X86::MOV32rm,
10201 X86::NOT32r, X86::EAX,
10202 X86::GR32RegisterClass);
10203 case X86::ATOMOR32:
10204 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
10205 X86::OR32ri, X86::MOV32rm,
10207 X86::NOT32r, X86::EAX,
10208 X86::GR32RegisterClass);
10209 case X86::ATOMXOR32:
10210 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
10211 X86::XOR32ri, X86::MOV32rm,
10213 X86::NOT32r, X86::EAX,
10214 X86::GR32RegisterClass);
10215 case X86::ATOMNAND32:
10216 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
10217 X86::AND32ri, X86::MOV32rm,
10219 X86::NOT32r, X86::EAX,
10220 X86::GR32RegisterClass, true);
10221 case X86::ATOMMIN32:
10222 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
10223 case X86::ATOMMAX32:
10224 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
10225 case X86::ATOMUMIN32:
10226 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
10227 case X86::ATOMUMAX32:
10228 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
10230 case X86::ATOMAND16:
10231 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
10232 X86::AND16ri, X86::MOV16rm,
10234 X86::NOT16r, X86::AX,
10235 X86::GR16RegisterClass);
10236 case X86::ATOMOR16:
10237 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
10238 X86::OR16ri, X86::MOV16rm,
10240 X86::NOT16r, X86::AX,
10241 X86::GR16RegisterClass);
10242 case X86::ATOMXOR16:
10243 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
10244 X86::XOR16ri, X86::MOV16rm,
10246 X86::NOT16r, X86::AX,
10247 X86::GR16RegisterClass);
10248 case X86::ATOMNAND16:
10249 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
10250 X86::AND16ri, X86::MOV16rm,
10252 X86::NOT16r, X86::AX,
10253 X86::GR16RegisterClass, true);
10254 case X86::ATOMMIN16:
10255 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
10256 case X86::ATOMMAX16:
10257 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
10258 case X86::ATOMUMIN16:
10259 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
10260 case X86::ATOMUMAX16:
10261 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
10263 case X86::ATOMAND8:
10264 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
10265 X86::AND8ri, X86::MOV8rm,
10267 X86::NOT8r, X86::AL,
10268 X86::GR8RegisterClass);
10270 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
10271 X86::OR8ri, X86::MOV8rm,
10273 X86::NOT8r, X86::AL,
10274 X86::GR8RegisterClass);
10275 case X86::ATOMXOR8:
10276 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
10277 X86::XOR8ri, X86::MOV8rm,
10279 X86::NOT8r, X86::AL,
10280 X86::GR8RegisterClass);
10281 case X86::ATOMNAND8:
10282 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
10283 X86::AND8ri, X86::MOV8rm,
10285 X86::NOT8r, X86::AL,
10286 X86::GR8RegisterClass, true);
10287 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
10288 // This group is for 64-bit host.
10289 case X86::ATOMAND64:
10290 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
10291 X86::AND64ri32, X86::MOV64rm,
10293 X86::NOT64r, X86::RAX,
10294 X86::GR64RegisterClass);
10295 case X86::ATOMOR64:
10296 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
10297 X86::OR64ri32, X86::MOV64rm,
10299 X86::NOT64r, X86::RAX,
10300 X86::GR64RegisterClass);
10301 case X86::ATOMXOR64:
10302 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
10303 X86::XOR64ri32, X86::MOV64rm,
10305 X86::NOT64r, X86::RAX,
10306 X86::GR64RegisterClass);
10307 case X86::ATOMNAND64:
10308 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
10309 X86::AND64ri32, X86::MOV64rm,
10311 X86::NOT64r, X86::RAX,
10312 X86::GR64RegisterClass, true);
10313 case X86::ATOMMIN64:
10314 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
10315 case X86::ATOMMAX64:
10316 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
10317 case X86::ATOMUMIN64:
10318 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
10319 case X86::ATOMUMAX64:
10320 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
10322 // This group does 64-bit operations on a 32-bit host.
10323 case X86::ATOMAND6432:
10324 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10325 X86::AND32rr, X86::AND32rr,
10326 X86::AND32ri, X86::AND32ri,
10328 case X86::ATOMOR6432:
10329 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10330 X86::OR32rr, X86::OR32rr,
10331 X86::OR32ri, X86::OR32ri,
10333 case X86::ATOMXOR6432:
10334 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10335 X86::XOR32rr, X86::XOR32rr,
10336 X86::XOR32ri, X86::XOR32ri,
10338 case X86::ATOMNAND6432:
10339 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10340 X86::AND32rr, X86::AND32rr,
10341 X86::AND32ri, X86::AND32ri,
10343 case X86::ATOMADD6432:
10344 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10345 X86::ADD32rr, X86::ADC32rr,
10346 X86::ADD32ri, X86::ADC32ri,
10348 case X86::ATOMSUB6432:
10349 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10350 X86::SUB32rr, X86::SBB32rr,
10351 X86::SUB32ri, X86::SBB32ri,
10353 case X86::ATOMSWAP6432:
10354 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10355 X86::MOV32rr, X86::MOV32rr,
10356 X86::MOV32ri, X86::MOV32ri,
10358 case X86::VASTART_SAVE_XMM_REGS:
10359 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
10361 case X86::VAARG_64:
10362 return EmitVAARG64WithCustomInserter(MI, BB);
10366 //===----------------------------------------------------------------------===//
10367 // X86 Optimization Hooks
10368 //===----------------------------------------------------------------------===//
10370 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
10374 const SelectionDAG &DAG,
10375 unsigned Depth) const {
10376 unsigned Opc = Op.getOpcode();
10377 assert((Opc >= ISD::BUILTIN_OP_END ||
10378 Opc == ISD::INTRINSIC_WO_CHAIN ||
10379 Opc == ISD::INTRINSIC_W_CHAIN ||
10380 Opc == ISD::INTRINSIC_VOID) &&
10381 "Should use MaskedValueIsZero if you don't know whether Op"
10382 " is a target node!");
10384 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
10398 // These nodes' second result is a boolean.
10399 if (Op.getResNo() == 0)
10402 case X86ISD::SETCC:
10403 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
10404 Mask.getBitWidth() - 1);
10409 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
10410 unsigned Depth) const {
10411 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
10412 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
10413 return Op.getValueType().getScalarType().getSizeInBits();
10419 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
10420 /// node is a GlobalAddress + offset.
10421 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
10422 const GlobalValue* &GA,
10423 int64_t &Offset) const {
10424 if (N->getOpcode() == X86ISD::Wrapper) {
10425 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
10426 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
10427 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
10431 return TargetLowering::isGAPlusOffset(N, GA, Offset);
10434 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
10435 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
10436 /// if the load addresses are consecutive, non-overlapping, and in the right
10438 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
10439 TargetLowering::DAGCombinerInfo &DCI) {
10440 DebugLoc dl = N->getDebugLoc();
10441 EVT VT = N->getValueType(0);
10443 if (VT.getSizeInBits() != 128)
10446 // Don't create instructions with illegal types after legalize types has run.
10447 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10448 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
10451 SmallVector<SDValue, 16> Elts;
10452 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
10453 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
10455 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
10458 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
10459 /// generation and convert it from being a bunch of shuffles and extracts
10460 /// to a simple store and scalar loads to extract the elements.
10461 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
10462 const TargetLowering &TLI) {
10463 SDValue InputVector = N->getOperand(0);
10465 // Only operate on vectors of 4 elements, where the alternative shuffling
10466 // gets to be more expensive.
10467 if (InputVector.getValueType() != MVT::v4i32)
10470 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
10471 // single use which is a sign-extend or zero-extend, and all elements are
10473 SmallVector<SDNode *, 4> Uses;
10474 unsigned ExtractedElements = 0;
10475 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
10476 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
10477 if (UI.getUse().getResNo() != InputVector.getResNo())
10480 SDNode *Extract = *UI;
10481 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
10484 if (Extract->getValueType(0) != MVT::i32)
10486 if (!Extract->hasOneUse())
10488 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
10489 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
10491 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
10494 // Record which element was extracted.
10495 ExtractedElements |=
10496 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
10498 Uses.push_back(Extract);
10501 // If not all the elements were used, this may not be worthwhile.
10502 if (ExtractedElements != 15)
10505 // Ok, we've now decided to do the transformation.
10506 DebugLoc dl = InputVector.getDebugLoc();
10508 // Store the value to a temporary stack slot.
10509 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
10510 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
10511 MachinePointerInfo(), false, false, 0);
10513 // Replace each use (extract) with a load of the appropriate element.
10514 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
10515 UE = Uses.end(); UI != UE; ++UI) {
10516 SDNode *Extract = *UI;
10518 // Compute the element's address.
10519 SDValue Idx = Extract->getOperand(1);
10521 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
10522 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
10523 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
10525 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(),
10526 StackPtr, OffsetVal);
10528 // Load the scalar.
10529 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
10530 ScalarAddr, MachinePointerInfo(),
10533 // Replace the exact with the load.
10534 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
10537 // The replacement was made in place; don't return anything.
10541 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
10542 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
10543 const X86Subtarget *Subtarget) {
10544 DebugLoc DL = N->getDebugLoc();
10545 SDValue Cond = N->getOperand(0);
10546 // Get the LHS/RHS of the select.
10547 SDValue LHS = N->getOperand(1);
10548 SDValue RHS = N->getOperand(2);
10550 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
10551 // instructions match the semantics of the common C idiom x<y?x:y but not
10552 // x<=y?x:y, because of how they handle negative zero (which can be
10553 // ignored in unsafe-math mode).
10554 if (Subtarget->hasSSE2() &&
10555 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
10556 Cond.getOpcode() == ISD::SETCC) {
10557 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
10559 unsigned Opcode = 0;
10560 // Check for x CC y ? x : y.
10561 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
10562 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
10566 // Converting this to a min would handle NaNs incorrectly, and swapping
10567 // the operands would cause it to handle comparisons between positive
10568 // and negative zero incorrectly.
10569 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
10570 if (!UnsafeFPMath &&
10571 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
10573 std::swap(LHS, RHS);
10575 Opcode = X86ISD::FMIN;
10578 // Converting this to a min would handle comparisons between positive
10579 // and negative zero incorrectly.
10580 if (!UnsafeFPMath &&
10581 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
10583 Opcode = X86ISD::FMIN;
10586 // Converting this to a min would handle both negative zeros and NaNs
10587 // incorrectly, but we can swap the operands to fix both.
10588 std::swap(LHS, RHS);
10592 Opcode = X86ISD::FMIN;
10596 // Converting this to a max would handle comparisons between positive
10597 // and negative zero incorrectly.
10598 if (!UnsafeFPMath &&
10599 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(LHS))
10601 Opcode = X86ISD::FMAX;
10604 // Converting this to a max would handle NaNs incorrectly, and swapping
10605 // the operands would cause it to handle comparisons between positive
10606 // and negative zero incorrectly.
10607 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
10608 if (!UnsafeFPMath &&
10609 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
10611 std::swap(LHS, RHS);
10613 Opcode = X86ISD::FMAX;
10616 // Converting this to a max would handle both negative zeros and NaNs
10617 // incorrectly, but we can swap the operands to fix both.
10618 std::swap(LHS, RHS);
10622 Opcode = X86ISD::FMAX;
10625 // Check for x CC y ? y : x -- a min/max with reversed arms.
10626 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
10627 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
10631 // Converting this to a min would handle comparisons between positive
10632 // and negative zero incorrectly, and swapping the operands would
10633 // cause it to handle NaNs incorrectly.
10634 if (!UnsafeFPMath &&
10635 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
10636 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
10638 std::swap(LHS, RHS);
10640 Opcode = X86ISD::FMIN;
10643 // Converting this to a min would handle NaNs incorrectly.
10644 if (!UnsafeFPMath &&
10645 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
10647 Opcode = X86ISD::FMIN;
10650 // Converting this to a min would handle both negative zeros and NaNs
10651 // incorrectly, but we can swap the operands to fix both.
10652 std::swap(LHS, RHS);
10656 Opcode = X86ISD::FMIN;
10660 // Converting this to a max would handle NaNs incorrectly.
10661 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
10663 Opcode = X86ISD::FMAX;
10666 // Converting this to a max would handle comparisons between positive
10667 // and negative zero incorrectly, and swapping the operands would
10668 // cause it to handle NaNs incorrectly.
10669 if (!UnsafeFPMath &&
10670 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
10671 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
10673 std::swap(LHS, RHS);
10675 Opcode = X86ISD::FMAX;
10678 // Converting this to a max would handle both negative zeros and NaNs
10679 // incorrectly, but we can swap the operands to fix both.
10680 std::swap(LHS, RHS);
10684 Opcode = X86ISD::FMAX;
10690 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
10693 // If this is a select between two integer constants, try to do some
10695 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
10696 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
10697 // Don't do this for crazy integer types.
10698 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
10699 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
10700 // so that TrueC (the true value) is larger than FalseC.
10701 bool NeedsCondInvert = false;
10703 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
10704 // Efficiently invertible.
10705 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
10706 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
10707 isa<ConstantSDNode>(Cond.getOperand(1))))) {
10708 NeedsCondInvert = true;
10709 std::swap(TrueC, FalseC);
10712 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
10713 if (FalseC->getAPIntValue() == 0 &&
10714 TrueC->getAPIntValue().isPowerOf2()) {
10715 if (NeedsCondInvert) // Invert the condition if needed.
10716 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
10717 DAG.getConstant(1, Cond.getValueType()));
10719 // Zero extend the condition if needed.
10720 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
10722 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
10723 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
10724 DAG.getConstant(ShAmt, MVT::i8));
10727 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
10728 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
10729 if (NeedsCondInvert) // Invert the condition if needed.
10730 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
10731 DAG.getConstant(1, Cond.getValueType()));
10733 // Zero extend the condition if needed.
10734 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
10735 FalseC->getValueType(0), Cond);
10736 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10737 SDValue(FalseC, 0));
10740 // Optimize cases that will turn into an LEA instruction. This requires
10741 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
10742 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
10743 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
10744 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
10746 bool isFastMultiplier = false;
10748 switch ((unsigned char)Diff) {
10750 case 1: // result = add base, cond
10751 case 2: // result = lea base( , cond*2)
10752 case 3: // result = lea base(cond, cond*2)
10753 case 4: // result = lea base( , cond*4)
10754 case 5: // result = lea base(cond, cond*4)
10755 case 8: // result = lea base( , cond*8)
10756 case 9: // result = lea base(cond, cond*8)
10757 isFastMultiplier = true;
10762 if (isFastMultiplier) {
10763 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
10764 if (NeedsCondInvert) // Invert the condition if needed.
10765 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
10766 DAG.getConstant(1, Cond.getValueType()));
10768 // Zero extend the condition if needed.
10769 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
10771 // Scale the condition by the difference.
10773 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
10774 DAG.getConstant(Diff, Cond.getValueType()));
10776 // Add the base if non-zero.
10777 if (FalseC->getAPIntValue() != 0)
10778 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10779 SDValue(FalseC, 0));
10789 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
10790 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
10791 TargetLowering::DAGCombinerInfo &DCI) {
10792 DebugLoc DL = N->getDebugLoc();
10794 // If the flag operand isn't dead, don't touch this CMOV.
10795 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
10798 // If this is a select between two integer constants, try to do some
10799 // optimizations. Note that the operands are ordered the opposite of SELECT
10801 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
10802 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10803 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
10804 // larger than FalseC (the false value).
10805 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
10807 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
10808 CC = X86::GetOppositeBranchCondition(CC);
10809 std::swap(TrueC, FalseC);
10812 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
10813 // This is efficient for any integer data type (including i8/i16) and
10815 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
10816 SDValue Cond = N->getOperand(3);
10817 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10818 DAG.getConstant(CC, MVT::i8), Cond);
10820 // Zero extend the condition if needed.
10821 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
10823 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
10824 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
10825 DAG.getConstant(ShAmt, MVT::i8));
10826 if (N->getNumValues() == 2) // Dead flag value?
10827 return DCI.CombineTo(N, Cond, SDValue());
10831 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
10832 // for any integer data type, including i8/i16.
10833 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
10834 SDValue Cond = N->getOperand(3);
10835 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10836 DAG.getConstant(CC, MVT::i8), Cond);
10838 // Zero extend the condition if needed.
10839 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
10840 FalseC->getValueType(0), Cond);
10841 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10842 SDValue(FalseC, 0));
10844 if (N->getNumValues() == 2) // Dead flag value?
10845 return DCI.CombineTo(N, Cond, SDValue());
10849 // Optimize cases that will turn into an LEA instruction. This requires
10850 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
10851 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
10852 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
10853 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
10855 bool isFastMultiplier = false;
10857 switch ((unsigned char)Diff) {
10859 case 1: // result = add base, cond
10860 case 2: // result = lea base( , cond*2)
10861 case 3: // result = lea base(cond, cond*2)
10862 case 4: // result = lea base( , cond*4)
10863 case 5: // result = lea base(cond, cond*4)
10864 case 8: // result = lea base( , cond*8)
10865 case 9: // result = lea base(cond, cond*8)
10866 isFastMultiplier = true;
10871 if (isFastMultiplier) {
10872 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
10873 SDValue Cond = N->getOperand(3);
10874 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10875 DAG.getConstant(CC, MVT::i8), Cond);
10876 // Zero extend the condition if needed.
10877 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
10879 // Scale the condition by the difference.
10881 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
10882 DAG.getConstant(Diff, Cond.getValueType()));
10884 // Add the base if non-zero.
10885 if (FalseC->getAPIntValue() != 0)
10886 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10887 SDValue(FalseC, 0));
10888 if (N->getNumValues() == 2) // Dead flag value?
10889 return DCI.CombineTo(N, Cond, SDValue());
10899 /// PerformMulCombine - Optimize a single multiply with constant into two
10900 /// in order to implement it with two cheaper instructions, e.g.
10901 /// LEA + SHL, LEA + LEA.
10902 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
10903 TargetLowering::DAGCombinerInfo &DCI) {
10904 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
10907 EVT VT = N->getValueType(0);
10908 if (VT != MVT::i64)
10911 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
10914 uint64_t MulAmt = C->getZExtValue();
10915 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
10918 uint64_t MulAmt1 = 0;
10919 uint64_t MulAmt2 = 0;
10920 if ((MulAmt % 9) == 0) {
10922 MulAmt2 = MulAmt / 9;
10923 } else if ((MulAmt % 5) == 0) {
10925 MulAmt2 = MulAmt / 5;
10926 } else if ((MulAmt % 3) == 0) {
10928 MulAmt2 = MulAmt / 3;
10931 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
10932 DebugLoc DL = N->getDebugLoc();
10934 if (isPowerOf2_64(MulAmt2) &&
10935 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
10936 // If second multiplifer is pow2, issue it first. We want the multiply by
10937 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
10939 std::swap(MulAmt1, MulAmt2);
10942 if (isPowerOf2_64(MulAmt1))
10943 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
10944 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
10946 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
10947 DAG.getConstant(MulAmt1, VT));
10949 if (isPowerOf2_64(MulAmt2))
10950 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
10951 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
10953 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
10954 DAG.getConstant(MulAmt2, VT));
10956 // Do not add new nodes to DAG combiner worklist.
10957 DCI.CombineTo(N, NewMul, false);
10962 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
10963 SDValue N0 = N->getOperand(0);
10964 SDValue N1 = N->getOperand(1);
10965 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
10966 EVT VT = N0.getValueType();
10968 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
10969 // since the result of setcc_c is all zero's or all ones.
10970 if (N1C && N0.getOpcode() == ISD::AND &&
10971 N0.getOperand(1).getOpcode() == ISD::Constant) {
10972 SDValue N00 = N0.getOperand(0);
10973 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
10974 ((N00.getOpcode() == ISD::ANY_EXTEND ||
10975 N00.getOpcode() == ISD::ZERO_EXTEND) &&
10976 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
10977 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
10978 APInt ShAmt = N1C->getAPIntValue();
10979 Mask = Mask.shl(ShAmt);
10981 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
10982 N00, DAG.getConstant(Mask, VT));
10989 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
10991 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
10992 const X86Subtarget *Subtarget) {
10993 EVT VT = N->getValueType(0);
10994 if (!VT.isVector() && VT.isInteger() &&
10995 N->getOpcode() == ISD::SHL)
10996 return PerformSHLCombine(N, DAG);
10998 // On X86 with SSE2 support, we can transform this to a vector shift if
10999 // all elements are shifted by the same amount. We can't do this in legalize
11000 // because the a constant vector is typically transformed to a constant pool
11001 // so we have no knowledge of the shift amount.
11002 if (!Subtarget->hasSSE2())
11005 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
11008 SDValue ShAmtOp = N->getOperand(1);
11009 EVT EltVT = VT.getVectorElementType();
11010 DebugLoc DL = N->getDebugLoc();
11011 SDValue BaseShAmt = SDValue();
11012 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
11013 unsigned NumElts = VT.getVectorNumElements();
11015 for (; i != NumElts; ++i) {
11016 SDValue Arg = ShAmtOp.getOperand(i);
11017 if (Arg.getOpcode() == ISD::UNDEF) continue;
11021 for (; i != NumElts; ++i) {
11022 SDValue Arg = ShAmtOp.getOperand(i);
11023 if (Arg.getOpcode() == ISD::UNDEF) continue;
11024 if (Arg != BaseShAmt) {
11028 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
11029 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
11030 SDValue InVec = ShAmtOp.getOperand(0);
11031 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
11032 unsigned NumElts = InVec.getValueType().getVectorNumElements();
11034 for (; i != NumElts; ++i) {
11035 SDValue Arg = InVec.getOperand(i);
11036 if (Arg.getOpcode() == ISD::UNDEF) continue;
11040 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
11041 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
11042 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
11043 if (C->getZExtValue() == SplatIdx)
11044 BaseShAmt = InVec.getOperand(1);
11047 if (BaseShAmt.getNode() == 0)
11048 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
11049 DAG.getIntPtrConstant(0));
11053 // The shift amount is an i32.
11054 if (EltVT.bitsGT(MVT::i32))
11055 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
11056 else if (EltVT.bitsLT(MVT::i32))
11057 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
11059 // The shift amount is identical so we can do a vector shift.
11060 SDValue ValOp = N->getOperand(0);
11061 switch (N->getOpcode()) {
11063 llvm_unreachable("Unknown shift opcode!");
11066 if (VT == MVT::v2i64)
11067 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11068 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
11070 if (VT == MVT::v4i32)
11071 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11072 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
11074 if (VT == MVT::v8i16)
11075 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11076 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
11080 if (VT == MVT::v4i32)
11081 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11082 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
11084 if (VT == MVT::v8i16)
11085 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11086 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
11090 if (VT == MVT::v2i64)
11091 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11092 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
11094 if (VT == MVT::v4i32)
11095 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11096 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
11098 if (VT == MVT::v8i16)
11099 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11100 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
11108 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
11109 TargetLowering::DAGCombinerInfo &DCI,
11110 const X86Subtarget *Subtarget) {
11111 if (DCI.isBeforeLegalizeOps())
11114 // Want to form PANDN nodes, in the hopes of then easily combining them with
11115 // OR and AND nodes to form PBLEND/PSIGN.
11116 EVT VT = N->getValueType(0);
11117 if (VT != MVT::v2i64)
11120 SDValue N0 = N->getOperand(0);
11121 SDValue N1 = N->getOperand(1);
11122 DebugLoc DL = N->getDebugLoc();
11124 // Check LHS for vnot
11125 if (N0.getOpcode() == ISD::XOR &&
11126 ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
11127 return DAG.getNode(X86ISD::PANDN, DL, VT, N0.getOperand(0), N1);
11129 // Check RHS for vnot
11130 if (N1.getOpcode() == ISD::XOR &&
11131 ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
11132 return DAG.getNode(X86ISD::PANDN, DL, VT, N1.getOperand(0), N0);
11137 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
11138 TargetLowering::DAGCombinerInfo &DCI,
11139 const X86Subtarget *Subtarget) {
11140 if (DCI.isBeforeLegalizeOps())
11143 EVT VT = N->getValueType(0);
11144 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64 && VT != MVT::v2i64)
11147 SDValue N0 = N->getOperand(0);
11148 SDValue N1 = N->getOperand(1);
11150 // look for psign/blend
11151 if (Subtarget->hasSSSE3()) {
11152 if (VT == MVT::v2i64) {
11153 // Canonicalize pandn to RHS
11154 if (N0.getOpcode() == X86ISD::PANDN)
11156 // or (and (m, x), (pandn m, y))
11157 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::PANDN) {
11158 SDValue Mask = N1.getOperand(0);
11159 SDValue X = N1.getOperand(1);
11161 if (N0.getOperand(0) == Mask)
11162 Y = N0.getOperand(1);
11163 if (N0.getOperand(1) == Mask)
11164 Y = N0.getOperand(0);
11166 // Check to see if the mask appeared in both the AND and PANDN and
11170 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
11171 if (Mask.getOpcode() != ISD::BITCAST ||
11172 X.getOpcode() != ISD::BITCAST ||
11173 Y.getOpcode() != ISD::BITCAST)
11176 // Look through mask bitcast.
11177 Mask = Mask.getOperand(0);
11178 EVT MaskVT = Mask.getValueType();
11180 // Validate that the Mask operand is a vector sra node. The sra node
11181 // will be an intrinsic.
11182 if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN)
11185 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
11186 // there is no psrai.b
11187 switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) {
11188 case Intrinsic::x86_sse2_psrai_w:
11189 case Intrinsic::x86_sse2_psrai_d:
11191 default: return SDValue();
11194 // Check that the SRA is all signbits.
11195 SDValue SraC = Mask.getOperand(2);
11196 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
11197 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
11198 if ((SraAmt + 1) != EltBits)
11201 DebugLoc DL = N->getDebugLoc();
11203 // Now we know we at least have a plendvb with the mask val. See if
11204 // we can form a psignb/w/d.
11205 // psign = x.type == y.type == mask.type && y = sub(0, x);
11206 X = X.getOperand(0);
11207 Y = Y.getOperand(0);
11208 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
11209 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
11210 X.getValueType() == MaskVT && X.getValueType() == Y.getValueType()){
11213 case 8: Opc = X86ISD::PSIGNB; break;
11214 case 16: Opc = X86ISD::PSIGNW; break;
11215 case 32: Opc = X86ISD::PSIGND; break;
11219 SDValue Sign = DAG.getNode(Opc, DL, MaskVT, X, Mask.getOperand(1));
11220 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Sign);
11223 // PBLENDVB only available on SSE 4.1
11224 if (!Subtarget->hasSSE41())
11227 X = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, X);
11228 Y = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Y);
11229 Mask = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Mask);
11230 Mask = DAG.getNode(X86ISD::PBLENDVB, DL, MVT::v16i8, X, Y, Mask);
11231 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Mask);
11236 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
11237 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
11239 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
11241 if (!N0.hasOneUse() || !N1.hasOneUse())
11244 SDValue ShAmt0 = N0.getOperand(1);
11245 if (ShAmt0.getValueType() != MVT::i8)
11247 SDValue ShAmt1 = N1.getOperand(1);
11248 if (ShAmt1.getValueType() != MVT::i8)
11250 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
11251 ShAmt0 = ShAmt0.getOperand(0);
11252 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
11253 ShAmt1 = ShAmt1.getOperand(0);
11255 DebugLoc DL = N->getDebugLoc();
11256 unsigned Opc = X86ISD::SHLD;
11257 SDValue Op0 = N0.getOperand(0);
11258 SDValue Op1 = N1.getOperand(0);
11259 if (ShAmt0.getOpcode() == ISD::SUB) {
11260 Opc = X86ISD::SHRD;
11261 std::swap(Op0, Op1);
11262 std::swap(ShAmt0, ShAmt1);
11265 unsigned Bits = VT.getSizeInBits();
11266 if (ShAmt1.getOpcode() == ISD::SUB) {
11267 SDValue Sum = ShAmt1.getOperand(0);
11268 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
11269 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
11270 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
11271 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
11272 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
11273 return DAG.getNode(Opc, DL, VT,
11275 DAG.getNode(ISD::TRUNCATE, DL,
11278 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
11279 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
11281 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
11282 return DAG.getNode(Opc, DL, VT,
11283 N0.getOperand(0), N1.getOperand(0),
11284 DAG.getNode(ISD::TRUNCATE, DL,
11291 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
11292 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
11293 const X86Subtarget *Subtarget) {
11294 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
11295 // the FP state in cases where an emms may be missing.
11296 // A preferable solution to the general problem is to figure out the right
11297 // places to insert EMMS. This qualifies as a quick hack.
11299 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
11300 StoreSDNode *St = cast<StoreSDNode>(N);
11301 EVT VT = St->getValue().getValueType();
11302 if (VT.getSizeInBits() != 64)
11305 const Function *F = DAG.getMachineFunction().getFunction();
11306 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
11307 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
11308 && Subtarget->hasSSE2();
11309 if ((VT.isVector() ||
11310 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
11311 isa<LoadSDNode>(St->getValue()) &&
11312 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
11313 St->getChain().hasOneUse() && !St->isVolatile()) {
11314 SDNode* LdVal = St->getValue().getNode();
11315 LoadSDNode *Ld = 0;
11316 int TokenFactorIndex = -1;
11317 SmallVector<SDValue, 8> Ops;
11318 SDNode* ChainVal = St->getChain().getNode();
11319 // Must be a store of a load. We currently handle two cases: the load
11320 // is a direct child, and it's under an intervening TokenFactor. It is
11321 // possible to dig deeper under nested TokenFactors.
11322 if (ChainVal == LdVal)
11323 Ld = cast<LoadSDNode>(St->getChain());
11324 else if (St->getValue().hasOneUse() &&
11325 ChainVal->getOpcode() == ISD::TokenFactor) {
11326 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
11327 if (ChainVal->getOperand(i).getNode() == LdVal) {
11328 TokenFactorIndex = i;
11329 Ld = cast<LoadSDNode>(St->getValue());
11331 Ops.push_back(ChainVal->getOperand(i));
11335 if (!Ld || !ISD::isNormalLoad(Ld))
11338 // If this is not the MMX case, i.e. we are just turning i64 load/store
11339 // into f64 load/store, avoid the transformation if there are multiple
11340 // uses of the loaded value.
11341 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
11344 DebugLoc LdDL = Ld->getDebugLoc();
11345 DebugLoc StDL = N->getDebugLoc();
11346 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
11347 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
11349 if (Subtarget->is64Bit() || F64IsLegal) {
11350 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
11351 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
11352 Ld->getPointerInfo(), Ld->isVolatile(),
11353 Ld->isNonTemporal(), Ld->getAlignment());
11354 SDValue NewChain = NewLd.getValue(1);
11355 if (TokenFactorIndex != -1) {
11356 Ops.push_back(NewChain);
11357 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
11360 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
11361 St->getPointerInfo(),
11362 St->isVolatile(), St->isNonTemporal(),
11363 St->getAlignment());
11366 // Otherwise, lower to two pairs of 32-bit loads / stores.
11367 SDValue LoAddr = Ld->getBasePtr();
11368 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
11369 DAG.getConstant(4, MVT::i32));
11371 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
11372 Ld->getPointerInfo(),
11373 Ld->isVolatile(), Ld->isNonTemporal(),
11374 Ld->getAlignment());
11375 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
11376 Ld->getPointerInfo().getWithOffset(4),
11377 Ld->isVolatile(), Ld->isNonTemporal(),
11378 MinAlign(Ld->getAlignment(), 4));
11380 SDValue NewChain = LoLd.getValue(1);
11381 if (TokenFactorIndex != -1) {
11382 Ops.push_back(LoLd);
11383 Ops.push_back(HiLd);
11384 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
11388 LoAddr = St->getBasePtr();
11389 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
11390 DAG.getConstant(4, MVT::i32));
11392 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
11393 St->getPointerInfo(),
11394 St->isVolatile(), St->isNonTemporal(),
11395 St->getAlignment());
11396 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
11397 St->getPointerInfo().getWithOffset(4),
11399 St->isNonTemporal(),
11400 MinAlign(St->getAlignment(), 4));
11401 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
11406 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
11407 /// X86ISD::FXOR nodes.
11408 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
11409 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
11410 // F[X]OR(0.0, x) -> x
11411 // F[X]OR(x, 0.0) -> x
11412 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
11413 if (C->getValueAPF().isPosZero())
11414 return N->getOperand(1);
11415 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
11416 if (C->getValueAPF().isPosZero())
11417 return N->getOperand(0);
11421 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
11422 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
11423 // FAND(0.0, x) -> 0.0
11424 // FAND(x, 0.0) -> 0.0
11425 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
11426 if (C->getValueAPF().isPosZero())
11427 return N->getOperand(0);
11428 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
11429 if (C->getValueAPF().isPosZero())
11430 return N->getOperand(1);
11434 static SDValue PerformBTCombine(SDNode *N,
11436 TargetLowering::DAGCombinerInfo &DCI) {
11437 // BT ignores high bits in the bit index operand.
11438 SDValue Op1 = N->getOperand(1);
11439 if (Op1.hasOneUse()) {
11440 unsigned BitWidth = Op1.getValueSizeInBits();
11441 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
11442 APInt KnownZero, KnownOne;
11443 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
11444 !DCI.isBeforeLegalizeOps());
11445 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11446 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
11447 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
11448 DCI.CommitTargetLoweringOpt(TLO);
11453 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
11454 SDValue Op = N->getOperand(0);
11455 if (Op.getOpcode() == ISD::BITCAST)
11456 Op = Op.getOperand(0);
11457 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
11458 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
11459 VT.getVectorElementType().getSizeInBits() ==
11460 OpVT.getVectorElementType().getSizeInBits()) {
11461 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
11466 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
11467 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
11468 // (and (i32 x86isd::setcc_carry), 1)
11469 // This eliminates the zext. This transformation is necessary because
11470 // ISD::SETCC is always legalized to i8.
11471 DebugLoc dl = N->getDebugLoc();
11472 SDValue N0 = N->getOperand(0);
11473 EVT VT = N->getValueType(0);
11474 if (N0.getOpcode() == ISD::AND &&
11476 N0.getOperand(0).hasOneUse()) {
11477 SDValue N00 = N0.getOperand(0);
11478 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
11480 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
11481 if (!C || C->getZExtValue() != 1)
11483 return DAG.getNode(ISD::AND, dl, VT,
11484 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
11485 N00.getOperand(0), N00.getOperand(1)),
11486 DAG.getConstant(1, VT));
11492 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
11493 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
11494 unsigned X86CC = N->getConstantOperandVal(0);
11495 SDValue EFLAG = N->getOperand(1);
11496 DebugLoc DL = N->getDebugLoc();
11498 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
11499 // a zext and produces an all-ones bit which is more useful than 0/1 in some
11501 if (X86CC == X86::COND_B)
11502 return DAG.getNode(ISD::AND, DL, MVT::i8,
11503 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
11504 DAG.getConstant(X86CC, MVT::i8), EFLAG),
11505 DAG.getConstant(1, MVT::i8));
11510 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
11511 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
11512 X86TargetLowering::DAGCombinerInfo &DCI) {
11513 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
11514 // the result is either zero or one (depending on the input carry bit).
11515 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
11516 if (X86::isZeroNode(N->getOperand(0)) &&
11517 X86::isZeroNode(N->getOperand(1)) &&
11518 // We don't have a good way to replace an EFLAGS use, so only do this when
11520 SDValue(N, 1).use_empty()) {
11521 DebugLoc DL = N->getDebugLoc();
11522 EVT VT = N->getValueType(0);
11523 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
11524 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
11525 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
11526 DAG.getConstant(X86::COND_B,MVT::i8),
11528 DAG.getConstant(1, VT));
11529 return DCI.CombineTo(N, Res1, CarryOut);
11535 // fold (add Y, (sete X, 0)) -> adc 0, Y
11536 // (add Y, (setne X, 0)) -> sbb -1, Y
11537 // (sub (sete X, 0), Y) -> sbb 0, Y
11538 // (sub (setne X, 0), Y) -> adc -1, Y
11539 static SDValue OptimizeConditonalInDecrement(SDNode *N, SelectionDAG &DAG) {
11540 DebugLoc DL = N->getDebugLoc();
11542 // Look through ZExts.
11543 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
11544 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
11547 SDValue SetCC = Ext.getOperand(0);
11548 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
11551 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
11552 if (CC != X86::COND_E && CC != X86::COND_NE)
11555 SDValue Cmp = SetCC.getOperand(1);
11556 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
11557 !X86::isZeroNode(Cmp.getOperand(1)))
11560 SDValue CmpOp0 = Cmp.getOperand(0);
11561 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
11562 DAG.getConstant(1, CmpOp0.getValueType()));
11564 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
11565 if (CC == X86::COND_NE)
11566 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
11567 DL, OtherVal.getValueType(), OtherVal,
11568 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
11569 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
11570 DL, OtherVal.getValueType(), OtherVal,
11571 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
11574 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
11575 DAGCombinerInfo &DCI) const {
11576 SelectionDAG &DAG = DCI.DAG;
11577 switch (N->getOpcode()) {
11579 case ISD::EXTRACT_VECTOR_ELT:
11580 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
11581 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
11582 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
11584 case ISD::SUB: return OptimizeConditonalInDecrement(N, DAG);
11585 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
11586 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
11589 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
11590 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
11591 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
11592 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
11594 case X86ISD::FOR: return PerformFORCombine(N, DAG);
11595 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
11596 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
11597 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
11598 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
11599 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
11600 case X86ISD::SHUFPS: // Handle all target specific shuffles
11601 case X86ISD::SHUFPD:
11602 case X86ISD::PALIGN:
11603 case X86ISD::PUNPCKHBW:
11604 case X86ISD::PUNPCKHWD:
11605 case X86ISD::PUNPCKHDQ:
11606 case X86ISD::PUNPCKHQDQ:
11607 case X86ISD::UNPCKHPS:
11608 case X86ISD::UNPCKHPD:
11609 case X86ISD::PUNPCKLBW:
11610 case X86ISD::PUNPCKLWD:
11611 case X86ISD::PUNPCKLDQ:
11612 case X86ISD::PUNPCKLQDQ:
11613 case X86ISD::UNPCKLPS:
11614 case X86ISD::UNPCKLPD:
11615 case X86ISD::MOVHLPS:
11616 case X86ISD::MOVLHPS:
11617 case X86ISD::PSHUFD:
11618 case X86ISD::PSHUFHW:
11619 case X86ISD::PSHUFLW:
11620 case X86ISD::MOVSS:
11621 case X86ISD::MOVSD:
11622 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI);
11628 /// isTypeDesirableForOp - Return true if the target has native support for
11629 /// the specified value type and it is 'desirable' to use the type for the
11630 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
11631 /// instruction encodings are longer and some i16 instructions are slow.
11632 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
11633 if (!isTypeLegal(VT))
11635 if (VT != MVT::i16)
11642 case ISD::SIGN_EXTEND:
11643 case ISD::ZERO_EXTEND:
11644 case ISD::ANY_EXTEND:
11657 /// IsDesirableToPromoteOp - This method query the target whether it is
11658 /// beneficial for dag combiner to promote the specified node. If true, it
11659 /// should return the desired promotion type by reference.
11660 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
11661 EVT VT = Op.getValueType();
11662 if (VT != MVT::i16)
11665 bool Promote = false;
11666 bool Commute = false;
11667 switch (Op.getOpcode()) {
11670 LoadSDNode *LD = cast<LoadSDNode>(Op);
11671 // If the non-extending load has a single use and it's not live out, then it
11672 // might be folded.
11673 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
11674 Op.hasOneUse()*/) {
11675 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
11676 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
11677 // The only case where we'd want to promote LOAD (rather then it being
11678 // promoted as an operand is when it's only use is liveout.
11679 if (UI->getOpcode() != ISD::CopyToReg)
11686 case ISD::SIGN_EXTEND:
11687 case ISD::ZERO_EXTEND:
11688 case ISD::ANY_EXTEND:
11693 SDValue N0 = Op.getOperand(0);
11694 // Look out for (store (shl (load), x)).
11695 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
11708 SDValue N0 = Op.getOperand(0);
11709 SDValue N1 = Op.getOperand(1);
11710 if (!Commute && MayFoldLoad(N1))
11712 // Avoid disabling potential load folding opportunities.
11713 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
11715 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
11725 //===----------------------------------------------------------------------===//
11726 // X86 Inline Assembly Support
11727 //===----------------------------------------------------------------------===//
11729 static bool LowerToBSwap(CallInst *CI) {
11730 // FIXME: this should verify that we are targetting a 486 or better. If not,
11731 // we will turn this bswap into something that will be lowered to logical ops
11732 // instead of emitting the bswap asm. For now, we don't support 486 or lower
11733 // so don't worry about this.
11735 // Verify this is a simple bswap.
11736 if (CI->getNumArgOperands() != 1 ||
11737 CI->getType() != CI->getArgOperand(0)->getType() ||
11738 !CI->getType()->isIntegerTy())
11741 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
11742 if (!Ty || Ty->getBitWidth() % 16 != 0)
11745 // Okay, we can do this xform, do so now.
11746 const Type *Tys[] = { Ty };
11747 Module *M = CI->getParent()->getParent()->getParent();
11748 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1);
11750 Value *Op = CI->getArgOperand(0);
11751 Op = CallInst::Create(Int, Op, CI->getName(), CI);
11753 CI->replaceAllUsesWith(Op);
11754 CI->eraseFromParent();
11758 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
11759 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
11760 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
11762 std::string AsmStr = IA->getAsmString();
11764 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
11765 SmallVector<StringRef, 4> AsmPieces;
11766 SplitString(AsmStr, AsmPieces, ";\n");
11768 switch (AsmPieces.size()) {
11769 default: return false;
11771 AsmStr = AsmPieces[0];
11773 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
11776 if (AsmPieces.size() == 2 &&
11777 (AsmPieces[0] == "bswap" ||
11778 AsmPieces[0] == "bswapq" ||
11779 AsmPieces[0] == "bswapl") &&
11780 (AsmPieces[1] == "$0" ||
11781 AsmPieces[1] == "${0:q}")) {
11782 // No need to check constraints, nothing other than the equivalent of
11783 // "=r,0" would be valid here.
11784 return LowerToBSwap(CI);
11786 // rorw $$8, ${0:w} --> llvm.bswap.i16
11787 if (CI->getType()->isIntegerTy(16) &&
11788 AsmPieces.size() == 3 &&
11789 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") &&
11790 AsmPieces[1] == "$$8," &&
11791 AsmPieces[2] == "${0:w}" &&
11792 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
11794 const std::string &Constraints = IA->getConstraintString();
11795 SplitString(StringRef(Constraints).substr(5), AsmPieces, ",");
11796 std::sort(AsmPieces.begin(), AsmPieces.end());
11797 if (AsmPieces.size() == 4 &&
11798 AsmPieces[0] == "~{cc}" &&
11799 AsmPieces[1] == "~{dirflag}" &&
11800 AsmPieces[2] == "~{flags}" &&
11801 AsmPieces[3] == "~{fpsr}") {
11802 return LowerToBSwap(CI);
11807 if (CI->getType()->isIntegerTy(32) &&
11808 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
11809 SmallVector<StringRef, 4> Words;
11810 SplitString(AsmPieces[0], Words, " \t,");
11811 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
11812 Words[2] == "${0:w}") {
11814 SplitString(AsmPieces[1], Words, " \t,");
11815 if (Words.size() == 3 && Words[0] == "rorl" && Words[1] == "$$16" &&
11816 Words[2] == "$0") {
11818 SplitString(AsmPieces[2], Words, " \t,");
11819 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
11820 Words[2] == "${0:w}") {
11822 const std::string &Constraints = IA->getConstraintString();
11823 SplitString(StringRef(Constraints).substr(5), AsmPieces, ",");
11824 std::sort(AsmPieces.begin(), AsmPieces.end());
11825 if (AsmPieces.size() == 4 &&
11826 AsmPieces[0] == "~{cc}" &&
11827 AsmPieces[1] == "~{dirflag}" &&
11828 AsmPieces[2] == "~{flags}" &&
11829 AsmPieces[3] == "~{fpsr}") {
11830 return LowerToBSwap(CI);
11836 if (CI->getType()->isIntegerTy(64) &&
11837 Constraints.size() >= 2 &&
11838 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
11839 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
11840 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
11841 SmallVector<StringRef, 4> Words;
11842 SplitString(AsmPieces[0], Words, " \t");
11843 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
11845 SplitString(AsmPieces[1], Words, " \t");
11846 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
11848 SplitString(AsmPieces[2], Words, " \t,");
11849 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
11850 Words[2] == "%edx") {
11851 return LowerToBSwap(CI);
11863 /// getConstraintType - Given a constraint letter, return the type of
11864 /// constraint it is for this target.
11865 X86TargetLowering::ConstraintType
11866 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
11867 if (Constraint.size() == 1) {
11868 switch (Constraint[0]) {
11878 return C_RegisterClass;
11902 return TargetLowering::getConstraintType(Constraint);
11905 /// Examine constraint type and operand type and determine a weight value.
11906 /// This object must already have been set up with the operand type
11907 /// and the current alternative constraint selected.
11908 TargetLowering::ConstraintWeight
11909 X86TargetLowering::getSingleConstraintMatchWeight(
11910 AsmOperandInfo &info, const char *constraint) const {
11911 ConstraintWeight weight = CW_Invalid;
11912 Value *CallOperandVal = info.CallOperandVal;
11913 // If we don't have a value, we can't do a match,
11914 // but allow it at the lowest weight.
11915 if (CallOperandVal == NULL)
11917 const Type *type = CallOperandVal->getType();
11918 // Look at the constraint type.
11919 switch (*constraint) {
11921 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
11932 if (CallOperandVal->getType()->isIntegerTy())
11933 weight = CW_SpecificReg;
11938 if (type->isFloatingPointTy())
11939 weight = CW_SpecificReg;
11942 if (type->isX86_MMXTy() && Subtarget->hasMMX())
11943 weight = CW_SpecificReg;
11947 if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM())
11948 weight = CW_Register;
11951 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
11952 if (C->getZExtValue() <= 31)
11953 weight = CW_Constant;
11957 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11958 if (C->getZExtValue() <= 63)
11959 weight = CW_Constant;
11963 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11964 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
11965 weight = CW_Constant;
11969 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11970 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
11971 weight = CW_Constant;
11975 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11976 if (C->getZExtValue() <= 3)
11977 weight = CW_Constant;
11981 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11982 if (C->getZExtValue() <= 0xff)
11983 weight = CW_Constant;
11988 if (dyn_cast<ConstantFP>(CallOperandVal)) {
11989 weight = CW_Constant;
11993 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11994 if ((C->getSExtValue() >= -0x80000000LL) &&
11995 (C->getSExtValue() <= 0x7fffffffLL))
11996 weight = CW_Constant;
12000 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
12001 if (C->getZExtValue() <= 0xffffffff)
12002 weight = CW_Constant;
12009 /// LowerXConstraint - try to replace an X constraint, which matches anything,
12010 /// with another that has more specific requirements based on the type of the
12011 /// corresponding operand.
12012 const char *X86TargetLowering::
12013 LowerXConstraint(EVT ConstraintVT) const {
12014 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
12015 // 'f' like normal targets.
12016 if (ConstraintVT.isFloatingPoint()) {
12017 if (Subtarget->hasXMMInt())
12019 if (Subtarget->hasXMM())
12023 return TargetLowering::LowerXConstraint(ConstraintVT);
12026 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
12027 /// vector. If it is invalid, don't add anything to Ops.
12028 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
12030 std::vector<SDValue>&Ops,
12031 SelectionDAG &DAG) const {
12032 SDValue Result(0, 0);
12034 switch (Constraint) {
12037 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
12038 if (C->getZExtValue() <= 31) {
12039 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
12045 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
12046 if (C->getZExtValue() <= 63) {
12047 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
12053 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
12054 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
12055 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
12061 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
12062 if (C->getZExtValue() <= 255) {
12063 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
12069 // 32-bit signed value
12070 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
12071 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
12072 C->getSExtValue())) {
12073 // Widen to 64 bits here to get it sign extended.
12074 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
12077 // FIXME gcc accepts some relocatable values here too, but only in certain
12078 // memory models; it's complicated.
12083 // 32-bit unsigned value
12084 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
12085 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
12086 C->getZExtValue())) {
12087 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
12091 // FIXME gcc accepts some relocatable values here too, but only in certain
12092 // memory models; it's complicated.
12096 // Literal immediates are always ok.
12097 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
12098 // Widen to 64 bits here to get it sign extended.
12099 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
12103 // In any sort of PIC mode addresses need to be computed at runtime by
12104 // adding in a register or some sort of table lookup. These can't
12105 // be used as immediates.
12106 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
12109 // If we are in non-pic codegen mode, we allow the address of a global (with
12110 // an optional displacement) to be used with 'i'.
12111 GlobalAddressSDNode *GA = 0;
12112 int64_t Offset = 0;
12114 // Match either (GA), (GA+C), (GA+C1+C2), etc.
12116 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
12117 Offset += GA->getOffset();
12119 } else if (Op.getOpcode() == ISD::ADD) {
12120 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
12121 Offset += C->getZExtValue();
12122 Op = Op.getOperand(0);
12125 } else if (Op.getOpcode() == ISD::SUB) {
12126 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
12127 Offset += -C->getZExtValue();
12128 Op = Op.getOperand(0);
12133 // Otherwise, this isn't something we can handle, reject it.
12137 const GlobalValue *GV = GA->getGlobal();
12138 // If we require an extra load to get this address, as in PIC mode, we
12139 // can't accept it.
12140 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
12141 getTargetMachine())))
12144 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
12145 GA->getValueType(0), Offset);
12150 if (Result.getNode()) {
12151 Ops.push_back(Result);
12154 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
12157 std::vector<unsigned> X86TargetLowering::
12158 getRegClassForInlineAsmConstraint(const std::string &Constraint,
12160 if (Constraint.size() == 1) {
12161 // FIXME: not handling fp-stack yet!
12162 switch (Constraint[0]) { // GCC X86 Constraint Letters
12163 default: break; // Unknown constraint letter
12164 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
12165 if (Subtarget->is64Bit()) {
12166 if (VT == MVT::i32)
12167 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
12168 X86::ESI, X86::EDI, X86::R8D, X86::R9D,
12169 X86::R10D,X86::R11D,X86::R12D,
12170 X86::R13D,X86::R14D,X86::R15D,
12171 X86::EBP, X86::ESP, 0);
12172 else if (VT == MVT::i16)
12173 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
12174 X86::SI, X86::DI, X86::R8W,X86::R9W,
12175 X86::R10W,X86::R11W,X86::R12W,
12176 X86::R13W,X86::R14W,X86::R15W,
12177 X86::BP, X86::SP, 0);
12178 else if (VT == MVT::i8)
12179 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
12180 X86::SIL, X86::DIL, X86::R8B,X86::R9B,
12181 X86::R10B,X86::R11B,X86::R12B,
12182 X86::R13B,X86::R14B,X86::R15B,
12183 X86::BPL, X86::SPL, 0);
12185 else if (VT == MVT::i64)
12186 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
12187 X86::RSI, X86::RDI, X86::R8, X86::R9,
12188 X86::R10, X86::R11, X86::R12,
12189 X86::R13, X86::R14, X86::R15,
12190 X86::RBP, X86::RSP, 0);
12194 // 32-bit fallthrough
12195 case 'Q': // Q_REGS
12196 if (VT == MVT::i32)
12197 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
12198 else if (VT == MVT::i16)
12199 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
12200 else if (VT == MVT::i8)
12201 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
12202 else if (VT == MVT::i64)
12203 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
12208 return std::vector<unsigned>();
12211 std::pair<unsigned, const TargetRegisterClass*>
12212 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
12214 // First, see if this is a constraint that directly corresponds to an LLVM
12216 if (Constraint.size() == 1) {
12217 // GCC Constraint Letters
12218 switch (Constraint[0]) {
12220 case 'r': // GENERAL_REGS
12221 case 'l': // INDEX_REGS
12223 return std::make_pair(0U, X86::GR8RegisterClass);
12224 if (VT == MVT::i16)
12225 return std::make_pair(0U, X86::GR16RegisterClass);
12226 if (VT == MVT::i32 || !Subtarget->is64Bit())
12227 return std::make_pair(0U, X86::GR32RegisterClass);
12228 return std::make_pair(0U, X86::GR64RegisterClass);
12229 case 'R': // LEGACY_REGS
12231 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
12232 if (VT == MVT::i16)
12233 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
12234 if (VT == MVT::i32 || !Subtarget->is64Bit())
12235 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
12236 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
12237 case 'f': // FP Stack registers.
12238 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
12239 // value to the correct fpstack register class.
12240 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
12241 return std::make_pair(0U, X86::RFP32RegisterClass);
12242 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
12243 return std::make_pair(0U, X86::RFP64RegisterClass);
12244 return std::make_pair(0U, X86::RFP80RegisterClass);
12245 case 'y': // MMX_REGS if MMX allowed.
12246 if (!Subtarget->hasMMX()) break;
12247 return std::make_pair(0U, X86::VR64RegisterClass);
12248 case 'Y': // SSE_REGS if SSE2 allowed
12249 if (!Subtarget->hasXMMInt()) break;
12251 case 'x': // SSE_REGS if SSE1 allowed
12252 if (!Subtarget->hasXMM()) break;
12254 switch (VT.getSimpleVT().SimpleTy) {
12256 // Scalar SSE types.
12259 return std::make_pair(0U, X86::FR32RegisterClass);
12262 return std::make_pair(0U, X86::FR64RegisterClass);
12270 return std::make_pair(0U, X86::VR128RegisterClass);
12276 // Use the default implementation in TargetLowering to convert the register
12277 // constraint into a member of a register class.
12278 std::pair<unsigned, const TargetRegisterClass*> Res;
12279 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
12281 // Not found as a standard register?
12282 if (Res.second == 0) {
12283 // Map st(0) -> st(7) -> ST0
12284 if (Constraint.size() == 7 && Constraint[0] == '{' &&
12285 tolower(Constraint[1]) == 's' &&
12286 tolower(Constraint[2]) == 't' &&
12287 Constraint[3] == '(' &&
12288 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
12289 Constraint[5] == ')' &&
12290 Constraint[6] == '}') {
12292 Res.first = X86::ST0+Constraint[4]-'0';
12293 Res.second = X86::RFP80RegisterClass;
12297 // GCC allows "st(0)" to be called just plain "st".
12298 if (StringRef("{st}").equals_lower(Constraint)) {
12299 Res.first = X86::ST0;
12300 Res.second = X86::RFP80RegisterClass;
12305 if (StringRef("{flags}").equals_lower(Constraint)) {
12306 Res.first = X86::EFLAGS;
12307 Res.second = X86::CCRRegisterClass;
12311 // 'A' means EAX + EDX.
12312 if (Constraint == "A") {
12313 Res.first = X86::EAX;
12314 Res.second = X86::GR32_ADRegisterClass;
12320 // Otherwise, check to see if this is a register class of the wrong value
12321 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
12322 // turn into {ax},{dx}.
12323 if (Res.second->hasType(VT))
12324 return Res; // Correct type already, nothing to do.
12326 // All of the single-register GCC register classes map their values onto
12327 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
12328 // really want an 8-bit or 32-bit register, map to the appropriate register
12329 // class and return the appropriate register.
12330 if (Res.second == X86::GR16RegisterClass) {
12331 if (VT == MVT::i8) {
12332 unsigned DestReg = 0;
12333 switch (Res.first) {
12335 case X86::AX: DestReg = X86::AL; break;
12336 case X86::DX: DestReg = X86::DL; break;
12337 case X86::CX: DestReg = X86::CL; break;
12338 case X86::BX: DestReg = X86::BL; break;
12341 Res.first = DestReg;
12342 Res.second = X86::GR8RegisterClass;
12344 } else if (VT == MVT::i32) {
12345 unsigned DestReg = 0;
12346 switch (Res.first) {
12348 case X86::AX: DestReg = X86::EAX; break;
12349 case X86::DX: DestReg = X86::EDX; break;
12350 case X86::CX: DestReg = X86::ECX; break;
12351 case X86::BX: DestReg = X86::EBX; break;
12352 case X86::SI: DestReg = X86::ESI; break;
12353 case X86::DI: DestReg = X86::EDI; break;
12354 case X86::BP: DestReg = X86::EBP; break;
12355 case X86::SP: DestReg = X86::ESP; break;
12358 Res.first = DestReg;
12359 Res.second = X86::GR32RegisterClass;
12361 } else if (VT == MVT::i64) {
12362 unsigned DestReg = 0;
12363 switch (Res.first) {
12365 case X86::AX: DestReg = X86::RAX; break;
12366 case X86::DX: DestReg = X86::RDX; break;
12367 case X86::CX: DestReg = X86::RCX; break;
12368 case X86::BX: DestReg = X86::RBX; break;
12369 case X86::SI: DestReg = X86::RSI; break;
12370 case X86::DI: DestReg = X86::RDI; break;
12371 case X86::BP: DestReg = X86::RBP; break;
12372 case X86::SP: DestReg = X86::RSP; break;
12375 Res.first = DestReg;
12376 Res.second = X86::GR64RegisterClass;
12379 } else if (Res.second == X86::FR32RegisterClass ||
12380 Res.second == X86::FR64RegisterClass ||
12381 Res.second == X86::VR128RegisterClass) {
12382 // Handle references to XMM physical registers that got mapped into the
12383 // wrong class. This can happen with constraints like {xmm0} where the
12384 // target independent register mapper will just pick the first match it can
12385 // find, ignoring the required type.
12386 if (VT == MVT::f32)
12387 Res.second = X86::FR32RegisterClass;
12388 else if (VT == MVT::f64)
12389 Res.second = X86::FR64RegisterClass;
12390 else if (X86::VR128RegisterClass->hasType(VT))
12391 Res.second = X86::VR128RegisterClass;