1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/WinEHFuncInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 static cl::opt<int> ReciprocalEstimateRefinementSteps(
71 "x86-recip-refinement-steps", cl::init(1),
72 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
73 "result of the hardware reciprocal estimate instruction."),
76 // Forward declarations.
77 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
80 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
81 const X86Subtarget &STI)
82 : TargetLowering(TM), Subtarget(&STI) {
83 X86ScalarSSEf64 = Subtarget->hasSSE2();
84 X86ScalarSSEf32 = Subtarget->hasSSE1();
87 // Set up the TargetLowering object.
88 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
90 // X86 is weird. It always uses i8 for shift amounts and setcc results.
91 setBooleanContents(ZeroOrOneBooleanContent);
92 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
93 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
95 // For 64-bit, since we have so many registers, use the ILP scheduler.
96 // For 32-bit, use the register pressure specific scheduling.
97 // For Atom, always use ILP scheduling.
98 if (Subtarget->isAtom())
99 setSchedulingPreference(Sched::ILP);
100 else if (Subtarget->is64Bit())
101 setSchedulingPreference(Sched::ILP);
103 setSchedulingPreference(Sched::RegPressure);
104 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
105 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
107 // Bypass expensive divides on Atom when compiling with O2.
108 if (TM.getOptLevel() >= CodeGenOpt::Default) {
109 if (Subtarget->hasSlowDivide32())
110 addBypassSlowDiv(32, 8);
111 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
112 addBypassSlowDiv(64, 16);
115 if (Subtarget->isTargetKnownWindowsMSVC()) {
116 // Setup Windows compiler runtime calls.
117 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
118 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
119 setLibcallName(RTLIB::SREM_I64, "_allrem");
120 setLibcallName(RTLIB::UREM_I64, "_aullrem");
121 setLibcallName(RTLIB::MUL_I64, "_allmul");
122 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
123 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
124 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
125 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
126 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
128 // The _ftol2 runtime function has an unusual calling conv, which
129 // is modeled by a special pseudo-instruction.
130 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
131 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
132 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
133 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
136 if (Subtarget->isTargetDarwin()) {
137 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
138 setUseUnderscoreSetJmp(false);
139 setUseUnderscoreLongJmp(false);
140 } else if (Subtarget->isTargetWindowsGNU()) {
141 // MS runtime is weird: it exports _setjmp, but longjmp!
142 setUseUnderscoreSetJmp(true);
143 setUseUnderscoreLongJmp(false);
145 setUseUnderscoreSetJmp(true);
146 setUseUnderscoreLongJmp(true);
149 // Set up the register classes.
150 addRegisterClass(MVT::i8, &X86::GR8RegClass);
151 addRegisterClass(MVT::i16, &X86::GR16RegClass);
152 addRegisterClass(MVT::i32, &X86::GR32RegClass);
153 if (Subtarget->is64Bit())
154 addRegisterClass(MVT::i64, &X86::GR64RegClass);
156 for (MVT VT : MVT::integer_valuetypes())
157 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
159 // We don't accept any truncstore of integer registers.
160 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
161 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
162 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
163 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
164 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
165 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
167 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
169 // SETOEQ and SETUNE require checking two conditions.
170 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
171 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
172 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
173 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
174 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
175 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
177 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
179 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
180 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
181 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
183 if (Subtarget->is64Bit()) {
184 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
185 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
186 } else if (!TM.Options.UseSoftFloat) {
187 // We have an algorithm for SSE2->double, and we turn this into a
188 // 64-bit FILD followed by conditional FADD for other targets.
189 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
190 // We have an algorithm for SSE2, and we turn this into a 64-bit
191 // FILD for other targets.
192 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
195 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
197 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
200 if (!TM.Options.UseSoftFloat) {
201 // SSE has no i16 to fp conversion, only i32
202 if (X86ScalarSSEf32) {
203 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
204 // f32 and f64 cases are Legal, f80 case is not
205 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
207 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
208 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
211 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
212 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
215 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
216 // are Legal, f80 is custom lowered.
217 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
218 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
220 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
222 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
223 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
225 if (X86ScalarSSEf32) {
226 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
227 // f32 and f64 cases are Legal, f80 case is not
228 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
230 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
231 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
234 // Handle FP_TO_UINT by promoting the destination to a larger signed
236 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
237 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
238 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
240 if (Subtarget->is64Bit()) {
241 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
242 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
243 } else if (!TM.Options.UseSoftFloat) {
244 // Since AVX is a superset of SSE3, only check for SSE here.
245 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
246 // Expand FP_TO_UINT into a select.
247 // FIXME: We would like to use a Custom expander here eventually to do
248 // the optimal thing for SSE vs. the default expansion in the legalizer.
249 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
251 // With SSE3 we can use fisttpll to convert to a signed i64; without
252 // SSE, we're stuck with a fistpll.
253 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
256 if (isTargetFTOL()) {
257 // Use the _ftol2 runtime function, which has a pseudo-instruction
258 // to handle its weird calling convention.
259 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
262 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
263 if (!X86ScalarSSEf64) {
264 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
265 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
266 if (Subtarget->is64Bit()) {
267 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
268 // Without SSE, i64->f64 goes through memory.
269 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
273 // Scalar integer divide and remainder are lowered to use operations that
274 // produce two results, to match the available instructions. This exposes
275 // the two-result form to trivial CSE, which is able to combine x/y and x%y
276 // into a single instruction.
278 // Scalar integer multiply-high is also lowered to use two-result
279 // operations, to match the available instructions. However, plain multiply
280 // (low) operations are left as Legal, as there are single-result
281 // instructions for this in x86. Using the two-result multiply instructions
282 // when both high and low results are needed must be arranged by dagcombine.
283 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
285 setOperationAction(ISD::MULHS, VT, Expand);
286 setOperationAction(ISD::MULHU, VT, Expand);
287 setOperationAction(ISD::SDIV, VT, Expand);
288 setOperationAction(ISD::UDIV, VT, Expand);
289 setOperationAction(ISD::SREM, VT, Expand);
290 setOperationAction(ISD::UREM, VT, Expand);
292 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
293 setOperationAction(ISD::ADDC, VT, Custom);
294 setOperationAction(ISD::ADDE, VT, Custom);
295 setOperationAction(ISD::SUBC, VT, Custom);
296 setOperationAction(ISD::SUBE, VT, Custom);
299 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
300 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
301 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
302 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
303 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
304 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
305 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
306 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
307 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
308 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
309 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
310 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
311 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
312 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
313 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
314 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
315 if (Subtarget->is64Bit())
316 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
317 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
318 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
319 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
320 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
321 setOperationAction(ISD::FREM , MVT::f32 , Expand);
322 setOperationAction(ISD::FREM , MVT::f64 , Expand);
323 setOperationAction(ISD::FREM , MVT::f80 , Expand);
324 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
326 // Promote the i8 variants and force them on up to i32 which has a shorter
328 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
329 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
330 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
331 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
332 if (Subtarget->hasBMI()) {
333 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
334 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
335 if (Subtarget->is64Bit())
336 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
338 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
339 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
340 if (Subtarget->is64Bit())
341 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
344 if (Subtarget->hasLZCNT()) {
345 // When promoting the i8 variants, force them to i32 for a shorter
347 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
348 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
349 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
350 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
351 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
352 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
353 if (Subtarget->is64Bit())
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
356 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
357 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
358 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
360 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
361 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
362 if (Subtarget->is64Bit()) {
363 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
364 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
368 // Special handling for half-precision floating point conversions.
369 // If we don't have F16C support, then lower half float conversions
370 // into library calls.
371 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
372 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
373 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
376 // There's never any support for operations beyond MVT::f32.
377 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
378 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
379 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
380 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
382 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
383 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
384 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
385 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
386 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
387 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
389 if (Subtarget->hasPOPCNT()) {
390 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
392 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
393 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
394 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
395 if (Subtarget->is64Bit())
396 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
399 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
401 if (!Subtarget->hasMOVBE())
402 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
404 // These should be promoted to a larger select which is supported.
405 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
406 // X86 wants to expand cmov itself.
407 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
408 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
409 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
410 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
411 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
412 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
413 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
414 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
415 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
416 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
417 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
418 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
419 if (Subtarget->is64Bit()) {
420 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
421 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
423 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
424 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
425 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
426 // support continuation, user-level threading, and etc.. As a result, no
427 // other SjLj exception interfaces are implemented and please don't build
428 // your own exception handling based on them.
429 // LLVM/Clang supports zero-cost DWARF exception handling.
430 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
431 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
434 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
435 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
436 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
437 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
438 if (Subtarget->is64Bit())
439 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
440 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
441 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
442 if (Subtarget->is64Bit()) {
443 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
444 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
445 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
446 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
447 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
449 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
450 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
451 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
452 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
453 if (Subtarget->is64Bit()) {
454 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
455 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
456 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
459 if (Subtarget->hasSSE1())
460 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
462 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
464 // Expand certain atomics
465 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
467 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
468 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
469 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
472 if (Subtarget->hasCmpxchg16b()) {
473 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
476 // FIXME - use subtarget debug flags
477 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
478 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
479 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
482 if (Subtarget->is64Bit()) {
483 setExceptionPointerRegister(X86::RAX);
484 setExceptionSelectorRegister(X86::RDX);
486 setExceptionPointerRegister(X86::EAX);
487 setExceptionSelectorRegister(X86::EDX);
489 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
490 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
492 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
493 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
495 setOperationAction(ISD::TRAP, MVT::Other, Legal);
496 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
498 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
499 setOperationAction(ISD::VASTART , MVT::Other, Custom);
500 setOperationAction(ISD::VAEND , MVT::Other, Expand);
501 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
502 // TargetInfo::X86_64ABIBuiltinVaList
503 setOperationAction(ISD::VAARG , MVT::Other, Custom);
504 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
506 // TargetInfo::CharPtrBuiltinVaList
507 setOperationAction(ISD::VAARG , MVT::Other, Expand);
508 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
511 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
512 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
514 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
516 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
517 // f32 and f64 use SSE.
518 // Set up the FP register classes.
519 addRegisterClass(MVT::f32, &X86::FR32RegClass);
520 addRegisterClass(MVT::f64, &X86::FR64RegClass);
522 // Use ANDPD to simulate FABS.
523 setOperationAction(ISD::FABS , MVT::f64, Custom);
524 setOperationAction(ISD::FABS , MVT::f32, Custom);
526 // Use XORP to simulate FNEG.
527 setOperationAction(ISD::FNEG , MVT::f64, Custom);
528 setOperationAction(ISD::FNEG , MVT::f32, Custom);
530 // Use ANDPD and ORPD to simulate FCOPYSIGN.
531 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
532 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
534 // Lower this to FGETSIGNx86 plus an AND.
535 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
536 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
538 // We don't support sin/cos/fmod
539 setOperationAction(ISD::FSIN , MVT::f64, Expand);
540 setOperationAction(ISD::FCOS , MVT::f64, Expand);
541 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
542 setOperationAction(ISD::FSIN , MVT::f32, Expand);
543 setOperationAction(ISD::FCOS , MVT::f32, Expand);
544 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
546 // Expand FP immediates into loads from the stack, except for the special
548 addLegalFPImmediate(APFloat(+0.0)); // xorpd
549 addLegalFPImmediate(APFloat(+0.0f)); // xorps
550 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
551 // Use SSE for f32, x87 for f64.
552 // Set up the FP register classes.
553 addRegisterClass(MVT::f32, &X86::FR32RegClass);
554 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
556 // Use ANDPS to simulate FABS.
557 setOperationAction(ISD::FABS , MVT::f32, Custom);
559 // Use XORP to simulate FNEG.
560 setOperationAction(ISD::FNEG , MVT::f32, Custom);
562 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
564 // Use ANDPS and ORPS to simulate FCOPYSIGN.
565 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
566 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
568 // We don't support sin/cos/fmod
569 setOperationAction(ISD::FSIN , MVT::f32, Expand);
570 setOperationAction(ISD::FCOS , MVT::f32, Expand);
571 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
573 // Special cases we handle for FP constants.
574 addLegalFPImmediate(APFloat(+0.0f)); // xorps
575 addLegalFPImmediate(APFloat(+0.0)); // FLD0
576 addLegalFPImmediate(APFloat(+1.0)); // FLD1
577 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
578 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
580 if (!TM.Options.UnsafeFPMath) {
581 setOperationAction(ISD::FSIN , MVT::f64, Expand);
582 setOperationAction(ISD::FCOS , MVT::f64, Expand);
583 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
585 } else if (!TM.Options.UseSoftFloat) {
586 // f32 and f64 in x87.
587 // Set up the FP register classes.
588 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
589 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
591 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
592 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
593 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
594 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
596 if (!TM.Options.UnsafeFPMath) {
597 setOperationAction(ISD::FSIN , MVT::f64, Expand);
598 setOperationAction(ISD::FSIN , MVT::f32, Expand);
599 setOperationAction(ISD::FCOS , MVT::f64, Expand);
600 setOperationAction(ISD::FCOS , MVT::f32, Expand);
601 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
602 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
604 addLegalFPImmediate(APFloat(+0.0)); // FLD0
605 addLegalFPImmediate(APFloat(+1.0)); // FLD1
606 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
607 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
608 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
609 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
610 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
611 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
614 // We don't support FMA.
615 setOperationAction(ISD::FMA, MVT::f64, Expand);
616 setOperationAction(ISD::FMA, MVT::f32, Expand);
618 // Long double always uses X87.
619 if (!TM.Options.UseSoftFloat) {
620 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
621 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
622 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
624 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
625 addLegalFPImmediate(TmpFlt); // FLD0
627 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
630 APFloat TmpFlt2(+1.0);
631 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
633 addLegalFPImmediate(TmpFlt2); // FLD1
634 TmpFlt2.changeSign();
635 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
638 if (!TM.Options.UnsafeFPMath) {
639 setOperationAction(ISD::FSIN , MVT::f80, Expand);
640 setOperationAction(ISD::FCOS , MVT::f80, Expand);
641 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
644 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
645 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
646 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
647 setOperationAction(ISD::FRINT, MVT::f80, Expand);
648 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
649 setOperationAction(ISD::FMA, MVT::f80, Expand);
652 // Always use a library call for pow.
653 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
654 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
655 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
657 setOperationAction(ISD::FLOG, MVT::f80, Expand);
658 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
659 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
660 setOperationAction(ISD::FEXP, MVT::f80, Expand);
661 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
662 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
663 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
665 // First set operation action for all vector types to either promote
666 // (for widening) or expand (for scalarization). Then we will selectively
667 // turn on ones that can be effectively codegen'd.
668 for (MVT VT : MVT::vector_valuetypes()) {
669 setOperationAction(ISD::ADD , VT, Expand);
670 setOperationAction(ISD::SUB , VT, Expand);
671 setOperationAction(ISD::FADD, VT, Expand);
672 setOperationAction(ISD::FNEG, VT, Expand);
673 setOperationAction(ISD::FSUB, VT, Expand);
674 setOperationAction(ISD::MUL , VT, Expand);
675 setOperationAction(ISD::FMUL, VT, Expand);
676 setOperationAction(ISD::SDIV, VT, Expand);
677 setOperationAction(ISD::UDIV, VT, Expand);
678 setOperationAction(ISD::FDIV, VT, Expand);
679 setOperationAction(ISD::SREM, VT, Expand);
680 setOperationAction(ISD::UREM, VT, Expand);
681 setOperationAction(ISD::LOAD, VT, Expand);
682 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
683 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
684 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
685 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
686 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
687 setOperationAction(ISD::FABS, VT, Expand);
688 setOperationAction(ISD::FSIN, VT, Expand);
689 setOperationAction(ISD::FSINCOS, VT, Expand);
690 setOperationAction(ISD::FCOS, VT, Expand);
691 setOperationAction(ISD::FSINCOS, VT, Expand);
692 setOperationAction(ISD::FREM, VT, Expand);
693 setOperationAction(ISD::FMA, VT, Expand);
694 setOperationAction(ISD::FPOWI, VT, Expand);
695 setOperationAction(ISD::FSQRT, VT, Expand);
696 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
697 setOperationAction(ISD::FFLOOR, VT, Expand);
698 setOperationAction(ISD::FCEIL, VT, Expand);
699 setOperationAction(ISD::FTRUNC, VT, Expand);
700 setOperationAction(ISD::FRINT, VT, Expand);
701 setOperationAction(ISD::FNEARBYINT, VT, Expand);
702 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
703 setOperationAction(ISD::MULHS, VT, Expand);
704 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
705 setOperationAction(ISD::MULHU, VT, Expand);
706 setOperationAction(ISD::SDIVREM, VT, Expand);
707 setOperationAction(ISD::UDIVREM, VT, Expand);
708 setOperationAction(ISD::FPOW, VT, Expand);
709 setOperationAction(ISD::CTPOP, VT, Expand);
710 setOperationAction(ISD::CTTZ, VT, Expand);
711 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
712 setOperationAction(ISD::CTLZ, VT, Expand);
713 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
714 setOperationAction(ISD::SHL, VT, Expand);
715 setOperationAction(ISD::SRA, VT, Expand);
716 setOperationAction(ISD::SRL, VT, Expand);
717 setOperationAction(ISD::ROTL, VT, Expand);
718 setOperationAction(ISD::ROTR, VT, Expand);
719 setOperationAction(ISD::BSWAP, VT, Expand);
720 setOperationAction(ISD::SETCC, VT, Expand);
721 setOperationAction(ISD::FLOG, VT, Expand);
722 setOperationAction(ISD::FLOG2, VT, Expand);
723 setOperationAction(ISD::FLOG10, VT, Expand);
724 setOperationAction(ISD::FEXP, VT, Expand);
725 setOperationAction(ISD::FEXP2, VT, Expand);
726 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
727 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
728 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
729 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
730 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
731 setOperationAction(ISD::TRUNCATE, VT, Expand);
732 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
733 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
734 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
735 setOperationAction(ISD::VSELECT, VT, Expand);
736 setOperationAction(ISD::SELECT_CC, VT, Expand);
737 for (MVT InnerVT : MVT::vector_valuetypes()) {
738 setTruncStoreAction(InnerVT, VT, Expand);
740 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
741 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
743 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
744 // types, we have to deal with them whether we ask for Expansion or not.
745 // Setting Expand causes its own optimisation problems though, so leave
747 if (VT.getVectorElementType() == MVT::i1)
748 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
752 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
753 // with -msoft-float, disable use of MMX as well.
754 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
755 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
756 // No operations on x86mmx supported, everything uses intrinsics.
759 // MMX-sized vectors (other than x86mmx) are expected to be expanded
760 // into smaller operations.
761 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
762 setOperationAction(ISD::MULHS, MMXTy, Expand);
763 setOperationAction(ISD::AND, MMXTy, Expand);
764 setOperationAction(ISD::OR, MMXTy, Expand);
765 setOperationAction(ISD::XOR, MMXTy, Expand);
766 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
767 setOperationAction(ISD::SELECT, MMXTy, Expand);
768 setOperationAction(ISD::BITCAST, MMXTy, Expand);
770 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
772 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
773 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
775 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
776 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
777 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
778 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
779 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
780 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
781 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
782 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
783 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
784 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
785 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
786 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
787 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
788 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
791 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
792 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
794 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
795 // registers cannot be used even for integer operations.
796 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
797 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
798 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
799 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
801 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
802 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
803 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
804 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
805 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
806 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
807 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
808 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
809 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
810 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
811 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
812 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
813 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
814 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
815 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
816 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
817 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
818 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
819 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
820 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
821 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
822 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
824 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
825 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
826 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
827 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
829 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
830 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
831 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
832 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
833 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
835 // Only provide customized ctpop vector bit twiddling for vector types we
836 // know to perform better than using the popcnt instructions on each vector
837 // element. If popcnt isn't supported, always provide the custom version.
838 if (!Subtarget->hasPOPCNT()) {
839 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
840 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
843 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
844 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
845 MVT VT = (MVT::SimpleValueType)i;
846 // Do not attempt to custom lower non-power-of-2 vectors
847 if (!isPowerOf2_32(VT.getVectorNumElements()))
849 // Do not attempt to custom lower non-128-bit vectors
850 if (!VT.is128BitVector())
852 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
853 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
854 setOperationAction(ISD::VSELECT, VT, Custom);
855 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
858 // We support custom legalizing of sext and anyext loads for specific
859 // memory vector types which we can load as a scalar (or sequence of
860 // scalars) and extend in-register to a legal 128-bit vector type. For sext
861 // loads these must work with a single scalar load.
862 for (MVT VT : MVT::integer_vector_valuetypes()) {
863 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
864 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
865 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
866 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
867 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
868 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
869 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
870 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
871 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
874 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
875 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
876 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
877 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
878 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
879 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
880 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
881 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
883 if (Subtarget->is64Bit()) {
884 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
885 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
888 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
889 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
890 MVT VT = (MVT::SimpleValueType)i;
892 // Do not attempt to promote non-128-bit vectors
893 if (!VT.is128BitVector())
896 setOperationAction(ISD::AND, VT, Promote);
897 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
898 setOperationAction(ISD::OR, VT, Promote);
899 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
900 setOperationAction(ISD::XOR, VT, Promote);
901 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
902 setOperationAction(ISD::LOAD, VT, Promote);
903 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
904 setOperationAction(ISD::SELECT, VT, Promote);
905 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
908 // Custom lower v2i64 and v2f64 selects.
909 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
910 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
911 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
912 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
914 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
915 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
917 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
918 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
919 // As there is no 64-bit GPR available, we need build a special custom
920 // sequence to convert from v2i32 to v2f32.
921 if (!Subtarget->is64Bit())
922 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
924 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
925 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
927 for (MVT VT : MVT::fp_vector_valuetypes())
928 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
930 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
931 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
932 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
935 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
936 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
937 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
938 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
939 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
940 setOperationAction(ISD::FRINT, RoundedTy, Legal);
941 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
944 // FIXME: Do we need to handle scalar-to-vector here?
945 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
947 // We directly match byte blends in the backend as they match the VSELECT
949 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
951 // SSE41 brings specific instructions for doing vector sign extend even in
952 // cases where we don't have SRA.
953 for (MVT VT : MVT::integer_vector_valuetypes()) {
954 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
955 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
956 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
959 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
960 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
961 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
962 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
963 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
964 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
965 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
967 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
968 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
969 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
970 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
971 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
972 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
974 // i8 and i16 vectors are custom because the source register and source
975 // source memory operand types are not the same width. f32 vectors are
976 // custom since the immediate controlling the insert encodes additional
978 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
979 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
980 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
981 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
983 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
984 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
985 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
986 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
988 // FIXME: these should be Legal, but that's only for the case where
989 // the index is constant. For now custom expand to deal with that.
990 if (Subtarget->is64Bit()) {
991 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
992 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
996 if (Subtarget->hasSSE2()) {
997 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
998 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1000 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1001 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1003 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1004 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1006 // In the customized shift lowering, the legal cases in AVX2 will be
1008 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1009 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1011 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1012 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1014 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1017 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1018 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1019 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1020 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1021 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1022 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1023 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1025 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1026 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1027 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1029 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1030 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1031 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1032 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1033 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1034 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1035 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1036 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1037 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1038 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1039 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1040 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1042 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1043 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1044 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1045 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1046 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1047 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1048 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1049 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1050 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1051 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1052 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1053 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1055 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1056 // even though v8i16 is a legal type.
1057 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1058 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1059 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1061 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1062 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1063 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1065 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1066 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1068 for (MVT VT : MVT::fp_vector_valuetypes())
1069 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1071 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1072 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1074 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1075 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1077 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1078 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1080 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1081 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1082 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1083 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1085 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1086 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1087 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1089 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1090 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1091 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1092 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1093 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1094 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1095 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1096 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1097 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1098 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1099 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1100 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1102 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1103 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1104 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1105 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1106 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1107 setOperationAction(ISD::FMA, MVT::f32, Legal);
1108 setOperationAction(ISD::FMA, MVT::f64, Legal);
1111 if (Subtarget->hasInt256()) {
1112 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1113 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1114 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1115 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1117 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1118 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1119 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1120 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1122 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1123 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1124 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1125 // Don't lower v32i8 because there is no 128-bit byte mul
1127 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1128 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1129 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1130 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1132 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1133 // when we have a 256bit-wide blend with immediate.
1134 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1136 // Only provide customized ctpop vector bit twiddling for vector types we
1137 // know to perform better than using the popcnt instructions on each
1138 // vector element. If popcnt isn't supported, always provide the custom
1140 if (!Subtarget->hasPOPCNT())
1141 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1143 // Custom CTPOP always performs better on natively supported v8i32
1144 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1146 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1147 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1148 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1149 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1150 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1151 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1152 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1154 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1155 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1156 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1157 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1158 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1159 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1161 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1162 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1163 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1164 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1166 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1167 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1168 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1169 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1171 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1172 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1173 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1174 // Don't lower v32i8 because there is no 128-bit byte mul
1177 // In the customized shift lowering, the legal cases in AVX2 will be
1179 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1180 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1182 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1183 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1185 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1187 // Custom lower several nodes for 256-bit types.
1188 for (MVT VT : MVT::vector_valuetypes()) {
1189 if (VT.getScalarSizeInBits() >= 32) {
1190 setOperationAction(ISD::MLOAD, VT, Legal);
1191 setOperationAction(ISD::MSTORE, VT, Legal);
1193 // Extract subvector is special because the value type
1194 // (result) is 128-bit but the source is 256-bit wide.
1195 if (VT.is128BitVector()) {
1196 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1198 // Do not attempt to custom lower other non-256-bit vectors
1199 if (!VT.is256BitVector())
1202 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1203 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1204 setOperationAction(ISD::VSELECT, VT, Custom);
1205 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1206 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1207 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1208 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1209 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1212 if (Subtarget->hasInt256())
1213 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1216 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1217 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1218 MVT VT = (MVT::SimpleValueType)i;
1220 // Do not attempt to promote non-256-bit vectors
1221 if (!VT.is256BitVector())
1224 setOperationAction(ISD::AND, VT, Promote);
1225 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1226 setOperationAction(ISD::OR, VT, Promote);
1227 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1228 setOperationAction(ISD::XOR, VT, Promote);
1229 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1230 setOperationAction(ISD::LOAD, VT, Promote);
1231 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1232 setOperationAction(ISD::SELECT, VT, Promote);
1233 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1237 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1238 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1239 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1240 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1241 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1243 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1244 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1245 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1247 for (MVT VT : MVT::fp_vector_valuetypes())
1248 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1250 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1251 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1252 setOperationAction(ISD::XOR, MVT::i1, Legal);
1253 setOperationAction(ISD::OR, MVT::i1, Legal);
1254 setOperationAction(ISD::AND, MVT::i1, Legal);
1255 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1256 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1257 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1258 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1259 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1261 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1262 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1263 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1264 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1265 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1266 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1268 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1269 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1270 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1271 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1272 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1273 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1274 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1275 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1277 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1278 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1279 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1280 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1281 if (Subtarget->is64Bit()) {
1282 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1283 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1284 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1285 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1287 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1288 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1289 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1290 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1291 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1292 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1293 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1294 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1295 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1296 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1297 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1298 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1299 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1300 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1302 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1303 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1304 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1305 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1306 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1307 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1308 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1309 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1310 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1311 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1312 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1313 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1314 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1316 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1317 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1318 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1319 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1320 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1321 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1322 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1323 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1324 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1325 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1327 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1328 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1329 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1330 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1331 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1333 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1334 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1336 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1338 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1339 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1340 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1341 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1342 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1343 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1344 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1345 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1346 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1348 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1349 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1351 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1352 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1354 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1356 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1357 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1359 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1360 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1362 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1363 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1365 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1366 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1367 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1368 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1369 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1370 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1372 if (Subtarget->hasCDI()) {
1373 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1374 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1377 // Custom lower several nodes.
1378 for (MVT VT : MVT::vector_valuetypes()) {
1379 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1380 // Extract subvector is special because the value type
1381 // (result) is 256/128-bit but the source is 512-bit wide.
1382 if (VT.is128BitVector() || VT.is256BitVector()) {
1383 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1385 if (VT.getVectorElementType() == MVT::i1)
1386 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1388 // Do not attempt to custom lower other non-512-bit vectors
1389 if (!VT.is512BitVector())
1392 if ( EltSize >= 32) {
1393 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1394 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1395 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1396 setOperationAction(ISD::VSELECT, VT, Legal);
1397 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1398 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1399 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1400 setOperationAction(ISD::MLOAD, VT, Legal);
1401 setOperationAction(ISD::MSTORE, VT, Legal);
1404 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1405 MVT VT = (MVT::SimpleValueType)i;
1407 // Do not attempt to promote non-512-bit vectors.
1408 if (!VT.is512BitVector())
1411 setOperationAction(ISD::SELECT, VT, Promote);
1412 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1416 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1417 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1418 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1420 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1421 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1423 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1424 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1425 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1426 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1427 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1428 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1429 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1430 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1431 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1432 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1433 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1434 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1435 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1437 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1438 const MVT VT = (MVT::SimpleValueType)i;
1440 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1442 // Do not attempt to promote non-512-bit vectors.
1443 if (!VT.is512BitVector())
1447 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1448 setOperationAction(ISD::VSELECT, VT, Legal);
1453 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1454 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1455 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1457 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1458 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1459 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1460 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1461 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1462 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1464 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1465 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1466 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1467 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1468 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1469 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1472 // We want to custom lower some of our intrinsics.
1473 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1474 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1475 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1476 if (!Subtarget->is64Bit())
1477 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1479 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1480 // handle type legalization for these operations here.
1482 // FIXME: We really should do custom legalization for addition and
1483 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1484 // than generic legalization for 64-bit multiplication-with-overflow, though.
1485 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1486 // Add/Sub/Mul with overflow operations are custom lowered.
1488 setOperationAction(ISD::SADDO, VT, Custom);
1489 setOperationAction(ISD::UADDO, VT, Custom);
1490 setOperationAction(ISD::SSUBO, VT, Custom);
1491 setOperationAction(ISD::USUBO, VT, Custom);
1492 setOperationAction(ISD::SMULO, VT, Custom);
1493 setOperationAction(ISD::UMULO, VT, Custom);
1497 if (!Subtarget->is64Bit()) {
1498 // These libcalls are not available in 32-bit.
1499 setLibcallName(RTLIB::SHL_I128, nullptr);
1500 setLibcallName(RTLIB::SRL_I128, nullptr);
1501 setLibcallName(RTLIB::SRA_I128, nullptr);
1504 // Combine sin / cos into one node or libcall if possible.
1505 if (Subtarget->hasSinCos()) {
1506 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1507 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1508 if (Subtarget->isTargetDarwin()) {
1509 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1510 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1511 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1512 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1516 if (Subtarget->isTargetWin64()) {
1517 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1518 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1519 setOperationAction(ISD::SREM, MVT::i128, Custom);
1520 setOperationAction(ISD::UREM, MVT::i128, Custom);
1521 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1522 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1525 // We have target-specific dag combine patterns for the following nodes:
1526 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1527 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1528 setTargetDAGCombine(ISD::BITCAST);
1529 setTargetDAGCombine(ISD::VSELECT);
1530 setTargetDAGCombine(ISD::SELECT);
1531 setTargetDAGCombine(ISD::SHL);
1532 setTargetDAGCombine(ISD::SRA);
1533 setTargetDAGCombine(ISD::SRL);
1534 setTargetDAGCombine(ISD::OR);
1535 setTargetDAGCombine(ISD::AND);
1536 setTargetDAGCombine(ISD::ADD);
1537 setTargetDAGCombine(ISD::FADD);
1538 setTargetDAGCombine(ISD::FSUB);
1539 setTargetDAGCombine(ISD::FMA);
1540 setTargetDAGCombine(ISD::SUB);
1541 setTargetDAGCombine(ISD::LOAD);
1542 setTargetDAGCombine(ISD::MLOAD);
1543 setTargetDAGCombine(ISD::STORE);
1544 setTargetDAGCombine(ISD::MSTORE);
1545 setTargetDAGCombine(ISD::ZERO_EXTEND);
1546 setTargetDAGCombine(ISD::ANY_EXTEND);
1547 setTargetDAGCombine(ISD::SIGN_EXTEND);
1548 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1549 setTargetDAGCombine(ISD::TRUNCATE);
1550 setTargetDAGCombine(ISD::SINT_TO_FP);
1551 setTargetDAGCombine(ISD::SETCC);
1552 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1553 setTargetDAGCombine(ISD::BUILD_VECTOR);
1554 setTargetDAGCombine(ISD::MUL);
1555 setTargetDAGCombine(ISD::XOR);
1557 computeRegisterProperties(Subtarget->getRegisterInfo());
1559 // On Darwin, -Os means optimize for size without hurting performance,
1560 // do not reduce the limit.
1561 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1562 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1563 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1564 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1565 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1566 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1567 setPrefLoopAlignment(4); // 2^4 bytes.
1569 // Predictable cmov don't hurt on atom because it's in-order.
1570 PredictableSelectIsExpensive = !Subtarget->isAtom();
1571 EnableExtLdPromotion = true;
1572 setPrefFunctionAlignment(4); // 2^4 bytes.
1574 verifyIntrinsicTables();
1577 // This has so far only been implemented for 64-bit MachO.
1578 bool X86TargetLowering::useLoadStackGuardNode() const {
1579 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1582 TargetLoweringBase::LegalizeTypeAction
1583 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1584 if (ExperimentalVectorWideningLegalization &&
1585 VT.getVectorNumElements() != 1 &&
1586 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1587 return TypeWidenVector;
1589 return TargetLoweringBase::getPreferredVectorAction(VT);
1592 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1594 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1596 const unsigned NumElts = VT.getVectorNumElements();
1597 const EVT EltVT = VT.getVectorElementType();
1598 if (VT.is512BitVector()) {
1599 if (Subtarget->hasAVX512())
1600 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1601 EltVT == MVT::f32 || EltVT == MVT::f64)
1603 case 8: return MVT::v8i1;
1604 case 16: return MVT::v16i1;
1606 if (Subtarget->hasBWI())
1607 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1609 case 32: return MVT::v32i1;
1610 case 64: return MVT::v64i1;
1614 if (VT.is256BitVector() || VT.is128BitVector()) {
1615 if (Subtarget->hasVLX())
1616 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1617 EltVT == MVT::f32 || EltVT == MVT::f64)
1619 case 2: return MVT::v2i1;
1620 case 4: return MVT::v4i1;
1621 case 8: return MVT::v8i1;
1623 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1624 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1626 case 8: return MVT::v8i1;
1627 case 16: return MVT::v16i1;
1628 case 32: return MVT::v32i1;
1632 return VT.changeVectorElementTypeToInteger();
1635 /// Helper for getByValTypeAlignment to determine
1636 /// the desired ByVal argument alignment.
1637 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1640 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1641 if (VTy->getBitWidth() == 128)
1643 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1644 unsigned EltAlign = 0;
1645 getMaxByValAlign(ATy->getElementType(), EltAlign);
1646 if (EltAlign > MaxAlign)
1647 MaxAlign = EltAlign;
1648 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1649 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1650 unsigned EltAlign = 0;
1651 getMaxByValAlign(STy->getElementType(i), EltAlign);
1652 if (EltAlign > MaxAlign)
1653 MaxAlign = EltAlign;
1660 /// Return the desired alignment for ByVal aggregate
1661 /// function arguments in the caller parameter area. For X86, aggregates
1662 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1663 /// are at 4-byte boundaries.
1664 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1665 if (Subtarget->is64Bit()) {
1666 // Max of 8 and alignment of type.
1667 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1674 if (Subtarget->hasSSE1())
1675 getMaxByValAlign(Ty, Align);
1679 /// Returns the target specific optimal type for load
1680 /// and store operations as a result of memset, memcpy, and memmove
1681 /// lowering. If DstAlign is zero that means it's safe to destination
1682 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1683 /// means there isn't a need to check it against alignment requirement,
1684 /// probably because the source does not need to be loaded. If 'IsMemset' is
1685 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1686 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1687 /// source is constant so it does not need to be loaded.
1688 /// It returns EVT::Other if the type should be determined using generic
1689 /// target-independent logic.
1691 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1692 unsigned DstAlign, unsigned SrcAlign,
1693 bool IsMemset, bool ZeroMemset,
1695 MachineFunction &MF) const {
1696 const Function *F = MF.getFunction();
1697 if ((!IsMemset || ZeroMemset) &&
1698 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1700 (Subtarget->isUnalignedMemAccessFast() ||
1701 ((DstAlign == 0 || DstAlign >= 16) &&
1702 (SrcAlign == 0 || SrcAlign >= 16)))) {
1704 if (Subtarget->hasInt256())
1706 if (Subtarget->hasFp256())
1709 if (Subtarget->hasSSE2())
1711 if (Subtarget->hasSSE1())
1713 } else if (!MemcpyStrSrc && Size >= 8 &&
1714 !Subtarget->is64Bit() &&
1715 Subtarget->hasSSE2()) {
1716 // Do not use f64 to lower memcpy if source is string constant. It's
1717 // better to use i32 to avoid the loads.
1721 if (Subtarget->is64Bit() && Size >= 8)
1726 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1728 return X86ScalarSSEf32;
1729 else if (VT == MVT::f64)
1730 return X86ScalarSSEf64;
1735 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1740 *Fast = Subtarget->isUnalignedMemAccessFast();
1744 /// Return the entry encoding for a jump table in the
1745 /// current function. The returned value is a member of the
1746 /// MachineJumpTableInfo::JTEntryKind enum.
1747 unsigned X86TargetLowering::getJumpTableEncoding() const {
1748 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1750 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1751 Subtarget->isPICStyleGOT())
1752 return MachineJumpTableInfo::EK_Custom32;
1754 // Otherwise, use the normal jump table encoding heuristics.
1755 return TargetLowering::getJumpTableEncoding();
1759 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1760 const MachineBasicBlock *MBB,
1761 unsigned uid,MCContext &Ctx) const{
1762 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1763 Subtarget->isPICStyleGOT());
1764 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1766 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1767 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1770 /// Returns relocation base for the given PIC jumptable.
1771 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1772 SelectionDAG &DAG) const {
1773 if (!Subtarget->is64Bit())
1774 // This doesn't have SDLoc associated with it, but is not really the
1775 // same as a Register.
1776 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1780 /// This returns the relocation base for the given PIC jumptable,
1781 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
1782 const MCExpr *X86TargetLowering::
1783 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1784 MCContext &Ctx) const {
1785 // X86-64 uses RIP relative addressing based on the jump table label.
1786 if (Subtarget->isPICStyleRIPRel())
1787 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1789 // Otherwise, the reference is relative to the PIC base.
1790 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1793 std::pair<const TargetRegisterClass *, uint8_t>
1794 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1796 const TargetRegisterClass *RRC = nullptr;
1798 switch (VT.SimpleTy) {
1800 return TargetLowering::findRepresentativeClass(TRI, VT);
1801 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1802 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1805 RRC = &X86::VR64RegClass;
1807 case MVT::f32: case MVT::f64:
1808 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1809 case MVT::v4f32: case MVT::v2f64:
1810 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1812 RRC = &X86::VR128RegClass;
1815 return std::make_pair(RRC, Cost);
1818 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1819 unsigned &Offset) const {
1820 if (!Subtarget->isTargetLinux())
1823 if (Subtarget->is64Bit()) {
1824 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1826 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1838 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1839 unsigned DestAS) const {
1840 assert(SrcAS != DestAS && "Expected different address spaces!");
1842 return SrcAS < 256 && DestAS < 256;
1845 //===----------------------------------------------------------------------===//
1846 // Return Value Calling Convention Implementation
1847 //===----------------------------------------------------------------------===//
1849 #include "X86GenCallingConv.inc"
1852 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1853 MachineFunction &MF, bool isVarArg,
1854 const SmallVectorImpl<ISD::OutputArg> &Outs,
1855 LLVMContext &Context) const {
1856 SmallVector<CCValAssign, 16> RVLocs;
1857 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1858 return CCInfo.CheckReturn(Outs, RetCC_X86);
1861 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1862 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1867 X86TargetLowering::LowerReturn(SDValue Chain,
1868 CallingConv::ID CallConv, bool isVarArg,
1869 const SmallVectorImpl<ISD::OutputArg> &Outs,
1870 const SmallVectorImpl<SDValue> &OutVals,
1871 SDLoc dl, SelectionDAG &DAG) const {
1872 MachineFunction &MF = DAG.getMachineFunction();
1873 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1875 SmallVector<CCValAssign, 16> RVLocs;
1876 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1877 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1880 SmallVector<SDValue, 6> RetOps;
1881 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1882 // Operand #1 = Bytes To Pop
1883 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1886 // Copy the result values into the output registers.
1887 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1888 CCValAssign &VA = RVLocs[i];
1889 assert(VA.isRegLoc() && "Can only return in registers!");
1890 SDValue ValToCopy = OutVals[i];
1891 EVT ValVT = ValToCopy.getValueType();
1893 // Promote values to the appropriate types.
1894 if (VA.getLocInfo() == CCValAssign::SExt)
1895 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1896 else if (VA.getLocInfo() == CCValAssign::ZExt)
1897 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1898 else if (VA.getLocInfo() == CCValAssign::AExt)
1899 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1900 else if (VA.getLocInfo() == CCValAssign::BCvt)
1901 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1903 assert(VA.getLocInfo() != CCValAssign::FPExt &&
1904 "Unexpected FP-extend for return value.");
1906 // If this is x86-64, and we disabled SSE, we can't return FP values,
1907 // or SSE or MMX vectors.
1908 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1909 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1910 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1911 report_fatal_error("SSE register return with SSE disabled");
1913 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1914 // llvm-gcc has never done it right and no one has noticed, so this
1915 // should be OK for now.
1916 if (ValVT == MVT::f64 &&
1917 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1918 report_fatal_error("SSE2 register return with SSE2 disabled");
1920 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1921 // the RET instruction and handled by the FP Stackifier.
1922 if (VA.getLocReg() == X86::FP0 ||
1923 VA.getLocReg() == X86::FP1) {
1924 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1925 // change the value to the FP stack register class.
1926 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1927 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1928 RetOps.push_back(ValToCopy);
1929 // Don't emit a copytoreg.
1933 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1934 // which is returned in RAX / RDX.
1935 if (Subtarget->is64Bit()) {
1936 if (ValVT == MVT::x86mmx) {
1937 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1938 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1939 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1941 // If we don't have SSE2 available, convert to v4f32 so the generated
1942 // register is legal.
1943 if (!Subtarget->hasSSE2())
1944 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1949 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1950 Flag = Chain.getValue(1);
1951 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1954 // The x86-64 ABIs require that for returning structs by value we copy
1955 // the sret argument into %rax/%eax (depending on ABI) for the return.
1956 // Win32 requires us to put the sret argument to %eax as well.
1957 // We saved the argument into a virtual register in the entry block,
1958 // so now we copy the value out and into %rax/%eax.
1960 // Checking Function.hasStructRetAttr() here is insufficient because the IR
1961 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
1962 // false, then an sret argument may be implicitly inserted in the SelDAG. In
1963 // either case FuncInfo->setSRetReturnReg() will have been called.
1964 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
1965 assert((Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) &&
1966 "No need for an sret register");
1967 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg, getPointerTy());
1970 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
1971 X86::RAX : X86::EAX;
1972 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1973 Flag = Chain.getValue(1);
1975 // RAX/EAX now acts like a return value.
1976 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
1979 RetOps[0] = Chain; // Update chain.
1981 // Add the flag if we have it.
1983 RetOps.push_back(Flag);
1985 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
1988 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1989 if (N->getNumValues() != 1)
1991 if (!N->hasNUsesOfValue(1, 0))
1994 SDValue TCChain = Chain;
1995 SDNode *Copy = *N->use_begin();
1996 if (Copy->getOpcode() == ISD::CopyToReg) {
1997 // If the copy has a glue operand, we conservatively assume it isn't safe to
1998 // perform a tail call.
1999 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2001 TCChain = Copy->getOperand(0);
2002 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2005 bool HasRet = false;
2006 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2008 if (UI->getOpcode() != X86ISD::RET_FLAG)
2010 // If we are returning more than one value, we can definitely
2011 // not make a tail call see PR19530
2012 if (UI->getNumOperands() > 4)
2014 if (UI->getNumOperands() == 4 &&
2015 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2028 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2029 ISD::NodeType ExtendKind) const {
2031 // TODO: Is this also valid on 32-bit?
2032 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2033 ReturnMVT = MVT::i8;
2035 ReturnMVT = MVT::i32;
2037 EVT MinVT = getRegisterType(Context, ReturnMVT);
2038 return VT.bitsLT(MinVT) ? MinVT : VT;
2041 /// Lower the result values of a call into the
2042 /// appropriate copies out of appropriate physical registers.
2045 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2046 CallingConv::ID CallConv, bool isVarArg,
2047 const SmallVectorImpl<ISD::InputArg> &Ins,
2048 SDLoc dl, SelectionDAG &DAG,
2049 SmallVectorImpl<SDValue> &InVals) const {
2051 // Assign locations to each value returned by this call.
2052 SmallVector<CCValAssign, 16> RVLocs;
2053 bool Is64Bit = Subtarget->is64Bit();
2054 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2056 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2058 // Copy all of the result registers out of their specified physreg.
2059 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2060 CCValAssign &VA = RVLocs[i];
2061 EVT CopyVT = VA.getValVT();
2063 // If this is x86-64, and we disabled SSE, we can't return FP values
2064 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2065 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2066 report_fatal_error("SSE register return with SSE disabled");
2069 // If we prefer to use the value in xmm registers, copy it out as f80 and
2070 // use a truncate to move it from fp stack reg to xmm reg.
2071 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2072 isScalarFPTypeInSSEReg(VA.getValVT()))
2075 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2076 CopyVT, InFlag).getValue(1);
2077 SDValue Val = Chain.getValue(0);
2079 if (CopyVT != VA.getValVT())
2080 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2081 // This truncation won't change the value.
2082 DAG.getIntPtrConstant(1));
2084 InFlag = Chain.getValue(2);
2085 InVals.push_back(Val);
2091 //===----------------------------------------------------------------------===//
2092 // C & StdCall & Fast Calling Convention implementation
2093 //===----------------------------------------------------------------------===//
2094 // StdCall calling convention seems to be standard for many Windows' API
2095 // routines and around. It differs from C calling convention just a little:
2096 // callee should clean up the stack, not caller. Symbols should be also
2097 // decorated in some fancy way :) It doesn't support any vector arguments.
2098 // For info on fast calling convention see Fast Calling Convention (tail call)
2099 // implementation LowerX86_32FastCCCallTo.
2101 /// CallIsStructReturn - Determines whether a call uses struct return
2103 enum StructReturnType {
2108 static StructReturnType
2109 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2111 return NotStructReturn;
2113 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2114 if (!Flags.isSRet())
2115 return NotStructReturn;
2116 if (Flags.isInReg())
2117 return RegStructReturn;
2118 return StackStructReturn;
2121 /// Determines whether a function uses struct return semantics.
2122 static StructReturnType
2123 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2125 return NotStructReturn;
2127 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2128 if (!Flags.isSRet())
2129 return NotStructReturn;
2130 if (Flags.isInReg())
2131 return RegStructReturn;
2132 return StackStructReturn;
2135 /// Make a copy of an aggregate at address specified by "Src" to address
2136 /// "Dst" with size and alignment information specified by the specific
2137 /// parameter attribute. The copy will be passed as a byval function parameter.
2139 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2140 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2142 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2144 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2145 /*isVolatile*/false, /*AlwaysInline=*/true,
2146 /*isTailCall*/false,
2147 MachinePointerInfo(), MachinePointerInfo());
2150 /// Return true if the calling convention is one that
2151 /// supports tail call optimization.
2152 static bool IsTailCallConvention(CallingConv::ID CC) {
2153 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2154 CC == CallingConv::HiPE);
2157 /// \brief Return true if the calling convention is a C calling convention.
2158 static bool IsCCallConvention(CallingConv::ID CC) {
2159 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2160 CC == CallingConv::X86_64_SysV);
2163 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2164 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2168 CallingConv::ID CalleeCC = CS.getCallingConv();
2169 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2175 /// Return true if the function is being made into
2176 /// a tailcall target by changing its ABI.
2177 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2178 bool GuaranteedTailCallOpt) {
2179 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2183 X86TargetLowering::LowerMemArgument(SDValue Chain,
2184 CallingConv::ID CallConv,
2185 const SmallVectorImpl<ISD::InputArg> &Ins,
2186 SDLoc dl, SelectionDAG &DAG,
2187 const CCValAssign &VA,
2188 MachineFrameInfo *MFI,
2190 // Create the nodes corresponding to a load from this parameter slot.
2191 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2192 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2193 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2194 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2197 // If value is passed by pointer we have address passed instead of the value
2199 if (VA.getLocInfo() == CCValAssign::Indirect)
2200 ValVT = VA.getLocVT();
2202 ValVT = VA.getValVT();
2204 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2205 // changed with more analysis.
2206 // In case of tail call optimization mark all arguments mutable. Since they
2207 // could be overwritten by lowering of arguments in case of a tail call.
2208 if (Flags.isByVal()) {
2209 unsigned Bytes = Flags.getByValSize();
2210 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2211 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2212 return DAG.getFrameIndex(FI, getPointerTy());
2214 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2215 VA.getLocMemOffset(), isImmutable);
2216 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2217 return DAG.getLoad(ValVT, dl, Chain, FIN,
2218 MachinePointerInfo::getFixedStack(FI),
2219 false, false, false, 0);
2223 // FIXME: Get this from tablegen.
2224 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2225 const X86Subtarget *Subtarget) {
2226 assert(Subtarget->is64Bit());
2228 if (Subtarget->isCallingConvWin64(CallConv)) {
2229 static const MCPhysReg GPR64ArgRegsWin64[] = {
2230 X86::RCX, X86::RDX, X86::R8, X86::R9
2232 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2235 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2236 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2238 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2241 // FIXME: Get this from tablegen.
2242 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2243 CallingConv::ID CallConv,
2244 const X86Subtarget *Subtarget) {
2245 assert(Subtarget->is64Bit());
2246 if (Subtarget->isCallingConvWin64(CallConv)) {
2247 // The XMM registers which might contain var arg parameters are shadowed
2248 // in their paired GPR. So we only need to save the GPR to their home
2250 // TODO: __vectorcall will change this.
2254 const Function *Fn = MF.getFunction();
2255 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2256 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2257 "SSE register cannot be used when SSE is disabled!");
2258 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2259 !Subtarget->hasSSE1())
2260 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2264 static const MCPhysReg XMMArgRegs64Bit[] = {
2265 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2266 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2268 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2272 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2273 CallingConv::ID CallConv,
2275 const SmallVectorImpl<ISD::InputArg> &Ins,
2278 SmallVectorImpl<SDValue> &InVals)
2280 MachineFunction &MF = DAG.getMachineFunction();
2281 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2282 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2284 const Function* Fn = MF.getFunction();
2285 if (Fn->hasExternalLinkage() &&
2286 Subtarget->isTargetCygMing() &&
2287 Fn->getName() == "main")
2288 FuncInfo->setForceFramePointer(true);
2290 MachineFrameInfo *MFI = MF.getFrameInfo();
2291 bool Is64Bit = Subtarget->is64Bit();
2292 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2294 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2295 "Var args not supported with calling convention fastcc, ghc or hipe");
2297 // Assign locations to all of the incoming arguments.
2298 SmallVector<CCValAssign, 16> ArgLocs;
2299 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2301 // Allocate shadow area for Win64
2303 CCInfo.AllocateStack(32, 8);
2305 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2307 unsigned LastVal = ~0U;
2309 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2310 CCValAssign &VA = ArgLocs[i];
2311 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2313 assert(VA.getValNo() != LastVal &&
2314 "Don't support value assigned to multiple locs yet");
2316 LastVal = VA.getValNo();
2318 if (VA.isRegLoc()) {
2319 EVT RegVT = VA.getLocVT();
2320 const TargetRegisterClass *RC;
2321 if (RegVT == MVT::i32)
2322 RC = &X86::GR32RegClass;
2323 else if (Is64Bit && RegVT == MVT::i64)
2324 RC = &X86::GR64RegClass;
2325 else if (RegVT == MVT::f32)
2326 RC = &X86::FR32RegClass;
2327 else if (RegVT == MVT::f64)
2328 RC = &X86::FR64RegClass;
2329 else if (RegVT.is512BitVector())
2330 RC = &X86::VR512RegClass;
2331 else if (RegVT.is256BitVector())
2332 RC = &X86::VR256RegClass;
2333 else if (RegVT.is128BitVector())
2334 RC = &X86::VR128RegClass;
2335 else if (RegVT == MVT::x86mmx)
2336 RC = &X86::VR64RegClass;
2337 else if (RegVT == MVT::i1)
2338 RC = &X86::VK1RegClass;
2339 else if (RegVT == MVT::v8i1)
2340 RC = &X86::VK8RegClass;
2341 else if (RegVT == MVT::v16i1)
2342 RC = &X86::VK16RegClass;
2343 else if (RegVT == MVT::v32i1)
2344 RC = &X86::VK32RegClass;
2345 else if (RegVT == MVT::v64i1)
2346 RC = &X86::VK64RegClass;
2348 llvm_unreachable("Unknown argument type!");
2350 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2351 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2353 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2354 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2356 if (VA.getLocInfo() == CCValAssign::SExt)
2357 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2358 DAG.getValueType(VA.getValVT()));
2359 else if (VA.getLocInfo() == CCValAssign::ZExt)
2360 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2361 DAG.getValueType(VA.getValVT()));
2362 else if (VA.getLocInfo() == CCValAssign::BCvt)
2363 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2365 if (VA.isExtInLoc()) {
2366 // Handle MMX values passed in XMM regs.
2367 if (RegVT.isVector())
2368 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2370 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2373 assert(VA.isMemLoc());
2374 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2377 // If value is passed via pointer - do a load.
2378 if (VA.getLocInfo() == CCValAssign::Indirect)
2379 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2380 MachinePointerInfo(), false, false, false, 0);
2382 InVals.push_back(ArgValue);
2385 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2386 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2387 // The x86-64 ABIs require that for returning structs by value we copy
2388 // the sret argument into %rax/%eax (depending on ABI) for the return.
2389 // Win32 requires us to put the sret argument to %eax as well.
2390 // Save the argument into a virtual register so that we can access it
2391 // from the return points.
2392 if (Ins[i].Flags.isSRet()) {
2393 unsigned Reg = FuncInfo->getSRetReturnReg();
2395 MVT PtrTy = getPointerTy();
2396 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2397 FuncInfo->setSRetReturnReg(Reg);
2399 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2400 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2406 unsigned StackSize = CCInfo.getNextStackOffset();
2407 // Align stack specially for tail calls.
2408 if (FuncIsMadeTailCallSafe(CallConv,
2409 MF.getTarget().Options.GuaranteedTailCallOpt))
2410 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2412 // If the function takes variable number of arguments, make a frame index for
2413 // the start of the first vararg value... for expansion of llvm.va_start. We
2414 // can skip this if there are no va_start calls.
2415 if (MFI->hasVAStart() &&
2416 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2417 CallConv != CallingConv::X86_ThisCall))) {
2418 FuncInfo->setVarArgsFrameIndex(
2419 MFI->CreateFixedObject(1, StackSize, true));
2422 MachineModuleInfo &MMI = MF.getMMI();
2423 const Function *WinEHParent = nullptr;
2424 if (IsWin64 && MMI.hasWinEHFuncInfo(Fn))
2425 WinEHParent = MMI.getWinEHParent(Fn);
2426 bool IsWinEHOutlined = WinEHParent && WinEHParent != Fn;
2427 bool IsWinEHParent = WinEHParent && WinEHParent == Fn;
2429 // Figure out if XMM registers are in use.
2430 assert(!(MF.getTarget().Options.UseSoftFloat &&
2431 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2432 "SSE register cannot be used when SSE is disabled!");
2434 // 64-bit calling conventions support varargs and register parameters, so we
2435 // have to do extra work to spill them in the prologue.
2436 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2437 // Find the first unallocated argument registers.
2438 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2439 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2440 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2441 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2442 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2443 "SSE register cannot be used when SSE is disabled!");
2445 // Gather all the live in physical registers.
2446 SmallVector<SDValue, 6> LiveGPRs;
2447 SmallVector<SDValue, 8> LiveXMMRegs;
2449 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2450 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2452 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2454 if (!ArgXMMs.empty()) {
2455 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2456 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2457 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2458 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2459 LiveXMMRegs.push_back(
2460 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2465 // Get to the caller-allocated home save location. Add 8 to account
2466 // for the return address.
2467 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2468 FuncInfo->setRegSaveFrameIndex(
2469 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2470 // Fixup to set vararg frame on shadow area (4 x i64).
2472 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2474 // For X86-64, if there are vararg parameters that are passed via
2475 // registers, then we must store them to their spots on the stack so
2476 // they may be loaded by deferencing the result of va_next.
2477 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2478 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2479 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2480 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2483 // Store the integer parameter registers.
2484 SmallVector<SDValue, 8> MemOps;
2485 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2487 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2488 for (SDValue Val : LiveGPRs) {
2489 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2490 DAG.getIntPtrConstant(Offset));
2492 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2493 MachinePointerInfo::getFixedStack(
2494 FuncInfo->getRegSaveFrameIndex(), Offset),
2496 MemOps.push_back(Store);
2500 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2501 // Now store the XMM (fp + vector) parameter registers.
2502 SmallVector<SDValue, 12> SaveXMMOps;
2503 SaveXMMOps.push_back(Chain);
2504 SaveXMMOps.push_back(ALVal);
2505 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2506 FuncInfo->getRegSaveFrameIndex()));
2507 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2508 FuncInfo->getVarArgsFPOffset()));
2509 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2511 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2512 MVT::Other, SaveXMMOps));
2515 if (!MemOps.empty())
2516 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2517 } else if (IsWinEHOutlined) {
2518 // Get to the caller-allocated home save location. Add 8 to account
2519 // for the return address.
2520 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2521 FuncInfo->setRegSaveFrameIndex(MFI->CreateFixedObject(
2522 /*Size=*/1, /*SPOffset=*/HomeOffset + 8, /*Immutable=*/false));
2524 MMI.getWinEHFuncInfo(Fn)
2525 .CatchHandlerParentFrameObjIdx[const_cast<Function *>(Fn)] =
2526 FuncInfo->getRegSaveFrameIndex();
2528 // Store the second integer parameter (rdx) into rsp+16 relative to the
2529 // stack pointer at the entry of the function.
2531 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), getPointerTy());
2532 unsigned GPR = MF.addLiveIn(X86::RDX, &X86::GR64RegClass);
2533 SDValue Val = DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64);
2534 Chain = DAG.getStore(
2535 Val.getValue(1), dl, Val, RSFIN,
2536 MachinePointerInfo::getFixedStack(FuncInfo->getRegSaveFrameIndex()),
2537 /*isVolatile=*/true, /*isNonTemporal=*/false, /*Alignment=*/0);
2540 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2541 // Find the largest legal vector type.
2542 MVT VecVT = MVT::Other;
2543 // FIXME: Only some x86_32 calling conventions support AVX512.
2544 if (Subtarget->hasAVX512() &&
2545 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2546 CallConv == CallingConv::Intel_OCL_BI)))
2547 VecVT = MVT::v16f32;
2548 else if (Subtarget->hasAVX())
2550 else if (Subtarget->hasSSE2())
2553 // We forward some GPRs and some vector types.
2554 SmallVector<MVT, 2> RegParmTypes;
2555 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2556 RegParmTypes.push_back(IntVT);
2557 if (VecVT != MVT::Other)
2558 RegParmTypes.push_back(VecVT);
2560 // Compute the set of forwarded registers. The rest are scratch.
2561 SmallVectorImpl<ForwardedRegister> &Forwards =
2562 FuncInfo->getForwardedMustTailRegParms();
2563 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2565 // Conservatively forward AL on x86_64, since it might be used for varargs.
2566 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2567 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2568 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2571 // Copy all forwards from physical to virtual registers.
2572 for (ForwardedRegister &F : Forwards) {
2573 // FIXME: Can we use a less constrained schedule?
2574 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2575 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2576 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2580 // Some CCs need callee pop.
2581 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2582 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2583 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2585 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2586 // If this is an sret function, the return should pop the hidden pointer.
2587 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2588 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2589 argsAreStructReturn(Ins) == StackStructReturn)
2590 FuncInfo->setBytesToPopOnReturn(4);
2594 // RegSaveFrameIndex is X86-64 only.
2595 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2596 if (CallConv == CallingConv::X86_FastCall ||
2597 CallConv == CallingConv::X86_ThisCall)
2598 // fastcc functions can't have varargs.
2599 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2602 FuncInfo->setArgumentStackSize(StackSize);
2604 if (IsWinEHParent) {
2605 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2606 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2607 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2608 SDValue Neg2 = DAG.getConstant(-2, MVT::i64);
2609 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2610 MachinePointerInfo::getFixedStack(UnwindHelpFI),
2611 /*isVolatile=*/true,
2612 /*isNonTemporal=*/false, /*Alignment=*/0);
2619 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2620 SDValue StackPtr, SDValue Arg,
2621 SDLoc dl, SelectionDAG &DAG,
2622 const CCValAssign &VA,
2623 ISD::ArgFlagsTy Flags) const {
2624 unsigned LocMemOffset = VA.getLocMemOffset();
2625 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2626 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2627 if (Flags.isByVal())
2628 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2630 return DAG.getStore(Chain, dl, Arg, PtrOff,
2631 MachinePointerInfo::getStack(LocMemOffset),
2635 /// Emit a load of return address if tail call
2636 /// optimization is performed and it is required.
2638 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2639 SDValue &OutRetAddr, SDValue Chain,
2640 bool IsTailCall, bool Is64Bit,
2641 int FPDiff, SDLoc dl) const {
2642 // Adjust the Return address stack slot.
2643 EVT VT = getPointerTy();
2644 OutRetAddr = getReturnAddressFrameIndex(DAG);
2646 // Load the "old" Return address.
2647 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2648 false, false, false, 0);
2649 return SDValue(OutRetAddr.getNode(), 1);
2652 /// Emit a store of the return address if tail call
2653 /// optimization is performed and it is required (FPDiff!=0).
2654 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2655 SDValue Chain, SDValue RetAddrFrIdx,
2656 EVT PtrVT, unsigned SlotSize,
2657 int FPDiff, SDLoc dl) {
2658 // Store the return address to the appropriate stack slot.
2659 if (!FPDiff) return Chain;
2660 // Calculate the new stack slot for the return address.
2661 int NewReturnAddrFI =
2662 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2664 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2665 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2666 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2672 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2673 SmallVectorImpl<SDValue> &InVals) const {
2674 SelectionDAG &DAG = CLI.DAG;
2676 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2677 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2678 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2679 SDValue Chain = CLI.Chain;
2680 SDValue Callee = CLI.Callee;
2681 CallingConv::ID CallConv = CLI.CallConv;
2682 bool &isTailCall = CLI.IsTailCall;
2683 bool isVarArg = CLI.IsVarArg;
2685 MachineFunction &MF = DAG.getMachineFunction();
2686 bool Is64Bit = Subtarget->is64Bit();
2687 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2688 StructReturnType SR = callIsStructReturn(Outs);
2689 bool IsSibcall = false;
2690 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2692 if (MF.getTarget().Options.DisableTailCalls)
2695 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2697 // Force this to be a tail call. The verifier rules are enough to ensure
2698 // that we can lower this successfully without moving the return address
2701 } else if (isTailCall) {
2702 // Check if it's really possible to do a tail call.
2703 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2704 isVarArg, SR != NotStructReturn,
2705 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2706 Outs, OutVals, Ins, DAG);
2708 // Sibcalls are automatically detected tailcalls which do not require
2710 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2717 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2718 "Var args not supported with calling convention fastcc, ghc or hipe");
2720 // Analyze operands of the call, assigning locations to each operand.
2721 SmallVector<CCValAssign, 16> ArgLocs;
2722 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2724 // Allocate shadow area for Win64
2726 CCInfo.AllocateStack(32, 8);
2728 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2730 // Get a count of how many bytes are to be pushed on the stack.
2731 unsigned NumBytes = CCInfo.getNextStackOffset();
2733 // This is a sibcall. The memory operands are available in caller's
2734 // own caller's stack.
2736 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2737 IsTailCallConvention(CallConv))
2738 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2741 if (isTailCall && !IsSibcall && !IsMustTail) {
2742 // Lower arguments at fp - stackoffset + fpdiff.
2743 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2745 FPDiff = NumBytesCallerPushed - NumBytes;
2747 // Set the delta of movement of the returnaddr stackslot.
2748 // But only set if delta is greater than previous delta.
2749 if (FPDiff < X86Info->getTCReturnAddrDelta())
2750 X86Info->setTCReturnAddrDelta(FPDiff);
2753 unsigned NumBytesToPush = NumBytes;
2754 unsigned NumBytesToPop = NumBytes;
2756 // If we have an inalloca argument, all stack space has already been allocated
2757 // for us and be right at the top of the stack. We don't support multiple
2758 // arguments passed in memory when using inalloca.
2759 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2761 if (!ArgLocs.back().isMemLoc())
2762 report_fatal_error("cannot use inalloca attribute on a register "
2764 if (ArgLocs.back().getLocMemOffset() != 0)
2765 report_fatal_error("any parameter with the inalloca attribute must be "
2766 "the only memory argument");
2770 Chain = DAG.getCALLSEQ_START(
2771 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2773 SDValue RetAddrFrIdx;
2774 // Load return address for tail calls.
2775 if (isTailCall && FPDiff)
2776 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2777 Is64Bit, FPDiff, dl);
2779 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2780 SmallVector<SDValue, 8> MemOpChains;
2783 // Walk the register/memloc assignments, inserting copies/loads. In the case
2784 // of tail call optimization arguments are handle later.
2785 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
2786 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2787 // Skip inalloca arguments, they have already been written.
2788 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2789 if (Flags.isInAlloca())
2792 CCValAssign &VA = ArgLocs[i];
2793 EVT RegVT = VA.getLocVT();
2794 SDValue Arg = OutVals[i];
2795 bool isByVal = Flags.isByVal();
2797 // Promote the value if needed.
2798 switch (VA.getLocInfo()) {
2799 default: llvm_unreachable("Unknown loc info!");
2800 case CCValAssign::Full: break;
2801 case CCValAssign::SExt:
2802 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2804 case CCValAssign::ZExt:
2805 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2807 case CCValAssign::AExt:
2808 if (RegVT.is128BitVector()) {
2809 // Special case: passing MMX values in XMM registers.
2810 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2811 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2812 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2814 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2816 case CCValAssign::BCvt:
2817 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2819 case CCValAssign::Indirect: {
2820 // Store the argument.
2821 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2822 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2823 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2824 MachinePointerInfo::getFixedStack(FI),
2831 if (VA.isRegLoc()) {
2832 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2833 if (isVarArg && IsWin64) {
2834 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2835 // shadow reg if callee is a varargs function.
2836 unsigned ShadowReg = 0;
2837 switch (VA.getLocReg()) {
2838 case X86::XMM0: ShadowReg = X86::RCX; break;
2839 case X86::XMM1: ShadowReg = X86::RDX; break;
2840 case X86::XMM2: ShadowReg = X86::R8; break;
2841 case X86::XMM3: ShadowReg = X86::R9; break;
2844 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2846 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2847 assert(VA.isMemLoc());
2848 if (!StackPtr.getNode())
2849 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2851 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2852 dl, DAG, VA, Flags));
2856 if (!MemOpChains.empty())
2857 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2859 if (Subtarget->isPICStyleGOT()) {
2860 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2863 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2864 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2866 // If we are tail calling and generating PIC/GOT style code load the
2867 // address of the callee into ECX. The value in ecx is used as target of
2868 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2869 // for tail calls on PIC/GOT architectures. Normally we would just put the
2870 // address of GOT into ebx and then call target@PLT. But for tail calls
2871 // ebx would be restored (since ebx is callee saved) before jumping to the
2874 // Note: The actual moving to ECX is done further down.
2875 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2876 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2877 !G->getGlobal()->hasProtectedVisibility())
2878 Callee = LowerGlobalAddress(Callee, DAG);
2879 else if (isa<ExternalSymbolSDNode>(Callee))
2880 Callee = LowerExternalSymbol(Callee, DAG);
2884 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2885 // From AMD64 ABI document:
2886 // For calls that may call functions that use varargs or stdargs
2887 // (prototype-less calls or calls to functions containing ellipsis (...) in
2888 // the declaration) %al is used as hidden argument to specify the number
2889 // of SSE registers used. The contents of %al do not need to match exactly
2890 // the number of registers, but must be an ubound on the number of SSE
2891 // registers used and is in the range 0 - 8 inclusive.
2893 // Count the number of XMM registers allocated.
2894 static const MCPhysReg XMMArgRegs[] = {
2895 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2896 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2898 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
2899 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2900 && "SSE registers cannot be used when SSE is disabled");
2902 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2903 DAG.getConstant(NumXMMRegs, MVT::i8)));
2906 if (isVarArg && IsMustTail) {
2907 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2908 for (const auto &F : Forwards) {
2909 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2910 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2914 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2915 // don't need this because the eligibility check rejects calls that require
2916 // shuffling arguments passed in memory.
2917 if (!IsSibcall && isTailCall) {
2918 // Force all the incoming stack arguments to be loaded from the stack
2919 // before any new outgoing arguments are stored to the stack, because the
2920 // outgoing stack slots may alias the incoming argument stack slots, and
2921 // the alias isn't otherwise explicit. This is slightly more conservative
2922 // than necessary, because it means that each store effectively depends
2923 // on every argument instead of just those arguments it would clobber.
2924 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2926 SmallVector<SDValue, 8> MemOpChains2;
2929 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2930 CCValAssign &VA = ArgLocs[i];
2933 assert(VA.isMemLoc());
2934 SDValue Arg = OutVals[i];
2935 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2936 // Skip inalloca arguments. They don't require any work.
2937 if (Flags.isInAlloca())
2939 // Create frame index.
2940 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2941 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2942 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2943 FIN = DAG.getFrameIndex(FI, getPointerTy());
2945 if (Flags.isByVal()) {
2946 // Copy relative to framepointer.
2947 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2948 if (!StackPtr.getNode())
2949 StackPtr = DAG.getCopyFromReg(Chain, dl,
2950 RegInfo->getStackRegister(),
2952 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2954 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2958 // Store relative to framepointer.
2959 MemOpChains2.push_back(
2960 DAG.getStore(ArgChain, dl, Arg, FIN,
2961 MachinePointerInfo::getFixedStack(FI),
2966 if (!MemOpChains2.empty())
2967 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
2969 // Store the return address to the appropriate stack slot.
2970 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2971 getPointerTy(), RegInfo->getSlotSize(),
2975 // Build a sequence of copy-to-reg nodes chained together with token chain
2976 // and flag operands which copy the outgoing args into registers.
2978 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2979 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2980 RegsToPass[i].second, InFlag);
2981 InFlag = Chain.getValue(1);
2984 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
2985 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2986 // In the 64-bit large code model, we have to make all calls
2987 // through a register, since the call instruction's 32-bit
2988 // pc-relative offset may not be large enough to hold the whole
2990 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
2991 // If the callee is a GlobalAddress node (quite common, every direct call
2992 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2994 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
2996 // We should use extra load for direct calls to dllimported functions in
2998 const GlobalValue *GV = G->getGlobal();
2999 if (!GV->hasDLLImportStorageClass()) {
3000 unsigned char OpFlags = 0;
3001 bool ExtraLoad = false;
3002 unsigned WrapperKind = ISD::DELETED_NODE;
3004 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3005 // external symbols most go through the PLT in PIC mode. If the symbol
3006 // has hidden or protected visibility, or if it is static or local, then
3007 // we don't need to use the PLT - we can directly call it.
3008 if (Subtarget->isTargetELF() &&
3009 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3010 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3011 OpFlags = X86II::MO_PLT;
3012 } else if (Subtarget->isPICStyleStubAny() &&
3013 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3014 (!Subtarget->getTargetTriple().isMacOSX() ||
3015 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3016 // PC-relative references to external symbols should go through $stub,
3017 // unless we're building with the leopard linker or later, which
3018 // automatically synthesizes these stubs.
3019 OpFlags = X86II::MO_DARWIN_STUB;
3020 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3021 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3022 // If the function is marked as non-lazy, generate an indirect call
3023 // which loads from the GOT directly. This avoids runtime overhead
3024 // at the cost of eager binding (and one extra byte of encoding).
3025 OpFlags = X86II::MO_GOTPCREL;
3026 WrapperKind = X86ISD::WrapperRIP;
3030 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3031 G->getOffset(), OpFlags);
3033 // Add a wrapper if needed.
3034 if (WrapperKind != ISD::DELETED_NODE)
3035 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3036 // Add extra indirection if needed.
3038 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3039 MachinePointerInfo::getGOT(),
3040 false, false, false, 0);
3042 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3043 unsigned char OpFlags = 0;
3045 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3046 // external symbols should go through the PLT.
3047 if (Subtarget->isTargetELF() &&
3048 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3049 OpFlags = X86II::MO_PLT;
3050 } else if (Subtarget->isPICStyleStubAny() &&
3051 (!Subtarget->getTargetTriple().isMacOSX() ||
3052 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3053 // PC-relative references to external symbols should go through $stub,
3054 // unless we're building with the leopard linker or later, which
3055 // automatically synthesizes these stubs.
3056 OpFlags = X86II::MO_DARWIN_STUB;
3059 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3061 } else if (Subtarget->isTarget64BitILP32() &&
3062 Callee->getValueType(0) == MVT::i32) {
3063 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3064 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3067 // Returns a chain & a flag for retval copy to use.
3068 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3069 SmallVector<SDValue, 8> Ops;
3071 if (!IsSibcall && isTailCall) {
3072 Chain = DAG.getCALLSEQ_END(Chain,
3073 DAG.getIntPtrConstant(NumBytesToPop, true),
3074 DAG.getIntPtrConstant(0, true), InFlag, dl);
3075 InFlag = Chain.getValue(1);
3078 Ops.push_back(Chain);
3079 Ops.push_back(Callee);
3082 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3084 // Add argument registers to the end of the list so that they are known live
3086 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3087 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3088 RegsToPass[i].second.getValueType()));
3090 // Add a register mask operand representing the call-preserved registers.
3091 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
3092 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
3093 assert(Mask && "Missing call preserved mask for calling convention");
3094 Ops.push_back(DAG.getRegisterMask(Mask));
3096 if (InFlag.getNode())
3097 Ops.push_back(InFlag);
3101 //// If this is the first return lowered for this function, add the regs
3102 //// to the liveout set for the function.
3103 // This isn't right, although it's probably harmless on x86; liveouts
3104 // should be computed from returns not tail calls. Consider a void
3105 // function making a tail call to a function returning int.
3106 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3109 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3110 InFlag = Chain.getValue(1);
3112 // Create the CALLSEQ_END node.
3113 unsigned NumBytesForCalleeToPop;
3114 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3115 DAG.getTarget().Options.GuaranteedTailCallOpt))
3116 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3117 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3118 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3119 SR == StackStructReturn)
3120 // If this is a call to a struct-return function, the callee
3121 // pops the hidden struct pointer, so we have to push it back.
3122 // This is common for Darwin/X86, Linux & Mingw32 targets.
3123 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3124 NumBytesForCalleeToPop = 4;
3126 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3128 // Returns a flag for retval copy to use.
3130 Chain = DAG.getCALLSEQ_END(Chain,
3131 DAG.getIntPtrConstant(NumBytesToPop, true),
3132 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3135 InFlag = Chain.getValue(1);
3138 // Handle result values, copying them out of physregs into vregs that we
3140 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3141 Ins, dl, DAG, InVals);
3144 //===----------------------------------------------------------------------===//
3145 // Fast Calling Convention (tail call) implementation
3146 //===----------------------------------------------------------------------===//
3148 // Like std call, callee cleans arguments, convention except that ECX is
3149 // reserved for storing the tail called function address. Only 2 registers are
3150 // free for argument passing (inreg). Tail call optimization is performed
3152 // * tailcallopt is enabled
3153 // * caller/callee are fastcc
3154 // On X86_64 architecture with GOT-style position independent code only local
3155 // (within module) calls are supported at the moment.
3156 // To keep the stack aligned according to platform abi the function
3157 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3158 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3159 // If a tail called function callee has more arguments than the caller the
3160 // caller needs to make sure that there is room to move the RETADDR to. This is
3161 // achieved by reserving an area the size of the argument delta right after the
3162 // original RETADDR, but before the saved framepointer or the spilled registers
3163 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3175 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3176 /// for a 16 byte align requirement.
3178 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3179 SelectionDAG& DAG) const {
3180 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3181 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3182 unsigned StackAlignment = TFI.getStackAlignment();
3183 uint64_t AlignMask = StackAlignment - 1;
3184 int64_t Offset = StackSize;
3185 unsigned SlotSize = RegInfo->getSlotSize();
3186 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3187 // Number smaller than 12 so just add the difference.
3188 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3190 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3191 Offset = ((~AlignMask) & Offset) + StackAlignment +
3192 (StackAlignment-SlotSize);
3197 /// MatchingStackOffset - Return true if the given stack call argument is
3198 /// already available in the same position (relatively) of the caller's
3199 /// incoming argument stack.
3201 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3202 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3203 const X86InstrInfo *TII) {
3204 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3206 if (Arg.getOpcode() == ISD::CopyFromReg) {
3207 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3208 if (!TargetRegisterInfo::isVirtualRegister(VR))
3210 MachineInstr *Def = MRI->getVRegDef(VR);
3213 if (!Flags.isByVal()) {
3214 if (!TII->isLoadFromStackSlot(Def, FI))
3217 unsigned Opcode = Def->getOpcode();
3218 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3219 Opcode == X86::LEA64_32r) &&
3220 Def->getOperand(1).isFI()) {
3221 FI = Def->getOperand(1).getIndex();
3222 Bytes = Flags.getByValSize();
3226 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3227 if (Flags.isByVal())
3228 // ByVal argument is passed in as a pointer but it's now being
3229 // dereferenced. e.g.
3230 // define @foo(%struct.X* %A) {
3231 // tail call @bar(%struct.X* byval %A)
3234 SDValue Ptr = Ld->getBasePtr();
3235 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3238 FI = FINode->getIndex();
3239 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3240 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3241 FI = FINode->getIndex();
3242 Bytes = Flags.getByValSize();
3246 assert(FI != INT_MAX);
3247 if (!MFI->isFixedObjectIndex(FI))
3249 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3252 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3253 /// for tail call optimization. Targets which want to do tail call
3254 /// optimization should implement this function.
3256 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3257 CallingConv::ID CalleeCC,
3259 bool isCalleeStructRet,
3260 bool isCallerStructRet,
3262 const SmallVectorImpl<ISD::OutputArg> &Outs,
3263 const SmallVectorImpl<SDValue> &OutVals,
3264 const SmallVectorImpl<ISD::InputArg> &Ins,
3265 SelectionDAG &DAG) const {
3266 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3269 // If -tailcallopt is specified, make fastcc functions tail-callable.
3270 const MachineFunction &MF = DAG.getMachineFunction();
3271 const Function *CallerF = MF.getFunction();
3273 // If the function return type is x86_fp80 and the callee return type is not,
3274 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3275 // perform a tailcall optimization here.
3276 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3279 CallingConv::ID CallerCC = CallerF->getCallingConv();
3280 bool CCMatch = CallerCC == CalleeCC;
3281 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3282 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3284 // Win64 functions have extra shadow space for argument homing. Don't do the
3285 // sibcall if the caller and callee have mismatched expectations for this
3287 if (IsCalleeWin64 != IsCallerWin64)
3290 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3291 if (IsTailCallConvention(CalleeCC) && CCMatch)
3296 // Look for obvious safe cases to perform tail call optimization that do not
3297 // require ABI changes. This is what gcc calls sibcall.
3299 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3300 // emit a special epilogue.
3301 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3302 if (RegInfo->needsStackRealignment(MF))
3305 // Also avoid sibcall optimization if either caller or callee uses struct
3306 // return semantics.
3307 if (isCalleeStructRet || isCallerStructRet)
3310 // An stdcall/thiscall caller is expected to clean up its arguments; the
3311 // callee isn't going to do that.
3312 // FIXME: this is more restrictive than needed. We could produce a tailcall
3313 // when the stack adjustment matches. For example, with a thiscall that takes
3314 // only one argument.
3315 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3316 CallerCC == CallingConv::X86_ThisCall))
3319 // Do not sibcall optimize vararg calls unless all arguments are passed via
3321 if (isVarArg && !Outs.empty()) {
3323 // Optimizing for varargs on Win64 is unlikely to be safe without
3324 // additional testing.
3325 if (IsCalleeWin64 || IsCallerWin64)
3328 SmallVector<CCValAssign, 16> ArgLocs;
3329 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3332 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3333 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3334 if (!ArgLocs[i].isRegLoc())
3338 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3339 // stack. Therefore, if it's not used by the call it is not safe to optimize
3340 // this into a sibcall.
3341 bool Unused = false;
3342 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3349 SmallVector<CCValAssign, 16> RVLocs;
3350 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3352 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3353 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3354 CCValAssign &VA = RVLocs[i];
3355 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3360 // If the calling conventions do not match, then we'd better make sure the
3361 // results are returned in the same way as what the caller expects.
3363 SmallVector<CCValAssign, 16> RVLocs1;
3364 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3366 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3368 SmallVector<CCValAssign, 16> RVLocs2;
3369 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3371 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3373 if (RVLocs1.size() != RVLocs2.size())
3375 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3376 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3378 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3380 if (RVLocs1[i].isRegLoc()) {
3381 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3384 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3390 // If the callee takes no arguments then go on to check the results of the
3392 if (!Outs.empty()) {
3393 // Check if stack adjustment is needed. For now, do not do this if any
3394 // argument is passed on the stack.
3395 SmallVector<CCValAssign, 16> ArgLocs;
3396 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3399 // Allocate shadow area for Win64
3401 CCInfo.AllocateStack(32, 8);
3403 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3404 if (CCInfo.getNextStackOffset()) {
3405 MachineFunction &MF = DAG.getMachineFunction();
3406 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3409 // Check if the arguments are already laid out in the right way as
3410 // the caller's fixed stack objects.
3411 MachineFrameInfo *MFI = MF.getFrameInfo();
3412 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3413 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3414 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3415 CCValAssign &VA = ArgLocs[i];
3416 SDValue Arg = OutVals[i];
3417 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3418 if (VA.getLocInfo() == CCValAssign::Indirect)
3420 if (!VA.isRegLoc()) {
3421 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3428 // If the tailcall address may be in a register, then make sure it's
3429 // possible to register allocate for it. In 32-bit, the call address can
3430 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3431 // callee-saved registers are restored. These happen to be the same
3432 // registers used to pass 'inreg' arguments so watch out for those.
3433 if (!Subtarget->is64Bit() &&
3434 ((!isa<GlobalAddressSDNode>(Callee) &&
3435 !isa<ExternalSymbolSDNode>(Callee)) ||
3436 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3437 unsigned NumInRegs = 0;
3438 // In PIC we need an extra register to formulate the address computation
3440 unsigned MaxInRegs =
3441 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3443 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3444 CCValAssign &VA = ArgLocs[i];
3447 unsigned Reg = VA.getLocReg();
3450 case X86::EAX: case X86::EDX: case X86::ECX:
3451 if (++NumInRegs == MaxInRegs)
3463 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3464 const TargetLibraryInfo *libInfo) const {
3465 return X86::createFastISel(funcInfo, libInfo);
3468 //===----------------------------------------------------------------------===//
3469 // Other Lowering Hooks
3470 //===----------------------------------------------------------------------===//
3472 static bool MayFoldLoad(SDValue Op) {
3473 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3476 static bool MayFoldIntoStore(SDValue Op) {
3477 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3480 static bool isTargetShuffle(unsigned Opcode) {
3482 default: return false;
3483 case X86ISD::BLENDI:
3484 case X86ISD::PSHUFB:
3485 case X86ISD::PSHUFD:
3486 case X86ISD::PSHUFHW:
3487 case X86ISD::PSHUFLW:
3489 case X86ISD::PALIGNR:
3490 case X86ISD::MOVLHPS:
3491 case X86ISD::MOVLHPD:
3492 case X86ISD::MOVHLPS:
3493 case X86ISD::MOVLPS:
3494 case X86ISD::MOVLPD:
3495 case X86ISD::MOVSHDUP:
3496 case X86ISD::MOVSLDUP:
3497 case X86ISD::MOVDDUP:
3500 case X86ISD::UNPCKL:
3501 case X86ISD::UNPCKH:
3502 case X86ISD::VPERMILPI:
3503 case X86ISD::VPERM2X128:
3504 case X86ISD::VPERMI:
3509 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3510 SDValue V1, unsigned TargetMask,
3511 SelectionDAG &DAG) {
3513 default: llvm_unreachable("Unknown x86 shuffle node");
3514 case X86ISD::PSHUFD:
3515 case X86ISD::PSHUFHW:
3516 case X86ISD::PSHUFLW:
3517 case X86ISD::VPERMILPI:
3518 case X86ISD::VPERMI:
3519 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3523 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3524 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3526 default: llvm_unreachable("Unknown x86 shuffle node");
3527 case X86ISD::MOVLHPS:
3528 case X86ISD::MOVLHPD:
3529 case X86ISD::MOVHLPS:
3530 case X86ISD::MOVLPS:
3531 case X86ISD::MOVLPD:
3534 case X86ISD::UNPCKL:
3535 case X86ISD::UNPCKH:
3536 return DAG.getNode(Opc, dl, VT, V1, V2);
3540 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3541 MachineFunction &MF = DAG.getMachineFunction();
3542 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3543 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3544 int ReturnAddrIndex = FuncInfo->getRAIndex();
3546 if (ReturnAddrIndex == 0) {
3547 // Set up a frame object for the return address.
3548 unsigned SlotSize = RegInfo->getSlotSize();
3549 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3552 FuncInfo->setRAIndex(ReturnAddrIndex);
3555 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3558 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3559 bool hasSymbolicDisplacement) {
3560 // Offset should fit into 32 bit immediate field.
3561 if (!isInt<32>(Offset))
3564 // If we don't have a symbolic displacement - we don't have any extra
3566 if (!hasSymbolicDisplacement)
3569 // FIXME: Some tweaks might be needed for medium code model.
3570 if (M != CodeModel::Small && M != CodeModel::Kernel)
3573 // For small code model we assume that latest object is 16MB before end of 31
3574 // bits boundary. We may also accept pretty large negative constants knowing
3575 // that all objects are in the positive half of address space.
3576 if (M == CodeModel::Small && Offset < 16*1024*1024)
3579 // For kernel code model we know that all object resist in the negative half
3580 // of 32bits address space. We may not accept negative offsets, since they may
3581 // be just off and we may accept pretty large positive ones.
3582 if (M == CodeModel::Kernel && Offset >= 0)
3588 /// isCalleePop - Determines whether the callee is required to pop its
3589 /// own arguments. Callee pop is necessary to support tail calls.
3590 bool X86::isCalleePop(CallingConv::ID CallingConv,
3591 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3592 switch (CallingConv) {
3595 case CallingConv::X86_StdCall:
3596 case CallingConv::X86_FastCall:
3597 case CallingConv::X86_ThisCall:
3599 case CallingConv::Fast:
3600 case CallingConv::GHC:
3601 case CallingConv::HiPE:
3608 /// \brief Return true if the condition is an unsigned comparison operation.
3609 static bool isX86CCUnsigned(unsigned X86CC) {
3611 default: llvm_unreachable("Invalid integer condition!");
3612 case X86::COND_E: return true;
3613 case X86::COND_G: return false;
3614 case X86::COND_GE: return false;
3615 case X86::COND_L: return false;
3616 case X86::COND_LE: return false;
3617 case X86::COND_NE: return true;
3618 case X86::COND_B: return true;
3619 case X86::COND_A: return true;
3620 case X86::COND_BE: return true;
3621 case X86::COND_AE: return true;
3623 llvm_unreachable("covered switch fell through?!");
3626 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3627 /// specific condition code, returning the condition code and the LHS/RHS of the
3628 /// comparison to make.
3629 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3630 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3632 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3633 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3634 // X > -1 -> X == 0, jump !sign.
3635 RHS = DAG.getConstant(0, RHS.getValueType());
3636 return X86::COND_NS;
3638 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3639 // X < 0 -> X == 0, jump on sign.
3642 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3644 RHS = DAG.getConstant(0, RHS.getValueType());
3645 return X86::COND_LE;
3649 switch (SetCCOpcode) {
3650 default: llvm_unreachable("Invalid integer condition!");
3651 case ISD::SETEQ: return X86::COND_E;
3652 case ISD::SETGT: return X86::COND_G;
3653 case ISD::SETGE: return X86::COND_GE;
3654 case ISD::SETLT: return X86::COND_L;
3655 case ISD::SETLE: return X86::COND_LE;
3656 case ISD::SETNE: return X86::COND_NE;
3657 case ISD::SETULT: return X86::COND_B;
3658 case ISD::SETUGT: return X86::COND_A;
3659 case ISD::SETULE: return X86::COND_BE;
3660 case ISD::SETUGE: return X86::COND_AE;
3664 // First determine if it is required or is profitable to flip the operands.
3666 // If LHS is a foldable load, but RHS is not, flip the condition.
3667 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3668 !ISD::isNON_EXTLoad(RHS.getNode())) {
3669 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3670 std::swap(LHS, RHS);
3673 switch (SetCCOpcode) {
3679 std::swap(LHS, RHS);
3683 // On a floating point condition, the flags are set as follows:
3685 // 0 | 0 | 0 | X > Y
3686 // 0 | 0 | 1 | X < Y
3687 // 1 | 0 | 0 | X == Y
3688 // 1 | 1 | 1 | unordered
3689 switch (SetCCOpcode) {
3690 default: llvm_unreachable("Condcode should be pre-legalized away");
3692 case ISD::SETEQ: return X86::COND_E;
3693 case ISD::SETOLT: // flipped
3695 case ISD::SETGT: return X86::COND_A;
3696 case ISD::SETOLE: // flipped
3698 case ISD::SETGE: return X86::COND_AE;
3699 case ISD::SETUGT: // flipped
3701 case ISD::SETLT: return X86::COND_B;
3702 case ISD::SETUGE: // flipped
3704 case ISD::SETLE: return X86::COND_BE;
3706 case ISD::SETNE: return X86::COND_NE;
3707 case ISD::SETUO: return X86::COND_P;
3708 case ISD::SETO: return X86::COND_NP;
3710 case ISD::SETUNE: return X86::COND_INVALID;
3714 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3715 /// code. Current x86 isa includes the following FP cmov instructions:
3716 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3717 static bool hasFPCMov(unsigned X86CC) {
3733 /// isFPImmLegal - Returns true if the target can instruction select the
3734 /// specified FP immediate natively. If false, the legalizer will
3735 /// materialize the FP immediate as a load from a constant pool.
3736 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3737 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3738 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3744 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
3745 ISD::LoadExtType ExtTy,
3747 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
3748 // relocation target a movq or addq instruction: don't let the load shrink.
3749 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
3750 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
3751 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
3752 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
3756 /// \brief Returns true if it is beneficial to convert a load of a constant
3757 /// to just the constant itself.
3758 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3760 assert(Ty->isIntegerTy());
3762 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3763 if (BitSize == 0 || BitSize > 64)
3768 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
3769 unsigned Index) const {
3770 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
3773 return (Index == 0 || Index == ResVT.getVectorNumElements());
3776 bool X86TargetLowering::isCheapToSpeculateCttz() const {
3777 // Speculate cttz only if we can directly use TZCNT.
3778 return Subtarget->hasBMI();
3781 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
3782 // Speculate ctlz only if we can directly use LZCNT.
3783 return Subtarget->hasLZCNT();
3786 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3787 /// the specified range (L, H].
3788 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3789 return (Val < 0) || (Val >= Low && Val < Hi);
3792 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3793 /// specified value.
3794 static bool isUndefOrEqual(int Val, int CmpVal) {
3795 return (Val < 0 || Val == CmpVal);
3798 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3799 /// from position Pos and ending in Pos+Size, falls within the specified
3800 /// sequential range (Low, Low+Size]. or is undef.
3801 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3802 unsigned Pos, unsigned Size, int Low) {
3803 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3804 if (!isUndefOrEqual(Mask[i], Low))
3809 /// isVEXTRACTIndex - Return true if the specified
3810 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3811 /// suitable for instruction that extract 128 or 256 bit vectors
3812 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
3813 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3814 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3817 // The index should be aligned on a vecWidth-bit boundary.
3819 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3821 MVT VT = N->getSimpleValueType(0);
3822 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
3823 bool Result = (Index * ElSize) % vecWidth == 0;
3828 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
3829 /// operand specifies a subvector insert that is suitable for input to
3830 /// insertion of 128 or 256-bit subvectors
3831 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
3832 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3833 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3835 // The index should be aligned on a vecWidth-bit boundary.
3837 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3839 MVT VT = N->getSimpleValueType(0);
3840 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
3841 bool Result = (Index * ElSize) % vecWidth == 0;
3846 bool X86::isVINSERT128Index(SDNode *N) {
3847 return isVINSERTIndex(N, 128);
3850 bool X86::isVINSERT256Index(SDNode *N) {
3851 return isVINSERTIndex(N, 256);
3854 bool X86::isVEXTRACT128Index(SDNode *N) {
3855 return isVEXTRACTIndex(N, 128);
3858 bool X86::isVEXTRACT256Index(SDNode *N) {
3859 return isVEXTRACTIndex(N, 256);
3862 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
3863 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
3864 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3865 llvm_unreachable("Illegal extract subvector for VEXTRACT");
3868 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3870 MVT VecVT = N->getOperand(0).getSimpleValueType();
3871 MVT ElVT = VecVT.getVectorElementType();
3873 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
3874 return Index / NumElemsPerChunk;
3877 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
3878 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
3879 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3880 llvm_unreachable("Illegal insert subvector for VINSERT");
3883 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3885 MVT VecVT = N->getSimpleValueType(0);
3886 MVT ElVT = VecVT.getVectorElementType();
3888 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
3889 return Index / NumElemsPerChunk;
3892 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
3893 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
3894 /// and VINSERTI128 instructions.
3895 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
3896 return getExtractVEXTRACTImmediate(N, 128);
3899 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
3900 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
3901 /// and VINSERTI64x4 instructions.
3902 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
3903 return getExtractVEXTRACTImmediate(N, 256);
3906 /// getInsertVINSERT128Immediate - Return the appropriate immediate
3907 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
3908 /// and VINSERTI128 instructions.
3909 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
3910 return getInsertVINSERTImmediate(N, 128);
3913 /// getInsertVINSERT256Immediate - Return the appropriate immediate
3914 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
3915 /// and VINSERTI64x4 instructions.
3916 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
3917 return getInsertVINSERTImmediate(N, 256);
3920 /// isZero - Returns true if Elt is a constant integer zero
3921 static bool isZero(SDValue V) {
3922 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
3923 return C && C->isNullValue();
3926 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3928 bool X86::isZeroNode(SDValue Elt) {
3931 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
3932 return CFP->getValueAPF().isPosZero();
3936 /// getZeroVector - Returns a vector of specified type with all zero elements.
3938 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
3939 SelectionDAG &DAG, SDLoc dl) {
3940 assert(VT.isVector() && "Expected a vector type");
3942 // Always build SSE zero vectors as <4 x i32> bitcasted
3943 // to their dest type. This ensures they get CSE'd.
3945 if (VT.is128BitVector()) { // SSE
3946 if (Subtarget->hasSSE2()) { // SSE2
3947 SDValue Cst = DAG.getConstant(0, MVT::i32);
3948 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3950 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
3951 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3953 } else if (VT.is256BitVector()) { // AVX
3954 if (Subtarget->hasInt256()) { // AVX2
3955 SDValue Cst = DAG.getConstant(0, MVT::i32);
3956 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
3957 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
3959 // 256-bit logic and arithmetic instructions in AVX are all
3960 // floating-point, no support for integer ops. Emit fp zeroed vectors.
3961 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
3962 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
3963 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
3965 } else if (VT.is512BitVector()) { // AVX-512
3966 SDValue Cst = DAG.getConstant(0, MVT::i32);
3967 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
3968 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
3969 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
3970 } else if (VT.getScalarType() == MVT::i1) {
3972 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
3973 && "Unexpected vector type");
3974 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
3975 && "Unexpected vector type");
3976 SDValue Cst = DAG.getConstant(0, MVT::i1);
3977 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
3978 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3980 llvm_unreachable("Unexpected vector type");
3982 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
3985 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
3986 SelectionDAG &DAG, SDLoc dl,
3987 unsigned vectorWidth) {
3988 assert((vectorWidth == 128 || vectorWidth == 256) &&
3989 "Unsupported vector width");
3990 EVT VT = Vec.getValueType();
3991 EVT ElVT = VT.getVectorElementType();
3992 unsigned Factor = VT.getSizeInBits()/vectorWidth;
3993 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
3994 VT.getVectorNumElements()/Factor);
3996 // Extract from UNDEF is UNDEF.
3997 if (Vec.getOpcode() == ISD::UNDEF)
3998 return DAG.getUNDEF(ResultVT);
4000 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4001 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4003 // This is the index of the first element of the vectorWidth-bit chunk
4005 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
4008 // If the input is a buildvector just emit a smaller one.
4009 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4010 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4011 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
4014 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
4015 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4018 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4019 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4020 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4021 /// instructions or a simple subregister reference. Idx is an index in the
4022 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4023 /// lowering EXTRACT_VECTOR_ELT operations easier.
4024 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4025 SelectionDAG &DAG, SDLoc dl) {
4026 assert((Vec.getValueType().is256BitVector() ||
4027 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4028 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4031 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4032 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4033 SelectionDAG &DAG, SDLoc dl) {
4034 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4035 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4038 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4039 unsigned IdxVal, SelectionDAG &DAG,
4040 SDLoc dl, unsigned vectorWidth) {
4041 assert((vectorWidth == 128 || vectorWidth == 256) &&
4042 "Unsupported vector width");
4043 // Inserting UNDEF is Result
4044 if (Vec.getOpcode() == ISD::UNDEF)
4046 EVT VT = Vec.getValueType();
4047 EVT ElVT = VT.getVectorElementType();
4048 EVT ResultVT = Result.getValueType();
4050 // Insert the relevant vectorWidth bits.
4051 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4053 // This is the index of the first element of the vectorWidth-bit chunk
4055 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
4058 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
4059 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4062 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4063 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4064 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4065 /// simple superregister reference. Idx is an index in the 128 bits
4066 /// we want. It need not be aligned to a 128-bit boundary. That makes
4067 /// lowering INSERT_VECTOR_ELT operations easier.
4068 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4069 SelectionDAG &DAG, SDLoc dl) {
4070 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4072 // For insertion into the zero index (low half) of a 256-bit vector, it is
4073 // more efficient to generate a blend with immediate instead of an insert*128.
4074 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4075 // extend the subvector to the size of the result vector. Make sure that
4076 // we are not recursing on that node by checking for undef here.
4077 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4078 Result.getOpcode() != ISD::UNDEF) {
4079 EVT ResultVT = Result.getValueType();
4080 SDValue ZeroIndex = DAG.getIntPtrConstant(0);
4081 SDValue Undef = DAG.getUNDEF(ResultVT);
4082 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4085 // The blend instruction, and therefore its mask, depend on the data type.
4086 MVT ScalarType = ResultVT.getScalarType().getSimpleVT();
4087 if (ScalarType.isFloatingPoint()) {
4088 // Choose either vblendps (float) or vblendpd (double).
4089 unsigned ScalarSize = ScalarType.getSizeInBits();
4090 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4091 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4092 SDValue Mask = DAG.getConstant(MaskVal, MVT::i8);
4093 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4096 const X86Subtarget &Subtarget =
4097 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4099 // AVX2 is needed for 256-bit integer blend support.
4100 // Integers must be cast to 32-bit because there is only vpblendd;
4101 // vpblendw can't be used for this because it has a handicapped mask.
4103 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4104 // is still more efficient than using the wrong domain vinsertf128 that
4105 // will be created by InsertSubVector().
4106 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4108 SDValue Mask = DAG.getConstant(0x0f, MVT::i8);
4109 Vec256 = DAG.getNode(ISD::BITCAST, dl, CastVT, Vec256);
4110 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4111 return DAG.getNode(ISD::BITCAST, dl, ResultVT, Vec256);
4114 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4117 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4118 SelectionDAG &DAG, SDLoc dl) {
4119 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4120 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4123 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4124 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4125 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4126 /// large BUILD_VECTORS.
4127 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4128 unsigned NumElems, SelectionDAG &DAG,
4130 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4131 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4134 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4135 unsigned NumElems, SelectionDAG &DAG,
4137 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4138 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4141 /// getOnesVector - Returns a vector of specified type with all bits set.
4142 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4143 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4144 /// Then bitcast to their original type, ensuring they get CSE'd.
4145 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4147 assert(VT.isVector() && "Expected a vector type");
4149 SDValue Cst = DAG.getConstant(~0U, MVT::i32);
4151 if (VT.is256BitVector()) {
4152 if (HasInt256) { // AVX2
4153 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4154 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4156 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4157 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4159 } else if (VT.is128BitVector()) {
4160 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4162 llvm_unreachable("Unexpected vector type");
4164 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4167 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4168 /// operation of specified width.
4169 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4171 unsigned NumElems = VT.getVectorNumElements();
4172 SmallVector<int, 8> Mask;
4173 Mask.push_back(NumElems);
4174 for (unsigned i = 1; i != NumElems; ++i)
4176 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4179 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4180 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4182 unsigned NumElems = VT.getVectorNumElements();
4183 SmallVector<int, 8> Mask;
4184 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4186 Mask.push_back(i + NumElems);
4188 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4191 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4192 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4194 unsigned NumElems = VT.getVectorNumElements();
4195 SmallVector<int, 8> Mask;
4196 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4197 Mask.push_back(i + Half);
4198 Mask.push_back(i + NumElems + Half);
4200 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4203 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4204 /// vector of zero or undef vector. This produces a shuffle where the low
4205 /// element of V2 is swizzled into the zero/undef vector, landing at element
4206 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4207 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4209 const X86Subtarget *Subtarget,
4210 SelectionDAG &DAG) {
4211 MVT VT = V2.getSimpleValueType();
4213 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4214 unsigned NumElems = VT.getVectorNumElements();
4215 SmallVector<int, 16> MaskVec;
4216 for (unsigned i = 0; i != NumElems; ++i)
4217 // If this is the insertion idx, put the low elt of V2 here.
4218 MaskVec.push_back(i == Idx ? NumElems : i);
4219 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4222 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4223 /// target specific opcode. Returns true if the Mask could be calculated. Sets
4224 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
4225 /// shuffles which use a single input multiple times, and in those cases it will
4226 /// adjust the mask to only have indices within that single input.
4227 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4228 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4229 unsigned NumElems = VT.getVectorNumElements();
4233 bool IsFakeUnary = false;
4234 switch(N->getOpcode()) {
4235 case X86ISD::BLENDI:
4236 ImmN = N->getOperand(N->getNumOperands()-1);
4237 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4240 ImmN = N->getOperand(N->getNumOperands()-1);
4241 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4242 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4244 case X86ISD::UNPCKH:
4245 DecodeUNPCKHMask(VT, Mask);
4246 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4248 case X86ISD::UNPCKL:
4249 DecodeUNPCKLMask(VT, Mask);
4250 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4252 case X86ISD::MOVHLPS:
4253 DecodeMOVHLPSMask(NumElems, Mask);
4254 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4256 case X86ISD::MOVLHPS:
4257 DecodeMOVLHPSMask(NumElems, Mask);
4258 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4260 case X86ISD::PALIGNR:
4261 ImmN = N->getOperand(N->getNumOperands()-1);
4262 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4264 case X86ISD::PSHUFD:
4265 case X86ISD::VPERMILPI:
4266 ImmN = N->getOperand(N->getNumOperands()-1);
4267 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4270 case X86ISD::PSHUFHW:
4271 ImmN = N->getOperand(N->getNumOperands()-1);
4272 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4275 case X86ISD::PSHUFLW:
4276 ImmN = N->getOperand(N->getNumOperands()-1);
4277 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4280 case X86ISD::PSHUFB: {
4282 SDValue MaskNode = N->getOperand(1);
4283 while (MaskNode->getOpcode() == ISD::BITCAST)
4284 MaskNode = MaskNode->getOperand(0);
4286 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4287 // If we have a build-vector, then things are easy.
4288 EVT VT = MaskNode.getValueType();
4289 assert(VT.isVector() &&
4290 "Can't produce a non-vector with a build_vector!");
4291 if (!VT.isInteger())
4294 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4296 SmallVector<uint64_t, 32> RawMask;
4297 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4298 SDValue Op = MaskNode->getOperand(i);
4299 if (Op->getOpcode() == ISD::UNDEF) {
4300 RawMask.push_back((uint64_t)SM_SentinelUndef);
4303 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4306 APInt MaskElement = CN->getAPIntValue();
4308 // We now have to decode the element which could be any integer size and
4309 // extract each byte of it.
4310 for (int j = 0; j < NumBytesPerElement; ++j) {
4311 // Note that this is x86 and so always little endian: the low byte is
4312 // the first byte of the mask.
4313 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4314 MaskElement = MaskElement.lshr(8);
4317 DecodePSHUFBMask(RawMask, Mask);
4321 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4325 SDValue Ptr = MaskLoad->getBasePtr();
4326 if (Ptr->getOpcode() == X86ISD::Wrapper)
4327 Ptr = Ptr->getOperand(0);
4329 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4330 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4333 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4334 DecodePSHUFBMask(C, Mask);
4342 case X86ISD::VPERMI:
4343 ImmN = N->getOperand(N->getNumOperands()-1);
4344 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4349 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4351 case X86ISD::VPERM2X128:
4352 ImmN = N->getOperand(N->getNumOperands()-1);
4353 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4354 if (Mask.empty()) return false;
4356 case X86ISD::MOVSLDUP:
4357 DecodeMOVSLDUPMask(VT, Mask);
4360 case X86ISD::MOVSHDUP:
4361 DecodeMOVSHDUPMask(VT, Mask);
4364 case X86ISD::MOVDDUP:
4365 DecodeMOVDDUPMask(VT, Mask);
4368 case X86ISD::MOVLHPD:
4369 case X86ISD::MOVLPD:
4370 case X86ISD::MOVLPS:
4371 // Not yet implemented
4373 default: llvm_unreachable("unknown target shuffle node");
4376 // If we have a fake unary shuffle, the shuffle mask is spread across two
4377 // inputs that are actually the same node. Re-map the mask to always point
4378 // into the first input.
4381 if (M >= (int)Mask.size())
4387 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4388 /// element of the result of the vector shuffle.
4389 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4392 return SDValue(); // Limit search depth.
4394 SDValue V = SDValue(N, 0);
4395 EVT VT = V.getValueType();
4396 unsigned Opcode = V.getOpcode();
4398 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4399 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4400 int Elt = SV->getMaskElt(Index);
4403 return DAG.getUNDEF(VT.getVectorElementType());
4405 unsigned NumElems = VT.getVectorNumElements();
4406 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4407 : SV->getOperand(1);
4408 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4411 // Recurse into target specific vector shuffles to find scalars.
4412 if (isTargetShuffle(Opcode)) {
4413 MVT ShufVT = V.getSimpleValueType();
4414 unsigned NumElems = ShufVT.getVectorNumElements();
4415 SmallVector<int, 16> ShuffleMask;
4418 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4421 int Elt = ShuffleMask[Index];
4423 return DAG.getUNDEF(ShufVT.getVectorElementType());
4425 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4427 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4431 // Actual nodes that may contain scalar elements
4432 if (Opcode == ISD::BITCAST) {
4433 V = V.getOperand(0);
4434 EVT SrcVT = V.getValueType();
4435 unsigned NumElems = VT.getVectorNumElements();
4437 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4441 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4442 return (Index == 0) ? V.getOperand(0)
4443 : DAG.getUNDEF(VT.getVectorElementType());
4445 if (V.getOpcode() == ISD::BUILD_VECTOR)
4446 return V.getOperand(Index);
4451 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4453 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4454 unsigned NumNonZero, unsigned NumZero,
4456 const X86Subtarget* Subtarget,
4457 const TargetLowering &TLI) {
4465 // SSE4.1 - use PINSRB to insert each byte directly.
4466 if (Subtarget->hasSSE41()) {
4467 for (unsigned i = 0; i < 16; ++i) {
4468 bool isNonZero = (NonZeros & (1 << i)) != 0;
4472 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4474 V = DAG.getUNDEF(MVT::v16i8);
4477 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4478 MVT::v16i8, V, Op.getOperand(i),
4479 DAG.getIntPtrConstant(i));
4486 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4487 for (unsigned i = 0; i < 16; ++i) {
4488 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4489 if (ThisIsNonZero && First) {
4491 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4493 V = DAG.getUNDEF(MVT::v8i16);
4498 SDValue ThisElt, LastElt;
4499 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4500 if (LastIsNonZero) {
4501 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4502 MVT::i16, Op.getOperand(i-1));
4504 if (ThisIsNonZero) {
4505 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4506 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4507 ThisElt, DAG.getConstant(8, MVT::i8));
4509 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4513 if (ThisElt.getNode())
4514 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4515 DAG.getIntPtrConstant(i/2));
4519 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4522 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4524 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4525 unsigned NumNonZero, unsigned NumZero,
4527 const X86Subtarget* Subtarget,
4528 const TargetLowering &TLI) {
4535 for (unsigned i = 0; i < 8; ++i) {
4536 bool isNonZero = (NonZeros & (1 << i)) != 0;
4540 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4542 V = DAG.getUNDEF(MVT::v8i16);
4545 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4546 MVT::v8i16, V, Op.getOperand(i),
4547 DAG.getIntPtrConstant(i));
4554 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
4555 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
4556 const X86Subtarget *Subtarget,
4557 const TargetLowering &TLI) {
4558 // Find all zeroable elements.
4559 std::bitset<4> Zeroable;
4560 for (int i=0; i < 4; ++i) {
4561 SDValue Elt = Op->getOperand(i);
4562 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
4564 assert(Zeroable.size() - Zeroable.count() > 1 &&
4565 "We expect at least two non-zero elements!");
4567 // We only know how to deal with build_vector nodes where elements are either
4568 // zeroable or extract_vector_elt with constant index.
4569 SDValue FirstNonZero;
4570 unsigned FirstNonZeroIdx;
4571 for (unsigned i=0; i < 4; ++i) {
4574 SDValue Elt = Op->getOperand(i);
4575 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4576 !isa<ConstantSDNode>(Elt.getOperand(1)))
4578 // Make sure that this node is extracting from a 128-bit vector.
4579 MVT VT = Elt.getOperand(0).getSimpleValueType();
4580 if (!VT.is128BitVector())
4582 if (!FirstNonZero.getNode()) {
4584 FirstNonZeroIdx = i;
4588 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
4589 SDValue V1 = FirstNonZero.getOperand(0);
4590 MVT VT = V1.getSimpleValueType();
4592 // See if this build_vector can be lowered as a blend with zero.
4594 unsigned EltMaskIdx, EltIdx;
4596 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
4597 if (Zeroable[EltIdx]) {
4598 // The zero vector will be on the right hand side.
4599 Mask[EltIdx] = EltIdx+4;
4603 Elt = Op->getOperand(EltIdx);
4604 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
4605 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
4606 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
4608 Mask[EltIdx] = EltIdx;
4612 // Let the shuffle legalizer deal with blend operations.
4613 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
4614 if (V1.getSimpleValueType() != VT)
4615 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
4616 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
4619 // See if we can lower this build_vector to a INSERTPS.
4620 if (!Subtarget->hasSSE41())
4623 SDValue V2 = Elt.getOperand(0);
4624 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
4627 bool CanFold = true;
4628 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
4632 SDValue Current = Op->getOperand(i);
4633 SDValue SrcVector = Current->getOperand(0);
4636 CanFold = SrcVector == V1 &&
4637 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
4643 assert(V1.getNode() && "Expected at least two non-zero elements!");
4644 if (V1.getSimpleValueType() != MVT::v4f32)
4645 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
4646 if (V2.getSimpleValueType() != MVT::v4f32)
4647 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
4649 // Ok, we can emit an INSERTPS instruction.
4650 unsigned ZMask = Zeroable.to_ulong();
4652 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
4653 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
4654 SDValue Result = DAG.getNode(X86ISD::INSERTPS, SDLoc(Op), MVT::v4f32, V1, V2,
4655 DAG.getIntPtrConstant(InsertPSMask));
4656 return DAG.getNode(ISD::BITCAST, SDLoc(Op), VT, Result);
4659 /// Return a vector logical shift node.
4660 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4661 unsigned NumBits, SelectionDAG &DAG,
4662 const TargetLowering &TLI, SDLoc dl) {
4663 assert(VT.is128BitVector() && "Unknown type for VShift");
4664 MVT ShVT = MVT::v2i64;
4665 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4666 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4667 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(SrcOp.getValueType());
4668 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
4669 SDValue ShiftVal = DAG.getConstant(NumBits/8, ScalarShiftTy);
4670 return DAG.getNode(ISD::BITCAST, dl, VT,
4671 DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
4675 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
4677 // Check if the scalar load can be widened into a vector load. And if
4678 // the address is "base + cst" see if the cst can be "absorbed" into
4679 // the shuffle mask.
4680 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4681 SDValue Ptr = LD->getBasePtr();
4682 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4684 EVT PVT = LD->getValueType(0);
4685 if (PVT != MVT::i32 && PVT != MVT::f32)
4690 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4691 FI = FINode->getIndex();
4693 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4694 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4695 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4696 Offset = Ptr.getConstantOperandVal(1);
4697 Ptr = Ptr.getOperand(0);
4702 // FIXME: 256-bit vector instructions don't require a strict alignment,
4703 // improve this code to support it better.
4704 unsigned RequiredAlign = VT.getSizeInBits()/8;
4705 SDValue Chain = LD->getChain();
4706 // Make sure the stack object alignment is at least 16 or 32.
4707 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4708 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4709 if (MFI->isFixedObjectIndex(FI)) {
4710 // Can't change the alignment. FIXME: It's possible to compute
4711 // the exact stack offset and reference FI + adjust offset instead.
4712 // If someone *really* cares about this. That's the way to implement it.
4715 MFI->setObjectAlignment(FI, RequiredAlign);
4719 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4720 // Ptr + (Offset & ~15).
4723 if ((Offset % RequiredAlign) & 3)
4725 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4727 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
4728 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4730 int EltNo = (Offset - StartOffset) >> 2;
4731 unsigned NumElems = VT.getVectorNumElements();
4733 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4734 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4735 LD->getPointerInfo().getWithOffset(StartOffset),
4736 false, false, false, 0);
4738 SmallVector<int, 8> Mask(NumElems, EltNo);
4740 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4746 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
4747 /// elements can be replaced by a single large load which has the same value as
4748 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
4750 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4752 /// FIXME: we'd also like to handle the case where the last elements are zero
4753 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4754 /// There's even a handy isZeroNode for that purpose.
4755 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
4756 SDLoc &DL, SelectionDAG &DAG,
4757 bool isAfterLegalize) {
4758 unsigned NumElems = Elts.size();
4760 LoadSDNode *LDBase = nullptr;
4761 unsigned LastLoadedElt = -1U;
4763 // For each element in the initializer, see if we've found a load or an undef.
4764 // If we don't find an initial load element, or later load elements are
4765 // non-consecutive, bail out.
4766 for (unsigned i = 0; i < NumElems; ++i) {
4767 SDValue Elt = Elts[i];
4768 // Look through a bitcast.
4769 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
4770 Elt = Elt.getOperand(0);
4771 if (!Elt.getNode() ||
4772 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4775 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4777 LDBase = cast<LoadSDNode>(Elt.getNode());
4781 if (Elt.getOpcode() == ISD::UNDEF)
4784 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4785 EVT LdVT = Elt.getValueType();
4786 // Each loaded element must be the correct fractional portion of the
4787 // requested vector load.
4788 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
4790 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
4795 // If we have found an entire vector of loads and undefs, then return a large
4796 // load of the entire vector width starting at the base pointer. If we found
4797 // consecutive loads for the low half, generate a vzext_load node.
4798 if (LastLoadedElt == NumElems - 1) {
4799 assert(LDBase && "Did not find base load for merging consecutive loads");
4800 EVT EltVT = LDBase->getValueType(0);
4801 // Ensure that the input vector size for the merged loads matches the
4802 // cumulative size of the input elements.
4803 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
4806 if (isAfterLegalize &&
4807 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
4810 SDValue NewLd = SDValue();
4812 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4813 LDBase->getPointerInfo(), LDBase->isVolatile(),
4814 LDBase->isNonTemporal(), LDBase->isInvariant(),
4815 LDBase->getAlignment());
4817 if (LDBase->hasAnyUseOfValue(1)) {
4818 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
4820 SDValue(NewLd.getNode(), 1));
4821 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
4822 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
4823 SDValue(NewLd.getNode(), 1));
4829 //TODO: The code below fires only for for loading the low v2i32 / v2f32
4830 //of a v4i32 / v4f32. It's probably worth generalizing.
4831 EVT EltVT = VT.getVectorElementType();
4832 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
4833 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4834 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4835 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4837 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
4838 LDBase->getPointerInfo(),
4839 LDBase->getAlignment(),
4840 false/*isVolatile*/, true/*ReadMem*/,
4843 // Make sure the newly-created LOAD is in the same position as LDBase in
4844 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
4845 // update uses of LDBase's output chain to use the TokenFactor.
4846 if (LDBase->hasAnyUseOfValue(1)) {
4847 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
4848 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
4849 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
4850 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
4851 SDValue(ResNode.getNode(), 1));
4854 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4859 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
4860 /// to generate a splat value for the following cases:
4861 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
4862 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4863 /// a scalar load, or a constant.
4864 /// The VBROADCAST node is returned when a pattern is found,
4865 /// or SDValue() otherwise.
4866 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
4867 SelectionDAG &DAG) {
4868 // VBROADCAST requires AVX.
4869 // TODO: Splats could be generated for non-AVX CPUs using SSE
4870 // instructions, but there's less potential gain for only 128-bit vectors.
4871 if (!Subtarget->hasAVX())
4874 MVT VT = Op.getSimpleValueType();
4877 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
4878 "Unsupported vector type for broadcast.");
4883 switch (Op.getOpcode()) {
4885 // Unknown pattern found.
4888 case ISD::BUILD_VECTOR: {
4889 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
4890 BitVector UndefElements;
4891 SDValue Splat = BVOp->getSplatValue(&UndefElements);
4893 // We need a splat of a single value to use broadcast, and it doesn't
4894 // make any sense if the value is only in one element of the vector.
4895 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
4899 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4900 Ld.getOpcode() == ISD::ConstantFP);
4902 // Make sure that all of the users of a non-constant load are from the
4903 // BUILD_VECTOR node.
4904 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
4909 case ISD::VECTOR_SHUFFLE: {
4910 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4912 // Shuffles must have a splat mask where the first element is
4914 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
4917 SDValue Sc = Op.getOperand(0);
4918 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
4919 Sc.getOpcode() != ISD::BUILD_VECTOR) {
4921 if (!Subtarget->hasInt256())
4924 // Use the register form of the broadcast instruction available on AVX2.
4925 if (VT.getSizeInBits() >= 256)
4926 Sc = Extract128BitVector(Sc, 0, DAG, dl);
4927 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
4930 Ld = Sc.getOperand(0);
4931 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4932 Ld.getOpcode() == ISD::ConstantFP);
4934 // The scalar_to_vector node and the suspected
4935 // load node must have exactly one user.
4936 // Constants may have multiple users.
4938 // AVX-512 has register version of the broadcast
4939 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
4940 Ld.getValueType().getSizeInBits() >= 32;
4941 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
4948 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
4949 bool IsGE256 = (VT.getSizeInBits() >= 256);
4951 // When optimizing for size, generate up to 5 extra bytes for a broadcast
4952 // instruction to save 8 or more bytes of constant pool data.
4953 // TODO: If multiple splats are generated to load the same constant,
4954 // it may be detrimental to overall size. There needs to be a way to detect
4955 // that condition to know if this is truly a size win.
4956 const Function *F = DAG.getMachineFunction().getFunction();
4957 bool OptForSize = F->hasFnAttribute(Attribute::OptimizeForSize);
4959 // Handle broadcasting a single constant scalar from the constant pool
4961 // On Sandybridge (no AVX2), it is still better to load a constant vector
4962 // from the constant pool and not to broadcast it from a scalar.
4963 // But override that restriction when optimizing for size.
4964 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
4965 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
4966 EVT CVT = Ld.getValueType();
4967 assert(!CVT.isVector() && "Must not broadcast a vector type");
4969 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
4970 // For size optimization, also splat v2f64 and v2i64, and for size opt
4971 // with AVX2, also splat i8 and i16.
4972 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
4973 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
4974 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
4975 const Constant *C = nullptr;
4976 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
4977 C = CI->getConstantIntValue();
4978 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
4979 C = CF->getConstantFPValue();
4981 assert(C && "Invalid constant type");
4983 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4984 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
4985 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
4986 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
4987 MachinePointerInfo::getConstantPool(),
4988 false, false, false, Alignment);
4990 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
4994 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
4996 // Handle AVX2 in-register broadcasts.
4997 if (!IsLoad && Subtarget->hasInt256() &&
4998 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
4999 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5001 // The scalar source must be a normal load.
5005 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5006 (Subtarget->hasVLX() && ScalarSize == 64))
5007 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5009 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5010 // double since there is no vbroadcastsd xmm
5011 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5012 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5013 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5016 // Unsupported broadcast.
5020 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5021 /// underlying vector and index.
5023 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5025 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5027 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5028 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5031 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5033 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5035 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5036 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5039 // In this case the vector is the extract_subvector expression and the index
5040 // is 2, as specified by the shuffle.
5041 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5042 SDValue ShuffleVec = SVOp->getOperand(0);
5043 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5044 assert(ShuffleVecVT.getVectorElementType() ==
5045 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5047 int ShuffleIdx = SVOp->getMaskElt(Idx);
5048 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5049 ExtractedFromVec = ShuffleVec;
5055 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5056 MVT VT = Op.getSimpleValueType();
5058 // Skip if insert_vec_elt is not supported.
5059 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5060 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5064 unsigned NumElems = Op.getNumOperands();
5068 SmallVector<unsigned, 4> InsertIndices;
5069 SmallVector<int, 8> Mask(NumElems, -1);
5071 for (unsigned i = 0; i != NumElems; ++i) {
5072 unsigned Opc = Op.getOperand(i).getOpcode();
5074 if (Opc == ISD::UNDEF)
5077 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5078 // Quit if more than 1 elements need inserting.
5079 if (InsertIndices.size() > 1)
5082 InsertIndices.push_back(i);
5086 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5087 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5088 // Quit if non-constant index.
5089 if (!isa<ConstantSDNode>(ExtIdx))
5091 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5093 // Quit if extracted from vector of different type.
5094 if (ExtractedFromVec.getValueType() != VT)
5097 if (!VecIn1.getNode())
5098 VecIn1 = ExtractedFromVec;
5099 else if (VecIn1 != ExtractedFromVec) {
5100 if (!VecIn2.getNode())
5101 VecIn2 = ExtractedFromVec;
5102 else if (VecIn2 != ExtractedFromVec)
5103 // Quit if more than 2 vectors to shuffle
5107 if (ExtractedFromVec == VecIn1)
5109 else if (ExtractedFromVec == VecIn2)
5110 Mask[i] = Idx + NumElems;
5113 if (!VecIn1.getNode())
5116 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5117 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5118 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5119 unsigned Idx = InsertIndices[i];
5120 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5121 DAG.getIntPtrConstant(Idx));
5127 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5129 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5131 MVT VT = Op.getSimpleValueType();
5132 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5133 "Unexpected type in LowerBUILD_VECTORvXi1!");
5136 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5137 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5138 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5139 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5142 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5143 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
5144 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5145 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5148 bool AllContants = true;
5149 uint64_t Immediate = 0;
5150 int NonConstIdx = -1;
5151 bool IsSplat = true;
5152 unsigned NumNonConsts = 0;
5153 unsigned NumConsts = 0;
5154 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5155 SDValue In = Op.getOperand(idx);
5156 if (In.getOpcode() == ISD::UNDEF)
5158 if (!isa<ConstantSDNode>(In)) {
5159 AllContants = false;
5164 if (cast<ConstantSDNode>(In)->getZExtValue())
5165 Immediate |= (1ULL << idx);
5167 if (In != Op.getOperand(0))
5172 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
5173 DAG.getConstant(Immediate, MVT::i16));
5174 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
5175 DAG.getIntPtrConstant(0));
5178 if (NumNonConsts == 1 && NonConstIdx != 0) {
5181 SDValue VecAsImm = DAG.getConstant(Immediate,
5182 MVT::getIntegerVT(VT.getSizeInBits()));
5183 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
5186 DstVec = DAG.getUNDEF(VT);
5187 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5188 Op.getOperand(NonConstIdx),
5189 DAG.getIntPtrConstant(NonConstIdx));
5191 if (!IsSplat && (NonConstIdx != 0))
5192 llvm_unreachable("Unsupported BUILD_VECTOR operation");
5193 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
5196 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
5197 DAG.getConstant(-1, SelectVT),
5198 DAG.getConstant(0, SelectVT));
5200 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
5201 DAG.getConstant((Immediate | 1), SelectVT),
5202 DAG.getConstant(Immediate, SelectVT));
5203 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
5206 /// \brief Return true if \p N implements a horizontal binop and return the
5207 /// operands for the horizontal binop into V0 and V1.
5209 /// This is a helper function of PerformBUILD_VECTORCombine.
5210 /// This function checks that the build_vector \p N in input implements a
5211 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5212 /// operation to match.
5213 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5214 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5215 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5218 /// This function only analyzes elements of \p N whose indices are
5219 /// in range [BaseIdx, LastIdx).
5220 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5222 unsigned BaseIdx, unsigned LastIdx,
5223 SDValue &V0, SDValue &V1) {
5224 EVT VT = N->getValueType(0);
5226 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5227 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5228 "Invalid Vector in input!");
5230 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5231 bool CanFold = true;
5232 unsigned ExpectedVExtractIdx = BaseIdx;
5233 unsigned NumElts = LastIdx - BaseIdx;
5234 V0 = DAG.getUNDEF(VT);
5235 V1 = DAG.getUNDEF(VT);
5237 // Check if N implements a horizontal binop.
5238 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5239 SDValue Op = N->getOperand(i + BaseIdx);
5242 if (Op->getOpcode() == ISD::UNDEF) {
5243 // Update the expected vector extract index.
5244 if (i * 2 == NumElts)
5245 ExpectedVExtractIdx = BaseIdx;
5246 ExpectedVExtractIdx += 2;
5250 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5255 SDValue Op0 = Op.getOperand(0);
5256 SDValue Op1 = Op.getOperand(1);
5258 // Try to match the following pattern:
5259 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5260 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5261 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5262 Op0.getOperand(0) == Op1.getOperand(0) &&
5263 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5264 isa<ConstantSDNode>(Op1.getOperand(1)));
5268 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5269 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5271 if (i * 2 < NumElts) {
5272 if (V0.getOpcode() == ISD::UNDEF)
5273 V0 = Op0.getOperand(0);
5275 if (V1.getOpcode() == ISD::UNDEF)
5276 V1 = Op0.getOperand(0);
5277 if (i * 2 == NumElts)
5278 ExpectedVExtractIdx = BaseIdx;
5281 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5282 if (I0 == ExpectedVExtractIdx)
5283 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5284 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5285 // Try to match the following dag sequence:
5286 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5287 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5291 ExpectedVExtractIdx += 2;
5297 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5298 /// a concat_vector.
5300 /// This is a helper function of PerformBUILD_VECTORCombine.
5301 /// This function expects two 256-bit vectors called V0 and V1.
5302 /// At first, each vector is split into two separate 128-bit vectors.
5303 /// Then, the resulting 128-bit vectors are used to implement two
5304 /// horizontal binary operations.
5306 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5308 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5309 /// the two new horizontal binop.
5310 /// When Mode is set, the first horizontal binop dag node would take as input
5311 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5312 /// horizontal binop dag node would take as input the lower 128-bit of V1
5313 /// and the upper 128-bit of V1.
5315 /// HADD V0_LO, V0_HI
5316 /// HADD V1_LO, V1_HI
5318 /// Otherwise, the first horizontal binop dag node takes as input the lower
5319 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5320 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
5322 /// HADD V0_LO, V1_LO
5323 /// HADD V0_HI, V1_HI
5325 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5326 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5327 /// the upper 128-bits of the result.
5328 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5329 SDLoc DL, SelectionDAG &DAG,
5330 unsigned X86Opcode, bool Mode,
5331 bool isUndefLO, bool isUndefHI) {
5332 EVT VT = V0.getValueType();
5333 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5334 "Invalid nodes in input!");
5336 unsigned NumElts = VT.getVectorNumElements();
5337 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5338 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5339 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5340 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5341 EVT NewVT = V0_LO.getValueType();
5343 SDValue LO = DAG.getUNDEF(NewVT);
5344 SDValue HI = DAG.getUNDEF(NewVT);
5347 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5348 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5349 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5350 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5351 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5353 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5354 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5355 V1_LO->getOpcode() != ISD::UNDEF))
5356 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5358 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5359 V1_HI->getOpcode() != ISD::UNDEF))
5360 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5363 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5366 /// \brief Try to fold a build_vector that performs an 'addsub' into the
5367 /// sequence of 'vadd + vsub + blendi'.
5368 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
5369 const X86Subtarget *Subtarget) {
5371 EVT VT = BV->getValueType(0);
5372 unsigned NumElts = VT.getVectorNumElements();
5373 SDValue InVec0 = DAG.getUNDEF(VT);
5374 SDValue InVec1 = DAG.getUNDEF(VT);
5376 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5377 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5379 // Odd-numbered elements in the input build vector are obtained from
5380 // adding two integer/float elements.
5381 // Even-numbered elements in the input build vector are obtained from
5382 // subtracting two integer/float elements.
5383 unsigned ExpectedOpcode = ISD::FSUB;
5384 unsigned NextExpectedOpcode = ISD::FADD;
5385 bool AddFound = false;
5386 bool SubFound = false;
5388 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5389 SDValue Op = BV->getOperand(i);
5391 // Skip 'undef' values.
5392 unsigned Opcode = Op.getOpcode();
5393 if (Opcode == ISD::UNDEF) {
5394 std::swap(ExpectedOpcode, NextExpectedOpcode);
5398 // Early exit if we found an unexpected opcode.
5399 if (Opcode != ExpectedOpcode)
5402 SDValue Op0 = Op.getOperand(0);
5403 SDValue Op1 = Op.getOperand(1);
5405 // Try to match the following pattern:
5406 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5407 // Early exit if we cannot match that sequence.
5408 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5409 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5410 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5411 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5412 Op0.getOperand(1) != Op1.getOperand(1))
5415 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5419 // We found a valid add/sub node. Update the information accordingly.
5425 // Update InVec0 and InVec1.
5426 if (InVec0.getOpcode() == ISD::UNDEF)
5427 InVec0 = Op0.getOperand(0);
5428 if (InVec1.getOpcode() == ISD::UNDEF)
5429 InVec1 = Op1.getOperand(0);
5431 // Make sure that operands in input to each add/sub node always
5432 // come from a same pair of vectors.
5433 if (InVec0 != Op0.getOperand(0)) {
5434 if (ExpectedOpcode == ISD::FSUB)
5437 // FADD is commutable. Try to commute the operands
5438 // and then test again.
5439 std::swap(Op0, Op1);
5440 if (InVec0 != Op0.getOperand(0))
5444 if (InVec1 != Op1.getOperand(0))
5447 // Update the pair of expected opcodes.
5448 std::swap(ExpectedOpcode, NextExpectedOpcode);
5451 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5452 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5453 InVec1.getOpcode() != ISD::UNDEF)
5454 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5459 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
5460 const X86Subtarget *Subtarget) {
5462 EVT VT = N->getValueType(0);
5463 unsigned NumElts = VT.getVectorNumElements();
5464 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
5465 SDValue InVec0, InVec1;
5467 // Try to match an ADDSUB.
5468 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
5469 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
5470 SDValue Value = matchAddSub(BV, DAG, Subtarget);
5471 if (Value.getNode())
5475 // Try to match horizontal ADD/SUB.
5476 unsigned NumUndefsLO = 0;
5477 unsigned NumUndefsHI = 0;
5478 unsigned Half = NumElts/2;
5480 // Count the number of UNDEF operands in the build_vector in input.
5481 for (unsigned i = 0, e = Half; i != e; ++i)
5482 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5485 for (unsigned i = Half, e = NumElts; i != e; ++i)
5486 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5489 // Early exit if this is either a build_vector of all UNDEFs or all the
5490 // operands but one are UNDEF.
5491 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
5494 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
5495 // Try to match an SSE3 float HADD/HSUB.
5496 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5497 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5499 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5500 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5501 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
5502 // Try to match an SSSE3 integer HADD/HSUB.
5503 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5504 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
5506 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5507 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
5510 if (!Subtarget->hasAVX())
5513 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
5514 // Try to match an AVX horizontal add/sub of packed single/double
5515 // precision floating point values from 256-bit vectors.
5516 SDValue InVec2, InVec3;
5517 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
5518 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
5519 ((InVec0.getOpcode() == ISD::UNDEF ||
5520 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5521 ((InVec1.getOpcode() == ISD::UNDEF ||
5522 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5523 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5525 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
5526 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
5527 ((InVec0.getOpcode() == ISD::UNDEF ||
5528 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5529 ((InVec1.getOpcode() == ISD::UNDEF ||
5530 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5531 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5532 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
5533 // Try to match an AVX2 horizontal add/sub of signed integers.
5534 SDValue InVec2, InVec3;
5536 bool CanFold = true;
5538 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
5539 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
5540 ((InVec0.getOpcode() == ISD::UNDEF ||
5541 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5542 ((InVec1.getOpcode() == ISD::UNDEF ||
5543 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5544 X86Opcode = X86ISD::HADD;
5545 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
5546 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
5547 ((InVec0.getOpcode() == ISD::UNDEF ||
5548 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5549 ((InVec1.getOpcode() == ISD::UNDEF ||
5550 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5551 X86Opcode = X86ISD::HSUB;
5556 // Fold this build_vector into a single horizontal add/sub.
5557 // Do this only if the target has AVX2.
5558 if (Subtarget->hasAVX2())
5559 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
5561 // Do not try to expand this build_vector into a pair of horizontal
5562 // add/sub if we can emit a pair of scalar add/sub.
5563 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5566 // Convert this build_vector into a pair of horizontal binop followed by
5568 bool isUndefLO = NumUndefsLO == Half;
5569 bool isUndefHI = NumUndefsHI == Half;
5570 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
5571 isUndefLO, isUndefHI);
5575 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
5576 VT == MVT::v16i16) && Subtarget->hasAVX()) {
5578 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5579 X86Opcode = X86ISD::HADD;
5580 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5581 X86Opcode = X86ISD::HSUB;
5582 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5583 X86Opcode = X86ISD::FHADD;
5584 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5585 X86Opcode = X86ISD::FHSUB;
5589 // Don't try to expand this build_vector into a pair of horizontal add/sub
5590 // if we can simply emit a pair of scalar add/sub.
5591 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5594 // Convert this build_vector into two horizontal add/sub followed by
5596 bool isUndefLO = NumUndefsLO == Half;
5597 bool isUndefHI = NumUndefsHI == Half;
5598 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
5599 isUndefLO, isUndefHI);
5606 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5609 MVT VT = Op.getSimpleValueType();
5610 MVT ExtVT = VT.getVectorElementType();
5611 unsigned NumElems = Op.getNumOperands();
5613 // Generate vectors for predicate vectors.
5614 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5615 return LowerBUILD_VECTORvXi1(Op, DAG);
5617 // Vectors containing all zeros can be matched by pxor and xorps later
5618 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5619 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5620 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5621 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5624 return getZeroVector(VT, Subtarget, DAG, dl);
5627 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5628 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5629 // vpcmpeqd on 256-bit vectors.
5630 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5631 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5634 if (!VT.is512BitVector())
5635 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5638 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
5641 unsigned EVTBits = ExtVT.getSizeInBits();
5643 unsigned NumZero = 0;
5644 unsigned NumNonZero = 0;
5645 unsigned NonZeros = 0;
5646 bool IsAllConstants = true;
5647 SmallSet<SDValue, 8> Values;
5648 for (unsigned i = 0; i < NumElems; ++i) {
5649 SDValue Elt = Op.getOperand(i);
5650 if (Elt.getOpcode() == ISD::UNDEF)
5653 if (Elt.getOpcode() != ISD::Constant &&
5654 Elt.getOpcode() != ISD::ConstantFP)
5655 IsAllConstants = false;
5656 if (X86::isZeroNode(Elt))
5659 NonZeros |= (1 << i);
5664 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5665 if (NumNonZero == 0)
5666 return DAG.getUNDEF(VT);
5668 // Special case for single non-zero, non-undef, element.
5669 if (NumNonZero == 1) {
5670 unsigned Idx = countTrailingZeros(NonZeros);
5671 SDValue Item = Op.getOperand(Idx);
5673 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5674 // the value are obviously zero, truncate the value to i32 and do the
5675 // insertion that way. Only do this if the value is non-constant or if the
5676 // value is a constant being inserted into element 0. It is cheaper to do
5677 // a constant pool load than it is to do a movd + shuffle.
5678 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5679 (!IsAllConstants || Idx == 0)) {
5680 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5682 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5683 EVT VecVT = MVT::v4i32;
5685 // Truncate the value (which may itself be a constant) to i32, and
5686 // convert it to a vector with movd (S2V+shuffle to zero extend).
5687 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5688 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5690 ISD::BITCAST, dl, VT,
5691 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
5695 // If we have a constant or non-constant insertion into the low element of
5696 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5697 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5698 // depending on what the source datatype is.
5701 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5703 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5704 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5705 if (VT.is512BitVector()) {
5706 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5707 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5708 Item, DAG.getIntPtrConstant(0));
5710 assert((VT.is128BitVector() || VT.is256BitVector()) &&
5711 "Expected an SSE value type!");
5712 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5713 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5714 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5717 // We can't directly insert an i8 or i16 into a vector, so zero extend
5719 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5720 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5721 if (VT.is256BitVector()) {
5722 if (Subtarget->hasAVX()) {
5723 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
5724 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5726 // Without AVX, we need to extend to a 128-bit vector and then
5727 // insert into the 256-bit vector.
5728 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5729 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5730 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5733 assert(VT.is128BitVector() && "Expected an SSE value type!");
5734 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5735 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5737 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5741 // Is it a vector logical left shift?
5742 if (NumElems == 2 && Idx == 1 &&
5743 X86::isZeroNode(Op.getOperand(0)) &&
5744 !X86::isZeroNode(Op.getOperand(1))) {
5745 unsigned NumBits = VT.getSizeInBits();
5746 return getVShift(true, VT,
5747 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5748 VT, Op.getOperand(1)),
5749 NumBits/2, DAG, *this, dl);
5752 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5755 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5756 // is a non-constant being inserted into an element other than the low one,
5757 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5758 // movd/movss) to move this into the low element, then shuffle it into
5760 if (EVTBits == 32) {
5761 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5762 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
5766 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5767 if (Values.size() == 1) {
5768 if (EVTBits == 32) {
5769 // Instead of a shuffle like this:
5770 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5771 // Check if it's possible to issue this instead.
5772 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5773 unsigned Idx = countTrailingZeros(NonZeros);
5774 SDValue Item = Op.getOperand(Idx);
5775 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5776 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5781 // A vector full of immediates; various special cases are already
5782 // handled, so this is best done with a single constant-pool load.
5786 // For AVX-length vectors, see if we can use a vector load to get all of the
5787 // elements, otherwise build the individual 128-bit pieces and use
5788 // shuffles to put them in place.
5789 if (VT.is256BitVector() || VT.is512BitVector()) {
5790 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
5792 // Check for a build vector of consecutive loads.
5793 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
5796 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5798 // Build both the lower and upper subvector.
5799 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
5800 makeArrayRef(&V[0], NumElems/2));
5801 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
5802 makeArrayRef(&V[NumElems / 2], NumElems/2));
5804 // Recreate the wider vector with the lower and upper part.
5805 if (VT.is256BitVector())
5806 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5807 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5810 // Let legalizer expand 2-wide build_vectors.
5811 if (EVTBits == 64) {
5812 if (NumNonZero == 1) {
5813 // One half is zero or undef.
5814 unsigned Idx = countTrailingZeros(NonZeros);
5815 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5816 Op.getOperand(Idx));
5817 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5822 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5823 if (EVTBits == 8 && NumElems == 16)
5824 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5828 if (EVTBits == 16 && NumElems == 8)
5829 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5833 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
5834 if (EVTBits == 32 && NumElems == 4)
5835 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
5838 // If element VT is == 32 bits, turn it into a number of shuffles.
5839 SmallVector<SDValue, 8> V(NumElems);
5840 if (NumElems == 4 && NumZero > 0) {
5841 for (unsigned i = 0; i < 4; ++i) {
5842 bool isZero = !(NonZeros & (1 << i));
5844 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5846 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5849 for (unsigned i = 0; i < 2; ++i) {
5850 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5853 V[i] = V[i*2]; // Must be a zero vector.
5856 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5859 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5862 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5867 bool Reverse1 = (NonZeros & 0x3) == 2;
5868 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5872 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5873 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5875 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5878 if (Values.size() > 1 && VT.is128BitVector()) {
5879 // Check for a build vector of consecutive loads.
5880 for (unsigned i = 0; i < NumElems; ++i)
5881 V[i] = Op.getOperand(i);
5883 // Check for elements which are consecutive loads.
5884 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
5887 // Check for a build vector from mostly shuffle plus few inserting.
5888 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
5891 // For SSE 4.1, use insertps to put the high elements into the low element.
5892 if (Subtarget->hasSSE41()) {
5894 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5895 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5897 Result = DAG.getUNDEF(VT);
5899 for (unsigned i = 1; i < NumElems; ++i) {
5900 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5901 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5902 Op.getOperand(i), DAG.getIntPtrConstant(i));
5907 // Otherwise, expand into a number of unpckl*, start by extending each of
5908 // our (non-undef) elements to the full vector width with the element in the
5909 // bottom slot of the vector (which generates no code for SSE).
5910 for (unsigned i = 0; i < NumElems; ++i) {
5911 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5912 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5914 V[i] = DAG.getUNDEF(VT);
5917 // Next, we iteratively mix elements, e.g. for v4f32:
5918 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5919 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5920 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5921 unsigned EltStride = NumElems >> 1;
5922 while (EltStride != 0) {
5923 for (unsigned i = 0; i < EltStride; ++i) {
5924 // If V[i+EltStride] is undef and this is the first round of mixing,
5925 // then it is safe to just drop this shuffle: V[i] is already in the
5926 // right place, the one element (since it's the first round) being
5927 // inserted as undef can be dropped. This isn't safe for successive
5928 // rounds because they will permute elements within both vectors.
5929 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5930 EltStride == NumElems/2)
5933 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5942 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5943 // to create 256-bit vectors from two other 128-bit ones.
5944 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5946 MVT ResVT = Op.getSimpleValueType();
5948 assert((ResVT.is256BitVector() ||
5949 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
5951 SDValue V1 = Op.getOperand(0);
5952 SDValue V2 = Op.getOperand(1);
5953 unsigned NumElems = ResVT.getVectorNumElements();
5954 if (ResVT.is256BitVector())
5955 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
5957 if (Op.getNumOperands() == 4) {
5958 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
5959 ResVT.getVectorNumElements()/2);
5960 SDValue V3 = Op.getOperand(2);
5961 SDValue V4 = Op.getOperand(3);
5962 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
5963 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
5965 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
5968 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
5969 const X86Subtarget *Subtarget,
5970 SelectionDAG & DAG) {
5972 MVT ResVT = Op.getSimpleValueType();
5973 unsigned NumOfOperands = Op.getNumOperands();
5975 assert(isPowerOf2_32(NumOfOperands) &&
5976 "Unexpected number of operands in CONCAT_VECTORS");
5978 if (NumOfOperands > 2) {
5979 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
5980 ResVT.getVectorNumElements()/2);
5981 SmallVector<SDValue, 2> Ops;
5982 for (unsigned i = 0; i < NumOfOperands/2; i++)
5983 Ops.push_back(Op.getOperand(i));
5984 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
5986 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
5987 Ops.push_back(Op.getOperand(i));
5988 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
5989 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
5992 SDValue V1 = Op.getOperand(0);
5993 SDValue V2 = Op.getOperand(1);
5994 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
5995 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
5997 if (IsZeroV1 && IsZeroV2)
5998 return getZeroVector(ResVT, Subtarget, DAG, dl);
6000 SDValue ZeroIdx = DAG.getIntPtrConstant(0);
6001 SDValue Undef = DAG.getUNDEF(ResVT);
6002 unsigned NumElems = ResVT.getVectorNumElements();
6003 SDValue ShiftBits = DAG.getConstant(NumElems/2, MVT::i8);
6005 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6006 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6010 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6011 // Zero the upper bits of V1
6012 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6013 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6016 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6019 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6020 const X86Subtarget *Subtarget,
6021 SelectionDAG &DAG) {
6022 MVT VT = Op.getSimpleValueType();
6023 if (VT.getVectorElementType() == MVT::i1)
6024 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6026 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6027 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6028 Op.getNumOperands() == 4)));
6030 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6031 // from two other 128-bit ones.
6033 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6034 return LowerAVXCONCAT_VECTORS(Op, DAG);
6038 //===----------------------------------------------------------------------===//
6039 // Vector shuffle lowering
6041 // This is an experimental code path for lowering vector shuffles on x86. It is
6042 // designed to handle arbitrary vector shuffles and blends, gracefully
6043 // degrading performance as necessary. It works hard to recognize idiomatic
6044 // shuffles and lower them to optimal instruction patterns without leaving
6045 // a framework that allows reasonably efficient handling of all vector shuffle
6047 //===----------------------------------------------------------------------===//
6049 /// \brief Tiny helper function to identify a no-op mask.
6051 /// This is a somewhat boring predicate function. It checks whether the mask
6052 /// array input, which is assumed to be a single-input shuffle mask of the kind
6053 /// used by the X86 shuffle instructions (not a fully general
6054 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6055 /// in-place shuffle are 'no-op's.
6056 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6057 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6058 if (Mask[i] != -1 && Mask[i] != i)
6063 /// \brief Helper function to classify a mask as a single-input mask.
6065 /// This isn't a generic single-input test because in the vector shuffle
6066 /// lowering we canonicalize single inputs to be the first input operand. This
6067 /// means we can more quickly test for a single input by only checking whether
6068 /// an input from the second operand exists. We also assume that the size of
6069 /// mask corresponds to the size of the input vectors which isn't true in the
6070 /// fully general case.
6071 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6073 if (M >= (int)Mask.size())
6078 /// \brief Test whether there are elements crossing 128-bit lanes in this
6081 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6082 /// and we routinely test for these.
6083 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6084 int LaneSize = 128 / VT.getScalarSizeInBits();
6085 int Size = Mask.size();
6086 for (int i = 0; i < Size; ++i)
6087 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6092 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6094 /// This checks a shuffle mask to see if it is performing the same
6095 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6096 /// that it is also not lane-crossing. It may however involve a blend from the
6097 /// same lane of a second vector.
6099 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6100 /// non-trivial to compute in the face of undef lanes. The representation is
6101 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6102 /// entries from both V1 and V2 inputs to the wider mask.
6104 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6105 SmallVectorImpl<int> &RepeatedMask) {
6106 int LaneSize = 128 / VT.getScalarSizeInBits();
6107 RepeatedMask.resize(LaneSize, -1);
6108 int Size = Mask.size();
6109 for (int i = 0; i < Size; ++i) {
6112 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6113 // This entry crosses lanes, so there is no way to model this shuffle.
6116 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6117 if (RepeatedMask[i % LaneSize] == -1)
6118 // This is the first non-undef entry in this slot of a 128-bit lane.
6119 RepeatedMask[i % LaneSize] =
6120 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6121 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6122 // Found a mismatch with the repeated mask.
6128 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6131 /// This is a fast way to test a shuffle mask against a fixed pattern:
6133 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6135 /// It returns true if the mask is exactly as wide as the argument list, and
6136 /// each element of the mask is either -1 (signifying undef) or the value given
6137 /// in the argument.
6138 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6139 ArrayRef<int> ExpectedMask) {
6140 if (Mask.size() != ExpectedMask.size())
6143 int Size = Mask.size();
6145 // If the values are build vectors, we can look through them to find
6146 // equivalent inputs that make the shuffles equivalent.
6147 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6148 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6150 for (int i = 0; i < Size; ++i)
6151 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6152 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6153 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6154 if (!MaskBV || !ExpectedBV ||
6155 MaskBV->getOperand(Mask[i] % Size) !=
6156 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6163 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6165 /// This helper function produces an 8-bit shuffle immediate corresponding to
6166 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6167 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6170 /// NB: We rely heavily on "undef" masks preserving the input lane.
6171 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
6172 SelectionDAG &DAG) {
6173 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6174 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6175 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6176 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6177 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6180 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6181 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6182 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6183 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6184 return DAG.getConstant(Imm, MVT::i8);
6187 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6189 /// This is used as a fallback approach when first class blend instructions are
6190 /// unavailable. Currently it is only suitable for integer vectors, but could
6191 /// be generalized for floating point vectors if desirable.
6192 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6193 SDValue V2, ArrayRef<int> Mask,
6194 SelectionDAG &DAG) {
6195 assert(VT.isInteger() && "Only supports integer vector types!");
6196 MVT EltVT = VT.getScalarType();
6197 int NumEltBits = EltVT.getSizeInBits();
6198 SDValue Zero = DAG.getConstant(0, EltVT);
6199 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), EltVT);
6200 SmallVector<SDValue, 16> MaskOps;
6201 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6202 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6203 return SDValue(); // Shuffled input!
6204 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6207 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6208 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6209 // We have to cast V2 around.
6210 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6211 V2 = DAG.getNode(ISD::BITCAST, DL, VT,
6212 DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6213 DAG.getNode(ISD::BITCAST, DL, MaskVT, V1Mask),
6214 DAG.getNode(ISD::BITCAST, DL, MaskVT, V2)));
6215 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6218 /// \brief Try to emit a blend instruction for a shuffle.
6220 /// This doesn't do any checks for the availability of instructions for blending
6221 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6222 /// be matched in the backend with the type given. What it does check for is
6223 /// that the shuffle mask is in fact a blend.
6224 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6225 SDValue V2, ArrayRef<int> Mask,
6226 const X86Subtarget *Subtarget,
6227 SelectionDAG &DAG) {
6228 unsigned BlendMask = 0;
6229 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6230 if (Mask[i] >= Size) {
6231 if (Mask[i] != i + Size)
6232 return SDValue(); // Shuffled V2 input!
6233 BlendMask |= 1u << i;
6236 if (Mask[i] >= 0 && Mask[i] != i)
6237 return SDValue(); // Shuffled V1 input!
6239 switch (VT.SimpleTy) {
6244 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6245 DAG.getConstant(BlendMask, MVT::i8));
6249 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6253 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6254 // that instruction.
6255 if (Subtarget->hasAVX2()) {
6256 // Scale the blend by the number of 32-bit dwords per element.
6257 int Scale = VT.getScalarSizeInBits() / 32;
6259 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6260 if (Mask[i] >= Size)
6261 for (int j = 0; j < Scale; ++j)
6262 BlendMask |= 1u << (i * Scale + j);
6264 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6265 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
6266 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
6267 return DAG.getNode(ISD::BITCAST, DL, VT,
6268 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6269 DAG.getConstant(BlendMask, MVT::i8)));
6273 // For integer shuffles we need to expand the mask and cast the inputs to
6274 // v8i16s prior to blending.
6275 int Scale = 8 / VT.getVectorNumElements();
6277 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6278 if (Mask[i] >= Size)
6279 for (int j = 0; j < Scale; ++j)
6280 BlendMask |= 1u << (i * Scale + j);
6282 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
6283 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
6284 return DAG.getNode(ISD::BITCAST, DL, VT,
6285 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6286 DAG.getConstant(BlendMask, MVT::i8)));
6290 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6291 SmallVector<int, 8> RepeatedMask;
6292 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6293 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6294 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6296 for (int i = 0; i < 8; ++i)
6297 if (RepeatedMask[i] >= 16)
6298 BlendMask |= 1u << i;
6299 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6300 DAG.getConstant(BlendMask, MVT::i8));
6306 assert((VT.getSizeInBits() == 128 || Subtarget->hasAVX2()) &&
6307 "256-bit byte-blends require AVX2 support!");
6309 // Scale the blend by the number of bytes per element.
6310 int Scale = VT.getScalarSizeInBits() / 8;
6312 // This form of blend is always done on bytes. Compute the byte vector
6314 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6316 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6317 // mix of LLVM's code generator and the x86 backend. We tell the code
6318 // generator that boolean values in the elements of an x86 vector register
6319 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6320 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6321 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6322 // of the element (the remaining are ignored) and 0 in that high bit would
6323 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6324 // the LLVM model for boolean values in vector elements gets the relevant
6325 // bit set, it is set backwards and over constrained relative to x86's
6327 SmallVector<SDValue, 32> VSELECTMask;
6328 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6329 for (int j = 0; j < Scale; ++j)
6330 VSELECTMask.push_back(
6331 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
6332 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8));
6334 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
6335 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
6337 ISD::BITCAST, DL, VT,
6338 DAG.getNode(ISD::VSELECT, DL, BlendVT,
6339 DAG.getNode(ISD::BUILD_VECTOR, DL, BlendVT, VSELECTMask),
6344 llvm_unreachable("Not a supported integer vector type!");
6348 /// \brief Try to lower as a blend of elements from two inputs followed by
6349 /// a single-input permutation.
6351 /// This matches the pattern where we can blend elements from two inputs and
6352 /// then reduce the shuffle to a single-input permutation.
6353 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
6356 SelectionDAG &DAG) {
6357 // We build up the blend mask while checking whether a blend is a viable way
6358 // to reduce the shuffle.
6359 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6360 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
6362 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6366 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
6368 if (BlendMask[Mask[i] % Size] == -1)
6369 BlendMask[Mask[i] % Size] = Mask[i];
6370 else if (BlendMask[Mask[i] % Size] != Mask[i])
6371 return SDValue(); // Can't blend in the needed input!
6373 PermuteMask[i] = Mask[i] % Size;
6376 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6377 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
6380 /// \brief Generic routine to decompose a shuffle and blend into indepndent
6381 /// blends and permutes.
6383 /// This matches the extremely common pattern for handling combined
6384 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
6385 /// operations. It will try to pick the best arrangement of shuffles and
6387 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
6391 SelectionDAG &DAG) {
6392 // Shuffle the input elements into the desired positions in V1 and V2 and
6393 // blend them together.
6394 SmallVector<int, 32> V1Mask(Mask.size(), -1);
6395 SmallVector<int, 32> V2Mask(Mask.size(), -1);
6396 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6397 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6398 if (Mask[i] >= 0 && Mask[i] < Size) {
6399 V1Mask[i] = Mask[i];
6401 } else if (Mask[i] >= Size) {
6402 V2Mask[i] = Mask[i] - Size;
6403 BlendMask[i] = i + Size;
6406 // Try to lower with the simpler initial blend strategy unless one of the
6407 // input shuffles would be a no-op. We prefer to shuffle inputs as the
6408 // shuffle may be able to fold with a load or other benefit. However, when
6409 // we'll have to do 2x as many shuffles in order to achieve this, blending
6410 // first is a better strategy.
6411 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
6412 if (SDValue BlendPerm =
6413 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
6416 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
6417 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
6418 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6421 /// \brief Try to lower a vector shuffle as a byte rotation.
6423 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
6424 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
6425 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
6426 /// try to generically lower a vector shuffle through such an pattern. It
6427 /// does not check for the profitability of lowering either as PALIGNR or
6428 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
6429 /// This matches shuffle vectors that look like:
6431 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
6433 /// Essentially it concatenates V1 and V2, shifts right by some number of
6434 /// elements, and takes the low elements as the result. Note that while this is
6435 /// specified as a *right shift* because x86 is little-endian, it is a *left
6436 /// rotate* of the vector lanes.
6437 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
6440 const X86Subtarget *Subtarget,
6441 SelectionDAG &DAG) {
6442 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
6444 int NumElts = Mask.size();
6445 int NumLanes = VT.getSizeInBits() / 128;
6446 int NumLaneElts = NumElts / NumLanes;
6448 // We need to detect various ways of spelling a rotation:
6449 // [11, 12, 13, 14, 15, 0, 1, 2]
6450 // [-1, 12, 13, 14, -1, -1, 1, -1]
6451 // [-1, -1, -1, -1, -1, -1, 1, 2]
6452 // [ 3, 4, 5, 6, 7, 8, 9, 10]
6453 // [-1, 4, 5, 6, -1, -1, 9, -1]
6454 // [-1, 4, 5, 6, -1, -1, -1, -1]
6457 for (int l = 0; l < NumElts; l += NumLaneElts) {
6458 for (int i = 0; i < NumLaneElts; ++i) {
6459 if (Mask[l + i] == -1)
6461 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
6463 // Get the mod-Size index and lane correct it.
6464 int LaneIdx = (Mask[l + i] % NumElts) - l;
6465 // Make sure it was in this lane.
6466 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
6469 // Determine where a rotated vector would have started.
6470 int StartIdx = i - LaneIdx;
6472 // The identity rotation isn't interesting, stop.
6475 // If we found the tail of a vector the rotation must be the missing
6476 // front. If we found the head of a vector, it must be how much of the
6478 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
6481 Rotation = CandidateRotation;
6482 else if (Rotation != CandidateRotation)
6483 // The rotations don't match, so we can't match this mask.
6486 // Compute which value this mask is pointing at.
6487 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
6489 // Compute which of the two target values this index should be assigned
6490 // to. This reflects whether the high elements are remaining or the low
6491 // elements are remaining.
6492 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
6494 // Either set up this value if we've not encountered it before, or check
6495 // that it remains consistent.
6498 else if (TargetV != MaskV)
6499 // This may be a rotation, but it pulls from the inputs in some
6500 // unsupported interleaving.
6505 // Check that we successfully analyzed the mask, and normalize the results.
6506 assert(Rotation != 0 && "Failed to locate a viable rotation!");
6507 assert((Lo || Hi) && "Failed to find a rotated input vector!");
6513 // The actual rotate instruction rotates bytes, so we need to scale the
6514 // rotation based on how many bytes are in the vector lane.
6515 int Scale = 16 / NumLaneElts;
6517 // SSSE3 targets can use the palignr instruction.
6518 if (Subtarget->hasSSSE3()) {
6519 // Cast the inputs to i8 vector of correct length to match PALIGNR.
6520 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
6521 Lo = DAG.getNode(ISD::BITCAST, DL, AlignVT, Lo);
6522 Hi = DAG.getNode(ISD::BITCAST, DL, AlignVT, Hi);
6524 return DAG.getNode(ISD::BITCAST, DL, VT,
6525 DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Hi, Lo,
6526 DAG.getConstant(Rotation * Scale, MVT::i8)));
6529 assert(VT.getSizeInBits() == 128 &&
6530 "Rotate-based lowering only supports 128-bit lowering!");
6531 assert(Mask.size() <= 16 &&
6532 "Can shuffle at most 16 bytes in a 128-bit vector!");
6534 // Default SSE2 implementation
6535 int LoByteShift = 16 - Rotation * Scale;
6536 int HiByteShift = Rotation * Scale;
6538 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
6539 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
6540 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
6542 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
6543 DAG.getConstant(LoByteShift, MVT::i8));
6544 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
6545 DAG.getConstant(HiByteShift, MVT::i8));
6546 return DAG.getNode(ISD::BITCAST, DL, VT,
6547 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
6550 /// \brief Compute whether each element of a shuffle is zeroable.
6552 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6553 /// Either it is an undef element in the shuffle mask, the element of the input
6554 /// referenced is undef, or the element of the input referenced is known to be
6555 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6556 /// as many lanes with this technique as possible to simplify the remaining
6558 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6559 SDValue V1, SDValue V2) {
6560 SmallBitVector Zeroable(Mask.size(), false);
6562 while (V1.getOpcode() == ISD::BITCAST)
6563 V1 = V1->getOperand(0);
6564 while (V2.getOpcode() == ISD::BITCAST)
6565 V2 = V2->getOperand(0);
6567 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6568 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6570 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6572 // Handle the easy cases.
6573 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6578 // If this is an index into a build_vector node (which has the same number
6579 // of elements), dig out the input value and use it.
6580 SDValue V = M < Size ? V1 : V2;
6581 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6584 SDValue Input = V.getOperand(M % Size);
6585 // The UNDEF opcode check really should be dead code here, but not quite
6586 // worth asserting on (it isn't invalid, just unexpected).
6587 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6594 /// \brief Try to emit a bitmask instruction for a shuffle.
6596 /// This handles cases where we can model a blend exactly as a bitmask due to
6597 /// one of the inputs being zeroable.
6598 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6599 SDValue V2, ArrayRef<int> Mask,
6600 SelectionDAG &DAG) {
6601 MVT EltVT = VT.getScalarType();
6602 int NumEltBits = EltVT.getSizeInBits();
6603 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6604 SDValue Zero = DAG.getConstant(0, IntEltVT);
6605 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), IntEltVT);
6606 if (EltVT.isFloatingPoint()) {
6607 Zero = DAG.getNode(ISD::BITCAST, DL, EltVT, Zero);
6608 AllOnes = DAG.getNode(ISD::BITCAST, DL, EltVT, AllOnes);
6610 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6611 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6613 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6616 if (Mask[i] % Size != i)
6617 return SDValue(); // Not a blend.
6619 V = Mask[i] < Size ? V1 : V2;
6620 else if (V != (Mask[i] < Size ? V1 : V2))
6621 return SDValue(); // Can only let one input through the mask.
6623 VMaskOps[i] = AllOnes;
6626 return SDValue(); // No non-zeroable elements!
6628 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6629 V = DAG.getNode(VT.isFloatingPoint()
6630 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6635 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
6637 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
6638 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
6639 /// matches elements from one of the input vectors shuffled to the left or
6640 /// right with zeroable elements 'shifted in'. It handles both the strictly
6641 /// bit-wise element shifts and the byte shift across an entire 128-bit double
6644 /// PSHL : (little-endian) left bit shift.
6645 /// [ zz, 0, zz, 2 ]
6646 /// [ -1, 4, zz, -1 ]
6647 /// PSRL : (little-endian) right bit shift.
6649 /// [ -1, -1, 7, zz]
6650 /// PSLLDQ : (little-endian) left byte shift
6651 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
6652 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
6653 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
6654 /// PSRLDQ : (little-endian) right byte shift
6655 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
6656 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
6657 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
6658 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
6659 SDValue V2, ArrayRef<int> Mask,
6660 SelectionDAG &DAG) {
6661 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6663 int Size = Mask.size();
6664 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
6666 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
6667 for (int i = 0; i < Size; i += Scale)
6668 for (int j = 0; j < Shift; ++j)
6669 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
6675 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
6676 for (int i = 0; i != Size; i += Scale) {
6677 unsigned Pos = Left ? i + Shift : i;
6678 unsigned Low = Left ? i : i + Shift;
6679 unsigned Len = Scale - Shift;
6680 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
6681 Low + (V == V1 ? 0 : Size)))
6685 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
6686 bool ByteShift = ShiftEltBits > 64;
6687 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
6688 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
6689 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
6691 // Normalize the scale for byte shifts to still produce an i64 element
6693 Scale = ByteShift ? Scale / 2 : Scale;
6695 // We need to round trip through the appropriate type for the shift.
6696 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
6697 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
6698 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
6699 "Illegal integer vector type");
6700 V = DAG.getNode(ISD::BITCAST, DL, ShiftVT, V);
6702 V = DAG.getNode(OpCode, DL, ShiftVT, V, DAG.getConstant(ShiftAmt, MVT::i8));
6703 return DAG.getNode(ISD::BITCAST, DL, VT, V);
6706 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
6707 // keep doubling the size of the integer elements up to that. We can
6708 // then shift the elements of the integer vector by whole multiples of
6709 // their width within the elements of the larger integer vector. Test each
6710 // multiple to see if we can find a match with the moved element indices
6711 // and that the shifted in elements are all zeroable.
6712 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
6713 for (int Shift = 1; Shift != Scale; ++Shift)
6714 for (bool Left : {true, false})
6715 if (CheckZeros(Shift, Scale, Left))
6716 for (SDValue V : {V1, V2})
6717 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
6724 /// \brief Lower a vector shuffle as a zero or any extension.
6726 /// Given a specific number of elements, element bit width, and extension
6727 /// stride, produce either a zero or any extension based on the available
6728 /// features of the subtarget.
6729 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
6730 SDLoc DL, MVT VT, int Scale, bool AnyExt, SDValue InputV,
6731 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6732 assert(Scale > 1 && "Need a scale to extend.");
6733 int NumElements = VT.getVectorNumElements();
6734 int EltBits = VT.getScalarSizeInBits();
6735 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
6736 "Only 8, 16, and 32 bit elements can be extended.");
6737 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
6739 // Found a valid zext mask! Try various lowering strategies based on the
6740 // input type and available ISA extensions.
6741 if (Subtarget->hasSSE41()) {
6742 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
6743 NumElements / Scale);
6744 return DAG.getNode(ISD::BITCAST, DL, VT,
6745 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
6748 // For any extends we can cheat for larger element sizes and use shuffle
6749 // instructions that can fold with a load and/or copy.
6750 if (AnyExt && EltBits == 32) {
6751 int PSHUFDMask[4] = {0, -1, 1, -1};
6753 ISD::BITCAST, DL, VT,
6754 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
6755 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
6756 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
6758 if (AnyExt && EltBits == 16 && Scale > 2) {
6759 int PSHUFDMask[4] = {0, -1, 0, -1};
6760 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
6761 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
6762 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
6763 int PSHUFHWMask[4] = {1, -1, -1, -1};
6765 ISD::BITCAST, DL, VT,
6766 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
6767 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
6768 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
6771 // If this would require more than 2 unpack instructions to expand, use
6772 // pshufb when available. We can only use more than 2 unpack instructions
6773 // when zero extending i8 elements which also makes it easier to use pshufb.
6774 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
6775 assert(NumElements == 16 && "Unexpected byte vector width!");
6776 SDValue PSHUFBMask[16];
6777 for (int i = 0; i < 16; ++i)
6779 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
6780 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
6781 return DAG.getNode(ISD::BITCAST, DL, VT,
6782 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
6783 DAG.getNode(ISD::BUILD_VECTOR, DL,
6784 MVT::v16i8, PSHUFBMask)));
6787 // Otherwise emit a sequence of unpacks.
6789 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
6790 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
6791 : getZeroVector(InputVT, Subtarget, DAG, DL);
6792 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
6793 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
6797 } while (Scale > 1);
6798 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
6801 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
6803 /// This routine will try to do everything in its power to cleverly lower
6804 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
6805 /// check for the profitability of this lowering, it tries to aggressively
6806 /// match this pattern. It will use all of the micro-architectural details it
6807 /// can to emit an efficient lowering. It handles both blends with all-zero
6808 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
6809 /// masking out later).
6811 /// The reason we have dedicated lowering for zext-style shuffles is that they
6812 /// are both incredibly common and often quite performance sensitive.
6813 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
6814 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
6815 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6816 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6818 int Bits = VT.getSizeInBits();
6819 int NumElements = VT.getVectorNumElements();
6820 assert(VT.getScalarSizeInBits() <= 32 &&
6821 "Exceeds 32-bit integer zero extension limit");
6822 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
6824 // Define a helper function to check a particular ext-scale and lower to it if
6826 auto Lower = [&](int Scale) -> SDValue {
6829 for (int i = 0; i < NumElements; ++i) {
6831 continue; // Valid anywhere but doesn't tell us anything.
6832 if (i % Scale != 0) {
6833 // Each of the extended elements need to be zeroable.
6837 // We no longer are in the anyext case.
6842 // Each of the base elements needs to be consecutive indices into the
6843 // same input vector.
6844 SDValue V = Mask[i] < NumElements ? V1 : V2;
6847 else if (InputV != V)
6848 return SDValue(); // Flip-flopping inputs.
6850 if (Mask[i] % NumElements != i / Scale)
6851 return SDValue(); // Non-consecutive strided elements.
6854 // If we fail to find an input, we have a zero-shuffle which should always
6855 // have already been handled.
6856 // FIXME: Maybe handle this here in case during blending we end up with one?
6860 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
6861 DL, VT, Scale, AnyExt, InputV, Subtarget, DAG);
6864 // The widest scale possible for extending is to a 64-bit integer.
6865 assert(Bits % 64 == 0 &&
6866 "The number of bits in a vector must be divisible by 64 on x86!");
6867 int NumExtElements = Bits / 64;
6869 // Each iteration, try extending the elements half as much, but into twice as
6871 for (; NumExtElements < NumElements; NumExtElements *= 2) {
6872 assert(NumElements % NumExtElements == 0 &&
6873 "The input vector size must be divisible by the extended size.");
6874 if (SDValue V = Lower(NumElements / NumExtElements))
6878 // General extends failed, but 128-bit vectors may be able to use MOVQ.
6882 // Returns one of the source operands if the shuffle can be reduced to a
6883 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
6884 auto CanZExtLowHalf = [&]() {
6885 for (int i = NumElements / 2; i != NumElements; ++i)
6888 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
6890 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
6895 if (SDValue V = CanZExtLowHalf()) {
6896 V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V);
6897 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
6898 return DAG.getNode(ISD::BITCAST, DL, VT, V);
6901 // No viable ext lowering found.
6905 /// \brief Try to get a scalar value for a specific element of a vector.
6907 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
6908 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
6909 SelectionDAG &DAG) {
6910 MVT VT = V.getSimpleValueType();
6911 MVT EltVT = VT.getVectorElementType();
6912 while (V.getOpcode() == ISD::BITCAST)
6913 V = V.getOperand(0);
6914 // If the bitcasts shift the element size, we can't extract an equivalent
6916 MVT NewVT = V.getSimpleValueType();
6917 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
6920 if (V.getOpcode() == ISD::BUILD_VECTOR ||
6921 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
6922 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
6927 /// \brief Helper to test for a load that can be folded with x86 shuffles.
6929 /// This is particularly important because the set of instructions varies
6930 /// significantly based on whether the operand is a load or not.
6931 static bool isShuffleFoldableLoad(SDValue V) {
6932 while (V.getOpcode() == ISD::BITCAST)
6933 V = V.getOperand(0);
6935 return ISD::isNON_EXTLoad(V.getNode());
6938 /// \brief Try to lower insertion of a single element into a zero vector.
6940 /// This is a common pattern that we have especially efficient patterns to lower
6941 /// across all subtarget feature sets.
6942 static SDValue lowerVectorShuffleAsElementInsertion(
6943 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
6944 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6945 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6947 MVT EltVT = VT.getVectorElementType();
6949 int V2Index = std::find_if(Mask.begin(), Mask.end(),
6950 [&Mask](int M) { return M >= (int)Mask.size(); }) -
6952 bool IsV1Zeroable = true;
6953 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6954 if (i != V2Index && !Zeroable[i]) {
6955 IsV1Zeroable = false;
6959 // Check for a single input from a SCALAR_TO_VECTOR node.
6960 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
6961 // all the smarts here sunk into that routine. However, the current
6962 // lowering of BUILD_VECTOR makes that nearly impossible until the old
6963 // vector shuffle lowering is dead.
6964 if (SDValue V2S = getScalarValueForVectorElement(
6965 V2, Mask[V2Index] - Mask.size(), DAG)) {
6966 // We need to zext the scalar if it is smaller than an i32.
6967 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
6968 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
6969 // Using zext to expand a narrow element won't work for non-zero
6974 // Zero-extend directly to i32.
6976 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
6978 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
6979 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
6980 EltVT == MVT::i16) {
6981 // Either not inserting from the low element of the input or the input
6982 // element size is too small to use VZEXT_MOVL to clear the high bits.
6986 if (!IsV1Zeroable) {
6987 // If V1 can't be treated as a zero vector we have fewer options to lower
6988 // this. We can't support integer vectors or non-zero targets cheaply, and
6989 // the V1 elements can't be permuted in any way.
6990 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
6991 if (!VT.isFloatingPoint() || V2Index != 0)
6993 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
6994 V1Mask[V2Index] = -1;
6995 if (!isNoopShuffleMask(V1Mask))
6997 // This is essentially a special case blend operation, but if we have
6998 // general purpose blend operations, they are always faster. Bail and let
6999 // the rest of the lowering handle these as blends.
7000 if (Subtarget->hasSSE41())
7003 // Otherwise, use MOVSD or MOVSS.
7004 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7005 "Only two types of floating point element types to handle!");
7006 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7010 // This lowering only works for the low element with floating point vectors.
7011 if (VT.isFloatingPoint() && V2Index != 0)
7014 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7016 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7019 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7020 // the desired position. Otherwise it is more efficient to do a vector
7021 // shift left. We know that we can do a vector shift left because all
7022 // the inputs are zero.
7023 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7024 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7025 V2Shuffle[V2Index] = 0;
7026 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7028 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7030 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7032 V2Index * EltVT.getSizeInBits()/8,
7033 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7034 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7040 /// \brief Try to lower broadcast of a single element.
7042 /// For convenience, this code also bundles all of the subtarget feature set
7043 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7044 /// a convenient way to factor it out.
7045 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7047 const X86Subtarget *Subtarget,
7048 SelectionDAG &DAG) {
7049 if (!Subtarget->hasAVX())
7051 if (VT.isInteger() && !Subtarget->hasAVX2())
7054 // Check that the mask is a broadcast.
7055 int BroadcastIdx = -1;
7057 if (M >= 0 && BroadcastIdx == -1)
7059 else if (M >= 0 && M != BroadcastIdx)
7062 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7063 "a sorted mask where the broadcast "
7066 // Go up the chain of (vector) values to find a scalar load that we can
7067 // combine with the broadcast.
7069 switch (V.getOpcode()) {
7070 case ISD::CONCAT_VECTORS: {
7071 int OperandSize = Mask.size() / V.getNumOperands();
7072 V = V.getOperand(BroadcastIdx / OperandSize);
7073 BroadcastIdx %= OperandSize;
7077 case ISD::INSERT_SUBVECTOR: {
7078 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7079 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7083 int BeginIdx = (int)ConstantIdx->getZExtValue();
7085 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7086 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7087 BroadcastIdx -= BeginIdx;
7098 // Check if this is a broadcast of a scalar. We special case lowering
7099 // for scalars so that we can more effectively fold with loads.
7100 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7101 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7102 V = V.getOperand(BroadcastIdx);
7104 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7105 // Only AVX2 has register broadcasts.
7106 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7108 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7109 // We can't broadcast from a vector register without AVX2, and we can only
7110 // broadcast from the zero-element of a vector register.
7114 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7117 // Check for whether we can use INSERTPS to perform the shuffle. We only use
7118 // INSERTPS when the V1 elements are already in the correct locations
7119 // because otherwise we can just always use two SHUFPS instructions which
7120 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
7121 // perform INSERTPS if a single V1 element is out of place and all V2
7122 // elements are zeroable.
7123 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
7125 SelectionDAG &DAG) {
7126 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7127 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7128 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7129 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7131 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7134 int V1DstIndex = -1;
7135 int V2DstIndex = -1;
7136 bool V1UsedInPlace = false;
7138 for (int i = 0; i < 4; ++i) {
7139 // Synthesize a zero mask from the zeroable elements (includes undefs).
7145 // Flag if we use any V1 inputs in place.
7147 V1UsedInPlace = true;
7151 // We can only insert a single non-zeroable element.
7152 if (V1DstIndex != -1 || V2DstIndex != -1)
7156 // V1 input out of place for insertion.
7159 // V2 input for insertion.
7164 // Don't bother if we have no (non-zeroable) element for insertion.
7165 if (V1DstIndex == -1 && V2DstIndex == -1)
7168 // Determine element insertion src/dst indices. The src index is from the
7169 // start of the inserted vector, not the start of the concatenated vector.
7170 unsigned V2SrcIndex = 0;
7171 if (V1DstIndex != -1) {
7172 // If we have a V1 input out of place, we use V1 as the V2 element insertion
7173 // and don't use the original V2 at all.
7174 V2SrcIndex = Mask[V1DstIndex];
7175 V2DstIndex = V1DstIndex;
7178 V2SrcIndex = Mask[V2DstIndex] - 4;
7181 // If no V1 inputs are used in place, then the result is created only from
7182 // the zero mask and the V2 insertion - so remove V1 dependency.
7184 V1 = DAG.getUNDEF(MVT::v4f32);
7186 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
7187 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7189 // Insert the V2 element into the desired position.
7191 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7192 DAG.getConstant(InsertPSMask, MVT::i8));
7195 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
7196 /// UNPCK instruction.
7198 /// This specifically targets cases where we end up with alternating between
7199 /// the two inputs, and so can permute them into something that feeds a single
7200 /// UNPCK instruction. Note that this routine only targets integer vectors
7201 /// because for floating point vectors we have a generalized SHUFPS lowering
7202 /// strategy that handles everything that doesn't *exactly* match an unpack,
7203 /// making this clever lowering unnecessary.
7204 static SDValue lowerVectorShuffleAsUnpack(SDLoc DL, MVT VT, SDValue V1,
7205 SDValue V2, ArrayRef<int> Mask,
7206 SelectionDAG &DAG) {
7207 assert(!VT.isFloatingPoint() &&
7208 "This routine only supports integer vectors.");
7209 assert(!isSingleInputShuffleMask(Mask) &&
7210 "This routine should only be used when blending two inputs.");
7211 assert(Mask.size() >= 2 && "Single element masks are invalid.");
7213 int Size = Mask.size();
7215 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
7216 return M >= 0 && M % Size < Size / 2;
7218 int NumHiInputs = std::count_if(
7219 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
7221 bool UnpackLo = NumLoInputs >= NumHiInputs;
7223 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
7224 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7225 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7227 for (int i = 0; i < Size; ++i) {
7231 // Each element of the unpack contains Scale elements from this mask.
7232 int UnpackIdx = i / Scale;
7234 // We only handle the case where V1 feeds the first slots of the unpack.
7235 // We rely on canonicalization to ensure this is the case.
7236 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
7239 // Setup the mask for this input. The indexing is tricky as we have to
7240 // handle the unpack stride.
7241 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
7242 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
7246 // If we will have to shuffle both inputs to use the unpack, check whether
7247 // we can just unpack first and shuffle the result. If so, skip this unpack.
7248 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
7249 !isNoopShuffleMask(V2Mask))
7252 // Shuffle the inputs into place.
7253 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7254 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7256 // Cast the inputs to the type we will use to unpack them.
7257 V1 = DAG.getNode(ISD::BITCAST, DL, UnpackVT, V1);
7258 V2 = DAG.getNode(ISD::BITCAST, DL, UnpackVT, V2);
7260 // Unpack the inputs and cast the result back to the desired type.
7261 return DAG.getNode(ISD::BITCAST, DL, VT,
7262 DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
7263 DL, UnpackVT, V1, V2));
7266 // We try each unpack from the largest to the smallest to try and find one
7267 // that fits this mask.
7268 int OrigNumElements = VT.getVectorNumElements();
7269 int OrigScalarSize = VT.getScalarSizeInBits();
7270 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
7271 int Scale = ScalarSize / OrigScalarSize;
7272 int NumElements = OrigNumElements / Scale;
7273 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
7274 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
7278 // If none of the unpack-rooted lowerings worked (or were profitable) try an
7280 if (NumLoInputs == 0 || NumHiInputs == 0) {
7281 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
7282 "We have to have *some* inputs!");
7283 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
7285 // FIXME: We could consider the total complexity of the permute of each
7286 // possible unpacking. Or at the least we should consider how many
7287 // half-crossings are created.
7288 // FIXME: We could consider commuting the unpacks.
7290 SmallVector<int, 32> PermMask;
7291 PermMask.assign(Size, -1);
7292 for (int i = 0; i < Size; ++i) {
7296 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
7299 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
7301 return DAG.getVectorShuffle(
7302 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
7304 DAG.getUNDEF(VT), PermMask);
7310 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7312 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7313 /// support for floating point shuffles but not integer shuffles. These
7314 /// instructions will incur a domain crossing penalty on some chips though so
7315 /// it is better to avoid lowering through this for integer vectors where
7317 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7318 const X86Subtarget *Subtarget,
7319 SelectionDAG &DAG) {
7321 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7322 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7323 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7324 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7325 ArrayRef<int> Mask = SVOp->getMask();
7326 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7328 if (isSingleInputShuffleMask(Mask)) {
7329 // Use low duplicate instructions for masks that match their pattern.
7330 if (Subtarget->hasSSE3())
7331 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
7332 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
7334 // Straight shuffle of a single input vector. Simulate this by using the
7335 // single input as both of the "inputs" to this instruction..
7336 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7338 if (Subtarget->hasAVX()) {
7339 // If we have AVX, we can use VPERMILPS which will allow folding a load
7340 // into the shuffle.
7341 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7342 DAG.getConstant(SHUFPDMask, MVT::i8));
7345 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7346 DAG.getConstant(SHUFPDMask, MVT::i8));
7348 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7349 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7351 // If we have a single input, insert that into V1 if we can do so cheaply.
7352 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
7353 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7354 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
7356 // Try inverting the insertion since for v2 masks it is easy to do and we
7357 // can't reliably sort the mask one way or the other.
7358 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7359 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7360 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7361 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
7365 // Try to use one of the special instruction patterns to handle two common
7366 // blend patterns if a zero-blend above didn't work.
7367 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
7368 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7369 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
7370 // We can either use a special instruction to load over the low double or
7371 // to move just the low double.
7373 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
7375 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
7377 if (Subtarget->hasSSE41())
7378 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7382 // Use dedicated unpack instructions for masks that match their pattern.
7383 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7384 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7385 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7386 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7388 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7389 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
7390 DAG.getConstant(SHUFPDMask, MVT::i8));
7393 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7395 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7396 /// the integer unit to minimize domain crossing penalties. However, for blends
7397 /// it falls back to the floating point shuffle operation with appropriate bit
7399 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7400 const X86Subtarget *Subtarget,
7401 SelectionDAG &DAG) {
7403 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7404 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7405 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7406 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7407 ArrayRef<int> Mask = SVOp->getMask();
7408 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7410 if (isSingleInputShuffleMask(Mask)) {
7411 // Check for being able to broadcast a single element.
7412 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
7413 Mask, Subtarget, DAG))
7416 // Straight shuffle of a single input vector. For everything from SSE2
7417 // onward this has a single fast instruction with no scary immediates.
7418 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7419 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7420 int WidenedMask[4] = {
7421 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7422 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7424 ISD::BITCAST, DL, MVT::v2i64,
7425 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7426 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7428 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
7429 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
7430 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
7431 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
7433 // If we have a blend of two PACKUS operations an the blend aligns with the
7434 // low and half halves, we can just merge the PACKUS operations. This is
7435 // particularly important as it lets us merge shuffles that this routine itself
7437 auto GetPackNode = [](SDValue V) {
7438 while (V.getOpcode() == ISD::BITCAST)
7439 V = V.getOperand(0);
7441 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
7443 if (SDValue V1Pack = GetPackNode(V1))
7444 if (SDValue V2Pack = GetPackNode(V2))
7445 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7446 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
7447 Mask[0] == 0 ? V1Pack.getOperand(0)
7448 : V1Pack.getOperand(1),
7449 Mask[1] == 2 ? V2Pack.getOperand(0)
7450 : V2Pack.getOperand(1)));
7452 // Try to use shift instructions.
7454 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
7457 // When loading a scalar and then shuffling it into a vector we can often do
7458 // the insertion cheaply.
7459 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7460 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7462 // Try inverting the insertion since for v2 masks it is easy to do and we
7463 // can't reliably sort the mask one way or the other.
7464 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
7465 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7466 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
7469 // We have different paths for blend lowering, but they all must use the
7470 // *exact* same predicate.
7471 bool IsBlendSupported = Subtarget->hasSSE41();
7472 if (IsBlendSupported)
7473 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
7477 // Use dedicated unpack instructions for masks that match their pattern.
7478 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7479 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7480 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7481 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7483 // Try to use byte rotation instructions.
7484 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7485 if (Subtarget->hasSSSE3())
7486 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7487 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7490 // If we have direct support for blends, we should lower by decomposing into
7491 // a permute. That will be faster than the domain cross.
7492 if (IsBlendSupported)
7493 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
7496 // We implement this with SHUFPD which is pretty lame because it will likely
7497 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7498 // However, all the alternatives are still more cycles and newer chips don't
7499 // have this problem. It would be really nice if x86 had better shuffles here.
7500 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7501 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7502 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7503 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7506 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
7508 /// This is used to disable more specialized lowerings when the shufps lowering
7509 /// will happen to be efficient.
7510 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
7511 // This routine only handles 128-bit shufps.
7512 assert(Mask.size() == 4 && "Unsupported mask size!");
7514 // To lower with a single SHUFPS we need to have the low half and high half
7515 // each requiring a single input.
7516 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
7518 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
7524 /// \brief Lower a vector shuffle using the SHUFPS instruction.
7526 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
7527 /// It makes no assumptions about whether this is the *best* lowering, it simply
7529 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
7530 ArrayRef<int> Mask, SDValue V1,
7531 SDValue V2, SelectionDAG &DAG) {
7532 SDValue LowV = V1, HighV = V2;
7533 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7536 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7538 if (NumV2Elements == 1) {
7540 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7543 // Compute the index adjacent to V2Index and in the same half by toggling
7545 int V2AdjIndex = V2Index ^ 1;
7547 if (Mask[V2AdjIndex] == -1) {
7548 // Handles all the cases where we have a single V2 element and an undef.
7549 // This will only ever happen in the high lanes because we commute the
7550 // vector otherwise.
7552 std::swap(LowV, HighV);
7553 NewMask[V2Index] -= 4;
7555 // Handle the case where the V2 element ends up adjacent to a V1 element.
7556 // To make this work, blend them together as the first step.
7557 int V1Index = V2AdjIndex;
7558 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7559 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
7560 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7562 // Now proceed to reconstruct the final blend as we have the necessary
7563 // high or low half formed.
7570 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7571 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7573 } else if (NumV2Elements == 2) {
7574 if (Mask[0] < 4 && Mask[1] < 4) {
7575 // Handle the easy case where we have V1 in the low lanes and V2 in the
7579 } else if (Mask[2] < 4 && Mask[3] < 4) {
7580 // We also handle the reversed case because this utility may get called
7581 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
7582 // arrange things in the right direction.
7588 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7589 // trying to place elements directly, just blend them and set up the final
7590 // shuffle to place them.
7592 // The first two blend mask elements are for V1, the second two are for
7594 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7595 Mask[2] < 4 ? Mask[2] : Mask[3],
7596 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7597 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7598 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
7599 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7601 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7604 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7605 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7606 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7607 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7610 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
7611 getV4X86ShuffleImm8ForMask(NewMask, DAG));
7614 /// \brief Lower 4-lane 32-bit floating point shuffles.
7616 /// Uses instructions exclusively from the floating point unit to minimize
7617 /// domain crossing penalties, as these are sufficient to implement all v4f32
7619 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7620 const X86Subtarget *Subtarget,
7621 SelectionDAG &DAG) {
7623 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7624 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7625 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7626 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7627 ArrayRef<int> Mask = SVOp->getMask();
7628 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7631 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7633 if (NumV2Elements == 0) {
7634 // Check for being able to broadcast a single element.
7635 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
7636 Mask, Subtarget, DAG))
7639 // Use even/odd duplicate instructions for masks that match their pattern.
7640 if (Subtarget->hasSSE3()) {
7641 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
7642 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
7643 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
7644 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
7647 if (Subtarget->hasAVX()) {
7648 // If we have AVX, we can use VPERMILPS which will allow folding a load
7649 // into the shuffle.
7650 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
7651 getV4X86ShuffleImm8ForMask(Mask, DAG));
7654 // Otherwise, use a straight shuffle of a single input vector. We pass the
7655 // input vector to both operands to simulate this with a SHUFPS.
7656 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7657 getV4X86ShuffleImm8ForMask(Mask, DAG));
7660 // There are special ways we can lower some single-element blends. However, we
7661 // have custom ways we can lower more complex single-element blends below that
7662 // we defer to if both this and BLENDPS fail to match, so restrict this to
7663 // when the V2 input is targeting element 0 of the mask -- that is the fast
7665 if (NumV2Elements == 1 && Mask[0] >= 4)
7666 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
7667 Mask, Subtarget, DAG))
7670 if (Subtarget->hasSSE41()) {
7671 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
7675 // Use INSERTPS if we can complete the shuffle efficiently.
7676 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
7679 if (!isSingleSHUFPSMask(Mask))
7680 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
7681 DL, MVT::v4f32, V1, V2, Mask, DAG))
7685 // Use dedicated unpack instructions for masks that match their pattern.
7686 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
7687 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
7688 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
7689 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
7690 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
7691 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V2, V1);
7692 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
7693 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V2, V1);
7695 // Otherwise fall back to a SHUFPS lowering strategy.
7696 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
7699 /// \brief Lower 4-lane i32 vector shuffles.
7701 /// We try to handle these with integer-domain shuffles where we can, but for
7702 /// blends we use the floating point domain blend instructions.
7703 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7704 const X86Subtarget *Subtarget,
7705 SelectionDAG &DAG) {
7707 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7708 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7709 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7710 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7711 ArrayRef<int> Mask = SVOp->getMask();
7712 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7714 // Whenever we can lower this as a zext, that instruction is strictly faster
7715 // than any alternative. It also allows us to fold memory operands into the
7716 // shuffle in many cases.
7717 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
7718 Mask, Subtarget, DAG))
7722 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7724 if (NumV2Elements == 0) {
7725 // Check for being able to broadcast a single element.
7726 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
7727 Mask, Subtarget, DAG))
7730 // Straight shuffle of a single input vector. For everything from SSE2
7731 // onward this has a single fast instruction with no scary immediates.
7732 // We coerce the shuffle pattern to be compatible with UNPCK instructions
7733 // but we aren't actually going to use the UNPCK instruction because doing
7734 // so prevents folding a load into this instruction or making a copy.
7735 const int UnpackLoMask[] = {0, 0, 1, 1};
7736 const int UnpackHiMask[] = {2, 2, 3, 3};
7737 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
7738 Mask = UnpackLoMask;
7739 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
7740 Mask = UnpackHiMask;
7742 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7743 getV4X86ShuffleImm8ForMask(Mask, DAG));
7746 // Try to use shift instructions.
7748 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
7751 // There are special ways we can lower some single-element blends.
7752 if (NumV2Elements == 1)
7753 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
7754 Mask, Subtarget, DAG))
7757 // We have different paths for blend lowering, but they all must use the
7758 // *exact* same predicate.
7759 bool IsBlendSupported = Subtarget->hasSSE41();
7760 if (IsBlendSupported)
7761 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
7765 if (SDValue Masked =
7766 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
7769 // Use dedicated unpack instructions for masks that match their pattern.
7770 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
7771 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
7772 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
7773 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
7774 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
7775 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
7776 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
7777 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
7779 // Try to use byte rotation instructions.
7780 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7781 if (Subtarget->hasSSSE3())
7782 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7783 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
7786 // If we have direct support for blends, we should lower by decomposing into
7787 // a permute. That will be faster than the domain cross.
7788 if (IsBlendSupported)
7789 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
7792 // Try to lower by permuting the inputs into an unpack instruction.
7793 if (SDValue Unpack =
7794 lowerVectorShuffleAsUnpack(DL, MVT::v4i32, V1, V2, Mask, DAG))
7797 // We implement this with SHUFPS because it can blend from two vectors.
7798 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
7799 // up the inputs, bypassing domain shift penalties that we would encur if we
7800 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
7802 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
7803 DAG.getVectorShuffle(
7805 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
7806 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
7809 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
7810 /// shuffle lowering, and the most complex part.
7812 /// The lowering strategy is to try to form pairs of input lanes which are
7813 /// targeted at the same half of the final vector, and then use a dword shuffle
7814 /// to place them onto the right half, and finally unpack the paired lanes into
7815 /// their final position.
7817 /// The exact breakdown of how to form these dword pairs and align them on the
7818 /// correct sides is really tricky. See the comments within the function for
7819 /// more of the details.
7821 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
7822 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
7823 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
7824 /// vector, form the analogous 128-bit 8-element Mask.
7825 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
7826 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
7827 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7828 assert(VT.getScalarType() == MVT::i16 && "Bad input type!");
7829 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
7831 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
7832 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
7833 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
7835 SmallVector<int, 4> LoInputs;
7836 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
7837 [](int M) { return M >= 0; });
7838 std::sort(LoInputs.begin(), LoInputs.end());
7839 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
7840 SmallVector<int, 4> HiInputs;
7841 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
7842 [](int M) { return M >= 0; });
7843 std::sort(HiInputs.begin(), HiInputs.end());
7844 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
7846 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
7847 int NumHToL = LoInputs.size() - NumLToL;
7849 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
7850 int NumHToH = HiInputs.size() - NumLToH;
7851 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
7852 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
7853 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
7854 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
7856 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
7857 // such inputs we can swap two of the dwords across the half mark and end up
7858 // with <=2 inputs to each half in each half. Once there, we can fall through
7859 // to the generic code below. For example:
7861 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7862 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
7864 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
7865 // and an existing 2-into-2 on the other half. In this case we may have to
7866 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
7867 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
7868 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
7869 // because any other situation (including a 3-into-1 or 1-into-3 in the other
7870 // half than the one we target for fixing) will be fixed when we re-enter this
7871 // path. We will also combine away any sequence of PSHUFD instructions that
7872 // result into a single instruction. Here is an example of the tricky case:
7874 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7875 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
7877 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
7879 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
7880 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
7882 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
7883 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
7885 // The result is fine to be handled by the generic logic.
7886 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
7887 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
7888 int AOffset, int BOffset) {
7889 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
7890 "Must call this with A having 3 or 1 inputs from the A half.");
7891 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
7892 "Must call this with B having 1 or 3 inputs from the B half.");
7893 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
7894 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
7896 // Compute the index of dword with only one word among the three inputs in
7897 // a half by taking the sum of the half with three inputs and subtracting
7898 // the sum of the actual three inputs. The difference is the remaining
7901 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
7902 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
7903 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
7904 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
7905 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
7906 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
7907 int TripleNonInputIdx =
7908 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
7909 TripleDWord = TripleNonInputIdx / 2;
7911 // We use xor with one to compute the adjacent DWord to whichever one the
7913 OneInputDWord = (OneInput / 2) ^ 1;
7915 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
7916 // and BToA inputs. If there is also such a problem with the BToB and AToB
7917 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
7918 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
7919 // is essential that we don't *create* a 3<-1 as then we might oscillate.
7920 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
7921 // Compute how many inputs will be flipped by swapping these DWords. We
7923 // to balance this to ensure we don't form a 3-1 shuffle in the other
7925 int NumFlippedAToBInputs =
7926 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
7927 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
7928 int NumFlippedBToBInputs =
7929 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
7930 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
7931 if ((NumFlippedAToBInputs == 1 &&
7932 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
7933 (NumFlippedBToBInputs == 1 &&
7934 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
7935 // We choose whether to fix the A half or B half based on whether that
7936 // half has zero flipped inputs. At zero, we may not be able to fix it
7937 // with that half. We also bias towards fixing the B half because that
7938 // will more commonly be the high half, and we have to bias one way.
7939 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
7940 ArrayRef<int> Inputs) {
7941 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
7942 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
7943 PinnedIdx ^ 1) != Inputs.end();
7944 // Determine whether the free index is in the flipped dword or the
7945 // unflipped dword based on where the pinned index is. We use this bit
7946 // in an xor to conditionally select the adjacent dword.
7947 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
7948 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
7949 FixFreeIdx) != Inputs.end();
7950 if (IsFixIdxInput == IsFixFreeIdxInput)
7952 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
7953 FixFreeIdx) != Inputs.end();
7954 assert(IsFixIdxInput != IsFixFreeIdxInput &&
7955 "We need to be changing the number of flipped inputs!");
7956 int PSHUFHalfMask[] = {0, 1, 2, 3};
7957 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
7958 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
7960 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
7963 if (M != -1 && M == FixIdx)
7965 else if (M != -1 && M == FixFreeIdx)
7968 if (NumFlippedBToBInputs != 0) {
7970 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
7971 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
7973 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
7975 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
7976 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
7981 int PSHUFDMask[] = {0, 1, 2, 3};
7982 PSHUFDMask[ADWord] = BDWord;
7983 PSHUFDMask[BDWord] = ADWord;
7984 V = DAG.getNode(ISD::BITCAST, DL, VT,
7985 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT,
7986 DAG.getNode(ISD::BITCAST, DL, PSHUFDVT, V),
7987 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7989 // Adjust the mask to match the new locations of A and B.
7991 if (M != -1 && M/2 == ADWord)
7992 M = 2 * BDWord + M % 2;
7993 else if (M != -1 && M/2 == BDWord)
7994 M = 2 * ADWord + M % 2;
7996 // Recurse back into this routine to re-compute state now that this isn't
7997 // a 3 and 1 problem.
7998 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8001 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8002 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8003 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8004 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8006 // At this point there are at most two inputs to the low and high halves from
8007 // each half. That means the inputs can always be grouped into dwords and
8008 // those dwords can then be moved to the correct half with a dword shuffle.
8009 // We use at most one low and one high word shuffle to collect these paired
8010 // inputs into dwords, and finally a dword shuffle to place them.
8011 int PSHUFLMask[4] = {-1, -1, -1, -1};
8012 int PSHUFHMask[4] = {-1, -1, -1, -1};
8013 int PSHUFDMask[4] = {-1, -1, -1, -1};
8015 // First fix the masks for all the inputs that are staying in their
8016 // original halves. This will then dictate the targets of the cross-half
8018 auto fixInPlaceInputs =
8019 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8020 MutableArrayRef<int> SourceHalfMask,
8021 MutableArrayRef<int> HalfMask, int HalfOffset) {
8022 if (InPlaceInputs.empty())
8024 if (InPlaceInputs.size() == 1) {
8025 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8026 InPlaceInputs[0] - HalfOffset;
8027 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8030 if (IncomingInputs.empty()) {
8031 // Just fix all of the in place inputs.
8032 for (int Input : InPlaceInputs) {
8033 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8034 PSHUFDMask[Input / 2] = Input / 2;
8039 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8040 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8041 InPlaceInputs[0] - HalfOffset;
8042 // Put the second input next to the first so that they are packed into
8043 // a dword. We find the adjacent index by toggling the low bit.
8044 int AdjIndex = InPlaceInputs[0] ^ 1;
8045 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8046 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8047 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8049 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8050 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8052 // Now gather the cross-half inputs and place them into a free dword of
8053 // their target half.
8054 // FIXME: This operation could almost certainly be simplified dramatically to
8055 // look more like the 3-1 fixing operation.
8056 auto moveInputsToRightHalf = [&PSHUFDMask](
8057 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8058 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8059 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8061 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8062 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8064 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8066 int LowWord = Word & ~1;
8067 int HighWord = Word | 1;
8068 return isWordClobbered(SourceHalfMask, LowWord) ||
8069 isWordClobbered(SourceHalfMask, HighWord);
8072 if (IncomingInputs.empty())
8075 if (ExistingInputs.empty()) {
8076 // Map any dwords with inputs from them into the right half.
8077 for (int Input : IncomingInputs) {
8078 // If the source half mask maps over the inputs, turn those into
8079 // swaps and use the swapped lane.
8080 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8081 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8082 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8083 Input - SourceOffset;
8084 // We have to swap the uses in our half mask in one sweep.
8085 for (int &M : HalfMask)
8086 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8088 else if (M == Input)
8089 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8091 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8092 Input - SourceOffset &&
8093 "Previous placement doesn't match!");
8095 // Note that this correctly re-maps both when we do a swap and when
8096 // we observe the other side of the swap above. We rely on that to
8097 // avoid swapping the members of the input list directly.
8098 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8101 // Map the input's dword into the correct half.
8102 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8103 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8105 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8107 "Previous placement doesn't match!");
8110 // And just directly shift any other-half mask elements to be same-half
8111 // as we will have mirrored the dword containing the element into the
8112 // same position within that half.
8113 for (int &M : HalfMask)
8114 if (M >= SourceOffset && M < SourceOffset + 4) {
8115 M = M - SourceOffset + DestOffset;
8116 assert(M >= 0 && "This should never wrap below zero!");
8121 // Ensure we have the input in a viable dword of its current half. This
8122 // is particularly tricky because the original position may be clobbered
8123 // by inputs being moved and *staying* in that half.
8124 if (IncomingInputs.size() == 1) {
8125 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8126 int InputFixed = std::find(std::begin(SourceHalfMask),
8127 std::end(SourceHalfMask), -1) -
8128 std::begin(SourceHalfMask) + SourceOffset;
8129 SourceHalfMask[InputFixed - SourceOffset] =
8130 IncomingInputs[0] - SourceOffset;
8131 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8133 IncomingInputs[0] = InputFixed;
8135 } else if (IncomingInputs.size() == 2) {
8136 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8137 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8138 // We have two non-adjacent or clobbered inputs we need to extract from
8139 // the source half. To do this, we need to map them into some adjacent
8140 // dword slot in the source mask.
8141 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8142 IncomingInputs[1] - SourceOffset};
8144 // If there is a free slot in the source half mask adjacent to one of
8145 // the inputs, place the other input in it. We use (Index XOR 1) to
8146 // compute an adjacent index.
8147 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8148 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8149 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8150 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8151 InputsFixed[1] = InputsFixed[0] ^ 1;
8152 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8153 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8154 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8155 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8156 InputsFixed[0] = InputsFixed[1] ^ 1;
8157 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8158 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8159 // The two inputs are in the same DWord but it is clobbered and the
8160 // adjacent DWord isn't used at all. Move both inputs to the free
8162 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8163 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8164 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8165 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8167 // The only way we hit this point is if there is no clobbering
8168 // (because there are no off-half inputs to this half) and there is no
8169 // free slot adjacent to one of the inputs. In this case, we have to
8170 // swap an input with a non-input.
8171 for (int i = 0; i < 4; ++i)
8172 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8173 "We can't handle any clobbers here!");
8174 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8175 "Cannot have adjacent inputs here!");
8177 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8178 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8180 // We also have to update the final source mask in this case because
8181 // it may need to undo the above swap.
8182 for (int &M : FinalSourceHalfMask)
8183 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8184 M = InputsFixed[1] + SourceOffset;
8185 else if (M == InputsFixed[1] + SourceOffset)
8186 M = (InputsFixed[0] ^ 1) + SourceOffset;
8188 InputsFixed[1] = InputsFixed[0] ^ 1;
8191 // Point everything at the fixed inputs.
8192 for (int &M : HalfMask)
8193 if (M == IncomingInputs[0])
8194 M = InputsFixed[0] + SourceOffset;
8195 else if (M == IncomingInputs[1])
8196 M = InputsFixed[1] + SourceOffset;
8198 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8199 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8202 llvm_unreachable("Unhandled input size!");
8205 // Now hoist the DWord down to the right half.
8206 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8207 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8208 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8209 for (int &M : HalfMask)
8210 for (int Input : IncomingInputs)
8212 M = FreeDWord * 2 + Input % 2;
8214 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8215 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8216 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8217 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8219 // Now enact all the shuffles we've computed to move the inputs into their
8221 if (!isNoopShuffleMask(PSHUFLMask))
8222 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8223 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8224 if (!isNoopShuffleMask(PSHUFHMask))
8225 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8226 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8227 if (!isNoopShuffleMask(PSHUFDMask))
8228 V = DAG.getNode(ISD::BITCAST, DL, VT,
8229 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT,
8230 DAG.getNode(ISD::BITCAST, DL, PSHUFDVT, V),
8231 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8233 // At this point, each half should contain all its inputs, and we can then
8234 // just shuffle them into their final position.
8235 assert(std::count_if(LoMask.begin(), LoMask.end(),
8236 [](int M) { return M >= 4; }) == 0 &&
8237 "Failed to lift all the high half inputs to the low mask!");
8238 assert(std::count_if(HiMask.begin(), HiMask.end(),
8239 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8240 "Failed to lift all the low half inputs to the high mask!");
8242 // Do a half shuffle for the low mask.
8243 if (!isNoopShuffleMask(LoMask))
8244 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8245 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8247 // Do a half shuffle with the high mask after shifting its values down.
8248 for (int &M : HiMask)
8251 if (!isNoopShuffleMask(HiMask))
8252 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8253 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8258 /// \brief Helper to form a PSHUFB-based shuffle+blend.
8259 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
8260 SDValue V2, ArrayRef<int> Mask,
8261 SelectionDAG &DAG, bool &V1InUse,
8263 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8269 int Size = Mask.size();
8270 int Scale = 16 / Size;
8271 for (int i = 0; i < 16; ++i) {
8272 if (Mask[i / Scale] == -1) {
8273 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
8275 const int ZeroMask = 0x80;
8276 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
8278 int V2Idx = Mask[i / Scale] < Size
8280 : (Mask[i / Scale] - Size) * Scale + i % Scale;
8281 if (Zeroable[i / Scale])
8282 V1Idx = V2Idx = ZeroMask;
8283 V1Mask[i] = DAG.getConstant(V1Idx, MVT::i8);
8284 V2Mask[i] = DAG.getConstant(V2Idx, MVT::i8);
8285 V1InUse |= (ZeroMask != V1Idx);
8286 V2InUse |= (ZeroMask != V2Idx);
8291 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8292 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, V1),
8293 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
8295 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8296 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, V2),
8297 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
8299 // If we need shuffled inputs from both, blend the two.
8301 if (V1InUse && V2InUse)
8302 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
8304 V = V1InUse ? V1 : V2;
8306 // Cast the result back to the correct type.
8307 return DAG.getNode(ISD::BITCAST, DL, VT, V);
8310 /// \brief Generic lowering of 8-lane i16 shuffles.
8312 /// This handles both single-input shuffles and combined shuffle/blends with
8313 /// two inputs. The single input shuffles are immediately delegated to
8314 /// a dedicated lowering routine.
8316 /// The blends are lowered in one of three fundamental ways. If there are few
8317 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8318 /// of the input is significantly cheaper when lowered as an interleaving of
8319 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8320 /// halves of the inputs separately (making them have relatively few inputs)
8321 /// and then concatenate them.
8322 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8323 const X86Subtarget *Subtarget,
8324 SelectionDAG &DAG) {
8326 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8327 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8328 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8329 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8330 ArrayRef<int> OrigMask = SVOp->getMask();
8331 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8332 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8333 MutableArrayRef<int> Mask(MaskStorage);
8335 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8337 // Whenever we can lower this as a zext, that instruction is strictly faster
8338 // than any alternative.
8339 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8340 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8343 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8345 auto isV2 = [](int M) { return M >= 8; };
8347 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8349 if (NumV2Inputs == 0) {
8350 // Check for being able to broadcast a single element.
8351 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
8352 Mask, Subtarget, DAG))
8355 // Try to use shift instructions.
8357 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
8360 // Use dedicated unpack instructions for masks that match their pattern.
8361 if (isShuffleEquivalent(V1, V1, Mask, {0, 0, 1, 1, 2, 2, 3, 3}))
8362 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V1);
8363 if (isShuffleEquivalent(V1, V1, Mask, {4, 4, 5, 5, 6, 6, 7, 7}))
8364 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V1);
8366 // Try to use byte rotation instructions.
8367 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
8368 Mask, Subtarget, DAG))
8371 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
8375 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
8376 "All single-input shuffles should be canonicalized to be V1-input "
8379 // Try to use shift instructions.
8381 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
8384 // There are special ways we can lower some single-element blends.
8385 if (NumV2Inputs == 1)
8386 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
8387 Mask, Subtarget, DAG))
8390 // We have different paths for blend lowering, but they all must use the
8391 // *exact* same predicate.
8392 bool IsBlendSupported = Subtarget->hasSSE41();
8393 if (IsBlendSupported)
8394 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
8398 if (SDValue Masked =
8399 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
8402 // Use dedicated unpack instructions for masks that match their pattern.
8403 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 2, 10, 3, 11}))
8404 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
8405 if (isShuffleEquivalent(V1, V2, Mask, {4, 12, 5, 13, 6, 14, 7, 15}))
8406 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
8408 // Try to use byte rotation instructions.
8409 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8410 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
8413 if (SDValue BitBlend =
8414 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
8417 if (SDValue Unpack =
8418 lowerVectorShuffleAsUnpack(DL, MVT::v8i16, V1, V2, Mask, DAG))
8421 // If we can't directly blend but can use PSHUFB, that will be better as it
8422 // can both shuffle and set up the inefficient blend.
8423 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
8424 bool V1InUse, V2InUse;
8425 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
8429 // We can always bit-blend if we have to so the fallback strategy is to
8430 // decompose into single-input permutes and blends.
8431 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
8435 /// \brief Check whether a compaction lowering can be done by dropping even
8436 /// elements and compute how many times even elements must be dropped.
8438 /// This handles shuffles which take every Nth element where N is a power of
8439 /// two. Example shuffle masks:
8441 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8442 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8443 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8444 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8445 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8446 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8448 /// Any of these lanes can of course be undef.
8450 /// This routine only supports N <= 3.
8451 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8454 /// \returns N above, or the number of times even elements must be dropped if
8455 /// there is such a number. Otherwise returns zero.
8456 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8457 // Figure out whether we're looping over two inputs or just one.
8458 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8460 // The modulus for the shuffle vector entries is based on whether this is
8461 // a single input or not.
8462 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8463 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8464 "We should only be called with masks with a power-of-2 size!");
8466 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8468 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8469 // and 2^3 simultaneously. This is because we may have ambiguity with
8470 // partially undef inputs.
8471 bool ViableForN[3] = {true, true, true};
8473 for (int i = 0, e = Mask.size(); i < e; ++i) {
8474 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8479 bool IsAnyViable = false;
8480 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8481 if (ViableForN[j]) {
8484 // The shuffle mask must be equal to (i * 2^N) % M.
8485 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8488 ViableForN[j] = false;
8490 // Early exit if we exhaust the possible powers of two.
8495 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8499 // Return 0 as there is no viable power of two.
8503 /// \brief Generic lowering of v16i8 shuffles.
8505 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8506 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8507 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8508 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8510 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8511 const X86Subtarget *Subtarget,
8512 SelectionDAG &DAG) {
8514 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8515 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8516 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8517 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8518 ArrayRef<int> Mask = SVOp->getMask();
8519 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8521 // Try to use shift instructions.
8523 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
8526 // Try to use byte rotation instructions.
8527 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8528 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8531 // Try to use a zext lowering.
8532 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8533 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8537 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
8539 // For single-input shuffles, there are some nicer lowering tricks we can use.
8540 if (NumV2Elements == 0) {
8541 // Check for being able to broadcast a single element.
8542 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
8543 Mask, Subtarget, DAG))
8546 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
8547 // Notably, this handles splat and partial-splat shuffles more efficiently.
8548 // However, it only makes sense if the pre-duplication shuffle simplifies
8549 // things significantly. Currently, this means we need to be able to
8550 // express the pre-duplication shuffle as an i16 shuffle.
8552 // FIXME: We should check for other patterns which can be widened into an
8553 // i16 shuffle as well.
8554 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
8555 for (int i = 0; i < 16; i += 2)
8556 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
8561 auto tryToWidenViaDuplication = [&]() -> SDValue {
8562 if (!canWidenViaDuplication(Mask))
8564 SmallVector<int, 4> LoInputs;
8565 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
8566 [](int M) { return M >= 0 && M < 8; });
8567 std::sort(LoInputs.begin(), LoInputs.end());
8568 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
8570 SmallVector<int, 4> HiInputs;
8571 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
8572 [](int M) { return M >= 8; });
8573 std::sort(HiInputs.begin(), HiInputs.end());
8574 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
8577 bool TargetLo = LoInputs.size() >= HiInputs.size();
8578 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
8579 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
8581 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8582 SmallDenseMap<int, int, 8> LaneMap;
8583 for (int I : InPlaceInputs) {
8584 PreDupI16Shuffle[I/2] = I/2;
8587 int j = TargetLo ? 0 : 4, je = j + 4;
8588 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8589 // Check if j is already a shuffle of this input. This happens when
8590 // there are two adjacent bytes after we move the low one.
8591 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
8592 // If we haven't yet mapped the input, search for a slot into which
8594 while (j < je && PreDupI16Shuffle[j] != -1)
8598 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
8601 // Map this input with the i16 shuffle.
8602 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
8605 // Update the lane map based on the mapping we ended up with.
8606 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
8609 ISD::BITCAST, DL, MVT::v16i8,
8610 DAG.getVectorShuffle(MVT::v8i16, DL,
8611 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8612 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
8614 // Unpack the bytes to form the i16s that will be shuffled into place.
8615 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8616 MVT::v16i8, V1, V1);
8618 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8619 for (int i = 0; i < 16; ++i)
8620 if (Mask[i] != -1) {
8621 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
8622 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
8623 if (PostDupI16Shuffle[i / 2] == -1)
8624 PostDupI16Shuffle[i / 2] = MappedMask;
8626 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
8627 "Conflicting entrties in the original shuffle!");
8630 ISD::BITCAST, DL, MVT::v16i8,
8631 DAG.getVectorShuffle(MVT::v8i16, DL,
8632 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
8633 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
8635 if (SDValue V = tryToWidenViaDuplication())
8639 // Use dedicated unpack instructions for masks that match their pattern.
8640 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
8641 0, 16, 1, 17, 2, 18, 3, 19,
8643 4, 20, 5, 21, 6, 22, 7, 23}))
8644 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, V2);
8645 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
8646 8, 24, 9, 25, 10, 26, 11, 27,
8648 12, 28, 13, 29, 14, 30, 15, 31}))
8649 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, V2);
8651 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
8652 // with PSHUFB. It is important to do this before we attempt to generate any
8653 // blends but after all of the single-input lowerings. If the single input
8654 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
8655 // want to preserve that and we can DAG combine any longer sequences into
8656 // a PSHUFB in the end. But once we start blending from multiple inputs,
8657 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
8658 // and there are *very* few patterns that would actually be faster than the
8659 // PSHUFB approach because of its ability to zero lanes.
8661 // FIXME: The only exceptions to the above are blends which are exact
8662 // interleavings with direct instructions supporting them. We currently don't
8663 // handle those well here.
8664 if (Subtarget->hasSSSE3()) {
8665 bool V1InUse = false;
8666 bool V2InUse = false;
8668 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
8669 DAG, V1InUse, V2InUse);
8671 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
8672 // do so. This avoids using them to handle blends-with-zero which is
8673 // important as a single pshufb is significantly faster for that.
8674 if (V1InUse && V2InUse) {
8675 if (Subtarget->hasSSE41())
8676 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
8677 Mask, Subtarget, DAG))
8680 // We can use an unpack to do the blending rather than an or in some
8681 // cases. Even though the or may be (very minorly) more efficient, we
8682 // preference this lowering because there are common cases where part of
8683 // the complexity of the shuffles goes away when we do the final blend as
8685 // FIXME: It might be worth trying to detect if the unpack-feeding
8686 // shuffles will both be pshufb, in which case we shouldn't bother with
8688 if (SDValue Unpack =
8689 lowerVectorShuffleAsUnpack(DL, MVT::v16i8, V1, V2, Mask, DAG))
8696 // There are special ways we can lower some single-element blends.
8697 if (NumV2Elements == 1)
8698 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
8699 Mask, Subtarget, DAG))
8702 if (SDValue BitBlend =
8703 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
8706 // Check whether a compaction lowering can be done. This handles shuffles
8707 // which take every Nth element for some even N. See the helper function for
8710 // We special case these as they can be particularly efficiently handled with
8711 // the PACKUSB instruction on x86 and they show up in common patterns of
8712 // rearranging bytes to truncate wide elements.
8713 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
8714 // NumEvenDrops is the power of two stride of the elements. Another way of
8715 // thinking about it is that we need to drop the even elements this many
8716 // times to get the original input.
8717 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8719 // First we need to zero all the dropped bytes.
8720 assert(NumEvenDrops <= 3 &&
8721 "No support for dropping even elements more than 3 times.");
8722 // We use the mask type to pick which bytes are preserved based on how many
8723 // elements are dropped.
8724 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
8725 SDValue ByteClearMask =
8726 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
8727 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
8728 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
8730 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
8732 // Now pack things back together.
8733 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
8734 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
8735 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
8736 for (int i = 1; i < NumEvenDrops; ++i) {
8737 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
8738 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
8744 // Handle multi-input cases by blending single-input shuffles.
8745 if (NumV2Elements > 0)
8746 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
8749 // The fallback path for single-input shuffles widens this into two v8i16
8750 // vectors with unpacks, shuffles those, and then pulls them back together
8754 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8755 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8756 for (int i = 0; i < 16; ++i)
8758 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
8760 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
8762 SDValue VLoHalf, VHiHalf;
8763 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
8764 // them out and avoid using UNPCK{L,H} to extract the elements of V as
8766 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
8767 [](int M) { return M >= 0 && M % 2 == 1; }) &&
8768 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
8769 [](int M) { return M >= 0 && M % 2 == 1; })) {
8770 // Use a mask to drop the high bytes.
8771 VLoHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
8772 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
8773 DAG.getConstant(0x00FF, MVT::v8i16));
8775 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
8776 VHiHalf = DAG.getUNDEF(MVT::v8i16);
8778 // Squash the masks to point directly into VLoHalf.
8779 for (int &M : LoBlendMask)
8782 for (int &M : HiBlendMask)
8786 // Otherwise just unpack the low half of V into VLoHalf and the high half into
8787 // VHiHalf so that we can blend them as i16s.
8788 VLoHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8789 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
8790 VHiHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8791 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
8794 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
8795 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
8797 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
8800 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
8802 /// This routine breaks down the specific type of 128-bit shuffle and
8803 /// dispatches to the lowering routines accordingly.
8804 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8805 MVT VT, const X86Subtarget *Subtarget,
8806 SelectionDAG &DAG) {
8807 switch (VT.SimpleTy) {
8809 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8811 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8813 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8815 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8817 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
8819 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
8822 llvm_unreachable("Unimplemented!");
8826 /// \brief Helper function to test whether a shuffle mask could be
8827 /// simplified by widening the elements being shuffled.
8829 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
8830 /// leaves it in an unspecified state.
8832 /// NOTE: This must handle normal vector shuffle masks and *target* vector
8833 /// shuffle masks. The latter have the special property of a '-2' representing
8834 /// a zero-ed lane of a vector.
8835 static bool canWidenShuffleElements(ArrayRef<int> Mask,
8836 SmallVectorImpl<int> &WidenedMask) {
8837 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
8838 // If both elements are undef, its trivial.
8839 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
8840 WidenedMask.push_back(SM_SentinelUndef);
8844 // Check for an undef mask and a mask value properly aligned to fit with
8845 // a pair of values. If we find such a case, use the non-undef mask's value.
8846 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
8847 WidenedMask.push_back(Mask[i + 1] / 2);
8850 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
8851 WidenedMask.push_back(Mask[i] / 2);
8855 // When zeroing, we need to spread the zeroing across both lanes to widen.
8856 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
8857 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
8858 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
8859 WidenedMask.push_back(SM_SentinelZero);
8865 // Finally check if the two mask values are adjacent and aligned with
8867 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
8868 WidenedMask.push_back(Mask[i] / 2);
8872 // Otherwise we can't safely widen the elements used in this shuffle.
8875 assert(WidenedMask.size() == Mask.size() / 2 &&
8876 "Incorrect size of mask after widening the elements!");
8881 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
8883 /// This routine just extracts two subvectors, shuffles them independently, and
8884 /// then concatenates them back together. This should work effectively with all
8885 /// AVX vector shuffle types.
8886 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
8887 SDValue V2, ArrayRef<int> Mask,
8888 SelectionDAG &DAG) {
8889 assert(VT.getSizeInBits() >= 256 &&
8890 "Only for 256-bit or wider vector shuffles!");
8891 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
8892 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
8894 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
8895 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
8897 int NumElements = VT.getVectorNumElements();
8898 int SplitNumElements = NumElements / 2;
8899 MVT ScalarVT = VT.getScalarType();
8900 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
8902 // Rather than splitting build-vectors, just build two narrower build
8903 // vectors. This helps shuffling with splats and zeros.
8904 auto SplitVector = [&](SDValue V) {
8905 while (V.getOpcode() == ISD::BITCAST)
8906 V = V->getOperand(0);
8908 MVT OrigVT = V.getSimpleValueType();
8909 int OrigNumElements = OrigVT.getVectorNumElements();
8910 int OrigSplitNumElements = OrigNumElements / 2;
8911 MVT OrigScalarVT = OrigVT.getScalarType();
8912 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
8916 auto *BV = dyn_cast<BuildVectorSDNode>(V);
8918 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
8919 DAG.getIntPtrConstant(0));
8920 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
8921 DAG.getIntPtrConstant(OrigSplitNumElements));
8924 SmallVector<SDValue, 16> LoOps, HiOps;
8925 for (int i = 0; i < OrigSplitNumElements; ++i) {
8926 LoOps.push_back(BV->getOperand(i));
8927 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
8929 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
8930 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
8932 return std::make_pair(DAG.getNode(ISD::BITCAST, DL, SplitVT, LoV),
8933 DAG.getNode(ISD::BITCAST, DL, SplitVT, HiV));
8936 SDValue LoV1, HiV1, LoV2, HiV2;
8937 std::tie(LoV1, HiV1) = SplitVector(V1);
8938 std::tie(LoV2, HiV2) = SplitVector(V2);
8940 // Now create two 4-way blends of these half-width vectors.
8941 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
8942 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
8943 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
8944 for (int i = 0; i < SplitNumElements; ++i) {
8945 int M = HalfMask[i];
8946 if (M >= NumElements) {
8947 if (M >= NumElements + SplitNumElements)
8951 V2BlendMask.push_back(M - NumElements);
8952 V1BlendMask.push_back(-1);
8953 BlendMask.push_back(SplitNumElements + i);
8954 } else if (M >= 0) {
8955 if (M >= SplitNumElements)
8959 V2BlendMask.push_back(-1);
8960 V1BlendMask.push_back(M);
8961 BlendMask.push_back(i);
8963 V2BlendMask.push_back(-1);
8964 V1BlendMask.push_back(-1);
8965 BlendMask.push_back(-1);
8969 // Because the lowering happens after all combining takes place, we need to
8970 // manually combine these blend masks as much as possible so that we create
8971 // a minimal number of high-level vector shuffle nodes.
8973 // First try just blending the halves of V1 or V2.
8974 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
8975 return DAG.getUNDEF(SplitVT);
8976 if (!UseLoV2 && !UseHiV2)
8977 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
8978 if (!UseLoV1 && !UseHiV1)
8979 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
8981 SDValue V1Blend, V2Blend;
8982 if (UseLoV1 && UseHiV1) {
8984 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
8986 // We only use half of V1 so map the usage down into the final blend mask.
8987 V1Blend = UseLoV1 ? LoV1 : HiV1;
8988 for (int i = 0; i < SplitNumElements; ++i)
8989 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
8990 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
8992 if (UseLoV2 && UseHiV2) {
8994 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
8996 // We only use half of V2 so map the usage down into the final blend mask.
8997 V2Blend = UseLoV2 ? LoV2 : HiV2;
8998 for (int i = 0; i < SplitNumElements; ++i)
8999 if (BlendMask[i] >= SplitNumElements)
9000 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9002 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9004 SDValue Lo = HalfBlend(LoMask);
9005 SDValue Hi = HalfBlend(HiMask);
9006 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9009 /// \brief Either split a vector in halves or decompose the shuffles and the
9012 /// This is provided as a good fallback for many lowerings of non-single-input
9013 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9014 /// between splitting the shuffle into 128-bit components and stitching those
9015 /// back together vs. extracting the single-input shuffles and blending those
9017 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9018 SDValue V2, ArrayRef<int> Mask,
9019 SelectionDAG &DAG) {
9020 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9021 "lower single-input shuffles as it "
9022 "could then recurse on itself.");
9023 int Size = Mask.size();
9025 // If this can be modeled as a broadcast of two elements followed by a blend,
9026 // prefer that lowering. This is especially important because broadcasts can
9027 // often fold with memory operands.
9028 auto DoBothBroadcast = [&] {
9029 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9032 if (V2BroadcastIdx == -1)
9033 V2BroadcastIdx = M - Size;
9034 else if (M - Size != V2BroadcastIdx)
9036 } else if (M >= 0) {
9037 if (V1BroadcastIdx == -1)
9039 else if (M != V1BroadcastIdx)
9044 if (DoBothBroadcast())
9045 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9048 // If the inputs all stem from a single 128-bit lane of each input, then we
9049 // split them rather than blending because the split will decompose to
9050 // unusually few instructions.
9051 int LaneCount = VT.getSizeInBits() / 128;
9052 int LaneSize = Size / LaneCount;
9053 SmallBitVector LaneInputs[2];
9054 LaneInputs[0].resize(LaneCount, false);
9055 LaneInputs[1].resize(LaneCount, false);
9056 for (int i = 0; i < Size; ++i)
9058 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9059 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9060 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9062 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9063 // that the decomposed single-input shuffles don't end up here.
9064 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9067 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9068 /// a permutation and blend of those lanes.
9070 /// This essentially blends the out-of-lane inputs to each lane into the lane
9071 /// from a permuted copy of the vector. This lowering strategy results in four
9072 /// instructions in the worst case for a single-input cross lane shuffle which
9073 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9074 /// of. Special cases for each particular shuffle pattern should be handled
9075 /// prior to trying this lowering.
9076 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9077 SDValue V1, SDValue V2,
9079 SelectionDAG &DAG) {
9080 // FIXME: This should probably be generalized for 512-bit vectors as well.
9081 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9082 int LaneSize = Mask.size() / 2;
9084 // If there are only inputs from one 128-bit lane, splitting will in fact be
9085 // less expensive. The flags track whether the given lane contains an element
9086 // that crosses to another lane.
9087 bool LaneCrossing[2] = {false, false};
9088 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9089 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9090 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9091 if (!LaneCrossing[0] || !LaneCrossing[1])
9092 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9094 if (isSingleInputShuffleMask(Mask)) {
9095 SmallVector<int, 32> FlippedBlendMask;
9096 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9097 FlippedBlendMask.push_back(
9098 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9100 : Mask[i] % LaneSize +
9101 (i / LaneSize) * LaneSize + Size));
9103 // Flip the vector, and blend the results which should now be in-lane. The
9104 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9105 // 5 for the high source. The value 3 selects the high half of source 2 and
9106 // the value 2 selects the low half of source 2. We only use source 2 to
9107 // allow folding it into a memory operand.
9108 unsigned PERMMask = 3 | 2 << 4;
9109 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9110 V1, DAG.getConstant(PERMMask, MVT::i8));
9111 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9114 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9115 // will be handled by the above logic and a blend of the results, much like
9116 // other patterns in AVX.
9117 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9120 /// \brief Handle lowering 2-lane 128-bit shuffles.
9121 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9122 SDValue V2, ArrayRef<int> Mask,
9123 const X86Subtarget *Subtarget,
9124 SelectionDAG &DAG) {
9125 // TODO: If minimizing size and one of the inputs is a zero vector and the
9126 // the zero vector has only one use, we could use a VPERM2X128 to save the
9127 // instruction bytes needed to explicitly generate the zero vector.
9129 // Blends are faster and handle all the non-lane-crossing cases.
9130 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9134 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
9135 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
9137 // If either input operand is a zero vector, use VPERM2X128 because its mask
9138 // allows us to replace the zero input with an implicit zero.
9139 if (!IsV1Zero && !IsV2Zero) {
9140 // Check for patterns which can be matched with a single insert of a 128-bit
9142 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
9143 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
9144 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9145 VT.getVectorNumElements() / 2);
9146 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9147 DAG.getIntPtrConstant(0));
9148 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9149 OnlyUsesV1 ? V1 : V2, DAG.getIntPtrConstant(0));
9150 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9154 // Otherwise form a 128-bit permutation. After accounting for undefs,
9155 // convert the 64-bit shuffle mask selection values into 128-bit
9156 // selection bits by dividing the indexes by 2 and shifting into positions
9157 // defined by a vperm2*128 instruction's immediate control byte.
9159 // The immediate permute control byte looks like this:
9160 // [1:0] - select 128 bits from sources for low half of destination
9162 // [3] - zero low half of destination
9163 // [5:4] - select 128 bits from sources for high half of destination
9165 // [7] - zero high half of destination
9167 int MaskLO = Mask[0];
9168 if (MaskLO == SM_SentinelUndef)
9169 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
9171 int MaskHI = Mask[2];
9172 if (MaskHI == SM_SentinelUndef)
9173 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
9175 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
9177 // If either input is a zero vector, replace it with an undef input.
9178 // Shuffle mask values < 4 are selecting elements of V1.
9179 // Shuffle mask values >= 4 are selecting elements of V2.
9180 // Adjust each half of the permute mask by clearing the half that was
9181 // selecting the zero vector and setting the zero mask bit.
9183 V1 = DAG.getUNDEF(VT);
9185 PermMask = (PermMask & 0xf0) | 0x08;
9187 PermMask = (PermMask & 0x0f) | 0x80;
9190 V2 = DAG.getUNDEF(VT);
9192 PermMask = (PermMask & 0xf0) | 0x08;
9194 PermMask = (PermMask & 0x0f) | 0x80;
9197 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9198 DAG.getConstant(PermMask, MVT::i8));
9201 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
9202 /// shuffling each lane.
9204 /// This will only succeed when the result of fixing the 128-bit lanes results
9205 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
9206 /// each 128-bit lanes. This handles many cases where we can quickly blend away
9207 /// the lane crosses early and then use simpler shuffles within each lane.
9209 /// FIXME: It might be worthwhile at some point to support this without
9210 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
9211 /// in x86 only floating point has interesting non-repeating shuffles, and even
9212 /// those are still *marginally* more expensive.
9213 static SDValue lowerVectorShuffleByMerging128BitLanes(
9214 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
9215 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
9216 assert(!isSingleInputShuffleMask(Mask) &&
9217 "This is only useful with multiple inputs.");
9219 int Size = Mask.size();
9220 int LaneSize = 128 / VT.getScalarSizeInBits();
9221 int NumLanes = Size / LaneSize;
9222 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
9224 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
9225 // check whether the in-128-bit lane shuffles share a repeating pattern.
9226 SmallVector<int, 4> Lanes;
9227 Lanes.resize(NumLanes, -1);
9228 SmallVector<int, 4> InLaneMask;
9229 InLaneMask.resize(LaneSize, -1);
9230 for (int i = 0; i < Size; ++i) {
9234 int j = i / LaneSize;
9237 // First entry we've seen for this lane.
9238 Lanes[j] = Mask[i] / LaneSize;
9239 } else if (Lanes[j] != Mask[i] / LaneSize) {
9240 // This doesn't match the lane selected previously!
9244 // Check that within each lane we have a consistent shuffle mask.
9245 int k = i % LaneSize;
9246 if (InLaneMask[k] < 0) {
9247 InLaneMask[k] = Mask[i] % LaneSize;
9248 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
9249 // This doesn't fit a repeating in-lane mask.
9254 // First shuffle the lanes into place.
9255 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
9256 VT.getSizeInBits() / 64);
9257 SmallVector<int, 8> LaneMask;
9258 LaneMask.resize(NumLanes * 2, -1);
9259 for (int i = 0; i < NumLanes; ++i)
9260 if (Lanes[i] >= 0) {
9261 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
9262 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
9265 V1 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V1);
9266 V2 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V2);
9267 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
9269 // Cast it back to the type we actually want.
9270 LaneShuffle = DAG.getNode(ISD::BITCAST, DL, VT, LaneShuffle);
9272 // Now do a simple shuffle that isn't lane crossing.
9273 SmallVector<int, 8> NewMask;
9274 NewMask.resize(Size, -1);
9275 for (int i = 0; i < Size; ++i)
9277 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
9278 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
9279 "Must not introduce lane crosses at this point!");
9281 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
9284 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
9287 /// This returns true if the elements from a particular input are already in the
9288 /// slot required by the given mask and require no permutation.
9289 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
9290 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
9291 int Size = Mask.size();
9292 for (int i = 0; i < Size; ++i)
9293 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
9299 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9301 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9302 /// isn't available.
9303 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9304 const X86Subtarget *Subtarget,
9305 SelectionDAG &DAG) {
9307 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9308 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9309 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9310 ArrayRef<int> Mask = SVOp->getMask();
9311 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9313 SmallVector<int, 4> WidenedMask;
9314 if (canWidenShuffleElements(Mask, WidenedMask))
9315 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
9318 if (isSingleInputShuffleMask(Mask)) {
9319 // Check for being able to broadcast a single element.
9320 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
9321 Mask, Subtarget, DAG))
9324 // Use low duplicate instructions for masks that match their pattern.
9325 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
9326 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
9328 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9329 // Non-half-crossing single input shuffles can be lowerid with an
9330 // interleaved permutation.
9331 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9332 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9333 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9334 DAG.getConstant(VPERMILPMask, MVT::i8));
9337 // With AVX2 we have direct support for this permutation.
9338 if (Subtarget->hasAVX2())
9339 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9340 getV4X86ShuffleImm8ForMask(Mask, DAG));
9342 // Otherwise, fall back.
9343 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9347 // X86 has dedicated unpack instructions that can handle specific blend
9348 // operations: UNPCKH and UNPCKL.
9349 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9350 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9351 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9352 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9353 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9354 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
9355 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9356 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
9358 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9362 // Check if the blend happens to exactly fit that of SHUFPD.
9363 if ((Mask[0] == -1 || Mask[0] < 2) &&
9364 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
9365 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
9366 (Mask[3] == -1 || Mask[3] >= 6)) {
9367 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9368 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9369 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9370 DAG.getConstant(SHUFPDMask, MVT::i8));
9372 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
9373 (Mask[1] == -1 || Mask[1] < 2) &&
9374 (Mask[2] == -1 || Mask[2] >= 6) &&
9375 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
9376 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9377 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9378 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9379 DAG.getConstant(SHUFPDMask, MVT::i8));
9382 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9383 // shuffle. However, if we have AVX2 and either inputs are already in place,
9384 // we will be able to shuffle even across lanes the other input in a single
9385 // instruction so skip this pattern.
9386 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9387 isShuffleMaskInputInPlace(1, Mask))))
9388 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9389 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
9392 // If we have AVX2 then we always want to lower with a blend because an v4 we
9393 // can fully permute the elements.
9394 if (Subtarget->hasAVX2())
9395 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9398 // Otherwise fall back on generic lowering.
9399 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
9402 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9404 /// This routine is only called when we have AVX2 and thus a reasonable
9405 /// instruction set for v4i64 shuffling..
9406 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9407 const X86Subtarget *Subtarget,
9408 SelectionDAG &DAG) {
9410 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9411 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9412 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9413 ArrayRef<int> Mask = SVOp->getMask();
9414 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9415 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9417 SmallVector<int, 4> WidenedMask;
9418 if (canWidenShuffleElements(Mask, WidenedMask))
9419 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
9422 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9426 // Check for being able to broadcast a single element.
9427 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
9428 Mask, Subtarget, DAG))
9431 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9432 // use lower latency instructions that will operate on both 128-bit lanes.
9433 SmallVector<int, 2> RepeatedMask;
9434 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9435 if (isSingleInputShuffleMask(Mask)) {
9436 int PSHUFDMask[] = {-1, -1, -1, -1};
9437 for (int i = 0; i < 2; ++i)
9438 if (RepeatedMask[i] >= 0) {
9439 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9440 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9443 ISD::BITCAST, DL, MVT::v4i64,
9444 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9445 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
9446 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
9450 // AVX2 provides a direct instruction for permuting a single input across
9452 if (isSingleInputShuffleMask(Mask))
9453 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9454 getV4X86ShuffleImm8ForMask(Mask, DAG));
9456 // Try to use shift instructions.
9458 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
9461 // Use dedicated unpack instructions for masks that match their pattern.
9462 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9463 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9464 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9465 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9466 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9467 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V2, V1);
9468 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9469 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V2, V1);
9471 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9472 // shuffle. However, if we have AVX2 and either inputs are already in place,
9473 // we will be able to shuffle even across lanes the other input in a single
9474 // instruction so skip this pattern.
9475 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9476 isShuffleMaskInputInPlace(1, Mask))))
9477 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9478 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
9481 // Otherwise fall back on generic blend lowering.
9482 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9486 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9488 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9489 /// isn't available.
9490 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9491 const X86Subtarget *Subtarget,
9492 SelectionDAG &DAG) {
9494 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9495 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9496 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9497 ArrayRef<int> Mask = SVOp->getMask();
9498 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9500 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9504 // Check for being able to broadcast a single element.
9505 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
9506 Mask, Subtarget, DAG))
9509 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9510 // options to efficiently lower the shuffle.
9511 SmallVector<int, 4> RepeatedMask;
9512 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9513 assert(RepeatedMask.size() == 4 &&
9514 "Repeated masks must be half the mask width!");
9516 // Use even/odd duplicate instructions for masks that match their pattern.
9517 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
9518 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
9519 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
9520 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
9522 if (isSingleInputShuffleMask(Mask))
9523 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9524 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9526 // Use dedicated unpack instructions for masks that match their pattern.
9527 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9528 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9529 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9530 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9531 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9532 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V2, V1);
9533 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9534 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V2, V1);
9536 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9537 // have already handled any direct blends. We also need to squash the
9538 // repeated mask into a simulated v4f32 mask.
9539 for (int i = 0; i < 4; ++i)
9540 if (RepeatedMask[i] >= 8)
9541 RepeatedMask[i] -= 4;
9542 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
9545 // If we have a single input shuffle with different shuffle patterns in the
9546 // two 128-bit lanes use the variable mask to VPERMILPS.
9547 if (isSingleInputShuffleMask(Mask)) {
9548 SDValue VPermMask[8];
9549 for (int i = 0; i < 8; ++i)
9550 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9551 : DAG.getConstant(Mask[i], MVT::i32);
9552 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9554 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9555 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9557 if (Subtarget->hasAVX2())
9558 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
9559 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
9560 DAG.getNode(ISD::BUILD_VECTOR, DL,
9561 MVT::v8i32, VPermMask)),
9564 // Otherwise, fall back.
9565 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
9569 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9571 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9572 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
9575 // If we have AVX2 then we always want to lower with a blend because at v8 we
9576 // can fully permute the elements.
9577 if (Subtarget->hasAVX2())
9578 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9581 // Otherwise fall back on generic lowering.
9582 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
9585 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9587 /// This routine is only called when we have AVX2 and thus a reasonable
9588 /// instruction set for v8i32 shuffling..
9589 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9590 const X86Subtarget *Subtarget,
9591 SelectionDAG &DAG) {
9593 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9594 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9595 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9596 ArrayRef<int> Mask = SVOp->getMask();
9597 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9598 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9600 // Whenever we can lower this as a zext, that instruction is strictly faster
9601 // than any alternative. It also allows us to fold memory operands into the
9602 // shuffle in many cases.
9603 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
9604 Mask, Subtarget, DAG))
9607 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
9611 // Check for being able to broadcast a single element.
9612 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
9613 Mask, Subtarget, DAG))
9616 // If the shuffle mask is repeated in each 128-bit lane we can use more
9617 // efficient instructions that mirror the shuffles across the two 128-bit
9619 SmallVector<int, 4> RepeatedMask;
9620 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
9621 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
9622 if (isSingleInputShuffleMask(Mask))
9623 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
9624 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9626 // Use dedicated unpack instructions for masks that match their pattern.
9627 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9628 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
9629 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9630 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
9631 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9632 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V2, V1);
9633 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9634 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V2, V1);
9637 // Try to use shift instructions.
9639 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
9642 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9643 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
9646 // If the shuffle patterns aren't repeated but it is a single input, directly
9647 // generate a cross-lane VPERMD instruction.
9648 if (isSingleInputShuffleMask(Mask)) {
9649 SDValue VPermMask[8];
9650 for (int i = 0; i < 8; ++i)
9651 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9652 : DAG.getConstant(Mask[i], MVT::i32);
9654 X86ISD::VPERMV, DL, MVT::v8i32,
9655 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
9658 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9660 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9661 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
9664 // Otherwise fall back on generic blend lowering.
9665 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
9669 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
9671 /// This routine is only called when we have AVX2 and thus a reasonable
9672 /// instruction set for v16i16 shuffling..
9673 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9674 const X86Subtarget *Subtarget,
9675 SelectionDAG &DAG) {
9677 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9678 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9679 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9680 ArrayRef<int> Mask = SVOp->getMask();
9681 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9682 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
9684 // Whenever we can lower this as a zext, that instruction is strictly faster
9685 // than any alternative. It also allows us to fold memory operands into the
9686 // shuffle in many cases.
9687 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
9688 Mask, Subtarget, DAG))
9691 // Check for being able to broadcast a single element.
9692 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
9693 Mask, Subtarget, DAG))
9696 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
9700 // Use dedicated unpack instructions for masks that match their pattern.
9701 if (isShuffleEquivalent(V1, V2, Mask,
9702 {// First 128-bit lane:
9703 0, 16, 1, 17, 2, 18, 3, 19,
9704 // Second 128-bit lane:
9705 8, 24, 9, 25, 10, 26, 11, 27}))
9706 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
9707 if (isShuffleEquivalent(V1, V2, Mask,
9708 {// First 128-bit lane:
9709 4, 20, 5, 21, 6, 22, 7, 23,
9710 // Second 128-bit lane:
9711 12, 28, 13, 29, 14, 30, 15, 31}))
9712 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
9714 // Try to use shift instructions.
9716 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
9719 // Try to use byte rotation instructions.
9720 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9721 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
9724 if (isSingleInputShuffleMask(Mask)) {
9725 // There are no generalized cross-lane shuffle operations available on i16
9727 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
9728 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
9731 SmallVector<int, 8> RepeatedMask;
9732 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
9733 // As this is a single-input shuffle, the repeated mask should be
9734 // a strictly valid v8i16 mask that we can pass through to the v8i16
9735 // lowering to handle even the v16 case.
9736 return lowerV8I16GeneralSingleInputVectorShuffle(
9737 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
9740 SDValue PSHUFBMask[32];
9741 for (int i = 0; i < 16; ++i) {
9742 if (Mask[i] == -1) {
9743 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
9747 int M = i < 8 ? Mask[i] : Mask[i] - 8;
9748 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
9749 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
9750 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
9753 ISD::BITCAST, DL, MVT::v16i16,
9755 X86ISD::PSHUFB, DL, MVT::v32i8,
9756 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
9757 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
9760 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9762 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9763 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
9766 // Otherwise fall back on generic lowering.
9767 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
9770 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
9772 /// This routine is only called when we have AVX2 and thus a reasonable
9773 /// instruction set for v32i8 shuffling..
9774 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9775 const X86Subtarget *Subtarget,
9776 SelectionDAG &DAG) {
9778 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9779 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9780 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9781 ArrayRef<int> Mask = SVOp->getMask();
9782 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9783 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
9785 // Whenever we can lower this as a zext, that instruction is strictly faster
9786 // than any alternative. It also allows us to fold memory operands into the
9787 // shuffle in many cases.
9788 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
9789 Mask, Subtarget, DAG))
9792 // Check for being able to broadcast a single element.
9793 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
9794 Mask, Subtarget, DAG))
9797 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
9801 // Use dedicated unpack instructions for masks that match their pattern.
9802 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
9804 if (isShuffleEquivalent(
9806 {// First 128-bit lane:
9807 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
9808 // Second 128-bit lane:
9809 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55}))
9810 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
9811 if (isShuffleEquivalent(
9813 {// First 128-bit lane:
9814 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
9815 // Second 128-bit lane:
9816 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63}))
9817 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
9819 // Try to use shift instructions.
9821 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
9824 // Try to use byte rotation instructions.
9825 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9826 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
9829 if (isSingleInputShuffleMask(Mask)) {
9830 // There are no generalized cross-lane shuffle operations available on i8
9832 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
9833 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
9836 SDValue PSHUFBMask[32];
9837 for (int i = 0; i < 32; ++i)
9840 ? DAG.getUNDEF(MVT::i8)
9841 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
9844 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
9845 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
9848 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9850 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9851 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
9854 // Otherwise fall back on generic lowering.
9855 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
9858 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
9860 /// This routine either breaks down the specific type of a 256-bit x86 vector
9861 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
9862 /// together based on the available instructions.
9863 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9864 MVT VT, const X86Subtarget *Subtarget,
9865 SelectionDAG &DAG) {
9867 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9868 ArrayRef<int> Mask = SVOp->getMask();
9870 // If we have a single input to the zero element, insert that into V1 if we
9871 // can do so cheaply.
9872 int NumElts = VT.getVectorNumElements();
9873 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
9874 return M >= NumElts;
9877 if (NumV2Elements == 1 && Mask[0] >= NumElts)
9878 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
9879 DL, VT, V1, V2, Mask, Subtarget, DAG))
9882 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
9883 // check for those subtargets here and avoid much of the subtarget querying in
9884 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
9885 // ability to manipulate a 256-bit vector with integer types. Since we'll use
9886 // floating point types there eventually, just immediately cast everything to
9887 // a float and operate entirely in that domain.
9888 if (VT.isInteger() && !Subtarget->hasAVX2()) {
9889 int ElementBits = VT.getScalarSizeInBits();
9890 if (ElementBits < 32)
9891 // No floating point type available, decompose into 128-bit vectors.
9892 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9894 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
9895 VT.getVectorNumElements());
9896 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
9897 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
9898 return DAG.getNode(ISD::BITCAST, DL, VT,
9899 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
9902 switch (VT.SimpleTy) {
9904 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9906 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9908 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9910 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9912 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9914 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9917 llvm_unreachable("Not a valid 256-bit x86 vector type!");
9921 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
9922 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9923 const X86Subtarget *Subtarget,
9924 SelectionDAG &DAG) {
9926 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
9927 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
9928 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9929 ArrayRef<int> Mask = SVOp->getMask();
9930 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9932 // X86 has dedicated unpack instructions that can handle specific blend
9933 // operations: UNPCKH and UNPCKL.
9934 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
9935 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f64, V1, V2);
9936 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
9937 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f64, V1, V2);
9939 // FIXME: Implement direct support for this type!
9940 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
9943 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
9944 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9945 const X86Subtarget *Subtarget,
9946 SelectionDAG &DAG) {
9948 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
9949 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
9950 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9951 ArrayRef<int> Mask = SVOp->getMask();
9952 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9954 // Use dedicated unpack instructions for masks that match their pattern.
9955 if (isShuffleEquivalent(V1, V2, Mask,
9956 {// First 128-bit lane.
9957 0, 16, 1, 17, 4, 20, 5, 21,
9958 // Second 128-bit lane.
9959 8, 24, 9, 25, 12, 28, 13, 29}))
9960 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16f32, V1, V2);
9961 if (isShuffleEquivalent(V1, V2, Mask,
9962 {// First 128-bit lane.
9963 2, 18, 3, 19, 6, 22, 7, 23,
9964 // Second 128-bit lane.
9965 10, 26, 11, 27, 14, 30, 15, 31}))
9966 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16f32, V1, V2);
9968 // FIXME: Implement direct support for this type!
9969 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
9972 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
9973 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9974 const X86Subtarget *Subtarget,
9975 SelectionDAG &DAG) {
9977 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
9978 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
9979 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9980 ArrayRef<int> Mask = SVOp->getMask();
9981 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9983 // X86 has dedicated unpack instructions that can handle specific blend
9984 // operations: UNPCKH and UNPCKL.
9985 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
9986 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i64, V1, V2);
9987 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
9988 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i64, V1, V2);
9990 // FIXME: Implement direct support for this type!
9991 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
9994 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
9995 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9996 const X86Subtarget *Subtarget,
9997 SelectionDAG &DAG) {
9999 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10000 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10001 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10002 ArrayRef<int> Mask = SVOp->getMask();
10003 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10005 // Use dedicated unpack instructions for masks that match their pattern.
10006 if (isShuffleEquivalent(V1, V2, Mask,
10007 {// First 128-bit lane.
10008 0, 16, 1, 17, 4, 20, 5, 21,
10009 // Second 128-bit lane.
10010 8, 24, 9, 25, 12, 28, 13, 29}))
10011 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i32, V1, V2);
10012 if (isShuffleEquivalent(V1, V2, Mask,
10013 {// First 128-bit lane.
10014 2, 18, 3, 19, 6, 22, 7, 23,
10015 // Second 128-bit lane.
10016 10, 26, 11, 27, 14, 30, 15, 31}))
10017 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i32, V1, V2);
10019 // FIXME: Implement direct support for this type!
10020 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10023 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10024 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10025 const X86Subtarget *Subtarget,
10026 SelectionDAG &DAG) {
10028 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10029 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10030 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10031 ArrayRef<int> Mask = SVOp->getMask();
10032 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10033 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10035 // FIXME: Implement direct support for this type!
10036 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10039 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10040 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10041 const X86Subtarget *Subtarget,
10042 SelectionDAG &DAG) {
10044 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10045 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10046 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10047 ArrayRef<int> Mask = SVOp->getMask();
10048 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10049 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10051 // FIXME: Implement direct support for this type!
10052 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10055 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10057 /// This routine either breaks down the specific type of a 512-bit x86 vector
10058 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10059 /// together based on the available instructions.
10060 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10061 MVT VT, const X86Subtarget *Subtarget,
10062 SelectionDAG &DAG) {
10064 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10065 ArrayRef<int> Mask = SVOp->getMask();
10066 assert(Subtarget->hasAVX512() &&
10067 "Cannot lower 512-bit vectors w/ basic ISA!");
10069 // Check for being able to broadcast a single element.
10070 if (SDValue Broadcast =
10071 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10074 // Dispatch to each element type for lowering. If we don't have supprot for
10075 // specific element type shuffles at 512 bits, immediately split them and
10076 // lower them. Each lowering routine of a given type is allowed to assume that
10077 // the requisite ISA extensions for that element type are available.
10078 switch (VT.SimpleTy) {
10080 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10082 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10084 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10086 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10088 if (Subtarget->hasBWI())
10089 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10092 if (Subtarget->hasBWI())
10093 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10097 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10100 // Otherwise fall back on splitting.
10101 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10104 /// \brief Top-level lowering for x86 vector shuffles.
10106 /// This handles decomposition, canonicalization, and lowering of all x86
10107 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10108 /// above in helper routines. The canonicalization attempts to widen shuffles
10109 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10110 /// s.t. only one of the two inputs needs to be tested, etc.
10111 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10112 SelectionDAG &DAG) {
10113 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10114 ArrayRef<int> Mask = SVOp->getMask();
10115 SDValue V1 = Op.getOperand(0);
10116 SDValue V2 = Op.getOperand(1);
10117 MVT VT = Op.getSimpleValueType();
10118 int NumElements = VT.getVectorNumElements();
10121 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10123 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10124 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10125 if (V1IsUndef && V2IsUndef)
10126 return DAG.getUNDEF(VT);
10128 // When we create a shuffle node we put the UNDEF node to second operand,
10129 // but in some cases the first operand may be transformed to UNDEF.
10130 // In this case we should just commute the node.
10132 return DAG.getCommutedVectorShuffle(*SVOp);
10134 // Check for non-undef masks pointing at an undef vector and make the masks
10135 // undef as well. This makes it easier to match the shuffle based solely on
10139 if (M >= NumElements) {
10140 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10141 for (int &M : NewMask)
10142 if (M >= NumElements)
10144 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10147 // We actually see shuffles that are entirely re-arrangements of a set of
10148 // zero inputs. This mostly happens while decomposing complex shuffles into
10149 // simple ones. Directly lower these as a buildvector of zeros.
10150 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
10151 if (Zeroable.all())
10152 return getZeroVector(VT, Subtarget, DAG, dl);
10154 // Try to collapse shuffles into using a vector type with fewer elements but
10155 // wider element types. We cap this to not form integers or floating point
10156 // elements wider than 64 bits, but it might be interesting to form i128
10157 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10158 SmallVector<int, 16> WidenedMask;
10159 if (VT.getScalarSizeInBits() < 64 &&
10160 canWidenShuffleElements(Mask, WidenedMask)) {
10161 MVT NewEltVT = VT.isFloatingPoint()
10162 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10163 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10164 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10165 // Make sure that the new vector type is legal. For example, v2f64 isn't
10167 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10168 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10169 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10170 return DAG.getNode(ISD::BITCAST, dl, VT,
10171 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10175 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10176 for (int M : SVOp->getMask())
10178 ++NumUndefElements;
10179 else if (M < NumElements)
10184 // Commute the shuffle as needed such that more elements come from V1 than
10185 // V2. This allows us to match the shuffle pattern strictly on how many
10186 // elements come from V1 without handling the symmetric cases.
10187 if (NumV2Elements > NumV1Elements)
10188 return DAG.getCommutedVectorShuffle(*SVOp);
10190 // When the number of V1 and V2 elements are the same, try to minimize the
10191 // number of uses of V2 in the low half of the vector. When that is tied,
10192 // ensure that the sum of indices for V1 is equal to or lower than the sum
10193 // indices for V2. When those are equal, try to ensure that the number of odd
10194 // indices for V1 is lower than the number of odd indices for V2.
10195 if (NumV1Elements == NumV2Elements) {
10196 int LowV1Elements = 0, LowV2Elements = 0;
10197 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10198 if (M >= NumElements)
10202 if (LowV2Elements > LowV1Elements) {
10203 return DAG.getCommutedVectorShuffle(*SVOp);
10204 } else if (LowV2Elements == LowV1Elements) {
10205 int SumV1Indices = 0, SumV2Indices = 0;
10206 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10207 if (SVOp->getMask()[i] >= NumElements)
10209 else if (SVOp->getMask()[i] >= 0)
10211 if (SumV2Indices < SumV1Indices) {
10212 return DAG.getCommutedVectorShuffle(*SVOp);
10213 } else if (SumV2Indices == SumV1Indices) {
10214 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10215 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10216 if (SVOp->getMask()[i] >= NumElements)
10217 NumV2OddIndices += i % 2;
10218 else if (SVOp->getMask()[i] >= 0)
10219 NumV1OddIndices += i % 2;
10220 if (NumV2OddIndices < NumV1OddIndices)
10221 return DAG.getCommutedVectorShuffle(*SVOp);
10226 // For each vector width, delegate to a specialized lowering routine.
10227 if (VT.getSizeInBits() == 128)
10228 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10230 if (VT.getSizeInBits() == 256)
10231 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10233 // Force AVX-512 vectors to be scalarized for now.
10234 // FIXME: Implement AVX-512 support!
10235 if (VT.getSizeInBits() == 512)
10236 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10238 llvm_unreachable("Unimplemented!");
10241 // This function assumes its argument is a BUILD_VECTOR of constants or
10242 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
10244 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
10245 unsigned &MaskValue) {
10247 unsigned NumElems = BuildVector->getNumOperands();
10248 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10249 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10250 unsigned NumElemsInLane = NumElems / NumLanes;
10252 // Blend for v16i16 should be symetric for the both lanes.
10253 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10254 SDValue EltCond = BuildVector->getOperand(i);
10255 SDValue SndLaneEltCond =
10256 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
10258 int Lane1Cond = -1, Lane2Cond = -1;
10259 if (isa<ConstantSDNode>(EltCond))
10260 Lane1Cond = !isZero(EltCond);
10261 if (isa<ConstantSDNode>(SndLaneEltCond))
10262 Lane2Cond = !isZero(SndLaneEltCond);
10264 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
10265 // Lane1Cond != 0, means we want the first argument.
10266 // Lane1Cond == 0, means we want the second argument.
10267 // The encoding of this argument is 0 for the first argument, 1
10268 // for the second. Therefore, invert the condition.
10269 MaskValue |= !Lane1Cond << i;
10270 else if (Lane1Cond < 0)
10271 MaskValue |= !Lane2Cond << i;
10278 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
10279 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
10280 const X86Subtarget *Subtarget,
10281 SelectionDAG &DAG) {
10282 SDValue Cond = Op.getOperand(0);
10283 SDValue LHS = Op.getOperand(1);
10284 SDValue RHS = Op.getOperand(2);
10286 MVT VT = Op.getSimpleValueType();
10288 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
10290 auto *CondBV = cast<BuildVectorSDNode>(Cond);
10292 // Only non-legal VSELECTs reach this lowering, convert those into generic
10293 // shuffles and re-use the shuffle lowering path for blends.
10294 SmallVector<int, 32> Mask;
10295 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
10296 SDValue CondElt = CondBV->getOperand(i);
10298 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
10300 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
10303 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
10304 // A vselect where all conditions and data are constants can be optimized into
10305 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
10306 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
10307 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
10308 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
10311 // Try to lower this to a blend-style vector shuffle. This can handle all
10312 // constant condition cases.
10313 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
10316 // Variable blends are only legal from SSE4.1 onward.
10317 if (!Subtarget->hasSSE41())
10320 // Only some types will be legal on some subtargets. If we can emit a legal
10321 // VSELECT-matching blend, return Op, and but if we need to expand, return
10323 switch (Op.getSimpleValueType().SimpleTy) {
10325 // Most of the vector types have blends past SSE4.1.
10329 // The byte blends for AVX vectors were introduced only in AVX2.
10330 if (Subtarget->hasAVX2())
10337 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
10338 if (Subtarget->hasBWI() && Subtarget->hasVLX())
10341 // FIXME: We should custom lower this by fixing the condition and using i8
10347 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
10348 MVT VT = Op.getSimpleValueType();
10351 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
10354 if (VT.getSizeInBits() == 8) {
10355 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
10356 Op.getOperand(0), Op.getOperand(1));
10357 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10358 DAG.getValueType(VT));
10359 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10362 if (VT.getSizeInBits() == 16) {
10363 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10364 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
10366 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10367 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10368 DAG.getNode(ISD::BITCAST, dl,
10371 Op.getOperand(1)));
10372 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
10373 Op.getOperand(0), Op.getOperand(1));
10374 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10375 DAG.getValueType(VT));
10376 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10379 if (VT == MVT::f32) {
10380 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
10381 // the result back to FR32 register. It's only worth matching if the
10382 // result has a single use which is a store or a bitcast to i32. And in
10383 // the case of a store, it's not worth it if the index is a constant 0,
10384 // because a MOVSSmr can be used instead, which is smaller and faster.
10385 if (!Op.hasOneUse())
10387 SDNode *User = *Op.getNode()->use_begin();
10388 if ((User->getOpcode() != ISD::STORE ||
10389 (isa<ConstantSDNode>(Op.getOperand(1)) &&
10390 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
10391 (User->getOpcode() != ISD::BITCAST ||
10392 User->getValueType(0) != MVT::i32))
10394 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10395 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
10398 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
10401 if (VT == MVT::i32 || VT == MVT::i64) {
10402 // ExtractPS/pextrq works with constant index.
10403 if (isa<ConstantSDNode>(Op.getOperand(1)))
10409 /// Extract one bit from mask vector, like v16i1 or v8i1.
10410 /// AVX-512 feature.
10412 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
10413 SDValue Vec = Op.getOperand(0);
10415 MVT VecVT = Vec.getSimpleValueType();
10416 SDValue Idx = Op.getOperand(1);
10417 MVT EltVT = Op.getSimpleValueType();
10419 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
10420 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
10421 "Unexpected vector type in ExtractBitFromMaskVector");
10423 // variable index can't be handled in mask registers,
10424 // extend vector to VR512
10425 if (!isa<ConstantSDNode>(Idx)) {
10426 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10427 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
10428 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
10429 ExtVT.getVectorElementType(), Ext, Idx);
10430 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
10433 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10434 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10435 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
10436 rc = getRegClassFor(MVT::v16i1);
10437 unsigned MaxSift = rc->getSize()*8 - 1;
10438 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
10439 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
10440 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
10441 DAG.getConstant(MaxSift, MVT::i8));
10442 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
10443 DAG.getIntPtrConstant(0));
10447 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
10448 SelectionDAG &DAG) const {
10450 SDValue Vec = Op.getOperand(0);
10451 MVT VecVT = Vec.getSimpleValueType();
10452 SDValue Idx = Op.getOperand(1);
10454 if (Op.getSimpleValueType() == MVT::i1)
10455 return ExtractBitFromMaskVector(Op, DAG);
10457 if (!isa<ConstantSDNode>(Idx)) {
10458 if (VecVT.is512BitVector() ||
10459 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
10460 VecVT.getVectorElementType().getSizeInBits() == 32)) {
10463 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
10464 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
10465 MaskEltVT.getSizeInBits());
10467 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
10468 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
10469 getZeroVector(MaskVT, Subtarget, DAG, dl),
10470 Idx, DAG.getConstant(0, getPointerTy()));
10471 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
10472 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
10473 Perm, DAG.getConstant(0, getPointerTy()));
10478 // If this is a 256-bit vector result, first extract the 128-bit vector and
10479 // then extract the element from the 128-bit vector.
10480 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
10482 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10483 // Get the 128-bit vector.
10484 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
10485 MVT EltVT = VecVT.getVectorElementType();
10487 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
10489 //if (IdxVal >= NumElems/2)
10490 // IdxVal -= NumElems/2;
10491 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
10492 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
10493 DAG.getConstant(IdxVal, MVT::i32));
10496 assert(VecVT.is128BitVector() && "Unexpected vector length");
10498 if (Subtarget->hasSSE41()) {
10499 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
10504 MVT VT = Op.getSimpleValueType();
10505 // TODO: handle v16i8.
10506 if (VT.getSizeInBits() == 16) {
10507 SDValue Vec = Op.getOperand(0);
10508 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10510 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10511 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10512 DAG.getNode(ISD::BITCAST, dl,
10514 Op.getOperand(1)));
10515 // Transform it so it match pextrw which produces a 32-bit result.
10516 MVT EltVT = MVT::i32;
10517 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
10518 Op.getOperand(0), Op.getOperand(1));
10519 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
10520 DAG.getValueType(VT));
10521 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10524 if (VT.getSizeInBits() == 32) {
10525 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10529 // SHUFPS the element to the lowest double word, then movss.
10530 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
10531 MVT VVT = Op.getOperand(0).getSimpleValueType();
10532 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10533 DAG.getUNDEF(VVT), Mask);
10534 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10535 DAG.getIntPtrConstant(0));
10538 if (VT.getSizeInBits() == 64) {
10539 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
10540 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
10541 // to match extract_elt for f64.
10542 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10546 // UNPCKHPD the element to the lowest double word, then movsd.
10547 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
10548 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
10549 int Mask[2] = { 1, -1 };
10550 MVT VVT = Op.getOperand(0).getSimpleValueType();
10551 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10552 DAG.getUNDEF(VVT), Mask);
10553 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10554 DAG.getIntPtrConstant(0));
10560 /// Insert one bit to mask vector, like v16i1 or v8i1.
10561 /// AVX-512 feature.
10563 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
10565 SDValue Vec = Op.getOperand(0);
10566 SDValue Elt = Op.getOperand(1);
10567 SDValue Idx = Op.getOperand(2);
10568 MVT VecVT = Vec.getSimpleValueType();
10570 if (!isa<ConstantSDNode>(Idx)) {
10571 // Non constant index. Extend source and destination,
10572 // insert element and then truncate the result.
10573 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10574 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
10575 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
10576 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
10577 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
10578 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
10581 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10582 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
10583 if (Vec.getOpcode() == ISD::UNDEF)
10584 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10585 DAG.getConstant(IdxVal, MVT::i8));
10586 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10587 unsigned MaxSift = rc->getSize()*8 - 1;
10588 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10589 DAG.getConstant(MaxSift, MVT::i8));
10590 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
10591 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
10592 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
10595 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
10596 SelectionDAG &DAG) const {
10597 MVT VT = Op.getSimpleValueType();
10598 MVT EltVT = VT.getVectorElementType();
10600 if (EltVT == MVT::i1)
10601 return InsertBitToMaskVector(Op, DAG);
10604 SDValue N0 = Op.getOperand(0);
10605 SDValue N1 = Op.getOperand(1);
10606 SDValue N2 = Op.getOperand(2);
10607 if (!isa<ConstantSDNode>(N2))
10609 auto *N2C = cast<ConstantSDNode>(N2);
10610 unsigned IdxVal = N2C->getZExtValue();
10612 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
10613 // into that, and then insert the subvector back into the result.
10614 if (VT.is256BitVector() || VT.is512BitVector()) {
10615 // With a 256-bit vector, we can insert into the zero element efficiently
10616 // using a blend if we have AVX or AVX2 and the right data type.
10617 if (VT.is256BitVector() && IdxVal == 0) {
10618 // TODO: It is worthwhile to cast integer to floating point and back
10619 // and incur a domain crossing penalty if that's what we'll end up
10620 // doing anyway after extracting to a 128-bit vector.
10621 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
10622 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
10623 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
10624 N2 = DAG.getIntPtrConstant(1);
10625 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
10629 // Get the desired 128-bit vector chunk.
10630 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
10632 // Insert the element into the desired chunk.
10633 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
10634 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
10636 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
10637 DAG.getConstant(IdxIn128, MVT::i32));
10639 // Insert the changed part back into the bigger vector
10640 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
10642 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
10644 if (Subtarget->hasSSE41()) {
10645 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
10647 if (VT == MVT::v8i16) {
10648 Opc = X86ISD::PINSRW;
10650 assert(VT == MVT::v16i8);
10651 Opc = X86ISD::PINSRB;
10654 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
10656 if (N1.getValueType() != MVT::i32)
10657 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10658 if (N2.getValueType() != MVT::i32)
10659 N2 = DAG.getIntPtrConstant(IdxVal);
10660 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
10663 if (EltVT == MVT::f32) {
10664 // Bits [7:6] of the constant are the source select. This will always be
10665 // zero here. The DAG Combiner may combine an extract_elt index into
10666 // these bits. For example (insert (extract, 3), 2) could be matched by
10667 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
10668 // Bits [5:4] of the constant are the destination select. This is the
10669 // value of the incoming immediate.
10670 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
10671 // combine either bitwise AND or insert of float 0.0 to set these bits.
10673 const Function *F = DAG.getMachineFunction().getFunction();
10674 bool MinSize = F->hasFnAttribute(Attribute::MinSize);
10675 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
10676 // If this is an insertion of 32-bits into the low 32-bits of
10677 // a vector, we prefer to generate a blend with immediate rather
10678 // than an insertps. Blends are simpler operations in hardware and so
10679 // will always have equal or better performance than insertps.
10680 // But if optimizing for size and there's a load folding opportunity,
10681 // generate insertps because blendps does not have a 32-bit memory
10683 N2 = DAG.getIntPtrConstant(1);
10684 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10685 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
10687 N2 = DAG.getIntPtrConstant(IdxVal << 4);
10688 // Create this as a scalar to vector..
10689 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10690 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
10693 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
10694 // PINSR* works with constant index.
10699 if (EltVT == MVT::i8)
10702 if (EltVT.getSizeInBits() == 16) {
10703 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
10704 // as its second argument.
10705 if (N1.getValueType() != MVT::i32)
10706 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10707 if (N2.getValueType() != MVT::i32)
10708 N2 = DAG.getIntPtrConstant(IdxVal);
10709 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
10714 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
10716 MVT OpVT = Op.getSimpleValueType();
10718 // If this is a 256-bit vector result, first insert into a 128-bit
10719 // vector and then insert into the 256-bit vector.
10720 if (!OpVT.is128BitVector()) {
10721 // Insert into a 128-bit vector.
10722 unsigned SizeFactor = OpVT.getSizeInBits()/128;
10723 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
10724 OpVT.getVectorNumElements() / SizeFactor);
10726 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
10728 // Insert the 128-bit vector.
10729 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
10732 if (OpVT == MVT::v1i64 &&
10733 Op.getOperand(0).getValueType() == MVT::i64)
10734 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
10736 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
10737 assert(OpVT.is128BitVector() && "Expected an SSE type!");
10738 return DAG.getNode(ISD::BITCAST, dl, OpVT,
10739 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
10742 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
10743 // a simple subregister reference or explicit instructions to grab
10744 // upper bits of a vector.
10745 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10746 SelectionDAG &DAG) {
10748 SDValue In = Op.getOperand(0);
10749 SDValue Idx = Op.getOperand(1);
10750 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10751 MVT ResVT = Op.getSimpleValueType();
10752 MVT InVT = In.getSimpleValueType();
10754 if (Subtarget->hasFp256()) {
10755 if (ResVT.is128BitVector() &&
10756 (InVT.is256BitVector() || InVT.is512BitVector()) &&
10757 isa<ConstantSDNode>(Idx)) {
10758 return Extract128BitVector(In, IdxVal, DAG, dl);
10760 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
10761 isa<ConstantSDNode>(Idx)) {
10762 return Extract256BitVector(In, IdxVal, DAG, dl);
10768 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
10769 // simple superregister reference or explicit instructions to insert
10770 // the upper bits of a vector.
10771 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10772 SelectionDAG &DAG) {
10773 if (!Subtarget->hasAVX())
10777 SDValue Vec = Op.getOperand(0);
10778 SDValue SubVec = Op.getOperand(1);
10779 SDValue Idx = Op.getOperand(2);
10781 if (!isa<ConstantSDNode>(Idx))
10784 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10785 MVT OpVT = Op.getSimpleValueType();
10786 MVT SubVecVT = SubVec.getSimpleValueType();
10788 // Fold two 16-byte subvector loads into one 32-byte load:
10789 // (insert_subvector (insert_subvector undef, (load addr), 0),
10790 // (load addr + 16), Elts/2)
10792 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
10793 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
10794 OpVT.is256BitVector() && SubVecVT.is128BitVector() &&
10795 !Subtarget->isUnalignedMem32Slow()) {
10796 SDValue SubVec2 = Vec.getOperand(1);
10797 if (auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2))) {
10798 if (Idx2->getZExtValue() == 0) {
10799 SDValue Ops[] = { SubVec2, SubVec };
10800 SDValue LD = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false);
10807 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
10808 SubVecVT.is128BitVector())
10809 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
10811 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
10812 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
10814 if (OpVT.getVectorElementType() == MVT::i1) {
10815 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
10817 SDValue ZeroIdx = DAG.getIntPtrConstant(0);
10818 SDValue Undef = DAG.getUNDEF(OpVT);
10819 unsigned NumElems = OpVT.getVectorNumElements();
10820 SDValue ShiftBits = DAG.getConstant(NumElems/2, MVT::i8);
10822 if (IdxVal == OpVT.getVectorNumElements() / 2) {
10823 // Zero upper bits of the Vec
10824 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
10825 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
10827 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
10829 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
10830 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
10833 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
10835 // Zero upper bits of the Vec2
10836 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
10837 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
10838 // Zero lower bits of the Vec
10839 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
10840 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
10841 // Merge them together
10842 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
10848 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
10849 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
10850 // one of the above mentioned nodes. It has to be wrapped because otherwise
10851 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
10852 // be used to form addressing mode. These wrapped nodes will be selected
10855 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
10856 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
10858 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10859 // global base reg.
10860 unsigned char OpFlag = 0;
10861 unsigned WrapperKind = X86ISD::Wrapper;
10862 CodeModel::Model M = DAG.getTarget().getCodeModel();
10864 if (Subtarget->isPICStyleRIPRel() &&
10865 (M == CodeModel::Small || M == CodeModel::Kernel))
10866 WrapperKind = X86ISD::WrapperRIP;
10867 else if (Subtarget->isPICStyleGOT())
10868 OpFlag = X86II::MO_GOTOFF;
10869 else if (Subtarget->isPICStyleStubPIC())
10870 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10872 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
10873 CP->getAlignment(),
10874 CP->getOffset(), OpFlag);
10876 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10877 // With PIC, the address is actually $g + Offset.
10879 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10880 DAG.getNode(X86ISD::GlobalBaseReg,
10881 SDLoc(), getPointerTy()),
10888 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
10889 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
10891 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10892 // global base reg.
10893 unsigned char OpFlag = 0;
10894 unsigned WrapperKind = X86ISD::Wrapper;
10895 CodeModel::Model M = DAG.getTarget().getCodeModel();
10897 if (Subtarget->isPICStyleRIPRel() &&
10898 (M == CodeModel::Small || M == CodeModel::Kernel))
10899 WrapperKind = X86ISD::WrapperRIP;
10900 else if (Subtarget->isPICStyleGOT())
10901 OpFlag = X86II::MO_GOTOFF;
10902 else if (Subtarget->isPICStyleStubPIC())
10903 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10905 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
10908 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10910 // With PIC, the address is actually $g + Offset.
10912 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10913 DAG.getNode(X86ISD::GlobalBaseReg,
10914 SDLoc(), getPointerTy()),
10921 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
10922 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
10924 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10925 // global base reg.
10926 unsigned char OpFlag = 0;
10927 unsigned WrapperKind = X86ISD::Wrapper;
10928 CodeModel::Model M = DAG.getTarget().getCodeModel();
10930 if (Subtarget->isPICStyleRIPRel() &&
10931 (M == CodeModel::Small || M == CodeModel::Kernel)) {
10932 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
10933 OpFlag = X86II::MO_GOTPCREL;
10934 WrapperKind = X86ISD::WrapperRIP;
10935 } else if (Subtarget->isPICStyleGOT()) {
10936 OpFlag = X86II::MO_GOT;
10937 } else if (Subtarget->isPICStyleStubPIC()) {
10938 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
10939 } else if (Subtarget->isPICStyleStubNoDynamic()) {
10940 OpFlag = X86II::MO_DARWIN_NONLAZY;
10943 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
10946 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10948 // With PIC, the address is actually $g + Offset.
10949 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
10950 !Subtarget->is64Bit()) {
10951 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10952 DAG.getNode(X86ISD::GlobalBaseReg,
10953 SDLoc(), getPointerTy()),
10957 // For symbols that require a load from a stub to get the address, emit the
10959 if (isGlobalStubReference(OpFlag))
10960 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
10961 MachinePointerInfo::getGOT(), false, false, false, 0);
10967 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
10968 // Create the TargetBlockAddressAddress node.
10969 unsigned char OpFlags =
10970 Subtarget->ClassifyBlockAddressReference();
10971 CodeModel::Model M = DAG.getTarget().getCodeModel();
10972 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
10973 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
10975 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
10978 if (Subtarget->isPICStyleRIPRel() &&
10979 (M == CodeModel::Small || M == CodeModel::Kernel))
10980 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
10982 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
10984 // With PIC, the address is actually $g + Offset.
10985 if (isGlobalRelativeToPICBase(OpFlags)) {
10986 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
10987 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
10995 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
10996 int64_t Offset, SelectionDAG &DAG) const {
10997 // Create the TargetGlobalAddress node, folding in the constant
10998 // offset if it is legal.
10999 unsigned char OpFlags =
11000 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11001 CodeModel::Model M = DAG.getTarget().getCodeModel();
11003 if (OpFlags == X86II::MO_NO_FLAG &&
11004 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11005 // A direct static reference to a global.
11006 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
11009 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
11012 if (Subtarget->isPICStyleRIPRel() &&
11013 (M == CodeModel::Small || M == CodeModel::Kernel))
11014 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11016 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11018 // With PIC, the address is actually $g + Offset.
11019 if (isGlobalRelativeToPICBase(OpFlags)) {
11020 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11021 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11025 // For globals that require a load from a stub to get the address, emit the
11027 if (isGlobalStubReference(OpFlags))
11028 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
11029 MachinePointerInfo::getGOT(), false, false, false, 0);
11031 // If there was a non-zero offset that we didn't fold, create an explicit
11032 // addition for it.
11034 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
11035 DAG.getConstant(Offset, getPointerTy()));
11041 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11042 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11043 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11044 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11048 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11049 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11050 unsigned char OperandFlags, bool LocalDynamic = false) {
11051 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11052 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11054 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11055 GA->getValueType(0),
11059 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11063 SDValue Ops[] = { Chain, TGA, *InFlag };
11064 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11066 SDValue Ops[] = { Chain, TGA };
11067 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11070 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11071 MFI->setAdjustsStack(true);
11072 MFI->setHasCalls(true);
11074 SDValue Flag = Chain.getValue(1);
11075 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11078 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11080 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11083 SDLoc dl(GA); // ? function entry point might be better
11084 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11085 DAG.getNode(X86ISD::GlobalBaseReg,
11086 SDLoc(), PtrVT), InFlag);
11087 InFlag = Chain.getValue(1);
11089 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11092 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11094 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11096 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11097 X86::RAX, X86II::MO_TLSGD);
11100 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11106 // Get the start address of the TLS block for this module.
11107 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11108 .getInfo<X86MachineFunctionInfo>();
11109 MFI->incNumLocalDynamicTLSAccesses();
11113 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11114 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11117 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11118 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
11119 InFlag = Chain.getValue(1);
11120 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
11121 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
11124 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
11128 unsigned char OperandFlags = X86II::MO_DTPOFF;
11129 unsigned WrapperKind = X86ISD::Wrapper;
11130 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11131 GA->getValueType(0),
11132 GA->getOffset(), OperandFlags);
11133 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11135 // Add x@dtpoff with the base.
11136 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
11139 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
11140 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11141 const EVT PtrVT, TLSModel::Model model,
11142 bool is64Bit, bool isPIC) {
11145 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
11146 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
11147 is64Bit ? 257 : 256));
11149 SDValue ThreadPointer =
11150 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
11151 MachinePointerInfo(Ptr), false, false, false, 0);
11153 unsigned char OperandFlags = 0;
11154 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
11156 unsigned WrapperKind = X86ISD::Wrapper;
11157 if (model == TLSModel::LocalExec) {
11158 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
11159 } else if (model == TLSModel::InitialExec) {
11161 OperandFlags = X86II::MO_GOTTPOFF;
11162 WrapperKind = X86ISD::WrapperRIP;
11164 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
11167 llvm_unreachable("Unexpected model");
11170 // emit "addl x@ntpoff,%eax" (local exec)
11171 // or "addl x@indntpoff,%eax" (initial exec)
11172 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
11174 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
11175 GA->getOffset(), OperandFlags);
11176 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11178 if (model == TLSModel::InitialExec) {
11179 if (isPIC && !is64Bit) {
11180 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
11181 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11185 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
11186 MachinePointerInfo::getGOT(), false, false, false, 0);
11189 // The address of the thread local variable is the add of the thread
11190 // pointer with the offset of the variable.
11191 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
11195 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
11197 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
11198 const GlobalValue *GV = GA->getGlobal();
11200 if (Subtarget->isTargetELF()) {
11201 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
11204 case TLSModel::GeneralDynamic:
11205 if (Subtarget->is64Bit())
11206 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
11207 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
11208 case TLSModel::LocalDynamic:
11209 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
11210 Subtarget->is64Bit());
11211 case TLSModel::InitialExec:
11212 case TLSModel::LocalExec:
11213 return LowerToTLSExecModel(
11214 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
11215 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
11217 llvm_unreachable("Unknown TLS model.");
11220 if (Subtarget->isTargetDarwin()) {
11221 // Darwin only has one model of TLS. Lower to that.
11222 unsigned char OpFlag = 0;
11223 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
11224 X86ISD::WrapperRIP : X86ISD::Wrapper;
11226 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11227 // global base reg.
11228 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
11229 !Subtarget->is64Bit();
11231 OpFlag = X86II::MO_TLVP_PIC_BASE;
11233 OpFlag = X86II::MO_TLVP;
11235 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
11236 GA->getValueType(0),
11237 GA->getOffset(), OpFlag);
11238 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11240 // With PIC32, the address is actually $g + Offset.
11242 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11243 DAG.getNode(X86ISD::GlobalBaseReg,
11244 SDLoc(), getPointerTy()),
11247 // Lowering the machine isd will make sure everything is in the right
11249 SDValue Chain = DAG.getEntryNode();
11250 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11251 SDValue Args[] = { Chain, Offset };
11252 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
11254 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
11255 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11256 MFI->setAdjustsStack(true);
11258 // And our return value (tls address) is in the standard call return value
11260 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11261 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
11262 Chain.getValue(1));
11265 if (Subtarget->isTargetKnownWindowsMSVC() ||
11266 Subtarget->isTargetWindowsGNU()) {
11267 // Just use the implicit TLS architecture
11268 // Need to generate someting similar to:
11269 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
11271 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
11272 // mov rcx, qword [rdx+rcx*8]
11273 // mov eax, .tls$:tlsvar
11274 // [rax+rcx] contains the address
11275 // Windows 64bit: gs:0x58
11276 // Windows 32bit: fs:__tls_array
11279 SDValue Chain = DAG.getEntryNode();
11281 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
11282 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
11283 // use its literal value of 0x2C.
11284 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
11285 ? Type::getInt8PtrTy(*DAG.getContext(),
11287 : Type::getInt32PtrTy(*DAG.getContext(),
11291 Subtarget->is64Bit()
11292 ? DAG.getIntPtrConstant(0x58)
11293 : (Subtarget->isTargetWindowsGNU()
11294 ? DAG.getIntPtrConstant(0x2C)
11295 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
11297 SDValue ThreadPointer =
11298 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
11299 MachinePointerInfo(Ptr), false, false, false, 0);
11301 // Load the _tls_index variable
11302 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
11303 if (Subtarget->is64Bit())
11304 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
11305 IDX, MachinePointerInfo(), MVT::i32,
11306 false, false, false, 0);
11308 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
11309 false, false, false, 0);
11311 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
11313 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
11315 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
11316 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
11317 false, false, false, 0);
11319 // Get the offset of start of .tls section
11320 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11321 GA->getValueType(0),
11322 GA->getOffset(), X86II::MO_SECREL);
11323 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
11325 // The address of the thread local variable is the add of the thread
11326 // pointer with the offset of the variable.
11327 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
11330 llvm_unreachable("TLS not implemented for this target.");
11333 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
11334 /// and take a 2 x i32 value to shift plus a shift amount.
11335 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
11336 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
11337 MVT VT = Op.getSimpleValueType();
11338 unsigned VTBits = VT.getSizeInBits();
11340 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
11341 SDValue ShOpLo = Op.getOperand(0);
11342 SDValue ShOpHi = Op.getOperand(1);
11343 SDValue ShAmt = Op.getOperand(2);
11344 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
11345 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
11347 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11348 DAG.getConstant(VTBits - 1, MVT::i8));
11349 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
11350 DAG.getConstant(VTBits - 1, MVT::i8))
11351 : DAG.getConstant(0, VT);
11353 SDValue Tmp2, Tmp3;
11354 if (Op.getOpcode() == ISD::SHL_PARTS) {
11355 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
11356 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
11358 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
11359 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
11362 // If the shift amount is larger or equal than the width of a part we can't
11363 // rely on the results of shld/shrd. Insert a test and select the appropriate
11364 // values for large shift amounts.
11365 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11366 DAG.getConstant(VTBits, MVT::i8));
11367 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
11368 AndNode, DAG.getConstant(0, MVT::i8));
11371 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
11372 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
11373 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
11375 if (Op.getOpcode() == ISD::SHL_PARTS) {
11376 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11377 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11379 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11380 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11383 SDValue Ops[2] = { Lo, Hi };
11384 return DAG.getMergeValues(Ops, dl);
11387 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
11388 SelectionDAG &DAG) const {
11389 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
11392 if (SrcVT.isVector()) {
11393 if (SrcVT.getVectorElementType() == MVT::i1) {
11394 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
11395 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11396 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
11397 Op.getOperand(0)));
11402 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
11403 "Unknown SINT_TO_FP to lower!");
11405 // These are really Legal; return the operand so the caller accepts it as
11407 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
11409 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
11410 Subtarget->is64Bit()) {
11414 unsigned Size = SrcVT.getSizeInBits()/8;
11415 MachineFunction &MF = DAG.getMachineFunction();
11416 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
11417 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11418 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11420 MachinePointerInfo::getFixedStack(SSFI),
11422 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
11425 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
11427 SelectionDAG &DAG) const {
11431 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
11433 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
11435 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
11437 unsigned ByteSize = SrcVT.getSizeInBits()/8;
11439 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
11440 MachineMemOperand *MMO;
11442 int SSFI = FI->getIndex();
11444 DAG.getMachineFunction()
11445 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11446 MachineMemOperand::MOLoad, ByteSize, ByteSize);
11448 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
11449 StackSlot = StackSlot.getOperand(1);
11451 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
11452 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
11454 Tys, Ops, SrcVT, MMO);
11457 Chain = Result.getValue(1);
11458 SDValue InFlag = Result.getValue(2);
11460 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
11461 // shouldn't be necessary except that RFP cannot be live across
11462 // multiple blocks. When stackifier is fixed, they can be uncoupled.
11463 MachineFunction &MF = DAG.getMachineFunction();
11464 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
11465 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
11466 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11467 Tys = DAG.getVTList(MVT::Other);
11469 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
11471 MachineMemOperand *MMO =
11472 DAG.getMachineFunction()
11473 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11474 MachineMemOperand::MOStore, SSFISize, SSFISize);
11476 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
11477 Ops, Op.getValueType(), MMO);
11478 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
11479 MachinePointerInfo::getFixedStack(SSFI),
11480 false, false, false, 0);
11486 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
11487 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
11488 SelectionDAG &DAG) const {
11489 // This algorithm is not obvious. Here it is what we're trying to output:
11492 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
11493 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
11495 haddpd %xmm0, %xmm0
11497 pshufd $0x4e, %xmm0, %xmm1
11503 LLVMContext *Context = DAG.getContext();
11505 // Build some magic constants.
11506 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
11507 Constant *C0 = ConstantDataVector::get(*Context, CV0);
11508 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
11510 SmallVector<Constant*,2> CV1;
11512 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11513 APInt(64, 0x4330000000000000ULL))));
11515 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11516 APInt(64, 0x4530000000000000ULL))));
11517 Constant *C1 = ConstantVector::get(CV1);
11518 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
11520 // Load the 64-bit value into an XMM register.
11521 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
11523 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
11524 MachinePointerInfo::getConstantPool(),
11525 false, false, false, 16);
11526 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
11527 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
11530 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
11531 MachinePointerInfo::getConstantPool(),
11532 false, false, false, 16);
11533 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
11534 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
11537 if (Subtarget->hasSSE3()) {
11538 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
11539 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
11541 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
11542 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
11544 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
11545 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
11549 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
11550 DAG.getIntPtrConstant(0));
11553 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
11554 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
11555 SelectionDAG &DAG) const {
11557 // FP constant to bias correct the final result.
11558 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
11561 // Load the 32-bit value into an XMM register.
11562 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
11565 // Zero out the upper parts of the register.
11566 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
11568 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11569 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
11570 DAG.getIntPtrConstant(0));
11572 // Or the load with the bias.
11573 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
11574 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11575 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11576 MVT::v2f64, Load)),
11577 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11578 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11579 MVT::v2f64, Bias)));
11580 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11581 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
11582 DAG.getIntPtrConstant(0));
11584 // Subtract the bias.
11585 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
11587 // Handle final rounding.
11588 EVT DestVT = Op.getValueType();
11590 if (DestVT.bitsLT(MVT::f64))
11591 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
11592 DAG.getIntPtrConstant(0));
11593 if (DestVT.bitsGT(MVT::f64))
11594 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
11596 // Handle final rounding.
11600 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
11601 const X86Subtarget &Subtarget) {
11602 // The algorithm is the following:
11603 // #ifdef __SSE4_1__
11604 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
11605 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
11606 // (uint4) 0x53000000, 0xaa);
11608 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
11609 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
11611 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
11612 // return (float4) lo + fhi;
11615 SDValue V = Op->getOperand(0);
11616 EVT VecIntVT = V.getValueType();
11617 bool Is128 = VecIntVT == MVT::v4i32;
11618 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
11619 // If we convert to something else than the supported type, e.g., to v4f64,
11621 if (VecFloatVT != Op->getValueType(0))
11624 unsigned NumElts = VecIntVT.getVectorNumElements();
11625 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
11626 "Unsupported custom type");
11627 assert(NumElts <= 8 && "The size of the constant array must be fixed");
11629 // In the #idef/#else code, we have in common:
11630 // - The vector of constants:
11636 // Create the splat vector for 0x4b000000.
11637 SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);
11638 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
11639 CstLow, CstLow, CstLow, CstLow};
11640 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11641 makeArrayRef(&CstLowArray[0], NumElts));
11642 // Create the splat vector for 0x53000000.
11643 SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);
11644 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
11645 CstHigh, CstHigh, CstHigh, CstHigh};
11646 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11647 makeArrayRef(&CstHighArray[0], NumElts));
11649 // Create the right shift.
11650 SDValue CstShift = DAG.getConstant(16, MVT::i32);
11651 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
11652 CstShift, CstShift, CstShift, CstShift};
11653 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11654 makeArrayRef(&CstShiftArray[0], NumElts));
11655 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
11658 if (Subtarget.hasSSE41()) {
11659 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
11660 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
11661 SDValue VecCstLowBitcast =
11662 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
11663 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
11664 // Low will be bitcasted right away, so do not bother bitcasting back to its
11666 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
11667 VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));
11668 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
11669 // (uint4) 0x53000000, 0xaa);
11670 SDValue VecCstHighBitcast =
11671 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
11672 SDValue VecShiftBitcast =
11673 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
11674 // High will be bitcasted right away, so do not bother bitcasting back to
11675 // its original type.
11676 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
11677 VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32));
11679 SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);
11680 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
11681 CstMask, CstMask, CstMask);
11682 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
11683 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
11684 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
11686 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
11687 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
11690 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
11691 SDValue CstFAdd = DAG.getConstantFP(
11692 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);
11693 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
11694 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
11695 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
11696 makeArrayRef(&CstFAddArray[0], NumElts));
11698 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
11699 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
11701 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
11702 // return (float4) lo + fhi;
11703 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
11704 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
11707 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
11708 SelectionDAG &DAG) const {
11709 SDValue N0 = Op.getOperand(0);
11710 MVT SVT = N0.getSimpleValueType();
11713 switch (SVT.SimpleTy) {
11715 llvm_unreachable("Custom UINT_TO_FP is not supported!");
11720 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
11721 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11722 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
11726 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
11728 llvm_unreachable(nullptr);
11731 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
11732 SelectionDAG &DAG) const {
11733 SDValue N0 = Op.getOperand(0);
11736 if (Op.getValueType().isVector())
11737 return lowerUINT_TO_FP_vec(Op, DAG);
11739 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
11740 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
11741 // the optimization here.
11742 if (DAG.SignBitIsZero(N0))
11743 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
11745 MVT SrcVT = N0.getSimpleValueType();
11746 MVT DstVT = Op.getSimpleValueType();
11747 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
11748 return LowerUINT_TO_FP_i64(Op, DAG);
11749 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
11750 return LowerUINT_TO_FP_i32(Op, DAG);
11751 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
11754 // Make a 64-bit buffer, and use it to build an FILD.
11755 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
11756 if (SrcVT == MVT::i32) {
11757 SDValue WordOff = DAG.getConstant(4, getPointerTy());
11758 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
11759 getPointerTy(), StackSlot, WordOff);
11760 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11761 StackSlot, MachinePointerInfo(),
11763 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
11764 OffsetSlot, MachinePointerInfo(),
11766 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
11770 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
11771 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11772 StackSlot, MachinePointerInfo(),
11774 // For i64 source, we need to add the appropriate power of 2 if the input
11775 // was negative. This is the same as the optimization in
11776 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
11777 // we must be careful to do the computation in x87 extended precision, not
11778 // in SSE. (The generic code can't know it's OK to do this, or how to.)
11779 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
11780 MachineMemOperand *MMO =
11781 DAG.getMachineFunction()
11782 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11783 MachineMemOperand::MOLoad, 8, 8);
11785 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
11786 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
11787 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
11790 APInt FF(32, 0x5F800000ULL);
11792 // Check whether the sign bit is set.
11793 SDValue SignSet = DAG.getSetCC(dl,
11794 getSetCCResultType(*DAG.getContext(), MVT::i64),
11795 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
11798 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
11799 SDValue FudgePtr = DAG.getConstantPool(
11800 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
11803 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
11804 SDValue Zero = DAG.getIntPtrConstant(0);
11805 SDValue Four = DAG.getIntPtrConstant(4);
11806 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
11808 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
11810 // Load the value out, extending it from f32 to f80.
11811 // FIXME: Avoid the extend by constructing the right constant pool?
11812 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
11813 FudgePtr, MachinePointerInfo::getConstantPool(),
11814 MVT::f32, false, false, false, 4);
11815 // Extend everything to 80 bits to force it to be done on x87.
11816 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
11817 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
11820 std::pair<SDValue,SDValue>
11821 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
11822 bool IsSigned, bool IsReplace) const {
11825 EVT DstTy = Op.getValueType();
11827 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
11828 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
11832 assert(DstTy.getSimpleVT() <= MVT::i64 &&
11833 DstTy.getSimpleVT() >= MVT::i16 &&
11834 "Unknown FP_TO_INT to lower!");
11836 // These are really Legal.
11837 if (DstTy == MVT::i32 &&
11838 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11839 return std::make_pair(SDValue(), SDValue());
11840 if (Subtarget->is64Bit() &&
11841 DstTy == MVT::i64 &&
11842 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11843 return std::make_pair(SDValue(), SDValue());
11845 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
11846 // stack slot, or into the FTOL runtime function.
11847 MachineFunction &MF = DAG.getMachineFunction();
11848 unsigned MemSize = DstTy.getSizeInBits()/8;
11849 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11850 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11853 if (!IsSigned && isIntegerTypeFTOL(DstTy))
11854 Opc = X86ISD::WIN_FTOL;
11856 switch (DstTy.getSimpleVT().SimpleTy) {
11857 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
11858 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
11859 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
11860 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
11863 SDValue Chain = DAG.getEntryNode();
11864 SDValue Value = Op.getOperand(0);
11865 EVT TheVT = Op.getOperand(0).getValueType();
11866 // FIXME This causes a redundant load/store if the SSE-class value is already
11867 // in memory, such as if it is on the callstack.
11868 if (isScalarFPTypeInSSEReg(TheVT)) {
11869 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
11870 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
11871 MachinePointerInfo::getFixedStack(SSFI),
11873 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
11875 Chain, StackSlot, DAG.getValueType(TheVT)
11878 MachineMemOperand *MMO =
11879 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11880 MachineMemOperand::MOLoad, MemSize, MemSize);
11881 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
11882 Chain = Value.getValue(1);
11883 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11884 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11887 MachineMemOperand *MMO =
11888 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11889 MachineMemOperand::MOStore, MemSize, MemSize);
11891 if (Opc != X86ISD::WIN_FTOL) {
11892 // Build the FP_TO_INT*_IN_MEM
11893 SDValue Ops[] = { Chain, Value, StackSlot };
11894 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
11896 return std::make_pair(FIST, StackSlot);
11898 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
11899 DAG.getVTList(MVT::Other, MVT::Glue),
11901 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
11902 MVT::i32, ftol.getValue(1));
11903 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
11904 MVT::i32, eax.getValue(2));
11905 SDValue Ops[] = { eax, edx };
11906 SDValue pair = IsReplace
11907 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
11908 : DAG.getMergeValues(Ops, DL);
11909 return std::make_pair(pair, SDValue());
11913 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
11914 const X86Subtarget *Subtarget) {
11915 MVT VT = Op->getSimpleValueType(0);
11916 SDValue In = Op->getOperand(0);
11917 MVT InVT = In.getSimpleValueType();
11920 // Optimize vectors in AVX mode:
11923 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
11924 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
11925 // Concat upper and lower parts.
11928 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
11929 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
11930 // Concat upper and lower parts.
11933 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
11934 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
11935 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
11938 if (Subtarget->hasInt256())
11939 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
11941 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
11942 SDValue Undef = DAG.getUNDEF(InVT);
11943 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
11944 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11945 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11947 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
11948 VT.getVectorNumElements()/2);
11950 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
11951 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
11953 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
11956 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
11957 SelectionDAG &DAG) {
11958 MVT VT = Op->getSimpleValueType(0);
11959 SDValue In = Op->getOperand(0);
11960 MVT InVT = In.getSimpleValueType();
11962 unsigned int NumElts = VT.getVectorNumElements();
11963 if (NumElts != 8 && NumElts != 16)
11966 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
11967 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
11969 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
11970 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11971 // Now we have only mask extension
11972 assert(InVT.getVectorElementType() == MVT::i1);
11973 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
11974 const Constant *C = cast<ConstantSDNode>(Cst)->getConstantIntValue();
11975 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
11976 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
11977 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
11978 MachinePointerInfo::getConstantPool(),
11979 false, false, false, Alignment);
11981 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
11982 if (VT.is512BitVector())
11984 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
11987 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
11988 SelectionDAG &DAG) {
11989 if (Subtarget->hasFp256()) {
11990 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
11998 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
11999 SelectionDAG &DAG) {
12001 MVT VT = Op.getSimpleValueType();
12002 SDValue In = Op.getOperand(0);
12003 MVT SVT = In.getSimpleValueType();
12005 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12006 return LowerZERO_EXTEND_AVX512(Op, DAG);
12008 if (Subtarget->hasFp256()) {
12009 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
12014 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12015 VT.getVectorNumElements() != SVT.getVectorNumElements());
12019 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
12021 MVT VT = Op.getSimpleValueType();
12022 SDValue In = Op.getOperand(0);
12023 MVT InVT = In.getSimpleValueType();
12025 if (VT == MVT::i1) {
12026 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
12027 "Invalid scalar TRUNCATE operation");
12028 if (InVT.getSizeInBits() >= 32)
12030 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
12031 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
12033 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
12034 "Invalid TRUNCATE operation");
12036 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
12037 if (VT.getVectorElementType().getSizeInBits() >=8)
12038 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
12040 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12041 unsigned NumElts = InVT.getVectorNumElements();
12042 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
12043 if (InVT.getSizeInBits() < 512) {
12044 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
12045 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
12049 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
12050 const Constant *C = cast<ConstantSDNode>(Cst)->getConstantIntValue();
12051 SDValue CP = DAG.getConstantPool(C, getPointerTy());
12052 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
12053 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
12054 MachinePointerInfo::getConstantPool(),
12055 false, false, false, Alignment);
12056 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
12057 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
12058 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
12061 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
12062 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
12063 if (Subtarget->hasInt256()) {
12064 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
12065 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
12066 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
12068 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
12069 DAG.getIntPtrConstant(0));
12072 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12073 DAG.getIntPtrConstant(0));
12074 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12075 DAG.getIntPtrConstant(2));
12076 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12077 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12078 static const int ShufMask[] = {0, 2, 4, 6};
12079 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
12082 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
12083 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
12084 if (Subtarget->hasInt256()) {
12085 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
12087 SmallVector<SDValue,32> pshufbMask;
12088 for (unsigned i = 0; i < 2; ++i) {
12089 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
12090 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
12091 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
12092 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
12093 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
12094 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
12095 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
12096 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
12097 for (unsigned j = 0; j < 8; ++j)
12098 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
12100 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
12101 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
12102 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
12104 static const int ShufMask[] = {0, 2, -1, -1};
12105 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
12107 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12108 DAG.getIntPtrConstant(0));
12109 return DAG.getNode(ISD::BITCAST, DL, VT, In);
12112 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12113 DAG.getIntPtrConstant(0));
12115 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12116 DAG.getIntPtrConstant(4));
12118 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
12119 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
12121 // The PSHUFB mask:
12122 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12123 -1, -1, -1, -1, -1, -1, -1, -1};
12125 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
12126 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
12127 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
12129 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
12130 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
12132 // The MOVLHPS Mask:
12133 static const int ShufMask2[] = {0, 1, 4, 5};
12134 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
12135 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
12138 // Handle truncation of V256 to V128 using shuffles.
12139 if (!VT.is128BitVector() || !InVT.is256BitVector())
12142 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
12144 unsigned NumElems = VT.getVectorNumElements();
12145 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
12147 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
12148 // Prepare truncation shuffle mask
12149 for (unsigned i = 0; i != NumElems; ++i)
12150 MaskVec[i] = i * 2;
12151 SDValue V = DAG.getVectorShuffle(NVT, DL,
12152 DAG.getNode(ISD::BITCAST, DL, NVT, In),
12153 DAG.getUNDEF(NVT), &MaskVec[0]);
12154 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
12155 DAG.getIntPtrConstant(0));
12158 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
12159 SelectionDAG &DAG) const {
12160 assert(!Op.getSimpleValueType().isVector());
12162 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12163 /*IsSigned=*/ true, /*IsReplace=*/ false);
12164 SDValue FIST = Vals.first, StackSlot = Vals.second;
12165 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
12166 if (!FIST.getNode()) return Op;
12168 if (StackSlot.getNode())
12169 // Load the result.
12170 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12171 FIST, StackSlot, MachinePointerInfo(),
12172 false, false, false, 0);
12174 // The node is the result.
12178 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
12179 SelectionDAG &DAG) const {
12180 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12181 /*IsSigned=*/ false, /*IsReplace=*/ false);
12182 SDValue FIST = Vals.first, StackSlot = Vals.second;
12183 assert(FIST.getNode() && "Unexpected failure");
12185 if (StackSlot.getNode())
12186 // Load the result.
12187 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12188 FIST, StackSlot, MachinePointerInfo(),
12189 false, false, false, 0);
12191 // The node is the result.
12195 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
12197 MVT VT = Op.getSimpleValueType();
12198 SDValue In = Op.getOperand(0);
12199 MVT SVT = In.getSimpleValueType();
12201 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
12203 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
12204 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
12205 In, DAG.getUNDEF(SVT)));
12208 /// The only differences between FABS and FNEG are the mask and the logic op.
12209 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
12210 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
12211 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
12212 "Wrong opcode for lowering FABS or FNEG.");
12214 bool IsFABS = (Op.getOpcode() == ISD::FABS);
12216 // If this is a FABS and it has an FNEG user, bail out to fold the combination
12217 // into an FNABS. We'll lower the FABS after that if it is still in use.
12219 for (SDNode *User : Op->uses())
12220 if (User->getOpcode() == ISD::FNEG)
12223 SDValue Op0 = Op.getOperand(0);
12224 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
12227 MVT VT = Op.getSimpleValueType();
12228 // Assume scalar op for initialization; update for vector if needed.
12229 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
12230 // generate a 16-byte vector constant and logic op even for the scalar case.
12231 // Using a 16-byte mask allows folding the load of the mask with
12232 // the logic op, so it can save (~4 bytes) on code size.
12234 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
12235 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
12236 // decide if we should generate a 16-byte constant mask when we only need 4 or
12237 // 8 bytes for the scalar case.
12238 if (VT.isVector()) {
12239 EltVT = VT.getVectorElementType();
12240 NumElts = VT.getVectorNumElements();
12243 unsigned EltBits = EltVT.getSizeInBits();
12244 LLVMContext *Context = DAG.getContext();
12245 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
12247 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
12248 Constant *C = ConstantInt::get(*Context, MaskElt);
12249 C = ConstantVector::getSplat(NumElts, C);
12250 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12251 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
12252 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
12253 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12254 MachinePointerInfo::getConstantPool(),
12255 false, false, false, Alignment);
12257 if (VT.isVector()) {
12258 // For a vector, cast operands to a vector type, perform the logic op,
12259 // and cast the result back to the original value type.
12260 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
12261 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
12262 SDValue Operand = IsFNABS ?
12263 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
12264 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
12265 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
12266 return DAG.getNode(ISD::BITCAST, dl, VT,
12267 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
12270 // If not vector, then scalar.
12271 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
12272 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
12273 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
12276 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
12277 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12278 LLVMContext *Context = DAG.getContext();
12279 SDValue Op0 = Op.getOperand(0);
12280 SDValue Op1 = Op.getOperand(1);
12282 MVT VT = Op.getSimpleValueType();
12283 MVT SrcVT = Op1.getSimpleValueType();
12285 // If second operand is smaller, extend it first.
12286 if (SrcVT.bitsLT(VT)) {
12287 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
12290 // And if it is bigger, shrink it first.
12291 if (SrcVT.bitsGT(VT)) {
12292 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
12296 // At this point the operands and the result should have the same
12297 // type, and that won't be f80 since that is not custom lowered.
12299 const fltSemantics &Sem =
12300 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
12301 const unsigned SizeInBits = VT.getSizeInBits();
12303 SmallVector<Constant *, 4> CV(
12304 VT == MVT::f64 ? 2 : 4,
12305 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
12307 // First, clear all bits but the sign bit from the second operand (sign).
12308 CV[0] = ConstantFP::get(*Context,
12309 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
12310 Constant *C = ConstantVector::get(CV);
12311 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12312 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
12313 MachinePointerInfo::getConstantPool(),
12314 false, false, false, 16);
12315 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
12317 // Next, clear the sign bit from the first operand (magnitude).
12318 // If it's a constant, we can clear it here.
12319 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
12320 APFloat APF = Op0CN->getValueAPF();
12321 // If the magnitude is a positive zero, the sign bit alone is enough.
12322 if (APF.isPosZero())
12325 CV[0] = ConstantFP::get(*Context, APF);
12327 CV[0] = ConstantFP::get(
12329 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
12331 C = ConstantVector::get(CV);
12332 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12333 SDValue Val = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12334 MachinePointerInfo::getConstantPool(),
12335 false, false, false, 16);
12336 // If the magnitude operand wasn't a constant, we need to AND out the sign.
12337 if (!isa<ConstantFPSDNode>(Op0))
12338 Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Val);
12340 // OR the magnitude value with the sign bit.
12341 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
12344 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
12345 SDValue N0 = Op.getOperand(0);
12347 MVT VT = Op.getSimpleValueType();
12349 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
12350 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
12351 DAG.getConstant(1, VT));
12352 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
12355 // Check whether an OR'd tree is PTEST-able.
12356 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
12357 SelectionDAG &DAG) {
12358 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
12360 if (!Subtarget->hasSSE41())
12363 if (!Op->hasOneUse())
12366 SDNode *N = Op.getNode();
12369 SmallVector<SDValue, 8> Opnds;
12370 DenseMap<SDValue, unsigned> VecInMap;
12371 SmallVector<SDValue, 8> VecIns;
12372 EVT VT = MVT::Other;
12374 // Recognize a special case where a vector is casted into wide integer to
12376 Opnds.push_back(N->getOperand(0));
12377 Opnds.push_back(N->getOperand(1));
12379 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
12380 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
12381 // BFS traverse all OR'd operands.
12382 if (I->getOpcode() == ISD::OR) {
12383 Opnds.push_back(I->getOperand(0));
12384 Opnds.push_back(I->getOperand(1));
12385 // Re-evaluate the number of nodes to be traversed.
12386 e += 2; // 2 more nodes (LHS and RHS) are pushed.
12390 // Quit if a non-EXTRACT_VECTOR_ELT
12391 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12394 // Quit if without a constant index.
12395 SDValue Idx = I->getOperand(1);
12396 if (!isa<ConstantSDNode>(Idx))
12399 SDValue ExtractedFromVec = I->getOperand(0);
12400 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
12401 if (M == VecInMap.end()) {
12402 VT = ExtractedFromVec.getValueType();
12403 // Quit if not 128/256-bit vector.
12404 if (!VT.is128BitVector() && !VT.is256BitVector())
12406 // Quit if not the same type.
12407 if (VecInMap.begin() != VecInMap.end() &&
12408 VT != VecInMap.begin()->first.getValueType())
12410 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
12411 VecIns.push_back(ExtractedFromVec);
12413 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
12416 assert((VT.is128BitVector() || VT.is256BitVector()) &&
12417 "Not extracted from 128-/256-bit vector.");
12419 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
12421 for (DenseMap<SDValue, unsigned>::const_iterator
12422 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
12423 // Quit if not all elements are used.
12424 if (I->second != FullMask)
12428 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
12430 // Cast all vectors into TestVT for PTEST.
12431 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
12432 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
12434 // If more than one full vectors are evaluated, OR them first before PTEST.
12435 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
12436 // Each iteration will OR 2 nodes and append the result until there is only
12437 // 1 node left, i.e. the final OR'd value of all vectors.
12438 SDValue LHS = VecIns[Slot];
12439 SDValue RHS = VecIns[Slot + 1];
12440 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
12443 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
12444 VecIns.back(), VecIns.back());
12447 /// \brief return true if \c Op has a use that doesn't just read flags.
12448 static bool hasNonFlagsUse(SDValue Op) {
12449 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
12451 SDNode *User = *UI;
12452 unsigned UOpNo = UI.getOperandNo();
12453 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
12454 // Look pass truncate.
12455 UOpNo = User->use_begin().getOperandNo();
12456 User = *User->use_begin();
12459 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
12460 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
12466 /// Emit nodes that will be selected as "test Op0,Op0", or something
12468 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
12469 SelectionDAG &DAG) const {
12470 if (Op.getValueType() == MVT::i1) {
12471 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
12472 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
12473 DAG.getConstant(0, MVT::i8));
12475 // CF and OF aren't always set the way we want. Determine which
12476 // of these we need.
12477 bool NeedCF = false;
12478 bool NeedOF = false;
12481 case X86::COND_A: case X86::COND_AE:
12482 case X86::COND_B: case X86::COND_BE:
12485 case X86::COND_G: case X86::COND_GE:
12486 case X86::COND_L: case X86::COND_LE:
12487 case X86::COND_O: case X86::COND_NO: {
12488 // Check if we really need to set the
12489 // Overflow flag. If NoSignedWrap is present
12490 // that is not actually needed.
12491 switch (Op->getOpcode()) {
12496 const BinaryWithFlagsSDNode *BinNode =
12497 cast<BinaryWithFlagsSDNode>(Op.getNode());
12498 if (BinNode->hasNoSignedWrap())
12508 // See if we can use the EFLAGS value from the operand instead of
12509 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
12510 // we prove that the arithmetic won't overflow, we can't use OF or CF.
12511 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
12512 // Emit a CMP with 0, which is the TEST pattern.
12513 //if (Op.getValueType() == MVT::i1)
12514 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
12515 // DAG.getConstant(0, MVT::i1));
12516 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12517 DAG.getConstant(0, Op.getValueType()));
12519 unsigned Opcode = 0;
12520 unsigned NumOperands = 0;
12522 // Truncate operations may prevent the merge of the SETCC instruction
12523 // and the arithmetic instruction before it. Attempt to truncate the operands
12524 // of the arithmetic instruction and use a reduced bit-width instruction.
12525 bool NeedTruncation = false;
12526 SDValue ArithOp = Op;
12527 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
12528 SDValue Arith = Op->getOperand(0);
12529 // Both the trunc and the arithmetic op need to have one user each.
12530 if (Arith->hasOneUse())
12531 switch (Arith.getOpcode()) {
12538 NeedTruncation = true;
12544 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
12545 // which may be the result of a CAST. We use the variable 'Op', which is the
12546 // non-casted variable when we check for possible users.
12547 switch (ArithOp.getOpcode()) {
12549 // Due to an isel shortcoming, be conservative if this add is likely to be
12550 // selected as part of a load-modify-store instruction. When the root node
12551 // in a match is a store, isel doesn't know how to remap non-chain non-flag
12552 // uses of other nodes in the match, such as the ADD in this case. This
12553 // leads to the ADD being left around and reselected, with the result being
12554 // two adds in the output. Alas, even if none our users are stores, that
12555 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
12556 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
12557 // climbing the DAG back to the root, and it doesn't seem to be worth the
12559 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12560 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12561 if (UI->getOpcode() != ISD::CopyToReg &&
12562 UI->getOpcode() != ISD::SETCC &&
12563 UI->getOpcode() != ISD::STORE)
12566 if (ConstantSDNode *C =
12567 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
12568 // An add of one will be selected as an INC.
12569 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
12570 Opcode = X86ISD::INC;
12575 // An add of negative one (subtract of one) will be selected as a DEC.
12576 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
12577 Opcode = X86ISD::DEC;
12583 // Otherwise use a regular EFLAGS-setting add.
12584 Opcode = X86ISD::ADD;
12589 // If we have a constant logical shift that's only used in a comparison
12590 // against zero turn it into an equivalent AND. This allows turning it into
12591 // a TEST instruction later.
12592 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
12593 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
12594 EVT VT = Op.getValueType();
12595 unsigned BitWidth = VT.getSizeInBits();
12596 unsigned ShAmt = Op->getConstantOperandVal(1);
12597 if (ShAmt >= BitWidth) // Avoid undefined shifts.
12599 APInt Mask = ArithOp.getOpcode() == ISD::SRL
12600 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
12601 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
12602 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
12604 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
12605 DAG.getConstant(Mask, VT));
12606 DAG.ReplaceAllUsesWith(Op, New);
12612 // If the primary and result isn't used, don't bother using X86ISD::AND,
12613 // because a TEST instruction will be better.
12614 if (!hasNonFlagsUse(Op))
12620 // Due to the ISEL shortcoming noted above, be conservative if this op is
12621 // likely to be selected as part of a load-modify-store instruction.
12622 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12623 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12624 if (UI->getOpcode() == ISD::STORE)
12627 // Otherwise use a regular EFLAGS-setting instruction.
12628 switch (ArithOp.getOpcode()) {
12629 default: llvm_unreachable("unexpected operator!");
12630 case ISD::SUB: Opcode = X86ISD::SUB; break;
12631 case ISD::XOR: Opcode = X86ISD::XOR; break;
12632 case ISD::AND: Opcode = X86ISD::AND; break;
12634 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
12635 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
12636 if (EFLAGS.getNode())
12639 Opcode = X86ISD::OR;
12653 return SDValue(Op.getNode(), 1);
12659 // If we found that truncation is beneficial, perform the truncation and
12661 if (NeedTruncation) {
12662 EVT VT = Op.getValueType();
12663 SDValue WideVal = Op->getOperand(0);
12664 EVT WideVT = WideVal.getValueType();
12665 unsigned ConvertedOp = 0;
12666 // Use a target machine opcode to prevent further DAGCombine
12667 // optimizations that may separate the arithmetic operations
12668 // from the setcc node.
12669 switch (WideVal.getOpcode()) {
12671 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
12672 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
12673 case ISD::AND: ConvertedOp = X86ISD::AND; break;
12674 case ISD::OR: ConvertedOp = X86ISD::OR; break;
12675 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
12679 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12680 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
12681 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
12682 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
12683 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
12689 // Emit a CMP with 0, which is the TEST pattern.
12690 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12691 DAG.getConstant(0, Op.getValueType()));
12693 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
12694 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
12696 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
12697 DAG.ReplaceAllUsesWith(Op, New);
12698 return SDValue(New.getNode(), 1);
12701 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
12703 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
12704 SDLoc dl, SelectionDAG &DAG) const {
12705 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
12706 if (C->getAPIntValue() == 0)
12707 return EmitTest(Op0, X86CC, dl, DAG);
12709 if (Op0.getValueType() == MVT::i1)
12710 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
12713 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
12714 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
12715 // Do the comparison at i32 if it's smaller, besides the Atom case.
12716 // This avoids subregister aliasing issues. Keep the smaller reference
12717 // if we're optimizing for size, however, as that'll allow better folding
12718 // of memory operations.
12719 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
12720 !DAG.getMachineFunction().getFunction()->hasFnAttribute(
12721 Attribute::MinSize) &&
12722 !Subtarget->isAtom()) {
12723 unsigned ExtendOp =
12724 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
12725 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
12726 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
12728 // Use SUB instead of CMP to enable CSE between SUB and CMP.
12729 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
12730 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
12732 return SDValue(Sub.getNode(), 1);
12734 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
12737 /// Convert a comparison if required by the subtarget.
12738 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
12739 SelectionDAG &DAG) const {
12740 // If the subtarget does not support the FUCOMI instruction, floating-point
12741 // comparisons have to be converted.
12742 if (Subtarget->hasCMov() ||
12743 Cmp.getOpcode() != X86ISD::CMP ||
12744 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
12745 !Cmp.getOperand(1).getValueType().isFloatingPoint())
12748 // The instruction selector will select an FUCOM instruction instead of
12749 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
12750 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
12751 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
12753 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
12754 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
12755 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
12756 DAG.getConstant(8, MVT::i8));
12757 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
12758 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
12761 /// The minimum architected relative accuracy is 2^-12. We need one
12762 /// Newton-Raphson step to have a good float result (24 bits of precision).
12763 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
12764 DAGCombinerInfo &DCI,
12765 unsigned &RefinementSteps,
12766 bool &UseOneConstNR) const {
12767 // FIXME: We should use instruction latency models to calculate the cost of
12768 // each potential sequence, but this is very hard to do reliably because
12769 // at least Intel's Core* chips have variable timing based on the number of
12770 // significant digits in the divisor and/or sqrt operand.
12771 if (!Subtarget->useSqrtEst())
12774 EVT VT = Op.getValueType();
12776 // SSE1 has rsqrtss and rsqrtps.
12777 // TODO: Add support for AVX512 (v16f32).
12778 // It is likely not profitable to do this for f64 because a double-precision
12779 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
12780 // instructions: convert to single, rsqrtss, convert back to double, refine
12781 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
12782 // along with FMA, this could be a throughput win.
12783 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
12784 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
12785 RefinementSteps = 1;
12786 UseOneConstNR = false;
12787 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
12792 /// The minimum architected relative accuracy is 2^-12. We need one
12793 /// Newton-Raphson step to have a good float result (24 bits of precision).
12794 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
12795 DAGCombinerInfo &DCI,
12796 unsigned &RefinementSteps) const {
12797 // FIXME: We should use instruction latency models to calculate the cost of
12798 // each potential sequence, but this is very hard to do reliably because
12799 // at least Intel's Core* chips have variable timing based on the number of
12800 // significant digits in the divisor.
12801 if (!Subtarget->useReciprocalEst())
12804 EVT VT = Op.getValueType();
12806 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
12807 // TODO: Add support for AVX512 (v16f32).
12808 // It is likely not profitable to do this for f64 because a double-precision
12809 // reciprocal estimate with refinement on x86 prior to FMA requires
12810 // 15 instructions: convert to single, rcpss, convert back to double, refine
12811 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
12812 // along with FMA, this could be a throughput win.
12813 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
12814 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
12815 RefinementSteps = ReciprocalEstimateRefinementSteps;
12816 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
12821 /// If we have at least two divisions that use the same divisor, convert to
12822 /// multplication by a reciprocal. This may need to be adjusted for a given
12823 /// CPU if a division's cost is not at least twice the cost of a multiplication.
12824 /// This is because we still need one division to calculate the reciprocal and
12825 /// then we need two multiplies by that reciprocal as replacements for the
12826 /// original divisions.
12827 bool X86TargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
12828 return NumUsers > 1;
12831 static bool isAllOnes(SDValue V) {
12832 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
12833 return C && C->isAllOnesValue();
12836 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
12837 /// if it's possible.
12838 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
12839 SDLoc dl, SelectionDAG &DAG) const {
12840 SDValue Op0 = And.getOperand(0);
12841 SDValue Op1 = And.getOperand(1);
12842 if (Op0.getOpcode() == ISD::TRUNCATE)
12843 Op0 = Op0.getOperand(0);
12844 if (Op1.getOpcode() == ISD::TRUNCATE)
12845 Op1 = Op1.getOperand(0);
12848 if (Op1.getOpcode() == ISD::SHL)
12849 std::swap(Op0, Op1);
12850 if (Op0.getOpcode() == ISD::SHL) {
12851 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
12852 if (And00C->getZExtValue() == 1) {
12853 // If we looked past a truncate, check that it's only truncating away
12855 unsigned BitWidth = Op0.getValueSizeInBits();
12856 unsigned AndBitWidth = And.getValueSizeInBits();
12857 if (BitWidth > AndBitWidth) {
12859 DAG.computeKnownBits(Op0, Zeros, Ones);
12860 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
12864 RHS = Op0.getOperand(1);
12866 } else if (Op1.getOpcode() == ISD::Constant) {
12867 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
12868 uint64_t AndRHSVal = AndRHS->getZExtValue();
12869 SDValue AndLHS = Op0;
12871 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
12872 LHS = AndLHS.getOperand(0);
12873 RHS = AndLHS.getOperand(1);
12876 // Use BT if the immediate can't be encoded in a TEST instruction.
12877 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
12879 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
12883 if (LHS.getNode()) {
12884 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
12885 // instruction. Since the shift amount is in-range-or-undefined, we know
12886 // that doing a bittest on the i32 value is ok. We extend to i32 because
12887 // the encoding for the i16 version is larger than the i32 version.
12888 // Also promote i16 to i32 for performance / code size reason.
12889 if (LHS.getValueType() == MVT::i8 ||
12890 LHS.getValueType() == MVT::i16)
12891 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
12893 // If the operand types disagree, extend the shift amount to match. Since
12894 // BT ignores high bits (like shifts) we can use anyextend.
12895 if (LHS.getValueType() != RHS.getValueType())
12896 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
12898 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
12899 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
12900 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12901 DAG.getConstant(Cond, MVT::i8), BT);
12907 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
12909 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
12914 // SSE Condition code mapping:
12923 switch (SetCCOpcode) {
12924 default: llvm_unreachable("Unexpected SETCC condition");
12926 case ISD::SETEQ: SSECC = 0; break;
12928 case ISD::SETGT: Swap = true; // Fallthrough
12930 case ISD::SETOLT: SSECC = 1; break;
12932 case ISD::SETGE: Swap = true; // Fallthrough
12934 case ISD::SETOLE: SSECC = 2; break;
12935 case ISD::SETUO: SSECC = 3; break;
12937 case ISD::SETNE: SSECC = 4; break;
12938 case ISD::SETULE: Swap = true; // Fallthrough
12939 case ISD::SETUGE: SSECC = 5; break;
12940 case ISD::SETULT: Swap = true; // Fallthrough
12941 case ISD::SETUGT: SSECC = 6; break;
12942 case ISD::SETO: SSECC = 7; break;
12944 case ISD::SETONE: SSECC = 8; break;
12947 std::swap(Op0, Op1);
12952 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
12953 // ones, and then concatenate the result back.
12954 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
12955 MVT VT = Op.getSimpleValueType();
12957 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
12958 "Unsupported value type for operation");
12960 unsigned NumElems = VT.getVectorNumElements();
12962 SDValue CC = Op.getOperand(2);
12964 // Extract the LHS vectors
12965 SDValue LHS = Op.getOperand(0);
12966 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12967 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12969 // Extract the RHS vectors
12970 SDValue RHS = Op.getOperand(1);
12971 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
12972 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
12974 // Issue the operation on the smaller types and concatenate the result back
12975 MVT EltVT = VT.getVectorElementType();
12976 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12977 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
12978 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
12979 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
12982 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
12983 const X86Subtarget *Subtarget) {
12984 SDValue Op0 = Op.getOperand(0);
12985 SDValue Op1 = Op.getOperand(1);
12986 SDValue CC = Op.getOperand(2);
12987 MVT VT = Op.getSimpleValueType();
12990 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
12991 Op.getValueType().getScalarType() == MVT::i1 &&
12992 "Cannot set masked compare for this operation");
12994 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
12996 bool Unsigned = false;
12999 switch (SetCCOpcode) {
13000 default: llvm_unreachable("Unexpected SETCC condition");
13001 case ISD::SETNE: SSECC = 4; break;
13002 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
13003 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
13004 case ISD::SETLT: Swap = true; //fall-through
13005 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
13006 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
13007 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
13008 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
13009 case ISD::SETULE: Unsigned = true; //fall-through
13010 case ISD::SETLE: SSECC = 2; break;
13014 std::swap(Op0, Op1);
13016 return DAG.getNode(Opc, dl, VT, Op0, Op1);
13017 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
13018 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13019 DAG.getConstant(SSECC, MVT::i8));
13022 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
13023 /// operand \p Op1. If non-trivial (for example because it's not constant)
13024 /// return an empty value.
13025 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
13027 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
13031 MVT VT = Op1.getSimpleValueType();
13032 MVT EVT = VT.getVectorElementType();
13033 unsigned n = VT.getVectorNumElements();
13034 SmallVector<SDValue, 8> ULTOp1;
13036 for (unsigned i = 0; i < n; ++i) {
13037 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
13038 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
13041 // Avoid underflow.
13042 APInt Val = Elt->getAPIntValue();
13046 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
13049 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
13052 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
13053 SelectionDAG &DAG) {
13054 SDValue Op0 = Op.getOperand(0);
13055 SDValue Op1 = Op.getOperand(1);
13056 SDValue CC = Op.getOperand(2);
13057 MVT VT = Op.getSimpleValueType();
13058 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13059 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
13064 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
13065 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
13068 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
13069 unsigned Opc = X86ISD::CMPP;
13070 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
13071 assert(VT.getVectorNumElements() <= 16);
13072 Opc = X86ISD::CMPM;
13074 // In the two special cases we can't handle, emit two comparisons.
13077 unsigned CombineOpc;
13078 if (SetCCOpcode == ISD::SETUEQ) {
13079 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
13081 assert(SetCCOpcode == ISD::SETONE);
13082 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
13085 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13086 DAG.getConstant(CC0, MVT::i8));
13087 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13088 DAG.getConstant(CC1, MVT::i8));
13089 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
13091 // Handle all other FP comparisons here.
13092 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13093 DAG.getConstant(SSECC, MVT::i8));
13096 // Break 256-bit integer vector compare into smaller ones.
13097 if (VT.is256BitVector() && !Subtarget->hasInt256())
13098 return Lower256IntVSETCC(Op, DAG);
13100 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
13101 EVT OpVT = Op1.getValueType();
13102 if (Subtarget->hasAVX512()) {
13103 if (Op1.getValueType().is512BitVector() ||
13104 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
13105 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
13106 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
13108 // In AVX-512 architecture setcc returns mask with i1 elements,
13109 // But there is no compare instruction for i8 and i16 elements in KNL.
13110 // We are not talking about 512-bit operands in this case, these
13111 // types are illegal.
13113 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
13114 OpVT.getVectorElementType().getSizeInBits() >= 8))
13115 return DAG.getNode(ISD::TRUNCATE, dl, VT,
13116 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
13119 // We are handling one of the integer comparisons here. Since SSE only has
13120 // GT and EQ comparisons for integer, swapping operands and multiple
13121 // operations may be required for some comparisons.
13123 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
13124 bool Subus = false;
13126 switch (SetCCOpcode) {
13127 default: llvm_unreachable("Unexpected SETCC condition");
13128 case ISD::SETNE: Invert = true;
13129 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
13130 case ISD::SETLT: Swap = true;
13131 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
13132 case ISD::SETGE: Swap = true;
13133 case ISD::SETLE: Opc = X86ISD::PCMPGT;
13134 Invert = true; break;
13135 case ISD::SETULT: Swap = true;
13136 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
13137 FlipSigns = true; break;
13138 case ISD::SETUGE: Swap = true;
13139 case ISD::SETULE: Opc = X86ISD::PCMPGT;
13140 FlipSigns = true; Invert = true; break;
13143 // Special case: Use min/max operations for SETULE/SETUGE
13144 MVT VET = VT.getVectorElementType();
13146 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
13147 || (Subtarget->hasSSE2() && (VET == MVT::i8));
13150 switch (SetCCOpcode) {
13152 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
13153 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
13156 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
13159 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
13160 if (!MinMax && hasSubus) {
13161 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
13163 // t = psubus Op0, Op1
13164 // pcmpeq t, <0..0>
13165 switch (SetCCOpcode) {
13167 case ISD::SETULT: {
13168 // If the comparison is against a constant we can turn this into a
13169 // setule. With psubus, setule does not require a swap. This is
13170 // beneficial because the constant in the register is no longer
13171 // destructed as the destination so it can be hoisted out of a loop.
13172 // Only do this pre-AVX since vpcmp* is no longer destructive.
13173 if (Subtarget->hasAVX())
13175 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
13176 if (ULEOp1.getNode()) {
13178 Subus = true; Invert = false; Swap = false;
13182 // Psubus is better than flip-sign because it requires no inversion.
13183 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
13184 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
13188 Opc = X86ISD::SUBUS;
13194 std::swap(Op0, Op1);
13196 // Check that the operation in question is available (most are plain SSE2,
13197 // but PCMPGTQ and PCMPEQQ have different requirements).
13198 if (VT == MVT::v2i64) {
13199 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
13200 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
13202 // First cast everything to the right type.
13203 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13204 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13206 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13207 // bits of the inputs before performing those operations. The lower
13208 // compare is always unsigned.
13211 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
13213 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
13214 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
13215 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
13216 Sign, Zero, Sign, Zero);
13218 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
13219 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
13221 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
13222 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
13223 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
13225 // Create masks for only the low parts/high parts of the 64 bit integers.
13226 static const int MaskHi[] = { 1, 1, 3, 3 };
13227 static const int MaskLo[] = { 0, 0, 2, 2 };
13228 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
13229 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
13230 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
13232 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
13233 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
13236 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13238 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13241 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
13242 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
13243 // pcmpeqd + pshufd + pand.
13244 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
13246 // First cast everything to the right type.
13247 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
13248 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
13251 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
13253 // Make sure the lower and upper halves are both all-ones.
13254 static const int Mask[] = { 1, 0, 3, 2 };
13255 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
13256 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
13259 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13261 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
13265 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13266 // bits of the inputs before performing those operations.
13268 EVT EltVT = VT.getVectorElementType();
13269 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
13270 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
13271 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
13274 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
13276 // If the logical-not of the result is required, perform that now.
13278 Result = DAG.getNOT(dl, Result, VT);
13281 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
13284 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
13285 getZeroVector(VT, Subtarget, DAG, dl));
13290 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
13292 MVT VT = Op.getSimpleValueType();
13294 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
13296 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
13297 && "SetCC type must be 8-bit or 1-bit integer");
13298 SDValue Op0 = Op.getOperand(0);
13299 SDValue Op1 = Op.getOperand(1);
13301 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
13303 // Optimize to BT if possible.
13304 // Lower (X & (1 << N)) == 0 to BT(X, N).
13305 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
13306 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
13307 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
13308 Op1.getOpcode() == ISD::Constant &&
13309 cast<ConstantSDNode>(Op1)->isNullValue() &&
13310 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13311 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
13312 if (NewSetCC.getNode()) {
13314 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
13319 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
13321 if (Op1.getOpcode() == ISD::Constant &&
13322 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
13323 cast<ConstantSDNode>(Op1)->isNullValue()) &&
13324 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13326 // If the input is a setcc, then reuse the input setcc or use a new one with
13327 // the inverted condition.
13328 if (Op0.getOpcode() == X86ISD::SETCC) {
13329 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
13330 bool Invert = (CC == ISD::SETNE) ^
13331 cast<ConstantSDNode>(Op1)->isNullValue();
13335 CCode = X86::GetOppositeBranchCondition(CCode);
13336 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13337 DAG.getConstant(CCode, MVT::i8),
13338 Op0.getOperand(1));
13340 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13344 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
13345 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
13346 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13348 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
13349 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
13352 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
13353 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
13354 if (X86CC == X86::COND_INVALID)
13357 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
13358 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
13359 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13360 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
13362 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13366 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
13367 static bool isX86LogicalCmp(SDValue Op) {
13368 unsigned Opc = Op.getNode()->getOpcode();
13369 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
13370 Opc == X86ISD::SAHF)
13372 if (Op.getResNo() == 1 &&
13373 (Opc == X86ISD::ADD ||
13374 Opc == X86ISD::SUB ||
13375 Opc == X86ISD::ADC ||
13376 Opc == X86ISD::SBB ||
13377 Opc == X86ISD::SMUL ||
13378 Opc == X86ISD::UMUL ||
13379 Opc == X86ISD::INC ||
13380 Opc == X86ISD::DEC ||
13381 Opc == X86ISD::OR ||
13382 Opc == X86ISD::XOR ||
13383 Opc == X86ISD::AND))
13386 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
13392 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
13393 if (V.getOpcode() != ISD::TRUNCATE)
13396 SDValue VOp0 = V.getOperand(0);
13397 unsigned InBits = VOp0.getValueSizeInBits();
13398 unsigned Bits = V.getValueSizeInBits();
13399 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
13402 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
13403 bool addTest = true;
13404 SDValue Cond = Op.getOperand(0);
13405 SDValue Op1 = Op.getOperand(1);
13406 SDValue Op2 = Op.getOperand(2);
13408 EVT VT = Op1.getValueType();
13411 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
13412 // are available or VBLENDV if AVX is available.
13413 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
13414 if (Cond.getOpcode() == ISD::SETCC &&
13415 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
13416 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
13417 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
13418 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
13419 int SSECC = translateX86FSETCC(
13420 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
13423 if (Subtarget->hasAVX512()) {
13424 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
13425 DAG.getConstant(SSECC, MVT::i8));
13426 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
13429 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
13430 DAG.getConstant(SSECC, MVT::i8));
13432 // If we have AVX, we can use a variable vector select (VBLENDV) instead
13433 // of 3 logic instructions for size savings and potentially speed.
13434 // Unfortunately, there is no scalar form of VBLENDV.
13436 // If either operand is a constant, don't try this. We can expect to
13437 // optimize away at least one of the logic instructions later in that
13438 // case, so that sequence would be faster than a variable blend.
13440 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
13441 // uses XMM0 as the selection register. That may need just as many
13442 // instructions as the AND/ANDN/OR sequence due to register moves, so
13445 if (Subtarget->hasAVX() &&
13446 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
13448 // Convert to vectors, do a VSELECT, and convert back to scalar.
13449 // All of the conversions should be optimized away.
13451 EVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
13452 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
13453 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
13454 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
13456 EVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
13457 VCmp = DAG.getNode(ISD::BITCAST, DL, VCmpVT, VCmp);
13459 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
13461 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
13462 VSel, DAG.getIntPtrConstant(0));
13464 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
13465 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
13466 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
13470 if (Cond.getOpcode() == ISD::SETCC) {
13471 SDValue NewCond = LowerSETCC(Cond, DAG);
13472 if (NewCond.getNode())
13476 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
13477 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
13478 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
13479 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
13480 if (Cond.getOpcode() == X86ISD::SETCC &&
13481 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
13482 isZero(Cond.getOperand(1).getOperand(1))) {
13483 SDValue Cmp = Cond.getOperand(1);
13485 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
13487 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
13488 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
13489 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
13491 SDValue CmpOp0 = Cmp.getOperand(0);
13492 // Apply further optimizations for special cases
13493 // (select (x != 0), -1, 0) -> neg & sbb
13494 // (select (x == 0), 0, -1) -> neg & sbb
13495 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
13496 if (YC->isNullValue() &&
13497 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
13498 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
13499 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
13500 DAG.getConstant(0, CmpOp0.getValueType()),
13502 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13503 DAG.getConstant(X86::COND_B, MVT::i8),
13504 SDValue(Neg.getNode(), 1));
13508 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
13509 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
13510 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13512 SDValue Res = // Res = 0 or -1.
13513 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13514 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
13516 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
13517 Res = DAG.getNOT(DL, Res, Res.getValueType());
13519 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
13520 if (!N2C || !N2C->isNullValue())
13521 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
13526 // Look past (and (setcc_carry (cmp ...)), 1).
13527 if (Cond.getOpcode() == ISD::AND &&
13528 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
13529 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
13530 if (C && C->getAPIntValue() == 1)
13531 Cond = Cond.getOperand(0);
13534 // If condition flag is set by a X86ISD::CMP, then use it as the condition
13535 // setting operand in place of the X86ISD::SETCC.
13536 unsigned CondOpcode = Cond.getOpcode();
13537 if (CondOpcode == X86ISD::SETCC ||
13538 CondOpcode == X86ISD::SETCC_CARRY) {
13539 CC = Cond.getOperand(0);
13541 SDValue Cmp = Cond.getOperand(1);
13542 unsigned Opc = Cmp.getOpcode();
13543 MVT VT = Op.getSimpleValueType();
13545 bool IllegalFPCMov = false;
13546 if (VT.isFloatingPoint() && !VT.isVector() &&
13547 !isScalarFPTypeInSSEReg(VT)) // FPStack?
13548 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
13550 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
13551 Opc == X86ISD::BT) { // FIXME
13555 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
13556 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
13557 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
13558 Cond.getOperand(0).getValueType() != MVT::i8)) {
13559 SDValue LHS = Cond.getOperand(0);
13560 SDValue RHS = Cond.getOperand(1);
13561 unsigned X86Opcode;
13564 switch (CondOpcode) {
13565 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
13566 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
13567 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
13568 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
13569 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
13570 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
13571 default: llvm_unreachable("unexpected overflowing operator");
13573 if (CondOpcode == ISD::UMULO)
13574 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
13577 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
13579 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
13581 if (CondOpcode == ISD::UMULO)
13582 Cond = X86Op.getValue(2);
13584 Cond = X86Op.getValue(1);
13586 CC = DAG.getConstant(X86Cond, MVT::i8);
13591 // Look pass the truncate if the high bits are known zero.
13592 if (isTruncWithZeroHighBitsInput(Cond, DAG))
13593 Cond = Cond.getOperand(0);
13595 // We know the result of AND is compared against zero. Try to match
13597 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
13598 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
13599 if (NewSetCC.getNode()) {
13600 CC = NewSetCC.getOperand(0);
13601 Cond = NewSetCC.getOperand(1);
13608 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13609 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
13612 // a < b ? -1 : 0 -> RES = ~setcc_carry
13613 // a < b ? 0 : -1 -> RES = setcc_carry
13614 // a >= b ? -1 : 0 -> RES = setcc_carry
13615 // a >= b ? 0 : -1 -> RES = ~setcc_carry
13616 if (Cond.getOpcode() == X86ISD::SUB) {
13617 Cond = ConvertCmpIfNecessary(Cond, DAG);
13618 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
13620 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
13621 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
13622 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13623 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
13624 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
13625 return DAG.getNOT(DL, Res, Res.getValueType());
13630 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
13631 // widen the cmov and push the truncate through. This avoids introducing a new
13632 // branch during isel and doesn't add any extensions.
13633 if (Op.getValueType() == MVT::i8 &&
13634 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
13635 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
13636 if (T1.getValueType() == T2.getValueType() &&
13637 // Blacklist CopyFromReg to avoid partial register stalls.
13638 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
13639 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
13640 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
13641 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
13645 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
13646 // condition is true.
13647 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
13648 SDValue Ops[] = { Op2, Op1, CC, Cond };
13649 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
13652 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
13653 SelectionDAG &DAG) {
13654 MVT VT = Op->getSimpleValueType(0);
13655 SDValue In = Op->getOperand(0);
13656 MVT InVT = In.getSimpleValueType();
13657 MVT VTElt = VT.getVectorElementType();
13658 MVT InVTElt = InVT.getVectorElementType();
13662 if ((InVTElt == MVT::i1) &&
13663 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
13664 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
13666 ((Subtarget->hasBWI() && VT.is512BitVector() &&
13667 VTElt.getSizeInBits() <= 16)) ||
13669 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
13670 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
13672 ((Subtarget->hasDQI() && VT.is512BitVector() &&
13673 VTElt.getSizeInBits() >= 32))))
13674 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13676 unsigned int NumElts = VT.getVectorNumElements();
13678 if (NumElts != 8 && NumElts != 16)
13681 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
13682 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
13683 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
13684 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13687 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13688 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13690 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
13691 Constant *C = ConstantInt::get(*DAG.getContext(),
13692 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
13694 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13695 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13696 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
13697 MachinePointerInfo::getConstantPool(),
13698 false, false, false, Alignment);
13699 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
13700 if (VT.is512BitVector())
13702 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
13705 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13706 SelectionDAG &DAG) {
13707 MVT VT = Op->getSimpleValueType(0);
13708 SDValue In = Op->getOperand(0);
13709 MVT InVT = In.getSimpleValueType();
13712 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
13713 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
13715 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
13716 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
13717 (VT != MVT::v16i16 || InVT != MVT::v16i8))
13720 if (Subtarget->hasInt256())
13721 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13723 // Optimize vectors in AVX mode
13724 // Sign extend v8i16 to v8i32 and
13727 // Divide input vector into two parts
13728 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
13729 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
13730 // concat the vectors to original VT
13732 unsigned NumElems = InVT.getVectorNumElements();
13733 SDValue Undef = DAG.getUNDEF(InVT);
13735 SmallVector<int,8> ShufMask1(NumElems, -1);
13736 for (unsigned i = 0; i != NumElems/2; ++i)
13739 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
13741 SmallVector<int,8> ShufMask2(NumElems, -1);
13742 for (unsigned i = 0; i != NumElems/2; ++i)
13743 ShufMask2[i] = i + NumElems/2;
13745 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
13747 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
13748 VT.getVectorNumElements()/2);
13750 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
13751 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
13753 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13756 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
13757 // may emit an illegal shuffle but the expansion is still better than scalar
13758 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
13759 // we'll emit a shuffle and a arithmetic shift.
13760 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
13761 // TODO: It is possible to support ZExt by zeroing the undef values during
13762 // the shuffle phase or after the shuffle.
13763 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
13764 SelectionDAG &DAG) {
13765 MVT RegVT = Op.getSimpleValueType();
13766 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
13767 assert(RegVT.isInteger() &&
13768 "We only custom lower integer vector sext loads.");
13770 // Nothing useful we can do without SSE2 shuffles.
13771 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
13773 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
13775 EVT MemVT = Ld->getMemoryVT();
13776 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13777 unsigned RegSz = RegVT.getSizeInBits();
13779 ISD::LoadExtType Ext = Ld->getExtensionType();
13781 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
13782 && "Only anyext and sext are currently implemented.");
13783 assert(MemVT != RegVT && "Cannot extend to the same type");
13784 assert(MemVT.isVector() && "Must load a vector from memory");
13786 unsigned NumElems = RegVT.getVectorNumElements();
13787 unsigned MemSz = MemVT.getSizeInBits();
13788 assert(RegSz > MemSz && "Register size must be greater than the mem size");
13790 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
13791 // The only way in which we have a legal 256-bit vector result but not the
13792 // integer 256-bit operations needed to directly lower a sextload is if we
13793 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
13794 // a 128-bit vector and a normal sign_extend to 256-bits that should get
13795 // correctly legalized. We do this late to allow the canonical form of
13796 // sextload to persist throughout the rest of the DAG combiner -- it wants
13797 // to fold together any extensions it can, and so will fuse a sign_extend
13798 // of an sextload into a sextload targeting a wider value.
13800 if (MemSz == 128) {
13801 // Just switch this to a normal load.
13802 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
13803 "it must be a legal 128-bit vector "
13805 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
13806 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
13807 Ld->isInvariant(), Ld->getAlignment());
13809 assert(MemSz < 128 &&
13810 "Can't extend a type wider than 128 bits to a 256 bit vector!");
13811 // Do an sext load to a 128-bit vector type. We want to use the same
13812 // number of elements, but elements half as wide. This will end up being
13813 // recursively lowered by this routine, but will succeed as we definitely
13814 // have all the necessary features if we're using AVX1.
13816 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
13817 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
13819 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
13820 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
13821 Ld->isNonTemporal(), Ld->isInvariant(),
13822 Ld->getAlignment());
13825 // Replace chain users with the new chain.
13826 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
13827 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
13829 // Finally, do a normal sign-extend to the desired register.
13830 return DAG.getSExtOrTrunc(Load, dl, RegVT);
13833 // All sizes must be a power of two.
13834 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
13835 "Non-power-of-two elements are not custom lowered!");
13837 // Attempt to load the original value using scalar loads.
13838 // Find the largest scalar type that divides the total loaded size.
13839 MVT SclrLoadTy = MVT::i8;
13840 for (MVT Tp : MVT::integer_valuetypes()) {
13841 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
13846 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
13847 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
13849 SclrLoadTy = MVT::f64;
13851 // Calculate the number of scalar loads that we need to perform
13852 // in order to load our vector from memory.
13853 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
13855 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
13856 "Can only lower sext loads with a single scalar load!");
13858 unsigned loadRegZize = RegSz;
13859 if (Ext == ISD::SEXTLOAD && RegSz == 256)
13862 // Represent our vector as a sequence of elements which are the
13863 // largest scalar that we can load.
13864 EVT LoadUnitVecVT = EVT::getVectorVT(
13865 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
13867 // Represent the data using the same element type that is stored in
13868 // memory. In practice, we ''widen'' MemVT.
13870 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
13871 loadRegZize / MemVT.getScalarType().getSizeInBits());
13873 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
13874 "Invalid vector type");
13876 // We can't shuffle using an illegal type.
13877 assert(TLI.isTypeLegal(WideVecVT) &&
13878 "We only lower types that form legal widened vector types");
13880 SmallVector<SDValue, 8> Chains;
13881 SDValue Ptr = Ld->getBasePtr();
13882 SDValue Increment =
13883 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
13884 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
13886 for (unsigned i = 0; i < NumLoads; ++i) {
13887 // Perform a single load.
13888 SDValue ScalarLoad =
13889 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
13890 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
13891 Ld->getAlignment());
13892 Chains.push_back(ScalarLoad.getValue(1));
13893 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
13894 // another round of DAGCombining.
13896 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
13898 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
13899 ScalarLoad, DAG.getIntPtrConstant(i));
13901 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
13904 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
13906 // Bitcast the loaded value to a vector of the original element type, in
13907 // the size of the target vector type.
13908 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
13909 unsigned SizeRatio = RegSz / MemSz;
13911 if (Ext == ISD::SEXTLOAD) {
13912 // If we have SSE4.1, we can directly emit a VSEXT node.
13913 if (Subtarget->hasSSE41()) {
13914 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
13915 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13919 // Otherwise we'll shuffle the small elements in the high bits of the
13920 // larger type and perform an arithmetic shift. If the shift is not legal
13921 // it's better to scalarize.
13922 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
13923 "We can't implement a sext load without an arithmetic right shift!");
13925 // Redistribute the loaded elements into the different locations.
13926 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
13927 for (unsigned i = 0; i != NumElems; ++i)
13928 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
13930 SDValue Shuff = DAG.getVectorShuffle(
13931 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
13933 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
13935 // Build the arithmetic shift.
13936 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
13937 MemVT.getVectorElementType().getSizeInBits();
13939 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
13941 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13945 // Redistribute the loaded elements into the different locations.
13946 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
13947 for (unsigned i = 0; i != NumElems; ++i)
13948 ShuffleVec[i * SizeRatio] = i;
13950 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
13951 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
13953 // Bitcast to the requested type.
13954 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
13955 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13959 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
13960 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
13961 // from the AND / OR.
13962 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
13963 Opc = Op.getOpcode();
13964 if (Opc != ISD::OR && Opc != ISD::AND)
13966 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
13967 Op.getOperand(0).hasOneUse() &&
13968 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
13969 Op.getOperand(1).hasOneUse());
13972 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
13973 // 1 and that the SETCC node has a single use.
13974 static bool isXor1OfSetCC(SDValue Op) {
13975 if (Op.getOpcode() != ISD::XOR)
13977 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
13978 if (N1C && N1C->getAPIntValue() == 1) {
13979 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
13980 Op.getOperand(0).hasOneUse();
13985 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
13986 bool addTest = true;
13987 SDValue Chain = Op.getOperand(0);
13988 SDValue Cond = Op.getOperand(1);
13989 SDValue Dest = Op.getOperand(2);
13992 bool Inverted = false;
13994 if (Cond.getOpcode() == ISD::SETCC) {
13995 // Check for setcc([su]{add,sub,mul}o == 0).
13996 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
13997 isa<ConstantSDNode>(Cond.getOperand(1)) &&
13998 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
13999 Cond.getOperand(0).getResNo() == 1 &&
14000 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
14001 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
14002 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
14003 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
14004 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
14005 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
14007 Cond = Cond.getOperand(0);
14009 SDValue NewCond = LowerSETCC(Cond, DAG);
14010 if (NewCond.getNode())
14015 // FIXME: LowerXALUO doesn't handle these!!
14016 else if (Cond.getOpcode() == X86ISD::ADD ||
14017 Cond.getOpcode() == X86ISD::SUB ||
14018 Cond.getOpcode() == X86ISD::SMUL ||
14019 Cond.getOpcode() == X86ISD::UMUL)
14020 Cond = LowerXALUO(Cond, DAG);
14023 // Look pass (and (setcc_carry (cmp ...)), 1).
14024 if (Cond.getOpcode() == ISD::AND &&
14025 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14026 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14027 if (C && C->getAPIntValue() == 1)
14028 Cond = Cond.getOperand(0);
14031 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14032 // setting operand in place of the X86ISD::SETCC.
14033 unsigned CondOpcode = Cond.getOpcode();
14034 if (CondOpcode == X86ISD::SETCC ||
14035 CondOpcode == X86ISD::SETCC_CARRY) {
14036 CC = Cond.getOperand(0);
14038 SDValue Cmp = Cond.getOperand(1);
14039 unsigned Opc = Cmp.getOpcode();
14040 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
14041 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
14045 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
14049 // These can only come from an arithmetic instruction with overflow,
14050 // e.g. SADDO, UADDO.
14051 Cond = Cond.getNode()->getOperand(1);
14057 CondOpcode = Cond.getOpcode();
14058 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14059 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14060 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14061 Cond.getOperand(0).getValueType() != MVT::i8)) {
14062 SDValue LHS = Cond.getOperand(0);
14063 SDValue RHS = Cond.getOperand(1);
14064 unsigned X86Opcode;
14067 // Keep this in sync with LowerXALUO, otherwise we might create redundant
14068 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
14070 switch (CondOpcode) {
14071 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14073 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14075 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
14078 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14079 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14081 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14083 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
14086 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14087 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14088 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14089 default: llvm_unreachable("unexpected overflowing operator");
14092 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
14093 if (CondOpcode == ISD::UMULO)
14094 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14097 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14099 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
14101 if (CondOpcode == ISD::UMULO)
14102 Cond = X86Op.getValue(2);
14104 Cond = X86Op.getValue(1);
14106 CC = DAG.getConstant(X86Cond, MVT::i8);
14110 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
14111 SDValue Cmp = Cond.getOperand(0).getOperand(1);
14112 if (CondOpc == ISD::OR) {
14113 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
14114 // two branches instead of an explicit OR instruction with a
14116 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14117 isX86LogicalCmp(Cmp)) {
14118 CC = Cond.getOperand(0).getOperand(0);
14119 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14120 Chain, Dest, CC, Cmp);
14121 CC = Cond.getOperand(1).getOperand(0);
14125 } else { // ISD::AND
14126 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
14127 // two branches instead of an explicit AND instruction with a
14128 // separate test. However, we only do this if this block doesn't
14129 // have a fall-through edge, because this requires an explicit
14130 // jmp when the condition is false.
14131 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14132 isX86LogicalCmp(Cmp) &&
14133 Op.getNode()->hasOneUse()) {
14134 X86::CondCode CCode =
14135 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14136 CCode = X86::GetOppositeBranchCondition(CCode);
14137 CC = DAG.getConstant(CCode, MVT::i8);
14138 SDNode *User = *Op.getNode()->use_begin();
14139 // Look for an unconditional branch following this conditional branch.
14140 // We need this because we need to reverse the successors in order
14141 // to implement FCMP_OEQ.
14142 if (User->getOpcode() == ISD::BR) {
14143 SDValue FalseBB = User->getOperand(1);
14145 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14146 assert(NewBR == User);
14150 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14151 Chain, Dest, CC, Cmp);
14152 X86::CondCode CCode =
14153 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
14154 CCode = X86::GetOppositeBranchCondition(CCode);
14155 CC = DAG.getConstant(CCode, MVT::i8);
14161 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
14162 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
14163 // It should be transformed during dag combiner except when the condition
14164 // is set by a arithmetics with overflow node.
14165 X86::CondCode CCode =
14166 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14167 CCode = X86::GetOppositeBranchCondition(CCode);
14168 CC = DAG.getConstant(CCode, MVT::i8);
14169 Cond = Cond.getOperand(0).getOperand(1);
14171 } else if (Cond.getOpcode() == ISD::SETCC &&
14172 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
14173 // For FCMP_OEQ, we can emit
14174 // two branches instead of an explicit AND instruction with a
14175 // separate test. However, we only do this if this block doesn't
14176 // have a fall-through edge, because this requires an explicit
14177 // jmp when the condition is false.
14178 if (Op.getNode()->hasOneUse()) {
14179 SDNode *User = *Op.getNode()->use_begin();
14180 // Look for an unconditional branch following this conditional branch.
14181 // We need this because we need to reverse the successors in order
14182 // to implement FCMP_OEQ.
14183 if (User->getOpcode() == ISD::BR) {
14184 SDValue FalseBB = User->getOperand(1);
14186 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14187 assert(NewBR == User);
14191 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14192 Cond.getOperand(0), Cond.getOperand(1));
14193 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14194 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14195 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14196 Chain, Dest, CC, Cmp);
14197 CC = DAG.getConstant(X86::COND_P, MVT::i8);
14202 } else if (Cond.getOpcode() == ISD::SETCC &&
14203 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
14204 // For FCMP_UNE, we can emit
14205 // two branches instead of an explicit AND instruction with a
14206 // separate test. However, we only do this if this block doesn't
14207 // have a fall-through edge, because this requires an explicit
14208 // jmp when the condition is false.
14209 if (Op.getNode()->hasOneUse()) {
14210 SDNode *User = *Op.getNode()->use_begin();
14211 // Look for an unconditional branch following this conditional branch.
14212 // We need this because we need to reverse the successors in order
14213 // to implement FCMP_UNE.
14214 if (User->getOpcode() == ISD::BR) {
14215 SDValue FalseBB = User->getOperand(1);
14217 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14218 assert(NewBR == User);
14221 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14222 Cond.getOperand(0), Cond.getOperand(1));
14223 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14224 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
14225 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14226 Chain, Dest, CC, Cmp);
14227 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
14237 // Look pass the truncate if the high bits are known zero.
14238 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14239 Cond = Cond.getOperand(0);
14241 // We know the result of AND is compared against zero. Try to match
14243 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14244 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
14245 if (NewSetCC.getNode()) {
14246 CC = NewSetCC.getOperand(0);
14247 Cond = NewSetCC.getOperand(1);
14254 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
14255 CC = DAG.getConstant(X86Cond, MVT::i8);
14256 Cond = EmitTest(Cond, X86Cond, dl, DAG);
14258 Cond = ConvertCmpIfNecessary(Cond, DAG);
14259 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14260 Chain, Dest, CC, Cond);
14263 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
14264 // Calls to _alloca are needed to probe the stack when allocating more than 4k
14265 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
14266 // that the guard pages used by the OS virtual memory manager are allocated in
14267 // correct sequence.
14269 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
14270 SelectionDAG &DAG) const {
14271 MachineFunction &MF = DAG.getMachineFunction();
14272 bool SplitStack = MF.shouldSplitStack();
14273 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
14278 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14279 SDNode* Node = Op.getNode();
14281 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
14282 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
14283 " not tell us which reg is the stack pointer!");
14284 EVT VT = Node->getValueType(0);
14285 SDValue Tmp1 = SDValue(Node, 0);
14286 SDValue Tmp2 = SDValue(Node, 1);
14287 SDValue Tmp3 = Node->getOperand(2);
14288 SDValue Chain = Tmp1.getOperand(0);
14290 // Chain the dynamic stack allocation so that it doesn't modify the stack
14291 // pointer when other instructions are using the stack.
14292 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
14295 SDValue Size = Tmp2.getOperand(1);
14296 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
14297 Chain = SP.getValue(1);
14298 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
14299 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
14300 unsigned StackAlign = TFI.getStackAlignment();
14301 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
14302 if (Align > StackAlign)
14303 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
14304 DAG.getConstant(-(uint64_t)Align, VT));
14305 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
14307 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
14308 DAG.getIntPtrConstant(0, true), SDValue(),
14311 SDValue Ops[2] = { Tmp1, Tmp2 };
14312 return DAG.getMergeValues(Ops, dl);
14316 SDValue Chain = Op.getOperand(0);
14317 SDValue Size = Op.getOperand(1);
14318 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
14319 EVT VT = Op.getNode()->getValueType(0);
14321 bool Is64Bit = Subtarget->is64Bit();
14322 EVT SPTy = getPointerTy();
14325 MachineRegisterInfo &MRI = MF.getRegInfo();
14328 // The 64 bit implementation of segmented stacks needs to clobber both r10
14329 // r11. This makes it impossible to use it along with nested parameters.
14330 const Function *F = MF.getFunction();
14332 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
14334 if (I->hasNestAttr())
14335 report_fatal_error("Cannot use segmented stacks with functions that "
14336 "have nested arguments.");
14339 const TargetRegisterClass *AddrRegClass =
14340 getRegClassFor(getPointerTy());
14341 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
14342 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
14343 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
14344 DAG.getRegister(Vreg, SPTy));
14345 SDValue Ops1[2] = { Value, Chain };
14346 return DAG.getMergeValues(Ops1, dl);
14349 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
14351 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
14352 Flag = Chain.getValue(1);
14353 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
14355 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
14357 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
14358 unsigned SPReg = RegInfo->getStackRegister();
14359 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
14360 Chain = SP.getValue(1);
14363 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
14364 DAG.getConstant(-(uint64_t)Align, VT));
14365 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
14368 SDValue Ops1[2] = { SP, Chain };
14369 return DAG.getMergeValues(Ops1, dl);
14373 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
14374 MachineFunction &MF = DAG.getMachineFunction();
14375 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
14377 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14380 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
14381 // vastart just stores the address of the VarArgsFrameIndex slot into the
14382 // memory location argument.
14383 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14385 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
14386 MachinePointerInfo(SV), false, false, 0);
14390 // gp_offset (0 - 6 * 8)
14391 // fp_offset (48 - 48 + 8 * 16)
14392 // overflow_arg_area (point to parameters coming in memory).
14394 SmallVector<SDValue, 8> MemOps;
14395 SDValue FIN = Op.getOperand(1);
14397 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
14398 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
14400 FIN, MachinePointerInfo(SV), false, false, 0);
14401 MemOps.push_back(Store);
14404 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14405 FIN, DAG.getIntPtrConstant(4));
14406 Store = DAG.getStore(Op.getOperand(0), DL,
14407 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
14409 FIN, MachinePointerInfo(SV, 4), false, false, 0);
14410 MemOps.push_back(Store);
14412 // Store ptr to overflow_arg_area
14413 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14414 FIN, DAG.getIntPtrConstant(4));
14415 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14417 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
14418 MachinePointerInfo(SV, 8),
14420 MemOps.push_back(Store);
14422 // Store ptr to reg_save_area.
14423 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14424 FIN, DAG.getIntPtrConstant(8));
14425 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
14427 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
14428 MachinePointerInfo(SV, 16), false, false, 0);
14429 MemOps.push_back(Store);
14430 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
14433 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
14434 assert(Subtarget->is64Bit() &&
14435 "LowerVAARG only handles 64-bit va_arg!");
14436 assert((Subtarget->isTargetLinux() ||
14437 Subtarget->isTargetDarwin()) &&
14438 "Unhandled target in LowerVAARG");
14439 assert(Op.getNode()->getNumOperands() == 4);
14440 SDValue Chain = Op.getOperand(0);
14441 SDValue SrcPtr = Op.getOperand(1);
14442 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14443 unsigned Align = Op.getConstantOperandVal(3);
14446 EVT ArgVT = Op.getNode()->getValueType(0);
14447 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
14448 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
14451 // Decide which area this value should be read from.
14452 // TODO: Implement the AMD64 ABI in its entirety. This simple
14453 // selection mechanism works only for the basic types.
14454 if (ArgVT == MVT::f80) {
14455 llvm_unreachable("va_arg for f80 not yet implemented");
14456 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
14457 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
14458 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
14459 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
14461 llvm_unreachable("Unhandled argument type in LowerVAARG");
14464 if (ArgMode == 2) {
14465 // Sanity Check: Make sure using fp_offset makes sense.
14466 assert(!DAG.getTarget().Options.UseSoftFloat &&
14467 !(DAG.getMachineFunction().getFunction()->hasFnAttribute(
14468 Attribute::NoImplicitFloat)) &&
14469 Subtarget->hasSSE1());
14472 // Insert VAARG_64 node into the DAG
14473 // VAARG_64 returns two values: Variable Argument Address, Chain
14474 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, MVT::i32),
14475 DAG.getConstant(ArgMode, MVT::i8),
14476 DAG.getConstant(Align, MVT::i32)};
14477 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
14478 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
14479 VTs, InstOps, MVT::i64,
14480 MachinePointerInfo(SV),
14482 /*Volatile=*/false,
14484 /*WriteMem=*/true);
14485 Chain = VAARG.getValue(1);
14487 // Load the next argument and return it
14488 return DAG.getLoad(ArgVT, dl,
14491 MachinePointerInfo(),
14492 false, false, false, 0);
14495 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
14496 SelectionDAG &DAG) {
14497 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
14498 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
14499 SDValue Chain = Op.getOperand(0);
14500 SDValue DstPtr = Op.getOperand(1);
14501 SDValue SrcPtr = Op.getOperand(2);
14502 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
14503 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
14506 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
14507 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
14509 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
14512 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
14513 // amount is a constant. Takes immediate version of shift as input.
14514 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
14515 SDValue SrcOp, uint64_t ShiftAmt,
14516 SelectionDAG &DAG) {
14517 MVT ElementType = VT.getVectorElementType();
14519 // Fold this packed shift into its first operand if ShiftAmt is 0.
14523 // Check for ShiftAmt >= element width
14524 if (ShiftAmt >= ElementType.getSizeInBits()) {
14525 if (Opc == X86ISD::VSRAI)
14526 ShiftAmt = ElementType.getSizeInBits() - 1;
14528 return DAG.getConstant(0, VT);
14531 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
14532 && "Unknown target vector shift-by-constant node");
14534 // Fold this packed vector shift into a build vector if SrcOp is a
14535 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
14536 if (VT == SrcOp.getSimpleValueType() &&
14537 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
14538 SmallVector<SDValue, 8> Elts;
14539 unsigned NumElts = SrcOp->getNumOperands();
14540 ConstantSDNode *ND;
14543 default: llvm_unreachable(nullptr);
14544 case X86ISD::VSHLI:
14545 for (unsigned i=0; i!=NumElts; ++i) {
14546 SDValue CurrentOp = SrcOp->getOperand(i);
14547 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14548 Elts.push_back(CurrentOp);
14551 ND = cast<ConstantSDNode>(CurrentOp);
14552 const APInt &C = ND->getAPIntValue();
14553 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
14556 case X86ISD::VSRLI:
14557 for (unsigned i=0; i!=NumElts; ++i) {
14558 SDValue CurrentOp = SrcOp->getOperand(i);
14559 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14560 Elts.push_back(CurrentOp);
14563 ND = cast<ConstantSDNode>(CurrentOp);
14564 const APInt &C = ND->getAPIntValue();
14565 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
14568 case X86ISD::VSRAI:
14569 for (unsigned i=0; i!=NumElts; ++i) {
14570 SDValue CurrentOp = SrcOp->getOperand(i);
14571 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14572 Elts.push_back(CurrentOp);
14575 ND = cast<ConstantSDNode>(CurrentOp);
14576 const APInt &C = ND->getAPIntValue();
14577 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
14582 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
14585 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
14588 // getTargetVShiftNode - Handle vector element shifts where the shift amount
14589 // may or may not be a constant. Takes immediate version of shift as input.
14590 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
14591 SDValue SrcOp, SDValue ShAmt,
14592 SelectionDAG &DAG) {
14593 MVT SVT = ShAmt.getSimpleValueType();
14594 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
14596 // Catch shift-by-constant.
14597 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
14598 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
14599 CShAmt->getZExtValue(), DAG);
14601 // Change opcode to non-immediate version
14603 default: llvm_unreachable("Unknown target vector shift node");
14604 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
14605 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
14606 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
14609 const X86Subtarget &Subtarget =
14610 static_cast<const X86Subtarget &>(DAG.getSubtarget());
14611 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
14612 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
14613 // Let the shuffle legalizer expand this shift amount node.
14614 SDValue Op0 = ShAmt.getOperand(0);
14615 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
14616 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
14618 // Need to build a vector containing shift amount.
14619 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
14620 SmallVector<SDValue, 4> ShOps;
14621 ShOps.push_back(ShAmt);
14622 if (SVT == MVT::i32) {
14623 ShOps.push_back(DAG.getConstant(0, SVT));
14624 ShOps.push_back(DAG.getUNDEF(SVT));
14626 ShOps.push_back(DAG.getUNDEF(SVT));
14628 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
14629 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
14632 // The return type has to be a 128-bit type with the same element
14633 // type as the input type.
14634 MVT EltVT = VT.getVectorElementType();
14635 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
14637 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
14638 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
14641 /// \brief Return (and \p Op, \p Mask) for compare instructions or
14642 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
14643 /// necessary casting for \p Mask when lowering masking intrinsics.
14644 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
14645 SDValue PreservedSrc,
14646 const X86Subtarget *Subtarget,
14647 SelectionDAG &DAG) {
14648 EVT VT = Op.getValueType();
14649 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
14650 MVT::i1, VT.getVectorNumElements());
14651 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14652 Mask.getValueType().getSizeInBits());
14655 assert(MaskVT.isSimple() && "invalid mask type");
14657 if (isAllOnes(Mask))
14660 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
14661 // are extracted by EXTRACT_SUBVECTOR.
14662 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
14663 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
14664 DAG.getIntPtrConstant(0));
14666 switch (Op.getOpcode()) {
14668 case X86ISD::PCMPEQM:
14669 case X86ISD::PCMPGTM:
14671 case X86ISD::CMPMU:
14672 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
14674 if (PreservedSrc.getOpcode() == ISD::UNDEF)
14675 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
14676 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
14679 /// \brief Creates an SDNode for a predicated scalar operation.
14680 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
14681 /// The mask is comming as MVT::i8 and it should be truncated
14682 /// to MVT::i1 while lowering masking intrinsics.
14683 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
14684 /// "X86select" instead of "vselect". We just can't create the "vselect" node for
14685 /// a scalar instruction.
14686 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
14687 SDValue PreservedSrc,
14688 const X86Subtarget *Subtarget,
14689 SelectionDAG &DAG) {
14690 if (isAllOnes(Mask))
14693 EVT VT = Op.getValueType();
14695 // The mask should be of type MVT::i1
14696 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
14698 if (PreservedSrc.getOpcode() == ISD::UNDEF)
14699 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
14700 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
14703 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
14704 SelectionDAG &DAG) {
14706 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
14707 EVT VT = Op.getValueType();
14708 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
14710 switch(IntrData->Type) {
14711 case INTR_TYPE_1OP:
14712 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
14713 case INTR_TYPE_2OP:
14714 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
14716 case INTR_TYPE_3OP:
14717 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
14718 Op.getOperand(2), Op.getOperand(3));
14719 case INTR_TYPE_1OP_MASK_RM: {
14720 SDValue Src = Op.getOperand(1);
14721 SDValue Src0 = Op.getOperand(2);
14722 SDValue Mask = Op.getOperand(3);
14723 SDValue RoundingMode = Op.getOperand(4);
14724 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
14726 Mask, Src0, Subtarget, DAG);
14728 case INTR_TYPE_SCALAR_MASK_RM: {
14729 SDValue Src1 = Op.getOperand(1);
14730 SDValue Src2 = Op.getOperand(2);
14731 SDValue Src0 = Op.getOperand(3);
14732 SDValue Mask = Op.getOperand(4);
14733 // There are 2 kinds of intrinsics in this group:
14734 // (1) With supress-all-exceptions (sae) - 6 operands
14735 // (2) With rounding mode and sae - 7 operands.
14736 if (Op.getNumOperands() == 6) {
14737 SDValue Sae = Op.getOperand(5);
14738 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
14740 Mask, Src0, Subtarget, DAG);
14742 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
14743 SDValue RoundingMode = Op.getOperand(5);
14744 SDValue Sae = Op.getOperand(6);
14745 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
14746 RoundingMode, Sae),
14747 Mask, Src0, Subtarget, DAG);
14749 case INTR_TYPE_2OP_MASK: {
14750 SDValue Src1 = Op.getOperand(1);
14751 SDValue Src2 = Op.getOperand(2);
14752 SDValue PassThru = Op.getOperand(3);
14753 SDValue Mask = Op.getOperand(4);
14754 // We specify 2 possible opcodes for intrinsics with rounding modes.
14755 // First, we check if the intrinsic may have non-default rounding mode,
14756 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
14757 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
14758 if (IntrWithRoundingModeOpcode != 0) {
14759 SDValue Rnd = Op.getOperand(5);
14760 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
14761 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
14762 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
14763 dl, Op.getValueType(),
14765 Mask, PassThru, Subtarget, DAG);
14768 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
14770 Mask, PassThru, Subtarget, DAG);
14772 case FMA_OP_MASK: {
14773 SDValue Src1 = Op.getOperand(1);
14774 SDValue Src2 = Op.getOperand(2);
14775 SDValue Src3 = Op.getOperand(3);
14776 SDValue Mask = Op.getOperand(4);
14777 // We specify 2 possible opcodes for intrinsics with rounding modes.
14778 // First, we check if the intrinsic may have non-default rounding mode,
14779 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
14780 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
14781 if (IntrWithRoundingModeOpcode != 0) {
14782 SDValue Rnd = Op.getOperand(5);
14783 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
14784 X86::STATIC_ROUNDING::CUR_DIRECTION)
14785 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
14786 dl, Op.getValueType(),
14787 Src1, Src2, Src3, Rnd),
14788 Mask, Src1, Subtarget, DAG);
14790 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
14791 dl, Op.getValueType(),
14793 Mask, Src1, Subtarget, DAG);
14796 case CMP_MASK_CC: {
14797 // Comparison intrinsics with masks.
14798 // Example of transformation:
14799 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
14800 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
14802 // (v8i1 (insert_subvector undef,
14803 // (v2i1 (and (PCMPEQM %a, %b),
14804 // (extract_subvector
14805 // (v8i1 (bitcast %mask)), 0))), 0))))
14806 EVT VT = Op.getOperand(1).getValueType();
14807 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14808 VT.getVectorNumElements());
14809 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
14810 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14811 Mask.getValueType().getSizeInBits());
14813 if (IntrData->Type == CMP_MASK_CC) {
14814 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
14815 Op.getOperand(2), Op.getOperand(3));
14817 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
14818 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
14821 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
14822 DAG.getTargetConstant(0, MaskVT),
14824 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
14825 DAG.getUNDEF(BitcastVT), CmpMask,
14826 DAG.getIntPtrConstant(0));
14827 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
14829 case COMI: { // Comparison intrinsics
14830 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
14831 SDValue LHS = Op.getOperand(1);
14832 SDValue RHS = Op.getOperand(2);
14833 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
14834 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
14835 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
14836 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14837 DAG.getConstant(X86CC, MVT::i8), Cond);
14838 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14841 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
14842 Op.getOperand(1), Op.getOperand(2), DAG);
14844 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
14845 Op.getSimpleValueType(),
14847 Op.getOperand(2), DAG),
14848 Op.getOperand(4), Op.getOperand(3), Subtarget,
14850 case COMPRESS_EXPAND_IN_REG: {
14851 SDValue Mask = Op.getOperand(3);
14852 SDValue DataToCompress = Op.getOperand(1);
14853 SDValue PassThru = Op.getOperand(2);
14854 if (isAllOnes(Mask)) // return data as is
14855 return Op.getOperand(1);
14856 EVT VT = Op.getValueType();
14857 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14858 VT.getVectorNumElements());
14859 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14860 Mask.getValueType().getSizeInBits());
14862 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
14863 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
14864 DAG.getIntPtrConstant(0));
14866 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToCompress,
14870 SDValue Mask = Op.getOperand(3);
14871 EVT VT = Op.getValueType();
14872 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14873 VT.getVectorNumElements());
14874 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14875 Mask.getValueType().getSizeInBits());
14877 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
14878 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
14879 DAG.getIntPtrConstant(0));
14880 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
14889 default: return SDValue(); // Don't custom lower most intrinsics.
14891 case Intrinsic::x86_avx2_permd:
14892 case Intrinsic::x86_avx2_permps:
14893 // Operands intentionally swapped. Mask is last operand to intrinsic,
14894 // but second operand for node/instruction.
14895 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
14896 Op.getOperand(2), Op.getOperand(1));
14898 case Intrinsic::x86_avx512_mask_valign_q_512:
14899 case Intrinsic::x86_avx512_mask_valign_d_512:
14900 // Vector source operands are swapped.
14901 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
14902 Op.getValueType(), Op.getOperand(2),
14905 Op.getOperand(5), Op.getOperand(4),
14908 // ptest and testp intrinsics. The intrinsic these come from are designed to
14909 // return an integer value, not just an instruction so lower it to the ptest
14910 // or testp pattern and a setcc for the result.
14911 case Intrinsic::x86_sse41_ptestz:
14912 case Intrinsic::x86_sse41_ptestc:
14913 case Intrinsic::x86_sse41_ptestnzc:
14914 case Intrinsic::x86_avx_ptestz_256:
14915 case Intrinsic::x86_avx_ptestc_256:
14916 case Intrinsic::x86_avx_ptestnzc_256:
14917 case Intrinsic::x86_avx_vtestz_ps:
14918 case Intrinsic::x86_avx_vtestc_ps:
14919 case Intrinsic::x86_avx_vtestnzc_ps:
14920 case Intrinsic::x86_avx_vtestz_pd:
14921 case Intrinsic::x86_avx_vtestc_pd:
14922 case Intrinsic::x86_avx_vtestnzc_pd:
14923 case Intrinsic::x86_avx_vtestz_ps_256:
14924 case Intrinsic::x86_avx_vtestc_ps_256:
14925 case Intrinsic::x86_avx_vtestnzc_ps_256:
14926 case Intrinsic::x86_avx_vtestz_pd_256:
14927 case Intrinsic::x86_avx_vtestc_pd_256:
14928 case Intrinsic::x86_avx_vtestnzc_pd_256: {
14929 bool IsTestPacked = false;
14932 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
14933 case Intrinsic::x86_avx_vtestz_ps:
14934 case Intrinsic::x86_avx_vtestz_pd:
14935 case Intrinsic::x86_avx_vtestz_ps_256:
14936 case Intrinsic::x86_avx_vtestz_pd_256:
14937 IsTestPacked = true; // Fallthrough
14938 case Intrinsic::x86_sse41_ptestz:
14939 case Intrinsic::x86_avx_ptestz_256:
14941 X86CC = X86::COND_E;
14943 case Intrinsic::x86_avx_vtestc_ps:
14944 case Intrinsic::x86_avx_vtestc_pd:
14945 case Intrinsic::x86_avx_vtestc_ps_256:
14946 case Intrinsic::x86_avx_vtestc_pd_256:
14947 IsTestPacked = true; // Fallthrough
14948 case Intrinsic::x86_sse41_ptestc:
14949 case Intrinsic::x86_avx_ptestc_256:
14951 X86CC = X86::COND_B;
14953 case Intrinsic::x86_avx_vtestnzc_ps:
14954 case Intrinsic::x86_avx_vtestnzc_pd:
14955 case Intrinsic::x86_avx_vtestnzc_ps_256:
14956 case Intrinsic::x86_avx_vtestnzc_pd_256:
14957 IsTestPacked = true; // Fallthrough
14958 case Intrinsic::x86_sse41_ptestnzc:
14959 case Intrinsic::x86_avx_ptestnzc_256:
14961 X86CC = X86::COND_A;
14965 SDValue LHS = Op.getOperand(1);
14966 SDValue RHS = Op.getOperand(2);
14967 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
14968 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
14969 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
14970 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
14971 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14973 case Intrinsic::x86_avx512_kortestz_w:
14974 case Intrinsic::x86_avx512_kortestc_w: {
14975 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
14976 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
14977 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
14978 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
14979 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
14980 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
14981 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14984 case Intrinsic::x86_sse42_pcmpistria128:
14985 case Intrinsic::x86_sse42_pcmpestria128:
14986 case Intrinsic::x86_sse42_pcmpistric128:
14987 case Intrinsic::x86_sse42_pcmpestric128:
14988 case Intrinsic::x86_sse42_pcmpistrio128:
14989 case Intrinsic::x86_sse42_pcmpestrio128:
14990 case Intrinsic::x86_sse42_pcmpistris128:
14991 case Intrinsic::x86_sse42_pcmpestris128:
14992 case Intrinsic::x86_sse42_pcmpistriz128:
14993 case Intrinsic::x86_sse42_pcmpestriz128: {
14997 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14998 case Intrinsic::x86_sse42_pcmpistria128:
14999 Opcode = X86ISD::PCMPISTRI;
15000 X86CC = X86::COND_A;
15002 case Intrinsic::x86_sse42_pcmpestria128:
15003 Opcode = X86ISD::PCMPESTRI;
15004 X86CC = X86::COND_A;
15006 case Intrinsic::x86_sse42_pcmpistric128:
15007 Opcode = X86ISD::PCMPISTRI;
15008 X86CC = X86::COND_B;
15010 case Intrinsic::x86_sse42_pcmpestric128:
15011 Opcode = X86ISD::PCMPESTRI;
15012 X86CC = X86::COND_B;
15014 case Intrinsic::x86_sse42_pcmpistrio128:
15015 Opcode = X86ISD::PCMPISTRI;
15016 X86CC = X86::COND_O;
15018 case Intrinsic::x86_sse42_pcmpestrio128:
15019 Opcode = X86ISD::PCMPESTRI;
15020 X86CC = X86::COND_O;
15022 case Intrinsic::x86_sse42_pcmpistris128:
15023 Opcode = X86ISD::PCMPISTRI;
15024 X86CC = X86::COND_S;
15026 case Intrinsic::x86_sse42_pcmpestris128:
15027 Opcode = X86ISD::PCMPESTRI;
15028 X86CC = X86::COND_S;
15030 case Intrinsic::x86_sse42_pcmpistriz128:
15031 Opcode = X86ISD::PCMPISTRI;
15032 X86CC = X86::COND_E;
15034 case Intrinsic::x86_sse42_pcmpestriz128:
15035 Opcode = X86ISD::PCMPESTRI;
15036 X86CC = X86::COND_E;
15039 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15040 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15041 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
15042 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15043 DAG.getConstant(X86CC, MVT::i8),
15044 SDValue(PCMP.getNode(), 1));
15045 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15048 case Intrinsic::x86_sse42_pcmpistri128:
15049 case Intrinsic::x86_sse42_pcmpestri128: {
15051 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
15052 Opcode = X86ISD::PCMPISTRI;
15054 Opcode = X86ISD::PCMPESTRI;
15056 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15057 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15058 return DAG.getNode(Opcode, dl, VTs, NewOps);
15063 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15064 SDValue Src, SDValue Mask, SDValue Base,
15065 SDValue Index, SDValue ScaleOp, SDValue Chain,
15066 const X86Subtarget * Subtarget) {
15068 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15069 assert(C && "Invalid scale type");
15070 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15071 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15072 Index.getSimpleValueType().getVectorNumElements());
15074 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15076 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15078 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15079 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
15080 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15081 SDValue Segment = DAG.getRegister(0, MVT::i32);
15082 if (Src.getOpcode() == ISD::UNDEF)
15083 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
15084 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15085 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15086 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
15087 return DAG.getMergeValues(RetOps, dl);
15090 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15091 SDValue Src, SDValue Mask, SDValue Base,
15092 SDValue Index, SDValue ScaleOp, SDValue Chain) {
15094 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15095 assert(C && "Invalid scale type");
15096 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15097 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15098 SDValue Segment = DAG.getRegister(0, MVT::i32);
15099 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15100 Index.getSimpleValueType().getVectorNumElements());
15102 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15104 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15106 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15107 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
15108 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
15109 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15110 return SDValue(Res, 1);
15113 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15114 SDValue Mask, SDValue Base, SDValue Index,
15115 SDValue ScaleOp, SDValue Chain) {
15117 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15118 assert(C && "Invalid scale type");
15119 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
15120 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
15121 SDValue Segment = DAG.getRegister(0, MVT::i32);
15123 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
15125 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15127 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
15129 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
15130 //SDVTList VTs = DAG.getVTList(MVT::Other);
15131 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15132 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
15133 return SDValue(Res, 0);
15136 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
15137 // read performance monitor counters (x86_rdpmc).
15138 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
15139 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15140 SmallVectorImpl<SDValue> &Results) {
15141 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15142 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15145 // The ECX register is used to select the index of the performance counter
15147 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
15149 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
15151 // Reads the content of a 64-bit performance counter and returns it in the
15152 // registers EDX:EAX.
15153 if (Subtarget->is64Bit()) {
15154 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15155 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15158 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15159 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15162 Chain = HI.getValue(1);
15164 if (Subtarget->is64Bit()) {
15165 // The EAX register is loaded with the low-order 32 bits. The EDX register
15166 // is loaded with the supported high-order bits of the counter.
15167 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15168 DAG.getConstant(32, MVT::i8));
15169 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15170 Results.push_back(Chain);
15174 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15175 SDValue Ops[] = { LO, HI };
15176 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15177 Results.push_back(Pair);
15178 Results.push_back(Chain);
15181 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
15182 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
15183 // also used to custom lower READCYCLECOUNTER nodes.
15184 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
15185 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15186 SmallVectorImpl<SDValue> &Results) {
15187 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15188 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
15191 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
15192 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
15193 // and the EAX register is loaded with the low-order 32 bits.
15194 if (Subtarget->is64Bit()) {
15195 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15196 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15199 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15200 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15203 SDValue Chain = HI.getValue(1);
15205 if (Opcode == X86ISD::RDTSCP_DAG) {
15206 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15208 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
15209 // the ECX register. Add 'ecx' explicitly to the chain.
15210 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
15212 // Explicitly store the content of ECX at the location passed in input
15213 // to the 'rdtscp' intrinsic.
15214 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
15215 MachinePointerInfo(), false, false, 0);
15218 if (Subtarget->is64Bit()) {
15219 // The EDX register is loaded with the high-order 32 bits of the MSR, and
15220 // the EAX register is loaded with the low-order 32 bits.
15221 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15222 DAG.getConstant(32, MVT::i8));
15223 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15224 Results.push_back(Chain);
15228 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15229 SDValue Ops[] = { LO, HI };
15230 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15231 Results.push_back(Pair);
15232 Results.push_back(Chain);
15235 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
15236 SelectionDAG &DAG) {
15237 SmallVector<SDValue, 2> Results;
15239 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
15241 return DAG.getMergeValues(Results, DL);
15245 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15246 SelectionDAG &DAG) {
15247 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
15249 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
15254 switch(IntrData->Type) {
15256 llvm_unreachable("Unknown Intrinsic Type");
15260 // Emit the node with the right value type.
15261 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
15262 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15264 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
15265 // Otherwise return the value from Rand, which is always 0, casted to i32.
15266 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
15267 DAG.getConstant(1, Op->getValueType(1)),
15268 DAG.getConstant(X86::COND_B, MVT::i32),
15269 SDValue(Result.getNode(), 1) };
15270 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
15271 DAG.getVTList(Op->getValueType(1), MVT::Glue),
15274 // Return { result, isValid, chain }.
15275 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
15276 SDValue(Result.getNode(), 2));
15279 //gather(v1, mask, index, base, scale);
15280 SDValue Chain = Op.getOperand(0);
15281 SDValue Src = Op.getOperand(2);
15282 SDValue Base = Op.getOperand(3);
15283 SDValue Index = Op.getOperand(4);
15284 SDValue Mask = Op.getOperand(5);
15285 SDValue Scale = Op.getOperand(6);
15286 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
15290 //scatter(base, mask, index, v1, scale);
15291 SDValue Chain = Op.getOperand(0);
15292 SDValue Base = Op.getOperand(2);
15293 SDValue Mask = Op.getOperand(3);
15294 SDValue Index = Op.getOperand(4);
15295 SDValue Src = Op.getOperand(5);
15296 SDValue Scale = Op.getOperand(6);
15297 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
15300 SDValue Hint = Op.getOperand(6);
15301 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
15302 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
15303 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
15304 SDValue Chain = Op.getOperand(0);
15305 SDValue Mask = Op.getOperand(2);
15306 SDValue Index = Op.getOperand(3);
15307 SDValue Base = Op.getOperand(4);
15308 SDValue Scale = Op.getOperand(5);
15309 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
15311 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
15313 SmallVector<SDValue, 2> Results;
15314 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
15315 return DAG.getMergeValues(Results, dl);
15317 // Read Performance Monitoring Counters.
15319 SmallVector<SDValue, 2> Results;
15320 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
15321 return DAG.getMergeValues(Results, dl);
15323 // XTEST intrinsics.
15325 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15326 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15327 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15328 DAG.getConstant(X86::COND_NE, MVT::i8),
15330 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
15331 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
15332 Ret, SDValue(InTrans.getNode(), 1));
15336 SmallVector<SDValue, 2> Results;
15337 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15338 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
15339 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
15340 DAG.getConstant(-1, MVT::i8));
15341 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
15342 Op.getOperand(4), GenCF.getValue(1));
15343 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
15344 Op.getOperand(5), MachinePointerInfo(),
15346 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15347 DAG.getConstant(X86::COND_B, MVT::i8),
15349 Results.push_back(SetCC);
15350 Results.push_back(Store);
15351 return DAG.getMergeValues(Results, dl);
15353 case COMPRESS_TO_MEM: {
15355 SDValue Mask = Op.getOperand(4);
15356 SDValue DataToCompress = Op.getOperand(3);
15357 SDValue Addr = Op.getOperand(2);
15358 SDValue Chain = Op.getOperand(0);
15360 if (isAllOnes(Mask)) // return just a store
15361 return DAG.getStore(Chain, dl, DataToCompress, Addr,
15362 MachinePointerInfo(), false, false, 0);
15364 EVT VT = DataToCompress.getValueType();
15365 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15366 VT.getVectorNumElements());
15367 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15368 Mask.getValueType().getSizeInBits());
15369 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15370 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15371 DAG.getIntPtrConstant(0));
15373 SDValue Compressed = DAG.getNode(IntrData->Opc0, dl, VT, VMask,
15374 DataToCompress, DAG.getUNDEF(VT));
15375 return DAG.getStore(Chain, dl, Compressed, Addr,
15376 MachinePointerInfo(), false, false, 0);
15378 case EXPAND_FROM_MEM: {
15380 SDValue Mask = Op.getOperand(4);
15381 SDValue PathThru = Op.getOperand(3);
15382 SDValue Addr = Op.getOperand(2);
15383 SDValue Chain = Op.getOperand(0);
15384 EVT VT = Op.getValueType();
15386 if (isAllOnes(Mask)) // return just a load
15387 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
15389 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15390 VT.getVectorNumElements());
15391 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15392 Mask.getValueType().getSizeInBits());
15393 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15394 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
15395 DAG.getIntPtrConstant(0));
15397 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
15398 false, false, false, 0);
15400 SDValue Results[] = {
15401 DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToExpand, PathThru),
15403 return DAG.getMergeValues(Results, dl);
15408 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
15409 SelectionDAG &DAG) const {
15410 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15411 MFI->setReturnAddressIsTaken(true);
15413 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
15416 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15418 EVT PtrVT = getPointerTy();
15421 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
15422 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15423 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
15424 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15425 DAG.getNode(ISD::ADD, dl, PtrVT,
15426 FrameAddr, Offset),
15427 MachinePointerInfo(), false, false, false, 0);
15430 // Just load the return address.
15431 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
15432 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15433 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
15436 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
15437 MachineFunction &MF = DAG.getMachineFunction();
15438 MachineFrameInfo *MFI = MF.getFrameInfo();
15439 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15440 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15441 EVT VT = Op.getValueType();
15443 MFI->setFrameAddressIsTaken(true);
15445 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
15446 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
15447 // is not possible to crawl up the stack without looking at the unwind codes
15449 int FrameAddrIndex = FuncInfo->getFAIndex();
15450 if (!FrameAddrIndex) {
15451 // Set up a frame object for the return address.
15452 unsigned SlotSize = RegInfo->getSlotSize();
15453 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
15454 SlotSize, /*Offset=*/INT64_MIN, /*IsImmutable=*/false);
15455 FuncInfo->setFAIndex(FrameAddrIndex);
15457 return DAG.getFrameIndex(FrameAddrIndex, VT);
15460 unsigned FrameReg =
15461 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
15462 SDLoc dl(Op); // FIXME probably not meaningful
15463 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15464 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
15465 (FrameReg == X86::EBP && VT == MVT::i32)) &&
15466 "Invalid Frame Register!");
15467 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
15469 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
15470 MachinePointerInfo(),
15471 false, false, false, 0);
15475 // FIXME? Maybe this could be a TableGen attribute on some registers and
15476 // this table could be generated automatically from RegInfo.
15477 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
15479 unsigned Reg = StringSwitch<unsigned>(RegName)
15480 .Case("esp", X86::ESP)
15481 .Case("rsp", X86::RSP)
15485 report_fatal_error("Invalid register name global variable");
15488 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
15489 SelectionDAG &DAG) const {
15490 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15491 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
15494 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
15495 SDValue Chain = Op.getOperand(0);
15496 SDValue Offset = Op.getOperand(1);
15497 SDValue Handler = Op.getOperand(2);
15500 EVT PtrVT = getPointerTy();
15501 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15502 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15503 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
15504 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
15505 "Invalid Frame Register!");
15506 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
15507 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
15509 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
15510 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
15511 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
15512 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
15514 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
15516 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
15517 DAG.getRegister(StoreAddrReg, PtrVT));
15520 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
15521 SelectionDAG &DAG) const {
15523 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
15524 DAG.getVTList(MVT::i32, MVT::Other),
15525 Op.getOperand(0), Op.getOperand(1));
15528 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
15529 SelectionDAG &DAG) const {
15531 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
15532 Op.getOperand(0), Op.getOperand(1));
15535 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
15536 return Op.getOperand(0);
15539 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
15540 SelectionDAG &DAG) const {
15541 SDValue Root = Op.getOperand(0);
15542 SDValue Trmp = Op.getOperand(1); // trampoline
15543 SDValue FPtr = Op.getOperand(2); // nested function
15544 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
15547 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15548 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
15550 if (Subtarget->is64Bit()) {
15551 SDValue OutChains[6];
15553 // Large code-model.
15554 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
15555 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
15557 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
15558 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
15560 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
15562 // Load the pointer to the nested function into R11.
15563 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
15564 SDValue Addr = Trmp;
15565 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15566 Addr, MachinePointerInfo(TrmpAddr),
15569 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15570 DAG.getConstant(2, MVT::i64));
15571 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
15572 MachinePointerInfo(TrmpAddr, 2),
15575 // Load the 'nest' parameter value into R10.
15576 // R10 is specified in X86CallingConv.td
15577 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
15578 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15579 DAG.getConstant(10, MVT::i64));
15580 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15581 Addr, MachinePointerInfo(TrmpAddr, 10),
15584 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15585 DAG.getConstant(12, MVT::i64));
15586 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
15587 MachinePointerInfo(TrmpAddr, 12),
15590 // Jump to the nested function.
15591 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
15592 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15593 DAG.getConstant(20, MVT::i64));
15594 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15595 Addr, MachinePointerInfo(TrmpAddr, 20),
15598 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
15599 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15600 DAG.getConstant(22, MVT::i64));
15601 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
15602 MachinePointerInfo(TrmpAddr, 22),
15605 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15607 const Function *Func =
15608 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
15609 CallingConv::ID CC = Func->getCallingConv();
15614 llvm_unreachable("Unsupported calling convention");
15615 case CallingConv::C:
15616 case CallingConv::X86_StdCall: {
15617 // Pass 'nest' parameter in ECX.
15618 // Must be kept in sync with X86CallingConv.td
15619 NestReg = X86::ECX;
15621 // Check that ECX wasn't needed by an 'inreg' parameter.
15622 FunctionType *FTy = Func->getFunctionType();
15623 const AttributeSet &Attrs = Func->getAttributes();
15625 if (!Attrs.isEmpty() && !Func->isVarArg()) {
15626 unsigned InRegCount = 0;
15629 for (FunctionType::param_iterator I = FTy->param_begin(),
15630 E = FTy->param_end(); I != E; ++I, ++Idx)
15631 if (Attrs.hasAttribute(Idx, Attribute::InReg))
15632 // FIXME: should only count parameters that are lowered to integers.
15633 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
15635 if (InRegCount > 2) {
15636 report_fatal_error("Nest register in use - reduce number of inreg"
15642 case CallingConv::X86_FastCall:
15643 case CallingConv::X86_ThisCall:
15644 case CallingConv::Fast:
15645 // Pass 'nest' parameter in EAX.
15646 // Must be kept in sync with X86CallingConv.td
15647 NestReg = X86::EAX;
15651 SDValue OutChains[4];
15652 SDValue Addr, Disp;
15654 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15655 DAG.getConstant(10, MVT::i32));
15656 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
15658 // This is storing the opcode for MOV32ri.
15659 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
15660 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
15661 OutChains[0] = DAG.getStore(Root, dl,
15662 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
15663 Trmp, MachinePointerInfo(TrmpAddr),
15666 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15667 DAG.getConstant(1, MVT::i32));
15668 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
15669 MachinePointerInfo(TrmpAddr, 1),
15672 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
15673 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15674 DAG.getConstant(5, MVT::i32));
15675 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
15676 MachinePointerInfo(TrmpAddr, 5),
15679 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15680 DAG.getConstant(6, MVT::i32));
15681 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
15682 MachinePointerInfo(TrmpAddr, 6),
15685 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15689 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
15690 SelectionDAG &DAG) const {
15692 The rounding mode is in bits 11:10 of FPSR, and has the following
15694 00 Round to nearest
15699 FLT_ROUNDS, on the other hand, expects the following:
15706 To perform the conversion, we do:
15707 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
15710 MachineFunction &MF = DAG.getMachineFunction();
15711 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15712 unsigned StackAlignment = TFI.getStackAlignment();
15713 MVT VT = Op.getSimpleValueType();
15716 // Save FP Control Word to stack slot
15717 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
15718 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
15720 MachineMemOperand *MMO =
15721 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
15722 MachineMemOperand::MOStore, 2, 2);
15724 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
15725 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
15726 DAG.getVTList(MVT::Other),
15727 Ops, MVT::i16, MMO);
15729 // Load FP Control Word from stack slot
15730 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
15731 MachinePointerInfo(), false, false, false, 0);
15733 // Transform as necessary
15735 DAG.getNode(ISD::SRL, DL, MVT::i16,
15736 DAG.getNode(ISD::AND, DL, MVT::i16,
15737 CWD, DAG.getConstant(0x800, MVT::i16)),
15738 DAG.getConstant(11, MVT::i8));
15740 DAG.getNode(ISD::SRL, DL, MVT::i16,
15741 DAG.getNode(ISD::AND, DL, MVT::i16,
15742 CWD, DAG.getConstant(0x400, MVT::i16)),
15743 DAG.getConstant(9, MVT::i8));
15746 DAG.getNode(ISD::AND, DL, MVT::i16,
15747 DAG.getNode(ISD::ADD, DL, MVT::i16,
15748 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
15749 DAG.getConstant(1, MVT::i16)),
15750 DAG.getConstant(3, MVT::i16));
15752 return DAG.getNode((VT.getSizeInBits() < 16 ?
15753 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
15756 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
15757 MVT VT = Op.getSimpleValueType();
15759 unsigned NumBits = VT.getSizeInBits();
15762 Op = Op.getOperand(0);
15763 if (VT == MVT::i8) {
15764 // Zero extend to i32 since there is not an i8 bsr.
15766 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
15769 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
15770 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
15771 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
15773 // If src is zero (i.e. bsr sets ZF), returns NumBits.
15776 DAG.getConstant(NumBits+NumBits-1, OpVT),
15777 DAG.getConstant(X86::COND_E, MVT::i8),
15780 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
15782 // Finally xor with NumBits-1.
15783 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
15786 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
15790 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
15791 MVT VT = Op.getSimpleValueType();
15793 unsigned NumBits = VT.getSizeInBits();
15796 Op = Op.getOperand(0);
15797 if (VT == MVT::i8) {
15798 // Zero extend to i32 since there is not an i8 bsr.
15800 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
15803 // Issue a bsr (scan bits in reverse).
15804 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
15805 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
15807 // And xor with NumBits-1.
15808 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
15811 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
15815 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
15816 MVT VT = Op.getSimpleValueType();
15817 unsigned NumBits = VT.getSizeInBits();
15819 Op = Op.getOperand(0);
15821 // Issue a bsf (scan bits forward) which also sets EFLAGS.
15822 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
15823 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
15825 // If src is zero (i.e. bsf sets ZF), returns NumBits.
15828 DAG.getConstant(NumBits, VT),
15829 DAG.getConstant(X86::COND_E, MVT::i8),
15832 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
15835 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
15836 // ones, and then concatenate the result back.
15837 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
15838 MVT VT = Op.getSimpleValueType();
15840 assert(VT.is256BitVector() && VT.isInteger() &&
15841 "Unsupported value type for operation");
15843 unsigned NumElems = VT.getVectorNumElements();
15846 // Extract the LHS vectors
15847 SDValue LHS = Op.getOperand(0);
15848 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15849 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15851 // Extract the RHS vectors
15852 SDValue RHS = Op.getOperand(1);
15853 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15854 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15856 MVT EltVT = VT.getVectorElementType();
15857 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15859 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15860 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
15861 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
15864 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
15865 assert(Op.getSimpleValueType().is256BitVector() &&
15866 Op.getSimpleValueType().isInteger() &&
15867 "Only handle AVX 256-bit vector integer operation");
15868 return Lower256IntArith(Op, DAG);
15871 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
15872 assert(Op.getSimpleValueType().is256BitVector() &&
15873 Op.getSimpleValueType().isInteger() &&
15874 "Only handle AVX 256-bit vector integer operation");
15875 return Lower256IntArith(Op, DAG);
15878 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
15879 SelectionDAG &DAG) {
15881 MVT VT = Op.getSimpleValueType();
15883 // Decompose 256-bit ops into smaller 128-bit ops.
15884 if (VT.is256BitVector() && !Subtarget->hasInt256())
15885 return Lower256IntArith(Op, DAG);
15887 SDValue A = Op.getOperand(0);
15888 SDValue B = Op.getOperand(1);
15890 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
15891 if (VT == MVT::v4i32) {
15892 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
15893 "Should not custom lower when pmuldq is available!");
15895 // Extract the odd parts.
15896 static const int UnpackMask[] = { 1, -1, 3, -1 };
15897 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
15898 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
15900 // Multiply the even parts.
15901 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
15902 // Now multiply odd parts.
15903 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
15905 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
15906 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
15908 // Merge the two vectors back together with a shuffle. This expands into 2
15910 static const int ShufMask[] = { 0, 4, 2, 6 };
15911 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
15914 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
15915 "Only know how to lower V2I64/V4I64/V8I64 multiply");
15917 // Ahi = psrlqi(a, 32);
15918 // Bhi = psrlqi(b, 32);
15920 // AloBlo = pmuludq(a, b);
15921 // AloBhi = pmuludq(a, Bhi);
15922 // AhiBlo = pmuludq(Ahi, b);
15924 // AloBhi = psllqi(AloBhi, 32);
15925 // AhiBlo = psllqi(AhiBlo, 32);
15926 // return AloBlo + AloBhi + AhiBlo;
15928 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
15929 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
15931 // Bit cast to 32-bit vectors for MULUDQ
15932 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
15933 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
15934 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
15935 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
15936 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
15937 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
15939 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
15940 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
15941 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
15943 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
15944 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
15946 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
15947 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
15950 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
15951 assert(Subtarget->isTargetWin64() && "Unexpected target");
15952 EVT VT = Op.getValueType();
15953 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
15954 "Unexpected return type for lowering");
15958 switch (Op->getOpcode()) {
15959 default: llvm_unreachable("Unexpected request for libcall!");
15960 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
15961 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
15962 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
15963 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
15964 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
15965 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
15969 SDValue InChain = DAG.getEntryNode();
15971 TargetLowering::ArgListTy Args;
15972 TargetLowering::ArgListEntry Entry;
15973 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
15974 EVT ArgVT = Op->getOperand(i).getValueType();
15975 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
15976 "Unexpected argument type for lowering");
15977 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
15978 Entry.Node = StackPtr;
15979 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
15981 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15982 Entry.Ty = PointerType::get(ArgTy,0);
15983 Entry.isSExt = false;
15984 Entry.isZExt = false;
15985 Args.push_back(Entry);
15988 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
15991 TargetLowering::CallLoweringInfo CLI(DAG);
15992 CLI.setDebugLoc(dl).setChain(InChain)
15993 .setCallee(getLibcallCallingConv(LC),
15994 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
15995 Callee, std::move(Args), 0)
15996 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
15998 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
15999 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
16002 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
16003 SelectionDAG &DAG) {
16004 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
16005 EVT VT = Op0.getValueType();
16008 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
16009 (VT == MVT::v8i32 && Subtarget->hasInt256()));
16011 // PMULxD operations multiply each even value (starting at 0) of LHS with
16012 // the related value of RHS and produce a widen result.
16013 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16014 // => <2 x i64> <ae|cg>
16016 // In other word, to have all the results, we need to perform two PMULxD:
16017 // 1. one with the even values.
16018 // 2. one with the odd values.
16019 // To achieve #2, with need to place the odd values at an even position.
16021 // Place the odd value at an even position (basically, shift all values 1
16022 // step to the left):
16023 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
16024 // <a|b|c|d> => <b|undef|d|undef>
16025 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
16026 // <e|f|g|h> => <f|undef|h|undef>
16027 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
16029 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
16031 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
16032 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
16034 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
16035 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16036 // => <2 x i64> <ae|cg>
16037 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
16038 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
16039 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
16040 // => <2 x i64> <bf|dh>
16041 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
16042 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
16044 // Shuffle it back into the right order.
16045 SDValue Highs, Lows;
16046 if (VT == MVT::v8i32) {
16047 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
16048 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16049 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
16050 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16052 const int HighMask[] = {1, 5, 3, 7};
16053 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16054 const int LowMask[] = {0, 4, 2, 6};
16055 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16058 // If we have a signed multiply but no PMULDQ fix up the high parts of a
16059 // unsigned multiply.
16060 if (IsSigned && !Subtarget->hasSSE41()) {
16062 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
16063 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
16064 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
16065 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
16066 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
16068 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
16069 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
16072 // The first result of MUL_LOHI is actually the low value, followed by the
16074 SDValue Ops[] = {Lows, Highs};
16075 return DAG.getMergeValues(Ops, dl);
16078 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
16079 const X86Subtarget *Subtarget) {
16080 MVT VT = Op.getSimpleValueType();
16082 SDValue R = Op.getOperand(0);
16083 SDValue Amt = Op.getOperand(1);
16085 // Optimize shl/srl/sra with constant shift amount.
16086 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
16087 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
16088 uint64_t ShiftAmt = ShiftConst->getZExtValue();
16090 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
16091 (Subtarget->hasInt256() &&
16092 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
16093 (Subtarget->hasAVX512() &&
16094 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
16095 if (Op.getOpcode() == ISD::SHL)
16096 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
16098 if (Op.getOpcode() == ISD::SRL)
16099 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
16101 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
16102 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
16106 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
16107 unsigned NumElts = VT.getVectorNumElements();
16108 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
16110 if (Op.getOpcode() == ISD::SHL) {
16111 // Make a large shift.
16112 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
16114 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
16115 // Zero out the rightmost bits.
16116 SmallVector<SDValue, 32> V(
16117 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), MVT::i8));
16118 return DAG.getNode(ISD::AND, dl, VT, SHL,
16119 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16121 if (Op.getOpcode() == ISD::SRL) {
16122 // Make a large shift.
16123 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
16125 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
16126 // Zero out the leftmost bits.
16127 SmallVector<SDValue, 32> V(
16128 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, MVT::i8));
16129 return DAG.getNode(ISD::AND, dl, VT, SRL,
16130 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16132 if (Op.getOpcode() == ISD::SRA) {
16133 if (ShiftAmt == 7) {
16134 // R s>> 7 === R s< 0
16135 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16136 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16139 // R s>> a === ((R u>> a) ^ m) - m
16140 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16141 SmallVector<SDValue, 32> V(NumElts,
16142 DAG.getConstant(128 >> ShiftAmt, MVT::i8));
16143 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16144 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16145 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16148 llvm_unreachable("Unknown shift opcode.");
16153 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16154 if (!Subtarget->is64Bit() &&
16155 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
16156 Amt.getOpcode() == ISD::BITCAST &&
16157 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16158 Amt = Amt.getOperand(0);
16159 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16160 VT.getVectorNumElements();
16161 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
16162 uint64_t ShiftAmt = 0;
16163 for (unsigned i = 0; i != Ratio; ++i) {
16164 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
16168 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
16170 // Check remaining shift amounts.
16171 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16172 uint64_t ShAmt = 0;
16173 for (unsigned j = 0; j != Ratio; ++j) {
16174 ConstantSDNode *C =
16175 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
16179 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
16181 if (ShAmt != ShiftAmt)
16184 switch (Op.getOpcode()) {
16186 llvm_unreachable("Unknown shift opcode!");
16188 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
16191 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
16194 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
16202 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
16203 const X86Subtarget* Subtarget) {
16204 MVT VT = Op.getSimpleValueType();
16206 SDValue R = Op.getOperand(0);
16207 SDValue Amt = Op.getOperand(1);
16209 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
16210 VT == MVT::v4i32 || VT == MVT::v8i16 ||
16211 (Subtarget->hasInt256() &&
16212 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
16213 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
16214 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
16216 EVT EltVT = VT.getVectorElementType();
16218 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
16219 // Check if this build_vector node is doing a splat.
16220 // If so, then set BaseShAmt equal to the splat value.
16221 BaseShAmt = BV->getSplatValue();
16222 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
16223 BaseShAmt = SDValue();
16225 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
16226 Amt = Amt.getOperand(0);
16228 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
16229 if (SVN && SVN->isSplat()) {
16230 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
16231 SDValue InVec = Amt.getOperand(0);
16232 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
16233 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
16234 "Unexpected shuffle index found!");
16235 BaseShAmt = InVec.getOperand(SplatIdx);
16236 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
16237 if (ConstantSDNode *C =
16238 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
16239 if (C->getZExtValue() == SplatIdx)
16240 BaseShAmt = InVec.getOperand(1);
16245 // Avoid introducing an extract element from a shuffle.
16246 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
16247 DAG.getIntPtrConstant(SplatIdx));
16251 if (BaseShAmt.getNode()) {
16252 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
16253 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
16254 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
16255 else if (EltVT.bitsLT(MVT::i32))
16256 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
16258 switch (Op.getOpcode()) {
16260 llvm_unreachable("Unknown shift opcode!");
16262 switch (VT.SimpleTy) {
16263 default: return SDValue();
16272 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
16275 switch (VT.SimpleTy) {
16276 default: return SDValue();
16283 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
16286 switch (VT.SimpleTy) {
16287 default: return SDValue();
16296 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
16302 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16303 if (!Subtarget->is64Bit() &&
16304 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
16305 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
16306 Amt.getOpcode() == ISD::BITCAST &&
16307 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16308 Amt = Amt.getOperand(0);
16309 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16310 VT.getVectorNumElements();
16311 std::vector<SDValue> Vals(Ratio);
16312 for (unsigned i = 0; i != Ratio; ++i)
16313 Vals[i] = Amt.getOperand(i);
16314 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16315 for (unsigned j = 0; j != Ratio; ++j)
16316 if (Vals[j] != Amt.getOperand(i + j))
16319 switch (Op.getOpcode()) {
16321 llvm_unreachable("Unknown shift opcode!");
16323 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
16325 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
16327 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
16334 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
16335 SelectionDAG &DAG) {
16336 MVT VT = Op.getSimpleValueType();
16338 SDValue R = Op.getOperand(0);
16339 SDValue Amt = Op.getOperand(1);
16341 assert(VT.isVector() && "Custom lowering only for vector shifts!");
16342 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
16344 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
16347 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
16350 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
16353 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
16354 if (Subtarget->hasInt256()) {
16355 if (Op.getOpcode() == ISD::SRL &&
16356 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16357 VT == MVT::v4i64 || VT == MVT::v8i32))
16359 if (Op.getOpcode() == ISD::SHL &&
16360 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16361 VT == MVT::v4i64 || VT == MVT::v8i32))
16363 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
16367 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
16368 // shifts per-lane and then shuffle the partial results back together.
16369 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
16370 // Splat the shift amounts so the scalar shifts above will catch it.
16371 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
16372 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
16373 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
16374 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
16375 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
16378 // If possible, lower this packed shift into a vector multiply instead of
16379 // expanding it into a sequence of scalar shifts.
16380 // Do this only if the vector shift count is a constant build_vector.
16381 if (Op.getOpcode() == ISD::SHL &&
16382 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
16383 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
16384 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16385 SmallVector<SDValue, 8> Elts;
16386 EVT SVT = VT.getScalarType();
16387 unsigned SVTBits = SVT.getSizeInBits();
16388 const APInt &One = APInt(SVTBits, 1);
16389 unsigned NumElems = VT.getVectorNumElements();
16391 for (unsigned i=0; i !=NumElems; ++i) {
16392 SDValue Op = Amt->getOperand(i);
16393 if (Op->getOpcode() == ISD::UNDEF) {
16394 Elts.push_back(Op);
16398 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
16399 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
16400 uint64_t ShAmt = C.getZExtValue();
16401 if (ShAmt >= SVTBits) {
16402 Elts.push_back(DAG.getUNDEF(SVT));
16405 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
16407 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16408 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
16411 // Lower SHL with variable shift amount.
16412 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
16413 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
16415 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
16416 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
16417 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
16418 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
16421 // If possible, lower this shift as a sequence of two shifts by
16422 // constant plus a MOVSS/MOVSD instead of scalarizing it.
16424 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
16426 // Could be rewritten as:
16427 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
16429 // The advantage is that the two shifts from the example would be
16430 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
16431 // the vector shift into four scalar shifts plus four pairs of vector
16433 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
16434 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16435 unsigned TargetOpcode = X86ISD::MOVSS;
16436 bool CanBeSimplified;
16437 // The splat value for the first packed shift (the 'X' from the example).
16438 SDValue Amt1 = Amt->getOperand(0);
16439 // The splat value for the second packed shift (the 'Y' from the example).
16440 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
16441 Amt->getOperand(2);
16443 // See if it is possible to replace this node with a sequence of
16444 // two shifts followed by a MOVSS/MOVSD
16445 if (VT == MVT::v4i32) {
16446 // Check if it is legal to use a MOVSS.
16447 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
16448 Amt2 == Amt->getOperand(3);
16449 if (!CanBeSimplified) {
16450 // Otherwise, check if we can still simplify this node using a MOVSD.
16451 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
16452 Amt->getOperand(2) == Amt->getOperand(3);
16453 TargetOpcode = X86ISD::MOVSD;
16454 Amt2 = Amt->getOperand(2);
16457 // Do similar checks for the case where the machine value type
16459 CanBeSimplified = Amt1 == Amt->getOperand(1);
16460 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
16461 CanBeSimplified = Amt2 == Amt->getOperand(i);
16463 if (!CanBeSimplified) {
16464 TargetOpcode = X86ISD::MOVSD;
16465 CanBeSimplified = true;
16466 Amt2 = Amt->getOperand(4);
16467 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
16468 CanBeSimplified = Amt1 == Amt->getOperand(i);
16469 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
16470 CanBeSimplified = Amt2 == Amt->getOperand(j);
16474 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
16475 isa<ConstantSDNode>(Amt2)) {
16476 // Replace this node with two shifts followed by a MOVSS/MOVSD.
16477 EVT CastVT = MVT::v4i32;
16479 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
16480 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
16482 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
16483 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
16484 if (TargetOpcode == X86ISD::MOVSD)
16485 CastVT = MVT::v2i64;
16486 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
16487 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
16488 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
16490 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
16494 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
16495 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
16498 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
16499 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
16501 // Turn 'a' into a mask suitable for VSELECT
16502 SDValue VSelM = DAG.getConstant(0x80, VT);
16503 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16504 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16506 SDValue CM1 = DAG.getConstant(0x0f, VT);
16507 SDValue CM2 = DAG.getConstant(0x3f, VT);
16509 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
16510 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
16511 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
16512 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
16513 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16516 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16517 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16518 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16520 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
16521 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
16522 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
16523 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
16524 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16527 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16528 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16529 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16531 // return VSELECT(r, r+r, a);
16532 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
16533 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
16537 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
16538 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
16539 // solution better.
16540 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
16541 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
16543 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
16544 R = DAG.getNode(ExtOpc, dl, NewVT, R);
16545 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
16546 return DAG.getNode(ISD::TRUNCATE, dl, VT,
16547 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
16550 // Decompose 256-bit shifts into smaller 128-bit shifts.
16551 if (VT.is256BitVector()) {
16552 unsigned NumElems = VT.getVectorNumElements();
16553 MVT EltVT = VT.getVectorElementType();
16554 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16556 // Extract the two vectors
16557 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
16558 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
16560 // Recreate the shift amount vectors
16561 SDValue Amt1, Amt2;
16562 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
16563 // Constant shift amount
16564 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
16565 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
16566 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
16568 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
16569 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
16571 // Variable shift amount
16572 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
16573 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
16576 // Issue new vector shifts for the smaller types
16577 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
16578 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
16580 // Concatenate the result back
16581 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
16587 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
16588 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
16589 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
16590 // looks for this combo and may remove the "setcc" instruction if the "setcc"
16591 // has only one use.
16592 SDNode *N = Op.getNode();
16593 SDValue LHS = N->getOperand(0);
16594 SDValue RHS = N->getOperand(1);
16595 unsigned BaseOp = 0;
16598 switch (Op.getOpcode()) {
16599 default: llvm_unreachable("Unknown ovf instruction!");
16601 // A subtract of one will be selected as a INC. Note that INC doesn't
16602 // set CF, so we can't do this for UADDO.
16603 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16605 BaseOp = X86ISD::INC;
16606 Cond = X86::COND_O;
16609 BaseOp = X86ISD::ADD;
16610 Cond = X86::COND_O;
16613 BaseOp = X86ISD::ADD;
16614 Cond = X86::COND_B;
16617 // A subtract of one will be selected as a DEC. Note that DEC doesn't
16618 // set CF, so we can't do this for USUBO.
16619 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16621 BaseOp = X86ISD::DEC;
16622 Cond = X86::COND_O;
16625 BaseOp = X86ISD::SUB;
16626 Cond = X86::COND_O;
16629 BaseOp = X86ISD::SUB;
16630 Cond = X86::COND_B;
16633 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
16634 Cond = X86::COND_O;
16636 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
16637 if (N->getValueType(0) == MVT::i8) {
16638 BaseOp = X86ISD::UMUL8;
16639 Cond = X86::COND_O;
16642 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
16644 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
16647 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16648 DAG.getConstant(X86::COND_O, MVT::i32),
16649 SDValue(Sum.getNode(), 2));
16651 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
16655 // Also sets EFLAGS.
16656 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
16657 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
16660 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
16661 DAG.getConstant(Cond, MVT::i32),
16662 SDValue(Sum.getNode(), 1));
16664 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
16667 /// Returns true if the operand type is exactly twice the native width, and
16668 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
16669 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
16670 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
16671 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
16672 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
16675 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
16676 else if (OpWidth == 128)
16677 return Subtarget->hasCmpxchg16b();
16682 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
16683 return needsCmpXchgNb(SI->getValueOperand()->getType());
16686 // Note: this turns large loads into lock cmpxchg8b/16b.
16687 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
16688 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
16689 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
16690 return needsCmpXchgNb(PTy->getElementType());
16693 TargetLoweringBase::AtomicRMWExpansionKind
16694 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
16695 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
16696 const Type *MemType = AI->getType();
16698 // If the operand is too big, we must see if cmpxchg8/16b is available
16699 // and default to library calls otherwise.
16700 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
16701 return needsCmpXchgNb(MemType) ? AtomicRMWExpansionKind::CmpXChg
16702 : AtomicRMWExpansionKind::None;
16705 AtomicRMWInst::BinOp Op = AI->getOperation();
16708 llvm_unreachable("Unknown atomic operation");
16709 case AtomicRMWInst::Xchg:
16710 case AtomicRMWInst::Add:
16711 case AtomicRMWInst::Sub:
16712 // It's better to use xadd, xsub or xchg for these in all cases.
16713 return AtomicRMWExpansionKind::None;
16714 case AtomicRMWInst::Or:
16715 case AtomicRMWInst::And:
16716 case AtomicRMWInst::Xor:
16717 // If the atomicrmw's result isn't actually used, we can just add a "lock"
16718 // prefix to a normal instruction for these operations.
16719 return !AI->use_empty() ? AtomicRMWExpansionKind::CmpXChg
16720 : AtomicRMWExpansionKind::None;
16721 case AtomicRMWInst::Nand:
16722 case AtomicRMWInst::Max:
16723 case AtomicRMWInst::Min:
16724 case AtomicRMWInst::UMax:
16725 case AtomicRMWInst::UMin:
16726 // These always require a non-trivial set of data operations on x86. We must
16727 // use a cmpxchg loop.
16728 return AtomicRMWExpansionKind::CmpXChg;
16732 static bool hasMFENCE(const X86Subtarget& Subtarget) {
16733 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
16734 // no-sse2). There isn't any reason to disable it if the target processor
16736 return Subtarget.hasSSE2() || Subtarget.is64Bit();
16740 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
16741 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
16742 const Type *MemType = AI->getType();
16743 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
16744 // there is no benefit in turning such RMWs into loads, and it is actually
16745 // harmful as it introduces a mfence.
16746 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
16749 auto Builder = IRBuilder<>(AI);
16750 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
16751 auto SynchScope = AI->getSynchScope();
16752 // We must restrict the ordering to avoid generating loads with Release or
16753 // ReleaseAcquire orderings.
16754 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
16755 auto Ptr = AI->getPointerOperand();
16757 // Before the load we need a fence. Here is an example lifted from
16758 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
16761 // x.store(1, relaxed);
16762 // r1 = y.fetch_add(0, release);
16764 // y.fetch_add(42, acquire);
16765 // r2 = x.load(relaxed);
16766 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
16767 // lowered to just a load without a fence. A mfence flushes the store buffer,
16768 // making the optimization clearly correct.
16769 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
16770 // otherwise, we might be able to be more agressive on relaxed idempotent
16771 // rmw. In practice, they do not look useful, so we don't try to be
16772 // especially clever.
16773 if (SynchScope == SingleThread) {
16774 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
16775 // the IR level, so we must wrap it in an intrinsic.
16777 } else if (hasMFENCE(*Subtarget)) {
16778 Function *MFence = llvm::Intrinsic::getDeclaration(M,
16779 Intrinsic::x86_sse2_mfence);
16780 Builder.CreateCall(MFence);
16782 // FIXME: it might make sense to use a locked operation here but on a
16783 // different cache-line to prevent cache-line bouncing. In practice it
16784 // is probably a small win, and x86 processors without mfence are rare
16785 // enough that we do not bother.
16789 // Finally we can emit the atomic load.
16790 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
16791 AI->getType()->getPrimitiveSizeInBits());
16792 Loaded->setAtomic(Order, SynchScope);
16793 AI->replaceAllUsesWith(Loaded);
16794 AI->eraseFromParent();
16798 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
16799 SelectionDAG &DAG) {
16801 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
16802 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
16803 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
16804 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
16806 // The only fence that needs an instruction is a sequentially-consistent
16807 // cross-thread fence.
16808 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
16809 if (hasMFENCE(*Subtarget))
16810 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
16812 SDValue Chain = Op.getOperand(0);
16813 SDValue Zero = DAG.getConstant(0, MVT::i32);
16815 DAG.getRegister(X86::ESP, MVT::i32), // Base
16816 DAG.getTargetConstant(1, MVT::i8), // Scale
16817 DAG.getRegister(0, MVT::i32), // Index
16818 DAG.getTargetConstant(0, MVT::i32), // Disp
16819 DAG.getRegister(0, MVT::i32), // Segment.
16823 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
16824 return SDValue(Res, 0);
16827 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
16828 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
16831 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
16832 SelectionDAG &DAG) {
16833 MVT T = Op.getSimpleValueType();
16837 switch(T.SimpleTy) {
16838 default: llvm_unreachable("Invalid value type!");
16839 case MVT::i8: Reg = X86::AL; size = 1; break;
16840 case MVT::i16: Reg = X86::AX; size = 2; break;
16841 case MVT::i32: Reg = X86::EAX; size = 4; break;
16843 assert(Subtarget->is64Bit() && "Node not type legal!");
16844 Reg = X86::RAX; size = 8;
16847 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
16848 Op.getOperand(2), SDValue());
16849 SDValue Ops[] = { cpIn.getValue(0),
16852 DAG.getTargetConstant(size, MVT::i8),
16853 cpIn.getValue(1) };
16854 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16855 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
16856 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
16860 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
16861 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
16862 MVT::i32, cpOut.getValue(2));
16863 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
16864 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
16866 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
16867 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
16868 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
16872 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
16873 SelectionDAG &DAG) {
16874 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
16875 MVT DstVT = Op.getSimpleValueType();
16877 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
16878 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
16879 if (DstVT != MVT::f64)
16880 // This conversion needs to be expanded.
16883 SDValue InVec = Op->getOperand(0);
16885 unsigned NumElts = SrcVT.getVectorNumElements();
16886 EVT SVT = SrcVT.getVectorElementType();
16888 // Widen the vector in input in the case of MVT::v2i32.
16889 // Example: from MVT::v2i32 to MVT::v4i32.
16890 SmallVector<SDValue, 16> Elts;
16891 for (unsigned i = 0, e = NumElts; i != e; ++i)
16892 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
16893 DAG.getIntPtrConstant(i)));
16895 // Explicitly mark the extra elements as Undef.
16896 Elts.append(NumElts, DAG.getUNDEF(SVT));
16898 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
16899 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
16900 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
16901 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
16902 DAG.getIntPtrConstant(0));
16905 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
16906 Subtarget->hasMMX() && "Unexpected custom BITCAST");
16907 assert((DstVT == MVT::i64 ||
16908 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
16909 "Unexpected custom BITCAST");
16910 // i64 <=> MMX conversions are Legal.
16911 if (SrcVT==MVT::i64 && DstVT.isVector())
16913 if (DstVT==MVT::i64 && SrcVT.isVector())
16915 // MMX <=> MMX conversions are Legal.
16916 if (SrcVT.isVector() && DstVT.isVector())
16918 // All other conversions need to be expanded.
16922 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
16923 SelectionDAG &DAG) {
16924 SDNode *Node = Op.getNode();
16927 Op = Op.getOperand(0);
16928 EVT VT = Op.getValueType();
16929 assert((VT.is128BitVector() || VT.is256BitVector()) &&
16930 "CTPOP lowering only implemented for 128/256-bit wide vector types");
16932 unsigned NumElts = VT.getVectorNumElements();
16933 EVT EltVT = VT.getVectorElementType();
16934 unsigned Len = EltVT.getSizeInBits();
16936 // This is the vectorized version of the "best" algorithm from
16937 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
16938 // with a minor tweak to use a series of adds + shifts instead of vector
16939 // multiplications. Implemented for the v2i64, v4i64, v4i32, v8i32 types:
16941 // v2i64, v4i64, v4i32 => Only profitable w/ popcnt disabled
16942 // v8i32 => Always profitable
16944 // FIXME: There a couple of possible improvements:
16946 // 1) Support for i8 and i16 vectors (needs measurements if popcnt enabled).
16947 // 2) Use strategies from http://wm.ite.pl/articles/sse-popcount.html
16949 assert(EltVT.isInteger() && (Len == 32 || Len == 64) && Len % 8 == 0 &&
16950 "CTPOP not implemented for this vector element type.");
16952 // X86 canonicalize ANDs to vXi64, generate the appropriate bitcasts to avoid
16953 // extra legalization.
16954 bool NeedsBitcast = EltVT == MVT::i32;
16955 MVT BitcastVT = VT.is256BitVector() ? MVT::v4i64 : MVT::v2i64;
16957 SDValue Cst55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), EltVT);
16958 SDValue Cst33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), EltVT);
16959 SDValue Cst0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), EltVT);
16961 // v = v - ((v >> 1) & 0x55555555...)
16962 SmallVector<SDValue, 8> Ones(NumElts, DAG.getConstant(1, EltVT));
16963 SDValue OnesV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ones);
16964 SDValue Srl = DAG.getNode(ISD::SRL, dl, VT, Op, OnesV);
16966 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
16968 SmallVector<SDValue, 8> Mask55(NumElts, Cst55);
16969 SDValue M55 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask55);
16971 M55 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M55);
16973 SDValue And = DAG.getNode(ISD::AND, dl, Srl.getValueType(), Srl, M55);
16974 if (VT != And.getValueType())
16975 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
16976 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Op, And);
16978 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
16979 SmallVector<SDValue, 8> Mask33(NumElts, Cst33);
16980 SDValue M33 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask33);
16981 SmallVector<SDValue, 8> Twos(NumElts, DAG.getConstant(2, EltVT));
16982 SDValue TwosV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Twos);
16984 Srl = DAG.getNode(ISD::SRL, dl, VT, Sub, TwosV);
16985 if (NeedsBitcast) {
16986 Srl = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Srl);
16987 M33 = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M33);
16988 Sub = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Sub);
16991 SDValue AndRHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Srl, M33);
16992 SDValue AndLHS = DAG.getNode(ISD::AND, dl, M33.getValueType(), Sub, M33);
16993 if (VT != AndRHS.getValueType()) {
16994 AndRHS = DAG.getNode(ISD::BITCAST, dl, VT, AndRHS);
16995 AndLHS = DAG.getNode(ISD::BITCAST, dl, VT, AndLHS);
16997 SDValue Add = DAG.getNode(ISD::ADD, dl, VT, AndLHS, AndRHS);
16999 // v = (v + (v >> 4)) & 0x0F0F0F0F...
17000 SmallVector<SDValue, 8> Fours(NumElts, DAG.getConstant(4, EltVT));
17001 SDValue FoursV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Fours);
17002 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, FoursV);
17003 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
17005 SmallVector<SDValue, 8> Mask0F(NumElts, Cst0F);
17006 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask0F);
17007 if (NeedsBitcast) {
17008 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
17009 M0F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M0F);
17011 And = DAG.getNode(ISD::AND, dl, M0F.getValueType(), Add, M0F);
17012 if (VT != And.getValueType())
17013 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
17015 // The algorithm mentioned above uses:
17016 // v = (v * 0x01010101...) >> (Len - 8)
17018 // Change it to use vector adds + vector shifts which yield faster results on
17019 // Haswell than using vector integer multiplication.
17021 // For i32 elements:
17022 // v = v + (v >> 8)
17023 // v = v + (v >> 16)
17025 // For i64 elements:
17026 // v = v + (v >> 8)
17027 // v = v + (v >> 16)
17028 // v = v + (v >> 32)
17031 SmallVector<SDValue, 8> Csts;
17032 for (unsigned i = 8; i <= Len/2; i *= 2) {
17033 Csts.assign(NumElts, DAG.getConstant(i, EltVT));
17034 SDValue CstsV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Csts);
17035 Srl = DAG.getNode(ISD::SRL, dl, VT, Add, CstsV);
17036 Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);
17040 // The result is on the least significant 6-bits on i32 and 7-bits on i64.
17041 SDValue Cst3F = DAG.getConstant(APInt(Len, Len == 32 ? 0x3F : 0x7F), EltVT);
17042 SmallVector<SDValue, 8> Cst3FV(NumElts, Cst3F);
17043 SDValue M3F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Cst3FV);
17044 if (NeedsBitcast) {
17045 Add = DAG.getNode(ISD::BITCAST, dl, BitcastVT, Add);
17046 M3F = DAG.getNode(ISD::BITCAST, dl, BitcastVT, M3F);
17048 And = DAG.getNode(ISD::AND, dl, M3F.getValueType(), Add, M3F);
17049 if (VT != And.getValueType())
17050 And = DAG.getNode(ISD::BITCAST, dl, VT, And);
17055 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
17056 SDNode *Node = Op.getNode();
17058 EVT T = Node->getValueType(0);
17059 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
17060 DAG.getConstant(0, T), Node->getOperand(2));
17061 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
17062 cast<AtomicSDNode>(Node)->getMemoryVT(),
17063 Node->getOperand(0),
17064 Node->getOperand(1), negOp,
17065 cast<AtomicSDNode>(Node)->getMemOperand(),
17066 cast<AtomicSDNode>(Node)->getOrdering(),
17067 cast<AtomicSDNode>(Node)->getSynchScope());
17070 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
17071 SDNode *Node = Op.getNode();
17073 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17075 // Convert seq_cst store -> xchg
17076 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
17077 // FIXME: On 32-bit, store -> fist or movq would be more efficient
17078 // (The only way to get a 16-byte store is cmpxchg16b)
17079 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
17080 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
17081 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
17082 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
17083 cast<AtomicSDNode>(Node)->getMemoryVT(),
17084 Node->getOperand(0),
17085 Node->getOperand(1), Node->getOperand(2),
17086 cast<AtomicSDNode>(Node)->getMemOperand(),
17087 cast<AtomicSDNode>(Node)->getOrdering(),
17088 cast<AtomicSDNode>(Node)->getSynchScope());
17089 return Swap.getValue(1);
17091 // Other atomic stores have a simple pattern.
17095 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
17096 EVT VT = Op.getNode()->getSimpleValueType(0);
17098 // Let legalize expand this if it isn't a legal type yet.
17099 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
17102 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17105 bool ExtraOp = false;
17106 switch (Op.getOpcode()) {
17107 default: llvm_unreachable("Invalid code");
17108 case ISD::ADDC: Opc = X86ISD::ADD; break;
17109 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
17110 case ISD::SUBC: Opc = X86ISD::SUB; break;
17111 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
17115 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17117 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17118 Op.getOperand(1), Op.getOperand(2));
17121 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
17122 SelectionDAG &DAG) {
17123 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
17125 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
17126 // which returns the values as { float, float } (in XMM0) or
17127 // { double, double } (which is returned in XMM0, XMM1).
17129 SDValue Arg = Op.getOperand(0);
17130 EVT ArgVT = Arg.getValueType();
17131 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17133 TargetLowering::ArgListTy Args;
17134 TargetLowering::ArgListEntry Entry;
17138 Entry.isSExt = false;
17139 Entry.isZExt = false;
17140 Args.push_back(Entry);
17142 bool isF64 = ArgVT == MVT::f64;
17143 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
17144 // the small struct {f32, f32} is returned in (eax, edx). For f64,
17145 // the results are returned via SRet in memory.
17146 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
17147 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17148 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
17150 Type *RetTy = isF64
17151 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
17152 : (Type*)VectorType::get(ArgTy, 4);
17154 TargetLowering::CallLoweringInfo CLI(DAG);
17155 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
17156 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
17158 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
17161 // Returned in xmm0 and xmm1.
17162 return CallResult.first;
17164 // Returned in bits 0:31 and 32:64 xmm0.
17165 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17166 CallResult.first, DAG.getIntPtrConstant(0));
17167 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17168 CallResult.first, DAG.getIntPtrConstant(1));
17169 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
17170 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
17173 /// LowerOperation - Provide custom lowering hooks for some operations.
17175 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
17176 switch (Op.getOpcode()) {
17177 default: llvm_unreachable("Should not custom lower this!");
17178 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
17179 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
17180 return LowerCMP_SWAP(Op, Subtarget, DAG);
17181 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
17182 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
17183 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
17184 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
17185 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
17186 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
17187 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
17188 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
17189 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
17190 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
17191 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
17192 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
17193 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
17194 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
17195 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
17196 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
17197 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
17198 case ISD::SHL_PARTS:
17199 case ISD::SRA_PARTS:
17200 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
17201 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
17202 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
17203 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
17204 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
17205 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
17206 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
17207 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
17208 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
17209 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
17210 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
17212 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
17213 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
17214 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
17215 case ISD::SETCC: return LowerSETCC(Op, DAG);
17216 case ISD::SELECT: return LowerSELECT(Op, DAG);
17217 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
17218 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
17219 case ISD::VASTART: return LowerVASTART(Op, DAG);
17220 case ISD::VAARG: return LowerVAARG(Op, DAG);
17221 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
17222 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
17223 case ISD::INTRINSIC_VOID:
17224 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
17225 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
17226 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
17227 case ISD::FRAME_TO_ARGS_OFFSET:
17228 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
17229 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
17230 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
17231 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
17232 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
17233 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
17234 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
17235 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
17236 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
17237 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
17238 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
17239 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
17240 case ISD::UMUL_LOHI:
17241 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
17244 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
17250 case ISD::UMULO: return LowerXALUO(Op, DAG);
17251 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
17252 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
17256 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
17257 case ISD::ADD: return LowerADD(Op, DAG);
17258 case ISD::SUB: return LowerSUB(Op, DAG);
17259 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
17263 /// ReplaceNodeResults - Replace a node with an illegal result type
17264 /// with a new node built out of custom code.
17265 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
17266 SmallVectorImpl<SDValue>&Results,
17267 SelectionDAG &DAG) const {
17269 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17270 switch (N->getOpcode()) {
17272 llvm_unreachable("Do not know how to custom type legalize this operation!");
17273 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
17274 case X86ISD::FMINC:
17276 case X86ISD::FMAXC:
17277 case X86ISD::FMAX: {
17278 EVT VT = N->getValueType(0);
17279 if (VT != MVT::v2f32)
17280 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
17281 SDValue UNDEF = DAG.getUNDEF(VT);
17282 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
17283 N->getOperand(0), UNDEF);
17284 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
17285 N->getOperand(1), UNDEF);
17286 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
17289 case ISD::SIGN_EXTEND_INREG:
17294 // We don't want to expand or promote these.
17301 case ISD::UDIVREM: {
17302 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
17303 Results.push_back(V);
17306 case ISD::FP_TO_SINT:
17307 case ISD::FP_TO_UINT: {
17308 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
17310 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
17313 std::pair<SDValue,SDValue> Vals =
17314 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
17315 SDValue FIST = Vals.first, StackSlot = Vals.second;
17316 if (FIST.getNode()) {
17317 EVT VT = N->getValueType(0);
17318 // Return a load from the stack slot.
17319 if (StackSlot.getNode())
17320 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
17321 MachinePointerInfo(),
17322 false, false, false, 0));
17324 Results.push_back(FIST);
17328 case ISD::UINT_TO_FP: {
17329 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17330 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
17331 N->getValueType(0) != MVT::v2f32)
17333 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
17335 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
17337 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
17338 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
17339 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
17340 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
17341 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
17342 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
17345 case ISD::FP_ROUND: {
17346 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
17348 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
17349 Results.push_back(V);
17352 case ISD::INTRINSIC_W_CHAIN: {
17353 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
17355 default : llvm_unreachable("Do not know how to custom type "
17356 "legalize this intrinsic operation!");
17357 case Intrinsic::x86_rdtsc:
17358 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17360 case Intrinsic::x86_rdtscp:
17361 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
17363 case Intrinsic::x86_rdpmc:
17364 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
17367 case ISD::READCYCLECOUNTER: {
17368 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
17371 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
17372 EVT T = N->getValueType(0);
17373 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
17374 bool Regs64bit = T == MVT::i128;
17375 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
17376 SDValue cpInL, cpInH;
17377 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17378 DAG.getConstant(0, HalfT));
17379 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
17380 DAG.getConstant(1, HalfT));
17381 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
17382 Regs64bit ? X86::RAX : X86::EAX,
17384 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
17385 Regs64bit ? X86::RDX : X86::EDX,
17386 cpInH, cpInL.getValue(1));
17387 SDValue swapInL, swapInH;
17388 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17389 DAG.getConstant(0, HalfT));
17390 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
17391 DAG.getConstant(1, HalfT));
17392 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
17393 Regs64bit ? X86::RBX : X86::EBX,
17394 swapInL, cpInH.getValue(1));
17395 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
17396 Regs64bit ? X86::RCX : X86::ECX,
17397 swapInH, swapInL.getValue(1));
17398 SDValue Ops[] = { swapInH.getValue(0),
17400 swapInH.getValue(1) };
17401 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17402 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
17403 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
17404 X86ISD::LCMPXCHG8_DAG;
17405 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
17406 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
17407 Regs64bit ? X86::RAX : X86::EAX,
17408 HalfT, Result.getValue(1));
17409 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
17410 Regs64bit ? X86::RDX : X86::EDX,
17411 HalfT, cpOutL.getValue(2));
17412 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
17414 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
17415 MVT::i32, cpOutH.getValue(2));
17417 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17418 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
17419 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
17421 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
17422 Results.push_back(Success);
17423 Results.push_back(EFLAGS.getValue(1));
17426 case ISD::ATOMIC_SWAP:
17427 case ISD::ATOMIC_LOAD_ADD:
17428 case ISD::ATOMIC_LOAD_SUB:
17429 case ISD::ATOMIC_LOAD_AND:
17430 case ISD::ATOMIC_LOAD_OR:
17431 case ISD::ATOMIC_LOAD_XOR:
17432 case ISD::ATOMIC_LOAD_NAND:
17433 case ISD::ATOMIC_LOAD_MIN:
17434 case ISD::ATOMIC_LOAD_MAX:
17435 case ISD::ATOMIC_LOAD_UMIN:
17436 case ISD::ATOMIC_LOAD_UMAX:
17437 case ISD::ATOMIC_LOAD: {
17438 // Delegate to generic TypeLegalization. Situations we can really handle
17439 // should have already been dealt with by AtomicExpandPass.cpp.
17442 case ISD::BITCAST: {
17443 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17444 EVT DstVT = N->getValueType(0);
17445 EVT SrcVT = N->getOperand(0)->getValueType(0);
17447 if (SrcVT != MVT::f64 ||
17448 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
17451 unsigned NumElts = DstVT.getVectorNumElements();
17452 EVT SVT = DstVT.getVectorElementType();
17453 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17454 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
17455 MVT::v2f64, N->getOperand(0));
17456 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
17458 if (ExperimentalVectorWideningLegalization) {
17459 // If we are legalizing vectors by widening, we already have the desired
17460 // legal vector type, just return it.
17461 Results.push_back(ToVecInt);
17465 SmallVector<SDValue, 8> Elts;
17466 for (unsigned i = 0, e = NumElts; i != e; ++i)
17467 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
17468 ToVecInt, DAG.getIntPtrConstant(i)));
17470 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
17475 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
17477 default: return nullptr;
17478 case X86ISD::BSF: return "X86ISD::BSF";
17479 case X86ISD::BSR: return "X86ISD::BSR";
17480 case X86ISD::SHLD: return "X86ISD::SHLD";
17481 case X86ISD::SHRD: return "X86ISD::SHRD";
17482 case X86ISD::FAND: return "X86ISD::FAND";
17483 case X86ISD::FANDN: return "X86ISD::FANDN";
17484 case X86ISD::FOR: return "X86ISD::FOR";
17485 case X86ISD::FXOR: return "X86ISD::FXOR";
17486 case X86ISD::FSRL: return "X86ISD::FSRL";
17487 case X86ISD::FILD: return "X86ISD::FILD";
17488 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
17489 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
17490 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
17491 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
17492 case X86ISD::FLD: return "X86ISD::FLD";
17493 case X86ISD::FST: return "X86ISD::FST";
17494 case X86ISD::CALL: return "X86ISD::CALL";
17495 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
17496 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
17497 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
17498 case X86ISD::BT: return "X86ISD::BT";
17499 case X86ISD::CMP: return "X86ISD::CMP";
17500 case X86ISD::COMI: return "X86ISD::COMI";
17501 case X86ISD::UCOMI: return "X86ISD::UCOMI";
17502 case X86ISD::CMPM: return "X86ISD::CMPM";
17503 case X86ISD::CMPMU: return "X86ISD::CMPMU";
17504 case X86ISD::SETCC: return "X86ISD::SETCC";
17505 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
17506 case X86ISD::FSETCC: return "X86ISD::FSETCC";
17507 case X86ISD::CMOV: return "X86ISD::CMOV";
17508 case X86ISD::BRCOND: return "X86ISD::BRCOND";
17509 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
17510 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
17511 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
17512 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
17513 case X86ISD::Wrapper: return "X86ISD::Wrapper";
17514 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
17515 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
17516 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
17517 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
17518 case X86ISD::PINSRB: return "X86ISD::PINSRB";
17519 case X86ISD::PINSRW: return "X86ISD::PINSRW";
17520 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
17521 case X86ISD::ANDNP: return "X86ISD::ANDNP";
17522 case X86ISD::PSIGN: return "X86ISD::PSIGN";
17523 case X86ISD::BLENDI: return "X86ISD::BLENDI";
17524 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
17525 case X86ISD::SUBUS: return "X86ISD::SUBUS";
17526 case X86ISD::HADD: return "X86ISD::HADD";
17527 case X86ISD::HSUB: return "X86ISD::HSUB";
17528 case X86ISD::FHADD: return "X86ISD::FHADD";
17529 case X86ISD::FHSUB: return "X86ISD::FHSUB";
17530 case X86ISD::UMAX: return "X86ISD::UMAX";
17531 case X86ISD::UMIN: return "X86ISD::UMIN";
17532 case X86ISD::SMAX: return "X86ISD::SMAX";
17533 case X86ISD::SMIN: return "X86ISD::SMIN";
17534 case X86ISD::FMAX: return "X86ISD::FMAX";
17535 case X86ISD::FMIN: return "X86ISD::FMIN";
17536 case X86ISD::FMAXC: return "X86ISD::FMAXC";
17537 case X86ISD::FMINC: return "X86ISD::FMINC";
17538 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
17539 case X86ISD::FRCP: return "X86ISD::FRCP";
17540 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
17541 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
17542 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
17543 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
17544 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
17545 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
17546 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
17547 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
17548 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
17549 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
17550 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
17551 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
17552 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
17553 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
17554 case X86ISD::VZEXT: return "X86ISD::VZEXT";
17555 case X86ISD::VSEXT: return "X86ISD::VSEXT";
17556 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
17557 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
17558 case X86ISD::VINSERT: return "X86ISD::VINSERT";
17559 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
17560 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
17561 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
17562 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
17563 case X86ISD::VSHL: return "X86ISD::VSHL";
17564 case X86ISD::VSRL: return "X86ISD::VSRL";
17565 case X86ISD::VSRA: return "X86ISD::VSRA";
17566 case X86ISD::VSHLI: return "X86ISD::VSHLI";
17567 case X86ISD::VSRLI: return "X86ISD::VSRLI";
17568 case X86ISD::VSRAI: return "X86ISD::VSRAI";
17569 case X86ISD::CMPP: return "X86ISD::CMPP";
17570 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
17571 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
17572 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
17573 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
17574 case X86ISD::ADD: return "X86ISD::ADD";
17575 case X86ISD::SUB: return "X86ISD::SUB";
17576 case X86ISD::ADC: return "X86ISD::ADC";
17577 case X86ISD::SBB: return "X86ISD::SBB";
17578 case X86ISD::SMUL: return "X86ISD::SMUL";
17579 case X86ISD::UMUL: return "X86ISD::UMUL";
17580 case X86ISD::SMUL8: return "X86ISD::SMUL8";
17581 case X86ISD::UMUL8: return "X86ISD::UMUL8";
17582 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
17583 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
17584 case X86ISD::INC: return "X86ISD::INC";
17585 case X86ISD::DEC: return "X86ISD::DEC";
17586 case X86ISD::OR: return "X86ISD::OR";
17587 case X86ISD::XOR: return "X86ISD::XOR";
17588 case X86ISD::AND: return "X86ISD::AND";
17589 case X86ISD::BEXTR: return "X86ISD::BEXTR";
17590 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
17591 case X86ISD::PTEST: return "X86ISD::PTEST";
17592 case X86ISD::TESTP: return "X86ISD::TESTP";
17593 case X86ISD::TESTM: return "X86ISD::TESTM";
17594 case X86ISD::TESTNM: return "X86ISD::TESTNM";
17595 case X86ISD::KORTEST: return "X86ISD::KORTEST";
17596 case X86ISD::PACKSS: return "X86ISD::PACKSS";
17597 case X86ISD::PACKUS: return "X86ISD::PACKUS";
17598 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
17599 case X86ISD::VALIGN: return "X86ISD::VALIGN";
17600 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
17601 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
17602 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
17603 case X86ISD::SHUFP: return "X86ISD::SHUFP";
17604 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
17605 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
17606 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
17607 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
17608 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
17609 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
17610 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
17611 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
17612 case X86ISD::MOVSD: return "X86ISD::MOVSD";
17613 case X86ISD::MOVSS: return "X86ISD::MOVSS";
17614 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
17615 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
17616 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
17617 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
17618 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
17619 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
17620 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
17621 case X86ISD::VPERMV: return "X86ISD::VPERMV";
17622 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
17623 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
17624 case X86ISD::VPERMI: return "X86ISD::VPERMI";
17625 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
17626 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
17627 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
17628 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
17629 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
17630 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
17631 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
17632 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
17633 case X86ISD::SAHF: return "X86ISD::SAHF";
17634 case X86ISD::RDRAND: return "X86ISD::RDRAND";
17635 case X86ISD::RDSEED: return "X86ISD::RDSEED";
17636 case X86ISD::FMADD: return "X86ISD::FMADD";
17637 case X86ISD::FMSUB: return "X86ISD::FMSUB";
17638 case X86ISD::FNMADD: return "X86ISD::FNMADD";
17639 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
17640 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
17641 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
17642 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
17643 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
17644 case X86ISD::XTEST: return "X86ISD::XTEST";
17645 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
17646 case X86ISD::EXPAND: return "X86ISD::EXPAND";
17647 case X86ISD::SELECT: return "X86ISD::SELECT";
17648 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
17649 case X86ISD::RCP28: return "X86ISD::RCP28";
17650 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
17651 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
17652 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
17653 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
17654 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
17658 // isLegalAddressingMode - Return true if the addressing mode represented
17659 // by AM is legal for this target, for a load/store of the specified type.
17660 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
17662 // X86 supports extremely general addressing modes.
17663 CodeModel::Model M = getTargetMachine().getCodeModel();
17664 Reloc::Model R = getTargetMachine().getRelocationModel();
17666 // X86 allows a sign-extended 32-bit immediate field as a displacement.
17667 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
17672 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
17674 // If a reference to this global requires an extra load, we can't fold it.
17675 if (isGlobalStubReference(GVFlags))
17678 // If BaseGV requires a register for the PIC base, we cannot also have a
17679 // BaseReg specified.
17680 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
17683 // If lower 4G is not available, then we must use rip-relative addressing.
17684 if ((M != CodeModel::Small || R != Reloc::Static) &&
17685 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
17689 switch (AM.Scale) {
17695 // These scales always work.
17700 // These scales are formed with basereg+scalereg. Only accept if there is
17705 default: // Other stuff never works.
17712 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
17713 unsigned Bits = Ty->getScalarSizeInBits();
17715 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
17716 // particularly cheaper than those without.
17720 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
17721 // variable shifts just as cheap as scalar ones.
17722 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
17725 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
17726 // fully general vector.
17730 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
17731 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
17733 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
17734 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
17735 return NumBits1 > NumBits2;
17738 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
17739 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
17742 if (!isTypeLegal(EVT::getEVT(Ty1)))
17745 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
17747 // Assuming the caller doesn't have a zeroext or signext return parameter,
17748 // truncation all the way down to i1 is valid.
17752 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
17753 return isInt<32>(Imm);
17756 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
17757 // Can also use sub to handle negated immediates.
17758 return isInt<32>(Imm);
17761 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
17762 if (!VT1.isInteger() || !VT2.isInteger())
17764 unsigned NumBits1 = VT1.getSizeInBits();
17765 unsigned NumBits2 = VT2.getSizeInBits();
17766 return NumBits1 > NumBits2;
17769 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
17770 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
17771 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
17774 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
17775 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
17776 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
17779 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
17780 EVT VT1 = Val.getValueType();
17781 if (isZExtFree(VT1, VT2))
17784 if (Val.getOpcode() != ISD::LOAD)
17787 if (!VT1.isSimple() || !VT1.isInteger() ||
17788 !VT2.isSimple() || !VT2.isInteger())
17791 switch (VT1.getSimpleVT().SimpleTy) {
17796 // X86 has 8, 16, and 32-bit zero-extending loads.
17803 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
17806 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
17807 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
17810 VT = VT.getScalarType();
17812 if (!VT.isSimple())
17815 switch (VT.getSimpleVT().SimpleTy) {
17826 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
17827 // i16 instructions are longer (0x66 prefix) and potentially slower.
17828 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
17831 /// isShuffleMaskLegal - Targets can use this to indicate that they only
17832 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
17833 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
17834 /// are assumed to be legal.
17836 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
17838 if (!VT.isSimple())
17841 // Very little shuffling can be done for 64-bit vectors right now.
17842 if (VT.getSizeInBits() == 64)
17845 // We only care that the types being shuffled are legal. The lowering can
17846 // handle any possible shuffle mask that results.
17847 return isTypeLegal(VT.getSimpleVT());
17851 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
17853 // Just delegate to the generic legality, clear masks aren't special.
17854 return isShuffleMaskLegal(Mask, VT);
17857 //===----------------------------------------------------------------------===//
17858 // X86 Scheduler Hooks
17859 //===----------------------------------------------------------------------===//
17861 /// Utility function to emit xbegin specifying the start of an RTM region.
17862 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
17863 const TargetInstrInfo *TII) {
17864 DebugLoc DL = MI->getDebugLoc();
17866 const BasicBlock *BB = MBB->getBasicBlock();
17867 MachineFunction::iterator I = MBB;
17870 // For the v = xbegin(), we generate
17881 MachineBasicBlock *thisMBB = MBB;
17882 MachineFunction *MF = MBB->getParent();
17883 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
17884 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
17885 MF->insert(I, mainMBB);
17886 MF->insert(I, sinkMBB);
17888 // Transfer the remainder of BB and its successor edges to sinkMBB.
17889 sinkMBB->splice(sinkMBB->begin(), MBB,
17890 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
17891 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
17895 // # fallthrough to mainMBB
17896 // # abortion to sinkMBB
17897 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
17898 thisMBB->addSuccessor(mainMBB);
17899 thisMBB->addSuccessor(sinkMBB);
17903 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
17904 mainMBB->addSuccessor(sinkMBB);
17907 // EAX is live into the sinkMBB
17908 sinkMBB->addLiveIn(X86::EAX);
17909 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
17910 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17913 MI->eraseFromParent();
17917 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
17918 // or XMM0_V32I8 in AVX all of this code can be replaced with that
17919 // in the .td file.
17920 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
17921 const TargetInstrInfo *TII) {
17923 switch (MI->getOpcode()) {
17924 default: llvm_unreachable("illegal opcode!");
17925 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
17926 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
17927 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
17928 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
17929 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
17930 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
17931 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
17932 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
17935 DebugLoc dl = MI->getDebugLoc();
17936 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
17938 unsigned NumArgs = MI->getNumOperands();
17939 for (unsigned i = 1; i < NumArgs; ++i) {
17940 MachineOperand &Op = MI->getOperand(i);
17941 if (!(Op.isReg() && Op.isImplicit()))
17942 MIB.addOperand(Op);
17944 if (MI->hasOneMemOperand())
17945 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
17947 BuildMI(*BB, MI, dl,
17948 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17949 .addReg(X86::XMM0);
17951 MI->eraseFromParent();
17955 // FIXME: Custom handling because TableGen doesn't support multiple implicit
17956 // defs in an instruction pattern
17957 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
17958 const TargetInstrInfo *TII) {
17960 switch (MI->getOpcode()) {
17961 default: llvm_unreachable("illegal opcode!");
17962 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
17963 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
17964 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
17965 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
17966 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
17967 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
17968 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
17969 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
17972 DebugLoc dl = MI->getDebugLoc();
17973 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
17975 unsigned NumArgs = MI->getNumOperands(); // remove the results
17976 for (unsigned i = 1; i < NumArgs; ++i) {
17977 MachineOperand &Op = MI->getOperand(i);
17978 if (!(Op.isReg() && Op.isImplicit()))
17979 MIB.addOperand(Op);
17981 if (MI->hasOneMemOperand())
17982 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
17984 BuildMI(*BB, MI, dl,
17985 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17988 MI->eraseFromParent();
17992 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
17993 const X86Subtarget *Subtarget) {
17994 DebugLoc dl = MI->getDebugLoc();
17995 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
17996 // Address into RAX/EAX, other two args into ECX, EDX.
17997 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
17998 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
17999 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
18000 for (int i = 0; i < X86::AddrNumOperands; ++i)
18001 MIB.addOperand(MI->getOperand(i));
18003 unsigned ValOps = X86::AddrNumOperands;
18004 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
18005 .addReg(MI->getOperand(ValOps).getReg());
18006 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
18007 .addReg(MI->getOperand(ValOps+1).getReg());
18009 // The instruction doesn't actually take any operands though.
18010 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
18012 MI->eraseFromParent(); // The pseudo is gone now.
18016 MachineBasicBlock *
18017 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
18018 MachineBasicBlock *MBB) const {
18019 // Emit va_arg instruction on X86-64.
18021 // Operands to this pseudo-instruction:
18022 // 0 ) Output : destination address (reg)
18023 // 1-5) Input : va_list address (addr, i64mem)
18024 // 6 ) ArgSize : Size (in bytes) of vararg type
18025 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
18026 // 8 ) Align : Alignment of type
18027 // 9 ) EFLAGS (implicit-def)
18029 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
18030 static_assert(X86::AddrNumOperands == 5,
18031 "VAARG_64 assumes 5 address operands");
18033 unsigned DestReg = MI->getOperand(0).getReg();
18034 MachineOperand &Base = MI->getOperand(1);
18035 MachineOperand &Scale = MI->getOperand(2);
18036 MachineOperand &Index = MI->getOperand(3);
18037 MachineOperand &Disp = MI->getOperand(4);
18038 MachineOperand &Segment = MI->getOperand(5);
18039 unsigned ArgSize = MI->getOperand(6).getImm();
18040 unsigned ArgMode = MI->getOperand(7).getImm();
18041 unsigned Align = MI->getOperand(8).getImm();
18043 // Memory Reference
18044 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
18045 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18046 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18048 // Machine Information
18049 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18050 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
18051 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
18052 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
18053 DebugLoc DL = MI->getDebugLoc();
18055 // struct va_list {
18058 // i64 overflow_area (address)
18059 // i64 reg_save_area (address)
18061 // sizeof(va_list) = 24
18062 // alignment(va_list) = 8
18064 unsigned TotalNumIntRegs = 6;
18065 unsigned TotalNumXMMRegs = 8;
18066 bool UseGPOffset = (ArgMode == 1);
18067 bool UseFPOffset = (ArgMode == 2);
18068 unsigned MaxOffset = TotalNumIntRegs * 8 +
18069 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
18071 /* Align ArgSize to a multiple of 8 */
18072 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
18073 bool NeedsAlign = (Align > 8);
18075 MachineBasicBlock *thisMBB = MBB;
18076 MachineBasicBlock *overflowMBB;
18077 MachineBasicBlock *offsetMBB;
18078 MachineBasicBlock *endMBB;
18080 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
18081 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
18082 unsigned OffsetReg = 0;
18084 if (!UseGPOffset && !UseFPOffset) {
18085 // If we only pull from the overflow region, we don't create a branch.
18086 // We don't need to alter control flow.
18087 OffsetDestReg = 0; // unused
18088 OverflowDestReg = DestReg;
18090 offsetMBB = nullptr;
18091 overflowMBB = thisMBB;
18094 // First emit code to check if gp_offset (or fp_offset) is below the bound.
18095 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
18096 // If not, pull from overflow_area. (branch to overflowMBB)
18101 // offsetMBB overflowMBB
18106 // Registers for the PHI in endMBB
18107 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
18108 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
18110 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18111 MachineFunction *MF = MBB->getParent();
18112 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18113 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18114 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18116 MachineFunction::iterator MBBIter = MBB;
18119 // Insert the new basic blocks
18120 MF->insert(MBBIter, offsetMBB);
18121 MF->insert(MBBIter, overflowMBB);
18122 MF->insert(MBBIter, endMBB);
18124 // Transfer the remainder of MBB and its successor edges to endMBB.
18125 endMBB->splice(endMBB->begin(), thisMBB,
18126 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
18127 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
18129 // Make offsetMBB and overflowMBB successors of thisMBB
18130 thisMBB->addSuccessor(offsetMBB);
18131 thisMBB->addSuccessor(overflowMBB);
18133 // endMBB is a successor of both offsetMBB and overflowMBB
18134 offsetMBB->addSuccessor(endMBB);
18135 overflowMBB->addSuccessor(endMBB);
18137 // Load the offset value into a register
18138 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18139 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
18143 .addDisp(Disp, UseFPOffset ? 4 : 0)
18144 .addOperand(Segment)
18145 .setMemRefs(MMOBegin, MMOEnd);
18147 // Check if there is enough room left to pull this argument.
18148 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
18150 .addImm(MaxOffset + 8 - ArgSizeA8);
18152 // Branch to "overflowMBB" if offset >= max
18153 // Fall through to "offsetMBB" otherwise
18154 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
18155 .addMBB(overflowMBB);
18158 // In offsetMBB, emit code to use the reg_save_area.
18160 assert(OffsetReg != 0);
18162 // Read the reg_save_area address.
18163 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
18164 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
18169 .addOperand(Segment)
18170 .setMemRefs(MMOBegin, MMOEnd);
18172 // Zero-extend the offset
18173 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
18174 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
18177 .addImm(X86::sub_32bit);
18179 // Add the offset to the reg_save_area to get the final address.
18180 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
18181 .addReg(OffsetReg64)
18182 .addReg(RegSaveReg);
18184 // Compute the offset for the next argument
18185 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18186 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
18188 .addImm(UseFPOffset ? 16 : 8);
18190 // Store it back into the va_list.
18191 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
18195 .addDisp(Disp, UseFPOffset ? 4 : 0)
18196 .addOperand(Segment)
18197 .addReg(NextOffsetReg)
18198 .setMemRefs(MMOBegin, MMOEnd);
18201 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
18206 // Emit code to use overflow area
18209 // Load the overflow_area address into a register.
18210 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
18211 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
18216 .addOperand(Segment)
18217 .setMemRefs(MMOBegin, MMOEnd);
18219 // If we need to align it, do so. Otherwise, just copy the address
18220 // to OverflowDestReg.
18222 // Align the overflow address
18223 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
18224 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
18226 // aligned_addr = (addr + (align-1)) & ~(align-1)
18227 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
18228 .addReg(OverflowAddrReg)
18231 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
18233 .addImm(~(uint64_t)(Align-1));
18235 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
18236 .addReg(OverflowAddrReg);
18239 // Compute the next overflow address after this argument.
18240 // (the overflow address should be kept 8-byte aligned)
18241 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
18242 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
18243 .addReg(OverflowDestReg)
18244 .addImm(ArgSizeA8);
18246 // Store the new overflow address.
18247 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
18252 .addOperand(Segment)
18253 .addReg(NextAddrReg)
18254 .setMemRefs(MMOBegin, MMOEnd);
18256 // If we branched, emit the PHI to the front of endMBB.
18258 BuildMI(*endMBB, endMBB->begin(), DL,
18259 TII->get(X86::PHI), DestReg)
18260 .addReg(OffsetDestReg).addMBB(offsetMBB)
18261 .addReg(OverflowDestReg).addMBB(overflowMBB);
18264 // Erase the pseudo instruction
18265 MI->eraseFromParent();
18270 MachineBasicBlock *
18271 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
18273 MachineBasicBlock *MBB) const {
18274 // Emit code to save XMM registers to the stack. The ABI says that the
18275 // number of registers to save is given in %al, so it's theoretically
18276 // possible to do an indirect jump trick to avoid saving all of them,
18277 // however this code takes a simpler approach and just executes all
18278 // of the stores if %al is non-zero. It's less code, and it's probably
18279 // easier on the hardware branch predictor, and stores aren't all that
18280 // expensive anyway.
18282 // Create the new basic blocks. One block contains all the XMM stores,
18283 // and one block is the final destination regardless of whether any
18284 // stores were performed.
18285 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18286 MachineFunction *F = MBB->getParent();
18287 MachineFunction::iterator MBBIter = MBB;
18289 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
18290 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
18291 F->insert(MBBIter, XMMSaveMBB);
18292 F->insert(MBBIter, EndMBB);
18294 // Transfer the remainder of MBB and its successor edges to EndMBB.
18295 EndMBB->splice(EndMBB->begin(), MBB,
18296 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18297 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
18299 // The original block will now fall through to the XMM save block.
18300 MBB->addSuccessor(XMMSaveMBB);
18301 // The XMMSaveMBB will fall through to the end block.
18302 XMMSaveMBB->addSuccessor(EndMBB);
18304 // Now add the instructions.
18305 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18306 DebugLoc DL = MI->getDebugLoc();
18308 unsigned CountReg = MI->getOperand(0).getReg();
18309 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
18310 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
18312 if (!Subtarget->isTargetWin64()) {
18313 // If %al is 0, branch around the XMM save block.
18314 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
18315 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
18316 MBB->addSuccessor(EndMBB);
18319 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
18320 // that was just emitted, but clearly shouldn't be "saved".
18321 assert((MI->getNumOperands() <= 3 ||
18322 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
18323 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
18324 && "Expected last argument to be EFLAGS");
18325 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
18326 // In the XMM save block, save all the XMM argument registers.
18327 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
18328 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
18329 MachineMemOperand *MMO =
18330 F->getMachineMemOperand(
18331 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
18332 MachineMemOperand::MOStore,
18333 /*Size=*/16, /*Align=*/16);
18334 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
18335 .addFrameIndex(RegSaveFrameIndex)
18336 .addImm(/*Scale=*/1)
18337 .addReg(/*IndexReg=*/0)
18338 .addImm(/*Disp=*/Offset)
18339 .addReg(/*Segment=*/0)
18340 .addReg(MI->getOperand(i).getReg())
18341 .addMemOperand(MMO);
18344 MI->eraseFromParent(); // The pseudo instruction is gone now.
18349 // The EFLAGS operand of SelectItr might be missing a kill marker
18350 // because there were multiple uses of EFLAGS, and ISel didn't know
18351 // which to mark. Figure out whether SelectItr should have had a
18352 // kill marker, and set it if it should. Returns the correct kill
18354 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
18355 MachineBasicBlock* BB,
18356 const TargetRegisterInfo* TRI) {
18357 // Scan forward through BB for a use/def of EFLAGS.
18358 MachineBasicBlock::iterator miI(std::next(SelectItr));
18359 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
18360 const MachineInstr& mi = *miI;
18361 if (mi.readsRegister(X86::EFLAGS))
18363 if (mi.definesRegister(X86::EFLAGS))
18364 break; // Should have kill-flag - update below.
18367 // If we hit the end of the block, check whether EFLAGS is live into a
18369 if (miI == BB->end()) {
18370 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
18371 sEnd = BB->succ_end();
18372 sItr != sEnd; ++sItr) {
18373 MachineBasicBlock* succ = *sItr;
18374 if (succ->isLiveIn(X86::EFLAGS))
18379 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
18380 // out. SelectMI should have a kill flag on EFLAGS.
18381 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
18385 MachineBasicBlock *
18386 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
18387 MachineBasicBlock *BB) const {
18388 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18389 DebugLoc DL = MI->getDebugLoc();
18391 // To "insert" a SELECT_CC instruction, we actually have to insert the
18392 // diamond control-flow pattern. The incoming instruction knows the
18393 // destination vreg to set, the condition code register to branch on, the
18394 // true/false values to select between, and a branch opcode to use.
18395 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18396 MachineFunction::iterator It = BB;
18402 // cmpTY ccX, r1, r2
18404 // fallthrough --> copy0MBB
18405 MachineBasicBlock *thisMBB = BB;
18406 MachineFunction *F = BB->getParent();
18408 // We also lower double CMOVs:
18409 // (CMOV (CMOV F, T, cc1), T, cc2)
18410 // to two successives branches. For that, we look for another CMOV as the
18411 // following instruction.
18413 // Without this, we would add a PHI between the two jumps, which ends up
18414 // creating a few copies all around. For instance, for
18416 // (sitofp (zext (fcmp une)))
18418 // we would generate:
18420 // ucomiss %xmm1, %xmm0
18421 // movss <1.0f>, %xmm0
18422 // movaps %xmm0, %xmm1
18424 // xorps %xmm1, %xmm1
18427 // movaps %xmm1, %xmm0
18431 // because this custom-inserter would have generated:
18443 // A: X = ...; Y = ...
18445 // C: Z = PHI [X, A], [Y, B]
18447 // E: PHI [X, C], [Z, D]
18449 // If we lower both CMOVs in a single step, we can instead generate:
18461 // A: X = ...; Y = ...
18463 // E: PHI [X, A], [X, C], [Y, D]
18465 // Which, in our sitofp/fcmp example, gives us something like:
18467 // ucomiss %xmm1, %xmm0
18468 // movss <1.0f>, %xmm0
18471 // xorps %xmm0, %xmm0
18475 MachineInstr *NextCMOV = nullptr;
18476 MachineBasicBlock::iterator NextMIIt =
18477 std::next(MachineBasicBlock::iterator(MI));
18478 if (NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
18479 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
18480 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg())
18481 NextCMOV = &*NextMIIt;
18483 MachineBasicBlock *jcc1MBB = nullptr;
18485 // If we have a double CMOV, we lower it to two successive branches to
18486 // the same block. EFLAGS is used by both, so mark it as live in the second.
18488 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
18489 F->insert(It, jcc1MBB);
18490 jcc1MBB->addLiveIn(X86::EFLAGS);
18493 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
18494 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
18495 F->insert(It, copy0MBB);
18496 F->insert(It, sinkMBB);
18498 // If the EFLAGS register isn't dead in the terminator, then claim that it's
18499 // live into the sink and copy blocks.
18500 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
18502 MachineInstr *LastEFLAGSUser = NextCMOV ? NextCMOV : MI;
18503 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
18504 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
18505 copy0MBB->addLiveIn(X86::EFLAGS);
18506 sinkMBB->addLiveIn(X86::EFLAGS);
18509 // Transfer the remainder of BB and its successor edges to sinkMBB.
18510 sinkMBB->splice(sinkMBB->begin(), BB,
18511 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18512 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
18514 // Add the true and fallthrough blocks as its successors.
18516 // The fallthrough block may be jcc1MBB, if we have a double CMOV.
18517 BB->addSuccessor(jcc1MBB);
18519 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
18520 // jump to the sinkMBB.
18521 jcc1MBB->addSuccessor(copy0MBB);
18522 jcc1MBB->addSuccessor(sinkMBB);
18524 BB->addSuccessor(copy0MBB);
18527 // The true block target of the first (or only) branch is always sinkMBB.
18528 BB->addSuccessor(sinkMBB);
18530 // Create the conditional branch instruction.
18532 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
18533 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
18536 unsigned Opc2 = X86::GetCondBranchFromCond(
18537 (X86::CondCode)NextCMOV->getOperand(3).getImm());
18538 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
18542 // %FalseValue = ...
18543 // # fallthrough to sinkMBB
18544 copy0MBB->addSuccessor(sinkMBB);
18547 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
18549 MachineInstrBuilder MIB =
18550 BuildMI(*sinkMBB, sinkMBB->begin(), DL, TII->get(X86::PHI),
18551 MI->getOperand(0).getReg())
18552 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
18553 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
18555 // If we have a double CMOV, the second Jcc provides the same incoming
18556 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
18558 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
18559 // Copy the PHI result to the register defined by the second CMOV.
18560 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
18561 DL, TII->get(TargetOpcode::COPY), NextCMOV->getOperand(0).getReg())
18562 .addReg(MI->getOperand(0).getReg());
18563 NextCMOV->eraseFromParent();
18566 MI->eraseFromParent(); // The pseudo instruction is gone now.
18570 MachineBasicBlock *
18571 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
18572 MachineBasicBlock *BB) const {
18573 MachineFunction *MF = BB->getParent();
18574 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18575 DebugLoc DL = MI->getDebugLoc();
18576 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18578 assert(MF->shouldSplitStack());
18580 const bool Is64Bit = Subtarget->is64Bit();
18581 const bool IsLP64 = Subtarget->isTarget64BitLP64();
18583 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
18584 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
18587 // ... [Till the alloca]
18588 // If stacklet is not large enough, jump to mallocMBB
18591 // Allocate by subtracting from RSP
18592 // Jump to continueMBB
18595 // Allocate by call to runtime
18599 // [rest of original BB]
18602 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18603 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18604 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18606 MachineRegisterInfo &MRI = MF->getRegInfo();
18607 const TargetRegisterClass *AddrRegClass =
18608 getRegClassFor(getPointerTy());
18610 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18611 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18612 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
18613 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
18614 sizeVReg = MI->getOperand(1).getReg(),
18615 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
18617 MachineFunction::iterator MBBIter = BB;
18620 MF->insert(MBBIter, bumpMBB);
18621 MF->insert(MBBIter, mallocMBB);
18622 MF->insert(MBBIter, continueMBB);
18624 continueMBB->splice(continueMBB->begin(), BB,
18625 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18626 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
18628 // Add code to the main basic block to check if the stack limit has been hit,
18629 // and if so, jump to mallocMBB otherwise to bumpMBB.
18630 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
18631 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
18632 .addReg(tmpSPVReg).addReg(sizeVReg);
18633 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
18634 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
18635 .addReg(SPLimitVReg);
18636 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
18638 // bumpMBB simply decreases the stack pointer, since we know the current
18639 // stacklet has enough space.
18640 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
18641 .addReg(SPLimitVReg);
18642 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
18643 .addReg(SPLimitVReg);
18644 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
18646 // Calls into a routine in libgcc to allocate more space from the heap.
18647 const uint32_t *RegMask =
18648 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
18650 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
18652 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
18653 .addExternalSymbol("__morestack_allocate_stack_space")
18654 .addRegMask(RegMask)
18655 .addReg(X86::RDI, RegState::Implicit)
18656 .addReg(X86::RAX, RegState::ImplicitDefine);
18657 } else if (Is64Bit) {
18658 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
18660 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
18661 .addExternalSymbol("__morestack_allocate_stack_space")
18662 .addRegMask(RegMask)
18663 .addReg(X86::EDI, RegState::Implicit)
18664 .addReg(X86::EAX, RegState::ImplicitDefine);
18666 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
18668 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
18669 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
18670 .addExternalSymbol("__morestack_allocate_stack_space")
18671 .addRegMask(RegMask)
18672 .addReg(X86::EAX, RegState::ImplicitDefine);
18676 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
18679 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
18680 .addReg(IsLP64 ? X86::RAX : X86::EAX);
18681 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
18683 // Set up the CFG correctly.
18684 BB->addSuccessor(bumpMBB);
18685 BB->addSuccessor(mallocMBB);
18686 mallocMBB->addSuccessor(continueMBB);
18687 bumpMBB->addSuccessor(continueMBB);
18689 // Take care of the PHI nodes.
18690 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
18691 MI->getOperand(0).getReg())
18692 .addReg(mallocPtrVReg).addMBB(mallocMBB)
18693 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
18695 // Delete the original pseudo instruction.
18696 MI->eraseFromParent();
18699 return continueMBB;
18702 MachineBasicBlock *
18703 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
18704 MachineBasicBlock *BB) const {
18705 DebugLoc DL = MI->getDebugLoc();
18707 assert(!Subtarget->isTargetMachO());
18709 X86FrameLowering::emitStackProbeCall(*BB->getParent(), *BB, MI, DL);
18711 MI->eraseFromParent(); // The pseudo instruction is gone now.
18715 MachineBasicBlock *
18716 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
18717 MachineBasicBlock *BB) const {
18718 // This is pretty easy. We're taking the value that we received from
18719 // our load from the relocation, sticking it in either RDI (x86-64)
18720 // or EAX and doing an indirect call. The return value will then
18721 // be in the normal return register.
18722 MachineFunction *F = BB->getParent();
18723 const X86InstrInfo *TII = Subtarget->getInstrInfo();
18724 DebugLoc DL = MI->getDebugLoc();
18726 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
18727 assert(MI->getOperand(3).isGlobal() && "This should be a global");
18729 // Get a register mask for the lowered call.
18730 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
18731 // proper register mask.
18732 const uint32_t *RegMask =
18733 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
18734 if (Subtarget->is64Bit()) {
18735 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18736 TII->get(X86::MOV64rm), X86::RDI)
18738 .addImm(0).addReg(0)
18739 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18740 MI->getOperand(3).getTargetFlags())
18742 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
18743 addDirectMem(MIB, X86::RDI);
18744 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
18745 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
18746 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18747 TII->get(X86::MOV32rm), X86::EAX)
18749 .addImm(0).addReg(0)
18750 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18751 MI->getOperand(3).getTargetFlags())
18753 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
18754 addDirectMem(MIB, X86::EAX);
18755 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
18757 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18758 TII->get(X86::MOV32rm), X86::EAX)
18759 .addReg(TII->getGlobalBaseReg(F))
18760 .addImm(0).addReg(0)
18761 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18762 MI->getOperand(3).getTargetFlags())
18764 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
18765 addDirectMem(MIB, X86::EAX);
18766 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
18769 MI->eraseFromParent(); // The pseudo instruction is gone now.
18773 MachineBasicBlock *
18774 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
18775 MachineBasicBlock *MBB) const {
18776 DebugLoc DL = MI->getDebugLoc();
18777 MachineFunction *MF = MBB->getParent();
18778 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18779 MachineRegisterInfo &MRI = MF->getRegInfo();
18781 const BasicBlock *BB = MBB->getBasicBlock();
18782 MachineFunction::iterator I = MBB;
18785 // Memory Reference
18786 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18787 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18790 unsigned MemOpndSlot = 0;
18792 unsigned CurOp = 0;
18794 DstReg = MI->getOperand(CurOp++).getReg();
18795 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
18796 assert(RC->hasType(MVT::i32) && "Invalid destination!");
18797 unsigned mainDstReg = MRI.createVirtualRegister(RC);
18798 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
18800 MemOpndSlot = CurOp;
18802 MVT PVT = getPointerTy();
18803 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
18804 "Invalid Pointer Size!");
18806 // For v = setjmp(buf), we generate
18809 // buf[LabelOffset] = restoreMBB
18810 // SjLjSetup restoreMBB
18816 // v = phi(main, restore)
18819 // if base pointer being used, load it from frame
18822 MachineBasicBlock *thisMBB = MBB;
18823 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18824 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18825 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
18826 MF->insert(I, mainMBB);
18827 MF->insert(I, sinkMBB);
18828 MF->push_back(restoreMBB);
18830 MachineInstrBuilder MIB;
18832 // Transfer the remainder of BB and its successor edges to sinkMBB.
18833 sinkMBB->splice(sinkMBB->begin(), MBB,
18834 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18835 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18838 unsigned PtrStoreOpc = 0;
18839 unsigned LabelReg = 0;
18840 const int64_t LabelOffset = 1 * PVT.getStoreSize();
18841 Reloc::Model RM = MF->getTarget().getRelocationModel();
18842 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
18843 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
18845 // Prepare IP either in reg or imm.
18846 if (!UseImmLabel) {
18847 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
18848 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
18849 LabelReg = MRI.createVirtualRegister(PtrRC);
18850 if (Subtarget->is64Bit()) {
18851 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
18855 .addMBB(restoreMBB)
18858 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
18859 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
18860 .addReg(XII->getGlobalBaseReg(MF))
18863 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
18867 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
18869 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
18870 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18871 if (i == X86::AddrDisp)
18872 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
18874 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
18877 MIB.addReg(LabelReg);
18879 MIB.addMBB(restoreMBB);
18880 MIB.setMemRefs(MMOBegin, MMOEnd);
18882 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
18883 .addMBB(restoreMBB);
18885 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
18886 MIB.addRegMask(RegInfo->getNoPreservedMask());
18887 thisMBB->addSuccessor(mainMBB);
18888 thisMBB->addSuccessor(restoreMBB);
18892 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
18893 mainMBB->addSuccessor(sinkMBB);
18896 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18897 TII->get(X86::PHI), DstReg)
18898 .addReg(mainDstReg).addMBB(mainMBB)
18899 .addReg(restoreDstReg).addMBB(restoreMBB);
18902 if (RegInfo->hasBasePointer(*MF)) {
18903 const bool Uses64BitFramePtr =
18904 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
18905 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
18906 X86FI->setRestoreBasePointer(MF);
18907 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
18908 unsigned BasePtr = RegInfo->getBaseRegister();
18909 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
18910 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
18911 FramePtr, true, X86FI->getRestoreBasePointerOffset())
18912 .setMIFlag(MachineInstr::FrameSetup);
18914 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
18915 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
18916 restoreMBB->addSuccessor(sinkMBB);
18918 MI->eraseFromParent();
18922 MachineBasicBlock *
18923 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
18924 MachineBasicBlock *MBB) const {
18925 DebugLoc DL = MI->getDebugLoc();
18926 MachineFunction *MF = MBB->getParent();
18927 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18928 MachineRegisterInfo &MRI = MF->getRegInfo();
18930 // Memory Reference
18931 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18932 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18934 MVT PVT = getPointerTy();
18935 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
18936 "Invalid Pointer Size!");
18938 const TargetRegisterClass *RC =
18939 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
18940 unsigned Tmp = MRI.createVirtualRegister(RC);
18941 // Since FP is only updated here but NOT referenced, it's treated as GPR.
18942 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
18943 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
18944 unsigned SP = RegInfo->getStackRegister();
18946 MachineInstrBuilder MIB;
18948 const int64_t LabelOffset = 1 * PVT.getStoreSize();
18949 const int64_t SPOffset = 2 * PVT.getStoreSize();
18951 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
18952 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
18955 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
18956 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
18957 MIB.addOperand(MI->getOperand(i));
18958 MIB.setMemRefs(MMOBegin, MMOEnd);
18960 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
18961 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18962 if (i == X86::AddrDisp)
18963 MIB.addDisp(MI->getOperand(i), LabelOffset);
18965 MIB.addOperand(MI->getOperand(i));
18967 MIB.setMemRefs(MMOBegin, MMOEnd);
18969 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
18970 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18971 if (i == X86::AddrDisp)
18972 MIB.addDisp(MI->getOperand(i), SPOffset);
18974 MIB.addOperand(MI->getOperand(i));
18976 MIB.setMemRefs(MMOBegin, MMOEnd);
18978 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
18980 MI->eraseFromParent();
18984 // Replace 213-type (isel default) FMA3 instructions with 231-type for
18985 // accumulator loops. Writing back to the accumulator allows the coalescer
18986 // to remove extra copies in the loop.
18987 MachineBasicBlock *
18988 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
18989 MachineBasicBlock *MBB) const {
18990 MachineOperand &AddendOp = MI->getOperand(3);
18992 // Bail out early if the addend isn't a register - we can't switch these.
18993 if (!AddendOp.isReg())
18996 MachineFunction &MF = *MBB->getParent();
18997 MachineRegisterInfo &MRI = MF.getRegInfo();
18999 // Check whether the addend is defined by a PHI:
19000 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
19001 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
19002 if (!AddendDef.isPHI())
19005 // Look for the following pattern:
19007 // %addend = phi [%entry, 0], [%loop, %result]
19009 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
19013 // %addend = phi [%entry, 0], [%loop, %result]
19015 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
19017 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
19018 assert(AddendDef.getOperand(i).isReg());
19019 MachineOperand PHISrcOp = AddendDef.getOperand(i);
19020 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
19021 if (&PHISrcInst == MI) {
19022 // Found a matching instruction.
19023 unsigned NewFMAOpc = 0;
19024 switch (MI->getOpcode()) {
19025 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
19026 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
19027 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
19028 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
19029 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
19030 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
19031 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
19032 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
19033 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
19034 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
19035 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
19036 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
19037 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
19038 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
19039 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
19040 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
19041 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
19042 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
19043 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
19044 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
19046 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
19047 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
19048 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
19049 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
19050 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
19051 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
19052 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
19053 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
19054 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
19055 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
19056 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
19057 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
19058 default: llvm_unreachable("Unrecognized FMA variant.");
19061 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
19062 MachineInstrBuilder MIB =
19063 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
19064 .addOperand(MI->getOperand(0))
19065 .addOperand(MI->getOperand(3))
19066 .addOperand(MI->getOperand(2))
19067 .addOperand(MI->getOperand(1));
19068 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
19069 MI->eraseFromParent();
19076 MachineBasicBlock *
19077 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
19078 MachineBasicBlock *BB) const {
19079 switch (MI->getOpcode()) {
19080 default: llvm_unreachable("Unexpected instr type to insert");
19081 case X86::TAILJMPd64:
19082 case X86::TAILJMPr64:
19083 case X86::TAILJMPm64:
19084 case X86::TAILJMPd64_REX:
19085 case X86::TAILJMPr64_REX:
19086 case X86::TAILJMPm64_REX:
19087 llvm_unreachable("TAILJMP64 would not be touched here.");
19088 case X86::TCRETURNdi64:
19089 case X86::TCRETURNri64:
19090 case X86::TCRETURNmi64:
19092 case X86::WIN_ALLOCA:
19093 return EmitLoweredWinAlloca(MI, BB);
19094 case X86::SEG_ALLOCA_32:
19095 case X86::SEG_ALLOCA_64:
19096 return EmitLoweredSegAlloca(MI, BB);
19097 case X86::TLSCall_32:
19098 case X86::TLSCall_64:
19099 return EmitLoweredTLSCall(MI, BB);
19100 case X86::CMOV_GR8:
19101 case X86::CMOV_FR32:
19102 case X86::CMOV_FR64:
19103 case X86::CMOV_V4F32:
19104 case X86::CMOV_V2F64:
19105 case X86::CMOV_V2I64:
19106 case X86::CMOV_V8F32:
19107 case X86::CMOV_V4F64:
19108 case X86::CMOV_V4I64:
19109 case X86::CMOV_V16F32:
19110 case X86::CMOV_V8F64:
19111 case X86::CMOV_V8I64:
19112 case X86::CMOV_GR16:
19113 case X86::CMOV_GR32:
19114 case X86::CMOV_RFP32:
19115 case X86::CMOV_RFP64:
19116 case X86::CMOV_RFP80:
19117 return EmitLoweredSelect(MI, BB);
19119 case X86::FP32_TO_INT16_IN_MEM:
19120 case X86::FP32_TO_INT32_IN_MEM:
19121 case X86::FP32_TO_INT64_IN_MEM:
19122 case X86::FP64_TO_INT16_IN_MEM:
19123 case X86::FP64_TO_INT32_IN_MEM:
19124 case X86::FP64_TO_INT64_IN_MEM:
19125 case X86::FP80_TO_INT16_IN_MEM:
19126 case X86::FP80_TO_INT32_IN_MEM:
19127 case X86::FP80_TO_INT64_IN_MEM: {
19128 MachineFunction *F = BB->getParent();
19129 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19130 DebugLoc DL = MI->getDebugLoc();
19132 // Change the floating point control register to use "round towards zero"
19133 // mode when truncating to an integer value.
19134 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
19135 addFrameReference(BuildMI(*BB, MI, DL,
19136 TII->get(X86::FNSTCW16m)), CWFrameIdx);
19138 // Load the old value of the high byte of the control word...
19140 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
19141 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
19144 // Set the high part to be round to zero...
19145 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
19148 // Reload the modified control word now...
19149 addFrameReference(BuildMI(*BB, MI, DL,
19150 TII->get(X86::FLDCW16m)), CWFrameIdx);
19152 // Restore the memory image of control word to original value
19153 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
19156 // Get the X86 opcode to use.
19158 switch (MI->getOpcode()) {
19159 default: llvm_unreachable("illegal opcode!");
19160 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
19161 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
19162 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
19163 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
19164 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
19165 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
19166 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
19167 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
19168 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
19172 MachineOperand &Op = MI->getOperand(0);
19174 AM.BaseType = X86AddressMode::RegBase;
19175 AM.Base.Reg = Op.getReg();
19177 AM.BaseType = X86AddressMode::FrameIndexBase;
19178 AM.Base.FrameIndex = Op.getIndex();
19180 Op = MI->getOperand(1);
19182 AM.Scale = Op.getImm();
19183 Op = MI->getOperand(2);
19185 AM.IndexReg = Op.getImm();
19186 Op = MI->getOperand(3);
19187 if (Op.isGlobal()) {
19188 AM.GV = Op.getGlobal();
19190 AM.Disp = Op.getImm();
19192 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
19193 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
19195 // Reload the original control word now.
19196 addFrameReference(BuildMI(*BB, MI, DL,
19197 TII->get(X86::FLDCW16m)), CWFrameIdx);
19199 MI->eraseFromParent(); // The pseudo instruction is gone now.
19202 // String/text processing lowering.
19203 case X86::PCMPISTRM128REG:
19204 case X86::VPCMPISTRM128REG:
19205 case X86::PCMPISTRM128MEM:
19206 case X86::VPCMPISTRM128MEM:
19207 case X86::PCMPESTRM128REG:
19208 case X86::VPCMPESTRM128REG:
19209 case X86::PCMPESTRM128MEM:
19210 case X86::VPCMPESTRM128MEM:
19211 assert(Subtarget->hasSSE42() &&
19212 "Target must have SSE4.2 or AVX features enabled");
19213 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
19215 // String/text processing lowering.
19216 case X86::PCMPISTRIREG:
19217 case X86::VPCMPISTRIREG:
19218 case X86::PCMPISTRIMEM:
19219 case X86::VPCMPISTRIMEM:
19220 case X86::PCMPESTRIREG:
19221 case X86::VPCMPESTRIREG:
19222 case X86::PCMPESTRIMEM:
19223 case X86::VPCMPESTRIMEM:
19224 assert(Subtarget->hasSSE42() &&
19225 "Target must have SSE4.2 or AVX features enabled");
19226 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
19228 // Thread synchronization.
19230 return EmitMonitor(MI, BB, Subtarget);
19234 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
19236 case X86::VASTART_SAVE_XMM_REGS:
19237 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
19239 case X86::VAARG_64:
19240 return EmitVAARG64WithCustomInserter(MI, BB);
19242 case X86::EH_SjLj_SetJmp32:
19243 case X86::EH_SjLj_SetJmp64:
19244 return emitEHSjLjSetJmp(MI, BB);
19246 case X86::EH_SjLj_LongJmp32:
19247 case X86::EH_SjLj_LongJmp64:
19248 return emitEHSjLjLongJmp(MI, BB);
19250 case TargetOpcode::STATEPOINT:
19251 // As an implementation detail, STATEPOINT shares the STACKMAP format at
19252 // this point in the process. We diverge later.
19253 return emitPatchPoint(MI, BB);
19255 case TargetOpcode::STACKMAP:
19256 case TargetOpcode::PATCHPOINT:
19257 return emitPatchPoint(MI, BB);
19259 case X86::VFMADDPDr213r:
19260 case X86::VFMADDPSr213r:
19261 case X86::VFMADDSDr213r:
19262 case X86::VFMADDSSr213r:
19263 case X86::VFMSUBPDr213r:
19264 case X86::VFMSUBPSr213r:
19265 case X86::VFMSUBSDr213r:
19266 case X86::VFMSUBSSr213r:
19267 case X86::VFNMADDPDr213r:
19268 case X86::VFNMADDPSr213r:
19269 case X86::VFNMADDSDr213r:
19270 case X86::VFNMADDSSr213r:
19271 case X86::VFNMSUBPDr213r:
19272 case X86::VFNMSUBPSr213r:
19273 case X86::VFNMSUBSDr213r:
19274 case X86::VFNMSUBSSr213r:
19275 case X86::VFMADDSUBPDr213r:
19276 case X86::VFMADDSUBPSr213r:
19277 case X86::VFMSUBADDPDr213r:
19278 case X86::VFMSUBADDPSr213r:
19279 case X86::VFMADDPDr213rY:
19280 case X86::VFMADDPSr213rY:
19281 case X86::VFMSUBPDr213rY:
19282 case X86::VFMSUBPSr213rY:
19283 case X86::VFNMADDPDr213rY:
19284 case X86::VFNMADDPSr213rY:
19285 case X86::VFNMSUBPDr213rY:
19286 case X86::VFNMSUBPSr213rY:
19287 case X86::VFMADDSUBPDr213rY:
19288 case X86::VFMADDSUBPSr213rY:
19289 case X86::VFMSUBADDPDr213rY:
19290 case X86::VFMSUBADDPSr213rY:
19291 return emitFMA3Instr(MI, BB);
19295 //===----------------------------------------------------------------------===//
19296 // X86 Optimization Hooks
19297 //===----------------------------------------------------------------------===//
19299 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
19302 const SelectionDAG &DAG,
19303 unsigned Depth) const {
19304 unsigned BitWidth = KnownZero.getBitWidth();
19305 unsigned Opc = Op.getOpcode();
19306 assert((Opc >= ISD::BUILTIN_OP_END ||
19307 Opc == ISD::INTRINSIC_WO_CHAIN ||
19308 Opc == ISD::INTRINSIC_W_CHAIN ||
19309 Opc == ISD::INTRINSIC_VOID) &&
19310 "Should use MaskedValueIsZero if you don't know whether Op"
19311 " is a target node!");
19313 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
19327 // These nodes' second result is a boolean.
19328 if (Op.getResNo() == 0)
19331 case X86ISD::SETCC:
19332 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
19334 case ISD::INTRINSIC_WO_CHAIN: {
19335 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
19336 unsigned NumLoBits = 0;
19339 case Intrinsic::x86_sse_movmsk_ps:
19340 case Intrinsic::x86_avx_movmsk_ps_256:
19341 case Intrinsic::x86_sse2_movmsk_pd:
19342 case Intrinsic::x86_avx_movmsk_pd_256:
19343 case Intrinsic::x86_mmx_pmovmskb:
19344 case Intrinsic::x86_sse2_pmovmskb_128:
19345 case Intrinsic::x86_avx2_pmovmskb: {
19346 // High bits of movmskp{s|d}, pmovmskb are known zero.
19348 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
19349 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
19350 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
19351 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
19352 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
19353 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
19354 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
19355 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
19357 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
19366 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
19368 const SelectionDAG &,
19369 unsigned Depth) const {
19370 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
19371 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
19372 return Op.getValueType().getScalarType().getSizeInBits();
19378 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
19379 /// node is a GlobalAddress + offset.
19380 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
19381 const GlobalValue* &GA,
19382 int64_t &Offset) const {
19383 if (N->getOpcode() == X86ISD::Wrapper) {
19384 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
19385 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
19386 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
19390 return TargetLowering::isGAPlusOffset(N, GA, Offset);
19393 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
19394 /// same as extracting the high 128-bit part of 256-bit vector and then
19395 /// inserting the result into the low part of a new 256-bit vector
19396 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
19397 EVT VT = SVOp->getValueType(0);
19398 unsigned NumElems = VT.getVectorNumElements();
19400 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19401 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
19402 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19403 SVOp->getMaskElt(j) >= 0)
19409 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
19410 /// same as extracting the low 128-bit part of 256-bit vector and then
19411 /// inserting the result into the high part of a new 256-bit vector
19412 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
19413 EVT VT = SVOp->getValueType(0);
19414 unsigned NumElems = VT.getVectorNumElements();
19416 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19417 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
19418 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
19419 SVOp->getMaskElt(j) >= 0)
19425 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
19426 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
19427 TargetLowering::DAGCombinerInfo &DCI,
19428 const X86Subtarget* Subtarget) {
19430 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
19431 SDValue V1 = SVOp->getOperand(0);
19432 SDValue V2 = SVOp->getOperand(1);
19433 EVT VT = SVOp->getValueType(0);
19434 unsigned NumElems = VT.getVectorNumElements();
19436 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
19437 V2.getOpcode() == ISD::CONCAT_VECTORS) {
19441 // V UNDEF BUILD_VECTOR UNDEF
19443 // CONCAT_VECTOR CONCAT_VECTOR
19446 // RESULT: V + zero extended
19448 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
19449 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
19450 V1.getOperand(1).getOpcode() != ISD::UNDEF)
19453 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
19456 // To match the shuffle mask, the first half of the mask should
19457 // be exactly the first vector, and all the rest a splat with the
19458 // first element of the second one.
19459 for (unsigned i = 0; i != NumElems/2; ++i)
19460 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
19461 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
19464 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
19465 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
19466 if (Ld->hasNUsesOfValue(1, 0)) {
19467 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
19468 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
19470 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
19472 Ld->getPointerInfo(),
19473 Ld->getAlignment(),
19474 false/*isVolatile*/, true/*ReadMem*/,
19475 false/*WriteMem*/);
19477 // Make sure the newly-created LOAD is in the same position as Ld in
19478 // terms of dependency. We create a TokenFactor for Ld and ResNode,
19479 // and update uses of Ld's output chain to use the TokenFactor.
19480 if (Ld->hasAnyUseOfValue(1)) {
19481 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
19482 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
19483 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
19484 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
19485 SDValue(ResNode.getNode(), 1));
19488 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
19492 // Emit a zeroed vector and insert the desired subvector on its
19494 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
19495 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
19496 return DCI.CombineTo(N, InsV);
19499 //===--------------------------------------------------------------------===//
19500 // Combine some shuffles into subvector extracts and inserts:
19503 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
19504 if (isShuffleHigh128VectorInsertLow(SVOp)) {
19505 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
19506 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
19507 return DCI.CombineTo(N, InsV);
19510 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
19511 if (isShuffleLow128VectorInsertHigh(SVOp)) {
19512 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
19513 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
19514 return DCI.CombineTo(N, InsV);
19520 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
19523 /// This is the leaf of the recursive combinine below. When we have found some
19524 /// chain of single-use x86 shuffle instructions and accumulated the combined
19525 /// shuffle mask represented by them, this will try to pattern match that mask
19526 /// into either a single instruction if there is a special purpose instruction
19527 /// for this operation, or into a PSHUFB instruction which is a fully general
19528 /// instruction but should only be used to replace chains over a certain depth.
19529 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
19530 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
19531 TargetLowering::DAGCombinerInfo &DCI,
19532 const X86Subtarget *Subtarget) {
19533 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
19535 // Find the operand that enters the chain. Note that multiple uses are OK
19536 // here, we're not going to remove the operand we find.
19537 SDValue Input = Op.getOperand(0);
19538 while (Input.getOpcode() == ISD::BITCAST)
19539 Input = Input.getOperand(0);
19541 MVT VT = Input.getSimpleValueType();
19542 MVT RootVT = Root.getSimpleValueType();
19545 // Just remove no-op shuffle masks.
19546 if (Mask.size() == 1) {
19547 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
19552 // Use the float domain if the operand type is a floating point type.
19553 bool FloatDomain = VT.isFloatingPoint();
19555 // For floating point shuffles, we don't have free copies in the shuffle
19556 // instructions or the ability to load as part of the instruction, so
19557 // canonicalize their shuffles to UNPCK or MOV variants.
19559 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
19560 // vectors because it can have a load folded into it that UNPCK cannot. This
19561 // doesn't preclude something switching to the shorter encoding post-RA.
19563 // FIXME: Should teach these routines about AVX vector widths.
19564 if (FloatDomain && VT.getSizeInBits() == 128) {
19565 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
19566 bool Lo = Mask.equals({0, 0});
19569 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
19570 // is no slower than UNPCKLPD but has the option to fold the input operand
19571 // into even an unaligned memory load.
19572 if (Lo && Subtarget->hasSSE3()) {
19573 Shuffle = X86ISD::MOVDDUP;
19574 ShuffleVT = MVT::v2f64;
19576 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
19577 // than the UNPCK variants.
19578 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
19579 ShuffleVT = MVT::v4f32;
19581 if (Depth == 1 && Root->getOpcode() == Shuffle)
19582 return false; // Nothing to do!
19583 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19584 DCI.AddToWorklist(Op.getNode());
19585 if (Shuffle == X86ISD::MOVDDUP)
19586 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
19588 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19589 DCI.AddToWorklist(Op.getNode());
19590 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19594 if (Subtarget->hasSSE3() &&
19595 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
19596 bool Lo = Mask.equals({0, 0, 2, 2});
19597 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
19598 MVT ShuffleVT = MVT::v4f32;
19599 if (Depth == 1 && Root->getOpcode() == Shuffle)
19600 return false; // Nothing to do!
19601 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19602 DCI.AddToWorklist(Op.getNode());
19603 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
19604 DCI.AddToWorklist(Op.getNode());
19605 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19609 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
19610 bool Lo = Mask.equals({0, 0, 1, 1});
19611 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
19612 MVT ShuffleVT = MVT::v4f32;
19613 if (Depth == 1 && Root->getOpcode() == Shuffle)
19614 return false; // Nothing to do!
19615 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19616 DCI.AddToWorklist(Op.getNode());
19617 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19618 DCI.AddToWorklist(Op.getNode());
19619 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19625 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
19626 // variants as none of these have single-instruction variants that are
19627 // superior to the UNPCK formulation.
19628 if (!FloatDomain && VT.getSizeInBits() == 128 &&
19629 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
19630 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
19631 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
19633 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
19634 bool Lo = Mask[0] == 0;
19635 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
19636 if (Depth == 1 && Root->getOpcode() == Shuffle)
19637 return false; // Nothing to do!
19639 switch (Mask.size()) {
19641 ShuffleVT = MVT::v8i16;
19644 ShuffleVT = MVT::v16i8;
19647 llvm_unreachable("Impossible mask size!");
19649 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19650 DCI.AddToWorklist(Op.getNode());
19651 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19652 DCI.AddToWorklist(Op.getNode());
19653 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19658 // Don't try to re-form single instruction chains under any circumstances now
19659 // that we've done encoding canonicalization for them.
19663 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
19664 // can replace them with a single PSHUFB instruction profitably. Intel's
19665 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
19666 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
19667 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
19668 SmallVector<SDValue, 16> PSHUFBMask;
19669 int NumBytes = VT.getSizeInBits() / 8;
19670 int Ratio = NumBytes / Mask.size();
19671 for (int i = 0; i < NumBytes; ++i) {
19672 if (Mask[i / Ratio] == SM_SentinelUndef) {
19673 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
19676 int M = Mask[i / Ratio] != SM_SentinelZero
19677 ? Ratio * Mask[i / Ratio] + i % Ratio
19679 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
19681 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
19682 Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Input);
19683 DCI.AddToWorklist(Op.getNode());
19684 SDValue PSHUFBMaskOp =
19685 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
19686 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
19687 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
19688 DCI.AddToWorklist(Op.getNode());
19689 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19694 // Failed to find any combines.
19698 /// \brief Fully generic combining of x86 shuffle instructions.
19700 /// This should be the last combine run over the x86 shuffle instructions. Once
19701 /// they have been fully optimized, this will recursively consider all chains
19702 /// of single-use shuffle instructions, build a generic model of the cumulative
19703 /// shuffle operation, and check for simpler instructions which implement this
19704 /// operation. We use this primarily for two purposes:
19706 /// 1) Collapse generic shuffles to specialized single instructions when
19707 /// equivalent. In most cases, this is just an encoding size win, but
19708 /// sometimes we will collapse multiple generic shuffles into a single
19709 /// special-purpose shuffle.
19710 /// 2) Look for sequences of shuffle instructions with 3 or more total
19711 /// instructions, and replace them with the slightly more expensive SSSE3
19712 /// PSHUFB instruction if available. We do this as the last combining step
19713 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
19714 /// a suitable short sequence of other instructions. The PHUFB will either
19715 /// use a register or have to read from memory and so is slightly (but only
19716 /// slightly) more expensive than the other shuffle instructions.
19718 /// Because this is inherently a quadratic operation (for each shuffle in
19719 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
19720 /// This should never be an issue in practice as the shuffle lowering doesn't
19721 /// produce sequences of more than 8 instructions.
19723 /// FIXME: We will currently miss some cases where the redundant shuffling
19724 /// would simplify under the threshold for PSHUFB formation because of
19725 /// combine-ordering. To fix this, we should do the redundant instruction
19726 /// combining in this recursive walk.
19727 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
19728 ArrayRef<int> RootMask,
19729 int Depth, bool HasPSHUFB,
19731 TargetLowering::DAGCombinerInfo &DCI,
19732 const X86Subtarget *Subtarget) {
19733 // Bound the depth of our recursive combine because this is ultimately
19734 // quadratic in nature.
19738 // Directly rip through bitcasts to find the underlying operand.
19739 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
19740 Op = Op.getOperand(0);
19742 MVT VT = Op.getSimpleValueType();
19743 if (!VT.isVector())
19744 return false; // Bail if we hit a non-vector.
19746 assert(Root.getSimpleValueType().isVector() &&
19747 "Shuffles operate on vector types!");
19748 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
19749 "Can only combine shuffles of the same vector register size.");
19751 if (!isTargetShuffle(Op.getOpcode()))
19753 SmallVector<int, 16> OpMask;
19755 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
19756 // We only can combine unary shuffles which we can decode the mask for.
19757 if (!HaveMask || !IsUnary)
19760 assert(VT.getVectorNumElements() == OpMask.size() &&
19761 "Different mask size from vector size!");
19762 assert(((RootMask.size() > OpMask.size() &&
19763 RootMask.size() % OpMask.size() == 0) ||
19764 (OpMask.size() > RootMask.size() &&
19765 OpMask.size() % RootMask.size() == 0) ||
19766 OpMask.size() == RootMask.size()) &&
19767 "The smaller number of elements must divide the larger.");
19768 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
19769 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
19770 assert(((RootRatio == 1 && OpRatio == 1) ||
19771 (RootRatio == 1) != (OpRatio == 1)) &&
19772 "Must not have a ratio for both incoming and op masks!");
19774 SmallVector<int, 16> Mask;
19775 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
19777 // Merge this shuffle operation's mask into our accumulated mask. Note that
19778 // this shuffle's mask will be the first applied to the input, followed by the
19779 // root mask to get us all the way to the root value arrangement. The reason
19780 // for this order is that we are recursing up the operation chain.
19781 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
19782 int RootIdx = i / RootRatio;
19783 if (RootMask[RootIdx] < 0) {
19784 // This is a zero or undef lane, we're done.
19785 Mask.push_back(RootMask[RootIdx]);
19789 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
19790 int OpIdx = RootMaskedIdx / OpRatio;
19791 if (OpMask[OpIdx] < 0) {
19792 // The incoming lanes are zero or undef, it doesn't matter which ones we
19794 Mask.push_back(OpMask[OpIdx]);
19798 // Ok, we have non-zero lanes, map them through.
19799 Mask.push_back(OpMask[OpIdx] * OpRatio +
19800 RootMaskedIdx % OpRatio);
19803 // See if we can recurse into the operand to combine more things.
19804 switch (Op.getOpcode()) {
19805 case X86ISD::PSHUFB:
19807 case X86ISD::PSHUFD:
19808 case X86ISD::PSHUFHW:
19809 case X86ISD::PSHUFLW:
19810 if (Op.getOperand(0).hasOneUse() &&
19811 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
19812 HasPSHUFB, DAG, DCI, Subtarget))
19816 case X86ISD::UNPCKL:
19817 case X86ISD::UNPCKH:
19818 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
19819 // We can't check for single use, we have to check that this shuffle is the only user.
19820 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
19821 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
19822 HasPSHUFB, DAG, DCI, Subtarget))
19827 // Minor canonicalization of the accumulated shuffle mask to make it easier
19828 // to match below. All this does is detect masks with squential pairs of
19829 // elements, and shrink them to the half-width mask. It does this in a loop
19830 // so it will reduce the size of the mask to the minimal width mask which
19831 // performs an equivalent shuffle.
19832 SmallVector<int, 16> WidenedMask;
19833 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
19834 Mask = std::move(WidenedMask);
19835 WidenedMask.clear();
19838 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
19842 /// \brief Get the PSHUF-style mask from PSHUF node.
19844 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
19845 /// PSHUF-style masks that can be reused with such instructions.
19846 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
19847 MVT VT = N.getSimpleValueType();
19848 SmallVector<int, 4> Mask;
19850 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
19854 // If we have more than 128-bits, only the low 128-bits of shuffle mask
19855 // matter. Check that the upper masks are repeats and remove them.
19856 if (VT.getSizeInBits() > 128) {
19857 int LaneElts = 128 / VT.getScalarSizeInBits();
19859 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
19860 for (int j = 0; j < LaneElts; ++j)
19861 assert(Mask[j] == Mask[i * LaneElts + j] - LaneElts &&
19862 "Mask doesn't repeat in high 128-bit lanes!");
19864 Mask.resize(LaneElts);
19867 switch (N.getOpcode()) {
19868 case X86ISD::PSHUFD:
19870 case X86ISD::PSHUFLW:
19873 case X86ISD::PSHUFHW:
19874 Mask.erase(Mask.begin(), Mask.begin() + 4);
19875 for (int &M : Mask)
19879 llvm_unreachable("No valid shuffle instruction found!");
19883 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
19885 /// We walk up the chain and look for a combinable shuffle, skipping over
19886 /// shuffles that we could hoist this shuffle's transformation past without
19887 /// altering anything.
19889 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
19891 TargetLowering::DAGCombinerInfo &DCI) {
19892 assert(N.getOpcode() == X86ISD::PSHUFD &&
19893 "Called with something other than an x86 128-bit half shuffle!");
19896 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
19897 // of the shuffles in the chain so that we can form a fresh chain to replace
19899 SmallVector<SDValue, 8> Chain;
19900 SDValue V = N.getOperand(0);
19901 for (; V.hasOneUse(); V = V.getOperand(0)) {
19902 switch (V.getOpcode()) {
19904 return SDValue(); // Nothing combined!
19907 // Skip bitcasts as we always know the type for the target specific
19911 case X86ISD::PSHUFD:
19912 // Found another dword shuffle.
19915 case X86ISD::PSHUFLW:
19916 // Check that the low words (being shuffled) are the identity in the
19917 // dword shuffle, and the high words are self-contained.
19918 if (Mask[0] != 0 || Mask[1] != 1 ||
19919 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
19922 Chain.push_back(V);
19925 case X86ISD::PSHUFHW:
19926 // Check that the high words (being shuffled) are the identity in the
19927 // dword shuffle, and the low words are self-contained.
19928 if (Mask[2] != 2 || Mask[3] != 3 ||
19929 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
19932 Chain.push_back(V);
19935 case X86ISD::UNPCKL:
19936 case X86ISD::UNPCKH:
19937 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
19938 // shuffle into a preceding word shuffle.
19939 if (V.getSimpleValueType().getScalarType() != MVT::i8 &&
19940 V.getSimpleValueType().getScalarType() != MVT::i16)
19943 // Search for a half-shuffle which we can combine with.
19944 unsigned CombineOp =
19945 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
19946 if (V.getOperand(0) != V.getOperand(1) ||
19947 !V->isOnlyUserOf(V.getOperand(0).getNode()))
19949 Chain.push_back(V);
19950 V = V.getOperand(0);
19952 switch (V.getOpcode()) {
19954 return SDValue(); // Nothing to combine.
19956 case X86ISD::PSHUFLW:
19957 case X86ISD::PSHUFHW:
19958 if (V.getOpcode() == CombineOp)
19961 Chain.push_back(V);
19965 V = V.getOperand(0);
19969 } while (V.hasOneUse());
19972 // Break out of the loop if we break out of the switch.
19976 if (!V.hasOneUse())
19977 // We fell out of the loop without finding a viable combining instruction.
19980 // Merge this node's mask and our incoming mask.
19981 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
19982 for (int &M : Mask)
19984 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
19985 getV4X86ShuffleImm8ForMask(Mask, DAG));
19987 // Rebuild the chain around this new shuffle.
19988 while (!Chain.empty()) {
19989 SDValue W = Chain.pop_back_val();
19991 if (V.getValueType() != W.getOperand(0).getValueType())
19992 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
19994 switch (W.getOpcode()) {
19996 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
19998 case X86ISD::UNPCKL:
19999 case X86ISD::UNPCKH:
20000 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
20003 case X86ISD::PSHUFD:
20004 case X86ISD::PSHUFLW:
20005 case X86ISD::PSHUFHW:
20006 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
20010 if (V.getValueType() != N.getValueType())
20011 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
20013 // Return the new chain to replace N.
20017 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
20019 /// We walk up the chain, skipping shuffles of the other half and looking
20020 /// through shuffles which switch halves trying to find a shuffle of the same
20021 /// pair of dwords.
20022 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
20024 TargetLowering::DAGCombinerInfo &DCI) {
20026 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
20027 "Called with something other than an x86 128-bit half shuffle!");
20029 unsigned CombineOpcode = N.getOpcode();
20031 // Walk up a single-use chain looking for a combinable shuffle.
20032 SDValue V = N.getOperand(0);
20033 for (; V.hasOneUse(); V = V.getOperand(0)) {
20034 switch (V.getOpcode()) {
20036 return false; // Nothing combined!
20039 // Skip bitcasts as we always know the type for the target specific
20043 case X86ISD::PSHUFLW:
20044 case X86ISD::PSHUFHW:
20045 if (V.getOpcode() == CombineOpcode)
20048 // Other-half shuffles are no-ops.
20051 // Break out of the loop if we break out of the switch.
20055 if (!V.hasOneUse())
20056 // We fell out of the loop without finding a viable combining instruction.
20059 // Combine away the bottom node as its shuffle will be accumulated into
20060 // a preceding shuffle.
20061 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20063 // Record the old value.
20066 // Merge this node's mask and our incoming mask (adjusted to account for all
20067 // the pshufd instructions encountered).
20068 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20069 for (int &M : Mask)
20071 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
20072 getV4X86ShuffleImm8ForMask(Mask, DAG));
20074 // Check that the shuffles didn't cancel each other out. If not, we need to
20075 // combine to the new one.
20077 // Replace the combinable shuffle with the combined one, updating all users
20078 // so that we re-evaluate the chain here.
20079 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
20084 /// \brief Try to combine x86 target specific shuffles.
20085 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
20086 TargetLowering::DAGCombinerInfo &DCI,
20087 const X86Subtarget *Subtarget) {
20089 MVT VT = N.getSimpleValueType();
20090 SmallVector<int, 4> Mask;
20092 switch (N.getOpcode()) {
20093 case X86ISD::PSHUFD:
20094 case X86ISD::PSHUFLW:
20095 case X86ISD::PSHUFHW:
20096 Mask = getPSHUFShuffleMask(N);
20097 assert(Mask.size() == 4);
20103 // Nuke no-op shuffles that show up after combining.
20104 if (isNoopShuffleMask(Mask))
20105 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20107 // Look for simplifications involving one or two shuffle instructions.
20108 SDValue V = N.getOperand(0);
20109 switch (N.getOpcode()) {
20112 case X86ISD::PSHUFLW:
20113 case X86ISD::PSHUFHW:
20114 assert(VT.getScalarType() == MVT::i16 && "Bad word shuffle type!");
20116 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
20117 return SDValue(); // We combined away this shuffle, so we're done.
20119 // See if this reduces to a PSHUFD which is no more expensive and can
20120 // combine with more operations. Note that it has to at least flip the
20121 // dwords as otherwise it would have been removed as a no-op.
20122 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
20123 int DMask[] = {0, 1, 2, 3};
20124 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
20125 DMask[DOffset + 0] = DOffset + 1;
20126 DMask[DOffset + 1] = DOffset + 0;
20127 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
20128 V = DAG.getNode(ISD::BITCAST, DL, DVT, V);
20129 DCI.AddToWorklist(V.getNode());
20130 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
20131 getV4X86ShuffleImm8ForMask(DMask, DAG));
20132 DCI.AddToWorklist(V.getNode());
20133 return DAG.getNode(ISD::BITCAST, DL, VT, V);
20136 // Look for shuffle patterns which can be implemented as a single unpack.
20137 // FIXME: This doesn't handle the location of the PSHUFD generically, and
20138 // only works when we have a PSHUFD followed by two half-shuffles.
20139 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
20140 (V.getOpcode() == X86ISD::PSHUFLW ||
20141 V.getOpcode() == X86ISD::PSHUFHW) &&
20142 V.getOpcode() != N.getOpcode() &&
20144 SDValue D = V.getOperand(0);
20145 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
20146 D = D.getOperand(0);
20147 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
20148 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20149 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
20150 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20151 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20153 for (int i = 0; i < 4; ++i) {
20154 WordMask[i + NOffset] = Mask[i] + NOffset;
20155 WordMask[i + VOffset] = VMask[i] + VOffset;
20157 // Map the word mask through the DWord mask.
20159 for (int i = 0; i < 8; ++i)
20160 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
20161 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
20162 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
20163 // We can replace all three shuffles with an unpack.
20164 V = DAG.getNode(ISD::BITCAST, DL, VT, D.getOperand(0));
20165 DCI.AddToWorklist(V.getNode());
20166 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
20175 case X86ISD::PSHUFD:
20176 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
20185 /// \brief Try to combine a shuffle into a target-specific add-sub node.
20187 /// We combine this directly on the abstract vector shuffle nodes so it is
20188 /// easier to generically match. We also insert dummy vector shuffle nodes for
20189 /// the operands which explicitly discard the lanes which are unused by this
20190 /// operation to try to flow through the rest of the combiner the fact that
20191 /// they're unused.
20192 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
20194 EVT VT = N->getValueType(0);
20196 // We only handle target-independent shuffles.
20197 // FIXME: It would be easy and harmless to use the target shuffle mask
20198 // extraction tool to support more.
20199 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
20202 auto *SVN = cast<ShuffleVectorSDNode>(N);
20203 ArrayRef<int> Mask = SVN->getMask();
20204 SDValue V1 = N->getOperand(0);
20205 SDValue V2 = N->getOperand(1);
20207 // We require the first shuffle operand to be the SUB node, and the second to
20208 // be the ADD node.
20209 // FIXME: We should support the commuted patterns.
20210 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
20213 // If there are other uses of these operations we can't fold them.
20214 if (!V1->hasOneUse() || !V2->hasOneUse())
20217 // Ensure that both operations have the same operands. Note that we can
20218 // commute the FADD operands.
20219 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
20220 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
20221 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
20224 // We're looking for blends between FADD and FSUB nodes. We insist on these
20225 // nodes being lined up in a specific expected pattern.
20226 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
20227 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
20228 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
20231 // Only specific types are legal at this point, assert so we notice if and
20232 // when these change.
20233 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
20234 VT == MVT::v4f64) &&
20235 "Unknown vector type encountered!");
20237 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
20240 /// PerformShuffleCombine - Performs several different shuffle combines.
20241 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
20242 TargetLowering::DAGCombinerInfo &DCI,
20243 const X86Subtarget *Subtarget) {
20245 SDValue N0 = N->getOperand(0);
20246 SDValue N1 = N->getOperand(1);
20247 EVT VT = N->getValueType(0);
20249 // Don't create instructions with illegal types after legalize types has run.
20250 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20251 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
20254 // If we have legalized the vector types, look for blends of FADD and FSUB
20255 // nodes that we can fuse into an ADDSUB node.
20256 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
20257 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
20260 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
20261 if (Subtarget->hasFp256() && VT.is256BitVector() &&
20262 N->getOpcode() == ISD::VECTOR_SHUFFLE)
20263 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
20265 // During Type Legalization, when promoting illegal vector types,
20266 // the backend might introduce new shuffle dag nodes and bitcasts.
20268 // This code performs the following transformation:
20269 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
20270 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
20272 // We do this only if both the bitcast and the BINOP dag nodes have
20273 // one use. Also, perform this transformation only if the new binary
20274 // operation is legal. This is to avoid introducing dag nodes that
20275 // potentially need to be further expanded (or custom lowered) into a
20276 // less optimal sequence of dag nodes.
20277 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
20278 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
20279 N0.getOpcode() == ISD::BITCAST) {
20280 SDValue BC0 = N0.getOperand(0);
20281 EVT SVT = BC0.getValueType();
20282 unsigned Opcode = BC0.getOpcode();
20283 unsigned NumElts = VT.getVectorNumElements();
20285 if (BC0.hasOneUse() && SVT.isVector() &&
20286 SVT.getVectorNumElements() * 2 == NumElts &&
20287 TLI.isOperationLegal(Opcode, VT)) {
20288 bool CanFold = false;
20300 unsigned SVTNumElts = SVT.getVectorNumElements();
20301 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20302 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
20303 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
20304 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
20305 CanFold = SVOp->getMaskElt(i) < 0;
20308 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
20309 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
20310 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
20311 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
20316 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
20317 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
20318 // consecutive, non-overlapping, and in the right order.
20319 SmallVector<SDValue, 16> Elts;
20320 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
20321 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
20323 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
20327 if (isTargetShuffle(N->getOpcode())) {
20329 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
20330 if (Shuffle.getNode())
20333 // Try recursively combining arbitrary sequences of x86 shuffle
20334 // instructions into higher-order shuffles. We do this after combining
20335 // specific PSHUF instruction sequences into their minimal form so that we
20336 // can evaluate how many specialized shuffle instructions are involved in
20337 // a particular chain.
20338 SmallVector<int, 1> NonceMask; // Just a placeholder.
20339 NonceMask.push_back(0);
20340 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
20341 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
20343 return SDValue(); // This routine will use CombineTo to replace N.
20349 /// PerformTruncateCombine - Converts truncate operation to
20350 /// a sequence of vector shuffle operations.
20351 /// It is possible when we truncate 256-bit vector to 128-bit vector
20352 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
20353 TargetLowering::DAGCombinerInfo &DCI,
20354 const X86Subtarget *Subtarget) {
20358 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
20359 /// specific shuffle of a load can be folded into a single element load.
20360 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
20361 /// shuffles have been custom lowered so we need to handle those here.
20362 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
20363 TargetLowering::DAGCombinerInfo &DCI) {
20364 if (DCI.isBeforeLegalizeOps())
20367 SDValue InVec = N->getOperand(0);
20368 SDValue EltNo = N->getOperand(1);
20370 if (!isa<ConstantSDNode>(EltNo))
20373 EVT OriginalVT = InVec.getValueType();
20375 if (InVec.getOpcode() == ISD::BITCAST) {
20376 // Don't duplicate a load with other uses.
20377 if (!InVec.hasOneUse())
20379 EVT BCVT = InVec.getOperand(0).getValueType();
20380 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
20382 InVec = InVec.getOperand(0);
20385 EVT CurrentVT = InVec.getValueType();
20387 if (!isTargetShuffle(InVec.getOpcode()))
20390 // Don't duplicate a load with other uses.
20391 if (!InVec.hasOneUse())
20394 SmallVector<int, 16> ShuffleMask;
20396 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
20397 ShuffleMask, UnaryShuffle))
20400 // Select the input vector, guarding against out of range extract vector.
20401 unsigned NumElems = CurrentVT.getVectorNumElements();
20402 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
20403 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
20404 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
20405 : InVec.getOperand(1);
20407 // If inputs to shuffle are the same for both ops, then allow 2 uses
20408 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
20409 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
20411 if (LdNode.getOpcode() == ISD::BITCAST) {
20412 // Don't duplicate a load with other uses.
20413 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
20416 AllowedUses = 1; // only allow 1 load use if we have a bitcast
20417 LdNode = LdNode.getOperand(0);
20420 if (!ISD::isNormalLoad(LdNode.getNode()))
20423 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
20425 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
20428 EVT EltVT = N->getValueType(0);
20429 // If there's a bitcast before the shuffle, check if the load type and
20430 // alignment is valid.
20431 unsigned Align = LN0->getAlignment();
20432 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20433 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
20434 EltVT.getTypeForEVT(*DAG.getContext()));
20436 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
20439 // All checks match so transform back to vector_shuffle so that DAG combiner
20440 // can finish the job
20443 // Create shuffle node taking into account the case that its a unary shuffle
20444 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
20445 : InVec.getOperand(1);
20446 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
20447 InVec.getOperand(0), Shuffle,
20449 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
20450 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
20454 /// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
20455 /// special and don't usually play with other vector types, it's better to
20456 /// handle them early to be sure we emit efficient code by avoiding
20457 /// store-load conversions.
20458 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
20459 if (N->getValueType(0) != MVT::x86mmx ||
20460 N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
20461 N->getOperand(0)->getValueType(0) != MVT::v2i32)
20464 SDValue V = N->getOperand(0);
20465 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
20466 if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
20467 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
20468 N->getValueType(0), V.getOperand(0));
20473 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
20474 /// generation and convert it from being a bunch of shuffles and extracts
20475 /// into a somewhat faster sequence. For i686, the best sequence is apparently
20476 /// storing the value and loading scalars back, while for x64 we should
20477 /// use 64-bit extracts and shifts.
20478 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
20479 TargetLowering::DAGCombinerInfo &DCI) {
20480 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
20481 if (NewOp.getNode())
20484 SDValue InputVector = N->getOperand(0);
20486 // Detect mmx to i32 conversion through a v2i32 elt extract.
20487 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
20488 N->getValueType(0) == MVT::i32 &&
20489 InputVector.getValueType() == MVT::v2i32) {
20491 // The bitcast source is a direct mmx result.
20492 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
20493 if (MMXSrc.getValueType() == MVT::x86mmx)
20494 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
20495 N->getValueType(0),
20496 InputVector.getNode()->getOperand(0));
20498 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
20499 SDValue MMXSrcOp = MMXSrc.getOperand(0);
20500 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
20501 MMXSrc.getValueType() == MVT::i64 && MMXSrcOp.hasOneUse() &&
20502 MMXSrcOp.getOpcode() == ISD::BITCAST &&
20503 MMXSrcOp.getValueType() == MVT::v1i64 &&
20504 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
20505 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
20506 N->getValueType(0),
20507 MMXSrcOp.getOperand(0));
20510 // Only operate on vectors of 4 elements, where the alternative shuffling
20511 // gets to be more expensive.
20512 if (InputVector.getValueType() != MVT::v4i32)
20515 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
20516 // single use which is a sign-extend or zero-extend, and all elements are
20518 SmallVector<SDNode *, 4> Uses;
20519 unsigned ExtractedElements = 0;
20520 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
20521 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
20522 if (UI.getUse().getResNo() != InputVector.getResNo())
20525 SDNode *Extract = *UI;
20526 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
20529 if (Extract->getValueType(0) != MVT::i32)
20531 if (!Extract->hasOneUse())
20533 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
20534 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
20536 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
20539 // Record which element was extracted.
20540 ExtractedElements |=
20541 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
20543 Uses.push_back(Extract);
20546 // If not all the elements were used, this may not be worthwhile.
20547 if (ExtractedElements != 15)
20550 // Ok, we've now decided to do the transformation.
20551 // If 64-bit shifts are legal, use the extract-shift sequence,
20552 // otherwise bounce the vector off the cache.
20553 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20555 SDLoc dl(InputVector);
20557 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
20558 SDValue Cst = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, InputVector);
20559 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();
20560 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
20561 DAG.getConstant(0, VecIdxTy));
20562 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
20563 DAG.getConstant(1, VecIdxTy));
20565 SDValue ShAmt = DAG.getConstant(32,
20566 DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));
20567 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
20568 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
20569 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
20570 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
20571 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
20572 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
20574 // Store the value to a temporary stack slot.
20575 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
20576 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
20577 MachinePointerInfo(), false, false, 0);
20579 EVT ElementType = InputVector.getValueType().getVectorElementType();
20580 unsigned EltSize = ElementType.getSizeInBits() / 8;
20582 // Replace each use (extract) with a load of the appropriate element.
20583 for (unsigned i = 0; i < 4; ++i) {
20584 uint64_t Offset = EltSize * i;
20585 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
20587 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
20588 StackPtr, OffsetVal);
20590 // Load the scalar.
20591 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
20592 ScalarAddr, MachinePointerInfo(),
20593 false, false, false, 0);
20598 // Replace the extracts
20599 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
20600 UE = Uses.end(); UI != UE; ++UI) {
20601 SDNode *Extract = *UI;
20603 SDValue Idx = Extract->getOperand(1);
20604 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
20605 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
20608 // The replacement was made in place; don't return anything.
20612 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
20613 static std::pair<unsigned, bool>
20614 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
20615 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
20616 if (!VT.isVector())
20617 return std::make_pair(0, false);
20619 bool NeedSplit = false;
20620 switch (VT.getSimpleVT().SimpleTy) {
20621 default: return std::make_pair(0, false);
20624 if (!Subtarget->hasVLX())
20625 return std::make_pair(0, false);
20629 if (!Subtarget->hasBWI())
20630 return std::make_pair(0, false);
20634 if (!Subtarget->hasAVX512())
20635 return std::make_pair(0, false);
20640 if (!Subtarget->hasAVX2())
20642 if (!Subtarget->hasAVX())
20643 return std::make_pair(0, false);
20648 if (!Subtarget->hasSSE2())
20649 return std::make_pair(0, false);
20652 // SSE2 has only a small subset of the operations.
20653 bool hasUnsigned = Subtarget->hasSSE41() ||
20654 (Subtarget->hasSSE2() && VT == MVT::v16i8);
20655 bool hasSigned = Subtarget->hasSSE41() ||
20656 (Subtarget->hasSSE2() && VT == MVT::v8i16);
20658 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20661 // Check for x CC y ? x : y.
20662 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20663 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20668 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
20671 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
20674 Opc = hasSigned ? X86ISD::SMIN : 0; break;
20677 Opc = hasSigned ? X86ISD::SMAX : 0; break;
20679 // Check for x CC y ? y : x -- a min/max with reversed arms.
20680 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
20681 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
20686 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
20689 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
20692 Opc = hasSigned ? X86ISD::SMAX : 0; break;
20695 Opc = hasSigned ? X86ISD::SMIN : 0; break;
20699 return std::make_pair(Opc, NeedSplit);
20703 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
20704 const X86Subtarget *Subtarget) {
20706 SDValue Cond = N->getOperand(0);
20707 SDValue LHS = N->getOperand(1);
20708 SDValue RHS = N->getOperand(2);
20710 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
20711 SDValue CondSrc = Cond->getOperand(0);
20712 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
20713 Cond = CondSrc->getOperand(0);
20716 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
20719 // A vselect where all conditions and data are constants can be optimized into
20720 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
20721 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
20722 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
20725 unsigned MaskValue = 0;
20726 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
20729 MVT VT = N->getSimpleValueType(0);
20730 unsigned NumElems = VT.getVectorNumElements();
20731 SmallVector<int, 8> ShuffleMask(NumElems, -1);
20732 for (unsigned i = 0; i < NumElems; ++i) {
20733 // Be sure we emit undef where we can.
20734 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
20735 ShuffleMask[i] = -1;
20737 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
20740 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20741 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
20743 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
20746 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
20748 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
20749 TargetLowering::DAGCombinerInfo &DCI,
20750 const X86Subtarget *Subtarget) {
20752 SDValue Cond = N->getOperand(0);
20753 // Get the LHS/RHS of the select.
20754 SDValue LHS = N->getOperand(1);
20755 SDValue RHS = N->getOperand(2);
20756 EVT VT = LHS.getValueType();
20757 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20759 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
20760 // instructions match the semantics of the common C idiom x<y?x:y but not
20761 // x<=y?x:y, because of how they handle negative zero (which can be
20762 // ignored in unsafe-math mode).
20763 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
20764 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
20765 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
20766 (Subtarget->hasSSE2() ||
20767 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
20768 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20770 unsigned Opcode = 0;
20771 // Check for x CC y ? x : y.
20772 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20773 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20777 // Converting this to a min would handle NaNs incorrectly, and swapping
20778 // the operands would cause it to handle comparisons between positive
20779 // and negative zero incorrectly.
20780 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
20781 if (!DAG.getTarget().Options.UnsafeFPMath &&
20782 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
20784 std::swap(LHS, RHS);
20786 Opcode = X86ISD::FMIN;
20789 // Converting this to a min would handle comparisons between positive
20790 // and negative zero incorrectly.
20791 if (!DAG.getTarget().Options.UnsafeFPMath &&
20792 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
20794 Opcode = X86ISD::FMIN;
20797 // Converting this to a min would handle both negative zeros and NaNs
20798 // incorrectly, but we can swap the operands to fix both.
20799 std::swap(LHS, RHS);
20803 Opcode = X86ISD::FMIN;
20807 // Converting this to a max would handle comparisons between positive
20808 // and negative zero incorrectly.
20809 if (!DAG.getTarget().Options.UnsafeFPMath &&
20810 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
20812 Opcode = X86ISD::FMAX;
20815 // Converting this to a max would handle NaNs incorrectly, and swapping
20816 // the operands would cause it to handle comparisons between positive
20817 // and negative zero incorrectly.
20818 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
20819 if (!DAG.getTarget().Options.UnsafeFPMath &&
20820 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
20822 std::swap(LHS, RHS);
20824 Opcode = X86ISD::FMAX;
20827 // Converting this to a max would handle both negative zeros and NaNs
20828 // incorrectly, but we can swap the operands to fix both.
20829 std::swap(LHS, RHS);
20833 Opcode = X86ISD::FMAX;
20836 // Check for x CC y ? y : x -- a min/max with reversed arms.
20837 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
20838 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
20842 // Converting this to a min would handle comparisons between positive
20843 // and negative zero incorrectly, and swapping the operands would
20844 // cause it to handle NaNs incorrectly.
20845 if (!DAG.getTarget().Options.UnsafeFPMath &&
20846 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
20847 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20849 std::swap(LHS, RHS);
20851 Opcode = X86ISD::FMIN;
20854 // Converting this to a min would handle NaNs incorrectly.
20855 if (!DAG.getTarget().Options.UnsafeFPMath &&
20856 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
20858 Opcode = X86ISD::FMIN;
20861 // Converting this to a min would handle both negative zeros and NaNs
20862 // incorrectly, but we can swap the operands to fix both.
20863 std::swap(LHS, RHS);
20867 Opcode = X86ISD::FMIN;
20871 // Converting this to a max would handle NaNs incorrectly.
20872 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20874 Opcode = X86ISD::FMAX;
20877 // Converting this to a max would handle comparisons between positive
20878 // and negative zero incorrectly, and swapping the operands would
20879 // cause it to handle NaNs incorrectly.
20880 if (!DAG.getTarget().Options.UnsafeFPMath &&
20881 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
20882 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20884 std::swap(LHS, RHS);
20886 Opcode = X86ISD::FMAX;
20889 // Converting this to a max would handle both negative zeros and NaNs
20890 // incorrectly, but we can swap the operands to fix both.
20891 std::swap(LHS, RHS);
20895 Opcode = X86ISD::FMAX;
20901 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
20904 EVT CondVT = Cond.getValueType();
20905 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
20906 CondVT.getVectorElementType() == MVT::i1) {
20907 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
20908 // lowering on KNL. In this case we convert it to
20909 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
20910 // The same situation for all 128 and 256-bit vectors of i8 and i16.
20911 // Since SKX these selects have a proper lowering.
20912 EVT OpVT = LHS.getValueType();
20913 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
20914 (OpVT.getVectorElementType() == MVT::i8 ||
20915 OpVT.getVectorElementType() == MVT::i16) &&
20916 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
20917 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
20918 DCI.AddToWorklist(Cond.getNode());
20919 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
20922 // If this is a select between two integer constants, try to do some
20924 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
20925 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
20926 // Don't do this for crazy integer types.
20927 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
20928 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
20929 // so that TrueC (the true value) is larger than FalseC.
20930 bool NeedsCondInvert = false;
20932 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
20933 // Efficiently invertible.
20934 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
20935 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
20936 isa<ConstantSDNode>(Cond.getOperand(1))))) {
20937 NeedsCondInvert = true;
20938 std::swap(TrueC, FalseC);
20941 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
20942 if (FalseC->getAPIntValue() == 0 &&
20943 TrueC->getAPIntValue().isPowerOf2()) {
20944 if (NeedsCondInvert) // Invert the condition if needed.
20945 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20946 DAG.getConstant(1, Cond.getValueType()));
20948 // Zero extend the condition if needed.
20949 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
20951 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
20952 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
20953 DAG.getConstant(ShAmt, MVT::i8));
20956 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
20957 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
20958 if (NeedsCondInvert) // Invert the condition if needed.
20959 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20960 DAG.getConstant(1, Cond.getValueType()));
20962 // Zero extend the condition if needed.
20963 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
20964 FalseC->getValueType(0), Cond);
20965 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
20966 SDValue(FalseC, 0));
20969 // Optimize cases that will turn into an LEA instruction. This requires
20970 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
20971 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
20972 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
20973 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
20975 bool isFastMultiplier = false;
20977 switch ((unsigned char)Diff) {
20979 case 1: // result = add base, cond
20980 case 2: // result = lea base( , cond*2)
20981 case 3: // result = lea base(cond, cond*2)
20982 case 4: // result = lea base( , cond*4)
20983 case 5: // result = lea base(cond, cond*4)
20984 case 8: // result = lea base( , cond*8)
20985 case 9: // result = lea base(cond, cond*8)
20986 isFastMultiplier = true;
20991 if (isFastMultiplier) {
20992 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
20993 if (NeedsCondInvert) // Invert the condition if needed.
20994 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20995 DAG.getConstant(1, Cond.getValueType()));
20997 // Zero extend the condition if needed.
20998 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21000 // Scale the condition by the difference.
21002 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21003 DAG.getConstant(Diff, Cond.getValueType()));
21005 // Add the base if non-zero.
21006 if (FalseC->getAPIntValue() != 0)
21007 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21008 SDValue(FalseC, 0));
21015 // Canonicalize max and min:
21016 // (x > y) ? x : y -> (x >= y) ? x : y
21017 // (x < y) ? x : y -> (x <= y) ? x : y
21018 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
21019 // the need for an extra compare
21020 // against zero. e.g.
21021 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
21023 // testl %edi, %edi
21025 // cmovgl %edi, %eax
21029 // cmovsl %eax, %edi
21030 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
21031 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21032 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21033 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21038 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
21039 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
21040 Cond.getOperand(0), Cond.getOperand(1), NewCC);
21041 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
21046 // Early exit check
21047 if (!TLI.isTypeLegal(VT))
21050 // Match VSELECTs into subs with unsigned saturation.
21051 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21052 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
21053 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
21054 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
21055 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21057 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
21058 // left side invert the predicate to simplify logic below.
21060 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
21062 CC = ISD::getSetCCInverse(CC, true);
21063 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
21067 if (Other.getNode() && Other->getNumOperands() == 2 &&
21068 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
21069 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
21070 SDValue CondRHS = Cond->getOperand(1);
21072 // Look for a general sub with unsigned saturation first.
21073 // x >= y ? x-y : 0 --> subus x, y
21074 // x > y ? x-y : 0 --> subus x, y
21075 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
21076 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
21077 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
21079 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
21080 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
21081 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
21082 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
21083 // If the RHS is a constant we have to reverse the const
21084 // canonicalization.
21085 // x > C-1 ? x+-C : 0 --> subus x, C
21086 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
21087 CondRHSConst->getAPIntValue() ==
21088 (-OpRHSConst->getAPIntValue() - 1))
21089 return DAG.getNode(
21090 X86ISD::SUBUS, DL, VT, OpLHS,
21091 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
21093 // Another special case: If C was a sign bit, the sub has been
21094 // canonicalized into a xor.
21095 // FIXME: Would it be better to use computeKnownBits to determine
21096 // whether it's safe to decanonicalize the xor?
21097 // x s< 0 ? x^C : 0 --> subus x, C
21098 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
21099 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
21100 OpRHSConst->getAPIntValue().isSignBit())
21101 // Note that we have to rebuild the RHS constant here to ensure we
21102 // don't rely on particular values of undef lanes.
21103 return DAG.getNode(
21104 X86ISD::SUBUS, DL, VT, OpLHS,
21105 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
21110 // Try to match a min/max vector operation.
21111 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
21112 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
21113 unsigned Opc = ret.first;
21114 bool NeedSplit = ret.second;
21116 if (Opc && NeedSplit) {
21117 unsigned NumElems = VT.getVectorNumElements();
21118 // Extract the LHS vectors
21119 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
21120 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
21122 // Extract the RHS vectors
21123 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
21124 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
21126 // Create min/max for each subvector
21127 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
21128 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
21130 // Merge the result
21131 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
21133 return DAG.getNode(Opc, DL, VT, LHS, RHS);
21136 // Simplify vector selection if condition value type matches vselect
21138 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
21139 assert(Cond.getValueType().isVector() &&
21140 "vector select expects a vector selector!");
21142 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
21143 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
21145 // Try invert the condition if true value is not all 1s and false value
21147 if (!TValIsAllOnes && !FValIsAllZeros &&
21148 // Check if the selector will be produced by CMPP*/PCMP*
21149 Cond.getOpcode() == ISD::SETCC &&
21150 // Check if SETCC has already been promoted
21151 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
21152 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
21153 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
21155 if (TValIsAllZeros || FValIsAllOnes) {
21156 SDValue CC = Cond.getOperand(2);
21157 ISD::CondCode NewCC =
21158 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
21159 Cond.getOperand(0).getValueType().isInteger());
21160 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
21161 std::swap(LHS, RHS);
21162 TValIsAllOnes = FValIsAllOnes;
21163 FValIsAllZeros = TValIsAllZeros;
21167 if (TValIsAllOnes || FValIsAllZeros) {
21170 if (TValIsAllOnes && FValIsAllZeros)
21172 else if (TValIsAllOnes)
21173 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
21174 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
21175 else if (FValIsAllZeros)
21176 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
21177 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
21179 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
21183 // We should generate an X86ISD::BLENDI from a vselect if its argument
21184 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
21185 // constants. This specific pattern gets generated when we split a
21186 // selector for a 512 bit vector in a machine without AVX512 (but with
21187 // 256-bit vectors), during legalization:
21189 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
21191 // Iff we find this pattern and the build_vectors are built from
21192 // constants, we translate the vselect into a shuffle_vector that we
21193 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
21194 if ((N->getOpcode() == ISD::VSELECT ||
21195 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
21196 !DCI.isBeforeLegalize()) {
21197 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
21198 if (Shuffle.getNode())
21202 // If this is a *dynamic* select (non-constant condition) and we can match
21203 // this node with one of the variable blend instructions, restructure the
21204 // condition so that the blends can use the high bit of each element and use
21205 // SimplifyDemandedBits to simplify the condition operand.
21206 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
21207 !DCI.isBeforeLegalize() &&
21208 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
21209 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
21211 // Don't optimize vector selects that map to mask-registers.
21215 // We can only handle the cases where VSELECT is directly legal on the
21216 // subtarget. We custom lower VSELECT nodes with constant conditions and
21217 // this makes it hard to see whether a dynamic VSELECT will correctly
21218 // lower, so we both check the operation's status and explicitly handle the
21219 // cases where a *dynamic* blend will fail even though a constant-condition
21220 // blend could be custom lowered.
21221 // FIXME: We should find a better way to handle this class of problems.
21222 // Potentially, we should combine constant-condition vselect nodes
21223 // pre-legalization into shuffles and not mark as many types as custom
21225 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
21227 // FIXME: We don't support i16-element blends currently. We could and
21228 // should support them by making *all* the bits in the condition be set
21229 // rather than just the high bit and using an i8-element blend.
21230 if (VT.getScalarType() == MVT::i16)
21232 // Dynamic blending was only available from SSE4.1 onward.
21233 if (VT.getSizeInBits() == 128 && !Subtarget->hasSSE41())
21235 // Byte blends are only available in AVX2
21236 if (VT.getSizeInBits() == 256 && VT.getScalarType() == MVT::i8 &&
21237 !Subtarget->hasAVX2())
21240 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
21241 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
21243 APInt KnownZero, KnownOne;
21244 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
21245 DCI.isBeforeLegalizeOps());
21246 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
21247 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
21249 // If we changed the computation somewhere in the DAG, this change
21250 // will affect all users of Cond.
21251 // Make sure it is fine and update all the nodes so that we do not
21252 // use the generic VSELECT anymore. Otherwise, we may perform
21253 // wrong optimizations as we messed up with the actual expectation
21254 // for the vector boolean values.
21255 if (Cond != TLO.Old) {
21256 // Check all uses of that condition operand to check whether it will be
21257 // consumed by non-BLEND instructions, which may depend on all bits are
21259 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
21261 if (I->getOpcode() != ISD::VSELECT)
21262 // TODO: Add other opcodes eventually lowered into BLEND.
21265 // Update all the users of the condition, before committing the change,
21266 // so that the VSELECT optimizations that expect the correct vector
21267 // boolean value will not be triggered.
21268 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
21270 DAG.ReplaceAllUsesOfValueWith(
21272 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
21273 Cond, I->getOperand(1), I->getOperand(2)));
21274 DCI.CommitTargetLoweringOpt(TLO);
21277 // At this point, only Cond is changed. Change the condition
21278 // just for N to keep the opportunity to optimize all other
21279 // users their own way.
21280 DAG.ReplaceAllUsesOfValueWith(
21282 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
21283 TLO.New, N->getOperand(1), N->getOperand(2)));
21291 // Check whether a boolean test is testing a boolean value generated by
21292 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
21295 // Simplify the following patterns:
21296 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
21297 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
21298 // to (Op EFLAGS Cond)
21300 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
21301 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
21302 // to (Op EFLAGS !Cond)
21304 // where Op could be BRCOND or CMOV.
21306 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
21307 // Quit if not CMP and SUB with its value result used.
21308 if (Cmp.getOpcode() != X86ISD::CMP &&
21309 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
21312 // Quit if not used as a boolean value.
21313 if (CC != X86::COND_E && CC != X86::COND_NE)
21316 // Check CMP operands. One of them should be 0 or 1 and the other should be
21317 // an SetCC or extended from it.
21318 SDValue Op1 = Cmp.getOperand(0);
21319 SDValue Op2 = Cmp.getOperand(1);
21322 const ConstantSDNode* C = nullptr;
21323 bool needOppositeCond = (CC == X86::COND_E);
21324 bool checkAgainstTrue = false; // Is it a comparison against 1?
21326 if ((C = dyn_cast<ConstantSDNode>(Op1)))
21328 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
21330 else // Quit if all operands are not constants.
21333 if (C->getZExtValue() == 1) {
21334 needOppositeCond = !needOppositeCond;
21335 checkAgainstTrue = true;
21336 } else if (C->getZExtValue() != 0)
21337 // Quit if the constant is neither 0 or 1.
21340 bool truncatedToBoolWithAnd = false;
21341 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
21342 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
21343 SetCC.getOpcode() == ISD::TRUNCATE ||
21344 SetCC.getOpcode() == ISD::AND) {
21345 if (SetCC.getOpcode() == ISD::AND) {
21347 ConstantSDNode *CS;
21348 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
21349 CS->getZExtValue() == 1)
21351 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
21352 CS->getZExtValue() == 1)
21356 SetCC = SetCC.getOperand(OpIdx);
21357 truncatedToBoolWithAnd = true;
21359 SetCC = SetCC.getOperand(0);
21362 switch (SetCC.getOpcode()) {
21363 case X86ISD::SETCC_CARRY:
21364 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
21365 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
21366 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
21367 // truncated to i1 using 'and'.
21368 if (checkAgainstTrue && !truncatedToBoolWithAnd)
21370 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
21371 "Invalid use of SETCC_CARRY!");
21373 case X86ISD::SETCC:
21374 // Set the condition code or opposite one if necessary.
21375 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
21376 if (needOppositeCond)
21377 CC = X86::GetOppositeBranchCondition(CC);
21378 return SetCC.getOperand(1);
21379 case X86ISD::CMOV: {
21380 // Check whether false/true value has canonical one, i.e. 0 or 1.
21381 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
21382 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
21383 // Quit if true value is not a constant.
21386 // Quit if false value is not a constant.
21388 SDValue Op = SetCC.getOperand(0);
21389 // Skip 'zext' or 'trunc' node.
21390 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
21391 Op.getOpcode() == ISD::TRUNCATE)
21392 Op = Op.getOperand(0);
21393 // A special case for rdrand/rdseed, where 0 is set if false cond is
21395 if ((Op.getOpcode() != X86ISD::RDRAND &&
21396 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
21399 // Quit if false value is not the constant 0 or 1.
21400 bool FValIsFalse = true;
21401 if (FVal && FVal->getZExtValue() != 0) {
21402 if (FVal->getZExtValue() != 1)
21404 // If FVal is 1, opposite cond is needed.
21405 needOppositeCond = !needOppositeCond;
21406 FValIsFalse = false;
21408 // Quit if TVal is not the constant opposite of FVal.
21409 if (FValIsFalse && TVal->getZExtValue() != 1)
21411 if (!FValIsFalse && TVal->getZExtValue() != 0)
21413 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
21414 if (needOppositeCond)
21415 CC = X86::GetOppositeBranchCondition(CC);
21416 return SetCC.getOperand(3);
21423 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
21425 /// (X86or (X86setcc) (X86setcc))
21426 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
21427 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
21428 X86::CondCode &CC1, SDValue &Flags,
21430 if (Cond->getOpcode() == X86ISD::CMP) {
21431 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
21432 if (!CondOp1C || !CondOp1C->isNullValue())
21435 Cond = Cond->getOperand(0);
21440 SDValue SetCC0, SetCC1;
21441 switch (Cond->getOpcode()) {
21442 default: return false;
21449 SetCC0 = Cond->getOperand(0);
21450 SetCC1 = Cond->getOperand(1);
21454 // Make sure we have SETCC nodes, using the same flags value.
21455 if (SetCC0.getOpcode() != X86ISD::SETCC ||
21456 SetCC1.getOpcode() != X86ISD::SETCC ||
21457 SetCC0->getOperand(1) != SetCC1->getOperand(1))
21460 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
21461 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
21462 Flags = SetCC0->getOperand(1);
21466 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
21467 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
21468 TargetLowering::DAGCombinerInfo &DCI,
21469 const X86Subtarget *Subtarget) {
21472 // If the flag operand isn't dead, don't touch this CMOV.
21473 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
21476 SDValue FalseOp = N->getOperand(0);
21477 SDValue TrueOp = N->getOperand(1);
21478 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
21479 SDValue Cond = N->getOperand(3);
21481 if (CC == X86::COND_E || CC == X86::COND_NE) {
21482 switch (Cond.getOpcode()) {
21486 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
21487 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
21488 return (CC == X86::COND_E) ? FalseOp : TrueOp;
21494 Flags = checkBoolTestSetCCCombine(Cond, CC);
21495 if (Flags.getNode() &&
21496 // Extra check as FCMOV only supports a subset of X86 cond.
21497 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
21498 SDValue Ops[] = { FalseOp, TrueOp,
21499 DAG.getConstant(CC, MVT::i8), Flags };
21500 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
21503 // If this is a select between two integer constants, try to do some
21504 // optimizations. Note that the operands are ordered the opposite of SELECT
21506 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
21507 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
21508 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
21509 // larger than FalseC (the false value).
21510 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
21511 CC = X86::GetOppositeBranchCondition(CC);
21512 std::swap(TrueC, FalseC);
21513 std::swap(TrueOp, FalseOp);
21516 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
21517 // This is efficient for any integer data type (including i8/i16) and
21519 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
21520 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21521 DAG.getConstant(CC, MVT::i8), Cond);
21523 // Zero extend the condition if needed.
21524 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
21526 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21527 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
21528 DAG.getConstant(ShAmt, MVT::i8));
21529 if (N->getNumValues() == 2) // Dead flag value?
21530 return DCI.CombineTo(N, Cond, SDValue());
21534 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
21535 // for any integer data type, including i8/i16.
21536 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21537 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21538 DAG.getConstant(CC, MVT::i8), Cond);
21540 // Zero extend the condition if needed.
21541 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21542 FalseC->getValueType(0), Cond);
21543 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21544 SDValue(FalseC, 0));
21546 if (N->getNumValues() == 2) // Dead flag value?
21547 return DCI.CombineTo(N, Cond, SDValue());
21551 // Optimize cases that will turn into an LEA instruction. This requires
21552 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21553 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21554 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21555 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21557 bool isFastMultiplier = false;
21559 switch ((unsigned char)Diff) {
21561 case 1: // result = add base, cond
21562 case 2: // result = lea base( , cond*2)
21563 case 3: // result = lea base(cond, cond*2)
21564 case 4: // result = lea base( , cond*4)
21565 case 5: // result = lea base(cond, cond*4)
21566 case 8: // result = lea base( , cond*8)
21567 case 9: // result = lea base(cond, cond*8)
21568 isFastMultiplier = true;
21573 if (isFastMultiplier) {
21574 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21575 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
21576 DAG.getConstant(CC, MVT::i8), Cond);
21577 // Zero extend the condition if needed.
21578 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21580 // Scale the condition by the difference.
21582 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21583 DAG.getConstant(Diff, Cond.getValueType()));
21585 // Add the base if non-zero.
21586 if (FalseC->getAPIntValue() != 0)
21587 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21588 SDValue(FalseC, 0));
21589 if (N->getNumValues() == 2) // Dead flag value?
21590 return DCI.CombineTo(N, Cond, SDValue());
21597 // Handle these cases:
21598 // (select (x != c), e, c) -> select (x != c), e, x),
21599 // (select (x == c), c, e) -> select (x == c), x, e)
21600 // where the c is an integer constant, and the "select" is the combination
21601 // of CMOV and CMP.
21603 // The rationale for this change is that the conditional-move from a constant
21604 // needs two instructions, however, conditional-move from a register needs
21605 // only one instruction.
21607 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
21608 // some instruction-combining opportunities. This opt needs to be
21609 // postponed as late as possible.
21611 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
21612 // the DCI.xxxx conditions are provided to postpone the optimization as
21613 // late as possible.
21615 ConstantSDNode *CmpAgainst = nullptr;
21616 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
21617 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
21618 !isa<ConstantSDNode>(Cond.getOperand(0))) {
21620 if (CC == X86::COND_NE &&
21621 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
21622 CC = X86::GetOppositeBranchCondition(CC);
21623 std::swap(TrueOp, FalseOp);
21626 if (CC == X86::COND_E &&
21627 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
21628 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
21629 DAG.getConstant(CC, MVT::i8), Cond };
21630 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
21635 // Fold and/or of setcc's to double CMOV:
21636 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
21637 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
21639 // This combine lets us generate:
21640 // cmovcc1 (jcc1 if we don't have CMOV)
21646 // cmovne (jne if we don't have CMOV)
21647 // When we can't use the CMOV instruction, it might increase branch
21649 // When we can use CMOV, or when there is no mispredict, this improves
21650 // throughput and reduces register pressure.
21652 if (CC == X86::COND_NE) {
21654 X86::CondCode CC0, CC1;
21656 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
21658 std::swap(FalseOp, TrueOp);
21659 CC0 = X86::GetOppositeBranchCondition(CC0);
21660 CC1 = X86::GetOppositeBranchCondition(CC1);
21663 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, MVT::i8),
21665 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
21666 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, MVT::i8), Flags};
21667 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
21668 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
21676 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
21677 const X86Subtarget *Subtarget) {
21678 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
21680 default: return SDValue();
21681 // SSE/AVX/AVX2 blend intrinsics.
21682 case Intrinsic::x86_avx2_pblendvb:
21683 // Don't try to simplify this intrinsic if we don't have AVX2.
21684 if (!Subtarget->hasAVX2())
21687 case Intrinsic::x86_avx_blendv_pd_256:
21688 case Intrinsic::x86_avx_blendv_ps_256:
21689 // Don't try to simplify this intrinsic if we don't have AVX.
21690 if (!Subtarget->hasAVX())
21693 case Intrinsic::x86_sse41_blendvps:
21694 case Intrinsic::x86_sse41_blendvpd:
21695 case Intrinsic::x86_sse41_pblendvb: {
21696 SDValue Op0 = N->getOperand(1);
21697 SDValue Op1 = N->getOperand(2);
21698 SDValue Mask = N->getOperand(3);
21700 // Don't try to simplify this intrinsic if we don't have SSE4.1.
21701 if (!Subtarget->hasSSE41())
21704 // fold (blend A, A, Mask) -> A
21707 // fold (blend A, B, allZeros) -> A
21708 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
21710 // fold (blend A, B, allOnes) -> B
21711 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
21714 // Simplify the case where the mask is a constant i32 value.
21715 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
21716 if (C->isNullValue())
21718 if (C->isAllOnesValue())
21725 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
21726 case Intrinsic::x86_sse2_psrai_w:
21727 case Intrinsic::x86_sse2_psrai_d:
21728 case Intrinsic::x86_avx2_psrai_w:
21729 case Intrinsic::x86_avx2_psrai_d:
21730 case Intrinsic::x86_sse2_psra_w:
21731 case Intrinsic::x86_sse2_psra_d:
21732 case Intrinsic::x86_avx2_psra_w:
21733 case Intrinsic::x86_avx2_psra_d: {
21734 SDValue Op0 = N->getOperand(1);
21735 SDValue Op1 = N->getOperand(2);
21736 EVT VT = Op0.getValueType();
21737 assert(VT.isVector() && "Expected a vector type!");
21739 if (isa<BuildVectorSDNode>(Op1))
21740 Op1 = Op1.getOperand(0);
21742 if (!isa<ConstantSDNode>(Op1))
21745 EVT SVT = VT.getVectorElementType();
21746 unsigned SVTBits = SVT.getSizeInBits();
21748 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
21749 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
21750 uint64_t ShAmt = C.getZExtValue();
21752 // Don't try to convert this shift into a ISD::SRA if the shift
21753 // count is bigger than or equal to the element size.
21754 if (ShAmt >= SVTBits)
21757 // Trivial case: if the shift count is zero, then fold this
21758 // into the first operand.
21762 // Replace this packed shift intrinsic with a target independent
21764 SDValue Splat = DAG.getConstant(C, VT);
21765 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
21770 /// PerformMulCombine - Optimize a single multiply with constant into two
21771 /// in order to implement it with two cheaper instructions, e.g.
21772 /// LEA + SHL, LEA + LEA.
21773 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
21774 TargetLowering::DAGCombinerInfo &DCI) {
21775 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
21778 EVT VT = N->getValueType(0);
21779 if (VT != MVT::i64 && VT != MVT::i32)
21782 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
21785 uint64_t MulAmt = C->getZExtValue();
21786 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
21789 uint64_t MulAmt1 = 0;
21790 uint64_t MulAmt2 = 0;
21791 if ((MulAmt % 9) == 0) {
21793 MulAmt2 = MulAmt / 9;
21794 } else if ((MulAmt % 5) == 0) {
21796 MulAmt2 = MulAmt / 5;
21797 } else if ((MulAmt % 3) == 0) {
21799 MulAmt2 = MulAmt / 3;
21802 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
21805 if (isPowerOf2_64(MulAmt2) &&
21806 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
21807 // If second multiplifer is pow2, issue it first. We want the multiply by
21808 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
21810 std::swap(MulAmt1, MulAmt2);
21813 if (isPowerOf2_64(MulAmt1))
21814 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
21815 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
21817 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
21818 DAG.getConstant(MulAmt1, VT));
21820 if (isPowerOf2_64(MulAmt2))
21821 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
21822 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
21824 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
21825 DAG.getConstant(MulAmt2, VT));
21827 // Do not add new nodes to DAG combiner worklist.
21828 DCI.CombineTo(N, NewMul, false);
21833 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
21834 SDValue N0 = N->getOperand(0);
21835 SDValue N1 = N->getOperand(1);
21836 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
21837 EVT VT = N0.getValueType();
21839 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
21840 // since the result of setcc_c is all zero's or all ones.
21841 if (VT.isInteger() && !VT.isVector() &&
21842 N1C && N0.getOpcode() == ISD::AND &&
21843 N0.getOperand(1).getOpcode() == ISD::Constant) {
21844 SDValue N00 = N0.getOperand(0);
21845 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
21846 ((N00.getOpcode() == ISD::ANY_EXTEND ||
21847 N00.getOpcode() == ISD::ZERO_EXTEND) &&
21848 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
21849 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
21850 APInt ShAmt = N1C->getAPIntValue();
21851 Mask = Mask.shl(ShAmt);
21853 return DAG.getNode(ISD::AND, SDLoc(N), VT,
21854 N00, DAG.getConstant(Mask, VT));
21858 // Hardware support for vector shifts is sparse which makes us scalarize the
21859 // vector operations in many cases. Also, on sandybridge ADD is faster than
21861 // (shl V, 1) -> add V,V
21862 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
21863 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
21864 assert(N0.getValueType().isVector() && "Invalid vector shift type");
21865 // We shift all of the values by one. In many cases we do not have
21866 // hardware support for this operation. This is better expressed as an ADD
21868 if (N1SplatC->getZExtValue() == 1)
21869 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
21875 /// \brief Returns a vector of 0s if the node in input is a vector logical
21876 /// shift by a constant amount which is known to be bigger than or equal
21877 /// to the vector element size in bits.
21878 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
21879 const X86Subtarget *Subtarget) {
21880 EVT VT = N->getValueType(0);
21882 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
21883 (!Subtarget->hasInt256() ||
21884 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
21887 SDValue Amt = N->getOperand(1);
21889 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
21890 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
21891 APInt ShiftAmt = AmtSplat->getAPIntValue();
21892 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
21894 // SSE2/AVX2 logical shifts always return a vector of 0s
21895 // if the shift amount is bigger than or equal to
21896 // the element size. The constant shift amount will be
21897 // encoded as a 8-bit immediate.
21898 if (ShiftAmt.trunc(8).uge(MaxAmount))
21899 return getZeroVector(VT, Subtarget, DAG, DL);
21905 /// PerformShiftCombine - Combine shifts.
21906 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
21907 TargetLowering::DAGCombinerInfo &DCI,
21908 const X86Subtarget *Subtarget) {
21909 if (N->getOpcode() == ISD::SHL) {
21910 SDValue V = PerformSHLCombine(N, DAG);
21911 if (V.getNode()) return V;
21914 if (N->getOpcode() != ISD::SRA) {
21915 // Try to fold this logical shift into a zero vector.
21916 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
21917 if (V.getNode()) return V;
21923 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
21924 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
21925 // and friends. Likewise for OR -> CMPNEQSS.
21926 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
21927 TargetLowering::DAGCombinerInfo &DCI,
21928 const X86Subtarget *Subtarget) {
21931 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
21932 // we're requiring SSE2 for both.
21933 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
21934 SDValue N0 = N->getOperand(0);
21935 SDValue N1 = N->getOperand(1);
21936 SDValue CMP0 = N0->getOperand(1);
21937 SDValue CMP1 = N1->getOperand(1);
21940 // The SETCCs should both refer to the same CMP.
21941 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
21944 SDValue CMP00 = CMP0->getOperand(0);
21945 SDValue CMP01 = CMP0->getOperand(1);
21946 EVT VT = CMP00.getValueType();
21948 if (VT == MVT::f32 || VT == MVT::f64) {
21949 bool ExpectingFlags = false;
21950 // Check for any users that want flags:
21951 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
21952 !ExpectingFlags && UI != UE; ++UI)
21953 switch (UI->getOpcode()) {
21958 ExpectingFlags = true;
21960 case ISD::CopyToReg:
21961 case ISD::SIGN_EXTEND:
21962 case ISD::ZERO_EXTEND:
21963 case ISD::ANY_EXTEND:
21967 if (!ExpectingFlags) {
21968 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
21969 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
21971 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
21972 X86::CondCode tmp = cc0;
21977 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
21978 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
21979 // FIXME: need symbolic constants for these magic numbers.
21980 // See X86ATTInstPrinter.cpp:printSSECC().
21981 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
21982 if (Subtarget->hasAVX512()) {
21983 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
21984 CMP01, DAG.getConstant(x86cc, MVT::i8));
21985 if (N->getValueType(0) != MVT::i1)
21986 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
21990 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
21991 CMP00.getValueType(), CMP00, CMP01,
21992 DAG.getConstant(x86cc, MVT::i8));
21994 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
21995 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
21997 if (is64BitFP && !Subtarget->is64Bit()) {
21998 // On a 32-bit target, we cannot bitcast the 64-bit float to a
21999 // 64-bit integer, since that's not a legal type. Since
22000 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
22001 // bits, but can do this little dance to extract the lowest 32 bits
22002 // and work with those going forward.
22003 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
22005 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
22007 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
22008 Vector32, DAG.getIntPtrConstant(0));
22012 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
22013 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
22014 DAG.getConstant(1, IntVT));
22015 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
22016 return OneBitOfTruth;
22024 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
22025 /// so it can be folded inside ANDNP.
22026 static bool CanFoldXORWithAllOnes(const SDNode *N) {
22027 EVT VT = N->getValueType(0);
22029 // Match direct AllOnes for 128 and 256-bit vectors
22030 if (ISD::isBuildVectorAllOnes(N))
22033 // Look through a bit convert.
22034 if (N->getOpcode() == ISD::BITCAST)
22035 N = N->getOperand(0).getNode();
22037 // Sometimes the operand may come from a insert_subvector building a 256-bit
22039 if (VT.is256BitVector() &&
22040 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
22041 SDValue V1 = N->getOperand(0);
22042 SDValue V2 = N->getOperand(1);
22044 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
22045 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
22046 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
22047 ISD::isBuildVectorAllOnes(V2.getNode()))
22054 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
22055 // register. In most cases we actually compare or select YMM-sized registers
22056 // and mixing the two types creates horrible code. This method optimizes
22057 // some of the transition sequences.
22058 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
22059 TargetLowering::DAGCombinerInfo &DCI,
22060 const X86Subtarget *Subtarget) {
22061 EVT VT = N->getValueType(0);
22062 if (!VT.is256BitVector())
22065 assert((N->getOpcode() == ISD::ANY_EXTEND ||
22066 N->getOpcode() == ISD::ZERO_EXTEND ||
22067 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
22069 SDValue Narrow = N->getOperand(0);
22070 EVT NarrowVT = Narrow->getValueType(0);
22071 if (!NarrowVT.is128BitVector())
22074 if (Narrow->getOpcode() != ISD::XOR &&
22075 Narrow->getOpcode() != ISD::AND &&
22076 Narrow->getOpcode() != ISD::OR)
22079 SDValue N0 = Narrow->getOperand(0);
22080 SDValue N1 = Narrow->getOperand(1);
22083 // The Left side has to be a trunc.
22084 if (N0.getOpcode() != ISD::TRUNCATE)
22087 // The type of the truncated inputs.
22088 EVT WideVT = N0->getOperand(0)->getValueType(0);
22092 // The right side has to be a 'trunc' or a constant vector.
22093 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
22094 ConstantSDNode *RHSConstSplat = nullptr;
22095 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
22096 RHSConstSplat = RHSBV->getConstantSplatNode();
22097 if (!RHSTrunc && !RHSConstSplat)
22100 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22102 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
22105 // Set N0 and N1 to hold the inputs to the new wide operation.
22106 N0 = N0->getOperand(0);
22107 if (RHSConstSplat) {
22108 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
22109 SDValue(RHSConstSplat, 0));
22110 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
22111 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
22112 } else if (RHSTrunc) {
22113 N1 = N1->getOperand(0);
22116 // Generate the wide operation.
22117 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
22118 unsigned Opcode = N->getOpcode();
22120 case ISD::ANY_EXTEND:
22122 case ISD::ZERO_EXTEND: {
22123 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
22124 APInt Mask = APInt::getAllOnesValue(InBits);
22125 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
22126 return DAG.getNode(ISD::AND, DL, VT,
22127 Op, DAG.getConstant(Mask, VT));
22129 case ISD::SIGN_EXTEND:
22130 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
22131 Op, DAG.getValueType(NarrowVT));
22133 llvm_unreachable("Unexpected opcode");
22137 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
22138 TargetLowering::DAGCombinerInfo &DCI,
22139 const X86Subtarget *Subtarget) {
22140 SDValue N0 = N->getOperand(0);
22141 SDValue N1 = N->getOperand(1);
22144 // A vector zext_in_reg may be represented as a shuffle,
22145 // feeding into a bitcast (this represents anyext) feeding into
22146 // an and with a mask.
22147 // We'd like to try to combine that into a shuffle with zero
22148 // plus a bitcast, removing the and.
22149 if (N0.getOpcode() != ISD::BITCAST ||
22150 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
22153 // The other side of the AND should be a splat of 2^C, where C
22154 // is the number of bits in the source type.
22155 if (N1.getOpcode() == ISD::BITCAST)
22156 N1 = N1.getOperand(0);
22157 if (N1.getOpcode() != ISD::BUILD_VECTOR)
22159 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
22161 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
22162 EVT SrcType = Shuffle->getValueType(0);
22164 // We expect a single-source shuffle
22165 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
22168 unsigned SrcSize = SrcType.getScalarSizeInBits();
22170 APInt SplatValue, SplatUndef;
22171 unsigned SplatBitSize;
22173 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
22174 SplatBitSize, HasAnyUndefs))
22177 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
22178 // Make sure the splat matches the mask we expect
22179 if (SplatBitSize > ResSize ||
22180 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
22183 // Make sure the input and output size make sense
22184 if (SrcSize >= ResSize || ResSize % SrcSize)
22187 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
22188 // The number of u's between each two values depends on the ratio between
22189 // the source and dest type.
22190 unsigned ZextRatio = ResSize / SrcSize;
22191 bool IsZext = true;
22192 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
22193 if (i % ZextRatio) {
22194 if (Shuffle->getMaskElt(i) > 0) {
22200 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
22201 // Expected element number
22211 // Ok, perform the transformation - replace the shuffle with
22212 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
22213 // (instead of undef) where the k elements come from the zero vector.
22214 SmallVector<int, 8> Mask;
22215 unsigned NumElems = SrcType.getVectorNumElements();
22216 for (unsigned i = 0; i < NumElems; ++i)
22218 Mask.push_back(NumElems);
22220 Mask.push_back(i / ZextRatio);
22222 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
22223 Shuffle->getOperand(0), DAG.getConstant(0, SrcType), Mask);
22224 return DAG.getNode(ISD::BITCAST, DL, N0.getValueType(), NewShuffle);
22227 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
22228 TargetLowering::DAGCombinerInfo &DCI,
22229 const X86Subtarget *Subtarget) {
22230 if (DCI.isBeforeLegalizeOps())
22233 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
22236 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
22239 EVT VT = N->getValueType(0);
22240 SDValue N0 = N->getOperand(0);
22241 SDValue N1 = N->getOperand(1);
22244 // Create BEXTR instructions
22245 // BEXTR is ((X >> imm) & (2**size-1))
22246 if (VT == MVT::i32 || VT == MVT::i64) {
22247 // Check for BEXTR.
22248 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
22249 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
22250 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
22251 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
22252 if (MaskNode && ShiftNode) {
22253 uint64_t Mask = MaskNode->getZExtValue();
22254 uint64_t Shift = ShiftNode->getZExtValue();
22255 if (isMask_64(Mask)) {
22256 uint64_t MaskSize = countPopulation(Mask);
22257 if (Shift + MaskSize <= VT.getSizeInBits())
22258 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
22259 DAG.getConstant(Shift | (MaskSize << 8), VT));
22267 // Want to form ANDNP nodes:
22268 // 1) In the hopes of then easily combining them with OR and AND nodes
22269 // to form PBLEND/PSIGN.
22270 // 2) To match ANDN packed intrinsics
22271 if (VT != MVT::v2i64 && VT != MVT::v4i64)
22274 // Check LHS for vnot
22275 if (N0.getOpcode() == ISD::XOR &&
22276 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
22277 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
22278 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
22280 // Check RHS for vnot
22281 if (N1.getOpcode() == ISD::XOR &&
22282 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
22283 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
22284 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
22289 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
22290 TargetLowering::DAGCombinerInfo &DCI,
22291 const X86Subtarget *Subtarget) {
22292 if (DCI.isBeforeLegalizeOps())
22295 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
22299 SDValue N0 = N->getOperand(0);
22300 SDValue N1 = N->getOperand(1);
22301 EVT VT = N->getValueType(0);
22303 // look for psign/blend
22304 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
22305 if (!Subtarget->hasSSSE3() ||
22306 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
22309 // Canonicalize pandn to RHS
22310 if (N0.getOpcode() == X86ISD::ANDNP)
22312 // or (and (m, y), (pandn m, x))
22313 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
22314 SDValue Mask = N1.getOperand(0);
22315 SDValue X = N1.getOperand(1);
22317 if (N0.getOperand(0) == Mask)
22318 Y = N0.getOperand(1);
22319 if (N0.getOperand(1) == Mask)
22320 Y = N0.getOperand(0);
22322 // Check to see if the mask appeared in both the AND and ANDNP and
22326 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
22327 // Look through mask bitcast.
22328 if (Mask.getOpcode() == ISD::BITCAST)
22329 Mask = Mask.getOperand(0);
22330 if (X.getOpcode() == ISD::BITCAST)
22331 X = X.getOperand(0);
22332 if (Y.getOpcode() == ISD::BITCAST)
22333 Y = Y.getOperand(0);
22335 EVT MaskVT = Mask.getValueType();
22337 // Validate that the Mask operand is a vector sra node.
22338 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
22339 // there is no psrai.b
22340 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
22341 unsigned SraAmt = ~0;
22342 if (Mask.getOpcode() == ISD::SRA) {
22343 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
22344 if (auto *AmtConst = AmtBV->getConstantSplatNode())
22345 SraAmt = AmtConst->getZExtValue();
22346 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
22347 SDValue SraC = Mask.getOperand(1);
22348 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
22350 if ((SraAmt + 1) != EltBits)
22355 // Now we know we at least have a plendvb with the mask val. See if
22356 // we can form a psignb/w/d.
22357 // psign = x.type == y.type == mask.type && y = sub(0, x);
22358 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
22359 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
22360 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
22361 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
22362 "Unsupported VT for PSIGN");
22363 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
22364 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22366 // PBLENDVB only available on SSE 4.1
22367 if (!Subtarget->hasSSE41())
22370 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
22372 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
22373 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
22374 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
22375 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
22376 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
22380 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
22383 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
22384 MachineFunction &MF = DAG.getMachineFunction();
22386 MF.getFunction()->hasFnAttribute(Attribute::OptimizeForSize);
22388 // SHLD/SHRD instructions have lower register pressure, but on some
22389 // platforms they have higher latency than the equivalent
22390 // series of shifts/or that would otherwise be generated.
22391 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
22392 // have higher latencies and we are not optimizing for size.
22393 if (!OptForSize && Subtarget->isSHLDSlow())
22396 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
22398 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
22400 if (!N0.hasOneUse() || !N1.hasOneUse())
22403 SDValue ShAmt0 = N0.getOperand(1);
22404 if (ShAmt0.getValueType() != MVT::i8)
22406 SDValue ShAmt1 = N1.getOperand(1);
22407 if (ShAmt1.getValueType() != MVT::i8)
22409 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
22410 ShAmt0 = ShAmt0.getOperand(0);
22411 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
22412 ShAmt1 = ShAmt1.getOperand(0);
22415 unsigned Opc = X86ISD::SHLD;
22416 SDValue Op0 = N0.getOperand(0);
22417 SDValue Op1 = N1.getOperand(0);
22418 if (ShAmt0.getOpcode() == ISD::SUB) {
22419 Opc = X86ISD::SHRD;
22420 std::swap(Op0, Op1);
22421 std::swap(ShAmt0, ShAmt1);
22424 unsigned Bits = VT.getSizeInBits();
22425 if (ShAmt1.getOpcode() == ISD::SUB) {
22426 SDValue Sum = ShAmt1.getOperand(0);
22427 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
22428 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
22429 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
22430 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
22431 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
22432 return DAG.getNode(Opc, DL, VT,
22434 DAG.getNode(ISD::TRUNCATE, DL,
22437 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
22438 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
22440 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
22441 return DAG.getNode(Opc, DL, VT,
22442 N0.getOperand(0), N1.getOperand(0),
22443 DAG.getNode(ISD::TRUNCATE, DL,
22450 // Generate NEG and CMOV for integer abs.
22451 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
22452 EVT VT = N->getValueType(0);
22454 // Since X86 does not have CMOV for 8-bit integer, we don't convert
22455 // 8-bit integer abs to NEG and CMOV.
22456 if (VT.isInteger() && VT.getSizeInBits() == 8)
22459 SDValue N0 = N->getOperand(0);
22460 SDValue N1 = N->getOperand(1);
22463 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
22464 // and change it to SUB and CMOV.
22465 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
22466 N0.getOpcode() == ISD::ADD &&
22467 N0.getOperand(1) == N1 &&
22468 N1.getOpcode() == ISD::SRA &&
22469 N1.getOperand(0) == N0.getOperand(0))
22470 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
22471 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
22472 // Generate SUB & CMOV.
22473 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
22474 DAG.getConstant(0, VT), N0.getOperand(0));
22476 SDValue Ops[] = { N0.getOperand(0), Neg,
22477 DAG.getConstant(X86::COND_GE, MVT::i8),
22478 SDValue(Neg.getNode(), 1) };
22479 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
22484 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
22485 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
22486 TargetLowering::DAGCombinerInfo &DCI,
22487 const X86Subtarget *Subtarget) {
22488 if (DCI.isBeforeLegalizeOps())
22491 if (Subtarget->hasCMov()) {
22492 SDValue RV = performIntegerAbsCombine(N, DAG);
22500 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
22501 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
22502 TargetLowering::DAGCombinerInfo &DCI,
22503 const X86Subtarget *Subtarget) {
22504 LoadSDNode *Ld = cast<LoadSDNode>(N);
22505 EVT RegVT = Ld->getValueType(0);
22506 EVT MemVT = Ld->getMemoryVT();
22508 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22510 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
22511 // into two 16-byte operations.
22512 ISD::LoadExtType Ext = Ld->getExtensionType();
22513 unsigned Alignment = Ld->getAlignment();
22514 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
22515 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
22516 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
22517 unsigned NumElems = RegVT.getVectorNumElements();
22521 SDValue Ptr = Ld->getBasePtr();
22522 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
22524 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
22526 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22527 Ld->getPointerInfo(), Ld->isVolatile(),
22528 Ld->isNonTemporal(), Ld->isInvariant(),
22530 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22531 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
22532 Ld->getPointerInfo(), Ld->isVolatile(),
22533 Ld->isNonTemporal(), Ld->isInvariant(),
22534 std::min(16U, Alignment));
22535 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22537 Load2.getValue(1));
22539 SDValue NewVec = DAG.getUNDEF(RegVT);
22540 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
22541 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
22542 return DCI.CombineTo(N, NewVec, TF, true);
22548 /// PerformMLOADCombine - Resolve extending loads
22549 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
22550 TargetLowering::DAGCombinerInfo &DCI,
22551 const X86Subtarget *Subtarget) {
22552 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
22553 if (Mld->getExtensionType() != ISD::SEXTLOAD)
22556 EVT VT = Mld->getValueType(0);
22557 unsigned NumElems = VT.getVectorNumElements();
22558 EVT LdVT = Mld->getMemoryVT();
22561 assert(LdVT != VT && "Cannot extend to the same type");
22562 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
22563 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
22564 // From, To sizes and ElemCount must be pow of two
22565 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
22566 "Unexpected size for extending masked load");
22568 unsigned SizeRatio = ToSz / FromSz;
22569 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
22571 // Create a type on which we perform the shuffle
22572 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
22573 LdVT.getScalarType(), NumElems*SizeRatio);
22574 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
22576 // Convert Src0 value
22577 SDValue WideSrc0 = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mld->getSrc0());
22578 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
22579 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
22580 for (unsigned i = 0; i != NumElems; ++i)
22581 ShuffleVec[i] = i * SizeRatio;
22583 // Can't shuffle using an illegal type.
22584 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
22585 && "WideVecVT should be legal");
22586 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
22587 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
22589 // Prepare the new mask
22591 SDValue Mask = Mld->getMask();
22592 if (Mask.getValueType() == VT) {
22593 // Mask and original value have the same type
22594 NewMask = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mask);
22595 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
22596 for (unsigned i = 0; i != NumElems; ++i)
22597 ShuffleVec[i] = i * SizeRatio;
22598 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
22599 ShuffleVec[i] = NumElems*SizeRatio;
22600 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
22601 DAG.getConstant(0, WideVecVT),
22605 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
22606 unsigned WidenNumElts = NumElems*SizeRatio;
22607 unsigned MaskNumElts = VT.getVectorNumElements();
22608 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
22611 unsigned NumConcat = WidenNumElts / MaskNumElts;
22612 SmallVector<SDValue, 16> Ops(NumConcat);
22613 SDValue ZeroVal = DAG.getConstant(0, Mask.getValueType());
22615 for (unsigned i = 1; i != NumConcat; ++i)
22618 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
22621 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
22622 Mld->getBasePtr(), NewMask, WideSrc0,
22623 Mld->getMemoryVT(), Mld->getMemOperand(),
22625 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
22626 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
22629 /// PerformMSTORECombine - Resolve truncating stores
22630 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
22631 const X86Subtarget *Subtarget) {
22632 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
22633 if (!Mst->isTruncatingStore())
22636 EVT VT = Mst->getValue().getValueType();
22637 unsigned NumElems = VT.getVectorNumElements();
22638 EVT StVT = Mst->getMemoryVT();
22641 assert(StVT != VT && "Cannot truncate to the same type");
22642 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
22643 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
22645 // From, To sizes and ElemCount must be pow of two
22646 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
22647 "Unexpected size for truncating masked store");
22648 // We are going to use the original vector elt for storing.
22649 // Accumulated smaller vector elements must be a multiple of the store size.
22650 assert (((NumElems * FromSz) % ToSz) == 0 &&
22651 "Unexpected ratio for truncating masked store");
22653 unsigned SizeRatio = FromSz / ToSz;
22654 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
22656 // Create a type on which we perform the shuffle
22657 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
22658 StVT.getScalarType(), NumElems*SizeRatio);
22660 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
22662 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mst->getValue());
22663 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
22664 for (unsigned i = 0; i != NumElems; ++i)
22665 ShuffleVec[i] = i * SizeRatio;
22667 // Can't shuffle using an illegal type.
22668 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
22669 && "WideVecVT should be legal");
22671 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
22672 DAG.getUNDEF(WideVecVT),
22676 SDValue Mask = Mst->getMask();
22677 if (Mask.getValueType() == VT) {
22678 // Mask and original value have the same type
22679 NewMask = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Mask);
22680 for (unsigned i = 0; i != NumElems; ++i)
22681 ShuffleVec[i] = i * SizeRatio;
22682 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
22683 ShuffleVec[i] = NumElems*SizeRatio;
22684 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
22685 DAG.getConstant(0, WideVecVT),
22689 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
22690 unsigned WidenNumElts = NumElems*SizeRatio;
22691 unsigned MaskNumElts = VT.getVectorNumElements();
22692 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
22695 unsigned NumConcat = WidenNumElts / MaskNumElts;
22696 SmallVector<SDValue, 16> Ops(NumConcat);
22697 SDValue ZeroVal = DAG.getConstant(0, Mask.getValueType());
22699 for (unsigned i = 1; i != NumConcat; ++i)
22702 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
22705 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
22706 NewMask, StVT, Mst->getMemOperand(), false);
22708 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
22709 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
22710 const X86Subtarget *Subtarget) {
22711 StoreSDNode *St = cast<StoreSDNode>(N);
22712 EVT VT = St->getValue().getValueType();
22713 EVT StVT = St->getMemoryVT();
22715 SDValue StoredVal = St->getOperand(1);
22716 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22718 // If we are saving a concatenation of two XMM registers and 32-byte stores
22719 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
22720 unsigned Alignment = St->getAlignment();
22721 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
22722 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
22723 StVT == VT && !IsAligned) {
22724 unsigned NumElems = VT.getVectorNumElements();
22728 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
22729 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
22731 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
22732 SDValue Ptr0 = St->getBasePtr();
22733 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
22735 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
22736 St->getPointerInfo(), St->isVolatile(),
22737 St->isNonTemporal(), Alignment);
22738 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
22739 St->getPointerInfo(), St->isVolatile(),
22740 St->isNonTemporal(),
22741 std::min(16U, Alignment));
22742 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
22745 // Optimize trunc store (of multiple scalars) to shuffle and store.
22746 // First, pack all of the elements in one place. Next, store to memory
22747 // in fewer chunks.
22748 if (St->isTruncatingStore() && VT.isVector()) {
22749 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22750 unsigned NumElems = VT.getVectorNumElements();
22751 assert(StVT != VT && "Cannot truncate to the same type");
22752 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
22753 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
22755 // From, To sizes and ElemCount must be pow of two
22756 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
22757 // We are going to use the original vector elt for storing.
22758 // Accumulated smaller vector elements must be a multiple of the store size.
22759 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
22761 unsigned SizeRatio = FromSz / ToSz;
22763 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
22765 // Create a type on which we perform the shuffle
22766 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
22767 StVT.getScalarType(), NumElems*SizeRatio);
22769 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
22771 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
22772 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
22773 for (unsigned i = 0; i != NumElems; ++i)
22774 ShuffleVec[i] = i * SizeRatio;
22776 // Can't shuffle using an illegal type.
22777 if (!TLI.isTypeLegal(WideVecVT))
22780 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
22781 DAG.getUNDEF(WideVecVT),
22783 // At this point all of the data is stored at the bottom of the
22784 // register. We now need to save it to mem.
22786 // Find the largest store unit
22787 MVT StoreType = MVT::i8;
22788 for (MVT Tp : MVT::integer_valuetypes()) {
22789 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
22793 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
22794 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
22795 (64 <= NumElems * ToSz))
22796 StoreType = MVT::f64;
22798 // Bitcast the original vector into a vector of store-size units
22799 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
22800 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
22801 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
22802 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
22803 SmallVector<SDValue, 8> Chains;
22804 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
22805 TLI.getPointerTy());
22806 SDValue Ptr = St->getBasePtr();
22808 // Perform one or more big stores into memory.
22809 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
22810 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
22811 StoreType, ShuffWide,
22812 DAG.getIntPtrConstant(i));
22813 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
22814 St->getPointerInfo(), St->isVolatile(),
22815 St->isNonTemporal(), St->getAlignment());
22816 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
22817 Chains.push_back(Ch);
22820 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
22823 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
22824 // the FP state in cases where an emms may be missing.
22825 // A preferable solution to the general problem is to figure out the right
22826 // places to insert EMMS. This qualifies as a quick hack.
22828 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
22829 if (VT.getSizeInBits() != 64)
22832 const Function *F = DAG.getMachineFunction().getFunction();
22833 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
22834 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
22835 && Subtarget->hasSSE2();
22836 if ((VT.isVector() ||
22837 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
22838 isa<LoadSDNode>(St->getValue()) &&
22839 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
22840 St->getChain().hasOneUse() && !St->isVolatile()) {
22841 SDNode* LdVal = St->getValue().getNode();
22842 LoadSDNode *Ld = nullptr;
22843 int TokenFactorIndex = -1;
22844 SmallVector<SDValue, 8> Ops;
22845 SDNode* ChainVal = St->getChain().getNode();
22846 // Must be a store of a load. We currently handle two cases: the load
22847 // is a direct child, and it's under an intervening TokenFactor. It is
22848 // possible to dig deeper under nested TokenFactors.
22849 if (ChainVal == LdVal)
22850 Ld = cast<LoadSDNode>(St->getChain());
22851 else if (St->getValue().hasOneUse() &&
22852 ChainVal->getOpcode() == ISD::TokenFactor) {
22853 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
22854 if (ChainVal->getOperand(i).getNode() == LdVal) {
22855 TokenFactorIndex = i;
22856 Ld = cast<LoadSDNode>(St->getValue());
22858 Ops.push_back(ChainVal->getOperand(i));
22862 if (!Ld || !ISD::isNormalLoad(Ld))
22865 // If this is not the MMX case, i.e. we are just turning i64 load/store
22866 // into f64 load/store, avoid the transformation if there are multiple
22867 // uses of the loaded value.
22868 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
22873 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
22874 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
22876 if (Subtarget->is64Bit() || F64IsLegal) {
22877 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
22878 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
22879 Ld->getPointerInfo(), Ld->isVolatile(),
22880 Ld->isNonTemporal(), Ld->isInvariant(),
22881 Ld->getAlignment());
22882 SDValue NewChain = NewLd.getValue(1);
22883 if (TokenFactorIndex != -1) {
22884 Ops.push_back(NewChain);
22885 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
22887 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
22888 St->getPointerInfo(),
22889 St->isVolatile(), St->isNonTemporal(),
22890 St->getAlignment());
22893 // Otherwise, lower to two pairs of 32-bit loads / stores.
22894 SDValue LoAddr = Ld->getBasePtr();
22895 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
22896 DAG.getConstant(4, MVT::i32));
22898 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
22899 Ld->getPointerInfo(),
22900 Ld->isVolatile(), Ld->isNonTemporal(),
22901 Ld->isInvariant(), Ld->getAlignment());
22902 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
22903 Ld->getPointerInfo().getWithOffset(4),
22904 Ld->isVolatile(), Ld->isNonTemporal(),
22906 MinAlign(Ld->getAlignment(), 4));
22908 SDValue NewChain = LoLd.getValue(1);
22909 if (TokenFactorIndex != -1) {
22910 Ops.push_back(LoLd);
22911 Ops.push_back(HiLd);
22912 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
22915 LoAddr = St->getBasePtr();
22916 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
22917 DAG.getConstant(4, MVT::i32));
22919 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
22920 St->getPointerInfo(),
22921 St->isVolatile(), St->isNonTemporal(),
22922 St->getAlignment());
22923 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
22924 St->getPointerInfo().getWithOffset(4),
22926 St->isNonTemporal(),
22927 MinAlign(St->getAlignment(), 4));
22928 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
22933 /// Return 'true' if this vector operation is "horizontal"
22934 /// and return the operands for the horizontal operation in LHS and RHS. A
22935 /// horizontal operation performs the binary operation on successive elements
22936 /// of its first operand, then on successive elements of its second operand,
22937 /// returning the resulting values in a vector. For example, if
22938 /// A = < float a0, float a1, float a2, float a3 >
22940 /// B = < float b0, float b1, float b2, float b3 >
22941 /// then the result of doing a horizontal operation on A and B is
22942 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
22943 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
22944 /// A horizontal-op B, for some already available A and B, and if so then LHS is
22945 /// set to A, RHS to B, and the routine returns 'true'.
22946 /// Note that the binary operation should have the property that if one of the
22947 /// operands is UNDEF then the result is UNDEF.
22948 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
22949 // Look for the following pattern: if
22950 // A = < float a0, float a1, float a2, float a3 >
22951 // B = < float b0, float b1, float b2, float b3 >
22953 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
22954 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
22955 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
22956 // which is A horizontal-op B.
22958 // At least one of the operands should be a vector shuffle.
22959 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
22960 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
22963 MVT VT = LHS.getSimpleValueType();
22965 assert((VT.is128BitVector() || VT.is256BitVector()) &&
22966 "Unsupported vector type for horizontal add/sub");
22968 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
22969 // operate independently on 128-bit lanes.
22970 unsigned NumElts = VT.getVectorNumElements();
22971 unsigned NumLanes = VT.getSizeInBits()/128;
22972 unsigned NumLaneElts = NumElts / NumLanes;
22973 assert((NumLaneElts % 2 == 0) &&
22974 "Vector type should have an even number of elements in each lane");
22975 unsigned HalfLaneElts = NumLaneElts/2;
22977 // View LHS in the form
22978 // LHS = VECTOR_SHUFFLE A, B, LMask
22979 // If LHS is not a shuffle then pretend it is the shuffle
22980 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
22981 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
22984 SmallVector<int, 16> LMask(NumElts);
22985 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
22986 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
22987 A = LHS.getOperand(0);
22988 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
22989 B = LHS.getOperand(1);
22990 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
22991 std::copy(Mask.begin(), Mask.end(), LMask.begin());
22993 if (LHS.getOpcode() != ISD::UNDEF)
22995 for (unsigned i = 0; i != NumElts; ++i)
22999 // Likewise, view RHS in the form
23000 // RHS = VECTOR_SHUFFLE C, D, RMask
23002 SmallVector<int, 16> RMask(NumElts);
23003 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23004 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
23005 C = RHS.getOperand(0);
23006 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
23007 D = RHS.getOperand(1);
23008 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
23009 std::copy(Mask.begin(), Mask.end(), RMask.begin());
23011 if (RHS.getOpcode() != ISD::UNDEF)
23013 for (unsigned i = 0; i != NumElts; ++i)
23017 // Check that the shuffles are both shuffling the same vectors.
23018 if (!(A == C && B == D) && !(A == D && B == C))
23021 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
23022 if (!A.getNode() && !B.getNode())
23025 // If A and B occur in reverse order in RHS, then "swap" them (which means
23026 // rewriting the mask).
23028 ShuffleVectorSDNode::commuteMask(RMask);
23030 // At this point LHS and RHS are equivalent to
23031 // LHS = VECTOR_SHUFFLE A, B, LMask
23032 // RHS = VECTOR_SHUFFLE A, B, RMask
23033 // Check that the masks correspond to performing a horizontal operation.
23034 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
23035 for (unsigned i = 0; i != NumLaneElts; ++i) {
23036 int LIdx = LMask[i+l], RIdx = RMask[i+l];
23038 // Ignore any UNDEF components.
23039 if (LIdx < 0 || RIdx < 0 ||
23040 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
23041 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
23044 // Check that successive elements are being operated on. If not, this is
23045 // not a horizontal operation.
23046 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
23047 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
23048 if (!(LIdx == Index && RIdx == Index + 1) &&
23049 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
23054 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
23055 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
23059 /// Do target-specific dag combines on floating point adds.
23060 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
23061 const X86Subtarget *Subtarget) {
23062 EVT VT = N->getValueType(0);
23063 SDValue LHS = N->getOperand(0);
23064 SDValue RHS = N->getOperand(1);
23066 // Try to synthesize horizontal adds from adds of shuffles.
23067 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23068 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23069 isHorizontalBinOp(LHS, RHS, true))
23070 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
23074 /// Do target-specific dag combines on floating point subs.
23075 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
23076 const X86Subtarget *Subtarget) {
23077 EVT VT = N->getValueType(0);
23078 SDValue LHS = N->getOperand(0);
23079 SDValue RHS = N->getOperand(1);
23081 // Try to synthesize horizontal subs from subs of shuffles.
23082 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23083 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23084 isHorizontalBinOp(LHS, RHS, false))
23085 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
23089 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
23090 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
23091 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
23093 // F[X]OR(0.0, x) -> x
23094 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23095 if (C->getValueAPF().isPosZero())
23096 return N->getOperand(1);
23098 // F[X]OR(x, 0.0) -> x
23099 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23100 if (C->getValueAPF().isPosZero())
23101 return N->getOperand(0);
23105 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
23106 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
23107 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
23109 // Only perform optimizations if UnsafeMath is used.
23110 if (!DAG.getTarget().Options.UnsafeFPMath)
23113 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
23114 // into FMINC and FMAXC, which are Commutative operations.
23115 unsigned NewOp = 0;
23116 switch (N->getOpcode()) {
23117 default: llvm_unreachable("unknown opcode");
23118 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
23119 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
23122 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
23123 N->getOperand(0), N->getOperand(1));
23126 /// Do target-specific dag combines on X86ISD::FAND nodes.
23127 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
23128 // FAND(0.0, x) -> 0.0
23129 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23130 if (C->getValueAPF().isPosZero())
23131 return N->getOperand(0);
23133 // FAND(x, 0.0) -> 0.0
23134 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23135 if (C->getValueAPF().isPosZero())
23136 return N->getOperand(1);
23141 /// Do target-specific dag combines on X86ISD::FANDN nodes
23142 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
23143 // FANDN(0.0, x) -> x
23144 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23145 if (C->getValueAPF().isPosZero())
23146 return N->getOperand(1);
23148 // FANDN(x, 0.0) -> 0.0
23149 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23150 if (C->getValueAPF().isPosZero())
23151 return N->getOperand(1);
23156 static SDValue PerformBTCombine(SDNode *N,
23158 TargetLowering::DAGCombinerInfo &DCI) {
23159 // BT ignores high bits in the bit index operand.
23160 SDValue Op1 = N->getOperand(1);
23161 if (Op1.hasOneUse()) {
23162 unsigned BitWidth = Op1.getValueSizeInBits();
23163 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
23164 APInt KnownZero, KnownOne;
23165 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
23166 !DCI.isBeforeLegalizeOps());
23167 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23168 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
23169 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
23170 DCI.CommitTargetLoweringOpt(TLO);
23175 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
23176 SDValue Op = N->getOperand(0);
23177 if (Op.getOpcode() == ISD::BITCAST)
23178 Op = Op.getOperand(0);
23179 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
23180 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
23181 VT.getVectorElementType().getSizeInBits() ==
23182 OpVT.getVectorElementType().getSizeInBits()) {
23183 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
23188 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
23189 const X86Subtarget *Subtarget) {
23190 EVT VT = N->getValueType(0);
23191 if (!VT.isVector())
23194 SDValue N0 = N->getOperand(0);
23195 SDValue N1 = N->getOperand(1);
23196 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
23199 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
23200 // both SSE and AVX2 since there is no sign-extended shift right
23201 // operation on a vector with 64-bit elements.
23202 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
23203 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
23204 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
23205 N0.getOpcode() == ISD::SIGN_EXTEND)) {
23206 SDValue N00 = N0.getOperand(0);
23208 // EXTLOAD has a better solution on AVX2,
23209 // it may be replaced with X86ISD::VSEXT node.
23210 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
23211 if (!ISD::isNormalLoad(N00.getNode()))
23214 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
23215 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
23217 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
23223 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
23224 TargetLowering::DAGCombinerInfo &DCI,
23225 const X86Subtarget *Subtarget) {
23226 SDValue N0 = N->getOperand(0);
23227 EVT VT = N->getValueType(0);
23229 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
23230 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
23231 // This exposes the sext to the sdivrem lowering, so that it directly extends
23232 // from AH (which we otherwise need to do contortions to access).
23233 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
23234 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
23236 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
23237 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
23238 N0.getOperand(0), N0.getOperand(1));
23239 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
23240 return R.getValue(1);
23243 if (!DCI.isBeforeLegalizeOps())
23246 if (!Subtarget->hasFp256())
23249 if (VT.isVector() && VT.getSizeInBits() == 256) {
23250 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23258 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
23259 const X86Subtarget* Subtarget) {
23261 EVT VT = N->getValueType(0);
23263 // Let legalize expand this if it isn't a legal type yet.
23264 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
23267 EVT ScalarVT = VT.getScalarType();
23268 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
23269 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
23272 SDValue A = N->getOperand(0);
23273 SDValue B = N->getOperand(1);
23274 SDValue C = N->getOperand(2);
23276 bool NegA = (A.getOpcode() == ISD::FNEG);
23277 bool NegB = (B.getOpcode() == ISD::FNEG);
23278 bool NegC = (C.getOpcode() == ISD::FNEG);
23280 // Negative multiplication when NegA xor NegB
23281 bool NegMul = (NegA != NegB);
23283 A = A.getOperand(0);
23285 B = B.getOperand(0);
23287 C = C.getOperand(0);
23291 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
23293 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
23295 return DAG.getNode(Opcode, dl, VT, A, B, C);
23298 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
23299 TargetLowering::DAGCombinerInfo &DCI,
23300 const X86Subtarget *Subtarget) {
23301 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
23302 // (and (i32 x86isd::setcc_carry), 1)
23303 // This eliminates the zext. This transformation is necessary because
23304 // ISD::SETCC is always legalized to i8.
23306 SDValue N0 = N->getOperand(0);
23307 EVT VT = N->getValueType(0);
23309 if (N0.getOpcode() == ISD::AND &&
23311 N0.getOperand(0).hasOneUse()) {
23312 SDValue N00 = N0.getOperand(0);
23313 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23314 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23315 if (!C || C->getZExtValue() != 1)
23317 return DAG.getNode(ISD::AND, dl, VT,
23318 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23319 N00.getOperand(0), N00.getOperand(1)),
23320 DAG.getConstant(1, VT));
23324 if (N0.getOpcode() == ISD::TRUNCATE &&
23326 N0.getOperand(0).hasOneUse()) {
23327 SDValue N00 = N0.getOperand(0);
23328 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
23329 return DAG.getNode(ISD::AND, dl, VT,
23330 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
23331 N00.getOperand(0), N00.getOperand(1)),
23332 DAG.getConstant(1, VT));
23335 if (VT.is256BitVector()) {
23336 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
23341 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
23342 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
23343 // This exposes the zext to the udivrem lowering, so that it directly extends
23344 // from AH (which we otherwise need to do contortions to access).
23345 if (N0.getOpcode() == ISD::UDIVREM &&
23346 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
23347 (VT == MVT::i32 || VT == MVT::i64)) {
23348 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
23349 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
23350 N0.getOperand(0), N0.getOperand(1));
23351 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
23352 return R.getValue(1);
23358 // Optimize x == -y --> x+y == 0
23359 // x != -y --> x+y != 0
23360 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
23361 const X86Subtarget* Subtarget) {
23362 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
23363 SDValue LHS = N->getOperand(0);
23364 SDValue RHS = N->getOperand(1);
23365 EVT VT = N->getValueType(0);
23368 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
23369 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
23370 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
23371 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N), LHS.getValueType(), RHS,
23372 LHS.getOperand(1));
23373 return DAG.getSetCC(SDLoc(N), N->getValueType(0), addV,
23374 DAG.getConstant(0, addV.getValueType()), CC);
23376 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
23377 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
23378 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
23379 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N), RHS.getValueType(), LHS,
23380 RHS.getOperand(1));
23381 return DAG.getSetCC(SDLoc(N), N->getValueType(0), addV,
23382 DAG.getConstant(0, addV.getValueType()), CC);
23385 if (VT.getScalarType() == MVT::i1 &&
23386 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
23388 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
23389 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23390 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
23392 if (!IsSEXT0 || !IsVZero1) {
23393 // Swap the operands and update the condition code.
23394 std::swap(LHS, RHS);
23395 CC = ISD::getSetCCSwappedOperands(CC);
23397 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
23398 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
23399 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
23402 if (IsSEXT0 && IsVZero1) {
23403 assert(VT == LHS.getOperand(0).getValueType() &&
23404 "Uexpected operand type");
23405 if (CC == ISD::SETGT)
23406 return DAG.getConstant(0, VT);
23407 if (CC == ISD::SETLE)
23408 return DAG.getConstant(1, VT);
23409 if (CC == ISD::SETEQ || CC == ISD::SETGE)
23410 return DAG.getNOT(DL, LHS.getOperand(0), VT);
23412 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
23413 "Unexpected condition code!");
23414 return LHS.getOperand(0);
23421 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
23422 SelectionDAG &DAG) {
23424 MVT VT = Load->getSimpleValueType(0);
23425 MVT EVT = VT.getVectorElementType();
23426 SDValue Addr = Load->getOperand(1);
23427 SDValue NewAddr = DAG.getNode(
23428 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
23429 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
23432 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
23433 DAG.getMachineFunction().getMachineMemOperand(
23434 Load->getMemOperand(), 0, EVT.getStoreSize()));
23438 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
23439 const X86Subtarget *Subtarget) {
23441 MVT VT = N->getOperand(1)->getSimpleValueType(0);
23442 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
23443 "X86insertps is only defined for v4x32");
23445 SDValue Ld = N->getOperand(1);
23446 if (MayFoldLoad(Ld)) {
23447 // Extract the countS bits from the immediate so we can get the proper
23448 // address when narrowing the vector load to a specific element.
23449 // When the second source op is a memory address, insertps doesn't use
23450 // countS and just gets an f32 from that address.
23451 unsigned DestIndex =
23452 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
23454 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
23456 // Create this as a scalar to vector to match the instruction pattern.
23457 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
23458 // countS bits are ignored when loading from memory on insertps, which
23459 // means we don't need to explicitly set them to 0.
23460 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
23461 LoadScalarToVector, N->getOperand(2));
23466 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
23467 SDValue V0 = N->getOperand(0);
23468 SDValue V1 = N->getOperand(1);
23470 EVT VT = N->getValueType(0);
23472 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
23473 // operands and changing the mask to 1. This saves us a bunch of
23474 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
23475 // x86InstrInfo knows how to commute this back after instruction selection
23476 // if it would help register allocation.
23478 // TODO: If optimizing for size or a processor that doesn't suffer from
23479 // partial register update stalls, this should be transformed into a MOVSD
23480 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
23482 if (VT == MVT::v2f64)
23483 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
23484 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
23485 SDValue NewMask = DAG.getConstant(1, MVT::i8);
23486 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
23492 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
23493 // as "sbb reg,reg", since it can be extended without zext and produces
23494 // an all-ones bit which is more useful than 0/1 in some cases.
23495 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
23498 return DAG.getNode(ISD::AND, DL, VT,
23499 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23500 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
23501 DAG.getConstant(1, VT));
23502 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
23503 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
23504 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
23505 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
23508 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
23509 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
23510 TargetLowering::DAGCombinerInfo &DCI,
23511 const X86Subtarget *Subtarget) {
23513 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
23514 SDValue EFLAGS = N->getOperand(1);
23516 if (CC == X86::COND_A) {
23517 // Try to convert COND_A into COND_B in an attempt to facilitate
23518 // materializing "setb reg".
23520 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
23521 // cannot take an immediate as its first operand.
23523 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
23524 EFLAGS.getValueType().isInteger() &&
23525 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
23526 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
23527 EFLAGS.getNode()->getVTList(),
23528 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
23529 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
23530 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
23534 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
23535 // a zext and produces an all-ones bit which is more useful than 0/1 in some
23537 if (CC == X86::COND_B)
23538 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
23542 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23543 if (Flags.getNode()) {
23544 SDValue Cond = DAG.getConstant(CC, MVT::i8);
23545 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
23551 // Optimize branch condition evaluation.
23553 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
23554 TargetLowering::DAGCombinerInfo &DCI,
23555 const X86Subtarget *Subtarget) {
23557 SDValue Chain = N->getOperand(0);
23558 SDValue Dest = N->getOperand(1);
23559 SDValue EFLAGS = N->getOperand(3);
23560 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
23564 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
23565 if (Flags.getNode()) {
23566 SDValue Cond = DAG.getConstant(CC, MVT::i8);
23567 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
23574 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
23575 SelectionDAG &DAG) {
23576 // Take advantage of vector comparisons producing 0 or -1 in each lane to
23577 // optimize away operation when it's from a constant.
23579 // The general transformation is:
23580 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
23581 // AND(VECTOR_CMP(x,y), constant2)
23582 // constant2 = UNARYOP(constant)
23584 // Early exit if this isn't a vector operation, the operand of the
23585 // unary operation isn't a bitwise AND, or if the sizes of the operations
23586 // aren't the same.
23587 EVT VT = N->getValueType(0);
23588 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
23589 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
23590 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
23593 // Now check that the other operand of the AND is a constant. We could
23594 // make the transformation for non-constant splats as well, but it's unclear
23595 // that would be a benefit as it would not eliminate any operations, just
23596 // perform one more step in scalar code before moving to the vector unit.
23597 if (BuildVectorSDNode *BV =
23598 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
23599 // Bail out if the vector isn't a constant.
23600 if (!BV->isConstant())
23603 // Everything checks out. Build up the new and improved node.
23605 EVT IntVT = BV->getValueType(0);
23606 // Create a new constant of the appropriate type for the transformed
23608 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
23609 // The AND node needs bitcasts to/from an integer vector type around it.
23610 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
23611 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
23612 N->getOperand(0)->getOperand(0), MaskConst);
23613 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
23620 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
23621 const X86Subtarget *Subtarget) {
23622 // First try to optimize away the conversion entirely when it's
23623 // conditionally from a constant. Vectors only.
23624 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
23625 if (Res != SDValue())
23628 // Now move on to more general possibilities.
23629 SDValue Op0 = N->getOperand(0);
23630 EVT InVT = Op0->getValueType(0);
23632 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
23633 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
23635 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
23636 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
23637 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
23640 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
23641 // a 32-bit target where SSE doesn't support i64->FP operations.
23642 if (Op0.getOpcode() == ISD::LOAD) {
23643 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
23644 EVT VT = Ld->getValueType(0);
23645 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
23646 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
23647 !Subtarget->is64Bit() && VT == MVT::i64) {
23648 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
23649 SDValue(N, 0), Ld->getValueType(0), Ld->getChain(), Op0, DAG);
23650 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
23657 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
23658 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
23659 X86TargetLowering::DAGCombinerInfo &DCI) {
23660 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
23661 // the result is either zero or one (depending on the input carry bit).
23662 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
23663 if (X86::isZeroNode(N->getOperand(0)) &&
23664 X86::isZeroNode(N->getOperand(1)) &&
23665 // We don't have a good way to replace an EFLAGS use, so only do this when
23667 SDValue(N, 1).use_empty()) {
23669 EVT VT = N->getValueType(0);
23670 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
23671 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
23672 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
23673 DAG.getConstant(X86::COND_B,MVT::i8),
23675 DAG.getConstant(1, VT));
23676 return DCI.CombineTo(N, Res1, CarryOut);
23682 // fold (add Y, (sete X, 0)) -> adc 0, Y
23683 // (add Y, (setne X, 0)) -> sbb -1, Y
23684 // (sub (sete X, 0), Y) -> sbb 0, Y
23685 // (sub (setne X, 0), Y) -> adc -1, Y
23686 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
23689 // Look through ZExts.
23690 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
23691 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
23694 SDValue SetCC = Ext.getOperand(0);
23695 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
23698 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
23699 if (CC != X86::COND_E && CC != X86::COND_NE)
23702 SDValue Cmp = SetCC.getOperand(1);
23703 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
23704 !X86::isZeroNode(Cmp.getOperand(1)) ||
23705 !Cmp.getOperand(0).getValueType().isInteger())
23708 SDValue CmpOp0 = Cmp.getOperand(0);
23709 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
23710 DAG.getConstant(1, CmpOp0.getValueType()));
23712 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
23713 if (CC == X86::COND_NE)
23714 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
23715 DL, OtherVal.getValueType(), OtherVal,
23716 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
23717 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
23718 DL, OtherVal.getValueType(), OtherVal,
23719 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
23722 /// PerformADDCombine - Do target-specific dag combines on integer adds.
23723 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
23724 const X86Subtarget *Subtarget) {
23725 EVT VT = N->getValueType(0);
23726 SDValue Op0 = N->getOperand(0);
23727 SDValue Op1 = N->getOperand(1);
23729 // Try to synthesize horizontal adds from adds of shuffles.
23730 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
23731 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
23732 isHorizontalBinOp(Op0, Op1, true))
23733 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
23735 return OptimizeConditionalInDecrement(N, DAG);
23738 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
23739 const X86Subtarget *Subtarget) {
23740 SDValue Op0 = N->getOperand(0);
23741 SDValue Op1 = N->getOperand(1);
23743 // X86 can't encode an immediate LHS of a sub. See if we can push the
23744 // negation into a preceding instruction.
23745 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
23746 // If the RHS of the sub is a XOR with one use and a constant, invert the
23747 // immediate. Then add one to the LHS of the sub so we can turn
23748 // X-Y -> X+~Y+1, saving one register.
23749 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
23750 isa<ConstantSDNode>(Op1.getOperand(1))) {
23751 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
23752 EVT VT = Op0.getValueType();
23753 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
23755 DAG.getConstant(~XorC, VT));
23756 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
23757 DAG.getConstant(C->getAPIntValue()+1, VT));
23761 // Try to synthesize horizontal adds from adds of shuffles.
23762 EVT VT = N->getValueType(0);
23763 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
23764 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
23765 isHorizontalBinOp(Op0, Op1, true))
23766 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
23768 return OptimizeConditionalInDecrement(N, DAG);
23771 /// performVZEXTCombine - Performs build vector combines
23772 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
23773 TargetLowering::DAGCombinerInfo &DCI,
23774 const X86Subtarget *Subtarget) {
23776 MVT VT = N->getSimpleValueType(0);
23777 SDValue Op = N->getOperand(0);
23778 MVT OpVT = Op.getSimpleValueType();
23779 MVT OpEltVT = OpVT.getVectorElementType();
23780 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
23782 // (vzext (bitcast (vzext (x)) -> (vzext x)
23784 while (V.getOpcode() == ISD::BITCAST)
23785 V = V.getOperand(0);
23787 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
23788 MVT InnerVT = V.getSimpleValueType();
23789 MVT InnerEltVT = InnerVT.getVectorElementType();
23791 // If the element sizes match exactly, we can just do one larger vzext. This
23792 // is always an exact type match as vzext operates on integer types.
23793 if (OpEltVT == InnerEltVT) {
23794 assert(OpVT == InnerVT && "Types must match for vzext!");
23795 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
23798 // The only other way we can combine them is if only a single element of the
23799 // inner vzext is used in the input to the outer vzext.
23800 if (InnerEltVT.getSizeInBits() < InputBits)
23803 // In this case, the inner vzext is completely dead because we're going to
23804 // only look at bits inside of the low element. Just do the outer vzext on
23805 // a bitcast of the input to the inner.
23806 return DAG.getNode(X86ISD::VZEXT, DL, VT,
23807 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
23810 // Check if we can bypass extracting and re-inserting an element of an input
23811 // vector. Essentialy:
23812 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
23813 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
23814 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
23815 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
23816 SDValue ExtractedV = V.getOperand(0);
23817 SDValue OrigV = ExtractedV.getOperand(0);
23818 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
23819 if (ExtractIdx->getZExtValue() == 0) {
23820 MVT OrigVT = OrigV.getSimpleValueType();
23821 // Extract a subvector if necessary...
23822 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
23823 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
23824 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
23825 OrigVT.getVectorNumElements() / Ratio);
23826 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
23827 DAG.getIntPtrConstant(0));
23829 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
23830 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
23837 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
23838 DAGCombinerInfo &DCI) const {
23839 SelectionDAG &DAG = DCI.DAG;
23840 switch (N->getOpcode()) {
23842 case ISD::EXTRACT_VECTOR_ELT:
23843 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
23846 case X86ISD::SHRUNKBLEND:
23847 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
23848 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG);
23849 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
23850 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
23851 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
23852 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
23853 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
23856 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
23857 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
23858 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
23859 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
23860 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
23861 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
23862 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
23863 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
23864 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
23865 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
23866 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
23868 case X86ISD::FOR: return PerformFORCombine(N, DAG);
23870 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
23871 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
23872 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
23873 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
23874 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
23875 case ISD::ANY_EXTEND:
23876 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
23877 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
23878 case ISD::SIGN_EXTEND_INREG:
23879 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
23880 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
23881 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
23882 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
23883 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
23884 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
23885 case X86ISD::SHUFP: // Handle all target specific shuffles
23886 case X86ISD::PALIGNR:
23887 case X86ISD::UNPCKH:
23888 case X86ISD::UNPCKL:
23889 case X86ISD::MOVHLPS:
23890 case X86ISD::MOVLHPS:
23891 case X86ISD::PSHUFB:
23892 case X86ISD::PSHUFD:
23893 case X86ISD::PSHUFHW:
23894 case X86ISD::PSHUFLW:
23895 case X86ISD::MOVSS:
23896 case X86ISD::MOVSD:
23897 case X86ISD::VPERMILPI:
23898 case X86ISD::VPERM2X128:
23899 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
23900 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
23901 case ISD::INTRINSIC_WO_CHAIN:
23902 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
23903 case X86ISD::INSERTPS: {
23904 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
23905 return PerformINSERTPSCombine(N, DAG, Subtarget);
23908 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
23909 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
23915 /// isTypeDesirableForOp - Return true if the target has native support for
23916 /// the specified value type and it is 'desirable' to use the type for the
23917 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
23918 /// instruction encodings are longer and some i16 instructions are slow.
23919 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
23920 if (!isTypeLegal(VT))
23922 if (VT != MVT::i16)
23929 case ISD::SIGN_EXTEND:
23930 case ISD::ZERO_EXTEND:
23931 case ISD::ANY_EXTEND:
23944 /// IsDesirableToPromoteOp - This method query the target whether it is
23945 /// beneficial for dag combiner to promote the specified node. If true, it
23946 /// should return the desired promotion type by reference.
23947 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
23948 EVT VT = Op.getValueType();
23949 if (VT != MVT::i16)
23952 bool Promote = false;
23953 bool Commute = false;
23954 switch (Op.getOpcode()) {
23957 LoadSDNode *LD = cast<LoadSDNode>(Op);
23958 // If the non-extending load has a single use and it's not live out, then it
23959 // might be folded.
23960 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
23961 Op.hasOneUse()*/) {
23962 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
23963 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
23964 // The only case where we'd want to promote LOAD (rather then it being
23965 // promoted as an operand is when it's only use is liveout.
23966 if (UI->getOpcode() != ISD::CopyToReg)
23973 case ISD::SIGN_EXTEND:
23974 case ISD::ZERO_EXTEND:
23975 case ISD::ANY_EXTEND:
23980 SDValue N0 = Op.getOperand(0);
23981 // Look out for (store (shl (load), x)).
23982 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
23995 SDValue N0 = Op.getOperand(0);
23996 SDValue N1 = Op.getOperand(1);
23997 if (!Commute && MayFoldLoad(N1))
23999 // Avoid disabling potential load folding opportunities.
24000 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
24002 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
24012 //===----------------------------------------------------------------------===//
24013 // X86 Inline Assembly Support
24014 //===----------------------------------------------------------------------===//
24016 // Helper to match a string separated by whitespace.
24017 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
24018 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
24020 for (StringRef Piece : Pieces) {
24021 if (!S.startswith(Piece)) // Check if the piece matches.
24024 S = S.substr(Piece.size());
24025 StringRef::size_type Pos = S.find_first_not_of(" \t");
24026 if (Pos == 0) // We matched a prefix.
24035 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
24037 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
24038 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
24039 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
24040 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
24042 if (AsmPieces.size() == 3)
24044 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
24051 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
24052 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
24054 std::string AsmStr = IA->getAsmString();
24056 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
24057 if (!Ty || Ty->getBitWidth() % 16 != 0)
24060 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
24061 SmallVector<StringRef, 4> AsmPieces;
24062 SplitString(AsmStr, AsmPieces, ";\n");
24064 switch (AsmPieces.size()) {
24065 default: return false;
24067 // FIXME: this should verify that we are targeting a 486 or better. If not,
24068 // we will turn this bswap into something that will be lowered to logical
24069 // ops instead of emitting the bswap asm. For now, we don't support 486 or
24070 // lower so don't worry about this.
24072 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
24073 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
24074 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
24075 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
24076 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
24077 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
24078 // No need to check constraints, nothing other than the equivalent of
24079 // "=r,0" would be valid here.
24080 return IntrinsicLowering::LowerToByteSwap(CI);
24083 // rorw $$8, ${0:w} --> llvm.bswap.i16
24084 if (CI->getType()->isIntegerTy(16) &&
24085 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24086 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
24087 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
24089 const std::string &ConstraintsStr = IA->getConstraintString();
24090 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24091 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24092 if (clobbersFlagRegisters(AsmPieces))
24093 return IntrinsicLowering::LowerToByteSwap(CI);
24097 if (CI->getType()->isIntegerTy(32) &&
24098 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24099 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
24100 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
24101 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
24103 const std::string &ConstraintsStr = IA->getConstraintString();
24104 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24105 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24106 if (clobbersFlagRegisters(AsmPieces))
24107 return IntrinsicLowering::LowerToByteSwap(CI);
24110 if (CI->getType()->isIntegerTy(64)) {
24111 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
24112 if (Constraints.size() >= 2 &&
24113 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
24114 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
24115 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
24116 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
24117 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
24118 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
24119 return IntrinsicLowering::LowerToByteSwap(CI);
24127 /// getConstraintType - Given a constraint letter, return the type of
24128 /// constraint it is for this target.
24129 X86TargetLowering::ConstraintType
24130 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
24131 if (Constraint.size() == 1) {
24132 switch (Constraint[0]) {
24143 return C_RegisterClass;
24167 return TargetLowering::getConstraintType(Constraint);
24170 /// Examine constraint type and operand type and determine a weight value.
24171 /// This object must already have been set up with the operand type
24172 /// and the current alternative constraint selected.
24173 TargetLowering::ConstraintWeight
24174 X86TargetLowering::getSingleConstraintMatchWeight(
24175 AsmOperandInfo &info, const char *constraint) const {
24176 ConstraintWeight weight = CW_Invalid;
24177 Value *CallOperandVal = info.CallOperandVal;
24178 // If we don't have a value, we can't do a match,
24179 // but allow it at the lowest weight.
24180 if (!CallOperandVal)
24182 Type *type = CallOperandVal->getType();
24183 // Look at the constraint type.
24184 switch (*constraint) {
24186 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
24197 if (CallOperandVal->getType()->isIntegerTy())
24198 weight = CW_SpecificReg;
24203 if (type->isFloatingPointTy())
24204 weight = CW_SpecificReg;
24207 if (type->isX86_MMXTy() && Subtarget->hasMMX())
24208 weight = CW_SpecificReg;
24212 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
24213 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
24214 weight = CW_Register;
24217 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
24218 if (C->getZExtValue() <= 31)
24219 weight = CW_Constant;
24223 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24224 if (C->getZExtValue() <= 63)
24225 weight = CW_Constant;
24229 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24230 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
24231 weight = CW_Constant;
24235 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24236 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
24237 weight = CW_Constant;
24241 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24242 if (C->getZExtValue() <= 3)
24243 weight = CW_Constant;
24247 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24248 if (C->getZExtValue() <= 0xff)
24249 weight = CW_Constant;
24254 if (isa<ConstantFP>(CallOperandVal)) {
24255 weight = CW_Constant;
24259 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24260 if ((C->getSExtValue() >= -0x80000000LL) &&
24261 (C->getSExtValue() <= 0x7fffffffLL))
24262 weight = CW_Constant;
24266 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
24267 if (C->getZExtValue() <= 0xffffffff)
24268 weight = CW_Constant;
24275 /// LowerXConstraint - try to replace an X constraint, which matches anything,
24276 /// with another that has more specific requirements based on the type of the
24277 /// corresponding operand.
24278 const char *X86TargetLowering::
24279 LowerXConstraint(EVT ConstraintVT) const {
24280 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
24281 // 'f' like normal targets.
24282 if (ConstraintVT.isFloatingPoint()) {
24283 if (Subtarget->hasSSE2())
24285 if (Subtarget->hasSSE1())
24289 return TargetLowering::LowerXConstraint(ConstraintVT);
24292 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
24293 /// vector. If it is invalid, don't add anything to Ops.
24294 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
24295 std::string &Constraint,
24296 std::vector<SDValue>&Ops,
24297 SelectionDAG &DAG) const {
24300 // Only support length 1 constraints for now.
24301 if (Constraint.length() > 1) return;
24303 char ConstraintLetter = Constraint[0];
24304 switch (ConstraintLetter) {
24307 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24308 if (C->getZExtValue() <= 31) {
24309 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24315 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24316 if (C->getZExtValue() <= 63) {
24317 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24323 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24324 if (isInt<8>(C->getSExtValue())) {
24325 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24331 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24332 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
24333 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
24334 Result = DAG.getTargetConstant(C->getSExtValue(), Op.getValueType());
24340 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24341 if (C->getZExtValue() <= 3) {
24342 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24348 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24349 if (C->getZExtValue() <= 255) {
24350 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24356 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24357 if (C->getZExtValue() <= 127) {
24358 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24364 // 32-bit signed value
24365 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24366 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24367 C->getSExtValue())) {
24368 // Widen to 64 bits here to get it sign extended.
24369 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
24372 // FIXME gcc accepts some relocatable values here too, but only in certain
24373 // memory models; it's complicated.
24378 // 32-bit unsigned value
24379 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
24380 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
24381 C->getZExtValue())) {
24382 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
24386 // FIXME gcc accepts some relocatable values here too, but only in certain
24387 // memory models; it's complicated.
24391 // Literal immediates are always ok.
24392 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
24393 // Widen to 64 bits here to get it sign extended.
24394 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
24398 // In any sort of PIC mode addresses need to be computed at runtime by
24399 // adding in a register or some sort of table lookup. These can't
24400 // be used as immediates.
24401 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
24404 // If we are in non-pic codegen mode, we allow the address of a global (with
24405 // an optional displacement) to be used with 'i'.
24406 GlobalAddressSDNode *GA = nullptr;
24407 int64_t Offset = 0;
24409 // Match either (GA), (GA+C), (GA+C1+C2), etc.
24411 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
24412 Offset += GA->getOffset();
24414 } else if (Op.getOpcode() == ISD::ADD) {
24415 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24416 Offset += C->getZExtValue();
24417 Op = Op.getOperand(0);
24420 } else if (Op.getOpcode() == ISD::SUB) {
24421 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
24422 Offset += -C->getZExtValue();
24423 Op = Op.getOperand(0);
24428 // Otherwise, this isn't something we can handle, reject it.
24432 const GlobalValue *GV = GA->getGlobal();
24433 // If we require an extra load to get this address, as in PIC mode, we
24434 // can't accept it.
24435 if (isGlobalStubReference(
24436 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
24439 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
24440 GA->getValueType(0), Offset);
24445 if (Result.getNode()) {
24446 Ops.push_back(Result);
24449 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
24452 std::pair<unsigned, const TargetRegisterClass *>
24453 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
24454 const std::string &Constraint,
24456 // First, see if this is a constraint that directly corresponds to an LLVM
24458 if (Constraint.size() == 1) {
24459 // GCC Constraint Letters
24460 switch (Constraint[0]) {
24462 // TODO: Slight differences here in allocation order and leaving
24463 // RIP in the class. Do they matter any more here than they do
24464 // in the normal allocation?
24465 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
24466 if (Subtarget->is64Bit()) {
24467 if (VT == MVT::i32 || VT == MVT::f32)
24468 return std::make_pair(0U, &X86::GR32RegClass);
24469 if (VT == MVT::i16)
24470 return std::make_pair(0U, &X86::GR16RegClass);
24471 if (VT == MVT::i8 || VT == MVT::i1)
24472 return std::make_pair(0U, &X86::GR8RegClass);
24473 if (VT == MVT::i64 || VT == MVT::f64)
24474 return std::make_pair(0U, &X86::GR64RegClass);
24477 // 32-bit fallthrough
24478 case 'Q': // Q_REGS
24479 if (VT == MVT::i32 || VT == MVT::f32)
24480 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
24481 if (VT == MVT::i16)
24482 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
24483 if (VT == MVT::i8 || VT == MVT::i1)
24484 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
24485 if (VT == MVT::i64)
24486 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
24488 case 'r': // GENERAL_REGS
24489 case 'l': // INDEX_REGS
24490 if (VT == MVT::i8 || VT == MVT::i1)
24491 return std::make_pair(0U, &X86::GR8RegClass);
24492 if (VT == MVT::i16)
24493 return std::make_pair(0U, &X86::GR16RegClass);
24494 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
24495 return std::make_pair(0U, &X86::GR32RegClass);
24496 return std::make_pair(0U, &X86::GR64RegClass);
24497 case 'R': // LEGACY_REGS
24498 if (VT == MVT::i8 || VT == MVT::i1)
24499 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
24500 if (VT == MVT::i16)
24501 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
24502 if (VT == MVT::i32 || !Subtarget->is64Bit())
24503 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
24504 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
24505 case 'f': // FP Stack registers.
24506 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
24507 // value to the correct fpstack register class.
24508 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
24509 return std::make_pair(0U, &X86::RFP32RegClass);
24510 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
24511 return std::make_pair(0U, &X86::RFP64RegClass);
24512 return std::make_pair(0U, &X86::RFP80RegClass);
24513 case 'y': // MMX_REGS if MMX allowed.
24514 if (!Subtarget->hasMMX()) break;
24515 return std::make_pair(0U, &X86::VR64RegClass);
24516 case 'Y': // SSE_REGS if SSE2 allowed
24517 if (!Subtarget->hasSSE2()) break;
24519 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
24520 if (!Subtarget->hasSSE1()) break;
24522 switch (VT.SimpleTy) {
24524 // Scalar SSE types.
24527 return std::make_pair(0U, &X86::FR32RegClass);
24530 return std::make_pair(0U, &X86::FR64RegClass);
24538 return std::make_pair(0U, &X86::VR128RegClass);
24546 return std::make_pair(0U, &X86::VR256RegClass);
24551 return std::make_pair(0U, &X86::VR512RegClass);
24557 // Use the default implementation in TargetLowering to convert the register
24558 // constraint into a member of a register class.
24559 std::pair<unsigned, const TargetRegisterClass*> Res;
24560 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
24562 // Not found as a standard register?
24564 // Map st(0) -> st(7) -> ST0
24565 if (Constraint.size() == 7 && Constraint[0] == '{' &&
24566 tolower(Constraint[1]) == 's' &&
24567 tolower(Constraint[2]) == 't' &&
24568 Constraint[3] == '(' &&
24569 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
24570 Constraint[5] == ')' &&
24571 Constraint[6] == '}') {
24573 Res.first = X86::FP0+Constraint[4]-'0';
24574 Res.second = &X86::RFP80RegClass;
24578 // GCC allows "st(0)" to be called just plain "st".
24579 if (StringRef("{st}").equals_lower(Constraint)) {
24580 Res.first = X86::FP0;
24581 Res.second = &X86::RFP80RegClass;
24586 if (StringRef("{flags}").equals_lower(Constraint)) {
24587 Res.first = X86::EFLAGS;
24588 Res.second = &X86::CCRRegClass;
24592 // 'A' means EAX + EDX.
24593 if (Constraint == "A") {
24594 Res.first = X86::EAX;
24595 Res.second = &X86::GR32_ADRegClass;
24601 // Otherwise, check to see if this is a register class of the wrong value
24602 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
24603 // turn into {ax},{dx}.
24604 if (Res.second->hasType(VT))
24605 return Res; // Correct type already, nothing to do.
24607 // All of the single-register GCC register classes map their values onto
24608 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
24609 // really want an 8-bit or 32-bit register, map to the appropriate register
24610 // class and return the appropriate register.
24611 if (Res.second == &X86::GR16RegClass) {
24612 if (VT == MVT::i8 || VT == MVT::i1) {
24613 unsigned DestReg = 0;
24614 switch (Res.first) {
24616 case X86::AX: DestReg = X86::AL; break;
24617 case X86::DX: DestReg = X86::DL; break;
24618 case X86::CX: DestReg = X86::CL; break;
24619 case X86::BX: DestReg = X86::BL; break;
24622 Res.first = DestReg;
24623 Res.second = &X86::GR8RegClass;
24625 } else if (VT == MVT::i32 || VT == MVT::f32) {
24626 unsigned DestReg = 0;
24627 switch (Res.first) {
24629 case X86::AX: DestReg = X86::EAX; break;
24630 case X86::DX: DestReg = X86::EDX; break;
24631 case X86::CX: DestReg = X86::ECX; break;
24632 case X86::BX: DestReg = X86::EBX; break;
24633 case X86::SI: DestReg = X86::ESI; break;
24634 case X86::DI: DestReg = X86::EDI; break;
24635 case X86::BP: DestReg = X86::EBP; break;
24636 case X86::SP: DestReg = X86::ESP; break;
24639 Res.first = DestReg;
24640 Res.second = &X86::GR32RegClass;
24642 } else if (VT == MVT::i64 || VT == MVT::f64) {
24643 unsigned DestReg = 0;
24644 switch (Res.first) {
24646 case X86::AX: DestReg = X86::RAX; break;
24647 case X86::DX: DestReg = X86::RDX; break;
24648 case X86::CX: DestReg = X86::RCX; break;
24649 case X86::BX: DestReg = X86::RBX; break;
24650 case X86::SI: DestReg = X86::RSI; break;
24651 case X86::DI: DestReg = X86::RDI; break;
24652 case X86::BP: DestReg = X86::RBP; break;
24653 case X86::SP: DestReg = X86::RSP; break;
24656 Res.first = DestReg;
24657 Res.second = &X86::GR64RegClass;
24660 } else if (Res.second == &X86::FR32RegClass ||
24661 Res.second == &X86::FR64RegClass ||
24662 Res.second == &X86::VR128RegClass ||
24663 Res.second == &X86::VR256RegClass ||
24664 Res.second == &X86::FR32XRegClass ||
24665 Res.second == &X86::FR64XRegClass ||
24666 Res.second == &X86::VR128XRegClass ||
24667 Res.second == &X86::VR256XRegClass ||
24668 Res.second == &X86::VR512RegClass) {
24669 // Handle references to XMM physical registers that got mapped into the
24670 // wrong class. This can happen with constraints like {xmm0} where the
24671 // target independent register mapper will just pick the first match it can
24672 // find, ignoring the required type.
24674 if (VT == MVT::f32 || VT == MVT::i32)
24675 Res.second = &X86::FR32RegClass;
24676 else if (VT == MVT::f64 || VT == MVT::i64)
24677 Res.second = &X86::FR64RegClass;
24678 else if (X86::VR128RegClass.hasType(VT))
24679 Res.second = &X86::VR128RegClass;
24680 else if (X86::VR256RegClass.hasType(VT))
24681 Res.second = &X86::VR256RegClass;
24682 else if (X86::VR512RegClass.hasType(VT))
24683 Res.second = &X86::VR512RegClass;
24689 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
24691 // Scaling factors are not free at all.
24692 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
24693 // will take 2 allocations in the out of order engine instead of 1
24694 // for plain addressing mode, i.e. inst (reg1).
24696 // vaddps (%rsi,%drx), %ymm0, %ymm1
24697 // Requires two allocations (one for the load, one for the computation)
24699 // vaddps (%rsi), %ymm0, %ymm1
24700 // Requires just 1 allocation, i.e., freeing allocations for other operations
24701 // and having less micro operations to execute.
24703 // For some X86 architectures, this is even worse because for instance for
24704 // stores, the complex addressing mode forces the instruction to use the
24705 // "load" ports instead of the dedicated "store" port.
24706 // E.g., on Haswell:
24707 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
24708 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
24709 if (isLegalAddressingMode(AM, Ty))
24710 // Scale represents reg2 * scale, thus account for 1
24711 // as soon as we use a second register.
24712 return AM.Scale != 0;
24716 bool X86TargetLowering::isTargetFTOL() const {
24717 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();