1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(true),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 // Forward declarations.
75 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
78 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
79 SelectionDAG &DAG, SDLoc dl,
80 unsigned vectorWidth) {
81 assert((vectorWidth == 128 || vectorWidth == 256) &&
82 "Unsupported vector width");
83 EVT VT = Vec.getValueType();
84 EVT ElVT = VT.getVectorElementType();
85 unsigned Factor = VT.getSizeInBits()/vectorWidth;
86 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
87 VT.getVectorNumElements()/Factor);
89 // Extract from UNDEF is UNDEF.
90 if (Vec.getOpcode() == ISD::UNDEF)
91 return DAG.getUNDEF(ResultVT);
93 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
94 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
96 // This is the index of the first element of the vectorWidth-bit chunk
98 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
101 // If the input is a buildvector just emit a smaller one.
102 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
103 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
104 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
107 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
114 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
115 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
116 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
117 /// instructions or a simple subregister reference. Idx is an index in the
118 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
119 /// lowering EXTRACT_VECTOR_ELT operations easier.
120 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
121 SelectionDAG &DAG, SDLoc dl) {
122 assert((Vec.getValueType().is256BitVector() ||
123 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
124 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
127 /// Generate a DAG to grab 256-bits from a 512-bit vector.
128 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
129 SelectionDAG &DAG, SDLoc dl) {
130 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
131 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
134 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
135 unsigned IdxVal, SelectionDAG &DAG,
136 SDLoc dl, unsigned vectorWidth) {
137 assert((vectorWidth == 128 || vectorWidth == 256) &&
138 "Unsupported vector width");
139 // Inserting UNDEF is Result
140 if (Vec.getOpcode() == ISD::UNDEF)
142 EVT VT = Vec.getValueType();
143 EVT ElVT = VT.getVectorElementType();
144 EVT ResultVT = Result.getValueType();
146 // Insert the relevant vectorWidth bits.
147 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
149 // This is the index of the first element of the vectorWidth-bit chunk
151 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
154 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
155 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
158 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
159 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
160 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
161 /// simple superregister reference. Idx is an index in the 128 bits
162 /// we want. It need not be aligned to a 128-bit bounday. That makes
163 /// lowering INSERT_VECTOR_ELT operations easier.
164 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
165 unsigned IdxVal, SelectionDAG &DAG,
167 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
168 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
171 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
172 unsigned IdxVal, SelectionDAG &DAG,
174 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
175 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
178 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
179 /// instructions. This is used because creating CONCAT_VECTOR nodes of
180 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
181 /// large BUILD_VECTORS.
182 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
183 unsigned NumElems, SelectionDAG &DAG,
185 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
186 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
189 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
190 unsigned NumElems, SelectionDAG &DAG,
192 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
193 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
196 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
197 if (TT.isOSBinFormatMachO()) {
198 if (TT.getArch() == Triple::x86_64)
199 return new X86_64MachoTargetObjectFile();
200 return new TargetLoweringObjectFileMachO();
204 return new X86LinuxTargetObjectFile();
205 if (TT.isOSBinFormatELF())
206 return new TargetLoweringObjectFileELF();
207 if (TT.isKnownWindowsMSVCEnvironment())
208 return new X86WindowsTargetObjectFile();
209 if (TT.isOSBinFormatCOFF())
210 return new TargetLoweringObjectFileCOFF();
211 llvm_unreachable("unknown subtarget type");
214 // FIXME: This should stop caching the target machine as soon as
215 // we can remove resetOperationActions et al.
216 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
217 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
218 Subtarget = &TM.getSubtarget<X86Subtarget>();
219 X86ScalarSSEf64 = Subtarget->hasSSE2();
220 X86ScalarSSEf32 = Subtarget->hasSSE1();
221 TD = getDataLayout();
223 resetOperationActions();
226 void X86TargetLowering::resetOperationActions() {
227 const TargetMachine &TM = getTargetMachine();
228 static bool FirstTimeThrough = true;
230 // If none of the target options have changed, then we don't need to reset the
231 // operation actions.
232 if (!FirstTimeThrough && TO == TM.Options) return;
234 if (!FirstTimeThrough) {
235 // Reinitialize the actions.
237 FirstTimeThrough = false;
242 // Set up the TargetLowering object.
243 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
245 // X86 is weird, it always uses i8 for shift amounts and setcc results.
246 setBooleanContents(ZeroOrOneBooleanContent);
247 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
248 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
250 // For 64-bit since we have so many registers use the ILP scheduler, for
251 // 32-bit code use the register pressure specific scheduling.
252 // For Atom, always use ILP scheduling.
253 if (Subtarget->isAtom())
254 setSchedulingPreference(Sched::ILP);
255 else if (Subtarget->is64Bit())
256 setSchedulingPreference(Sched::ILP);
258 setSchedulingPreference(Sched::RegPressure);
259 const X86RegisterInfo *RegInfo =
260 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
261 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
263 // Bypass expensive divides on Atom when compiling with O2
264 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
265 addBypassSlowDiv(32, 8);
266 if (Subtarget->is64Bit())
267 addBypassSlowDiv(64, 16);
270 if (Subtarget->isTargetKnownWindowsMSVC()) {
271 // Setup Windows compiler runtime calls.
272 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
273 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
274 setLibcallName(RTLIB::SREM_I64, "_allrem");
275 setLibcallName(RTLIB::UREM_I64, "_aullrem");
276 setLibcallName(RTLIB::MUL_I64, "_allmul");
277 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
280 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
281 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
283 // The _ftol2 runtime function has an unusual calling conv, which
284 // is modeled by a special pseudo-instruction.
285 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
287 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
288 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
291 if (Subtarget->isTargetDarwin()) {
292 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
293 setUseUnderscoreSetJmp(false);
294 setUseUnderscoreLongJmp(false);
295 } else if (Subtarget->isTargetWindowsGNU()) {
296 // MS runtime is weird: it exports _setjmp, but longjmp!
297 setUseUnderscoreSetJmp(true);
298 setUseUnderscoreLongJmp(false);
300 setUseUnderscoreSetJmp(true);
301 setUseUnderscoreLongJmp(true);
304 // Set up the register classes.
305 addRegisterClass(MVT::i8, &X86::GR8RegClass);
306 addRegisterClass(MVT::i16, &X86::GR16RegClass);
307 addRegisterClass(MVT::i32, &X86::GR32RegClass);
308 if (Subtarget->is64Bit())
309 addRegisterClass(MVT::i64, &X86::GR64RegClass);
311 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
313 // We don't accept any truncstore of integer registers.
314 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
315 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
318 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
319 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
321 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
323 // SETOEQ and SETUNE require checking two conditions.
324 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
325 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
326 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
327 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
328 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
329 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
331 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
333 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
334 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
337 if (Subtarget->is64Bit()) {
338 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 } else if (!TM.Options.UseSoftFloat) {
341 // We have an algorithm for SSE2->double, and we turn this into a
342 // 64-bit FILD followed by conditional FADD for other targets.
343 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
344 // We have an algorithm for SSE2, and we turn this into a 64-bit
345 // FILD for other targets.
346 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
349 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
351 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
352 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
354 if (!TM.Options.UseSoftFloat) {
355 // SSE has no i16 to fp conversion, only i32
356 if (X86ScalarSSEf32) {
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
358 // f32 and f64 cases are Legal, f80 case is not
359 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
365 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
366 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
369 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
370 // are Legal, f80 is custom lowered.
371 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
372 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
374 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
376 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
377 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
379 if (X86ScalarSSEf32) {
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
381 // f32 and f64 cases are Legal, f80 case is not
382 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
384 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
385 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
388 // Handle FP_TO_UINT by promoting the destination to a larger signed
390 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
391 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
394 if (Subtarget->is64Bit()) {
395 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
396 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
397 } else if (!TM.Options.UseSoftFloat) {
398 // Since AVX is a superset of SSE3, only check for SSE here.
399 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
400 // Expand FP_TO_UINT into a select.
401 // FIXME: We would like to use a Custom expander here eventually to do
402 // the optimal thing for SSE vs. the default expansion in the legalizer.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
405 // With SSE3 we can use fisttpll to convert to a signed i64; without
406 // SSE, we're stuck with a fistpll.
407 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
410 if (isTargetFTOL()) {
411 // Use the _ftol2 runtime function, which has a pseudo-instruction
412 // to handle its weird calling convention.
413 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
416 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
417 if (!X86ScalarSSEf64) {
418 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
419 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
420 if (Subtarget->is64Bit()) {
421 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
422 // Without SSE, i64->f64 goes through memory.
423 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
427 // Scalar integer divide and remainder are lowered to use operations that
428 // produce two results, to match the available instructions. This exposes
429 // the two-result form to trivial CSE, which is able to combine x/y and x%y
430 // into a single instruction.
432 // Scalar integer multiply-high is also lowered to use two-result
433 // operations, to match the available instructions. However, plain multiply
434 // (low) operations are left as Legal, as there are single-result
435 // instructions for this in x86. Using the two-result multiply instructions
436 // when both high and low results are needed must be arranged by dagcombine.
437 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
439 setOperationAction(ISD::MULHS, VT, Expand);
440 setOperationAction(ISD::MULHU, VT, Expand);
441 setOperationAction(ISD::SDIV, VT, Expand);
442 setOperationAction(ISD::UDIV, VT, Expand);
443 setOperationAction(ISD::SREM, VT, Expand);
444 setOperationAction(ISD::UREM, VT, Expand);
446 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
447 setOperationAction(ISD::ADDC, VT, Custom);
448 setOperationAction(ISD::ADDE, VT, Custom);
449 setOperationAction(ISD::SUBC, VT, Custom);
450 setOperationAction(ISD::SUBE, VT, Custom);
453 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
454 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
455 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
456 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
457 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
458 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
459 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
460 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
461 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
465 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
466 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
467 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
468 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
469 if (Subtarget->is64Bit())
470 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
471 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
472 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
473 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
474 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
475 setOperationAction(ISD::FREM , MVT::f32 , Expand);
476 setOperationAction(ISD::FREM , MVT::f64 , Expand);
477 setOperationAction(ISD::FREM , MVT::f80 , Expand);
478 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
480 // Promote the i8 variants and force them on up to i32 which has a shorter
482 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
483 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
485 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
486 if (Subtarget->hasBMI()) {
487 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
488 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
489 if (Subtarget->is64Bit())
490 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
492 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
493 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
494 if (Subtarget->is64Bit())
495 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
498 if (Subtarget->hasLZCNT()) {
499 // When promoting the i8 variants, force them to i32 for a shorter
501 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
502 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
503 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
504 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
505 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
506 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
507 if (Subtarget->is64Bit())
508 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
510 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
511 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
512 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
513 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
516 if (Subtarget->is64Bit()) {
517 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
518 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
522 // Special handling for half-precision floating point conversions.
523 // If we don't have F16C support, then lower half float conversions
524 // into library calls.
525 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
526 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
527 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
530 // There's never any support for operations beyond MVT::f32.
531 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
532 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
533 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
534 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
536 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
537 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
538 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
539 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
541 if (Subtarget->hasPOPCNT()) {
542 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
544 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
545 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
546 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
547 if (Subtarget->is64Bit())
548 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
551 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
553 if (!Subtarget->hasMOVBE())
554 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
556 // These should be promoted to a larger select which is supported.
557 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
558 // X86 wants to expand cmov itself.
559 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
560 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
561 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
562 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
563 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
564 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
565 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
566 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
567 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
568 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
569 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
570 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
571 if (Subtarget->is64Bit()) {
572 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
573 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
575 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
576 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
577 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
578 // support continuation, user-level threading, and etc.. As a result, no
579 // other SjLj exception interfaces are implemented and please don't build
580 // your own exception handling based on them.
581 // LLVM/Clang supports zero-cost DWARF exception handling.
582 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
583 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
586 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
587 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
588 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
589 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
590 if (Subtarget->is64Bit())
591 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
592 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
593 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
594 if (Subtarget->is64Bit()) {
595 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
596 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
597 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
598 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
599 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
601 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
602 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
603 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
604 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
605 if (Subtarget->is64Bit()) {
606 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
607 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
608 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
611 if (Subtarget->hasSSE1())
612 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
614 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
616 // Expand certain atomics
617 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
619 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
620 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
621 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
624 if (Subtarget->hasCmpxchg16b()) {
625 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
628 // FIXME - use subtarget debug flags
629 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
630 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
631 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
634 if (Subtarget->is64Bit()) {
635 setExceptionPointerRegister(X86::RAX);
636 setExceptionSelectorRegister(X86::RDX);
638 setExceptionPointerRegister(X86::EAX);
639 setExceptionSelectorRegister(X86::EDX);
641 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
642 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
644 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
645 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
647 setOperationAction(ISD::TRAP, MVT::Other, Legal);
648 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
650 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
651 setOperationAction(ISD::VASTART , MVT::Other, Custom);
652 setOperationAction(ISD::VAEND , MVT::Other, Expand);
653 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
654 // TargetInfo::X86_64ABIBuiltinVaList
655 setOperationAction(ISD::VAARG , MVT::Other, Custom);
656 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
658 // TargetInfo::CharPtrBuiltinVaList
659 setOperationAction(ISD::VAARG , MVT::Other, Expand);
660 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
663 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
664 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
666 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
668 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
669 // f32 and f64 use SSE.
670 // Set up the FP register classes.
671 addRegisterClass(MVT::f32, &X86::FR32RegClass);
672 addRegisterClass(MVT::f64, &X86::FR64RegClass);
674 // Use ANDPD to simulate FABS.
675 setOperationAction(ISD::FABS , MVT::f64, Custom);
676 setOperationAction(ISD::FABS , MVT::f32, Custom);
678 // Use XORP to simulate FNEG.
679 setOperationAction(ISD::FNEG , MVT::f64, Custom);
680 setOperationAction(ISD::FNEG , MVT::f32, Custom);
682 // Use ANDPD and ORPD to simulate FCOPYSIGN.
683 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
684 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
686 // Lower this to FGETSIGNx86 plus an AND.
687 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
688 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
690 // We don't support sin/cos/fmod
691 setOperationAction(ISD::FSIN , MVT::f64, Expand);
692 setOperationAction(ISD::FCOS , MVT::f64, Expand);
693 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
694 setOperationAction(ISD::FSIN , MVT::f32, Expand);
695 setOperationAction(ISD::FCOS , MVT::f32, Expand);
696 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
698 // Expand FP immediates into loads from the stack, except for the special
700 addLegalFPImmediate(APFloat(+0.0)); // xorpd
701 addLegalFPImmediate(APFloat(+0.0f)); // xorps
702 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
703 // Use SSE for f32, x87 for f64.
704 // Set up the FP register classes.
705 addRegisterClass(MVT::f32, &X86::FR32RegClass);
706 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
708 // Use ANDPS to simulate FABS.
709 setOperationAction(ISD::FABS , MVT::f32, Custom);
711 // Use XORP to simulate FNEG.
712 setOperationAction(ISD::FNEG , MVT::f32, Custom);
714 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
716 // Use ANDPS and ORPS to simulate FCOPYSIGN.
717 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
718 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
720 // We don't support sin/cos/fmod
721 setOperationAction(ISD::FSIN , MVT::f32, Expand);
722 setOperationAction(ISD::FCOS , MVT::f32, Expand);
723 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
725 // Special cases we handle for FP constants.
726 addLegalFPImmediate(APFloat(+0.0f)); // xorps
727 addLegalFPImmediate(APFloat(+0.0)); // FLD0
728 addLegalFPImmediate(APFloat(+1.0)); // FLD1
729 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
730 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
732 if (!TM.Options.UnsafeFPMath) {
733 setOperationAction(ISD::FSIN , MVT::f64, Expand);
734 setOperationAction(ISD::FCOS , MVT::f64, Expand);
735 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
737 } else if (!TM.Options.UseSoftFloat) {
738 // f32 and f64 in x87.
739 // Set up the FP register classes.
740 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
741 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
743 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
744 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
745 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
746 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
748 if (!TM.Options.UnsafeFPMath) {
749 setOperationAction(ISD::FSIN , MVT::f64, Expand);
750 setOperationAction(ISD::FSIN , MVT::f32, Expand);
751 setOperationAction(ISD::FCOS , MVT::f64, Expand);
752 setOperationAction(ISD::FCOS , MVT::f32, Expand);
753 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
754 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
756 addLegalFPImmediate(APFloat(+0.0)); // FLD0
757 addLegalFPImmediate(APFloat(+1.0)); // FLD1
758 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
759 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
760 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
761 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
762 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
763 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
766 // We don't support FMA.
767 setOperationAction(ISD::FMA, MVT::f64, Expand);
768 setOperationAction(ISD::FMA, MVT::f32, Expand);
770 // Long double always uses X87.
771 if (!TM.Options.UseSoftFloat) {
772 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
773 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
774 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
776 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
777 addLegalFPImmediate(TmpFlt); // FLD0
779 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
782 APFloat TmpFlt2(+1.0);
783 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
785 addLegalFPImmediate(TmpFlt2); // FLD1
786 TmpFlt2.changeSign();
787 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
790 if (!TM.Options.UnsafeFPMath) {
791 setOperationAction(ISD::FSIN , MVT::f80, Expand);
792 setOperationAction(ISD::FCOS , MVT::f80, Expand);
793 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
796 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
797 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
798 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
799 setOperationAction(ISD::FRINT, MVT::f80, Expand);
800 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
801 setOperationAction(ISD::FMA, MVT::f80, Expand);
804 // Always use a library call for pow.
805 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
806 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
807 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
809 setOperationAction(ISD::FLOG, MVT::f80, Expand);
810 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
811 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
812 setOperationAction(ISD::FEXP, MVT::f80, Expand);
813 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
815 // First set operation action for all vector types to either promote
816 // (for widening) or expand (for scalarization). Then we will selectively
817 // turn on ones that can be effectively codegen'd.
818 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
819 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
820 MVT VT = (MVT::SimpleValueType)i;
821 setOperationAction(ISD::ADD , VT, Expand);
822 setOperationAction(ISD::SUB , VT, Expand);
823 setOperationAction(ISD::FADD, VT, Expand);
824 setOperationAction(ISD::FNEG, VT, Expand);
825 setOperationAction(ISD::FSUB, VT, Expand);
826 setOperationAction(ISD::MUL , VT, Expand);
827 setOperationAction(ISD::FMUL, VT, Expand);
828 setOperationAction(ISD::SDIV, VT, Expand);
829 setOperationAction(ISD::UDIV, VT, Expand);
830 setOperationAction(ISD::FDIV, VT, Expand);
831 setOperationAction(ISD::SREM, VT, Expand);
832 setOperationAction(ISD::UREM, VT, Expand);
833 setOperationAction(ISD::LOAD, VT, Expand);
834 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
835 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
836 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
837 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
838 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
839 setOperationAction(ISD::FABS, VT, Expand);
840 setOperationAction(ISD::FSIN, VT, Expand);
841 setOperationAction(ISD::FSINCOS, VT, Expand);
842 setOperationAction(ISD::FCOS, VT, Expand);
843 setOperationAction(ISD::FSINCOS, VT, Expand);
844 setOperationAction(ISD::FREM, VT, Expand);
845 setOperationAction(ISD::FMA, VT, Expand);
846 setOperationAction(ISD::FPOWI, VT, Expand);
847 setOperationAction(ISD::FSQRT, VT, Expand);
848 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
849 setOperationAction(ISD::FFLOOR, VT, Expand);
850 setOperationAction(ISD::FCEIL, VT, Expand);
851 setOperationAction(ISD::FTRUNC, VT, Expand);
852 setOperationAction(ISD::FRINT, VT, Expand);
853 setOperationAction(ISD::FNEARBYINT, VT, Expand);
854 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
855 setOperationAction(ISD::MULHS, VT, Expand);
856 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
857 setOperationAction(ISD::MULHU, VT, Expand);
858 setOperationAction(ISD::SDIVREM, VT, Expand);
859 setOperationAction(ISD::UDIVREM, VT, Expand);
860 setOperationAction(ISD::FPOW, VT, Expand);
861 setOperationAction(ISD::CTPOP, VT, Expand);
862 setOperationAction(ISD::CTTZ, VT, Expand);
863 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
864 setOperationAction(ISD::CTLZ, VT, Expand);
865 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
866 setOperationAction(ISD::SHL, VT, Expand);
867 setOperationAction(ISD::SRA, VT, Expand);
868 setOperationAction(ISD::SRL, VT, Expand);
869 setOperationAction(ISD::ROTL, VT, Expand);
870 setOperationAction(ISD::ROTR, VT, Expand);
871 setOperationAction(ISD::BSWAP, VT, Expand);
872 setOperationAction(ISD::SETCC, VT, Expand);
873 setOperationAction(ISD::FLOG, VT, Expand);
874 setOperationAction(ISD::FLOG2, VT, Expand);
875 setOperationAction(ISD::FLOG10, VT, Expand);
876 setOperationAction(ISD::FEXP, VT, Expand);
877 setOperationAction(ISD::FEXP2, VT, Expand);
878 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
879 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
880 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
881 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
882 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
883 setOperationAction(ISD::TRUNCATE, VT, Expand);
884 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
885 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
886 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
887 setOperationAction(ISD::VSELECT, VT, Expand);
888 setOperationAction(ISD::SELECT_CC, VT, Expand);
889 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
890 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
891 setTruncStoreAction(VT,
892 (MVT::SimpleValueType)InnerVT, Expand);
893 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
894 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
896 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
897 // we have to deal with them whether we ask for Expansion or not. Setting
898 // Expand causes its own optimisation problems though, so leave them legal.
899 if (VT.getVectorElementType() == MVT::i1)
900 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
903 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
904 // with -msoft-float, disable use of MMX as well.
905 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
906 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
907 // No operations on x86mmx supported, everything uses intrinsics.
910 // MMX-sized vectors (other than x86mmx) are expected to be expanded
911 // into smaller operations.
912 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
913 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
914 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
915 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
916 setOperationAction(ISD::AND, MVT::v8i8, Expand);
917 setOperationAction(ISD::AND, MVT::v4i16, Expand);
918 setOperationAction(ISD::AND, MVT::v2i32, Expand);
919 setOperationAction(ISD::AND, MVT::v1i64, Expand);
920 setOperationAction(ISD::OR, MVT::v8i8, Expand);
921 setOperationAction(ISD::OR, MVT::v4i16, Expand);
922 setOperationAction(ISD::OR, MVT::v2i32, Expand);
923 setOperationAction(ISD::OR, MVT::v1i64, Expand);
924 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
925 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
926 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
927 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
928 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
929 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
930 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
931 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
932 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
933 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
934 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
935 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
936 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
937 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
938 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
939 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
940 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
942 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
943 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
945 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
946 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
947 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
948 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
949 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
950 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
951 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
952 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
953 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
954 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
955 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
956 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
959 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
960 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
962 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
963 // registers cannot be used even for integer operations.
964 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
965 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
966 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
967 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
969 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
970 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
971 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
972 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
973 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
974 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
975 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
976 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
977 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
978 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
979 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
980 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
981 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
982 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
983 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
984 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
985 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
986 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
987 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
988 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
989 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
990 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
992 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
993 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
994 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
995 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
997 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
998 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
999 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1000 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1001 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1003 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1004 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1005 MVT VT = (MVT::SimpleValueType)i;
1006 // Do not attempt to custom lower non-power-of-2 vectors
1007 if (!isPowerOf2_32(VT.getVectorNumElements()))
1009 // Do not attempt to custom lower non-128-bit vectors
1010 if (!VT.is128BitVector())
1012 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1013 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1014 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1017 // We support custom legalizing of sext and anyext loads for specific
1018 // memory vector types which we can load as a scalar (or sequence of
1019 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1020 // loads these must work with a single scalar load.
1021 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1022 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1023 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1025 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1026 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1027 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1028 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1029 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1031 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1032 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1033 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1034 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1035 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1036 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1038 if (Subtarget->is64Bit()) {
1039 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1040 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1043 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1044 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1045 MVT VT = (MVT::SimpleValueType)i;
1047 // Do not attempt to promote non-128-bit vectors
1048 if (!VT.is128BitVector())
1051 setOperationAction(ISD::AND, VT, Promote);
1052 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1053 setOperationAction(ISD::OR, VT, Promote);
1054 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1055 setOperationAction(ISD::XOR, VT, Promote);
1056 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1057 setOperationAction(ISD::LOAD, VT, Promote);
1058 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1059 setOperationAction(ISD::SELECT, VT, Promote);
1060 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1063 // Custom lower v2i64 and v2f64 selects.
1064 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1065 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1066 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1067 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1069 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1070 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1073 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1074 // As there is no 64-bit GPR available, we need build a special custom
1075 // sequence to convert from v2i32 to v2f32.
1076 if (!Subtarget->is64Bit())
1077 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1079 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1080 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1082 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1084 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1085 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1086 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1089 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1090 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1091 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1092 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1093 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1094 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1095 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1096 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1097 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1098 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1099 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1101 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1102 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1103 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1104 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1105 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1107 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1108 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1109 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1110 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1112 // FIXME: Do we need to handle scalar-to-vector here?
1113 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1115 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1116 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1117 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1118 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1119 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1120 // There is no BLENDI for byte vectors. We don't need to custom lower
1121 // some vselects for now.
1122 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1124 // SSE41 brings specific instructions for doing vector sign extend even in
1125 // cases where we don't have SRA.
1126 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1127 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1128 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1130 // i8 and i16 vectors are custom because the source register and source
1131 // source memory operand types are not the same width. f32 vectors are
1132 // custom since the immediate controlling the insert encodes additional
1134 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1135 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1139 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1144 // FIXME: these should be Legal, but that's only for the case where
1145 // the index is constant. For now custom expand to deal with that.
1146 if (Subtarget->is64Bit()) {
1147 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1148 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1152 if (Subtarget->hasSSE2()) {
1153 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1154 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1156 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1157 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1159 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1160 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1162 // In the customized shift lowering, the legal cases in AVX2 will be
1164 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1165 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1167 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1168 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1170 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1173 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1174 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1175 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1176 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1177 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1178 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1179 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1181 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1182 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1183 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1185 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1186 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1191 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1192 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1193 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1194 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1196 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1198 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1199 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1209 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1211 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1212 // even though v8i16 is a legal type.
1213 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1214 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1215 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1217 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1218 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1219 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1221 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1222 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1224 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1226 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1227 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1230 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1232 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1233 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1238 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1240 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1241 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1242 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1244 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1245 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1246 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1247 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1249 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1250 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1252 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1253 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1254 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1255 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1256 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1257 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1258 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1259 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1260 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1262 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1263 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1264 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1265 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1266 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1267 setOperationAction(ISD::FMA, MVT::f32, Legal);
1268 setOperationAction(ISD::FMA, MVT::f64, Legal);
1271 if (Subtarget->hasInt256()) {
1272 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1273 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1274 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1275 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1277 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1278 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1279 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1280 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1282 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1283 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1284 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1285 // Don't lower v32i8 because there is no 128-bit byte mul
1287 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1288 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1289 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1290 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1292 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1293 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1295 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1296 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1297 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1298 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1300 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1301 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1302 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1303 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1305 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1306 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1307 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1308 // Don't lower v32i8 because there is no 128-bit byte mul
1311 // In the customized shift lowering, the legal cases in AVX2 will be
1313 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1314 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1316 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1317 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1319 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1321 // Custom lower several nodes for 256-bit types.
1322 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1323 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1324 MVT VT = (MVT::SimpleValueType)i;
1326 // Extract subvector is special because the value type
1327 // (result) is 128-bit but the source is 256-bit wide.
1328 if (VT.is128BitVector())
1329 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1331 // Do not attempt to custom lower other non-256-bit vectors
1332 if (!VT.is256BitVector())
1335 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1336 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1337 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1338 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1339 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1340 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1341 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1344 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1345 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1346 MVT VT = (MVT::SimpleValueType)i;
1348 // Do not attempt to promote non-256-bit vectors
1349 if (!VT.is256BitVector())
1352 setOperationAction(ISD::AND, VT, Promote);
1353 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1354 setOperationAction(ISD::OR, VT, Promote);
1355 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1356 setOperationAction(ISD::XOR, VT, Promote);
1357 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1358 setOperationAction(ISD::LOAD, VT, Promote);
1359 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1360 setOperationAction(ISD::SELECT, VT, Promote);
1361 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1365 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1366 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1367 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1368 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1369 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1371 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1372 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1373 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1375 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1376 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1377 setOperationAction(ISD::XOR, MVT::i1, Legal);
1378 setOperationAction(ISD::OR, MVT::i1, Legal);
1379 setOperationAction(ISD::AND, MVT::i1, Legal);
1380 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1381 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1382 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1385 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1387 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1388 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1389 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1392 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1394 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1395 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1399 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1400 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1401 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1403 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1404 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1405 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1406 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1407 if (Subtarget->is64Bit()) {
1408 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1409 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1410 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1421 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1422 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1424 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1425 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1430 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1438 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1445 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1446 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1448 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1450 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1451 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1452 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1453 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1454 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1455 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1456 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1460 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1461 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1463 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1464 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1466 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1468 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1469 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1471 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1472 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1474 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1477 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1478 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1479 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1480 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1481 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1482 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1484 if (Subtarget->hasCDI()) {
1485 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1486 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1489 // Custom lower several nodes.
1490 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1491 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1492 MVT VT = (MVT::SimpleValueType)i;
1494 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1495 // Extract subvector is special because the value type
1496 // (result) is 256/128-bit but the source is 512-bit wide.
1497 if (VT.is128BitVector() || VT.is256BitVector())
1498 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1500 if (VT.getVectorElementType() == MVT::i1)
1501 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1503 // Do not attempt to custom lower other non-512-bit vectors
1504 if (!VT.is512BitVector())
1507 if ( EltSize >= 32) {
1508 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1509 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1510 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1511 setOperationAction(ISD::VSELECT, VT, Legal);
1512 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1513 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1514 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1517 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1518 MVT VT = (MVT::SimpleValueType)i;
1520 // Do not attempt to promote non-256-bit vectors
1521 if (!VT.is512BitVector())
1524 setOperationAction(ISD::SELECT, VT, Promote);
1525 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1529 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1530 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1531 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1533 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1534 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1536 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1537 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1538 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1539 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1541 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1542 const MVT VT = (MVT::SimpleValueType)i;
1544 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1546 // Do not attempt to promote non-256-bit vectors
1547 if (!VT.is512BitVector())
1550 if ( EltSize < 32) {
1551 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1552 setOperationAction(ISD::VSELECT, VT, Legal);
1557 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1558 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1559 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1561 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1562 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1563 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1566 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1567 // of this type with custom code.
1568 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1569 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1570 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1574 // We want to custom lower some of our intrinsics.
1575 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1576 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1577 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1578 if (!Subtarget->is64Bit())
1579 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1581 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1582 // handle type legalization for these operations here.
1584 // FIXME: We really should do custom legalization for addition and
1585 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1586 // than generic legalization for 64-bit multiplication-with-overflow, though.
1587 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1588 // Add/Sub/Mul with overflow operations are custom lowered.
1590 setOperationAction(ISD::SADDO, VT, Custom);
1591 setOperationAction(ISD::UADDO, VT, Custom);
1592 setOperationAction(ISD::SSUBO, VT, Custom);
1593 setOperationAction(ISD::USUBO, VT, Custom);
1594 setOperationAction(ISD::SMULO, VT, Custom);
1595 setOperationAction(ISD::UMULO, VT, Custom);
1598 // There are no 8-bit 3-address imul/mul instructions
1599 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1600 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1602 if (!Subtarget->is64Bit()) {
1603 // These libcalls are not available in 32-bit.
1604 setLibcallName(RTLIB::SHL_I128, nullptr);
1605 setLibcallName(RTLIB::SRL_I128, nullptr);
1606 setLibcallName(RTLIB::SRA_I128, nullptr);
1609 // Combine sin / cos into one node or libcall if possible.
1610 if (Subtarget->hasSinCos()) {
1611 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1612 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1613 if (Subtarget->isTargetDarwin()) {
1614 // For MacOSX, we don't want to the normal expansion of a libcall to
1615 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1617 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1618 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1622 if (Subtarget->isTargetWin64()) {
1623 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1624 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1625 setOperationAction(ISD::SREM, MVT::i128, Custom);
1626 setOperationAction(ISD::UREM, MVT::i128, Custom);
1627 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1628 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1631 // We have target-specific dag combine patterns for the following nodes:
1632 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1633 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1634 setTargetDAGCombine(ISD::VSELECT);
1635 setTargetDAGCombine(ISD::SELECT);
1636 setTargetDAGCombine(ISD::SHL);
1637 setTargetDAGCombine(ISD::SRA);
1638 setTargetDAGCombine(ISD::SRL);
1639 setTargetDAGCombine(ISD::OR);
1640 setTargetDAGCombine(ISD::AND);
1641 setTargetDAGCombine(ISD::ADD);
1642 setTargetDAGCombine(ISD::FADD);
1643 setTargetDAGCombine(ISD::FSUB);
1644 setTargetDAGCombine(ISD::FMA);
1645 setTargetDAGCombine(ISD::SUB);
1646 setTargetDAGCombine(ISD::LOAD);
1647 setTargetDAGCombine(ISD::STORE);
1648 setTargetDAGCombine(ISD::ZERO_EXTEND);
1649 setTargetDAGCombine(ISD::ANY_EXTEND);
1650 setTargetDAGCombine(ISD::SIGN_EXTEND);
1651 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1652 setTargetDAGCombine(ISD::TRUNCATE);
1653 setTargetDAGCombine(ISD::SINT_TO_FP);
1654 setTargetDAGCombine(ISD::SETCC);
1655 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1656 setTargetDAGCombine(ISD::BUILD_VECTOR);
1657 if (Subtarget->is64Bit())
1658 setTargetDAGCombine(ISD::MUL);
1659 setTargetDAGCombine(ISD::XOR);
1661 computeRegisterProperties();
1663 // On Darwin, -Os means optimize for size without hurting performance,
1664 // do not reduce the limit.
1665 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1666 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1667 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1668 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1669 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1670 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1671 setPrefLoopAlignment(4); // 2^4 bytes.
1673 // Predictable cmov don't hurt on atom because it's in-order.
1674 PredictableSelectIsExpensive = !Subtarget->isAtom();
1676 setPrefFunctionAlignment(4); // 2^4 bytes.
1678 verifyIntrinsicTables();
1681 // This has so far only been implemented for 64-bit MachO.
1682 bool X86TargetLowering::useLoadStackGuardNode() const {
1683 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1684 Subtarget->is64Bit();
1687 TargetLoweringBase::LegalizeTypeAction
1688 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1689 if (ExperimentalVectorWideningLegalization &&
1690 VT.getVectorNumElements() != 1 &&
1691 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1692 return TypeWidenVector;
1694 return TargetLoweringBase::getPreferredVectorAction(VT);
1697 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1699 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1701 const unsigned NumElts = VT.getVectorNumElements();
1702 const EVT EltVT = VT.getVectorElementType();
1703 if (VT.is512BitVector()) {
1704 if (Subtarget->hasAVX512())
1705 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1706 EltVT == MVT::f32 || EltVT == MVT::f64)
1708 case 8: return MVT::v8i1;
1709 case 16: return MVT::v16i1;
1711 if (Subtarget->hasBWI())
1712 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1714 case 32: return MVT::v32i1;
1715 case 64: return MVT::v64i1;
1719 if (VT.is256BitVector() || VT.is128BitVector()) {
1720 if (Subtarget->hasVLX())
1721 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1722 EltVT == MVT::f32 || EltVT == MVT::f64)
1724 case 2: return MVT::v2i1;
1725 case 4: return MVT::v4i1;
1726 case 8: return MVT::v8i1;
1728 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1729 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1731 case 8: return MVT::v8i1;
1732 case 16: return MVT::v16i1;
1733 case 32: return MVT::v32i1;
1737 return VT.changeVectorElementTypeToInteger();
1740 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1741 /// the desired ByVal argument alignment.
1742 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1745 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1746 if (VTy->getBitWidth() == 128)
1748 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1749 unsigned EltAlign = 0;
1750 getMaxByValAlign(ATy->getElementType(), EltAlign);
1751 if (EltAlign > MaxAlign)
1752 MaxAlign = EltAlign;
1753 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1754 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1755 unsigned EltAlign = 0;
1756 getMaxByValAlign(STy->getElementType(i), EltAlign);
1757 if (EltAlign > MaxAlign)
1758 MaxAlign = EltAlign;
1765 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1766 /// function arguments in the caller parameter area. For X86, aggregates
1767 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1768 /// are at 4-byte boundaries.
1769 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1770 if (Subtarget->is64Bit()) {
1771 // Max of 8 and alignment of type.
1772 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1779 if (Subtarget->hasSSE1())
1780 getMaxByValAlign(Ty, Align);
1784 /// getOptimalMemOpType - Returns the target specific optimal type for load
1785 /// and store operations as a result of memset, memcpy, and memmove
1786 /// lowering. If DstAlign is zero that means it's safe to destination
1787 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1788 /// means there isn't a need to check it against alignment requirement,
1789 /// probably because the source does not need to be loaded. If 'IsMemset' is
1790 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1791 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1792 /// source is constant so it does not need to be loaded.
1793 /// It returns EVT::Other if the type should be determined using generic
1794 /// target-independent logic.
1796 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1797 unsigned DstAlign, unsigned SrcAlign,
1798 bool IsMemset, bool ZeroMemset,
1800 MachineFunction &MF) const {
1801 const Function *F = MF.getFunction();
1802 if ((!IsMemset || ZeroMemset) &&
1803 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1804 Attribute::NoImplicitFloat)) {
1806 (Subtarget->isUnalignedMemAccessFast() ||
1807 ((DstAlign == 0 || DstAlign >= 16) &&
1808 (SrcAlign == 0 || SrcAlign >= 16)))) {
1810 if (Subtarget->hasInt256())
1812 if (Subtarget->hasFp256())
1815 if (Subtarget->hasSSE2())
1817 if (Subtarget->hasSSE1())
1819 } else if (!MemcpyStrSrc && Size >= 8 &&
1820 !Subtarget->is64Bit() &&
1821 Subtarget->hasSSE2()) {
1822 // Do not use f64 to lower memcpy if source is string constant. It's
1823 // better to use i32 to avoid the loads.
1827 if (Subtarget->is64Bit() && Size >= 8)
1832 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1834 return X86ScalarSSEf32;
1835 else if (VT == MVT::f64)
1836 return X86ScalarSSEf64;
1841 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1846 *Fast = Subtarget->isUnalignedMemAccessFast();
1850 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1851 /// current function. The returned value is a member of the
1852 /// MachineJumpTableInfo::JTEntryKind enum.
1853 unsigned X86TargetLowering::getJumpTableEncoding() const {
1854 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1856 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1857 Subtarget->isPICStyleGOT())
1858 return MachineJumpTableInfo::EK_Custom32;
1860 // Otherwise, use the normal jump table encoding heuristics.
1861 return TargetLowering::getJumpTableEncoding();
1865 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1866 const MachineBasicBlock *MBB,
1867 unsigned uid,MCContext &Ctx) const{
1868 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1869 Subtarget->isPICStyleGOT());
1870 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1872 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1873 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1876 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1878 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1879 SelectionDAG &DAG) const {
1880 if (!Subtarget->is64Bit())
1881 // This doesn't have SDLoc associated with it, but is not really the
1882 // same as a Register.
1883 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1887 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1888 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1890 const MCExpr *X86TargetLowering::
1891 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1892 MCContext &Ctx) const {
1893 // X86-64 uses RIP relative addressing based on the jump table label.
1894 if (Subtarget->isPICStyleRIPRel())
1895 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1897 // Otherwise, the reference is relative to the PIC base.
1898 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1901 // FIXME: Why this routine is here? Move to RegInfo!
1902 std::pair<const TargetRegisterClass*, uint8_t>
1903 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1904 const TargetRegisterClass *RRC = nullptr;
1906 switch (VT.SimpleTy) {
1908 return TargetLowering::findRepresentativeClass(VT);
1909 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1910 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1913 RRC = &X86::VR64RegClass;
1915 case MVT::f32: case MVT::f64:
1916 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1917 case MVT::v4f32: case MVT::v2f64:
1918 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1920 RRC = &X86::VR128RegClass;
1923 return std::make_pair(RRC, Cost);
1926 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1927 unsigned &Offset) const {
1928 if (!Subtarget->isTargetLinux())
1931 if (Subtarget->is64Bit()) {
1932 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1934 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1946 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1947 unsigned DestAS) const {
1948 assert(SrcAS != DestAS && "Expected different address spaces!");
1950 return SrcAS < 256 && DestAS < 256;
1953 //===----------------------------------------------------------------------===//
1954 // Return Value Calling Convention Implementation
1955 //===----------------------------------------------------------------------===//
1957 #include "X86GenCallingConv.inc"
1960 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1961 MachineFunction &MF, bool isVarArg,
1962 const SmallVectorImpl<ISD::OutputArg> &Outs,
1963 LLVMContext &Context) const {
1964 SmallVector<CCValAssign, 16> RVLocs;
1965 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1966 return CCInfo.CheckReturn(Outs, RetCC_X86);
1969 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1970 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1975 X86TargetLowering::LowerReturn(SDValue Chain,
1976 CallingConv::ID CallConv, bool isVarArg,
1977 const SmallVectorImpl<ISD::OutputArg> &Outs,
1978 const SmallVectorImpl<SDValue> &OutVals,
1979 SDLoc dl, SelectionDAG &DAG) const {
1980 MachineFunction &MF = DAG.getMachineFunction();
1981 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1983 SmallVector<CCValAssign, 16> RVLocs;
1984 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1985 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1988 SmallVector<SDValue, 6> RetOps;
1989 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1990 // Operand #1 = Bytes To Pop
1991 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1994 // Copy the result values into the output registers.
1995 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1996 CCValAssign &VA = RVLocs[i];
1997 assert(VA.isRegLoc() && "Can only return in registers!");
1998 SDValue ValToCopy = OutVals[i];
1999 EVT ValVT = ValToCopy.getValueType();
2001 // Promote values to the appropriate types
2002 if (VA.getLocInfo() == CCValAssign::SExt)
2003 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2004 else if (VA.getLocInfo() == CCValAssign::ZExt)
2005 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2006 else if (VA.getLocInfo() == CCValAssign::AExt)
2007 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2008 else if (VA.getLocInfo() == CCValAssign::BCvt)
2009 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2011 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2012 "Unexpected FP-extend for return value.");
2014 // If this is x86-64, and we disabled SSE, we can't return FP values,
2015 // or SSE or MMX vectors.
2016 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2017 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2018 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2019 report_fatal_error("SSE register return with SSE disabled");
2021 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2022 // llvm-gcc has never done it right and no one has noticed, so this
2023 // should be OK for now.
2024 if (ValVT == MVT::f64 &&
2025 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2026 report_fatal_error("SSE2 register return with SSE2 disabled");
2028 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2029 // the RET instruction and handled by the FP Stackifier.
2030 if (VA.getLocReg() == X86::FP0 ||
2031 VA.getLocReg() == X86::FP1) {
2032 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2033 // change the value to the FP stack register class.
2034 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2035 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2036 RetOps.push_back(ValToCopy);
2037 // Don't emit a copytoreg.
2041 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2042 // which is returned in RAX / RDX.
2043 if (Subtarget->is64Bit()) {
2044 if (ValVT == MVT::x86mmx) {
2045 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2046 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2047 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2049 // If we don't have SSE2 available, convert to v4f32 so the generated
2050 // register is legal.
2051 if (!Subtarget->hasSSE2())
2052 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2057 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2058 Flag = Chain.getValue(1);
2059 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2062 // The x86-64 ABIs require that for returning structs by value we copy
2063 // the sret argument into %rax/%eax (depending on ABI) for the return.
2064 // Win32 requires us to put the sret argument to %eax as well.
2065 // We saved the argument into a virtual register in the entry block,
2066 // so now we copy the value out and into %rax/%eax.
2067 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2068 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2069 MachineFunction &MF = DAG.getMachineFunction();
2070 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2071 unsigned Reg = FuncInfo->getSRetReturnReg();
2073 "SRetReturnReg should have been set in LowerFormalArguments().");
2074 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2077 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2078 X86::RAX : X86::EAX;
2079 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2080 Flag = Chain.getValue(1);
2082 // RAX/EAX now acts like a return value.
2083 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2086 RetOps[0] = Chain; // Update chain.
2088 // Add the flag if we have it.
2090 RetOps.push_back(Flag);
2092 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2095 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2096 if (N->getNumValues() != 1)
2098 if (!N->hasNUsesOfValue(1, 0))
2101 SDValue TCChain = Chain;
2102 SDNode *Copy = *N->use_begin();
2103 if (Copy->getOpcode() == ISD::CopyToReg) {
2104 // If the copy has a glue operand, we conservatively assume it isn't safe to
2105 // perform a tail call.
2106 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2108 TCChain = Copy->getOperand(0);
2109 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2112 bool HasRet = false;
2113 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2115 if (UI->getOpcode() != X86ISD::RET_FLAG)
2117 // If we are returning more than one value, we can definitely
2118 // not make a tail call see PR19530
2119 if (UI->getNumOperands() > 4)
2121 if (UI->getNumOperands() == 4 &&
2122 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2135 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2136 ISD::NodeType ExtendKind) const {
2138 // TODO: Is this also valid on 32-bit?
2139 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2140 ReturnMVT = MVT::i8;
2142 ReturnMVT = MVT::i32;
2144 EVT MinVT = getRegisterType(Context, ReturnMVT);
2145 return VT.bitsLT(MinVT) ? MinVT : VT;
2148 /// LowerCallResult - Lower the result values of a call into the
2149 /// appropriate copies out of appropriate physical registers.
2152 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2153 CallingConv::ID CallConv, bool isVarArg,
2154 const SmallVectorImpl<ISD::InputArg> &Ins,
2155 SDLoc dl, SelectionDAG &DAG,
2156 SmallVectorImpl<SDValue> &InVals) const {
2158 // Assign locations to each value returned by this call.
2159 SmallVector<CCValAssign, 16> RVLocs;
2160 bool Is64Bit = Subtarget->is64Bit();
2161 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2163 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2165 // Copy all of the result registers out of their specified physreg.
2166 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2167 CCValAssign &VA = RVLocs[i];
2168 EVT CopyVT = VA.getValVT();
2170 // If this is x86-64, and we disabled SSE, we can't return FP values
2171 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2172 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2173 report_fatal_error("SSE register return with SSE disabled");
2176 // If we prefer to use the value in xmm registers, copy it out as f80 and
2177 // use a truncate to move it from fp stack reg to xmm reg.
2178 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2179 isScalarFPTypeInSSEReg(VA.getValVT()))
2182 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2183 CopyVT, InFlag).getValue(1);
2184 SDValue Val = Chain.getValue(0);
2186 if (CopyVT != VA.getValVT())
2187 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2188 // This truncation won't change the value.
2189 DAG.getIntPtrConstant(1));
2191 InFlag = Chain.getValue(2);
2192 InVals.push_back(Val);
2198 //===----------------------------------------------------------------------===//
2199 // C & StdCall & Fast Calling Convention implementation
2200 //===----------------------------------------------------------------------===//
2201 // StdCall calling convention seems to be standard for many Windows' API
2202 // routines and around. It differs from C calling convention just a little:
2203 // callee should clean up the stack, not caller. Symbols should be also
2204 // decorated in some fancy way :) It doesn't support any vector arguments.
2205 // For info on fast calling convention see Fast Calling Convention (tail call)
2206 // implementation LowerX86_32FastCCCallTo.
2208 /// CallIsStructReturn - Determines whether a call uses struct return
2210 enum StructReturnType {
2215 static StructReturnType
2216 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2218 return NotStructReturn;
2220 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2221 if (!Flags.isSRet())
2222 return NotStructReturn;
2223 if (Flags.isInReg())
2224 return RegStructReturn;
2225 return StackStructReturn;
2228 /// ArgsAreStructReturn - Determines whether a function uses struct
2229 /// return semantics.
2230 static StructReturnType
2231 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2233 return NotStructReturn;
2235 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2236 if (!Flags.isSRet())
2237 return NotStructReturn;
2238 if (Flags.isInReg())
2239 return RegStructReturn;
2240 return StackStructReturn;
2243 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2244 /// by "Src" to address "Dst" with size and alignment information specified by
2245 /// the specific parameter attribute. The copy will be passed as a byval
2246 /// function parameter.
2248 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2249 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2251 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2253 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2254 /*isVolatile*/false, /*AlwaysInline=*/true,
2255 MachinePointerInfo(), MachinePointerInfo());
2258 /// IsTailCallConvention - Return true if the calling convention is one that
2259 /// supports tail call optimization.
2260 static bool IsTailCallConvention(CallingConv::ID CC) {
2261 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2262 CC == CallingConv::HiPE);
2265 /// \brief Return true if the calling convention is a C calling convention.
2266 static bool IsCCallConvention(CallingConv::ID CC) {
2267 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2268 CC == CallingConv::X86_64_SysV);
2271 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2272 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2276 CallingConv::ID CalleeCC = CS.getCallingConv();
2277 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2283 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2284 /// a tailcall target by changing its ABI.
2285 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2286 bool GuaranteedTailCallOpt) {
2287 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2291 X86TargetLowering::LowerMemArgument(SDValue Chain,
2292 CallingConv::ID CallConv,
2293 const SmallVectorImpl<ISD::InputArg> &Ins,
2294 SDLoc dl, SelectionDAG &DAG,
2295 const CCValAssign &VA,
2296 MachineFrameInfo *MFI,
2298 // Create the nodes corresponding to a load from this parameter slot.
2299 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2300 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2301 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2302 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2305 // If value is passed by pointer we have address passed instead of the value
2307 if (VA.getLocInfo() == CCValAssign::Indirect)
2308 ValVT = VA.getLocVT();
2310 ValVT = VA.getValVT();
2312 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2313 // changed with more analysis.
2314 // In case of tail call optimization mark all arguments mutable. Since they
2315 // could be overwritten by lowering of arguments in case of a tail call.
2316 if (Flags.isByVal()) {
2317 unsigned Bytes = Flags.getByValSize();
2318 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2319 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2320 return DAG.getFrameIndex(FI, getPointerTy());
2322 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2323 VA.getLocMemOffset(), isImmutable);
2324 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2325 return DAG.getLoad(ValVT, dl, Chain, FIN,
2326 MachinePointerInfo::getFixedStack(FI),
2327 false, false, false, 0);
2331 // FIXME: Get this from tablegen.
2332 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2333 const X86Subtarget *Subtarget) {
2334 assert(Subtarget->is64Bit());
2336 if (Subtarget->isCallingConvWin64(CallConv)) {
2337 static const MCPhysReg GPR64ArgRegsWin64[] = {
2338 X86::RCX, X86::RDX, X86::R8, X86::R9
2340 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2343 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2344 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2346 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2349 // FIXME: Get this from tablegen.
2350 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2351 CallingConv::ID CallConv,
2352 const X86Subtarget *Subtarget) {
2353 assert(Subtarget->is64Bit());
2354 if (Subtarget->isCallingConvWin64(CallConv)) {
2355 // The XMM registers which might contain var arg parameters are shadowed
2356 // in their paired GPR. So we only need to save the GPR to their home
2358 // TODO: __vectorcall will change this.
2362 const Function *Fn = MF.getFunction();
2363 bool NoImplicitFloatOps = Fn->getAttributes().
2364 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2365 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2366 "SSE register cannot be used when SSE is disabled!");
2367 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2368 !Subtarget->hasSSE1())
2369 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2373 static const MCPhysReg XMMArgRegs64Bit[] = {
2374 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2375 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2377 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2381 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2382 CallingConv::ID CallConv,
2384 const SmallVectorImpl<ISD::InputArg> &Ins,
2387 SmallVectorImpl<SDValue> &InVals)
2389 MachineFunction &MF = DAG.getMachineFunction();
2390 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2392 const Function* Fn = MF.getFunction();
2393 if (Fn->hasExternalLinkage() &&
2394 Subtarget->isTargetCygMing() &&
2395 Fn->getName() == "main")
2396 FuncInfo->setForceFramePointer(true);
2398 MachineFrameInfo *MFI = MF.getFrameInfo();
2399 bool Is64Bit = Subtarget->is64Bit();
2400 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2402 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2403 "Var args not supported with calling convention fastcc, ghc or hipe");
2405 // Assign locations to all of the incoming arguments.
2406 SmallVector<CCValAssign, 16> ArgLocs;
2407 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2409 // Allocate shadow area for Win64
2411 CCInfo.AllocateStack(32, 8);
2413 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2415 unsigned LastVal = ~0U;
2417 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2418 CCValAssign &VA = ArgLocs[i];
2419 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2421 assert(VA.getValNo() != LastVal &&
2422 "Don't support value assigned to multiple locs yet");
2424 LastVal = VA.getValNo();
2426 if (VA.isRegLoc()) {
2427 EVT RegVT = VA.getLocVT();
2428 const TargetRegisterClass *RC;
2429 if (RegVT == MVT::i32)
2430 RC = &X86::GR32RegClass;
2431 else if (Is64Bit && RegVT == MVT::i64)
2432 RC = &X86::GR64RegClass;
2433 else if (RegVT == MVT::f32)
2434 RC = &X86::FR32RegClass;
2435 else if (RegVT == MVT::f64)
2436 RC = &X86::FR64RegClass;
2437 else if (RegVT.is512BitVector())
2438 RC = &X86::VR512RegClass;
2439 else if (RegVT.is256BitVector())
2440 RC = &X86::VR256RegClass;
2441 else if (RegVT.is128BitVector())
2442 RC = &X86::VR128RegClass;
2443 else if (RegVT == MVT::x86mmx)
2444 RC = &X86::VR64RegClass;
2445 else if (RegVT == MVT::i1)
2446 RC = &X86::VK1RegClass;
2447 else if (RegVT == MVT::v8i1)
2448 RC = &X86::VK8RegClass;
2449 else if (RegVT == MVT::v16i1)
2450 RC = &X86::VK16RegClass;
2451 else if (RegVT == MVT::v32i1)
2452 RC = &X86::VK32RegClass;
2453 else if (RegVT == MVT::v64i1)
2454 RC = &X86::VK64RegClass;
2456 llvm_unreachable("Unknown argument type!");
2458 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2459 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2461 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2462 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2464 if (VA.getLocInfo() == CCValAssign::SExt)
2465 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2466 DAG.getValueType(VA.getValVT()));
2467 else if (VA.getLocInfo() == CCValAssign::ZExt)
2468 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2469 DAG.getValueType(VA.getValVT()));
2470 else if (VA.getLocInfo() == CCValAssign::BCvt)
2471 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2473 if (VA.isExtInLoc()) {
2474 // Handle MMX values passed in XMM regs.
2475 if (RegVT.isVector())
2476 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2478 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2481 assert(VA.isMemLoc());
2482 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2485 // If value is passed via pointer - do a load.
2486 if (VA.getLocInfo() == CCValAssign::Indirect)
2487 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2488 MachinePointerInfo(), false, false, false, 0);
2490 InVals.push_back(ArgValue);
2493 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2494 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2495 // The x86-64 ABIs require that for returning structs by value we copy
2496 // the sret argument into %rax/%eax (depending on ABI) for the return.
2497 // Win32 requires us to put the sret argument to %eax as well.
2498 // Save the argument into a virtual register so that we can access it
2499 // from the return points.
2500 if (Ins[i].Flags.isSRet()) {
2501 unsigned Reg = FuncInfo->getSRetReturnReg();
2503 MVT PtrTy = getPointerTy();
2504 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2505 FuncInfo->setSRetReturnReg(Reg);
2507 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2508 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2514 unsigned StackSize = CCInfo.getNextStackOffset();
2515 // Align stack specially for tail calls.
2516 if (FuncIsMadeTailCallSafe(CallConv,
2517 MF.getTarget().Options.GuaranteedTailCallOpt))
2518 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2520 // If the function takes variable number of arguments, make a frame index for
2521 // the start of the first vararg value... for expansion of llvm.va_start. We
2522 // can skip this if there are no va_start calls.
2523 if (MFI->hasVAStart() &&
2524 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2525 CallConv != CallingConv::X86_ThisCall))) {
2526 FuncInfo->setVarArgsFrameIndex(
2527 MFI->CreateFixedObject(1, StackSize, true));
2530 // 64-bit calling conventions support varargs and register parameters, so we
2531 // have to do extra work to spill them in the prologue or forward them to
2533 if (Is64Bit && isVarArg &&
2534 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2535 // Find the first unallocated argument registers.
2536 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2537 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2538 unsigned NumIntRegs =
2539 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2540 unsigned NumXMMRegs =
2541 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2542 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2543 "SSE register cannot be used when SSE is disabled!");
2545 // Gather all the live in physical registers.
2546 SmallVector<SDValue, 6> LiveGPRs;
2547 SmallVector<SDValue, 8> LiveXMMRegs;
2549 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2550 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2552 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2554 if (!ArgXMMs.empty()) {
2555 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2556 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2557 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2558 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2559 LiveXMMRegs.push_back(
2560 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2564 // Store them to the va_list returned by va_start.
2565 if (MFI->hasVAStart()) {
2567 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2568 // Get to the caller-allocated home save location. Add 8 to account
2569 // for the return address.
2570 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2571 FuncInfo->setRegSaveFrameIndex(
2572 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2573 // Fixup to set vararg frame on shadow area (4 x i64).
2575 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2577 // For X86-64, if there are vararg parameters that are passed via
2578 // registers, then we must store them to their spots on the stack so
2579 // they may be loaded by deferencing the result of va_next.
2580 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2581 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2582 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2583 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2586 // Store the integer parameter registers.
2587 SmallVector<SDValue, 8> MemOps;
2588 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2590 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2591 for (SDValue Val : LiveGPRs) {
2592 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2593 DAG.getIntPtrConstant(Offset));
2595 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2596 MachinePointerInfo::getFixedStack(
2597 FuncInfo->getRegSaveFrameIndex(), Offset),
2599 MemOps.push_back(Store);
2603 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2604 // Now store the XMM (fp + vector) parameter registers.
2605 SmallVector<SDValue, 12> SaveXMMOps;
2606 SaveXMMOps.push_back(Chain);
2607 SaveXMMOps.push_back(ALVal);
2608 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2609 FuncInfo->getRegSaveFrameIndex()));
2610 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2611 FuncInfo->getVarArgsFPOffset()));
2612 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2614 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2615 MVT::Other, SaveXMMOps));
2618 if (!MemOps.empty())
2619 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2621 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2622 // to the liveout set on a musttail call.
2623 assert(MFI->hasMustTailInVarArgFunc());
2624 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2625 typedef X86MachineFunctionInfo::Forward Forward;
2627 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2629 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2630 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2631 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2634 if (!ArgXMMs.empty()) {
2636 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2637 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2638 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2640 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2642 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2643 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2645 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2651 // Some CCs need callee pop.
2652 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2653 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2654 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2656 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2657 // If this is an sret function, the return should pop the hidden pointer.
2658 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2659 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2660 argsAreStructReturn(Ins) == StackStructReturn)
2661 FuncInfo->setBytesToPopOnReturn(4);
2665 // RegSaveFrameIndex is X86-64 only.
2666 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2667 if (CallConv == CallingConv::X86_FastCall ||
2668 CallConv == CallingConv::X86_ThisCall)
2669 // fastcc functions can't have varargs.
2670 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2673 FuncInfo->setArgumentStackSize(StackSize);
2679 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2680 SDValue StackPtr, SDValue Arg,
2681 SDLoc dl, SelectionDAG &DAG,
2682 const CCValAssign &VA,
2683 ISD::ArgFlagsTy Flags) const {
2684 unsigned LocMemOffset = VA.getLocMemOffset();
2685 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2686 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2687 if (Flags.isByVal())
2688 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2690 return DAG.getStore(Chain, dl, Arg, PtrOff,
2691 MachinePointerInfo::getStack(LocMemOffset),
2695 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2696 /// optimization is performed and it is required.
2698 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2699 SDValue &OutRetAddr, SDValue Chain,
2700 bool IsTailCall, bool Is64Bit,
2701 int FPDiff, SDLoc dl) const {
2702 // Adjust the Return address stack slot.
2703 EVT VT = getPointerTy();
2704 OutRetAddr = getReturnAddressFrameIndex(DAG);
2706 // Load the "old" Return address.
2707 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2708 false, false, false, 0);
2709 return SDValue(OutRetAddr.getNode(), 1);
2712 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2713 /// optimization is performed and it is required (FPDiff!=0).
2714 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2715 SDValue Chain, SDValue RetAddrFrIdx,
2716 EVT PtrVT, unsigned SlotSize,
2717 int FPDiff, SDLoc dl) {
2718 // Store the return address to the appropriate stack slot.
2719 if (!FPDiff) return Chain;
2720 // Calculate the new stack slot for the return address.
2721 int NewReturnAddrFI =
2722 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2724 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2725 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2726 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2732 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2733 SmallVectorImpl<SDValue> &InVals) const {
2734 SelectionDAG &DAG = CLI.DAG;
2736 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2737 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2738 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2739 SDValue Chain = CLI.Chain;
2740 SDValue Callee = CLI.Callee;
2741 CallingConv::ID CallConv = CLI.CallConv;
2742 bool &isTailCall = CLI.IsTailCall;
2743 bool isVarArg = CLI.IsVarArg;
2745 MachineFunction &MF = DAG.getMachineFunction();
2746 bool Is64Bit = Subtarget->is64Bit();
2747 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2748 StructReturnType SR = callIsStructReturn(Outs);
2749 bool IsSibcall = false;
2750 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2752 if (MF.getTarget().Options.DisableTailCalls)
2755 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2757 // Force this to be a tail call. The verifier rules are enough to ensure
2758 // that we can lower this successfully without moving the return address
2761 } else if (isTailCall) {
2762 // Check if it's really possible to do a tail call.
2763 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2764 isVarArg, SR != NotStructReturn,
2765 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2766 Outs, OutVals, Ins, DAG);
2768 // Sibcalls are automatically detected tailcalls which do not require
2770 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2777 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2778 "Var args not supported with calling convention fastcc, ghc or hipe");
2780 // Analyze operands of the call, assigning locations to each operand.
2781 SmallVector<CCValAssign, 16> ArgLocs;
2782 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2784 // Allocate shadow area for Win64
2786 CCInfo.AllocateStack(32, 8);
2788 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2790 // Get a count of how many bytes are to be pushed on the stack.
2791 unsigned NumBytes = CCInfo.getNextStackOffset();
2793 // This is a sibcall. The memory operands are available in caller's
2794 // own caller's stack.
2796 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2797 IsTailCallConvention(CallConv))
2798 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2801 if (isTailCall && !IsSibcall && !IsMustTail) {
2802 // Lower arguments at fp - stackoffset + fpdiff.
2803 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2805 FPDiff = NumBytesCallerPushed - NumBytes;
2807 // Set the delta of movement of the returnaddr stackslot.
2808 // But only set if delta is greater than previous delta.
2809 if (FPDiff < X86Info->getTCReturnAddrDelta())
2810 X86Info->setTCReturnAddrDelta(FPDiff);
2813 unsigned NumBytesToPush = NumBytes;
2814 unsigned NumBytesToPop = NumBytes;
2816 // If we have an inalloca argument, all stack space has already been allocated
2817 // for us and be right at the top of the stack. We don't support multiple
2818 // arguments passed in memory when using inalloca.
2819 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2821 if (!ArgLocs.back().isMemLoc())
2822 report_fatal_error("cannot use inalloca attribute on a register "
2824 if (ArgLocs.back().getLocMemOffset() != 0)
2825 report_fatal_error("any parameter with the inalloca attribute must be "
2826 "the only memory argument");
2830 Chain = DAG.getCALLSEQ_START(
2831 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2833 SDValue RetAddrFrIdx;
2834 // Load return address for tail calls.
2835 if (isTailCall && FPDiff)
2836 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2837 Is64Bit, FPDiff, dl);
2839 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2840 SmallVector<SDValue, 8> MemOpChains;
2843 // Walk the register/memloc assignments, inserting copies/loads. In the case
2844 // of tail call optimization arguments are handle later.
2845 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2846 DAG.getSubtarget().getRegisterInfo());
2847 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2848 // Skip inalloca arguments, they have already been written.
2849 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2850 if (Flags.isInAlloca())
2853 CCValAssign &VA = ArgLocs[i];
2854 EVT RegVT = VA.getLocVT();
2855 SDValue Arg = OutVals[i];
2856 bool isByVal = Flags.isByVal();
2858 // Promote the value if needed.
2859 switch (VA.getLocInfo()) {
2860 default: llvm_unreachable("Unknown loc info!");
2861 case CCValAssign::Full: break;
2862 case CCValAssign::SExt:
2863 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2865 case CCValAssign::ZExt:
2866 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2868 case CCValAssign::AExt:
2869 if (RegVT.is128BitVector()) {
2870 // Special case: passing MMX values in XMM registers.
2871 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2872 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2873 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2875 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2877 case CCValAssign::BCvt:
2878 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2880 case CCValAssign::Indirect: {
2881 // Store the argument.
2882 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2883 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2884 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2885 MachinePointerInfo::getFixedStack(FI),
2892 if (VA.isRegLoc()) {
2893 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2894 if (isVarArg && IsWin64) {
2895 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2896 // shadow reg if callee is a varargs function.
2897 unsigned ShadowReg = 0;
2898 switch (VA.getLocReg()) {
2899 case X86::XMM0: ShadowReg = X86::RCX; break;
2900 case X86::XMM1: ShadowReg = X86::RDX; break;
2901 case X86::XMM2: ShadowReg = X86::R8; break;
2902 case X86::XMM3: ShadowReg = X86::R9; break;
2905 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2907 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2908 assert(VA.isMemLoc());
2909 if (!StackPtr.getNode())
2910 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2912 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2913 dl, DAG, VA, Flags));
2917 if (!MemOpChains.empty())
2918 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2920 if (Subtarget->isPICStyleGOT()) {
2921 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2924 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2925 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2927 // If we are tail calling and generating PIC/GOT style code load the
2928 // address of the callee into ECX. The value in ecx is used as target of
2929 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2930 // for tail calls on PIC/GOT architectures. Normally we would just put the
2931 // address of GOT into ebx and then call target@PLT. But for tail calls
2932 // ebx would be restored (since ebx is callee saved) before jumping to the
2935 // Note: The actual moving to ECX is done further down.
2936 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2937 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2938 !G->getGlobal()->hasProtectedVisibility())
2939 Callee = LowerGlobalAddress(Callee, DAG);
2940 else if (isa<ExternalSymbolSDNode>(Callee))
2941 Callee = LowerExternalSymbol(Callee, DAG);
2945 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2946 // From AMD64 ABI document:
2947 // For calls that may call functions that use varargs or stdargs
2948 // (prototype-less calls or calls to functions containing ellipsis (...) in
2949 // the declaration) %al is used as hidden argument to specify the number
2950 // of SSE registers used. The contents of %al do not need to match exactly
2951 // the number of registers, but must be an ubound on the number of SSE
2952 // registers used and is in the range 0 - 8 inclusive.
2954 // Count the number of XMM registers allocated.
2955 static const MCPhysReg XMMArgRegs[] = {
2956 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2957 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2959 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2960 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2961 && "SSE registers cannot be used when SSE is disabled");
2963 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2964 DAG.getConstant(NumXMMRegs, MVT::i8)));
2967 if (Is64Bit && isVarArg && IsMustTail) {
2968 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2969 for (const auto &F : Forwards) {
2970 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2971 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2975 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2976 // don't need this because the eligibility check rejects calls that require
2977 // shuffling arguments passed in memory.
2978 if (!IsSibcall && isTailCall) {
2979 // Force all the incoming stack arguments to be loaded from the stack
2980 // before any new outgoing arguments are stored to the stack, because the
2981 // outgoing stack slots may alias the incoming argument stack slots, and
2982 // the alias isn't otherwise explicit. This is slightly more conservative
2983 // than necessary, because it means that each store effectively depends
2984 // on every argument instead of just those arguments it would clobber.
2985 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2987 SmallVector<SDValue, 8> MemOpChains2;
2990 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2991 CCValAssign &VA = ArgLocs[i];
2994 assert(VA.isMemLoc());
2995 SDValue Arg = OutVals[i];
2996 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2997 // Skip inalloca arguments. They don't require any work.
2998 if (Flags.isInAlloca())
3000 // Create frame index.
3001 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3002 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3003 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3004 FIN = DAG.getFrameIndex(FI, getPointerTy());
3006 if (Flags.isByVal()) {
3007 // Copy relative to framepointer.
3008 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3009 if (!StackPtr.getNode())
3010 StackPtr = DAG.getCopyFromReg(Chain, dl,
3011 RegInfo->getStackRegister(),
3013 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3015 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3019 // Store relative to framepointer.
3020 MemOpChains2.push_back(
3021 DAG.getStore(ArgChain, dl, Arg, FIN,
3022 MachinePointerInfo::getFixedStack(FI),
3027 if (!MemOpChains2.empty())
3028 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3030 // Store the return address to the appropriate stack slot.
3031 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3032 getPointerTy(), RegInfo->getSlotSize(),
3036 // Build a sequence of copy-to-reg nodes chained together with token chain
3037 // and flag operands which copy the outgoing args into registers.
3039 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3040 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3041 RegsToPass[i].second, InFlag);
3042 InFlag = Chain.getValue(1);
3045 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3046 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3047 // In the 64-bit large code model, we have to make all calls
3048 // through a register, since the call instruction's 32-bit
3049 // pc-relative offset may not be large enough to hold the whole
3051 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3052 // If the callee is a GlobalAddress node (quite common, every direct call
3053 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3056 // We should use extra load for direct calls to dllimported functions in
3058 const GlobalValue *GV = G->getGlobal();
3059 if (!GV->hasDLLImportStorageClass()) {
3060 unsigned char OpFlags = 0;
3061 bool ExtraLoad = false;
3062 unsigned WrapperKind = ISD::DELETED_NODE;
3064 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3065 // external symbols most go through the PLT in PIC mode. If the symbol
3066 // has hidden or protected visibility, or if it is static or local, then
3067 // we don't need to use the PLT - we can directly call it.
3068 if (Subtarget->isTargetELF() &&
3069 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3070 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3071 OpFlags = X86II::MO_PLT;
3072 } else if (Subtarget->isPICStyleStubAny() &&
3073 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3074 (!Subtarget->getTargetTriple().isMacOSX() ||
3075 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3076 // PC-relative references to external symbols should go through $stub,
3077 // unless we're building with the leopard linker or later, which
3078 // automatically synthesizes these stubs.
3079 OpFlags = X86II::MO_DARWIN_STUB;
3080 } else if (Subtarget->isPICStyleRIPRel() &&
3081 isa<Function>(GV) &&
3082 cast<Function>(GV)->getAttributes().
3083 hasAttribute(AttributeSet::FunctionIndex,
3084 Attribute::NonLazyBind)) {
3085 // If the function is marked as non-lazy, generate an indirect call
3086 // which loads from the GOT directly. This avoids runtime overhead
3087 // at the cost of eager binding (and one extra byte of encoding).
3088 OpFlags = X86II::MO_GOTPCREL;
3089 WrapperKind = X86ISD::WrapperRIP;
3093 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3094 G->getOffset(), OpFlags);
3096 // Add a wrapper if needed.
3097 if (WrapperKind != ISD::DELETED_NODE)
3098 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3099 // Add extra indirection if needed.
3101 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3102 MachinePointerInfo::getGOT(),
3103 false, false, false, 0);
3105 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3106 unsigned char OpFlags = 0;
3108 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3109 // external symbols should go through the PLT.
3110 if (Subtarget->isTargetELF() &&
3111 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3112 OpFlags = X86II::MO_PLT;
3113 } else if (Subtarget->isPICStyleStubAny() &&
3114 (!Subtarget->getTargetTriple().isMacOSX() ||
3115 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3116 // PC-relative references to external symbols should go through $stub,
3117 // unless we're building with the leopard linker or later, which
3118 // automatically synthesizes these stubs.
3119 OpFlags = X86II::MO_DARWIN_STUB;
3122 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3124 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3125 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3126 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3129 // Returns a chain & a flag for retval copy to use.
3130 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3131 SmallVector<SDValue, 8> Ops;
3133 if (!IsSibcall && isTailCall) {
3134 Chain = DAG.getCALLSEQ_END(Chain,
3135 DAG.getIntPtrConstant(NumBytesToPop, true),
3136 DAG.getIntPtrConstant(0, true), InFlag, dl);
3137 InFlag = Chain.getValue(1);
3140 Ops.push_back(Chain);
3141 Ops.push_back(Callee);
3144 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3146 // Add argument registers to the end of the list so that they are known live
3148 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3149 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3150 RegsToPass[i].second.getValueType()));
3152 // Add a register mask operand representing the call-preserved registers.
3153 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3154 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3155 assert(Mask && "Missing call preserved mask for calling convention");
3156 Ops.push_back(DAG.getRegisterMask(Mask));
3158 if (InFlag.getNode())
3159 Ops.push_back(InFlag);
3163 //// If this is the first return lowered for this function, add the regs
3164 //// to the liveout set for the function.
3165 // This isn't right, although it's probably harmless on x86; liveouts
3166 // should be computed from returns not tail calls. Consider a void
3167 // function making a tail call to a function returning int.
3168 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3171 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3172 InFlag = Chain.getValue(1);
3174 // Create the CALLSEQ_END node.
3175 unsigned NumBytesForCalleeToPop;
3176 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3177 DAG.getTarget().Options.GuaranteedTailCallOpt))
3178 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3179 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3180 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3181 SR == StackStructReturn)
3182 // If this is a call to a struct-return function, the callee
3183 // pops the hidden struct pointer, so we have to push it back.
3184 // This is common for Darwin/X86, Linux & Mingw32 targets.
3185 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3186 NumBytesForCalleeToPop = 4;
3188 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3190 // Returns a flag for retval copy to use.
3192 Chain = DAG.getCALLSEQ_END(Chain,
3193 DAG.getIntPtrConstant(NumBytesToPop, true),
3194 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3197 InFlag = Chain.getValue(1);
3200 // Handle result values, copying them out of physregs into vregs that we
3202 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3203 Ins, dl, DAG, InVals);
3206 //===----------------------------------------------------------------------===//
3207 // Fast Calling Convention (tail call) implementation
3208 //===----------------------------------------------------------------------===//
3210 // Like std call, callee cleans arguments, convention except that ECX is
3211 // reserved for storing the tail called function address. Only 2 registers are
3212 // free for argument passing (inreg). Tail call optimization is performed
3214 // * tailcallopt is enabled
3215 // * caller/callee are fastcc
3216 // On X86_64 architecture with GOT-style position independent code only local
3217 // (within module) calls are supported at the moment.
3218 // To keep the stack aligned according to platform abi the function
3219 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3220 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3221 // If a tail called function callee has more arguments than the caller the
3222 // caller needs to make sure that there is room to move the RETADDR to. This is
3223 // achieved by reserving an area the size of the argument delta right after the
3224 // original RETADDR, but before the saved framepointer or the spilled registers
3225 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3237 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3238 /// for a 16 byte align requirement.
3240 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3241 SelectionDAG& DAG) const {
3242 MachineFunction &MF = DAG.getMachineFunction();
3243 const TargetMachine &TM = MF.getTarget();
3244 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3245 TM.getSubtargetImpl()->getRegisterInfo());
3246 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3247 unsigned StackAlignment = TFI.getStackAlignment();
3248 uint64_t AlignMask = StackAlignment - 1;
3249 int64_t Offset = StackSize;
3250 unsigned SlotSize = RegInfo->getSlotSize();
3251 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3252 // Number smaller than 12 so just add the difference.
3253 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3255 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3256 Offset = ((~AlignMask) & Offset) + StackAlignment +
3257 (StackAlignment-SlotSize);
3262 /// MatchingStackOffset - Return true if the given stack call argument is
3263 /// already available in the same position (relatively) of the caller's
3264 /// incoming argument stack.
3266 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3267 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3268 const X86InstrInfo *TII) {
3269 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3271 if (Arg.getOpcode() == ISD::CopyFromReg) {
3272 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3273 if (!TargetRegisterInfo::isVirtualRegister(VR))
3275 MachineInstr *Def = MRI->getVRegDef(VR);
3278 if (!Flags.isByVal()) {
3279 if (!TII->isLoadFromStackSlot(Def, FI))
3282 unsigned Opcode = Def->getOpcode();
3283 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3284 Def->getOperand(1).isFI()) {
3285 FI = Def->getOperand(1).getIndex();
3286 Bytes = Flags.getByValSize();
3290 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3291 if (Flags.isByVal())
3292 // ByVal argument is passed in as a pointer but it's now being
3293 // dereferenced. e.g.
3294 // define @foo(%struct.X* %A) {
3295 // tail call @bar(%struct.X* byval %A)
3298 SDValue Ptr = Ld->getBasePtr();
3299 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3302 FI = FINode->getIndex();
3303 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3304 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3305 FI = FINode->getIndex();
3306 Bytes = Flags.getByValSize();
3310 assert(FI != INT_MAX);
3311 if (!MFI->isFixedObjectIndex(FI))
3313 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3316 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3317 /// for tail call optimization. Targets which want to do tail call
3318 /// optimization should implement this function.
3320 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3321 CallingConv::ID CalleeCC,
3323 bool isCalleeStructRet,
3324 bool isCallerStructRet,
3326 const SmallVectorImpl<ISD::OutputArg> &Outs,
3327 const SmallVectorImpl<SDValue> &OutVals,
3328 const SmallVectorImpl<ISD::InputArg> &Ins,
3329 SelectionDAG &DAG) const {
3330 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3333 // If -tailcallopt is specified, make fastcc functions tail-callable.
3334 const MachineFunction &MF = DAG.getMachineFunction();
3335 const Function *CallerF = MF.getFunction();
3337 // If the function return type is x86_fp80 and the callee return type is not,
3338 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3339 // perform a tailcall optimization here.
3340 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3343 CallingConv::ID CallerCC = CallerF->getCallingConv();
3344 bool CCMatch = CallerCC == CalleeCC;
3345 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3346 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3348 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3349 if (IsTailCallConvention(CalleeCC) && CCMatch)
3354 // Look for obvious safe cases to perform tail call optimization that do not
3355 // require ABI changes. This is what gcc calls sibcall.
3357 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3358 // emit a special epilogue.
3359 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3360 DAG.getSubtarget().getRegisterInfo());
3361 if (RegInfo->needsStackRealignment(MF))
3364 // Also avoid sibcall optimization if either caller or callee uses struct
3365 // return semantics.
3366 if (isCalleeStructRet || isCallerStructRet)
3369 // An stdcall/thiscall caller is expected to clean up its arguments; the
3370 // callee isn't going to do that.
3371 // FIXME: this is more restrictive than needed. We could produce a tailcall
3372 // when the stack adjustment matches. For example, with a thiscall that takes
3373 // only one argument.
3374 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3375 CallerCC == CallingConv::X86_ThisCall))
3378 // Do not sibcall optimize vararg calls unless all arguments are passed via
3380 if (isVarArg && !Outs.empty()) {
3382 // Optimizing for varargs on Win64 is unlikely to be safe without
3383 // additional testing.
3384 if (IsCalleeWin64 || IsCallerWin64)
3387 SmallVector<CCValAssign, 16> ArgLocs;
3388 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3391 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3392 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3393 if (!ArgLocs[i].isRegLoc())
3397 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3398 // stack. Therefore, if it's not used by the call it is not safe to optimize
3399 // this into a sibcall.
3400 bool Unused = false;
3401 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3408 SmallVector<CCValAssign, 16> RVLocs;
3409 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3411 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3412 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3413 CCValAssign &VA = RVLocs[i];
3414 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3419 // If the calling conventions do not match, then we'd better make sure the
3420 // results are returned in the same way as what the caller expects.
3422 SmallVector<CCValAssign, 16> RVLocs1;
3423 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3425 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3427 SmallVector<CCValAssign, 16> RVLocs2;
3428 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3430 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3432 if (RVLocs1.size() != RVLocs2.size())
3434 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3435 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3437 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3439 if (RVLocs1[i].isRegLoc()) {
3440 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3443 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3449 // If the callee takes no arguments then go on to check the results of the
3451 if (!Outs.empty()) {
3452 // Check if stack adjustment is needed. For now, do not do this if any
3453 // argument is passed on the stack.
3454 SmallVector<CCValAssign, 16> ArgLocs;
3455 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3458 // Allocate shadow area for Win64
3460 CCInfo.AllocateStack(32, 8);
3462 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3463 if (CCInfo.getNextStackOffset()) {
3464 MachineFunction &MF = DAG.getMachineFunction();
3465 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3468 // Check if the arguments are already laid out in the right way as
3469 // the caller's fixed stack objects.
3470 MachineFrameInfo *MFI = MF.getFrameInfo();
3471 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3472 const X86InstrInfo *TII =
3473 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3474 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3475 CCValAssign &VA = ArgLocs[i];
3476 SDValue Arg = OutVals[i];
3477 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3478 if (VA.getLocInfo() == CCValAssign::Indirect)
3480 if (!VA.isRegLoc()) {
3481 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3488 // If the tailcall address may be in a register, then make sure it's
3489 // possible to register allocate for it. In 32-bit, the call address can
3490 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3491 // callee-saved registers are restored. These happen to be the same
3492 // registers used to pass 'inreg' arguments so watch out for those.
3493 if (!Subtarget->is64Bit() &&
3494 ((!isa<GlobalAddressSDNode>(Callee) &&
3495 !isa<ExternalSymbolSDNode>(Callee)) ||
3496 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3497 unsigned NumInRegs = 0;
3498 // In PIC we need an extra register to formulate the address computation
3500 unsigned MaxInRegs =
3501 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3503 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3504 CCValAssign &VA = ArgLocs[i];
3507 unsigned Reg = VA.getLocReg();
3510 case X86::EAX: case X86::EDX: case X86::ECX:
3511 if (++NumInRegs == MaxInRegs)
3523 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3524 const TargetLibraryInfo *libInfo) const {
3525 return X86::createFastISel(funcInfo, libInfo);
3528 //===----------------------------------------------------------------------===//
3529 // Other Lowering Hooks
3530 //===----------------------------------------------------------------------===//
3532 static bool MayFoldLoad(SDValue Op) {
3533 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3536 static bool MayFoldIntoStore(SDValue Op) {
3537 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3540 static bool isTargetShuffle(unsigned Opcode) {
3542 default: return false;
3543 case X86ISD::BLENDI:
3544 case X86ISD::PSHUFB:
3545 case X86ISD::PSHUFD:
3546 case X86ISD::PSHUFHW:
3547 case X86ISD::PSHUFLW:
3549 case X86ISD::PALIGNR:
3550 case X86ISD::MOVLHPS:
3551 case X86ISD::MOVLHPD:
3552 case X86ISD::MOVHLPS:
3553 case X86ISD::MOVLPS:
3554 case X86ISD::MOVLPD:
3555 case X86ISD::MOVSHDUP:
3556 case X86ISD::MOVSLDUP:
3557 case X86ISD::MOVDDUP:
3560 case X86ISD::UNPCKL:
3561 case X86ISD::UNPCKH:
3562 case X86ISD::VPERMILPI:
3563 case X86ISD::VPERM2X128:
3564 case X86ISD::VPERMI:
3569 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3570 SDValue V1, SelectionDAG &DAG) {
3572 default: llvm_unreachable("Unknown x86 shuffle node");
3573 case X86ISD::MOVSHDUP:
3574 case X86ISD::MOVSLDUP:
3575 case X86ISD::MOVDDUP:
3576 return DAG.getNode(Opc, dl, VT, V1);
3580 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3581 SDValue V1, unsigned TargetMask,
3582 SelectionDAG &DAG) {
3584 default: llvm_unreachable("Unknown x86 shuffle node");
3585 case X86ISD::PSHUFD:
3586 case X86ISD::PSHUFHW:
3587 case X86ISD::PSHUFLW:
3588 case X86ISD::VPERMILPI:
3589 case X86ISD::VPERMI:
3590 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3594 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3595 SDValue V1, SDValue V2, unsigned TargetMask,
3596 SelectionDAG &DAG) {
3598 default: llvm_unreachable("Unknown x86 shuffle node");
3599 case X86ISD::PALIGNR:
3600 case X86ISD::VALIGN:
3602 case X86ISD::VPERM2X128:
3603 return DAG.getNode(Opc, dl, VT, V1, V2,
3604 DAG.getConstant(TargetMask, MVT::i8));
3608 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3609 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3611 default: llvm_unreachable("Unknown x86 shuffle node");
3612 case X86ISD::MOVLHPS:
3613 case X86ISD::MOVLHPD:
3614 case X86ISD::MOVHLPS:
3615 case X86ISD::MOVLPS:
3616 case X86ISD::MOVLPD:
3619 case X86ISD::UNPCKL:
3620 case X86ISD::UNPCKH:
3621 return DAG.getNode(Opc, dl, VT, V1, V2);
3625 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3626 MachineFunction &MF = DAG.getMachineFunction();
3627 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3628 DAG.getSubtarget().getRegisterInfo());
3629 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3630 int ReturnAddrIndex = FuncInfo->getRAIndex();
3632 if (ReturnAddrIndex == 0) {
3633 // Set up a frame object for the return address.
3634 unsigned SlotSize = RegInfo->getSlotSize();
3635 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3638 FuncInfo->setRAIndex(ReturnAddrIndex);
3641 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3644 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3645 bool hasSymbolicDisplacement) {
3646 // Offset should fit into 32 bit immediate field.
3647 if (!isInt<32>(Offset))
3650 // If we don't have a symbolic displacement - we don't have any extra
3652 if (!hasSymbolicDisplacement)
3655 // FIXME: Some tweaks might be needed for medium code model.
3656 if (M != CodeModel::Small && M != CodeModel::Kernel)
3659 // For small code model we assume that latest object is 16MB before end of 31
3660 // bits boundary. We may also accept pretty large negative constants knowing
3661 // that all objects are in the positive half of address space.
3662 if (M == CodeModel::Small && Offset < 16*1024*1024)
3665 // For kernel code model we know that all object resist in the negative half
3666 // of 32bits address space. We may not accept negative offsets, since they may
3667 // be just off and we may accept pretty large positive ones.
3668 if (M == CodeModel::Kernel && Offset > 0)
3674 /// isCalleePop - Determines whether the callee is required to pop its
3675 /// own arguments. Callee pop is necessary to support tail calls.
3676 bool X86::isCalleePop(CallingConv::ID CallingConv,
3677 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3678 switch (CallingConv) {
3681 case CallingConv::X86_StdCall:
3682 case CallingConv::X86_FastCall:
3683 case CallingConv::X86_ThisCall:
3685 case CallingConv::Fast:
3686 case CallingConv::GHC:
3687 case CallingConv::HiPE:
3694 /// \brief Return true if the condition is an unsigned comparison operation.
3695 static bool isX86CCUnsigned(unsigned X86CC) {
3697 default: llvm_unreachable("Invalid integer condition!");
3698 case X86::COND_E: return true;
3699 case X86::COND_G: return false;
3700 case X86::COND_GE: return false;
3701 case X86::COND_L: return false;
3702 case X86::COND_LE: return false;
3703 case X86::COND_NE: return true;
3704 case X86::COND_B: return true;
3705 case X86::COND_A: return true;
3706 case X86::COND_BE: return true;
3707 case X86::COND_AE: return true;
3709 llvm_unreachable("covered switch fell through?!");
3712 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3713 /// specific condition code, returning the condition code and the LHS/RHS of the
3714 /// comparison to make.
3715 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3716 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3718 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3719 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3720 // X > -1 -> X == 0, jump !sign.
3721 RHS = DAG.getConstant(0, RHS.getValueType());
3722 return X86::COND_NS;
3724 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3725 // X < 0 -> X == 0, jump on sign.
3728 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3730 RHS = DAG.getConstant(0, RHS.getValueType());
3731 return X86::COND_LE;
3735 switch (SetCCOpcode) {
3736 default: llvm_unreachable("Invalid integer condition!");
3737 case ISD::SETEQ: return X86::COND_E;
3738 case ISD::SETGT: return X86::COND_G;
3739 case ISD::SETGE: return X86::COND_GE;
3740 case ISD::SETLT: return X86::COND_L;
3741 case ISD::SETLE: return X86::COND_LE;
3742 case ISD::SETNE: return X86::COND_NE;
3743 case ISD::SETULT: return X86::COND_B;
3744 case ISD::SETUGT: return X86::COND_A;
3745 case ISD::SETULE: return X86::COND_BE;
3746 case ISD::SETUGE: return X86::COND_AE;
3750 // First determine if it is required or is profitable to flip the operands.
3752 // If LHS is a foldable load, but RHS is not, flip the condition.
3753 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3754 !ISD::isNON_EXTLoad(RHS.getNode())) {
3755 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3756 std::swap(LHS, RHS);
3759 switch (SetCCOpcode) {
3765 std::swap(LHS, RHS);
3769 // On a floating point condition, the flags are set as follows:
3771 // 0 | 0 | 0 | X > Y
3772 // 0 | 0 | 1 | X < Y
3773 // 1 | 0 | 0 | X == Y
3774 // 1 | 1 | 1 | unordered
3775 switch (SetCCOpcode) {
3776 default: llvm_unreachable("Condcode should be pre-legalized away");
3778 case ISD::SETEQ: return X86::COND_E;
3779 case ISD::SETOLT: // flipped
3781 case ISD::SETGT: return X86::COND_A;
3782 case ISD::SETOLE: // flipped
3784 case ISD::SETGE: return X86::COND_AE;
3785 case ISD::SETUGT: // flipped
3787 case ISD::SETLT: return X86::COND_B;
3788 case ISD::SETUGE: // flipped
3790 case ISD::SETLE: return X86::COND_BE;
3792 case ISD::SETNE: return X86::COND_NE;
3793 case ISD::SETUO: return X86::COND_P;
3794 case ISD::SETO: return X86::COND_NP;
3796 case ISD::SETUNE: return X86::COND_INVALID;
3800 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3801 /// code. Current x86 isa includes the following FP cmov instructions:
3802 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3803 static bool hasFPCMov(unsigned X86CC) {
3819 /// isFPImmLegal - Returns true if the target can instruction select the
3820 /// specified FP immediate natively. If false, the legalizer will
3821 /// materialize the FP immediate as a load from a constant pool.
3822 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3823 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3824 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3830 /// \brief Returns true if it is beneficial to convert a load of a constant
3831 /// to just the constant itself.
3832 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3834 assert(Ty->isIntegerTy());
3836 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3837 if (BitSize == 0 || BitSize > 64)
3842 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3843 /// the specified range (L, H].
3844 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3845 return (Val < 0) || (Val >= Low && Val < Hi);
3848 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3849 /// specified value.
3850 static bool isUndefOrEqual(int Val, int CmpVal) {
3851 return (Val < 0 || Val == CmpVal);
3854 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3855 /// from position Pos and ending in Pos+Size, falls within the specified
3856 /// sequential range (L, L+Pos]. or is undef.
3857 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3858 unsigned Pos, unsigned Size, int Low) {
3859 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3860 if (!isUndefOrEqual(Mask[i], Low))
3865 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3866 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3867 /// the second operand.
3868 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3869 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3870 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3871 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3872 return (Mask[0] < 2 && Mask[1] < 2);
3876 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3877 /// is suitable for input to PSHUFHW.
3878 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3879 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3882 // Lower quadword copied in order or undef.
3883 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3886 // Upper quadword shuffled.
3887 for (unsigned i = 4; i != 8; ++i)
3888 if (!isUndefOrInRange(Mask[i], 4, 8))
3891 if (VT == MVT::v16i16) {
3892 // Lower quadword copied in order or undef.
3893 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3896 // Upper quadword shuffled.
3897 for (unsigned i = 12; i != 16; ++i)
3898 if (!isUndefOrInRange(Mask[i], 12, 16))
3905 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3906 /// is suitable for input to PSHUFLW.
3907 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3908 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3911 // Upper quadword copied in order.
3912 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3915 // Lower quadword shuffled.
3916 for (unsigned i = 0; i != 4; ++i)
3917 if (!isUndefOrInRange(Mask[i], 0, 4))
3920 if (VT == MVT::v16i16) {
3921 // Upper quadword copied in order.
3922 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3925 // Lower quadword shuffled.
3926 for (unsigned i = 8; i != 12; ++i)
3927 if (!isUndefOrInRange(Mask[i], 8, 12))
3934 /// \brief Return true if the mask specifies a shuffle of elements that is
3935 /// suitable for input to intralane (palignr) or interlane (valign) vector
3937 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3938 unsigned NumElts = VT.getVectorNumElements();
3939 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3940 unsigned NumLaneElts = NumElts/NumLanes;
3942 // Do not handle 64-bit element shuffles with palignr.
3943 if (NumLaneElts == 2)
3946 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3948 for (i = 0; i != NumLaneElts; ++i) {
3953 // Lane is all undef, go to next lane
3954 if (i == NumLaneElts)
3957 int Start = Mask[i+l];
3959 // Make sure its in this lane in one of the sources
3960 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3961 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3964 // If not lane 0, then we must match lane 0
3965 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3968 // Correct second source to be contiguous with first source
3969 if (Start >= (int)NumElts)
3970 Start -= NumElts - NumLaneElts;
3972 // Make sure we're shifting in the right direction.
3973 if (Start <= (int)(i+l))
3978 // Check the rest of the elements to see if they are consecutive.
3979 for (++i; i != NumLaneElts; ++i) {
3980 int Idx = Mask[i+l];
3982 // Make sure its in this lane
3983 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3984 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3987 // If not lane 0, then we must match lane 0
3988 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3991 if (Idx >= (int)NumElts)
3992 Idx -= NumElts - NumLaneElts;
3994 if (!isUndefOrEqual(Idx, Start+i))
4003 /// \brief Return true if the node specifies a shuffle of elements that is
4004 /// suitable for input to PALIGNR.
4005 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4006 const X86Subtarget *Subtarget) {
4007 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4008 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4009 VT.is512BitVector())
4010 // FIXME: Add AVX512BW.
4013 return isAlignrMask(Mask, VT, false);
4016 /// \brief Return true if the node specifies a shuffle of elements that is
4017 /// suitable for input to VALIGN.
4018 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4019 const X86Subtarget *Subtarget) {
4020 // FIXME: Add AVX512VL.
4021 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4023 return isAlignrMask(Mask, VT, true);
4026 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4027 /// the two vector operands have swapped position.
4028 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4029 unsigned NumElems) {
4030 for (unsigned i = 0; i != NumElems; ++i) {
4034 else if (idx < (int)NumElems)
4035 Mask[i] = idx + NumElems;
4037 Mask[i] = idx - NumElems;
4041 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4042 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4043 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4044 /// reverse of what x86 shuffles want.
4045 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4047 unsigned NumElems = VT.getVectorNumElements();
4048 unsigned NumLanes = VT.getSizeInBits()/128;
4049 unsigned NumLaneElems = NumElems/NumLanes;
4051 if (NumLaneElems != 2 && NumLaneElems != 4)
4054 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4055 bool symetricMaskRequired =
4056 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4058 // VSHUFPSY divides the resulting vector into 4 chunks.
4059 // The sources are also splitted into 4 chunks, and each destination
4060 // chunk must come from a different source chunk.
4062 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4063 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4065 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4066 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4068 // VSHUFPDY divides the resulting vector into 4 chunks.
4069 // The sources are also splitted into 4 chunks, and each destination
4070 // chunk must come from a different source chunk.
4072 // SRC1 => X3 X2 X1 X0
4073 // SRC2 => Y3 Y2 Y1 Y0
4075 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4077 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4078 unsigned HalfLaneElems = NumLaneElems/2;
4079 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4080 for (unsigned i = 0; i != NumLaneElems; ++i) {
4081 int Idx = Mask[i+l];
4082 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4083 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4085 // For VSHUFPSY, the mask of the second half must be the same as the
4086 // first but with the appropriate offsets. This works in the same way as
4087 // VPERMILPS works with masks.
4088 if (!symetricMaskRequired || Idx < 0)
4090 if (MaskVal[i] < 0) {
4091 MaskVal[i] = Idx - l;
4094 if ((signed)(Idx - l) != MaskVal[i])
4102 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4103 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4104 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4105 if (!VT.is128BitVector())
4108 unsigned NumElems = VT.getVectorNumElements();
4113 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4114 return isUndefOrEqual(Mask[0], 6) &&
4115 isUndefOrEqual(Mask[1], 7) &&
4116 isUndefOrEqual(Mask[2], 2) &&
4117 isUndefOrEqual(Mask[3], 3);
4120 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4121 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4123 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4124 if (!VT.is128BitVector())
4127 unsigned NumElems = VT.getVectorNumElements();
4132 return isUndefOrEqual(Mask[0], 2) &&
4133 isUndefOrEqual(Mask[1], 3) &&
4134 isUndefOrEqual(Mask[2], 2) &&
4135 isUndefOrEqual(Mask[3], 3);
4138 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4139 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4140 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4141 if (!VT.is128BitVector())
4144 unsigned NumElems = VT.getVectorNumElements();
4146 if (NumElems != 2 && NumElems != 4)
4149 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4150 if (!isUndefOrEqual(Mask[i], i + NumElems))
4153 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4154 if (!isUndefOrEqual(Mask[i], i))
4160 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4161 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4162 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4163 if (!VT.is128BitVector())
4166 unsigned NumElems = VT.getVectorNumElements();
4168 if (NumElems != 2 && NumElems != 4)
4171 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4172 if (!isUndefOrEqual(Mask[i], i))
4175 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4176 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4182 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4183 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4184 /// i. e: If all but one element come from the same vector.
4185 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4186 // TODO: Deal with AVX's VINSERTPS
4187 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4190 unsigned CorrectPosV1 = 0;
4191 unsigned CorrectPosV2 = 0;
4192 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4193 if (Mask[i] == -1) {
4201 else if (Mask[i] == i + 4)
4205 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4206 // We have 3 elements (undefs count as elements from any vector) from one
4207 // vector, and one from another.
4214 // Some special combinations that can be optimized.
4217 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4218 SelectionDAG &DAG) {
4219 MVT VT = SVOp->getSimpleValueType(0);
4222 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4225 ArrayRef<int> Mask = SVOp->getMask();
4227 // These are the special masks that may be optimized.
4228 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4229 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4230 bool MatchEvenMask = true;
4231 bool MatchOddMask = true;
4232 for (int i=0; i<8; ++i) {
4233 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4234 MatchEvenMask = false;
4235 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4236 MatchOddMask = false;
4239 if (!MatchEvenMask && !MatchOddMask)
4242 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4244 SDValue Op0 = SVOp->getOperand(0);
4245 SDValue Op1 = SVOp->getOperand(1);
4247 if (MatchEvenMask) {
4248 // Shift the second operand right to 32 bits.
4249 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4250 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4252 // Shift the first operand left to 32 bits.
4253 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4254 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4256 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4257 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4260 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4261 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4262 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4263 bool HasInt256, bool V2IsSplat = false) {
4265 assert(VT.getSizeInBits() >= 128 &&
4266 "Unsupported vector type for unpckl");
4268 unsigned NumElts = VT.getVectorNumElements();
4269 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4270 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4273 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4274 "Unsupported vector type for unpckh");
4276 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4277 unsigned NumLanes = VT.getSizeInBits()/128;
4278 unsigned NumLaneElts = NumElts/NumLanes;
4280 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4281 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4282 int BitI = Mask[l+i];
4283 int BitI1 = Mask[l+i+1];
4284 if (!isUndefOrEqual(BitI, j))
4287 if (!isUndefOrEqual(BitI1, NumElts))
4290 if (!isUndefOrEqual(BitI1, j + NumElts))
4299 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4300 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4301 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4302 bool HasInt256, bool V2IsSplat = false) {
4303 assert(VT.getSizeInBits() >= 128 &&
4304 "Unsupported vector type for unpckh");
4306 unsigned NumElts = VT.getVectorNumElements();
4307 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4308 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4311 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4312 "Unsupported vector type for unpckh");
4314 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4315 unsigned NumLanes = VT.getSizeInBits()/128;
4316 unsigned NumLaneElts = NumElts/NumLanes;
4318 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4319 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4320 int BitI = Mask[l+i];
4321 int BitI1 = Mask[l+i+1];
4322 if (!isUndefOrEqual(BitI, j))
4325 if (isUndefOrEqual(BitI1, NumElts))
4328 if (!isUndefOrEqual(BitI1, j+NumElts))
4336 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4337 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4339 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4340 unsigned NumElts = VT.getVectorNumElements();
4341 bool Is256BitVec = VT.is256BitVector();
4343 if (VT.is512BitVector())
4345 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4346 "Unsupported vector type for unpckh");
4348 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4349 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4352 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4353 // FIXME: Need a better way to get rid of this, there's no latency difference
4354 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4355 // the former later. We should also remove the "_undef" special mask.
4356 if (NumElts == 4 && Is256BitVec)
4359 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4360 // independently on 128-bit lanes.
4361 unsigned NumLanes = VT.getSizeInBits()/128;
4362 unsigned NumLaneElts = NumElts/NumLanes;
4364 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4365 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4366 int BitI = Mask[l+i];
4367 int BitI1 = Mask[l+i+1];
4369 if (!isUndefOrEqual(BitI, j))
4371 if (!isUndefOrEqual(BitI1, j))
4379 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4380 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4382 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4383 unsigned NumElts = VT.getVectorNumElements();
4385 if (VT.is512BitVector())
4388 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4389 "Unsupported vector type for unpckh");
4391 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4392 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4395 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4396 // independently on 128-bit lanes.
4397 unsigned NumLanes = VT.getSizeInBits()/128;
4398 unsigned NumLaneElts = NumElts/NumLanes;
4400 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4401 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4402 int BitI = Mask[l+i];
4403 int BitI1 = Mask[l+i+1];
4404 if (!isUndefOrEqual(BitI, j))
4406 if (!isUndefOrEqual(BitI1, j))
4413 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4414 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4415 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4416 if (!VT.is512BitVector())
4419 unsigned NumElts = VT.getVectorNumElements();
4420 unsigned HalfSize = NumElts/2;
4421 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4422 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4427 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4428 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4436 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4437 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4438 /// MOVSD, and MOVD, i.e. setting the lowest element.
4439 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4440 if (VT.getVectorElementType().getSizeInBits() < 32)
4442 if (!VT.is128BitVector())
4445 unsigned NumElts = VT.getVectorNumElements();
4447 if (!isUndefOrEqual(Mask[0], NumElts))
4450 for (unsigned i = 1; i != NumElts; ++i)
4451 if (!isUndefOrEqual(Mask[i], i))
4457 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4458 /// as permutations between 128-bit chunks or halves. As an example: this
4460 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4461 /// The first half comes from the second half of V1 and the second half from the
4462 /// the second half of V2.
4463 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4464 if (!HasFp256 || !VT.is256BitVector())
4467 // The shuffle result is divided into half A and half B. In total the two
4468 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4469 // B must come from C, D, E or F.
4470 unsigned HalfSize = VT.getVectorNumElements()/2;
4471 bool MatchA = false, MatchB = false;
4473 // Check if A comes from one of C, D, E, F.
4474 for (unsigned Half = 0; Half != 4; ++Half) {
4475 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4481 // Check if B comes from one of C, D, E, F.
4482 for (unsigned Half = 0; Half != 4; ++Half) {
4483 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4489 return MatchA && MatchB;
4492 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4493 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4494 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4495 MVT VT = SVOp->getSimpleValueType(0);
4497 unsigned HalfSize = VT.getVectorNumElements()/2;
4499 unsigned FstHalf = 0, SndHalf = 0;
4500 for (unsigned i = 0; i < HalfSize; ++i) {
4501 if (SVOp->getMaskElt(i) > 0) {
4502 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4506 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4507 if (SVOp->getMaskElt(i) > 0) {
4508 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4513 return (FstHalf | (SndHalf << 4));
4516 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4517 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4518 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4522 unsigned NumElts = VT.getVectorNumElements();
4524 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4525 for (unsigned i = 0; i != NumElts; ++i) {
4528 Imm8 |= Mask[i] << (i*2);
4533 unsigned LaneSize = 4;
4534 SmallVector<int, 4> MaskVal(LaneSize, -1);
4536 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4537 for (unsigned i = 0; i != LaneSize; ++i) {
4538 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4542 if (MaskVal[i] < 0) {
4543 MaskVal[i] = Mask[i+l] - l;
4544 Imm8 |= MaskVal[i] << (i*2);
4547 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4554 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4555 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4556 /// Note that VPERMIL mask matching is different depending whether theunderlying
4557 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4558 /// to the same elements of the low, but to the higher half of the source.
4559 /// In VPERMILPD the two lanes could be shuffled independently of each other
4560 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4561 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4562 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4563 if (VT.getSizeInBits() < 256 || EltSize < 32)
4565 bool symetricMaskRequired = (EltSize == 32);
4566 unsigned NumElts = VT.getVectorNumElements();
4568 unsigned NumLanes = VT.getSizeInBits()/128;
4569 unsigned LaneSize = NumElts/NumLanes;
4570 // 2 or 4 elements in one lane
4572 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4573 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4574 for (unsigned i = 0; i != LaneSize; ++i) {
4575 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4577 if (symetricMaskRequired) {
4578 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4579 ExpectedMaskVal[i] = Mask[i+l] - l;
4582 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4590 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4591 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4592 /// element of vector 2 and the other elements to come from vector 1 in order.
4593 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4594 bool V2IsSplat = false, bool V2IsUndef = false) {
4595 if (!VT.is128BitVector())
4598 unsigned NumOps = VT.getVectorNumElements();
4599 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4602 if (!isUndefOrEqual(Mask[0], 0))
4605 for (unsigned i = 1; i != NumOps; ++i)
4606 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4607 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4608 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4614 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4615 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4616 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4617 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4618 const X86Subtarget *Subtarget) {
4619 if (!Subtarget->hasSSE3())
4622 unsigned NumElems = VT.getVectorNumElements();
4624 if ((VT.is128BitVector() && NumElems != 4) ||
4625 (VT.is256BitVector() && NumElems != 8) ||
4626 (VT.is512BitVector() && NumElems != 16))
4629 // "i+1" is the value the indexed mask element must have
4630 for (unsigned i = 0; i != NumElems; i += 2)
4631 if (!isUndefOrEqual(Mask[i], i+1) ||
4632 !isUndefOrEqual(Mask[i+1], i+1))
4638 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4639 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4640 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4641 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4642 const X86Subtarget *Subtarget) {
4643 if (!Subtarget->hasSSE3())
4646 unsigned NumElems = VT.getVectorNumElements();
4648 if ((VT.is128BitVector() && NumElems != 4) ||
4649 (VT.is256BitVector() && NumElems != 8) ||
4650 (VT.is512BitVector() && NumElems != 16))
4653 // "i" is the value the indexed mask element must have
4654 for (unsigned i = 0; i != NumElems; i += 2)
4655 if (!isUndefOrEqual(Mask[i], i) ||
4656 !isUndefOrEqual(Mask[i+1], i))
4662 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4663 /// specifies a shuffle of elements that is suitable for input to 256-bit
4664 /// version of MOVDDUP.
4665 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4666 if (!HasFp256 || !VT.is256BitVector())
4669 unsigned NumElts = VT.getVectorNumElements();
4673 for (unsigned i = 0; i != NumElts/2; ++i)
4674 if (!isUndefOrEqual(Mask[i], 0))
4676 for (unsigned i = NumElts/2; i != NumElts; ++i)
4677 if (!isUndefOrEqual(Mask[i], NumElts/2))
4682 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4683 /// specifies a shuffle of elements that is suitable for input to 128-bit
4684 /// version of MOVDDUP.
4685 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4686 if (!VT.is128BitVector())
4689 unsigned e = VT.getVectorNumElements() / 2;
4690 for (unsigned i = 0; i != e; ++i)
4691 if (!isUndefOrEqual(Mask[i], i))
4693 for (unsigned i = 0; i != e; ++i)
4694 if (!isUndefOrEqual(Mask[e+i], i))
4699 /// isVEXTRACTIndex - Return true if the specified
4700 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4701 /// suitable for instruction that extract 128 or 256 bit vectors
4702 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4703 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4704 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4707 // The index should be aligned on a vecWidth-bit boundary.
4709 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4711 MVT VT = N->getSimpleValueType(0);
4712 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4713 bool Result = (Index * ElSize) % vecWidth == 0;
4718 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4719 /// operand specifies a subvector insert that is suitable for input to
4720 /// insertion of 128 or 256-bit subvectors
4721 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4722 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4723 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4725 // The index should be aligned on a vecWidth-bit boundary.
4727 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4729 MVT VT = N->getSimpleValueType(0);
4730 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4731 bool Result = (Index * ElSize) % vecWidth == 0;
4736 bool X86::isVINSERT128Index(SDNode *N) {
4737 return isVINSERTIndex(N, 128);
4740 bool X86::isVINSERT256Index(SDNode *N) {
4741 return isVINSERTIndex(N, 256);
4744 bool X86::isVEXTRACT128Index(SDNode *N) {
4745 return isVEXTRACTIndex(N, 128);
4748 bool X86::isVEXTRACT256Index(SDNode *N) {
4749 return isVEXTRACTIndex(N, 256);
4752 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4753 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4754 /// Handles 128-bit and 256-bit.
4755 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4756 MVT VT = N->getSimpleValueType(0);
4758 assert((VT.getSizeInBits() >= 128) &&
4759 "Unsupported vector type for PSHUF/SHUFP");
4761 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4762 // independently on 128-bit lanes.
4763 unsigned NumElts = VT.getVectorNumElements();
4764 unsigned NumLanes = VT.getSizeInBits()/128;
4765 unsigned NumLaneElts = NumElts/NumLanes;
4767 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4768 "Only supports 2, 4 or 8 elements per lane");
4770 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4772 for (unsigned i = 0; i != NumElts; ++i) {
4773 int Elt = N->getMaskElt(i);
4774 if (Elt < 0) continue;
4775 Elt &= NumLaneElts - 1;
4776 unsigned ShAmt = (i << Shift) % 8;
4777 Mask |= Elt << ShAmt;
4783 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4784 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4785 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4786 MVT VT = N->getSimpleValueType(0);
4788 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4789 "Unsupported vector type for PSHUFHW");
4791 unsigned NumElts = VT.getVectorNumElements();
4794 for (unsigned l = 0; l != NumElts; l += 8) {
4795 // 8 nodes per lane, but we only care about the last 4.
4796 for (unsigned i = 0; i < 4; ++i) {
4797 int Elt = N->getMaskElt(l+i+4);
4798 if (Elt < 0) continue;
4799 Elt &= 0x3; // only 2-bits.
4800 Mask |= Elt << (i * 2);
4807 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4808 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4809 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4810 MVT VT = N->getSimpleValueType(0);
4812 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4813 "Unsupported vector type for PSHUFHW");
4815 unsigned NumElts = VT.getVectorNumElements();
4818 for (unsigned l = 0; l != NumElts; l += 8) {
4819 // 8 nodes per lane, but we only care about the first 4.
4820 for (unsigned i = 0; i < 4; ++i) {
4821 int Elt = N->getMaskElt(l+i);
4822 if (Elt < 0) continue;
4823 Elt &= 0x3; // only 2-bits
4824 Mask |= Elt << (i * 2);
4831 /// \brief Return the appropriate immediate to shuffle the specified
4832 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4833 /// VALIGN (if Interlane is true) instructions.
4834 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4836 MVT VT = SVOp->getSimpleValueType(0);
4837 unsigned EltSize = InterLane ? 1 :
4838 VT.getVectorElementType().getSizeInBits() >> 3;
4840 unsigned NumElts = VT.getVectorNumElements();
4841 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4842 unsigned NumLaneElts = NumElts/NumLanes;
4846 for (i = 0; i != NumElts; ++i) {
4847 Val = SVOp->getMaskElt(i);
4851 if (Val >= (int)NumElts)
4852 Val -= NumElts - NumLaneElts;
4854 assert(Val - i > 0 && "PALIGNR imm should be positive");
4855 return (Val - i) * EltSize;
4858 /// \brief Return the appropriate immediate to shuffle the specified
4859 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4860 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4861 return getShuffleAlignrImmediate(SVOp, false);
4864 /// \brief Return the appropriate immediate to shuffle the specified
4865 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4866 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4867 return getShuffleAlignrImmediate(SVOp, true);
4871 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4872 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4873 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4874 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4877 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4879 MVT VecVT = N->getOperand(0).getSimpleValueType();
4880 MVT ElVT = VecVT.getVectorElementType();
4882 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4883 return Index / NumElemsPerChunk;
4886 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4887 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4888 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4889 llvm_unreachable("Illegal insert subvector for VINSERT");
4892 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4894 MVT VecVT = N->getSimpleValueType(0);
4895 MVT ElVT = VecVT.getVectorElementType();
4897 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4898 return Index / NumElemsPerChunk;
4901 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4902 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4903 /// and VINSERTI128 instructions.
4904 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4905 return getExtractVEXTRACTImmediate(N, 128);
4908 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4909 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4910 /// and VINSERTI64x4 instructions.
4911 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4912 return getExtractVEXTRACTImmediate(N, 256);
4915 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4916 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4917 /// and VINSERTI128 instructions.
4918 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4919 return getInsertVINSERTImmediate(N, 128);
4922 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4923 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4924 /// and VINSERTI64x4 instructions.
4925 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4926 return getInsertVINSERTImmediate(N, 256);
4929 /// isZero - Returns true if Elt is a constant integer zero
4930 static bool isZero(SDValue V) {
4931 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4932 return C && C->isNullValue();
4935 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4937 bool X86::isZeroNode(SDValue Elt) {
4940 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4941 return CFP->getValueAPF().isPosZero();
4945 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4946 /// match movhlps. The lower half elements should come from upper half of
4947 /// V1 (and in order), and the upper half elements should come from the upper
4948 /// half of V2 (and in order).
4949 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4950 if (!VT.is128BitVector())
4952 if (VT.getVectorNumElements() != 4)
4954 for (unsigned i = 0, e = 2; i != e; ++i)
4955 if (!isUndefOrEqual(Mask[i], i+2))
4957 for (unsigned i = 2; i != 4; ++i)
4958 if (!isUndefOrEqual(Mask[i], i+4))
4963 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4964 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4966 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4967 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4969 N = N->getOperand(0).getNode();
4970 if (!ISD::isNON_EXTLoad(N))
4973 *LD = cast<LoadSDNode>(N);
4977 // Test whether the given value is a vector value which will be legalized
4979 static bool WillBeConstantPoolLoad(SDNode *N) {
4980 if (N->getOpcode() != ISD::BUILD_VECTOR)
4983 // Check for any non-constant elements.
4984 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4985 switch (N->getOperand(i).getNode()->getOpcode()) {
4987 case ISD::ConstantFP:
4994 // Vectors of all-zeros and all-ones are materialized with special
4995 // instructions rather than being loaded.
4996 return !ISD::isBuildVectorAllZeros(N) &&
4997 !ISD::isBuildVectorAllOnes(N);
5000 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5001 /// match movlp{s|d}. The lower half elements should come from lower half of
5002 /// V1 (and in order), and the upper half elements should come from the upper
5003 /// half of V2 (and in order). And since V1 will become the source of the
5004 /// MOVLP, it must be either a vector load or a scalar load to vector.
5005 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5006 ArrayRef<int> Mask, MVT VT) {
5007 if (!VT.is128BitVector())
5010 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5012 // Is V2 is a vector load, don't do this transformation. We will try to use
5013 // load folding shufps op.
5014 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5017 unsigned NumElems = VT.getVectorNumElements();
5019 if (NumElems != 2 && NumElems != 4)
5021 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5022 if (!isUndefOrEqual(Mask[i], i))
5024 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5025 if (!isUndefOrEqual(Mask[i], i+NumElems))
5030 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5031 /// to an zero vector.
5032 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5033 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5034 SDValue V1 = N->getOperand(0);
5035 SDValue V2 = N->getOperand(1);
5036 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5037 for (unsigned i = 0; i != NumElems; ++i) {
5038 int Idx = N->getMaskElt(i);
5039 if (Idx >= (int)NumElems) {
5040 unsigned Opc = V2.getOpcode();
5041 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5043 if (Opc != ISD::BUILD_VECTOR ||
5044 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5046 } else if (Idx >= 0) {
5047 unsigned Opc = V1.getOpcode();
5048 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5050 if (Opc != ISD::BUILD_VECTOR ||
5051 !X86::isZeroNode(V1.getOperand(Idx)))
5058 /// getZeroVector - Returns a vector of specified type with all zero elements.
5060 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5061 SelectionDAG &DAG, SDLoc dl) {
5062 assert(VT.isVector() && "Expected a vector type");
5064 // Always build SSE zero vectors as <4 x i32> bitcasted
5065 // to their dest type. This ensures they get CSE'd.
5067 if (VT.is128BitVector()) { // SSE
5068 if (Subtarget->hasSSE2()) { // SSE2
5069 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5070 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5072 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5073 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5075 } else if (VT.is256BitVector()) { // AVX
5076 if (Subtarget->hasInt256()) { // AVX2
5077 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5078 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5079 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5081 // 256-bit logic and arithmetic instructions in AVX are all
5082 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5083 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
5084 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5085 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5087 } else if (VT.is512BitVector()) { // AVX-512
5088 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
5089 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5090 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5091 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5092 } else if (VT.getScalarType() == MVT::i1) {
5093 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5094 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5095 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5096 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5098 llvm_unreachable("Unexpected vector type");
5100 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5103 /// getOnesVector - Returns a vector of specified type with all bits set.
5104 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5105 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5106 /// Then bitcast to their original type, ensuring they get CSE'd.
5107 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5109 assert(VT.isVector() && "Expected a vector type");
5111 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
5113 if (VT.is256BitVector()) {
5114 if (HasInt256) { // AVX2
5115 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5116 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5118 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5119 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5121 } else if (VT.is128BitVector()) {
5122 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5124 llvm_unreachable("Unexpected vector type");
5126 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5129 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5130 /// that point to V2 points to its first element.
5131 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5132 for (unsigned i = 0; i != NumElems; ++i) {
5133 if (Mask[i] > (int)NumElems) {
5139 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5140 /// operation of specified width.
5141 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5143 unsigned NumElems = VT.getVectorNumElements();
5144 SmallVector<int, 8> Mask;
5145 Mask.push_back(NumElems);
5146 for (unsigned i = 1; i != NumElems; ++i)
5148 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5151 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5152 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5154 unsigned NumElems = VT.getVectorNumElements();
5155 SmallVector<int, 8> Mask;
5156 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5158 Mask.push_back(i + NumElems);
5160 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5163 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5164 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5166 unsigned NumElems = VT.getVectorNumElements();
5167 SmallVector<int, 8> Mask;
5168 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5169 Mask.push_back(i + Half);
5170 Mask.push_back(i + NumElems + Half);
5172 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5175 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5176 // a generic shuffle instruction because the target has no such instructions.
5177 // Generate shuffles which repeat i16 and i8 several times until they can be
5178 // represented by v4f32 and then be manipulated by target suported shuffles.
5179 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5180 MVT VT = V.getSimpleValueType();
5181 int NumElems = VT.getVectorNumElements();
5184 while (NumElems > 4) {
5185 if (EltNo < NumElems/2) {
5186 V = getUnpackl(DAG, dl, VT, V, V);
5188 V = getUnpackh(DAG, dl, VT, V, V);
5189 EltNo -= NumElems/2;
5196 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5197 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5198 MVT VT = V.getSimpleValueType();
5201 if (VT.is128BitVector()) {
5202 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5203 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5204 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5206 } else if (VT.is256BitVector()) {
5207 // To use VPERMILPS to splat scalars, the second half of indicies must
5208 // refer to the higher part, which is a duplication of the lower one,
5209 // because VPERMILPS can only handle in-lane permutations.
5210 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5211 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5213 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5214 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5217 llvm_unreachable("Vector size not supported");
5219 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5222 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5223 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5224 MVT SrcVT = SV->getSimpleValueType(0);
5225 SDValue V1 = SV->getOperand(0);
5228 int EltNo = SV->getSplatIndex();
5229 int NumElems = SrcVT.getVectorNumElements();
5230 bool Is256BitVec = SrcVT.is256BitVector();
5232 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5233 "Unknown how to promote splat for type");
5235 // Extract the 128-bit part containing the splat element and update
5236 // the splat element index when it refers to the higher register.
5238 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5239 if (EltNo >= NumElems/2)
5240 EltNo -= NumElems/2;
5243 // All i16 and i8 vector types can't be used directly by a generic shuffle
5244 // instruction because the target has no such instruction. Generate shuffles
5245 // which repeat i16 and i8 several times until they fit in i32, and then can
5246 // be manipulated by target suported shuffles.
5247 MVT EltVT = SrcVT.getVectorElementType();
5248 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5249 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5251 // Recreate the 256-bit vector and place the same 128-bit vector
5252 // into the low and high part. This is necessary because we want
5253 // to use VPERM* to shuffle the vectors
5255 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5258 return getLegalSplat(DAG, V1, EltNo);
5261 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5262 /// vector of zero or undef vector. This produces a shuffle where the low
5263 /// element of V2 is swizzled into the zero/undef vector, landing at element
5264 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5265 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5267 const X86Subtarget *Subtarget,
5268 SelectionDAG &DAG) {
5269 MVT VT = V2.getSimpleValueType();
5271 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5272 unsigned NumElems = VT.getVectorNumElements();
5273 SmallVector<int, 16> MaskVec;
5274 for (unsigned i = 0; i != NumElems; ++i)
5275 // If this is the insertion idx, put the low elt of V2 here.
5276 MaskVec.push_back(i == Idx ? NumElems : i);
5277 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5280 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5281 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5282 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5283 /// shuffles which use a single input multiple times, and in those cases it will
5284 /// adjust the mask to only have indices within that single input.
5285 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5286 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5287 unsigned NumElems = VT.getVectorNumElements();
5291 bool IsFakeUnary = false;
5292 switch(N->getOpcode()) {
5293 case X86ISD::BLENDI:
5294 ImmN = N->getOperand(N->getNumOperands()-1);
5295 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5298 ImmN = N->getOperand(N->getNumOperands()-1);
5299 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5300 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5302 case X86ISD::UNPCKH:
5303 DecodeUNPCKHMask(VT, Mask);
5304 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5306 case X86ISD::UNPCKL:
5307 DecodeUNPCKLMask(VT, Mask);
5308 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5310 case X86ISD::MOVHLPS:
5311 DecodeMOVHLPSMask(NumElems, Mask);
5312 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5314 case X86ISD::MOVLHPS:
5315 DecodeMOVLHPSMask(NumElems, Mask);
5316 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5318 case X86ISD::PALIGNR:
5319 ImmN = N->getOperand(N->getNumOperands()-1);
5320 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5322 case X86ISD::PSHUFD:
5323 case X86ISD::VPERMILPI:
5324 ImmN = N->getOperand(N->getNumOperands()-1);
5325 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5328 case X86ISD::PSHUFHW:
5329 ImmN = N->getOperand(N->getNumOperands()-1);
5330 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5333 case X86ISD::PSHUFLW:
5334 ImmN = N->getOperand(N->getNumOperands()-1);
5335 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5338 case X86ISD::PSHUFB: {
5340 SDValue MaskNode = N->getOperand(1);
5341 while (MaskNode->getOpcode() == ISD::BITCAST)
5342 MaskNode = MaskNode->getOperand(0);
5344 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5345 // If we have a build-vector, then things are easy.
5346 EVT VT = MaskNode.getValueType();
5347 assert(VT.isVector() &&
5348 "Can't produce a non-vector with a build_vector!");
5349 if (!VT.isInteger())
5352 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5354 SmallVector<uint64_t, 32> RawMask;
5355 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5356 SDValue Op = MaskNode->getOperand(i);
5357 if (Op->getOpcode() == ISD::UNDEF) {
5358 RawMask.push_back((uint64_t)SM_SentinelUndef);
5361 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5364 APInt MaskElement = CN->getAPIntValue();
5366 // We now have to decode the element which could be any integer size and
5367 // extract each byte of it.
5368 for (int j = 0; j < NumBytesPerElement; ++j) {
5369 // Note that this is x86 and so always little endian: the low byte is
5370 // the first byte of the mask.
5371 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5372 MaskElement = MaskElement.lshr(8);
5375 DecodePSHUFBMask(RawMask, Mask);
5379 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5383 SDValue Ptr = MaskLoad->getBasePtr();
5384 if (Ptr->getOpcode() == X86ISD::Wrapper)
5385 Ptr = Ptr->getOperand(0);
5387 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5388 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5391 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5392 // FIXME: Support AVX-512 here.
5393 Type *Ty = C->getType();
5394 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5395 Ty->getVectorNumElements() != 32))
5398 DecodePSHUFBMask(C, Mask);
5404 case X86ISD::VPERMI:
5405 ImmN = N->getOperand(N->getNumOperands()-1);
5406 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5410 case X86ISD::MOVSD: {
5411 // The index 0 always comes from the first element of the second source,
5412 // this is why MOVSS and MOVSD are used in the first place. The other
5413 // elements come from the other positions of the first source vector
5414 Mask.push_back(NumElems);
5415 for (unsigned i = 1; i != NumElems; ++i) {
5420 case X86ISD::VPERM2X128:
5421 ImmN = N->getOperand(N->getNumOperands()-1);
5422 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5423 if (Mask.empty()) return false;
5425 case X86ISD::MOVSLDUP:
5426 DecodeMOVSLDUPMask(VT, Mask);
5428 case X86ISD::MOVSHDUP:
5429 DecodeMOVSHDUPMask(VT, Mask);
5431 case X86ISD::MOVDDUP:
5432 case X86ISD::MOVLHPD:
5433 case X86ISD::MOVLPD:
5434 case X86ISD::MOVLPS:
5435 // Not yet implemented
5437 default: llvm_unreachable("unknown target shuffle node");
5440 // If we have a fake unary shuffle, the shuffle mask is spread across two
5441 // inputs that are actually the same node. Re-map the mask to always point
5442 // into the first input.
5445 if (M >= (int)Mask.size())
5451 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5452 /// element of the result of the vector shuffle.
5453 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5456 return SDValue(); // Limit search depth.
5458 SDValue V = SDValue(N, 0);
5459 EVT VT = V.getValueType();
5460 unsigned Opcode = V.getOpcode();
5462 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5463 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5464 int Elt = SV->getMaskElt(Index);
5467 return DAG.getUNDEF(VT.getVectorElementType());
5469 unsigned NumElems = VT.getVectorNumElements();
5470 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5471 : SV->getOperand(1);
5472 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5475 // Recurse into target specific vector shuffles to find scalars.
5476 if (isTargetShuffle(Opcode)) {
5477 MVT ShufVT = V.getSimpleValueType();
5478 unsigned NumElems = ShufVT.getVectorNumElements();
5479 SmallVector<int, 16> ShuffleMask;
5482 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5485 int Elt = ShuffleMask[Index];
5487 return DAG.getUNDEF(ShufVT.getVectorElementType());
5489 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5491 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5495 // Actual nodes that may contain scalar elements
5496 if (Opcode == ISD::BITCAST) {
5497 V = V.getOperand(0);
5498 EVT SrcVT = V.getValueType();
5499 unsigned NumElems = VT.getVectorNumElements();
5501 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5505 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5506 return (Index == 0) ? V.getOperand(0)
5507 : DAG.getUNDEF(VT.getVectorElementType());
5509 if (V.getOpcode() == ISD::BUILD_VECTOR)
5510 return V.getOperand(Index);
5515 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5516 /// shuffle operation which come from a consecutively from a zero. The
5517 /// search can start in two different directions, from left or right.
5518 /// We count undefs as zeros until PreferredNum is reached.
5519 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5520 unsigned NumElems, bool ZerosFromLeft,
5522 unsigned PreferredNum = -1U) {
5523 unsigned NumZeros = 0;
5524 for (unsigned i = 0; i != NumElems; ++i) {
5525 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5526 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5530 if (X86::isZeroNode(Elt))
5532 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5533 NumZeros = std::min(NumZeros + 1, PreferredNum);
5541 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5542 /// correspond consecutively to elements from one of the vector operands,
5543 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5545 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5546 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5547 unsigned NumElems, unsigned &OpNum) {
5548 bool SeenV1 = false;
5549 bool SeenV2 = false;
5551 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5552 int Idx = SVOp->getMaskElt(i);
5553 // Ignore undef indicies
5557 if (Idx < (int)NumElems)
5562 // Only accept consecutive elements from the same vector
5563 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5567 OpNum = SeenV1 ? 0 : 1;
5571 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5572 /// logical left shift of a vector.
5573 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5574 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5576 SVOp->getSimpleValueType(0).getVectorNumElements();
5577 unsigned NumZeros = getNumOfConsecutiveZeros(
5578 SVOp, NumElems, false /* check zeros from right */, DAG,
5579 SVOp->getMaskElt(0));
5585 // Considering the elements in the mask that are not consecutive zeros,
5586 // check if they consecutively come from only one of the source vectors.
5588 // V1 = {X, A, B, C} 0
5590 // vector_shuffle V1, V2 <1, 2, 3, X>
5592 if (!isShuffleMaskConsecutive(SVOp,
5593 0, // Mask Start Index
5594 NumElems-NumZeros, // Mask End Index(exclusive)
5595 NumZeros, // Where to start looking in the src vector
5596 NumElems, // Number of elements in vector
5597 OpSrc)) // Which source operand ?
5602 ShVal = SVOp->getOperand(OpSrc);
5606 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5607 /// logical left shift of a vector.
5608 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5609 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5611 SVOp->getSimpleValueType(0).getVectorNumElements();
5612 unsigned NumZeros = getNumOfConsecutiveZeros(
5613 SVOp, NumElems, true /* check zeros from left */, DAG,
5614 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5620 // Considering the elements in the mask that are not consecutive zeros,
5621 // check if they consecutively come from only one of the source vectors.
5623 // 0 { A, B, X, X } = V2
5625 // vector_shuffle V1, V2 <X, X, 4, 5>
5627 if (!isShuffleMaskConsecutive(SVOp,
5628 NumZeros, // Mask Start Index
5629 NumElems, // Mask End Index(exclusive)
5630 0, // Where to start looking in the src vector
5631 NumElems, // Number of elements in vector
5632 OpSrc)) // Which source operand ?
5637 ShVal = SVOp->getOperand(OpSrc);
5641 /// isVectorShift - Returns true if the shuffle can be implemented as a
5642 /// logical left or right shift of a vector.
5643 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5644 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5645 // Although the logic below support any bitwidth size, there are no
5646 // shift instructions which handle more than 128-bit vectors.
5647 if (!SVOp->getSimpleValueType(0).is128BitVector())
5650 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5651 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5657 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5659 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5660 unsigned NumNonZero, unsigned NumZero,
5662 const X86Subtarget* Subtarget,
5663 const TargetLowering &TLI) {
5670 for (unsigned i = 0; i < 16; ++i) {
5671 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5672 if (ThisIsNonZero && First) {
5674 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5676 V = DAG.getUNDEF(MVT::v8i16);
5681 SDValue ThisElt, LastElt;
5682 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5683 if (LastIsNonZero) {
5684 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5685 MVT::i16, Op.getOperand(i-1));
5687 if (ThisIsNonZero) {
5688 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5689 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5690 ThisElt, DAG.getConstant(8, MVT::i8));
5692 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5696 if (ThisElt.getNode())
5697 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5698 DAG.getIntPtrConstant(i/2));
5702 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5705 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5707 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5708 unsigned NumNonZero, unsigned NumZero,
5710 const X86Subtarget* Subtarget,
5711 const TargetLowering &TLI) {
5718 for (unsigned i = 0; i < 8; ++i) {
5719 bool isNonZero = (NonZeros & (1 << i)) != 0;
5723 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5725 V = DAG.getUNDEF(MVT::v8i16);
5728 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5729 MVT::v8i16, V, Op.getOperand(i),
5730 DAG.getIntPtrConstant(i));
5737 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5738 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5739 unsigned NonZeros, unsigned NumNonZero,
5740 unsigned NumZero, SelectionDAG &DAG,
5741 const X86Subtarget *Subtarget,
5742 const TargetLowering &TLI) {
5743 // We know there's at least one non-zero element
5744 unsigned FirstNonZeroIdx = 0;
5745 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5746 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5747 X86::isZeroNode(FirstNonZero)) {
5749 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5752 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5753 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5756 SDValue V = FirstNonZero.getOperand(0);
5757 MVT VVT = V.getSimpleValueType();
5758 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5761 unsigned FirstNonZeroDst =
5762 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5763 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5764 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5765 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5767 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5768 SDValue Elem = Op.getOperand(Idx);
5769 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5772 // TODO: What else can be here? Deal with it.
5773 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5776 // TODO: Some optimizations are still possible here
5777 // ex: Getting one element from a vector, and the rest from another.
5778 if (Elem.getOperand(0) != V)
5781 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5784 else if (IncorrectIdx == -1U) {
5788 // There was already one element with an incorrect index.
5789 // We can't optimize this case to an insertps.
5793 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5795 EVT VT = Op.getSimpleValueType();
5796 unsigned ElementMoveMask = 0;
5797 if (IncorrectIdx == -1U)
5798 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5800 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5802 SDValue InsertpsMask =
5803 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5804 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5810 /// getVShift - Return a vector logical shift node.
5812 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5813 unsigned NumBits, SelectionDAG &DAG,
5814 const TargetLowering &TLI, SDLoc dl) {
5815 assert(VT.is128BitVector() && "Unknown type for VShift");
5816 EVT ShVT = MVT::v2i64;
5817 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5818 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5819 return DAG.getNode(ISD::BITCAST, dl, VT,
5820 DAG.getNode(Opc, dl, ShVT, SrcOp,
5821 DAG.getConstant(NumBits,
5822 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5826 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5828 // Check if the scalar load can be widened into a vector load. And if
5829 // the address is "base + cst" see if the cst can be "absorbed" into
5830 // the shuffle mask.
5831 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5832 SDValue Ptr = LD->getBasePtr();
5833 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5835 EVT PVT = LD->getValueType(0);
5836 if (PVT != MVT::i32 && PVT != MVT::f32)
5841 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5842 FI = FINode->getIndex();
5844 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5845 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5846 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5847 Offset = Ptr.getConstantOperandVal(1);
5848 Ptr = Ptr.getOperand(0);
5853 // FIXME: 256-bit vector instructions don't require a strict alignment,
5854 // improve this code to support it better.
5855 unsigned RequiredAlign = VT.getSizeInBits()/8;
5856 SDValue Chain = LD->getChain();
5857 // Make sure the stack object alignment is at least 16 or 32.
5858 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5859 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5860 if (MFI->isFixedObjectIndex(FI)) {
5861 // Can't change the alignment. FIXME: It's possible to compute
5862 // the exact stack offset and reference FI + adjust offset instead.
5863 // If someone *really* cares about this. That's the way to implement it.
5866 MFI->setObjectAlignment(FI, RequiredAlign);
5870 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5871 // Ptr + (Offset & ~15).
5874 if ((Offset % RequiredAlign) & 3)
5876 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5878 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5879 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5881 int EltNo = (Offset - StartOffset) >> 2;
5882 unsigned NumElems = VT.getVectorNumElements();
5884 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5885 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5886 LD->getPointerInfo().getWithOffset(StartOffset),
5887 false, false, false, 0);
5889 SmallVector<int, 8> Mask;
5890 for (unsigned i = 0; i != NumElems; ++i)
5891 Mask.push_back(EltNo);
5893 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5899 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5900 /// vector of type 'VT', see if the elements can be replaced by a single large
5901 /// load which has the same value as a build_vector whose operands are 'elts'.
5903 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5905 /// FIXME: we'd also like to handle the case where the last elements are zero
5906 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5907 /// There's even a handy isZeroNode for that purpose.
5908 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5909 SDLoc &DL, SelectionDAG &DAG,
5910 bool isAfterLegalize) {
5911 EVT EltVT = VT.getVectorElementType();
5912 unsigned NumElems = Elts.size();
5914 LoadSDNode *LDBase = nullptr;
5915 unsigned LastLoadedElt = -1U;
5917 // For each element in the initializer, see if we've found a load or an undef.
5918 // If we don't find an initial load element, or later load elements are
5919 // non-consecutive, bail out.
5920 for (unsigned i = 0; i < NumElems; ++i) {
5921 SDValue Elt = Elts[i];
5923 if (!Elt.getNode() ||
5924 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5927 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5929 LDBase = cast<LoadSDNode>(Elt.getNode());
5933 if (Elt.getOpcode() == ISD::UNDEF)
5936 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5937 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5942 // If we have found an entire vector of loads and undefs, then return a large
5943 // load of the entire vector width starting at the base pointer. If we found
5944 // consecutive loads for the low half, generate a vzext_load node.
5945 if (LastLoadedElt == NumElems - 1) {
5947 if (isAfterLegalize &&
5948 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5951 SDValue NewLd = SDValue();
5953 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5954 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5955 LDBase->getPointerInfo(),
5956 LDBase->isVolatile(), LDBase->isNonTemporal(),
5957 LDBase->isInvariant(), 0);
5958 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5959 LDBase->getPointerInfo(),
5960 LDBase->isVolatile(), LDBase->isNonTemporal(),
5961 LDBase->isInvariant(), LDBase->getAlignment());
5963 if (LDBase->hasAnyUseOfValue(1)) {
5964 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5966 SDValue(NewLd.getNode(), 1));
5967 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5968 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5969 SDValue(NewLd.getNode(), 1));
5974 if (NumElems == 4 && LastLoadedElt == 1 &&
5975 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5976 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5977 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5979 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5980 LDBase->getPointerInfo(),
5981 LDBase->getAlignment(),
5982 false/*isVolatile*/, true/*ReadMem*/,
5985 // Make sure the newly-created LOAD is in the same position as LDBase in
5986 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5987 // update uses of LDBase's output chain to use the TokenFactor.
5988 if (LDBase->hasAnyUseOfValue(1)) {
5989 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5990 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5991 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5992 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5993 SDValue(ResNode.getNode(), 1));
5996 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6001 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6002 /// to generate a splat value for the following cases:
6003 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6004 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6005 /// a scalar load, or a constant.
6006 /// The VBROADCAST node is returned when a pattern is found,
6007 /// or SDValue() otherwise.
6008 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6009 SelectionDAG &DAG) {
6010 // VBROADCAST requires AVX.
6011 // TODO: Splats could be generated for non-AVX CPUs using SSE
6012 // instructions, but there's less potential gain for only 128-bit vectors.
6013 if (!Subtarget->hasAVX())
6016 MVT VT = Op.getSimpleValueType();
6019 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6020 "Unsupported vector type for broadcast.");
6025 switch (Op.getOpcode()) {
6027 // Unknown pattern found.
6030 case ISD::BUILD_VECTOR: {
6031 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6032 BitVector UndefElements;
6033 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6035 // We need a splat of a single value to use broadcast, and it doesn't
6036 // make any sense if the value is only in one element of the vector.
6037 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6041 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6042 Ld.getOpcode() == ISD::ConstantFP);
6044 // Make sure that all of the users of a non-constant load are from the
6045 // BUILD_VECTOR node.
6046 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6051 case ISD::VECTOR_SHUFFLE: {
6052 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6054 // Shuffles must have a splat mask where the first element is
6056 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6059 SDValue Sc = Op.getOperand(0);
6060 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6061 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6063 if (!Subtarget->hasInt256())
6066 // Use the register form of the broadcast instruction available on AVX2.
6067 if (VT.getSizeInBits() >= 256)
6068 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6069 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6072 Ld = Sc.getOperand(0);
6073 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6074 Ld.getOpcode() == ISD::ConstantFP);
6076 // The scalar_to_vector node and the suspected
6077 // load node must have exactly one user.
6078 // Constants may have multiple users.
6080 // AVX-512 has register version of the broadcast
6081 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6082 Ld.getValueType().getSizeInBits() >= 32;
6083 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6090 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6091 bool IsGE256 = (VT.getSizeInBits() >= 256);
6093 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6094 // instruction to save 8 or more bytes of constant pool data.
6095 // TODO: If multiple splats are generated to load the same constant,
6096 // it may be detrimental to overall size. There needs to be a way to detect
6097 // that condition to know if this is truly a size win.
6098 const Function *F = DAG.getMachineFunction().getFunction();
6099 bool OptForSize = F->getAttributes().
6100 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6102 // Handle broadcasting a single constant scalar from the constant pool
6104 // On Sandybridge (no AVX2), it is still better to load a constant vector
6105 // from the constant pool and not to broadcast it from a scalar.
6106 // But override that restriction when optimizing for size.
6107 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6108 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6109 EVT CVT = Ld.getValueType();
6110 assert(!CVT.isVector() && "Must not broadcast a vector type");
6112 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6113 // For size optimization, also splat v2f64 and v2i64, and for size opt
6114 // with AVX2, also splat i8 and i16.
6115 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6116 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6117 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6118 const Constant *C = nullptr;
6119 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6120 C = CI->getConstantIntValue();
6121 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6122 C = CF->getConstantFPValue();
6124 assert(C && "Invalid constant type");
6126 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6127 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6128 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6129 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6130 MachinePointerInfo::getConstantPool(),
6131 false, false, false, Alignment);
6133 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6137 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6139 // Handle AVX2 in-register broadcasts.
6140 if (!IsLoad && Subtarget->hasInt256() &&
6141 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6142 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6144 // The scalar source must be a normal load.
6148 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6149 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6151 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6152 // double since there is no vbroadcastsd xmm
6153 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6154 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6155 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6158 // Unsupported broadcast.
6162 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6163 /// underlying vector and index.
6165 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6167 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6169 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6170 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6173 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6175 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6177 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6178 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6181 // In this case the vector is the extract_subvector expression and the index
6182 // is 2, as specified by the shuffle.
6183 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6184 SDValue ShuffleVec = SVOp->getOperand(0);
6185 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6186 assert(ShuffleVecVT.getVectorElementType() ==
6187 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6189 int ShuffleIdx = SVOp->getMaskElt(Idx);
6190 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6191 ExtractedFromVec = ShuffleVec;
6197 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6198 MVT VT = Op.getSimpleValueType();
6200 // Skip if insert_vec_elt is not supported.
6201 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6202 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6206 unsigned NumElems = Op.getNumOperands();
6210 SmallVector<unsigned, 4> InsertIndices;
6211 SmallVector<int, 8> Mask(NumElems, -1);
6213 for (unsigned i = 0; i != NumElems; ++i) {
6214 unsigned Opc = Op.getOperand(i).getOpcode();
6216 if (Opc == ISD::UNDEF)
6219 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6220 // Quit if more than 1 elements need inserting.
6221 if (InsertIndices.size() > 1)
6224 InsertIndices.push_back(i);
6228 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6229 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6230 // Quit if non-constant index.
6231 if (!isa<ConstantSDNode>(ExtIdx))
6233 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6235 // Quit if extracted from vector of different type.
6236 if (ExtractedFromVec.getValueType() != VT)
6239 if (!VecIn1.getNode())
6240 VecIn1 = ExtractedFromVec;
6241 else if (VecIn1 != ExtractedFromVec) {
6242 if (!VecIn2.getNode())
6243 VecIn2 = ExtractedFromVec;
6244 else if (VecIn2 != ExtractedFromVec)
6245 // Quit if more than 2 vectors to shuffle
6249 if (ExtractedFromVec == VecIn1)
6251 else if (ExtractedFromVec == VecIn2)
6252 Mask[i] = Idx + NumElems;
6255 if (!VecIn1.getNode())
6258 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6259 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6260 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6261 unsigned Idx = InsertIndices[i];
6262 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6263 DAG.getIntPtrConstant(Idx));
6269 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6271 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6273 MVT VT = Op.getSimpleValueType();
6274 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6275 "Unexpected type in LowerBUILD_VECTORvXi1!");
6278 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6279 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6280 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6281 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6284 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6285 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6286 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6287 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6290 bool AllContants = true;
6291 uint64_t Immediate = 0;
6292 int NonConstIdx = -1;
6293 bool IsSplat = true;
6294 unsigned NumNonConsts = 0;
6295 unsigned NumConsts = 0;
6296 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6297 SDValue In = Op.getOperand(idx);
6298 if (In.getOpcode() == ISD::UNDEF)
6300 if (!isa<ConstantSDNode>(In)) {
6301 AllContants = false;
6307 if (cast<ConstantSDNode>(In)->getZExtValue())
6308 Immediate |= (1ULL << idx);
6310 if (In != Op.getOperand(0))
6315 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6316 DAG.getConstant(Immediate, MVT::i16));
6317 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6318 DAG.getIntPtrConstant(0));
6321 if (NumNonConsts == 1 && NonConstIdx != 0) {
6324 SDValue VecAsImm = DAG.getConstant(Immediate,
6325 MVT::getIntegerVT(VT.getSizeInBits()));
6326 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6329 DstVec = DAG.getUNDEF(VT);
6330 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6331 Op.getOperand(NonConstIdx),
6332 DAG.getIntPtrConstant(NonConstIdx));
6334 if (!IsSplat && (NonConstIdx != 0))
6335 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6336 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6339 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6340 DAG.getConstant(-1, SelectVT),
6341 DAG.getConstant(0, SelectVT));
6343 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6344 DAG.getConstant((Immediate | 1), SelectVT),
6345 DAG.getConstant(Immediate, SelectVT));
6346 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6349 /// \brief Return true if \p N implements a horizontal binop and return the
6350 /// operands for the horizontal binop into V0 and V1.
6352 /// This is a helper function of PerformBUILD_VECTORCombine.
6353 /// This function checks that the build_vector \p N in input implements a
6354 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6355 /// operation to match.
6356 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6357 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6358 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6361 /// This function only analyzes elements of \p N whose indices are
6362 /// in range [BaseIdx, LastIdx).
6363 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6365 unsigned BaseIdx, unsigned LastIdx,
6366 SDValue &V0, SDValue &V1) {
6367 EVT VT = N->getValueType(0);
6369 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6370 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6371 "Invalid Vector in input!");
6373 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6374 bool CanFold = true;
6375 unsigned ExpectedVExtractIdx = BaseIdx;
6376 unsigned NumElts = LastIdx - BaseIdx;
6377 V0 = DAG.getUNDEF(VT);
6378 V1 = DAG.getUNDEF(VT);
6380 // Check if N implements a horizontal binop.
6381 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6382 SDValue Op = N->getOperand(i + BaseIdx);
6385 if (Op->getOpcode() == ISD::UNDEF) {
6386 // Update the expected vector extract index.
6387 if (i * 2 == NumElts)
6388 ExpectedVExtractIdx = BaseIdx;
6389 ExpectedVExtractIdx += 2;
6393 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6398 SDValue Op0 = Op.getOperand(0);
6399 SDValue Op1 = Op.getOperand(1);
6401 // Try to match the following pattern:
6402 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6403 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6404 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6405 Op0.getOperand(0) == Op1.getOperand(0) &&
6406 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6407 isa<ConstantSDNode>(Op1.getOperand(1)));
6411 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6412 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6414 if (i * 2 < NumElts) {
6415 if (V0.getOpcode() == ISD::UNDEF)
6416 V0 = Op0.getOperand(0);
6418 if (V1.getOpcode() == ISD::UNDEF)
6419 V1 = Op0.getOperand(0);
6420 if (i * 2 == NumElts)
6421 ExpectedVExtractIdx = BaseIdx;
6424 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6425 if (I0 == ExpectedVExtractIdx)
6426 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6427 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6428 // Try to match the following dag sequence:
6429 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6430 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6434 ExpectedVExtractIdx += 2;
6440 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6441 /// a concat_vector.
6443 /// This is a helper function of PerformBUILD_VECTORCombine.
6444 /// This function expects two 256-bit vectors called V0 and V1.
6445 /// At first, each vector is split into two separate 128-bit vectors.
6446 /// Then, the resulting 128-bit vectors are used to implement two
6447 /// horizontal binary operations.
6449 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6451 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6452 /// the two new horizontal binop.
6453 /// When Mode is set, the first horizontal binop dag node would take as input
6454 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6455 /// horizontal binop dag node would take as input the lower 128-bit of V1
6456 /// and the upper 128-bit of V1.
6458 /// HADD V0_LO, V0_HI
6459 /// HADD V1_LO, V1_HI
6461 /// Otherwise, the first horizontal binop dag node takes as input the lower
6462 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6463 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6465 /// HADD V0_LO, V1_LO
6466 /// HADD V0_HI, V1_HI
6468 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6469 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6470 /// the upper 128-bits of the result.
6471 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6472 SDLoc DL, SelectionDAG &DAG,
6473 unsigned X86Opcode, bool Mode,
6474 bool isUndefLO, bool isUndefHI) {
6475 EVT VT = V0.getValueType();
6476 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6477 "Invalid nodes in input!");
6479 unsigned NumElts = VT.getVectorNumElements();
6480 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6481 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6482 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6483 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6484 EVT NewVT = V0_LO.getValueType();
6486 SDValue LO = DAG.getUNDEF(NewVT);
6487 SDValue HI = DAG.getUNDEF(NewVT);
6490 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6491 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6492 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6493 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6494 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6496 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6497 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6498 V1_LO->getOpcode() != ISD::UNDEF))
6499 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6501 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6502 V1_HI->getOpcode() != ISD::UNDEF))
6503 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6506 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6509 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6510 /// sequence of 'vadd + vsub + blendi'.
6511 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6512 const X86Subtarget *Subtarget) {
6514 EVT VT = BV->getValueType(0);
6515 unsigned NumElts = VT.getVectorNumElements();
6516 SDValue InVec0 = DAG.getUNDEF(VT);
6517 SDValue InVec1 = DAG.getUNDEF(VT);
6519 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6520 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6522 // Odd-numbered elements in the input build vector are obtained from
6523 // adding two integer/float elements.
6524 // Even-numbered elements in the input build vector are obtained from
6525 // subtracting two integer/float elements.
6526 unsigned ExpectedOpcode = ISD::FSUB;
6527 unsigned NextExpectedOpcode = ISD::FADD;
6528 bool AddFound = false;
6529 bool SubFound = false;
6531 for (unsigned i = 0, e = NumElts; i != e; i++) {
6532 SDValue Op = BV->getOperand(i);
6534 // Skip 'undef' values.
6535 unsigned Opcode = Op.getOpcode();
6536 if (Opcode == ISD::UNDEF) {
6537 std::swap(ExpectedOpcode, NextExpectedOpcode);
6541 // Early exit if we found an unexpected opcode.
6542 if (Opcode != ExpectedOpcode)
6545 SDValue Op0 = Op.getOperand(0);
6546 SDValue Op1 = Op.getOperand(1);
6548 // Try to match the following pattern:
6549 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6550 // Early exit if we cannot match that sequence.
6551 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6552 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6553 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6554 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6555 Op0.getOperand(1) != Op1.getOperand(1))
6558 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6562 // We found a valid add/sub node. Update the information accordingly.
6568 // Update InVec0 and InVec1.
6569 if (InVec0.getOpcode() == ISD::UNDEF)
6570 InVec0 = Op0.getOperand(0);
6571 if (InVec1.getOpcode() == ISD::UNDEF)
6572 InVec1 = Op1.getOperand(0);
6574 // Make sure that operands in input to each add/sub node always
6575 // come from a same pair of vectors.
6576 if (InVec0 != Op0.getOperand(0)) {
6577 if (ExpectedOpcode == ISD::FSUB)
6580 // FADD is commutable. Try to commute the operands
6581 // and then test again.
6582 std::swap(Op0, Op1);
6583 if (InVec0 != Op0.getOperand(0))
6587 if (InVec1 != Op1.getOperand(0))
6590 // Update the pair of expected opcodes.
6591 std::swap(ExpectedOpcode, NextExpectedOpcode);
6594 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6595 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6596 InVec1.getOpcode() != ISD::UNDEF)
6597 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6602 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6603 const X86Subtarget *Subtarget) {
6605 EVT VT = N->getValueType(0);
6606 unsigned NumElts = VT.getVectorNumElements();
6607 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6608 SDValue InVec0, InVec1;
6610 // Try to match an ADDSUB.
6611 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6612 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6613 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6614 if (Value.getNode())
6618 // Try to match horizontal ADD/SUB.
6619 unsigned NumUndefsLO = 0;
6620 unsigned NumUndefsHI = 0;
6621 unsigned Half = NumElts/2;
6623 // Count the number of UNDEF operands in the build_vector in input.
6624 for (unsigned i = 0, e = Half; i != e; ++i)
6625 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6628 for (unsigned i = Half, e = NumElts; i != e; ++i)
6629 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6632 // Early exit if this is either a build_vector of all UNDEFs or all the
6633 // operands but one are UNDEF.
6634 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6637 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6638 // Try to match an SSE3 float HADD/HSUB.
6639 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6640 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6642 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6643 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6644 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6645 // Try to match an SSSE3 integer HADD/HSUB.
6646 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6647 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6649 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6650 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6653 if (!Subtarget->hasAVX())
6656 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6657 // Try to match an AVX horizontal add/sub of packed single/double
6658 // precision floating point values from 256-bit vectors.
6659 SDValue InVec2, InVec3;
6660 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6661 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6662 ((InVec0.getOpcode() == ISD::UNDEF ||
6663 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6664 ((InVec1.getOpcode() == ISD::UNDEF ||
6665 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6666 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6668 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6669 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6670 ((InVec0.getOpcode() == ISD::UNDEF ||
6671 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6672 ((InVec1.getOpcode() == ISD::UNDEF ||
6673 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6674 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6675 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6676 // Try to match an AVX2 horizontal add/sub of signed integers.
6677 SDValue InVec2, InVec3;
6679 bool CanFold = true;
6681 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6682 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6683 ((InVec0.getOpcode() == ISD::UNDEF ||
6684 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6685 ((InVec1.getOpcode() == ISD::UNDEF ||
6686 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6687 X86Opcode = X86ISD::HADD;
6688 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6689 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6690 ((InVec0.getOpcode() == ISD::UNDEF ||
6691 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6692 ((InVec1.getOpcode() == ISD::UNDEF ||
6693 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6694 X86Opcode = X86ISD::HSUB;
6699 // Fold this build_vector into a single horizontal add/sub.
6700 // Do this only if the target has AVX2.
6701 if (Subtarget->hasAVX2())
6702 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6704 // Do not try to expand this build_vector into a pair of horizontal
6705 // add/sub if we can emit a pair of scalar add/sub.
6706 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6709 // Convert this build_vector into a pair of horizontal binop followed by
6711 bool isUndefLO = NumUndefsLO == Half;
6712 bool isUndefHI = NumUndefsHI == Half;
6713 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6714 isUndefLO, isUndefHI);
6718 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6719 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6721 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6722 X86Opcode = X86ISD::HADD;
6723 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6724 X86Opcode = X86ISD::HSUB;
6725 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6726 X86Opcode = X86ISD::FHADD;
6727 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6728 X86Opcode = X86ISD::FHSUB;
6732 // Don't try to expand this build_vector into a pair of horizontal add/sub
6733 // if we can simply emit a pair of scalar add/sub.
6734 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6737 // Convert this build_vector into two horizontal add/sub followed by
6739 bool isUndefLO = NumUndefsLO == Half;
6740 bool isUndefHI = NumUndefsHI == Half;
6741 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6742 isUndefLO, isUndefHI);
6749 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6752 MVT VT = Op.getSimpleValueType();
6753 MVT ExtVT = VT.getVectorElementType();
6754 unsigned NumElems = Op.getNumOperands();
6756 // Generate vectors for predicate vectors.
6757 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6758 return LowerBUILD_VECTORvXi1(Op, DAG);
6760 // Vectors containing all zeros can be matched by pxor and xorps later
6761 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6762 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6763 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6764 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6767 return getZeroVector(VT, Subtarget, DAG, dl);
6770 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6771 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6772 // vpcmpeqd on 256-bit vectors.
6773 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6774 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6777 if (!VT.is512BitVector())
6778 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6781 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6782 if (Broadcast.getNode())
6785 unsigned EVTBits = ExtVT.getSizeInBits();
6787 unsigned NumZero = 0;
6788 unsigned NumNonZero = 0;
6789 unsigned NonZeros = 0;
6790 bool IsAllConstants = true;
6791 SmallSet<SDValue, 8> Values;
6792 for (unsigned i = 0; i < NumElems; ++i) {
6793 SDValue Elt = Op.getOperand(i);
6794 if (Elt.getOpcode() == ISD::UNDEF)
6797 if (Elt.getOpcode() != ISD::Constant &&
6798 Elt.getOpcode() != ISD::ConstantFP)
6799 IsAllConstants = false;
6800 if (X86::isZeroNode(Elt))
6803 NonZeros |= (1 << i);
6808 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6809 if (NumNonZero == 0)
6810 return DAG.getUNDEF(VT);
6812 // Special case for single non-zero, non-undef, element.
6813 if (NumNonZero == 1) {
6814 unsigned Idx = countTrailingZeros(NonZeros);
6815 SDValue Item = Op.getOperand(Idx);
6817 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6818 // the value are obviously zero, truncate the value to i32 and do the
6819 // insertion that way. Only do this if the value is non-constant or if the
6820 // value is a constant being inserted into element 0. It is cheaper to do
6821 // a constant pool load than it is to do a movd + shuffle.
6822 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6823 (!IsAllConstants || Idx == 0)) {
6824 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6826 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6827 EVT VecVT = MVT::v4i32;
6828 unsigned VecElts = 4;
6830 // Truncate the value (which may itself be a constant) to i32, and
6831 // convert it to a vector with movd (S2V+shuffle to zero extend).
6832 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6833 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6835 // If using the new shuffle lowering, just directly insert this.
6836 if (ExperimentalVectorShuffleLowering)
6838 ISD::BITCAST, dl, VT,
6839 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6841 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6843 // Now we have our 32-bit value zero extended in the low element of
6844 // a vector. If Idx != 0, swizzle it into place.
6846 SmallVector<int, 4> Mask;
6847 Mask.push_back(Idx);
6848 for (unsigned i = 1; i != VecElts; ++i)
6850 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6853 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6857 // If we have a constant or non-constant insertion into the low element of
6858 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6859 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6860 // depending on what the source datatype is.
6863 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6865 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6866 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6867 if (VT.is256BitVector() || VT.is512BitVector()) {
6868 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6869 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6870 Item, DAG.getIntPtrConstant(0));
6872 assert(VT.is128BitVector() && "Expected an SSE value type!");
6873 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6874 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6875 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6878 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6879 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6880 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6881 if (VT.is256BitVector()) {
6882 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6883 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6885 assert(VT.is128BitVector() && "Expected an SSE value type!");
6886 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6888 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6892 // Is it a vector logical left shift?
6893 if (NumElems == 2 && Idx == 1 &&
6894 X86::isZeroNode(Op.getOperand(0)) &&
6895 !X86::isZeroNode(Op.getOperand(1))) {
6896 unsigned NumBits = VT.getSizeInBits();
6897 return getVShift(true, VT,
6898 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6899 VT, Op.getOperand(1)),
6900 NumBits/2, DAG, *this, dl);
6903 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6906 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6907 // is a non-constant being inserted into an element other than the low one,
6908 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6909 // movd/movss) to move this into the low element, then shuffle it into
6911 if (EVTBits == 32) {
6912 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6914 // If using the new shuffle lowering, just directly insert this.
6915 if (ExperimentalVectorShuffleLowering)
6916 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6918 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6919 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6920 SmallVector<int, 8> MaskVec;
6921 for (unsigned i = 0; i != NumElems; ++i)
6922 MaskVec.push_back(i == Idx ? 0 : 1);
6923 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6927 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6928 if (Values.size() == 1) {
6929 if (EVTBits == 32) {
6930 // Instead of a shuffle like this:
6931 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6932 // Check if it's possible to issue this instead.
6933 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6934 unsigned Idx = countTrailingZeros(NonZeros);
6935 SDValue Item = Op.getOperand(Idx);
6936 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6937 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6942 // A vector full of immediates; various special cases are already
6943 // handled, so this is best done with a single constant-pool load.
6947 // For AVX-length vectors, build the individual 128-bit pieces and use
6948 // shuffles to put them in place.
6949 if (VT.is256BitVector() || VT.is512BitVector()) {
6950 SmallVector<SDValue, 64> V;
6951 for (unsigned i = 0; i != NumElems; ++i)
6952 V.push_back(Op.getOperand(i));
6954 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6956 // Build both the lower and upper subvector.
6957 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6958 makeArrayRef(&V[0], NumElems/2));
6959 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6960 makeArrayRef(&V[NumElems / 2], NumElems/2));
6962 // Recreate the wider vector with the lower and upper part.
6963 if (VT.is256BitVector())
6964 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6965 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6968 // Let legalizer expand 2-wide build_vectors.
6969 if (EVTBits == 64) {
6970 if (NumNonZero == 1) {
6971 // One half is zero or undef.
6972 unsigned Idx = countTrailingZeros(NonZeros);
6973 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6974 Op.getOperand(Idx));
6975 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6980 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6981 if (EVTBits == 8 && NumElems == 16) {
6982 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6984 if (V.getNode()) return V;
6987 if (EVTBits == 16 && NumElems == 8) {
6988 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6990 if (V.getNode()) return V;
6993 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6994 if (EVTBits == 32 && NumElems == 4) {
6995 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6996 NumZero, DAG, Subtarget, *this);
7001 // If element VT is == 32 bits, turn it into a number of shuffles.
7002 SmallVector<SDValue, 8> V(NumElems);
7003 if (NumElems == 4 && NumZero > 0) {
7004 for (unsigned i = 0; i < 4; ++i) {
7005 bool isZero = !(NonZeros & (1 << i));
7007 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7009 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7012 for (unsigned i = 0; i < 2; ++i) {
7013 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7016 V[i] = V[i*2]; // Must be a zero vector.
7019 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7022 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7025 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7030 bool Reverse1 = (NonZeros & 0x3) == 2;
7031 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7035 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7036 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7038 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7041 if (Values.size() > 1 && VT.is128BitVector()) {
7042 // Check for a build vector of consecutive loads.
7043 for (unsigned i = 0; i < NumElems; ++i)
7044 V[i] = Op.getOperand(i);
7046 // Check for elements which are consecutive loads.
7047 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7051 // Check for a build vector from mostly shuffle plus few inserting.
7052 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7056 // For SSE 4.1, use insertps to put the high elements into the low element.
7057 if (getSubtarget()->hasSSE41()) {
7059 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7060 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7062 Result = DAG.getUNDEF(VT);
7064 for (unsigned i = 1; i < NumElems; ++i) {
7065 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7066 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7067 Op.getOperand(i), DAG.getIntPtrConstant(i));
7072 // Otherwise, expand into a number of unpckl*, start by extending each of
7073 // our (non-undef) elements to the full vector width with the element in the
7074 // bottom slot of the vector (which generates no code for SSE).
7075 for (unsigned i = 0; i < NumElems; ++i) {
7076 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7077 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7079 V[i] = DAG.getUNDEF(VT);
7082 // Next, we iteratively mix elements, e.g. for v4f32:
7083 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7084 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7085 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7086 unsigned EltStride = NumElems >> 1;
7087 while (EltStride != 0) {
7088 for (unsigned i = 0; i < EltStride; ++i) {
7089 // If V[i+EltStride] is undef and this is the first round of mixing,
7090 // then it is safe to just drop this shuffle: V[i] is already in the
7091 // right place, the one element (since it's the first round) being
7092 // inserted as undef can be dropped. This isn't safe for successive
7093 // rounds because they will permute elements within both vectors.
7094 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7095 EltStride == NumElems/2)
7098 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7107 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7108 // to create 256-bit vectors from two other 128-bit ones.
7109 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7111 MVT ResVT = Op.getSimpleValueType();
7113 assert((ResVT.is256BitVector() ||
7114 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7116 SDValue V1 = Op.getOperand(0);
7117 SDValue V2 = Op.getOperand(1);
7118 unsigned NumElems = ResVT.getVectorNumElements();
7119 if(ResVT.is256BitVector())
7120 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7122 if (Op.getNumOperands() == 4) {
7123 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7124 ResVT.getVectorNumElements()/2);
7125 SDValue V3 = Op.getOperand(2);
7126 SDValue V4 = Op.getOperand(3);
7127 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7128 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7130 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7133 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7134 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7135 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7136 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7137 Op.getNumOperands() == 4)));
7139 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7140 // from two other 128-bit ones.
7142 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7143 return LowerAVXCONCAT_VECTORS(Op, DAG);
7147 //===----------------------------------------------------------------------===//
7148 // Vector shuffle lowering
7150 // This is an experimental code path for lowering vector shuffles on x86. It is
7151 // designed to handle arbitrary vector shuffles and blends, gracefully
7152 // degrading performance as necessary. It works hard to recognize idiomatic
7153 // shuffles and lower them to optimal instruction patterns without leaving
7154 // a framework that allows reasonably efficient handling of all vector shuffle
7156 //===----------------------------------------------------------------------===//
7158 /// \brief Tiny helper function to identify a no-op mask.
7160 /// This is a somewhat boring predicate function. It checks whether the mask
7161 /// array input, which is assumed to be a single-input shuffle mask of the kind
7162 /// used by the X86 shuffle instructions (not a fully general
7163 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7164 /// in-place shuffle are 'no-op's.
7165 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7166 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7167 if (Mask[i] != -1 && Mask[i] != i)
7172 /// \brief Helper function to classify a mask as a single-input mask.
7174 /// This isn't a generic single-input test because in the vector shuffle
7175 /// lowering we canonicalize single inputs to be the first input operand. This
7176 /// means we can more quickly test for a single input by only checking whether
7177 /// an input from the second operand exists. We also assume that the size of
7178 /// mask corresponds to the size of the input vectors which isn't true in the
7179 /// fully general case.
7180 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7182 if (M >= (int)Mask.size())
7187 /// \brief Test whether there are elements crossing 128-bit lanes in this
7190 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7191 /// and we routinely test for these.
7192 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7193 int LaneSize = 128 / VT.getScalarSizeInBits();
7194 int Size = Mask.size();
7195 for (int i = 0; i < Size; ++i)
7196 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7201 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7203 /// This checks a shuffle mask to see if it is performing the same
7204 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7205 /// that it is also not lane-crossing. It may however involve a blend from the
7206 /// same lane of a second vector.
7208 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7209 /// non-trivial to compute in the face of undef lanes. The representation is
7210 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7211 /// entries from both V1 and V2 inputs to the wider mask.
7213 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7214 SmallVectorImpl<int> &RepeatedMask) {
7215 int LaneSize = 128 / VT.getScalarSizeInBits();
7216 RepeatedMask.resize(LaneSize, -1);
7217 int Size = Mask.size();
7218 for (int i = 0; i < Size; ++i) {
7221 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7222 // This entry crosses lanes, so there is no way to model this shuffle.
7225 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7226 if (RepeatedMask[i % LaneSize] == -1)
7227 // This is the first non-undef entry in this slot of a 128-bit lane.
7228 RepeatedMask[i % LaneSize] =
7229 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7230 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7231 // Found a mismatch with the repeated mask.
7237 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7238 // 2013 will allow us to use it as a non-type template parameter.
7241 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7243 /// See its documentation for details.
7244 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7245 if (Mask.size() != Args.size())
7247 for (int i = 0, e = Mask.size(); i < e; ++i) {
7248 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7249 if (Mask[i] != -1 && Mask[i] != *Args[i])
7257 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7260 /// This is a fast way to test a shuffle mask against a fixed pattern:
7262 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7264 /// It returns true if the mask is exactly as wide as the argument list, and
7265 /// each element of the mask is either -1 (signifying undef) or the value given
7266 /// in the argument.
7267 static const VariadicFunction1<
7268 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7270 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7272 /// This helper function produces an 8-bit shuffle immediate corresponding to
7273 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7274 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7277 /// NB: We rely heavily on "undef" masks preserving the input lane.
7278 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7279 SelectionDAG &DAG) {
7280 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7281 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7282 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7283 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7284 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7287 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7288 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7289 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7290 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7291 return DAG.getConstant(Imm, MVT::i8);
7294 /// \brief Try to emit a blend instruction for a shuffle.
7296 /// This doesn't do any checks for the availability of instructions for blending
7297 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7298 /// be matched in the backend with the type given. What it does check for is
7299 /// that the shuffle mask is in fact a blend.
7300 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7301 SDValue V2, ArrayRef<int> Mask,
7302 const X86Subtarget *Subtarget,
7303 SelectionDAG &DAG) {
7305 unsigned BlendMask = 0;
7306 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7307 if (Mask[i] >= Size) {
7308 if (Mask[i] != i + Size)
7309 return SDValue(); // Shuffled V2 input!
7310 BlendMask |= 1u << i;
7313 if (Mask[i] >= 0 && Mask[i] != i)
7314 return SDValue(); // Shuffled V1 input!
7316 switch (VT.SimpleTy) {
7321 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7322 DAG.getConstant(BlendMask, MVT::i8));
7326 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7330 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7331 // that instruction.
7332 if (Subtarget->hasAVX2()) {
7333 // Scale the blend by the number of 32-bit dwords per element.
7334 int Scale = VT.getScalarSizeInBits() / 32;
7336 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7337 if (Mask[i] >= Size)
7338 for (int j = 0; j < Scale; ++j)
7339 BlendMask |= 1u << (i * Scale + j);
7341 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7342 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7343 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7344 return DAG.getNode(ISD::BITCAST, DL, VT,
7345 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7346 DAG.getConstant(BlendMask, MVT::i8)));
7350 // For integer shuffles we need to expand the mask and cast the inputs to
7351 // v8i16s prior to blending.
7352 int Scale = 8 / VT.getVectorNumElements();
7354 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7355 if (Mask[i] >= Size)
7356 for (int j = 0; j < Scale; ++j)
7357 BlendMask |= 1u << (i * Scale + j);
7359 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7360 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7361 return DAG.getNode(ISD::BITCAST, DL, VT,
7362 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7363 DAG.getConstant(BlendMask, MVT::i8)));
7367 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7368 SmallVector<int, 8> RepeatedMask;
7369 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7370 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7371 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7373 for (int i = 0; i < 8; ++i)
7374 if (RepeatedMask[i] >= 16)
7375 BlendMask |= 1u << i;
7376 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7377 DAG.getConstant(BlendMask, MVT::i8));
7382 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7383 // Scale the blend by the number of bytes per element.
7384 int Scale = VT.getScalarSizeInBits() / 8;
7385 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7387 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7388 // mix of LLVM's code generator and the x86 backend. We tell the code
7389 // generator that boolean values in the elements of an x86 vector register
7390 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7391 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7392 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7393 // of the element (the remaining are ignored) and 0 in that high bit would
7394 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7395 // the LLVM model for boolean values in vector elements gets the relevant
7396 // bit set, it is set backwards and over constrained relative to x86's
7398 SDValue VSELECTMask[32];
7399 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7400 for (int j = 0; j < Scale; ++j)
7401 VSELECTMask[Scale * i + j] =
7402 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7403 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7405 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7406 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7408 ISD::BITCAST, DL, VT,
7409 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7410 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7415 llvm_unreachable("Not a supported integer vector type!");
7419 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7420 /// unblended shuffles followed by an unshuffled blend.
7422 /// This matches the extremely common pattern for handling combined
7423 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7425 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7429 SelectionDAG &DAG) {
7430 // Shuffle the input elements into the desired positions in V1 and V2 and
7431 // blend them together.
7432 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7433 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7434 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7435 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7436 if (Mask[i] >= 0 && Mask[i] < Size) {
7437 V1Mask[i] = Mask[i];
7439 } else if (Mask[i] >= Size) {
7440 V2Mask[i] = Mask[i] - Size;
7441 BlendMask[i] = i + Size;
7444 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7445 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7446 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7449 /// \brief Try to lower a vector shuffle as a byte rotation.
7451 /// We have a generic PALIGNR instruction in x86 that will do an arbitrary
7452 /// byte-rotation of a the concatentation of two vectors. This routine will
7453 /// try to generically lower a vector shuffle through such an instruction. It
7454 /// does not check for the availability of PALIGNR-based lowerings, only the
7455 /// applicability of this strategy to the given mask. This matches shuffle
7456 /// vectors that look like:
7458 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7460 /// Essentially it concatenates V1 and V2, shifts right by some number of
7461 /// elements, and takes the low elements as the result. Note that while this is
7462 /// specified as a *right shift* because x86 is little-endian, it is a *left
7463 /// rotate* of the vector lanes.
7465 /// Note that this only handles 128-bit vector widths currently.
7466 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7469 SelectionDAG &DAG) {
7470 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7472 // We need to detect various ways of spelling a rotation:
7473 // [11, 12, 13, 14, 15, 0, 1, 2]
7474 // [-1, 12, 13, 14, -1, -1, 1, -1]
7475 // [-1, -1, -1, -1, -1, -1, 1, 2]
7476 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7477 // [-1, 4, 5, 6, -1, -1, 9, -1]
7478 // [-1, 4, 5, 6, -1, -1, -1, -1]
7481 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7484 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7486 // Based on the mod-Size value of this mask element determine where
7487 // a rotated vector would have started.
7488 int StartIdx = i - (Mask[i] % Size);
7490 // The identity rotation isn't interesting, stop.
7493 // If we found the tail of a vector the rotation must be the missing
7494 // front. If we found the head of a vector, it must be how much of the head.
7495 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7498 Rotation = CandidateRotation;
7499 else if (Rotation != CandidateRotation)
7500 // The rotations don't match, so we can't match this mask.
7503 // Compute which value this mask is pointing at.
7504 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7506 // Compute which of the two target values this index should be assigned to.
7507 // This reflects whether the high elements are remaining or the low elements
7509 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7511 // Either set up this value if we've not encountered it before, or check
7512 // that it remains consistent.
7515 else if (TargetV != MaskV)
7516 // This may be a rotation, but it pulls from the inputs in some
7517 // unsupported interleaving.
7521 // Check that we successfully analyzed the mask, and normalize the results.
7522 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7523 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7529 // Cast the inputs to v16i8 to match PALIGNR.
7530 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7531 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7533 assert(VT.getSizeInBits() == 128 &&
7534 "Rotate-based lowering only supports 128-bit lowering!");
7535 assert(Mask.size() <= 16 &&
7536 "Can shuffle at most 16 bytes in a 128-bit vector!");
7537 // The actual rotate instruction rotates bytes, so we need to scale the
7538 // rotation based on how many bytes are in the vector.
7539 int Scale = 16 / Mask.size();
7541 return DAG.getNode(ISD::BITCAST, DL, VT,
7542 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7543 DAG.getConstant(Rotation * Scale, MVT::i8)));
7546 /// \brief Compute whether each element of a shuffle is zeroable.
7548 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7549 /// Either it is an undef element in the shuffle mask, the element of the input
7550 /// referenced is undef, or the element of the input referenced is known to be
7551 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7552 /// as many lanes with this technique as possible to simplify the remaining
7554 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7555 SDValue V1, SDValue V2) {
7556 SmallBitVector Zeroable(Mask.size(), false);
7558 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7559 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7561 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7563 // Handle the easy cases.
7564 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7569 // If this is an index into a build_vector node, dig out the input value and
7571 SDValue V = M < Size ? V1 : V2;
7572 if (V.getOpcode() != ISD::BUILD_VECTOR)
7575 SDValue Input = V.getOperand(M % Size);
7576 // The UNDEF opcode check really should be dead code here, but not quite
7577 // worth asserting on (it isn't invalid, just unexpected).
7578 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7585 /// \brief Lower a vector shuffle as a zero or any extension.
7587 /// Given a specific number of elements, element bit width, and extension
7588 /// stride, produce either a zero or any extension based on the available
7589 /// features of the subtarget.
7590 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7591 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7592 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7593 assert(Scale > 1 && "Need a scale to extend.");
7594 int EltBits = VT.getSizeInBits() / NumElements;
7595 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7596 "Only 8, 16, and 32 bit elements can be extended.");
7597 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7599 // Found a valid zext mask! Try various lowering strategies based on the
7600 // input type and available ISA extensions.
7601 if (Subtarget->hasSSE41()) {
7602 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7603 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7604 NumElements / Scale);
7605 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7606 return DAG.getNode(ISD::BITCAST, DL, VT,
7607 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7610 // For any extends we can cheat for larger element sizes and use shuffle
7611 // instructions that can fold with a load and/or copy.
7612 if (AnyExt && EltBits == 32) {
7613 int PSHUFDMask[4] = {0, -1, 1, -1};
7615 ISD::BITCAST, DL, VT,
7616 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7617 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7618 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7620 if (AnyExt && EltBits == 16 && Scale > 2) {
7621 int PSHUFDMask[4] = {0, -1, 0, -1};
7622 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7623 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7624 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7625 int PSHUFHWMask[4] = {1, -1, -1, -1};
7627 ISD::BITCAST, DL, VT,
7628 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7629 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7630 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7633 // If this would require more than 2 unpack instructions to expand, use
7634 // pshufb when available. We can only use more than 2 unpack instructions
7635 // when zero extending i8 elements which also makes it easier to use pshufb.
7636 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7637 assert(NumElements == 16 && "Unexpected byte vector width!");
7638 SDValue PSHUFBMask[16];
7639 for (int i = 0; i < 16; ++i)
7641 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7642 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7643 return DAG.getNode(ISD::BITCAST, DL, VT,
7644 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7645 DAG.getNode(ISD::BUILD_VECTOR, DL,
7646 MVT::v16i8, PSHUFBMask)));
7649 // Otherwise emit a sequence of unpacks.
7651 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7652 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7653 : getZeroVector(InputVT, Subtarget, DAG, DL);
7654 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7655 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7659 } while (Scale > 1);
7660 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7663 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7665 /// This routine will try to do everything in its power to cleverly lower
7666 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7667 /// check for the profitability of this lowering, it tries to aggressively
7668 /// match this pattern. It will use all of the micro-architectural details it
7669 /// can to emit an efficient lowering. It handles both blends with all-zero
7670 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7671 /// masking out later).
7673 /// The reason we have dedicated lowering for zext-style shuffles is that they
7674 /// are both incredibly common and often quite performance sensitive.
7675 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7676 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7677 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7678 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7680 int Bits = VT.getSizeInBits();
7681 int NumElements = Mask.size();
7683 // Define a helper function to check a particular ext-scale and lower to it if
7685 auto Lower = [&](int Scale) -> SDValue {
7688 for (int i = 0; i < NumElements; ++i) {
7690 continue; // Valid anywhere but doesn't tell us anything.
7691 if (i % Scale != 0) {
7692 // Each of the extend elements needs to be zeroable.
7696 // We no lorger are in the anyext case.
7701 // Each of the base elements needs to be consecutive indices into the
7702 // same input vector.
7703 SDValue V = Mask[i] < NumElements ? V1 : V2;
7706 else if (InputV != V)
7707 return SDValue(); // Flip-flopping inputs.
7709 if (Mask[i] % NumElements != i / Scale)
7710 return SDValue(); // Non-consecutive strided elemenst.
7713 // If we fail to find an input, we have a zero-shuffle which should always
7714 // have already been handled.
7715 // FIXME: Maybe handle this here in case during blending we end up with one?
7719 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7720 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7723 // The widest scale possible for extending is to a 64-bit integer.
7724 assert(Bits % 64 == 0 &&
7725 "The number of bits in a vector must be divisible by 64 on x86!");
7726 int NumExtElements = Bits / 64;
7728 // Each iteration, try extending the elements half as much, but into twice as
7730 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7731 assert(NumElements % NumExtElements == 0 &&
7732 "The input vector size must be divisble by the extended size.");
7733 if (SDValue V = Lower(NumElements / NumExtElements))
7737 // No viable ext lowering found.
7741 /// \brief Try to get a scalar value for a specific element of a vector.
7743 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7744 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7745 SelectionDAG &DAG) {
7746 MVT VT = V.getSimpleValueType();
7747 MVT EltVT = VT.getVectorElementType();
7748 while (V.getOpcode() == ISD::BITCAST)
7749 V = V.getOperand(0);
7750 // If the bitcasts shift the element size, we can't extract an equivalent
7752 MVT NewVT = V.getSimpleValueType();
7753 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7756 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7757 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
7758 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
7763 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7765 /// This is particularly important because the set of instructions varies
7766 /// significantly based on whether the operand is a load or not.
7767 static bool isShuffleFoldableLoad(SDValue V) {
7768 while (V.getOpcode() == ISD::BITCAST)
7769 V = V.getOperand(0);
7771 return ISD::isNON_EXTLoad(V.getNode());
7774 /// \brief Try to lower insertion of a single element into a zero vector.
7776 /// This is a common pattern that we have especially efficient patterns to lower
7777 /// across all subtarget feature sets.
7778 static SDValue lowerVectorShuffleAsElementInsertion(
7779 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7780 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7781 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7783 MVT EltVT = VT.getVectorElementType();
7785 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7786 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7788 bool IsV1Zeroable = true;
7789 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7790 if (i != V2Index && !Zeroable[i]) {
7791 IsV1Zeroable = false;
7795 // Check for a single input from a SCALAR_TO_VECTOR node.
7796 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7797 // all the smarts here sunk into that routine. However, the current
7798 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7799 // vector shuffle lowering is dead.
7800 if (SDValue V2S = getScalarValueForVectorElement(
7801 V2, Mask[V2Index] - Mask.size(), DAG)) {
7802 // We need to zext the scalar if it is smaller than an i32.
7803 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7804 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7805 // Using zext to expand a narrow element won't work for non-zero
7810 // Zero-extend directly to i32.
7812 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7814 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7815 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7816 EltVT == MVT::i16) {
7817 // Either not inserting from the low element of the input or the input
7818 // element size is too small to use VZEXT_MOVL to clear the high bits.
7822 if (!IsV1Zeroable) {
7823 // If V1 can't be treated as a zero vector we have fewer options to lower
7824 // this. We can't support integer vectors or non-zero targets cheaply, and
7825 // the V1 elements can't be permuted in any way.
7826 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7827 if (!VT.isFloatingPoint() || V2Index != 0)
7829 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7830 V1Mask[V2Index] = -1;
7831 if (!isNoopShuffleMask(V1Mask))
7833 // This is essentially a special case blend operation, but if we have
7834 // general purpose blend operations, they are always faster. Bail and let
7835 // the rest of the lowering handle these as blends.
7836 if (Subtarget->hasSSE41())
7839 // Otherwise, use MOVSD or MOVSS.
7840 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7841 "Only two types of floating point element types to handle!");
7842 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7846 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7848 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7851 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7852 // the desired position. Otherwise it is more efficient to do a vector
7853 // shift left. We know that we can do a vector shift left because all
7854 // the inputs are zero.
7855 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7856 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7857 V2Shuffle[V2Index] = 0;
7858 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7860 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
7862 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7864 V2Index * EltVT.getSizeInBits(),
7865 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7866 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
7872 /// \brief Try to lower broadcast of a single element.
7874 /// For convenience, this code also bundles all of the subtarget feature set
7875 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7876 /// a convenient way to factor it out.
7877 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
7879 const X86Subtarget *Subtarget,
7880 SelectionDAG &DAG) {
7881 if (!Subtarget->hasAVX())
7883 if (VT.isInteger() && !Subtarget->hasAVX2())
7886 // Check that the mask is a broadcast.
7887 int BroadcastIdx = -1;
7889 if (M >= 0 && BroadcastIdx == -1)
7891 else if (M >= 0 && M != BroadcastIdx)
7894 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7895 "a sorted mask where the broadcast "
7898 // Check if this is a broadcast of a scalar. We special case lowering for
7899 // scalars so that we can more effectively fold with loads.
7900 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7901 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7902 V = V.getOperand(BroadcastIdx);
7904 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
7906 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7908 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7909 // We can't broadcast from a vector register w/o AVX2, and we can only
7910 // broadcast from the zero-element of a vector register.
7914 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7917 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7919 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7920 /// support for floating point shuffles but not integer shuffles. These
7921 /// instructions will incur a domain crossing penalty on some chips though so
7922 /// it is better to avoid lowering through this for integer vectors where
7924 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7925 const X86Subtarget *Subtarget,
7926 SelectionDAG &DAG) {
7928 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7929 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7930 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7931 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7932 ArrayRef<int> Mask = SVOp->getMask();
7933 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7935 if (isSingleInputShuffleMask(Mask)) {
7936 // Straight shuffle of a single input vector. Simulate this by using the
7937 // single input as both of the "inputs" to this instruction..
7938 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7940 if (Subtarget->hasAVX()) {
7941 // If we have AVX, we can use VPERMILPS which will allow folding a load
7942 // into the shuffle.
7943 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7944 DAG.getConstant(SHUFPDMask, MVT::i8));
7947 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7948 DAG.getConstant(SHUFPDMask, MVT::i8));
7950 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7951 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7953 // Use dedicated unpack instructions for masks that match their pattern.
7954 if (isShuffleEquivalent(Mask, 0, 2))
7955 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7956 if (isShuffleEquivalent(Mask, 1, 3))
7957 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7959 // If we have a single input, insert that into V1 if we can do so cheaply.
7960 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
7961 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7962 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
7964 // Try inverting the insertion since for v2 masks it is easy to do and we
7965 // can't reliably sort the mask one way or the other.
7966 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7967 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7968 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7969 MVT::v2f64, DL, V2, V1, InverseMask, Subtarget, DAG))
7973 // Try to use one of the special instruction patterns to handle two common
7974 // blend patterns if a zero-blend above didn't work.
7975 if (isShuffleEquivalent(Mask, 0, 3) || isShuffleEquivalent(Mask, 1, 3))
7976 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
7977 // We can either use a special instruction to load over the low double or
7978 // to move just the low double.
7980 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
7982 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
7984 if (Subtarget->hasSSE41())
7985 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7989 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7990 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
7991 DAG.getConstant(SHUFPDMask, MVT::i8));
7994 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7996 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7997 /// the integer unit to minimize domain crossing penalties. However, for blends
7998 /// it falls back to the floating point shuffle operation with appropriate bit
8000 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8001 const X86Subtarget *Subtarget,
8002 SelectionDAG &DAG) {
8004 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8005 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8006 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8007 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8008 ArrayRef<int> Mask = SVOp->getMask();
8009 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8011 if (isSingleInputShuffleMask(Mask)) {
8012 // Check for being able to broadcast a single element.
8013 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
8014 Mask, Subtarget, DAG))
8017 // Straight shuffle of a single input vector. For everything from SSE2
8018 // onward this has a single fast instruction with no scary immediates.
8019 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8020 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
8021 int WidenedMask[4] = {
8022 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8023 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8025 ISD::BITCAST, DL, MVT::v2i64,
8026 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
8027 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
8030 // If we have a single input from V2 insert that into V1 if we can do so
8032 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8033 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8034 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
8036 // Try inverting the insertion since for v2 masks it is easy to do and we
8037 // can't reliably sort the mask one way or the other.
8038 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8039 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8040 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8041 MVT::v2i64, DL, V2, V1, InverseMask, Subtarget, DAG))
8045 // Use dedicated unpack instructions for masks that match their pattern.
8046 if (isShuffleEquivalent(Mask, 0, 2))
8047 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8048 if (isShuffleEquivalent(Mask, 1, 3))
8049 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8051 if (Subtarget->hasSSE41())
8052 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8056 // Try to use rotation instructions if available.
8057 if (Subtarget->hasSSSE3())
8058 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8059 DL, MVT::v2i64, V1, V2, Mask, DAG))
8062 // We implement this with SHUFPD which is pretty lame because it will likely
8063 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8064 // However, all the alternatives are still more cycles and newer chips don't
8065 // have this problem. It would be really nice if x86 had better shuffles here.
8066 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
8067 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
8068 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
8069 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8072 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8074 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8075 /// It makes no assumptions about whether this is the *best* lowering, it simply
8077 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8078 ArrayRef<int> Mask, SDValue V1,
8079 SDValue V2, SelectionDAG &DAG) {
8080 SDValue LowV = V1, HighV = V2;
8081 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8084 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8086 if (NumV2Elements == 1) {
8088 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8091 // Compute the index adjacent to V2Index and in the same half by toggling
8093 int V2AdjIndex = V2Index ^ 1;
8095 if (Mask[V2AdjIndex] == -1) {
8096 // Handles all the cases where we have a single V2 element and an undef.
8097 // This will only ever happen in the high lanes because we commute the
8098 // vector otherwise.
8100 std::swap(LowV, HighV);
8101 NewMask[V2Index] -= 4;
8103 // Handle the case where the V2 element ends up adjacent to a V1 element.
8104 // To make this work, blend them together as the first step.
8105 int V1Index = V2AdjIndex;
8106 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8107 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8108 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8110 // Now proceed to reconstruct the final blend as we have the necessary
8111 // high or low half formed.
8118 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8119 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8121 } else if (NumV2Elements == 2) {
8122 if (Mask[0] < 4 && Mask[1] < 4) {
8123 // Handle the easy case where we have V1 in the low lanes and V2 in the
8127 } else if (Mask[2] < 4 && Mask[3] < 4) {
8128 // We also handle the reversed case because this utility may get called
8129 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8130 // arrange things in the right direction.
8136 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8137 // trying to place elements directly, just blend them and set up the final
8138 // shuffle to place them.
8140 // The first two blend mask elements are for V1, the second two are for
8142 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8143 Mask[2] < 4 ? Mask[2] : Mask[3],
8144 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8145 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8146 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8147 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8149 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8152 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8153 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8154 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8155 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8158 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8159 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8162 /// \brief Lower 4-lane 32-bit floating point shuffles.
8164 /// Uses instructions exclusively from the floating point unit to minimize
8165 /// domain crossing penalties, as these are sufficient to implement all v4f32
8167 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8168 const X86Subtarget *Subtarget,
8169 SelectionDAG &DAG) {
8171 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8172 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8173 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8174 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8175 ArrayRef<int> Mask = SVOp->getMask();
8176 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8179 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8181 if (NumV2Elements == 0) {
8182 // Check for being able to broadcast a single element.
8183 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8184 Mask, Subtarget, DAG))
8187 if (Subtarget->hasAVX()) {
8188 // If we have AVX, we can use VPERMILPS which will allow folding a load
8189 // into the shuffle.
8190 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8191 getV4X86ShuffleImm8ForMask(Mask, DAG));
8194 // Otherwise, use a straight shuffle of a single input vector. We pass the
8195 // input vector to both operands to simulate this with a SHUFPS.
8196 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8197 getV4X86ShuffleImm8ForMask(Mask, DAG));
8200 // Use dedicated unpack instructions for masks that match their pattern.
8201 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8202 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8203 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8204 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8206 // There are special ways we can lower some single-element blends. However, we
8207 // have custom ways we can lower more complex single-element blends below that
8208 // we defer to if both this and BLENDPS fail to match, so restrict this to
8209 // when the V2 input is targeting element 0 of the mask -- that is the fast
8211 if (NumV2Elements == 1 && Mask[0] >= 4)
8212 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8213 Mask, Subtarget, DAG))
8216 if (Subtarget->hasSSE41())
8217 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8221 // Check for whether we can use INSERTPS to perform the blend. We only use
8222 // INSERTPS when the V1 elements are already in the correct locations
8223 // because otherwise we can just always use two SHUFPS instructions which
8224 // are much smaller to encode than a SHUFPS and an INSERTPS.
8225 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8227 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8230 // When using INSERTPS we can zero any lane of the destination. Collect
8231 // the zero inputs into a mask and drop them from the lanes of V1 which
8232 // actually need to be present as inputs to the INSERTPS.
8233 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8235 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8236 bool InsertNeedsShuffle = false;
8238 for (int i = 0; i < 4; ++i)
8242 } else if (Mask[i] != i) {
8243 InsertNeedsShuffle = true;
8248 // We don't want to use INSERTPS or other insertion techniques if it will
8249 // require shuffling anyways.
8250 if (!InsertNeedsShuffle) {
8251 // If all of V1 is zeroable, replace it with undef.
8252 if ((ZMask | 1 << V2Index) == 0xF)
8253 V1 = DAG.getUNDEF(MVT::v4f32);
8255 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8256 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8258 // Insert the V2 element into the desired position.
8259 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8260 DAG.getConstant(InsertPSMask, MVT::i8));
8264 // Otherwise fall back to a SHUFPS lowering strategy.
8265 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8268 /// \brief Lower 4-lane i32 vector shuffles.
8270 /// We try to handle these with integer-domain shuffles where we can, but for
8271 /// blends we use the floating point domain blend instructions.
8272 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8273 const X86Subtarget *Subtarget,
8274 SelectionDAG &DAG) {
8276 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8277 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8278 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8279 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8280 ArrayRef<int> Mask = SVOp->getMask();
8281 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8283 // Whenever we can lower this as a zext, that instruction is strictly faster
8284 // than any alternative. It also allows us to fold memory operands into the
8285 // shuffle in many cases.
8286 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8287 Mask, Subtarget, DAG))
8291 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8293 if (NumV2Elements == 0) {
8294 // Check for being able to broadcast a single element.
8295 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8296 Mask, Subtarget, DAG))
8299 // Straight shuffle of a single input vector. For everything from SSE2
8300 // onward this has a single fast instruction with no scary immediates.
8301 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8302 // but we aren't actually going to use the UNPCK instruction because doing
8303 // so prevents folding a load into this instruction or making a copy.
8304 const int UnpackLoMask[] = {0, 0, 1, 1};
8305 const int UnpackHiMask[] = {2, 2, 3, 3};
8306 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8307 Mask = UnpackLoMask;
8308 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8309 Mask = UnpackHiMask;
8311 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8312 getV4X86ShuffleImm8ForMask(Mask, DAG));
8315 // There are special ways we can lower some single-element blends.
8316 if (NumV2Elements == 1)
8317 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8318 Mask, Subtarget, DAG))
8321 // Use dedicated unpack instructions for masks that match their pattern.
8322 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8323 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8324 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8325 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8327 if (Subtarget->hasSSE41())
8328 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8332 // Try to use rotation instructions if available.
8333 if (Subtarget->hasSSSE3())
8334 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8335 DL, MVT::v4i32, V1, V2, Mask, DAG))
8338 // We implement this with SHUFPS because it can blend from two vectors.
8339 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8340 // up the inputs, bypassing domain shift penalties that we would encur if we
8341 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8343 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8344 DAG.getVectorShuffle(
8346 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8347 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8350 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8351 /// shuffle lowering, and the most complex part.
8353 /// The lowering strategy is to try to form pairs of input lanes which are
8354 /// targeted at the same half of the final vector, and then use a dword shuffle
8355 /// to place them onto the right half, and finally unpack the paired lanes into
8356 /// their final position.
8358 /// The exact breakdown of how to form these dword pairs and align them on the
8359 /// correct sides is really tricky. See the comments within the function for
8360 /// more of the details.
8361 static SDValue lowerV8I16SingleInputVectorShuffle(
8362 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8363 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8364 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8365 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8366 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8368 SmallVector<int, 4> LoInputs;
8369 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8370 [](int M) { return M >= 0; });
8371 std::sort(LoInputs.begin(), LoInputs.end());
8372 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8373 SmallVector<int, 4> HiInputs;
8374 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8375 [](int M) { return M >= 0; });
8376 std::sort(HiInputs.begin(), HiInputs.end());
8377 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8379 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8380 int NumHToL = LoInputs.size() - NumLToL;
8382 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8383 int NumHToH = HiInputs.size() - NumLToH;
8384 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8385 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8386 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8387 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8389 // Check for being able to broadcast a single element.
8390 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8391 Mask, Subtarget, DAG))
8394 // Use dedicated unpack instructions for masks that match their pattern.
8395 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8396 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8397 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8398 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8400 // Try to use rotation instructions if available.
8401 if (Subtarget->hasSSSE3())
8402 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8403 DL, MVT::v8i16, V, V, Mask, DAG))
8406 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8407 // such inputs we can swap two of the dwords across the half mark and end up
8408 // with <=2 inputs to each half in each half. Once there, we can fall through
8409 // to the generic code below. For example:
8411 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8412 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8414 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8415 // and an existing 2-into-2 on the other half. In this case we may have to
8416 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8417 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8418 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8419 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8420 // half than the one we target for fixing) will be fixed when we re-enter this
8421 // path. We will also combine away any sequence of PSHUFD instructions that
8422 // result into a single instruction. Here is an example of the tricky case:
8424 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8425 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8427 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8429 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8430 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8432 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8433 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8435 // The result is fine to be handled by the generic logic.
8436 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8437 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8438 int AOffset, int BOffset) {
8439 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8440 "Must call this with A having 3 or 1 inputs from the A half.");
8441 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8442 "Must call this with B having 1 or 3 inputs from the B half.");
8443 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8444 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8446 // Compute the index of dword with only one word among the three inputs in
8447 // a half by taking the sum of the half with three inputs and subtracting
8448 // the sum of the actual three inputs. The difference is the remaining
8451 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8452 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8453 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8454 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8455 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8456 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8457 int TripleNonInputIdx =
8458 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8459 TripleDWord = TripleNonInputIdx / 2;
8461 // We use xor with one to compute the adjacent DWord to whichever one the
8463 OneInputDWord = (OneInput / 2) ^ 1;
8465 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8466 // and BToA inputs. If there is also such a problem with the BToB and AToB
8467 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8468 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8469 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8470 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8471 // Compute how many inputs will be flipped by swapping these DWords. We
8473 // to balance this to ensure we don't form a 3-1 shuffle in the other
8475 int NumFlippedAToBInputs =
8476 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8477 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8478 int NumFlippedBToBInputs =
8479 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8480 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8481 if ((NumFlippedAToBInputs == 1 &&
8482 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8483 (NumFlippedBToBInputs == 1 &&
8484 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8485 // We choose whether to fix the A half or B half based on whether that
8486 // half has zero flipped inputs. At zero, we may not be able to fix it
8487 // with that half. We also bias towards fixing the B half because that
8488 // will more commonly be the high half, and we have to bias one way.
8489 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8490 ArrayRef<int> Inputs) {
8491 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8492 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8493 PinnedIdx ^ 1) != Inputs.end();
8494 // Determine whether the free index is in the flipped dword or the
8495 // unflipped dword based on where the pinned index is. We use this bit
8496 // in an xor to conditionally select the adjacent dword.
8497 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8498 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8499 FixFreeIdx) != Inputs.end();
8500 if (IsFixIdxInput == IsFixFreeIdxInput)
8502 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8503 FixFreeIdx) != Inputs.end();
8504 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8505 "We need to be changing the number of flipped inputs!");
8506 int PSHUFHalfMask[] = {0, 1, 2, 3};
8507 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8508 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8510 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8513 if (M != -1 && M == FixIdx)
8515 else if (M != -1 && M == FixFreeIdx)
8518 if (NumFlippedBToBInputs != 0) {
8520 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8521 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8523 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8525 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8526 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8531 int PSHUFDMask[] = {0, 1, 2, 3};
8532 PSHUFDMask[ADWord] = BDWord;
8533 PSHUFDMask[BDWord] = ADWord;
8534 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8535 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8536 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8537 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8539 // Adjust the mask to match the new locations of A and B.
8541 if (M != -1 && M/2 == ADWord)
8542 M = 2 * BDWord + M % 2;
8543 else if (M != -1 && M/2 == BDWord)
8544 M = 2 * ADWord + M % 2;
8546 // Recurse back into this routine to re-compute state now that this isn't
8547 // a 3 and 1 problem.
8548 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8551 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8552 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8553 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8554 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8556 // At this point there are at most two inputs to the low and high halves from
8557 // each half. That means the inputs can always be grouped into dwords and
8558 // those dwords can then be moved to the correct half with a dword shuffle.
8559 // We use at most one low and one high word shuffle to collect these paired
8560 // inputs into dwords, and finally a dword shuffle to place them.
8561 int PSHUFLMask[4] = {-1, -1, -1, -1};
8562 int PSHUFHMask[4] = {-1, -1, -1, -1};
8563 int PSHUFDMask[4] = {-1, -1, -1, -1};
8565 // First fix the masks for all the inputs that are staying in their
8566 // original halves. This will then dictate the targets of the cross-half
8568 auto fixInPlaceInputs =
8569 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8570 MutableArrayRef<int> SourceHalfMask,
8571 MutableArrayRef<int> HalfMask, int HalfOffset) {
8572 if (InPlaceInputs.empty())
8574 if (InPlaceInputs.size() == 1) {
8575 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8576 InPlaceInputs[0] - HalfOffset;
8577 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8580 if (IncomingInputs.empty()) {
8581 // Just fix all of the in place inputs.
8582 for (int Input : InPlaceInputs) {
8583 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8584 PSHUFDMask[Input / 2] = Input / 2;
8589 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8590 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8591 InPlaceInputs[0] - HalfOffset;
8592 // Put the second input next to the first so that they are packed into
8593 // a dword. We find the adjacent index by toggling the low bit.
8594 int AdjIndex = InPlaceInputs[0] ^ 1;
8595 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8596 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8597 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8599 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8600 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8602 // Now gather the cross-half inputs and place them into a free dword of
8603 // their target half.
8604 // FIXME: This operation could almost certainly be simplified dramatically to
8605 // look more like the 3-1 fixing operation.
8606 auto moveInputsToRightHalf = [&PSHUFDMask](
8607 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8608 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8609 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8611 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8612 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8614 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8616 int LowWord = Word & ~1;
8617 int HighWord = Word | 1;
8618 return isWordClobbered(SourceHalfMask, LowWord) ||
8619 isWordClobbered(SourceHalfMask, HighWord);
8622 if (IncomingInputs.empty())
8625 if (ExistingInputs.empty()) {
8626 // Map any dwords with inputs from them into the right half.
8627 for (int Input : IncomingInputs) {
8628 // If the source half mask maps over the inputs, turn those into
8629 // swaps and use the swapped lane.
8630 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8631 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8632 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8633 Input - SourceOffset;
8634 // We have to swap the uses in our half mask in one sweep.
8635 for (int &M : HalfMask)
8636 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8638 else if (M == Input)
8639 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8641 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8642 Input - SourceOffset &&
8643 "Previous placement doesn't match!");
8645 // Note that this correctly re-maps both when we do a swap and when
8646 // we observe the other side of the swap above. We rely on that to
8647 // avoid swapping the members of the input list directly.
8648 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8651 // Map the input's dword into the correct half.
8652 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8653 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8655 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8657 "Previous placement doesn't match!");
8660 // And just directly shift any other-half mask elements to be same-half
8661 // as we will have mirrored the dword containing the element into the
8662 // same position within that half.
8663 for (int &M : HalfMask)
8664 if (M >= SourceOffset && M < SourceOffset + 4) {
8665 M = M - SourceOffset + DestOffset;
8666 assert(M >= 0 && "This should never wrap below zero!");
8671 // Ensure we have the input in a viable dword of its current half. This
8672 // is particularly tricky because the original position may be clobbered
8673 // by inputs being moved and *staying* in that half.
8674 if (IncomingInputs.size() == 1) {
8675 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8676 int InputFixed = std::find(std::begin(SourceHalfMask),
8677 std::end(SourceHalfMask), -1) -
8678 std::begin(SourceHalfMask) + SourceOffset;
8679 SourceHalfMask[InputFixed - SourceOffset] =
8680 IncomingInputs[0] - SourceOffset;
8681 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8683 IncomingInputs[0] = InputFixed;
8685 } else if (IncomingInputs.size() == 2) {
8686 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8687 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8688 // We have two non-adjacent or clobbered inputs we need to extract from
8689 // the source half. To do this, we need to map them into some adjacent
8690 // dword slot in the source mask.
8691 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8692 IncomingInputs[1] - SourceOffset};
8694 // If there is a free slot in the source half mask adjacent to one of
8695 // the inputs, place the other input in it. We use (Index XOR 1) to
8696 // compute an adjacent index.
8697 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8698 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8699 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8700 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8701 InputsFixed[1] = InputsFixed[0] ^ 1;
8702 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8703 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8704 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8705 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8706 InputsFixed[0] = InputsFixed[1] ^ 1;
8707 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8708 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8709 // The two inputs are in the same DWord but it is clobbered and the
8710 // adjacent DWord isn't used at all. Move both inputs to the free
8712 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8713 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8714 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8715 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8717 // The only way we hit this point is if there is no clobbering
8718 // (because there are no off-half inputs to this half) and there is no
8719 // free slot adjacent to one of the inputs. In this case, we have to
8720 // swap an input with a non-input.
8721 for (int i = 0; i < 4; ++i)
8722 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8723 "We can't handle any clobbers here!");
8724 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8725 "Cannot have adjacent inputs here!");
8727 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8728 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8730 // We also have to update the final source mask in this case because
8731 // it may need to undo the above swap.
8732 for (int &M : FinalSourceHalfMask)
8733 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8734 M = InputsFixed[1] + SourceOffset;
8735 else if (M == InputsFixed[1] + SourceOffset)
8736 M = (InputsFixed[0] ^ 1) + SourceOffset;
8738 InputsFixed[1] = InputsFixed[0] ^ 1;
8741 // Point everything at the fixed inputs.
8742 for (int &M : HalfMask)
8743 if (M == IncomingInputs[0])
8744 M = InputsFixed[0] + SourceOffset;
8745 else if (M == IncomingInputs[1])
8746 M = InputsFixed[1] + SourceOffset;
8748 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8749 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8752 llvm_unreachable("Unhandled input size!");
8755 // Now hoist the DWord down to the right half.
8756 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8757 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8758 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8759 for (int &M : HalfMask)
8760 for (int Input : IncomingInputs)
8762 M = FreeDWord * 2 + Input % 2;
8764 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8765 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8766 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8767 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8769 // Now enact all the shuffles we've computed to move the inputs into their
8771 if (!isNoopShuffleMask(PSHUFLMask))
8772 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8773 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8774 if (!isNoopShuffleMask(PSHUFHMask))
8775 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8776 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8777 if (!isNoopShuffleMask(PSHUFDMask))
8778 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8779 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8780 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8781 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8783 // At this point, each half should contain all its inputs, and we can then
8784 // just shuffle them into their final position.
8785 assert(std::count_if(LoMask.begin(), LoMask.end(),
8786 [](int M) { return M >= 4; }) == 0 &&
8787 "Failed to lift all the high half inputs to the low mask!");
8788 assert(std::count_if(HiMask.begin(), HiMask.end(),
8789 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8790 "Failed to lift all the low half inputs to the high mask!");
8792 // Do a half shuffle for the low mask.
8793 if (!isNoopShuffleMask(LoMask))
8794 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8795 getV4X86ShuffleImm8ForMask(LoMask, DAG));
8797 // Do a half shuffle with the high mask after shifting its values down.
8798 for (int &M : HiMask)
8801 if (!isNoopShuffleMask(HiMask))
8802 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8803 getV4X86ShuffleImm8ForMask(HiMask, DAG));
8808 /// \brief Detect whether the mask pattern should be lowered through
8811 /// This essentially tests whether viewing the mask as an interleaving of two
8812 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
8813 /// lowering it through interleaving is a significantly better strategy.
8814 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
8815 int NumEvenInputs[2] = {0, 0};
8816 int NumOddInputs[2] = {0, 0};
8817 int NumLoInputs[2] = {0, 0};
8818 int NumHiInputs[2] = {0, 0};
8819 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
8823 int InputIdx = Mask[i] >= Size;
8826 ++NumLoInputs[InputIdx];
8828 ++NumHiInputs[InputIdx];
8831 ++NumEvenInputs[InputIdx];
8833 ++NumOddInputs[InputIdx];
8836 // The minimum number of cross-input results for both the interleaved and
8837 // split cases. If interleaving results in fewer cross-input results, return
8839 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
8840 NumEvenInputs[0] + NumOddInputs[1]);
8841 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
8842 NumLoInputs[0] + NumHiInputs[1]);
8843 return InterleavedCrosses < SplitCrosses;
8846 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
8848 /// This strategy only works when the inputs from each vector fit into a single
8849 /// half of that vector, and generally there are not so many inputs as to leave
8850 /// the in-place shuffles required highly constrained (and thus expensive). It
8851 /// shifts all the inputs into a single side of both input vectors and then
8852 /// uses an unpack to interleave these inputs in a single vector. At that
8853 /// point, we will fall back on the generic single input shuffle lowering.
8854 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
8856 MutableArrayRef<int> Mask,
8857 const X86Subtarget *Subtarget,
8858 SelectionDAG &DAG) {
8859 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8860 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8861 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
8862 for (int i = 0; i < 8; ++i)
8863 if (Mask[i] >= 0 && Mask[i] < 4)
8864 LoV1Inputs.push_back(i);
8865 else if (Mask[i] >= 4 && Mask[i] < 8)
8866 HiV1Inputs.push_back(i);
8867 else if (Mask[i] >= 8 && Mask[i] < 12)
8868 LoV2Inputs.push_back(i);
8869 else if (Mask[i] >= 12)
8870 HiV2Inputs.push_back(i);
8872 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
8873 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
8876 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
8877 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
8878 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
8880 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
8881 HiV1Inputs.size() + HiV2Inputs.size();
8883 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
8884 ArrayRef<int> HiInputs, bool MoveToLo,
8886 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
8887 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
8888 if (BadInputs.empty())
8891 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8892 int MoveOffset = MoveToLo ? 0 : 4;
8894 if (GoodInputs.empty()) {
8895 for (int BadInput : BadInputs) {
8896 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
8897 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
8900 if (GoodInputs.size() == 2) {
8901 // If the low inputs are spread across two dwords, pack them into
8903 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
8904 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
8905 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
8906 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
8908 // Otherwise pin the good inputs.
8909 for (int GoodInput : GoodInputs)
8910 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
8913 if (BadInputs.size() == 2) {
8914 // If we have two bad inputs then there may be either one or two good
8915 // inputs fixed in place. Find a fixed input, and then find the *other*
8916 // two adjacent indices by using modular arithmetic.
8918 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
8919 [](int M) { return M >= 0; }) -
8920 std::begin(MoveMask);
8922 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
8923 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
8924 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
8925 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8926 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
8927 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8928 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
8930 assert(BadInputs.size() == 1 && "All sizes handled");
8931 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
8932 std::end(MoveMask), -1) -
8933 std::begin(MoveMask);
8934 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
8935 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
8939 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8942 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
8944 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
8947 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
8948 // cross-half traffic in the final shuffle.
8950 // Munge the mask to be a single-input mask after the unpack merges the
8954 M = 2 * (M % 4) + (M / 8);
8956 return DAG.getVectorShuffle(
8957 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
8958 DL, MVT::v8i16, V1, V2),
8959 DAG.getUNDEF(MVT::v8i16), Mask);
8962 /// \brief Generic lowering of 8-lane i16 shuffles.
8964 /// This handles both single-input shuffles and combined shuffle/blends with
8965 /// two inputs. The single input shuffles are immediately delegated to
8966 /// a dedicated lowering routine.
8968 /// The blends are lowered in one of three fundamental ways. If there are few
8969 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8970 /// of the input is significantly cheaper when lowered as an interleaving of
8971 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8972 /// halves of the inputs separately (making them have relatively few inputs)
8973 /// and then concatenate them.
8974 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8975 const X86Subtarget *Subtarget,
8976 SelectionDAG &DAG) {
8978 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8979 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8980 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8981 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8982 ArrayRef<int> OrigMask = SVOp->getMask();
8983 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8984 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8985 MutableArrayRef<int> Mask(MaskStorage);
8987 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8989 // Whenever we can lower this as a zext, that instruction is strictly faster
8990 // than any alternative.
8991 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8992 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8995 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8996 auto isV2 = [](int M) { return M >= 8; };
8998 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
8999 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9001 if (NumV2Inputs == 0)
9002 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
9004 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
9005 "to be V1-input shuffles.");
9007 // There are special ways we can lower some single-element blends.
9008 if (NumV2Inputs == 1)
9009 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
9010 Mask, Subtarget, DAG))
9013 if (Subtarget->hasSSE41())
9014 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9018 // Try to use rotation instructions if available.
9019 if (Subtarget->hasSSSE3())
9020 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V2, Mask, DAG))
9023 if (NumV1Inputs + NumV2Inputs <= 4)
9024 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
9026 // Check whether an interleaving lowering is likely to be more efficient.
9027 // This isn't perfect but it is a strong heuristic that tends to work well on
9028 // the kinds of shuffles that show up in practice.
9030 // FIXME: Handle 1x, 2x, and 4x interleaving.
9031 if (shouldLowerAsInterleaving(Mask)) {
9032 // FIXME: Figure out whether we should pack these into the low or high
9035 int EMask[8], OMask[8];
9036 for (int i = 0; i < 4; ++i) {
9037 EMask[i] = Mask[2*i];
9038 OMask[i] = Mask[2*i + 1];
9043 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
9044 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
9046 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
9049 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9050 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9052 for (int i = 0; i < 4; ++i) {
9053 LoBlendMask[i] = Mask[i];
9054 HiBlendMask[i] = Mask[i + 4];
9057 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9058 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9059 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
9060 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
9062 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9063 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
9066 /// \brief Check whether a compaction lowering can be done by dropping even
9067 /// elements and compute how many times even elements must be dropped.
9069 /// This handles shuffles which take every Nth element where N is a power of
9070 /// two. Example shuffle masks:
9072 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9073 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9074 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9075 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9076 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9077 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9079 /// Any of these lanes can of course be undef.
9081 /// This routine only supports N <= 3.
9082 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9085 /// \returns N above, or the number of times even elements must be dropped if
9086 /// there is such a number. Otherwise returns zero.
9087 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9088 // Figure out whether we're looping over two inputs or just one.
9089 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9091 // The modulus for the shuffle vector entries is based on whether this is
9092 // a single input or not.
9093 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9094 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9095 "We should only be called with masks with a power-of-2 size!");
9097 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9099 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9100 // and 2^3 simultaneously. This is because we may have ambiguity with
9101 // partially undef inputs.
9102 bool ViableForN[3] = {true, true, true};
9104 for (int i = 0, e = Mask.size(); i < e; ++i) {
9105 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9110 bool IsAnyViable = false;
9111 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9112 if (ViableForN[j]) {
9115 // The shuffle mask must be equal to (i * 2^N) % M.
9116 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9119 ViableForN[j] = false;
9121 // Early exit if we exhaust the possible powers of two.
9126 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9130 // Return 0 as there is no viable power of two.
9134 /// \brief Generic lowering of v16i8 shuffles.
9136 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9137 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9138 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9139 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9141 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9142 const X86Subtarget *Subtarget,
9143 SelectionDAG &DAG) {
9145 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9146 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9147 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9148 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9149 ArrayRef<int> OrigMask = SVOp->getMask();
9150 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9152 // Try to use rotation instructions if available.
9153 if (Subtarget->hasSSSE3())
9154 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v16i8, V1, V2,
9158 // Try to use a zext lowering.
9159 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9160 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9163 int MaskStorage[16] = {
9164 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9165 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9166 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9167 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9168 MutableArrayRef<int> Mask(MaskStorage);
9169 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9170 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9173 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9175 // For single-input shuffles, there are some nicer lowering tricks we can use.
9176 if (NumV2Elements == 0) {
9177 // Check for being able to broadcast a single element.
9178 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9179 Mask, Subtarget, DAG))
9182 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9183 // Notably, this handles splat and partial-splat shuffles more efficiently.
9184 // However, it only makes sense if the pre-duplication shuffle simplifies
9185 // things significantly. Currently, this means we need to be able to
9186 // express the pre-duplication shuffle as an i16 shuffle.
9188 // FIXME: We should check for other patterns which can be widened into an
9189 // i16 shuffle as well.
9190 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9191 for (int i = 0; i < 16; i += 2)
9192 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9197 auto tryToWidenViaDuplication = [&]() -> SDValue {
9198 if (!canWidenViaDuplication(Mask))
9200 SmallVector<int, 4> LoInputs;
9201 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9202 [](int M) { return M >= 0 && M < 8; });
9203 std::sort(LoInputs.begin(), LoInputs.end());
9204 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9206 SmallVector<int, 4> HiInputs;
9207 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9208 [](int M) { return M >= 8; });
9209 std::sort(HiInputs.begin(), HiInputs.end());
9210 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9213 bool TargetLo = LoInputs.size() >= HiInputs.size();
9214 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9215 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9217 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9218 SmallDenseMap<int, int, 8> LaneMap;
9219 for (int I : InPlaceInputs) {
9220 PreDupI16Shuffle[I/2] = I/2;
9223 int j = TargetLo ? 0 : 4, je = j + 4;
9224 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9225 // Check if j is already a shuffle of this input. This happens when
9226 // there are two adjacent bytes after we move the low one.
9227 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9228 // If we haven't yet mapped the input, search for a slot into which
9230 while (j < je && PreDupI16Shuffle[j] != -1)
9234 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9237 // Map this input with the i16 shuffle.
9238 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9241 // Update the lane map based on the mapping we ended up with.
9242 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9245 ISD::BITCAST, DL, MVT::v16i8,
9246 DAG.getVectorShuffle(MVT::v8i16, DL,
9247 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9248 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9250 // Unpack the bytes to form the i16s that will be shuffled into place.
9251 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9252 MVT::v16i8, V1, V1);
9254 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9255 for (int i = 0; i < 16; ++i)
9256 if (Mask[i] != -1) {
9257 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9258 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9259 if (PostDupI16Shuffle[i / 2] == -1)
9260 PostDupI16Shuffle[i / 2] = MappedMask;
9262 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9263 "Conflicting entrties in the original shuffle!");
9266 ISD::BITCAST, DL, MVT::v16i8,
9267 DAG.getVectorShuffle(MVT::v8i16, DL,
9268 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9269 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9271 if (SDValue V = tryToWidenViaDuplication())
9275 // Check whether an interleaving lowering is likely to be more efficient.
9276 // This isn't perfect but it is a strong heuristic that tends to work well on
9277 // the kinds of shuffles that show up in practice.
9279 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9280 if (shouldLowerAsInterleaving(Mask)) {
9281 // FIXME: Figure out whether we should pack these into the low or high
9284 int EMask[16], OMask[16];
9285 for (int i = 0; i < 8; ++i) {
9286 EMask[i] = Mask[2*i];
9287 OMask[i] = Mask[2*i + 1];
9292 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9293 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9295 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, Evens, Odds);
9298 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9299 // with PSHUFB. It is important to do this before we attempt to generate any
9300 // blends but after all of the single-input lowerings. If the single input
9301 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9302 // want to preserve that and we can DAG combine any longer sequences into
9303 // a PSHUFB in the end. But once we start blending from multiple inputs,
9304 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9305 // and there are *very* few patterns that would actually be faster than the
9306 // PSHUFB approach because of its ability to zero lanes.
9308 // FIXME: The only exceptions to the above are blends which are exact
9309 // interleavings with direct instructions supporting them. We currently don't
9310 // handle those well here.
9311 if (Subtarget->hasSSSE3()) {
9314 for (int i = 0; i < 16; ++i)
9315 if (Mask[i] == -1) {
9316 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9318 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9320 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9322 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9323 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9324 if (isSingleInputShuffleMask(Mask))
9325 return V1; // Single inputs are easy.
9327 // Otherwise, blend the two.
9328 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9329 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9330 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9333 // There are special ways we can lower some single-element blends.
9334 if (NumV2Elements == 1)
9335 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9336 Mask, Subtarget, DAG))
9339 // Check whether a compaction lowering can be done. This handles shuffles
9340 // which take every Nth element for some even N. See the helper function for
9343 // We special case these as they can be particularly efficiently handled with
9344 // the PACKUSB instruction on x86 and they show up in common patterns of
9345 // rearranging bytes to truncate wide elements.
9346 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9347 // NumEvenDrops is the power of two stride of the elements. Another way of
9348 // thinking about it is that we need to drop the even elements this many
9349 // times to get the original input.
9350 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9352 // First we need to zero all the dropped bytes.
9353 assert(NumEvenDrops <= 3 &&
9354 "No support for dropping even elements more than 3 times.");
9355 // We use the mask type to pick which bytes are preserved based on how many
9356 // elements are dropped.
9357 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9358 SDValue ByteClearMask =
9359 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9360 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9361 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9363 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9365 // Now pack things back together.
9366 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9367 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9368 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9369 for (int i = 1; i < NumEvenDrops; ++i) {
9370 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9371 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9377 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9378 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9379 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9380 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9382 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9383 MutableArrayRef<int> V1HalfBlendMask,
9384 MutableArrayRef<int> V2HalfBlendMask) {
9385 for (int i = 0; i < 8; ++i)
9386 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9387 V1HalfBlendMask[i] = HalfMask[i];
9389 } else if (HalfMask[i] >= 16) {
9390 V2HalfBlendMask[i] = HalfMask[i] - 16;
9391 HalfMask[i] = i + 8;
9394 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9395 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9397 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9399 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9400 MutableArrayRef<int> HiBlendMask) {
9402 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9403 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9405 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9406 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9407 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9408 [](int M) { return M >= 0 && M % 2 == 1; })) {
9409 // Use a mask to drop the high bytes.
9410 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9411 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9412 DAG.getConstant(0x00FF, MVT::v8i16));
9414 // This will be a single vector shuffle instead of a blend so nuke V2.
9415 V2 = DAG.getUNDEF(MVT::v8i16);
9417 // Squash the masks to point directly into V1.
9418 for (int &M : LoBlendMask)
9421 for (int &M : HiBlendMask)
9425 // Otherwise just unpack the low half of V into V1 and the high half into
9426 // V2 so that we can blend them as i16s.
9427 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9428 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9429 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9430 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9433 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9434 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9435 return std::make_pair(BlendedLo, BlendedHi);
9437 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9438 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9439 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9441 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9442 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9444 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9447 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9449 /// This routine breaks down the specific type of 128-bit shuffle and
9450 /// dispatches to the lowering routines accordingly.
9451 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9452 MVT VT, const X86Subtarget *Subtarget,
9453 SelectionDAG &DAG) {
9454 switch (VT.SimpleTy) {
9456 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9458 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9460 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9462 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9464 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9466 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9469 llvm_unreachable("Unimplemented!");
9473 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9475 /// This routine just extracts two subvectors, shuffles them independently, and
9476 /// then concatenates them back together. This should work effectively with all
9477 /// AVX vector shuffle types.
9478 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9479 SDValue V2, ArrayRef<int> Mask,
9480 SelectionDAG &DAG) {
9481 assert(VT.getSizeInBits() >= 256 &&
9482 "Only for 256-bit or wider vector shuffles!");
9483 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9484 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9486 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9487 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9489 int NumElements = VT.getVectorNumElements();
9490 int SplitNumElements = NumElements / 2;
9491 MVT ScalarVT = VT.getScalarType();
9492 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9494 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9495 DAG.getIntPtrConstant(0));
9496 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9497 DAG.getIntPtrConstant(SplitNumElements));
9498 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9499 DAG.getIntPtrConstant(0));
9500 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9501 DAG.getIntPtrConstant(SplitNumElements));
9503 // Now create two 4-way blends of these half-width vectors.
9504 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9505 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9506 for (int i = 0; i < SplitNumElements; ++i) {
9507 int M = HalfMask[i];
9508 if (M >= NumElements) {
9509 V2BlendMask.push_back(M - NumElements);
9510 V1BlendMask.push_back(-1);
9511 BlendMask.push_back(SplitNumElements + i);
9512 } else if (M >= 0) {
9513 V2BlendMask.push_back(-1);
9514 V1BlendMask.push_back(M);
9515 BlendMask.push_back(i);
9517 V2BlendMask.push_back(-1);
9518 V1BlendMask.push_back(-1);
9519 BlendMask.push_back(-1);
9523 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9525 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9526 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9528 SDValue Lo = HalfBlend(LoMask);
9529 SDValue Hi = HalfBlend(HiMask);
9530 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9533 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9534 /// a permutation and blend of those lanes.
9536 /// This essentially blends the out-of-lane inputs to each lane into the lane
9537 /// from a permuted copy of the vector. This lowering strategy results in four
9538 /// instructions in the worst case for a single-input cross lane shuffle which
9539 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9540 /// of. Special cases for each particular shuffle pattern should be handled
9541 /// prior to trying this lowering.
9542 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9543 SDValue V1, SDValue V2,
9545 SelectionDAG &DAG) {
9546 // FIXME: This should probably be generalized for 512-bit vectors as well.
9547 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9548 int LaneSize = Mask.size() / 2;
9550 // If there are only inputs from one 128-bit lane, splitting will in fact be
9551 // less expensive. The flags track wether the given lane contains an element
9552 // that crosses to another lane.
9553 bool LaneCrossing[2] = {false, false};
9554 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9555 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9556 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9557 if (!LaneCrossing[0] || !LaneCrossing[1])
9558 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9560 if (isSingleInputShuffleMask(Mask)) {
9561 SmallVector<int, 32> FlippedBlendMask;
9562 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9563 FlippedBlendMask.push_back(
9564 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9566 : Mask[i] % LaneSize +
9567 (i / LaneSize) * LaneSize + Size));
9569 // Flip the vector, and blend the results which should now be in-lane. The
9570 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9571 // 5 for the high source. The value 3 selects the high half of source 2 and
9572 // the value 2 selects the low half of source 2. We only use source 2 to
9573 // allow folding it into a memory operand.
9574 unsigned PERMMask = 3 | 2 << 4;
9575 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9576 V1, DAG.getConstant(PERMMask, MVT::i8));
9577 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9580 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9581 // will be handled by the above logic and a blend of the results, much like
9582 // other patterns in AVX.
9583 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9586 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9588 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9589 /// isn't available.
9590 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9591 const X86Subtarget *Subtarget,
9592 SelectionDAG &DAG) {
9594 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9595 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9596 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9597 ArrayRef<int> Mask = SVOp->getMask();
9598 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9600 if (isSingleInputShuffleMask(Mask)) {
9601 // Check for being able to broadcast a single element.
9602 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
9603 Mask, Subtarget, DAG))
9606 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9607 // Non-half-crossing single input shuffles can be lowerid with an
9608 // interleaved permutation.
9609 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9610 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9611 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9612 DAG.getConstant(VPERMILPMask, MVT::i8));
9615 // With AVX2 we have direct support for this permutation.
9616 if (Subtarget->hasAVX2())
9617 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9618 getV4X86ShuffleImm8ForMask(Mask, DAG));
9620 // Otherwise, fall back.
9621 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9625 // X86 has dedicated unpack instructions that can handle specific blend
9626 // operations: UNPCKH and UNPCKL.
9627 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9628 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9629 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9630 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9632 // If we have a single input to the zero element, insert that into V1 if we
9633 // can do so cheaply.
9635 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
9636 if (NumV2Elements == 1 && Mask[0] >= 4)
9637 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
9638 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
9641 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9645 // Check if the blend happens to exactly fit that of SHUFPD.
9646 if ((Mask[0] == -1 || Mask[0] < 2) &&
9647 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
9648 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
9649 (Mask[3] == -1 || Mask[3] >= 6)) {
9650 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
9651 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
9652 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
9653 DAG.getConstant(SHUFPDMask, MVT::i8));
9655 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
9656 (Mask[1] == -1 || Mask[1] < 2) &&
9657 (Mask[2] == -1 || Mask[2] >= 6) &&
9658 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
9659 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
9660 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
9661 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
9662 DAG.getConstant(SHUFPDMask, MVT::i8));
9665 // Otherwise fall back on generic blend lowering.
9666 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9670 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9672 /// This routine is only called when we have AVX2 and thus a reasonable
9673 /// instruction set for v4i64 shuffling..
9674 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9675 const X86Subtarget *Subtarget,
9676 SelectionDAG &DAG) {
9678 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9679 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9680 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9681 ArrayRef<int> Mask = SVOp->getMask();
9682 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9683 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9685 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9689 // Check for being able to broadcast a single element.
9690 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
9691 Mask, Subtarget, DAG))
9694 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9695 // use lower latency instructions that will operate on both 128-bit lanes.
9696 SmallVector<int, 2> RepeatedMask;
9697 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9698 if (isSingleInputShuffleMask(Mask)) {
9699 int PSHUFDMask[] = {-1, -1, -1, -1};
9700 for (int i = 0; i < 2; ++i)
9701 if (RepeatedMask[i] >= 0) {
9702 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9703 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9706 ISD::BITCAST, DL, MVT::v4i64,
9707 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9708 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
9709 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
9712 // Use dedicated unpack instructions for masks that match their pattern.
9713 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
9714 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9715 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
9716 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9719 // AVX2 provides a direct instruction for permuting a single input across
9721 if (isSingleInputShuffleMask(Mask))
9722 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9723 getV4X86ShuffleImm8ForMask(Mask, DAG));
9725 // Otherwise fall back on generic blend lowering.
9726 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9730 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9732 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9733 /// isn't available.
9734 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9735 const X86Subtarget *Subtarget,
9736 SelectionDAG &DAG) {
9738 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9739 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9740 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9741 ArrayRef<int> Mask = SVOp->getMask();
9742 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9744 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9748 // Check for being able to broadcast a single element.
9749 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
9750 Mask, Subtarget, DAG))
9753 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9754 // options to efficiently lower the shuffle.
9755 SmallVector<int, 4> RepeatedMask;
9756 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9757 assert(RepeatedMask.size() == 4 &&
9758 "Repeated masks must be half the mask width!");
9759 if (isSingleInputShuffleMask(Mask))
9760 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9761 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9763 // Use dedicated unpack instructions for masks that match their pattern.
9764 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
9765 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9766 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
9767 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9769 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9770 // have already handled any direct blends. We also need to squash the
9771 // repeated mask into a simulated v4f32 mask.
9772 for (int i = 0; i < 4; ++i)
9773 if (RepeatedMask[i] >= 8)
9774 RepeatedMask[i] -= 4;
9775 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
9778 // If we have a single input shuffle with different shuffle patterns in the
9779 // two 128-bit lanes use the variable mask to VPERMILPS.
9780 if (isSingleInputShuffleMask(Mask)) {
9781 SDValue VPermMask[8];
9782 for (int i = 0; i < 8; ++i)
9783 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9784 : DAG.getConstant(Mask[i], MVT::i32);
9785 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9787 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9788 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9790 if (Subtarget->hasAVX2())
9791 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
9792 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
9793 DAG.getNode(ISD::BUILD_VECTOR, DL,
9794 MVT::v8i32, VPermMask)),
9797 // Otherwise, fall back.
9798 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
9802 // Otherwise fall back on generic blend lowering.
9803 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9807 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9809 /// This routine is only called when we have AVX2 and thus a reasonable
9810 /// instruction set for v8i32 shuffling..
9811 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9812 const X86Subtarget *Subtarget,
9813 SelectionDAG &DAG) {
9815 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9816 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9817 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9818 ArrayRef<int> Mask = SVOp->getMask();
9819 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9820 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9822 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
9826 // Check for being able to broadcast a single element.
9827 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
9828 Mask, Subtarget, DAG))
9831 // If the shuffle mask is repeated in each 128-bit lane we can use more
9832 // efficient instructions that mirror the shuffles across the two 128-bit
9834 SmallVector<int, 4> RepeatedMask;
9835 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
9836 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
9837 if (isSingleInputShuffleMask(Mask))
9838 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
9839 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
9841 // Use dedicated unpack instructions for masks that match their pattern.
9842 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
9843 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
9844 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
9845 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
9848 // If the shuffle patterns aren't repeated but it is a single input, directly
9849 // generate a cross-lane VPERMD instruction.
9850 if (isSingleInputShuffleMask(Mask)) {
9851 SDValue VPermMask[8];
9852 for (int i = 0; i < 8; ++i)
9853 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9854 : DAG.getConstant(Mask[i], MVT::i32);
9856 X86ISD::VPERMV, DL, MVT::v8i32,
9857 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
9860 // Otherwise fall back on generic blend lowering.
9861 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
9865 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
9867 /// This routine is only called when we have AVX2 and thus a reasonable
9868 /// instruction set for v16i16 shuffling..
9869 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9870 const X86Subtarget *Subtarget,
9871 SelectionDAG &DAG) {
9873 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9874 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9875 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9876 ArrayRef<int> Mask = SVOp->getMask();
9877 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9878 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
9880 // Check for being able to broadcast a single element.
9881 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
9882 Mask, Subtarget, DAG))
9885 // There are no generalized cross-lane shuffle operations available on i16
9887 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
9888 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
9891 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
9895 // Use dedicated unpack instructions for masks that match their pattern.
9896 if (isShuffleEquivalent(Mask,
9897 // First 128-bit lane:
9898 0, 16, 1, 17, 2, 18, 3, 19,
9899 // Second 128-bit lane:
9900 8, 24, 9, 25, 10, 26, 11, 27))
9901 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
9902 if (isShuffleEquivalent(Mask,
9903 // First 128-bit lane:
9904 4, 20, 5, 21, 6, 22, 7, 23,
9905 // Second 128-bit lane:
9906 12, 28, 13, 29, 14, 30, 15, 31))
9907 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
9909 if (isSingleInputShuffleMask(Mask)) {
9910 SDValue PSHUFBMask[32];
9911 for (int i = 0; i < 16; ++i) {
9912 if (Mask[i] == -1) {
9913 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
9917 int M = i < 8 ? Mask[i] : Mask[i] - 8;
9918 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
9919 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
9920 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
9923 ISD::BITCAST, DL, MVT::v16i16,
9925 X86ISD::PSHUFB, DL, MVT::v32i8,
9926 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
9927 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
9930 // Otherwise fall back on generic blend lowering.
9931 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i16, V1, V2,
9935 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
9937 /// This routine is only called when we have AVX2 and thus a reasonable
9938 /// instruction set for v32i8 shuffling..
9939 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9940 const X86Subtarget *Subtarget,
9941 SelectionDAG &DAG) {
9943 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9944 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9945 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9946 ArrayRef<int> Mask = SVOp->getMask();
9947 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9948 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
9950 // Check for being able to broadcast a single element.
9951 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
9952 Mask, Subtarget, DAG))
9955 // There are no generalized cross-lane shuffle operations available on i8
9957 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
9958 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
9961 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
9965 // Use dedicated unpack instructions for masks that match their pattern.
9966 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
9968 if (isShuffleEquivalent(
9970 // First 128-bit lane:
9971 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
9972 // Second 128-bit lane:
9973 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
9974 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
9975 if (isShuffleEquivalent(
9977 // First 128-bit lane:
9978 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
9979 // Second 128-bit lane:
9980 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
9981 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
9983 if (isSingleInputShuffleMask(Mask)) {
9984 SDValue PSHUFBMask[32];
9985 for (int i = 0; i < 32; ++i)
9988 ? DAG.getUNDEF(MVT::i8)
9989 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
9992 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
9993 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
9996 // Otherwise fall back on generic blend lowering.
9997 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v32i8, V1, V2,
10001 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10003 /// This routine either breaks down the specific type of a 256-bit x86 vector
10004 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10005 /// together based on the available instructions.
10006 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10007 MVT VT, const X86Subtarget *Subtarget,
10008 SelectionDAG &DAG) {
10010 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10011 ArrayRef<int> Mask = SVOp->getMask();
10013 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10014 // check for those subtargets here and avoid much of the subtarget querying in
10015 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10016 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10017 // floating point types there eventually, just immediately cast everything to
10018 // a float and operate entirely in that domain.
10019 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10020 int ElementBits = VT.getScalarSizeInBits();
10021 if (ElementBits < 32)
10022 // No floating point type available, decompose into 128-bit vectors.
10023 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10025 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10026 VT.getVectorNumElements());
10027 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10028 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10029 return DAG.getNode(ISD::BITCAST, DL, VT,
10030 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10033 switch (VT.SimpleTy) {
10035 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10037 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10039 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10041 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10043 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10045 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10048 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10052 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10053 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10054 const X86Subtarget *Subtarget,
10055 SelectionDAG &DAG) {
10057 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10058 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10059 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10060 ArrayRef<int> Mask = SVOp->getMask();
10061 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10063 // FIXME: Implement direct support for this type!
10064 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10067 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10068 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10069 const X86Subtarget *Subtarget,
10070 SelectionDAG &DAG) {
10072 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10073 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10074 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10075 ArrayRef<int> Mask = SVOp->getMask();
10076 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10078 // FIXME: Implement direct support for this type!
10079 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10082 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10083 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10084 const X86Subtarget *Subtarget,
10085 SelectionDAG &DAG) {
10087 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10088 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10089 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10090 ArrayRef<int> Mask = SVOp->getMask();
10091 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10092 assert(Subtarget->hasDQI() && "We can only lower v8i64 with AVX-512-DQI");
10094 // FIXME: Implement direct support for this type!
10095 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10098 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10099 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10100 const X86Subtarget *Subtarget,
10101 SelectionDAG &DAG) {
10103 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10104 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10105 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10106 ArrayRef<int> Mask = SVOp->getMask();
10107 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10108 assert(Subtarget->hasDQI() && "We can only lower v16i32 with AVX-512-DQI!");
10110 // FIXME: Implement direct support for this type!
10111 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10114 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10115 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10116 const X86Subtarget *Subtarget,
10117 SelectionDAG &DAG) {
10119 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10120 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10121 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10122 ArrayRef<int> Mask = SVOp->getMask();
10123 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10124 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10126 // FIXME: Implement direct support for this type!
10127 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10130 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10131 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10132 const X86Subtarget *Subtarget,
10133 SelectionDAG &DAG) {
10135 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10136 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10137 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10138 ArrayRef<int> Mask = SVOp->getMask();
10139 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10140 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10142 // FIXME: Implement direct support for this type!
10143 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10146 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10148 /// This routine either breaks down the specific type of a 512-bit x86 vector
10149 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10150 /// together based on the available instructions.
10151 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10152 MVT VT, const X86Subtarget *Subtarget,
10153 SelectionDAG &DAG) {
10155 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10156 ArrayRef<int> Mask = SVOp->getMask();
10157 assert(Subtarget->hasAVX512() &&
10158 "Cannot lower 512-bit vectors w/ basic ISA!");
10160 // Dispatch to each element type for lowering. If we don't have supprot for
10161 // specific element type shuffles at 512 bits, immediately split them and
10162 // lower them. Each lowering routine of a given type is allowed to assume that
10163 // the requisite ISA extensions for that element type are available.
10164 switch (VT.SimpleTy) {
10166 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10168 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10170 if (Subtarget->hasDQI())
10171 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10174 if (Subtarget->hasDQI())
10175 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10178 if (Subtarget->hasBWI())
10179 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10182 if (Subtarget->hasBWI())
10183 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10187 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10190 // Otherwise fall back on splitting.
10191 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10194 /// \brief Helper function to test whether a shuffle mask could be
10195 /// simplified by widening the elements being shuffled.
10197 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
10198 /// leaves it in an unspecified state.
10200 /// NOTE: This must handle normal vector shuffle masks and *target* vector
10201 /// shuffle masks. The latter have the special property of a '-2' representing
10202 /// a zero-ed lane of a vector.
10203 static bool canWidenShuffleElements(ArrayRef<int> Mask,
10204 SmallVectorImpl<int> &WidenedMask) {
10205 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
10206 // If both elements are undef, its trivial.
10207 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
10208 WidenedMask.push_back(SM_SentinelUndef);
10212 // Check for an undef mask and a mask value properly aligned to fit with
10213 // a pair of values. If we find such a case, use the non-undef mask's value.
10214 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
10215 WidenedMask.push_back(Mask[i + 1] / 2);
10218 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
10219 WidenedMask.push_back(Mask[i] / 2);
10223 // When zeroing, we need to spread the zeroing across both lanes to widen.
10224 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
10225 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
10226 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
10227 WidenedMask.push_back(SM_SentinelZero);
10233 // Finally check if the two mask values are adjacent and aligned with
10235 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
10236 WidenedMask.push_back(Mask[i] / 2);
10240 // Otherwise we can't safely widen the elements used in this shuffle.
10243 assert(WidenedMask.size() == Mask.size() / 2 &&
10244 "Incorrect size of mask after widening the elements!");
10249 /// \brief Top-level lowering for x86 vector shuffles.
10251 /// This handles decomposition, canonicalization, and lowering of all x86
10252 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10253 /// above in helper routines. The canonicalization attempts to widen shuffles
10254 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10255 /// s.t. only one of the two inputs needs to be tested, etc.
10256 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10257 SelectionDAG &DAG) {
10258 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10259 ArrayRef<int> Mask = SVOp->getMask();
10260 SDValue V1 = Op.getOperand(0);
10261 SDValue V2 = Op.getOperand(1);
10262 MVT VT = Op.getSimpleValueType();
10263 int NumElements = VT.getVectorNumElements();
10266 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10268 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10269 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10270 if (V1IsUndef && V2IsUndef)
10271 return DAG.getUNDEF(VT);
10273 // When we create a shuffle node we put the UNDEF node to second operand,
10274 // but in some cases the first operand may be transformed to UNDEF.
10275 // In this case we should just commute the node.
10277 return DAG.getCommutedVectorShuffle(*SVOp);
10279 // Check for non-undef masks pointing at an undef vector and make the masks
10280 // undef as well. This makes it easier to match the shuffle based solely on
10284 if (M >= NumElements) {
10285 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10286 for (int &M : NewMask)
10287 if (M >= NumElements)
10289 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10292 // Try to collapse shuffles into using a vector type with fewer elements but
10293 // wider element types. We cap this to not form integers or floating point
10294 // elements wider than 64 bits, but it might be interesting to form i128
10295 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10296 SmallVector<int, 16> WidenedMask;
10297 if (VT.getScalarSizeInBits() < 64 &&
10298 canWidenShuffleElements(Mask, WidenedMask)) {
10299 MVT NewEltVT = VT.isFloatingPoint()
10300 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10301 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10302 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10303 // Make sure that the new vector type is legal. For example, v2f64 isn't
10305 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10306 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10307 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10308 return DAG.getNode(ISD::BITCAST, dl, VT,
10309 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10313 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10314 for (int M : SVOp->getMask())
10316 ++NumUndefElements;
10317 else if (M < NumElements)
10322 // Commute the shuffle as needed such that more elements come from V1 than
10323 // V2. This allows us to match the shuffle pattern strictly on how many
10324 // elements come from V1 without handling the symmetric cases.
10325 if (NumV2Elements > NumV1Elements)
10326 return DAG.getCommutedVectorShuffle(*SVOp);
10328 // When the number of V1 and V2 elements are the same, try to minimize the
10329 // number of uses of V2 in the low half of the vector. When that is tied,
10330 // ensure that the sum of indices for V1 is equal to or lower than the sum
10332 if (NumV1Elements == NumV2Elements) {
10333 int LowV1Elements = 0, LowV2Elements = 0;
10334 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10335 if (M >= NumElements)
10339 if (LowV2Elements > LowV1Elements) {
10340 return DAG.getCommutedVectorShuffle(*SVOp);
10341 } else if (LowV2Elements == LowV1Elements) {
10342 int SumV1Indices = 0, SumV2Indices = 0;
10343 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10344 if (SVOp->getMask()[i] >= NumElements)
10346 else if (SVOp->getMask()[i] >= 0)
10348 if (SumV2Indices < SumV1Indices)
10349 return DAG.getCommutedVectorShuffle(*SVOp);
10353 // For each vector width, delegate to a specialized lowering routine.
10354 if (VT.getSizeInBits() == 128)
10355 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10357 if (VT.getSizeInBits() == 256)
10358 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10360 // Force AVX-512 vectors to be scalarized for now.
10361 // FIXME: Implement AVX-512 support!
10362 if (VT.getSizeInBits() == 512)
10363 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10365 llvm_unreachable("Unimplemented!");
10369 //===----------------------------------------------------------------------===//
10370 // Legacy vector shuffle lowering
10372 // This code is the legacy code handling vector shuffles until the above
10373 // replaces its functionality and performance.
10374 //===----------------------------------------------------------------------===//
10376 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10377 bool hasInt256, unsigned *MaskOut = nullptr) {
10378 MVT EltVT = VT.getVectorElementType();
10380 // There is no blend with immediate in AVX-512.
10381 if (VT.is512BitVector())
10384 if (!hasSSE41 || EltVT == MVT::i8)
10386 if (!hasInt256 && VT == MVT::v16i16)
10389 unsigned MaskValue = 0;
10390 unsigned NumElems = VT.getVectorNumElements();
10391 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10392 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10393 unsigned NumElemsInLane = NumElems / NumLanes;
10395 // Blend for v16i16 should be symetric for the both lanes.
10396 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10398 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10399 int EltIdx = MaskVals[i];
10401 if ((EltIdx < 0 || EltIdx == (int)i) &&
10402 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10405 if (((unsigned)EltIdx == (i + NumElems)) &&
10406 (SndLaneEltIdx < 0 ||
10407 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10408 MaskValue |= (1 << i);
10414 *MaskOut = MaskValue;
10418 // Try to lower a shuffle node into a simple blend instruction.
10419 // This function assumes isBlendMask returns true for this
10420 // SuffleVectorSDNode
10421 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
10422 unsigned MaskValue,
10423 const X86Subtarget *Subtarget,
10424 SelectionDAG &DAG) {
10425 MVT VT = SVOp->getSimpleValueType(0);
10426 MVT EltVT = VT.getVectorElementType();
10427 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
10428 Subtarget->hasInt256() && "Trying to lower a "
10429 "VECTOR_SHUFFLE to a Blend but "
10430 "with the wrong mask"));
10431 SDValue V1 = SVOp->getOperand(0);
10432 SDValue V2 = SVOp->getOperand(1);
10434 unsigned NumElems = VT.getVectorNumElements();
10436 // Convert i32 vectors to floating point if it is not AVX2.
10437 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10439 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10440 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10442 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
10443 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
10446 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
10447 DAG.getConstant(MaskValue, MVT::i32));
10448 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10451 /// In vector type \p VT, return true if the element at index \p InputIdx
10452 /// falls on a different 128-bit lane than \p OutputIdx.
10453 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
10454 unsigned OutputIdx) {
10455 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
10456 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
10459 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
10460 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
10461 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
10462 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
10464 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
10465 SelectionDAG &DAG) {
10466 MVT VT = V1.getSimpleValueType();
10467 assert(VT.is128BitVector() || VT.is256BitVector());
10469 MVT EltVT = VT.getVectorElementType();
10470 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
10471 unsigned NumElts = VT.getVectorNumElements();
10473 SmallVector<SDValue, 32> PshufbMask;
10474 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
10475 int InputIdx = MaskVals[OutputIdx];
10476 unsigned InputByteIdx;
10478 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
10479 InputByteIdx = 0x80;
10481 // Cross lane is not allowed.
10482 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
10484 InputByteIdx = InputIdx * EltSizeInBytes;
10485 // Index is an byte offset within the 128-bit lane.
10486 InputByteIdx &= 0xf;
10489 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
10490 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
10491 if (InputByteIdx != 0x80)
10496 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
10498 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
10499 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
10500 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
10503 // v8i16 shuffles - Prefer shuffles in the following order:
10504 // 1. [all] pshuflw, pshufhw, optional move
10505 // 2. [ssse3] 1 x pshufb
10506 // 3. [ssse3] 2 x pshufb + 1 x por
10507 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
10509 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
10510 SelectionDAG &DAG) {
10511 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10512 SDValue V1 = SVOp->getOperand(0);
10513 SDValue V2 = SVOp->getOperand(1);
10515 SmallVector<int, 8> MaskVals;
10517 // Determine if more than 1 of the words in each of the low and high quadwords
10518 // of the result come from the same quadword of one of the two inputs. Undef
10519 // mask values count as coming from any quadword, for better codegen.
10521 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
10522 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
10523 unsigned LoQuad[] = { 0, 0, 0, 0 };
10524 unsigned HiQuad[] = { 0, 0, 0, 0 };
10525 // Indices of quads used.
10526 std::bitset<4> InputQuads;
10527 for (unsigned i = 0; i < 8; ++i) {
10528 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
10529 int EltIdx = SVOp->getMaskElt(i);
10530 MaskVals.push_back(EltIdx);
10538 ++Quad[EltIdx / 4];
10539 InputQuads.set(EltIdx / 4);
10542 int BestLoQuad = -1;
10543 unsigned MaxQuad = 1;
10544 for (unsigned i = 0; i < 4; ++i) {
10545 if (LoQuad[i] > MaxQuad) {
10547 MaxQuad = LoQuad[i];
10551 int BestHiQuad = -1;
10553 for (unsigned i = 0; i < 4; ++i) {
10554 if (HiQuad[i] > MaxQuad) {
10556 MaxQuad = HiQuad[i];
10560 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
10561 // of the two input vectors, shuffle them into one input vector so only a
10562 // single pshufb instruction is necessary. If there are more than 2 input
10563 // quads, disable the next transformation since it does not help SSSE3.
10564 bool V1Used = InputQuads[0] || InputQuads[1];
10565 bool V2Used = InputQuads[2] || InputQuads[3];
10566 if (Subtarget->hasSSSE3()) {
10567 if (InputQuads.count() == 2 && V1Used && V2Used) {
10568 BestLoQuad = InputQuads[0] ? 0 : 1;
10569 BestHiQuad = InputQuads[2] ? 2 : 3;
10571 if (InputQuads.count() > 2) {
10577 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
10578 // the shuffle mask. If a quad is scored as -1, that means that it contains
10579 // words from all 4 input quadwords.
10581 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
10583 BestLoQuad < 0 ? 0 : BestLoQuad,
10584 BestHiQuad < 0 ? 1 : BestHiQuad
10586 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
10587 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
10588 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
10589 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
10591 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
10592 // source words for the shuffle, to aid later transformations.
10593 bool AllWordsInNewV = true;
10594 bool InOrder[2] = { true, true };
10595 for (unsigned i = 0; i != 8; ++i) {
10596 int idx = MaskVals[i];
10598 InOrder[i/4] = false;
10599 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
10601 AllWordsInNewV = false;
10605 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
10606 if (AllWordsInNewV) {
10607 for (int i = 0; i != 8; ++i) {
10608 int idx = MaskVals[i];
10611 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
10612 if ((idx != i) && idx < 4)
10614 if ((idx != i) && idx > 3)
10623 // If we've eliminated the use of V2, and the new mask is a pshuflw or
10624 // pshufhw, that's as cheap as it gets. Return the new shuffle.
10625 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
10626 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
10627 unsigned TargetMask = 0;
10628 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
10629 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
10630 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10631 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
10632 getShufflePSHUFLWImmediate(SVOp);
10633 V1 = NewV.getOperand(0);
10634 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
10638 // Promote splats to a larger type which usually leads to more efficient code.
10639 // FIXME: Is this true if pshufb is available?
10640 if (SVOp->isSplat())
10641 return PromoteSplat(SVOp, DAG);
10643 // If we have SSSE3, and all words of the result are from 1 input vector,
10644 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
10645 // is present, fall back to case 4.
10646 if (Subtarget->hasSSSE3()) {
10647 SmallVector<SDValue,16> pshufbMask;
10649 // If we have elements from both input vectors, set the high bit of the
10650 // shuffle mask element to zero out elements that come from V2 in the V1
10651 // mask, and elements that come from V1 in the V2 mask, so that the two
10652 // results can be OR'd together.
10653 bool TwoInputs = V1Used && V2Used;
10654 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
10656 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10658 // Calculate the shuffle mask for the second input, shuffle it, and
10659 // OR it with the first shuffled input.
10660 CommuteVectorShuffleMask(MaskVals, 8);
10661 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
10662 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10663 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10666 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
10667 // and update MaskVals with new element order.
10668 std::bitset<8> InOrder;
10669 if (BestLoQuad >= 0) {
10670 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
10671 for (int i = 0; i != 4; ++i) {
10672 int idx = MaskVals[i];
10675 } else if ((idx / 4) == BestLoQuad) {
10676 MaskV[i] = idx & 3;
10680 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10683 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10684 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10685 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
10686 NewV.getOperand(0),
10687 getShufflePSHUFLWImmediate(SVOp), DAG);
10691 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
10692 // and update MaskVals with the new element order.
10693 if (BestHiQuad >= 0) {
10694 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
10695 for (unsigned i = 4; i != 8; ++i) {
10696 int idx = MaskVals[i];
10699 } else if ((idx / 4) == BestHiQuad) {
10700 MaskV[i] = (idx & 3) + 4;
10704 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
10707 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
10708 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
10709 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
10710 NewV.getOperand(0),
10711 getShufflePSHUFHWImmediate(SVOp), DAG);
10715 // In case BestHi & BestLo were both -1, which means each quadword has a word
10716 // from each of the four input quadwords, calculate the InOrder bitvector now
10717 // before falling through to the insert/extract cleanup.
10718 if (BestLoQuad == -1 && BestHiQuad == -1) {
10720 for (int i = 0; i != 8; ++i)
10721 if (MaskVals[i] < 0 || MaskVals[i] == i)
10725 // The other elements are put in the right place using pextrw and pinsrw.
10726 for (unsigned i = 0; i != 8; ++i) {
10729 int EltIdx = MaskVals[i];
10732 SDValue ExtOp = (EltIdx < 8) ?
10733 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
10734 DAG.getIntPtrConstant(EltIdx)) :
10735 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
10736 DAG.getIntPtrConstant(EltIdx - 8));
10737 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
10738 DAG.getIntPtrConstant(i));
10743 /// \brief v16i16 shuffles
10745 /// FIXME: We only support generation of a single pshufb currently. We can
10746 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
10747 /// well (e.g 2 x pshufb + 1 x por).
10749 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
10750 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10751 SDValue V1 = SVOp->getOperand(0);
10752 SDValue V2 = SVOp->getOperand(1);
10755 if (V2.getOpcode() != ISD::UNDEF)
10758 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10759 return getPSHUFB(MaskVals, V1, dl, DAG);
10762 // v16i8 shuffles - Prefer shuffles in the following order:
10763 // 1. [ssse3] 1 x pshufb
10764 // 2. [ssse3] 2 x pshufb + 1 x por
10765 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
10766 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
10767 const X86Subtarget* Subtarget,
10768 SelectionDAG &DAG) {
10769 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10770 SDValue V1 = SVOp->getOperand(0);
10771 SDValue V2 = SVOp->getOperand(1);
10773 ArrayRef<int> MaskVals = SVOp->getMask();
10775 // Promote splats to a larger type which usually leads to more efficient code.
10776 // FIXME: Is this true if pshufb is available?
10777 if (SVOp->isSplat())
10778 return PromoteSplat(SVOp, DAG);
10780 // If we have SSSE3, case 1 is generated when all result bytes come from
10781 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
10782 // present, fall back to case 3.
10784 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
10785 if (Subtarget->hasSSSE3()) {
10786 SmallVector<SDValue,16> pshufbMask;
10788 // If all result elements are from one input vector, then only translate
10789 // undef mask values to 0x80 (zero out result) in the pshufb mask.
10791 // Otherwise, we have elements from both input vectors, and must zero out
10792 // elements that come from V2 in the first mask, and V1 in the second mask
10793 // so that we can OR them together.
10794 for (unsigned i = 0; i != 16; ++i) {
10795 int EltIdx = MaskVals[i];
10796 if (EltIdx < 0 || EltIdx >= 16)
10798 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10800 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
10801 DAG.getNode(ISD::BUILD_VECTOR, dl,
10802 MVT::v16i8, pshufbMask));
10804 // As PSHUFB will zero elements with negative indices, it's safe to ignore
10805 // the 2nd operand if it's undefined or zero.
10806 if (V2.getOpcode() == ISD::UNDEF ||
10807 ISD::isBuildVectorAllZeros(V2.getNode()))
10810 // Calculate the shuffle mask for the second input, shuffle it, and
10811 // OR it with the first shuffled input.
10812 pshufbMask.clear();
10813 for (unsigned i = 0; i != 16; ++i) {
10814 int EltIdx = MaskVals[i];
10815 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
10816 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
10818 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
10819 DAG.getNode(ISD::BUILD_VECTOR, dl,
10820 MVT::v16i8, pshufbMask));
10821 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
10824 // No SSSE3 - Calculate in place words and then fix all out of place words
10825 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
10826 // the 16 different words that comprise the two doublequadword input vectors.
10827 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
10828 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
10830 for (int i = 0; i != 8; ++i) {
10831 int Elt0 = MaskVals[i*2];
10832 int Elt1 = MaskVals[i*2+1];
10834 // This word of the result is all undef, skip it.
10835 if (Elt0 < 0 && Elt1 < 0)
10838 // This word of the result is already in the correct place, skip it.
10839 if ((Elt0 == i*2) && (Elt1 == i*2+1))
10842 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
10843 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
10846 // If Elt0 and Elt1 are defined, are consecutive, and can be load
10847 // using a single extract together, load it and store it.
10848 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
10849 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10850 DAG.getIntPtrConstant(Elt1 / 2));
10851 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10852 DAG.getIntPtrConstant(i));
10856 // If Elt1 is defined, extract it from the appropriate source. If the
10857 // source byte is not also odd, shift the extracted word left 8 bits
10858 // otherwise clear the bottom 8 bits if we need to do an or.
10860 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
10861 DAG.getIntPtrConstant(Elt1 / 2));
10862 if ((Elt1 & 1) == 0)
10863 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
10865 TLI.getShiftAmountTy(InsElt.getValueType())));
10866 else if (Elt0 >= 0)
10867 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
10868 DAG.getConstant(0xFF00, MVT::i16));
10870 // If Elt0 is defined, extract it from the appropriate source. If the
10871 // source byte is not also even, shift the extracted word right 8 bits. If
10872 // Elt1 was also defined, OR the extracted values together before
10873 // inserting them in the result.
10875 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
10876 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
10877 if ((Elt0 & 1) != 0)
10878 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
10880 TLI.getShiftAmountTy(InsElt0.getValueType())));
10881 else if (Elt1 >= 0)
10882 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
10883 DAG.getConstant(0x00FF, MVT::i16));
10884 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
10887 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
10888 DAG.getIntPtrConstant(i));
10890 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
10893 // v32i8 shuffles - Translate to VPSHUFB if possible.
10895 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
10896 const X86Subtarget *Subtarget,
10897 SelectionDAG &DAG) {
10898 MVT VT = SVOp->getSimpleValueType(0);
10899 SDValue V1 = SVOp->getOperand(0);
10900 SDValue V2 = SVOp->getOperand(1);
10902 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
10904 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10905 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
10906 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
10908 // VPSHUFB may be generated if
10909 // (1) one of input vector is undefined or zeroinitializer.
10910 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
10911 // And (2) the mask indexes don't cross the 128-bit lane.
10912 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
10913 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
10916 if (V1IsAllZero && !V2IsAllZero) {
10917 CommuteVectorShuffleMask(MaskVals, 32);
10920 return getPSHUFB(MaskVals, V1, dl, DAG);
10923 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
10924 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
10925 /// done when every pair / quad of shuffle mask elements point to elements in
10926 /// the right sequence. e.g.
10927 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
10929 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
10930 SelectionDAG &DAG) {
10931 MVT VT = SVOp->getSimpleValueType(0);
10933 unsigned NumElems = VT.getVectorNumElements();
10936 switch (VT.SimpleTy) {
10937 default: llvm_unreachable("Unexpected!");
10940 return SDValue(SVOp, 0);
10941 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
10942 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
10943 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
10944 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
10945 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
10946 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
10949 SmallVector<int, 8> MaskVec;
10950 for (unsigned i = 0; i != NumElems; i += Scale) {
10952 for (unsigned j = 0; j != Scale; ++j) {
10953 int EltIdx = SVOp->getMaskElt(i+j);
10957 StartIdx = (EltIdx / Scale);
10958 if (EltIdx != (int)(StartIdx*Scale + j))
10961 MaskVec.push_back(StartIdx);
10964 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
10965 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
10966 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
10969 /// getVZextMovL - Return a zero-extending vector move low node.
10971 static SDValue getVZextMovL(MVT VT, MVT OpVT,
10972 SDValue SrcOp, SelectionDAG &DAG,
10973 const X86Subtarget *Subtarget, SDLoc dl) {
10974 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
10975 LoadSDNode *LD = nullptr;
10976 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
10977 LD = dyn_cast<LoadSDNode>(SrcOp);
10979 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
10981 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
10982 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
10983 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
10984 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
10985 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
10987 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
10988 return DAG.getNode(ISD::BITCAST, dl, VT,
10989 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
10990 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
10992 SrcOp.getOperand(0)
10998 return DAG.getNode(ISD::BITCAST, dl, VT,
10999 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11000 DAG.getNode(ISD::BITCAST, dl,
11004 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
11005 /// which could not be matched by any known target speficic shuffle
11007 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11009 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
11010 if (NewOp.getNode())
11013 MVT VT = SVOp->getSimpleValueType(0);
11015 unsigned NumElems = VT.getVectorNumElements();
11016 unsigned NumLaneElems = NumElems / 2;
11019 MVT EltVT = VT.getVectorElementType();
11020 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
11023 SmallVector<int, 16> Mask;
11024 for (unsigned l = 0; l < 2; ++l) {
11025 // Build a shuffle mask for the output, discovering on the fly which
11026 // input vectors to use as shuffle operands (recorded in InputUsed).
11027 // If building a suitable shuffle vector proves too hard, then bail
11028 // out with UseBuildVector set.
11029 bool UseBuildVector = false;
11030 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
11031 unsigned LaneStart = l * NumLaneElems;
11032 for (unsigned i = 0; i != NumLaneElems; ++i) {
11033 // The mask element. This indexes into the input.
11034 int Idx = SVOp->getMaskElt(i+LaneStart);
11036 // the mask element does not index into any input vector.
11037 Mask.push_back(-1);
11041 // The input vector this mask element indexes into.
11042 int Input = Idx / NumLaneElems;
11044 // Turn the index into an offset from the start of the input vector.
11045 Idx -= Input * NumLaneElems;
11047 // Find or create a shuffle vector operand to hold this input.
11049 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
11050 if (InputUsed[OpNo] == Input)
11051 // This input vector is already an operand.
11053 if (InputUsed[OpNo] < 0) {
11054 // Create a new operand for this input vector.
11055 InputUsed[OpNo] = Input;
11060 if (OpNo >= array_lengthof(InputUsed)) {
11061 // More than two input vectors used! Give up on trying to create a
11062 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
11063 UseBuildVector = true;
11067 // Add the mask index for the new shuffle vector.
11068 Mask.push_back(Idx + OpNo * NumLaneElems);
11071 if (UseBuildVector) {
11072 SmallVector<SDValue, 16> SVOps;
11073 for (unsigned i = 0; i != NumLaneElems; ++i) {
11074 // The mask element. This indexes into the input.
11075 int Idx = SVOp->getMaskElt(i+LaneStart);
11077 SVOps.push_back(DAG.getUNDEF(EltVT));
11081 // The input vector this mask element indexes into.
11082 int Input = Idx / NumElems;
11084 // Turn the index into an offset from the start of the input vector.
11085 Idx -= Input * NumElems;
11087 // Extract the vector element by hand.
11088 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11089 SVOp->getOperand(Input),
11090 DAG.getIntPtrConstant(Idx)));
11093 // Construct the output using a BUILD_VECTOR.
11094 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11095 } else if (InputUsed[0] < 0) {
11096 // No input vectors were used! The result is undefined.
11097 Output[l] = DAG.getUNDEF(NVT);
11099 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11100 (InputUsed[0] % 2) * NumLaneElems,
11102 // If only one input was used, use an undefined vector for the other.
11103 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11104 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11105 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11106 // At least one input vector was used. Create a new shuffle vector.
11107 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11113 // Concatenate the result back
11114 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11117 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11118 /// 4 elements, and match them with several different shuffle types.
11120 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11121 SDValue V1 = SVOp->getOperand(0);
11122 SDValue V2 = SVOp->getOperand(1);
11124 MVT VT = SVOp->getSimpleValueType(0);
11126 assert(VT.is128BitVector() && "Unsupported vector size");
11128 std::pair<int, int> Locs[4];
11129 int Mask1[] = { -1, -1, -1, -1 };
11130 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11132 unsigned NumHi = 0;
11133 unsigned NumLo = 0;
11134 for (unsigned i = 0; i != 4; ++i) {
11135 int Idx = PermMask[i];
11137 Locs[i] = std::make_pair(-1, -1);
11139 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11141 Locs[i] = std::make_pair(0, NumLo);
11142 Mask1[NumLo] = Idx;
11145 Locs[i] = std::make_pair(1, NumHi);
11147 Mask1[2+NumHi] = Idx;
11153 if (NumLo <= 2 && NumHi <= 2) {
11154 // If no more than two elements come from either vector. This can be
11155 // implemented with two shuffles. First shuffle gather the elements.
11156 // The second shuffle, which takes the first shuffle as both of its
11157 // vector operands, put the elements into the right order.
11158 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11160 int Mask2[] = { -1, -1, -1, -1 };
11162 for (unsigned i = 0; i != 4; ++i)
11163 if (Locs[i].first != -1) {
11164 unsigned Idx = (i < 2) ? 0 : 4;
11165 Idx += Locs[i].first * 2 + Locs[i].second;
11169 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11172 if (NumLo == 3 || NumHi == 3) {
11173 // Otherwise, we must have three elements from one vector, call it X, and
11174 // one element from the other, call it Y. First, use a shufps to build an
11175 // intermediate vector with the one element from Y and the element from X
11176 // that will be in the same half in the final destination (the indexes don't
11177 // matter). Then, use a shufps to build the final vector, taking the half
11178 // containing the element from Y from the intermediate, and the other half
11181 // Normalize it so the 3 elements come from V1.
11182 CommuteVectorShuffleMask(PermMask, 4);
11186 // Find the element from V2.
11188 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11189 int Val = PermMask[HiIndex];
11196 Mask1[0] = PermMask[HiIndex];
11198 Mask1[2] = PermMask[HiIndex^1];
11200 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11202 if (HiIndex >= 2) {
11203 Mask1[0] = PermMask[0];
11204 Mask1[1] = PermMask[1];
11205 Mask1[2] = HiIndex & 1 ? 6 : 4;
11206 Mask1[3] = HiIndex & 1 ? 4 : 6;
11207 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11210 Mask1[0] = HiIndex & 1 ? 2 : 0;
11211 Mask1[1] = HiIndex & 1 ? 0 : 2;
11212 Mask1[2] = PermMask[2];
11213 Mask1[3] = PermMask[3];
11218 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11221 // Break it into (shuffle shuffle_hi, shuffle_lo).
11222 int LoMask[] = { -1, -1, -1, -1 };
11223 int HiMask[] = { -1, -1, -1, -1 };
11225 int *MaskPtr = LoMask;
11226 unsigned MaskIdx = 0;
11227 unsigned LoIdx = 0;
11228 unsigned HiIdx = 2;
11229 for (unsigned i = 0; i != 4; ++i) {
11236 int Idx = PermMask[i];
11238 Locs[i] = std::make_pair(-1, -1);
11239 } else if (Idx < 4) {
11240 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11241 MaskPtr[LoIdx] = Idx;
11244 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11245 MaskPtr[HiIdx] = Idx;
11250 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11251 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11252 int MaskOps[] = { -1, -1, -1, -1 };
11253 for (unsigned i = 0; i != 4; ++i)
11254 if (Locs[i].first != -1)
11255 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11256 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11259 static bool MayFoldVectorLoad(SDValue V) {
11260 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11261 V = V.getOperand(0);
11263 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11264 V = V.getOperand(0);
11265 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11266 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11267 // BUILD_VECTOR (load), undef
11268 V = V.getOperand(0);
11270 return MayFoldLoad(V);
11274 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11275 MVT VT = Op.getSimpleValueType();
11277 // Canonizalize to v2f64.
11278 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11279 return DAG.getNode(ISD::BITCAST, dl, VT,
11280 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11285 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11287 SDValue V1 = Op.getOperand(0);
11288 SDValue V2 = Op.getOperand(1);
11289 MVT VT = Op.getSimpleValueType();
11291 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11293 if (HasSSE2 && VT == MVT::v2f64)
11294 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11296 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11297 return DAG.getNode(ISD::BITCAST, dl, VT,
11298 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11299 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11300 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11304 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11305 SDValue V1 = Op.getOperand(0);
11306 SDValue V2 = Op.getOperand(1);
11307 MVT VT = Op.getSimpleValueType();
11309 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11310 "unsupported shuffle type");
11312 if (V2.getOpcode() == ISD::UNDEF)
11316 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11320 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11321 SDValue V1 = Op.getOperand(0);
11322 SDValue V2 = Op.getOperand(1);
11323 MVT VT = Op.getSimpleValueType();
11324 unsigned NumElems = VT.getVectorNumElements();
11326 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11327 // operand of these instructions is only memory, so check if there's a
11328 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11330 bool CanFoldLoad = false;
11332 // Trivial case, when V2 comes from a load.
11333 if (MayFoldVectorLoad(V2))
11334 CanFoldLoad = true;
11336 // When V1 is a load, it can be folded later into a store in isel, example:
11337 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11339 // (MOVLPSmr addr:$src1, VR128:$src2)
11340 // So, recognize this potential and also use MOVLPS or MOVLPD
11341 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11342 CanFoldLoad = true;
11344 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11346 if (HasSSE2 && NumElems == 2)
11347 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11350 // If we don't care about the second element, proceed to use movss.
11351 if (SVOp->getMaskElt(1) != -1)
11352 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11355 // movl and movlp will both match v2i64, but v2i64 is never matched by
11356 // movl earlier because we make it strict to avoid messing with the movlp load
11357 // folding logic (see the code above getMOVLP call). Match it here then,
11358 // this is horrible, but will stay like this until we move all shuffle
11359 // matching to x86 specific nodes. Note that for the 1st condition all
11360 // types are matched with movsd.
11362 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11363 // as to remove this logic from here, as much as possible
11364 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11365 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11366 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11369 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11371 // Invert the operand order and use SHUFPS to match it.
11372 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11373 getShuffleSHUFImmediate(SVOp), DAG);
11376 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11377 SelectionDAG &DAG) {
11379 MVT VT = Load->getSimpleValueType(0);
11380 MVT EVT = VT.getVectorElementType();
11381 SDValue Addr = Load->getOperand(1);
11382 SDValue NewAddr = DAG.getNode(
11383 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11384 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11387 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11388 DAG.getMachineFunction().getMachineMemOperand(
11389 Load->getMemOperand(), 0, EVT.getStoreSize()));
11393 // It is only safe to call this function if isINSERTPSMask is true for
11394 // this shufflevector mask.
11395 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11396 SelectionDAG &DAG) {
11397 // Generate an insertps instruction when inserting an f32 from memory onto a
11398 // v4f32 or when copying a member from one v4f32 to another.
11399 // We also use it for transferring i32 from one register to another,
11400 // since it simply copies the same bits.
11401 // If we're transferring an i32 from memory to a specific element in a
11402 // register, we output a generic DAG that will match the PINSRD
11404 MVT VT = SVOp->getSimpleValueType(0);
11405 MVT EVT = VT.getVectorElementType();
11406 SDValue V1 = SVOp->getOperand(0);
11407 SDValue V2 = SVOp->getOperand(1);
11408 auto Mask = SVOp->getMask();
11409 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11410 "unsupported vector type for insertps/pinsrd");
11412 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11413 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11414 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11418 unsigned DestIndex;
11422 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
11425 // If we have 1 element from each vector, we have to check if we're
11426 // changing V1's element's place. If so, we're done. Otherwise, we
11427 // should assume we're changing V2's element's place and behave
11429 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
11430 assert(DestIndex <= INT32_MAX && "truncated destination index");
11431 if (FromV1 == FromV2 &&
11432 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
11436 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11439 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
11440 "More than one element from V1 and from V2, or no elements from one "
11441 "of the vectors. This case should not have returned true from "
11446 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11449 // Get an index into the source vector in the range [0,4) (the mask is
11450 // in the range [0,8) because it can address V1 and V2)
11451 unsigned SrcIndex = Mask[DestIndex] % 4;
11452 if (MayFoldLoad(From)) {
11453 // Trivial case, when From comes from a load and is only used by the
11454 // shuffle. Make it use insertps from the vector that we need from that
11457 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
11458 if (!NewLoad.getNode())
11461 if (EVT == MVT::f32) {
11462 // Create this as a scalar to vector to match the instruction pattern.
11463 SDValue LoadScalarToVector =
11464 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
11465 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
11466 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
11468 } else { // EVT == MVT::i32
11469 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
11470 // instruction, to match the PINSRD instruction, which loads an i32 to a
11471 // certain vector element.
11472 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
11473 DAG.getConstant(DestIndex, MVT::i32));
11477 // Vector-element-to-vector
11478 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
11479 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
11482 // Reduce a vector shuffle to zext.
11483 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
11484 SelectionDAG &DAG) {
11485 // PMOVZX is only available from SSE41.
11486 if (!Subtarget->hasSSE41())
11489 MVT VT = Op.getSimpleValueType();
11491 // Only AVX2 support 256-bit vector integer extending.
11492 if (!Subtarget->hasInt256() && VT.is256BitVector())
11495 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11497 SDValue V1 = Op.getOperand(0);
11498 SDValue V2 = Op.getOperand(1);
11499 unsigned NumElems = VT.getVectorNumElements();
11501 // Extending is an unary operation and the element type of the source vector
11502 // won't be equal to or larger than i64.
11503 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
11504 VT.getVectorElementType() == MVT::i64)
11507 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
11508 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
11509 while ((1U << Shift) < NumElems) {
11510 if (SVOp->getMaskElt(1U << Shift) == 1)
11513 // The maximal ratio is 8, i.e. from i8 to i64.
11518 // Check the shuffle mask.
11519 unsigned Mask = (1U << Shift) - 1;
11520 for (unsigned i = 0; i != NumElems; ++i) {
11521 int EltIdx = SVOp->getMaskElt(i);
11522 if ((i & Mask) != 0 && EltIdx != -1)
11524 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
11528 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
11529 MVT NeVT = MVT::getIntegerVT(NBits);
11530 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
11532 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
11535 return DAG.getNode(ISD::BITCAST, DL, VT,
11536 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
11539 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11540 SelectionDAG &DAG) {
11541 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11542 MVT VT = Op.getSimpleValueType();
11544 SDValue V1 = Op.getOperand(0);
11545 SDValue V2 = Op.getOperand(1);
11547 if (isZeroShuffle(SVOp))
11548 return getZeroVector(VT, Subtarget, DAG, dl);
11550 // Handle splat operations
11551 if (SVOp->isSplat()) {
11552 // Use vbroadcast whenever the splat comes from a foldable load
11553 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
11554 if (Broadcast.getNode())
11558 // Check integer expanding shuffles.
11559 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
11560 if (NewOp.getNode())
11563 // If the shuffle can be profitably rewritten as a narrower shuffle, then
11565 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
11566 VT == MVT::v32i8) {
11567 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11568 if (NewOp.getNode())
11569 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
11570 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
11571 // FIXME: Figure out a cleaner way to do this.
11572 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
11573 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11574 if (NewOp.getNode()) {
11575 MVT NewVT = NewOp.getSimpleValueType();
11576 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
11577 NewVT, true, false))
11578 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
11581 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
11582 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
11583 if (NewOp.getNode()) {
11584 MVT NewVT = NewOp.getSimpleValueType();
11585 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
11586 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
11595 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
11596 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11597 SDValue V1 = Op.getOperand(0);
11598 SDValue V2 = Op.getOperand(1);
11599 MVT VT = Op.getSimpleValueType();
11601 unsigned NumElems = VT.getVectorNumElements();
11602 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11603 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11604 bool V1IsSplat = false;
11605 bool V2IsSplat = false;
11606 bool HasSSE2 = Subtarget->hasSSE2();
11607 bool HasFp256 = Subtarget->hasFp256();
11608 bool HasInt256 = Subtarget->hasInt256();
11609 MachineFunction &MF = DAG.getMachineFunction();
11610 bool OptForSize = MF.getFunction()->getAttributes().
11611 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
11613 // Check if we should use the experimental vector shuffle lowering. If so,
11614 // delegate completely to that code path.
11615 if (ExperimentalVectorShuffleLowering)
11616 return lowerVectorShuffle(Op, Subtarget, DAG);
11618 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
11620 if (V1IsUndef && V2IsUndef)
11621 return DAG.getUNDEF(VT);
11623 // When we create a shuffle node we put the UNDEF node to second operand,
11624 // but in some cases the first operand may be transformed to UNDEF.
11625 // In this case we should just commute the node.
11627 return DAG.getCommutedVectorShuffle(*SVOp);
11629 // Vector shuffle lowering takes 3 steps:
11631 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
11632 // narrowing and commutation of operands should be handled.
11633 // 2) Matching of shuffles with known shuffle masks to x86 target specific
11635 // 3) Rewriting of unmatched masks into new generic shuffle operations,
11636 // so the shuffle can be broken into other shuffles and the legalizer can
11637 // try the lowering again.
11639 // The general idea is that no vector_shuffle operation should be left to
11640 // be matched during isel, all of them must be converted to a target specific
11643 // Normalize the input vectors. Here splats, zeroed vectors, profitable
11644 // narrowing and commutation of operands should be handled. The actual code
11645 // doesn't include all of those, work in progress...
11646 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
11647 if (NewOp.getNode())
11650 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
11652 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
11653 // unpckh_undef). Only use pshufd if speed is more important than size.
11654 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11655 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11656 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11657 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11659 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
11660 V2IsUndef && MayFoldVectorLoad(V1))
11661 return getMOVDDup(Op, dl, V1, DAG);
11663 if (isMOVHLPS_v_undef_Mask(M, VT))
11664 return getMOVHighToLow(Op, dl, DAG);
11666 // Use to match splats
11667 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
11668 (VT == MVT::v2f64 || VT == MVT::v2i64))
11669 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11671 if (isPSHUFDMask(M, VT)) {
11672 // The actual implementation will match the mask in the if above and then
11673 // during isel it can match several different instructions, not only pshufd
11674 // as its name says, sad but true, emulate the behavior for now...
11675 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
11676 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
11678 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
11680 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
11681 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
11683 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
11684 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
11687 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
11691 if (isPALIGNRMask(M, VT, Subtarget))
11692 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
11693 getShufflePALIGNRImmediate(SVOp),
11696 if (isVALIGNMask(M, VT, Subtarget))
11697 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
11698 getShuffleVALIGNImmediate(SVOp),
11701 // Check if this can be converted into a logical shift.
11702 bool isLeft = false;
11703 unsigned ShAmt = 0;
11705 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
11706 if (isShift && ShVal.hasOneUse()) {
11707 // If the shifted value has multiple uses, it may be cheaper to use
11708 // v_set0 + movlhps or movhlps, etc.
11709 MVT EltVT = VT.getVectorElementType();
11710 ShAmt *= EltVT.getSizeInBits();
11711 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11714 if (isMOVLMask(M, VT)) {
11715 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11716 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
11717 if (!isMOVLPMask(M, VT)) {
11718 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
11719 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11721 if (VT == MVT::v4i32 || VT == MVT::v4f32)
11722 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11726 // FIXME: fold these into legal mask.
11727 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
11728 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
11730 if (isMOVHLPSMask(M, VT))
11731 return getMOVHighToLow(Op, dl, DAG);
11733 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
11734 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
11736 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
11737 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
11739 if (isMOVLPMask(M, VT))
11740 return getMOVLP(Op, dl, DAG, HasSSE2);
11742 if (ShouldXformToMOVHLPS(M, VT) ||
11743 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
11744 return DAG.getCommutedVectorShuffle(*SVOp);
11747 // No better options. Use a vshldq / vsrldq.
11748 MVT EltVT = VT.getVectorElementType();
11749 ShAmt *= EltVT.getSizeInBits();
11750 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
11753 bool Commuted = false;
11754 // FIXME: This should also accept a bitcast of a splat? Be careful, not
11755 // 1,1,1,1 -> v8i16 though.
11756 BitVector UndefElements;
11757 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
11758 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11760 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
11761 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
11764 // Canonicalize the splat or undef, if present, to be on the RHS.
11765 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
11766 CommuteVectorShuffleMask(M, NumElems);
11768 std::swap(V1IsSplat, V2IsSplat);
11772 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
11773 // Shuffling low element of v1 into undef, just return v1.
11776 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
11777 // the instruction selector will not match, so get a canonical MOVL with
11778 // swapped operands to undo the commute.
11779 return getMOVL(DAG, dl, VT, V2, V1);
11782 if (isUNPCKLMask(M, VT, HasInt256))
11783 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11785 if (isUNPCKHMask(M, VT, HasInt256))
11786 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11789 // Normalize mask so all entries that point to V2 points to its first
11790 // element then try to match unpck{h|l} again. If match, return a
11791 // new vector_shuffle with the corrected mask.p
11792 SmallVector<int, 8> NewMask(M.begin(), M.end());
11793 NormalizeMask(NewMask, NumElems);
11794 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
11795 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11796 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
11797 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11801 // Commute is back and try unpck* again.
11802 // FIXME: this seems wrong.
11803 CommuteVectorShuffleMask(M, NumElems);
11805 std::swap(V1IsSplat, V2IsSplat);
11807 if (isUNPCKLMask(M, VT, HasInt256))
11808 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
11810 if (isUNPCKHMask(M, VT, HasInt256))
11811 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
11814 // Normalize the node to match x86 shuffle ops if needed
11815 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
11816 return DAG.getCommutedVectorShuffle(*SVOp);
11818 // The checks below are all present in isShuffleMaskLegal, but they are
11819 // inlined here right now to enable us to directly emit target specific
11820 // nodes, and remove one by one until they don't return Op anymore.
11822 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
11823 SVOp->getSplatIndex() == 0 && V2IsUndef) {
11824 if (VT == MVT::v2f64 || VT == MVT::v2i64)
11825 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11828 if (isPSHUFHWMask(M, VT, HasInt256))
11829 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
11830 getShufflePSHUFHWImmediate(SVOp),
11833 if (isPSHUFLWMask(M, VT, HasInt256))
11834 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
11835 getShufflePSHUFLWImmediate(SVOp),
11838 unsigned MaskValue;
11839 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
11841 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
11843 if (isSHUFPMask(M, VT))
11844 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
11845 getShuffleSHUFImmediate(SVOp), DAG);
11847 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
11848 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
11849 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
11850 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
11852 //===--------------------------------------------------------------------===//
11853 // Generate target specific nodes for 128 or 256-bit shuffles only
11854 // supported in the AVX instruction set.
11857 // Handle VMOVDDUPY permutations
11858 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
11859 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
11861 // Handle VPERMILPS/D* permutations
11862 if (isVPERMILPMask(M, VT)) {
11863 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
11864 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
11865 getShuffleSHUFImmediate(SVOp), DAG);
11866 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
11867 getShuffleSHUFImmediate(SVOp), DAG);
11871 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
11872 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
11873 Idx*(NumElems/2), DAG, dl);
11875 // Handle VPERM2F128/VPERM2I128 permutations
11876 if (isVPERM2X128Mask(M, VT, HasFp256))
11877 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
11878 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
11880 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
11881 return getINSERTPS(SVOp, dl, DAG);
11884 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
11885 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
11887 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
11888 VT.is512BitVector()) {
11889 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
11890 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
11891 SmallVector<SDValue, 16> permclMask;
11892 for (unsigned i = 0; i != NumElems; ++i) {
11893 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
11896 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
11898 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
11899 return DAG.getNode(X86ISD::VPERMV, dl, VT,
11900 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
11901 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
11902 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
11905 //===--------------------------------------------------------------------===//
11906 // Since no target specific shuffle was selected for this generic one,
11907 // lower it into other known shuffles. FIXME: this isn't true yet, but
11908 // this is the plan.
11911 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
11912 if (VT == MVT::v8i16) {
11913 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
11914 if (NewOp.getNode())
11918 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
11919 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
11920 if (NewOp.getNode())
11924 if (VT == MVT::v16i8) {
11925 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
11926 if (NewOp.getNode())
11930 if (VT == MVT::v32i8) {
11931 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
11932 if (NewOp.getNode())
11936 // Handle all 128-bit wide vectors with 4 elements, and match them with
11937 // several different shuffle types.
11938 if (NumElems == 4 && VT.is128BitVector())
11939 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
11941 // Handle general 256-bit shuffles
11942 if (VT.is256BitVector())
11943 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
11948 // This function assumes its argument is a BUILD_VECTOR of constants or
11949 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11951 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11952 unsigned &MaskValue) {
11954 unsigned NumElems = BuildVector->getNumOperands();
11955 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11956 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11957 unsigned NumElemsInLane = NumElems / NumLanes;
11959 // Blend for v16i16 should be symetric for the both lanes.
11960 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11961 SDValue EltCond = BuildVector->getOperand(i);
11962 SDValue SndLaneEltCond =
11963 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11965 int Lane1Cond = -1, Lane2Cond = -1;
11966 if (isa<ConstantSDNode>(EltCond))
11967 Lane1Cond = !isZero(EltCond);
11968 if (isa<ConstantSDNode>(SndLaneEltCond))
11969 Lane2Cond = !isZero(SndLaneEltCond);
11971 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11972 // Lane1Cond != 0, means we want the first argument.
11973 // Lane1Cond == 0, means we want the second argument.
11974 // The encoding of this argument is 0 for the first argument, 1
11975 // for the second. Therefore, invert the condition.
11976 MaskValue |= !Lane1Cond << i;
11977 else if (Lane1Cond < 0)
11978 MaskValue |= !Lane2Cond << i;
11985 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
11987 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
11988 SelectionDAG &DAG) {
11989 SDValue Cond = Op.getOperand(0);
11990 SDValue LHS = Op.getOperand(1);
11991 SDValue RHS = Op.getOperand(2);
11993 MVT VT = Op.getSimpleValueType();
11994 MVT EltVT = VT.getVectorElementType();
11995 unsigned NumElems = VT.getVectorNumElements();
11997 // There is no blend with immediate in AVX-512.
11998 if (VT.is512BitVector())
12001 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
12003 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
12006 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
12009 // Check the mask for BLEND and build the value.
12010 unsigned MaskValue = 0;
12011 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
12014 // Convert i32 vectors to floating point if it is not AVX2.
12015 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
12017 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
12018 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
12020 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
12021 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
12024 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
12025 DAG.getConstant(MaskValue, MVT::i32));
12026 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
12029 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
12030 // A vselect where all conditions and data are constants can be optimized into
12031 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
12032 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
12033 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
12034 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
12037 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
12038 if (BlendOp.getNode())
12041 // Some types for vselect were previously set to Expand, not Legal or
12042 // Custom. Return an empty SDValue so we fall-through to Expand, after
12043 // the Custom lowering phase.
12044 MVT VT = Op.getSimpleValueType();
12045 switch (VT.SimpleTy) {
12050 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12055 // We couldn't create a "Blend with immediate" node.
12056 // This node should still be legal, but we'll have to emit a blendv*
12061 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12062 MVT VT = Op.getSimpleValueType();
12065 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12068 if (VT.getSizeInBits() == 8) {
12069 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12070 Op.getOperand(0), Op.getOperand(1));
12071 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12072 DAG.getValueType(VT));
12073 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12076 if (VT.getSizeInBits() == 16) {
12077 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12078 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12080 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12081 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12082 DAG.getNode(ISD::BITCAST, dl,
12085 Op.getOperand(1)));
12086 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12087 Op.getOperand(0), Op.getOperand(1));
12088 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12089 DAG.getValueType(VT));
12090 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12093 if (VT == MVT::f32) {
12094 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12095 // the result back to FR32 register. It's only worth matching if the
12096 // result has a single use which is a store or a bitcast to i32. And in
12097 // the case of a store, it's not worth it if the index is a constant 0,
12098 // because a MOVSSmr can be used instead, which is smaller and faster.
12099 if (!Op.hasOneUse())
12101 SDNode *User = *Op.getNode()->use_begin();
12102 if ((User->getOpcode() != ISD::STORE ||
12103 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12104 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12105 (User->getOpcode() != ISD::BITCAST ||
12106 User->getValueType(0) != MVT::i32))
12108 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12109 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12112 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12115 if (VT == MVT::i32 || VT == MVT::i64) {
12116 // ExtractPS/pextrq works with constant index.
12117 if (isa<ConstantSDNode>(Op.getOperand(1)))
12123 /// Extract one bit from mask vector, like v16i1 or v8i1.
12124 /// AVX-512 feature.
12126 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12127 SDValue Vec = Op.getOperand(0);
12129 MVT VecVT = Vec.getSimpleValueType();
12130 SDValue Idx = Op.getOperand(1);
12131 MVT EltVT = Op.getSimpleValueType();
12133 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12135 // variable index can't be handled in mask registers,
12136 // extend vector to VR512
12137 if (!isa<ConstantSDNode>(Idx)) {
12138 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12139 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12140 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12141 ExtVT.getVectorElementType(), Ext, Idx);
12142 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12145 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12146 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12147 unsigned MaxSift = rc->getSize()*8 - 1;
12148 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12149 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12150 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12151 DAG.getConstant(MaxSift, MVT::i8));
12152 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12153 DAG.getIntPtrConstant(0));
12157 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12158 SelectionDAG &DAG) const {
12160 SDValue Vec = Op.getOperand(0);
12161 MVT VecVT = Vec.getSimpleValueType();
12162 SDValue Idx = Op.getOperand(1);
12164 if (Op.getSimpleValueType() == MVT::i1)
12165 return ExtractBitFromMaskVector(Op, DAG);
12167 if (!isa<ConstantSDNode>(Idx)) {
12168 if (VecVT.is512BitVector() ||
12169 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12170 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12173 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12174 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12175 MaskEltVT.getSizeInBits());
12177 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12178 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12179 getZeroVector(MaskVT, Subtarget, DAG, dl),
12180 Idx, DAG.getConstant(0, getPointerTy()));
12181 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12182 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12183 Perm, DAG.getConstant(0, getPointerTy()));
12188 // If this is a 256-bit vector result, first extract the 128-bit vector and
12189 // then extract the element from the 128-bit vector.
12190 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12192 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12193 // Get the 128-bit vector.
12194 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12195 MVT EltVT = VecVT.getVectorElementType();
12197 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12199 //if (IdxVal >= NumElems/2)
12200 // IdxVal -= NumElems/2;
12201 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12202 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12203 DAG.getConstant(IdxVal, MVT::i32));
12206 assert(VecVT.is128BitVector() && "Unexpected vector length");
12208 if (Subtarget->hasSSE41()) {
12209 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12214 MVT VT = Op.getSimpleValueType();
12215 // TODO: handle v16i8.
12216 if (VT.getSizeInBits() == 16) {
12217 SDValue Vec = Op.getOperand(0);
12218 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12220 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12221 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12222 DAG.getNode(ISD::BITCAST, dl,
12224 Op.getOperand(1)));
12225 // Transform it so it match pextrw which produces a 32-bit result.
12226 MVT EltVT = MVT::i32;
12227 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12228 Op.getOperand(0), Op.getOperand(1));
12229 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12230 DAG.getValueType(VT));
12231 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12234 if (VT.getSizeInBits() == 32) {
12235 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12239 // SHUFPS the element to the lowest double word, then movss.
12240 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12241 MVT VVT = Op.getOperand(0).getSimpleValueType();
12242 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12243 DAG.getUNDEF(VVT), Mask);
12244 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12245 DAG.getIntPtrConstant(0));
12248 if (VT.getSizeInBits() == 64) {
12249 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12250 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12251 // to match extract_elt for f64.
12252 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12256 // UNPCKHPD the element to the lowest double word, then movsd.
12257 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12258 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12259 int Mask[2] = { 1, -1 };
12260 MVT VVT = Op.getOperand(0).getSimpleValueType();
12261 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12262 DAG.getUNDEF(VVT), Mask);
12263 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12264 DAG.getIntPtrConstant(0));
12270 /// Insert one bit to mask vector, like v16i1 or v8i1.
12271 /// AVX-512 feature.
12273 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12275 SDValue Vec = Op.getOperand(0);
12276 SDValue Elt = Op.getOperand(1);
12277 SDValue Idx = Op.getOperand(2);
12278 MVT VecVT = Vec.getSimpleValueType();
12280 if (!isa<ConstantSDNode>(Idx)) {
12281 // Non constant index. Extend source and destination,
12282 // insert element and then truncate the result.
12283 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12284 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12285 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12286 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12287 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12288 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12291 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12292 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12293 if (Vec.getOpcode() == ISD::UNDEF)
12294 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12295 DAG.getConstant(IdxVal, MVT::i8));
12296 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12297 unsigned MaxSift = rc->getSize()*8 - 1;
12298 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12299 DAG.getConstant(MaxSift, MVT::i8));
12300 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12301 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12302 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12305 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12306 SelectionDAG &DAG) const {
12307 MVT VT = Op.getSimpleValueType();
12308 MVT EltVT = VT.getVectorElementType();
12310 if (EltVT == MVT::i1)
12311 return InsertBitToMaskVector(Op, DAG);
12314 SDValue N0 = Op.getOperand(0);
12315 SDValue N1 = Op.getOperand(1);
12316 SDValue N2 = Op.getOperand(2);
12317 if (!isa<ConstantSDNode>(N2))
12319 auto *N2C = cast<ConstantSDNode>(N2);
12320 unsigned IdxVal = N2C->getZExtValue();
12322 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12323 // into that, and then insert the subvector back into the result.
12324 if (VT.is256BitVector() || VT.is512BitVector()) {
12325 // Get the desired 128-bit vector half.
12326 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12328 // Insert the element into the desired half.
12329 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12330 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12332 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12333 DAG.getConstant(IdxIn128, MVT::i32));
12335 // Insert the changed part back to the 256-bit vector
12336 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12338 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12340 if (Subtarget->hasSSE41()) {
12341 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12343 if (VT == MVT::v8i16) {
12344 Opc = X86ISD::PINSRW;
12346 assert(VT == MVT::v16i8);
12347 Opc = X86ISD::PINSRB;
12350 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12352 if (N1.getValueType() != MVT::i32)
12353 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12354 if (N2.getValueType() != MVT::i32)
12355 N2 = DAG.getIntPtrConstant(IdxVal);
12356 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12359 if (EltVT == MVT::f32) {
12360 // Bits [7:6] of the constant are the source select. This will always be
12361 // zero here. The DAG Combiner may combine an extract_elt index into
12363 // bits. For example (insert (extract, 3), 2) could be matched by
12365 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12366 // Bits [5:4] of the constant are the destination select. This is the
12367 // value of the incoming immediate.
12368 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12369 // combine either bitwise AND or insert of float 0.0 to set these bits.
12370 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12371 // Create this as a scalar to vector..
12372 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12373 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12376 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12377 // PINSR* works with constant index.
12382 if (EltVT == MVT::i8)
12385 if (EltVT.getSizeInBits() == 16) {
12386 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12387 // as its second argument.
12388 if (N1.getValueType() != MVT::i32)
12389 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12390 if (N2.getValueType() != MVT::i32)
12391 N2 = DAG.getIntPtrConstant(IdxVal);
12392 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12397 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12399 MVT OpVT = Op.getSimpleValueType();
12401 // If this is a 256-bit vector result, first insert into a 128-bit
12402 // vector and then insert into the 256-bit vector.
12403 if (!OpVT.is128BitVector()) {
12404 // Insert into a 128-bit vector.
12405 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12406 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12407 OpVT.getVectorNumElements() / SizeFactor);
12409 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12411 // Insert the 128-bit vector.
12412 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12415 if (OpVT == MVT::v1i64 &&
12416 Op.getOperand(0).getValueType() == MVT::i64)
12417 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12419 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12420 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12421 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12422 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12425 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12426 // a simple subregister reference or explicit instructions to grab
12427 // upper bits of a vector.
12428 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12429 SelectionDAG &DAG) {
12431 SDValue In = Op.getOperand(0);
12432 SDValue Idx = Op.getOperand(1);
12433 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12434 MVT ResVT = Op.getSimpleValueType();
12435 MVT InVT = In.getSimpleValueType();
12437 if (Subtarget->hasFp256()) {
12438 if (ResVT.is128BitVector() &&
12439 (InVT.is256BitVector() || InVT.is512BitVector()) &&
12440 isa<ConstantSDNode>(Idx)) {
12441 return Extract128BitVector(In, IdxVal, DAG, dl);
12443 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
12444 isa<ConstantSDNode>(Idx)) {
12445 return Extract256BitVector(In, IdxVal, DAG, dl);
12451 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12452 // simple superregister reference or explicit instructions to insert
12453 // the upper bits of a vector.
12454 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12455 SelectionDAG &DAG) {
12456 if (Subtarget->hasFp256()) {
12457 SDLoc dl(Op.getNode());
12458 SDValue Vec = Op.getNode()->getOperand(0);
12459 SDValue SubVec = Op.getNode()->getOperand(1);
12460 SDValue Idx = Op.getNode()->getOperand(2);
12462 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
12463 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
12464 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
12465 isa<ConstantSDNode>(Idx)) {
12466 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12467 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
12470 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
12471 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
12472 isa<ConstantSDNode>(Idx)) {
12473 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12474 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
12480 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
12481 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
12482 // one of the above mentioned nodes. It has to be wrapped because otherwise
12483 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
12484 // be used to form addressing mode. These wrapped nodes will be selected
12487 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
12488 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
12490 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12491 // global base reg.
12492 unsigned char OpFlag = 0;
12493 unsigned WrapperKind = X86ISD::Wrapper;
12494 CodeModel::Model M = DAG.getTarget().getCodeModel();
12496 if (Subtarget->isPICStyleRIPRel() &&
12497 (M == CodeModel::Small || M == CodeModel::Kernel))
12498 WrapperKind = X86ISD::WrapperRIP;
12499 else if (Subtarget->isPICStyleGOT())
12500 OpFlag = X86II::MO_GOTOFF;
12501 else if (Subtarget->isPICStyleStubPIC())
12502 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12504 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
12505 CP->getAlignment(),
12506 CP->getOffset(), OpFlag);
12508 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12509 // With PIC, the address is actually $g + Offset.
12511 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12512 DAG.getNode(X86ISD::GlobalBaseReg,
12513 SDLoc(), getPointerTy()),
12520 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
12521 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
12523 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12524 // global base reg.
12525 unsigned char OpFlag = 0;
12526 unsigned WrapperKind = X86ISD::Wrapper;
12527 CodeModel::Model M = DAG.getTarget().getCodeModel();
12529 if (Subtarget->isPICStyleRIPRel() &&
12530 (M == CodeModel::Small || M == CodeModel::Kernel))
12531 WrapperKind = X86ISD::WrapperRIP;
12532 else if (Subtarget->isPICStyleGOT())
12533 OpFlag = X86II::MO_GOTOFF;
12534 else if (Subtarget->isPICStyleStubPIC())
12535 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12537 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
12540 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12542 // With PIC, the address is actually $g + Offset.
12544 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12545 DAG.getNode(X86ISD::GlobalBaseReg,
12546 SDLoc(), getPointerTy()),
12553 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
12554 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
12556 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12557 // global base reg.
12558 unsigned char OpFlag = 0;
12559 unsigned WrapperKind = X86ISD::Wrapper;
12560 CodeModel::Model M = DAG.getTarget().getCodeModel();
12562 if (Subtarget->isPICStyleRIPRel() &&
12563 (M == CodeModel::Small || M == CodeModel::Kernel)) {
12564 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
12565 OpFlag = X86II::MO_GOTPCREL;
12566 WrapperKind = X86ISD::WrapperRIP;
12567 } else if (Subtarget->isPICStyleGOT()) {
12568 OpFlag = X86II::MO_GOT;
12569 } else if (Subtarget->isPICStyleStubPIC()) {
12570 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
12571 } else if (Subtarget->isPICStyleStubNoDynamic()) {
12572 OpFlag = X86II::MO_DARWIN_NONLAZY;
12575 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
12578 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12580 // With PIC, the address is actually $g + Offset.
12581 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
12582 !Subtarget->is64Bit()) {
12583 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12584 DAG.getNode(X86ISD::GlobalBaseReg,
12585 SDLoc(), getPointerTy()),
12589 // For symbols that require a load from a stub to get the address, emit the
12591 if (isGlobalStubReference(OpFlag))
12592 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
12593 MachinePointerInfo::getGOT(), false, false, false, 0);
12599 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
12600 // Create the TargetBlockAddressAddress node.
12601 unsigned char OpFlags =
12602 Subtarget->ClassifyBlockAddressReference();
12603 CodeModel::Model M = DAG.getTarget().getCodeModel();
12604 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
12605 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
12607 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
12610 if (Subtarget->isPICStyleRIPRel() &&
12611 (M == CodeModel::Small || M == CodeModel::Kernel))
12612 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12614 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12616 // With PIC, the address is actually $g + Offset.
12617 if (isGlobalRelativeToPICBase(OpFlags)) {
12618 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12619 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12627 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
12628 int64_t Offset, SelectionDAG &DAG) const {
12629 // Create the TargetGlobalAddress node, folding in the constant
12630 // offset if it is legal.
12631 unsigned char OpFlags =
12632 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
12633 CodeModel::Model M = DAG.getTarget().getCodeModel();
12635 if (OpFlags == X86II::MO_NO_FLAG &&
12636 X86::isOffsetSuitableForCodeModel(Offset, M)) {
12637 // A direct static reference to a global.
12638 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
12641 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
12644 if (Subtarget->isPICStyleRIPRel() &&
12645 (M == CodeModel::Small || M == CodeModel::Kernel))
12646 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
12648 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
12650 // With PIC, the address is actually $g + Offset.
12651 if (isGlobalRelativeToPICBase(OpFlags)) {
12652 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
12653 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
12657 // For globals that require a load from a stub to get the address, emit the
12659 if (isGlobalStubReference(OpFlags))
12660 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
12661 MachinePointerInfo::getGOT(), false, false, false, 0);
12663 // If there was a non-zero offset that we didn't fold, create an explicit
12664 // addition for it.
12666 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
12667 DAG.getConstant(Offset, getPointerTy()));
12673 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12674 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12675 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12676 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12680 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12681 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12682 unsigned char OperandFlags, bool LocalDynamic = false) {
12683 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12684 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12686 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12687 GA->getValueType(0),
12691 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12695 SDValue Ops[] = { Chain, TGA, *InFlag };
12696 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12698 SDValue Ops[] = { Chain, TGA };
12699 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12702 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12703 MFI->setAdjustsStack(true);
12705 SDValue Flag = Chain.getValue(1);
12706 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12709 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12711 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12714 SDLoc dl(GA); // ? function entry point might be better
12715 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12716 DAG.getNode(X86ISD::GlobalBaseReg,
12717 SDLoc(), PtrVT), InFlag);
12718 InFlag = Chain.getValue(1);
12720 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12723 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12725 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12727 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12728 X86::RAX, X86II::MO_TLSGD);
12731 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12737 // Get the start address of the TLS block for this module.
12738 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12739 .getInfo<X86MachineFunctionInfo>();
12740 MFI->incNumLocalDynamicTLSAccesses();
12744 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12745 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12748 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12749 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12750 InFlag = Chain.getValue(1);
12751 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12752 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12755 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12759 unsigned char OperandFlags = X86II::MO_DTPOFF;
12760 unsigned WrapperKind = X86ISD::Wrapper;
12761 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12762 GA->getValueType(0),
12763 GA->getOffset(), OperandFlags);
12764 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12766 // Add x@dtpoff with the base.
12767 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12770 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12771 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12772 const EVT PtrVT, TLSModel::Model model,
12773 bool is64Bit, bool isPIC) {
12776 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12777 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12778 is64Bit ? 257 : 256));
12780 SDValue ThreadPointer =
12781 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
12782 MachinePointerInfo(Ptr), false, false, false, 0);
12784 unsigned char OperandFlags = 0;
12785 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12787 unsigned WrapperKind = X86ISD::Wrapper;
12788 if (model == TLSModel::LocalExec) {
12789 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12790 } else if (model == TLSModel::InitialExec) {
12792 OperandFlags = X86II::MO_GOTTPOFF;
12793 WrapperKind = X86ISD::WrapperRIP;
12795 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12798 llvm_unreachable("Unexpected model");
12801 // emit "addl x@ntpoff,%eax" (local exec)
12802 // or "addl x@indntpoff,%eax" (initial exec)
12803 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12805 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12806 GA->getOffset(), OperandFlags);
12807 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12809 if (model == TLSModel::InitialExec) {
12810 if (isPIC && !is64Bit) {
12811 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12812 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12816 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12817 MachinePointerInfo::getGOT(), false, false, false, 0);
12820 // The address of the thread local variable is the add of the thread
12821 // pointer with the offset of the variable.
12822 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12826 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12828 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12829 const GlobalValue *GV = GA->getGlobal();
12831 if (Subtarget->isTargetELF()) {
12832 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12835 case TLSModel::GeneralDynamic:
12836 if (Subtarget->is64Bit())
12837 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
12838 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
12839 case TLSModel::LocalDynamic:
12840 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
12841 Subtarget->is64Bit());
12842 case TLSModel::InitialExec:
12843 case TLSModel::LocalExec:
12844 return LowerToTLSExecModel(
12845 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
12846 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
12848 llvm_unreachable("Unknown TLS model.");
12851 if (Subtarget->isTargetDarwin()) {
12852 // Darwin only has one model of TLS. Lower to that.
12853 unsigned char OpFlag = 0;
12854 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12855 X86ISD::WrapperRIP : X86ISD::Wrapper;
12857 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12858 // global base reg.
12859 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12860 !Subtarget->is64Bit();
12862 OpFlag = X86II::MO_TLVP_PIC_BASE;
12864 OpFlag = X86II::MO_TLVP;
12866 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12867 GA->getValueType(0),
12868 GA->getOffset(), OpFlag);
12869 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
12871 // With PIC32, the address is actually $g + Offset.
12873 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
12874 DAG.getNode(X86ISD::GlobalBaseReg,
12875 SDLoc(), getPointerTy()),
12878 // Lowering the machine isd will make sure everything is in the right
12880 SDValue Chain = DAG.getEntryNode();
12881 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12882 SDValue Args[] = { Chain, Offset };
12883 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12885 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12886 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12887 MFI->setAdjustsStack(true);
12889 // And our return value (tls address) is in the standard call return value
12891 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12892 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
12893 Chain.getValue(1));
12896 if (Subtarget->isTargetKnownWindowsMSVC() ||
12897 Subtarget->isTargetWindowsGNU()) {
12898 // Just use the implicit TLS architecture
12899 // Need to generate someting similar to:
12900 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12902 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12903 // mov rcx, qword [rdx+rcx*8]
12904 // mov eax, .tls$:tlsvar
12905 // [rax+rcx] contains the address
12906 // Windows 64bit: gs:0x58
12907 // Windows 32bit: fs:__tls_array
12910 SDValue Chain = DAG.getEntryNode();
12912 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12913 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12914 // use its literal value of 0x2C.
12915 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12916 ? Type::getInt8PtrTy(*DAG.getContext(),
12918 : Type::getInt32PtrTy(*DAG.getContext(),
12922 Subtarget->is64Bit()
12923 ? DAG.getIntPtrConstant(0x58)
12924 : (Subtarget->isTargetWindowsGNU()
12925 ? DAG.getIntPtrConstant(0x2C)
12926 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
12928 SDValue ThreadPointer =
12929 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
12930 MachinePointerInfo(Ptr), false, false, false, 0);
12932 // Load the _tls_index variable
12933 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
12934 if (Subtarget->is64Bit())
12935 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
12936 IDX, MachinePointerInfo(), MVT::i32,
12937 false, false, false, 0);
12939 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
12940 false, false, false, 0);
12942 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
12944 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
12946 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
12947 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
12948 false, false, false, 0);
12950 // Get the offset of start of .tls section
12951 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12952 GA->getValueType(0),
12953 GA->getOffset(), X86II::MO_SECREL);
12954 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
12956 // The address of the thread local variable is the add of the thread
12957 // pointer with the offset of the variable.
12958 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
12961 llvm_unreachable("TLS not implemented for this target.");
12964 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12965 /// and take a 2 x i32 value to shift plus a shift amount.
12966 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12967 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12968 MVT VT = Op.getSimpleValueType();
12969 unsigned VTBits = VT.getSizeInBits();
12971 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12972 SDValue ShOpLo = Op.getOperand(0);
12973 SDValue ShOpHi = Op.getOperand(1);
12974 SDValue ShAmt = Op.getOperand(2);
12975 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12976 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12978 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12979 DAG.getConstant(VTBits - 1, MVT::i8));
12980 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12981 DAG.getConstant(VTBits - 1, MVT::i8))
12982 : DAG.getConstant(0, VT);
12984 SDValue Tmp2, Tmp3;
12985 if (Op.getOpcode() == ISD::SHL_PARTS) {
12986 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12987 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12989 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12990 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12993 // If the shift amount is larger or equal than the width of a part we can't
12994 // rely on the results of shld/shrd. Insert a test and select the appropriate
12995 // values for large shift amounts.
12996 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12997 DAG.getConstant(VTBits, MVT::i8));
12998 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12999 AndNode, DAG.getConstant(0, MVT::i8));
13002 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13003 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13004 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13006 if (Op.getOpcode() == ISD::SHL_PARTS) {
13007 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13008 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13010 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13011 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13014 SDValue Ops[2] = { Lo, Hi };
13015 return DAG.getMergeValues(Ops, dl);
13018 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
13019 SelectionDAG &DAG) const {
13020 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13022 if (SrcVT.isVector())
13025 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
13026 "Unknown SINT_TO_FP to lower!");
13028 // These are really Legal; return the operand so the caller accepts it as
13030 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
13032 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
13033 Subtarget->is64Bit()) {
13038 unsigned Size = SrcVT.getSizeInBits()/8;
13039 MachineFunction &MF = DAG.getMachineFunction();
13040 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
13041 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13042 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13044 MachinePointerInfo::getFixedStack(SSFI),
13046 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13049 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13051 SelectionDAG &DAG) const {
13055 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13057 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13059 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13061 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13063 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13064 MachineMemOperand *MMO;
13066 int SSFI = FI->getIndex();
13068 DAG.getMachineFunction()
13069 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13070 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13072 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13073 StackSlot = StackSlot.getOperand(1);
13075 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13076 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13078 Tys, Ops, SrcVT, MMO);
13081 Chain = Result.getValue(1);
13082 SDValue InFlag = Result.getValue(2);
13084 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13085 // shouldn't be necessary except that RFP cannot be live across
13086 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13087 MachineFunction &MF = DAG.getMachineFunction();
13088 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13089 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13090 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13091 Tys = DAG.getVTList(MVT::Other);
13093 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13095 MachineMemOperand *MMO =
13096 DAG.getMachineFunction()
13097 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13098 MachineMemOperand::MOStore, SSFISize, SSFISize);
13100 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13101 Ops, Op.getValueType(), MMO);
13102 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13103 MachinePointerInfo::getFixedStack(SSFI),
13104 false, false, false, 0);
13110 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13111 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13112 SelectionDAG &DAG) const {
13113 // This algorithm is not obvious. Here it is what we're trying to output:
13116 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13117 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13119 haddpd %xmm0, %xmm0
13121 pshufd $0x4e, %xmm0, %xmm1
13127 LLVMContext *Context = DAG.getContext();
13129 // Build some magic constants.
13130 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13131 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13132 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13134 SmallVector<Constant*,2> CV1;
13136 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13137 APInt(64, 0x4330000000000000ULL))));
13139 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13140 APInt(64, 0x4530000000000000ULL))));
13141 Constant *C1 = ConstantVector::get(CV1);
13142 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13144 // Load the 64-bit value into an XMM register.
13145 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13147 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13148 MachinePointerInfo::getConstantPool(),
13149 false, false, false, 16);
13150 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13151 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13154 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13155 MachinePointerInfo::getConstantPool(),
13156 false, false, false, 16);
13157 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13158 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13161 if (Subtarget->hasSSE3()) {
13162 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13163 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13165 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13166 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13168 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13169 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13173 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13174 DAG.getIntPtrConstant(0));
13177 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13178 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13179 SelectionDAG &DAG) const {
13181 // FP constant to bias correct the final result.
13182 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13185 // Load the 32-bit value into an XMM register.
13186 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13189 // Zero out the upper parts of the register.
13190 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13192 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13193 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13194 DAG.getIntPtrConstant(0));
13196 // Or the load with the bias.
13197 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13198 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13199 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13200 MVT::v2f64, Load)),
13201 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13202 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13203 MVT::v2f64, Bias)));
13204 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13205 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13206 DAG.getIntPtrConstant(0));
13208 // Subtract the bias.
13209 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13211 // Handle final rounding.
13212 EVT DestVT = Op.getValueType();
13214 if (DestVT.bitsLT(MVT::f64))
13215 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13216 DAG.getIntPtrConstant(0));
13217 if (DestVT.bitsGT(MVT::f64))
13218 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13220 // Handle final rounding.
13224 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13225 SelectionDAG &DAG) const {
13226 SDValue N0 = Op.getOperand(0);
13227 MVT SVT = N0.getSimpleValueType();
13230 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
13231 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
13232 "Custom UINT_TO_FP is not supported!");
13234 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13235 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13236 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13239 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13240 SelectionDAG &DAG) const {
13241 SDValue N0 = Op.getOperand(0);
13244 if (Op.getValueType().isVector())
13245 return lowerUINT_TO_FP_vec(Op, DAG);
13247 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13248 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13249 // the optimization here.
13250 if (DAG.SignBitIsZero(N0))
13251 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13253 MVT SrcVT = N0.getSimpleValueType();
13254 MVT DstVT = Op.getSimpleValueType();
13255 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13256 return LowerUINT_TO_FP_i64(Op, DAG);
13257 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13258 return LowerUINT_TO_FP_i32(Op, DAG);
13259 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13262 // Make a 64-bit buffer, and use it to build an FILD.
13263 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13264 if (SrcVT == MVT::i32) {
13265 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13266 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13267 getPointerTy(), StackSlot, WordOff);
13268 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13269 StackSlot, MachinePointerInfo(),
13271 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13272 OffsetSlot, MachinePointerInfo(),
13274 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13278 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13279 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13280 StackSlot, MachinePointerInfo(),
13282 // For i64 source, we need to add the appropriate power of 2 if the input
13283 // was negative. This is the same as the optimization in
13284 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13285 // we must be careful to do the computation in x87 extended precision, not
13286 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13287 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13288 MachineMemOperand *MMO =
13289 DAG.getMachineFunction()
13290 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13291 MachineMemOperand::MOLoad, 8, 8);
13293 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13294 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13295 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13298 APInt FF(32, 0x5F800000ULL);
13300 // Check whether the sign bit is set.
13301 SDValue SignSet = DAG.getSetCC(dl,
13302 getSetCCResultType(*DAG.getContext(), MVT::i64),
13303 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
13306 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
13307 SDValue FudgePtr = DAG.getConstantPool(
13308 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
13311 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
13312 SDValue Zero = DAG.getIntPtrConstant(0);
13313 SDValue Four = DAG.getIntPtrConstant(4);
13314 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
13316 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
13318 // Load the value out, extending it from f32 to f80.
13319 // FIXME: Avoid the extend by constructing the right constant pool?
13320 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
13321 FudgePtr, MachinePointerInfo::getConstantPool(),
13322 MVT::f32, false, false, false, 4);
13323 // Extend everything to 80 bits to force it to be done on x87.
13324 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
13325 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
13328 std::pair<SDValue,SDValue>
13329 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
13330 bool IsSigned, bool IsReplace) const {
13333 EVT DstTy = Op.getValueType();
13335 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
13336 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
13340 assert(DstTy.getSimpleVT() <= MVT::i64 &&
13341 DstTy.getSimpleVT() >= MVT::i16 &&
13342 "Unknown FP_TO_INT to lower!");
13344 // These are really Legal.
13345 if (DstTy == MVT::i32 &&
13346 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13347 return std::make_pair(SDValue(), SDValue());
13348 if (Subtarget->is64Bit() &&
13349 DstTy == MVT::i64 &&
13350 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13351 return std::make_pair(SDValue(), SDValue());
13353 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
13354 // stack slot, or into the FTOL runtime function.
13355 MachineFunction &MF = DAG.getMachineFunction();
13356 unsigned MemSize = DstTy.getSizeInBits()/8;
13357 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13358 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13361 if (!IsSigned && isIntegerTypeFTOL(DstTy))
13362 Opc = X86ISD::WIN_FTOL;
13364 switch (DstTy.getSimpleVT().SimpleTy) {
13365 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
13366 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
13367 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
13368 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
13371 SDValue Chain = DAG.getEntryNode();
13372 SDValue Value = Op.getOperand(0);
13373 EVT TheVT = Op.getOperand(0).getValueType();
13374 // FIXME This causes a redundant load/store if the SSE-class value is already
13375 // in memory, such as if it is on the callstack.
13376 if (isScalarFPTypeInSSEReg(TheVT)) {
13377 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
13378 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
13379 MachinePointerInfo::getFixedStack(SSFI),
13381 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
13383 Chain, StackSlot, DAG.getValueType(TheVT)
13386 MachineMemOperand *MMO =
13387 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13388 MachineMemOperand::MOLoad, MemSize, MemSize);
13389 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
13390 Chain = Value.getValue(1);
13391 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13392 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13395 MachineMemOperand *MMO =
13396 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13397 MachineMemOperand::MOStore, MemSize, MemSize);
13399 if (Opc != X86ISD::WIN_FTOL) {
13400 // Build the FP_TO_INT*_IN_MEM
13401 SDValue Ops[] = { Chain, Value, StackSlot };
13402 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13404 return std::make_pair(FIST, StackSlot);
13406 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
13407 DAG.getVTList(MVT::Other, MVT::Glue),
13409 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
13410 MVT::i32, ftol.getValue(1));
13411 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
13412 MVT::i32, eax.getValue(2));
13413 SDValue Ops[] = { eax, edx };
13414 SDValue pair = IsReplace
13415 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
13416 : DAG.getMergeValues(Ops, DL);
13417 return std::make_pair(pair, SDValue());
13421 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13422 const X86Subtarget *Subtarget) {
13423 MVT VT = Op->getSimpleValueType(0);
13424 SDValue In = Op->getOperand(0);
13425 MVT InVT = In.getSimpleValueType();
13428 // Optimize vectors in AVX mode:
13431 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13432 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13433 // Concat upper and lower parts.
13436 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13437 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13438 // Concat upper and lower parts.
13441 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13442 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13443 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13446 if (Subtarget->hasInt256())
13447 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13449 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13450 SDValue Undef = DAG.getUNDEF(InVT);
13451 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13452 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13453 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13455 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13456 VT.getVectorNumElements()/2);
13458 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
13459 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
13461 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13464 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13465 SelectionDAG &DAG) {
13466 MVT VT = Op->getSimpleValueType(0);
13467 SDValue In = Op->getOperand(0);
13468 MVT InVT = In.getSimpleValueType();
13470 unsigned int NumElts = VT.getVectorNumElements();
13471 if (NumElts != 8 && NumElts != 16)
13474 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13475 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13477 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
13478 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13479 // Now we have only mask extension
13480 assert(InVT.getVectorElementType() == MVT::i1);
13481 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
13482 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13483 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13484 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13485 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13486 MachinePointerInfo::getConstantPool(),
13487 false, false, false, Alignment);
13489 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
13490 if (VT.is512BitVector())
13492 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
13495 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13496 SelectionDAG &DAG) {
13497 if (Subtarget->hasFp256()) {
13498 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13506 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13507 SelectionDAG &DAG) {
13509 MVT VT = Op.getSimpleValueType();
13510 SDValue In = Op.getOperand(0);
13511 MVT SVT = In.getSimpleValueType();
13513 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13514 return LowerZERO_EXTEND_AVX512(Op, DAG);
13516 if (Subtarget->hasFp256()) {
13517 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
13522 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13523 VT.getVectorNumElements() != SVT.getVectorNumElements());
13527 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13529 MVT VT = Op.getSimpleValueType();
13530 SDValue In = Op.getOperand(0);
13531 MVT InVT = In.getSimpleValueType();
13533 if (VT == MVT::i1) {
13534 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13535 "Invalid scalar TRUNCATE operation");
13536 if (InVT.getSizeInBits() >= 32)
13538 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13539 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13541 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13542 "Invalid TRUNCATE operation");
13544 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
13545 if (VT.getVectorElementType().getSizeInBits() >=8)
13546 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13548 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13549 unsigned NumElts = InVT.getVectorNumElements();
13550 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13551 if (InVT.getSizeInBits() < 512) {
13552 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13553 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13557 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
13558 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
13559 SDValue CP = DAG.getConstantPool(C, getPointerTy());
13560 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13561 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
13562 MachinePointerInfo::getConstantPool(),
13563 false, false, false, Alignment);
13564 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
13565 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13566 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13569 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13570 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13571 if (Subtarget->hasInt256()) {
13572 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13573 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
13574 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13576 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13577 DAG.getIntPtrConstant(0));
13580 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13581 DAG.getIntPtrConstant(0));
13582 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13583 DAG.getIntPtrConstant(2));
13584 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13585 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13586 static const int ShufMask[] = {0, 2, 4, 6};
13587 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13590 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13591 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13592 if (Subtarget->hasInt256()) {
13593 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
13595 SmallVector<SDValue,32> pshufbMask;
13596 for (unsigned i = 0; i < 2; ++i) {
13597 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13598 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13599 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13600 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13601 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13602 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13603 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13604 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13605 for (unsigned j = 0; j < 8; ++j)
13606 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13608 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13609 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13610 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
13612 static const int ShufMask[] = {0, 2, -1, -1};
13613 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13615 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13616 DAG.getIntPtrConstant(0));
13617 return DAG.getNode(ISD::BITCAST, DL, VT, In);
13620 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13621 DAG.getIntPtrConstant(0));
13623 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13624 DAG.getIntPtrConstant(4));
13626 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
13627 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
13629 // The PSHUFB mask:
13630 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13631 -1, -1, -1, -1, -1, -1, -1, -1};
13633 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13634 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13635 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13637 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
13638 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
13640 // The MOVLHPS Mask:
13641 static const int ShufMask2[] = {0, 1, 4, 5};
13642 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13643 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
13646 // Handle truncation of V256 to V128 using shuffles.
13647 if (!VT.is128BitVector() || !InVT.is256BitVector())
13650 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13652 unsigned NumElems = VT.getVectorNumElements();
13653 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13655 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13656 // Prepare truncation shuffle mask
13657 for (unsigned i = 0; i != NumElems; ++i)
13658 MaskVec[i] = i * 2;
13659 SDValue V = DAG.getVectorShuffle(NVT, DL,
13660 DAG.getNode(ISD::BITCAST, DL, NVT, In),
13661 DAG.getUNDEF(NVT), &MaskVec[0]);
13662 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13663 DAG.getIntPtrConstant(0));
13666 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13667 SelectionDAG &DAG) const {
13668 assert(!Op.getSimpleValueType().isVector());
13670 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13671 /*IsSigned=*/ true, /*IsReplace=*/ false);
13672 SDValue FIST = Vals.first, StackSlot = Vals.second;
13673 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13674 if (!FIST.getNode()) return Op;
13676 if (StackSlot.getNode())
13677 // Load the result.
13678 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13679 FIST, StackSlot, MachinePointerInfo(),
13680 false, false, false, 0);
13682 // The node is the result.
13686 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13687 SelectionDAG &DAG) const {
13688 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13689 /*IsSigned=*/ false, /*IsReplace=*/ false);
13690 SDValue FIST = Vals.first, StackSlot = Vals.second;
13691 assert(FIST.getNode() && "Unexpected failure");
13693 if (StackSlot.getNode())
13694 // Load the result.
13695 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13696 FIST, StackSlot, MachinePointerInfo(),
13697 false, false, false, 0);
13699 // The node is the result.
13703 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13705 MVT VT = Op.getSimpleValueType();
13706 SDValue In = Op.getOperand(0);
13707 MVT SVT = In.getSimpleValueType();
13709 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13711 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13712 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13713 In, DAG.getUNDEF(SVT)));
13716 /// The only differences between FABS and FNEG are the mask and the logic op.
13717 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
13718 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13719 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13720 "Wrong opcode for lowering FABS or FNEG.");
13722 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13724 // If this is a FABS and it has an FNEG user, bail out to fold the combination
13725 // into an FNABS. We'll lower the FABS after that if it is still in use.
13727 for (SDNode *User : Op->uses())
13728 if (User->getOpcode() == ISD::FNEG)
13731 SDValue Op0 = Op.getOperand(0);
13732 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13735 MVT VT = Op.getSimpleValueType();
13736 // Assume scalar op for initialization; update for vector if needed.
13737 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
13738 // generate a 16-byte vector constant and logic op even for the scalar case.
13739 // Using a 16-byte mask allows folding the load of the mask with
13740 // the logic op, so it can save (~4 bytes) on code size.
13742 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
13743 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13744 // decide if we should generate a 16-byte constant mask when we only need 4 or
13745 // 8 bytes for the scalar case.
13746 if (VT.isVector()) {
13747 EltVT = VT.getVectorElementType();
13748 NumElts = VT.getVectorNumElements();
13751 unsigned EltBits = EltVT.getSizeInBits();
13752 LLVMContext *Context = DAG.getContext();
13753 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13755 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13756 Constant *C = ConstantInt::get(*Context, MaskElt);
13757 C = ConstantVector::getSplat(NumElts, C);
13758 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13759 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
13760 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13761 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13762 MachinePointerInfo::getConstantPool(),
13763 false, false, false, Alignment);
13765 if (VT.isVector()) {
13766 // For a vector, cast operands to a vector type, perform the logic op,
13767 // and cast the result back to the original value type.
13768 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
13769 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
13770 SDValue Operand = IsFNABS ?
13771 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
13772 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
13773 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
13774 return DAG.getNode(ISD::BITCAST, dl, VT,
13775 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
13778 // If not vector, then scalar.
13779 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
13780 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
13781 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
13784 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13785 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13786 LLVMContext *Context = DAG.getContext();
13787 SDValue Op0 = Op.getOperand(0);
13788 SDValue Op1 = Op.getOperand(1);
13790 MVT VT = Op.getSimpleValueType();
13791 MVT SrcVT = Op1.getSimpleValueType();
13793 // If second operand is smaller, extend it first.
13794 if (SrcVT.bitsLT(VT)) {
13795 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13798 // And if it is bigger, shrink it first.
13799 if (SrcVT.bitsGT(VT)) {
13800 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
13804 // At this point the operands and the result should have the same
13805 // type, and that won't be f80 since that is not custom lowered.
13807 // First get the sign bit of second operand.
13808 SmallVector<Constant*,4> CV;
13809 if (SrcVT == MVT::f64) {
13810 const fltSemantics &Sem = APFloat::IEEEdouble;
13811 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
13812 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13814 const fltSemantics &Sem = APFloat::IEEEsingle;
13815 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
13816 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13817 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13818 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13820 Constant *C = ConstantVector::get(CV);
13821 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13822 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
13823 MachinePointerInfo::getConstantPool(),
13824 false, false, false, 16);
13825 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
13827 // Shift sign bit right or left if the two operands have different types.
13828 if (SrcVT.bitsGT(VT)) {
13829 // Op0 is MVT::f32, Op1 is MVT::f64.
13830 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
13831 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
13832 DAG.getConstant(32, MVT::i32));
13833 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
13834 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
13835 DAG.getIntPtrConstant(0));
13838 // Clear first operand sign bit.
13840 if (VT == MVT::f64) {
13841 const fltSemantics &Sem = APFloat::IEEEdouble;
13842 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13843 APInt(64, ~(1ULL << 63)))));
13844 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
13846 const fltSemantics &Sem = APFloat::IEEEsingle;
13847 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
13848 APInt(32, ~(1U << 31)))));
13849 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13850 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13851 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
13853 C = ConstantVector::get(CV);
13854 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
13855 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
13856 MachinePointerInfo::getConstantPool(),
13857 false, false, false, 16);
13858 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
13860 // Or the value with the sign bit.
13861 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
13864 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13865 SDValue N0 = Op.getOperand(0);
13867 MVT VT = Op.getSimpleValueType();
13869 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13870 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13871 DAG.getConstant(1, VT));
13872 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
13875 // Check whether an OR'd tree is PTEST-able.
13876 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13877 SelectionDAG &DAG) {
13878 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13880 if (!Subtarget->hasSSE41())
13883 if (!Op->hasOneUse())
13886 SDNode *N = Op.getNode();
13889 SmallVector<SDValue, 8> Opnds;
13890 DenseMap<SDValue, unsigned> VecInMap;
13891 SmallVector<SDValue, 8> VecIns;
13892 EVT VT = MVT::Other;
13894 // Recognize a special case where a vector is casted into wide integer to
13896 Opnds.push_back(N->getOperand(0));
13897 Opnds.push_back(N->getOperand(1));
13899 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13900 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13901 // BFS traverse all OR'd operands.
13902 if (I->getOpcode() == ISD::OR) {
13903 Opnds.push_back(I->getOperand(0));
13904 Opnds.push_back(I->getOperand(1));
13905 // Re-evaluate the number of nodes to be traversed.
13906 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13910 // Quit if a non-EXTRACT_VECTOR_ELT
13911 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13914 // Quit if without a constant index.
13915 SDValue Idx = I->getOperand(1);
13916 if (!isa<ConstantSDNode>(Idx))
13919 SDValue ExtractedFromVec = I->getOperand(0);
13920 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13921 if (M == VecInMap.end()) {
13922 VT = ExtractedFromVec.getValueType();
13923 // Quit if not 128/256-bit vector.
13924 if (!VT.is128BitVector() && !VT.is256BitVector())
13926 // Quit if not the same type.
13927 if (VecInMap.begin() != VecInMap.end() &&
13928 VT != VecInMap.begin()->first.getValueType())
13930 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13931 VecIns.push_back(ExtractedFromVec);
13933 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13936 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13937 "Not extracted from 128-/256-bit vector.");
13939 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13941 for (DenseMap<SDValue, unsigned>::const_iterator
13942 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13943 // Quit if not all elements are used.
13944 if (I->second != FullMask)
13948 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13950 // Cast all vectors into TestVT for PTEST.
13951 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13952 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
13954 // If more than one full vectors are evaluated, OR them first before PTEST.
13955 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13956 // Each iteration will OR 2 nodes and append the result until there is only
13957 // 1 node left, i.e. the final OR'd value of all vectors.
13958 SDValue LHS = VecIns[Slot];
13959 SDValue RHS = VecIns[Slot + 1];
13960 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13963 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13964 VecIns.back(), VecIns.back());
13967 /// \brief return true if \c Op has a use that doesn't just read flags.
13968 static bool hasNonFlagsUse(SDValue Op) {
13969 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13971 SDNode *User = *UI;
13972 unsigned UOpNo = UI.getOperandNo();
13973 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13974 // Look pass truncate.
13975 UOpNo = User->use_begin().getOperandNo();
13976 User = *User->use_begin();
13979 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13980 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13986 /// Emit nodes that will be selected as "test Op0,Op0", or something
13988 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13989 SelectionDAG &DAG) const {
13990 if (Op.getValueType() == MVT::i1)
13991 // KORTEST instruction should be selected
13992 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13993 DAG.getConstant(0, Op.getValueType()));
13995 // CF and OF aren't always set the way we want. Determine which
13996 // of these we need.
13997 bool NeedCF = false;
13998 bool NeedOF = false;
14001 case X86::COND_A: case X86::COND_AE:
14002 case X86::COND_B: case X86::COND_BE:
14005 case X86::COND_G: case X86::COND_GE:
14006 case X86::COND_L: case X86::COND_LE:
14007 case X86::COND_O: case X86::COND_NO: {
14008 // Check if we really need to set the
14009 // Overflow flag. If NoSignedWrap is present
14010 // that is not actually needed.
14011 switch (Op->getOpcode()) {
14016 const BinaryWithFlagsSDNode *BinNode =
14017 cast<BinaryWithFlagsSDNode>(Op.getNode());
14018 if (BinNode->hasNoSignedWrap())
14028 // See if we can use the EFLAGS value from the operand instead of
14029 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
14030 // we prove that the arithmetic won't overflow, we can't use OF or CF.
14031 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
14032 // Emit a CMP with 0, which is the TEST pattern.
14033 //if (Op.getValueType() == MVT::i1)
14034 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
14035 // DAG.getConstant(0, MVT::i1));
14036 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14037 DAG.getConstant(0, Op.getValueType()));
14039 unsigned Opcode = 0;
14040 unsigned NumOperands = 0;
14042 // Truncate operations may prevent the merge of the SETCC instruction
14043 // and the arithmetic instruction before it. Attempt to truncate the operands
14044 // of the arithmetic instruction and use a reduced bit-width instruction.
14045 bool NeedTruncation = false;
14046 SDValue ArithOp = Op;
14047 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
14048 SDValue Arith = Op->getOperand(0);
14049 // Both the trunc and the arithmetic op need to have one user each.
14050 if (Arith->hasOneUse())
14051 switch (Arith.getOpcode()) {
14058 NeedTruncation = true;
14064 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14065 // which may be the result of a CAST. We use the variable 'Op', which is the
14066 // non-casted variable when we check for possible users.
14067 switch (ArithOp.getOpcode()) {
14069 // Due to an isel shortcoming, be conservative if this add is likely to be
14070 // selected as part of a load-modify-store instruction. When the root node
14071 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14072 // uses of other nodes in the match, such as the ADD in this case. This
14073 // leads to the ADD being left around and reselected, with the result being
14074 // two adds in the output. Alas, even if none our users are stores, that
14075 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14076 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14077 // climbing the DAG back to the root, and it doesn't seem to be worth the
14079 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14080 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14081 if (UI->getOpcode() != ISD::CopyToReg &&
14082 UI->getOpcode() != ISD::SETCC &&
14083 UI->getOpcode() != ISD::STORE)
14086 if (ConstantSDNode *C =
14087 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14088 // An add of one will be selected as an INC.
14089 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14090 Opcode = X86ISD::INC;
14095 // An add of negative one (subtract of one) will be selected as a DEC.
14096 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14097 Opcode = X86ISD::DEC;
14103 // Otherwise use a regular EFLAGS-setting add.
14104 Opcode = X86ISD::ADD;
14109 // If we have a constant logical shift that's only used in a comparison
14110 // against zero turn it into an equivalent AND. This allows turning it into
14111 // a TEST instruction later.
14112 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14113 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14114 EVT VT = Op.getValueType();
14115 unsigned BitWidth = VT.getSizeInBits();
14116 unsigned ShAmt = Op->getConstantOperandVal(1);
14117 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14119 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14120 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14121 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14122 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14124 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14125 DAG.getConstant(Mask, VT));
14126 DAG.ReplaceAllUsesWith(Op, New);
14132 // If the primary and result isn't used, don't bother using X86ISD::AND,
14133 // because a TEST instruction will be better.
14134 if (!hasNonFlagsUse(Op))
14140 // Due to the ISEL shortcoming noted above, be conservative if this op is
14141 // likely to be selected as part of a load-modify-store instruction.
14142 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14143 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14144 if (UI->getOpcode() == ISD::STORE)
14147 // Otherwise use a regular EFLAGS-setting instruction.
14148 switch (ArithOp.getOpcode()) {
14149 default: llvm_unreachable("unexpected operator!");
14150 case ISD::SUB: Opcode = X86ISD::SUB; break;
14151 case ISD::XOR: Opcode = X86ISD::XOR; break;
14152 case ISD::AND: Opcode = X86ISD::AND; break;
14154 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14155 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14156 if (EFLAGS.getNode())
14159 Opcode = X86ISD::OR;
14173 return SDValue(Op.getNode(), 1);
14179 // If we found that truncation is beneficial, perform the truncation and
14181 if (NeedTruncation) {
14182 EVT VT = Op.getValueType();
14183 SDValue WideVal = Op->getOperand(0);
14184 EVT WideVT = WideVal.getValueType();
14185 unsigned ConvertedOp = 0;
14186 // Use a target machine opcode to prevent further DAGCombine
14187 // optimizations that may separate the arithmetic operations
14188 // from the setcc node.
14189 switch (WideVal.getOpcode()) {
14191 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14192 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14193 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14194 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14195 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14199 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14200 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14201 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14202 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14203 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14209 // Emit a CMP with 0, which is the TEST pattern.
14210 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14211 DAG.getConstant(0, Op.getValueType()));
14213 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14214 SmallVector<SDValue, 4> Ops;
14215 for (unsigned i = 0; i != NumOperands; ++i)
14216 Ops.push_back(Op.getOperand(i));
14218 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14219 DAG.ReplaceAllUsesWith(Op, New);
14220 return SDValue(New.getNode(), 1);
14223 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14225 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14226 SDLoc dl, SelectionDAG &DAG) const {
14227 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14228 if (C->getAPIntValue() == 0)
14229 return EmitTest(Op0, X86CC, dl, DAG);
14231 if (Op0.getValueType() == MVT::i1)
14232 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14235 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14236 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14237 // Do the comparison at i32 if it's smaller, besides the Atom case.
14238 // This avoids subregister aliasing issues. Keep the smaller reference
14239 // if we're optimizing for size, however, as that'll allow better folding
14240 // of memory operations.
14241 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14242 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14243 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14244 !Subtarget->isAtom()) {
14245 unsigned ExtendOp =
14246 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14247 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14248 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14250 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14251 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14252 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14254 return SDValue(Sub.getNode(), 1);
14256 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14259 /// Convert a comparison if required by the subtarget.
14260 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14261 SelectionDAG &DAG) const {
14262 // If the subtarget does not support the FUCOMI instruction, floating-point
14263 // comparisons have to be converted.
14264 if (Subtarget->hasCMov() ||
14265 Cmp.getOpcode() != X86ISD::CMP ||
14266 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14267 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14270 // The instruction selector will select an FUCOM instruction instead of
14271 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14272 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14273 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14275 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14276 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14277 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14278 DAG.getConstant(8, MVT::i8));
14279 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14280 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14283 static bool isAllOnes(SDValue V) {
14284 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
14285 return C && C->isAllOnesValue();
14288 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14289 /// if it's possible.
14290 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14291 SDLoc dl, SelectionDAG &DAG) const {
14292 SDValue Op0 = And.getOperand(0);
14293 SDValue Op1 = And.getOperand(1);
14294 if (Op0.getOpcode() == ISD::TRUNCATE)
14295 Op0 = Op0.getOperand(0);
14296 if (Op1.getOpcode() == ISD::TRUNCATE)
14297 Op1 = Op1.getOperand(0);
14300 if (Op1.getOpcode() == ISD::SHL)
14301 std::swap(Op0, Op1);
14302 if (Op0.getOpcode() == ISD::SHL) {
14303 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
14304 if (And00C->getZExtValue() == 1) {
14305 // If we looked past a truncate, check that it's only truncating away
14307 unsigned BitWidth = Op0.getValueSizeInBits();
14308 unsigned AndBitWidth = And.getValueSizeInBits();
14309 if (BitWidth > AndBitWidth) {
14311 DAG.computeKnownBits(Op0, Zeros, Ones);
14312 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
14316 RHS = Op0.getOperand(1);
14318 } else if (Op1.getOpcode() == ISD::Constant) {
14319 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
14320 uint64_t AndRHSVal = AndRHS->getZExtValue();
14321 SDValue AndLHS = Op0;
14323 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
14324 LHS = AndLHS.getOperand(0);
14325 RHS = AndLHS.getOperand(1);
14328 // Use BT if the immediate can't be encoded in a TEST instruction.
14329 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
14331 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
14335 if (LHS.getNode()) {
14336 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
14337 // instruction. Since the shift amount is in-range-or-undefined, we know
14338 // that doing a bittest on the i32 value is ok. We extend to i32 because
14339 // the encoding for the i16 version is larger than the i32 version.
14340 // Also promote i16 to i32 for performance / code size reason.
14341 if (LHS.getValueType() == MVT::i8 ||
14342 LHS.getValueType() == MVT::i16)
14343 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
14345 // If the operand types disagree, extend the shift amount to match. Since
14346 // BT ignores high bits (like shifts) we can use anyextend.
14347 if (LHS.getValueType() != RHS.getValueType())
14348 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
14350 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
14351 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
14352 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14353 DAG.getConstant(Cond, MVT::i8), BT);
14359 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
14361 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14366 // SSE Condition code mapping:
14375 switch (SetCCOpcode) {
14376 default: llvm_unreachable("Unexpected SETCC condition");
14378 case ISD::SETEQ: SSECC = 0; break;
14380 case ISD::SETGT: Swap = true; // Fallthrough
14382 case ISD::SETOLT: SSECC = 1; break;
14384 case ISD::SETGE: Swap = true; // Fallthrough
14386 case ISD::SETOLE: SSECC = 2; break;
14387 case ISD::SETUO: SSECC = 3; break;
14389 case ISD::SETNE: SSECC = 4; break;
14390 case ISD::SETULE: Swap = true; // Fallthrough
14391 case ISD::SETUGE: SSECC = 5; break;
14392 case ISD::SETULT: Swap = true; // Fallthrough
14393 case ISD::SETUGT: SSECC = 6; break;
14394 case ISD::SETO: SSECC = 7; break;
14396 case ISD::SETONE: SSECC = 8; break;
14399 std::swap(Op0, Op1);
14404 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14405 // ones, and then concatenate the result back.
14406 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14407 MVT VT = Op.getSimpleValueType();
14409 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14410 "Unsupported value type for operation");
14412 unsigned NumElems = VT.getVectorNumElements();
14414 SDValue CC = Op.getOperand(2);
14416 // Extract the LHS vectors
14417 SDValue LHS = Op.getOperand(0);
14418 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14419 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14421 // Extract the RHS vectors
14422 SDValue RHS = Op.getOperand(1);
14423 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14424 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14426 // Issue the operation on the smaller types and concatenate the result back
14427 MVT EltVT = VT.getVectorElementType();
14428 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14429 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14430 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14431 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14434 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14435 const X86Subtarget *Subtarget) {
14436 SDValue Op0 = Op.getOperand(0);
14437 SDValue Op1 = Op.getOperand(1);
14438 SDValue CC = Op.getOperand(2);
14439 MVT VT = Op.getSimpleValueType();
14442 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
14443 Op.getValueType().getScalarType() == MVT::i1 &&
14444 "Cannot set masked compare for this operation");
14446 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14448 bool Unsigned = false;
14451 switch (SetCCOpcode) {
14452 default: llvm_unreachable("Unexpected SETCC condition");
14453 case ISD::SETNE: SSECC = 4; break;
14454 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14455 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14456 case ISD::SETLT: Swap = true; //fall-through
14457 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14458 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14459 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14460 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14461 case ISD::SETULE: Unsigned = true; //fall-through
14462 case ISD::SETLE: SSECC = 2; break;
14466 std::swap(Op0, Op1);
14468 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14469 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14470 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14471 DAG.getConstant(SSECC, MVT::i8));
14474 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14475 /// operand \p Op1. If non-trivial (for example because it's not constant)
14476 /// return an empty value.
14477 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14479 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14483 MVT VT = Op1.getSimpleValueType();
14484 MVT EVT = VT.getVectorElementType();
14485 unsigned n = VT.getVectorNumElements();
14486 SmallVector<SDValue, 8> ULTOp1;
14488 for (unsigned i = 0; i < n; ++i) {
14489 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14490 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
14493 // Avoid underflow.
14494 APInt Val = Elt->getAPIntValue();
14498 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
14501 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14504 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14505 SelectionDAG &DAG) {
14506 SDValue Op0 = Op.getOperand(0);
14507 SDValue Op1 = Op.getOperand(1);
14508 SDValue CC = Op.getOperand(2);
14509 MVT VT = Op.getSimpleValueType();
14510 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14511 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14516 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14517 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14520 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14521 unsigned Opc = X86ISD::CMPP;
14522 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14523 assert(VT.getVectorNumElements() <= 16);
14524 Opc = X86ISD::CMPM;
14526 // In the two special cases we can't handle, emit two comparisons.
14529 unsigned CombineOpc;
14530 if (SetCCOpcode == ISD::SETUEQ) {
14531 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14533 assert(SetCCOpcode == ISD::SETONE);
14534 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14537 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14538 DAG.getConstant(CC0, MVT::i8));
14539 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14540 DAG.getConstant(CC1, MVT::i8));
14541 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14543 // Handle all other FP comparisons here.
14544 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14545 DAG.getConstant(SSECC, MVT::i8));
14548 // Break 256-bit integer vector compare into smaller ones.
14549 if (VT.is256BitVector() && !Subtarget->hasInt256())
14550 return Lower256IntVSETCC(Op, DAG);
14552 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14553 EVT OpVT = Op1.getValueType();
14554 if (Subtarget->hasAVX512()) {
14555 if (Op1.getValueType().is512BitVector() ||
14556 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14557 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14558 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14560 // In AVX-512 architecture setcc returns mask with i1 elements,
14561 // But there is no compare instruction for i8 and i16 elements in KNL.
14562 // We are not talking about 512-bit operands in this case, these
14563 // types are illegal.
14565 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14566 OpVT.getVectorElementType().getSizeInBits() >= 8))
14567 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14568 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14571 // We are handling one of the integer comparisons here. Since SSE only has
14572 // GT and EQ comparisons for integer, swapping operands and multiple
14573 // operations may be required for some comparisons.
14575 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14576 bool Subus = false;
14578 switch (SetCCOpcode) {
14579 default: llvm_unreachable("Unexpected SETCC condition");
14580 case ISD::SETNE: Invert = true;
14581 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14582 case ISD::SETLT: Swap = true;
14583 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14584 case ISD::SETGE: Swap = true;
14585 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14586 Invert = true; break;
14587 case ISD::SETULT: Swap = true;
14588 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14589 FlipSigns = true; break;
14590 case ISD::SETUGE: Swap = true;
14591 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14592 FlipSigns = true; Invert = true; break;
14595 // Special case: Use min/max operations for SETULE/SETUGE
14596 MVT VET = VT.getVectorElementType();
14598 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14599 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14602 switch (SetCCOpcode) {
14604 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
14605 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
14608 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14611 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14612 if (!MinMax && hasSubus) {
14613 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14615 // t = psubus Op0, Op1
14616 // pcmpeq t, <0..0>
14617 switch (SetCCOpcode) {
14619 case ISD::SETULT: {
14620 // If the comparison is against a constant we can turn this into a
14621 // setule. With psubus, setule does not require a swap. This is
14622 // beneficial because the constant in the register is no longer
14623 // destructed as the destination so it can be hoisted out of a loop.
14624 // Only do this pre-AVX since vpcmp* is no longer destructive.
14625 if (Subtarget->hasAVX())
14627 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14628 if (ULEOp1.getNode()) {
14630 Subus = true; Invert = false; Swap = false;
14634 // Psubus is better than flip-sign because it requires no inversion.
14635 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14636 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14640 Opc = X86ISD::SUBUS;
14646 std::swap(Op0, Op1);
14648 // Check that the operation in question is available (most are plain SSE2,
14649 // but PCMPGTQ and PCMPEQQ have different requirements).
14650 if (VT == MVT::v2i64) {
14651 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14652 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14654 // First cast everything to the right type.
14655 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14656 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14658 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14659 // bits of the inputs before performing those operations. The lower
14660 // compare is always unsigned.
14663 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
14665 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
14666 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
14667 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14668 Sign, Zero, Sign, Zero);
14670 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14671 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14673 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14674 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14675 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14677 // Create masks for only the low parts/high parts of the 64 bit integers.
14678 static const int MaskHi[] = { 1, 1, 3, 3 };
14679 static const int MaskLo[] = { 0, 0, 2, 2 };
14680 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14681 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14682 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14684 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14685 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14688 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14690 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14693 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14694 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14695 // pcmpeqd + pshufd + pand.
14696 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14698 // First cast everything to the right type.
14699 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
14700 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
14703 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14705 // Make sure the lower and upper halves are both all-ones.
14706 static const int Mask[] = { 1, 0, 3, 2 };
14707 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14708 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14711 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14713 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
14717 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14718 // bits of the inputs before performing those operations.
14720 EVT EltVT = VT.getVectorElementType();
14721 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
14722 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14723 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14726 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14728 // If the logical-not of the result is required, perform that now.
14730 Result = DAG.getNOT(dl, Result, VT);
14733 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14736 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14737 getZeroVector(VT, Subtarget, DAG, dl));
14742 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14744 MVT VT = Op.getSimpleValueType();
14746 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14748 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14749 && "SetCC type must be 8-bit or 1-bit integer");
14750 SDValue Op0 = Op.getOperand(0);
14751 SDValue Op1 = Op.getOperand(1);
14753 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14755 // Optimize to BT if possible.
14756 // Lower (X & (1 << N)) == 0 to BT(X, N).
14757 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14758 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14759 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14760 Op1.getOpcode() == ISD::Constant &&
14761 cast<ConstantSDNode>(Op1)->isNullValue() &&
14762 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14763 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14764 if (NewSetCC.getNode())
14768 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14770 if (Op1.getOpcode() == ISD::Constant &&
14771 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14772 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14773 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14775 // If the input is a setcc, then reuse the input setcc or use a new one with
14776 // the inverted condition.
14777 if (Op0.getOpcode() == X86ISD::SETCC) {
14778 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14779 bool Invert = (CC == ISD::SETNE) ^
14780 cast<ConstantSDNode>(Op1)->isNullValue();
14784 CCode = X86::GetOppositeBranchCondition(CCode);
14785 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14786 DAG.getConstant(CCode, MVT::i8),
14787 Op0.getOperand(1));
14789 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14793 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14794 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14795 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14797 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14798 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
14801 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14802 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
14803 if (X86CC == X86::COND_INVALID)
14806 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14807 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14808 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14809 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
14811 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14815 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14816 static bool isX86LogicalCmp(SDValue Op) {
14817 unsigned Opc = Op.getNode()->getOpcode();
14818 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14819 Opc == X86ISD::SAHF)
14821 if (Op.getResNo() == 1 &&
14822 (Opc == X86ISD::ADD ||
14823 Opc == X86ISD::SUB ||
14824 Opc == X86ISD::ADC ||
14825 Opc == X86ISD::SBB ||
14826 Opc == X86ISD::SMUL ||
14827 Opc == X86ISD::UMUL ||
14828 Opc == X86ISD::INC ||
14829 Opc == X86ISD::DEC ||
14830 Opc == X86ISD::OR ||
14831 Opc == X86ISD::XOR ||
14832 Opc == X86ISD::AND))
14835 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14841 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14842 if (V.getOpcode() != ISD::TRUNCATE)
14845 SDValue VOp0 = V.getOperand(0);
14846 unsigned InBits = VOp0.getValueSizeInBits();
14847 unsigned Bits = V.getValueSizeInBits();
14848 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14851 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14852 bool addTest = true;
14853 SDValue Cond = Op.getOperand(0);
14854 SDValue Op1 = Op.getOperand(1);
14855 SDValue Op2 = Op.getOperand(2);
14857 EVT VT = Op1.getValueType();
14860 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14861 // are available. Otherwise fp cmovs get lowered into a less efficient branch
14862 // sequence later on.
14863 if (Cond.getOpcode() == ISD::SETCC &&
14864 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14865 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14866 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14867 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14868 int SSECC = translateX86FSETCC(
14869 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14872 if (Subtarget->hasAVX512()) {
14873 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14874 DAG.getConstant(SSECC, MVT::i8));
14875 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14877 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14878 DAG.getConstant(SSECC, MVT::i8));
14879 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14880 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14881 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14885 if (Cond.getOpcode() == ISD::SETCC) {
14886 SDValue NewCond = LowerSETCC(Cond, DAG);
14887 if (NewCond.getNode())
14891 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14892 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14893 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14894 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14895 if (Cond.getOpcode() == X86ISD::SETCC &&
14896 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14897 isZero(Cond.getOperand(1).getOperand(1))) {
14898 SDValue Cmp = Cond.getOperand(1);
14900 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14902 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14903 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14904 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14906 SDValue CmpOp0 = Cmp.getOperand(0);
14907 // Apply further optimizations for special cases
14908 // (select (x != 0), -1, 0) -> neg & sbb
14909 // (select (x == 0), 0, -1) -> neg & sbb
14910 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14911 if (YC->isNullValue() &&
14912 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14913 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14914 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14915 DAG.getConstant(0, CmpOp0.getValueType()),
14917 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14918 DAG.getConstant(X86::COND_B, MVT::i8),
14919 SDValue(Neg.getNode(), 1));
14923 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14924 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
14925 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14927 SDValue Res = // Res = 0 or -1.
14928 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14929 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
14931 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14932 Res = DAG.getNOT(DL, Res, Res.getValueType());
14934 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14935 if (!N2C || !N2C->isNullValue())
14936 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14941 // Look past (and (setcc_carry (cmp ...)), 1).
14942 if (Cond.getOpcode() == ISD::AND &&
14943 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14944 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14945 if (C && C->getAPIntValue() == 1)
14946 Cond = Cond.getOperand(0);
14949 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14950 // setting operand in place of the X86ISD::SETCC.
14951 unsigned CondOpcode = Cond.getOpcode();
14952 if (CondOpcode == X86ISD::SETCC ||
14953 CondOpcode == X86ISD::SETCC_CARRY) {
14954 CC = Cond.getOperand(0);
14956 SDValue Cmp = Cond.getOperand(1);
14957 unsigned Opc = Cmp.getOpcode();
14958 MVT VT = Op.getSimpleValueType();
14960 bool IllegalFPCMov = false;
14961 if (VT.isFloatingPoint() && !VT.isVector() &&
14962 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14963 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14965 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14966 Opc == X86ISD::BT) { // FIXME
14970 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14971 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14972 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14973 Cond.getOperand(0).getValueType() != MVT::i8)) {
14974 SDValue LHS = Cond.getOperand(0);
14975 SDValue RHS = Cond.getOperand(1);
14976 unsigned X86Opcode;
14979 switch (CondOpcode) {
14980 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14981 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14982 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14983 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14984 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14985 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14986 default: llvm_unreachable("unexpected overflowing operator");
14988 if (CondOpcode == ISD::UMULO)
14989 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14992 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14994 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14996 if (CondOpcode == ISD::UMULO)
14997 Cond = X86Op.getValue(2);
14999 Cond = X86Op.getValue(1);
15001 CC = DAG.getConstant(X86Cond, MVT::i8);
15006 // Look pass the truncate if the high bits are known zero.
15007 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15008 Cond = Cond.getOperand(0);
15010 // We know the result of AND is compared against zero. Try to match
15012 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15013 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
15014 if (NewSetCC.getNode()) {
15015 CC = NewSetCC.getOperand(0);
15016 Cond = NewSetCC.getOperand(1);
15023 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15024 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15027 // a < b ? -1 : 0 -> RES = ~setcc_carry
15028 // a < b ? 0 : -1 -> RES = setcc_carry
15029 // a >= b ? -1 : 0 -> RES = setcc_carry
15030 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15031 if (Cond.getOpcode() == X86ISD::SUB) {
15032 Cond = ConvertCmpIfNecessary(Cond, DAG);
15033 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15035 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15036 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
15037 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15038 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
15039 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
15040 return DAG.getNOT(DL, Res, Res.getValueType());
15045 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15046 // widen the cmov and push the truncate through. This avoids introducing a new
15047 // branch during isel and doesn't add any extensions.
15048 if (Op.getValueType() == MVT::i8 &&
15049 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15050 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15051 if (T1.getValueType() == T2.getValueType() &&
15052 // Blacklist CopyFromReg to avoid partial register stalls.
15053 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15054 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15055 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15056 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15060 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15061 // condition is true.
15062 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15063 SDValue Ops[] = { Op2, Op1, CC, Cond };
15064 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15067 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
15068 MVT VT = Op->getSimpleValueType(0);
15069 SDValue In = Op->getOperand(0);
15070 MVT InVT = In.getSimpleValueType();
15073 unsigned int NumElts = VT.getVectorNumElements();
15074 if (NumElts != 8 && NumElts != 16)
15077 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
15078 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15080 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15081 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15083 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15084 Constant *C = ConstantInt::get(*DAG.getContext(),
15085 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15087 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15088 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15089 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15090 MachinePointerInfo::getConstantPool(),
15091 false, false, false, Alignment);
15092 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15093 if (VT.is512BitVector())
15095 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15098 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15099 SelectionDAG &DAG) {
15100 MVT VT = Op->getSimpleValueType(0);
15101 SDValue In = Op->getOperand(0);
15102 MVT InVT = In.getSimpleValueType();
15105 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15106 return LowerSIGN_EXTEND_AVX512(Op, DAG);
15108 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15109 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15110 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15113 if (Subtarget->hasInt256())
15114 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15116 // Optimize vectors in AVX mode
15117 // Sign extend v8i16 to v8i32 and
15120 // Divide input vector into two parts
15121 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15122 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15123 // concat the vectors to original VT
15125 unsigned NumElems = InVT.getVectorNumElements();
15126 SDValue Undef = DAG.getUNDEF(InVT);
15128 SmallVector<int,8> ShufMask1(NumElems, -1);
15129 for (unsigned i = 0; i != NumElems/2; ++i)
15132 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15134 SmallVector<int,8> ShufMask2(NumElems, -1);
15135 for (unsigned i = 0; i != NumElems/2; ++i)
15136 ShufMask2[i] = i + NumElems/2;
15138 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15140 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15141 VT.getVectorNumElements()/2);
15143 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15144 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15146 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15149 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15150 // may emit an illegal shuffle but the expansion is still better than scalar
15151 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15152 // we'll emit a shuffle and a arithmetic shift.
15153 // TODO: It is possible to support ZExt by zeroing the undef values during
15154 // the shuffle phase or after the shuffle.
15155 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15156 SelectionDAG &DAG) {
15157 MVT RegVT = Op.getSimpleValueType();
15158 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15159 assert(RegVT.isInteger() &&
15160 "We only custom lower integer vector sext loads.");
15162 // Nothing useful we can do without SSE2 shuffles.
15163 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15165 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15167 EVT MemVT = Ld->getMemoryVT();
15168 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15169 unsigned RegSz = RegVT.getSizeInBits();
15171 ISD::LoadExtType Ext = Ld->getExtensionType();
15173 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15174 && "Only anyext and sext are currently implemented.");
15175 assert(MemVT != RegVT && "Cannot extend to the same type");
15176 assert(MemVT.isVector() && "Must load a vector from memory");
15178 unsigned NumElems = RegVT.getVectorNumElements();
15179 unsigned MemSz = MemVT.getSizeInBits();
15180 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15182 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15183 // The only way in which we have a legal 256-bit vector result but not the
15184 // integer 256-bit operations needed to directly lower a sextload is if we
15185 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15186 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15187 // correctly legalized. We do this late to allow the canonical form of
15188 // sextload to persist throughout the rest of the DAG combiner -- it wants
15189 // to fold together any extensions it can, and so will fuse a sign_extend
15190 // of an sextload into a sextload targeting a wider value.
15192 if (MemSz == 128) {
15193 // Just switch this to a normal load.
15194 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15195 "it must be a legal 128-bit vector "
15197 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15198 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15199 Ld->isInvariant(), Ld->getAlignment());
15201 assert(MemSz < 128 &&
15202 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15203 // Do an sext load to a 128-bit vector type. We want to use the same
15204 // number of elements, but elements half as wide. This will end up being
15205 // recursively lowered by this routine, but will succeed as we definitely
15206 // have all the necessary features if we're using AVX1.
15208 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15209 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15211 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15212 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15213 Ld->isNonTemporal(), Ld->isInvariant(),
15214 Ld->getAlignment());
15217 // Replace chain users with the new chain.
15218 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15219 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15221 // Finally, do a normal sign-extend to the desired register.
15222 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15225 // All sizes must be a power of two.
15226 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15227 "Non-power-of-two elements are not custom lowered!");
15229 // Attempt to load the original value using scalar loads.
15230 // Find the largest scalar type that divides the total loaded size.
15231 MVT SclrLoadTy = MVT::i8;
15232 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15233 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15234 MVT Tp = (MVT::SimpleValueType)tp;
15235 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15240 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15241 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15243 SclrLoadTy = MVT::f64;
15245 // Calculate the number of scalar loads that we need to perform
15246 // in order to load our vector from memory.
15247 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15249 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15250 "Can only lower sext loads with a single scalar load!");
15252 unsigned loadRegZize = RegSz;
15253 if (Ext == ISD::SEXTLOAD && RegSz == 256)
15256 // Represent our vector as a sequence of elements which are the
15257 // largest scalar that we can load.
15258 EVT LoadUnitVecVT = EVT::getVectorVT(
15259 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15261 // Represent the data using the same element type that is stored in
15262 // memory. In practice, we ''widen'' MemVT.
15264 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15265 loadRegZize / MemVT.getScalarType().getSizeInBits());
15267 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15268 "Invalid vector type");
15270 // We can't shuffle using an illegal type.
15271 assert(TLI.isTypeLegal(WideVecVT) &&
15272 "We only lower types that form legal widened vector types");
15274 SmallVector<SDValue, 8> Chains;
15275 SDValue Ptr = Ld->getBasePtr();
15276 SDValue Increment =
15277 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
15278 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15280 for (unsigned i = 0; i < NumLoads; ++i) {
15281 // Perform a single load.
15282 SDValue ScalarLoad =
15283 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15284 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15285 Ld->getAlignment());
15286 Chains.push_back(ScalarLoad.getValue(1));
15287 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15288 // another round of DAGCombining.
15290 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15292 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15293 ScalarLoad, DAG.getIntPtrConstant(i));
15295 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15298 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15300 // Bitcast the loaded value to a vector of the original element type, in
15301 // the size of the target vector type.
15302 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
15303 unsigned SizeRatio = RegSz / MemSz;
15305 if (Ext == ISD::SEXTLOAD) {
15306 // If we have SSE4.1, we can directly emit a VSEXT node.
15307 if (Subtarget->hasSSE41()) {
15308 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15309 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15313 // Otherwise we'll shuffle the small elements in the high bits of the
15314 // larger type and perform an arithmetic shift. If the shift is not legal
15315 // it's better to scalarize.
15316 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
15317 "We can't implement a sext load without an arithmetic right shift!");
15319 // Redistribute the loaded elements into the different locations.
15320 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15321 for (unsigned i = 0; i != NumElems; ++i)
15322 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
15324 SDValue Shuff = DAG.getVectorShuffle(
15325 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15327 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15329 // Build the arithmetic shift.
15330 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
15331 MemVT.getVectorElementType().getSizeInBits();
15333 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
15335 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15339 // Redistribute the loaded elements into the different locations.
15340 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15341 for (unsigned i = 0; i != NumElems; ++i)
15342 ShuffleVec[i * SizeRatio] = i;
15344 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15345 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15347 // Bitcast to the requested type.
15348 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
15349 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15353 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15354 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15355 // from the AND / OR.
15356 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15357 Opc = Op.getOpcode();
15358 if (Opc != ISD::OR && Opc != ISD::AND)
15360 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15361 Op.getOperand(0).hasOneUse() &&
15362 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15363 Op.getOperand(1).hasOneUse());
15366 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15367 // 1 and that the SETCC node has a single use.
15368 static bool isXor1OfSetCC(SDValue Op) {
15369 if (Op.getOpcode() != ISD::XOR)
15371 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15372 if (N1C && N1C->getAPIntValue() == 1) {
15373 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15374 Op.getOperand(0).hasOneUse();
15379 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15380 bool addTest = true;
15381 SDValue Chain = Op.getOperand(0);
15382 SDValue Cond = Op.getOperand(1);
15383 SDValue Dest = Op.getOperand(2);
15386 bool Inverted = false;
15388 if (Cond.getOpcode() == ISD::SETCC) {
15389 // Check for setcc([su]{add,sub,mul}o == 0).
15390 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15391 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15392 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15393 Cond.getOperand(0).getResNo() == 1 &&
15394 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15395 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15396 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15397 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15398 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15399 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15401 Cond = Cond.getOperand(0);
15403 SDValue NewCond = LowerSETCC(Cond, DAG);
15404 if (NewCond.getNode())
15409 // FIXME: LowerXALUO doesn't handle these!!
15410 else if (Cond.getOpcode() == X86ISD::ADD ||
15411 Cond.getOpcode() == X86ISD::SUB ||
15412 Cond.getOpcode() == X86ISD::SMUL ||
15413 Cond.getOpcode() == X86ISD::UMUL)
15414 Cond = LowerXALUO(Cond, DAG);
15417 // Look pass (and (setcc_carry (cmp ...)), 1).
15418 if (Cond.getOpcode() == ISD::AND &&
15419 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15420 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15421 if (C && C->getAPIntValue() == 1)
15422 Cond = Cond.getOperand(0);
15425 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15426 // setting operand in place of the X86ISD::SETCC.
15427 unsigned CondOpcode = Cond.getOpcode();
15428 if (CondOpcode == X86ISD::SETCC ||
15429 CondOpcode == X86ISD::SETCC_CARRY) {
15430 CC = Cond.getOperand(0);
15432 SDValue Cmp = Cond.getOperand(1);
15433 unsigned Opc = Cmp.getOpcode();
15434 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15435 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15439 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15443 // These can only come from an arithmetic instruction with overflow,
15444 // e.g. SADDO, UADDO.
15445 Cond = Cond.getNode()->getOperand(1);
15451 CondOpcode = Cond.getOpcode();
15452 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15453 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15454 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15455 Cond.getOperand(0).getValueType() != MVT::i8)) {
15456 SDValue LHS = Cond.getOperand(0);
15457 SDValue RHS = Cond.getOperand(1);
15458 unsigned X86Opcode;
15461 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15462 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15464 switch (CondOpcode) {
15465 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15467 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15469 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15472 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15473 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15475 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15477 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15480 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15481 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15482 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15483 default: llvm_unreachable("unexpected overflowing operator");
15486 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15487 if (CondOpcode == ISD::UMULO)
15488 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15491 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15493 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15495 if (CondOpcode == ISD::UMULO)
15496 Cond = X86Op.getValue(2);
15498 Cond = X86Op.getValue(1);
15500 CC = DAG.getConstant(X86Cond, MVT::i8);
15504 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15505 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15506 if (CondOpc == ISD::OR) {
15507 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15508 // two branches instead of an explicit OR instruction with a
15510 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15511 isX86LogicalCmp(Cmp)) {
15512 CC = Cond.getOperand(0).getOperand(0);
15513 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15514 Chain, Dest, CC, Cmp);
15515 CC = Cond.getOperand(1).getOperand(0);
15519 } else { // ISD::AND
15520 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15521 // two branches instead of an explicit AND instruction with a
15522 // separate test. However, we only do this if this block doesn't
15523 // have a fall-through edge, because this requires an explicit
15524 // jmp when the condition is false.
15525 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15526 isX86LogicalCmp(Cmp) &&
15527 Op.getNode()->hasOneUse()) {
15528 X86::CondCode CCode =
15529 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15530 CCode = X86::GetOppositeBranchCondition(CCode);
15531 CC = DAG.getConstant(CCode, MVT::i8);
15532 SDNode *User = *Op.getNode()->use_begin();
15533 // Look for an unconditional branch following this conditional branch.
15534 // We need this because we need to reverse the successors in order
15535 // to implement FCMP_OEQ.
15536 if (User->getOpcode() == ISD::BR) {
15537 SDValue FalseBB = User->getOperand(1);
15539 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15540 assert(NewBR == User);
15544 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15545 Chain, Dest, CC, Cmp);
15546 X86::CondCode CCode =
15547 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15548 CCode = X86::GetOppositeBranchCondition(CCode);
15549 CC = DAG.getConstant(CCode, MVT::i8);
15555 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15556 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15557 // It should be transformed during dag combiner except when the condition
15558 // is set by a arithmetics with overflow node.
15559 X86::CondCode CCode =
15560 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15561 CCode = X86::GetOppositeBranchCondition(CCode);
15562 CC = DAG.getConstant(CCode, MVT::i8);
15563 Cond = Cond.getOperand(0).getOperand(1);
15565 } else if (Cond.getOpcode() == ISD::SETCC &&
15566 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15567 // For FCMP_OEQ, we can emit
15568 // two branches instead of an explicit AND instruction with a
15569 // separate test. However, we only do this if this block doesn't
15570 // have a fall-through edge, because this requires an explicit
15571 // jmp when the condition is false.
15572 if (Op.getNode()->hasOneUse()) {
15573 SDNode *User = *Op.getNode()->use_begin();
15574 // Look for an unconditional branch following this conditional branch.
15575 // We need this because we need to reverse the successors in order
15576 // to implement FCMP_OEQ.
15577 if (User->getOpcode() == ISD::BR) {
15578 SDValue FalseBB = User->getOperand(1);
15580 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15581 assert(NewBR == User);
15585 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15586 Cond.getOperand(0), Cond.getOperand(1));
15587 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15588 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15589 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15590 Chain, Dest, CC, Cmp);
15591 CC = DAG.getConstant(X86::COND_P, MVT::i8);
15596 } else if (Cond.getOpcode() == ISD::SETCC &&
15597 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15598 // For FCMP_UNE, we can emit
15599 // two branches instead of an explicit AND instruction with a
15600 // separate test. However, we only do this if this block doesn't
15601 // have a fall-through edge, because this requires an explicit
15602 // jmp when the condition is false.
15603 if (Op.getNode()->hasOneUse()) {
15604 SDNode *User = *Op.getNode()->use_begin();
15605 // Look for an unconditional branch following this conditional branch.
15606 // We need this because we need to reverse the successors in order
15607 // to implement FCMP_UNE.
15608 if (User->getOpcode() == ISD::BR) {
15609 SDValue FalseBB = User->getOperand(1);
15611 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15612 assert(NewBR == User);
15615 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15616 Cond.getOperand(0), Cond.getOperand(1));
15617 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15618 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15619 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15620 Chain, Dest, CC, Cmp);
15621 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
15631 // Look pass the truncate if the high bits are known zero.
15632 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15633 Cond = Cond.getOperand(0);
15635 // We know the result of AND is compared against zero. Try to match
15637 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15638 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
15639 if (NewSetCC.getNode()) {
15640 CC = NewSetCC.getOperand(0);
15641 Cond = NewSetCC.getOperand(1);
15648 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15649 CC = DAG.getConstant(X86Cond, MVT::i8);
15650 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15652 Cond = ConvertCmpIfNecessary(Cond, DAG);
15653 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15654 Chain, Dest, CC, Cond);
15657 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15658 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15659 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15660 // that the guard pages used by the OS virtual memory manager are allocated in
15661 // correct sequence.
15663 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15664 SelectionDAG &DAG) const {
15665 MachineFunction &MF = DAG.getMachineFunction();
15666 bool SplitStack = MF.shouldSplitStack();
15667 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
15672 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15673 SDNode* Node = Op.getNode();
15675 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15676 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15677 " not tell us which reg is the stack pointer!");
15678 EVT VT = Node->getValueType(0);
15679 SDValue Tmp1 = SDValue(Node, 0);
15680 SDValue Tmp2 = SDValue(Node, 1);
15681 SDValue Tmp3 = Node->getOperand(2);
15682 SDValue Chain = Tmp1.getOperand(0);
15684 // Chain the dynamic stack allocation so that it doesn't modify the stack
15685 // pointer when other instructions are using the stack.
15686 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
15689 SDValue Size = Tmp2.getOperand(1);
15690 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15691 Chain = SP.getValue(1);
15692 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15693 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
15694 unsigned StackAlign = TFI.getStackAlignment();
15695 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15696 if (Align > StackAlign)
15697 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15698 DAG.getConstant(-(uint64_t)Align, VT));
15699 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15701 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
15702 DAG.getIntPtrConstant(0, true), SDValue(),
15705 SDValue Ops[2] = { Tmp1, Tmp2 };
15706 return DAG.getMergeValues(Ops, dl);
15710 SDValue Chain = Op.getOperand(0);
15711 SDValue Size = Op.getOperand(1);
15712 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15713 EVT VT = Op.getNode()->getValueType(0);
15715 bool Is64Bit = Subtarget->is64Bit();
15716 EVT SPTy = getPointerTy();
15719 MachineRegisterInfo &MRI = MF.getRegInfo();
15722 // The 64 bit implementation of segmented stacks needs to clobber both r10
15723 // r11. This makes it impossible to use it along with nested parameters.
15724 const Function *F = MF.getFunction();
15726 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15728 if (I->hasNestAttr())
15729 report_fatal_error("Cannot use segmented stacks with functions that "
15730 "have nested arguments.");
15733 const TargetRegisterClass *AddrRegClass =
15734 getRegClassFor(getPointerTy());
15735 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15736 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15737 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15738 DAG.getRegister(Vreg, SPTy));
15739 SDValue Ops1[2] = { Value, Chain };
15740 return DAG.getMergeValues(Ops1, dl);
15743 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15745 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15746 Flag = Chain.getValue(1);
15747 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15749 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15751 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15752 DAG.getSubtarget().getRegisterInfo());
15753 unsigned SPReg = RegInfo->getStackRegister();
15754 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15755 Chain = SP.getValue(1);
15758 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15759 DAG.getConstant(-(uint64_t)Align, VT));
15760 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15763 SDValue Ops1[2] = { SP, Chain };
15764 return DAG.getMergeValues(Ops1, dl);
15768 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15769 MachineFunction &MF = DAG.getMachineFunction();
15770 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15772 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15775 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
15776 // vastart just stores the address of the VarArgsFrameIndex slot into the
15777 // memory location argument.
15778 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15780 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15781 MachinePointerInfo(SV), false, false, 0);
15785 // gp_offset (0 - 6 * 8)
15786 // fp_offset (48 - 48 + 8 * 16)
15787 // overflow_arg_area (point to parameters coming in memory).
15789 SmallVector<SDValue, 8> MemOps;
15790 SDValue FIN = Op.getOperand(1);
15792 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15793 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15795 FIN, MachinePointerInfo(SV), false, false, 0);
15796 MemOps.push_back(Store);
15799 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15800 FIN, DAG.getIntPtrConstant(4));
15801 Store = DAG.getStore(Op.getOperand(0), DL,
15802 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
15804 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15805 MemOps.push_back(Store);
15807 // Store ptr to overflow_arg_area
15808 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15809 FIN, DAG.getIntPtrConstant(4));
15810 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
15812 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15813 MachinePointerInfo(SV, 8),
15815 MemOps.push_back(Store);
15817 // Store ptr to reg_save_area.
15818 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
15819 FIN, DAG.getIntPtrConstant(8));
15820 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
15822 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
15823 MachinePointerInfo(SV, 16), false, false, 0);
15824 MemOps.push_back(Store);
15825 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15828 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15829 assert(Subtarget->is64Bit() &&
15830 "LowerVAARG only handles 64-bit va_arg!");
15831 assert((Subtarget->isTargetLinux() ||
15832 Subtarget->isTargetDarwin()) &&
15833 "Unhandled target in LowerVAARG");
15834 assert(Op.getNode()->getNumOperands() == 4);
15835 SDValue Chain = Op.getOperand(0);
15836 SDValue SrcPtr = Op.getOperand(1);
15837 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15838 unsigned Align = Op.getConstantOperandVal(3);
15841 EVT ArgVT = Op.getNode()->getValueType(0);
15842 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15843 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
15846 // Decide which area this value should be read from.
15847 // TODO: Implement the AMD64 ABI in its entirety. This simple
15848 // selection mechanism works only for the basic types.
15849 if (ArgVT == MVT::f80) {
15850 llvm_unreachable("va_arg for f80 not yet implemented");
15851 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15852 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15853 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15854 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15856 llvm_unreachable("Unhandled argument type in LowerVAARG");
15859 if (ArgMode == 2) {
15860 // Sanity Check: Make sure using fp_offset makes sense.
15861 assert(!DAG.getTarget().Options.UseSoftFloat &&
15862 !(DAG.getMachineFunction()
15863 .getFunction()->getAttributes()
15864 .hasAttribute(AttributeSet::FunctionIndex,
15865 Attribute::NoImplicitFloat)) &&
15866 Subtarget->hasSSE1());
15869 // Insert VAARG_64 node into the DAG
15870 // VAARG_64 returns two values: Variable Argument Address, Chain
15871 SmallVector<SDValue, 11> InstOps;
15872 InstOps.push_back(Chain);
15873 InstOps.push_back(SrcPtr);
15874 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
15875 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
15876 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
15877 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
15878 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15879 VTs, InstOps, MVT::i64,
15880 MachinePointerInfo(SV),
15882 /*Volatile=*/false,
15884 /*WriteMem=*/true);
15885 Chain = VAARG.getValue(1);
15887 // Load the next argument and return it
15888 return DAG.getLoad(ArgVT, dl,
15891 MachinePointerInfo(),
15892 false, false, false, 0);
15895 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15896 SelectionDAG &DAG) {
15897 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
15898 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15899 SDValue Chain = Op.getOperand(0);
15900 SDValue DstPtr = Op.getOperand(1);
15901 SDValue SrcPtr = Op.getOperand(2);
15902 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15903 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15906 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15907 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
15909 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15912 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15913 // amount is a constant. Takes immediate version of shift as input.
15914 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15915 SDValue SrcOp, uint64_t ShiftAmt,
15916 SelectionDAG &DAG) {
15917 MVT ElementType = VT.getVectorElementType();
15919 // Fold this packed shift into its first operand if ShiftAmt is 0.
15923 // Check for ShiftAmt >= element width
15924 if (ShiftAmt >= ElementType.getSizeInBits()) {
15925 if (Opc == X86ISD::VSRAI)
15926 ShiftAmt = ElementType.getSizeInBits() - 1;
15928 return DAG.getConstant(0, VT);
15931 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15932 && "Unknown target vector shift-by-constant node");
15934 // Fold this packed vector shift into a build vector if SrcOp is a
15935 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15936 if (VT == SrcOp.getSimpleValueType() &&
15937 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15938 SmallVector<SDValue, 8> Elts;
15939 unsigned NumElts = SrcOp->getNumOperands();
15940 ConstantSDNode *ND;
15943 default: llvm_unreachable(nullptr);
15944 case X86ISD::VSHLI:
15945 for (unsigned i=0; i!=NumElts; ++i) {
15946 SDValue CurrentOp = SrcOp->getOperand(i);
15947 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15948 Elts.push_back(CurrentOp);
15951 ND = cast<ConstantSDNode>(CurrentOp);
15952 const APInt &C = ND->getAPIntValue();
15953 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
15956 case X86ISD::VSRLI:
15957 for (unsigned i=0; i!=NumElts; ++i) {
15958 SDValue CurrentOp = SrcOp->getOperand(i);
15959 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15960 Elts.push_back(CurrentOp);
15963 ND = cast<ConstantSDNode>(CurrentOp);
15964 const APInt &C = ND->getAPIntValue();
15965 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
15968 case X86ISD::VSRAI:
15969 for (unsigned i=0; i!=NumElts; ++i) {
15970 SDValue CurrentOp = SrcOp->getOperand(i);
15971 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15972 Elts.push_back(CurrentOp);
15975 ND = cast<ConstantSDNode>(CurrentOp);
15976 const APInt &C = ND->getAPIntValue();
15977 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
15982 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15985 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
15988 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15989 // may or may not be a constant. Takes immediate version of shift as input.
15990 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15991 SDValue SrcOp, SDValue ShAmt,
15992 SelectionDAG &DAG) {
15993 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
15995 // Catch shift-by-constant.
15996 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15997 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15998 CShAmt->getZExtValue(), DAG);
16000 // Change opcode to non-immediate version
16002 default: llvm_unreachable("Unknown target vector shift node");
16003 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16004 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16005 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16008 // Need to build a vector containing shift amount
16009 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
16012 ShOps[1] = DAG.getConstant(0, MVT::i32);
16013 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
16014 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
16016 // The return type has to be a 128-bit type with the same element
16017 // type as the input type.
16018 MVT EltVT = VT.getVectorElementType();
16019 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16021 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
16022 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16025 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16026 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16027 /// necessary casting for \p Mask when lowering masking intrinsics.
16028 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16029 SDValue PreservedSrc, SelectionDAG &DAG) {
16030 EVT VT = Op.getValueType();
16031 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16032 MVT::i1, VT.getVectorNumElements());
16033 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16034 Mask.getValueType().getSizeInBits());
16037 assert(MaskVT.isSimple() && "invalid mask type");
16039 if (isAllOnes(Mask))
16042 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16043 // are extracted by EXTRACT_SUBVECTOR.
16044 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16045 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16046 DAG.getIntPtrConstant(0));
16048 switch (Op.getOpcode()) {
16050 case X86ISD::PCMPEQM:
16051 case X86ISD::PCMPGTM:
16053 case X86ISD::CMPMU:
16054 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16057 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
16060 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
16062 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16063 case Intrinsic::x86_fma_vfmadd_ps:
16064 case Intrinsic::x86_fma_vfmadd_pd:
16065 case Intrinsic::x86_fma_vfmadd_ps_256:
16066 case Intrinsic::x86_fma_vfmadd_pd_256:
16067 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16068 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16069 return X86ISD::FMADD;
16070 case Intrinsic::x86_fma_vfmsub_ps:
16071 case Intrinsic::x86_fma_vfmsub_pd:
16072 case Intrinsic::x86_fma_vfmsub_ps_256:
16073 case Intrinsic::x86_fma_vfmsub_pd_256:
16074 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16075 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16076 return X86ISD::FMSUB;
16077 case Intrinsic::x86_fma_vfnmadd_ps:
16078 case Intrinsic::x86_fma_vfnmadd_pd:
16079 case Intrinsic::x86_fma_vfnmadd_ps_256:
16080 case Intrinsic::x86_fma_vfnmadd_pd_256:
16081 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16082 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16083 return X86ISD::FNMADD;
16084 case Intrinsic::x86_fma_vfnmsub_ps:
16085 case Intrinsic::x86_fma_vfnmsub_pd:
16086 case Intrinsic::x86_fma_vfnmsub_ps_256:
16087 case Intrinsic::x86_fma_vfnmsub_pd_256:
16088 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16089 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16090 return X86ISD::FNMSUB;
16091 case Intrinsic::x86_fma_vfmaddsub_ps:
16092 case Intrinsic::x86_fma_vfmaddsub_pd:
16093 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16094 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16095 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16096 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16097 return X86ISD::FMADDSUB;
16098 case Intrinsic::x86_fma_vfmsubadd_ps:
16099 case Intrinsic::x86_fma_vfmsubadd_pd:
16100 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16101 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16102 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16103 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16104 return X86ISD::FMSUBADD;
16108 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
16110 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16112 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16114 switch(IntrData->Type) {
16115 case INTR_TYPE_1OP:
16116 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16117 case INTR_TYPE_2OP:
16118 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16120 case INTR_TYPE_3OP:
16121 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16122 Op.getOperand(2), Op.getOperand(3));
16124 // Comparison intrinsics with masks.
16125 // Example of transformation:
16126 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16127 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16129 // (v8i1 (insert_subvector undef,
16130 // (v2i1 (and (PCMPEQM %a, %b),
16131 // (extract_subvector
16132 // (v8i1 (bitcast %mask)), 0))), 0))))
16133 EVT VT = Op.getOperand(1).getValueType();
16134 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16135 VT.getVectorNumElements());
16136 SDValue Mask = Op.getOperand(3);
16137 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16138 Mask.getValueType().getSizeInBits());
16139 SDValue Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT,
16140 Op.getOperand(1), Op.getOperand(2));
16141 SDValue CmpMask = getVectorMaskingNode(Cmp, Op.getOperand(3),
16142 DAG.getTargetConstant(0, MaskVT), DAG);
16143 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16144 DAG.getUNDEF(BitcastVT), CmpMask,
16145 DAG.getIntPtrConstant(0));
16146 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
16148 case COMI: { // Comparison intrinsics
16149 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16150 SDValue LHS = Op.getOperand(1);
16151 SDValue RHS = Op.getOperand(2);
16152 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
16153 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16154 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16155 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16156 DAG.getConstant(X86CC, MVT::i8), Cond);
16157 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16160 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16161 Op.getOperand(1), Op.getOperand(2), DAG);
16168 default: return SDValue(); // Don't custom lower most intrinsics.
16170 // Arithmetic intrinsics.
16171 case Intrinsic::x86_sse2_pmulu_dq:
16172 case Intrinsic::x86_avx2_pmulu_dq:
16173 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
16174 Op.getOperand(1), Op.getOperand(2));
16176 case Intrinsic::x86_sse41_pmuldq:
16177 case Intrinsic::x86_avx2_pmul_dq:
16178 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
16179 Op.getOperand(1), Op.getOperand(2));
16181 case Intrinsic::x86_sse2_pmulhu_w:
16182 case Intrinsic::x86_avx2_pmulhu_w:
16183 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
16184 Op.getOperand(1), Op.getOperand(2));
16186 case Intrinsic::x86_sse2_pmulh_w:
16187 case Intrinsic::x86_avx2_pmulh_w:
16188 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
16189 Op.getOperand(1), Op.getOperand(2));
16191 // SSE/SSE2/AVX floating point max/min intrinsics.
16192 case Intrinsic::x86_sse_max_ps:
16193 case Intrinsic::x86_sse2_max_pd:
16194 case Intrinsic::x86_avx_max_ps_256:
16195 case Intrinsic::x86_avx_max_pd_256:
16196 case Intrinsic::x86_sse_min_ps:
16197 case Intrinsic::x86_sse2_min_pd:
16198 case Intrinsic::x86_avx_min_ps_256:
16199 case Intrinsic::x86_avx_min_pd_256: {
16202 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16203 case Intrinsic::x86_sse_max_ps:
16204 case Intrinsic::x86_sse2_max_pd:
16205 case Intrinsic::x86_avx_max_ps_256:
16206 case Intrinsic::x86_avx_max_pd_256:
16207 Opcode = X86ISD::FMAX;
16209 case Intrinsic::x86_sse_min_ps:
16210 case Intrinsic::x86_sse2_min_pd:
16211 case Intrinsic::x86_avx_min_ps_256:
16212 case Intrinsic::x86_avx_min_pd_256:
16213 Opcode = X86ISD::FMIN;
16216 return DAG.getNode(Opcode, dl, Op.getValueType(),
16217 Op.getOperand(1), Op.getOperand(2));
16220 // AVX2 variable shift intrinsics
16221 case Intrinsic::x86_avx2_psllv_d:
16222 case Intrinsic::x86_avx2_psllv_q:
16223 case Intrinsic::x86_avx2_psllv_d_256:
16224 case Intrinsic::x86_avx2_psllv_q_256:
16225 case Intrinsic::x86_avx2_psrlv_d:
16226 case Intrinsic::x86_avx2_psrlv_q:
16227 case Intrinsic::x86_avx2_psrlv_d_256:
16228 case Intrinsic::x86_avx2_psrlv_q_256:
16229 case Intrinsic::x86_avx2_psrav_d:
16230 case Intrinsic::x86_avx2_psrav_d_256: {
16233 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16234 case Intrinsic::x86_avx2_psllv_d:
16235 case Intrinsic::x86_avx2_psllv_q:
16236 case Intrinsic::x86_avx2_psllv_d_256:
16237 case Intrinsic::x86_avx2_psllv_q_256:
16240 case Intrinsic::x86_avx2_psrlv_d:
16241 case Intrinsic::x86_avx2_psrlv_q:
16242 case Intrinsic::x86_avx2_psrlv_d_256:
16243 case Intrinsic::x86_avx2_psrlv_q_256:
16246 case Intrinsic::x86_avx2_psrav_d:
16247 case Intrinsic::x86_avx2_psrav_d_256:
16251 return DAG.getNode(Opcode, dl, Op.getValueType(),
16252 Op.getOperand(1), Op.getOperand(2));
16255 case Intrinsic::x86_sse2_packssdw_128:
16256 case Intrinsic::x86_sse2_packsswb_128:
16257 case Intrinsic::x86_avx2_packssdw:
16258 case Intrinsic::x86_avx2_packsswb:
16259 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
16260 Op.getOperand(1), Op.getOperand(2));
16262 case Intrinsic::x86_sse2_packuswb_128:
16263 case Intrinsic::x86_sse41_packusdw:
16264 case Intrinsic::x86_avx2_packuswb:
16265 case Intrinsic::x86_avx2_packusdw:
16266 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
16267 Op.getOperand(1), Op.getOperand(2));
16269 case Intrinsic::x86_ssse3_pshuf_b_128:
16270 case Intrinsic::x86_avx2_pshuf_b:
16271 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
16272 Op.getOperand(1), Op.getOperand(2));
16274 case Intrinsic::x86_sse2_pshuf_d:
16275 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
16276 Op.getOperand(1), Op.getOperand(2));
16278 case Intrinsic::x86_sse2_pshufl_w:
16279 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
16280 Op.getOperand(1), Op.getOperand(2));
16282 case Intrinsic::x86_sse2_pshufh_w:
16283 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
16284 Op.getOperand(1), Op.getOperand(2));
16286 case Intrinsic::x86_ssse3_psign_b_128:
16287 case Intrinsic::x86_ssse3_psign_w_128:
16288 case Intrinsic::x86_ssse3_psign_d_128:
16289 case Intrinsic::x86_avx2_psign_b:
16290 case Intrinsic::x86_avx2_psign_w:
16291 case Intrinsic::x86_avx2_psign_d:
16292 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
16293 Op.getOperand(1), Op.getOperand(2));
16295 case Intrinsic::x86_avx2_permd:
16296 case Intrinsic::x86_avx2_permps:
16297 // Operands intentionally swapped. Mask is last operand to intrinsic,
16298 // but second operand for node/instruction.
16299 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16300 Op.getOperand(2), Op.getOperand(1));
16302 case Intrinsic::x86_avx512_mask_valign_q_512:
16303 case Intrinsic::x86_avx512_mask_valign_d_512:
16304 // Vector source operands are swapped.
16305 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
16306 Op.getValueType(), Op.getOperand(2),
16309 Op.getOperand(5), Op.getOperand(4), DAG);
16311 // ptest and testp intrinsics. The intrinsic these come from are designed to
16312 // return an integer value, not just an instruction so lower it to the ptest
16313 // or testp pattern and a setcc for the result.
16314 case Intrinsic::x86_sse41_ptestz:
16315 case Intrinsic::x86_sse41_ptestc:
16316 case Intrinsic::x86_sse41_ptestnzc:
16317 case Intrinsic::x86_avx_ptestz_256:
16318 case Intrinsic::x86_avx_ptestc_256:
16319 case Intrinsic::x86_avx_ptestnzc_256:
16320 case Intrinsic::x86_avx_vtestz_ps:
16321 case Intrinsic::x86_avx_vtestc_ps:
16322 case Intrinsic::x86_avx_vtestnzc_ps:
16323 case Intrinsic::x86_avx_vtestz_pd:
16324 case Intrinsic::x86_avx_vtestc_pd:
16325 case Intrinsic::x86_avx_vtestnzc_pd:
16326 case Intrinsic::x86_avx_vtestz_ps_256:
16327 case Intrinsic::x86_avx_vtestc_ps_256:
16328 case Intrinsic::x86_avx_vtestnzc_ps_256:
16329 case Intrinsic::x86_avx_vtestz_pd_256:
16330 case Intrinsic::x86_avx_vtestc_pd_256:
16331 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16332 bool IsTestPacked = false;
16335 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16336 case Intrinsic::x86_avx_vtestz_ps:
16337 case Intrinsic::x86_avx_vtestz_pd:
16338 case Intrinsic::x86_avx_vtestz_ps_256:
16339 case Intrinsic::x86_avx_vtestz_pd_256:
16340 IsTestPacked = true; // Fallthrough
16341 case Intrinsic::x86_sse41_ptestz:
16342 case Intrinsic::x86_avx_ptestz_256:
16344 X86CC = X86::COND_E;
16346 case Intrinsic::x86_avx_vtestc_ps:
16347 case Intrinsic::x86_avx_vtestc_pd:
16348 case Intrinsic::x86_avx_vtestc_ps_256:
16349 case Intrinsic::x86_avx_vtestc_pd_256:
16350 IsTestPacked = true; // Fallthrough
16351 case Intrinsic::x86_sse41_ptestc:
16352 case Intrinsic::x86_avx_ptestc_256:
16354 X86CC = X86::COND_B;
16356 case Intrinsic::x86_avx_vtestnzc_ps:
16357 case Intrinsic::x86_avx_vtestnzc_pd:
16358 case Intrinsic::x86_avx_vtestnzc_ps_256:
16359 case Intrinsic::x86_avx_vtestnzc_pd_256:
16360 IsTestPacked = true; // Fallthrough
16361 case Intrinsic::x86_sse41_ptestnzc:
16362 case Intrinsic::x86_avx_ptestnzc_256:
16364 X86CC = X86::COND_A;
16368 SDValue LHS = Op.getOperand(1);
16369 SDValue RHS = Op.getOperand(2);
16370 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16371 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16372 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16373 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16374 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16376 case Intrinsic::x86_avx512_kortestz_w:
16377 case Intrinsic::x86_avx512_kortestc_w: {
16378 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16379 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
16380 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
16381 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
16382 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16383 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16384 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16387 case Intrinsic::x86_sse42_pcmpistria128:
16388 case Intrinsic::x86_sse42_pcmpestria128:
16389 case Intrinsic::x86_sse42_pcmpistric128:
16390 case Intrinsic::x86_sse42_pcmpestric128:
16391 case Intrinsic::x86_sse42_pcmpistrio128:
16392 case Intrinsic::x86_sse42_pcmpestrio128:
16393 case Intrinsic::x86_sse42_pcmpistris128:
16394 case Intrinsic::x86_sse42_pcmpestris128:
16395 case Intrinsic::x86_sse42_pcmpistriz128:
16396 case Intrinsic::x86_sse42_pcmpestriz128: {
16400 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16401 case Intrinsic::x86_sse42_pcmpistria128:
16402 Opcode = X86ISD::PCMPISTRI;
16403 X86CC = X86::COND_A;
16405 case Intrinsic::x86_sse42_pcmpestria128:
16406 Opcode = X86ISD::PCMPESTRI;
16407 X86CC = X86::COND_A;
16409 case Intrinsic::x86_sse42_pcmpistric128:
16410 Opcode = X86ISD::PCMPISTRI;
16411 X86CC = X86::COND_B;
16413 case Intrinsic::x86_sse42_pcmpestric128:
16414 Opcode = X86ISD::PCMPESTRI;
16415 X86CC = X86::COND_B;
16417 case Intrinsic::x86_sse42_pcmpistrio128:
16418 Opcode = X86ISD::PCMPISTRI;
16419 X86CC = X86::COND_O;
16421 case Intrinsic::x86_sse42_pcmpestrio128:
16422 Opcode = X86ISD::PCMPESTRI;
16423 X86CC = X86::COND_O;
16425 case Intrinsic::x86_sse42_pcmpistris128:
16426 Opcode = X86ISD::PCMPISTRI;
16427 X86CC = X86::COND_S;
16429 case Intrinsic::x86_sse42_pcmpestris128:
16430 Opcode = X86ISD::PCMPESTRI;
16431 X86CC = X86::COND_S;
16433 case Intrinsic::x86_sse42_pcmpistriz128:
16434 Opcode = X86ISD::PCMPISTRI;
16435 X86CC = X86::COND_E;
16437 case Intrinsic::x86_sse42_pcmpestriz128:
16438 Opcode = X86ISD::PCMPESTRI;
16439 X86CC = X86::COND_E;
16442 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16443 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16444 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16445 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16446 DAG.getConstant(X86CC, MVT::i8),
16447 SDValue(PCMP.getNode(), 1));
16448 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16451 case Intrinsic::x86_sse42_pcmpistri128:
16452 case Intrinsic::x86_sse42_pcmpestri128: {
16454 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16455 Opcode = X86ISD::PCMPISTRI;
16457 Opcode = X86ISD::PCMPESTRI;
16459 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16460 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16461 return DAG.getNode(Opcode, dl, VTs, NewOps);
16464 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16465 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16466 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16467 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16468 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16469 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16470 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16471 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16472 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16473 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16474 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16475 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
16476 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
16477 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
16478 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
16479 dl, Op.getValueType(),
16483 Op.getOperand(4), Op.getOperand(1), DAG);
16488 case Intrinsic::x86_fma_vfmadd_ps:
16489 case Intrinsic::x86_fma_vfmadd_pd:
16490 case Intrinsic::x86_fma_vfmsub_ps:
16491 case Intrinsic::x86_fma_vfmsub_pd:
16492 case Intrinsic::x86_fma_vfnmadd_ps:
16493 case Intrinsic::x86_fma_vfnmadd_pd:
16494 case Intrinsic::x86_fma_vfnmsub_ps:
16495 case Intrinsic::x86_fma_vfnmsub_pd:
16496 case Intrinsic::x86_fma_vfmaddsub_ps:
16497 case Intrinsic::x86_fma_vfmaddsub_pd:
16498 case Intrinsic::x86_fma_vfmsubadd_ps:
16499 case Intrinsic::x86_fma_vfmsubadd_pd:
16500 case Intrinsic::x86_fma_vfmadd_ps_256:
16501 case Intrinsic::x86_fma_vfmadd_pd_256:
16502 case Intrinsic::x86_fma_vfmsub_ps_256:
16503 case Intrinsic::x86_fma_vfmsub_pd_256:
16504 case Intrinsic::x86_fma_vfnmadd_ps_256:
16505 case Intrinsic::x86_fma_vfnmadd_pd_256:
16506 case Intrinsic::x86_fma_vfnmsub_ps_256:
16507 case Intrinsic::x86_fma_vfnmsub_pd_256:
16508 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16509 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16510 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16511 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16512 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
16513 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
16517 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16518 SDValue Src, SDValue Mask, SDValue Base,
16519 SDValue Index, SDValue ScaleOp, SDValue Chain,
16520 const X86Subtarget * Subtarget) {
16522 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16523 assert(C && "Invalid scale type");
16524 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16525 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16526 Index.getSimpleValueType().getVectorNumElements());
16528 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16530 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16532 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16533 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16534 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16535 SDValue Segment = DAG.getRegister(0, MVT::i32);
16536 if (Src.getOpcode() == ISD::UNDEF)
16537 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16538 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16539 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16540 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16541 return DAG.getMergeValues(RetOps, dl);
16544 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16545 SDValue Src, SDValue Mask, SDValue Base,
16546 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16548 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16549 assert(C && "Invalid scale type");
16550 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16551 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16552 SDValue Segment = DAG.getRegister(0, MVT::i32);
16553 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16554 Index.getSimpleValueType().getVectorNumElements());
16556 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16558 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16560 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16561 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16562 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16563 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16564 return SDValue(Res, 1);
16567 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16568 SDValue Mask, SDValue Base, SDValue Index,
16569 SDValue ScaleOp, SDValue Chain) {
16571 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16572 assert(C && "Invalid scale type");
16573 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
16574 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
16575 SDValue Segment = DAG.getRegister(0, MVT::i32);
16577 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16579 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16581 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
16583 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
16584 //SDVTList VTs = DAG.getVTList(MVT::Other);
16585 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16586 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16587 return SDValue(Res, 0);
16590 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16591 // read performance monitor counters (x86_rdpmc).
16592 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16593 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16594 SmallVectorImpl<SDValue> &Results) {
16595 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16596 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16599 // The ECX register is used to select the index of the performance counter
16601 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16603 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16605 // Reads the content of a 64-bit performance counter and returns it in the
16606 // registers EDX:EAX.
16607 if (Subtarget->is64Bit()) {
16608 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16609 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16612 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16613 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16616 Chain = HI.getValue(1);
16618 if (Subtarget->is64Bit()) {
16619 // The EAX register is loaded with the low-order 32 bits. The EDX register
16620 // is loaded with the supported high-order bits of the counter.
16621 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16622 DAG.getConstant(32, MVT::i8));
16623 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16624 Results.push_back(Chain);
16628 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16629 SDValue Ops[] = { LO, HI };
16630 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16631 Results.push_back(Pair);
16632 Results.push_back(Chain);
16635 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16636 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16637 // also used to custom lower READCYCLECOUNTER nodes.
16638 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16639 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16640 SmallVectorImpl<SDValue> &Results) {
16641 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16642 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16645 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16646 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16647 // and the EAX register is loaded with the low-order 32 bits.
16648 if (Subtarget->is64Bit()) {
16649 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16650 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16653 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16654 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16657 SDValue Chain = HI.getValue(1);
16659 if (Opcode == X86ISD::RDTSCP_DAG) {
16660 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16662 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16663 // the ECX register. Add 'ecx' explicitly to the chain.
16664 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16666 // Explicitly store the content of ECX at the location passed in input
16667 // to the 'rdtscp' intrinsic.
16668 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16669 MachinePointerInfo(), false, false, 0);
16672 if (Subtarget->is64Bit()) {
16673 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16674 // the EAX register is loaded with the low-order 32 bits.
16675 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16676 DAG.getConstant(32, MVT::i8));
16677 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16678 Results.push_back(Chain);
16682 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16683 SDValue Ops[] = { LO, HI };
16684 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16685 Results.push_back(Pair);
16686 Results.push_back(Chain);
16689 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16690 SelectionDAG &DAG) {
16691 SmallVector<SDValue, 2> Results;
16693 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16695 return DAG.getMergeValues(Results, DL);
16699 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16700 SelectionDAG &DAG) {
16701 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
16703 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
16708 switch(IntrData->Type) {
16710 llvm_unreachable("Unknown Intrinsic Type");
16714 // Emit the node with the right value type.
16715 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16716 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16718 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16719 // Otherwise return the value from Rand, which is always 0, casted to i32.
16720 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16721 DAG.getConstant(1, Op->getValueType(1)),
16722 DAG.getConstant(X86::COND_B, MVT::i32),
16723 SDValue(Result.getNode(), 1) };
16724 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
16725 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16728 // Return { result, isValid, chain }.
16729 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16730 SDValue(Result.getNode(), 2));
16733 //gather(v1, mask, index, base, scale);
16734 SDValue Chain = Op.getOperand(0);
16735 SDValue Src = Op.getOperand(2);
16736 SDValue Base = Op.getOperand(3);
16737 SDValue Index = Op.getOperand(4);
16738 SDValue Mask = Op.getOperand(5);
16739 SDValue Scale = Op.getOperand(6);
16740 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
16744 //scatter(base, mask, index, v1, scale);
16745 SDValue Chain = Op.getOperand(0);
16746 SDValue Base = Op.getOperand(2);
16747 SDValue Mask = Op.getOperand(3);
16748 SDValue Index = Op.getOperand(4);
16749 SDValue Src = Op.getOperand(5);
16750 SDValue Scale = Op.getOperand(6);
16751 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
16754 SDValue Hint = Op.getOperand(6);
16756 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
16757 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
16758 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
16759 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
16760 SDValue Chain = Op.getOperand(0);
16761 SDValue Mask = Op.getOperand(2);
16762 SDValue Index = Op.getOperand(3);
16763 SDValue Base = Op.getOperand(4);
16764 SDValue Scale = Op.getOperand(5);
16765 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
16767 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
16769 SmallVector<SDValue, 2> Results;
16770 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
16771 return DAG.getMergeValues(Results, dl);
16773 // Read Performance Monitoring Counters.
16775 SmallVector<SDValue, 2> Results;
16776 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
16777 return DAG.getMergeValues(Results, dl);
16779 // XTEST intrinsics.
16781 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16782 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16783 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16784 DAG.getConstant(X86::COND_NE, MVT::i8),
16786 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
16787 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
16788 Ret, SDValue(InTrans.getNode(), 1));
16792 SmallVector<SDValue, 2> Results;
16793 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16794 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
16795 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
16796 DAG.getConstant(-1, MVT::i8));
16797 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
16798 Op.getOperand(4), GenCF.getValue(1));
16799 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
16800 Op.getOperand(5), MachinePointerInfo(),
16802 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16803 DAG.getConstant(X86::COND_B, MVT::i8),
16805 Results.push_back(SetCC);
16806 Results.push_back(Store);
16807 return DAG.getMergeValues(Results, dl);
16812 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
16813 SelectionDAG &DAG) const {
16814 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16815 MFI->setReturnAddressIsTaken(true);
16817 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
16820 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16822 EVT PtrVT = getPointerTy();
16825 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
16826 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16827 DAG.getSubtarget().getRegisterInfo());
16828 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
16829 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16830 DAG.getNode(ISD::ADD, dl, PtrVT,
16831 FrameAddr, Offset),
16832 MachinePointerInfo(), false, false, false, 0);
16835 // Just load the return address.
16836 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
16837 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16838 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
16841 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
16842 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16843 MFI->setFrameAddressIsTaken(true);
16845 EVT VT = Op.getValueType();
16846 SDLoc dl(Op); // FIXME probably not meaningful
16847 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16848 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16849 DAG.getSubtarget().getRegisterInfo());
16850 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16851 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
16852 (FrameReg == X86::EBP && VT == MVT::i32)) &&
16853 "Invalid Frame Register!");
16854 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
16856 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
16857 MachinePointerInfo(),
16858 false, false, false, 0);
16862 // FIXME? Maybe this could be a TableGen attribute on some registers and
16863 // this table could be generated automatically from RegInfo.
16864 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
16866 unsigned Reg = StringSwitch<unsigned>(RegName)
16867 .Case("esp", X86::ESP)
16868 .Case("rsp", X86::RSP)
16872 report_fatal_error("Invalid register name global variable");
16875 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
16876 SelectionDAG &DAG) const {
16877 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16878 DAG.getSubtarget().getRegisterInfo());
16879 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
16882 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
16883 SDValue Chain = Op.getOperand(0);
16884 SDValue Offset = Op.getOperand(1);
16885 SDValue Handler = Op.getOperand(2);
16888 EVT PtrVT = getPointerTy();
16889 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16890 DAG.getSubtarget().getRegisterInfo());
16891 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16892 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
16893 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
16894 "Invalid Frame Register!");
16895 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
16896 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
16898 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
16899 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
16900 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
16901 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
16903 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
16905 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
16906 DAG.getRegister(StoreAddrReg, PtrVT));
16909 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
16910 SelectionDAG &DAG) const {
16912 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
16913 DAG.getVTList(MVT::i32, MVT::Other),
16914 Op.getOperand(0), Op.getOperand(1));
16917 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
16918 SelectionDAG &DAG) const {
16920 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
16921 Op.getOperand(0), Op.getOperand(1));
16924 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
16925 return Op.getOperand(0);
16928 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
16929 SelectionDAG &DAG) const {
16930 SDValue Root = Op.getOperand(0);
16931 SDValue Trmp = Op.getOperand(1); // trampoline
16932 SDValue FPtr = Op.getOperand(2); // nested function
16933 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
16936 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16937 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
16939 if (Subtarget->is64Bit()) {
16940 SDValue OutChains[6];
16942 // Large code-model.
16943 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
16944 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
16946 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
16947 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
16949 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
16951 // Load the pointer to the nested function into R11.
16952 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
16953 SDValue Addr = Trmp;
16954 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16955 Addr, MachinePointerInfo(TrmpAddr),
16958 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16959 DAG.getConstant(2, MVT::i64));
16960 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
16961 MachinePointerInfo(TrmpAddr, 2),
16964 // Load the 'nest' parameter value into R10.
16965 // R10 is specified in X86CallingConv.td
16966 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
16967 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16968 DAG.getConstant(10, MVT::i64));
16969 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16970 Addr, MachinePointerInfo(TrmpAddr, 10),
16973 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16974 DAG.getConstant(12, MVT::i64));
16975 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
16976 MachinePointerInfo(TrmpAddr, 12),
16979 // Jump to the nested function.
16980 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
16981 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16982 DAG.getConstant(20, MVT::i64));
16983 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
16984 Addr, MachinePointerInfo(TrmpAddr, 20),
16987 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
16988 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16989 DAG.getConstant(22, MVT::i64));
16990 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
16991 MachinePointerInfo(TrmpAddr, 22),
16994 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16996 const Function *Func =
16997 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
16998 CallingConv::ID CC = Func->getCallingConv();
17003 llvm_unreachable("Unsupported calling convention");
17004 case CallingConv::C:
17005 case CallingConv::X86_StdCall: {
17006 // Pass 'nest' parameter in ECX.
17007 // Must be kept in sync with X86CallingConv.td
17008 NestReg = X86::ECX;
17010 // Check that ECX wasn't needed by an 'inreg' parameter.
17011 FunctionType *FTy = Func->getFunctionType();
17012 const AttributeSet &Attrs = Func->getAttributes();
17014 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17015 unsigned InRegCount = 0;
17018 for (FunctionType::param_iterator I = FTy->param_begin(),
17019 E = FTy->param_end(); I != E; ++I, ++Idx)
17020 if (Attrs.hasAttribute(Idx, Attribute::InReg))
17021 // FIXME: should only count parameters that are lowered to integers.
17022 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
17024 if (InRegCount > 2) {
17025 report_fatal_error("Nest register in use - reduce number of inreg"
17031 case CallingConv::X86_FastCall:
17032 case CallingConv::X86_ThisCall:
17033 case CallingConv::Fast:
17034 // Pass 'nest' parameter in EAX.
17035 // Must be kept in sync with X86CallingConv.td
17036 NestReg = X86::EAX;
17040 SDValue OutChains[4];
17041 SDValue Addr, Disp;
17043 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17044 DAG.getConstant(10, MVT::i32));
17045 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17047 // This is storing the opcode for MOV32ri.
17048 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17049 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17050 OutChains[0] = DAG.getStore(Root, dl,
17051 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
17052 Trmp, MachinePointerInfo(TrmpAddr),
17055 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17056 DAG.getConstant(1, MVT::i32));
17057 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17058 MachinePointerInfo(TrmpAddr, 1),
17061 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17062 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17063 DAG.getConstant(5, MVT::i32));
17064 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17065 MachinePointerInfo(TrmpAddr, 5),
17068 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17069 DAG.getConstant(6, MVT::i32));
17070 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17071 MachinePointerInfo(TrmpAddr, 6),
17074 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17078 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17079 SelectionDAG &DAG) const {
17081 The rounding mode is in bits 11:10 of FPSR, and has the following
17083 00 Round to nearest
17088 FLT_ROUNDS, on the other hand, expects the following:
17095 To perform the conversion, we do:
17096 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17099 MachineFunction &MF = DAG.getMachineFunction();
17100 const TargetMachine &TM = MF.getTarget();
17101 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17102 unsigned StackAlignment = TFI.getStackAlignment();
17103 MVT VT = Op.getSimpleValueType();
17106 // Save FP Control Word to stack slot
17107 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17108 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
17110 MachineMemOperand *MMO =
17111 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
17112 MachineMemOperand::MOStore, 2, 2);
17114 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17115 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17116 DAG.getVTList(MVT::Other),
17117 Ops, MVT::i16, MMO);
17119 // Load FP Control Word from stack slot
17120 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17121 MachinePointerInfo(), false, false, false, 0);
17123 // Transform as necessary
17125 DAG.getNode(ISD::SRL, DL, MVT::i16,
17126 DAG.getNode(ISD::AND, DL, MVT::i16,
17127 CWD, DAG.getConstant(0x800, MVT::i16)),
17128 DAG.getConstant(11, MVT::i8));
17130 DAG.getNode(ISD::SRL, DL, MVT::i16,
17131 DAG.getNode(ISD::AND, DL, MVT::i16,
17132 CWD, DAG.getConstant(0x400, MVT::i16)),
17133 DAG.getConstant(9, MVT::i8));
17136 DAG.getNode(ISD::AND, DL, MVT::i16,
17137 DAG.getNode(ISD::ADD, DL, MVT::i16,
17138 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17139 DAG.getConstant(1, MVT::i16)),
17140 DAG.getConstant(3, MVT::i16));
17142 return DAG.getNode((VT.getSizeInBits() < 16 ?
17143 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17146 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17147 MVT VT = Op.getSimpleValueType();
17149 unsigned NumBits = VT.getSizeInBits();
17152 Op = Op.getOperand(0);
17153 if (VT == MVT::i8) {
17154 // Zero extend to i32 since there is not an i8 bsr.
17156 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17159 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17160 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17161 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17163 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17166 DAG.getConstant(NumBits+NumBits-1, OpVT),
17167 DAG.getConstant(X86::COND_E, MVT::i8),
17170 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17172 // Finally xor with NumBits-1.
17173 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17176 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17180 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17181 MVT VT = Op.getSimpleValueType();
17183 unsigned NumBits = VT.getSizeInBits();
17186 Op = Op.getOperand(0);
17187 if (VT == MVT::i8) {
17188 // Zero extend to i32 since there is not an i8 bsr.
17190 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17193 // Issue a bsr (scan bits in reverse).
17194 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17195 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17197 // And xor with NumBits-1.
17198 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17201 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17205 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17206 MVT VT = Op.getSimpleValueType();
17207 unsigned NumBits = VT.getSizeInBits();
17209 Op = Op.getOperand(0);
17211 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17212 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17213 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
17215 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17218 DAG.getConstant(NumBits, VT),
17219 DAG.getConstant(X86::COND_E, MVT::i8),
17222 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17225 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17226 // ones, and then concatenate the result back.
17227 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17228 MVT VT = Op.getSimpleValueType();
17230 assert(VT.is256BitVector() && VT.isInteger() &&
17231 "Unsupported value type for operation");
17233 unsigned NumElems = VT.getVectorNumElements();
17236 // Extract the LHS vectors
17237 SDValue LHS = Op.getOperand(0);
17238 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17239 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17241 // Extract the RHS vectors
17242 SDValue RHS = Op.getOperand(1);
17243 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17244 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17246 MVT EltVT = VT.getVectorElementType();
17247 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17249 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17250 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17251 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17254 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17255 assert(Op.getSimpleValueType().is256BitVector() &&
17256 Op.getSimpleValueType().isInteger() &&
17257 "Only handle AVX 256-bit vector integer operation");
17258 return Lower256IntArith(Op, DAG);
17261 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17262 assert(Op.getSimpleValueType().is256BitVector() &&
17263 Op.getSimpleValueType().isInteger() &&
17264 "Only handle AVX 256-bit vector integer operation");
17265 return Lower256IntArith(Op, DAG);
17268 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17269 SelectionDAG &DAG) {
17271 MVT VT = Op.getSimpleValueType();
17273 // Decompose 256-bit ops into smaller 128-bit ops.
17274 if (VT.is256BitVector() && !Subtarget->hasInt256())
17275 return Lower256IntArith(Op, DAG);
17277 SDValue A = Op.getOperand(0);
17278 SDValue B = Op.getOperand(1);
17280 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17281 if (VT == MVT::v4i32) {
17282 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17283 "Should not custom lower when pmuldq is available!");
17285 // Extract the odd parts.
17286 static const int UnpackMask[] = { 1, -1, 3, -1 };
17287 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17288 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17290 // Multiply the even parts.
17291 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17292 // Now multiply odd parts.
17293 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17295 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
17296 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
17298 // Merge the two vectors back together with a shuffle. This expands into 2
17300 static const int ShufMask[] = { 0, 4, 2, 6 };
17301 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17304 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17305 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17307 // Ahi = psrlqi(a, 32);
17308 // Bhi = psrlqi(b, 32);
17310 // AloBlo = pmuludq(a, b);
17311 // AloBhi = pmuludq(a, Bhi);
17312 // AhiBlo = pmuludq(Ahi, b);
17314 // AloBhi = psllqi(AloBhi, 32);
17315 // AhiBlo = psllqi(AhiBlo, 32);
17316 // return AloBlo + AloBhi + AhiBlo;
17318 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17319 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17321 // Bit cast to 32-bit vectors for MULUDQ
17322 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17323 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17324 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
17325 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
17326 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
17327 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
17329 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17330 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17331 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17333 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17334 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17336 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17337 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17340 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17341 assert(Subtarget->isTargetWin64() && "Unexpected target");
17342 EVT VT = Op.getValueType();
17343 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17344 "Unexpected return type for lowering");
17348 switch (Op->getOpcode()) {
17349 default: llvm_unreachable("Unexpected request for libcall!");
17350 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17351 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17352 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17353 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17354 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17355 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17359 SDValue InChain = DAG.getEntryNode();
17361 TargetLowering::ArgListTy Args;
17362 TargetLowering::ArgListEntry Entry;
17363 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17364 EVT ArgVT = Op->getOperand(i).getValueType();
17365 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17366 "Unexpected argument type for lowering");
17367 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17368 Entry.Node = StackPtr;
17369 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17371 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17372 Entry.Ty = PointerType::get(ArgTy,0);
17373 Entry.isSExt = false;
17374 Entry.isZExt = false;
17375 Args.push_back(Entry);
17378 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17381 TargetLowering::CallLoweringInfo CLI(DAG);
17382 CLI.setDebugLoc(dl).setChain(InChain)
17383 .setCallee(getLibcallCallingConv(LC),
17384 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17385 Callee, std::move(Args), 0)
17386 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17388 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17389 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
17392 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17393 SelectionDAG &DAG) {
17394 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17395 EVT VT = Op0.getValueType();
17398 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17399 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17401 // PMULxD operations multiply each even value (starting at 0) of LHS with
17402 // the related value of RHS and produce a widen result.
17403 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17404 // => <2 x i64> <ae|cg>
17406 // In other word, to have all the results, we need to perform two PMULxD:
17407 // 1. one with the even values.
17408 // 2. one with the odd values.
17409 // To achieve #2, with need to place the odd values at an even position.
17411 // Place the odd value at an even position (basically, shift all values 1
17412 // step to the left):
17413 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
17414 // <a|b|c|d> => <b|undef|d|undef>
17415 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
17416 // <e|f|g|h> => <f|undef|h|undef>
17417 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
17419 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
17421 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
17422 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
17424 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
17425 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17426 // => <2 x i64> <ae|cg>
17427 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
17428 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
17429 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
17430 // => <2 x i64> <bf|dh>
17431 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
17432 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
17434 // Shuffle it back into the right order.
17435 SDValue Highs, Lows;
17436 if (VT == MVT::v8i32) {
17437 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
17438 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17439 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
17440 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17442 const int HighMask[] = {1, 5, 3, 7};
17443 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
17444 const int LowMask[] = {0, 4, 2, 6};
17445 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
17448 // If we have a signed multiply but no PMULDQ fix up the high parts of a
17449 // unsigned multiply.
17450 if (IsSigned && !Subtarget->hasSSE41()) {
17452 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
17453 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
17454 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
17455 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
17456 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
17458 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
17459 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
17462 // The first result of MUL_LOHI is actually the low value, followed by the
17464 SDValue Ops[] = {Lows, Highs};
17465 return DAG.getMergeValues(Ops, dl);
17468 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
17469 const X86Subtarget *Subtarget) {
17470 MVT VT = Op.getSimpleValueType();
17472 SDValue R = Op.getOperand(0);
17473 SDValue Amt = Op.getOperand(1);
17475 // Optimize shl/srl/sra with constant shift amount.
17476 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
17477 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
17478 uint64_t ShiftAmt = ShiftConst->getZExtValue();
17480 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
17481 (Subtarget->hasInt256() &&
17482 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
17483 (Subtarget->hasAVX512() &&
17484 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
17485 if (Op.getOpcode() == ISD::SHL)
17486 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
17488 if (Op.getOpcode() == ISD::SRL)
17489 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
17491 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
17492 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
17496 if (VT == MVT::v16i8) {
17497 if (Op.getOpcode() == ISD::SHL) {
17498 // Make a large shift.
17499 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17500 MVT::v8i16, R, ShiftAmt,
17502 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17503 // Zero out the rightmost bits.
17504 SmallVector<SDValue, 16> V(16,
17505 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17507 return DAG.getNode(ISD::AND, dl, VT, SHL,
17508 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17510 if (Op.getOpcode() == ISD::SRL) {
17511 // Make a large shift.
17512 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17513 MVT::v8i16, R, ShiftAmt,
17515 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17516 // Zero out the leftmost bits.
17517 SmallVector<SDValue, 16> V(16,
17518 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17520 return DAG.getNode(ISD::AND, dl, VT, SRL,
17521 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17523 if (Op.getOpcode() == ISD::SRA) {
17524 if (ShiftAmt == 7) {
17525 // R s>> 7 === R s< 0
17526 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17527 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17530 // R s>> a === ((R u>> a) ^ m) - m
17531 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17532 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
17534 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17535 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17536 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17539 llvm_unreachable("Unknown shift opcode.");
17542 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
17543 if (Op.getOpcode() == ISD::SHL) {
17544 // Make a large shift.
17545 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
17546 MVT::v16i16, R, ShiftAmt,
17548 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
17549 // Zero out the rightmost bits.
17550 SmallVector<SDValue, 32> V(32,
17551 DAG.getConstant(uint8_t(-1U << ShiftAmt),
17553 return DAG.getNode(ISD::AND, dl, VT, SHL,
17554 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17556 if (Op.getOpcode() == ISD::SRL) {
17557 // Make a large shift.
17558 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
17559 MVT::v16i16, R, ShiftAmt,
17561 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
17562 // Zero out the leftmost bits.
17563 SmallVector<SDValue, 32> V(32,
17564 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
17566 return DAG.getNode(ISD::AND, dl, VT, SRL,
17567 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17569 if (Op.getOpcode() == ISD::SRA) {
17570 if (ShiftAmt == 7) {
17571 // R s>> 7 === R s< 0
17572 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17573 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17576 // R s>> a === ((R u>> a) ^ m) - m
17577 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17578 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
17580 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17581 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17582 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17585 llvm_unreachable("Unknown shift opcode.");
17590 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17591 if (!Subtarget->is64Bit() &&
17592 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
17593 Amt.getOpcode() == ISD::BITCAST &&
17594 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17595 Amt = Amt.getOperand(0);
17596 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17597 VT.getVectorNumElements();
17598 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
17599 uint64_t ShiftAmt = 0;
17600 for (unsigned i = 0; i != Ratio; ++i) {
17601 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
17605 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
17607 // Check remaining shift amounts.
17608 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17609 uint64_t ShAmt = 0;
17610 for (unsigned j = 0; j != Ratio; ++j) {
17611 ConstantSDNode *C =
17612 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
17616 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
17618 if (ShAmt != ShiftAmt)
17621 switch (Op.getOpcode()) {
17623 llvm_unreachable("Unknown shift opcode!");
17625 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
17628 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
17631 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
17639 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
17640 const X86Subtarget* Subtarget) {
17641 MVT VT = Op.getSimpleValueType();
17643 SDValue R = Op.getOperand(0);
17644 SDValue Amt = Op.getOperand(1);
17646 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
17647 VT == MVT::v4i32 || VT == MVT::v8i16 ||
17648 (Subtarget->hasInt256() &&
17649 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
17650 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
17651 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
17653 EVT EltVT = VT.getVectorElementType();
17655 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17656 unsigned NumElts = VT.getVectorNumElements();
17658 for (i = 0; i != NumElts; ++i) {
17659 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
17663 for (j = i; j != NumElts; ++j) {
17664 SDValue Arg = Amt.getOperand(j);
17665 if (Arg.getOpcode() == ISD::UNDEF) continue;
17666 if (Arg != Amt.getOperand(i))
17669 if (i != NumElts && j == NumElts)
17670 BaseShAmt = Amt.getOperand(i);
17672 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
17673 Amt = Amt.getOperand(0);
17674 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
17675 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
17676 SDValue InVec = Amt.getOperand(0);
17677 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
17678 unsigned NumElts = InVec.getValueType().getVectorNumElements();
17680 for (; i != NumElts; ++i) {
17681 SDValue Arg = InVec.getOperand(i);
17682 if (Arg.getOpcode() == ISD::UNDEF) continue;
17686 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
17687 if (ConstantSDNode *C =
17688 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
17689 unsigned SplatIdx =
17690 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
17691 if (C->getZExtValue() == SplatIdx)
17692 BaseShAmt = InVec.getOperand(1);
17695 if (!BaseShAmt.getNode())
17696 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
17697 DAG.getIntPtrConstant(0));
17701 if (BaseShAmt.getNode()) {
17702 if (EltVT.bitsGT(MVT::i32))
17703 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
17704 else if (EltVT.bitsLT(MVT::i32))
17705 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
17707 switch (Op.getOpcode()) {
17709 llvm_unreachable("Unknown shift opcode!");
17711 switch (VT.SimpleTy) {
17712 default: return SDValue();
17721 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
17724 switch (VT.SimpleTy) {
17725 default: return SDValue();
17732 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
17735 switch (VT.SimpleTy) {
17736 default: return SDValue();
17745 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
17751 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17752 if (!Subtarget->is64Bit() &&
17753 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
17754 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
17755 Amt.getOpcode() == ISD::BITCAST &&
17756 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17757 Amt = Amt.getOperand(0);
17758 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17759 VT.getVectorNumElements();
17760 std::vector<SDValue> Vals(Ratio);
17761 for (unsigned i = 0; i != Ratio; ++i)
17762 Vals[i] = Amt.getOperand(i);
17763 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17764 for (unsigned j = 0; j != Ratio; ++j)
17765 if (Vals[j] != Amt.getOperand(i + j))
17768 switch (Op.getOpcode()) {
17770 llvm_unreachable("Unknown shift opcode!");
17772 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
17774 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
17776 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
17783 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
17784 SelectionDAG &DAG) {
17785 MVT VT = Op.getSimpleValueType();
17787 SDValue R = Op.getOperand(0);
17788 SDValue Amt = Op.getOperand(1);
17791 assert(VT.isVector() && "Custom lowering only for vector shifts!");
17792 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
17794 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
17798 V = LowerScalarVariableShift(Op, DAG, Subtarget);
17802 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
17804 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
17805 if (Subtarget->hasInt256()) {
17806 if (Op.getOpcode() == ISD::SRL &&
17807 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17808 VT == MVT::v4i64 || VT == MVT::v8i32))
17810 if (Op.getOpcode() == ISD::SHL &&
17811 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
17812 VT == MVT::v4i64 || VT == MVT::v8i32))
17814 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
17818 // If possible, lower this packed shift into a vector multiply instead of
17819 // expanding it into a sequence of scalar shifts.
17820 // Do this only if the vector shift count is a constant build_vector.
17821 if (Op.getOpcode() == ISD::SHL &&
17822 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
17823 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
17824 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17825 SmallVector<SDValue, 8> Elts;
17826 EVT SVT = VT.getScalarType();
17827 unsigned SVTBits = SVT.getSizeInBits();
17828 const APInt &One = APInt(SVTBits, 1);
17829 unsigned NumElems = VT.getVectorNumElements();
17831 for (unsigned i=0; i !=NumElems; ++i) {
17832 SDValue Op = Amt->getOperand(i);
17833 if (Op->getOpcode() == ISD::UNDEF) {
17834 Elts.push_back(Op);
17838 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
17839 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
17840 uint64_t ShAmt = C.getZExtValue();
17841 if (ShAmt >= SVTBits) {
17842 Elts.push_back(DAG.getUNDEF(SVT));
17845 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
17847 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
17848 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
17851 // Lower SHL with variable shift amount.
17852 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
17853 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
17855 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
17856 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
17857 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
17858 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
17861 // If possible, lower this shift as a sequence of two shifts by
17862 // constant plus a MOVSS/MOVSD instead of scalarizing it.
17864 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
17866 // Could be rewritten as:
17867 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
17869 // The advantage is that the two shifts from the example would be
17870 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
17871 // the vector shift into four scalar shifts plus four pairs of vector
17873 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
17874 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17875 unsigned TargetOpcode = X86ISD::MOVSS;
17876 bool CanBeSimplified;
17877 // The splat value for the first packed shift (the 'X' from the example).
17878 SDValue Amt1 = Amt->getOperand(0);
17879 // The splat value for the second packed shift (the 'Y' from the example).
17880 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
17881 Amt->getOperand(2);
17883 // See if it is possible to replace this node with a sequence of
17884 // two shifts followed by a MOVSS/MOVSD
17885 if (VT == MVT::v4i32) {
17886 // Check if it is legal to use a MOVSS.
17887 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
17888 Amt2 == Amt->getOperand(3);
17889 if (!CanBeSimplified) {
17890 // Otherwise, check if we can still simplify this node using a MOVSD.
17891 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
17892 Amt->getOperand(2) == Amt->getOperand(3);
17893 TargetOpcode = X86ISD::MOVSD;
17894 Amt2 = Amt->getOperand(2);
17897 // Do similar checks for the case where the machine value type
17899 CanBeSimplified = Amt1 == Amt->getOperand(1);
17900 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
17901 CanBeSimplified = Amt2 == Amt->getOperand(i);
17903 if (!CanBeSimplified) {
17904 TargetOpcode = X86ISD::MOVSD;
17905 CanBeSimplified = true;
17906 Amt2 = Amt->getOperand(4);
17907 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
17908 CanBeSimplified = Amt1 == Amt->getOperand(i);
17909 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
17910 CanBeSimplified = Amt2 == Amt->getOperand(j);
17914 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
17915 isa<ConstantSDNode>(Amt2)) {
17916 // Replace this node with two shifts followed by a MOVSS/MOVSD.
17917 EVT CastVT = MVT::v4i32;
17919 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
17920 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
17922 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
17923 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
17924 if (TargetOpcode == X86ISD::MOVSD)
17925 CastVT = MVT::v2i64;
17926 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
17927 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
17928 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
17930 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
17934 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
17935 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
17938 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
17939 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
17941 // Turn 'a' into a mask suitable for VSELECT
17942 SDValue VSelM = DAG.getConstant(0x80, VT);
17943 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17944 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17946 SDValue CM1 = DAG.getConstant(0x0f, VT);
17947 SDValue CM2 = DAG.getConstant(0x3f, VT);
17949 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
17950 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
17951 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
17952 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17953 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17956 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17957 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17958 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17960 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
17961 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
17962 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
17963 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
17964 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
17967 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
17968 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
17969 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
17971 // return VSELECT(r, r+r, a);
17972 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
17973 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
17977 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
17978 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
17979 // solution better.
17980 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
17981 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
17983 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
17984 R = DAG.getNode(ExtOpc, dl, NewVT, R);
17985 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
17986 return DAG.getNode(ISD::TRUNCATE, dl, VT,
17987 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
17990 // Decompose 256-bit shifts into smaller 128-bit shifts.
17991 if (VT.is256BitVector()) {
17992 unsigned NumElems = VT.getVectorNumElements();
17993 MVT EltVT = VT.getVectorElementType();
17994 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17996 // Extract the two vectors
17997 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
17998 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18000 // Recreate the shift amount vectors
18001 SDValue Amt1, Amt2;
18002 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18003 // Constant shift amount
18004 SmallVector<SDValue, 4> Amt1Csts;
18005 SmallVector<SDValue, 4> Amt2Csts;
18006 for (unsigned i = 0; i != NumElems/2; ++i)
18007 Amt1Csts.push_back(Amt->getOperand(i));
18008 for (unsigned i = NumElems/2; i != NumElems; ++i)
18009 Amt2Csts.push_back(Amt->getOperand(i));
18011 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18012 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18014 // Variable shift amount
18015 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18016 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18019 // Issue new vector shifts for the smaller types
18020 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18021 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18023 // Concatenate the result back
18024 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18030 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18031 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18032 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18033 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18034 // has only one use.
18035 SDNode *N = Op.getNode();
18036 SDValue LHS = N->getOperand(0);
18037 SDValue RHS = N->getOperand(1);
18038 unsigned BaseOp = 0;
18041 switch (Op.getOpcode()) {
18042 default: llvm_unreachable("Unknown ovf instruction!");
18044 // A subtract of one will be selected as a INC. Note that INC doesn't
18045 // set CF, so we can't do this for UADDO.
18046 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18048 BaseOp = X86ISD::INC;
18049 Cond = X86::COND_O;
18052 BaseOp = X86ISD::ADD;
18053 Cond = X86::COND_O;
18056 BaseOp = X86ISD::ADD;
18057 Cond = X86::COND_B;
18060 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18061 // set CF, so we can't do this for USUBO.
18062 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18064 BaseOp = X86ISD::DEC;
18065 Cond = X86::COND_O;
18068 BaseOp = X86ISD::SUB;
18069 Cond = X86::COND_O;
18072 BaseOp = X86ISD::SUB;
18073 Cond = X86::COND_B;
18076 BaseOp = X86ISD::SMUL;
18077 Cond = X86::COND_O;
18079 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18080 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18082 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18085 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18086 DAG.getConstant(X86::COND_O, MVT::i32),
18087 SDValue(Sum.getNode(), 2));
18089 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18093 // Also sets EFLAGS.
18094 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18095 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18098 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18099 DAG.getConstant(Cond, MVT::i32),
18100 SDValue(Sum.getNode(), 1));
18102 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18105 // Sign extension of the low part of vector elements. This may be used either
18106 // when sign extend instructions are not available or if the vector element
18107 // sizes already match the sign-extended size. If the vector elements are in
18108 // their pre-extended size and sign extend instructions are available, that will
18109 // be handled by LowerSIGN_EXTEND.
18110 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18111 SelectionDAG &DAG) const {
18113 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18114 MVT VT = Op.getSimpleValueType();
18116 if (!Subtarget->hasSSE2() || !VT.isVector())
18119 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
18120 ExtraVT.getScalarType().getSizeInBits();
18122 switch (VT.SimpleTy) {
18123 default: return SDValue();
18126 if (!Subtarget->hasFp256())
18128 if (!Subtarget->hasInt256()) {
18129 // needs to be split
18130 unsigned NumElems = VT.getVectorNumElements();
18132 // Extract the LHS vectors
18133 SDValue LHS = Op.getOperand(0);
18134 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18135 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18137 MVT EltVT = VT.getVectorElementType();
18138 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18140 EVT ExtraEltVT = ExtraVT.getVectorElementType();
18141 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
18142 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
18144 SDValue Extra = DAG.getValueType(ExtraVT);
18146 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
18147 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
18149 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
18154 SDValue Op0 = Op.getOperand(0);
18156 // This is a sign extension of some low part of vector elements without
18157 // changing the size of the vector elements themselves:
18158 // Shift-Left + Shift-Right-Algebraic.
18159 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
18161 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
18167 /// Returns true if the operand type is exactly twice the native width, and
18168 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18169 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18170 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18171 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
18172 const X86Subtarget &Subtarget =
18173 getTargetMachine().getSubtarget<X86Subtarget>();
18174 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18177 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18178 else if (OpWidth == 128)
18179 return Subtarget.hasCmpxchg16b();
18184 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18185 return needsCmpXchgNb(SI->getValueOperand()->getType());
18188 // Note: this turns large loads into lock cmpxchg8b/16b.
18189 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18190 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18191 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18192 return needsCmpXchgNb(PTy->getElementType());
18195 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18196 const X86Subtarget &Subtarget =
18197 getTargetMachine().getSubtarget<X86Subtarget>();
18198 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18199 const Type *MemType = AI->getType();
18201 // If the operand is too big, we must see if cmpxchg8/16b is available
18202 // and default to library calls otherwise.
18203 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18204 return needsCmpXchgNb(MemType);
18206 AtomicRMWInst::BinOp Op = AI->getOperation();
18209 llvm_unreachable("Unknown atomic operation");
18210 case AtomicRMWInst::Xchg:
18211 case AtomicRMWInst::Add:
18212 case AtomicRMWInst::Sub:
18213 // It's better to use xadd, xsub or xchg for these in all cases.
18215 case AtomicRMWInst::Or:
18216 case AtomicRMWInst::And:
18217 case AtomicRMWInst::Xor:
18218 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18219 // prefix to a normal instruction for these operations.
18220 return !AI->use_empty();
18221 case AtomicRMWInst::Nand:
18222 case AtomicRMWInst::Max:
18223 case AtomicRMWInst::Min:
18224 case AtomicRMWInst::UMax:
18225 case AtomicRMWInst::UMin:
18226 // These always require a non-trivial set of data operations on x86. We must
18227 // use a cmpxchg loop.
18232 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18233 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18234 // no-sse2). There isn't any reason to disable it if the target processor
18236 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18240 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18241 const X86Subtarget &Subtarget =
18242 getTargetMachine().getSubtarget<X86Subtarget>();
18243 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18244 const Type *MemType = AI->getType();
18245 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18246 // there is no benefit in turning such RMWs into loads, and it is actually
18247 // harmful as it introduces a mfence.
18248 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18251 auto Builder = IRBuilder<>(AI);
18252 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18253 auto SynchScope = AI->getSynchScope();
18254 // We must restrict the ordering to avoid generating loads with Release or
18255 // ReleaseAcquire orderings.
18256 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18257 auto Ptr = AI->getPointerOperand();
18259 // Before the load we need a fence. Here is an example lifted from
18260 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18263 // x.store(1, relaxed);
18264 // r1 = y.fetch_add(0, release);
18266 // y.fetch_add(42, acquire);
18267 // r2 = x.load(relaxed);
18268 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18269 // lowered to just a load without a fence. A mfence flushes the store buffer,
18270 // making the optimization clearly correct.
18271 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18272 // otherwise, we might be able to be more agressive on relaxed idempotent
18273 // rmw. In practice, they do not look useful, so we don't try to be
18274 // especially clever.
18275 if (SynchScope == SingleThread) {
18276 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
18277 // the IR level, so we must wrap it in an intrinsic.
18279 } else if (hasMFENCE(Subtarget)) {
18280 Function *MFence = llvm::Intrinsic::getDeclaration(M,
18281 Intrinsic::x86_sse2_mfence);
18282 Builder.CreateCall(MFence);
18284 // FIXME: it might make sense to use a locked operation here but on a
18285 // different cache-line to prevent cache-line bouncing. In practice it
18286 // is probably a small win, and x86 processors without mfence are rare
18287 // enough that we do not bother.
18291 // Finally we can emit the atomic load.
18292 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
18293 AI->getType()->getPrimitiveSizeInBits());
18294 Loaded->setAtomic(Order, SynchScope);
18295 AI->replaceAllUsesWith(Loaded);
18296 AI->eraseFromParent();
18300 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
18301 SelectionDAG &DAG) {
18303 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
18304 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
18305 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
18306 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
18308 // The only fence that needs an instruction is a sequentially-consistent
18309 // cross-thread fence.
18310 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
18311 if (hasMFENCE(*Subtarget))
18312 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
18314 SDValue Chain = Op.getOperand(0);
18315 SDValue Zero = DAG.getConstant(0, MVT::i32);
18317 DAG.getRegister(X86::ESP, MVT::i32), // Base
18318 DAG.getTargetConstant(1, MVT::i8), // Scale
18319 DAG.getRegister(0, MVT::i32), // Index
18320 DAG.getTargetConstant(0, MVT::i32), // Disp
18321 DAG.getRegister(0, MVT::i32), // Segment.
18325 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
18326 return SDValue(Res, 0);
18329 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
18330 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
18333 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
18334 SelectionDAG &DAG) {
18335 MVT T = Op.getSimpleValueType();
18339 switch(T.SimpleTy) {
18340 default: llvm_unreachable("Invalid value type!");
18341 case MVT::i8: Reg = X86::AL; size = 1; break;
18342 case MVT::i16: Reg = X86::AX; size = 2; break;
18343 case MVT::i32: Reg = X86::EAX; size = 4; break;
18345 assert(Subtarget->is64Bit() && "Node not type legal!");
18346 Reg = X86::RAX; size = 8;
18349 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
18350 Op.getOperand(2), SDValue());
18351 SDValue Ops[] = { cpIn.getValue(0),
18354 DAG.getTargetConstant(size, MVT::i8),
18355 cpIn.getValue(1) };
18356 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18357 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
18358 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
18362 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
18363 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
18364 MVT::i32, cpOut.getValue(2));
18365 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
18366 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18368 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
18369 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
18370 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
18374 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
18375 SelectionDAG &DAG) {
18376 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
18377 MVT DstVT = Op.getSimpleValueType();
18379 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
18380 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18381 if (DstVT != MVT::f64)
18382 // This conversion needs to be expanded.
18385 SDValue InVec = Op->getOperand(0);
18387 unsigned NumElts = SrcVT.getVectorNumElements();
18388 EVT SVT = SrcVT.getVectorElementType();
18390 // Widen the vector in input in the case of MVT::v2i32.
18391 // Example: from MVT::v2i32 to MVT::v4i32.
18392 SmallVector<SDValue, 16> Elts;
18393 for (unsigned i = 0, e = NumElts; i != e; ++i)
18394 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
18395 DAG.getIntPtrConstant(i)));
18397 // Explicitly mark the extra elements as Undef.
18398 SDValue Undef = DAG.getUNDEF(SVT);
18399 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
18400 Elts.push_back(Undef);
18402 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18403 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
18404 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
18405 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
18406 DAG.getIntPtrConstant(0));
18409 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
18410 Subtarget->hasMMX() && "Unexpected custom BITCAST");
18411 assert((DstVT == MVT::i64 ||
18412 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
18413 "Unexpected custom BITCAST");
18414 // i64 <=> MMX conversions are Legal.
18415 if (SrcVT==MVT::i64 && DstVT.isVector())
18417 if (DstVT==MVT::i64 && SrcVT.isVector())
18419 // MMX <=> MMX conversions are Legal.
18420 if (SrcVT.isVector() && DstVT.isVector())
18422 // All other conversions need to be expanded.
18426 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
18427 SDNode *Node = Op.getNode();
18429 EVT T = Node->getValueType(0);
18430 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
18431 DAG.getConstant(0, T), Node->getOperand(2));
18432 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
18433 cast<AtomicSDNode>(Node)->getMemoryVT(),
18434 Node->getOperand(0),
18435 Node->getOperand(1), negOp,
18436 cast<AtomicSDNode>(Node)->getMemOperand(),
18437 cast<AtomicSDNode>(Node)->getOrdering(),
18438 cast<AtomicSDNode>(Node)->getSynchScope());
18441 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
18442 SDNode *Node = Op.getNode();
18444 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
18446 // Convert seq_cst store -> xchg
18447 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
18448 // FIXME: On 32-bit, store -> fist or movq would be more efficient
18449 // (The only way to get a 16-byte store is cmpxchg16b)
18450 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
18451 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
18452 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
18453 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
18454 cast<AtomicSDNode>(Node)->getMemoryVT(),
18455 Node->getOperand(0),
18456 Node->getOperand(1), Node->getOperand(2),
18457 cast<AtomicSDNode>(Node)->getMemOperand(),
18458 cast<AtomicSDNode>(Node)->getOrdering(),
18459 cast<AtomicSDNode>(Node)->getSynchScope());
18460 return Swap.getValue(1);
18462 // Other atomic stores have a simple pattern.
18466 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
18467 EVT VT = Op.getNode()->getSimpleValueType(0);
18469 // Let legalize expand this if it isn't a legal type yet.
18470 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18473 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18476 bool ExtraOp = false;
18477 switch (Op.getOpcode()) {
18478 default: llvm_unreachable("Invalid code");
18479 case ISD::ADDC: Opc = X86ISD::ADD; break;
18480 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
18481 case ISD::SUBC: Opc = X86ISD::SUB; break;
18482 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
18486 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18488 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18489 Op.getOperand(1), Op.getOperand(2));
18492 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
18493 SelectionDAG &DAG) {
18494 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
18496 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
18497 // which returns the values as { float, float } (in XMM0) or
18498 // { double, double } (which is returned in XMM0, XMM1).
18500 SDValue Arg = Op.getOperand(0);
18501 EVT ArgVT = Arg.getValueType();
18502 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18504 TargetLowering::ArgListTy Args;
18505 TargetLowering::ArgListEntry Entry;
18509 Entry.isSExt = false;
18510 Entry.isZExt = false;
18511 Args.push_back(Entry);
18513 bool isF64 = ArgVT == MVT::f64;
18514 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
18515 // the small struct {f32, f32} is returned in (eax, edx). For f64,
18516 // the results are returned via SRet in memory.
18517 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
18518 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18519 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
18521 Type *RetTy = isF64
18522 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
18523 : (Type*)VectorType::get(ArgTy, 4);
18525 TargetLowering::CallLoweringInfo CLI(DAG);
18526 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
18527 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
18529 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
18532 // Returned in xmm0 and xmm1.
18533 return CallResult.first;
18535 // Returned in bits 0:31 and 32:64 xmm0.
18536 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18537 CallResult.first, DAG.getIntPtrConstant(0));
18538 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18539 CallResult.first, DAG.getIntPtrConstant(1));
18540 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
18541 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
18544 /// LowerOperation - Provide custom lowering hooks for some operations.
18546 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
18547 switch (Op.getOpcode()) {
18548 default: llvm_unreachable("Should not custom lower this!");
18549 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
18550 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
18551 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
18552 return LowerCMP_SWAP(Op, Subtarget, DAG);
18553 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
18554 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
18555 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
18556 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
18557 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
18558 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
18559 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
18560 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
18561 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
18562 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
18563 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
18564 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
18565 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
18566 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
18567 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
18568 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
18569 case ISD::SHL_PARTS:
18570 case ISD::SRA_PARTS:
18571 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
18572 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
18573 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
18574 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
18575 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
18576 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
18577 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
18578 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
18579 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
18580 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
18581 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
18583 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
18584 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
18585 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
18586 case ISD::SETCC: return LowerSETCC(Op, DAG);
18587 case ISD::SELECT: return LowerSELECT(Op, DAG);
18588 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
18589 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
18590 case ISD::VASTART: return LowerVASTART(Op, DAG);
18591 case ISD::VAARG: return LowerVAARG(Op, DAG);
18592 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
18593 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
18594 case ISD::INTRINSIC_VOID:
18595 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
18596 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
18597 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
18598 case ISD::FRAME_TO_ARGS_OFFSET:
18599 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
18600 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
18601 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
18602 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
18603 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
18604 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
18605 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
18606 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
18607 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
18608 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
18609 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
18610 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
18611 case ISD::UMUL_LOHI:
18612 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
18615 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
18621 case ISD::UMULO: return LowerXALUO(Op, DAG);
18622 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
18623 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
18627 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
18628 case ISD::ADD: return LowerADD(Op, DAG);
18629 case ISD::SUB: return LowerSUB(Op, DAG);
18630 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
18634 /// ReplaceNodeResults - Replace a node with an illegal result type
18635 /// with a new node built out of custom code.
18636 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
18637 SmallVectorImpl<SDValue>&Results,
18638 SelectionDAG &DAG) const {
18640 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18641 switch (N->getOpcode()) {
18643 llvm_unreachable("Do not know how to custom type legalize this operation!");
18644 case ISD::SIGN_EXTEND_INREG:
18649 // We don't want to expand or promote these.
18656 case ISD::UDIVREM: {
18657 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
18658 Results.push_back(V);
18661 case ISD::FP_TO_SINT:
18662 case ISD::FP_TO_UINT: {
18663 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
18665 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
18668 std::pair<SDValue,SDValue> Vals =
18669 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
18670 SDValue FIST = Vals.first, StackSlot = Vals.second;
18671 if (FIST.getNode()) {
18672 EVT VT = N->getValueType(0);
18673 // Return a load from the stack slot.
18674 if (StackSlot.getNode())
18675 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
18676 MachinePointerInfo(),
18677 false, false, false, 0));
18679 Results.push_back(FIST);
18683 case ISD::UINT_TO_FP: {
18684 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18685 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
18686 N->getValueType(0) != MVT::v2f32)
18688 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
18690 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
18692 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
18693 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
18694 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
18695 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
18696 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
18697 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
18700 case ISD::FP_ROUND: {
18701 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
18703 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
18704 Results.push_back(V);
18707 case ISD::INTRINSIC_W_CHAIN: {
18708 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
18710 default : llvm_unreachable("Do not know how to custom type "
18711 "legalize this intrinsic operation!");
18712 case Intrinsic::x86_rdtsc:
18713 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18715 case Intrinsic::x86_rdtscp:
18716 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
18718 case Intrinsic::x86_rdpmc:
18719 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
18722 case ISD::READCYCLECOUNTER: {
18723 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18726 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
18727 EVT T = N->getValueType(0);
18728 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
18729 bool Regs64bit = T == MVT::i128;
18730 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
18731 SDValue cpInL, cpInH;
18732 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18733 DAG.getConstant(0, HalfT));
18734 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18735 DAG.getConstant(1, HalfT));
18736 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
18737 Regs64bit ? X86::RAX : X86::EAX,
18739 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
18740 Regs64bit ? X86::RDX : X86::EDX,
18741 cpInH, cpInL.getValue(1));
18742 SDValue swapInL, swapInH;
18743 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18744 DAG.getConstant(0, HalfT));
18745 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18746 DAG.getConstant(1, HalfT));
18747 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
18748 Regs64bit ? X86::RBX : X86::EBX,
18749 swapInL, cpInH.getValue(1));
18750 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
18751 Regs64bit ? X86::RCX : X86::ECX,
18752 swapInH, swapInL.getValue(1));
18753 SDValue Ops[] = { swapInH.getValue(0),
18755 swapInH.getValue(1) };
18756 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18757 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
18758 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
18759 X86ISD::LCMPXCHG8_DAG;
18760 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
18761 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
18762 Regs64bit ? X86::RAX : X86::EAX,
18763 HalfT, Result.getValue(1));
18764 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
18765 Regs64bit ? X86::RDX : X86::EDX,
18766 HalfT, cpOutL.getValue(2));
18767 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
18769 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
18770 MVT::i32, cpOutH.getValue(2));
18772 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
18773 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
18774 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
18776 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
18777 Results.push_back(Success);
18778 Results.push_back(EFLAGS.getValue(1));
18781 case ISD::ATOMIC_SWAP:
18782 case ISD::ATOMIC_LOAD_ADD:
18783 case ISD::ATOMIC_LOAD_SUB:
18784 case ISD::ATOMIC_LOAD_AND:
18785 case ISD::ATOMIC_LOAD_OR:
18786 case ISD::ATOMIC_LOAD_XOR:
18787 case ISD::ATOMIC_LOAD_NAND:
18788 case ISD::ATOMIC_LOAD_MIN:
18789 case ISD::ATOMIC_LOAD_MAX:
18790 case ISD::ATOMIC_LOAD_UMIN:
18791 case ISD::ATOMIC_LOAD_UMAX:
18792 case ISD::ATOMIC_LOAD: {
18793 // Delegate to generic TypeLegalization. Situations we can really handle
18794 // should have already been dealt with by AtomicExpandPass.cpp.
18797 case ISD::BITCAST: {
18798 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18799 EVT DstVT = N->getValueType(0);
18800 EVT SrcVT = N->getOperand(0)->getValueType(0);
18802 if (SrcVT != MVT::f64 ||
18803 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
18806 unsigned NumElts = DstVT.getVectorNumElements();
18807 EVT SVT = DstVT.getVectorElementType();
18808 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18809 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
18810 MVT::v2f64, N->getOperand(0));
18811 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
18813 if (ExperimentalVectorWideningLegalization) {
18814 // If we are legalizing vectors by widening, we already have the desired
18815 // legal vector type, just return it.
18816 Results.push_back(ToVecInt);
18820 SmallVector<SDValue, 8> Elts;
18821 for (unsigned i = 0, e = NumElts; i != e; ++i)
18822 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
18823 ToVecInt, DAG.getIntPtrConstant(i)));
18825 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
18830 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
18832 default: return nullptr;
18833 case X86ISD::BSF: return "X86ISD::BSF";
18834 case X86ISD::BSR: return "X86ISD::BSR";
18835 case X86ISD::SHLD: return "X86ISD::SHLD";
18836 case X86ISD::SHRD: return "X86ISD::SHRD";
18837 case X86ISD::FAND: return "X86ISD::FAND";
18838 case X86ISD::FANDN: return "X86ISD::FANDN";
18839 case X86ISD::FOR: return "X86ISD::FOR";
18840 case X86ISD::FXOR: return "X86ISD::FXOR";
18841 case X86ISD::FSRL: return "X86ISD::FSRL";
18842 case X86ISD::FILD: return "X86ISD::FILD";
18843 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
18844 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
18845 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
18846 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
18847 case X86ISD::FLD: return "X86ISD::FLD";
18848 case X86ISD::FST: return "X86ISD::FST";
18849 case X86ISD::CALL: return "X86ISD::CALL";
18850 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
18851 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
18852 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
18853 case X86ISD::BT: return "X86ISD::BT";
18854 case X86ISD::CMP: return "X86ISD::CMP";
18855 case X86ISD::COMI: return "X86ISD::COMI";
18856 case X86ISD::UCOMI: return "X86ISD::UCOMI";
18857 case X86ISD::CMPM: return "X86ISD::CMPM";
18858 case X86ISD::CMPMU: return "X86ISD::CMPMU";
18859 case X86ISD::SETCC: return "X86ISD::SETCC";
18860 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
18861 case X86ISD::FSETCC: return "X86ISD::FSETCC";
18862 case X86ISD::CMOV: return "X86ISD::CMOV";
18863 case X86ISD::BRCOND: return "X86ISD::BRCOND";
18864 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
18865 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
18866 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
18867 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
18868 case X86ISD::Wrapper: return "X86ISD::Wrapper";
18869 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
18870 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
18871 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
18872 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
18873 case X86ISD::PINSRB: return "X86ISD::PINSRB";
18874 case X86ISD::PINSRW: return "X86ISD::PINSRW";
18875 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
18876 case X86ISD::ANDNP: return "X86ISD::ANDNP";
18877 case X86ISD::PSIGN: return "X86ISD::PSIGN";
18878 case X86ISD::BLENDI: return "X86ISD::BLENDI";
18879 case X86ISD::SUBUS: return "X86ISD::SUBUS";
18880 case X86ISD::HADD: return "X86ISD::HADD";
18881 case X86ISD::HSUB: return "X86ISD::HSUB";
18882 case X86ISD::FHADD: return "X86ISD::FHADD";
18883 case X86ISD::FHSUB: return "X86ISD::FHSUB";
18884 case X86ISD::UMAX: return "X86ISD::UMAX";
18885 case X86ISD::UMIN: return "X86ISD::UMIN";
18886 case X86ISD::SMAX: return "X86ISD::SMAX";
18887 case X86ISD::SMIN: return "X86ISD::SMIN";
18888 case X86ISD::FMAX: return "X86ISD::FMAX";
18889 case X86ISD::FMIN: return "X86ISD::FMIN";
18890 case X86ISD::FMAXC: return "X86ISD::FMAXC";
18891 case X86ISD::FMINC: return "X86ISD::FMINC";
18892 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
18893 case X86ISD::FRCP: return "X86ISD::FRCP";
18894 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
18895 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
18896 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
18897 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
18898 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
18899 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
18900 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
18901 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
18902 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
18903 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
18904 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
18905 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
18906 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
18907 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
18908 case X86ISD::VZEXT: return "X86ISD::VZEXT";
18909 case X86ISD::VSEXT: return "X86ISD::VSEXT";
18910 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
18911 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
18912 case X86ISD::VINSERT: return "X86ISD::VINSERT";
18913 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
18914 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
18915 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
18916 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
18917 case X86ISD::VSHL: return "X86ISD::VSHL";
18918 case X86ISD::VSRL: return "X86ISD::VSRL";
18919 case X86ISD::VSRA: return "X86ISD::VSRA";
18920 case X86ISD::VSHLI: return "X86ISD::VSHLI";
18921 case X86ISD::VSRLI: return "X86ISD::VSRLI";
18922 case X86ISD::VSRAI: return "X86ISD::VSRAI";
18923 case X86ISD::CMPP: return "X86ISD::CMPP";
18924 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
18925 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
18926 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
18927 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
18928 case X86ISD::ADD: return "X86ISD::ADD";
18929 case X86ISD::SUB: return "X86ISD::SUB";
18930 case X86ISD::ADC: return "X86ISD::ADC";
18931 case X86ISD::SBB: return "X86ISD::SBB";
18932 case X86ISD::SMUL: return "X86ISD::SMUL";
18933 case X86ISD::UMUL: return "X86ISD::UMUL";
18934 case X86ISD::INC: return "X86ISD::INC";
18935 case X86ISD::DEC: return "X86ISD::DEC";
18936 case X86ISD::OR: return "X86ISD::OR";
18937 case X86ISD::XOR: return "X86ISD::XOR";
18938 case X86ISD::AND: return "X86ISD::AND";
18939 case X86ISD::BEXTR: return "X86ISD::BEXTR";
18940 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
18941 case X86ISD::PTEST: return "X86ISD::PTEST";
18942 case X86ISD::TESTP: return "X86ISD::TESTP";
18943 case X86ISD::TESTM: return "X86ISD::TESTM";
18944 case X86ISD::TESTNM: return "X86ISD::TESTNM";
18945 case X86ISD::KORTEST: return "X86ISD::KORTEST";
18946 case X86ISD::PACKSS: return "X86ISD::PACKSS";
18947 case X86ISD::PACKUS: return "X86ISD::PACKUS";
18948 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
18949 case X86ISD::VALIGN: return "X86ISD::VALIGN";
18950 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
18951 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
18952 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
18953 case X86ISD::SHUFP: return "X86ISD::SHUFP";
18954 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
18955 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
18956 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
18957 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
18958 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
18959 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
18960 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
18961 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
18962 case X86ISD::MOVSD: return "X86ISD::MOVSD";
18963 case X86ISD::MOVSS: return "X86ISD::MOVSS";
18964 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
18965 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
18966 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
18967 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
18968 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
18969 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
18970 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
18971 case X86ISD::VPERMV: return "X86ISD::VPERMV";
18972 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
18973 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
18974 case X86ISD::VPERMI: return "X86ISD::VPERMI";
18975 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
18976 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
18977 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
18978 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
18979 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
18980 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
18981 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
18982 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
18983 case X86ISD::SAHF: return "X86ISD::SAHF";
18984 case X86ISD::RDRAND: return "X86ISD::RDRAND";
18985 case X86ISD::RDSEED: return "X86ISD::RDSEED";
18986 case X86ISD::FMADD: return "X86ISD::FMADD";
18987 case X86ISD::FMSUB: return "X86ISD::FMSUB";
18988 case X86ISD::FNMADD: return "X86ISD::FNMADD";
18989 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
18990 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
18991 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
18992 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
18993 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
18994 case X86ISD::XTEST: return "X86ISD::XTEST";
18998 // isLegalAddressingMode - Return true if the addressing mode represented
18999 // by AM is legal for this target, for a load/store of the specified type.
19000 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
19002 // X86 supports extremely general addressing modes.
19003 CodeModel::Model M = getTargetMachine().getCodeModel();
19004 Reloc::Model R = getTargetMachine().getRelocationModel();
19006 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19007 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19012 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19014 // If a reference to this global requires an extra load, we can't fold it.
19015 if (isGlobalStubReference(GVFlags))
19018 // If BaseGV requires a register for the PIC base, we cannot also have a
19019 // BaseReg specified.
19020 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19023 // If lower 4G is not available, then we must use rip-relative addressing.
19024 if ((M != CodeModel::Small || R != Reloc::Static) &&
19025 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19029 switch (AM.Scale) {
19035 // These scales always work.
19040 // These scales are formed with basereg+scalereg. Only accept if there is
19045 default: // Other stuff never works.
19052 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19053 unsigned Bits = Ty->getScalarSizeInBits();
19055 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19056 // particularly cheaper than those without.
19060 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19061 // variable shifts just as cheap as scalar ones.
19062 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19065 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19066 // fully general vector.
19070 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19071 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19073 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19074 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19075 return NumBits1 > NumBits2;
19078 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19079 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19082 if (!isTypeLegal(EVT::getEVT(Ty1)))
19085 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19087 // Assuming the caller doesn't have a zeroext or signext return parameter,
19088 // truncation all the way down to i1 is valid.
19092 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19093 return isInt<32>(Imm);
19096 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19097 // Can also use sub to handle negated immediates.
19098 return isInt<32>(Imm);
19101 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
19102 if (!VT1.isInteger() || !VT2.isInteger())
19104 unsigned NumBits1 = VT1.getSizeInBits();
19105 unsigned NumBits2 = VT2.getSizeInBits();
19106 return NumBits1 > NumBits2;
19109 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19110 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19111 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19114 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19115 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19116 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19119 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19120 EVT VT1 = Val.getValueType();
19121 if (isZExtFree(VT1, VT2))
19124 if (Val.getOpcode() != ISD::LOAD)
19127 if (!VT1.isSimple() || !VT1.isInteger() ||
19128 !VT2.isSimple() || !VT2.isInteger())
19131 switch (VT1.getSimpleVT().SimpleTy) {
19136 // X86 has 8, 16, and 32-bit zero-extending loads.
19144 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
19145 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
19148 VT = VT.getScalarType();
19150 if (!VT.isSimple())
19153 switch (VT.getSimpleVT().SimpleTy) {
19164 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
19165 // i16 instructions are longer (0x66 prefix) and potentially slower.
19166 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19169 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19170 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19171 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19172 /// are assumed to be legal.
19174 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19176 if (!VT.isSimple())
19179 MVT SVT = VT.getSimpleVT();
19181 // Very little shuffling can be done for 64-bit vectors right now.
19182 if (VT.getSizeInBits() == 64)
19185 // If this is a single-input shuffle with no 128 bit lane crossings we can
19186 // lower it into pshufb.
19187 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
19188 (SVT.is256BitVector() && Subtarget->hasInt256())) {
19189 bool isLegal = true;
19190 for (unsigned I = 0, E = M.size(); I != E; ++I) {
19191 if (M[I] >= (int)SVT.getVectorNumElements() ||
19192 ShuffleCrosses128bitLane(SVT, I, M[I])) {
19201 // FIXME: blends, shifts.
19202 return (SVT.getVectorNumElements() == 2 ||
19203 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
19204 isMOVLMask(M, SVT) ||
19205 isMOVHLPSMask(M, SVT) ||
19206 isSHUFPMask(M, SVT) ||
19207 isPSHUFDMask(M, SVT) ||
19208 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
19209 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
19210 isPALIGNRMask(M, SVT, Subtarget) ||
19211 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
19212 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
19213 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19214 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19215 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
19219 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
19221 if (!VT.isSimple())
19224 MVT SVT = VT.getSimpleVT();
19225 unsigned NumElts = SVT.getVectorNumElements();
19226 // FIXME: This collection of masks seems suspect.
19229 if (NumElts == 4 && SVT.is128BitVector()) {
19230 return (isMOVLMask(Mask, SVT) ||
19231 isCommutedMOVLMask(Mask, SVT, true) ||
19232 isSHUFPMask(Mask, SVT) ||
19233 isSHUFPMask(Mask, SVT, /* Commuted */ true));
19238 //===----------------------------------------------------------------------===//
19239 // X86 Scheduler Hooks
19240 //===----------------------------------------------------------------------===//
19242 /// Utility function to emit xbegin specifying the start of an RTM region.
19243 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
19244 const TargetInstrInfo *TII) {
19245 DebugLoc DL = MI->getDebugLoc();
19247 const BasicBlock *BB = MBB->getBasicBlock();
19248 MachineFunction::iterator I = MBB;
19251 // For the v = xbegin(), we generate
19262 MachineBasicBlock *thisMBB = MBB;
19263 MachineFunction *MF = MBB->getParent();
19264 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19265 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19266 MF->insert(I, mainMBB);
19267 MF->insert(I, sinkMBB);
19269 // Transfer the remainder of BB and its successor edges to sinkMBB.
19270 sinkMBB->splice(sinkMBB->begin(), MBB,
19271 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19272 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19276 // # fallthrough to mainMBB
19277 // # abortion to sinkMBB
19278 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
19279 thisMBB->addSuccessor(mainMBB);
19280 thisMBB->addSuccessor(sinkMBB);
19284 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
19285 mainMBB->addSuccessor(sinkMBB);
19288 // EAX is live into the sinkMBB
19289 sinkMBB->addLiveIn(X86::EAX);
19290 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19291 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19294 MI->eraseFromParent();
19298 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
19299 // or XMM0_V32I8 in AVX all of this code can be replaced with that
19300 // in the .td file.
19301 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
19302 const TargetInstrInfo *TII) {
19304 switch (MI->getOpcode()) {
19305 default: llvm_unreachable("illegal opcode!");
19306 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
19307 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
19308 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
19309 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
19310 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
19311 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
19312 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
19313 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
19316 DebugLoc dl = MI->getDebugLoc();
19317 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19319 unsigned NumArgs = MI->getNumOperands();
19320 for (unsigned i = 1; i < NumArgs; ++i) {
19321 MachineOperand &Op = MI->getOperand(i);
19322 if (!(Op.isReg() && Op.isImplicit()))
19323 MIB.addOperand(Op);
19325 if (MI->hasOneMemOperand())
19326 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19328 BuildMI(*BB, MI, dl,
19329 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19330 .addReg(X86::XMM0);
19332 MI->eraseFromParent();
19336 // FIXME: Custom handling because TableGen doesn't support multiple implicit
19337 // defs in an instruction pattern
19338 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
19339 const TargetInstrInfo *TII) {
19341 switch (MI->getOpcode()) {
19342 default: llvm_unreachable("illegal opcode!");
19343 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
19344 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
19345 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
19346 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
19347 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
19348 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
19349 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
19350 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
19353 DebugLoc dl = MI->getDebugLoc();
19354 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19356 unsigned NumArgs = MI->getNumOperands(); // remove the results
19357 for (unsigned i = 1; i < NumArgs; ++i) {
19358 MachineOperand &Op = MI->getOperand(i);
19359 if (!(Op.isReg() && Op.isImplicit()))
19360 MIB.addOperand(Op);
19362 if (MI->hasOneMemOperand())
19363 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19365 BuildMI(*BB, MI, dl,
19366 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19369 MI->eraseFromParent();
19373 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
19374 const TargetInstrInfo *TII,
19375 const X86Subtarget* Subtarget) {
19376 DebugLoc dl = MI->getDebugLoc();
19378 // Address into RAX/EAX, other two args into ECX, EDX.
19379 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
19380 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
19381 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
19382 for (int i = 0; i < X86::AddrNumOperands; ++i)
19383 MIB.addOperand(MI->getOperand(i));
19385 unsigned ValOps = X86::AddrNumOperands;
19386 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
19387 .addReg(MI->getOperand(ValOps).getReg());
19388 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
19389 .addReg(MI->getOperand(ValOps+1).getReg());
19391 // The instruction doesn't actually take any operands though.
19392 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
19394 MI->eraseFromParent(); // The pseudo is gone now.
19398 MachineBasicBlock *
19399 X86TargetLowering::EmitVAARG64WithCustomInserter(
19401 MachineBasicBlock *MBB) const {
19402 // Emit va_arg instruction on X86-64.
19404 // Operands to this pseudo-instruction:
19405 // 0 ) Output : destination address (reg)
19406 // 1-5) Input : va_list address (addr, i64mem)
19407 // 6 ) ArgSize : Size (in bytes) of vararg type
19408 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
19409 // 8 ) Align : Alignment of type
19410 // 9 ) EFLAGS (implicit-def)
19412 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
19413 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
19415 unsigned DestReg = MI->getOperand(0).getReg();
19416 MachineOperand &Base = MI->getOperand(1);
19417 MachineOperand &Scale = MI->getOperand(2);
19418 MachineOperand &Index = MI->getOperand(3);
19419 MachineOperand &Disp = MI->getOperand(4);
19420 MachineOperand &Segment = MI->getOperand(5);
19421 unsigned ArgSize = MI->getOperand(6).getImm();
19422 unsigned ArgMode = MI->getOperand(7).getImm();
19423 unsigned Align = MI->getOperand(8).getImm();
19425 // Memory Reference
19426 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
19427 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19428 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19430 // Machine Information
19431 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
19432 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
19433 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
19434 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
19435 DebugLoc DL = MI->getDebugLoc();
19437 // struct va_list {
19440 // i64 overflow_area (address)
19441 // i64 reg_save_area (address)
19443 // sizeof(va_list) = 24
19444 // alignment(va_list) = 8
19446 unsigned TotalNumIntRegs = 6;
19447 unsigned TotalNumXMMRegs = 8;
19448 bool UseGPOffset = (ArgMode == 1);
19449 bool UseFPOffset = (ArgMode == 2);
19450 unsigned MaxOffset = TotalNumIntRegs * 8 +
19451 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
19453 /* Align ArgSize to a multiple of 8 */
19454 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
19455 bool NeedsAlign = (Align > 8);
19457 MachineBasicBlock *thisMBB = MBB;
19458 MachineBasicBlock *overflowMBB;
19459 MachineBasicBlock *offsetMBB;
19460 MachineBasicBlock *endMBB;
19462 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
19463 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
19464 unsigned OffsetReg = 0;
19466 if (!UseGPOffset && !UseFPOffset) {
19467 // If we only pull from the overflow region, we don't create a branch.
19468 // We don't need to alter control flow.
19469 OffsetDestReg = 0; // unused
19470 OverflowDestReg = DestReg;
19472 offsetMBB = nullptr;
19473 overflowMBB = thisMBB;
19476 // First emit code to check if gp_offset (or fp_offset) is below the bound.
19477 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
19478 // If not, pull from overflow_area. (branch to overflowMBB)
19483 // offsetMBB overflowMBB
19488 // Registers for the PHI in endMBB
19489 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
19490 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
19492 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19493 MachineFunction *MF = MBB->getParent();
19494 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19495 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19496 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19498 MachineFunction::iterator MBBIter = MBB;
19501 // Insert the new basic blocks
19502 MF->insert(MBBIter, offsetMBB);
19503 MF->insert(MBBIter, overflowMBB);
19504 MF->insert(MBBIter, endMBB);
19506 // Transfer the remainder of MBB and its successor edges to endMBB.
19507 endMBB->splice(endMBB->begin(), thisMBB,
19508 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
19509 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
19511 // Make offsetMBB and overflowMBB successors of thisMBB
19512 thisMBB->addSuccessor(offsetMBB);
19513 thisMBB->addSuccessor(overflowMBB);
19515 // endMBB is a successor of both offsetMBB and overflowMBB
19516 offsetMBB->addSuccessor(endMBB);
19517 overflowMBB->addSuccessor(endMBB);
19519 // Load the offset value into a register
19520 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19521 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
19525 .addDisp(Disp, UseFPOffset ? 4 : 0)
19526 .addOperand(Segment)
19527 .setMemRefs(MMOBegin, MMOEnd);
19529 // Check if there is enough room left to pull this argument.
19530 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
19532 .addImm(MaxOffset + 8 - ArgSizeA8);
19534 // Branch to "overflowMBB" if offset >= max
19535 // Fall through to "offsetMBB" otherwise
19536 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
19537 .addMBB(overflowMBB);
19540 // In offsetMBB, emit code to use the reg_save_area.
19542 assert(OffsetReg != 0);
19544 // Read the reg_save_area address.
19545 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
19546 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
19551 .addOperand(Segment)
19552 .setMemRefs(MMOBegin, MMOEnd);
19554 // Zero-extend the offset
19555 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
19556 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
19559 .addImm(X86::sub_32bit);
19561 // Add the offset to the reg_save_area to get the final address.
19562 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
19563 .addReg(OffsetReg64)
19564 .addReg(RegSaveReg);
19566 // Compute the offset for the next argument
19567 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19568 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
19570 .addImm(UseFPOffset ? 16 : 8);
19572 // Store it back into the va_list.
19573 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
19577 .addDisp(Disp, UseFPOffset ? 4 : 0)
19578 .addOperand(Segment)
19579 .addReg(NextOffsetReg)
19580 .setMemRefs(MMOBegin, MMOEnd);
19583 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
19588 // Emit code to use overflow area
19591 // Load the overflow_area address into a register.
19592 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
19593 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
19598 .addOperand(Segment)
19599 .setMemRefs(MMOBegin, MMOEnd);
19601 // If we need to align it, do so. Otherwise, just copy the address
19602 // to OverflowDestReg.
19604 // Align the overflow address
19605 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
19606 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
19608 // aligned_addr = (addr + (align-1)) & ~(align-1)
19609 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
19610 .addReg(OverflowAddrReg)
19613 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
19615 .addImm(~(uint64_t)(Align-1));
19617 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
19618 .addReg(OverflowAddrReg);
19621 // Compute the next overflow address after this argument.
19622 // (the overflow address should be kept 8-byte aligned)
19623 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
19624 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
19625 .addReg(OverflowDestReg)
19626 .addImm(ArgSizeA8);
19628 // Store the new overflow address.
19629 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
19634 .addOperand(Segment)
19635 .addReg(NextAddrReg)
19636 .setMemRefs(MMOBegin, MMOEnd);
19638 // If we branched, emit the PHI to the front of endMBB.
19640 BuildMI(*endMBB, endMBB->begin(), DL,
19641 TII->get(X86::PHI), DestReg)
19642 .addReg(OffsetDestReg).addMBB(offsetMBB)
19643 .addReg(OverflowDestReg).addMBB(overflowMBB);
19646 // Erase the pseudo instruction
19647 MI->eraseFromParent();
19652 MachineBasicBlock *
19653 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
19655 MachineBasicBlock *MBB) const {
19656 // Emit code to save XMM registers to the stack. The ABI says that the
19657 // number of registers to save is given in %al, so it's theoretically
19658 // possible to do an indirect jump trick to avoid saving all of them,
19659 // however this code takes a simpler approach and just executes all
19660 // of the stores if %al is non-zero. It's less code, and it's probably
19661 // easier on the hardware branch predictor, and stores aren't all that
19662 // expensive anyway.
19664 // Create the new basic blocks. One block contains all the XMM stores,
19665 // and one block is the final destination regardless of whether any
19666 // stores were performed.
19667 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19668 MachineFunction *F = MBB->getParent();
19669 MachineFunction::iterator MBBIter = MBB;
19671 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
19672 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
19673 F->insert(MBBIter, XMMSaveMBB);
19674 F->insert(MBBIter, EndMBB);
19676 // Transfer the remainder of MBB and its successor edges to EndMBB.
19677 EndMBB->splice(EndMBB->begin(), MBB,
19678 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19679 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
19681 // The original block will now fall through to the XMM save block.
19682 MBB->addSuccessor(XMMSaveMBB);
19683 // The XMMSaveMBB will fall through to the end block.
19684 XMMSaveMBB->addSuccessor(EndMBB);
19686 // Now add the instructions.
19687 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
19688 DebugLoc DL = MI->getDebugLoc();
19690 unsigned CountReg = MI->getOperand(0).getReg();
19691 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
19692 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
19694 if (!Subtarget->isTargetWin64()) {
19695 // If %al is 0, branch around the XMM save block.
19696 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
19697 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
19698 MBB->addSuccessor(EndMBB);
19701 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
19702 // that was just emitted, but clearly shouldn't be "saved".
19703 assert((MI->getNumOperands() <= 3 ||
19704 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
19705 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
19706 && "Expected last argument to be EFLAGS");
19707 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
19708 // In the XMM save block, save all the XMM argument registers.
19709 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
19710 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
19711 MachineMemOperand *MMO =
19712 F->getMachineMemOperand(
19713 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
19714 MachineMemOperand::MOStore,
19715 /*Size=*/16, /*Align=*/16);
19716 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
19717 .addFrameIndex(RegSaveFrameIndex)
19718 .addImm(/*Scale=*/1)
19719 .addReg(/*IndexReg=*/0)
19720 .addImm(/*Disp=*/Offset)
19721 .addReg(/*Segment=*/0)
19722 .addReg(MI->getOperand(i).getReg())
19723 .addMemOperand(MMO);
19726 MI->eraseFromParent(); // The pseudo instruction is gone now.
19731 // The EFLAGS operand of SelectItr might be missing a kill marker
19732 // because there were multiple uses of EFLAGS, and ISel didn't know
19733 // which to mark. Figure out whether SelectItr should have had a
19734 // kill marker, and set it if it should. Returns the correct kill
19736 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
19737 MachineBasicBlock* BB,
19738 const TargetRegisterInfo* TRI) {
19739 // Scan forward through BB for a use/def of EFLAGS.
19740 MachineBasicBlock::iterator miI(std::next(SelectItr));
19741 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
19742 const MachineInstr& mi = *miI;
19743 if (mi.readsRegister(X86::EFLAGS))
19745 if (mi.definesRegister(X86::EFLAGS))
19746 break; // Should have kill-flag - update below.
19749 // If we hit the end of the block, check whether EFLAGS is live into a
19751 if (miI == BB->end()) {
19752 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
19753 sEnd = BB->succ_end();
19754 sItr != sEnd; ++sItr) {
19755 MachineBasicBlock* succ = *sItr;
19756 if (succ->isLiveIn(X86::EFLAGS))
19761 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
19762 // out. SelectMI should have a kill flag on EFLAGS.
19763 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
19767 MachineBasicBlock *
19768 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
19769 MachineBasicBlock *BB) const {
19770 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19771 DebugLoc DL = MI->getDebugLoc();
19773 // To "insert" a SELECT_CC instruction, we actually have to insert the
19774 // diamond control-flow pattern. The incoming instruction knows the
19775 // destination vreg to set, the condition code register to branch on, the
19776 // true/false values to select between, and a branch opcode to use.
19777 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19778 MachineFunction::iterator It = BB;
19784 // cmpTY ccX, r1, r2
19786 // fallthrough --> copy0MBB
19787 MachineBasicBlock *thisMBB = BB;
19788 MachineFunction *F = BB->getParent();
19789 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
19790 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
19791 F->insert(It, copy0MBB);
19792 F->insert(It, sinkMBB);
19794 // If the EFLAGS register isn't dead in the terminator, then claim that it's
19795 // live into the sink and copy blocks.
19796 const TargetRegisterInfo *TRI =
19797 BB->getParent()->getSubtarget().getRegisterInfo();
19798 if (!MI->killsRegister(X86::EFLAGS) &&
19799 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
19800 copy0MBB->addLiveIn(X86::EFLAGS);
19801 sinkMBB->addLiveIn(X86::EFLAGS);
19804 // Transfer the remainder of BB and its successor edges to sinkMBB.
19805 sinkMBB->splice(sinkMBB->begin(), BB,
19806 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19807 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
19809 // Add the true and fallthrough blocks as its successors.
19810 BB->addSuccessor(copy0MBB);
19811 BB->addSuccessor(sinkMBB);
19813 // Create the conditional branch instruction.
19815 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
19816 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
19819 // %FalseValue = ...
19820 // # fallthrough to sinkMBB
19821 copy0MBB->addSuccessor(sinkMBB);
19824 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
19826 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19827 TII->get(X86::PHI), MI->getOperand(0).getReg())
19828 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
19829 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
19831 MI->eraseFromParent(); // The pseudo instruction is gone now.
19835 MachineBasicBlock *
19836 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
19837 MachineBasicBlock *BB) const {
19838 MachineFunction *MF = BB->getParent();
19839 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
19840 DebugLoc DL = MI->getDebugLoc();
19841 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19843 assert(MF->shouldSplitStack());
19845 const bool Is64Bit = Subtarget->is64Bit();
19846 const bool IsLP64 = Subtarget->isTarget64BitLP64();
19848 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
19849 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
19852 // ... [Till the alloca]
19853 // If stacklet is not large enough, jump to mallocMBB
19856 // Allocate by subtracting from RSP
19857 // Jump to continueMBB
19860 // Allocate by call to runtime
19864 // [rest of original BB]
19867 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19868 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19869 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19871 MachineRegisterInfo &MRI = MF->getRegInfo();
19872 const TargetRegisterClass *AddrRegClass =
19873 getRegClassFor(getPointerTy());
19875 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19876 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19877 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
19878 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
19879 sizeVReg = MI->getOperand(1).getReg(),
19880 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
19882 MachineFunction::iterator MBBIter = BB;
19885 MF->insert(MBBIter, bumpMBB);
19886 MF->insert(MBBIter, mallocMBB);
19887 MF->insert(MBBIter, continueMBB);
19889 continueMBB->splice(continueMBB->begin(), BB,
19890 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19891 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
19893 // Add code to the main basic block to check if the stack limit has been hit,
19894 // and if so, jump to mallocMBB otherwise to bumpMBB.
19895 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
19896 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
19897 .addReg(tmpSPVReg).addReg(sizeVReg);
19898 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
19899 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
19900 .addReg(SPLimitVReg);
19901 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
19903 // bumpMBB simply decreases the stack pointer, since we know the current
19904 // stacklet has enough space.
19905 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
19906 .addReg(SPLimitVReg);
19907 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
19908 .addReg(SPLimitVReg);
19909 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
19911 // Calls into a routine in libgcc to allocate more space from the heap.
19912 const uint32_t *RegMask = MF->getTarget()
19913 .getSubtargetImpl()
19914 ->getRegisterInfo()
19915 ->getCallPreservedMask(CallingConv::C);
19917 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
19919 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19920 .addExternalSymbol("__morestack_allocate_stack_space")
19921 .addRegMask(RegMask)
19922 .addReg(X86::RDI, RegState::Implicit)
19923 .addReg(X86::RAX, RegState::ImplicitDefine);
19924 } else if (Is64Bit) {
19925 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
19927 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19928 .addExternalSymbol("__morestack_allocate_stack_space")
19929 .addRegMask(RegMask)
19930 .addReg(X86::EDI, RegState::Implicit)
19931 .addReg(X86::EAX, RegState::ImplicitDefine);
19933 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
19935 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
19936 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
19937 .addExternalSymbol("__morestack_allocate_stack_space")
19938 .addRegMask(RegMask)
19939 .addReg(X86::EAX, RegState::ImplicitDefine);
19943 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
19946 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
19947 .addReg(IsLP64 ? X86::RAX : X86::EAX);
19948 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
19950 // Set up the CFG correctly.
19951 BB->addSuccessor(bumpMBB);
19952 BB->addSuccessor(mallocMBB);
19953 mallocMBB->addSuccessor(continueMBB);
19954 bumpMBB->addSuccessor(continueMBB);
19956 // Take care of the PHI nodes.
19957 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
19958 MI->getOperand(0).getReg())
19959 .addReg(mallocPtrVReg).addMBB(mallocMBB)
19960 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
19962 // Delete the original pseudo instruction.
19963 MI->eraseFromParent();
19966 return continueMBB;
19969 MachineBasicBlock *
19970 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
19971 MachineBasicBlock *BB) const {
19972 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
19973 DebugLoc DL = MI->getDebugLoc();
19975 assert(!Subtarget->isTargetMacho());
19977 // The lowering is pretty easy: we're just emitting the call to _alloca. The
19978 // non-trivial part is impdef of ESP.
19980 if (Subtarget->isTargetWin64()) {
19981 if (Subtarget->isTargetCygMing()) {
19982 // ___chkstk(Mingw64):
19983 // Clobbers R10, R11, RAX and EFLAGS.
19985 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19986 .addExternalSymbol("___chkstk")
19987 .addReg(X86::RAX, RegState::Implicit)
19988 .addReg(X86::RSP, RegState::Implicit)
19989 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
19990 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
19991 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19993 // __chkstk(MSVCRT): does not update stack pointer.
19994 // Clobbers R10, R11 and EFLAGS.
19995 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
19996 .addExternalSymbol("__chkstk")
19997 .addReg(X86::RAX, RegState::Implicit)
19998 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
19999 // RAX has the offset to be subtracted from RSP.
20000 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
20005 const char *StackProbeSymbol =
20006 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
20008 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
20009 .addExternalSymbol(StackProbeSymbol)
20010 .addReg(X86::EAX, RegState::Implicit)
20011 .addReg(X86::ESP, RegState::Implicit)
20012 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
20013 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
20014 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20017 MI->eraseFromParent(); // The pseudo instruction is gone now.
20021 MachineBasicBlock *
20022 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20023 MachineBasicBlock *BB) const {
20024 // This is pretty easy. We're taking the value that we received from
20025 // our load from the relocation, sticking it in either RDI (x86-64)
20026 // or EAX and doing an indirect call. The return value will then
20027 // be in the normal return register.
20028 MachineFunction *F = BB->getParent();
20029 const X86InstrInfo *TII =
20030 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
20031 DebugLoc DL = MI->getDebugLoc();
20033 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
20034 assert(MI->getOperand(3).isGlobal() && "This should be a global");
20036 // Get a register mask for the lowered call.
20037 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
20038 // proper register mask.
20039 const uint32_t *RegMask = F->getTarget()
20040 .getSubtargetImpl()
20041 ->getRegisterInfo()
20042 ->getCallPreservedMask(CallingConv::C);
20043 if (Subtarget->is64Bit()) {
20044 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20045 TII->get(X86::MOV64rm), X86::RDI)
20047 .addImm(0).addReg(0)
20048 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20049 MI->getOperand(3).getTargetFlags())
20051 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
20052 addDirectMem(MIB, X86::RDI);
20053 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
20054 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
20055 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20056 TII->get(X86::MOV32rm), X86::EAX)
20058 .addImm(0).addReg(0)
20059 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20060 MI->getOperand(3).getTargetFlags())
20062 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20063 addDirectMem(MIB, X86::EAX);
20064 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20066 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20067 TII->get(X86::MOV32rm), X86::EAX)
20068 .addReg(TII->getGlobalBaseReg(F))
20069 .addImm(0).addReg(0)
20070 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20071 MI->getOperand(3).getTargetFlags())
20073 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20074 addDirectMem(MIB, X86::EAX);
20075 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20078 MI->eraseFromParent(); // The pseudo instruction is gone now.
20082 MachineBasicBlock *
20083 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
20084 MachineBasicBlock *MBB) const {
20085 DebugLoc DL = MI->getDebugLoc();
20086 MachineFunction *MF = MBB->getParent();
20087 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20088 MachineRegisterInfo &MRI = MF->getRegInfo();
20090 const BasicBlock *BB = MBB->getBasicBlock();
20091 MachineFunction::iterator I = MBB;
20094 // Memory Reference
20095 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20096 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20099 unsigned MemOpndSlot = 0;
20101 unsigned CurOp = 0;
20103 DstReg = MI->getOperand(CurOp++).getReg();
20104 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
20105 assert(RC->hasType(MVT::i32) && "Invalid destination!");
20106 unsigned mainDstReg = MRI.createVirtualRegister(RC);
20107 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
20109 MemOpndSlot = CurOp;
20111 MVT PVT = getPointerTy();
20112 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20113 "Invalid Pointer Size!");
20115 // For v = setjmp(buf), we generate
20118 // buf[LabelOffset] = restoreMBB
20119 // SjLjSetup restoreMBB
20125 // v = phi(main, restore)
20130 MachineBasicBlock *thisMBB = MBB;
20131 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20132 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20133 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
20134 MF->insert(I, mainMBB);
20135 MF->insert(I, sinkMBB);
20136 MF->push_back(restoreMBB);
20138 MachineInstrBuilder MIB;
20140 // Transfer the remainder of BB and its successor edges to sinkMBB.
20141 sinkMBB->splice(sinkMBB->begin(), MBB,
20142 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20143 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20146 unsigned PtrStoreOpc = 0;
20147 unsigned LabelReg = 0;
20148 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20149 Reloc::Model RM = MF->getTarget().getRelocationModel();
20150 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
20151 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
20153 // Prepare IP either in reg or imm.
20154 if (!UseImmLabel) {
20155 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
20156 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
20157 LabelReg = MRI.createVirtualRegister(PtrRC);
20158 if (Subtarget->is64Bit()) {
20159 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
20163 .addMBB(restoreMBB)
20166 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
20167 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
20168 .addReg(XII->getGlobalBaseReg(MF))
20171 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
20175 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
20177 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
20178 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20179 if (i == X86::AddrDisp)
20180 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
20182 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
20185 MIB.addReg(LabelReg);
20187 MIB.addMBB(restoreMBB);
20188 MIB.setMemRefs(MMOBegin, MMOEnd);
20190 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
20191 .addMBB(restoreMBB);
20193 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20194 MF->getSubtarget().getRegisterInfo());
20195 MIB.addRegMask(RegInfo->getNoPreservedMask());
20196 thisMBB->addSuccessor(mainMBB);
20197 thisMBB->addSuccessor(restoreMBB);
20201 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
20202 mainMBB->addSuccessor(sinkMBB);
20205 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20206 TII->get(X86::PHI), DstReg)
20207 .addReg(mainDstReg).addMBB(mainMBB)
20208 .addReg(restoreDstReg).addMBB(restoreMBB);
20211 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
20212 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
20213 restoreMBB->addSuccessor(sinkMBB);
20215 MI->eraseFromParent();
20219 MachineBasicBlock *
20220 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
20221 MachineBasicBlock *MBB) const {
20222 DebugLoc DL = MI->getDebugLoc();
20223 MachineFunction *MF = MBB->getParent();
20224 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20225 MachineRegisterInfo &MRI = MF->getRegInfo();
20227 // Memory Reference
20228 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20229 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20231 MVT PVT = getPointerTy();
20232 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20233 "Invalid Pointer Size!");
20235 const TargetRegisterClass *RC =
20236 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
20237 unsigned Tmp = MRI.createVirtualRegister(RC);
20238 // Since FP is only updated here but NOT referenced, it's treated as GPR.
20239 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20240 MF->getSubtarget().getRegisterInfo());
20241 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
20242 unsigned SP = RegInfo->getStackRegister();
20244 MachineInstrBuilder MIB;
20246 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20247 const int64_t SPOffset = 2 * PVT.getStoreSize();
20249 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
20250 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
20253 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
20254 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
20255 MIB.addOperand(MI->getOperand(i));
20256 MIB.setMemRefs(MMOBegin, MMOEnd);
20258 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
20259 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20260 if (i == X86::AddrDisp)
20261 MIB.addDisp(MI->getOperand(i), LabelOffset);
20263 MIB.addOperand(MI->getOperand(i));
20265 MIB.setMemRefs(MMOBegin, MMOEnd);
20267 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
20268 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20269 if (i == X86::AddrDisp)
20270 MIB.addDisp(MI->getOperand(i), SPOffset);
20272 MIB.addOperand(MI->getOperand(i));
20274 MIB.setMemRefs(MMOBegin, MMOEnd);
20276 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
20278 MI->eraseFromParent();
20282 // Replace 213-type (isel default) FMA3 instructions with 231-type for
20283 // accumulator loops. Writing back to the accumulator allows the coalescer
20284 // to remove extra copies in the loop.
20285 MachineBasicBlock *
20286 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
20287 MachineBasicBlock *MBB) const {
20288 MachineOperand &AddendOp = MI->getOperand(3);
20290 // Bail out early if the addend isn't a register - we can't switch these.
20291 if (!AddendOp.isReg())
20294 MachineFunction &MF = *MBB->getParent();
20295 MachineRegisterInfo &MRI = MF.getRegInfo();
20297 // Check whether the addend is defined by a PHI:
20298 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
20299 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
20300 if (!AddendDef.isPHI())
20303 // Look for the following pattern:
20305 // %addend = phi [%entry, 0], [%loop, %result]
20307 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
20311 // %addend = phi [%entry, 0], [%loop, %result]
20313 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
20315 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
20316 assert(AddendDef.getOperand(i).isReg());
20317 MachineOperand PHISrcOp = AddendDef.getOperand(i);
20318 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
20319 if (&PHISrcInst == MI) {
20320 // Found a matching instruction.
20321 unsigned NewFMAOpc = 0;
20322 switch (MI->getOpcode()) {
20323 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
20324 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
20325 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
20326 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
20327 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
20328 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
20329 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
20330 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
20331 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
20332 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
20333 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
20334 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
20335 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
20336 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
20337 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
20338 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
20339 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
20340 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
20341 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
20342 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
20343 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
20344 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
20345 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
20346 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
20347 default: llvm_unreachable("Unrecognized FMA variant.");
20350 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
20351 MachineInstrBuilder MIB =
20352 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
20353 .addOperand(MI->getOperand(0))
20354 .addOperand(MI->getOperand(3))
20355 .addOperand(MI->getOperand(2))
20356 .addOperand(MI->getOperand(1));
20357 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
20358 MI->eraseFromParent();
20365 MachineBasicBlock *
20366 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
20367 MachineBasicBlock *BB) const {
20368 switch (MI->getOpcode()) {
20369 default: llvm_unreachable("Unexpected instr type to insert");
20370 case X86::TAILJMPd64:
20371 case X86::TAILJMPr64:
20372 case X86::TAILJMPm64:
20373 llvm_unreachable("TAILJMP64 would not be touched here.");
20374 case X86::TCRETURNdi64:
20375 case X86::TCRETURNri64:
20376 case X86::TCRETURNmi64:
20378 case X86::WIN_ALLOCA:
20379 return EmitLoweredWinAlloca(MI, BB);
20380 case X86::SEG_ALLOCA_32:
20381 case X86::SEG_ALLOCA_64:
20382 return EmitLoweredSegAlloca(MI, BB);
20383 case X86::TLSCall_32:
20384 case X86::TLSCall_64:
20385 return EmitLoweredTLSCall(MI, BB);
20386 case X86::CMOV_GR8:
20387 case X86::CMOV_FR32:
20388 case X86::CMOV_FR64:
20389 case X86::CMOV_V4F32:
20390 case X86::CMOV_V2F64:
20391 case X86::CMOV_V2I64:
20392 case X86::CMOV_V8F32:
20393 case X86::CMOV_V4F64:
20394 case X86::CMOV_V4I64:
20395 case X86::CMOV_V16F32:
20396 case X86::CMOV_V8F64:
20397 case X86::CMOV_V8I64:
20398 case X86::CMOV_GR16:
20399 case X86::CMOV_GR32:
20400 case X86::CMOV_RFP32:
20401 case X86::CMOV_RFP64:
20402 case X86::CMOV_RFP80:
20403 return EmitLoweredSelect(MI, BB);
20405 case X86::FP32_TO_INT16_IN_MEM:
20406 case X86::FP32_TO_INT32_IN_MEM:
20407 case X86::FP32_TO_INT64_IN_MEM:
20408 case X86::FP64_TO_INT16_IN_MEM:
20409 case X86::FP64_TO_INT32_IN_MEM:
20410 case X86::FP64_TO_INT64_IN_MEM:
20411 case X86::FP80_TO_INT16_IN_MEM:
20412 case X86::FP80_TO_INT32_IN_MEM:
20413 case X86::FP80_TO_INT64_IN_MEM: {
20414 MachineFunction *F = BB->getParent();
20415 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
20416 DebugLoc DL = MI->getDebugLoc();
20418 // Change the floating point control register to use "round towards zero"
20419 // mode when truncating to an integer value.
20420 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
20421 addFrameReference(BuildMI(*BB, MI, DL,
20422 TII->get(X86::FNSTCW16m)), CWFrameIdx);
20424 // Load the old value of the high byte of the control word...
20426 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
20427 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
20430 // Set the high part to be round to zero...
20431 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
20434 // Reload the modified control word now...
20435 addFrameReference(BuildMI(*BB, MI, DL,
20436 TII->get(X86::FLDCW16m)), CWFrameIdx);
20438 // Restore the memory image of control word to original value
20439 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
20442 // Get the X86 opcode to use.
20444 switch (MI->getOpcode()) {
20445 default: llvm_unreachable("illegal opcode!");
20446 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
20447 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
20448 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
20449 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
20450 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
20451 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
20452 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
20453 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
20454 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
20458 MachineOperand &Op = MI->getOperand(0);
20460 AM.BaseType = X86AddressMode::RegBase;
20461 AM.Base.Reg = Op.getReg();
20463 AM.BaseType = X86AddressMode::FrameIndexBase;
20464 AM.Base.FrameIndex = Op.getIndex();
20466 Op = MI->getOperand(1);
20468 AM.Scale = Op.getImm();
20469 Op = MI->getOperand(2);
20471 AM.IndexReg = Op.getImm();
20472 Op = MI->getOperand(3);
20473 if (Op.isGlobal()) {
20474 AM.GV = Op.getGlobal();
20476 AM.Disp = Op.getImm();
20478 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
20479 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
20481 // Reload the original control word now.
20482 addFrameReference(BuildMI(*BB, MI, DL,
20483 TII->get(X86::FLDCW16m)), CWFrameIdx);
20485 MI->eraseFromParent(); // The pseudo instruction is gone now.
20488 // String/text processing lowering.
20489 case X86::PCMPISTRM128REG:
20490 case X86::VPCMPISTRM128REG:
20491 case X86::PCMPISTRM128MEM:
20492 case X86::VPCMPISTRM128MEM:
20493 case X86::PCMPESTRM128REG:
20494 case X86::VPCMPESTRM128REG:
20495 case X86::PCMPESTRM128MEM:
20496 case X86::VPCMPESTRM128MEM:
20497 assert(Subtarget->hasSSE42() &&
20498 "Target must have SSE4.2 or AVX features enabled");
20499 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20501 // String/text processing lowering.
20502 case X86::PCMPISTRIREG:
20503 case X86::VPCMPISTRIREG:
20504 case X86::PCMPISTRIMEM:
20505 case X86::VPCMPISTRIMEM:
20506 case X86::PCMPESTRIREG:
20507 case X86::VPCMPESTRIREG:
20508 case X86::PCMPESTRIMEM:
20509 case X86::VPCMPESTRIMEM:
20510 assert(Subtarget->hasSSE42() &&
20511 "Target must have SSE4.2 or AVX features enabled");
20512 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20514 // Thread synchronization.
20516 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
20521 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
20523 case X86::VASTART_SAVE_XMM_REGS:
20524 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
20526 case X86::VAARG_64:
20527 return EmitVAARG64WithCustomInserter(MI, BB);
20529 case X86::EH_SjLj_SetJmp32:
20530 case X86::EH_SjLj_SetJmp64:
20531 return emitEHSjLjSetJmp(MI, BB);
20533 case X86::EH_SjLj_LongJmp32:
20534 case X86::EH_SjLj_LongJmp64:
20535 return emitEHSjLjLongJmp(MI, BB);
20537 case TargetOpcode::STACKMAP:
20538 case TargetOpcode::PATCHPOINT:
20539 return emitPatchPoint(MI, BB);
20541 case X86::VFMADDPDr213r:
20542 case X86::VFMADDPSr213r:
20543 case X86::VFMADDSDr213r:
20544 case X86::VFMADDSSr213r:
20545 case X86::VFMSUBPDr213r:
20546 case X86::VFMSUBPSr213r:
20547 case X86::VFMSUBSDr213r:
20548 case X86::VFMSUBSSr213r:
20549 case X86::VFNMADDPDr213r:
20550 case X86::VFNMADDPSr213r:
20551 case X86::VFNMADDSDr213r:
20552 case X86::VFNMADDSSr213r:
20553 case X86::VFNMSUBPDr213r:
20554 case X86::VFNMSUBPSr213r:
20555 case X86::VFNMSUBSDr213r:
20556 case X86::VFNMSUBSSr213r:
20557 case X86::VFMADDPDr213rY:
20558 case X86::VFMADDPSr213rY:
20559 case X86::VFMSUBPDr213rY:
20560 case X86::VFMSUBPSr213rY:
20561 case X86::VFNMADDPDr213rY:
20562 case X86::VFNMADDPSr213rY:
20563 case X86::VFNMSUBPDr213rY:
20564 case X86::VFNMSUBPSr213rY:
20565 return emitFMA3Instr(MI, BB);
20569 //===----------------------------------------------------------------------===//
20570 // X86 Optimization Hooks
20571 //===----------------------------------------------------------------------===//
20573 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
20576 const SelectionDAG &DAG,
20577 unsigned Depth) const {
20578 unsigned BitWidth = KnownZero.getBitWidth();
20579 unsigned Opc = Op.getOpcode();
20580 assert((Opc >= ISD::BUILTIN_OP_END ||
20581 Opc == ISD::INTRINSIC_WO_CHAIN ||
20582 Opc == ISD::INTRINSIC_W_CHAIN ||
20583 Opc == ISD::INTRINSIC_VOID) &&
20584 "Should use MaskedValueIsZero if you don't know whether Op"
20585 " is a target node!");
20587 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
20601 // These nodes' second result is a boolean.
20602 if (Op.getResNo() == 0)
20605 case X86ISD::SETCC:
20606 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
20608 case ISD::INTRINSIC_WO_CHAIN: {
20609 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
20610 unsigned NumLoBits = 0;
20613 case Intrinsic::x86_sse_movmsk_ps:
20614 case Intrinsic::x86_avx_movmsk_ps_256:
20615 case Intrinsic::x86_sse2_movmsk_pd:
20616 case Intrinsic::x86_avx_movmsk_pd_256:
20617 case Intrinsic::x86_mmx_pmovmskb:
20618 case Intrinsic::x86_sse2_pmovmskb_128:
20619 case Intrinsic::x86_avx2_pmovmskb: {
20620 // High bits of movmskp{s|d}, pmovmskb are known zero.
20622 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
20623 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
20624 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
20625 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
20626 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
20627 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
20628 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
20629 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
20631 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
20640 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
20642 const SelectionDAG &,
20643 unsigned Depth) const {
20644 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
20645 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
20646 return Op.getValueType().getScalarType().getSizeInBits();
20652 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
20653 /// node is a GlobalAddress + offset.
20654 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
20655 const GlobalValue* &GA,
20656 int64_t &Offset) const {
20657 if (N->getOpcode() == X86ISD::Wrapper) {
20658 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
20659 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
20660 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
20664 return TargetLowering::isGAPlusOffset(N, GA, Offset);
20667 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
20668 /// same as extracting the high 128-bit part of 256-bit vector and then
20669 /// inserting the result into the low part of a new 256-bit vector
20670 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
20671 EVT VT = SVOp->getValueType(0);
20672 unsigned NumElems = VT.getVectorNumElements();
20674 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20675 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
20676 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20677 SVOp->getMaskElt(j) >= 0)
20683 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
20684 /// same as extracting the low 128-bit part of 256-bit vector and then
20685 /// inserting the result into the high part of a new 256-bit vector
20686 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
20687 EVT VT = SVOp->getValueType(0);
20688 unsigned NumElems = VT.getVectorNumElements();
20690 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20691 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
20692 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20693 SVOp->getMaskElt(j) >= 0)
20699 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
20700 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
20701 TargetLowering::DAGCombinerInfo &DCI,
20702 const X86Subtarget* Subtarget) {
20704 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20705 SDValue V1 = SVOp->getOperand(0);
20706 SDValue V2 = SVOp->getOperand(1);
20707 EVT VT = SVOp->getValueType(0);
20708 unsigned NumElems = VT.getVectorNumElements();
20710 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
20711 V2.getOpcode() == ISD::CONCAT_VECTORS) {
20715 // V UNDEF BUILD_VECTOR UNDEF
20717 // CONCAT_VECTOR CONCAT_VECTOR
20720 // RESULT: V + zero extended
20722 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
20723 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
20724 V1.getOperand(1).getOpcode() != ISD::UNDEF)
20727 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
20730 // To match the shuffle mask, the first half of the mask should
20731 // be exactly the first vector, and all the rest a splat with the
20732 // first element of the second one.
20733 for (unsigned i = 0; i != NumElems/2; ++i)
20734 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
20735 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
20738 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
20739 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
20740 if (Ld->hasNUsesOfValue(1, 0)) {
20741 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
20742 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
20744 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
20746 Ld->getPointerInfo(),
20747 Ld->getAlignment(),
20748 false/*isVolatile*/, true/*ReadMem*/,
20749 false/*WriteMem*/);
20751 // Make sure the newly-created LOAD is in the same position as Ld in
20752 // terms of dependency. We create a TokenFactor for Ld and ResNode,
20753 // and update uses of Ld's output chain to use the TokenFactor.
20754 if (Ld->hasAnyUseOfValue(1)) {
20755 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
20756 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
20757 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
20758 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
20759 SDValue(ResNode.getNode(), 1));
20762 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
20766 // Emit a zeroed vector and insert the desired subvector on its
20768 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
20769 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
20770 return DCI.CombineTo(N, InsV);
20773 //===--------------------------------------------------------------------===//
20774 // Combine some shuffles into subvector extracts and inserts:
20777 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20778 if (isShuffleHigh128VectorInsertLow(SVOp)) {
20779 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
20780 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
20781 return DCI.CombineTo(N, InsV);
20784 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20785 if (isShuffleLow128VectorInsertHigh(SVOp)) {
20786 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
20787 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
20788 return DCI.CombineTo(N, InsV);
20794 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
20797 /// This is the leaf of the recursive combinine below. When we have found some
20798 /// chain of single-use x86 shuffle instructions and accumulated the combined
20799 /// shuffle mask represented by them, this will try to pattern match that mask
20800 /// into either a single instruction if there is a special purpose instruction
20801 /// for this operation, or into a PSHUFB instruction which is a fully general
20802 /// instruction but should only be used to replace chains over a certain depth.
20803 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
20804 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
20805 TargetLowering::DAGCombinerInfo &DCI,
20806 const X86Subtarget *Subtarget) {
20807 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
20809 // Find the operand that enters the chain. Note that multiple uses are OK
20810 // here, we're not going to remove the operand we find.
20811 SDValue Input = Op.getOperand(0);
20812 while (Input.getOpcode() == ISD::BITCAST)
20813 Input = Input.getOperand(0);
20815 MVT VT = Input.getSimpleValueType();
20816 MVT RootVT = Root.getSimpleValueType();
20819 // Just remove no-op shuffle masks.
20820 if (Mask.size() == 1) {
20821 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
20826 // Use the float domain if the operand type is a floating point type.
20827 bool FloatDomain = VT.isFloatingPoint();
20829 // For floating point shuffles, we don't have free copies in the shuffle
20830 // instructions or the ability to load as part of the instruction, so
20831 // canonicalize their shuffles to UNPCK or MOV variants.
20833 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
20834 // vectors because it can have a load folded into it that UNPCK cannot. This
20835 // doesn't preclude something switching to the shorter encoding post-RA.
20837 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
20838 bool Lo = Mask.equals(0, 0);
20841 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
20842 // is no slower than UNPCKLPD but has the option to fold the input operand
20843 // into even an unaligned memory load.
20844 if (Lo && Subtarget->hasSSE3()) {
20845 Shuffle = X86ISD::MOVDDUP;
20846 ShuffleVT = MVT::v2f64;
20848 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
20849 // than the UNPCK variants.
20850 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
20851 ShuffleVT = MVT::v4f32;
20853 if (Depth == 1 && Root->getOpcode() == Shuffle)
20854 return false; // Nothing to do!
20855 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20856 DCI.AddToWorklist(Op.getNode());
20857 if (Shuffle == X86ISD::MOVDDUP)
20858 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20860 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20861 DCI.AddToWorklist(Op.getNode());
20862 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20866 if (Subtarget->hasSSE3() &&
20867 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
20868 bool Lo = Mask.equals(0, 0, 2, 2);
20869 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
20870 MVT ShuffleVT = MVT::v4f32;
20871 if (Depth == 1 && Root->getOpcode() == Shuffle)
20872 return false; // Nothing to do!
20873 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20874 DCI.AddToWorklist(Op.getNode());
20875 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20876 DCI.AddToWorklist(Op.getNode());
20877 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20881 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
20882 bool Lo = Mask.equals(0, 0, 1, 1);
20883 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20884 MVT ShuffleVT = MVT::v4f32;
20885 if (Depth == 1 && Root->getOpcode() == Shuffle)
20886 return false; // Nothing to do!
20887 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20888 DCI.AddToWorklist(Op.getNode());
20889 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20890 DCI.AddToWorklist(Op.getNode());
20891 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20897 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
20898 // variants as none of these have single-instruction variants that are
20899 // superior to the UNPCK formulation.
20900 if (!FloatDomain &&
20901 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
20902 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
20903 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
20904 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
20906 bool Lo = Mask[0] == 0;
20907 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20908 if (Depth == 1 && Root->getOpcode() == Shuffle)
20909 return false; // Nothing to do!
20911 switch (Mask.size()) {
20913 ShuffleVT = MVT::v8i16;
20916 ShuffleVT = MVT::v16i8;
20919 llvm_unreachable("Impossible mask size!");
20921 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
20922 DCI.AddToWorklist(Op.getNode());
20923 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20924 DCI.AddToWorklist(Op.getNode());
20925 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20930 // Don't try to re-form single instruction chains under any circumstances now
20931 // that we've done encoding canonicalization for them.
20935 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
20936 // can replace them with a single PSHUFB instruction profitably. Intel's
20937 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
20938 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
20939 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
20940 SmallVector<SDValue, 16> PSHUFBMask;
20941 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
20942 int Ratio = 16 / Mask.size();
20943 for (unsigned i = 0; i < 16; ++i) {
20944 if (Mask[i / Ratio] == SM_SentinelUndef) {
20945 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
20948 int M = Mask[i / Ratio] != SM_SentinelZero
20949 ? Ratio * Mask[i / Ratio] + i % Ratio
20951 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
20953 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
20954 DCI.AddToWorklist(Op.getNode());
20955 SDValue PSHUFBMaskOp =
20956 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
20957 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
20958 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
20959 DCI.AddToWorklist(Op.getNode());
20960 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
20965 // Failed to find any combines.
20969 /// \brief Fully generic combining of x86 shuffle instructions.
20971 /// This should be the last combine run over the x86 shuffle instructions. Once
20972 /// they have been fully optimized, this will recursively consider all chains
20973 /// of single-use shuffle instructions, build a generic model of the cumulative
20974 /// shuffle operation, and check for simpler instructions which implement this
20975 /// operation. We use this primarily for two purposes:
20977 /// 1) Collapse generic shuffles to specialized single instructions when
20978 /// equivalent. In most cases, this is just an encoding size win, but
20979 /// sometimes we will collapse multiple generic shuffles into a single
20980 /// special-purpose shuffle.
20981 /// 2) Look for sequences of shuffle instructions with 3 or more total
20982 /// instructions, and replace them with the slightly more expensive SSSE3
20983 /// PSHUFB instruction if available. We do this as the last combining step
20984 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
20985 /// a suitable short sequence of other instructions. The PHUFB will either
20986 /// use a register or have to read from memory and so is slightly (but only
20987 /// slightly) more expensive than the other shuffle instructions.
20989 /// Because this is inherently a quadratic operation (for each shuffle in
20990 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
20991 /// This should never be an issue in practice as the shuffle lowering doesn't
20992 /// produce sequences of more than 8 instructions.
20994 /// FIXME: We will currently miss some cases where the redundant shuffling
20995 /// would simplify under the threshold for PSHUFB formation because of
20996 /// combine-ordering. To fix this, we should do the redundant instruction
20997 /// combining in this recursive walk.
20998 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
20999 ArrayRef<int> RootMask,
21000 int Depth, bool HasPSHUFB,
21002 TargetLowering::DAGCombinerInfo &DCI,
21003 const X86Subtarget *Subtarget) {
21004 // Bound the depth of our recursive combine because this is ultimately
21005 // quadratic in nature.
21009 // Directly rip through bitcasts to find the underlying operand.
21010 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
21011 Op = Op.getOperand(0);
21013 MVT VT = Op.getSimpleValueType();
21014 if (!VT.isVector())
21015 return false; // Bail if we hit a non-vector.
21016 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
21017 // version should be added.
21018 if (VT.getSizeInBits() != 128)
21021 assert(Root.getSimpleValueType().isVector() &&
21022 "Shuffles operate on vector types!");
21023 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
21024 "Can only combine shuffles of the same vector register size.");
21026 if (!isTargetShuffle(Op.getOpcode()))
21028 SmallVector<int, 16> OpMask;
21030 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
21031 // We only can combine unary shuffles which we can decode the mask for.
21032 if (!HaveMask || !IsUnary)
21035 assert(VT.getVectorNumElements() == OpMask.size() &&
21036 "Different mask size from vector size!");
21037 assert(((RootMask.size() > OpMask.size() &&
21038 RootMask.size() % OpMask.size() == 0) ||
21039 (OpMask.size() > RootMask.size() &&
21040 OpMask.size() % RootMask.size() == 0) ||
21041 OpMask.size() == RootMask.size()) &&
21042 "The smaller number of elements must divide the larger.");
21043 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
21044 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
21045 assert(((RootRatio == 1 && OpRatio == 1) ||
21046 (RootRatio == 1) != (OpRatio == 1)) &&
21047 "Must not have a ratio for both incoming and op masks!");
21049 SmallVector<int, 16> Mask;
21050 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
21052 // Merge this shuffle operation's mask into our accumulated mask. Note that
21053 // this shuffle's mask will be the first applied to the input, followed by the
21054 // root mask to get us all the way to the root value arrangement. The reason
21055 // for this order is that we are recursing up the operation chain.
21056 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
21057 int RootIdx = i / RootRatio;
21058 if (RootMask[RootIdx] < 0) {
21059 // This is a zero or undef lane, we're done.
21060 Mask.push_back(RootMask[RootIdx]);
21064 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
21065 int OpIdx = RootMaskedIdx / OpRatio;
21066 if (OpMask[OpIdx] < 0) {
21067 // The incoming lanes are zero or undef, it doesn't matter which ones we
21069 Mask.push_back(OpMask[OpIdx]);
21073 // Ok, we have non-zero lanes, map them through.
21074 Mask.push_back(OpMask[OpIdx] * OpRatio +
21075 RootMaskedIdx % OpRatio);
21078 // See if we can recurse into the operand to combine more things.
21079 switch (Op.getOpcode()) {
21080 case X86ISD::PSHUFB:
21082 case X86ISD::PSHUFD:
21083 case X86ISD::PSHUFHW:
21084 case X86ISD::PSHUFLW:
21085 if (Op.getOperand(0).hasOneUse() &&
21086 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21087 HasPSHUFB, DAG, DCI, Subtarget))
21091 case X86ISD::UNPCKL:
21092 case X86ISD::UNPCKH:
21093 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
21094 // We can't check for single use, we have to check that this shuffle is the only user.
21095 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
21096 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21097 HasPSHUFB, DAG, DCI, Subtarget))
21102 // Minor canonicalization of the accumulated shuffle mask to make it easier
21103 // to match below. All this does is detect masks with squential pairs of
21104 // elements, and shrink them to the half-width mask. It does this in a loop
21105 // so it will reduce the size of the mask to the minimal width mask which
21106 // performs an equivalent shuffle.
21107 SmallVector<int, 16> WidenedMask;
21108 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
21109 Mask = std::move(WidenedMask);
21110 WidenedMask.clear();
21113 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
21117 /// \brief Get the PSHUF-style mask from PSHUF node.
21119 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
21120 /// PSHUF-style masks that can be reused with such instructions.
21121 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
21122 SmallVector<int, 4> Mask;
21124 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
21128 switch (N.getOpcode()) {
21129 case X86ISD::PSHUFD:
21131 case X86ISD::PSHUFLW:
21134 case X86ISD::PSHUFHW:
21135 Mask.erase(Mask.begin(), Mask.begin() + 4);
21136 for (int &M : Mask)
21140 llvm_unreachable("No valid shuffle instruction found!");
21144 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
21146 /// We walk up the chain and look for a combinable shuffle, skipping over
21147 /// shuffles that we could hoist this shuffle's transformation past without
21148 /// altering anything.
21150 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
21152 TargetLowering::DAGCombinerInfo &DCI) {
21153 assert(N.getOpcode() == X86ISD::PSHUFD &&
21154 "Called with something other than an x86 128-bit half shuffle!");
21157 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
21158 // of the shuffles in the chain so that we can form a fresh chain to replace
21160 SmallVector<SDValue, 8> Chain;
21161 SDValue V = N.getOperand(0);
21162 for (; V.hasOneUse(); V = V.getOperand(0)) {
21163 switch (V.getOpcode()) {
21165 return SDValue(); // Nothing combined!
21168 // Skip bitcasts as we always know the type for the target specific
21172 case X86ISD::PSHUFD:
21173 // Found another dword shuffle.
21176 case X86ISD::PSHUFLW:
21177 // Check that the low words (being shuffled) are the identity in the
21178 // dword shuffle, and the high words are self-contained.
21179 if (Mask[0] != 0 || Mask[1] != 1 ||
21180 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
21183 Chain.push_back(V);
21186 case X86ISD::PSHUFHW:
21187 // Check that the high words (being shuffled) are the identity in the
21188 // dword shuffle, and the low words are self-contained.
21189 if (Mask[2] != 2 || Mask[3] != 3 ||
21190 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
21193 Chain.push_back(V);
21196 case X86ISD::UNPCKL:
21197 case X86ISD::UNPCKH:
21198 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
21199 // shuffle into a preceding word shuffle.
21200 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
21203 // Search for a half-shuffle which we can combine with.
21204 unsigned CombineOp =
21205 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
21206 if (V.getOperand(0) != V.getOperand(1) ||
21207 !V->isOnlyUserOf(V.getOperand(0).getNode()))
21209 Chain.push_back(V);
21210 V = V.getOperand(0);
21212 switch (V.getOpcode()) {
21214 return SDValue(); // Nothing to combine.
21216 case X86ISD::PSHUFLW:
21217 case X86ISD::PSHUFHW:
21218 if (V.getOpcode() == CombineOp)
21221 Chain.push_back(V);
21225 V = V.getOperand(0);
21229 } while (V.hasOneUse());
21232 // Break out of the loop if we break out of the switch.
21236 if (!V.hasOneUse())
21237 // We fell out of the loop without finding a viable combining instruction.
21240 // Merge this node's mask and our incoming mask.
21241 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21242 for (int &M : Mask)
21244 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
21245 getV4X86ShuffleImm8ForMask(Mask, DAG));
21247 // Rebuild the chain around this new shuffle.
21248 while (!Chain.empty()) {
21249 SDValue W = Chain.pop_back_val();
21251 if (V.getValueType() != W.getOperand(0).getValueType())
21252 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
21254 switch (W.getOpcode()) {
21256 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
21258 case X86ISD::UNPCKL:
21259 case X86ISD::UNPCKH:
21260 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
21263 case X86ISD::PSHUFD:
21264 case X86ISD::PSHUFLW:
21265 case X86ISD::PSHUFHW:
21266 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
21270 if (V.getValueType() != N.getValueType())
21271 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
21273 // Return the new chain to replace N.
21277 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
21279 /// We walk up the chain, skipping shuffles of the other half and looking
21280 /// through shuffles which switch halves trying to find a shuffle of the same
21281 /// pair of dwords.
21282 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
21284 TargetLowering::DAGCombinerInfo &DCI) {
21286 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
21287 "Called with something other than an x86 128-bit half shuffle!");
21289 unsigned CombineOpcode = N.getOpcode();
21291 // Walk up a single-use chain looking for a combinable shuffle.
21292 SDValue V = N.getOperand(0);
21293 for (; V.hasOneUse(); V = V.getOperand(0)) {
21294 switch (V.getOpcode()) {
21296 return false; // Nothing combined!
21299 // Skip bitcasts as we always know the type for the target specific
21303 case X86ISD::PSHUFLW:
21304 case X86ISD::PSHUFHW:
21305 if (V.getOpcode() == CombineOpcode)
21308 // Other-half shuffles are no-ops.
21311 // Break out of the loop if we break out of the switch.
21315 if (!V.hasOneUse())
21316 // We fell out of the loop without finding a viable combining instruction.
21319 // Combine away the bottom node as its shuffle will be accumulated into
21320 // a preceding shuffle.
21321 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21323 // Record the old value.
21326 // Merge this node's mask and our incoming mask (adjusted to account for all
21327 // the pshufd instructions encountered).
21328 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21329 for (int &M : Mask)
21331 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
21332 getV4X86ShuffleImm8ForMask(Mask, DAG));
21334 // Check that the shuffles didn't cancel each other out. If not, we need to
21335 // combine to the new one.
21337 // Replace the combinable shuffle with the combined one, updating all users
21338 // so that we re-evaluate the chain here.
21339 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
21344 /// \brief Try to combine x86 target specific shuffles.
21345 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
21346 TargetLowering::DAGCombinerInfo &DCI,
21347 const X86Subtarget *Subtarget) {
21349 MVT VT = N.getSimpleValueType();
21350 SmallVector<int, 4> Mask;
21352 switch (N.getOpcode()) {
21353 case X86ISD::PSHUFD:
21354 case X86ISD::PSHUFLW:
21355 case X86ISD::PSHUFHW:
21356 Mask = getPSHUFShuffleMask(N);
21357 assert(Mask.size() == 4);
21363 // Nuke no-op shuffles that show up after combining.
21364 if (isNoopShuffleMask(Mask))
21365 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21367 // Look for simplifications involving one or two shuffle instructions.
21368 SDValue V = N.getOperand(0);
21369 switch (N.getOpcode()) {
21372 case X86ISD::PSHUFLW:
21373 case X86ISD::PSHUFHW:
21374 assert(VT == MVT::v8i16);
21377 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
21378 return SDValue(); // We combined away this shuffle, so we're done.
21380 // See if this reduces to a PSHUFD which is no more expensive and can
21381 // combine with more operations. Note that it has to at least flip the
21382 // dwords as otherwise it would have been removed as a no-op.
21383 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
21384 int DMask[] = {0, 1, 2, 3};
21385 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
21386 DMask[DOffset + 0] = DOffset + 1;
21387 DMask[DOffset + 1] = DOffset + 0;
21388 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
21389 DCI.AddToWorklist(V.getNode());
21390 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
21391 getV4X86ShuffleImm8ForMask(DMask, DAG));
21392 DCI.AddToWorklist(V.getNode());
21393 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
21396 // Look for shuffle patterns which can be implemented as a single unpack.
21397 // FIXME: This doesn't handle the location of the PSHUFD generically, and
21398 // only works when we have a PSHUFD followed by two half-shuffles.
21399 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
21400 (V.getOpcode() == X86ISD::PSHUFLW ||
21401 V.getOpcode() == X86ISD::PSHUFHW) &&
21402 V.getOpcode() != N.getOpcode() &&
21404 SDValue D = V.getOperand(0);
21405 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
21406 D = D.getOperand(0);
21407 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
21408 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21409 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
21410 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21411 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21413 for (int i = 0; i < 4; ++i) {
21414 WordMask[i + NOffset] = Mask[i] + NOffset;
21415 WordMask[i + VOffset] = VMask[i] + VOffset;
21417 // Map the word mask through the DWord mask.
21419 for (int i = 0; i < 8; ++i)
21420 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
21421 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
21422 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
21423 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
21424 std::begin(UnpackLoMask)) ||
21425 std::equal(std::begin(MappedMask), std::end(MappedMask),
21426 std::begin(UnpackHiMask))) {
21427 // We can replace all three shuffles with an unpack.
21428 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
21429 DCI.AddToWorklist(V.getNode());
21430 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
21432 DL, MVT::v8i16, V, V);
21439 case X86ISD::PSHUFD:
21440 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
21449 /// \brief Try to combine a shuffle into a target-specific add-sub node.
21451 /// We combine this directly on the abstract vector shuffle nodes so it is
21452 /// easier to generically match. We also insert dummy vector shuffle nodes for
21453 /// the operands which explicitly discard the lanes which are unused by this
21454 /// operation to try to flow through the rest of the combiner the fact that
21455 /// they're unused.
21456 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
21458 EVT VT = N->getValueType(0);
21460 // We only handle target-independent shuffles.
21461 // FIXME: It would be easy and harmless to use the target shuffle mask
21462 // extraction tool to support more.
21463 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
21466 auto *SVN = cast<ShuffleVectorSDNode>(N);
21467 ArrayRef<int> Mask = SVN->getMask();
21468 SDValue V1 = N->getOperand(0);
21469 SDValue V2 = N->getOperand(1);
21471 // We require the first shuffle operand to be the SUB node, and the second to
21472 // be the ADD node.
21473 // FIXME: We should support the commuted patterns.
21474 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
21477 // If there are other uses of these operations we can't fold them.
21478 if (!V1->hasOneUse() || !V2->hasOneUse())
21481 // Ensure that both operations have the same operands. Note that we can
21482 // commute the FADD operands.
21483 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
21484 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
21485 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
21488 // We're looking for blends between FADD and FSUB nodes. We insist on these
21489 // nodes being lined up in a specific expected pattern.
21490 if (!(isShuffleEquivalent(Mask, 0, 3) ||
21491 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
21492 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
21495 // Only specific types are legal at this point, assert so we notice if and
21496 // when these change.
21497 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
21498 VT == MVT::v4f64) &&
21499 "Unknown vector type encountered!");
21501 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
21504 /// PerformShuffleCombine - Performs several different shuffle combines.
21505 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
21506 TargetLowering::DAGCombinerInfo &DCI,
21507 const X86Subtarget *Subtarget) {
21509 SDValue N0 = N->getOperand(0);
21510 SDValue N1 = N->getOperand(1);
21511 EVT VT = N->getValueType(0);
21513 // Don't create instructions with illegal types after legalize types has run.
21514 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21515 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
21518 // If we have legalized the vector types, look for blends of FADD and FSUB
21519 // nodes that we can fuse into an ADDSUB node.
21520 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
21521 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
21524 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
21525 if (Subtarget->hasFp256() && VT.is256BitVector() &&
21526 N->getOpcode() == ISD::VECTOR_SHUFFLE)
21527 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
21529 // During Type Legalization, when promoting illegal vector types,
21530 // the backend might introduce new shuffle dag nodes and bitcasts.
21532 // This code performs the following transformation:
21533 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
21534 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
21536 // We do this only if both the bitcast and the BINOP dag nodes have
21537 // one use. Also, perform this transformation only if the new binary
21538 // operation is legal. This is to avoid introducing dag nodes that
21539 // potentially need to be further expanded (or custom lowered) into a
21540 // less optimal sequence of dag nodes.
21541 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
21542 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
21543 N0.getOpcode() == ISD::BITCAST) {
21544 SDValue BC0 = N0.getOperand(0);
21545 EVT SVT = BC0.getValueType();
21546 unsigned Opcode = BC0.getOpcode();
21547 unsigned NumElts = VT.getVectorNumElements();
21549 if (BC0.hasOneUse() && SVT.isVector() &&
21550 SVT.getVectorNumElements() * 2 == NumElts &&
21551 TLI.isOperationLegal(Opcode, VT)) {
21552 bool CanFold = false;
21564 unsigned SVTNumElts = SVT.getVectorNumElements();
21565 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21566 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
21567 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
21568 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
21569 CanFold = SVOp->getMaskElt(i) < 0;
21572 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
21573 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
21574 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
21575 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
21580 // Only handle 128 wide vector from here on.
21581 if (!VT.is128BitVector())
21584 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
21585 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
21586 // consecutive, non-overlapping, and in the right order.
21587 SmallVector<SDValue, 16> Elts;
21588 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
21589 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
21591 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
21595 if (isTargetShuffle(N->getOpcode())) {
21597 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
21598 if (Shuffle.getNode())
21601 // Try recursively combining arbitrary sequences of x86 shuffle
21602 // instructions into higher-order shuffles. We do this after combining
21603 // specific PSHUF instruction sequences into their minimal form so that we
21604 // can evaluate how many specialized shuffle instructions are involved in
21605 // a particular chain.
21606 SmallVector<int, 1> NonceMask; // Just a placeholder.
21607 NonceMask.push_back(0);
21608 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
21609 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
21611 return SDValue(); // This routine will use CombineTo to replace N.
21617 /// PerformTruncateCombine - Converts truncate operation to
21618 /// a sequence of vector shuffle operations.
21619 /// It is possible when we truncate 256-bit vector to 128-bit vector
21620 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
21621 TargetLowering::DAGCombinerInfo &DCI,
21622 const X86Subtarget *Subtarget) {
21626 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
21627 /// specific shuffle of a load can be folded into a single element load.
21628 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
21629 /// shuffles have been customed lowered so we need to handle those here.
21630 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
21631 TargetLowering::DAGCombinerInfo &DCI) {
21632 if (DCI.isBeforeLegalizeOps())
21635 SDValue InVec = N->getOperand(0);
21636 SDValue EltNo = N->getOperand(1);
21638 if (!isa<ConstantSDNode>(EltNo))
21641 EVT VT = InVec.getValueType();
21643 if (InVec.getOpcode() == ISD::BITCAST) {
21644 // Don't duplicate a load with other uses.
21645 if (!InVec.hasOneUse())
21647 EVT BCVT = InVec.getOperand(0).getValueType();
21648 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
21650 InVec = InVec.getOperand(0);
21653 if (!isTargetShuffle(InVec.getOpcode()))
21656 // Don't duplicate a load with other uses.
21657 if (!InVec.hasOneUse())
21660 SmallVector<int, 16> ShuffleMask;
21662 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
21666 // Select the input vector, guarding against out of range extract vector.
21667 unsigned NumElems = VT.getVectorNumElements();
21668 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
21669 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
21670 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
21671 : InVec.getOperand(1);
21673 // If inputs to shuffle are the same for both ops, then allow 2 uses
21674 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
21676 if (LdNode.getOpcode() == ISD::BITCAST) {
21677 // Don't duplicate a load with other uses.
21678 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
21681 AllowedUses = 1; // only allow 1 load use if we have a bitcast
21682 LdNode = LdNode.getOperand(0);
21685 if (!ISD::isNormalLoad(LdNode.getNode()))
21688 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
21690 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
21693 EVT EltVT = N->getValueType(0);
21694 // If there's a bitcast before the shuffle, check if the load type and
21695 // alignment is valid.
21696 unsigned Align = LN0->getAlignment();
21697 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21698 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
21699 EltVT.getTypeForEVT(*DAG.getContext()));
21701 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
21704 // All checks match so transform back to vector_shuffle so that DAG combiner
21705 // can finish the job
21708 // Create shuffle node taking into account the case that its a unary shuffle
21709 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
21710 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
21711 InVec.getOperand(0), Shuffle,
21713 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
21714 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
21718 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
21719 /// generation and convert it from being a bunch of shuffles and extracts
21720 /// to a simple store and scalar loads to extract the elements.
21721 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
21722 TargetLowering::DAGCombinerInfo &DCI) {
21723 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
21724 if (NewOp.getNode())
21727 SDValue InputVector = N->getOperand(0);
21729 // Detect whether we are trying to convert from mmx to i32 and the bitcast
21730 // from mmx to v2i32 has a single usage.
21731 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
21732 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
21733 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
21734 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21735 N->getValueType(0),
21736 InputVector.getNode()->getOperand(0));
21738 // Only operate on vectors of 4 elements, where the alternative shuffling
21739 // gets to be more expensive.
21740 if (InputVector.getValueType() != MVT::v4i32)
21743 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
21744 // single use which is a sign-extend or zero-extend, and all elements are
21746 SmallVector<SDNode *, 4> Uses;
21747 unsigned ExtractedElements = 0;
21748 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
21749 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
21750 if (UI.getUse().getResNo() != InputVector.getResNo())
21753 SDNode *Extract = *UI;
21754 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
21757 if (Extract->getValueType(0) != MVT::i32)
21759 if (!Extract->hasOneUse())
21761 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
21762 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
21764 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
21767 // Record which element was extracted.
21768 ExtractedElements |=
21769 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
21771 Uses.push_back(Extract);
21774 // If not all the elements were used, this may not be worthwhile.
21775 if (ExtractedElements != 15)
21778 // Ok, we've now decided to do the transformation.
21779 SDLoc dl(InputVector);
21781 // Store the value to a temporary stack slot.
21782 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
21783 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
21784 MachinePointerInfo(), false, false, 0);
21786 // Replace each use (extract) with a load of the appropriate element.
21787 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
21788 UE = Uses.end(); UI != UE; ++UI) {
21789 SDNode *Extract = *UI;
21791 // cOMpute the element's address.
21792 SDValue Idx = Extract->getOperand(1);
21794 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
21795 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
21796 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21797 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
21799 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
21800 StackPtr, OffsetVal);
21802 // Load the scalar.
21803 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
21804 ScalarAddr, MachinePointerInfo(),
21805 false, false, false, 0);
21807 // Replace the exact with the load.
21808 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
21811 // The replacement was made in place; don't return anything.
21815 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
21816 static std::pair<unsigned, bool>
21817 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
21818 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
21819 if (!VT.isVector())
21820 return std::make_pair(0, false);
21822 bool NeedSplit = false;
21823 switch (VT.getSimpleVT().SimpleTy) {
21824 default: return std::make_pair(0, false);
21828 if (!Subtarget->hasAVX2())
21830 if (!Subtarget->hasAVX())
21831 return std::make_pair(0, false);
21836 if (!Subtarget->hasSSE2())
21837 return std::make_pair(0, false);
21840 // SSE2 has only a small subset of the operations.
21841 bool hasUnsigned = Subtarget->hasSSE41() ||
21842 (Subtarget->hasSSE2() && VT == MVT::v16i8);
21843 bool hasSigned = Subtarget->hasSSE41() ||
21844 (Subtarget->hasSSE2() && VT == MVT::v8i16);
21846 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21849 // Check for x CC y ? x : y.
21850 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21851 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21856 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21859 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21862 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21865 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21867 // Check for x CC y ? y : x -- a min/max with reversed arms.
21868 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21869 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21874 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
21877 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
21880 Opc = hasSigned ? X86ISD::SMAX : 0; break;
21883 Opc = hasSigned ? X86ISD::SMIN : 0; break;
21887 return std::make_pair(Opc, NeedSplit);
21891 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
21892 const X86Subtarget *Subtarget) {
21894 SDValue Cond = N->getOperand(0);
21895 SDValue LHS = N->getOperand(1);
21896 SDValue RHS = N->getOperand(2);
21898 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
21899 SDValue CondSrc = Cond->getOperand(0);
21900 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
21901 Cond = CondSrc->getOperand(0);
21904 MVT VT = N->getSimpleValueType(0);
21905 MVT EltVT = VT.getVectorElementType();
21906 unsigned NumElems = VT.getVectorNumElements();
21907 // There is no blend with immediate in AVX-512.
21908 if (VT.is512BitVector())
21911 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
21913 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
21916 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
21919 // A vselect where all conditions and data are constants can be optimized into
21920 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
21921 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
21922 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
21925 unsigned MaskValue = 0;
21926 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
21929 SmallVector<int, 8> ShuffleMask(NumElems, -1);
21930 for (unsigned i = 0; i < NumElems; ++i) {
21931 // Be sure we emit undef where we can.
21932 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
21933 ShuffleMask[i] = -1;
21935 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
21938 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
21941 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
21943 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
21944 TargetLowering::DAGCombinerInfo &DCI,
21945 const X86Subtarget *Subtarget) {
21947 SDValue Cond = N->getOperand(0);
21948 // Get the LHS/RHS of the select.
21949 SDValue LHS = N->getOperand(1);
21950 SDValue RHS = N->getOperand(2);
21951 EVT VT = LHS.getValueType();
21952 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21954 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
21955 // instructions match the semantics of the common C idiom x<y?x:y but not
21956 // x<=y?x:y, because of how they handle negative zero (which can be
21957 // ignored in unsafe-math mode).
21958 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
21959 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
21960 (Subtarget->hasSSE2() ||
21961 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
21962 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21964 unsigned Opcode = 0;
21965 // Check for x CC y ? x : y.
21966 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21967 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21971 // Converting this to a min would handle NaNs incorrectly, and swapping
21972 // the operands would cause it to handle comparisons between positive
21973 // and negative zero incorrectly.
21974 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21975 if (!DAG.getTarget().Options.UnsafeFPMath &&
21976 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21978 std::swap(LHS, RHS);
21980 Opcode = X86ISD::FMIN;
21983 // Converting this to a min would handle comparisons between positive
21984 // and negative zero incorrectly.
21985 if (!DAG.getTarget().Options.UnsafeFPMath &&
21986 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21988 Opcode = X86ISD::FMIN;
21991 // Converting this to a min would handle both negative zeros and NaNs
21992 // incorrectly, but we can swap the operands to fix both.
21993 std::swap(LHS, RHS);
21997 Opcode = X86ISD::FMIN;
22001 // Converting this to a max would handle comparisons between positive
22002 // and negative zero incorrectly.
22003 if (!DAG.getTarget().Options.UnsafeFPMath &&
22004 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22006 Opcode = X86ISD::FMAX;
22009 // Converting this to a max would handle NaNs incorrectly, and swapping
22010 // the operands would cause it to handle comparisons between positive
22011 // and negative zero incorrectly.
22012 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22013 if (!DAG.getTarget().Options.UnsafeFPMath &&
22014 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22016 std::swap(LHS, RHS);
22018 Opcode = X86ISD::FMAX;
22021 // Converting this to a max would handle both negative zeros and NaNs
22022 // incorrectly, but we can swap the operands to fix both.
22023 std::swap(LHS, RHS);
22027 Opcode = X86ISD::FMAX;
22030 // Check for x CC y ? y : x -- a min/max with reversed arms.
22031 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22032 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22036 // Converting this to a min would handle comparisons between positive
22037 // and negative zero incorrectly, and swapping the operands would
22038 // cause it to handle NaNs incorrectly.
22039 if (!DAG.getTarget().Options.UnsafeFPMath &&
22040 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
22041 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22043 std::swap(LHS, RHS);
22045 Opcode = X86ISD::FMIN;
22048 // Converting this to a min would handle NaNs incorrectly.
22049 if (!DAG.getTarget().Options.UnsafeFPMath &&
22050 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
22052 Opcode = X86ISD::FMIN;
22055 // Converting this to a min would handle both negative zeros and NaNs
22056 // incorrectly, but we can swap the operands to fix both.
22057 std::swap(LHS, RHS);
22061 Opcode = X86ISD::FMIN;
22065 // Converting this to a max would handle NaNs incorrectly.
22066 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22068 Opcode = X86ISD::FMAX;
22071 // Converting this to a max would handle comparisons between positive
22072 // and negative zero incorrectly, and swapping the operands would
22073 // cause it to handle NaNs incorrectly.
22074 if (!DAG.getTarget().Options.UnsafeFPMath &&
22075 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
22076 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22078 std::swap(LHS, RHS);
22080 Opcode = X86ISD::FMAX;
22083 // Converting this to a max would handle both negative zeros and NaNs
22084 // incorrectly, but we can swap the operands to fix both.
22085 std::swap(LHS, RHS);
22089 Opcode = X86ISD::FMAX;
22095 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
22098 EVT CondVT = Cond.getValueType();
22099 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
22100 CondVT.getVectorElementType() == MVT::i1) {
22101 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
22102 // lowering on KNL. In this case we convert it to
22103 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
22104 // The same situation for all 128 and 256-bit vectors of i8 and i16.
22105 // Since SKX these selects have a proper lowering.
22106 EVT OpVT = LHS.getValueType();
22107 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
22108 (OpVT.getVectorElementType() == MVT::i8 ||
22109 OpVT.getVectorElementType() == MVT::i16) &&
22110 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
22111 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
22112 DCI.AddToWorklist(Cond.getNode());
22113 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
22116 // If this is a select between two integer constants, try to do some
22118 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
22119 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
22120 // Don't do this for crazy integer types.
22121 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
22122 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
22123 // so that TrueC (the true value) is larger than FalseC.
22124 bool NeedsCondInvert = false;
22126 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
22127 // Efficiently invertible.
22128 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
22129 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
22130 isa<ConstantSDNode>(Cond.getOperand(1))))) {
22131 NeedsCondInvert = true;
22132 std::swap(TrueC, FalseC);
22135 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
22136 if (FalseC->getAPIntValue() == 0 &&
22137 TrueC->getAPIntValue().isPowerOf2()) {
22138 if (NeedsCondInvert) // Invert the condition if needed.
22139 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22140 DAG.getConstant(1, Cond.getValueType()));
22142 // Zero extend the condition if needed.
22143 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
22145 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22146 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
22147 DAG.getConstant(ShAmt, MVT::i8));
22150 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
22151 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22152 if (NeedsCondInvert) // Invert the condition if needed.
22153 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22154 DAG.getConstant(1, Cond.getValueType()));
22156 // Zero extend the condition if needed.
22157 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22158 FalseC->getValueType(0), Cond);
22159 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22160 SDValue(FalseC, 0));
22163 // Optimize cases that will turn into an LEA instruction. This requires
22164 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22165 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22166 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22167 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22169 bool isFastMultiplier = false;
22171 switch ((unsigned char)Diff) {
22173 case 1: // result = add base, cond
22174 case 2: // result = lea base( , cond*2)
22175 case 3: // result = lea base(cond, cond*2)
22176 case 4: // result = lea base( , cond*4)
22177 case 5: // result = lea base(cond, cond*4)
22178 case 8: // result = lea base( , cond*8)
22179 case 9: // result = lea base(cond, cond*8)
22180 isFastMultiplier = true;
22185 if (isFastMultiplier) {
22186 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22187 if (NeedsCondInvert) // Invert the condition if needed.
22188 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22189 DAG.getConstant(1, Cond.getValueType()));
22191 // Zero extend the condition if needed.
22192 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22194 // Scale the condition by the difference.
22196 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22197 DAG.getConstant(Diff, Cond.getValueType()));
22199 // Add the base if non-zero.
22200 if (FalseC->getAPIntValue() != 0)
22201 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22202 SDValue(FalseC, 0));
22209 // Canonicalize max and min:
22210 // (x > y) ? x : y -> (x >= y) ? x : y
22211 // (x < y) ? x : y -> (x <= y) ? x : y
22212 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
22213 // the need for an extra compare
22214 // against zero. e.g.
22215 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
22217 // testl %edi, %edi
22219 // cmovgl %edi, %eax
22223 // cmovsl %eax, %edi
22224 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
22225 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22226 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22227 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22232 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
22233 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
22234 Cond.getOperand(0), Cond.getOperand(1), NewCC);
22235 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
22240 // Early exit check
22241 if (!TLI.isTypeLegal(VT))
22244 // Match VSELECTs into subs with unsigned saturation.
22245 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
22246 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
22247 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
22248 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
22249 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22251 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
22252 // left side invert the predicate to simplify logic below.
22254 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
22256 CC = ISD::getSetCCInverse(CC, true);
22257 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
22261 if (Other.getNode() && Other->getNumOperands() == 2 &&
22262 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
22263 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
22264 SDValue CondRHS = Cond->getOperand(1);
22266 // Look for a general sub with unsigned saturation first.
22267 // x >= y ? x-y : 0 --> subus x, y
22268 // x > y ? x-y : 0 --> subus x, y
22269 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
22270 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
22271 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
22273 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
22274 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
22275 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
22276 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
22277 // If the RHS is a constant we have to reverse the const
22278 // canonicalization.
22279 // x > C-1 ? x+-C : 0 --> subus x, C
22280 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
22281 CondRHSConst->getAPIntValue() ==
22282 (-OpRHSConst->getAPIntValue() - 1))
22283 return DAG.getNode(
22284 X86ISD::SUBUS, DL, VT, OpLHS,
22285 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
22287 // Another special case: If C was a sign bit, the sub has been
22288 // canonicalized into a xor.
22289 // FIXME: Would it be better to use computeKnownBits to determine
22290 // whether it's safe to decanonicalize the xor?
22291 // x s< 0 ? x^C : 0 --> subus x, C
22292 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
22293 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
22294 OpRHSConst->getAPIntValue().isSignBit())
22295 // Note that we have to rebuild the RHS constant here to ensure we
22296 // don't rely on particular values of undef lanes.
22297 return DAG.getNode(
22298 X86ISD::SUBUS, DL, VT, OpLHS,
22299 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
22304 // Try to match a min/max vector operation.
22305 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
22306 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
22307 unsigned Opc = ret.first;
22308 bool NeedSplit = ret.second;
22310 if (Opc && NeedSplit) {
22311 unsigned NumElems = VT.getVectorNumElements();
22312 // Extract the LHS vectors
22313 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
22314 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
22316 // Extract the RHS vectors
22317 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
22318 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
22320 // Create min/max for each subvector
22321 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
22322 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
22324 // Merge the result
22325 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
22327 return DAG.getNode(Opc, DL, VT, LHS, RHS);
22330 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
22331 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
22332 // Check if SETCC has already been promoted
22333 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
22334 // Check that condition value type matches vselect operand type
22337 assert(Cond.getValueType().isVector() &&
22338 "vector select expects a vector selector!");
22340 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
22341 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
22343 if (!TValIsAllOnes && !FValIsAllZeros) {
22344 // Try invert the condition if true value is not all 1s and false value
22346 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
22347 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
22349 if (TValIsAllZeros || FValIsAllOnes) {
22350 SDValue CC = Cond.getOperand(2);
22351 ISD::CondCode NewCC =
22352 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
22353 Cond.getOperand(0).getValueType().isInteger());
22354 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
22355 std::swap(LHS, RHS);
22356 TValIsAllOnes = FValIsAllOnes;
22357 FValIsAllZeros = TValIsAllZeros;
22361 if (TValIsAllOnes || FValIsAllZeros) {
22364 if (TValIsAllOnes && FValIsAllZeros)
22366 else if (TValIsAllOnes)
22367 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
22368 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
22369 else if (FValIsAllZeros)
22370 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
22371 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
22373 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
22377 // Try to fold this VSELECT into a MOVSS/MOVSD
22378 if (N->getOpcode() == ISD::VSELECT &&
22379 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
22380 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
22381 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
22382 bool CanFold = false;
22383 unsigned NumElems = Cond.getNumOperands();
22387 if (isZero(Cond.getOperand(0))) {
22390 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
22391 // fold (vselect <0,-1> -> (movsd A, B)
22392 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
22393 CanFold = isAllOnes(Cond.getOperand(i));
22394 } else if (isAllOnes(Cond.getOperand(0))) {
22398 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
22399 // fold (vselect <-1,0> -> (movsd B, A)
22400 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
22401 CanFold = isZero(Cond.getOperand(i));
22405 if (VT == MVT::v4i32 || VT == MVT::v4f32)
22406 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
22407 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
22410 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
22411 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
22412 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
22413 // (v2i64 (bitcast B)))))
22415 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
22416 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
22417 // (v2f64 (bitcast B)))))
22419 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
22420 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
22421 // (v2i64 (bitcast A)))))
22423 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
22424 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
22425 // (v2f64 (bitcast A)))))
22427 CanFold = (isZero(Cond.getOperand(0)) &&
22428 isZero(Cond.getOperand(1)) &&
22429 isAllOnes(Cond.getOperand(2)) &&
22430 isAllOnes(Cond.getOperand(3)));
22432 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
22433 isAllOnes(Cond.getOperand(1)) &&
22434 isZero(Cond.getOperand(2)) &&
22435 isZero(Cond.getOperand(3))) {
22437 std::swap(LHS, RHS);
22441 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
22442 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
22443 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
22444 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
22446 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
22452 // If we know that this node is legal then we know that it is going to be
22453 // matched by one of the SSE/AVX BLEND instructions. These instructions only
22454 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
22455 // to simplify previous instructions.
22456 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
22457 !DCI.isBeforeLegalize() &&
22458 // We explicitly check against v8i16 and v16i16 because, although
22459 // they're marked as Custom, they might only be legal when Cond is a
22460 // build_vector of constants. This will be taken care in a later
22462 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
22463 VT != MVT::v8i16)) {
22464 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
22466 // Don't optimize vector selects that map to mask-registers.
22470 // Check all uses of that condition operand to check whether it will be
22471 // consumed by non-BLEND instructions, which may depend on all bits are set
22473 for (SDNode::use_iterator I = Cond->use_begin(),
22474 E = Cond->use_end(); I != E; ++I)
22475 if (I->getOpcode() != ISD::VSELECT)
22476 // TODO: Add other opcodes eventually lowered into BLEND.
22479 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
22480 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
22482 APInt KnownZero, KnownOne;
22483 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
22484 DCI.isBeforeLegalizeOps());
22485 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
22486 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
22487 DCI.CommitTargetLoweringOpt(TLO);
22490 // We should generate an X86ISD::BLENDI from a vselect if its argument
22491 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
22492 // constants. This specific pattern gets generated when we split a
22493 // selector for a 512 bit vector in a machine without AVX512 (but with
22494 // 256-bit vectors), during legalization:
22496 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
22498 // Iff we find this pattern and the build_vectors are built from
22499 // constants, we translate the vselect into a shuffle_vector that we
22500 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
22501 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
22502 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
22503 if (Shuffle.getNode())
22510 // Check whether a boolean test is testing a boolean value generated by
22511 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
22514 // Simplify the following patterns:
22515 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
22516 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
22517 // to (Op EFLAGS Cond)
22519 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
22520 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
22521 // to (Op EFLAGS !Cond)
22523 // where Op could be BRCOND or CMOV.
22525 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
22526 // Quit if not CMP and SUB with its value result used.
22527 if (Cmp.getOpcode() != X86ISD::CMP &&
22528 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
22531 // Quit if not used as a boolean value.
22532 if (CC != X86::COND_E && CC != X86::COND_NE)
22535 // Check CMP operands. One of them should be 0 or 1 and the other should be
22536 // an SetCC or extended from it.
22537 SDValue Op1 = Cmp.getOperand(0);
22538 SDValue Op2 = Cmp.getOperand(1);
22541 const ConstantSDNode* C = nullptr;
22542 bool needOppositeCond = (CC == X86::COND_E);
22543 bool checkAgainstTrue = false; // Is it a comparison against 1?
22545 if ((C = dyn_cast<ConstantSDNode>(Op1)))
22547 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
22549 else // Quit if all operands are not constants.
22552 if (C->getZExtValue() == 1) {
22553 needOppositeCond = !needOppositeCond;
22554 checkAgainstTrue = true;
22555 } else if (C->getZExtValue() != 0)
22556 // Quit if the constant is neither 0 or 1.
22559 bool truncatedToBoolWithAnd = false;
22560 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
22561 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
22562 SetCC.getOpcode() == ISD::TRUNCATE ||
22563 SetCC.getOpcode() == ISD::AND) {
22564 if (SetCC.getOpcode() == ISD::AND) {
22566 ConstantSDNode *CS;
22567 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
22568 CS->getZExtValue() == 1)
22570 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
22571 CS->getZExtValue() == 1)
22575 SetCC = SetCC.getOperand(OpIdx);
22576 truncatedToBoolWithAnd = true;
22578 SetCC = SetCC.getOperand(0);
22581 switch (SetCC.getOpcode()) {
22582 case X86ISD::SETCC_CARRY:
22583 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
22584 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
22585 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
22586 // truncated to i1 using 'and'.
22587 if (checkAgainstTrue && !truncatedToBoolWithAnd)
22589 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
22590 "Invalid use of SETCC_CARRY!");
22592 case X86ISD::SETCC:
22593 // Set the condition code or opposite one if necessary.
22594 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
22595 if (needOppositeCond)
22596 CC = X86::GetOppositeBranchCondition(CC);
22597 return SetCC.getOperand(1);
22598 case X86ISD::CMOV: {
22599 // Check whether false/true value has canonical one, i.e. 0 or 1.
22600 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
22601 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
22602 // Quit if true value is not a constant.
22605 // Quit if false value is not a constant.
22607 SDValue Op = SetCC.getOperand(0);
22608 // Skip 'zext' or 'trunc' node.
22609 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
22610 Op.getOpcode() == ISD::TRUNCATE)
22611 Op = Op.getOperand(0);
22612 // A special case for rdrand/rdseed, where 0 is set if false cond is
22614 if ((Op.getOpcode() != X86ISD::RDRAND &&
22615 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
22618 // Quit if false value is not the constant 0 or 1.
22619 bool FValIsFalse = true;
22620 if (FVal && FVal->getZExtValue() != 0) {
22621 if (FVal->getZExtValue() != 1)
22623 // If FVal is 1, opposite cond is needed.
22624 needOppositeCond = !needOppositeCond;
22625 FValIsFalse = false;
22627 // Quit if TVal is not the constant opposite of FVal.
22628 if (FValIsFalse && TVal->getZExtValue() != 1)
22630 if (!FValIsFalse && TVal->getZExtValue() != 0)
22632 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
22633 if (needOppositeCond)
22634 CC = X86::GetOppositeBranchCondition(CC);
22635 return SetCC.getOperand(3);
22642 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
22643 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
22644 TargetLowering::DAGCombinerInfo &DCI,
22645 const X86Subtarget *Subtarget) {
22648 // If the flag operand isn't dead, don't touch this CMOV.
22649 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
22652 SDValue FalseOp = N->getOperand(0);
22653 SDValue TrueOp = N->getOperand(1);
22654 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
22655 SDValue Cond = N->getOperand(3);
22657 if (CC == X86::COND_E || CC == X86::COND_NE) {
22658 switch (Cond.getOpcode()) {
22662 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
22663 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
22664 return (CC == X86::COND_E) ? FalseOp : TrueOp;
22670 Flags = checkBoolTestSetCCCombine(Cond, CC);
22671 if (Flags.getNode() &&
22672 // Extra check as FCMOV only supports a subset of X86 cond.
22673 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
22674 SDValue Ops[] = { FalseOp, TrueOp,
22675 DAG.getConstant(CC, MVT::i8), Flags };
22676 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22679 // If this is a select between two integer constants, try to do some
22680 // optimizations. Note that the operands are ordered the opposite of SELECT
22682 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
22683 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
22684 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
22685 // larger than FalseC (the false value).
22686 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
22687 CC = X86::GetOppositeBranchCondition(CC);
22688 std::swap(TrueC, FalseC);
22689 std::swap(TrueOp, FalseOp);
22692 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
22693 // This is efficient for any integer data type (including i8/i16) and
22695 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
22696 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22697 DAG.getConstant(CC, MVT::i8), Cond);
22699 // Zero extend the condition if needed.
22700 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
22702 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22703 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
22704 DAG.getConstant(ShAmt, MVT::i8));
22705 if (N->getNumValues() == 2) // Dead flag value?
22706 return DCI.CombineTo(N, Cond, SDValue());
22710 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
22711 // for any integer data type, including i8/i16.
22712 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22713 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22714 DAG.getConstant(CC, MVT::i8), Cond);
22716 // Zero extend the condition if needed.
22717 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22718 FalseC->getValueType(0), Cond);
22719 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22720 SDValue(FalseC, 0));
22722 if (N->getNumValues() == 2) // Dead flag value?
22723 return DCI.CombineTo(N, Cond, SDValue());
22727 // Optimize cases that will turn into an LEA instruction. This requires
22728 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22729 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22730 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22731 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22733 bool isFastMultiplier = false;
22735 switch ((unsigned char)Diff) {
22737 case 1: // result = add base, cond
22738 case 2: // result = lea base( , cond*2)
22739 case 3: // result = lea base(cond, cond*2)
22740 case 4: // result = lea base( , cond*4)
22741 case 5: // result = lea base(cond, cond*4)
22742 case 8: // result = lea base( , cond*8)
22743 case 9: // result = lea base(cond, cond*8)
22744 isFastMultiplier = true;
22749 if (isFastMultiplier) {
22750 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22751 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22752 DAG.getConstant(CC, MVT::i8), Cond);
22753 // Zero extend the condition if needed.
22754 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22756 // Scale the condition by the difference.
22758 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22759 DAG.getConstant(Diff, Cond.getValueType()));
22761 // Add the base if non-zero.
22762 if (FalseC->getAPIntValue() != 0)
22763 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22764 SDValue(FalseC, 0));
22765 if (N->getNumValues() == 2) // Dead flag value?
22766 return DCI.CombineTo(N, Cond, SDValue());
22773 // Handle these cases:
22774 // (select (x != c), e, c) -> select (x != c), e, x),
22775 // (select (x == c), c, e) -> select (x == c), x, e)
22776 // where the c is an integer constant, and the "select" is the combination
22777 // of CMOV and CMP.
22779 // The rationale for this change is that the conditional-move from a constant
22780 // needs two instructions, however, conditional-move from a register needs
22781 // only one instruction.
22783 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
22784 // some instruction-combining opportunities. This opt needs to be
22785 // postponed as late as possible.
22787 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
22788 // the DCI.xxxx conditions are provided to postpone the optimization as
22789 // late as possible.
22791 ConstantSDNode *CmpAgainst = nullptr;
22792 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
22793 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
22794 !isa<ConstantSDNode>(Cond.getOperand(0))) {
22796 if (CC == X86::COND_NE &&
22797 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
22798 CC = X86::GetOppositeBranchCondition(CC);
22799 std::swap(TrueOp, FalseOp);
22802 if (CC == X86::COND_E &&
22803 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
22804 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
22805 DAG.getConstant(CC, MVT::i8), Cond };
22806 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
22814 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
22815 const X86Subtarget *Subtarget) {
22816 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
22818 default: return SDValue();
22819 // SSE/AVX/AVX2 blend intrinsics.
22820 case Intrinsic::x86_avx2_pblendvb:
22821 case Intrinsic::x86_avx2_pblendw:
22822 case Intrinsic::x86_avx2_pblendd_128:
22823 case Intrinsic::x86_avx2_pblendd_256:
22824 // Don't try to simplify this intrinsic if we don't have AVX2.
22825 if (!Subtarget->hasAVX2())
22828 case Intrinsic::x86_avx_blend_pd_256:
22829 case Intrinsic::x86_avx_blend_ps_256:
22830 case Intrinsic::x86_avx_blendv_pd_256:
22831 case Intrinsic::x86_avx_blendv_ps_256:
22832 // Don't try to simplify this intrinsic if we don't have AVX.
22833 if (!Subtarget->hasAVX())
22836 case Intrinsic::x86_sse41_pblendw:
22837 case Intrinsic::x86_sse41_blendpd:
22838 case Intrinsic::x86_sse41_blendps:
22839 case Intrinsic::x86_sse41_blendvps:
22840 case Intrinsic::x86_sse41_blendvpd:
22841 case Intrinsic::x86_sse41_pblendvb: {
22842 SDValue Op0 = N->getOperand(1);
22843 SDValue Op1 = N->getOperand(2);
22844 SDValue Mask = N->getOperand(3);
22846 // Don't try to simplify this intrinsic if we don't have SSE4.1.
22847 if (!Subtarget->hasSSE41())
22850 // fold (blend A, A, Mask) -> A
22853 // fold (blend A, B, allZeros) -> A
22854 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
22856 // fold (blend A, B, allOnes) -> B
22857 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
22860 // Simplify the case where the mask is a constant i32 value.
22861 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
22862 if (C->isNullValue())
22864 if (C->isAllOnesValue())
22871 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
22872 case Intrinsic::x86_sse2_psrai_w:
22873 case Intrinsic::x86_sse2_psrai_d:
22874 case Intrinsic::x86_avx2_psrai_w:
22875 case Intrinsic::x86_avx2_psrai_d:
22876 case Intrinsic::x86_sse2_psra_w:
22877 case Intrinsic::x86_sse2_psra_d:
22878 case Intrinsic::x86_avx2_psra_w:
22879 case Intrinsic::x86_avx2_psra_d: {
22880 SDValue Op0 = N->getOperand(1);
22881 SDValue Op1 = N->getOperand(2);
22882 EVT VT = Op0.getValueType();
22883 assert(VT.isVector() && "Expected a vector type!");
22885 if (isa<BuildVectorSDNode>(Op1))
22886 Op1 = Op1.getOperand(0);
22888 if (!isa<ConstantSDNode>(Op1))
22891 EVT SVT = VT.getVectorElementType();
22892 unsigned SVTBits = SVT.getSizeInBits();
22894 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
22895 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
22896 uint64_t ShAmt = C.getZExtValue();
22898 // Don't try to convert this shift into a ISD::SRA if the shift
22899 // count is bigger than or equal to the element size.
22900 if (ShAmt >= SVTBits)
22903 // Trivial case: if the shift count is zero, then fold this
22904 // into the first operand.
22908 // Replace this packed shift intrinsic with a target independent
22910 SDValue Splat = DAG.getConstant(C, VT);
22911 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
22916 /// PerformMulCombine - Optimize a single multiply with constant into two
22917 /// in order to implement it with two cheaper instructions, e.g.
22918 /// LEA + SHL, LEA + LEA.
22919 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
22920 TargetLowering::DAGCombinerInfo &DCI) {
22921 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
22924 EVT VT = N->getValueType(0);
22925 if (VT != MVT::i64)
22928 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
22931 uint64_t MulAmt = C->getZExtValue();
22932 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
22935 uint64_t MulAmt1 = 0;
22936 uint64_t MulAmt2 = 0;
22937 if ((MulAmt % 9) == 0) {
22939 MulAmt2 = MulAmt / 9;
22940 } else if ((MulAmt % 5) == 0) {
22942 MulAmt2 = MulAmt / 5;
22943 } else if ((MulAmt % 3) == 0) {
22945 MulAmt2 = MulAmt / 3;
22948 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
22951 if (isPowerOf2_64(MulAmt2) &&
22952 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
22953 // If second multiplifer is pow2, issue it first. We want the multiply by
22954 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
22956 std::swap(MulAmt1, MulAmt2);
22959 if (isPowerOf2_64(MulAmt1))
22960 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
22961 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
22963 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
22964 DAG.getConstant(MulAmt1, VT));
22966 if (isPowerOf2_64(MulAmt2))
22967 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
22968 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
22970 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
22971 DAG.getConstant(MulAmt2, VT));
22973 // Do not add new nodes to DAG combiner worklist.
22974 DCI.CombineTo(N, NewMul, false);
22979 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
22980 SDValue N0 = N->getOperand(0);
22981 SDValue N1 = N->getOperand(1);
22982 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
22983 EVT VT = N0.getValueType();
22985 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
22986 // since the result of setcc_c is all zero's or all ones.
22987 if (VT.isInteger() && !VT.isVector() &&
22988 N1C && N0.getOpcode() == ISD::AND &&
22989 N0.getOperand(1).getOpcode() == ISD::Constant) {
22990 SDValue N00 = N0.getOperand(0);
22991 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
22992 ((N00.getOpcode() == ISD::ANY_EXTEND ||
22993 N00.getOpcode() == ISD::ZERO_EXTEND) &&
22994 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
22995 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
22996 APInt ShAmt = N1C->getAPIntValue();
22997 Mask = Mask.shl(ShAmt);
22999 return DAG.getNode(ISD::AND, SDLoc(N), VT,
23000 N00, DAG.getConstant(Mask, VT));
23004 // Hardware support for vector shifts is sparse which makes us scalarize the
23005 // vector operations in many cases. Also, on sandybridge ADD is faster than
23007 // (shl V, 1) -> add V,V
23008 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23009 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23010 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23011 // We shift all of the values by one. In many cases we do not have
23012 // hardware support for this operation. This is better expressed as an ADD
23014 if (N1SplatC->getZExtValue() == 1)
23015 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
23021 /// \brief Returns a vector of 0s if the node in input is a vector logical
23022 /// shift by a constant amount which is known to be bigger than or equal
23023 /// to the vector element size in bits.
23024 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
23025 const X86Subtarget *Subtarget) {
23026 EVT VT = N->getValueType(0);
23028 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
23029 (!Subtarget->hasInt256() ||
23030 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
23033 SDValue Amt = N->getOperand(1);
23035 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
23036 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
23037 APInt ShiftAmt = AmtSplat->getAPIntValue();
23038 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
23040 // SSE2/AVX2 logical shifts always return a vector of 0s
23041 // if the shift amount is bigger than or equal to
23042 // the element size. The constant shift amount will be
23043 // encoded as a 8-bit immediate.
23044 if (ShiftAmt.trunc(8).uge(MaxAmount))
23045 return getZeroVector(VT, Subtarget, DAG, DL);
23051 /// PerformShiftCombine - Combine shifts.
23052 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
23053 TargetLowering::DAGCombinerInfo &DCI,
23054 const X86Subtarget *Subtarget) {
23055 if (N->getOpcode() == ISD::SHL) {
23056 SDValue V = PerformSHLCombine(N, DAG);
23057 if (V.getNode()) return V;
23060 if (N->getOpcode() != ISD::SRA) {
23061 // Try to fold this logical shift into a zero vector.
23062 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
23063 if (V.getNode()) return V;
23069 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
23070 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
23071 // and friends. Likewise for OR -> CMPNEQSS.
23072 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
23073 TargetLowering::DAGCombinerInfo &DCI,
23074 const X86Subtarget *Subtarget) {
23077 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
23078 // we're requiring SSE2 for both.
23079 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
23080 SDValue N0 = N->getOperand(0);
23081 SDValue N1 = N->getOperand(1);
23082 SDValue CMP0 = N0->getOperand(1);
23083 SDValue CMP1 = N1->getOperand(1);
23086 // The SETCCs should both refer to the same CMP.
23087 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
23090 SDValue CMP00 = CMP0->getOperand(0);
23091 SDValue CMP01 = CMP0->getOperand(1);
23092 EVT VT = CMP00.getValueType();
23094 if (VT == MVT::f32 || VT == MVT::f64) {
23095 bool ExpectingFlags = false;
23096 // Check for any users that want flags:
23097 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
23098 !ExpectingFlags && UI != UE; ++UI)
23099 switch (UI->getOpcode()) {
23104 ExpectingFlags = true;
23106 case ISD::CopyToReg:
23107 case ISD::SIGN_EXTEND:
23108 case ISD::ZERO_EXTEND:
23109 case ISD::ANY_EXTEND:
23113 if (!ExpectingFlags) {
23114 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
23115 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
23117 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
23118 X86::CondCode tmp = cc0;
23123 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
23124 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
23125 // FIXME: need symbolic constants for these magic numbers.
23126 // See X86ATTInstPrinter.cpp:printSSECC().
23127 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
23128 if (Subtarget->hasAVX512()) {
23129 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
23130 CMP01, DAG.getConstant(x86cc, MVT::i8));
23131 if (N->getValueType(0) != MVT::i1)
23132 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
23136 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
23137 CMP00.getValueType(), CMP00, CMP01,
23138 DAG.getConstant(x86cc, MVT::i8));
23140 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
23141 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
23143 if (is64BitFP && !Subtarget->is64Bit()) {
23144 // On a 32-bit target, we cannot bitcast the 64-bit float to a
23145 // 64-bit integer, since that's not a legal type. Since
23146 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
23147 // bits, but can do this little dance to extract the lowest 32 bits
23148 // and work with those going forward.
23149 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
23151 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
23153 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
23154 Vector32, DAG.getIntPtrConstant(0));
23158 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
23159 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
23160 DAG.getConstant(1, IntVT));
23161 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
23162 return OneBitOfTruth;
23170 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
23171 /// so it can be folded inside ANDNP.
23172 static bool CanFoldXORWithAllOnes(const SDNode *N) {
23173 EVT VT = N->getValueType(0);
23175 // Match direct AllOnes for 128 and 256-bit vectors
23176 if (ISD::isBuildVectorAllOnes(N))
23179 // Look through a bit convert.
23180 if (N->getOpcode() == ISD::BITCAST)
23181 N = N->getOperand(0).getNode();
23183 // Sometimes the operand may come from a insert_subvector building a 256-bit
23185 if (VT.is256BitVector() &&
23186 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
23187 SDValue V1 = N->getOperand(0);
23188 SDValue V2 = N->getOperand(1);
23190 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
23191 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
23192 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
23193 ISD::isBuildVectorAllOnes(V2.getNode()))
23200 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
23201 // register. In most cases we actually compare or select YMM-sized registers
23202 // and mixing the two types creates horrible code. This method optimizes
23203 // some of the transition sequences.
23204 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
23205 TargetLowering::DAGCombinerInfo &DCI,
23206 const X86Subtarget *Subtarget) {
23207 EVT VT = N->getValueType(0);
23208 if (!VT.is256BitVector())
23211 assert((N->getOpcode() == ISD::ANY_EXTEND ||
23212 N->getOpcode() == ISD::ZERO_EXTEND ||
23213 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
23215 SDValue Narrow = N->getOperand(0);
23216 EVT NarrowVT = Narrow->getValueType(0);
23217 if (!NarrowVT.is128BitVector())
23220 if (Narrow->getOpcode() != ISD::XOR &&
23221 Narrow->getOpcode() != ISD::AND &&
23222 Narrow->getOpcode() != ISD::OR)
23225 SDValue N0 = Narrow->getOperand(0);
23226 SDValue N1 = Narrow->getOperand(1);
23229 // The Left side has to be a trunc.
23230 if (N0.getOpcode() != ISD::TRUNCATE)
23233 // The type of the truncated inputs.
23234 EVT WideVT = N0->getOperand(0)->getValueType(0);
23238 // The right side has to be a 'trunc' or a constant vector.
23239 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
23240 ConstantSDNode *RHSConstSplat = nullptr;
23241 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
23242 RHSConstSplat = RHSBV->getConstantSplatNode();
23243 if (!RHSTrunc && !RHSConstSplat)
23246 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23248 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
23251 // Set N0 and N1 to hold the inputs to the new wide operation.
23252 N0 = N0->getOperand(0);
23253 if (RHSConstSplat) {
23254 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
23255 SDValue(RHSConstSplat, 0));
23256 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
23257 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
23258 } else if (RHSTrunc) {
23259 N1 = N1->getOperand(0);
23262 // Generate the wide operation.
23263 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
23264 unsigned Opcode = N->getOpcode();
23266 case ISD::ANY_EXTEND:
23268 case ISD::ZERO_EXTEND: {
23269 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
23270 APInt Mask = APInt::getAllOnesValue(InBits);
23271 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
23272 return DAG.getNode(ISD::AND, DL, VT,
23273 Op, DAG.getConstant(Mask, VT));
23275 case ISD::SIGN_EXTEND:
23276 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
23277 Op, DAG.getValueType(NarrowVT));
23279 llvm_unreachable("Unexpected opcode");
23283 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
23284 TargetLowering::DAGCombinerInfo &DCI,
23285 const X86Subtarget *Subtarget) {
23286 EVT VT = N->getValueType(0);
23287 if (DCI.isBeforeLegalizeOps())
23290 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23294 // Create BEXTR instructions
23295 // BEXTR is ((X >> imm) & (2**size-1))
23296 if (VT == MVT::i32 || VT == MVT::i64) {
23297 SDValue N0 = N->getOperand(0);
23298 SDValue N1 = N->getOperand(1);
23301 // Check for BEXTR.
23302 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
23303 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
23304 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
23305 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23306 if (MaskNode && ShiftNode) {
23307 uint64_t Mask = MaskNode->getZExtValue();
23308 uint64_t Shift = ShiftNode->getZExtValue();
23309 if (isMask_64(Mask)) {
23310 uint64_t MaskSize = CountPopulation_64(Mask);
23311 if (Shift + MaskSize <= VT.getSizeInBits())
23312 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
23313 DAG.getConstant(Shift | (MaskSize << 8), VT));
23321 // Want to form ANDNP nodes:
23322 // 1) In the hopes of then easily combining them with OR and AND nodes
23323 // to form PBLEND/PSIGN.
23324 // 2) To match ANDN packed intrinsics
23325 if (VT != MVT::v2i64 && VT != MVT::v4i64)
23328 SDValue N0 = N->getOperand(0);
23329 SDValue N1 = N->getOperand(1);
23332 // Check LHS for vnot
23333 if (N0.getOpcode() == ISD::XOR &&
23334 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
23335 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
23336 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
23338 // Check RHS for vnot
23339 if (N1.getOpcode() == ISD::XOR &&
23340 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
23341 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
23342 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
23347 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
23348 TargetLowering::DAGCombinerInfo &DCI,
23349 const X86Subtarget *Subtarget) {
23350 if (DCI.isBeforeLegalizeOps())
23353 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
23357 SDValue N0 = N->getOperand(0);
23358 SDValue N1 = N->getOperand(1);
23359 EVT VT = N->getValueType(0);
23361 // look for psign/blend
23362 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
23363 if (!Subtarget->hasSSSE3() ||
23364 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
23367 // Canonicalize pandn to RHS
23368 if (N0.getOpcode() == X86ISD::ANDNP)
23370 // or (and (m, y), (pandn m, x))
23371 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
23372 SDValue Mask = N1.getOperand(0);
23373 SDValue X = N1.getOperand(1);
23375 if (N0.getOperand(0) == Mask)
23376 Y = N0.getOperand(1);
23377 if (N0.getOperand(1) == Mask)
23378 Y = N0.getOperand(0);
23380 // Check to see if the mask appeared in both the AND and ANDNP and
23384 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
23385 // Look through mask bitcast.
23386 if (Mask.getOpcode() == ISD::BITCAST)
23387 Mask = Mask.getOperand(0);
23388 if (X.getOpcode() == ISD::BITCAST)
23389 X = X.getOperand(0);
23390 if (Y.getOpcode() == ISD::BITCAST)
23391 Y = Y.getOperand(0);
23393 EVT MaskVT = Mask.getValueType();
23395 // Validate that the Mask operand is a vector sra node.
23396 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
23397 // there is no psrai.b
23398 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
23399 unsigned SraAmt = ~0;
23400 if (Mask.getOpcode() == ISD::SRA) {
23401 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
23402 if (auto *AmtConst = AmtBV->getConstantSplatNode())
23403 SraAmt = AmtConst->getZExtValue();
23404 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
23405 SDValue SraC = Mask.getOperand(1);
23406 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
23408 if ((SraAmt + 1) != EltBits)
23413 // Now we know we at least have a plendvb with the mask val. See if
23414 // we can form a psignb/w/d.
23415 // psign = x.type == y.type == mask.type && y = sub(0, x);
23416 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
23417 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
23418 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
23419 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
23420 "Unsupported VT for PSIGN");
23421 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
23422 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
23424 // PBLENDVB only available on SSE 4.1
23425 if (!Subtarget->hasSSE41())
23428 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
23430 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
23431 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
23432 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
23433 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
23434 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
23438 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
23441 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
23442 MachineFunction &MF = DAG.getMachineFunction();
23443 bool OptForSize = MF.getFunction()->getAttributes().
23444 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
23446 // SHLD/SHRD instructions have lower register pressure, but on some
23447 // platforms they have higher latency than the equivalent
23448 // series of shifts/or that would otherwise be generated.
23449 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
23450 // have higher latencies and we are not optimizing for size.
23451 if (!OptForSize && Subtarget->isSHLDSlow())
23454 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
23456 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
23458 if (!N0.hasOneUse() || !N1.hasOneUse())
23461 SDValue ShAmt0 = N0.getOperand(1);
23462 if (ShAmt0.getValueType() != MVT::i8)
23464 SDValue ShAmt1 = N1.getOperand(1);
23465 if (ShAmt1.getValueType() != MVT::i8)
23467 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
23468 ShAmt0 = ShAmt0.getOperand(0);
23469 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
23470 ShAmt1 = ShAmt1.getOperand(0);
23473 unsigned Opc = X86ISD::SHLD;
23474 SDValue Op0 = N0.getOperand(0);
23475 SDValue Op1 = N1.getOperand(0);
23476 if (ShAmt0.getOpcode() == ISD::SUB) {
23477 Opc = X86ISD::SHRD;
23478 std::swap(Op0, Op1);
23479 std::swap(ShAmt0, ShAmt1);
23482 unsigned Bits = VT.getSizeInBits();
23483 if (ShAmt1.getOpcode() == ISD::SUB) {
23484 SDValue Sum = ShAmt1.getOperand(0);
23485 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
23486 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
23487 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
23488 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
23489 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
23490 return DAG.getNode(Opc, DL, VT,
23492 DAG.getNode(ISD::TRUNCATE, DL,
23495 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
23496 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
23498 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
23499 return DAG.getNode(Opc, DL, VT,
23500 N0.getOperand(0), N1.getOperand(0),
23501 DAG.getNode(ISD::TRUNCATE, DL,
23508 // Generate NEG and CMOV for integer abs.
23509 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
23510 EVT VT = N->getValueType(0);
23512 // Since X86 does not have CMOV for 8-bit integer, we don't convert
23513 // 8-bit integer abs to NEG and CMOV.
23514 if (VT.isInteger() && VT.getSizeInBits() == 8)
23517 SDValue N0 = N->getOperand(0);
23518 SDValue N1 = N->getOperand(1);
23521 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
23522 // and change it to SUB and CMOV.
23523 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
23524 N0.getOpcode() == ISD::ADD &&
23525 N0.getOperand(1) == N1 &&
23526 N1.getOpcode() == ISD::SRA &&
23527 N1.getOperand(0) == N0.getOperand(0))
23528 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
23529 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
23530 // Generate SUB & CMOV.
23531 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
23532 DAG.getConstant(0, VT), N0.getOperand(0));
23534 SDValue Ops[] = { N0.getOperand(0), Neg,
23535 DAG.getConstant(X86::COND_GE, MVT::i8),
23536 SDValue(Neg.getNode(), 1) };
23537 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
23542 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
23543 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
23544 TargetLowering::DAGCombinerInfo &DCI,
23545 const X86Subtarget *Subtarget) {
23546 if (DCI.isBeforeLegalizeOps())
23549 if (Subtarget->hasCMov()) {
23550 SDValue RV = performIntegerAbsCombine(N, DAG);
23558 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
23559 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
23560 TargetLowering::DAGCombinerInfo &DCI,
23561 const X86Subtarget *Subtarget) {
23562 LoadSDNode *Ld = cast<LoadSDNode>(N);
23563 EVT RegVT = Ld->getValueType(0);
23564 EVT MemVT = Ld->getMemoryVT();
23566 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23568 // On Sandybridge unaligned 256bit loads are inefficient.
23569 ISD::LoadExtType Ext = Ld->getExtensionType();
23570 unsigned Alignment = Ld->getAlignment();
23571 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
23572 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
23573 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
23574 unsigned NumElems = RegVT.getVectorNumElements();
23578 SDValue Ptr = Ld->getBasePtr();
23579 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
23581 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
23583 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23584 Ld->getPointerInfo(), Ld->isVolatile(),
23585 Ld->isNonTemporal(), Ld->isInvariant(),
23587 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23588 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23589 Ld->getPointerInfo(), Ld->isVolatile(),
23590 Ld->isNonTemporal(), Ld->isInvariant(),
23591 std::min(16U, Alignment));
23592 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
23594 Load2.getValue(1));
23596 SDValue NewVec = DAG.getUNDEF(RegVT);
23597 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
23598 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
23599 return DCI.CombineTo(N, NewVec, TF, true);
23605 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
23606 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
23607 const X86Subtarget *Subtarget) {
23608 StoreSDNode *St = cast<StoreSDNode>(N);
23609 EVT VT = St->getValue().getValueType();
23610 EVT StVT = St->getMemoryVT();
23612 SDValue StoredVal = St->getOperand(1);
23613 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23615 // If we are saving a concatenation of two XMM registers, perform two stores.
23616 // On Sandy Bridge, 256-bit memory operations are executed by two
23617 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
23618 // memory operation.
23619 unsigned Alignment = St->getAlignment();
23620 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
23621 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
23622 StVT == VT && !IsAligned) {
23623 unsigned NumElems = VT.getVectorNumElements();
23627 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
23628 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
23630 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
23631 SDValue Ptr0 = St->getBasePtr();
23632 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
23634 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
23635 St->getPointerInfo(), St->isVolatile(),
23636 St->isNonTemporal(), Alignment);
23637 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
23638 St->getPointerInfo(), St->isVolatile(),
23639 St->isNonTemporal(),
23640 std::min(16U, Alignment));
23641 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
23644 // Optimize trunc store (of multiple scalars) to shuffle and store.
23645 // First, pack all of the elements in one place. Next, store to memory
23646 // in fewer chunks.
23647 if (St->isTruncatingStore() && VT.isVector()) {
23648 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23649 unsigned NumElems = VT.getVectorNumElements();
23650 assert(StVT != VT && "Cannot truncate to the same type");
23651 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23652 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23654 // From, To sizes and ElemCount must be pow of two
23655 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
23656 // We are going to use the original vector elt for storing.
23657 // Accumulated smaller vector elements must be a multiple of the store size.
23658 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
23660 unsigned SizeRatio = FromSz / ToSz;
23662 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23664 // Create a type on which we perform the shuffle
23665 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23666 StVT.getScalarType(), NumElems*SizeRatio);
23668 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23670 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
23671 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
23672 for (unsigned i = 0; i != NumElems; ++i)
23673 ShuffleVec[i] = i * SizeRatio;
23675 // Can't shuffle using an illegal type.
23676 if (!TLI.isTypeLegal(WideVecVT))
23679 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23680 DAG.getUNDEF(WideVecVT),
23682 // At this point all of the data is stored at the bottom of the
23683 // register. We now need to save it to mem.
23685 // Find the largest store unit
23686 MVT StoreType = MVT::i8;
23687 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
23688 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
23689 MVT Tp = (MVT::SimpleValueType)tp;
23690 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
23694 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
23695 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
23696 (64 <= NumElems * ToSz))
23697 StoreType = MVT::f64;
23699 // Bitcast the original vector into a vector of store-size units
23700 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
23701 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
23702 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
23703 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
23704 SmallVector<SDValue, 8> Chains;
23705 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
23706 TLI.getPointerTy());
23707 SDValue Ptr = St->getBasePtr();
23709 // Perform one or more big stores into memory.
23710 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
23711 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
23712 StoreType, ShuffWide,
23713 DAG.getIntPtrConstant(i));
23714 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
23715 St->getPointerInfo(), St->isVolatile(),
23716 St->isNonTemporal(), St->getAlignment());
23717 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23718 Chains.push_back(Ch);
23721 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
23724 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
23725 // the FP state in cases where an emms may be missing.
23726 // A preferable solution to the general problem is to figure out the right
23727 // places to insert EMMS. This qualifies as a quick hack.
23729 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
23730 if (VT.getSizeInBits() != 64)
23733 const Function *F = DAG.getMachineFunction().getFunction();
23734 bool NoImplicitFloatOps = F->getAttributes().
23735 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
23736 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
23737 && Subtarget->hasSSE2();
23738 if ((VT.isVector() ||
23739 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
23740 isa<LoadSDNode>(St->getValue()) &&
23741 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
23742 St->getChain().hasOneUse() && !St->isVolatile()) {
23743 SDNode* LdVal = St->getValue().getNode();
23744 LoadSDNode *Ld = nullptr;
23745 int TokenFactorIndex = -1;
23746 SmallVector<SDValue, 8> Ops;
23747 SDNode* ChainVal = St->getChain().getNode();
23748 // Must be a store of a load. We currently handle two cases: the load
23749 // is a direct child, and it's under an intervening TokenFactor. It is
23750 // possible to dig deeper under nested TokenFactors.
23751 if (ChainVal == LdVal)
23752 Ld = cast<LoadSDNode>(St->getChain());
23753 else if (St->getValue().hasOneUse() &&
23754 ChainVal->getOpcode() == ISD::TokenFactor) {
23755 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
23756 if (ChainVal->getOperand(i).getNode() == LdVal) {
23757 TokenFactorIndex = i;
23758 Ld = cast<LoadSDNode>(St->getValue());
23760 Ops.push_back(ChainVal->getOperand(i));
23764 if (!Ld || !ISD::isNormalLoad(Ld))
23767 // If this is not the MMX case, i.e. we are just turning i64 load/store
23768 // into f64 load/store, avoid the transformation if there are multiple
23769 // uses of the loaded value.
23770 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
23775 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
23776 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
23778 if (Subtarget->is64Bit() || F64IsLegal) {
23779 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
23780 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
23781 Ld->getPointerInfo(), Ld->isVolatile(),
23782 Ld->isNonTemporal(), Ld->isInvariant(),
23783 Ld->getAlignment());
23784 SDValue NewChain = NewLd.getValue(1);
23785 if (TokenFactorIndex != -1) {
23786 Ops.push_back(NewChain);
23787 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23789 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
23790 St->getPointerInfo(),
23791 St->isVolatile(), St->isNonTemporal(),
23792 St->getAlignment());
23795 // Otherwise, lower to two pairs of 32-bit loads / stores.
23796 SDValue LoAddr = Ld->getBasePtr();
23797 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
23798 DAG.getConstant(4, MVT::i32));
23800 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
23801 Ld->getPointerInfo(),
23802 Ld->isVolatile(), Ld->isNonTemporal(),
23803 Ld->isInvariant(), Ld->getAlignment());
23804 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
23805 Ld->getPointerInfo().getWithOffset(4),
23806 Ld->isVolatile(), Ld->isNonTemporal(),
23808 MinAlign(Ld->getAlignment(), 4));
23810 SDValue NewChain = LoLd.getValue(1);
23811 if (TokenFactorIndex != -1) {
23812 Ops.push_back(LoLd);
23813 Ops.push_back(HiLd);
23814 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23817 LoAddr = St->getBasePtr();
23818 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
23819 DAG.getConstant(4, MVT::i32));
23821 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
23822 St->getPointerInfo(),
23823 St->isVolatile(), St->isNonTemporal(),
23824 St->getAlignment());
23825 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
23826 St->getPointerInfo().getWithOffset(4),
23828 St->isNonTemporal(),
23829 MinAlign(St->getAlignment(), 4));
23830 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
23835 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
23836 /// and return the operands for the horizontal operation in LHS and RHS. A
23837 /// horizontal operation performs the binary operation on successive elements
23838 /// of its first operand, then on successive elements of its second operand,
23839 /// returning the resulting values in a vector. For example, if
23840 /// A = < float a0, float a1, float a2, float a3 >
23842 /// B = < float b0, float b1, float b2, float b3 >
23843 /// then the result of doing a horizontal operation on A and B is
23844 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
23845 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
23846 /// A horizontal-op B, for some already available A and B, and if so then LHS is
23847 /// set to A, RHS to B, and the routine returns 'true'.
23848 /// Note that the binary operation should have the property that if one of the
23849 /// operands is UNDEF then the result is UNDEF.
23850 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
23851 // Look for the following pattern: if
23852 // A = < float a0, float a1, float a2, float a3 >
23853 // B = < float b0, float b1, float b2, float b3 >
23855 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
23856 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
23857 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
23858 // which is A horizontal-op B.
23860 // At least one of the operands should be a vector shuffle.
23861 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
23862 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
23865 MVT VT = LHS.getSimpleValueType();
23867 assert((VT.is128BitVector() || VT.is256BitVector()) &&
23868 "Unsupported vector type for horizontal add/sub");
23870 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
23871 // operate independently on 128-bit lanes.
23872 unsigned NumElts = VT.getVectorNumElements();
23873 unsigned NumLanes = VT.getSizeInBits()/128;
23874 unsigned NumLaneElts = NumElts / NumLanes;
23875 assert((NumLaneElts % 2 == 0) &&
23876 "Vector type should have an even number of elements in each lane");
23877 unsigned HalfLaneElts = NumLaneElts/2;
23879 // View LHS in the form
23880 // LHS = VECTOR_SHUFFLE A, B, LMask
23881 // If LHS is not a shuffle then pretend it is the shuffle
23882 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
23883 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
23886 SmallVector<int, 16> LMask(NumElts);
23887 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23888 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
23889 A = LHS.getOperand(0);
23890 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
23891 B = LHS.getOperand(1);
23892 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
23893 std::copy(Mask.begin(), Mask.end(), LMask.begin());
23895 if (LHS.getOpcode() != ISD::UNDEF)
23897 for (unsigned i = 0; i != NumElts; ++i)
23901 // Likewise, view RHS in the form
23902 // RHS = VECTOR_SHUFFLE C, D, RMask
23904 SmallVector<int, 16> RMask(NumElts);
23905 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23906 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
23907 C = RHS.getOperand(0);
23908 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
23909 D = RHS.getOperand(1);
23910 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
23911 std::copy(Mask.begin(), Mask.end(), RMask.begin());
23913 if (RHS.getOpcode() != ISD::UNDEF)
23915 for (unsigned i = 0; i != NumElts; ++i)
23919 // Check that the shuffles are both shuffling the same vectors.
23920 if (!(A == C && B == D) && !(A == D && B == C))
23923 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
23924 if (!A.getNode() && !B.getNode())
23927 // If A and B occur in reverse order in RHS, then "swap" them (which means
23928 // rewriting the mask).
23930 CommuteVectorShuffleMask(RMask, NumElts);
23932 // At this point LHS and RHS are equivalent to
23933 // LHS = VECTOR_SHUFFLE A, B, LMask
23934 // RHS = VECTOR_SHUFFLE A, B, RMask
23935 // Check that the masks correspond to performing a horizontal operation.
23936 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
23937 for (unsigned i = 0; i != NumLaneElts; ++i) {
23938 int LIdx = LMask[i+l], RIdx = RMask[i+l];
23940 // Ignore any UNDEF components.
23941 if (LIdx < 0 || RIdx < 0 ||
23942 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
23943 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
23946 // Check that successive elements are being operated on. If not, this is
23947 // not a horizontal operation.
23948 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
23949 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
23950 if (!(LIdx == Index && RIdx == Index + 1) &&
23951 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
23956 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
23957 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
23961 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
23962 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
23963 const X86Subtarget *Subtarget) {
23964 EVT VT = N->getValueType(0);
23965 SDValue LHS = N->getOperand(0);
23966 SDValue RHS = N->getOperand(1);
23968 // Try to synthesize horizontal adds from adds of shuffles.
23969 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23970 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23971 isHorizontalBinOp(LHS, RHS, true))
23972 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
23976 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
23977 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
23978 const X86Subtarget *Subtarget) {
23979 EVT VT = N->getValueType(0);
23980 SDValue LHS = N->getOperand(0);
23981 SDValue RHS = N->getOperand(1);
23983 // Try to synthesize horizontal subs from subs of shuffles.
23984 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23985 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23986 isHorizontalBinOp(LHS, RHS, false))
23987 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
23991 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
23992 /// X86ISD::FXOR nodes.
23993 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
23994 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
23995 // F[X]OR(0.0, x) -> x
23996 // F[X]OR(x, 0.0) -> x
23997 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23998 if (C->getValueAPF().isPosZero())
23999 return N->getOperand(1);
24000 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24001 if (C->getValueAPF().isPosZero())
24002 return N->getOperand(0);
24006 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
24007 /// X86ISD::FMAX nodes.
24008 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24009 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24011 // Only perform optimizations if UnsafeMath is used.
24012 if (!DAG.getTarget().Options.UnsafeFPMath)
24015 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24016 // into FMINC and FMAXC, which are Commutative operations.
24017 unsigned NewOp = 0;
24018 switch (N->getOpcode()) {
24019 default: llvm_unreachable("unknown opcode");
24020 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24021 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
24024 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
24025 N->getOperand(0), N->getOperand(1));
24028 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
24029 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
24030 // FAND(0.0, x) -> 0.0
24031 // FAND(x, 0.0) -> 0.0
24032 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24033 if (C->getValueAPF().isPosZero())
24034 return N->getOperand(0);
24035 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24036 if (C->getValueAPF().isPosZero())
24037 return N->getOperand(1);
24041 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
24042 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
24043 // FANDN(x, 0.0) -> 0.0
24044 // FANDN(0.0, x) -> x
24045 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24046 if (C->getValueAPF().isPosZero())
24047 return N->getOperand(1);
24048 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24049 if (C->getValueAPF().isPosZero())
24050 return N->getOperand(1);
24054 static SDValue PerformBTCombine(SDNode *N,
24056 TargetLowering::DAGCombinerInfo &DCI) {
24057 // BT ignores high bits in the bit index operand.
24058 SDValue Op1 = N->getOperand(1);
24059 if (Op1.hasOneUse()) {
24060 unsigned BitWidth = Op1.getValueSizeInBits();
24061 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
24062 APInt KnownZero, KnownOne;
24063 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
24064 !DCI.isBeforeLegalizeOps());
24065 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24066 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
24067 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
24068 DCI.CommitTargetLoweringOpt(TLO);
24073 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
24074 SDValue Op = N->getOperand(0);
24075 if (Op.getOpcode() == ISD::BITCAST)
24076 Op = Op.getOperand(0);
24077 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
24078 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
24079 VT.getVectorElementType().getSizeInBits() ==
24080 OpVT.getVectorElementType().getSizeInBits()) {
24081 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
24086 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
24087 const X86Subtarget *Subtarget) {
24088 EVT VT = N->getValueType(0);
24089 if (!VT.isVector())
24092 SDValue N0 = N->getOperand(0);
24093 SDValue N1 = N->getOperand(1);
24094 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
24097 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
24098 // both SSE and AVX2 since there is no sign-extended shift right
24099 // operation on a vector with 64-bit elements.
24100 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
24101 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
24102 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
24103 N0.getOpcode() == ISD::SIGN_EXTEND)) {
24104 SDValue N00 = N0.getOperand(0);
24106 // EXTLOAD has a better solution on AVX2,
24107 // it may be replaced with X86ISD::VSEXT node.
24108 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
24109 if (!ISD::isNormalLoad(N00.getNode()))
24112 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
24113 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
24115 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24121 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24122 TargetLowering::DAGCombinerInfo &DCI,
24123 const X86Subtarget *Subtarget) {
24124 if (!DCI.isBeforeLegalizeOps())
24127 if (!Subtarget->hasFp256())
24130 EVT VT = N->getValueType(0);
24131 if (VT.isVector() && VT.getSizeInBits() == 256) {
24132 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24140 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24141 const X86Subtarget* Subtarget) {
24143 EVT VT = N->getValueType(0);
24145 // Let legalize expand this if it isn't a legal type yet.
24146 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
24149 EVT ScalarVT = VT.getScalarType();
24150 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
24151 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
24154 SDValue A = N->getOperand(0);
24155 SDValue B = N->getOperand(1);
24156 SDValue C = N->getOperand(2);
24158 bool NegA = (A.getOpcode() == ISD::FNEG);
24159 bool NegB = (B.getOpcode() == ISD::FNEG);
24160 bool NegC = (C.getOpcode() == ISD::FNEG);
24162 // Negative multiplication when NegA xor NegB
24163 bool NegMul = (NegA != NegB);
24165 A = A.getOperand(0);
24167 B = B.getOperand(0);
24169 C = C.getOperand(0);
24173 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
24175 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
24177 return DAG.getNode(Opcode, dl, VT, A, B, C);
24180 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
24181 TargetLowering::DAGCombinerInfo &DCI,
24182 const X86Subtarget *Subtarget) {
24183 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
24184 // (and (i32 x86isd::setcc_carry), 1)
24185 // This eliminates the zext. This transformation is necessary because
24186 // ISD::SETCC is always legalized to i8.
24188 SDValue N0 = N->getOperand(0);
24189 EVT VT = N->getValueType(0);
24191 if (N0.getOpcode() == ISD::AND &&
24193 N0.getOperand(0).hasOneUse()) {
24194 SDValue N00 = N0.getOperand(0);
24195 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24196 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24197 if (!C || C->getZExtValue() != 1)
24199 return DAG.getNode(ISD::AND, dl, VT,
24200 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24201 N00.getOperand(0), N00.getOperand(1)),
24202 DAG.getConstant(1, VT));
24206 if (N0.getOpcode() == ISD::TRUNCATE &&
24208 N0.getOperand(0).hasOneUse()) {
24209 SDValue N00 = N0.getOperand(0);
24210 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24211 return DAG.getNode(ISD::AND, dl, VT,
24212 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24213 N00.getOperand(0), N00.getOperand(1)),
24214 DAG.getConstant(1, VT));
24217 if (VT.is256BitVector()) {
24218 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24226 // Optimize x == -y --> x+y == 0
24227 // x != -y --> x+y != 0
24228 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
24229 const X86Subtarget* Subtarget) {
24230 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
24231 SDValue LHS = N->getOperand(0);
24232 SDValue RHS = N->getOperand(1);
24233 EVT VT = N->getValueType(0);
24236 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
24237 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
24238 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
24239 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24240 LHS.getValueType(), RHS, LHS.getOperand(1));
24241 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24242 addV, DAG.getConstant(0, addV.getValueType()), CC);
24244 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
24245 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
24246 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
24247 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
24248 RHS.getValueType(), LHS, RHS.getOperand(1));
24249 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
24250 addV, DAG.getConstant(0, addV.getValueType()), CC);
24253 if (VT.getScalarType() == MVT::i1) {
24254 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24255 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24256 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
24257 if (!IsSEXT0 && !IsVZero0)
24259 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
24260 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24261 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24263 if (!IsSEXT1 && !IsVZero1)
24266 if (IsSEXT0 && IsVZero1) {
24267 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
24268 if (CC == ISD::SETEQ)
24269 return DAG.getNOT(DL, LHS.getOperand(0), VT);
24270 return LHS.getOperand(0);
24272 if (IsSEXT1 && IsVZero0) {
24273 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
24274 if (CC == ISD::SETEQ)
24275 return DAG.getNOT(DL, RHS.getOperand(0), VT);
24276 return RHS.getOperand(0);
24283 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
24284 const X86Subtarget *Subtarget) {
24286 MVT VT = N->getOperand(1)->getSimpleValueType(0);
24287 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
24288 "X86insertps is only defined for v4x32");
24290 SDValue Ld = N->getOperand(1);
24291 if (MayFoldLoad(Ld)) {
24292 // Extract the countS bits from the immediate so we can get the proper
24293 // address when narrowing the vector load to a specific element.
24294 // When the second source op is a memory address, interps doesn't use
24295 // countS and just gets an f32 from that address.
24296 unsigned DestIndex =
24297 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
24298 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
24302 // Create this as a scalar to vector to match the instruction pattern.
24303 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
24304 // countS bits are ignored when loading from memory on insertps, which
24305 // means we don't need to explicitly set them to 0.
24306 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
24307 LoadScalarToVector, N->getOperand(2));
24310 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
24311 // as "sbb reg,reg", since it can be extended without zext and produces
24312 // an all-ones bit which is more useful than 0/1 in some cases.
24313 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
24316 return DAG.getNode(ISD::AND, DL, VT,
24317 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24318 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
24319 DAG.getConstant(1, VT));
24320 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
24321 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
24322 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24323 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
24326 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
24327 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
24328 TargetLowering::DAGCombinerInfo &DCI,
24329 const X86Subtarget *Subtarget) {
24331 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
24332 SDValue EFLAGS = N->getOperand(1);
24334 if (CC == X86::COND_A) {
24335 // Try to convert COND_A into COND_B in an attempt to facilitate
24336 // materializing "setb reg".
24338 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
24339 // cannot take an immediate as its first operand.
24341 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
24342 EFLAGS.getValueType().isInteger() &&
24343 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
24344 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
24345 EFLAGS.getNode()->getVTList(),
24346 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
24347 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
24348 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
24352 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
24353 // a zext and produces an all-ones bit which is more useful than 0/1 in some
24355 if (CC == X86::COND_B)
24356 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
24360 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24361 if (Flags.getNode()) {
24362 SDValue Cond = DAG.getConstant(CC, MVT::i8);
24363 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
24369 // Optimize branch condition evaluation.
24371 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
24372 TargetLowering::DAGCombinerInfo &DCI,
24373 const X86Subtarget *Subtarget) {
24375 SDValue Chain = N->getOperand(0);
24376 SDValue Dest = N->getOperand(1);
24377 SDValue EFLAGS = N->getOperand(3);
24378 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
24382 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
24383 if (Flags.getNode()) {
24384 SDValue Cond = DAG.getConstant(CC, MVT::i8);
24385 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
24392 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
24393 SelectionDAG &DAG) {
24394 // Take advantage of vector comparisons producing 0 or -1 in each lane to
24395 // optimize away operation when it's from a constant.
24397 // The general transformation is:
24398 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
24399 // AND(VECTOR_CMP(x,y), constant2)
24400 // constant2 = UNARYOP(constant)
24402 // Early exit if this isn't a vector operation, the operand of the
24403 // unary operation isn't a bitwise AND, or if the sizes of the operations
24404 // aren't the same.
24405 EVT VT = N->getValueType(0);
24406 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
24407 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
24408 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
24411 // Now check that the other operand of the AND is a constant. We could
24412 // make the transformation for non-constant splats as well, but it's unclear
24413 // that would be a benefit as it would not eliminate any operations, just
24414 // perform one more step in scalar code before moving to the vector unit.
24415 if (BuildVectorSDNode *BV =
24416 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
24417 // Bail out if the vector isn't a constant.
24418 if (!BV->isConstant())
24421 // Everything checks out. Build up the new and improved node.
24423 EVT IntVT = BV->getValueType(0);
24424 // Create a new constant of the appropriate type for the transformed
24426 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
24427 // The AND node needs bitcasts to/from an integer vector type around it.
24428 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
24429 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
24430 N->getOperand(0)->getOperand(0), MaskConst);
24431 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
24438 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
24439 const X86TargetLowering *XTLI) {
24440 // First try to optimize away the conversion entirely when it's
24441 // conditionally from a constant. Vectors only.
24442 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
24443 if (Res != SDValue())
24446 // Now move on to more general possibilities.
24447 SDValue Op0 = N->getOperand(0);
24448 EVT InVT = Op0->getValueType(0);
24450 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
24451 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
24453 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
24454 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
24455 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
24458 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
24459 // a 32-bit target where SSE doesn't support i64->FP operations.
24460 if (Op0.getOpcode() == ISD::LOAD) {
24461 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
24462 EVT VT = Ld->getValueType(0);
24463 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
24464 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
24465 !XTLI->getSubtarget()->is64Bit() &&
24467 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
24468 Ld->getChain(), Op0, DAG);
24469 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
24476 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
24477 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
24478 X86TargetLowering::DAGCombinerInfo &DCI) {
24479 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
24480 // the result is either zero or one (depending on the input carry bit).
24481 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
24482 if (X86::isZeroNode(N->getOperand(0)) &&
24483 X86::isZeroNode(N->getOperand(1)) &&
24484 // We don't have a good way to replace an EFLAGS use, so only do this when
24486 SDValue(N, 1).use_empty()) {
24488 EVT VT = N->getValueType(0);
24489 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
24490 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
24491 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
24492 DAG.getConstant(X86::COND_B,MVT::i8),
24494 DAG.getConstant(1, VT));
24495 return DCI.CombineTo(N, Res1, CarryOut);
24501 // fold (add Y, (sete X, 0)) -> adc 0, Y
24502 // (add Y, (setne X, 0)) -> sbb -1, Y
24503 // (sub (sete X, 0), Y) -> sbb 0, Y
24504 // (sub (setne X, 0), Y) -> adc -1, Y
24505 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
24508 // Look through ZExts.
24509 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
24510 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
24513 SDValue SetCC = Ext.getOperand(0);
24514 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
24517 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
24518 if (CC != X86::COND_E && CC != X86::COND_NE)
24521 SDValue Cmp = SetCC.getOperand(1);
24522 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
24523 !X86::isZeroNode(Cmp.getOperand(1)) ||
24524 !Cmp.getOperand(0).getValueType().isInteger())
24527 SDValue CmpOp0 = Cmp.getOperand(0);
24528 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
24529 DAG.getConstant(1, CmpOp0.getValueType()));
24531 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
24532 if (CC == X86::COND_NE)
24533 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
24534 DL, OtherVal.getValueType(), OtherVal,
24535 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
24536 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
24537 DL, OtherVal.getValueType(), OtherVal,
24538 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
24541 /// PerformADDCombine - Do target-specific dag combines on integer adds.
24542 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
24543 const X86Subtarget *Subtarget) {
24544 EVT VT = N->getValueType(0);
24545 SDValue Op0 = N->getOperand(0);
24546 SDValue Op1 = N->getOperand(1);
24548 // Try to synthesize horizontal adds from adds of shuffles.
24549 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24550 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24551 isHorizontalBinOp(Op0, Op1, true))
24552 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
24554 return OptimizeConditionalInDecrement(N, DAG);
24557 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
24558 const X86Subtarget *Subtarget) {
24559 SDValue Op0 = N->getOperand(0);
24560 SDValue Op1 = N->getOperand(1);
24562 // X86 can't encode an immediate LHS of a sub. See if we can push the
24563 // negation into a preceding instruction.
24564 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
24565 // If the RHS of the sub is a XOR with one use and a constant, invert the
24566 // immediate. Then add one to the LHS of the sub so we can turn
24567 // X-Y -> X+~Y+1, saving one register.
24568 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
24569 isa<ConstantSDNode>(Op1.getOperand(1))) {
24570 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
24571 EVT VT = Op0.getValueType();
24572 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
24574 DAG.getConstant(~XorC, VT));
24575 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
24576 DAG.getConstant(C->getAPIntValue()+1, VT));
24580 // Try to synthesize horizontal adds from adds of shuffles.
24581 EVT VT = N->getValueType(0);
24582 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24583 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24584 isHorizontalBinOp(Op0, Op1, true))
24585 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
24587 return OptimizeConditionalInDecrement(N, DAG);
24590 /// performVZEXTCombine - Performs build vector combines
24591 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
24592 TargetLowering::DAGCombinerInfo &DCI,
24593 const X86Subtarget *Subtarget) {
24595 MVT VT = N->getSimpleValueType(0);
24596 SDValue Op = N->getOperand(0);
24597 MVT OpVT = Op.getSimpleValueType();
24598 MVT OpEltVT = OpVT.getVectorElementType();
24599 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
24601 // (vzext (bitcast (vzext (x)) -> (vzext x)
24603 while (V.getOpcode() == ISD::BITCAST)
24604 V = V.getOperand(0);
24606 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
24607 MVT InnerVT = V.getSimpleValueType();
24608 MVT InnerEltVT = InnerVT.getVectorElementType();
24610 // If the element sizes match exactly, we can just do one larger vzext. This
24611 // is always an exact type match as vzext operates on integer types.
24612 if (OpEltVT == InnerEltVT) {
24613 assert(OpVT == InnerVT && "Types must match for vzext!");
24614 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
24617 // The only other way we can combine them is if only a single element of the
24618 // inner vzext is used in the input to the outer vzext.
24619 if (InnerEltVT.getSizeInBits() < InputBits)
24622 // In this case, the inner vzext is completely dead because we're going to
24623 // only look at bits inside of the low element. Just do the outer vzext on
24624 // a bitcast of the input to the inner.
24625 return DAG.getNode(X86ISD::VZEXT, DL, VT,
24626 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
24629 // Check if we can bypass extracting and re-inserting an element of an input
24630 // vector. Essentialy:
24631 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
24632 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
24633 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
24634 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
24635 SDValue ExtractedV = V.getOperand(0);
24636 SDValue OrigV = ExtractedV.getOperand(0);
24637 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
24638 if (ExtractIdx->getZExtValue() == 0) {
24639 MVT OrigVT = OrigV.getSimpleValueType();
24640 // Extract a subvector if necessary...
24641 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
24642 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
24643 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
24644 OrigVT.getVectorNumElements() / Ratio);
24645 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
24646 DAG.getIntPtrConstant(0));
24648 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
24649 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
24656 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
24657 DAGCombinerInfo &DCI) const {
24658 SelectionDAG &DAG = DCI.DAG;
24659 switch (N->getOpcode()) {
24661 case ISD::EXTRACT_VECTOR_ELT:
24662 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
24664 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
24665 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
24666 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
24667 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
24668 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
24669 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
24672 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
24673 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
24674 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
24675 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
24676 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
24677 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
24678 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
24679 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
24680 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
24682 case X86ISD::FOR: return PerformFORCombine(N, DAG);
24684 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
24685 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
24686 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
24687 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
24688 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
24689 case ISD::ANY_EXTEND:
24690 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
24691 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
24692 case ISD::SIGN_EXTEND_INREG:
24693 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
24694 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
24695 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
24696 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
24697 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
24698 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
24699 case X86ISD::SHUFP: // Handle all target specific shuffles
24700 case X86ISD::PALIGNR:
24701 case X86ISD::UNPCKH:
24702 case X86ISD::UNPCKL:
24703 case X86ISD::MOVHLPS:
24704 case X86ISD::MOVLHPS:
24705 case X86ISD::PSHUFB:
24706 case X86ISD::PSHUFD:
24707 case X86ISD::PSHUFHW:
24708 case X86ISD::PSHUFLW:
24709 case X86ISD::MOVSS:
24710 case X86ISD::MOVSD:
24711 case X86ISD::VPERMILPI:
24712 case X86ISD::VPERM2X128:
24713 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
24714 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
24715 case ISD::INTRINSIC_WO_CHAIN:
24716 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
24717 case X86ISD::INSERTPS:
24718 return PerformINSERTPSCombine(N, DAG, Subtarget);
24719 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
24725 /// isTypeDesirableForOp - Return true if the target has native support for
24726 /// the specified value type and it is 'desirable' to use the type for the
24727 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
24728 /// instruction encodings are longer and some i16 instructions are slow.
24729 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
24730 if (!isTypeLegal(VT))
24732 if (VT != MVT::i16)
24739 case ISD::SIGN_EXTEND:
24740 case ISD::ZERO_EXTEND:
24741 case ISD::ANY_EXTEND:
24754 /// IsDesirableToPromoteOp - This method query the target whether it is
24755 /// beneficial for dag combiner to promote the specified node. If true, it
24756 /// should return the desired promotion type by reference.
24757 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
24758 EVT VT = Op.getValueType();
24759 if (VT != MVT::i16)
24762 bool Promote = false;
24763 bool Commute = false;
24764 switch (Op.getOpcode()) {
24767 LoadSDNode *LD = cast<LoadSDNode>(Op);
24768 // If the non-extending load has a single use and it's not live out, then it
24769 // might be folded.
24770 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
24771 Op.hasOneUse()*/) {
24772 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
24773 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
24774 // The only case where we'd want to promote LOAD (rather then it being
24775 // promoted as an operand is when it's only use is liveout.
24776 if (UI->getOpcode() != ISD::CopyToReg)
24783 case ISD::SIGN_EXTEND:
24784 case ISD::ZERO_EXTEND:
24785 case ISD::ANY_EXTEND:
24790 SDValue N0 = Op.getOperand(0);
24791 // Look out for (store (shl (load), x)).
24792 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
24805 SDValue N0 = Op.getOperand(0);
24806 SDValue N1 = Op.getOperand(1);
24807 if (!Commute && MayFoldLoad(N1))
24809 // Avoid disabling potential load folding opportunities.
24810 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
24812 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
24822 //===----------------------------------------------------------------------===//
24823 // X86 Inline Assembly Support
24824 //===----------------------------------------------------------------------===//
24827 // Helper to match a string separated by whitespace.
24828 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
24829 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
24831 for (unsigned i = 0, e = args.size(); i != e; ++i) {
24832 StringRef piece(*args[i]);
24833 if (!s.startswith(piece)) // Check if the piece matches.
24836 s = s.substr(piece.size());
24837 StringRef::size_type pos = s.find_first_not_of(" \t");
24838 if (pos == 0) // We matched a prefix.
24846 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
24849 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
24851 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
24852 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
24853 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
24854 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
24856 if (AsmPieces.size() == 3)
24858 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
24865 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
24866 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
24868 std::string AsmStr = IA->getAsmString();
24870 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
24871 if (!Ty || Ty->getBitWidth() % 16 != 0)
24874 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
24875 SmallVector<StringRef, 4> AsmPieces;
24876 SplitString(AsmStr, AsmPieces, ";\n");
24878 switch (AsmPieces.size()) {
24879 default: return false;
24881 // FIXME: this should verify that we are targeting a 486 or better. If not,
24882 // we will turn this bswap into something that will be lowered to logical
24883 // ops instead of emitting the bswap asm. For now, we don't support 486 or
24884 // lower so don't worry about this.
24886 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
24887 matchAsm(AsmPieces[0], "bswapl", "$0") ||
24888 matchAsm(AsmPieces[0], "bswapq", "$0") ||
24889 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
24890 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
24891 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
24892 // No need to check constraints, nothing other than the equivalent of
24893 // "=r,0" would be valid here.
24894 return IntrinsicLowering::LowerToByteSwap(CI);
24897 // rorw $$8, ${0:w} --> llvm.bswap.i16
24898 if (CI->getType()->isIntegerTy(16) &&
24899 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24900 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
24901 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
24903 const std::string &ConstraintsStr = IA->getConstraintString();
24904 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24905 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24906 if (clobbersFlagRegisters(AsmPieces))
24907 return IntrinsicLowering::LowerToByteSwap(CI);
24911 if (CI->getType()->isIntegerTy(32) &&
24912 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
24913 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
24914 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
24915 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
24917 const std::string &ConstraintsStr = IA->getConstraintString();
24918 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
24919 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
24920 if (clobbersFlagRegisters(AsmPieces))
24921 return IntrinsicLowering::LowerToByteSwap(CI);
24924 if (CI->getType()->isIntegerTy(64)) {
24925 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
24926 if (Constraints.size() >= 2 &&
24927 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
24928 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
24929 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
24930 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
24931 matchAsm(AsmPieces[1], "bswap", "%edx") &&
24932 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
24933 return IntrinsicLowering::LowerToByteSwap(CI);
24941 /// getConstraintType - Given a constraint letter, return the type of
24942 /// constraint it is for this target.
24943 X86TargetLowering::ConstraintType
24944 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
24945 if (Constraint.size() == 1) {
24946 switch (Constraint[0]) {
24957 return C_RegisterClass;
24981 return TargetLowering::getConstraintType(Constraint);
24984 /// Examine constraint type and operand type and determine a weight value.
24985 /// This object must already have been set up with the operand type
24986 /// and the current alternative constraint selected.
24987 TargetLowering::ConstraintWeight
24988 X86TargetLowering::getSingleConstraintMatchWeight(
24989 AsmOperandInfo &info, const char *constraint) const {
24990 ConstraintWeight weight = CW_Invalid;
24991 Value *CallOperandVal = info.CallOperandVal;
24992 // If we don't have a value, we can't do a match,
24993 // but allow it at the lowest weight.
24994 if (!CallOperandVal)
24996 Type *type = CallOperandVal->getType();
24997 // Look at the constraint type.
24998 switch (*constraint) {
25000 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
25011 if (CallOperandVal->getType()->isIntegerTy())
25012 weight = CW_SpecificReg;
25017 if (type->isFloatingPointTy())
25018 weight = CW_SpecificReg;
25021 if (type->isX86_MMXTy() && Subtarget->hasMMX())
25022 weight = CW_SpecificReg;
25026 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
25027 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
25028 weight = CW_Register;
25031 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
25032 if (C->getZExtValue() <= 31)
25033 weight = CW_Constant;
25037 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25038 if (C->getZExtValue() <= 63)
25039 weight = CW_Constant;
25043 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25044 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
25045 weight = CW_Constant;
25049 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25050 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
25051 weight = CW_Constant;
25055 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25056 if (C->getZExtValue() <= 3)
25057 weight = CW_Constant;
25061 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25062 if (C->getZExtValue() <= 0xff)
25063 weight = CW_Constant;
25068 if (dyn_cast<ConstantFP>(CallOperandVal)) {
25069 weight = CW_Constant;
25073 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25074 if ((C->getSExtValue() >= -0x80000000LL) &&
25075 (C->getSExtValue() <= 0x7fffffffLL))
25076 weight = CW_Constant;
25080 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25081 if (C->getZExtValue() <= 0xffffffff)
25082 weight = CW_Constant;
25089 /// LowerXConstraint - try to replace an X constraint, which matches anything,
25090 /// with another that has more specific requirements based on the type of the
25091 /// corresponding operand.
25092 const char *X86TargetLowering::
25093 LowerXConstraint(EVT ConstraintVT) const {
25094 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
25095 // 'f' like normal targets.
25096 if (ConstraintVT.isFloatingPoint()) {
25097 if (Subtarget->hasSSE2())
25099 if (Subtarget->hasSSE1())
25103 return TargetLowering::LowerXConstraint(ConstraintVT);
25106 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
25107 /// vector. If it is invalid, don't add anything to Ops.
25108 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
25109 std::string &Constraint,
25110 std::vector<SDValue>&Ops,
25111 SelectionDAG &DAG) const {
25114 // Only support length 1 constraints for now.
25115 if (Constraint.length() > 1) return;
25117 char ConstraintLetter = Constraint[0];
25118 switch (ConstraintLetter) {
25121 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25122 if (C->getZExtValue() <= 31) {
25123 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25129 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25130 if (C->getZExtValue() <= 63) {
25131 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25137 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25138 if (isInt<8>(C->getSExtValue())) {
25139 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25145 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25146 if (C->getZExtValue() <= 255) {
25147 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25153 // 32-bit signed value
25154 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25155 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25156 C->getSExtValue())) {
25157 // Widen to 64 bits here to get it sign extended.
25158 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
25161 // FIXME gcc accepts some relocatable values here too, but only in certain
25162 // memory models; it's complicated.
25167 // 32-bit unsigned value
25168 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25169 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25170 C->getZExtValue())) {
25171 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25175 // FIXME gcc accepts some relocatable values here too, but only in certain
25176 // memory models; it's complicated.
25180 // Literal immediates are always ok.
25181 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
25182 // Widen to 64 bits here to get it sign extended.
25183 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
25187 // In any sort of PIC mode addresses need to be computed at runtime by
25188 // adding in a register or some sort of table lookup. These can't
25189 // be used as immediates.
25190 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
25193 // If we are in non-pic codegen mode, we allow the address of a global (with
25194 // an optional displacement) to be used with 'i'.
25195 GlobalAddressSDNode *GA = nullptr;
25196 int64_t Offset = 0;
25198 // Match either (GA), (GA+C), (GA+C1+C2), etc.
25200 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
25201 Offset += GA->getOffset();
25203 } else if (Op.getOpcode() == ISD::ADD) {
25204 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25205 Offset += C->getZExtValue();
25206 Op = Op.getOperand(0);
25209 } else if (Op.getOpcode() == ISD::SUB) {
25210 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25211 Offset += -C->getZExtValue();
25212 Op = Op.getOperand(0);
25217 // Otherwise, this isn't something we can handle, reject it.
25221 const GlobalValue *GV = GA->getGlobal();
25222 // If we require an extra load to get this address, as in PIC mode, we
25223 // can't accept it.
25224 if (isGlobalStubReference(
25225 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
25228 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
25229 GA->getValueType(0), Offset);
25234 if (Result.getNode()) {
25235 Ops.push_back(Result);
25238 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
25241 std::pair<unsigned, const TargetRegisterClass*>
25242 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
25244 // First, see if this is a constraint that directly corresponds to an LLVM
25246 if (Constraint.size() == 1) {
25247 // GCC Constraint Letters
25248 switch (Constraint[0]) {
25250 // TODO: Slight differences here in allocation order and leaving
25251 // RIP in the class. Do they matter any more here than they do
25252 // in the normal allocation?
25253 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
25254 if (Subtarget->is64Bit()) {
25255 if (VT == MVT::i32 || VT == MVT::f32)
25256 return std::make_pair(0U, &X86::GR32RegClass);
25257 if (VT == MVT::i16)
25258 return std::make_pair(0U, &X86::GR16RegClass);
25259 if (VT == MVT::i8 || VT == MVT::i1)
25260 return std::make_pair(0U, &X86::GR8RegClass);
25261 if (VT == MVT::i64 || VT == MVT::f64)
25262 return std::make_pair(0U, &X86::GR64RegClass);
25265 // 32-bit fallthrough
25266 case 'Q': // Q_REGS
25267 if (VT == MVT::i32 || VT == MVT::f32)
25268 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
25269 if (VT == MVT::i16)
25270 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
25271 if (VT == MVT::i8 || VT == MVT::i1)
25272 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
25273 if (VT == MVT::i64)
25274 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
25276 case 'r': // GENERAL_REGS
25277 case 'l': // INDEX_REGS
25278 if (VT == MVT::i8 || VT == MVT::i1)
25279 return std::make_pair(0U, &X86::GR8RegClass);
25280 if (VT == MVT::i16)
25281 return std::make_pair(0U, &X86::GR16RegClass);
25282 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
25283 return std::make_pair(0U, &X86::GR32RegClass);
25284 return std::make_pair(0U, &X86::GR64RegClass);
25285 case 'R': // LEGACY_REGS
25286 if (VT == MVT::i8 || VT == MVT::i1)
25287 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
25288 if (VT == MVT::i16)
25289 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
25290 if (VT == MVT::i32 || !Subtarget->is64Bit())
25291 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
25292 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
25293 case 'f': // FP Stack registers.
25294 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
25295 // value to the correct fpstack register class.
25296 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
25297 return std::make_pair(0U, &X86::RFP32RegClass);
25298 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
25299 return std::make_pair(0U, &X86::RFP64RegClass);
25300 return std::make_pair(0U, &X86::RFP80RegClass);
25301 case 'y': // MMX_REGS if MMX allowed.
25302 if (!Subtarget->hasMMX()) break;
25303 return std::make_pair(0U, &X86::VR64RegClass);
25304 case 'Y': // SSE_REGS if SSE2 allowed
25305 if (!Subtarget->hasSSE2()) break;
25307 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
25308 if (!Subtarget->hasSSE1()) break;
25310 switch (VT.SimpleTy) {
25312 // Scalar SSE types.
25315 return std::make_pair(0U, &X86::FR32RegClass);
25318 return std::make_pair(0U, &X86::FR64RegClass);
25326 return std::make_pair(0U, &X86::VR128RegClass);
25334 return std::make_pair(0U, &X86::VR256RegClass);
25339 return std::make_pair(0U, &X86::VR512RegClass);
25345 // Use the default implementation in TargetLowering to convert the register
25346 // constraint into a member of a register class.
25347 std::pair<unsigned, const TargetRegisterClass*> Res;
25348 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
25350 // Not found as a standard register?
25352 // Map st(0) -> st(7) -> ST0
25353 if (Constraint.size() == 7 && Constraint[0] == '{' &&
25354 tolower(Constraint[1]) == 's' &&
25355 tolower(Constraint[2]) == 't' &&
25356 Constraint[3] == '(' &&
25357 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
25358 Constraint[5] == ')' &&
25359 Constraint[6] == '}') {
25361 Res.first = X86::FP0+Constraint[4]-'0';
25362 Res.second = &X86::RFP80RegClass;
25366 // GCC allows "st(0)" to be called just plain "st".
25367 if (StringRef("{st}").equals_lower(Constraint)) {
25368 Res.first = X86::FP0;
25369 Res.second = &X86::RFP80RegClass;
25374 if (StringRef("{flags}").equals_lower(Constraint)) {
25375 Res.first = X86::EFLAGS;
25376 Res.second = &X86::CCRRegClass;
25380 // 'A' means EAX + EDX.
25381 if (Constraint == "A") {
25382 Res.first = X86::EAX;
25383 Res.second = &X86::GR32_ADRegClass;
25389 // Otherwise, check to see if this is a register class of the wrong value
25390 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
25391 // turn into {ax},{dx}.
25392 if (Res.second->hasType(VT))
25393 return Res; // Correct type already, nothing to do.
25395 // All of the single-register GCC register classes map their values onto
25396 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
25397 // really want an 8-bit or 32-bit register, map to the appropriate register
25398 // class and return the appropriate register.
25399 if (Res.second == &X86::GR16RegClass) {
25400 if (VT == MVT::i8 || VT == MVT::i1) {
25401 unsigned DestReg = 0;
25402 switch (Res.first) {
25404 case X86::AX: DestReg = X86::AL; break;
25405 case X86::DX: DestReg = X86::DL; break;
25406 case X86::CX: DestReg = X86::CL; break;
25407 case X86::BX: DestReg = X86::BL; break;
25410 Res.first = DestReg;
25411 Res.second = &X86::GR8RegClass;
25413 } else if (VT == MVT::i32 || VT == MVT::f32) {
25414 unsigned DestReg = 0;
25415 switch (Res.first) {
25417 case X86::AX: DestReg = X86::EAX; break;
25418 case X86::DX: DestReg = X86::EDX; break;
25419 case X86::CX: DestReg = X86::ECX; break;
25420 case X86::BX: DestReg = X86::EBX; break;
25421 case X86::SI: DestReg = X86::ESI; break;
25422 case X86::DI: DestReg = X86::EDI; break;
25423 case X86::BP: DestReg = X86::EBP; break;
25424 case X86::SP: DestReg = X86::ESP; break;
25427 Res.first = DestReg;
25428 Res.second = &X86::GR32RegClass;
25430 } else if (VT == MVT::i64 || VT == MVT::f64) {
25431 unsigned DestReg = 0;
25432 switch (Res.first) {
25434 case X86::AX: DestReg = X86::RAX; break;
25435 case X86::DX: DestReg = X86::RDX; break;
25436 case X86::CX: DestReg = X86::RCX; break;
25437 case X86::BX: DestReg = X86::RBX; break;
25438 case X86::SI: DestReg = X86::RSI; break;
25439 case X86::DI: DestReg = X86::RDI; break;
25440 case X86::BP: DestReg = X86::RBP; break;
25441 case X86::SP: DestReg = X86::RSP; break;
25444 Res.first = DestReg;
25445 Res.second = &X86::GR64RegClass;
25448 } else if (Res.second == &X86::FR32RegClass ||
25449 Res.second == &X86::FR64RegClass ||
25450 Res.second == &X86::VR128RegClass ||
25451 Res.second == &X86::VR256RegClass ||
25452 Res.second == &X86::FR32XRegClass ||
25453 Res.second == &X86::FR64XRegClass ||
25454 Res.second == &X86::VR128XRegClass ||
25455 Res.second == &X86::VR256XRegClass ||
25456 Res.second == &X86::VR512RegClass) {
25457 // Handle references to XMM physical registers that got mapped into the
25458 // wrong class. This can happen with constraints like {xmm0} where the
25459 // target independent register mapper will just pick the first match it can
25460 // find, ignoring the required type.
25462 if (VT == MVT::f32 || VT == MVT::i32)
25463 Res.second = &X86::FR32RegClass;
25464 else if (VT == MVT::f64 || VT == MVT::i64)
25465 Res.second = &X86::FR64RegClass;
25466 else if (X86::VR128RegClass.hasType(VT))
25467 Res.second = &X86::VR128RegClass;
25468 else if (X86::VR256RegClass.hasType(VT))
25469 Res.second = &X86::VR256RegClass;
25470 else if (X86::VR512RegClass.hasType(VT))
25471 Res.second = &X86::VR512RegClass;
25477 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
25479 // Scaling factors are not free at all.
25480 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
25481 // will take 2 allocations in the out of order engine instead of 1
25482 // for plain addressing mode, i.e. inst (reg1).
25484 // vaddps (%rsi,%drx), %ymm0, %ymm1
25485 // Requires two allocations (one for the load, one for the computation)
25487 // vaddps (%rsi), %ymm0, %ymm1
25488 // Requires just 1 allocation, i.e., freeing allocations for other operations
25489 // and having less micro operations to execute.
25491 // For some X86 architectures, this is even worse because for instance for
25492 // stores, the complex addressing mode forces the instruction to use the
25493 // "load" ports instead of the dedicated "store" port.
25494 // E.g., on Haswell:
25495 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
25496 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
25497 if (isLegalAddressingMode(AM, Ty))
25498 // Scale represents reg2 * scale, thus account for 1
25499 // as soon as we use a second register.
25500 return AM.Scale != 0;
25504 bool X86TargetLowering::isTargetFTOL() const {
25505 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();