1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/StringSwitch.h"
26 #include "llvm/ADT/VariadicFunction.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/IR/CallSite.h"
35 #include "llvm/IR/CallingConv.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/DerivedTypes.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/GlobalAlias.h"
40 #include "llvm/IR/GlobalVariable.h"
41 #include "llvm/IR/Instructions.h"
42 #include "llvm/IR/Intrinsics.h"
43 #include "llvm/MC/MCAsmInfo.h"
44 #include "llvm/MC/MCContext.h"
45 #include "llvm/MC/MCExpr.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/MathExtras.h"
51 #include "llvm/Target/TargetOptions.h"
57 #define DEBUG_TYPE "x86-isel"
59 STATISTIC(NumTailCalls, "Number of tail calls");
61 static cl::opt<bool> ExperimentalVectorWideningLegalization(
62 "x86-experimental-vector-widening-legalization", cl::init(false),
63 cl::desc("Enable an experimental vector type legalization through widening "
64 "rather than promotion."),
67 static cl::opt<bool> ExperimentalVectorShuffleLowering(
68 "x86-experimental-vector-shuffle-lowering", cl::init(false),
69 cl::desc("Enable an experimental vector shuffle lowering code path."),
72 // Forward declarations.
73 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
76 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
77 SelectionDAG &DAG, SDLoc dl,
78 unsigned vectorWidth) {
79 assert((vectorWidth == 128 || vectorWidth == 256) &&
80 "Unsupported vector width");
81 EVT VT = Vec.getValueType();
82 EVT ElVT = VT.getVectorElementType();
83 unsigned Factor = VT.getSizeInBits()/vectorWidth;
84 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
85 VT.getVectorNumElements()/Factor);
87 // Extract from UNDEF is UNDEF.
88 if (Vec.getOpcode() == ISD::UNDEF)
89 return DAG.getUNDEF(ResultVT);
91 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
92 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
94 // This is the index of the first element of the vectorWidth-bit chunk
96 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
99 // If the input is a buildvector just emit a smaller one.
100 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
101 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
102 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
105 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
106 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
112 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
113 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
114 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
115 /// instructions or a simple subregister reference. Idx is an index in the
116 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
117 /// lowering EXTRACT_VECTOR_ELT operations easier.
118 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
119 SelectionDAG &DAG, SDLoc dl) {
120 assert((Vec.getValueType().is256BitVector() ||
121 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
122 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
125 /// Generate a DAG to grab 256-bits from a 512-bit vector.
126 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
127 SelectionDAG &DAG, SDLoc dl) {
128 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
129 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
132 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
133 unsigned IdxVal, SelectionDAG &DAG,
134 SDLoc dl, unsigned vectorWidth) {
135 assert((vectorWidth == 128 || vectorWidth == 256) &&
136 "Unsupported vector width");
137 // Inserting UNDEF is Result
138 if (Vec.getOpcode() == ISD::UNDEF)
140 EVT VT = Vec.getValueType();
141 EVT ElVT = VT.getVectorElementType();
142 EVT ResultVT = Result.getValueType();
144 // Insert the relevant vectorWidth bits.
145 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
147 // This is the index of the first element of the vectorWidth-bit chunk
149 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
152 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
153 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
156 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
157 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
158 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
159 /// simple superregister reference. Idx is an index in the 128 bits
160 /// we want. It need not be aligned to a 128-bit bounday. That makes
161 /// lowering INSERT_VECTOR_ELT operations easier.
162 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
163 unsigned IdxVal, SelectionDAG &DAG,
165 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
166 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
169 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
170 unsigned IdxVal, SelectionDAG &DAG,
172 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
173 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
176 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
177 /// instructions. This is used because creating CONCAT_VECTOR nodes of
178 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
179 /// large BUILD_VECTORS.
180 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
181 unsigned NumElems, SelectionDAG &DAG,
183 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
184 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
187 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
188 unsigned NumElems, SelectionDAG &DAG,
190 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
191 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
194 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
195 if (TT.isOSBinFormatMachO()) {
196 if (TT.getArch() == Triple::x86_64)
197 return new X86_64MachoTargetObjectFile();
198 return new TargetLoweringObjectFileMachO();
202 return new X86LinuxTargetObjectFile();
203 if (TT.isOSBinFormatELF())
204 return new TargetLoweringObjectFileELF();
205 if (TT.isKnownWindowsMSVCEnvironment())
206 return new X86WindowsTargetObjectFile();
207 if (TT.isOSBinFormatCOFF())
208 return new TargetLoweringObjectFileCOFF();
209 llvm_unreachable("unknown subtarget type");
212 // FIXME: This should stop caching the target machine as soon as
213 // we can remove resetOperationActions et al.
214 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
215 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
216 Subtarget = &TM.getSubtarget<X86Subtarget>();
217 X86ScalarSSEf64 = Subtarget->hasSSE2();
218 X86ScalarSSEf32 = Subtarget->hasSSE1();
219 TD = getDataLayout();
221 resetOperationActions();
224 void X86TargetLowering::resetOperationActions() {
225 const TargetMachine &TM = getTargetMachine();
226 static bool FirstTimeThrough = true;
228 // If none of the target options have changed, then we don't need to reset the
229 // operation actions.
230 if (!FirstTimeThrough && TO == TM.Options) return;
232 if (!FirstTimeThrough) {
233 // Reinitialize the actions.
235 FirstTimeThrough = false;
240 // Set up the TargetLowering object.
241 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
243 // X86 is weird, it always uses i8 for shift amounts and setcc results.
244 setBooleanContents(ZeroOrOneBooleanContent);
245 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
246 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
248 // For 64-bit since we have so many registers use the ILP scheduler, for
249 // 32-bit code use the register pressure specific scheduling.
250 // For Atom, always use ILP scheduling.
251 if (Subtarget->isAtom())
252 setSchedulingPreference(Sched::ILP);
253 else if (Subtarget->is64Bit())
254 setSchedulingPreference(Sched::ILP);
256 setSchedulingPreference(Sched::RegPressure);
257 const X86RegisterInfo *RegInfo =
258 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
259 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
261 // Bypass expensive divides on Atom when compiling with O2
262 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
263 addBypassSlowDiv(32, 8);
264 if (Subtarget->is64Bit())
265 addBypassSlowDiv(64, 16);
268 if (Subtarget->isTargetKnownWindowsMSVC()) {
269 // Setup Windows compiler runtime calls.
270 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
271 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
272 setLibcallName(RTLIB::SREM_I64, "_allrem");
273 setLibcallName(RTLIB::UREM_I64, "_aullrem");
274 setLibcallName(RTLIB::MUL_I64, "_allmul");
275 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
276 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
277 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
281 // The _ftol2 runtime function has an unusual calling conv, which
282 // is modeled by a special pseudo-instruction.
283 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
284 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
285 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
289 if (Subtarget->isTargetDarwin()) {
290 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
291 setUseUnderscoreSetJmp(false);
292 setUseUnderscoreLongJmp(false);
293 } else if (Subtarget->isTargetWindowsGNU()) {
294 // MS runtime is weird: it exports _setjmp, but longjmp!
295 setUseUnderscoreSetJmp(true);
296 setUseUnderscoreLongJmp(false);
298 setUseUnderscoreSetJmp(true);
299 setUseUnderscoreLongJmp(true);
302 // Set up the register classes.
303 addRegisterClass(MVT::i8, &X86::GR8RegClass);
304 addRegisterClass(MVT::i16, &X86::GR16RegClass);
305 addRegisterClass(MVT::i32, &X86::GR32RegClass);
306 if (Subtarget->is64Bit())
307 addRegisterClass(MVT::i64, &X86::GR64RegClass);
309 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
311 // We don't accept any truncstore of integer registers.
312 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
313 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
314 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
315 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
319 // SETOEQ and SETUNE require checking two conditions.
320 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
321 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
322 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
323 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
324 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
325 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
327 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
329 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
330 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
331 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
333 if (Subtarget->is64Bit()) {
334 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
336 } else if (!TM.Options.UseSoftFloat) {
337 // We have an algorithm for SSE2->double, and we turn this into a
338 // 64-bit FILD followed by conditional FADD for other targets.
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 // We have an algorithm for SSE2, and we turn this into a 64-bit
341 // FILD for other targets.
342 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
345 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
347 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
348 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
350 if (!TM.Options.UseSoftFloat) {
351 // SSE has no i16 to fp conversion, only i32
352 if (X86ScalarSSEf32) {
353 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
354 // f32 and f64 cases are Legal, f80 case is not
355 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
358 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
365 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
366 // are Legal, f80 is custom lowered.
367 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
368 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
370 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
372 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
373 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
375 if (X86ScalarSSEf32) {
376 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
377 // f32 and f64 cases are Legal, f80 case is not
378 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
381 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
384 // Handle FP_TO_UINT by promoting the destination to a larger signed
386 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
387 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
388 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
390 if (Subtarget->is64Bit()) {
391 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
393 } else if (!TM.Options.UseSoftFloat) {
394 // Since AVX is a superset of SSE3, only check for SSE here.
395 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
396 // Expand FP_TO_UINT into a select.
397 // FIXME: We would like to use a Custom expander here eventually to do
398 // the optimal thing for SSE vs. the default expansion in the legalizer.
399 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
401 // With SSE3 we can use fisttpll to convert to a signed i64; without
402 // SSE, we're stuck with a fistpll.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
406 if (isTargetFTOL()) {
407 // Use the _ftol2 runtime function, which has a pseudo-instruction
408 // to handle its weird calling convention.
409 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
412 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
413 if (!X86ScalarSSEf64) {
414 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
415 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
416 if (Subtarget->is64Bit()) {
417 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
418 // Without SSE, i64->f64 goes through memory.
419 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
423 // Scalar integer divide and remainder are lowered to use operations that
424 // produce two results, to match the available instructions. This exposes
425 // the two-result form to trivial CSE, which is able to combine x/y and x%y
426 // into a single instruction.
428 // Scalar integer multiply-high is also lowered to use two-result
429 // operations, to match the available instructions. However, plain multiply
430 // (low) operations are left as Legal, as there are single-result
431 // instructions for this in x86. Using the two-result multiply instructions
432 // when both high and low results are needed must be arranged by dagcombine.
433 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
435 setOperationAction(ISD::MULHS, VT, Expand);
436 setOperationAction(ISD::MULHU, VT, Expand);
437 setOperationAction(ISD::SDIV, VT, Expand);
438 setOperationAction(ISD::UDIV, VT, Expand);
439 setOperationAction(ISD::SREM, VT, Expand);
440 setOperationAction(ISD::UREM, VT, Expand);
442 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
443 setOperationAction(ISD::ADDC, VT, Custom);
444 setOperationAction(ISD::ADDE, VT, Custom);
445 setOperationAction(ISD::SUBC, VT, Custom);
446 setOperationAction(ISD::SUBE, VT, Custom);
449 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
450 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
451 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
452 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
453 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
454 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
455 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
456 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
457 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
458 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
459 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
460 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
461 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
465 if (Subtarget->is64Bit())
466 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
467 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
468 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
469 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
470 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
471 setOperationAction(ISD::FREM , MVT::f32 , Expand);
472 setOperationAction(ISD::FREM , MVT::f64 , Expand);
473 setOperationAction(ISD::FREM , MVT::f80 , Expand);
474 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
476 // Promote the i8 variants and force them on up to i32 which has a shorter
478 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
479 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
480 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
481 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
482 if (Subtarget->hasBMI()) {
483 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
485 if (Subtarget->is64Bit())
486 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
488 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
489 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
490 if (Subtarget->is64Bit())
491 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
494 if (Subtarget->hasLZCNT()) {
495 // When promoting the i8 variants, force them to i32 for a shorter
497 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
498 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
499 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
500 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
501 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
502 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
503 if (Subtarget->is64Bit())
504 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
506 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
507 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
508 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
509 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
510 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
511 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
512 if (Subtarget->is64Bit()) {
513 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
518 // Special handling for half-precision floating point conversions.
519 // If we don't have F16C support, then lower half float conversions
520 // into library calls.
521 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
522 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
523 setOperationAction(ISD::FP32_TO_FP16, MVT::i16, Expand);
526 if (Subtarget->hasPOPCNT()) {
527 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
529 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
530 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
531 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
532 if (Subtarget->is64Bit())
533 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
536 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
538 if (!Subtarget->hasMOVBE())
539 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
541 // These should be promoted to a larger select which is supported.
542 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
543 // X86 wants to expand cmov itself.
544 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
545 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
546 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
547 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
548 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
549 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
550 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
551 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
552 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
553 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
554 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
555 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
556 if (Subtarget->is64Bit()) {
557 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
558 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
560 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
561 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
562 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
563 // support continuation, user-level threading, and etc.. As a result, no
564 // other SjLj exception interfaces are implemented and please don't build
565 // your own exception handling based on them.
566 // LLVM/Clang supports zero-cost DWARF exception handling.
567 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
568 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
571 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
572 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
573 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
574 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
575 if (Subtarget->is64Bit())
576 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
577 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
578 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
579 if (Subtarget->is64Bit()) {
580 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
581 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
582 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
583 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
584 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
586 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
587 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
588 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
589 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
590 if (Subtarget->is64Bit()) {
591 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
592 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
593 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
596 if (Subtarget->hasSSE1())
597 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
599 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
601 // Expand certain atomics
602 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
604 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
605 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
606 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
609 if (Subtarget->hasCmpxchg16b()) {
610 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
613 // FIXME - use subtarget debug flags
614 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
615 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
616 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
619 if (Subtarget->is64Bit()) {
620 setExceptionPointerRegister(X86::RAX);
621 setExceptionSelectorRegister(X86::RDX);
623 setExceptionPointerRegister(X86::EAX);
624 setExceptionSelectorRegister(X86::EDX);
626 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
627 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
629 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
630 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
632 setOperationAction(ISD::TRAP, MVT::Other, Legal);
633 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
635 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
636 setOperationAction(ISD::VASTART , MVT::Other, Custom);
637 setOperationAction(ISD::VAEND , MVT::Other, Expand);
638 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
639 // TargetInfo::X86_64ABIBuiltinVaList
640 setOperationAction(ISD::VAARG , MVT::Other, Custom);
641 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
643 // TargetInfo::CharPtrBuiltinVaList
644 setOperationAction(ISD::VAARG , MVT::Other, Expand);
645 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
648 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
649 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
651 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
652 MVT::i64 : MVT::i32, Custom);
654 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
655 // f32 and f64 use SSE.
656 // Set up the FP register classes.
657 addRegisterClass(MVT::f32, &X86::FR32RegClass);
658 addRegisterClass(MVT::f64, &X86::FR64RegClass);
660 // Use ANDPD to simulate FABS.
661 setOperationAction(ISD::FABS , MVT::f64, Custom);
662 setOperationAction(ISD::FABS , MVT::f32, Custom);
664 // Use XORP to simulate FNEG.
665 setOperationAction(ISD::FNEG , MVT::f64, Custom);
666 setOperationAction(ISD::FNEG , MVT::f32, Custom);
668 // Use ANDPD and ORPD to simulate FCOPYSIGN.
669 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
670 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
672 // Lower this to FGETSIGNx86 plus an AND.
673 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
674 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
676 // We don't support sin/cos/fmod
677 setOperationAction(ISD::FSIN , MVT::f64, Expand);
678 setOperationAction(ISD::FCOS , MVT::f64, Expand);
679 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
680 setOperationAction(ISD::FSIN , MVT::f32, Expand);
681 setOperationAction(ISD::FCOS , MVT::f32, Expand);
682 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
684 // Expand FP immediates into loads from the stack, except for the special
686 addLegalFPImmediate(APFloat(+0.0)); // xorpd
687 addLegalFPImmediate(APFloat(+0.0f)); // xorps
688 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
689 // Use SSE for f32, x87 for f64.
690 // Set up the FP register classes.
691 addRegisterClass(MVT::f32, &X86::FR32RegClass);
692 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
694 // Use ANDPS to simulate FABS.
695 setOperationAction(ISD::FABS , MVT::f32, Custom);
697 // Use XORP to simulate FNEG.
698 setOperationAction(ISD::FNEG , MVT::f32, Custom);
700 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
702 // Use ANDPS and ORPS to simulate FCOPYSIGN.
703 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
704 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
706 // We don't support sin/cos/fmod
707 setOperationAction(ISD::FSIN , MVT::f32, Expand);
708 setOperationAction(ISD::FCOS , MVT::f32, Expand);
709 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
711 // Special cases we handle for FP constants.
712 addLegalFPImmediate(APFloat(+0.0f)); // xorps
713 addLegalFPImmediate(APFloat(+0.0)); // FLD0
714 addLegalFPImmediate(APFloat(+1.0)); // FLD1
715 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
716 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
718 if (!TM.Options.UnsafeFPMath) {
719 setOperationAction(ISD::FSIN , MVT::f64, Expand);
720 setOperationAction(ISD::FCOS , MVT::f64, Expand);
721 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
723 } else if (!TM.Options.UseSoftFloat) {
724 // f32 and f64 in x87.
725 // Set up the FP register classes.
726 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
727 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
729 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
730 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
731 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
732 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
734 if (!TM.Options.UnsafeFPMath) {
735 setOperationAction(ISD::FSIN , MVT::f64, Expand);
736 setOperationAction(ISD::FSIN , MVT::f32, Expand);
737 setOperationAction(ISD::FCOS , MVT::f64, Expand);
738 setOperationAction(ISD::FCOS , MVT::f32, Expand);
739 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
740 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
742 addLegalFPImmediate(APFloat(+0.0)); // FLD0
743 addLegalFPImmediate(APFloat(+1.0)); // FLD1
744 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
745 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
746 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
747 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
748 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
749 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
752 // We don't support FMA.
753 setOperationAction(ISD::FMA, MVT::f64, Expand);
754 setOperationAction(ISD::FMA, MVT::f32, Expand);
756 // Long double always uses X87.
757 if (!TM.Options.UseSoftFloat) {
758 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
759 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
760 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
762 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
763 addLegalFPImmediate(TmpFlt); // FLD0
765 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
768 APFloat TmpFlt2(+1.0);
769 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
771 addLegalFPImmediate(TmpFlt2); // FLD1
772 TmpFlt2.changeSign();
773 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
776 if (!TM.Options.UnsafeFPMath) {
777 setOperationAction(ISD::FSIN , MVT::f80, Expand);
778 setOperationAction(ISD::FCOS , MVT::f80, Expand);
779 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
782 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
783 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
784 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
785 setOperationAction(ISD::FRINT, MVT::f80, Expand);
786 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
787 setOperationAction(ISD::FMA, MVT::f80, Expand);
790 // Always use a library call for pow.
791 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
792 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
793 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
795 setOperationAction(ISD::FLOG, MVT::f80, Expand);
796 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
797 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
798 setOperationAction(ISD::FEXP, MVT::f80, Expand);
799 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
801 // First set operation action for all vector types to either promote
802 // (for widening) or expand (for scalarization). Then we will selectively
803 // turn on ones that can be effectively codegen'd.
804 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
805 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
806 MVT VT = (MVT::SimpleValueType)i;
807 setOperationAction(ISD::ADD , VT, Expand);
808 setOperationAction(ISD::SUB , VT, Expand);
809 setOperationAction(ISD::FADD, VT, Expand);
810 setOperationAction(ISD::FNEG, VT, Expand);
811 setOperationAction(ISD::FSUB, VT, Expand);
812 setOperationAction(ISD::MUL , VT, Expand);
813 setOperationAction(ISD::FMUL, VT, Expand);
814 setOperationAction(ISD::SDIV, VT, Expand);
815 setOperationAction(ISD::UDIV, VT, Expand);
816 setOperationAction(ISD::FDIV, VT, Expand);
817 setOperationAction(ISD::SREM, VT, Expand);
818 setOperationAction(ISD::UREM, VT, Expand);
819 setOperationAction(ISD::LOAD, VT, Expand);
820 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
821 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
822 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
823 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
824 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
825 setOperationAction(ISD::FABS, VT, Expand);
826 setOperationAction(ISD::FSIN, VT, Expand);
827 setOperationAction(ISD::FSINCOS, VT, Expand);
828 setOperationAction(ISD::FCOS, VT, Expand);
829 setOperationAction(ISD::FSINCOS, VT, Expand);
830 setOperationAction(ISD::FREM, VT, Expand);
831 setOperationAction(ISD::FMA, VT, Expand);
832 setOperationAction(ISD::FPOWI, VT, Expand);
833 setOperationAction(ISD::FSQRT, VT, Expand);
834 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
835 setOperationAction(ISD::FFLOOR, VT, Expand);
836 setOperationAction(ISD::FCEIL, VT, Expand);
837 setOperationAction(ISD::FTRUNC, VT, Expand);
838 setOperationAction(ISD::FRINT, VT, Expand);
839 setOperationAction(ISD::FNEARBYINT, VT, Expand);
840 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
841 setOperationAction(ISD::MULHS, VT, Expand);
842 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
843 setOperationAction(ISD::MULHU, VT, Expand);
844 setOperationAction(ISD::SDIVREM, VT, Expand);
845 setOperationAction(ISD::UDIVREM, VT, Expand);
846 setOperationAction(ISD::FPOW, VT, Expand);
847 setOperationAction(ISD::CTPOP, VT, Expand);
848 setOperationAction(ISD::CTTZ, VT, Expand);
849 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
850 setOperationAction(ISD::CTLZ, VT, Expand);
851 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
852 setOperationAction(ISD::SHL, VT, Expand);
853 setOperationAction(ISD::SRA, VT, Expand);
854 setOperationAction(ISD::SRL, VT, Expand);
855 setOperationAction(ISD::ROTL, VT, Expand);
856 setOperationAction(ISD::ROTR, VT, Expand);
857 setOperationAction(ISD::BSWAP, VT, Expand);
858 setOperationAction(ISD::SETCC, VT, Expand);
859 setOperationAction(ISD::FLOG, VT, Expand);
860 setOperationAction(ISD::FLOG2, VT, Expand);
861 setOperationAction(ISD::FLOG10, VT, Expand);
862 setOperationAction(ISD::FEXP, VT, Expand);
863 setOperationAction(ISD::FEXP2, VT, Expand);
864 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
865 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
866 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
867 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
868 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
869 setOperationAction(ISD::TRUNCATE, VT, Expand);
870 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
871 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
872 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
873 setOperationAction(ISD::VSELECT, VT, Expand);
874 setOperationAction(ISD::SELECT_CC, VT, Expand);
875 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
876 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
877 setTruncStoreAction(VT,
878 (MVT::SimpleValueType)InnerVT, Expand);
879 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
880 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
881 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
884 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
885 // with -msoft-float, disable use of MMX as well.
886 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
887 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
888 // No operations on x86mmx supported, everything uses intrinsics.
891 // MMX-sized vectors (other than x86mmx) are expected to be expanded
892 // into smaller operations.
893 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
894 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
895 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
896 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
897 setOperationAction(ISD::AND, MVT::v8i8, Expand);
898 setOperationAction(ISD::AND, MVT::v4i16, Expand);
899 setOperationAction(ISD::AND, MVT::v2i32, Expand);
900 setOperationAction(ISD::AND, MVT::v1i64, Expand);
901 setOperationAction(ISD::OR, MVT::v8i8, Expand);
902 setOperationAction(ISD::OR, MVT::v4i16, Expand);
903 setOperationAction(ISD::OR, MVT::v2i32, Expand);
904 setOperationAction(ISD::OR, MVT::v1i64, Expand);
905 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
906 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
907 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
908 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
909 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
910 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
911 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
912 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
913 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
914 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
915 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
916 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
917 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
918 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
919 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
920 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
921 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
923 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
924 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
926 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
927 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
928 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
929 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
930 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
931 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
932 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
933 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
934 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
935 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
936 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
937 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
940 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
941 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
943 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
944 // registers cannot be used even for integer operations.
945 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
946 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
947 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
948 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
950 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
951 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
952 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
953 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
954 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
955 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
956 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
957 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
958 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
959 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
960 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
961 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
962 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
963 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
964 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
965 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
966 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
967 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
968 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
969 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
970 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
971 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
973 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
974 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
975 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
976 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
978 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
979 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
980 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
981 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
982 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
984 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
985 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
986 MVT VT = (MVT::SimpleValueType)i;
987 // Do not attempt to custom lower non-power-of-2 vectors
988 if (!isPowerOf2_32(VT.getVectorNumElements()))
990 // Do not attempt to custom lower non-128-bit vectors
991 if (!VT.is128BitVector())
993 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
994 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
995 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
998 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
999 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1000 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1001 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1002 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1003 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1005 if (Subtarget->is64Bit()) {
1006 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1007 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1010 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1011 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1012 MVT VT = (MVT::SimpleValueType)i;
1014 // Do not attempt to promote non-128-bit vectors
1015 if (!VT.is128BitVector())
1018 setOperationAction(ISD::AND, VT, Promote);
1019 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1020 setOperationAction(ISD::OR, VT, Promote);
1021 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1022 setOperationAction(ISD::XOR, VT, Promote);
1023 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1024 setOperationAction(ISD::LOAD, VT, Promote);
1025 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1026 setOperationAction(ISD::SELECT, VT, Promote);
1027 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1030 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1032 // Custom lower v2i64 and v2f64 selects.
1033 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1034 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1035 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1036 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1038 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1039 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1041 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1042 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1043 // As there is no 64-bit GPR available, we need build a special custom
1044 // sequence to convert from v2i32 to v2f32.
1045 if (!Subtarget->is64Bit())
1046 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1048 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1049 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1051 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1053 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1054 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1055 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1058 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1059 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1060 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1061 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1062 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1063 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1064 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1065 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1066 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1067 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1068 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1070 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1071 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1072 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1073 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1074 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1075 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1076 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1077 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1078 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1079 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1081 // FIXME: Do we need to handle scalar-to-vector here?
1082 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1084 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1085 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1086 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1087 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1088 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1089 // There is no BLENDI for byte vectors. We don't need to custom lower
1090 // some vselects for now.
1091 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1093 // i8 and i16 vectors are custom , because the source register and source
1094 // source memory operand types are not the same width. f32 vectors are
1095 // custom since the immediate controlling the insert encodes additional
1097 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1098 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1099 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1100 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1102 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1103 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1104 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1105 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1107 // FIXME: these should be Legal but thats only for the case where
1108 // the index is constant. For now custom expand to deal with that.
1109 if (Subtarget->is64Bit()) {
1110 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1111 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1115 if (Subtarget->hasSSE2()) {
1116 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1117 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1119 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1120 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1122 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1123 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1125 // In the customized shift lowering, the legal cases in AVX2 will be
1127 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1128 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1130 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1131 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1133 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1136 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1137 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1138 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1139 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1140 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1141 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1142 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1144 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1145 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1146 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1148 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1149 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1150 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1151 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1152 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1153 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1154 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1155 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1156 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1157 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1158 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1159 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1161 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1162 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1163 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1164 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1165 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1166 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1167 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1168 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1169 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1170 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1171 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1172 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1174 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1175 // even though v8i16 is a legal type.
1176 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1177 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1178 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1180 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1181 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1182 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1184 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1185 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1187 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1189 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1190 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1192 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1193 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1195 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1196 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1198 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1199 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1200 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1201 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1203 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1204 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1205 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1207 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1208 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1209 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1210 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1212 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1213 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1214 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1215 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1216 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1217 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1218 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1219 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1220 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1221 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1222 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1223 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1225 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1226 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1227 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1228 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1229 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1230 setOperationAction(ISD::FMA, MVT::f32, Legal);
1231 setOperationAction(ISD::FMA, MVT::f64, Legal);
1234 if (Subtarget->hasInt256()) {
1235 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1236 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1237 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1238 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1240 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1241 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1242 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1243 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1245 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1246 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1247 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1248 // Don't lower v32i8 because there is no 128-bit byte mul
1250 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1252 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1253 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1255 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1256 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1258 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1259 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1260 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1261 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1263 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1264 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1265 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1266 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1268 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1269 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1270 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1271 // Don't lower v32i8 because there is no 128-bit byte mul
1274 // In the customized shift lowering, the legal cases in AVX2 will be
1276 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1277 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1279 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1280 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1282 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1284 // Custom lower several nodes for 256-bit types.
1285 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1286 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1287 MVT VT = (MVT::SimpleValueType)i;
1289 // Extract subvector is special because the value type
1290 // (result) is 128-bit but the source is 256-bit wide.
1291 if (VT.is128BitVector())
1292 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1294 // Do not attempt to custom lower other non-256-bit vectors
1295 if (!VT.is256BitVector())
1298 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1299 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1300 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1301 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1302 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1303 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1304 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1307 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1308 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1309 MVT VT = (MVT::SimpleValueType)i;
1311 // Do not attempt to promote non-256-bit vectors
1312 if (!VT.is256BitVector())
1315 setOperationAction(ISD::AND, VT, Promote);
1316 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1317 setOperationAction(ISD::OR, VT, Promote);
1318 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1319 setOperationAction(ISD::XOR, VT, Promote);
1320 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1321 setOperationAction(ISD::LOAD, VT, Promote);
1322 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1323 setOperationAction(ISD::SELECT, VT, Promote);
1324 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1328 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1329 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1330 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1331 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1332 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1334 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1335 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1336 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1338 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1339 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1340 setOperationAction(ISD::XOR, MVT::i1, Legal);
1341 setOperationAction(ISD::OR, MVT::i1, Legal);
1342 setOperationAction(ISD::AND, MVT::i1, Legal);
1343 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1344 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1345 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1346 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1347 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1348 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1350 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1351 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1352 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1353 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1354 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1355 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1357 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1358 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1359 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1360 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1361 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1362 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1363 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1364 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1366 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1367 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1368 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1369 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1370 if (Subtarget->is64Bit()) {
1371 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1372 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1373 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1374 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1376 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1377 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1378 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1379 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1380 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1381 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1382 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1383 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1384 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1385 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1387 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1388 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1389 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1390 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1391 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1392 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1393 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1394 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1395 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1396 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1397 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1398 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1399 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1401 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1402 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1403 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1404 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1405 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1406 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1408 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1409 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1411 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1413 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1414 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1415 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1416 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1417 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1418 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1419 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1420 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1421 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1423 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1424 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1426 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1427 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1429 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1431 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1434 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1435 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1437 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1438 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1440 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1441 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1442 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1443 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1444 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1445 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1447 if (Subtarget->hasCDI()) {
1448 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1449 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1452 // Custom lower several nodes.
1453 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1454 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1455 MVT VT = (MVT::SimpleValueType)i;
1457 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1458 // Extract subvector is special because the value type
1459 // (result) is 256/128-bit but the source is 512-bit wide.
1460 if (VT.is128BitVector() || VT.is256BitVector())
1461 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1463 if (VT.getVectorElementType() == MVT::i1)
1464 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1466 // Do not attempt to custom lower other non-512-bit vectors
1467 if (!VT.is512BitVector())
1470 if ( EltSize >= 32) {
1471 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1472 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1473 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1474 setOperationAction(ISD::VSELECT, VT, Legal);
1475 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1476 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1477 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1480 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1481 MVT VT = (MVT::SimpleValueType)i;
1483 // Do not attempt to promote non-256-bit vectors
1484 if (!VT.is512BitVector())
1487 setOperationAction(ISD::SELECT, VT, Promote);
1488 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1492 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1493 // of this type with custom code.
1494 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1495 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1496 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1500 // We want to custom lower some of our intrinsics.
1501 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1502 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1503 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1504 if (!Subtarget->is64Bit())
1505 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1507 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1508 // handle type legalization for these operations here.
1510 // FIXME: We really should do custom legalization for addition and
1511 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1512 // than generic legalization for 64-bit multiplication-with-overflow, though.
1513 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1514 // Add/Sub/Mul with overflow operations are custom lowered.
1516 setOperationAction(ISD::SADDO, VT, Custom);
1517 setOperationAction(ISD::UADDO, VT, Custom);
1518 setOperationAction(ISD::SSUBO, VT, Custom);
1519 setOperationAction(ISD::USUBO, VT, Custom);
1520 setOperationAction(ISD::SMULO, VT, Custom);
1521 setOperationAction(ISD::UMULO, VT, Custom);
1524 // There are no 8-bit 3-address imul/mul instructions
1525 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1526 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1528 if (!Subtarget->is64Bit()) {
1529 // These libcalls are not available in 32-bit.
1530 setLibcallName(RTLIB::SHL_I128, nullptr);
1531 setLibcallName(RTLIB::SRL_I128, nullptr);
1532 setLibcallName(RTLIB::SRA_I128, nullptr);
1535 // Combine sin / cos into one node or libcall if possible.
1536 if (Subtarget->hasSinCos()) {
1537 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1538 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1539 if (Subtarget->isTargetDarwin()) {
1540 // For MacOSX, we don't want to the normal expansion of a libcall to
1541 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1543 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1544 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1548 if (Subtarget->isTargetWin64()) {
1549 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1550 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1551 setOperationAction(ISD::SREM, MVT::i128, Custom);
1552 setOperationAction(ISD::UREM, MVT::i128, Custom);
1553 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1554 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1557 // We have target-specific dag combine patterns for the following nodes:
1558 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1559 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1560 setTargetDAGCombine(ISD::VSELECT);
1561 setTargetDAGCombine(ISD::SELECT);
1562 setTargetDAGCombine(ISD::SHL);
1563 setTargetDAGCombine(ISD::SRA);
1564 setTargetDAGCombine(ISD::SRL);
1565 setTargetDAGCombine(ISD::OR);
1566 setTargetDAGCombine(ISD::AND);
1567 setTargetDAGCombine(ISD::ADD);
1568 setTargetDAGCombine(ISD::FADD);
1569 setTargetDAGCombine(ISD::FSUB);
1570 setTargetDAGCombine(ISD::FMA);
1571 setTargetDAGCombine(ISD::SUB);
1572 setTargetDAGCombine(ISD::LOAD);
1573 setTargetDAGCombine(ISD::STORE);
1574 setTargetDAGCombine(ISD::ZERO_EXTEND);
1575 setTargetDAGCombine(ISD::ANY_EXTEND);
1576 setTargetDAGCombine(ISD::SIGN_EXTEND);
1577 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1578 setTargetDAGCombine(ISD::TRUNCATE);
1579 setTargetDAGCombine(ISD::SINT_TO_FP);
1580 setTargetDAGCombine(ISD::SETCC);
1581 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1582 setTargetDAGCombine(ISD::BUILD_VECTOR);
1583 if (Subtarget->is64Bit())
1584 setTargetDAGCombine(ISD::MUL);
1585 setTargetDAGCombine(ISD::XOR);
1587 computeRegisterProperties();
1589 // On Darwin, -Os means optimize for size without hurting performance,
1590 // do not reduce the limit.
1591 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1592 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1593 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1594 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1595 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1596 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1597 setPrefLoopAlignment(4); // 2^4 bytes.
1599 // Predictable cmov don't hurt on atom because it's in-order.
1600 PredictableSelectIsExpensive = !Subtarget->isAtom();
1602 setPrefFunctionAlignment(4); // 2^4 bytes.
1605 TargetLoweringBase::LegalizeTypeAction
1606 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1607 if (ExperimentalVectorWideningLegalization &&
1608 VT.getVectorNumElements() != 1 &&
1609 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1610 return TypeWidenVector;
1612 return TargetLoweringBase::getPreferredVectorAction(VT);
1615 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1617 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1619 if (Subtarget->hasAVX512())
1620 switch(VT.getVectorNumElements()) {
1621 case 8: return MVT::v8i1;
1622 case 16: return MVT::v16i1;
1625 return VT.changeVectorElementTypeToInteger();
1628 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1629 /// the desired ByVal argument alignment.
1630 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1633 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1634 if (VTy->getBitWidth() == 128)
1636 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1637 unsigned EltAlign = 0;
1638 getMaxByValAlign(ATy->getElementType(), EltAlign);
1639 if (EltAlign > MaxAlign)
1640 MaxAlign = EltAlign;
1641 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1642 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1643 unsigned EltAlign = 0;
1644 getMaxByValAlign(STy->getElementType(i), EltAlign);
1645 if (EltAlign > MaxAlign)
1646 MaxAlign = EltAlign;
1653 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1654 /// function arguments in the caller parameter area. For X86, aggregates
1655 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1656 /// are at 4-byte boundaries.
1657 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1658 if (Subtarget->is64Bit()) {
1659 // Max of 8 and alignment of type.
1660 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1667 if (Subtarget->hasSSE1())
1668 getMaxByValAlign(Ty, Align);
1672 /// getOptimalMemOpType - Returns the target specific optimal type for load
1673 /// and store operations as a result of memset, memcpy, and memmove
1674 /// lowering. If DstAlign is zero that means it's safe to destination
1675 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1676 /// means there isn't a need to check it against alignment requirement,
1677 /// probably because the source does not need to be loaded. If 'IsMemset' is
1678 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1679 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1680 /// source is constant so it does not need to be loaded.
1681 /// It returns EVT::Other if the type should be determined using generic
1682 /// target-independent logic.
1684 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1685 unsigned DstAlign, unsigned SrcAlign,
1686 bool IsMemset, bool ZeroMemset,
1688 MachineFunction &MF) const {
1689 const Function *F = MF.getFunction();
1690 if ((!IsMemset || ZeroMemset) &&
1691 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1692 Attribute::NoImplicitFloat)) {
1694 (Subtarget->isUnalignedMemAccessFast() ||
1695 ((DstAlign == 0 || DstAlign >= 16) &&
1696 (SrcAlign == 0 || SrcAlign >= 16)))) {
1698 if (Subtarget->hasInt256())
1700 if (Subtarget->hasFp256())
1703 if (Subtarget->hasSSE2())
1705 if (Subtarget->hasSSE1())
1707 } else if (!MemcpyStrSrc && Size >= 8 &&
1708 !Subtarget->is64Bit() &&
1709 Subtarget->hasSSE2()) {
1710 // Do not use f64 to lower memcpy if source is string constant. It's
1711 // better to use i32 to avoid the loads.
1715 if (Subtarget->is64Bit() && Size >= 8)
1720 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1722 return X86ScalarSSEf32;
1723 else if (VT == MVT::f64)
1724 return X86ScalarSSEf64;
1729 X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
1733 *Fast = Subtarget->isUnalignedMemAccessFast();
1737 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1738 /// current function. The returned value is a member of the
1739 /// MachineJumpTableInfo::JTEntryKind enum.
1740 unsigned X86TargetLowering::getJumpTableEncoding() const {
1741 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1743 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1744 Subtarget->isPICStyleGOT())
1745 return MachineJumpTableInfo::EK_Custom32;
1747 // Otherwise, use the normal jump table encoding heuristics.
1748 return TargetLowering::getJumpTableEncoding();
1752 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1753 const MachineBasicBlock *MBB,
1754 unsigned uid,MCContext &Ctx) const{
1755 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1756 Subtarget->isPICStyleGOT());
1757 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1759 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1760 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1763 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1765 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1766 SelectionDAG &DAG) const {
1767 if (!Subtarget->is64Bit())
1768 // This doesn't have SDLoc associated with it, but is not really the
1769 // same as a Register.
1770 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1774 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1775 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1777 const MCExpr *X86TargetLowering::
1778 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1779 MCContext &Ctx) const {
1780 // X86-64 uses RIP relative addressing based on the jump table label.
1781 if (Subtarget->isPICStyleRIPRel())
1782 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1784 // Otherwise, the reference is relative to the PIC base.
1785 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1788 // FIXME: Why this routine is here? Move to RegInfo!
1789 std::pair<const TargetRegisterClass*, uint8_t>
1790 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1791 const TargetRegisterClass *RRC = nullptr;
1793 switch (VT.SimpleTy) {
1795 return TargetLowering::findRepresentativeClass(VT);
1796 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1797 RRC = Subtarget->is64Bit() ?
1798 (const TargetRegisterClass*)&X86::GR64RegClass :
1799 (const TargetRegisterClass*)&X86::GR32RegClass;
1802 RRC = &X86::VR64RegClass;
1804 case MVT::f32: case MVT::f64:
1805 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1806 case MVT::v4f32: case MVT::v2f64:
1807 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1809 RRC = &X86::VR128RegClass;
1812 return std::make_pair(RRC, Cost);
1815 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1816 unsigned &Offset) const {
1817 if (!Subtarget->isTargetLinux())
1820 if (Subtarget->is64Bit()) {
1821 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1823 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1835 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1836 unsigned DestAS) const {
1837 assert(SrcAS != DestAS && "Expected different address spaces!");
1839 return SrcAS < 256 && DestAS < 256;
1842 //===----------------------------------------------------------------------===//
1843 // Return Value Calling Convention Implementation
1844 //===----------------------------------------------------------------------===//
1846 #include "X86GenCallingConv.inc"
1849 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1850 MachineFunction &MF, bool isVarArg,
1851 const SmallVectorImpl<ISD::OutputArg> &Outs,
1852 LLVMContext &Context) const {
1853 SmallVector<CCValAssign, 16> RVLocs;
1854 CCState CCInfo(CallConv, isVarArg, MF, MF.getTarget(),
1856 return CCInfo.CheckReturn(Outs, RetCC_X86);
1859 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1860 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1865 X86TargetLowering::LowerReturn(SDValue Chain,
1866 CallingConv::ID CallConv, bool isVarArg,
1867 const SmallVectorImpl<ISD::OutputArg> &Outs,
1868 const SmallVectorImpl<SDValue> &OutVals,
1869 SDLoc dl, SelectionDAG &DAG) const {
1870 MachineFunction &MF = DAG.getMachineFunction();
1871 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1873 SmallVector<CCValAssign, 16> RVLocs;
1874 CCState CCInfo(CallConv, isVarArg, MF, DAG.getTarget(),
1875 RVLocs, *DAG.getContext());
1876 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1879 SmallVector<SDValue, 6> RetOps;
1880 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1881 // Operand #1 = Bytes To Pop
1882 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1885 // Copy the result values into the output registers.
1886 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1887 CCValAssign &VA = RVLocs[i];
1888 assert(VA.isRegLoc() && "Can only return in registers!");
1889 SDValue ValToCopy = OutVals[i];
1890 EVT ValVT = ValToCopy.getValueType();
1892 // Promote values to the appropriate types
1893 if (VA.getLocInfo() == CCValAssign::SExt)
1894 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1895 else if (VA.getLocInfo() == CCValAssign::ZExt)
1896 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1897 else if (VA.getLocInfo() == CCValAssign::AExt)
1898 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1899 else if (VA.getLocInfo() == CCValAssign::BCvt)
1900 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1902 assert(VA.getLocInfo() != CCValAssign::FPExt &&
1903 "Unexpected FP-extend for return value.");
1905 // If this is x86-64, and we disabled SSE, we can't return FP values,
1906 // or SSE or MMX vectors.
1907 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1908 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1909 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1910 report_fatal_error("SSE register return with SSE disabled");
1912 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1913 // llvm-gcc has never done it right and no one has noticed, so this
1914 // should be OK for now.
1915 if (ValVT == MVT::f64 &&
1916 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1917 report_fatal_error("SSE2 register return with SSE2 disabled");
1919 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1920 // the RET instruction and handled by the FP Stackifier.
1921 if (VA.getLocReg() == X86::ST0 ||
1922 VA.getLocReg() == X86::ST1) {
1923 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1924 // change the value to the FP stack register class.
1925 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1926 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1927 RetOps.push_back(ValToCopy);
1928 // Don't emit a copytoreg.
1932 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1933 // which is returned in RAX / RDX.
1934 if (Subtarget->is64Bit()) {
1935 if (ValVT == MVT::x86mmx) {
1936 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1937 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1938 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1940 // If we don't have SSE2 available, convert to v4f32 so the generated
1941 // register is legal.
1942 if (!Subtarget->hasSSE2())
1943 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1948 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1949 Flag = Chain.getValue(1);
1950 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1953 // The x86-64 ABIs require that for returning structs by value we copy
1954 // the sret argument into %rax/%eax (depending on ABI) for the return.
1955 // Win32 requires us to put the sret argument to %eax as well.
1956 // We saved the argument into a virtual register in the entry block,
1957 // so now we copy the value out and into %rax/%eax.
1958 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
1959 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
1960 MachineFunction &MF = DAG.getMachineFunction();
1961 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1962 unsigned Reg = FuncInfo->getSRetReturnReg();
1964 "SRetReturnReg should have been set in LowerFormalArguments().");
1965 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1968 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
1969 X86::RAX : X86::EAX;
1970 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1971 Flag = Chain.getValue(1);
1973 // RAX/EAX now acts like a return value.
1974 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
1977 RetOps[0] = Chain; // Update chain.
1979 // Add the flag if we have it.
1981 RetOps.push_back(Flag);
1983 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
1986 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1987 if (N->getNumValues() != 1)
1989 if (!N->hasNUsesOfValue(1, 0))
1992 SDValue TCChain = Chain;
1993 SDNode *Copy = *N->use_begin();
1994 if (Copy->getOpcode() == ISD::CopyToReg) {
1995 // If the copy has a glue operand, we conservatively assume it isn't safe to
1996 // perform a tail call.
1997 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1999 TCChain = Copy->getOperand(0);
2000 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2003 bool HasRet = false;
2004 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2006 if (UI->getOpcode() != X86ISD::RET_FLAG)
2019 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
2020 ISD::NodeType ExtendKind) const {
2022 // TODO: Is this also valid on 32-bit?
2023 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2024 ReturnMVT = MVT::i8;
2026 ReturnMVT = MVT::i32;
2028 MVT MinVT = getRegisterType(ReturnMVT);
2029 return VT.bitsLT(MinVT) ? MinVT : VT;
2032 /// LowerCallResult - Lower the result values of a call into the
2033 /// appropriate copies out of appropriate physical registers.
2036 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2037 CallingConv::ID CallConv, bool isVarArg,
2038 const SmallVectorImpl<ISD::InputArg> &Ins,
2039 SDLoc dl, SelectionDAG &DAG,
2040 SmallVectorImpl<SDValue> &InVals) const {
2042 // Assign locations to each value returned by this call.
2043 SmallVector<CCValAssign, 16> RVLocs;
2044 bool Is64Bit = Subtarget->is64Bit();
2045 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2046 DAG.getTarget(), RVLocs, *DAG.getContext());
2047 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2049 // Copy all of the result registers out of their specified physreg.
2050 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2051 CCValAssign &VA = RVLocs[i];
2052 EVT CopyVT = VA.getValVT();
2054 // If this is x86-64, and we disabled SSE, we can't return FP values
2055 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2056 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2057 report_fatal_error("SSE register return with SSE disabled");
2062 // If this is a call to a function that returns an fp value on the floating
2063 // point stack, we must guarantee the value is popped from the stack, so
2064 // a CopyFromReg is not good enough - the copy instruction may be eliminated
2065 // if the return value is not used. We use the FpPOP_RETVAL instruction
2067 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
2068 // If we prefer to use the value in xmm registers, copy it out as f80 and
2069 // use a truncate to move it from fp stack reg to xmm reg.
2070 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
2071 SDValue Ops[] = { Chain, InFlag };
2072 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
2073 MVT::Other, MVT::Glue, Ops), 1);
2074 Val = Chain.getValue(0);
2076 // Round the f80 to the right size, which also moves it to the appropriate
2078 if (CopyVT != VA.getValVT())
2079 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2080 // This truncation won't change the value.
2081 DAG.getIntPtrConstant(1));
2083 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2084 CopyVT, InFlag).getValue(1);
2085 Val = Chain.getValue(0);
2087 InFlag = Chain.getValue(2);
2088 InVals.push_back(Val);
2094 //===----------------------------------------------------------------------===//
2095 // C & StdCall & Fast Calling Convention implementation
2096 //===----------------------------------------------------------------------===//
2097 // StdCall calling convention seems to be standard for many Windows' API
2098 // routines and around. It differs from C calling convention just a little:
2099 // callee should clean up the stack, not caller. Symbols should be also
2100 // decorated in some fancy way :) It doesn't support any vector arguments.
2101 // For info on fast calling convention see Fast Calling Convention (tail call)
2102 // implementation LowerX86_32FastCCCallTo.
2104 /// CallIsStructReturn - Determines whether a call uses struct return
2106 enum StructReturnType {
2111 static StructReturnType
2112 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2114 return NotStructReturn;
2116 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2117 if (!Flags.isSRet())
2118 return NotStructReturn;
2119 if (Flags.isInReg())
2120 return RegStructReturn;
2121 return StackStructReturn;
2124 /// ArgsAreStructReturn - Determines whether a function uses struct
2125 /// return semantics.
2126 static StructReturnType
2127 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2129 return NotStructReturn;
2131 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2132 if (!Flags.isSRet())
2133 return NotStructReturn;
2134 if (Flags.isInReg())
2135 return RegStructReturn;
2136 return StackStructReturn;
2139 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2140 /// by "Src" to address "Dst" with size and alignment information specified by
2141 /// the specific parameter attribute. The copy will be passed as a byval
2142 /// function parameter.
2144 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2145 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2147 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2149 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2150 /*isVolatile*/false, /*AlwaysInline=*/true,
2151 MachinePointerInfo(), MachinePointerInfo());
2154 /// IsTailCallConvention - Return true if the calling convention is one that
2155 /// supports tail call optimization.
2156 static bool IsTailCallConvention(CallingConv::ID CC) {
2157 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2158 CC == CallingConv::HiPE);
2161 /// \brief Return true if the calling convention is a C calling convention.
2162 static bool IsCCallConvention(CallingConv::ID CC) {
2163 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2164 CC == CallingConv::X86_64_SysV);
2167 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2168 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2172 CallingConv::ID CalleeCC = CS.getCallingConv();
2173 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2179 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2180 /// a tailcall target by changing its ABI.
2181 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2182 bool GuaranteedTailCallOpt) {
2183 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2187 X86TargetLowering::LowerMemArgument(SDValue Chain,
2188 CallingConv::ID CallConv,
2189 const SmallVectorImpl<ISD::InputArg> &Ins,
2190 SDLoc dl, SelectionDAG &DAG,
2191 const CCValAssign &VA,
2192 MachineFrameInfo *MFI,
2194 // Create the nodes corresponding to a load from this parameter slot.
2195 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2196 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2197 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2198 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2201 // If value is passed by pointer we have address passed instead of the value
2203 if (VA.getLocInfo() == CCValAssign::Indirect)
2204 ValVT = VA.getLocVT();
2206 ValVT = VA.getValVT();
2208 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2209 // changed with more analysis.
2210 // In case of tail call optimization mark all arguments mutable. Since they
2211 // could be overwritten by lowering of arguments in case of a tail call.
2212 if (Flags.isByVal()) {
2213 unsigned Bytes = Flags.getByValSize();
2214 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2215 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2216 return DAG.getFrameIndex(FI, getPointerTy());
2218 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2219 VA.getLocMemOffset(), isImmutable);
2220 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2221 return DAG.getLoad(ValVT, dl, Chain, FIN,
2222 MachinePointerInfo::getFixedStack(FI),
2223 false, false, false, 0);
2228 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2229 CallingConv::ID CallConv,
2231 const SmallVectorImpl<ISD::InputArg> &Ins,
2234 SmallVectorImpl<SDValue> &InVals)
2236 MachineFunction &MF = DAG.getMachineFunction();
2237 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2239 const Function* Fn = MF.getFunction();
2240 if (Fn->hasExternalLinkage() &&
2241 Subtarget->isTargetCygMing() &&
2242 Fn->getName() == "main")
2243 FuncInfo->setForceFramePointer(true);
2245 MachineFrameInfo *MFI = MF.getFrameInfo();
2246 bool Is64Bit = Subtarget->is64Bit();
2247 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2249 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2250 "Var args not supported with calling convention fastcc, ghc or hipe");
2252 // Assign locations to all of the incoming arguments.
2253 SmallVector<CCValAssign, 16> ArgLocs;
2254 CCState CCInfo(CallConv, isVarArg, MF, DAG.getTarget(),
2255 ArgLocs, *DAG.getContext());
2257 // Allocate shadow area for Win64
2259 CCInfo.AllocateStack(32, 8);
2261 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2263 unsigned LastVal = ~0U;
2265 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2266 CCValAssign &VA = ArgLocs[i];
2267 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2269 assert(VA.getValNo() != LastVal &&
2270 "Don't support value assigned to multiple locs yet");
2272 LastVal = VA.getValNo();
2274 if (VA.isRegLoc()) {
2275 EVT RegVT = VA.getLocVT();
2276 const TargetRegisterClass *RC;
2277 if (RegVT == MVT::i32)
2278 RC = &X86::GR32RegClass;
2279 else if (Is64Bit && RegVT == MVT::i64)
2280 RC = &X86::GR64RegClass;
2281 else if (RegVT == MVT::f32)
2282 RC = &X86::FR32RegClass;
2283 else if (RegVT == MVT::f64)
2284 RC = &X86::FR64RegClass;
2285 else if (RegVT.is512BitVector())
2286 RC = &X86::VR512RegClass;
2287 else if (RegVT.is256BitVector())
2288 RC = &X86::VR256RegClass;
2289 else if (RegVT.is128BitVector())
2290 RC = &X86::VR128RegClass;
2291 else if (RegVT == MVT::x86mmx)
2292 RC = &X86::VR64RegClass;
2293 else if (RegVT == MVT::i1)
2294 RC = &X86::VK1RegClass;
2295 else if (RegVT == MVT::v8i1)
2296 RC = &X86::VK8RegClass;
2297 else if (RegVT == MVT::v16i1)
2298 RC = &X86::VK16RegClass;
2300 llvm_unreachable("Unknown argument type!");
2302 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2303 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2305 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2306 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2308 if (VA.getLocInfo() == CCValAssign::SExt)
2309 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2310 DAG.getValueType(VA.getValVT()));
2311 else if (VA.getLocInfo() == CCValAssign::ZExt)
2312 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2313 DAG.getValueType(VA.getValVT()));
2314 else if (VA.getLocInfo() == CCValAssign::BCvt)
2315 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2317 if (VA.isExtInLoc()) {
2318 // Handle MMX values passed in XMM regs.
2319 if (RegVT.isVector())
2320 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2322 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2325 assert(VA.isMemLoc());
2326 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2329 // If value is passed via pointer - do a load.
2330 if (VA.getLocInfo() == CCValAssign::Indirect)
2331 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2332 MachinePointerInfo(), false, false, false, 0);
2334 InVals.push_back(ArgValue);
2337 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2338 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2339 // The x86-64 ABIs require that for returning structs by value we copy
2340 // the sret argument into %rax/%eax (depending on ABI) for the return.
2341 // Win32 requires us to put the sret argument to %eax as well.
2342 // Save the argument into a virtual register so that we can access it
2343 // from the return points.
2344 if (Ins[i].Flags.isSRet()) {
2345 unsigned Reg = FuncInfo->getSRetReturnReg();
2347 MVT PtrTy = getPointerTy();
2348 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2349 FuncInfo->setSRetReturnReg(Reg);
2351 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2352 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2358 unsigned StackSize = CCInfo.getNextStackOffset();
2359 // Align stack specially for tail calls.
2360 if (FuncIsMadeTailCallSafe(CallConv,
2361 MF.getTarget().Options.GuaranteedTailCallOpt))
2362 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2364 // If the function takes variable number of arguments, make a frame index for
2365 // the start of the first vararg value... for expansion of llvm.va_start.
2367 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2368 CallConv != CallingConv::X86_ThisCall)) {
2369 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2372 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2374 // FIXME: We should really autogenerate these arrays
2375 static const MCPhysReg GPR64ArgRegsWin64[] = {
2376 X86::RCX, X86::RDX, X86::R8, X86::R9
2378 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2379 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2381 static const MCPhysReg XMMArgRegs64Bit[] = {
2382 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2383 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2385 const MCPhysReg *GPR64ArgRegs;
2386 unsigned NumXMMRegs = 0;
2389 // The XMM registers which might contain var arg parameters are shadowed
2390 // in their paired GPR. So we only need to save the GPR to their home
2392 TotalNumIntRegs = 4;
2393 GPR64ArgRegs = GPR64ArgRegsWin64;
2395 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2396 GPR64ArgRegs = GPR64ArgRegs64Bit;
2398 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2401 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2404 bool NoImplicitFloatOps = Fn->getAttributes().
2405 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2406 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2407 "SSE register cannot be used when SSE is disabled!");
2408 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2409 NoImplicitFloatOps) &&
2410 "SSE register cannot be used when SSE is disabled!");
2411 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2412 !Subtarget->hasSSE1())
2413 // Kernel mode asks for SSE to be disabled, so don't push them
2415 TotalNumXMMRegs = 0;
2418 const TargetFrameLowering &TFI = *MF.getTarget().getFrameLowering();
2419 // Get to the caller-allocated home save location. Add 8 to account
2420 // for the return address.
2421 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2422 FuncInfo->setRegSaveFrameIndex(
2423 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2424 // Fixup to set vararg frame on shadow area (4 x i64).
2426 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2428 // For X86-64, if there are vararg parameters that are passed via
2429 // registers, then we must store them to their spots on the stack so
2430 // they may be loaded by deferencing the result of va_next.
2431 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2432 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2433 FuncInfo->setRegSaveFrameIndex(
2434 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2438 // Store the integer parameter registers.
2439 SmallVector<SDValue, 8> MemOps;
2440 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2442 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2443 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2444 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2445 DAG.getIntPtrConstant(Offset));
2446 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2447 &X86::GR64RegClass);
2448 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2450 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2451 MachinePointerInfo::getFixedStack(
2452 FuncInfo->getRegSaveFrameIndex(), Offset),
2454 MemOps.push_back(Store);
2458 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2459 // Now store the XMM (fp + vector) parameter registers.
2460 SmallVector<SDValue, 11> SaveXMMOps;
2461 SaveXMMOps.push_back(Chain);
2463 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2464 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2465 SaveXMMOps.push_back(ALVal);
2467 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2468 FuncInfo->getRegSaveFrameIndex()));
2469 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2470 FuncInfo->getVarArgsFPOffset()));
2472 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2473 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2474 &X86::VR128RegClass);
2475 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2476 SaveXMMOps.push_back(Val);
2478 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2479 MVT::Other, SaveXMMOps));
2482 if (!MemOps.empty())
2483 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2487 // Some CCs need callee pop.
2488 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2489 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2490 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2492 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2493 // If this is an sret function, the return should pop the hidden pointer.
2494 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2495 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2496 argsAreStructReturn(Ins) == StackStructReturn)
2497 FuncInfo->setBytesToPopOnReturn(4);
2501 // RegSaveFrameIndex is X86-64 only.
2502 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2503 if (CallConv == CallingConv::X86_FastCall ||
2504 CallConv == CallingConv::X86_ThisCall)
2505 // fastcc functions can't have varargs.
2506 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2509 FuncInfo->setArgumentStackSize(StackSize);
2515 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2516 SDValue StackPtr, SDValue Arg,
2517 SDLoc dl, SelectionDAG &DAG,
2518 const CCValAssign &VA,
2519 ISD::ArgFlagsTy Flags) const {
2520 unsigned LocMemOffset = VA.getLocMemOffset();
2521 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2522 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2523 if (Flags.isByVal())
2524 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2526 return DAG.getStore(Chain, dl, Arg, PtrOff,
2527 MachinePointerInfo::getStack(LocMemOffset),
2531 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2532 /// optimization is performed and it is required.
2534 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2535 SDValue &OutRetAddr, SDValue Chain,
2536 bool IsTailCall, bool Is64Bit,
2537 int FPDiff, SDLoc dl) const {
2538 // Adjust the Return address stack slot.
2539 EVT VT = getPointerTy();
2540 OutRetAddr = getReturnAddressFrameIndex(DAG);
2542 // Load the "old" Return address.
2543 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2544 false, false, false, 0);
2545 return SDValue(OutRetAddr.getNode(), 1);
2548 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2549 /// optimization is performed and it is required (FPDiff!=0).
2550 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2551 SDValue Chain, SDValue RetAddrFrIdx,
2552 EVT PtrVT, unsigned SlotSize,
2553 int FPDiff, SDLoc dl) {
2554 // Store the return address to the appropriate stack slot.
2555 if (!FPDiff) return Chain;
2556 // Calculate the new stack slot for the return address.
2557 int NewReturnAddrFI =
2558 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2560 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2561 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2562 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2568 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2569 SmallVectorImpl<SDValue> &InVals) const {
2570 SelectionDAG &DAG = CLI.DAG;
2572 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2573 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2574 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2575 SDValue Chain = CLI.Chain;
2576 SDValue Callee = CLI.Callee;
2577 CallingConv::ID CallConv = CLI.CallConv;
2578 bool &isTailCall = CLI.IsTailCall;
2579 bool isVarArg = CLI.IsVarArg;
2581 MachineFunction &MF = DAG.getMachineFunction();
2582 bool Is64Bit = Subtarget->is64Bit();
2583 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2584 StructReturnType SR = callIsStructReturn(Outs);
2585 bool IsSibcall = false;
2587 if (MF.getTarget().Options.DisableTailCalls)
2590 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2592 // Force this to be a tail call. The verifier rules are enough to ensure
2593 // that we can lower this successfully without moving the return address
2596 } else if (isTailCall) {
2597 // Check if it's really possible to do a tail call.
2598 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2599 isVarArg, SR != NotStructReturn,
2600 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2601 Outs, OutVals, Ins, DAG);
2603 // Sibcalls are automatically detected tailcalls which do not require
2605 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2612 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2613 "Var args not supported with calling convention fastcc, ghc or hipe");
2615 // Analyze operands of the call, assigning locations to each operand.
2616 SmallVector<CCValAssign, 16> ArgLocs;
2617 CCState CCInfo(CallConv, isVarArg, MF, MF.getTarget(),
2618 ArgLocs, *DAG.getContext());
2620 // Allocate shadow area for Win64
2622 CCInfo.AllocateStack(32, 8);
2624 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2626 // Get a count of how many bytes are to be pushed on the stack.
2627 unsigned NumBytes = CCInfo.getNextStackOffset();
2629 // This is a sibcall. The memory operands are available in caller's
2630 // own caller's stack.
2632 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2633 IsTailCallConvention(CallConv))
2634 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2637 if (isTailCall && !IsSibcall && !IsMustTail) {
2638 // Lower arguments at fp - stackoffset + fpdiff.
2639 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2640 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2642 FPDiff = NumBytesCallerPushed - NumBytes;
2644 // Set the delta of movement of the returnaddr stackslot.
2645 // But only set if delta is greater than previous delta.
2646 if (FPDiff < X86Info->getTCReturnAddrDelta())
2647 X86Info->setTCReturnAddrDelta(FPDiff);
2650 unsigned NumBytesToPush = NumBytes;
2651 unsigned NumBytesToPop = NumBytes;
2653 // If we have an inalloca argument, all stack space has already been allocated
2654 // for us and be right at the top of the stack. We don't support multiple
2655 // arguments passed in memory when using inalloca.
2656 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2658 assert(ArgLocs.back().getLocMemOffset() == 0 &&
2659 "an inalloca argument must be the only memory argument");
2663 Chain = DAG.getCALLSEQ_START(
2664 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2666 SDValue RetAddrFrIdx;
2667 // Load return address for tail calls.
2668 if (isTailCall && FPDiff)
2669 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2670 Is64Bit, FPDiff, dl);
2672 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2673 SmallVector<SDValue, 8> MemOpChains;
2676 // Walk the register/memloc assignments, inserting copies/loads. In the case
2677 // of tail call optimization arguments are handle later.
2678 const X86RegisterInfo *RegInfo =
2679 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
2680 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2681 // Skip inalloca arguments, they have already been written.
2682 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2683 if (Flags.isInAlloca())
2686 CCValAssign &VA = ArgLocs[i];
2687 EVT RegVT = VA.getLocVT();
2688 SDValue Arg = OutVals[i];
2689 bool isByVal = Flags.isByVal();
2691 // Promote the value if needed.
2692 switch (VA.getLocInfo()) {
2693 default: llvm_unreachable("Unknown loc info!");
2694 case CCValAssign::Full: break;
2695 case CCValAssign::SExt:
2696 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2698 case CCValAssign::ZExt:
2699 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2701 case CCValAssign::AExt:
2702 if (RegVT.is128BitVector()) {
2703 // Special case: passing MMX values in XMM registers.
2704 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2705 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2706 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2708 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2710 case CCValAssign::BCvt:
2711 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2713 case CCValAssign::Indirect: {
2714 // Store the argument.
2715 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2716 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2717 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2718 MachinePointerInfo::getFixedStack(FI),
2725 if (VA.isRegLoc()) {
2726 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2727 if (isVarArg && IsWin64) {
2728 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2729 // shadow reg if callee is a varargs function.
2730 unsigned ShadowReg = 0;
2731 switch (VA.getLocReg()) {
2732 case X86::XMM0: ShadowReg = X86::RCX; break;
2733 case X86::XMM1: ShadowReg = X86::RDX; break;
2734 case X86::XMM2: ShadowReg = X86::R8; break;
2735 case X86::XMM3: ShadowReg = X86::R9; break;
2738 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2740 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2741 assert(VA.isMemLoc());
2742 if (!StackPtr.getNode())
2743 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2745 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2746 dl, DAG, VA, Flags));
2750 if (!MemOpChains.empty())
2751 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2753 if (Subtarget->isPICStyleGOT()) {
2754 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2757 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2758 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2760 // If we are tail calling and generating PIC/GOT style code load the
2761 // address of the callee into ECX. The value in ecx is used as target of
2762 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2763 // for tail calls on PIC/GOT architectures. Normally we would just put the
2764 // address of GOT into ebx and then call target@PLT. But for tail calls
2765 // ebx would be restored (since ebx is callee saved) before jumping to the
2768 // Note: The actual moving to ECX is done further down.
2769 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2770 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2771 !G->getGlobal()->hasProtectedVisibility())
2772 Callee = LowerGlobalAddress(Callee, DAG);
2773 else if (isa<ExternalSymbolSDNode>(Callee))
2774 Callee = LowerExternalSymbol(Callee, DAG);
2778 if (Is64Bit && isVarArg && !IsWin64) {
2779 // From AMD64 ABI document:
2780 // For calls that may call functions that use varargs or stdargs
2781 // (prototype-less calls or calls to functions containing ellipsis (...) in
2782 // the declaration) %al is used as hidden argument to specify the number
2783 // of SSE registers used. The contents of %al do not need to match exactly
2784 // the number of registers, but must be an ubound on the number of SSE
2785 // registers used and is in the range 0 - 8 inclusive.
2787 // Count the number of XMM registers allocated.
2788 static const MCPhysReg XMMArgRegs[] = {
2789 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2790 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2792 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2793 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2794 && "SSE registers cannot be used when SSE is disabled");
2796 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2797 DAG.getConstant(NumXMMRegs, MVT::i8)));
2800 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2801 // don't need this because the eligibility check rejects calls that require
2802 // shuffling arguments passed in memory.
2803 if (!IsSibcall && isTailCall) {
2804 // Force all the incoming stack arguments to be loaded from the stack
2805 // before any new outgoing arguments are stored to the stack, because the
2806 // outgoing stack slots may alias the incoming argument stack slots, and
2807 // the alias isn't otherwise explicit. This is slightly more conservative
2808 // than necessary, because it means that each store effectively depends
2809 // on every argument instead of just those arguments it would clobber.
2810 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2812 SmallVector<SDValue, 8> MemOpChains2;
2815 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2816 CCValAssign &VA = ArgLocs[i];
2819 assert(VA.isMemLoc());
2820 SDValue Arg = OutVals[i];
2821 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2822 // Skip inalloca arguments. They don't require any work.
2823 if (Flags.isInAlloca())
2825 // Create frame index.
2826 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2827 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2828 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2829 FIN = DAG.getFrameIndex(FI, getPointerTy());
2831 if (Flags.isByVal()) {
2832 // Copy relative to framepointer.
2833 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2834 if (!StackPtr.getNode())
2835 StackPtr = DAG.getCopyFromReg(Chain, dl,
2836 RegInfo->getStackRegister(),
2838 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2840 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2844 // Store relative to framepointer.
2845 MemOpChains2.push_back(
2846 DAG.getStore(ArgChain, dl, Arg, FIN,
2847 MachinePointerInfo::getFixedStack(FI),
2852 if (!MemOpChains2.empty())
2853 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
2855 // Store the return address to the appropriate stack slot.
2856 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2857 getPointerTy(), RegInfo->getSlotSize(),
2861 // Build a sequence of copy-to-reg nodes chained together with token chain
2862 // and flag operands which copy the outgoing args into registers.
2864 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2865 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2866 RegsToPass[i].second, InFlag);
2867 InFlag = Chain.getValue(1);
2870 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
2871 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2872 // In the 64-bit large code model, we have to make all calls
2873 // through a register, since the call instruction's 32-bit
2874 // pc-relative offset may not be large enough to hold the whole
2876 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2877 // If the callee is a GlobalAddress node (quite common, every direct call
2878 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2881 // We should use extra load for direct calls to dllimported functions in
2883 const GlobalValue *GV = G->getGlobal();
2884 if (!GV->hasDLLImportStorageClass()) {
2885 unsigned char OpFlags = 0;
2886 bool ExtraLoad = false;
2887 unsigned WrapperKind = ISD::DELETED_NODE;
2889 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2890 // external symbols most go through the PLT in PIC mode. If the symbol
2891 // has hidden or protected visibility, or if it is static or local, then
2892 // we don't need to use the PLT - we can directly call it.
2893 if (Subtarget->isTargetELF() &&
2894 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
2895 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2896 OpFlags = X86II::MO_PLT;
2897 } else if (Subtarget->isPICStyleStubAny() &&
2898 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2899 (!Subtarget->getTargetTriple().isMacOSX() ||
2900 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2901 // PC-relative references to external symbols should go through $stub,
2902 // unless we're building with the leopard linker or later, which
2903 // automatically synthesizes these stubs.
2904 OpFlags = X86II::MO_DARWIN_STUB;
2905 } else if (Subtarget->isPICStyleRIPRel() &&
2906 isa<Function>(GV) &&
2907 cast<Function>(GV)->getAttributes().
2908 hasAttribute(AttributeSet::FunctionIndex,
2909 Attribute::NonLazyBind)) {
2910 // If the function is marked as non-lazy, generate an indirect call
2911 // which loads from the GOT directly. This avoids runtime overhead
2912 // at the cost of eager binding (and one extra byte of encoding).
2913 OpFlags = X86II::MO_GOTPCREL;
2914 WrapperKind = X86ISD::WrapperRIP;
2918 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2919 G->getOffset(), OpFlags);
2921 // Add a wrapper if needed.
2922 if (WrapperKind != ISD::DELETED_NODE)
2923 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2924 // Add extra indirection if needed.
2926 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2927 MachinePointerInfo::getGOT(),
2928 false, false, false, 0);
2930 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2931 unsigned char OpFlags = 0;
2933 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2934 // external symbols should go through the PLT.
2935 if (Subtarget->isTargetELF() &&
2936 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
2937 OpFlags = X86II::MO_PLT;
2938 } else if (Subtarget->isPICStyleStubAny() &&
2939 (!Subtarget->getTargetTriple().isMacOSX() ||
2940 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2941 // PC-relative references to external symbols should go through $stub,
2942 // unless we're building with the leopard linker or later, which
2943 // automatically synthesizes these stubs.
2944 OpFlags = X86II::MO_DARWIN_STUB;
2947 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2951 // Returns a chain & a flag for retval copy to use.
2952 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2953 SmallVector<SDValue, 8> Ops;
2955 if (!IsSibcall && isTailCall) {
2956 Chain = DAG.getCALLSEQ_END(Chain,
2957 DAG.getIntPtrConstant(NumBytesToPop, true),
2958 DAG.getIntPtrConstant(0, true), InFlag, dl);
2959 InFlag = Chain.getValue(1);
2962 Ops.push_back(Chain);
2963 Ops.push_back(Callee);
2966 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2968 // Add argument registers to the end of the list so that they are known live
2970 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2971 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2972 RegsToPass[i].second.getValueType()));
2974 // Add a register mask operand representing the call-preserved registers.
2975 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
2976 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2977 assert(Mask && "Missing call preserved mask for calling convention");
2978 Ops.push_back(DAG.getRegisterMask(Mask));
2980 if (InFlag.getNode())
2981 Ops.push_back(InFlag);
2985 //// If this is the first return lowered for this function, add the regs
2986 //// to the liveout set for the function.
2987 // This isn't right, although it's probably harmless on x86; liveouts
2988 // should be computed from returns not tail calls. Consider a void
2989 // function making a tail call to a function returning int.
2990 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
2993 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
2994 InFlag = Chain.getValue(1);
2996 // Create the CALLSEQ_END node.
2997 unsigned NumBytesForCalleeToPop;
2998 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2999 DAG.getTarget().Options.GuaranteedTailCallOpt))
3000 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3001 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3002 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3003 SR == StackStructReturn)
3004 // If this is a call to a struct-return function, the callee
3005 // pops the hidden struct pointer, so we have to push it back.
3006 // This is common for Darwin/X86, Linux & Mingw32 targets.
3007 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3008 NumBytesForCalleeToPop = 4;
3010 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3012 // Returns a flag for retval copy to use.
3014 Chain = DAG.getCALLSEQ_END(Chain,
3015 DAG.getIntPtrConstant(NumBytesToPop, true),
3016 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3019 InFlag = Chain.getValue(1);
3022 // Handle result values, copying them out of physregs into vregs that we
3024 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3025 Ins, dl, DAG, InVals);
3028 //===----------------------------------------------------------------------===//
3029 // Fast Calling Convention (tail call) implementation
3030 //===----------------------------------------------------------------------===//
3032 // Like std call, callee cleans arguments, convention except that ECX is
3033 // reserved for storing the tail called function address. Only 2 registers are
3034 // free for argument passing (inreg). Tail call optimization is performed
3036 // * tailcallopt is enabled
3037 // * caller/callee are fastcc
3038 // On X86_64 architecture with GOT-style position independent code only local
3039 // (within module) calls are supported at the moment.
3040 // To keep the stack aligned according to platform abi the function
3041 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3042 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3043 // If a tail called function callee has more arguments than the caller the
3044 // caller needs to make sure that there is room to move the RETADDR to. This is
3045 // achieved by reserving an area the size of the argument delta right after the
3046 // original REtADDR, but before the saved framepointer or the spilled registers
3047 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3059 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3060 /// for a 16 byte align requirement.
3062 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3063 SelectionDAG& DAG) const {
3064 MachineFunction &MF = DAG.getMachineFunction();
3065 const TargetMachine &TM = MF.getTarget();
3066 const X86RegisterInfo *RegInfo =
3067 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
3068 const TargetFrameLowering &TFI = *TM.getFrameLowering();
3069 unsigned StackAlignment = TFI.getStackAlignment();
3070 uint64_t AlignMask = StackAlignment - 1;
3071 int64_t Offset = StackSize;
3072 unsigned SlotSize = RegInfo->getSlotSize();
3073 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3074 // Number smaller than 12 so just add the difference.
3075 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3077 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3078 Offset = ((~AlignMask) & Offset) + StackAlignment +
3079 (StackAlignment-SlotSize);
3084 /// MatchingStackOffset - Return true if the given stack call argument is
3085 /// already available in the same position (relatively) of the caller's
3086 /// incoming argument stack.
3088 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3089 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3090 const X86InstrInfo *TII) {
3091 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3093 if (Arg.getOpcode() == ISD::CopyFromReg) {
3094 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3095 if (!TargetRegisterInfo::isVirtualRegister(VR))
3097 MachineInstr *Def = MRI->getVRegDef(VR);
3100 if (!Flags.isByVal()) {
3101 if (!TII->isLoadFromStackSlot(Def, FI))
3104 unsigned Opcode = Def->getOpcode();
3105 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3106 Def->getOperand(1).isFI()) {
3107 FI = Def->getOperand(1).getIndex();
3108 Bytes = Flags.getByValSize();
3112 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3113 if (Flags.isByVal())
3114 // ByVal argument is passed in as a pointer but it's now being
3115 // dereferenced. e.g.
3116 // define @foo(%struct.X* %A) {
3117 // tail call @bar(%struct.X* byval %A)
3120 SDValue Ptr = Ld->getBasePtr();
3121 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3124 FI = FINode->getIndex();
3125 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3126 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3127 FI = FINode->getIndex();
3128 Bytes = Flags.getByValSize();
3132 assert(FI != INT_MAX);
3133 if (!MFI->isFixedObjectIndex(FI))
3135 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3138 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3139 /// for tail call optimization. Targets which want to do tail call
3140 /// optimization should implement this function.
3142 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3143 CallingConv::ID CalleeCC,
3145 bool isCalleeStructRet,
3146 bool isCallerStructRet,
3148 const SmallVectorImpl<ISD::OutputArg> &Outs,
3149 const SmallVectorImpl<SDValue> &OutVals,
3150 const SmallVectorImpl<ISD::InputArg> &Ins,
3151 SelectionDAG &DAG) const {
3152 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3155 // If -tailcallopt is specified, make fastcc functions tail-callable.
3156 const MachineFunction &MF = DAG.getMachineFunction();
3157 const Function *CallerF = MF.getFunction();
3159 // If the function return type is x86_fp80 and the callee return type is not,
3160 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3161 // perform a tailcall optimization here.
3162 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3165 CallingConv::ID CallerCC = CallerF->getCallingConv();
3166 bool CCMatch = CallerCC == CalleeCC;
3167 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3168 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3170 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3171 if (IsTailCallConvention(CalleeCC) && CCMatch)
3176 // Look for obvious safe cases to perform tail call optimization that do not
3177 // require ABI changes. This is what gcc calls sibcall.
3179 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3180 // emit a special epilogue.
3181 const X86RegisterInfo *RegInfo =
3182 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
3183 if (RegInfo->needsStackRealignment(MF))
3186 // Also avoid sibcall optimization if either caller or callee uses struct
3187 // return semantics.
3188 if (isCalleeStructRet || isCallerStructRet)
3191 // An stdcall/thiscall caller is expected to clean up its arguments; the
3192 // callee isn't going to do that.
3193 // FIXME: this is more restrictive than needed. We could produce a tailcall
3194 // when the stack adjustment matches. For example, with a thiscall that takes
3195 // only one argument.
3196 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3197 CallerCC == CallingConv::X86_ThisCall))
3200 // Do not sibcall optimize vararg calls unless all arguments are passed via
3202 if (isVarArg && !Outs.empty()) {
3204 // Optimizing for varargs on Win64 is unlikely to be safe without
3205 // additional testing.
3206 if (IsCalleeWin64 || IsCallerWin64)
3209 SmallVector<CCValAssign, 16> ArgLocs;
3210 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3211 DAG.getTarget(), ArgLocs, *DAG.getContext());
3213 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3214 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3215 if (!ArgLocs[i].isRegLoc())
3219 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3220 // stack. Therefore, if it's not used by the call it is not safe to optimize
3221 // this into a sibcall.
3222 bool Unused = false;
3223 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3230 SmallVector<CCValAssign, 16> RVLocs;
3231 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
3232 DAG.getTarget(), RVLocs, *DAG.getContext());
3233 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3234 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3235 CCValAssign &VA = RVLocs[i];
3236 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
3241 // If the calling conventions do not match, then we'd better make sure the
3242 // results are returned in the same way as what the caller expects.
3244 SmallVector<CCValAssign, 16> RVLocs1;
3245 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
3246 DAG.getTarget(), RVLocs1, *DAG.getContext());
3247 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3249 SmallVector<CCValAssign, 16> RVLocs2;
3250 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
3251 DAG.getTarget(), RVLocs2, *DAG.getContext());
3252 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3254 if (RVLocs1.size() != RVLocs2.size())
3256 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3257 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3259 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3261 if (RVLocs1[i].isRegLoc()) {
3262 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3265 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3271 // If the callee takes no arguments then go on to check the results of the
3273 if (!Outs.empty()) {
3274 // Check if stack adjustment is needed. For now, do not do this if any
3275 // argument is passed on the stack.
3276 SmallVector<CCValAssign, 16> ArgLocs;
3277 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3278 DAG.getTarget(), ArgLocs, *DAG.getContext());
3280 // Allocate shadow area for Win64
3282 CCInfo.AllocateStack(32, 8);
3284 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3285 if (CCInfo.getNextStackOffset()) {
3286 MachineFunction &MF = DAG.getMachineFunction();
3287 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3290 // Check if the arguments are already laid out in the right way as
3291 // the caller's fixed stack objects.
3292 MachineFrameInfo *MFI = MF.getFrameInfo();
3293 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3294 const X86InstrInfo *TII =
3295 static_cast<const X86InstrInfo *>(DAG.getTarget().getInstrInfo());
3296 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3297 CCValAssign &VA = ArgLocs[i];
3298 SDValue Arg = OutVals[i];
3299 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3300 if (VA.getLocInfo() == CCValAssign::Indirect)
3302 if (!VA.isRegLoc()) {
3303 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3310 // If the tailcall address may be in a register, then make sure it's
3311 // possible to register allocate for it. In 32-bit, the call address can
3312 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3313 // callee-saved registers are restored. These happen to be the same
3314 // registers used to pass 'inreg' arguments so watch out for those.
3315 if (!Subtarget->is64Bit() &&
3316 ((!isa<GlobalAddressSDNode>(Callee) &&
3317 !isa<ExternalSymbolSDNode>(Callee)) ||
3318 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3319 unsigned NumInRegs = 0;
3320 // In PIC we need an extra register to formulate the address computation
3322 unsigned MaxInRegs =
3323 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3325 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3326 CCValAssign &VA = ArgLocs[i];
3329 unsigned Reg = VA.getLocReg();
3332 case X86::EAX: case X86::EDX: case X86::ECX:
3333 if (++NumInRegs == MaxInRegs)
3345 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3346 const TargetLibraryInfo *libInfo) const {
3347 return X86::createFastISel(funcInfo, libInfo);
3350 //===----------------------------------------------------------------------===//
3351 // Other Lowering Hooks
3352 //===----------------------------------------------------------------------===//
3354 static bool MayFoldLoad(SDValue Op) {
3355 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3358 static bool MayFoldIntoStore(SDValue Op) {
3359 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3362 static bool isTargetShuffle(unsigned Opcode) {
3364 default: return false;
3365 case X86ISD::PSHUFD:
3366 case X86ISD::PSHUFHW:
3367 case X86ISD::PSHUFLW:
3369 case X86ISD::PALIGNR:
3370 case X86ISD::MOVLHPS:
3371 case X86ISD::MOVLHPD:
3372 case X86ISD::MOVHLPS:
3373 case X86ISD::MOVLPS:
3374 case X86ISD::MOVLPD:
3375 case X86ISD::MOVSHDUP:
3376 case X86ISD::MOVSLDUP:
3377 case X86ISD::MOVDDUP:
3380 case X86ISD::UNPCKL:
3381 case X86ISD::UNPCKH:
3382 case X86ISD::VPERMILP:
3383 case X86ISD::VPERM2X128:
3384 case X86ISD::VPERMI:
3389 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3390 SDValue V1, SelectionDAG &DAG) {
3392 default: llvm_unreachable("Unknown x86 shuffle node");
3393 case X86ISD::MOVSHDUP:
3394 case X86ISD::MOVSLDUP:
3395 case X86ISD::MOVDDUP:
3396 return DAG.getNode(Opc, dl, VT, V1);
3400 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3401 SDValue V1, unsigned TargetMask,
3402 SelectionDAG &DAG) {
3404 default: llvm_unreachable("Unknown x86 shuffle node");
3405 case X86ISD::PSHUFD:
3406 case X86ISD::PSHUFHW:
3407 case X86ISD::PSHUFLW:
3408 case X86ISD::VPERMILP:
3409 case X86ISD::VPERMI:
3410 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3414 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3415 SDValue V1, SDValue V2, unsigned TargetMask,
3416 SelectionDAG &DAG) {
3418 default: llvm_unreachable("Unknown x86 shuffle node");
3419 case X86ISD::PALIGNR:
3421 case X86ISD::VPERM2X128:
3422 return DAG.getNode(Opc, dl, VT, V1, V2,
3423 DAG.getConstant(TargetMask, MVT::i8));
3427 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3428 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3430 default: llvm_unreachable("Unknown x86 shuffle node");
3431 case X86ISD::MOVLHPS:
3432 case X86ISD::MOVLHPD:
3433 case X86ISD::MOVHLPS:
3434 case X86ISD::MOVLPS:
3435 case X86ISD::MOVLPD:
3438 case X86ISD::UNPCKL:
3439 case X86ISD::UNPCKH:
3440 return DAG.getNode(Opc, dl, VT, V1, V2);
3444 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3445 MachineFunction &MF = DAG.getMachineFunction();
3446 const X86RegisterInfo *RegInfo =
3447 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
3448 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3449 int ReturnAddrIndex = FuncInfo->getRAIndex();
3451 if (ReturnAddrIndex == 0) {
3452 // Set up a frame object for the return address.
3453 unsigned SlotSize = RegInfo->getSlotSize();
3454 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3457 FuncInfo->setRAIndex(ReturnAddrIndex);
3460 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3463 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3464 bool hasSymbolicDisplacement) {
3465 // Offset should fit into 32 bit immediate field.
3466 if (!isInt<32>(Offset))
3469 // If we don't have a symbolic displacement - we don't have any extra
3471 if (!hasSymbolicDisplacement)
3474 // FIXME: Some tweaks might be needed for medium code model.
3475 if (M != CodeModel::Small && M != CodeModel::Kernel)
3478 // For small code model we assume that latest object is 16MB before end of 31
3479 // bits boundary. We may also accept pretty large negative constants knowing
3480 // that all objects are in the positive half of address space.
3481 if (M == CodeModel::Small && Offset < 16*1024*1024)
3484 // For kernel code model we know that all object resist in the negative half
3485 // of 32bits address space. We may not accept negative offsets, since they may
3486 // be just off and we may accept pretty large positive ones.
3487 if (M == CodeModel::Kernel && Offset > 0)
3493 /// isCalleePop - Determines whether the callee is required to pop its
3494 /// own arguments. Callee pop is necessary to support tail calls.
3495 bool X86::isCalleePop(CallingConv::ID CallingConv,
3496 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3500 switch (CallingConv) {
3503 case CallingConv::X86_StdCall:
3505 case CallingConv::X86_FastCall:
3507 case CallingConv::X86_ThisCall:
3509 case CallingConv::Fast:
3511 case CallingConv::GHC:
3513 case CallingConv::HiPE:
3518 /// \brief Return true if the condition is an unsigned comparison operation.
3519 static bool isX86CCUnsigned(unsigned X86CC) {
3521 default: llvm_unreachable("Invalid integer condition!");
3522 case X86::COND_E: return true;
3523 case X86::COND_G: return false;
3524 case X86::COND_GE: return false;
3525 case X86::COND_L: return false;
3526 case X86::COND_LE: return false;
3527 case X86::COND_NE: return true;
3528 case X86::COND_B: return true;
3529 case X86::COND_A: return true;
3530 case X86::COND_BE: return true;
3531 case X86::COND_AE: return true;
3533 llvm_unreachable("covered switch fell through?!");
3536 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3537 /// specific condition code, returning the condition code and the LHS/RHS of the
3538 /// comparison to make.
3539 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3540 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3542 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3543 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3544 // X > -1 -> X == 0, jump !sign.
3545 RHS = DAG.getConstant(0, RHS.getValueType());
3546 return X86::COND_NS;
3548 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3549 // X < 0 -> X == 0, jump on sign.
3552 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3554 RHS = DAG.getConstant(0, RHS.getValueType());
3555 return X86::COND_LE;
3559 switch (SetCCOpcode) {
3560 default: llvm_unreachable("Invalid integer condition!");
3561 case ISD::SETEQ: return X86::COND_E;
3562 case ISD::SETGT: return X86::COND_G;
3563 case ISD::SETGE: return X86::COND_GE;
3564 case ISD::SETLT: return X86::COND_L;
3565 case ISD::SETLE: return X86::COND_LE;
3566 case ISD::SETNE: return X86::COND_NE;
3567 case ISD::SETULT: return X86::COND_B;
3568 case ISD::SETUGT: return X86::COND_A;
3569 case ISD::SETULE: return X86::COND_BE;
3570 case ISD::SETUGE: return X86::COND_AE;
3574 // First determine if it is required or is profitable to flip the operands.
3576 // If LHS is a foldable load, but RHS is not, flip the condition.
3577 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3578 !ISD::isNON_EXTLoad(RHS.getNode())) {
3579 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3580 std::swap(LHS, RHS);
3583 switch (SetCCOpcode) {
3589 std::swap(LHS, RHS);
3593 // On a floating point condition, the flags are set as follows:
3595 // 0 | 0 | 0 | X > Y
3596 // 0 | 0 | 1 | X < Y
3597 // 1 | 0 | 0 | X == Y
3598 // 1 | 1 | 1 | unordered
3599 switch (SetCCOpcode) {
3600 default: llvm_unreachable("Condcode should be pre-legalized away");
3602 case ISD::SETEQ: return X86::COND_E;
3603 case ISD::SETOLT: // flipped
3605 case ISD::SETGT: return X86::COND_A;
3606 case ISD::SETOLE: // flipped
3608 case ISD::SETGE: return X86::COND_AE;
3609 case ISD::SETUGT: // flipped
3611 case ISD::SETLT: return X86::COND_B;
3612 case ISD::SETUGE: // flipped
3614 case ISD::SETLE: return X86::COND_BE;
3616 case ISD::SETNE: return X86::COND_NE;
3617 case ISD::SETUO: return X86::COND_P;
3618 case ISD::SETO: return X86::COND_NP;
3620 case ISD::SETUNE: return X86::COND_INVALID;
3624 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3625 /// code. Current x86 isa includes the following FP cmov instructions:
3626 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3627 static bool hasFPCMov(unsigned X86CC) {
3643 /// isFPImmLegal - Returns true if the target can instruction select the
3644 /// specified FP immediate natively. If false, the legalizer will
3645 /// materialize the FP immediate as a load from a constant pool.
3646 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3647 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3648 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3654 /// \brief Returns true if it is beneficial to convert a load of a constant
3655 /// to just the constant itself.
3656 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3658 assert(Ty->isIntegerTy());
3660 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3661 if (BitSize == 0 || BitSize > 64)
3666 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3667 /// the specified range (L, H].
3668 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3669 return (Val < 0) || (Val >= Low && Val < Hi);
3672 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3673 /// specified value.
3674 static bool isUndefOrEqual(int Val, int CmpVal) {
3675 return (Val < 0 || Val == CmpVal);
3678 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3679 /// from position Pos and ending in Pos+Size, falls within the specified
3680 /// sequential range (L, L+Pos]. or is undef.
3681 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3682 unsigned Pos, unsigned Size, int Low) {
3683 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3684 if (!isUndefOrEqual(Mask[i], Low))
3689 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3690 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3691 /// the second operand.
3692 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3693 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3694 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3695 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3696 return (Mask[0] < 2 && Mask[1] < 2);
3700 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3701 /// is suitable for input to PSHUFHW.
3702 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3703 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3706 // Lower quadword copied in order or undef.
3707 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3710 // Upper quadword shuffled.
3711 for (unsigned i = 4; i != 8; ++i)
3712 if (!isUndefOrInRange(Mask[i], 4, 8))
3715 if (VT == MVT::v16i16) {
3716 // Lower quadword copied in order or undef.
3717 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3720 // Upper quadword shuffled.
3721 for (unsigned i = 12; i != 16; ++i)
3722 if (!isUndefOrInRange(Mask[i], 12, 16))
3729 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3730 /// is suitable for input to PSHUFLW.
3731 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3732 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3735 // Upper quadword copied in order.
3736 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3739 // Lower quadword shuffled.
3740 for (unsigned i = 0; i != 4; ++i)
3741 if (!isUndefOrInRange(Mask[i], 0, 4))
3744 if (VT == MVT::v16i16) {
3745 // Upper quadword copied in order.
3746 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3749 // Lower quadword shuffled.
3750 for (unsigned i = 8; i != 12; ++i)
3751 if (!isUndefOrInRange(Mask[i], 8, 12))
3758 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3759 /// is suitable for input to PALIGNR.
3760 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
3761 const X86Subtarget *Subtarget) {
3762 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3763 (VT.is256BitVector() && !Subtarget->hasInt256()))
3766 unsigned NumElts = VT.getVectorNumElements();
3767 unsigned NumLanes = VT.is512BitVector() ? 1: VT.getSizeInBits()/128;
3768 unsigned NumLaneElts = NumElts/NumLanes;
3770 // Do not handle 64-bit element shuffles with palignr.
3771 if (NumLaneElts == 2)
3774 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3776 for (i = 0; i != NumLaneElts; ++i) {
3781 // Lane is all undef, go to next lane
3782 if (i == NumLaneElts)
3785 int Start = Mask[i+l];
3787 // Make sure its in this lane in one of the sources
3788 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3789 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3792 // If not lane 0, then we must match lane 0
3793 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3796 // Correct second source to be contiguous with first source
3797 if (Start >= (int)NumElts)
3798 Start -= NumElts - NumLaneElts;
3800 // Make sure we're shifting in the right direction.
3801 if (Start <= (int)(i+l))
3806 // Check the rest of the elements to see if they are consecutive.
3807 for (++i; i != NumLaneElts; ++i) {
3808 int Idx = Mask[i+l];
3810 // Make sure its in this lane
3811 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3812 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3815 // If not lane 0, then we must match lane 0
3816 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3819 if (Idx >= (int)NumElts)
3820 Idx -= NumElts - NumLaneElts;
3822 if (!isUndefOrEqual(Idx, Start+i))
3831 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3832 /// the two vector operands have swapped position.
3833 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3834 unsigned NumElems) {
3835 for (unsigned i = 0; i != NumElems; ++i) {
3839 else if (idx < (int)NumElems)
3840 Mask[i] = idx + NumElems;
3842 Mask[i] = idx - NumElems;
3846 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3847 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3848 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3849 /// reverse of what x86 shuffles want.
3850 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
3852 unsigned NumElems = VT.getVectorNumElements();
3853 unsigned NumLanes = VT.getSizeInBits()/128;
3854 unsigned NumLaneElems = NumElems/NumLanes;
3856 if (NumLaneElems != 2 && NumLaneElems != 4)
3859 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3860 bool symetricMaskRequired =
3861 (VT.getSizeInBits() >= 256) && (EltSize == 32);
3863 // VSHUFPSY divides the resulting vector into 4 chunks.
3864 // The sources are also splitted into 4 chunks, and each destination
3865 // chunk must come from a different source chunk.
3867 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3868 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3870 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3871 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3873 // VSHUFPDY divides the resulting vector into 4 chunks.
3874 // The sources are also splitted into 4 chunks, and each destination
3875 // chunk must come from a different source chunk.
3877 // SRC1 => X3 X2 X1 X0
3878 // SRC2 => Y3 Y2 Y1 Y0
3880 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3882 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
3883 unsigned HalfLaneElems = NumLaneElems/2;
3884 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3885 for (unsigned i = 0; i != NumLaneElems; ++i) {
3886 int Idx = Mask[i+l];
3887 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3888 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3890 // For VSHUFPSY, the mask of the second half must be the same as the
3891 // first but with the appropriate offsets. This works in the same way as
3892 // VPERMILPS works with masks.
3893 if (!symetricMaskRequired || Idx < 0)
3895 if (MaskVal[i] < 0) {
3896 MaskVal[i] = Idx - l;
3899 if ((signed)(Idx - l) != MaskVal[i])
3907 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3908 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3909 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
3910 if (!VT.is128BitVector())
3913 unsigned NumElems = VT.getVectorNumElements();
3918 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3919 return isUndefOrEqual(Mask[0], 6) &&
3920 isUndefOrEqual(Mask[1], 7) &&
3921 isUndefOrEqual(Mask[2], 2) &&
3922 isUndefOrEqual(Mask[3], 3);
3925 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3926 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3928 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
3929 if (!VT.is128BitVector())
3932 unsigned NumElems = VT.getVectorNumElements();
3937 return isUndefOrEqual(Mask[0], 2) &&
3938 isUndefOrEqual(Mask[1], 3) &&
3939 isUndefOrEqual(Mask[2], 2) &&
3940 isUndefOrEqual(Mask[3], 3);
3943 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3944 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3945 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
3946 if (!VT.is128BitVector())
3949 unsigned NumElems = VT.getVectorNumElements();
3951 if (NumElems != 2 && NumElems != 4)
3954 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3955 if (!isUndefOrEqual(Mask[i], i + NumElems))
3958 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3959 if (!isUndefOrEqual(Mask[i], i))
3965 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3966 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3967 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
3968 if (!VT.is128BitVector())
3971 unsigned NumElems = VT.getVectorNumElements();
3973 if (NumElems != 2 && NumElems != 4)
3976 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3977 if (!isUndefOrEqual(Mask[i], i))
3980 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3981 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3987 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
3988 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
3989 /// i. e: If all but one element come from the same vector.
3990 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
3991 // TODO: Deal with AVX's VINSERTPS
3992 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
3995 unsigned CorrectPosV1 = 0;
3996 unsigned CorrectPosV2 = 0;
3997 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
3998 if (Mask[i] == -1) {
4006 else if (Mask[i] == i + 4)
4010 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4011 // We have 3 elements (undefs count as elements from any vector) from one
4012 // vector, and one from another.
4019 // Some special combinations that can be optimized.
4022 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4023 SelectionDAG &DAG) {
4024 MVT VT = SVOp->getSimpleValueType(0);
4027 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4030 ArrayRef<int> Mask = SVOp->getMask();
4032 // These are the special masks that may be optimized.
4033 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4034 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4035 bool MatchEvenMask = true;
4036 bool MatchOddMask = true;
4037 for (int i=0; i<8; ++i) {
4038 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4039 MatchEvenMask = false;
4040 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4041 MatchOddMask = false;
4044 if (!MatchEvenMask && !MatchOddMask)
4047 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4049 SDValue Op0 = SVOp->getOperand(0);
4050 SDValue Op1 = SVOp->getOperand(1);
4052 if (MatchEvenMask) {
4053 // Shift the second operand right to 32 bits.
4054 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4055 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4057 // Shift the first operand left to 32 bits.
4058 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4059 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4061 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4062 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4065 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4066 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4067 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4068 bool HasInt256, bool V2IsSplat = false) {
4070 assert(VT.getSizeInBits() >= 128 &&
4071 "Unsupported vector type for unpckl");
4073 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4075 unsigned NumOf256BitLanes;
4076 unsigned NumElts = VT.getVectorNumElements();
4077 if (VT.is256BitVector()) {
4078 if (NumElts != 4 && NumElts != 8 &&
4079 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4082 NumOf256BitLanes = 1;
4083 } else if (VT.is512BitVector()) {
4084 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4085 "Unsupported vector type for unpckh");
4087 NumOf256BitLanes = 2;
4090 NumOf256BitLanes = 1;
4093 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4094 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4096 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4097 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4098 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4099 int BitI = Mask[l256*NumEltsInStride+l+i];
4100 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4101 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4103 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4105 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4113 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4114 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4115 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4116 bool HasInt256, bool V2IsSplat = false) {
4117 assert(VT.getSizeInBits() >= 128 &&
4118 "Unsupported vector type for unpckh");
4120 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4122 unsigned NumOf256BitLanes;
4123 unsigned NumElts = VT.getVectorNumElements();
4124 if (VT.is256BitVector()) {
4125 if (NumElts != 4 && NumElts != 8 &&
4126 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4129 NumOf256BitLanes = 1;
4130 } else if (VT.is512BitVector()) {
4131 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4132 "Unsupported vector type for unpckh");
4134 NumOf256BitLanes = 2;
4137 NumOf256BitLanes = 1;
4140 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4141 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4143 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4144 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4145 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4146 int BitI = Mask[l256*NumEltsInStride+l+i];
4147 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4148 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4150 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4152 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4160 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4161 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4163 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4164 unsigned NumElts = VT.getVectorNumElements();
4165 bool Is256BitVec = VT.is256BitVector();
4167 if (VT.is512BitVector())
4169 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4170 "Unsupported vector type for unpckh");
4172 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4173 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4176 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4177 // FIXME: Need a better way to get rid of this, there's no latency difference
4178 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4179 // the former later. We should also remove the "_undef" special mask.
4180 if (NumElts == 4 && Is256BitVec)
4183 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4184 // independently on 128-bit lanes.
4185 unsigned NumLanes = VT.getSizeInBits()/128;
4186 unsigned NumLaneElts = NumElts/NumLanes;
4188 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4189 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4190 int BitI = Mask[l+i];
4191 int BitI1 = Mask[l+i+1];
4193 if (!isUndefOrEqual(BitI, j))
4195 if (!isUndefOrEqual(BitI1, j))
4203 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4204 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4206 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4207 unsigned NumElts = VT.getVectorNumElements();
4209 if (VT.is512BitVector())
4212 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4213 "Unsupported vector type for unpckh");
4215 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4216 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4219 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4220 // independently on 128-bit lanes.
4221 unsigned NumLanes = VT.getSizeInBits()/128;
4222 unsigned NumLaneElts = NumElts/NumLanes;
4224 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4225 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4226 int BitI = Mask[l+i];
4227 int BitI1 = Mask[l+i+1];
4228 if (!isUndefOrEqual(BitI, j))
4230 if (!isUndefOrEqual(BitI1, j))
4237 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4238 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4239 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4240 if (!VT.is512BitVector())
4243 unsigned NumElts = VT.getVectorNumElements();
4244 unsigned HalfSize = NumElts/2;
4245 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4246 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4251 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4252 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4260 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4261 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4262 /// MOVSD, and MOVD, i.e. setting the lowest element.
4263 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4264 if (VT.getVectorElementType().getSizeInBits() < 32)
4266 if (!VT.is128BitVector())
4269 unsigned NumElts = VT.getVectorNumElements();
4271 if (!isUndefOrEqual(Mask[0], NumElts))
4274 for (unsigned i = 1; i != NumElts; ++i)
4275 if (!isUndefOrEqual(Mask[i], i))
4281 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4282 /// as permutations between 128-bit chunks or halves. As an example: this
4284 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4285 /// The first half comes from the second half of V1 and the second half from the
4286 /// the second half of V2.
4287 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4288 if (!HasFp256 || !VT.is256BitVector())
4291 // The shuffle result is divided into half A and half B. In total the two
4292 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4293 // B must come from C, D, E or F.
4294 unsigned HalfSize = VT.getVectorNumElements()/2;
4295 bool MatchA = false, MatchB = false;
4297 // Check if A comes from one of C, D, E, F.
4298 for (unsigned Half = 0; Half != 4; ++Half) {
4299 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4305 // Check if B comes from one of C, D, E, F.
4306 for (unsigned Half = 0; Half != 4; ++Half) {
4307 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4313 return MatchA && MatchB;
4316 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4317 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4318 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4319 MVT VT = SVOp->getSimpleValueType(0);
4321 unsigned HalfSize = VT.getVectorNumElements()/2;
4323 unsigned FstHalf = 0, SndHalf = 0;
4324 for (unsigned i = 0; i < HalfSize; ++i) {
4325 if (SVOp->getMaskElt(i) > 0) {
4326 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4330 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4331 if (SVOp->getMaskElt(i) > 0) {
4332 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4337 return (FstHalf | (SndHalf << 4));
4340 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4341 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4342 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4346 unsigned NumElts = VT.getVectorNumElements();
4348 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4349 for (unsigned i = 0; i != NumElts; ++i) {
4352 Imm8 |= Mask[i] << (i*2);
4357 unsigned LaneSize = 4;
4358 SmallVector<int, 4> MaskVal(LaneSize, -1);
4360 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4361 for (unsigned i = 0; i != LaneSize; ++i) {
4362 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4366 if (MaskVal[i] < 0) {
4367 MaskVal[i] = Mask[i+l] - l;
4368 Imm8 |= MaskVal[i] << (i*2);
4371 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4378 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4379 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4380 /// Note that VPERMIL mask matching is different depending whether theunderlying
4381 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4382 /// to the same elements of the low, but to the higher half of the source.
4383 /// In VPERMILPD the two lanes could be shuffled independently of each other
4384 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4385 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4386 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4387 if (VT.getSizeInBits() < 256 || EltSize < 32)
4389 bool symetricMaskRequired = (EltSize == 32);
4390 unsigned NumElts = VT.getVectorNumElements();
4392 unsigned NumLanes = VT.getSizeInBits()/128;
4393 unsigned LaneSize = NumElts/NumLanes;
4394 // 2 or 4 elements in one lane
4396 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4397 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4398 for (unsigned i = 0; i != LaneSize; ++i) {
4399 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4401 if (symetricMaskRequired) {
4402 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4403 ExpectedMaskVal[i] = Mask[i+l] - l;
4406 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4414 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4415 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4416 /// element of vector 2 and the other elements to come from vector 1 in order.
4417 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4418 bool V2IsSplat = false, bool V2IsUndef = false) {
4419 if (!VT.is128BitVector())
4422 unsigned NumOps = VT.getVectorNumElements();
4423 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4426 if (!isUndefOrEqual(Mask[0], 0))
4429 for (unsigned i = 1; i != NumOps; ++i)
4430 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4431 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4432 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4438 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4439 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4440 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4441 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4442 const X86Subtarget *Subtarget) {
4443 if (!Subtarget->hasSSE3())
4446 unsigned NumElems = VT.getVectorNumElements();
4448 if ((VT.is128BitVector() && NumElems != 4) ||
4449 (VT.is256BitVector() && NumElems != 8) ||
4450 (VT.is512BitVector() && NumElems != 16))
4453 // "i+1" is the value the indexed mask element must have
4454 for (unsigned i = 0; i != NumElems; i += 2)
4455 if (!isUndefOrEqual(Mask[i], i+1) ||
4456 !isUndefOrEqual(Mask[i+1], i+1))
4462 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4463 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4464 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4465 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4466 const X86Subtarget *Subtarget) {
4467 if (!Subtarget->hasSSE3())
4470 unsigned NumElems = VT.getVectorNumElements();
4472 if ((VT.is128BitVector() && NumElems != 4) ||
4473 (VT.is256BitVector() && NumElems != 8) ||
4474 (VT.is512BitVector() && NumElems != 16))
4477 // "i" is the value the indexed mask element must have
4478 for (unsigned i = 0; i != NumElems; i += 2)
4479 if (!isUndefOrEqual(Mask[i], i) ||
4480 !isUndefOrEqual(Mask[i+1], i))
4486 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4487 /// specifies a shuffle of elements that is suitable for input to 256-bit
4488 /// version of MOVDDUP.
4489 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4490 if (!HasFp256 || !VT.is256BitVector())
4493 unsigned NumElts = VT.getVectorNumElements();
4497 for (unsigned i = 0; i != NumElts/2; ++i)
4498 if (!isUndefOrEqual(Mask[i], 0))
4500 for (unsigned i = NumElts/2; i != NumElts; ++i)
4501 if (!isUndefOrEqual(Mask[i], NumElts/2))
4506 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4507 /// specifies a shuffle of elements that is suitable for input to 128-bit
4508 /// version of MOVDDUP.
4509 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4510 if (!VT.is128BitVector())
4513 unsigned e = VT.getVectorNumElements() / 2;
4514 for (unsigned i = 0; i != e; ++i)
4515 if (!isUndefOrEqual(Mask[i], i))
4517 for (unsigned i = 0; i != e; ++i)
4518 if (!isUndefOrEqual(Mask[e+i], i))
4523 /// isVEXTRACTIndex - Return true if the specified
4524 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4525 /// suitable for instruction that extract 128 or 256 bit vectors
4526 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4527 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4528 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4531 // The index should be aligned on a vecWidth-bit boundary.
4533 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4535 MVT VT = N->getSimpleValueType(0);
4536 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4537 bool Result = (Index * ElSize) % vecWidth == 0;
4542 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4543 /// operand specifies a subvector insert that is suitable for input to
4544 /// insertion of 128 or 256-bit subvectors
4545 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4546 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4547 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4549 // The index should be aligned on a vecWidth-bit boundary.
4551 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4553 MVT VT = N->getSimpleValueType(0);
4554 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4555 bool Result = (Index * ElSize) % vecWidth == 0;
4560 bool X86::isVINSERT128Index(SDNode *N) {
4561 return isVINSERTIndex(N, 128);
4564 bool X86::isVINSERT256Index(SDNode *N) {
4565 return isVINSERTIndex(N, 256);
4568 bool X86::isVEXTRACT128Index(SDNode *N) {
4569 return isVEXTRACTIndex(N, 128);
4572 bool X86::isVEXTRACT256Index(SDNode *N) {
4573 return isVEXTRACTIndex(N, 256);
4576 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4577 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4578 /// Handles 128-bit and 256-bit.
4579 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4580 MVT VT = N->getSimpleValueType(0);
4582 assert((VT.getSizeInBits() >= 128) &&
4583 "Unsupported vector type for PSHUF/SHUFP");
4585 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4586 // independently on 128-bit lanes.
4587 unsigned NumElts = VT.getVectorNumElements();
4588 unsigned NumLanes = VT.getSizeInBits()/128;
4589 unsigned NumLaneElts = NumElts/NumLanes;
4591 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4592 "Only supports 2, 4 or 8 elements per lane");
4594 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4596 for (unsigned i = 0; i != NumElts; ++i) {
4597 int Elt = N->getMaskElt(i);
4598 if (Elt < 0) continue;
4599 Elt &= NumLaneElts - 1;
4600 unsigned ShAmt = (i << Shift) % 8;
4601 Mask |= Elt << ShAmt;
4607 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4608 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4609 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4610 MVT VT = N->getSimpleValueType(0);
4612 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4613 "Unsupported vector type for PSHUFHW");
4615 unsigned NumElts = VT.getVectorNumElements();
4618 for (unsigned l = 0; l != NumElts; l += 8) {
4619 // 8 nodes per lane, but we only care about the last 4.
4620 for (unsigned i = 0; i < 4; ++i) {
4621 int Elt = N->getMaskElt(l+i+4);
4622 if (Elt < 0) continue;
4623 Elt &= 0x3; // only 2-bits.
4624 Mask |= Elt << (i * 2);
4631 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4632 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4633 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4634 MVT VT = N->getSimpleValueType(0);
4636 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4637 "Unsupported vector type for PSHUFHW");
4639 unsigned NumElts = VT.getVectorNumElements();
4642 for (unsigned l = 0; l != NumElts; l += 8) {
4643 // 8 nodes per lane, but we only care about the first 4.
4644 for (unsigned i = 0; i < 4; ++i) {
4645 int Elt = N->getMaskElt(l+i);
4646 if (Elt < 0) continue;
4647 Elt &= 0x3; // only 2-bits
4648 Mask |= Elt << (i * 2);
4655 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4656 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4657 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4658 MVT VT = SVOp->getSimpleValueType(0);
4659 unsigned EltSize = VT.is512BitVector() ? 1 :
4660 VT.getVectorElementType().getSizeInBits() >> 3;
4662 unsigned NumElts = VT.getVectorNumElements();
4663 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4664 unsigned NumLaneElts = NumElts/NumLanes;
4668 for (i = 0; i != NumElts; ++i) {
4669 Val = SVOp->getMaskElt(i);
4673 if (Val >= (int)NumElts)
4674 Val -= NumElts - NumLaneElts;
4676 assert(Val - i > 0 && "PALIGNR imm should be positive");
4677 return (Val - i) * EltSize;
4680 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4681 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4682 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4683 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4686 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4688 MVT VecVT = N->getOperand(0).getSimpleValueType();
4689 MVT ElVT = VecVT.getVectorElementType();
4691 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4692 return Index / NumElemsPerChunk;
4695 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4696 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4697 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4698 llvm_unreachable("Illegal insert subvector for VINSERT");
4701 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4703 MVT VecVT = N->getSimpleValueType(0);
4704 MVT ElVT = VecVT.getVectorElementType();
4706 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4707 return Index / NumElemsPerChunk;
4710 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4711 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4712 /// and VINSERTI128 instructions.
4713 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4714 return getExtractVEXTRACTImmediate(N, 128);
4717 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4718 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4719 /// and VINSERTI64x4 instructions.
4720 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4721 return getExtractVEXTRACTImmediate(N, 256);
4724 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4725 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4726 /// and VINSERTI128 instructions.
4727 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4728 return getInsertVINSERTImmediate(N, 128);
4731 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4732 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4733 /// and VINSERTI64x4 instructions.
4734 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4735 return getInsertVINSERTImmediate(N, 256);
4738 /// isZero - Returns true if Elt is a constant integer zero
4739 static bool isZero(SDValue V) {
4740 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4741 return C && C->isNullValue();
4744 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4746 bool X86::isZeroNode(SDValue Elt) {
4749 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4750 return CFP->getValueAPF().isPosZero();
4754 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4755 /// their permute mask.
4756 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4757 SelectionDAG &DAG) {
4758 MVT VT = SVOp->getSimpleValueType(0);
4759 unsigned NumElems = VT.getVectorNumElements();
4760 SmallVector<int, 8> MaskVec;
4762 for (unsigned i = 0; i != NumElems; ++i) {
4763 int Idx = SVOp->getMaskElt(i);
4765 if (Idx < (int)NumElems)
4770 MaskVec.push_back(Idx);
4772 return DAG.getVectorShuffle(VT, SDLoc(SVOp), SVOp->getOperand(1),
4773 SVOp->getOperand(0), &MaskVec[0]);
4776 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4777 /// match movhlps. The lower half elements should come from upper half of
4778 /// V1 (and in order), and the upper half elements should come from the upper
4779 /// half of V2 (and in order).
4780 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4781 if (!VT.is128BitVector())
4783 if (VT.getVectorNumElements() != 4)
4785 for (unsigned i = 0, e = 2; i != e; ++i)
4786 if (!isUndefOrEqual(Mask[i], i+2))
4788 for (unsigned i = 2; i != 4; ++i)
4789 if (!isUndefOrEqual(Mask[i], i+4))
4794 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4795 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4797 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4798 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4800 N = N->getOperand(0).getNode();
4801 if (!ISD::isNON_EXTLoad(N))
4804 *LD = cast<LoadSDNode>(N);
4808 // Test whether the given value is a vector value which will be legalized
4810 static bool WillBeConstantPoolLoad(SDNode *N) {
4811 if (N->getOpcode() != ISD::BUILD_VECTOR)
4814 // Check for any non-constant elements.
4815 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4816 switch (N->getOperand(i).getNode()->getOpcode()) {
4818 case ISD::ConstantFP:
4825 // Vectors of all-zeros and all-ones are materialized with special
4826 // instructions rather than being loaded.
4827 return !ISD::isBuildVectorAllZeros(N) &&
4828 !ISD::isBuildVectorAllOnes(N);
4831 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4832 /// match movlp{s|d}. The lower half elements should come from lower half of
4833 /// V1 (and in order), and the upper half elements should come from the upper
4834 /// half of V2 (and in order). And since V1 will become the source of the
4835 /// MOVLP, it must be either a vector load or a scalar load to vector.
4836 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4837 ArrayRef<int> Mask, MVT VT) {
4838 if (!VT.is128BitVector())
4841 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4843 // Is V2 is a vector load, don't do this transformation. We will try to use
4844 // load folding shufps op.
4845 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4848 unsigned NumElems = VT.getVectorNumElements();
4850 if (NumElems != 2 && NumElems != 4)
4852 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4853 if (!isUndefOrEqual(Mask[i], i))
4855 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4856 if (!isUndefOrEqual(Mask[i], i+NumElems))
4861 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4863 static bool isSplatVector(SDNode *N) {
4864 if (N->getOpcode() != ISD::BUILD_VECTOR)
4867 SDValue SplatValue = N->getOperand(0);
4868 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4869 if (N->getOperand(i) != SplatValue)
4874 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4875 /// to an zero vector.
4876 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4877 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4878 SDValue V1 = N->getOperand(0);
4879 SDValue V2 = N->getOperand(1);
4880 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4881 for (unsigned i = 0; i != NumElems; ++i) {
4882 int Idx = N->getMaskElt(i);
4883 if (Idx >= (int)NumElems) {
4884 unsigned Opc = V2.getOpcode();
4885 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4887 if (Opc != ISD::BUILD_VECTOR ||
4888 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4890 } else if (Idx >= 0) {
4891 unsigned Opc = V1.getOpcode();
4892 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4894 if (Opc != ISD::BUILD_VECTOR ||
4895 !X86::isZeroNode(V1.getOperand(Idx)))
4902 /// getZeroVector - Returns a vector of specified type with all zero elements.
4904 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4905 SelectionDAG &DAG, SDLoc dl) {
4906 assert(VT.isVector() && "Expected a vector type");
4908 // Always build SSE zero vectors as <4 x i32> bitcasted
4909 // to their dest type. This ensures they get CSE'd.
4911 if (VT.is128BitVector()) { // SSE
4912 if (Subtarget->hasSSE2()) { // SSE2
4913 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4914 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4916 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4917 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4919 } else if (VT.is256BitVector()) { // AVX
4920 if (Subtarget->hasInt256()) { // AVX2
4921 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4922 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4923 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4925 // 256-bit logic and arithmetic instructions in AVX are all
4926 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4927 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4928 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4929 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4931 } else if (VT.is512BitVector()) { // AVX-512
4932 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4933 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4934 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4935 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4936 } else if (VT.getScalarType() == MVT::i1) {
4937 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
4938 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
4939 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
4940 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4942 llvm_unreachable("Unexpected vector type");
4944 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4947 /// getOnesVector - Returns a vector of specified type with all bits set.
4948 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4949 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4950 /// Then bitcast to their original type, ensuring they get CSE'd.
4951 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4953 assert(VT.isVector() && "Expected a vector type");
4955 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4957 if (VT.is256BitVector()) {
4958 if (HasInt256) { // AVX2
4959 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4960 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4962 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4963 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4965 } else if (VT.is128BitVector()) {
4966 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4968 llvm_unreachable("Unexpected vector type");
4970 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4973 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4974 /// that point to V2 points to its first element.
4975 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4976 for (unsigned i = 0; i != NumElems; ++i) {
4977 if (Mask[i] > (int)NumElems) {
4983 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4984 /// operation of specified width.
4985 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4987 unsigned NumElems = VT.getVectorNumElements();
4988 SmallVector<int, 8> Mask;
4989 Mask.push_back(NumElems);
4990 for (unsigned i = 1; i != NumElems; ++i)
4992 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4995 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4996 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4998 unsigned NumElems = VT.getVectorNumElements();
4999 SmallVector<int, 8> Mask;
5000 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5002 Mask.push_back(i + NumElems);
5004 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5007 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5008 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5010 unsigned NumElems = VT.getVectorNumElements();
5011 SmallVector<int, 8> Mask;
5012 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5013 Mask.push_back(i + Half);
5014 Mask.push_back(i + NumElems + Half);
5016 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5019 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5020 // a generic shuffle instruction because the target has no such instructions.
5021 // Generate shuffles which repeat i16 and i8 several times until they can be
5022 // represented by v4f32 and then be manipulated by target suported shuffles.
5023 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5024 MVT VT = V.getSimpleValueType();
5025 int NumElems = VT.getVectorNumElements();
5028 while (NumElems > 4) {
5029 if (EltNo < NumElems/2) {
5030 V = getUnpackl(DAG, dl, VT, V, V);
5032 V = getUnpackh(DAG, dl, VT, V, V);
5033 EltNo -= NumElems/2;
5040 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5041 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5042 MVT VT = V.getSimpleValueType();
5045 if (VT.is128BitVector()) {
5046 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5047 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5048 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5050 } else if (VT.is256BitVector()) {
5051 // To use VPERMILPS to splat scalars, the second half of indicies must
5052 // refer to the higher part, which is a duplication of the lower one,
5053 // because VPERMILPS can only handle in-lane permutations.
5054 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5055 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5057 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5058 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5061 llvm_unreachable("Vector size not supported");
5063 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5066 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5067 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5068 MVT SrcVT = SV->getSimpleValueType(0);
5069 SDValue V1 = SV->getOperand(0);
5072 int EltNo = SV->getSplatIndex();
5073 int NumElems = SrcVT.getVectorNumElements();
5074 bool Is256BitVec = SrcVT.is256BitVector();
5076 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5077 "Unknown how to promote splat for type");
5079 // Extract the 128-bit part containing the splat element and update
5080 // the splat element index when it refers to the higher register.
5082 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5083 if (EltNo >= NumElems/2)
5084 EltNo -= NumElems/2;
5087 // All i16 and i8 vector types can't be used directly by a generic shuffle
5088 // instruction because the target has no such instruction. Generate shuffles
5089 // which repeat i16 and i8 several times until they fit in i32, and then can
5090 // be manipulated by target suported shuffles.
5091 MVT EltVT = SrcVT.getVectorElementType();
5092 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5093 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5095 // Recreate the 256-bit vector and place the same 128-bit vector
5096 // into the low and high part. This is necessary because we want
5097 // to use VPERM* to shuffle the vectors
5099 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5102 return getLegalSplat(DAG, V1, EltNo);
5105 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5106 /// vector of zero or undef vector. This produces a shuffle where the low
5107 /// element of V2 is swizzled into the zero/undef vector, landing at element
5108 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5109 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5111 const X86Subtarget *Subtarget,
5112 SelectionDAG &DAG) {
5113 MVT VT = V2.getSimpleValueType();
5115 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5116 unsigned NumElems = VT.getVectorNumElements();
5117 SmallVector<int, 16> MaskVec;
5118 for (unsigned i = 0; i != NumElems; ++i)
5119 // If this is the insertion idx, put the low elt of V2 here.
5120 MaskVec.push_back(i == Idx ? NumElems : i);
5121 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5124 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5125 /// target specific opcode. Returns true if the Mask could be calculated.
5126 /// Sets IsUnary to true if only uses one source.
5127 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5128 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5129 unsigned NumElems = VT.getVectorNumElements();
5133 switch(N->getOpcode()) {
5135 ImmN = N->getOperand(N->getNumOperands()-1);
5136 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5138 case X86ISD::UNPCKH:
5139 DecodeUNPCKHMask(VT, Mask);
5141 case X86ISD::UNPCKL:
5142 DecodeUNPCKLMask(VT, Mask);
5144 case X86ISD::MOVHLPS:
5145 DecodeMOVHLPSMask(NumElems, Mask);
5147 case X86ISD::MOVLHPS:
5148 DecodeMOVLHPSMask(NumElems, Mask);
5150 case X86ISD::PALIGNR:
5151 ImmN = N->getOperand(N->getNumOperands()-1);
5152 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5154 case X86ISD::PSHUFD:
5155 case X86ISD::VPERMILP:
5156 ImmN = N->getOperand(N->getNumOperands()-1);
5157 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5160 case X86ISD::PSHUFHW:
5161 ImmN = N->getOperand(N->getNumOperands()-1);
5162 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5165 case X86ISD::PSHUFLW:
5166 ImmN = N->getOperand(N->getNumOperands()-1);
5167 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5170 case X86ISD::VPERMI:
5171 ImmN = N->getOperand(N->getNumOperands()-1);
5172 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5176 case X86ISD::MOVSD: {
5177 // The index 0 always comes from the first element of the second source,
5178 // this is why MOVSS and MOVSD are used in the first place. The other
5179 // elements come from the other positions of the first source vector
5180 Mask.push_back(NumElems);
5181 for (unsigned i = 1; i != NumElems; ++i) {
5186 case X86ISD::VPERM2X128:
5187 ImmN = N->getOperand(N->getNumOperands()-1);
5188 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5189 if (Mask.empty()) return false;
5191 case X86ISD::MOVDDUP:
5192 case X86ISD::MOVLHPD:
5193 case X86ISD::MOVLPD:
5194 case X86ISD::MOVLPS:
5195 case X86ISD::MOVSHDUP:
5196 case X86ISD::MOVSLDUP:
5197 // Not yet implemented
5199 default: llvm_unreachable("unknown target shuffle node");
5205 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5206 /// element of the result of the vector shuffle.
5207 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5210 return SDValue(); // Limit search depth.
5212 SDValue V = SDValue(N, 0);
5213 EVT VT = V.getValueType();
5214 unsigned Opcode = V.getOpcode();
5216 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5217 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5218 int Elt = SV->getMaskElt(Index);
5221 return DAG.getUNDEF(VT.getVectorElementType());
5223 unsigned NumElems = VT.getVectorNumElements();
5224 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5225 : SV->getOperand(1);
5226 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5229 // Recurse into target specific vector shuffles to find scalars.
5230 if (isTargetShuffle(Opcode)) {
5231 MVT ShufVT = V.getSimpleValueType();
5232 unsigned NumElems = ShufVT.getVectorNumElements();
5233 SmallVector<int, 16> ShuffleMask;
5236 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5239 int Elt = ShuffleMask[Index];
5241 return DAG.getUNDEF(ShufVT.getVectorElementType());
5243 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5245 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5249 // Actual nodes that may contain scalar elements
5250 if (Opcode == ISD::BITCAST) {
5251 V = V.getOperand(0);
5252 EVT SrcVT = V.getValueType();
5253 unsigned NumElems = VT.getVectorNumElements();
5255 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5259 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5260 return (Index == 0) ? V.getOperand(0)
5261 : DAG.getUNDEF(VT.getVectorElementType());
5263 if (V.getOpcode() == ISD::BUILD_VECTOR)
5264 return V.getOperand(Index);
5269 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5270 /// shuffle operation which come from a consecutively from a zero. The
5271 /// search can start in two different directions, from left or right.
5272 /// We count undefs as zeros until PreferredNum is reached.
5273 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5274 unsigned NumElems, bool ZerosFromLeft,
5276 unsigned PreferredNum = -1U) {
5277 unsigned NumZeros = 0;
5278 for (unsigned i = 0; i != NumElems; ++i) {
5279 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5280 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5284 if (X86::isZeroNode(Elt))
5286 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5287 NumZeros = std::min(NumZeros + 1, PreferredNum);
5295 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5296 /// correspond consecutively to elements from one of the vector operands,
5297 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5299 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5300 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5301 unsigned NumElems, unsigned &OpNum) {
5302 bool SeenV1 = false;
5303 bool SeenV2 = false;
5305 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5306 int Idx = SVOp->getMaskElt(i);
5307 // Ignore undef indicies
5311 if (Idx < (int)NumElems)
5316 // Only accept consecutive elements from the same vector
5317 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5321 OpNum = SeenV1 ? 0 : 1;
5325 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5326 /// logical left shift of a vector.
5327 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5328 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5330 SVOp->getSimpleValueType(0).getVectorNumElements();
5331 unsigned NumZeros = getNumOfConsecutiveZeros(
5332 SVOp, NumElems, false /* check zeros from right */, DAG,
5333 SVOp->getMaskElt(0));
5339 // Considering the elements in the mask that are not consecutive zeros,
5340 // check if they consecutively come from only one of the source vectors.
5342 // V1 = {X, A, B, C} 0
5344 // vector_shuffle V1, V2 <1, 2, 3, X>
5346 if (!isShuffleMaskConsecutive(SVOp,
5347 0, // Mask Start Index
5348 NumElems-NumZeros, // Mask End Index(exclusive)
5349 NumZeros, // Where to start looking in the src vector
5350 NumElems, // Number of elements in vector
5351 OpSrc)) // Which source operand ?
5356 ShVal = SVOp->getOperand(OpSrc);
5360 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5361 /// logical left shift of a vector.
5362 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5363 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5365 SVOp->getSimpleValueType(0).getVectorNumElements();
5366 unsigned NumZeros = getNumOfConsecutiveZeros(
5367 SVOp, NumElems, true /* check zeros from left */, DAG,
5368 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5374 // Considering the elements in the mask that are not consecutive zeros,
5375 // check if they consecutively come from only one of the source vectors.
5377 // 0 { A, B, X, X } = V2
5379 // vector_shuffle V1, V2 <X, X, 4, 5>
5381 if (!isShuffleMaskConsecutive(SVOp,
5382 NumZeros, // Mask Start Index
5383 NumElems, // Mask End Index(exclusive)
5384 0, // Where to start looking in the src vector
5385 NumElems, // Number of elements in vector
5386 OpSrc)) // Which source operand ?
5391 ShVal = SVOp->getOperand(OpSrc);
5395 /// isVectorShift - Returns true if the shuffle can be implemented as a
5396 /// logical left or right shift of a vector.
5397 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5398 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5399 // Although the logic below support any bitwidth size, there are no
5400 // shift instructions which handle more than 128-bit vectors.
5401 if (!SVOp->getSimpleValueType(0).is128BitVector())
5404 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5405 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5411 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5413 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5414 unsigned NumNonZero, unsigned NumZero,
5416 const X86Subtarget* Subtarget,
5417 const TargetLowering &TLI) {
5424 for (unsigned i = 0; i < 16; ++i) {
5425 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5426 if (ThisIsNonZero && First) {
5428 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5430 V = DAG.getUNDEF(MVT::v8i16);
5435 SDValue ThisElt, LastElt;
5436 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5437 if (LastIsNonZero) {
5438 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5439 MVT::i16, Op.getOperand(i-1));
5441 if (ThisIsNonZero) {
5442 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5443 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5444 ThisElt, DAG.getConstant(8, MVT::i8));
5446 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5450 if (ThisElt.getNode())
5451 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5452 DAG.getIntPtrConstant(i/2));
5456 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5459 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5461 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5462 unsigned NumNonZero, unsigned NumZero,
5464 const X86Subtarget* Subtarget,
5465 const TargetLowering &TLI) {
5472 for (unsigned i = 0; i < 8; ++i) {
5473 bool isNonZero = (NonZeros & (1 << i)) != 0;
5477 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5479 V = DAG.getUNDEF(MVT::v8i16);
5482 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5483 MVT::v8i16, V, Op.getOperand(i),
5484 DAG.getIntPtrConstant(i));
5491 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5492 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5493 unsigned NonZeros, unsigned NumNonZero,
5494 unsigned NumZero, SelectionDAG &DAG,
5495 const X86Subtarget *Subtarget,
5496 const TargetLowering &TLI) {
5497 // We know there's at least one non-zero element
5498 unsigned FirstNonZeroIdx = 0;
5499 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5500 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5501 X86::isZeroNode(FirstNonZero)) {
5503 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5506 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5507 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5510 SDValue V = FirstNonZero.getOperand(0);
5511 MVT VVT = V.getSimpleValueType();
5512 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5515 unsigned FirstNonZeroDst =
5516 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5517 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5518 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5519 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5521 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5522 SDValue Elem = Op.getOperand(Idx);
5523 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5526 // TODO: What else can be here? Deal with it.
5527 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5530 // TODO: Some optimizations are still possible here
5531 // ex: Getting one element from a vector, and the rest from another.
5532 if (Elem.getOperand(0) != V)
5535 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5538 else if (IncorrectIdx == -1U) {
5542 // There was already one element with an incorrect index.
5543 // We can't optimize this case to an insertps.
5547 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5549 EVT VT = Op.getSimpleValueType();
5550 unsigned ElementMoveMask = 0;
5551 if (IncorrectIdx == -1U)
5552 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5554 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5556 SDValue InsertpsMask =
5557 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5558 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5564 /// getVShift - Return a vector logical shift node.
5566 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5567 unsigned NumBits, SelectionDAG &DAG,
5568 const TargetLowering &TLI, SDLoc dl) {
5569 assert(VT.is128BitVector() && "Unknown type for VShift");
5570 EVT ShVT = MVT::v2i64;
5571 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5572 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5573 return DAG.getNode(ISD::BITCAST, dl, VT,
5574 DAG.getNode(Opc, dl, ShVT, SrcOp,
5575 DAG.getConstant(NumBits,
5576 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5580 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5582 // Check if the scalar load can be widened into a vector load. And if
5583 // the address is "base + cst" see if the cst can be "absorbed" into
5584 // the shuffle mask.
5585 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5586 SDValue Ptr = LD->getBasePtr();
5587 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5589 EVT PVT = LD->getValueType(0);
5590 if (PVT != MVT::i32 && PVT != MVT::f32)
5595 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5596 FI = FINode->getIndex();
5598 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5599 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5600 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5601 Offset = Ptr.getConstantOperandVal(1);
5602 Ptr = Ptr.getOperand(0);
5607 // FIXME: 256-bit vector instructions don't require a strict alignment,
5608 // improve this code to support it better.
5609 unsigned RequiredAlign = VT.getSizeInBits()/8;
5610 SDValue Chain = LD->getChain();
5611 // Make sure the stack object alignment is at least 16 or 32.
5612 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5613 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5614 if (MFI->isFixedObjectIndex(FI)) {
5615 // Can't change the alignment. FIXME: It's possible to compute
5616 // the exact stack offset and reference FI + adjust offset instead.
5617 // If someone *really* cares about this. That's the way to implement it.
5620 MFI->setObjectAlignment(FI, RequiredAlign);
5624 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5625 // Ptr + (Offset & ~15).
5628 if ((Offset % RequiredAlign) & 3)
5630 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5632 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5633 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5635 int EltNo = (Offset - StartOffset) >> 2;
5636 unsigned NumElems = VT.getVectorNumElements();
5638 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5639 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5640 LD->getPointerInfo().getWithOffset(StartOffset),
5641 false, false, false, 0);
5643 SmallVector<int, 8> Mask;
5644 for (unsigned i = 0; i != NumElems; ++i)
5645 Mask.push_back(EltNo);
5647 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5653 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5654 /// vector of type 'VT', see if the elements can be replaced by a single large
5655 /// load which has the same value as a build_vector whose operands are 'elts'.
5657 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5659 /// FIXME: we'd also like to handle the case where the last elements are zero
5660 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5661 /// There's even a handy isZeroNode for that purpose.
5662 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5663 SDLoc &DL, SelectionDAG &DAG,
5664 bool isAfterLegalize) {
5665 EVT EltVT = VT.getVectorElementType();
5666 unsigned NumElems = Elts.size();
5668 LoadSDNode *LDBase = nullptr;
5669 unsigned LastLoadedElt = -1U;
5671 // For each element in the initializer, see if we've found a load or an undef.
5672 // If we don't find an initial load element, or later load elements are
5673 // non-consecutive, bail out.
5674 for (unsigned i = 0; i < NumElems; ++i) {
5675 SDValue Elt = Elts[i];
5677 if (!Elt.getNode() ||
5678 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5681 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5683 LDBase = cast<LoadSDNode>(Elt.getNode());
5687 if (Elt.getOpcode() == ISD::UNDEF)
5690 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5691 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5696 // If we have found an entire vector of loads and undefs, then return a large
5697 // load of the entire vector width starting at the base pointer. If we found
5698 // consecutive loads for the low half, generate a vzext_load node.
5699 if (LastLoadedElt == NumElems - 1) {
5701 if (isAfterLegalize &&
5702 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5705 SDValue NewLd = SDValue();
5707 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5708 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5709 LDBase->getPointerInfo(),
5710 LDBase->isVolatile(), LDBase->isNonTemporal(),
5711 LDBase->isInvariant(), 0);
5712 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5713 LDBase->getPointerInfo(),
5714 LDBase->isVolatile(), LDBase->isNonTemporal(),
5715 LDBase->isInvariant(), LDBase->getAlignment());
5717 if (LDBase->hasAnyUseOfValue(1)) {
5718 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5720 SDValue(NewLd.getNode(), 1));
5721 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5722 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5723 SDValue(NewLd.getNode(), 1));
5728 if (NumElems == 4 && LastLoadedElt == 1 &&
5729 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5730 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5731 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5733 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5734 LDBase->getPointerInfo(),
5735 LDBase->getAlignment(),
5736 false/*isVolatile*/, true/*ReadMem*/,
5739 // Make sure the newly-created LOAD is in the same position as LDBase in
5740 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5741 // update uses of LDBase's output chain to use the TokenFactor.
5742 if (LDBase->hasAnyUseOfValue(1)) {
5743 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5744 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5745 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5746 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5747 SDValue(ResNode.getNode(), 1));
5750 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5755 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5756 /// to generate a splat value for the following cases:
5757 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5758 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5759 /// a scalar load, or a constant.
5760 /// The VBROADCAST node is returned when a pattern is found,
5761 /// or SDValue() otherwise.
5762 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5763 SelectionDAG &DAG) {
5764 if (!Subtarget->hasFp256())
5767 MVT VT = Op.getSimpleValueType();
5770 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5771 "Unsupported vector type for broadcast.");
5776 switch (Op.getOpcode()) {
5778 // Unknown pattern found.
5781 case ISD::BUILD_VECTOR: {
5782 // The BUILD_VECTOR node must be a splat.
5783 if (!isSplatVector(Op.getNode()))
5786 Ld = Op.getOperand(0);
5787 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5788 Ld.getOpcode() == ISD::ConstantFP);
5790 // The suspected load node has several users. Make sure that all
5791 // of its users are from the BUILD_VECTOR node.
5792 // Constants may have multiple users.
5793 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5798 case ISD::VECTOR_SHUFFLE: {
5799 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5801 // Shuffles must have a splat mask where the first element is
5803 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5806 SDValue Sc = Op.getOperand(0);
5807 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5808 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5810 if (!Subtarget->hasInt256())
5813 // Use the register form of the broadcast instruction available on AVX2.
5814 if (VT.getSizeInBits() >= 256)
5815 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5816 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5819 Ld = Sc.getOperand(0);
5820 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5821 Ld.getOpcode() == ISD::ConstantFP);
5823 // The scalar_to_vector node and the suspected
5824 // load node must have exactly one user.
5825 // Constants may have multiple users.
5827 // AVX-512 has register version of the broadcast
5828 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5829 Ld.getValueType().getSizeInBits() >= 32;
5830 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5837 bool IsGE256 = (VT.getSizeInBits() >= 256);
5839 // Handle the broadcasting a single constant scalar from the constant pool
5840 // into a vector. On Sandybridge it is still better to load a constant vector
5841 // from the constant pool and not to broadcast it from a scalar.
5842 if (ConstSplatVal && Subtarget->hasInt256()) {
5843 EVT CVT = Ld.getValueType();
5844 assert(!CVT.isVector() && "Must not broadcast a vector type");
5845 unsigned ScalarSize = CVT.getSizeInBits();
5847 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
5848 const Constant *C = nullptr;
5849 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5850 C = CI->getConstantIntValue();
5851 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5852 C = CF->getConstantFPValue();
5854 assert(C && "Invalid constant type");
5856 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5857 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5858 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5859 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5860 MachinePointerInfo::getConstantPool(),
5861 false, false, false, Alignment);
5863 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5867 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5868 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5870 // Handle AVX2 in-register broadcasts.
5871 if (!IsLoad && Subtarget->hasInt256() &&
5872 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5873 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5875 // The scalar source must be a normal load.
5879 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
5880 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5882 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5883 // double since there is no vbroadcastsd xmm
5884 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5885 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5886 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5889 // Unsupported broadcast.
5893 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5894 /// underlying vector and index.
5896 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5898 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5900 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5901 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5904 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5906 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5908 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5909 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5912 // In this case the vector is the extract_subvector expression and the index
5913 // is 2, as specified by the shuffle.
5914 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5915 SDValue ShuffleVec = SVOp->getOperand(0);
5916 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5917 assert(ShuffleVecVT.getVectorElementType() ==
5918 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5920 int ShuffleIdx = SVOp->getMaskElt(Idx);
5921 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5922 ExtractedFromVec = ShuffleVec;
5928 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5929 MVT VT = Op.getSimpleValueType();
5931 // Skip if insert_vec_elt is not supported.
5932 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5933 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5937 unsigned NumElems = Op.getNumOperands();
5941 SmallVector<unsigned, 4> InsertIndices;
5942 SmallVector<int, 8> Mask(NumElems, -1);
5944 for (unsigned i = 0; i != NumElems; ++i) {
5945 unsigned Opc = Op.getOperand(i).getOpcode();
5947 if (Opc == ISD::UNDEF)
5950 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5951 // Quit if more than 1 elements need inserting.
5952 if (InsertIndices.size() > 1)
5955 InsertIndices.push_back(i);
5959 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5960 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5961 // Quit if non-constant index.
5962 if (!isa<ConstantSDNode>(ExtIdx))
5964 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5966 // Quit if extracted from vector of different type.
5967 if (ExtractedFromVec.getValueType() != VT)
5970 if (!VecIn1.getNode())
5971 VecIn1 = ExtractedFromVec;
5972 else if (VecIn1 != ExtractedFromVec) {
5973 if (!VecIn2.getNode())
5974 VecIn2 = ExtractedFromVec;
5975 else if (VecIn2 != ExtractedFromVec)
5976 // Quit if more than 2 vectors to shuffle
5980 if (ExtractedFromVec == VecIn1)
5982 else if (ExtractedFromVec == VecIn2)
5983 Mask[i] = Idx + NumElems;
5986 if (!VecIn1.getNode())
5989 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5990 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5991 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5992 unsigned Idx = InsertIndices[i];
5993 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5994 DAG.getIntPtrConstant(Idx));
6000 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6002 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6004 MVT VT = Op.getSimpleValueType();
6005 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6006 "Unexpected type in LowerBUILD_VECTORvXi1!");
6009 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6010 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6011 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6012 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6015 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6016 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6017 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6018 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6021 bool AllContants = true;
6022 uint64_t Immediate = 0;
6023 int NonConstIdx = -1;
6024 bool IsSplat = true;
6025 unsigned NumNonConsts = 0;
6026 unsigned NumConsts = 0;
6027 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6028 SDValue In = Op.getOperand(idx);
6029 if (In.getOpcode() == ISD::UNDEF)
6031 if (!isa<ConstantSDNode>(In)) {
6032 AllContants = false;
6038 if (cast<ConstantSDNode>(In)->getZExtValue())
6039 Immediate |= (1ULL << idx);
6041 if (In != Op.getOperand(0))
6046 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6047 DAG.getConstant(Immediate, MVT::i16));
6048 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6049 DAG.getIntPtrConstant(0));
6052 if (NumNonConsts == 1 && NonConstIdx != 0) {
6055 SDValue VecAsImm = DAG.getConstant(Immediate,
6056 MVT::getIntegerVT(VT.getSizeInBits()));
6057 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6060 DstVec = DAG.getUNDEF(VT);
6061 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6062 Op.getOperand(NonConstIdx),
6063 DAG.getIntPtrConstant(NonConstIdx));
6065 if (!IsSplat && (NonConstIdx != 0))
6066 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6067 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6070 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6071 DAG.getConstant(-1, SelectVT),
6072 DAG.getConstant(0, SelectVT));
6074 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6075 DAG.getConstant((Immediate | 1), SelectVT),
6076 DAG.getConstant(Immediate, SelectVT));
6077 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6080 /// \brief Return true if \p N implements a horizontal binop and return the
6081 /// operands for the horizontal binop into V0 and V1.
6083 /// This is a helper function of PerformBUILD_VECTORCombine.
6084 /// This function checks that the build_vector \p N in input implements a
6085 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6086 /// operation to match.
6087 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6088 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6089 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6092 /// This function only analyzes elements of \p N whose indices are
6093 /// in range [BaseIdx, LastIdx).
6094 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6096 unsigned BaseIdx, unsigned LastIdx,
6097 SDValue &V0, SDValue &V1) {
6098 EVT VT = N->getValueType(0);
6100 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6101 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6102 "Invalid Vector in input!");
6104 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6105 bool CanFold = true;
6106 unsigned ExpectedVExtractIdx = BaseIdx;
6107 unsigned NumElts = LastIdx - BaseIdx;
6108 V0 = DAG.getUNDEF(VT);
6109 V1 = DAG.getUNDEF(VT);
6111 // Check if N implements a horizontal binop.
6112 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6113 SDValue Op = N->getOperand(i + BaseIdx);
6116 if (Op->getOpcode() == ISD::UNDEF) {
6117 // Update the expected vector extract index.
6118 if (i * 2 == NumElts)
6119 ExpectedVExtractIdx = BaseIdx;
6120 ExpectedVExtractIdx += 2;
6124 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6129 SDValue Op0 = Op.getOperand(0);
6130 SDValue Op1 = Op.getOperand(1);
6132 // Try to match the following pattern:
6133 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6134 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6135 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6136 Op0.getOperand(0) == Op1.getOperand(0) &&
6137 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6138 isa<ConstantSDNode>(Op1.getOperand(1)));
6142 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6143 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6145 if (i * 2 < NumElts) {
6146 if (V0.getOpcode() == ISD::UNDEF)
6147 V0 = Op0.getOperand(0);
6149 if (V1.getOpcode() == ISD::UNDEF)
6150 V1 = Op0.getOperand(0);
6151 if (i * 2 == NumElts)
6152 ExpectedVExtractIdx = BaseIdx;
6155 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6156 if (I0 == ExpectedVExtractIdx)
6157 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6158 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6159 // Try to match the following dag sequence:
6160 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6161 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6165 ExpectedVExtractIdx += 2;
6171 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6172 /// a concat_vector.
6174 /// This is a helper function of PerformBUILD_VECTORCombine.
6175 /// This function expects two 256-bit vectors called V0 and V1.
6176 /// At first, each vector is split into two separate 128-bit vectors.
6177 /// Then, the resulting 128-bit vectors are used to implement two
6178 /// horizontal binary operations.
6180 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6182 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6183 /// the two new horizontal binop.
6184 /// When Mode is set, the first horizontal binop dag node would take as input
6185 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6186 /// horizontal binop dag node would take as input the lower 128-bit of V1
6187 /// and the upper 128-bit of V1.
6189 /// HADD V0_LO, V0_HI
6190 /// HADD V1_LO, V1_HI
6192 /// Otherwise, the first horizontal binop dag node takes as input the lower
6193 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6194 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6196 /// HADD V0_LO, V1_LO
6197 /// HADD V0_HI, V1_HI
6199 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6200 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6201 /// the upper 128-bits of the result.
6202 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6203 SDLoc DL, SelectionDAG &DAG,
6204 unsigned X86Opcode, bool Mode,
6205 bool isUndefLO, bool isUndefHI) {
6206 EVT VT = V0.getValueType();
6207 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6208 "Invalid nodes in input!");
6210 unsigned NumElts = VT.getVectorNumElements();
6211 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6212 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6213 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6214 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6215 EVT NewVT = V0_LO.getValueType();
6217 SDValue LO = DAG.getUNDEF(NewVT);
6218 SDValue HI = DAG.getUNDEF(NewVT);
6221 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6222 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6223 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6224 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6225 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6227 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6228 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6229 V1_LO->getOpcode() != ISD::UNDEF))
6230 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6232 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6233 V1_HI->getOpcode() != ISD::UNDEF))
6234 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6237 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6240 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6241 /// sequence of 'vadd + vsub + blendi'.
6242 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6243 const X86Subtarget *Subtarget) {
6245 EVT VT = BV->getValueType(0);
6246 unsigned NumElts = VT.getVectorNumElements();
6247 SDValue InVec0 = DAG.getUNDEF(VT);
6248 SDValue InVec1 = DAG.getUNDEF(VT);
6250 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6251 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6253 // Don't try to emit a VSELECT that cannot be lowered into a blend.
6254 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6255 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
6258 // Odd-numbered elements in the input build vector are obtained from
6259 // adding two integer/float elements.
6260 // Even-numbered elements in the input build vector are obtained from
6261 // subtracting two integer/float elements.
6262 unsigned ExpectedOpcode = ISD::FSUB;
6263 unsigned NextExpectedOpcode = ISD::FADD;
6264 bool AddFound = false;
6265 bool SubFound = false;
6267 for (unsigned i = 0, e = NumElts; i != e; i++) {
6268 SDValue Op = BV->getOperand(i);
6270 // Skip 'undef' values.
6271 unsigned Opcode = Op.getOpcode();
6272 if (Opcode == ISD::UNDEF) {
6273 std::swap(ExpectedOpcode, NextExpectedOpcode);
6277 // Early exit if we found an unexpected opcode.
6278 if (Opcode != ExpectedOpcode)
6281 SDValue Op0 = Op.getOperand(0);
6282 SDValue Op1 = Op.getOperand(1);
6284 // Try to match the following pattern:
6285 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6286 // Early exit if we cannot match that sequence.
6287 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6288 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6289 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6290 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6291 Op0.getOperand(1) != Op1.getOperand(1))
6294 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6298 // We found a valid add/sub node. Update the information accordingly.
6304 // Update InVec0 and InVec1.
6305 if (InVec0.getOpcode() == ISD::UNDEF)
6306 InVec0 = Op0.getOperand(0);
6307 if (InVec1.getOpcode() == ISD::UNDEF)
6308 InVec1 = Op1.getOperand(0);
6310 // Make sure that operands in input to each add/sub node always
6311 // come from a same pair of vectors.
6312 if (InVec0 != Op0.getOperand(0)) {
6313 if (ExpectedOpcode == ISD::FSUB)
6316 // FADD is commutable. Try to commute the operands
6317 // and then test again.
6318 std::swap(Op0, Op1);
6319 if (InVec0 != Op0.getOperand(0))
6323 if (InVec1 != Op1.getOperand(0))
6326 // Update the pair of expected opcodes.
6327 std::swap(ExpectedOpcode, NextExpectedOpcode);
6330 // Don't try to fold this build_vector into a VSELECT if it has
6331 // too many UNDEF operands.
6332 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6333 InVec1.getOpcode() != ISD::UNDEF) {
6334 // Emit a sequence of vector add and sub followed by a VSELECT.
6335 // The new VSELECT will be lowered into a BLENDI.
6336 // At ISel stage, we pattern-match the sequence 'add + sub + BLENDI'
6337 // and emit a single ADDSUB instruction.
6338 SDValue Sub = DAG.getNode(ExpectedOpcode, DL, VT, InVec0, InVec1);
6339 SDValue Add = DAG.getNode(NextExpectedOpcode, DL, VT, InVec0, InVec1);
6341 // Construct the VSELECT mask.
6342 EVT MaskVT = VT.changeVectorElementTypeToInteger();
6343 EVT SVT = MaskVT.getVectorElementType();
6344 unsigned SVTBits = SVT.getSizeInBits();
6345 SmallVector<SDValue, 8> Ops;
6347 for (unsigned i = 0, e = NumElts; i != e; ++i) {
6348 APInt Value = i & 1 ? APInt::getNullValue(SVTBits) :
6349 APInt::getAllOnesValue(SVTBits);
6350 SDValue Constant = DAG.getConstant(Value, SVT);
6351 Ops.push_back(Constant);
6354 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVT, Ops);
6355 return DAG.getSelect(DL, VT, Mask, Sub, Add);
6361 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6362 const X86Subtarget *Subtarget) {
6364 EVT VT = N->getValueType(0);
6365 unsigned NumElts = VT.getVectorNumElements();
6366 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6367 SDValue InVec0, InVec1;
6369 // Try to match an ADDSUB.
6370 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6371 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6372 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6373 if (Value.getNode())
6377 // Try to match horizontal ADD/SUB.
6378 unsigned NumUndefsLO = 0;
6379 unsigned NumUndefsHI = 0;
6380 unsigned Half = NumElts/2;
6382 // Count the number of UNDEF operands in the build_vector in input.
6383 for (unsigned i = 0, e = Half; i != e; ++i)
6384 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6387 for (unsigned i = Half, e = NumElts; i != e; ++i)
6388 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6391 // Early exit if this is either a build_vector of all UNDEFs or all the
6392 // operands but one are UNDEF.
6393 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6396 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6397 // Try to match an SSE3 float HADD/HSUB.
6398 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6399 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6401 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6402 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6403 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6404 // Try to match an SSSE3 integer HADD/HSUB.
6405 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6406 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6408 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6409 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6412 if (!Subtarget->hasAVX())
6415 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6416 // Try to match an AVX horizontal add/sub of packed single/double
6417 // precision floating point values from 256-bit vectors.
6418 SDValue InVec2, InVec3;
6419 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6420 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6421 ((InVec0.getOpcode() == ISD::UNDEF ||
6422 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6423 ((InVec1.getOpcode() == ISD::UNDEF ||
6424 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6425 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6427 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6428 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6429 ((InVec0.getOpcode() == ISD::UNDEF ||
6430 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6431 ((InVec1.getOpcode() == ISD::UNDEF ||
6432 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6433 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6434 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6435 // Try to match an AVX2 horizontal add/sub of signed integers.
6436 SDValue InVec2, InVec3;
6438 bool CanFold = true;
6440 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6441 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6442 ((InVec0.getOpcode() == ISD::UNDEF ||
6443 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6444 ((InVec1.getOpcode() == ISD::UNDEF ||
6445 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6446 X86Opcode = X86ISD::HADD;
6447 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6448 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6449 ((InVec0.getOpcode() == ISD::UNDEF ||
6450 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6451 ((InVec1.getOpcode() == ISD::UNDEF ||
6452 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6453 X86Opcode = X86ISD::HSUB;
6458 // Fold this build_vector into a single horizontal add/sub.
6459 // Do this only if the target has AVX2.
6460 if (Subtarget->hasAVX2())
6461 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6463 // Do not try to expand this build_vector into a pair of horizontal
6464 // add/sub if we can emit a pair of scalar add/sub.
6465 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6468 // Convert this build_vector into a pair of horizontal binop followed by
6470 bool isUndefLO = NumUndefsLO == Half;
6471 bool isUndefHI = NumUndefsHI == Half;
6472 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6473 isUndefLO, isUndefHI);
6477 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6478 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6480 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6481 X86Opcode = X86ISD::HADD;
6482 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6483 X86Opcode = X86ISD::HSUB;
6484 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6485 X86Opcode = X86ISD::FHADD;
6486 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6487 X86Opcode = X86ISD::FHSUB;
6491 // Don't try to expand this build_vector into a pair of horizontal add/sub
6492 // if we can simply emit a pair of scalar add/sub.
6493 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6496 // Convert this build_vector into two horizontal add/sub followed by
6498 bool isUndefLO = NumUndefsLO == Half;
6499 bool isUndefHI = NumUndefsHI == Half;
6500 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6501 isUndefLO, isUndefHI);
6508 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6511 MVT VT = Op.getSimpleValueType();
6512 MVT ExtVT = VT.getVectorElementType();
6513 unsigned NumElems = Op.getNumOperands();
6515 // Generate vectors for predicate vectors.
6516 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6517 return LowerBUILD_VECTORvXi1(Op, DAG);
6519 // Vectors containing all zeros can be matched by pxor and xorps later
6520 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6521 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6522 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6523 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6526 return getZeroVector(VT, Subtarget, DAG, dl);
6529 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6530 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6531 // vpcmpeqd on 256-bit vectors.
6532 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6533 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6536 if (!VT.is512BitVector())
6537 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6540 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6541 if (Broadcast.getNode())
6544 unsigned EVTBits = ExtVT.getSizeInBits();
6546 unsigned NumZero = 0;
6547 unsigned NumNonZero = 0;
6548 unsigned NonZeros = 0;
6549 bool IsAllConstants = true;
6550 SmallSet<SDValue, 8> Values;
6551 for (unsigned i = 0; i < NumElems; ++i) {
6552 SDValue Elt = Op.getOperand(i);
6553 if (Elt.getOpcode() == ISD::UNDEF)
6556 if (Elt.getOpcode() != ISD::Constant &&
6557 Elt.getOpcode() != ISD::ConstantFP)
6558 IsAllConstants = false;
6559 if (X86::isZeroNode(Elt))
6562 NonZeros |= (1 << i);
6567 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6568 if (NumNonZero == 0)
6569 return DAG.getUNDEF(VT);
6571 // Special case for single non-zero, non-undef, element.
6572 if (NumNonZero == 1) {
6573 unsigned Idx = countTrailingZeros(NonZeros);
6574 SDValue Item = Op.getOperand(Idx);
6576 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6577 // the value are obviously zero, truncate the value to i32 and do the
6578 // insertion that way. Only do this if the value is non-constant or if the
6579 // value is a constant being inserted into element 0. It is cheaper to do
6580 // a constant pool load than it is to do a movd + shuffle.
6581 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6582 (!IsAllConstants || Idx == 0)) {
6583 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6585 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6586 EVT VecVT = MVT::v4i32;
6587 unsigned VecElts = 4;
6589 // Truncate the value (which may itself be a constant) to i32, and
6590 // convert it to a vector with movd (S2V+shuffle to zero extend).
6591 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6592 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6593 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6595 // Now we have our 32-bit value zero extended in the low element of
6596 // a vector. If Idx != 0, swizzle it into place.
6598 SmallVector<int, 4> Mask;
6599 Mask.push_back(Idx);
6600 for (unsigned i = 1; i != VecElts; ++i)
6602 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6605 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6609 // If we have a constant or non-constant insertion into the low element of
6610 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6611 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6612 // depending on what the source datatype is.
6615 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6617 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6618 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6619 if (VT.is256BitVector() || VT.is512BitVector()) {
6620 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6621 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6622 Item, DAG.getIntPtrConstant(0));
6624 assert(VT.is128BitVector() && "Expected an SSE value type!");
6625 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6626 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6627 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6630 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6631 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6632 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6633 if (VT.is256BitVector()) {
6634 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6635 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6637 assert(VT.is128BitVector() && "Expected an SSE value type!");
6638 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6640 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6644 // Is it a vector logical left shift?
6645 if (NumElems == 2 && Idx == 1 &&
6646 X86::isZeroNode(Op.getOperand(0)) &&
6647 !X86::isZeroNode(Op.getOperand(1))) {
6648 unsigned NumBits = VT.getSizeInBits();
6649 return getVShift(true, VT,
6650 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6651 VT, Op.getOperand(1)),
6652 NumBits/2, DAG, *this, dl);
6655 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6658 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6659 // is a non-constant being inserted into an element other than the low one,
6660 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6661 // movd/movss) to move this into the low element, then shuffle it into
6663 if (EVTBits == 32) {
6664 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6666 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6667 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6668 SmallVector<int, 8> MaskVec;
6669 for (unsigned i = 0; i != NumElems; ++i)
6670 MaskVec.push_back(i == Idx ? 0 : 1);
6671 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6675 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6676 if (Values.size() == 1) {
6677 if (EVTBits == 32) {
6678 // Instead of a shuffle like this:
6679 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6680 // Check if it's possible to issue this instead.
6681 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6682 unsigned Idx = countTrailingZeros(NonZeros);
6683 SDValue Item = Op.getOperand(Idx);
6684 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6685 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6690 // A vector full of immediates; various special cases are already
6691 // handled, so this is best done with a single constant-pool load.
6695 // For AVX-length vectors, build the individual 128-bit pieces and use
6696 // shuffles to put them in place.
6697 if (VT.is256BitVector() || VT.is512BitVector()) {
6698 SmallVector<SDValue, 64> V;
6699 for (unsigned i = 0; i != NumElems; ++i)
6700 V.push_back(Op.getOperand(i));
6702 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6704 // Build both the lower and upper subvector.
6705 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6706 makeArrayRef(&V[0], NumElems/2));
6707 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6708 makeArrayRef(&V[NumElems / 2], NumElems/2));
6710 // Recreate the wider vector with the lower and upper part.
6711 if (VT.is256BitVector())
6712 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6713 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6716 // Let legalizer expand 2-wide build_vectors.
6717 if (EVTBits == 64) {
6718 if (NumNonZero == 1) {
6719 // One half is zero or undef.
6720 unsigned Idx = countTrailingZeros(NonZeros);
6721 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6722 Op.getOperand(Idx));
6723 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6728 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6729 if (EVTBits == 8 && NumElems == 16) {
6730 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6732 if (V.getNode()) return V;
6735 if (EVTBits == 16 && NumElems == 8) {
6736 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6738 if (V.getNode()) return V;
6741 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6742 if (EVTBits == 32 && NumElems == 4) {
6743 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6744 NumZero, DAG, Subtarget, *this);
6749 // If element VT is == 32 bits, turn it into a number of shuffles.
6750 SmallVector<SDValue, 8> V(NumElems);
6751 if (NumElems == 4 && NumZero > 0) {
6752 for (unsigned i = 0; i < 4; ++i) {
6753 bool isZero = !(NonZeros & (1 << i));
6755 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6757 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6760 for (unsigned i = 0; i < 2; ++i) {
6761 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6764 V[i] = V[i*2]; // Must be a zero vector.
6767 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6770 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6773 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6778 bool Reverse1 = (NonZeros & 0x3) == 2;
6779 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6783 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6784 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6786 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6789 if (Values.size() > 1 && VT.is128BitVector()) {
6790 // Check for a build vector of consecutive loads.
6791 for (unsigned i = 0; i < NumElems; ++i)
6792 V[i] = Op.getOperand(i);
6794 // Check for elements which are consecutive loads.
6795 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
6799 // Check for a build vector from mostly shuffle plus few inserting.
6800 SDValue Sh = buildFromShuffleMostly(Op, DAG);
6804 // For SSE 4.1, use insertps to put the high elements into the low element.
6805 if (getSubtarget()->hasSSE41()) {
6807 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6808 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6810 Result = DAG.getUNDEF(VT);
6812 for (unsigned i = 1; i < NumElems; ++i) {
6813 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6814 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6815 Op.getOperand(i), DAG.getIntPtrConstant(i));
6820 // Otherwise, expand into a number of unpckl*, start by extending each of
6821 // our (non-undef) elements to the full vector width with the element in the
6822 // bottom slot of the vector (which generates no code for SSE).
6823 for (unsigned i = 0; i < NumElems; ++i) {
6824 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6825 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6827 V[i] = DAG.getUNDEF(VT);
6830 // Next, we iteratively mix elements, e.g. for v4f32:
6831 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6832 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6833 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6834 unsigned EltStride = NumElems >> 1;
6835 while (EltStride != 0) {
6836 for (unsigned i = 0; i < EltStride; ++i) {
6837 // If V[i+EltStride] is undef and this is the first round of mixing,
6838 // then it is safe to just drop this shuffle: V[i] is already in the
6839 // right place, the one element (since it's the first round) being
6840 // inserted as undef can be dropped. This isn't safe for successive
6841 // rounds because they will permute elements within both vectors.
6842 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6843 EltStride == NumElems/2)
6846 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6855 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6856 // to create 256-bit vectors from two other 128-bit ones.
6857 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6859 MVT ResVT = Op.getSimpleValueType();
6861 assert((ResVT.is256BitVector() ||
6862 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6864 SDValue V1 = Op.getOperand(0);
6865 SDValue V2 = Op.getOperand(1);
6866 unsigned NumElems = ResVT.getVectorNumElements();
6867 if(ResVT.is256BitVector())
6868 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6870 if (Op.getNumOperands() == 4) {
6871 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6872 ResVT.getVectorNumElements()/2);
6873 SDValue V3 = Op.getOperand(2);
6874 SDValue V4 = Op.getOperand(3);
6875 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6876 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6878 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6881 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6882 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
6883 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6884 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6885 Op.getNumOperands() == 4)));
6887 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6888 // from two other 128-bit ones.
6890 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6891 return LowerAVXCONCAT_VECTORS(Op, DAG);
6895 //===----------------------------------------------------------------------===//
6896 // Vector shuffle lowering
6898 // This is an experimental code path for lowering vector shuffles on x86. It is
6899 // designed to handle arbitrary vector shuffles and blends, gracefully
6900 // degrading performance as necessary. It works hard to recognize idiomatic
6901 // shuffles and lower them to optimal instruction patterns without leaving
6902 // a framework that allows reasonably efficient handling of all vector shuffle
6904 //===----------------------------------------------------------------------===//
6906 /// \brief Tiny helper function to identify a no-op mask.
6908 /// This is a somewhat boring predicate function. It checks whether the mask
6909 /// array input, which is assumed to be a single-input shuffle mask of the kind
6910 /// used by the X86 shuffle instructions (not a fully general
6911 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6912 /// in-place shuffle are 'no-op's.
6913 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6914 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6915 if (Mask[i] != -1 && Mask[i] != i)
6920 /// \brief Helper function to classify a mask as a single-input mask.
6922 /// This isn't a generic single-input test because in the vector shuffle
6923 /// lowering we canonicalize single inputs to be the first input operand. This
6924 /// means we can more quickly test for a single input by only checking whether
6925 /// an input from the second operand exists. We also assume that the size of
6926 /// mask corresponds to the size of the input vectors which isn't true in the
6927 /// fully general case.
6928 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6930 if (M >= (int)Mask.size())
6935 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6937 /// This helper function produces an 8-bit shuffle immediate corresponding to
6938 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6939 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6942 /// NB: We rely heavily on "undef" masks preserving the input lane.
6943 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
6944 SelectionDAG &DAG) {
6945 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6946 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6947 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6948 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6949 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6952 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6953 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6954 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6955 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6956 return DAG.getConstant(Imm, MVT::i8);
6959 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
6961 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
6962 /// support for floating point shuffles but not integer shuffles. These
6963 /// instructions will incur a domain crossing penalty on some chips though so
6964 /// it is better to avoid lowering through this for integer vectors where
6966 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
6967 const X86Subtarget *Subtarget,
6968 SelectionDAG &DAG) {
6970 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
6971 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
6972 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
6973 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6974 ArrayRef<int> Mask = SVOp->getMask();
6975 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
6977 if (isSingleInputShuffleMask(Mask)) {
6978 // Straight shuffle of a single input vector. Simulate this by using the
6979 // single input as both of the "inputs" to this instruction..
6980 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
6981 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
6982 DAG.getConstant(SHUFPDMask, MVT::i8));
6984 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
6985 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
6987 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
6988 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
6989 DAG.getConstant(SHUFPDMask, MVT::i8));
6992 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
6994 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
6995 /// the integer unit to minimize domain crossing penalties. However, for blends
6996 /// it falls back to the floating point shuffle operation with appropriate bit
6998 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
6999 const X86Subtarget *Subtarget,
7000 SelectionDAG &DAG) {
7002 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7003 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7004 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7005 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7006 ArrayRef<int> Mask = SVOp->getMask();
7007 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7009 if (isSingleInputShuffleMask(Mask)) {
7010 // Straight shuffle of a single input vector. For everything from SSE2
7011 // onward this has a single fast instruction with no scary immediates.
7012 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7013 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7014 int WidenedMask[4] = {
7015 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7016 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7018 ISD::BITCAST, DL, MVT::v2i64,
7019 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7020 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7023 // We implement this with SHUFPD which is pretty lame because it will likely
7024 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7025 // However, all the alternatives are still more cycles and newer chips don't
7026 // have this problem. It would be really nice if x86 had better shuffles here.
7027 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7028 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7029 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7030 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7033 /// \brief Lower 4-lane 32-bit floating point shuffles.
7035 /// Uses instructions exclusively from the floating point unit to minimize
7036 /// domain crossing penalties, as these are sufficient to implement all v4f32
7038 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7039 const X86Subtarget *Subtarget,
7040 SelectionDAG &DAG) {
7042 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7043 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7044 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7045 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7046 ArrayRef<int> Mask = SVOp->getMask();
7047 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7049 SDValue LowV = V1, HighV = V2;
7050 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7053 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7055 if (NumV2Elements == 0)
7056 // Straight shuffle of a single input vector. We pass the input vector to
7057 // both operands to simulate this with a SHUFPS.
7058 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7059 getV4X86ShuffleImm8ForMask(Mask, DAG));
7061 if (NumV2Elements == 1) {
7063 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7065 // Compute the index adjacent to V2Index and in the same half by toggling
7067 int V2AdjIndex = V2Index ^ 1;
7069 if (Mask[V2AdjIndex] == -1) {
7070 // Handles all the cases where we have a single V2 element and an undef.
7071 // This will only ever happen in the high lanes because we commute the
7072 // vector otherwise.
7074 std::swap(LowV, HighV);
7075 NewMask[V2Index] -= 4;
7077 // Handle the case where the V2 element ends up adjacent to a V1 element.
7078 // To make this work, blend them together as the first step.
7079 int V1Index = V2AdjIndex;
7080 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7081 V2 = DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V2, V1,
7082 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7084 // Now proceed to reconstruct the final blend as we have the necessary
7085 // high or low half formed.
7092 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7093 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7095 } else if (NumV2Elements == 2) {
7096 if (Mask[0] < 4 && Mask[1] < 4) {
7097 // Handle the easy case where we have V1 in the low lanes and V2 in the
7098 // high lanes. We never see this reversed because we sort the shuffle.
7102 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7103 // trying to place elements directly, just blend them and set up the final
7104 // shuffle to place them.
7106 // The first two blend mask elements are for V1, the second two are for
7108 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7109 Mask[2] < 4 ? Mask[2] : Mask[3],
7110 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7111 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7112 V1 = DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V2,
7113 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7115 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7118 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7119 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7120 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7121 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7124 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, LowV, HighV,
7125 getV4X86ShuffleImm8ForMask(NewMask, DAG));
7128 /// \brief Lower 4-lane i32 vector shuffles.
7130 /// We try to handle these with integer-domain shuffles where we can, but for
7131 /// blends we use the floating point domain blend instructions.
7132 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7133 const X86Subtarget *Subtarget,
7134 SelectionDAG &DAG) {
7136 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7137 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7138 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7139 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7140 ArrayRef<int> Mask = SVOp->getMask();
7141 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7143 if (isSingleInputShuffleMask(Mask))
7144 // Straight shuffle of a single input vector. For everything from SSE2
7145 // onward this has a single fast instruction with no scary immediates.
7146 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7147 getV4X86ShuffleImm8ForMask(Mask, DAG));
7149 // We implement this with SHUFPS because it can blend from two vectors.
7150 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
7151 // up the inputs, bypassing domain shift penalties that we would encur if we
7152 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
7154 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
7155 DAG.getVectorShuffle(
7157 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
7158 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
7161 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
7162 /// shuffle lowering, and the most complex part.
7164 /// The lowering strategy is to try to form pairs of input lanes which are
7165 /// targeted at the same half of the final vector, and then use a dword shuffle
7166 /// to place them onto the right half, and finally unpack the paired lanes into
7167 /// their final position.
7169 /// The exact breakdown of how to form these dword pairs and align them on the
7170 /// correct sides is really tricky. See the comments within the function for
7171 /// more of the details.
7172 static SDValue lowerV8I16SingleInputVectorShuffle(
7173 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
7174 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7175 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7176 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
7177 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
7179 SmallVector<int, 4> LoInputs;
7180 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
7181 [](int M) { return M >= 0; });
7182 std::sort(LoInputs.begin(), LoInputs.end());
7183 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
7184 SmallVector<int, 4> HiInputs;
7185 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
7186 [](int M) { return M >= 0; });
7187 std::sort(HiInputs.begin(), HiInputs.end());
7188 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
7190 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
7191 int NumHToL = LoInputs.size() - NumLToL;
7193 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
7194 int NumHToH = HiInputs.size() - NumLToH;
7195 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
7196 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
7197 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
7198 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
7200 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
7201 // such inputs we can swap two of the dwords across the half mark and end up
7202 // with <=2 inputs to each half in each half. Once there, we can fall through
7203 // to the generic code below. For example:
7205 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7206 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
7208 // Before we had 3-1 in the low half and 3-1 in the high half. Afterward, 2-2
7210 auto balanceSides = [&](ArrayRef<int> ThreeInputs, int OneInput,
7211 int ThreeInputHalfSum, int OneInputHalfOffset) {
7212 // Compute the index of dword with only one word among the three inputs in
7213 // a half by taking the sum of the half with three inputs and subtracting
7214 // the sum of the actual three inputs. The difference is the remaining
7216 int DWordA = (ThreeInputHalfSum -
7217 std::accumulate(ThreeInputs.begin(), ThreeInputs.end(), 0)) /
7219 int DWordB = OneInputHalfOffset / 2 + (OneInput / 2 + 1) % 2;
7221 int PSHUFDMask[] = {0, 1, 2, 3};
7222 PSHUFDMask[DWordA] = DWordB;
7223 PSHUFDMask[DWordB] = DWordA;
7224 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7225 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7226 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
7227 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7229 // Adjust the mask to match the new locations of A and B.
7231 if (M != -1 && M/2 == DWordA)
7232 M = 2 * DWordB + M % 2;
7233 else if (M != -1 && M/2 == DWordB)
7234 M = 2 * DWordA + M % 2;
7236 // Recurse back into this routine to re-compute state now that this isn't
7237 // a 3 and 1 problem.
7238 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
7241 if (NumLToL == 3 && NumHToL == 1)
7242 return balanceSides(LToLInputs, HToLInputs[0], 0 + 1 + 2 + 3, 4);
7243 else if (NumLToL == 1 && NumHToL == 3)
7244 return balanceSides(HToLInputs, LToLInputs[0], 4 + 5 + 6 + 7, 0);
7245 else if (NumLToH == 1 && NumHToH == 3)
7246 return balanceSides(HToHInputs, LToHInputs[0], 4 + 5 + 6 + 7, 0);
7247 else if (NumLToH == 3 && NumHToH == 1)
7248 return balanceSides(LToHInputs, HToHInputs[0], 0 + 1 + 2 + 3, 4);
7250 // At this point there are at most two inputs to the low and high halves from
7251 // each half. That means the inputs can always be grouped into dwords and
7252 // those dwords can then be moved to the correct half with a dword shuffle.
7253 // We use at most one low and one high word shuffle to collect these paired
7254 // inputs into dwords, and finally a dword shuffle to place them.
7255 int PSHUFLMask[4] = {-1, -1, -1, -1};
7256 int PSHUFHMask[4] = {-1, -1, -1, -1};
7257 int PSHUFDMask[4] = {-1, -1, -1, -1};
7259 // First fix the masks for all the inputs that are staying in their
7260 // original halves. This will then dictate the targets of the cross-half
7262 auto fixInPlaceInputs = [&PSHUFDMask](
7263 ArrayRef<int> InPlaceInputs, MutableArrayRef<int> SourceHalfMask,
7264 MutableArrayRef<int> HalfMask, int HalfOffset) {
7265 if (InPlaceInputs.empty())
7267 if (InPlaceInputs.size() == 1) {
7268 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
7269 InPlaceInputs[0] - HalfOffset;
7270 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
7274 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
7275 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
7276 InPlaceInputs[0] - HalfOffset;
7277 // Put the second input next to the first so that they are packed into
7278 // a dword. We find the adjacent index by toggling the low bit.
7279 int AdjIndex = InPlaceInputs[0] ^ 1;
7280 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
7281 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
7282 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
7284 if (!HToLInputs.empty())
7285 fixInPlaceInputs(LToLInputs, PSHUFLMask, LoMask, 0);
7286 if (!LToHInputs.empty())
7287 fixInPlaceInputs(HToHInputs, PSHUFHMask, HiMask, 4);
7289 // Now gather the cross-half inputs and place them into a free dword of
7290 // their target half.
7291 // FIXME: This operation could almost certainly be simplified dramatically to
7292 // look more like the 3-1 fixing operation.
7293 auto moveInputsToRightHalf = [&PSHUFDMask](
7294 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
7295 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
7296 int SourceOffset, int DestOffset) {
7297 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
7298 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
7300 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
7302 int LowWord = Word & ~1;
7303 int HighWord = Word | 1;
7304 return isWordClobbered(SourceHalfMask, LowWord) ||
7305 isWordClobbered(SourceHalfMask, HighWord);
7308 if (IncomingInputs.empty())
7311 if (ExistingInputs.empty()) {
7312 // Map any dwords with inputs from them into the right half.
7313 for (int Input : IncomingInputs) {
7314 // If the source half mask maps over the inputs, turn those into
7315 // swaps and use the swapped lane.
7316 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
7317 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
7318 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
7319 Input - SourceOffset;
7320 // We have to swap the uses in our half mask in one sweep.
7321 for (int &M : HalfMask)
7322 if (M == SourceHalfMask[Input - SourceOffset])
7324 else if (M == Input)
7325 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
7327 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
7328 Input - SourceOffset &&
7329 "Previous placement doesn't match!");
7331 // Note that this correctly re-maps both when we do a swap and when
7332 // we observe the other side of the swap above. We rely on that to
7333 // avoid swapping the members of the input list directly.
7334 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
7337 // Map the input's dword into the correct half.
7338 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
7339 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
7341 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
7343 "Previous placement doesn't match!");
7346 // And just directly shift any other-half mask elements to be same-half
7347 // as we will have mirrored the dword containing the element into the
7348 // same position within that half.
7349 for (int &M : HalfMask)
7350 if (M >= SourceOffset && M < SourceOffset + 4) {
7351 M = M - SourceOffset + DestOffset;
7352 assert(M >= 0 && "This should never wrap below zero!");
7357 // Ensure we have the input in a viable dword of its current half. This
7358 // is particularly tricky because the original position may be clobbered
7359 // by inputs being moved and *staying* in that half.
7360 if (IncomingInputs.size() == 1) {
7361 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
7362 int InputFixed = std::find(std::begin(SourceHalfMask),
7363 std::end(SourceHalfMask), -1) -
7364 std::begin(SourceHalfMask) + SourceOffset;
7365 SourceHalfMask[InputFixed - SourceOffset] =
7366 IncomingInputs[0] - SourceOffset;
7367 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
7369 IncomingInputs[0] = InputFixed;
7371 } else if (IncomingInputs.size() == 2) {
7372 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
7373 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
7374 int SourceDWordBase = !isDWordClobbered(SourceHalfMask, 0) ? 0 : 2;
7375 assert(!isDWordClobbered(SourceHalfMask, SourceDWordBase) &&
7376 "Not all dwords can be clobbered!");
7377 SourceHalfMask[SourceDWordBase] = IncomingInputs[0] - SourceOffset;
7378 SourceHalfMask[SourceDWordBase + 1] = IncomingInputs[1] - SourceOffset;
7379 for (int &M : HalfMask)
7380 if (M == IncomingInputs[0])
7381 M = SourceDWordBase + SourceOffset;
7382 else if (M == IncomingInputs[1])
7383 M = SourceDWordBase + 1 + SourceOffset;
7384 IncomingInputs[0] = SourceDWordBase + SourceOffset;
7385 IncomingInputs[1] = SourceDWordBase + 1 + SourceOffset;
7388 llvm_unreachable("Unhandled input size!");
7391 // Now hoist the DWord down to the right half.
7392 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
7393 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
7394 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
7395 for (int Input : IncomingInputs)
7396 std::replace(HalfMask.begin(), HalfMask.end(), Input,
7397 FreeDWord * 2 + Input % 2);
7399 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask,
7400 /*SourceOffset*/ 4, /*DestOffset*/ 0);
7401 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask,
7402 /*SourceOffset*/ 0, /*DestOffset*/ 4);
7404 // Now enact all the shuffles we've computed to move the inputs into their
7406 if (!isNoopShuffleMask(PSHUFLMask))
7407 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
7408 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
7409 if (!isNoopShuffleMask(PSHUFHMask))
7410 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
7411 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
7412 if (!isNoopShuffleMask(PSHUFDMask))
7413 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7414 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7415 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
7416 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7418 // At this point, each half should contain all its inputs, and we can then
7419 // just shuffle them into their final position.
7420 assert(std::count_if(LoMask.begin(), LoMask.end(),
7421 [](int M) { return M >= 4; }) == 0 &&
7422 "Failed to lift all the high half inputs to the low mask!");
7423 assert(std::count_if(HiMask.begin(), HiMask.end(),
7424 [](int M) { return M >= 0 && M < 4; }) == 0 &&
7425 "Failed to lift all the low half inputs to the high mask!");
7427 // Do a half shuffle for the low mask.
7428 if (!isNoopShuffleMask(LoMask))
7429 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
7430 getV4X86ShuffleImm8ForMask(LoMask, DAG));
7432 // Do a half shuffle with the high mask after shifting its values down.
7433 for (int &M : HiMask)
7436 if (!isNoopShuffleMask(HiMask))
7437 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
7438 getV4X86ShuffleImm8ForMask(HiMask, DAG));
7443 /// \brief Detect whether the mask pattern should be lowered through
7446 /// This essentially tests whether viewing the mask as an interleaving of two
7447 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
7448 /// lowering it through interleaving is a significantly better strategy.
7449 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
7450 int NumEvenInputs[2] = {0, 0};
7451 int NumOddInputs[2] = {0, 0};
7452 int NumLoInputs[2] = {0, 0};
7453 int NumHiInputs[2] = {0, 0};
7454 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7458 int InputIdx = Mask[i] >= Size;
7461 ++NumLoInputs[InputIdx];
7463 ++NumHiInputs[InputIdx];
7466 ++NumEvenInputs[InputIdx];
7468 ++NumOddInputs[InputIdx];
7471 // The minimum number of cross-input results for both the interleaved and
7472 // split cases. If interleaving results in fewer cross-input results, return
7474 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
7475 NumEvenInputs[0] + NumOddInputs[1]);
7476 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
7477 NumLoInputs[0] + NumHiInputs[1]);
7478 return InterleavedCrosses < SplitCrosses;
7481 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
7483 /// This strategy only works when the inputs from each vector fit into a single
7484 /// half of that vector, and generally there are not so many inputs as to leave
7485 /// the in-place shuffles required highly constrained (and thus expensive). It
7486 /// shifts all the inputs into a single side of both input vectors and then
7487 /// uses an unpack to interleave these inputs in a single vector. At that
7488 /// point, we will fall back on the generic single input shuffle lowering.
7489 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
7491 MutableArrayRef<int> Mask,
7492 const X86Subtarget *Subtarget,
7493 SelectionDAG &DAG) {
7494 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7495 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7496 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
7497 for (int i = 0; i < 8; ++i)
7498 if (Mask[i] >= 0 && Mask[i] < 4)
7499 LoV1Inputs.push_back(i);
7500 else if (Mask[i] >= 4 && Mask[i] < 8)
7501 HiV1Inputs.push_back(i);
7502 else if (Mask[i] >= 8 && Mask[i] < 12)
7503 LoV2Inputs.push_back(i);
7504 else if (Mask[i] >= 12)
7505 HiV2Inputs.push_back(i);
7507 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
7508 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
7511 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
7512 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
7513 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
7515 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
7516 HiV1Inputs.size() + HiV2Inputs.size();
7518 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
7519 ArrayRef<int> HiInputs, bool MoveToLo,
7521 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
7522 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
7523 if (BadInputs.empty())
7526 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
7527 int MoveOffset = MoveToLo ? 0 : 4;
7529 if (GoodInputs.empty()) {
7530 for (int BadInput : BadInputs) {
7531 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
7532 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
7535 if (GoodInputs.size() == 2) {
7536 // If the low inputs are spread across two dwords, pack them into
7538 MoveMask[Mask[GoodInputs[0]] % 2 + MoveOffset] =
7539 Mask[GoodInputs[0]] - MaskOffset;
7540 MoveMask[Mask[GoodInputs[1]] % 2 + MoveOffset] =
7541 Mask[GoodInputs[1]] - MaskOffset;
7542 Mask[GoodInputs[0]] = Mask[GoodInputs[0]] % 2 + MoveOffset + MaskOffset;
7543 Mask[GoodInputs[1]] = Mask[GoodInputs[0]] % 2 + MoveOffset + MaskOffset;
7545 // Otherwise pin the low inputs.
7546 for (int GoodInput : GoodInputs)
7547 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
7551 std::find(std::begin(MoveMask) + MoveOffset, std::end(MoveMask), -1) -
7552 std::begin(MoveMask);
7553 assert(MoveMaskIdx >= MoveOffset && "Established above");
7555 if (BadInputs.size() == 2) {
7556 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
7557 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
7558 MoveMask[MoveMaskIdx + Mask[BadInputs[0]] % 2] =
7559 Mask[BadInputs[0]] - MaskOffset;
7560 MoveMask[MoveMaskIdx + Mask[BadInputs[1]] % 2] =
7561 Mask[BadInputs[1]] - MaskOffset;
7562 Mask[BadInputs[0]] = MoveMaskIdx + Mask[BadInputs[0]] % 2 + MaskOffset;
7563 Mask[BadInputs[1]] = MoveMaskIdx + Mask[BadInputs[1]] % 2 + MaskOffset;
7565 assert(BadInputs.size() == 1 && "All sizes handled");
7566 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
7567 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
7571 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
7574 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
7576 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
7579 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
7580 // cross-half traffic in the final shuffle.
7582 // Munge the mask to be a single-input mask after the unpack merges the
7586 M = 2 * (M % 4) + (M / 8);
7588 return DAG.getVectorShuffle(
7589 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
7590 DL, MVT::v8i16, V1, V2),
7591 DAG.getUNDEF(MVT::v8i16), Mask);
7594 /// \brief Generic lowering of 8-lane i16 shuffles.
7596 /// This handles both single-input shuffles and combined shuffle/blends with
7597 /// two inputs. The single input shuffles are immediately delegated to
7598 /// a dedicated lowering routine.
7600 /// The blends are lowered in one of three fundamental ways. If there are few
7601 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
7602 /// of the input is significantly cheaper when lowered as an interleaving of
7603 /// the two inputs, try to interleave them. Otherwise, blend the low and high
7604 /// halves of the inputs separately (making them have relatively few inputs)
7605 /// and then concatenate them.
7606 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7607 const X86Subtarget *Subtarget,
7608 SelectionDAG &DAG) {
7610 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
7611 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
7612 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
7613 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7614 ArrayRef<int> OrigMask = SVOp->getMask();
7615 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
7616 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
7617 MutableArrayRef<int> Mask(MaskStorage);
7619 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
7621 auto isV1 = [](int M) { return M >= 0 && M < 8; };
7622 auto isV2 = [](int M) { return M >= 8; };
7624 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
7625 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
7627 if (NumV2Inputs == 0)
7628 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
7630 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
7631 "to be V1-input shuffles.");
7633 if (NumV1Inputs + NumV2Inputs <= 4)
7634 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
7636 // Check whether an interleaving lowering is likely to be more efficient.
7637 // This isn't perfect but it is a strong heuristic that tends to work well on
7638 // the kinds of shuffles that show up in practice.
7640 // FIXME: Handle 1x, 2x, and 4x interleaving.
7641 if (shouldLowerAsInterleaving(Mask)) {
7642 // FIXME: Figure out whether we should pack these into the low or high
7645 int EMask[8], OMask[8];
7646 for (int i = 0; i < 4; ++i) {
7647 EMask[i] = Mask[2*i];
7648 OMask[i] = Mask[2*i + 1];
7653 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
7654 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
7656 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
7659 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7660 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7662 for (int i = 0; i < 4; ++i) {
7663 LoBlendMask[i] = Mask[i];
7664 HiBlendMask[i] = Mask[i + 4];
7667 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
7668 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
7669 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
7670 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
7672 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7673 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
7676 /// \brief Generic lowering of v16i8 shuffles.
7678 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
7679 /// detect any complexity reducing interleaving. If that doesn't help, it uses
7680 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
7681 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
7683 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7684 const X86Subtarget *Subtarget,
7685 SelectionDAG &DAG) {
7687 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
7688 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
7689 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
7690 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7691 ArrayRef<int> OrigMask = SVOp->getMask();
7692 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
7693 int MaskStorage[16] = {
7694 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
7695 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
7696 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
7697 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
7698 MutableArrayRef<int> Mask(MaskStorage);
7699 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
7700 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
7702 // For single-input shuffles, there are some nicer lowering tricks we can use.
7703 if (isSingleInputShuffleMask(Mask)) {
7704 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
7705 // Notably, this handles splat and partial-splat shuffles more efficiently.
7707 // FIXME: We should check for other patterns which can be widened into an
7708 // i16 shuffle as well.
7709 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
7710 for (int i = 0; i < 16; i += 2) {
7711 if (Mask[i] != Mask[i + 1])
7716 if (canWidenViaDuplication(Mask)) {
7717 SmallVector<int, 4> LoInputs;
7718 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
7719 [](int M) { return M >= 0 && M < 8; });
7720 std::sort(LoInputs.begin(), LoInputs.end());
7721 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
7723 SmallVector<int, 4> HiInputs;
7724 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
7725 [](int M) { return M >= 8; });
7726 std::sort(HiInputs.begin(), HiInputs.end());
7727 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
7730 bool TargetLo = LoInputs.size() >= HiInputs.size();
7731 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
7732 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
7735 SmallDenseMap<int, int, 8> LaneMap;
7736 for (int i = 0; i < 16; ++i)
7738 for (int I : InPlaceInputs) {
7742 int FreeByteIdx = 0;
7743 int TargetOffset = TargetLo ? 0 : 8;
7744 for (int I : MovingInputs) {
7745 // Walk the free index into the byte mask until we find an unoccupied
7746 // spot. We bound this to 8 steps to catch bugs, the pigeonhole
7747 // principle indicates that there *must* be a spot as we can only have
7748 // 8 duplicated inputs. We have to walk the index using modular
7749 // arithmetic to wrap around as necessary.
7750 // FIXME: We could do a much better job of picking an inexpensive slot
7751 // so this doesn't go through the worst case for the byte shuffle.
7752 for (int j = 0; j < 8 && ByteMask[FreeByteIdx + TargetOffset] != -1;
7753 ++j, FreeByteIdx = (FreeByteIdx + 1) % 8)
7755 assert(ByteMask[FreeByteIdx + TargetOffset] == -1 &&
7756 "Failed to find a free byte!");
7757 ByteMask[FreeByteIdx + TargetOffset] = I;
7758 LaneMap[I] = FreeByteIdx + TargetOffset;
7760 V1 = DAG.getVectorShuffle(MVT::v16i8, DL, V1, DAG.getUNDEF(MVT::v16i8),
7766 // Unpack the bytes to form the i16s that will be shuffled into place.
7767 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
7768 MVT::v16i8, V1, V1);
7770 int I16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7771 for (int i = 0; i < 16; i += 2) {
7773 I16Shuffle[i / 2] = Mask[i] - (TargetLo ? 0 : 8);
7774 assert(I16Shuffle[i / 2] < 8 && "Invalid v8 shuffle mask!");
7776 return DAG.getVectorShuffle(MVT::v8i16, DL,
7777 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
7778 DAG.getUNDEF(MVT::v8i16), I16Shuffle);
7782 // Check whether an interleaving lowering is likely to be more efficient.
7783 // This isn't perfect but it is a strong heuristic that tends to work well on
7784 // the kinds of shuffles that show up in practice.
7786 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
7787 if (shouldLowerAsInterleaving(Mask)) {
7788 // FIXME: Figure out whether we should pack these into the low or high
7791 int EMask[16], OMask[16];
7792 for (int i = 0; i < 8; ++i) {
7793 EMask[i] = Mask[2*i];
7794 OMask[i] = Mask[2*i + 1];
7799 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
7800 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
7802 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, Evens, Odds);
7804 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
7806 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7807 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, Zero));
7809 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7810 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, Zero));
7812 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7813 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V2, Zero));
7815 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7816 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V2, Zero));
7818 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7819 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7820 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7821 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7823 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
7824 MutableArrayRef<int> V1HalfBlendMask,
7825 MutableArrayRef<int> V2HalfBlendMask) {
7826 for (int i = 0; i < 8; ++i)
7827 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
7828 V1HalfBlendMask[i] = HalfMask[i];
7830 } else if (HalfMask[i] >= 16) {
7831 V2HalfBlendMask[i] = HalfMask[i] - 16;
7832 HalfMask[i] = i + 8;
7835 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
7836 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
7838 SDValue V1Lo = DAG.getVectorShuffle(MVT::v8i16, DL, LoV1, HiV1, V1LoBlendMask);
7839 SDValue V2Lo = DAG.getVectorShuffle(MVT::v8i16, DL, LoV2, HiV2, V2LoBlendMask);
7840 SDValue V1Hi = DAG.getVectorShuffle(MVT::v8i16, DL, LoV1, HiV1, V1HiBlendMask);
7841 SDValue V2Hi = DAG.getVectorShuffle(MVT::v8i16, DL, LoV2, HiV2, V2HiBlendMask);
7843 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
7844 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
7846 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
7849 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
7851 /// This routine breaks down the specific type of 128-bit shuffle and
7852 /// dispatches to the lowering routines accordingly.
7853 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7854 MVT VT, const X86Subtarget *Subtarget,
7855 SelectionDAG &DAG) {
7856 switch (VT.SimpleTy) {
7858 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
7860 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
7862 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
7864 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
7866 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
7868 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
7871 llvm_unreachable("Unimplemented!");
7875 /// \brief Tiny helper function to test whether adjacent masks are sequential.
7876 static bool areAdjacentMasksSequential(ArrayRef<int> Mask) {
7877 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
7878 if (Mask[i] + 1 != Mask[i+1])
7884 /// \brief Top-level lowering for x86 vector shuffles.
7886 /// This handles decomposition, canonicalization, and lowering of all x86
7887 /// vector shuffles. Most of the specific lowering strategies are encapsulated
7888 /// above in helper routines. The canonicalization attempts to widen shuffles
7889 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
7890 /// s.t. only one of the two inputs needs to be tested, etc.
7891 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
7892 SelectionDAG &DAG) {
7893 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7894 ArrayRef<int> Mask = SVOp->getMask();
7895 SDValue V1 = Op.getOperand(0);
7896 SDValue V2 = Op.getOperand(1);
7897 MVT VT = Op.getSimpleValueType();
7898 int NumElements = VT.getVectorNumElements();
7901 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
7903 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
7904 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
7905 if (V1IsUndef && V2IsUndef)
7906 return DAG.getUNDEF(VT);
7908 // When we create a shuffle node we put the UNDEF node to second operand,
7909 // but in some cases the first operand may be transformed to UNDEF.
7910 // In this case we should just commute the node.
7912 return CommuteVectorShuffle(SVOp, DAG);
7914 // Check for non-undef masks pointing at an undef vector and make the masks
7915 // undef as well. This makes it easier to match the shuffle based solely on
7919 if (M >= NumElements) {
7920 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
7921 for (int &M : NewMask)
7922 if (M >= NumElements)
7924 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
7927 // For integer vector shuffles, try to collapse them into a shuffle of fewer
7928 // lanes but wider integers. We cap this to not form integers larger than i64
7929 // but it might be interesting to form i128 integers to handle flipping the
7930 // low and high halves of AVX 256-bit vectors.
7931 if (VT.isInteger() && VT.getScalarSizeInBits() < 64 &&
7932 areAdjacentMasksSequential(Mask)) {
7933 SmallVector<int, 8> NewMask;
7934 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
7935 NewMask.push_back(Mask[i] / 2);
7937 MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits() * 2),
7938 VT.getVectorNumElements() / 2);
7939 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
7940 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
7941 return DAG.getNode(ISD::BITCAST, dl, VT,
7942 DAG.getVectorShuffle(NewVT, dl, V1, V2, NewMask));
7945 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
7946 for (int M : SVOp->getMask())
7949 else if (M < NumElements)
7954 // Commute the shuffle as needed such that more elements come from V1 than
7955 // V2. This allows us to match the shuffle pattern strictly on how many
7956 // elements come from V1 without handling the symmetric cases.
7957 if (NumV2Elements > NumV1Elements)
7958 return CommuteVectorShuffle(SVOp, DAG);
7960 // When the number of V1 and V2 elements are the same, try to minimize the
7961 // number of uses of V2 in the low half of the vector.
7962 if (NumV1Elements == NumV2Elements) {
7963 int LowV1Elements = 0, LowV2Elements = 0;
7964 for (int M : SVOp->getMask().slice(0, NumElements / 2))
7965 if (M >= NumElements)
7969 if (LowV2Elements > LowV1Elements)
7970 return CommuteVectorShuffle(SVOp, DAG);
7973 // For each vector width, delegate to a specialized lowering routine.
7974 if (VT.getSizeInBits() == 128)
7975 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
7977 llvm_unreachable("Unimplemented!");
7981 //===----------------------------------------------------------------------===//
7982 // Legacy vector shuffle lowering
7984 // This code is the legacy code handling vector shuffles until the above
7985 // replaces its functionality and performance.
7986 //===----------------------------------------------------------------------===//
7988 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
7989 bool hasInt256, unsigned *MaskOut = nullptr) {
7990 MVT EltVT = VT.getVectorElementType();
7992 // There is no blend with immediate in AVX-512.
7993 if (VT.is512BitVector())
7996 if (!hasSSE41 || EltVT == MVT::i8)
7998 if (!hasInt256 && VT == MVT::v16i16)
8001 unsigned MaskValue = 0;
8002 unsigned NumElems = VT.getVectorNumElements();
8003 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
8004 unsigned NumLanes = (NumElems - 1) / 8 + 1;
8005 unsigned NumElemsInLane = NumElems / NumLanes;
8007 // Blend for v16i16 should be symetric for the both lanes.
8008 for (unsigned i = 0; i < NumElemsInLane; ++i) {
8010 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
8011 int EltIdx = MaskVals[i];
8013 if ((EltIdx < 0 || EltIdx == (int)i) &&
8014 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
8017 if (((unsigned)EltIdx == (i + NumElems)) &&
8018 (SndLaneEltIdx < 0 ||
8019 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
8020 MaskValue |= (1 << i);
8026 *MaskOut = MaskValue;
8030 // Try to lower a shuffle node into a simple blend instruction.
8031 // This function assumes isBlendMask returns true for this
8032 // SuffleVectorSDNode
8033 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
8035 const X86Subtarget *Subtarget,
8036 SelectionDAG &DAG) {
8037 MVT VT = SVOp->getSimpleValueType(0);
8038 MVT EltVT = VT.getVectorElementType();
8039 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
8040 Subtarget->hasInt256() && "Trying to lower a "
8041 "VECTOR_SHUFFLE to a Blend but "
8042 "with the wrong mask"));
8043 SDValue V1 = SVOp->getOperand(0);
8044 SDValue V2 = SVOp->getOperand(1);
8046 unsigned NumElems = VT.getVectorNumElements();
8048 // Convert i32 vectors to floating point if it is not AVX2.
8049 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
8051 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
8052 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
8054 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
8055 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
8058 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
8059 DAG.getConstant(MaskValue, MVT::i32));
8060 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
8063 /// In vector type \p VT, return true if the element at index \p InputIdx
8064 /// falls on a different 128-bit lane than \p OutputIdx.
8065 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
8066 unsigned OutputIdx) {
8067 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
8068 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
8071 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
8072 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
8073 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
8074 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
8076 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
8077 SelectionDAG &DAG) {
8078 MVT VT = V1.getSimpleValueType();
8079 assert(VT.is128BitVector() || VT.is256BitVector());
8081 MVT EltVT = VT.getVectorElementType();
8082 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
8083 unsigned NumElts = VT.getVectorNumElements();
8085 SmallVector<SDValue, 32> PshufbMask;
8086 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
8087 int InputIdx = MaskVals[OutputIdx];
8088 unsigned InputByteIdx;
8090 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
8091 InputByteIdx = 0x80;
8093 // Cross lane is not allowed.
8094 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
8096 InputByteIdx = InputIdx * EltSizeInBytes;
8097 // Index is an byte offset within the 128-bit lane.
8098 InputByteIdx &= 0xf;
8101 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
8102 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
8103 if (InputByteIdx != 0x80)
8108 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
8110 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
8111 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
8112 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
8115 // v8i16 shuffles - Prefer shuffles in the following order:
8116 // 1. [all] pshuflw, pshufhw, optional move
8117 // 2. [ssse3] 1 x pshufb
8118 // 3. [ssse3] 2 x pshufb + 1 x por
8119 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
8121 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
8122 SelectionDAG &DAG) {
8123 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8124 SDValue V1 = SVOp->getOperand(0);
8125 SDValue V2 = SVOp->getOperand(1);
8127 SmallVector<int, 8> MaskVals;
8129 // Determine if more than 1 of the words in each of the low and high quadwords
8130 // of the result come from the same quadword of one of the two inputs. Undef
8131 // mask values count as coming from any quadword, for better codegen.
8133 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
8134 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
8135 unsigned LoQuad[] = { 0, 0, 0, 0 };
8136 unsigned HiQuad[] = { 0, 0, 0, 0 };
8137 // Indices of quads used.
8138 std::bitset<4> InputQuads;
8139 for (unsigned i = 0; i < 8; ++i) {
8140 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
8141 int EltIdx = SVOp->getMaskElt(i);
8142 MaskVals.push_back(EltIdx);
8151 InputQuads.set(EltIdx / 4);
8154 int BestLoQuad = -1;
8155 unsigned MaxQuad = 1;
8156 for (unsigned i = 0; i < 4; ++i) {
8157 if (LoQuad[i] > MaxQuad) {
8159 MaxQuad = LoQuad[i];
8163 int BestHiQuad = -1;
8165 for (unsigned i = 0; i < 4; ++i) {
8166 if (HiQuad[i] > MaxQuad) {
8168 MaxQuad = HiQuad[i];
8172 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
8173 // of the two input vectors, shuffle them into one input vector so only a
8174 // single pshufb instruction is necessary. If there are more than 2 input
8175 // quads, disable the next transformation since it does not help SSSE3.
8176 bool V1Used = InputQuads[0] || InputQuads[1];
8177 bool V2Used = InputQuads[2] || InputQuads[3];
8178 if (Subtarget->hasSSSE3()) {
8179 if (InputQuads.count() == 2 && V1Used && V2Used) {
8180 BestLoQuad = InputQuads[0] ? 0 : 1;
8181 BestHiQuad = InputQuads[2] ? 2 : 3;
8183 if (InputQuads.count() > 2) {
8189 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
8190 // the shuffle mask. If a quad is scored as -1, that means that it contains
8191 // words from all 4 input quadwords.
8193 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
8195 BestLoQuad < 0 ? 0 : BestLoQuad,
8196 BestHiQuad < 0 ? 1 : BestHiQuad
8198 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
8199 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
8200 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
8201 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
8203 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
8204 // source words for the shuffle, to aid later transformations.
8205 bool AllWordsInNewV = true;
8206 bool InOrder[2] = { true, true };
8207 for (unsigned i = 0; i != 8; ++i) {
8208 int idx = MaskVals[i];
8210 InOrder[i/4] = false;
8211 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
8213 AllWordsInNewV = false;
8217 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
8218 if (AllWordsInNewV) {
8219 for (int i = 0; i != 8; ++i) {
8220 int idx = MaskVals[i];
8223 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
8224 if ((idx != i) && idx < 4)
8226 if ((idx != i) && idx > 3)
8235 // If we've eliminated the use of V2, and the new mask is a pshuflw or
8236 // pshufhw, that's as cheap as it gets. Return the new shuffle.
8237 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
8238 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
8239 unsigned TargetMask = 0;
8240 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
8241 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
8242 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
8243 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
8244 getShufflePSHUFLWImmediate(SVOp);
8245 V1 = NewV.getOperand(0);
8246 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
8250 // Promote splats to a larger type which usually leads to more efficient code.
8251 // FIXME: Is this true if pshufb is available?
8252 if (SVOp->isSplat())
8253 return PromoteSplat(SVOp, DAG);
8255 // If we have SSSE3, and all words of the result are from 1 input vector,
8256 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
8257 // is present, fall back to case 4.
8258 if (Subtarget->hasSSSE3()) {
8259 SmallVector<SDValue,16> pshufbMask;
8261 // If we have elements from both input vectors, set the high bit of the
8262 // shuffle mask element to zero out elements that come from V2 in the V1
8263 // mask, and elements that come from V1 in the V2 mask, so that the two
8264 // results can be OR'd together.
8265 bool TwoInputs = V1Used && V2Used;
8266 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
8268 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
8270 // Calculate the shuffle mask for the second input, shuffle it, and
8271 // OR it with the first shuffled input.
8272 CommuteVectorShuffleMask(MaskVals, 8);
8273 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
8274 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
8275 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
8278 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
8279 // and update MaskVals with new element order.
8280 std::bitset<8> InOrder;
8281 if (BestLoQuad >= 0) {
8282 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
8283 for (int i = 0; i != 4; ++i) {
8284 int idx = MaskVals[i];
8287 } else if ((idx / 4) == BestLoQuad) {
8292 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
8295 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
8296 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
8297 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
8299 getShufflePSHUFLWImmediate(SVOp), DAG);
8303 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
8304 // and update MaskVals with the new element order.
8305 if (BestHiQuad >= 0) {
8306 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
8307 for (unsigned i = 4; i != 8; ++i) {
8308 int idx = MaskVals[i];
8311 } else if ((idx / 4) == BestHiQuad) {
8312 MaskV[i] = (idx & 3) + 4;
8316 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
8319 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
8320 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
8321 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
8323 getShufflePSHUFHWImmediate(SVOp), DAG);
8327 // In case BestHi & BestLo were both -1, which means each quadword has a word
8328 // from each of the four input quadwords, calculate the InOrder bitvector now
8329 // before falling through to the insert/extract cleanup.
8330 if (BestLoQuad == -1 && BestHiQuad == -1) {
8332 for (int i = 0; i != 8; ++i)
8333 if (MaskVals[i] < 0 || MaskVals[i] == i)
8337 // The other elements are put in the right place using pextrw and pinsrw.
8338 for (unsigned i = 0; i != 8; ++i) {
8341 int EltIdx = MaskVals[i];
8344 SDValue ExtOp = (EltIdx < 8) ?
8345 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
8346 DAG.getIntPtrConstant(EltIdx)) :
8347 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
8348 DAG.getIntPtrConstant(EltIdx - 8));
8349 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
8350 DAG.getIntPtrConstant(i));
8355 /// \brief v16i16 shuffles
8357 /// FIXME: We only support generation of a single pshufb currently. We can
8358 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
8359 /// well (e.g 2 x pshufb + 1 x por).
8361 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
8362 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8363 SDValue V1 = SVOp->getOperand(0);
8364 SDValue V2 = SVOp->getOperand(1);
8367 if (V2.getOpcode() != ISD::UNDEF)
8370 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
8371 return getPSHUFB(MaskVals, V1, dl, DAG);
8374 // v16i8 shuffles - Prefer shuffles in the following order:
8375 // 1. [ssse3] 1 x pshufb
8376 // 2. [ssse3] 2 x pshufb + 1 x por
8377 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
8378 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
8379 const X86Subtarget* Subtarget,
8380 SelectionDAG &DAG) {
8381 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8382 SDValue V1 = SVOp->getOperand(0);
8383 SDValue V2 = SVOp->getOperand(1);
8385 ArrayRef<int> MaskVals = SVOp->getMask();
8387 // Promote splats to a larger type which usually leads to more efficient code.
8388 // FIXME: Is this true if pshufb is available?
8389 if (SVOp->isSplat())
8390 return PromoteSplat(SVOp, DAG);
8392 // If we have SSSE3, case 1 is generated when all result bytes come from
8393 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
8394 // present, fall back to case 3.
8396 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
8397 if (Subtarget->hasSSSE3()) {
8398 SmallVector<SDValue,16> pshufbMask;
8400 // If all result elements are from one input vector, then only translate
8401 // undef mask values to 0x80 (zero out result) in the pshufb mask.
8403 // Otherwise, we have elements from both input vectors, and must zero out
8404 // elements that come from V2 in the first mask, and V1 in the second mask
8405 // so that we can OR them together.
8406 for (unsigned i = 0; i != 16; ++i) {
8407 int EltIdx = MaskVals[i];
8408 if (EltIdx < 0 || EltIdx >= 16)
8410 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
8412 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
8413 DAG.getNode(ISD::BUILD_VECTOR, dl,
8414 MVT::v16i8, pshufbMask));
8416 // As PSHUFB will zero elements with negative indices, it's safe to ignore
8417 // the 2nd operand if it's undefined or zero.
8418 if (V2.getOpcode() == ISD::UNDEF ||
8419 ISD::isBuildVectorAllZeros(V2.getNode()))
8422 // Calculate the shuffle mask for the second input, shuffle it, and
8423 // OR it with the first shuffled input.
8425 for (unsigned i = 0; i != 16; ++i) {
8426 int EltIdx = MaskVals[i];
8427 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
8428 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
8430 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
8431 DAG.getNode(ISD::BUILD_VECTOR, dl,
8432 MVT::v16i8, pshufbMask));
8433 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
8436 // No SSSE3 - Calculate in place words and then fix all out of place words
8437 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
8438 // the 16 different words that comprise the two doublequadword input vectors.
8439 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
8440 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
8442 for (int i = 0; i != 8; ++i) {
8443 int Elt0 = MaskVals[i*2];
8444 int Elt1 = MaskVals[i*2+1];
8446 // This word of the result is all undef, skip it.
8447 if (Elt0 < 0 && Elt1 < 0)
8450 // This word of the result is already in the correct place, skip it.
8451 if ((Elt0 == i*2) && (Elt1 == i*2+1))
8454 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
8455 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
8458 // If Elt0 and Elt1 are defined, are consecutive, and can be load
8459 // using a single extract together, load it and store it.
8460 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
8461 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
8462 DAG.getIntPtrConstant(Elt1 / 2));
8463 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
8464 DAG.getIntPtrConstant(i));
8468 // If Elt1 is defined, extract it from the appropriate source. If the
8469 // source byte is not also odd, shift the extracted word left 8 bits
8470 // otherwise clear the bottom 8 bits if we need to do an or.
8472 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
8473 DAG.getIntPtrConstant(Elt1 / 2));
8474 if ((Elt1 & 1) == 0)
8475 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
8477 TLI.getShiftAmountTy(InsElt.getValueType())));
8479 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
8480 DAG.getConstant(0xFF00, MVT::i16));
8482 // If Elt0 is defined, extract it from the appropriate source. If the
8483 // source byte is not also even, shift the extracted word right 8 bits. If
8484 // Elt1 was also defined, OR the extracted values together before
8485 // inserting them in the result.
8487 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
8488 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
8489 if ((Elt0 & 1) != 0)
8490 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
8492 TLI.getShiftAmountTy(InsElt0.getValueType())));
8494 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
8495 DAG.getConstant(0x00FF, MVT::i16));
8496 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
8499 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
8500 DAG.getIntPtrConstant(i));
8502 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
8505 // v32i8 shuffles - Translate to VPSHUFB if possible.
8507 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
8508 const X86Subtarget *Subtarget,
8509 SelectionDAG &DAG) {
8510 MVT VT = SVOp->getSimpleValueType(0);
8511 SDValue V1 = SVOp->getOperand(0);
8512 SDValue V2 = SVOp->getOperand(1);
8514 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
8516 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
8517 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
8518 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
8520 // VPSHUFB may be generated if
8521 // (1) one of input vector is undefined or zeroinitializer.
8522 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
8523 // And (2) the mask indexes don't cross the 128-bit lane.
8524 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
8525 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
8528 if (V1IsAllZero && !V2IsAllZero) {
8529 CommuteVectorShuffleMask(MaskVals, 32);
8532 return getPSHUFB(MaskVals, V1, dl, DAG);
8535 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
8536 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
8537 /// done when every pair / quad of shuffle mask elements point to elements in
8538 /// the right sequence. e.g.
8539 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
8541 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
8542 SelectionDAG &DAG) {
8543 MVT VT = SVOp->getSimpleValueType(0);
8545 unsigned NumElems = VT.getVectorNumElements();
8548 switch (VT.SimpleTy) {
8549 default: llvm_unreachable("Unexpected!");
8552 return SDValue(SVOp, 0);
8553 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
8554 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
8555 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
8556 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
8557 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
8558 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
8561 SmallVector<int, 8> MaskVec;
8562 for (unsigned i = 0; i != NumElems; i += Scale) {
8564 for (unsigned j = 0; j != Scale; ++j) {
8565 int EltIdx = SVOp->getMaskElt(i+j);
8569 StartIdx = (EltIdx / Scale);
8570 if (EltIdx != (int)(StartIdx*Scale + j))
8573 MaskVec.push_back(StartIdx);
8576 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
8577 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
8578 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
8581 /// getVZextMovL - Return a zero-extending vector move low node.
8583 static SDValue getVZextMovL(MVT VT, MVT OpVT,
8584 SDValue SrcOp, SelectionDAG &DAG,
8585 const X86Subtarget *Subtarget, SDLoc dl) {
8586 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
8587 LoadSDNode *LD = nullptr;
8588 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
8589 LD = dyn_cast<LoadSDNode>(SrcOp);
8591 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
8593 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
8594 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
8595 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
8596 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
8597 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
8599 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
8600 return DAG.getNode(ISD::BITCAST, dl, VT,
8601 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
8602 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8610 return DAG.getNode(ISD::BITCAST, dl, VT,
8611 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
8612 DAG.getNode(ISD::BITCAST, dl,
8616 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
8617 /// which could not be matched by any known target speficic shuffle
8619 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
8621 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
8622 if (NewOp.getNode())
8625 MVT VT = SVOp->getSimpleValueType(0);
8627 unsigned NumElems = VT.getVectorNumElements();
8628 unsigned NumLaneElems = NumElems / 2;
8631 MVT EltVT = VT.getVectorElementType();
8632 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
8635 SmallVector<int, 16> Mask;
8636 for (unsigned l = 0; l < 2; ++l) {
8637 // Build a shuffle mask for the output, discovering on the fly which
8638 // input vectors to use as shuffle operands (recorded in InputUsed).
8639 // If building a suitable shuffle vector proves too hard, then bail
8640 // out with UseBuildVector set.
8641 bool UseBuildVector = false;
8642 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
8643 unsigned LaneStart = l * NumLaneElems;
8644 for (unsigned i = 0; i != NumLaneElems; ++i) {
8645 // The mask element. This indexes into the input.
8646 int Idx = SVOp->getMaskElt(i+LaneStart);
8648 // the mask element does not index into any input vector.
8653 // The input vector this mask element indexes into.
8654 int Input = Idx / NumLaneElems;
8656 // Turn the index into an offset from the start of the input vector.
8657 Idx -= Input * NumLaneElems;
8659 // Find or create a shuffle vector operand to hold this input.
8661 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
8662 if (InputUsed[OpNo] == Input)
8663 // This input vector is already an operand.
8665 if (InputUsed[OpNo] < 0) {
8666 // Create a new operand for this input vector.
8667 InputUsed[OpNo] = Input;
8672 if (OpNo >= array_lengthof(InputUsed)) {
8673 // More than two input vectors used! Give up on trying to create a
8674 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
8675 UseBuildVector = true;
8679 // Add the mask index for the new shuffle vector.
8680 Mask.push_back(Idx + OpNo * NumLaneElems);
8683 if (UseBuildVector) {
8684 SmallVector<SDValue, 16> SVOps;
8685 for (unsigned i = 0; i != NumLaneElems; ++i) {
8686 // The mask element. This indexes into the input.
8687 int Idx = SVOp->getMaskElt(i+LaneStart);
8689 SVOps.push_back(DAG.getUNDEF(EltVT));
8693 // The input vector this mask element indexes into.
8694 int Input = Idx / NumElems;
8696 // Turn the index into an offset from the start of the input vector.
8697 Idx -= Input * NumElems;
8699 // Extract the vector element by hand.
8700 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
8701 SVOp->getOperand(Input),
8702 DAG.getIntPtrConstant(Idx)));
8705 // Construct the output using a BUILD_VECTOR.
8706 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
8707 } else if (InputUsed[0] < 0) {
8708 // No input vectors were used! The result is undefined.
8709 Output[l] = DAG.getUNDEF(NVT);
8711 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
8712 (InputUsed[0] % 2) * NumLaneElems,
8714 // If only one input was used, use an undefined vector for the other.
8715 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
8716 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
8717 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
8718 // At least one input vector was used. Create a new shuffle vector.
8719 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
8725 // Concatenate the result back
8726 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
8729 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
8730 /// 4 elements, and match them with several different shuffle types.
8732 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
8733 SDValue V1 = SVOp->getOperand(0);
8734 SDValue V2 = SVOp->getOperand(1);
8736 MVT VT = SVOp->getSimpleValueType(0);
8738 assert(VT.is128BitVector() && "Unsupported vector size");
8740 std::pair<int, int> Locs[4];
8741 int Mask1[] = { -1, -1, -1, -1 };
8742 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
8746 for (unsigned i = 0; i != 4; ++i) {
8747 int Idx = PermMask[i];
8749 Locs[i] = std::make_pair(-1, -1);
8751 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
8753 Locs[i] = std::make_pair(0, NumLo);
8757 Locs[i] = std::make_pair(1, NumHi);
8759 Mask1[2+NumHi] = Idx;
8765 if (NumLo <= 2 && NumHi <= 2) {
8766 // If no more than two elements come from either vector. This can be
8767 // implemented with two shuffles. First shuffle gather the elements.
8768 // The second shuffle, which takes the first shuffle as both of its
8769 // vector operands, put the elements into the right order.
8770 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
8772 int Mask2[] = { -1, -1, -1, -1 };
8774 for (unsigned i = 0; i != 4; ++i)
8775 if (Locs[i].first != -1) {
8776 unsigned Idx = (i < 2) ? 0 : 4;
8777 Idx += Locs[i].first * 2 + Locs[i].second;
8781 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
8784 if (NumLo == 3 || NumHi == 3) {
8785 // Otherwise, we must have three elements from one vector, call it X, and
8786 // one element from the other, call it Y. First, use a shufps to build an
8787 // intermediate vector with the one element from Y and the element from X
8788 // that will be in the same half in the final destination (the indexes don't
8789 // matter). Then, use a shufps to build the final vector, taking the half
8790 // containing the element from Y from the intermediate, and the other half
8793 // Normalize it so the 3 elements come from V1.
8794 CommuteVectorShuffleMask(PermMask, 4);
8798 // Find the element from V2.
8800 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
8801 int Val = PermMask[HiIndex];
8808 Mask1[0] = PermMask[HiIndex];
8810 Mask1[2] = PermMask[HiIndex^1];
8812 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
8815 Mask1[0] = PermMask[0];
8816 Mask1[1] = PermMask[1];
8817 Mask1[2] = HiIndex & 1 ? 6 : 4;
8818 Mask1[3] = HiIndex & 1 ? 4 : 6;
8819 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
8822 Mask1[0] = HiIndex & 1 ? 2 : 0;
8823 Mask1[1] = HiIndex & 1 ? 0 : 2;
8824 Mask1[2] = PermMask[2];
8825 Mask1[3] = PermMask[3];
8830 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
8833 // Break it into (shuffle shuffle_hi, shuffle_lo).
8834 int LoMask[] = { -1, -1, -1, -1 };
8835 int HiMask[] = { -1, -1, -1, -1 };
8837 int *MaskPtr = LoMask;
8838 unsigned MaskIdx = 0;
8841 for (unsigned i = 0; i != 4; ++i) {
8848 int Idx = PermMask[i];
8850 Locs[i] = std::make_pair(-1, -1);
8851 } else if (Idx < 4) {
8852 Locs[i] = std::make_pair(MaskIdx, LoIdx);
8853 MaskPtr[LoIdx] = Idx;
8856 Locs[i] = std::make_pair(MaskIdx, HiIdx);
8857 MaskPtr[HiIdx] = Idx;
8862 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
8863 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
8864 int MaskOps[] = { -1, -1, -1, -1 };
8865 for (unsigned i = 0; i != 4; ++i)
8866 if (Locs[i].first != -1)
8867 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
8868 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
8871 static bool MayFoldVectorLoad(SDValue V) {
8872 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
8873 V = V.getOperand(0);
8875 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
8876 V = V.getOperand(0);
8877 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
8878 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
8879 // BUILD_VECTOR (load), undef
8880 V = V.getOperand(0);
8882 return MayFoldLoad(V);
8886 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
8887 MVT VT = Op.getSimpleValueType();
8889 // Canonizalize to v2f64.
8890 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
8891 return DAG.getNode(ISD::BITCAST, dl, VT,
8892 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
8897 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
8899 SDValue V1 = Op.getOperand(0);
8900 SDValue V2 = Op.getOperand(1);
8901 MVT VT = Op.getSimpleValueType();
8903 assert(VT != MVT::v2i64 && "unsupported shuffle type");
8905 if (HasSSE2 && VT == MVT::v2f64)
8906 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
8908 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
8909 return DAG.getNode(ISD::BITCAST, dl, VT,
8910 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
8911 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
8912 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
8916 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
8917 SDValue V1 = Op.getOperand(0);
8918 SDValue V2 = Op.getOperand(1);
8919 MVT VT = Op.getSimpleValueType();
8921 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
8922 "unsupported shuffle type");
8924 if (V2.getOpcode() == ISD::UNDEF)
8928 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
8932 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
8933 SDValue V1 = Op.getOperand(0);
8934 SDValue V2 = Op.getOperand(1);
8935 MVT VT = Op.getSimpleValueType();
8936 unsigned NumElems = VT.getVectorNumElements();
8938 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
8939 // operand of these instructions is only memory, so check if there's a
8940 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
8942 bool CanFoldLoad = false;
8944 // Trivial case, when V2 comes from a load.
8945 if (MayFoldVectorLoad(V2))
8948 // When V1 is a load, it can be folded later into a store in isel, example:
8949 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
8951 // (MOVLPSmr addr:$src1, VR128:$src2)
8952 // So, recognize this potential and also use MOVLPS or MOVLPD
8953 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
8956 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8958 if (HasSSE2 && NumElems == 2)
8959 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
8962 // If we don't care about the second element, proceed to use movss.
8963 if (SVOp->getMaskElt(1) != -1)
8964 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
8967 // movl and movlp will both match v2i64, but v2i64 is never matched by
8968 // movl earlier because we make it strict to avoid messing with the movlp load
8969 // folding logic (see the code above getMOVLP call). Match it here then,
8970 // this is horrible, but will stay like this until we move all shuffle
8971 // matching to x86 specific nodes. Note that for the 1st condition all
8972 // types are matched with movsd.
8974 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
8975 // as to remove this logic from here, as much as possible
8976 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
8977 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
8978 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
8981 assert(VT != MVT::v4i32 && "unsupported shuffle type");
8983 // Invert the operand order and use SHUFPS to match it.
8984 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
8985 getShuffleSHUFImmediate(SVOp), DAG);
8988 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
8989 SelectionDAG &DAG) {
8991 MVT VT = Load->getSimpleValueType(0);
8992 MVT EVT = VT.getVectorElementType();
8993 SDValue Addr = Load->getOperand(1);
8994 SDValue NewAddr = DAG.getNode(
8995 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
8996 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
8999 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
9000 DAG.getMachineFunction().getMachineMemOperand(
9001 Load->getMemOperand(), 0, EVT.getStoreSize()));
9005 // It is only safe to call this function if isINSERTPSMask is true for
9006 // this shufflevector mask.
9007 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
9008 SelectionDAG &DAG) {
9009 // Generate an insertps instruction when inserting an f32 from memory onto a
9010 // v4f32 or when copying a member from one v4f32 to another.
9011 // We also use it for transferring i32 from one register to another,
9012 // since it simply copies the same bits.
9013 // If we're transferring an i32 from memory to a specific element in a
9014 // register, we output a generic DAG that will match the PINSRD
9016 MVT VT = SVOp->getSimpleValueType(0);
9017 MVT EVT = VT.getVectorElementType();
9018 SDValue V1 = SVOp->getOperand(0);
9019 SDValue V2 = SVOp->getOperand(1);
9020 auto Mask = SVOp->getMask();
9021 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
9022 "unsupported vector type for insertps/pinsrd");
9024 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
9025 auto FromV2Predicate = [](const int &i) { return i >= 4; };
9026 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
9034 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
9037 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
9038 "More than one element from V1 and from V2, or no elements from one "
9039 "of the vectors. This case should not have returned true from "
9044 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
9047 unsigned SrcIndex = Mask[DestIndex] % 4;
9048 if (MayFoldLoad(From)) {
9049 // Trivial case, when From comes from a load and is only used by the
9050 // shuffle. Make it use insertps from the vector that we need from that
9053 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
9054 if (!NewLoad.getNode())
9057 if (EVT == MVT::f32) {
9058 // Create this as a scalar to vector to match the instruction pattern.
9059 SDValue LoadScalarToVector =
9060 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
9061 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
9062 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
9064 } else { // EVT == MVT::i32
9065 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
9066 // instruction, to match the PINSRD instruction, which loads an i32 to a
9067 // certain vector element.
9068 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
9069 DAG.getConstant(DestIndex, MVT::i32));
9073 // Vector-element-to-vector
9074 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
9075 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
9078 // Reduce a vector shuffle to zext.
9079 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
9080 SelectionDAG &DAG) {
9081 // PMOVZX is only available from SSE41.
9082 if (!Subtarget->hasSSE41())
9085 MVT VT = Op.getSimpleValueType();
9087 // Only AVX2 support 256-bit vector integer extending.
9088 if (!Subtarget->hasInt256() && VT.is256BitVector())
9091 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9093 SDValue V1 = Op.getOperand(0);
9094 SDValue V2 = Op.getOperand(1);
9095 unsigned NumElems = VT.getVectorNumElements();
9097 // Extending is an unary operation and the element type of the source vector
9098 // won't be equal to or larger than i64.
9099 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
9100 VT.getVectorElementType() == MVT::i64)
9103 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
9104 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
9105 while ((1U << Shift) < NumElems) {
9106 if (SVOp->getMaskElt(1U << Shift) == 1)
9109 // The maximal ratio is 8, i.e. from i8 to i64.
9114 // Check the shuffle mask.
9115 unsigned Mask = (1U << Shift) - 1;
9116 for (unsigned i = 0; i != NumElems; ++i) {
9117 int EltIdx = SVOp->getMaskElt(i);
9118 if ((i & Mask) != 0 && EltIdx != -1)
9120 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
9124 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
9125 MVT NeVT = MVT::getIntegerVT(NBits);
9126 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
9128 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
9131 // Simplify the operand as it's prepared to be fed into shuffle.
9132 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
9133 if (V1.getOpcode() == ISD::BITCAST &&
9134 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
9135 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
9136 V1.getOperand(0).getOperand(0)
9137 .getSimpleValueType().getSizeInBits() == SignificantBits) {
9138 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
9139 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
9140 ConstantSDNode *CIdx =
9141 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
9142 // If it's foldable, i.e. normal load with single use, we will let code
9143 // selection to fold it. Otherwise, we will short the conversion sequence.
9144 if (CIdx && CIdx->getZExtValue() == 0 &&
9145 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
9146 MVT FullVT = V.getSimpleValueType();
9147 MVT V1VT = V1.getSimpleValueType();
9148 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
9149 // The "ext_vec_elt" node is wider than the result node.
9150 // In this case we should extract subvector from V.
9151 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
9152 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
9153 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
9154 FullVT.getVectorNumElements()/Ratio);
9155 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
9156 DAG.getIntPtrConstant(0));
9158 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
9162 return DAG.getNode(ISD::BITCAST, DL, VT,
9163 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
9166 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
9167 SelectionDAG &DAG) {
9168 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9169 MVT VT = Op.getSimpleValueType();
9171 SDValue V1 = Op.getOperand(0);
9172 SDValue V2 = Op.getOperand(1);
9174 if (isZeroShuffle(SVOp))
9175 return getZeroVector(VT, Subtarget, DAG, dl);
9177 // Handle splat operations
9178 if (SVOp->isSplat()) {
9179 // Use vbroadcast whenever the splat comes from a foldable load
9180 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
9181 if (Broadcast.getNode())
9185 // Check integer expanding shuffles.
9186 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
9187 if (NewOp.getNode())
9190 // If the shuffle can be profitably rewritten as a narrower shuffle, then
9192 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
9194 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
9195 if (NewOp.getNode())
9196 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
9197 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
9198 // FIXME: Figure out a cleaner way to do this.
9199 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
9200 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
9201 if (NewOp.getNode()) {
9202 MVT NewVT = NewOp.getSimpleValueType();
9203 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
9204 NewVT, true, false))
9205 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
9208 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
9209 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
9210 if (NewOp.getNode()) {
9211 MVT NewVT = NewOp.getSimpleValueType();
9212 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
9213 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
9222 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
9223 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9224 SDValue V1 = Op.getOperand(0);
9225 SDValue V2 = Op.getOperand(1);
9226 MVT VT = Op.getSimpleValueType();
9228 unsigned NumElems = VT.getVectorNumElements();
9229 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
9230 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9231 bool V1IsSplat = false;
9232 bool V2IsSplat = false;
9233 bool HasSSE2 = Subtarget->hasSSE2();
9234 bool HasFp256 = Subtarget->hasFp256();
9235 bool HasInt256 = Subtarget->hasInt256();
9236 MachineFunction &MF = DAG.getMachineFunction();
9237 bool OptForSize = MF.getFunction()->getAttributes().
9238 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
9240 // Check if we should use the experimental vector shuffle lowering. If so,
9241 // delegate completely to that code path.
9242 if (ExperimentalVectorShuffleLowering)
9243 return lowerVectorShuffle(Op, Subtarget, DAG);
9245 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
9247 if (V1IsUndef && V2IsUndef)
9248 return DAG.getUNDEF(VT);
9250 // When we create a shuffle node we put the UNDEF node to second operand,
9251 // but in some cases the first operand may be transformed to UNDEF.
9252 // In this case we should just commute the node.
9254 return CommuteVectorShuffle(SVOp, DAG);
9256 // Vector shuffle lowering takes 3 steps:
9258 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
9259 // narrowing and commutation of operands should be handled.
9260 // 2) Matching of shuffles with known shuffle masks to x86 target specific
9262 // 3) Rewriting of unmatched masks into new generic shuffle operations,
9263 // so the shuffle can be broken into other shuffles and the legalizer can
9264 // try the lowering again.
9266 // The general idea is that no vector_shuffle operation should be left to
9267 // be matched during isel, all of them must be converted to a target specific
9270 // Normalize the input vectors. Here splats, zeroed vectors, profitable
9271 // narrowing and commutation of operands should be handled. The actual code
9272 // doesn't include all of those, work in progress...
9273 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
9274 if (NewOp.getNode())
9277 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
9279 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
9280 // unpckh_undef). Only use pshufd if speed is more important than size.
9281 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
9282 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
9283 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
9284 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
9286 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
9287 V2IsUndef && MayFoldVectorLoad(V1))
9288 return getMOVDDup(Op, dl, V1, DAG);
9290 if (isMOVHLPS_v_undef_Mask(M, VT))
9291 return getMOVHighToLow(Op, dl, DAG);
9293 // Use to match splats
9294 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
9295 (VT == MVT::v2f64 || VT == MVT::v2i64))
9296 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
9298 if (isPSHUFDMask(M, VT)) {
9299 // The actual implementation will match the mask in the if above and then
9300 // during isel it can match several different instructions, not only pshufd
9301 // as its name says, sad but true, emulate the behavior for now...
9302 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
9303 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
9305 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
9307 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
9308 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
9310 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
9311 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
9314 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
9318 if (isPALIGNRMask(M, VT, Subtarget))
9319 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
9320 getShufflePALIGNRImmediate(SVOp),
9323 // Check if this can be converted into a logical shift.
9324 bool isLeft = false;
9327 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
9328 if (isShift && ShVal.hasOneUse()) {
9329 // If the shifted value has multiple uses, it may be cheaper to use
9330 // v_set0 + movlhps or movhlps, etc.
9331 MVT EltVT = VT.getVectorElementType();
9332 ShAmt *= EltVT.getSizeInBits();
9333 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
9336 if (isMOVLMask(M, VT)) {
9337 if (ISD::isBuildVectorAllZeros(V1.getNode()))
9338 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
9339 if (!isMOVLPMask(M, VT)) {
9340 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
9341 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
9343 if (VT == MVT::v4i32 || VT == MVT::v4f32)
9344 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
9348 // FIXME: fold these into legal mask.
9349 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
9350 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
9352 if (isMOVHLPSMask(M, VT))
9353 return getMOVHighToLow(Op, dl, DAG);
9355 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
9356 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
9358 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
9359 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
9361 if (isMOVLPMask(M, VT))
9362 return getMOVLP(Op, dl, DAG, HasSSE2);
9364 if (ShouldXformToMOVHLPS(M, VT) ||
9365 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
9366 return CommuteVectorShuffle(SVOp, DAG);
9369 // No better options. Use a vshldq / vsrldq.
9370 MVT EltVT = VT.getVectorElementType();
9371 ShAmt *= EltVT.getSizeInBits();
9372 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
9375 bool Commuted = false;
9376 // FIXME: This should also accept a bitcast of a splat? Be careful, not
9377 // 1,1,1,1 -> v8i16 though.
9378 V1IsSplat = isSplatVector(V1.getNode());
9379 V2IsSplat = isSplatVector(V2.getNode());
9381 // Canonicalize the splat or undef, if present, to be on the RHS.
9382 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
9383 CommuteVectorShuffleMask(M, NumElems);
9385 std::swap(V1IsSplat, V2IsSplat);
9389 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
9390 // Shuffling low element of v1 into undef, just return v1.
9393 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
9394 // the instruction selector will not match, so get a canonical MOVL with
9395 // swapped operands to undo the commute.
9396 return getMOVL(DAG, dl, VT, V2, V1);
9399 if (isUNPCKLMask(M, VT, HasInt256))
9400 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
9402 if (isUNPCKHMask(M, VT, HasInt256))
9403 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
9406 // Normalize mask so all entries that point to V2 points to its first
9407 // element then try to match unpck{h|l} again. If match, return a
9408 // new vector_shuffle with the corrected mask.p
9409 SmallVector<int, 8> NewMask(M.begin(), M.end());
9410 NormalizeMask(NewMask, NumElems);
9411 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
9412 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
9413 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
9414 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
9418 // Commute is back and try unpck* again.
9419 // FIXME: this seems wrong.
9420 CommuteVectorShuffleMask(M, NumElems);
9422 std::swap(V1IsSplat, V2IsSplat);
9424 if (isUNPCKLMask(M, VT, HasInt256))
9425 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
9427 if (isUNPCKHMask(M, VT, HasInt256))
9428 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
9431 // Normalize the node to match x86 shuffle ops if needed
9432 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
9433 return CommuteVectorShuffle(SVOp, DAG);
9435 // The checks below are all present in isShuffleMaskLegal, but they are
9436 // inlined here right now to enable us to directly emit target specific
9437 // nodes, and remove one by one until they don't return Op anymore.
9439 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
9440 SVOp->getSplatIndex() == 0 && V2IsUndef) {
9441 if (VT == MVT::v2f64 || VT == MVT::v2i64)
9442 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
9445 if (isPSHUFHWMask(M, VT, HasInt256))
9446 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
9447 getShufflePSHUFHWImmediate(SVOp),
9450 if (isPSHUFLWMask(M, VT, HasInt256))
9451 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
9452 getShufflePSHUFLWImmediate(SVOp),
9456 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
9458 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
9460 if (isSHUFPMask(M, VT))
9461 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
9462 getShuffleSHUFImmediate(SVOp), DAG);
9464 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
9465 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
9466 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
9467 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
9469 //===--------------------------------------------------------------------===//
9470 // Generate target specific nodes for 128 or 256-bit shuffles only
9471 // supported in the AVX instruction set.
9474 // Handle VMOVDDUPY permutations
9475 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
9476 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
9478 // Handle VPERMILPS/D* permutations
9479 if (isVPERMILPMask(M, VT)) {
9480 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
9481 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
9482 getShuffleSHUFImmediate(SVOp), DAG);
9483 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
9484 getShuffleSHUFImmediate(SVOp), DAG);
9488 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
9489 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
9490 Idx*(NumElems/2), DAG, dl);
9492 // Handle VPERM2F128/VPERM2I128 permutations
9493 if (isVPERM2X128Mask(M, VT, HasFp256))
9494 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
9495 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
9497 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
9498 return getINSERTPS(SVOp, dl, DAG);
9501 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
9502 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
9504 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
9505 VT.is512BitVector()) {
9506 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
9507 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
9508 SmallVector<SDValue, 16> permclMask;
9509 for (unsigned i = 0; i != NumElems; ++i) {
9510 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
9513 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
9515 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
9516 return DAG.getNode(X86ISD::VPERMV, dl, VT,
9517 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
9518 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
9519 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
9522 //===--------------------------------------------------------------------===//
9523 // Since no target specific shuffle was selected for this generic one,
9524 // lower it into other known shuffles. FIXME: this isn't true yet, but
9525 // this is the plan.
9528 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
9529 if (VT == MVT::v8i16) {
9530 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
9531 if (NewOp.getNode())
9535 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
9536 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
9537 if (NewOp.getNode())
9541 if (VT == MVT::v16i8) {
9542 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
9543 if (NewOp.getNode())
9547 if (VT == MVT::v32i8) {
9548 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
9549 if (NewOp.getNode())
9553 // Handle all 128-bit wide vectors with 4 elements, and match them with
9554 // several different shuffle types.
9555 if (NumElems == 4 && VT.is128BitVector())
9556 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
9558 // Handle general 256-bit shuffles
9559 if (VT.is256BitVector())
9560 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
9565 // This function assumes its argument is a BUILD_VECTOR of constants or
9566 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
9568 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
9569 unsigned &MaskValue) {
9571 unsigned NumElems = BuildVector->getNumOperands();
9572 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
9573 unsigned NumLanes = (NumElems - 1) / 8 + 1;
9574 unsigned NumElemsInLane = NumElems / NumLanes;
9576 // Blend for v16i16 should be symetric for the both lanes.
9577 for (unsigned i = 0; i < NumElemsInLane; ++i) {
9578 SDValue EltCond = BuildVector->getOperand(i);
9579 SDValue SndLaneEltCond =
9580 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
9582 int Lane1Cond = -1, Lane2Cond = -1;
9583 if (isa<ConstantSDNode>(EltCond))
9584 Lane1Cond = !isZero(EltCond);
9585 if (isa<ConstantSDNode>(SndLaneEltCond))
9586 Lane2Cond = !isZero(SndLaneEltCond);
9588 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
9589 // Lane1Cond != 0, means we want the first argument.
9590 // Lane1Cond == 0, means we want the second argument.
9591 // The encoding of this argument is 0 for the first argument, 1
9592 // for the second. Therefore, invert the condition.
9593 MaskValue |= !Lane1Cond << i;
9594 else if (Lane1Cond < 0)
9595 MaskValue |= !Lane2Cond << i;
9602 // Try to lower a vselect node into a simple blend instruction.
9603 static SDValue LowerVSELECTtoBlend(SDValue Op, const X86Subtarget *Subtarget,
9604 SelectionDAG &DAG) {
9605 SDValue Cond = Op.getOperand(0);
9606 SDValue LHS = Op.getOperand(1);
9607 SDValue RHS = Op.getOperand(2);
9609 MVT VT = Op.getSimpleValueType();
9610 MVT EltVT = VT.getVectorElementType();
9611 unsigned NumElems = VT.getVectorNumElements();
9613 // There is no blend with immediate in AVX-512.
9614 if (VT.is512BitVector())
9617 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
9619 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
9622 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
9625 // Check the mask for BLEND and build the value.
9626 unsigned MaskValue = 0;
9627 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
9630 // Convert i32 vectors to floating point if it is not AVX2.
9631 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
9633 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
9634 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
9636 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
9637 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
9640 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
9641 DAG.getConstant(MaskValue, MVT::i32));
9642 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
9645 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
9646 SDValue BlendOp = LowerVSELECTtoBlend(Op, Subtarget, DAG);
9647 if (BlendOp.getNode())
9650 // Some types for vselect were previously set to Expand, not Legal or
9651 // Custom. Return an empty SDValue so we fall-through to Expand, after
9652 // the Custom lowering phase.
9653 MVT VT = Op.getSimpleValueType();
9654 switch (VT.SimpleTy) {
9662 // We couldn't create a "Blend with immediate" node.
9663 // This node should still be legal, but we'll have to emit a blendv*
9668 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
9669 MVT VT = Op.getSimpleValueType();
9672 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
9675 if (VT.getSizeInBits() == 8) {
9676 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
9677 Op.getOperand(0), Op.getOperand(1));
9678 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
9679 DAG.getValueType(VT));
9680 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
9683 if (VT.getSizeInBits() == 16) {
9684 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
9685 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
9687 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
9688 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
9689 DAG.getNode(ISD::BITCAST, dl,
9693 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
9694 Op.getOperand(0), Op.getOperand(1));
9695 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
9696 DAG.getValueType(VT));
9697 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
9700 if (VT == MVT::f32) {
9701 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
9702 // the result back to FR32 register. It's only worth matching if the
9703 // result has a single use which is a store or a bitcast to i32. And in
9704 // the case of a store, it's not worth it if the index is a constant 0,
9705 // because a MOVSSmr can be used instead, which is smaller and faster.
9706 if (!Op.hasOneUse())
9708 SDNode *User = *Op.getNode()->use_begin();
9709 if ((User->getOpcode() != ISD::STORE ||
9710 (isa<ConstantSDNode>(Op.getOperand(1)) &&
9711 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
9712 (User->getOpcode() != ISD::BITCAST ||
9713 User->getValueType(0) != MVT::i32))
9715 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
9716 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
9719 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
9722 if (VT == MVT::i32 || VT == MVT::i64) {
9723 // ExtractPS/pextrq works with constant index.
9724 if (isa<ConstantSDNode>(Op.getOperand(1)))
9730 /// Extract one bit from mask vector, like v16i1 or v8i1.
9731 /// AVX-512 feature.
9733 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
9734 SDValue Vec = Op.getOperand(0);
9736 MVT VecVT = Vec.getSimpleValueType();
9737 SDValue Idx = Op.getOperand(1);
9738 MVT EltVT = Op.getSimpleValueType();
9740 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
9742 // variable index can't be handled in mask registers,
9743 // extend vector to VR512
9744 if (!isa<ConstantSDNode>(Idx)) {
9745 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
9746 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
9747 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
9748 ExtVT.getVectorElementType(), Ext, Idx);
9749 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
9752 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
9753 const TargetRegisterClass* rc = getRegClassFor(VecVT);
9754 unsigned MaxSift = rc->getSize()*8 - 1;
9755 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
9756 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
9757 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
9758 DAG.getConstant(MaxSift, MVT::i8));
9759 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
9760 DAG.getIntPtrConstant(0));
9764 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
9765 SelectionDAG &DAG) const {
9767 SDValue Vec = Op.getOperand(0);
9768 MVT VecVT = Vec.getSimpleValueType();
9769 SDValue Idx = Op.getOperand(1);
9771 if (Op.getSimpleValueType() == MVT::i1)
9772 return ExtractBitFromMaskVector(Op, DAG);
9774 if (!isa<ConstantSDNode>(Idx)) {
9775 if (VecVT.is512BitVector() ||
9776 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
9777 VecVT.getVectorElementType().getSizeInBits() == 32)) {
9780 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
9781 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
9782 MaskEltVT.getSizeInBits());
9784 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
9785 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
9786 getZeroVector(MaskVT, Subtarget, DAG, dl),
9787 Idx, DAG.getConstant(0, getPointerTy()));
9788 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
9789 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
9790 Perm, DAG.getConstant(0, getPointerTy()));
9795 // If this is a 256-bit vector result, first extract the 128-bit vector and
9796 // then extract the element from the 128-bit vector.
9797 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
9799 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
9800 // Get the 128-bit vector.
9801 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
9802 MVT EltVT = VecVT.getVectorElementType();
9804 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
9806 //if (IdxVal >= NumElems/2)
9807 // IdxVal -= NumElems/2;
9808 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
9809 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
9810 DAG.getConstant(IdxVal, MVT::i32));
9813 assert(VecVT.is128BitVector() && "Unexpected vector length");
9815 if (Subtarget->hasSSE41()) {
9816 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
9821 MVT VT = Op.getSimpleValueType();
9822 // TODO: handle v16i8.
9823 if (VT.getSizeInBits() == 16) {
9824 SDValue Vec = Op.getOperand(0);
9825 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
9827 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
9828 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
9829 DAG.getNode(ISD::BITCAST, dl,
9832 // Transform it so it match pextrw which produces a 32-bit result.
9833 MVT EltVT = MVT::i32;
9834 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
9835 Op.getOperand(0), Op.getOperand(1));
9836 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
9837 DAG.getValueType(VT));
9838 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
9841 if (VT.getSizeInBits() == 32) {
9842 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
9846 // SHUFPS the element to the lowest double word, then movss.
9847 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
9848 MVT VVT = Op.getOperand(0).getSimpleValueType();
9849 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
9850 DAG.getUNDEF(VVT), Mask);
9851 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
9852 DAG.getIntPtrConstant(0));
9855 if (VT.getSizeInBits() == 64) {
9856 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
9857 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
9858 // to match extract_elt for f64.
9859 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
9863 // UNPCKHPD the element to the lowest double word, then movsd.
9864 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
9865 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
9866 int Mask[2] = { 1, -1 };
9867 MVT VVT = Op.getOperand(0).getSimpleValueType();
9868 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
9869 DAG.getUNDEF(VVT), Mask);
9870 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
9871 DAG.getIntPtrConstant(0));
9877 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
9878 MVT VT = Op.getSimpleValueType();
9879 MVT EltVT = VT.getVectorElementType();
9882 SDValue N0 = Op.getOperand(0);
9883 SDValue N1 = Op.getOperand(1);
9884 SDValue N2 = Op.getOperand(2);
9886 if (!VT.is128BitVector())
9889 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
9890 isa<ConstantSDNode>(N2)) {
9892 if (VT == MVT::v8i16)
9893 Opc = X86ISD::PINSRW;
9894 else if (VT == MVT::v16i8)
9895 Opc = X86ISD::PINSRB;
9897 Opc = X86ISD::PINSRB;
9899 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
9901 if (N1.getValueType() != MVT::i32)
9902 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
9903 if (N2.getValueType() != MVT::i32)
9904 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
9905 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
9908 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
9909 // Bits [7:6] of the constant are the source select. This will always be
9910 // zero here. The DAG Combiner may combine an extract_elt index into these
9911 // bits. For example (insert (extract, 3), 2) could be matched by putting
9912 // the '3' into bits [7:6] of X86ISD::INSERTPS.
9913 // Bits [5:4] of the constant are the destination select. This is the
9914 // value of the incoming immediate.
9915 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
9916 // combine either bitwise AND or insert of float 0.0 to set these bits.
9917 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
9918 // Create this as a scalar to vector..
9919 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
9920 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
9923 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
9924 // PINSR* works with constant index.
9930 /// Insert one bit to mask vector, like v16i1 or v8i1.
9931 /// AVX-512 feature.
9933 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
9935 SDValue Vec = Op.getOperand(0);
9936 SDValue Elt = Op.getOperand(1);
9937 SDValue Idx = Op.getOperand(2);
9938 MVT VecVT = Vec.getSimpleValueType();
9940 if (!isa<ConstantSDNode>(Idx)) {
9941 // Non constant index. Extend source and destination,
9942 // insert element and then truncate the result.
9943 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
9944 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
9945 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
9946 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
9947 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
9948 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
9951 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
9952 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
9953 if (Vec.getOpcode() == ISD::UNDEF)
9954 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
9955 DAG.getConstant(IdxVal, MVT::i8));
9956 const TargetRegisterClass* rc = getRegClassFor(VecVT);
9957 unsigned MaxSift = rc->getSize()*8 - 1;
9958 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
9959 DAG.getConstant(MaxSift, MVT::i8));
9960 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
9961 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
9962 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
9965 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
9966 MVT VT = Op.getSimpleValueType();
9967 MVT EltVT = VT.getVectorElementType();
9969 if (EltVT == MVT::i1)
9970 return InsertBitToMaskVector(Op, DAG);
9973 SDValue N0 = Op.getOperand(0);
9974 SDValue N1 = Op.getOperand(1);
9975 SDValue N2 = Op.getOperand(2);
9977 // If this is a 256-bit vector result, first extract the 128-bit vector,
9978 // insert the element into the extracted half and then place it back.
9979 if (VT.is256BitVector() || VT.is512BitVector()) {
9980 if (!isa<ConstantSDNode>(N2))
9983 // Get the desired 128-bit vector half.
9984 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
9985 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
9987 // Insert the element into the desired half.
9988 unsigned NumEltsIn128 = 128/EltVT.getSizeInBits();
9989 unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128;
9991 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
9992 DAG.getConstant(IdxIn128, MVT::i32));
9994 // Insert the changed part back to the 256-bit vector
9995 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
9998 if (Subtarget->hasSSE41())
9999 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
10001 if (EltVT == MVT::i8)
10004 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
10005 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
10006 // as its second argument.
10007 if (N1.getValueType() != MVT::i32)
10008 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10009 if (N2.getValueType() != MVT::i32)
10010 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
10011 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
10016 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
10018 MVT OpVT = Op.getSimpleValueType();
10020 // If this is a 256-bit vector result, first insert into a 128-bit
10021 // vector and then insert into the 256-bit vector.
10022 if (!OpVT.is128BitVector()) {
10023 // Insert into a 128-bit vector.
10024 unsigned SizeFactor = OpVT.getSizeInBits()/128;
10025 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
10026 OpVT.getVectorNumElements() / SizeFactor);
10028 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
10030 // Insert the 128-bit vector.
10031 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
10034 if (OpVT == MVT::v1i64 &&
10035 Op.getOperand(0).getValueType() == MVT::i64)
10036 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
10038 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
10039 assert(OpVT.is128BitVector() && "Expected an SSE type!");
10040 return DAG.getNode(ISD::BITCAST, dl, OpVT,
10041 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
10044 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
10045 // a simple subregister reference or explicit instructions to grab
10046 // upper bits of a vector.
10047 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10048 SelectionDAG &DAG) {
10050 SDValue In = Op.getOperand(0);
10051 SDValue Idx = Op.getOperand(1);
10052 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10053 MVT ResVT = Op.getSimpleValueType();
10054 MVT InVT = In.getSimpleValueType();
10056 if (Subtarget->hasFp256()) {
10057 if (ResVT.is128BitVector() &&
10058 (InVT.is256BitVector() || InVT.is512BitVector()) &&
10059 isa<ConstantSDNode>(Idx)) {
10060 return Extract128BitVector(In, IdxVal, DAG, dl);
10062 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
10063 isa<ConstantSDNode>(Idx)) {
10064 return Extract256BitVector(In, IdxVal, DAG, dl);
10070 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
10071 // simple superregister reference or explicit instructions to insert
10072 // the upper bits of a vector.
10073 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10074 SelectionDAG &DAG) {
10075 if (Subtarget->hasFp256()) {
10076 SDLoc dl(Op.getNode());
10077 SDValue Vec = Op.getNode()->getOperand(0);
10078 SDValue SubVec = Op.getNode()->getOperand(1);
10079 SDValue Idx = Op.getNode()->getOperand(2);
10081 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
10082 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
10083 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
10084 isa<ConstantSDNode>(Idx)) {
10085 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10086 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
10089 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
10090 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
10091 isa<ConstantSDNode>(Idx)) {
10092 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10093 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
10099 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
10100 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
10101 // one of the above mentioned nodes. It has to be wrapped because otherwise
10102 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
10103 // be used to form addressing mode. These wrapped nodes will be selected
10106 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
10107 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
10109 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10110 // global base reg.
10111 unsigned char OpFlag = 0;
10112 unsigned WrapperKind = X86ISD::Wrapper;
10113 CodeModel::Model M = DAG.getTarget().getCodeModel();
10115 if (Subtarget->isPICStyleRIPRel() &&
10116 (M == CodeModel::Small || M == CodeModel::Kernel))
10117 WrapperKind = X86ISD::WrapperRIP;
10118 else if (Subtarget->isPICStyleGOT())
10119 OpFlag = X86II::MO_GOTOFF;
10120 else if (Subtarget->isPICStyleStubPIC())
10121 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10123 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
10124 CP->getAlignment(),
10125 CP->getOffset(), OpFlag);
10127 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10128 // With PIC, the address is actually $g + Offset.
10130 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10131 DAG.getNode(X86ISD::GlobalBaseReg,
10132 SDLoc(), getPointerTy()),
10139 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
10140 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
10142 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10143 // global base reg.
10144 unsigned char OpFlag = 0;
10145 unsigned WrapperKind = X86ISD::Wrapper;
10146 CodeModel::Model M = DAG.getTarget().getCodeModel();
10148 if (Subtarget->isPICStyleRIPRel() &&
10149 (M == CodeModel::Small || M == CodeModel::Kernel))
10150 WrapperKind = X86ISD::WrapperRIP;
10151 else if (Subtarget->isPICStyleGOT())
10152 OpFlag = X86II::MO_GOTOFF;
10153 else if (Subtarget->isPICStyleStubPIC())
10154 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10156 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
10159 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10161 // With PIC, the address is actually $g + Offset.
10163 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10164 DAG.getNode(X86ISD::GlobalBaseReg,
10165 SDLoc(), getPointerTy()),
10172 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
10173 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
10175 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10176 // global base reg.
10177 unsigned char OpFlag = 0;
10178 unsigned WrapperKind = X86ISD::Wrapper;
10179 CodeModel::Model M = DAG.getTarget().getCodeModel();
10181 if (Subtarget->isPICStyleRIPRel() &&
10182 (M == CodeModel::Small || M == CodeModel::Kernel)) {
10183 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
10184 OpFlag = X86II::MO_GOTPCREL;
10185 WrapperKind = X86ISD::WrapperRIP;
10186 } else if (Subtarget->isPICStyleGOT()) {
10187 OpFlag = X86II::MO_GOT;
10188 } else if (Subtarget->isPICStyleStubPIC()) {
10189 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
10190 } else if (Subtarget->isPICStyleStubNoDynamic()) {
10191 OpFlag = X86II::MO_DARWIN_NONLAZY;
10194 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
10197 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10199 // With PIC, the address is actually $g + Offset.
10200 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
10201 !Subtarget->is64Bit()) {
10202 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10203 DAG.getNode(X86ISD::GlobalBaseReg,
10204 SDLoc(), getPointerTy()),
10208 // For symbols that require a load from a stub to get the address, emit the
10210 if (isGlobalStubReference(OpFlag))
10211 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
10212 MachinePointerInfo::getGOT(), false, false, false, 0);
10218 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
10219 // Create the TargetBlockAddressAddress node.
10220 unsigned char OpFlags =
10221 Subtarget->ClassifyBlockAddressReference();
10222 CodeModel::Model M = DAG.getTarget().getCodeModel();
10223 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
10224 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
10226 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
10229 if (Subtarget->isPICStyleRIPRel() &&
10230 (M == CodeModel::Small || M == CodeModel::Kernel))
10231 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
10233 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
10235 // With PIC, the address is actually $g + Offset.
10236 if (isGlobalRelativeToPICBase(OpFlags)) {
10237 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
10238 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
10246 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
10247 int64_t Offset, SelectionDAG &DAG) const {
10248 // Create the TargetGlobalAddress node, folding in the constant
10249 // offset if it is legal.
10250 unsigned char OpFlags =
10251 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
10252 CodeModel::Model M = DAG.getTarget().getCodeModel();
10254 if (OpFlags == X86II::MO_NO_FLAG &&
10255 X86::isOffsetSuitableForCodeModel(Offset, M)) {
10256 // A direct static reference to a global.
10257 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
10260 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
10263 if (Subtarget->isPICStyleRIPRel() &&
10264 (M == CodeModel::Small || M == CodeModel::Kernel))
10265 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
10267 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
10269 // With PIC, the address is actually $g + Offset.
10270 if (isGlobalRelativeToPICBase(OpFlags)) {
10271 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
10272 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
10276 // For globals that require a load from a stub to get the address, emit the
10278 if (isGlobalStubReference(OpFlags))
10279 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
10280 MachinePointerInfo::getGOT(), false, false, false, 0);
10282 // If there was a non-zero offset that we didn't fold, create an explicit
10283 // addition for it.
10285 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
10286 DAG.getConstant(Offset, getPointerTy()));
10292 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
10293 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
10294 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
10295 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
10299 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
10300 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
10301 unsigned char OperandFlags, bool LocalDynamic = false) {
10302 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10303 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10305 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
10306 GA->getValueType(0),
10310 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
10314 SDValue Ops[] = { Chain, TGA, *InFlag };
10315 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
10317 SDValue Ops[] = { Chain, TGA };
10318 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
10321 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
10322 MFI->setAdjustsStack(true);
10324 SDValue Flag = Chain.getValue(1);
10325 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
10328 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
10330 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
10333 SDLoc dl(GA); // ? function entry point might be better
10334 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
10335 DAG.getNode(X86ISD::GlobalBaseReg,
10336 SDLoc(), PtrVT), InFlag);
10337 InFlag = Chain.getValue(1);
10339 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
10342 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
10344 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
10346 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
10347 X86::RAX, X86II::MO_TLSGD);
10350 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
10356 // Get the start address of the TLS block for this module.
10357 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
10358 .getInfo<X86MachineFunctionInfo>();
10359 MFI->incNumLocalDynamicTLSAccesses();
10363 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
10364 X86II::MO_TLSLD, /*LocalDynamic=*/true);
10367 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
10368 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
10369 InFlag = Chain.getValue(1);
10370 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
10371 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
10374 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
10378 unsigned char OperandFlags = X86II::MO_DTPOFF;
10379 unsigned WrapperKind = X86ISD::Wrapper;
10380 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
10381 GA->getValueType(0),
10382 GA->getOffset(), OperandFlags);
10383 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
10385 // Add x@dtpoff with the base.
10386 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
10389 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
10390 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
10391 const EVT PtrVT, TLSModel::Model model,
10392 bool is64Bit, bool isPIC) {
10395 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
10396 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
10397 is64Bit ? 257 : 256));
10399 SDValue ThreadPointer =
10400 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
10401 MachinePointerInfo(Ptr), false, false, false, 0);
10403 unsigned char OperandFlags = 0;
10404 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
10406 unsigned WrapperKind = X86ISD::Wrapper;
10407 if (model == TLSModel::LocalExec) {
10408 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
10409 } else if (model == TLSModel::InitialExec) {
10411 OperandFlags = X86II::MO_GOTTPOFF;
10412 WrapperKind = X86ISD::WrapperRIP;
10414 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
10417 llvm_unreachable("Unexpected model");
10420 // emit "addl x@ntpoff,%eax" (local exec)
10421 // or "addl x@indntpoff,%eax" (initial exec)
10422 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
10424 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
10425 GA->getOffset(), OperandFlags);
10426 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
10428 if (model == TLSModel::InitialExec) {
10429 if (isPIC && !is64Bit) {
10430 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
10431 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
10435 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
10436 MachinePointerInfo::getGOT(), false, false, false, 0);
10439 // The address of the thread local variable is the add of the thread
10440 // pointer with the offset of the variable.
10441 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
10445 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
10447 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
10448 const GlobalValue *GV = GA->getGlobal();
10450 if (Subtarget->isTargetELF()) {
10451 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
10454 case TLSModel::GeneralDynamic:
10455 if (Subtarget->is64Bit())
10456 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
10457 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
10458 case TLSModel::LocalDynamic:
10459 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
10460 Subtarget->is64Bit());
10461 case TLSModel::InitialExec:
10462 case TLSModel::LocalExec:
10463 return LowerToTLSExecModel(
10464 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
10465 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
10467 llvm_unreachable("Unknown TLS model.");
10470 if (Subtarget->isTargetDarwin()) {
10471 // Darwin only has one model of TLS. Lower to that.
10472 unsigned char OpFlag = 0;
10473 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
10474 X86ISD::WrapperRIP : X86ISD::Wrapper;
10476 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10477 // global base reg.
10478 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
10479 !Subtarget->is64Bit();
10481 OpFlag = X86II::MO_TLVP_PIC_BASE;
10483 OpFlag = X86II::MO_TLVP;
10485 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
10486 GA->getValueType(0),
10487 GA->getOffset(), OpFlag);
10488 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10490 // With PIC32, the address is actually $g + Offset.
10492 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10493 DAG.getNode(X86ISD::GlobalBaseReg,
10494 SDLoc(), getPointerTy()),
10497 // Lowering the machine isd will make sure everything is in the right
10499 SDValue Chain = DAG.getEntryNode();
10500 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10501 SDValue Args[] = { Chain, Offset };
10502 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
10504 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
10505 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10506 MFI->setAdjustsStack(true);
10508 // And our return value (tls address) is in the standard call return value
10510 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
10511 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
10512 Chain.getValue(1));
10515 if (Subtarget->isTargetKnownWindowsMSVC() ||
10516 Subtarget->isTargetWindowsGNU()) {
10517 // Just use the implicit TLS architecture
10518 // Need to generate someting similar to:
10519 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
10521 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
10522 // mov rcx, qword [rdx+rcx*8]
10523 // mov eax, .tls$:tlsvar
10524 // [rax+rcx] contains the address
10525 // Windows 64bit: gs:0x58
10526 // Windows 32bit: fs:__tls_array
10529 SDValue Chain = DAG.getEntryNode();
10531 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
10532 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
10533 // use its literal value of 0x2C.
10534 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
10535 ? Type::getInt8PtrTy(*DAG.getContext(),
10537 : Type::getInt32PtrTy(*DAG.getContext(),
10541 Subtarget->is64Bit()
10542 ? DAG.getIntPtrConstant(0x58)
10543 : (Subtarget->isTargetWindowsGNU()
10544 ? DAG.getIntPtrConstant(0x2C)
10545 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
10547 SDValue ThreadPointer =
10548 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
10549 MachinePointerInfo(Ptr), false, false, false, 0);
10551 // Load the _tls_index variable
10552 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
10553 if (Subtarget->is64Bit())
10554 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
10555 IDX, MachinePointerInfo(), MVT::i32,
10558 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
10559 false, false, false, 0);
10561 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
10563 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
10565 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
10566 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
10567 false, false, false, 0);
10569 // Get the offset of start of .tls section
10570 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
10571 GA->getValueType(0),
10572 GA->getOffset(), X86II::MO_SECREL);
10573 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
10575 // The address of the thread local variable is the add of the thread
10576 // pointer with the offset of the variable.
10577 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
10580 llvm_unreachable("TLS not implemented for this target.");
10583 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
10584 /// and take a 2 x i32 value to shift plus a shift amount.
10585 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
10586 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
10587 MVT VT = Op.getSimpleValueType();
10588 unsigned VTBits = VT.getSizeInBits();
10590 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
10591 SDValue ShOpLo = Op.getOperand(0);
10592 SDValue ShOpHi = Op.getOperand(1);
10593 SDValue ShAmt = Op.getOperand(2);
10594 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
10595 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
10597 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
10598 DAG.getConstant(VTBits - 1, MVT::i8));
10599 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
10600 DAG.getConstant(VTBits - 1, MVT::i8))
10601 : DAG.getConstant(0, VT);
10603 SDValue Tmp2, Tmp3;
10604 if (Op.getOpcode() == ISD::SHL_PARTS) {
10605 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
10606 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
10608 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
10609 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
10612 // If the shift amount is larger or equal than the width of a part we can't
10613 // rely on the results of shld/shrd. Insert a test and select the appropriate
10614 // values for large shift amounts.
10615 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
10616 DAG.getConstant(VTBits, MVT::i8));
10617 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10618 AndNode, DAG.getConstant(0, MVT::i8));
10621 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10622 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
10623 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
10625 if (Op.getOpcode() == ISD::SHL_PARTS) {
10626 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
10627 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
10629 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
10630 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
10633 SDValue Ops[2] = { Lo, Hi };
10634 return DAG.getMergeValues(Ops, dl);
10637 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
10638 SelectionDAG &DAG) const {
10639 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
10641 if (SrcVT.isVector())
10644 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
10645 "Unknown SINT_TO_FP to lower!");
10647 // These are really Legal; return the operand so the caller accepts it as
10649 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
10651 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
10652 Subtarget->is64Bit()) {
10657 unsigned Size = SrcVT.getSizeInBits()/8;
10658 MachineFunction &MF = DAG.getMachineFunction();
10659 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
10660 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
10661 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
10663 MachinePointerInfo::getFixedStack(SSFI),
10665 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
10668 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
10670 SelectionDAG &DAG) const {
10674 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
10676 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
10678 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
10680 unsigned ByteSize = SrcVT.getSizeInBits()/8;
10682 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
10683 MachineMemOperand *MMO;
10685 int SSFI = FI->getIndex();
10687 DAG.getMachineFunction()
10688 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10689 MachineMemOperand::MOLoad, ByteSize, ByteSize);
10691 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
10692 StackSlot = StackSlot.getOperand(1);
10694 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
10695 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
10697 Tys, Ops, SrcVT, MMO);
10700 Chain = Result.getValue(1);
10701 SDValue InFlag = Result.getValue(2);
10703 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
10704 // shouldn't be necessary except that RFP cannot be live across
10705 // multiple blocks. When stackifier is fixed, they can be uncoupled.
10706 MachineFunction &MF = DAG.getMachineFunction();
10707 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
10708 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
10709 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
10710 Tys = DAG.getVTList(MVT::Other);
10712 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
10714 MachineMemOperand *MMO =
10715 DAG.getMachineFunction()
10716 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10717 MachineMemOperand::MOStore, SSFISize, SSFISize);
10719 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
10720 Ops, Op.getValueType(), MMO);
10721 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
10722 MachinePointerInfo::getFixedStack(SSFI),
10723 false, false, false, 0);
10729 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
10730 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
10731 SelectionDAG &DAG) const {
10732 // This algorithm is not obvious. Here it is what we're trying to output:
10735 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
10736 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
10738 haddpd %xmm0, %xmm0
10740 pshufd $0x4e, %xmm0, %xmm1
10746 LLVMContext *Context = DAG.getContext();
10748 // Build some magic constants.
10749 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
10750 Constant *C0 = ConstantDataVector::get(*Context, CV0);
10751 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
10753 SmallVector<Constant*,2> CV1;
10755 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
10756 APInt(64, 0x4330000000000000ULL))));
10758 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
10759 APInt(64, 0x4530000000000000ULL))));
10760 Constant *C1 = ConstantVector::get(CV1);
10761 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
10763 // Load the 64-bit value into an XMM register.
10764 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
10766 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
10767 MachinePointerInfo::getConstantPool(),
10768 false, false, false, 16);
10769 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
10770 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
10773 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
10774 MachinePointerInfo::getConstantPool(),
10775 false, false, false, 16);
10776 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
10777 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
10780 if (Subtarget->hasSSE3()) {
10781 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
10782 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
10784 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
10785 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
10787 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
10788 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
10792 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
10793 DAG.getIntPtrConstant(0));
10796 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
10797 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
10798 SelectionDAG &DAG) const {
10800 // FP constant to bias correct the final result.
10801 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
10804 // Load the 32-bit value into an XMM register.
10805 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
10808 // Zero out the upper parts of the register.
10809 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
10811 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
10812 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
10813 DAG.getIntPtrConstant(0));
10815 // Or the load with the bias.
10816 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
10817 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
10818 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
10819 MVT::v2f64, Load)),
10820 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
10821 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
10822 MVT::v2f64, Bias)));
10823 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
10824 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
10825 DAG.getIntPtrConstant(0));
10827 // Subtract the bias.
10828 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
10830 // Handle final rounding.
10831 EVT DestVT = Op.getValueType();
10833 if (DestVT.bitsLT(MVT::f64))
10834 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
10835 DAG.getIntPtrConstant(0));
10836 if (DestVT.bitsGT(MVT::f64))
10837 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
10839 // Handle final rounding.
10843 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
10844 SelectionDAG &DAG) const {
10845 SDValue N0 = Op.getOperand(0);
10846 MVT SVT = N0.getSimpleValueType();
10849 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
10850 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
10851 "Custom UINT_TO_FP is not supported!");
10853 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
10854 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
10855 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
10858 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
10859 SelectionDAG &DAG) const {
10860 SDValue N0 = Op.getOperand(0);
10863 if (Op.getValueType().isVector())
10864 return lowerUINT_TO_FP_vec(Op, DAG);
10866 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
10867 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
10868 // the optimization here.
10869 if (DAG.SignBitIsZero(N0))
10870 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
10872 MVT SrcVT = N0.getSimpleValueType();
10873 MVT DstVT = Op.getSimpleValueType();
10874 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
10875 return LowerUINT_TO_FP_i64(Op, DAG);
10876 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
10877 return LowerUINT_TO_FP_i32(Op, DAG);
10878 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
10881 // Make a 64-bit buffer, and use it to build an FILD.
10882 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
10883 if (SrcVT == MVT::i32) {
10884 SDValue WordOff = DAG.getConstant(4, getPointerTy());
10885 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
10886 getPointerTy(), StackSlot, WordOff);
10887 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
10888 StackSlot, MachinePointerInfo(),
10890 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
10891 OffsetSlot, MachinePointerInfo(),
10893 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
10897 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
10898 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
10899 StackSlot, MachinePointerInfo(),
10901 // For i64 source, we need to add the appropriate power of 2 if the input
10902 // was negative. This is the same as the optimization in
10903 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
10904 // we must be careful to do the computation in x87 extended precision, not
10905 // in SSE. (The generic code can't know it's OK to do this, or how to.)
10906 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
10907 MachineMemOperand *MMO =
10908 DAG.getMachineFunction()
10909 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10910 MachineMemOperand::MOLoad, 8, 8);
10912 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
10913 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
10914 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
10917 APInt FF(32, 0x5F800000ULL);
10919 // Check whether the sign bit is set.
10920 SDValue SignSet = DAG.getSetCC(dl,
10921 getSetCCResultType(*DAG.getContext(), MVT::i64),
10922 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
10925 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
10926 SDValue FudgePtr = DAG.getConstantPool(
10927 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
10930 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
10931 SDValue Zero = DAG.getIntPtrConstant(0);
10932 SDValue Four = DAG.getIntPtrConstant(4);
10933 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
10935 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
10937 // Load the value out, extending it from f32 to f80.
10938 // FIXME: Avoid the extend by constructing the right constant pool?
10939 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
10940 FudgePtr, MachinePointerInfo::getConstantPool(),
10941 MVT::f32, false, false, 4);
10942 // Extend everything to 80 bits to force it to be done on x87.
10943 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
10944 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
10947 std::pair<SDValue,SDValue>
10948 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
10949 bool IsSigned, bool IsReplace) const {
10952 EVT DstTy = Op.getValueType();
10954 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
10955 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
10959 assert(DstTy.getSimpleVT() <= MVT::i64 &&
10960 DstTy.getSimpleVT() >= MVT::i16 &&
10961 "Unknown FP_TO_INT to lower!");
10963 // These are really Legal.
10964 if (DstTy == MVT::i32 &&
10965 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
10966 return std::make_pair(SDValue(), SDValue());
10967 if (Subtarget->is64Bit() &&
10968 DstTy == MVT::i64 &&
10969 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
10970 return std::make_pair(SDValue(), SDValue());
10972 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
10973 // stack slot, or into the FTOL runtime function.
10974 MachineFunction &MF = DAG.getMachineFunction();
10975 unsigned MemSize = DstTy.getSizeInBits()/8;
10976 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
10977 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
10980 if (!IsSigned && isIntegerTypeFTOL(DstTy))
10981 Opc = X86ISD::WIN_FTOL;
10983 switch (DstTy.getSimpleVT().SimpleTy) {
10984 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
10985 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
10986 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
10987 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
10990 SDValue Chain = DAG.getEntryNode();
10991 SDValue Value = Op.getOperand(0);
10992 EVT TheVT = Op.getOperand(0).getValueType();
10993 // FIXME This causes a redundant load/store if the SSE-class value is already
10994 // in memory, such as if it is on the callstack.
10995 if (isScalarFPTypeInSSEReg(TheVT)) {
10996 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
10997 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
10998 MachinePointerInfo::getFixedStack(SSFI),
11000 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
11002 Chain, StackSlot, DAG.getValueType(TheVT)
11005 MachineMemOperand *MMO =
11006 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11007 MachineMemOperand::MOLoad, MemSize, MemSize);
11008 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
11009 Chain = Value.getValue(1);
11010 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11011 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11014 MachineMemOperand *MMO =
11015 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11016 MachineMemOperand::MOStore, MemSize, MemSize);
11018 if (Opc != X86ISD::WIN_FTOL) {
11019 // Build the FP_TO_INT*_IN_MEM
11020 SDValue Ops[] = { Chain, Value, StackSlot };
11021 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
11023 return std::make_pair(FIST, StackSlot);
11025 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
11026 DAG.getVTList(MVT::Other, MVT::Glue),
11028 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
11029 MVT::i32, ftol.getValue(1));
11030 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
11031 MVT::i32, eax.getValue(2));
11032 SDValue Ops[] = { eax, edx };
11033 SDValue pair = IsReplace
11034 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
11035 : DAG.getMergeValues(Ops, DL);
11036 return std::make_pair(pair, SDValue());
11040 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
11041 const X86Subtarget *Subtarget) {
11042 MVT VT = Op->getSimpleValueType(0);
11043 SDValue In = Op->getOperand(0);
11044 MVT InVT = In.getSimpleValueType();
11047 // Optimize vectors in AVX mode:
11050 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
11051 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
11052 // Concat upper and lower parts.
11055 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
11056 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
11057 // Concat upper and lower parts.
11060 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
11061 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
11062 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
11065 if (Subtarget->hasInt256())
11066 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
11068 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
11069 SDValue Undef = DAG.getUNDEF(InVT);
11070 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
11071 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11072 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11074 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
11075 VT.getVectorNumElements()/2);
11077 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
11078 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
11080 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
11083 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
11084 SelectionDAG &DAG) {
11085 MVT VT = Op->getSimpleValueType(0);
11086 SDValue In = Op->getOperand(0);
11087 MVT InVT = In.getSimpleValueType();
11089 unsigned int NumElts = VT.getVectorNumElements();
11090 if (NumElts != 8 && NumElts != 16)
11093 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
11094 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
11096 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
11097 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11098 // Now we have only mask extension
11099 assert(InVT.getVectorElementType() == MVT::i1);
11100 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
11101 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
11102 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
11103 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
11104 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
11105 MachinePointerInfo::getConstantPool(),
11106 false, false, false, Alignment);
11108 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
11109 if (VT.is512BitVector())
11111 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
11114 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
11115 SelectionDAG &DAG) {
11116 if (Subtarget->hasFp256()) {
11117 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
11125 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
11126 SelectionDAG &DAG) {
11128 MVT VT = Op.getSimpleValueType();
11129 SDValue In = Op.getOperand(0);
11130 MVT SVT = In.getSimpleValueType();
11132 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
11133 return LowerZERO_EXTEND_AVX512(Op, DAG);
11135 if (Subtarget->hasFp256()) {
11136 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
11141 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
11142 VT.getVectorNumElements() != SVT.getVectorNumElements());
11146 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
11148 MVT VT = Op.getSimpleValueType();
11149 SDValue In = Op.getOperand(0);
11150 MVT InVT = In.getSimpleValueType();
11152 if (VT == MVT::i1) {
11153 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
11154 "Invalid scalar TRUNCATE operation");
11155 if (InVT == MVT::i32)
11157 if (InVT.getSizeInBits() == 64)
11158 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::i32, In);
11159 else if (InVT.getSizeInBits() < 32)
11160 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
11161 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
11163 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
11164 "Invalid TRUNCATE operation");
11166 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
11167 if (VT.getVectorElementType().getSizeInBits() >=8)
11168 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
11170 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
11171 unsigned NumElts = InVT.getVectorNumElements();
11172 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
11173 if (InVT.getSizeInBits() < 512) {
11174 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
11175 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
11179 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
11180 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
11181 SDValue CP = DAG.getConstantPool(C, getPointerTy());
11182 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
11183 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
11184 MachinePointerInfo::getConstantPool(),
11185 false, false, false, Alignment);
11186 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
11187 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
11188 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
11191 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
11192 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
11193 if (Subtarget->hasInt256()) {
11194 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
11195 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
11196 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
11198 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
11199 DAG.getIntPtrConstant(0));
11202 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11203 DAG.getIntPtrConstant(0));
11204 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11205 DAG.getIntPtrConstant(2));
11206 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
11207 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
11208 static const int ShufMask[] = {0, 2, 4, 6};
11209 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
11212 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
11213 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
11214 if (Subtarget->hasInt256()) {
11215 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
11217 SmallVector<SDValue,32> pshufbMask;
11218 for (unsigned i = 0; i < 2; ++i) {
11219 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
11220 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
11221 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
11222 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
11223 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
11224 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
11225 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
11226 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
11227 for (unsigned j = 0; j < 8; ++j)
11228 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
11230 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
11231 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
11232 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
11234 static const int ShufMask[] = {0, 2, -1, -1};
11235 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
11237 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11238 DAG.getIntPtrConstant(0));
11239 return DAG.getNode(ISD::BITCAST, DL, VT, In);
11242 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
11243 DAG.getIntPtrConstant(0));
11245 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
11246 DAG.getIntPtrConstant(4));
11248 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
11249 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
11251 // The PSHUFB mask:
11252 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
11253 -1, -1, -1, -1, -1, -1, -1, -1};
11255 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
11256 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
11257 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
11259 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
11260 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
11262 // The MOVLHPS Mask:
11263 static const int ShufMask2[] = {0, 1, 4, 5};
11264 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
11265 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
11268 // Handle truncation of V256 to V128 using shuffles.
11269 if (!VT.is128BitVector() || !InVT.is256BitVector())
11272 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
11274 unsigned NumElems = VT.getVectorNumElements();
11275 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
11277 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
11278 // Prepare truncation shuffle mask
11279 for (unsigned i = 0; i != NumElems; ++i)
11280 MaskVec[i] = i * 2;
11281 SDValue V = DAG.getVectorShuffle(NVT, DL,
11282 DAG.getNode(ISD::BITCAST, DL, NVT, In),
11283 DAG.getUNDEF(NVT), &MaskVec[0]);
11284 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
11285 DAG.getIntPtrConstant(0));
11288 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
11289 SelectionDAG &DAG) const {
11290 assert(!Op.getSimpleValueType().isVector());
11292 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
11293 /*IsSigned=*/ true, /*IsReplace=*/ false);
11294 SDValue FIST = Vals.first, StackSlot = Vals.second;
11295 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
11296 if (!FIST.getNode()) return Op;
11298 if (StackSlot.getNode())
11299 // Load the result.
11300 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
11301 FIST, StackSlot, MachinePointerInfo(),
11302 false, false, false, 0);
11304 // The node is the result.
11308 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
11309 SelectionDAG &DAG) const {
11310 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
11311 /*IsSigned=*/ false, /*IsReplace=*/ false);
11312 SDValue FIST = Vals.first, StackSlot = Vals.second;
11313 assert(FIST.getNode() && "Unexpected failure");
11315 if (StackSlot.getNode())
11316 // Load the result.
11317 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
11318 FIST, StackSlot, MachinePointerInfo(),
11319 false, false, false, 0);
11321 // The node is the result.
11325 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
11327 MVT VT = Op.getSimpleValueType();
11328 SDValue In = Op.getOperand(0);
11329 MVT SVT = In.getSimpleValueType();
11331 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
11333 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
11334 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
11335 In, DAG.getUNDEF(SVT)));
11338 static SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) {
11339 LLVMContext *Context = DAG.getContext();
11341 MVT VT = Op.getSimpleValueType();
11343 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
11344 if (VT.isVector()) {
11345 EltVT = VT.getVectorElementType();
11346 NumElts = VT.getVectorNumElements();
11349 if (EltVT == MVT::f64)
11350 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11351 APInt(64, ~(1ULL << 63))));
11353 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
11354 APInt(32, ~(1U << 31))));
11355 C = ConstantVector::getSplat(NumElts, C);
11356 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11357 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
11358 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
11359 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
11360 MachinePointerInfo::getConstantPool(),
11361 false, false, false, Alignment);
11362 if (VT.isVector()) {
11363 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
11364 return DAG.getNode(ISD::BITCAST, dl, VT,
11365 DAG.getNode(ISD::AND, dl, ANDVT,
11366 DAG.getNode(ISD::BITCAST, dl, ANDVT,
11368 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
11370 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
11373 static SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) {
11374 LLVMContext *Context = DAG.getContext();
11376 MVT VT = Op.getSimpleValueType();
11378 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
11379 if (VT.isVector()) {
11380 EltVT = VT.getVectorElementType();
11381 NumElts = VT.getVectorNumElements();
11384 if (EltVT == MVT::f64)
11385 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11386 APInt(64, 1ULL << 63)));
11388 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
11389 APInt(32, 1U << 31)));
11390 C = ConstantVector::getSplat(NumElts, C);
11391 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11392 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
11393 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
11394 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
11395 MachinePointerInfo::getConstantPool(),
11396 false, false, false, Alignment);
11397 if (VT.isVector()) {
11398 MVT XORVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits()/64);
11399 return DAG.getNode(ISD::BITCAST, dl, VT,
11400 DAG.getNode(ISD::XOR, dl, XORVT,
11401 DAG.getNode(ISD::BITCAST, dl, XORVT,
11403 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
11406 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
11409 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
11410 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11411 LLVMContext *Context = DAG.getContext();
11412 SDValue Op0 = Op.getOperand(0);
11413 SDValue Op1 = Op.getOperand(1);
11415 MVT VT = Op.getSimpleValueType();
11416 MVT SrcVT = Op1.getSimpleValueType();
11418 // If second operand is smaller, extend it first.
11419 if (SrcVT.bitsLT(VT)) {
11420 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
11423 // And if it is bigger, shrink it first.
11424 if (SrcVT.bitsGT(VT)) {
11425 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
11429 // At this point the operands and the result should have the same
11430 // type, and that won't be f80 since that is not custom lowered.
11432 // First get the sign bit of second operand.
11433 SmallVector<Constant*,4> CV;
11434 if (SrcVT == MVT::f64) {
11435 const fltSemantics &Sem = APFloat::IEEEdouble;
11436 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
11437 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
11439 const fltSemantics &Sem = APFloat::IEEEsingle;
11440 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
11441 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11442 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11443 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11445 Constant *C = ConstantVector::get(CV);
11446 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
11447 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
11448 MachinePointerInfo::getConstantPool(),
11449 false, false, false, 16);
11450 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
11452 // Shift sign bit right or left if the two operands have different types.
11453 if (SrcVT.bitsGT(VT)) {
11454 // Op0 is MVT::f32, Op1 is MVT::f64.
11455 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
11456 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
11457 DAG.getConstant(32, MVT::i32));
11458 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
11459 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
11460 DAG.getIntPtrConstant(0));
11463 // Clear first operand sign bit.
11465 if (VT == MVT::f64) {
11466 const fltSemantics &Sem = APFloat::IEEEdouble;
11467 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
11468 APInt(64, ~(1ULL << 63)))));
11469 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
11471 const fltSemantics &Sem = APFloat::IEEEsingle;
11472 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
11473 APInt(32, ~(1U << 31)))));
11474 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11475 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11476 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11478 C = ConstantVector::get(CV);
11479 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
11480 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
11481 MachinePointerInfo::getConstantPool(),
11482 false, false, false, 16);
11483 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
11485 // Or the value with the sign bit.
11486 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
11489 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
11490 SDValue N0 = Op.getOperand(0);
11492 MVT VT = Op.getSimpleValueType();
11494 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
11495 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
11496 DAG.getConstant(1, VT));
11497 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
11500 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
11502 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
11503 SelectionDAG &DAG) {
11504 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
11506 if (!Subtarget->hasSSE41())
11509 if (!Op->hasOneUse())
11512 SDNode *N = Op.getNode();
11515 SmallVector<SDValue, 8> Opnds;
11516 DenseMap<SDValue, unsigned> VecInMap;
11517 SmallVector<SDValue, 8> VecIns;
11518 EVT VT = MVT::Other;
11520 // Recognize a special case where a vector is casted into wide integer to
11522 Opnds.push_back(N->getOperand(0));
11523 Opnds.push_back(N->getOperand(1));
11525 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
11526 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
11527 // BFS traverse all OR'd operands.
11528 if (I->getOpcode() == ISD::OR) {
11529 Opnds.push_back(I->getOperand(0));
11530 Opnds.push_back(I->getOperand(1));
11531 // Re-evaluate the number of nodes to be traversed.
11532 e += 2; // 2 more nodes (LHS and RHS) are pushed.
11536 // Quit if a non-EXTRACT_VECTOR_ELT
11537 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
11540 // Quit if without a constant index.
11541 SDValue Idx = I->getOperand(1);
11542 if (!isa<ConstantSDNode>(Idx))
11545 SDValue ExtractedFromVec = I->getOperand(0);
11546 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
11547 if (M == VecInMap.end()) {
11548 VT = ExtractedFromVec.getValueType();
11549 // Quit if not 128/256-bit vector.
11550 if (!VT.is128BitVector() && !VT.is256BitVector())
11552 // Quit if not the same type.
11553 if (VecInMap.begin() != VecInMap.end() &&
11554 VT != VecInMap.begin()->first.getValueType())
11556 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
11557 VecIns.push_back(ExtractedFromVec);
11559 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
11562 assert((VT.is128BitVector() || VT.is256BitVector()) &&
11563 "Not extracted from 128-/256-bit vector.");
11565 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
11567 for (DenseMap<SDValue, unsigned>::const_iterator
11568 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
11569 // Quit if not all elements are used.
11570 if (I->second != FullMask)
11574 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
11576 // Cast all vectors into TestVT for PTEST.
11577 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
11578 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
11580 // If more than one full vectors are evaluated, OR them first before PTEST.
11581 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
11582 // Each iteration will OR 2 nodes and append the result until there is only
11583 // 1 node left, i.e. the final OR'd value of all vectors.
11584 SDValue LHS = VecIns[Slot];
11585 SDValue RHS = VecIns[Slot + 1];
11586 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
11589 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
11590 VecIns.back(), VecIns.back());
11593 /// \brief return true if \c Op has a use that doesn't just read flags.
11594 static bool hasNonFlagsUse(SDValue Op) {
11595 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
11597 SDNode *User = *UI;
11598 unsigned UOpNo = UI.getOperandNo();
11599 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
11600 // Look pass truncate.
11601 UOpNo = User->use_begin().getOperandNo();
11602 User = *User->use_begin();
11605 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
11606 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
11612 /// Emit nodes that will be selected as "test Op0,Op0", or something
11614 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
11615 SelectionDAG &DAG) const {
11616 if (Op.getValueType() == MVT::i1)
11617 // KORTEST instruction should be selected
11618 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
11619 DAG.getConstant(0, Op.getValueType()));
11621 // CF and OF aren't always set the way we want. Determine which
11622 // of these we need.
11623 bool NeedCF = false;
11624 bool NeedOF = false;
11627 case X86::COND_A: case X86::COND_AE:
11628 case X86::COND_B: case X86::COND_BE:
11631 case X86::COND_G: case X86::COND_GE:
11632 case X86::COND_L: case X86::COND_LE:
11633 case X86::COND_O: case X86::COND_NO: {
11634 // Check if we really need to set the
11635 // Overflow flag. If NoSignedWrap is present
11636 // that is not actually needed.
11637 switch (Op->getOpcode()) {
11642 const BinaryWithFlagsSDNode *BinNode =
11643 cast<BinaryWithFlagsSDNode>(Op.getNode());
11644 if (BinNode->hasNoSignedWrap())
11654 // See if we can use the EFLAGS value from the operand instead of
11655 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
11656 // we prove that the arithmetic won't overflow, we can't use OF or CF.
11657 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
11658 // Emit a CMP with 0, which is the TEST pattern.
11659 //if (Op.getValueType() == MVT::i1)
11660 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
11661 // DAG.getConstant(0, MVT::i1));
11662 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
11663 DAG.getConstant(0, Op.getValueType()));
11665 unsigned Opcode = 0;
11666 unsigned NumOperands = 0;
11668 // Truncate operations may prevent the merge of the SETCC instruction
11669 // and the arithmetic instruction before it. Attempt to truncate the operands
11670 // of the arithmetic instruction and use a reduced bit-width instruction.
11671 bool NeedTruncation = false;
11672 SDValue ArithOp = Op;
11673 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
11674 SDValue Arith = Op->getOperand(0);
11675 // Both the trunc and the arithmetic op need to have one user each.
11676 if (Arith->hasOneUse())
11677 switch (Arith.getOpcode()) {
11684 NeedTruncation = true;
11690 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
11691 // which may be the result of a CAST. We use the variable 'Op', which is the
11692 // non-casted variable when we check for possible users.
11693 switch (ArithOp.getOpcode()) {
11695 // Due to an isel shortcoming, be conservative if this add is likely to be
11696 // selected as part of a load-modify-store instruction. When the root node
11697 // in a match is a store, isel doesn't know how to remap non-chain non-flag
11698 // uses of other nodes in the match, such as the ADD in this case. This
11699 // leads to the ADD being left around and reselected, with the result being
11700 // two adds in the output. Alas, even if none our users are stores, that
11701 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
11702 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
11703 // climbing the DAG back to the root, and it doesn't seem to be worth the
11705 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
11706 UE = Op.getNode()->use_end(); UI != UE; ++UI)
11707 if (UI->getOpcode() != ISD::CopyToReg &&
11708 UI->getOpcode() != ISD::SETCC &&
11709 UI->getOpcode() != ISD::STORE)
11712 if (ConstantSDNode *C =
11713 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
11714 // An add of one will be selected as an INC.
11715 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
11716 Opcode = X86ISD::INC;
11721 // An add of negative one (subtract of one) will be selected as a DEC.
11722 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
11723 Opcode = X86ISD::DEC;
11729 // Otherwise use a regular EFLAGS-setting add.
11730 Opcode = X86ISD::ADD;
11735 // If we have a constant logical shift that's only used in a comparison
11736 // against zero turn it into an equivalent AND. This allows turning it into
11737 // a TEST instruction later.
11738 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
11739 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
11740 EVT VT = Op.getValueType();
11741 unsigned BitWidth = VT.getSizeInBits();
11742 unsigned ShAmt = Op->getConstantOperandVal(1);
11743 if (ShAmt >= BitWidth) // Avoid undefined shifts.
11745 APInt Mask = ArithOp.getOpcode() == ISD::SRL
11746 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
11747 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
11748 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
11750 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
11751 DAG.getConstant(Mask, VT));
11752 DAG.ReplaceAllUsesWith(Op, New);
11758 // If the primary and result isn't used, don't bother using X86ISD::AND,
11759 // because a TEST instruction will be better.
11760 if (!hasNonFlagsUse(Op))
11766 // Due to the ISEL shortcoming noted above, be conservative if this op is
11767 // likely to be selected as part of a load-modify-store instruction.
11768 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
11769 UE = Op.getNode()->use_end(); UI != UE; ++UI)
11770 if (UI->getOpcode() == ISD::STORE)
11773 // Otherwise use a regular EFLAGS-setting instruction.
11774 switch (ArithOp.getOpcode()) {
11775 default: llvm_unreachable("unexpected operator!");
11776 case ISD::SUB: Opcode = X86ISD::SUB; break;
11777 case ISD::XOR: Opcode = X86ISD::XOR; break;
11778 case ISD::AND: Opcode = X86ISD::AND; break;
11780 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
11781 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
11782 if (EFLAGS.getNode())
11785 Opcode = X86ISD::OR;
11799 return SDValue(Op.getNode(), 1);
11805 // If we found that truncation is beneficial, perform the truncation and
11807 if (NeedTruncation) {
11808 EVT VT = Op.getValueType();
11809 SDValue WideVal = Op->getOperand(0);
11810 EVT WideVT = WideVal.getValueType();
11811 unsigned ConvertedOp = 0;
11812 // Use a target machine opcode to prevent further DAGCombine
11813 // optimizations that may separate the arithmetic operations
11814 // from the setcc node.
11815 switch (WideVal.getOpcode()) {
11817 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
11818 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
11819 case ISD::AND: ConvertedOp = X86ISD::AND; break;
11820 case ISD::OR: ConvertedOp = X86ISD::OR; break;
11821 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
11825 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11826 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
11827 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
11828 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
11829 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
11835 // Emit a CMP with 0, which is the TEST pattern.
11836 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
11837 DAG.getConstant(0, Op.getValueType()));
11839 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11840 SmallVector<SDValue, 4> Ops;
11841 for (unsigned i = 0; i != NumOperands; ++i)
11842 Ops.push_back(Op.getOperand(i));
11844 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
11845 DAG.ReplaceAllUsesWith(Op, New);
11846 return SDValue(New.getNode(), 1);
11849 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
11851 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
11852 SDLoc dl, SelectionDAG &DAG) const {
11853 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
11854 if (C->getAPIntValue() == 0)
11855 return EmitTest(Op0, X86CC, dl, DAG);
11857 if (Op0.getValueType() == MVT::i1)
11858 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
11861 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
11862 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
11863 // Do the comparison at i32 if it's smaller, besides the Atom case.
11864 // This avoids subregister aliasing issues. Keep the smaller reference
11865 // if we're optimizing for size, however, as that'll allow better folding
11866 // of memory operations.
11867 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
11868 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
11869 AttributeSet::FunctionIndex, Attribute::MinSize) &&
11870 !Subtarget->isAtom()) {
11871 unsigned ExtendOp =
11872 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
11873 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
11874 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
11876 // Use SUB instead of CMP to enable CSE between SUB and CMP.
11877 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
11878 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
11880 return SDValue(Sub.getNode(), 1);
11882 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
11885 /// Convert a comparison if required by the subtarget.
11886 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
11887 SelectionDAG &DAG) const {
11888 // If the subtarget does not support the FUCOMI instruction, floating-point
11889 // comparisons have to be converted.
11890 if (Subtarget->hasCMov() ||
11891 Cmp.getOpcode() != X86ISD::CMP ||
11892 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
11893 !Cmp.getOperand(1).getValueType().isFloatingPoint())
11896 // The instruction selector will select an FUCOM instruction instead of
11897 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
11898 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
11899 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
11901 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
11902 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
11903 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
11904 DAG.getConstant(8, MVT::i8));
11905 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
11906 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
11909 static bool isAllOnes(SDValue V) {
11910 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
11911 return C && C->isAllOnesValue();
11914 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
11915 /// if it's possible.
11916 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
11917 SDLoc dl, SelectionDAG &DAG) const {
11918 SDValue Op0 = And.getOperand(0);
11919 SDValue Op1 = And.getOperand(1);
11920 if (Op0.getOpcode() == ISD::TRUNCATE)
11921 Op0 = Op0.getOperand(0);
11922 if (Op1.getOpcode() == ISD::TRUNCATE)
11923 Op1 = Op1.getOperand(0);
11926 if (Op1.getOpcode() == ISD::SHL)
11927 std::swap(Op0, Op1);
11928 if (Op0.getOpcode() == ISD::SHL) {
11929 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
11930 if (And00C->getZExtValue() == 1) {
11931 // If we looked past a truncate, check that it's only truncating away
11933 unsigned BitWidth = Op0.getValueSizeInBits();
11934 unsigned AndBitWidth = And.getValueSizeInBits();
11935 if (BitWidth > AndBitWidth) {
11937 DAG.computeKnownBits(Op0, Zeros, Ones);
11938 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
11942 RHS = Op0.getOperand(1);
11944 } else if (Op1.getOpcode() == ISD::Constant) {
11945 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
11946 uint64_t AndRHSVal = AndRHS->getZExtValue();
11947 SDValue AndLHS = Op0;
11949 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
11950 LHS = AndLHS.getOperand(0);
11951 RHS = AndLHS.getOperand(1);
11954 // Use BT if the immediate can't be encoded in a TEST instruction.
11955 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
11957 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
11961 if (LHS.getNode()) {
11962 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
11963 // instruction. Since the shift amount is in-range-or-undefined, we know
11964 // that doing a bittest on the i32 value is ok. We extend to i32 because
11965 // the encoding for the i16 version is larger than the i32 version.
11966 // Also promote i16 to i32 for performance / code size reason.
11967 if (LHS.getValueType() == MVT::i8 ||
11968 LHS.getValueType() == MVT::i16)
11969 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
11971 // If the operand types disagree, extend the shift amount to match. Since
11972 // BT ignores high bits (like shifts) we can use anyextend.
11973 if (LHS.getValueType() != RHS.getValueType())
11974 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
11976 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
11977 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
11978 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11979 DAG.getConstant(Cond, MVT::i8), BT);
11985 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
11987 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
11992 // SSE Condition code mapping:
12001 switch (SetCCOpcode) {
12002 default: llvm_unreachable("Unexpected SETCC condition");
12004 case ISD::SETEQ: SSECC = 0; break;
12006 case ISD::SETGT: Swap = true; // Fallthrough
12008 case ISD::SETOLT: SSECC = 1; break;
12010 case ISD::SETGE: Swap = true; // Fallthrough
12012 case ISD::SETOLE: SSECC = 2; break;
12013 case ISD::SETUO: SSECC = 3; break;
12015 case ISD::SETNE: SSECC = 4; break;
12016 case ISD::SETULE: Swap = true; // Fallthrough
12017 case ISD::SETUGE: SSECC = 5; break;
12018 case ISD::SETULT: Swap = true; // Fallthrough
12019 case ISD::SETUGT: SSECC = 6; break;
12020 case ISD::SETO: SSECC = 7; break;
12022 case ISD::SETONE: SSECC = 8; break;
12025 std::swap(Op0, Op1);
12030 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
12031 // ones, and then concatenate the result back.
12032 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
12033 MVT VT = Op.getSimpleValueType();
12035 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
12036 "Unsupported value type for operation");
12038 unsigned NumElems = VT.getVectorNumElements();
12040 SDValue CC = Op.getOperand(2);
12042 // Extract the LHS vectors
12043 SDValue LHS = Op.getOperand(0);
12044 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12045 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12047 // Extract the RHS vectors
12048 SDValue RHS = Op.getOperand(1);
12049 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
12050 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
12052 // Issue the operation on the smaller types and concatenate the result back
12053 MVT EltVT = VT.getVectorElementType();
12054 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12055 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
12056 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
12057 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
12060 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
12061 const X86Subtarget *Subtarget) {
12062 SDValue Op0 = Op.getOperand(0);
12063 SDValue Op1 = Op.getOperand(1);
12064 SDValue CC = Op.getOperand(2);
12065 MVT VT = Op.getSimpleValueType();
12068 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 32 &&
12069 Op.getValueType().getScalarType() == MVT::i1 &&
12070 "Cannot set masked compare for this operation");
12072 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
12074 bool Unsigned = false;
12077 switch (SetCCOpcode) {
12078 default: llvm_unreachable("Unexpected SETCC condition");
12079 case ISD::SETNE: SSECC = 4; break;
12080 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
12081 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
12082 case ISD::SETLT: Swap = true; //fall-through
12083 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
12084 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
12085 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
12086 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
12087 case ISD::SETULE: Unsigned = true; //fall-through
12088 case ISD::SETLE: SSECC = 2; break;
12092 std::swap(Op0, Op1);
12094 return DAG.getNode(Opc, dl, VT, Op0, Op1);
12095 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
12096 return DAG.getNode(Opc, dl, VT, Op0, Op1,
12097 DAG.getConstant(SSECC, MVT::i8));
12100 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
12101 /// operand \p Op1. If non-trivial (for example because it's not constant)
12102 /// return an empty value.
12103 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
12105 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
12109 MVT VT = Op1.getSimpleValueType();
12110 MVT EVT = VT.getVectorElementType();
12111 unsigned n = VT.getVectorNumElements();
12112 SmallVector<SDValue, 8> ULTOp1;
12114 for (unsigned i = 0; i < n; ++i) {
12115 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
12116 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
12119 // Avoid underflow.
12120 APInt Val = Elt->getAPIntValue();
12124 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
12127 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
12130 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
12131 SelectionDAG &DAG) {
12132 SDValue Op0 = Op.getOperand(0);
12133 SDValue Op1 = Op.getOperand(1);
12134 SDValue CC = Op.getOperand(2);
12135 MVT VT = Op.getSimpleValueType();
12136 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
12137 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
12142 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
12143 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
12146 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
12147 unsigned Opc = X86ISD::CMPP;
12148 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
12149 assert(VT.getVectorNumElements() <= 16);
12150 Opc = X86ISD::CMPM;
12152 // In the two special cases we can't handle, emit two comparisons.
12155 unsigned CombineOpc;
12156 if (SetCCOpcode == ISD::SETUEQ) {
12157 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
12159 assert(SetCCOpcode == ISD::SETONE);
12160 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
12163 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
12164 DAG.getConstant(CC0, MVT::i8));
12165 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
12166 DAG.getConstant(CC1, MVT::i8));
12167 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
12169 // Handle all other FP comparisons here.
12170 return DAG.getNode(Opc, dl, VT, Op0, Op1,
12171 DAG.getConstant(SSECC, MVT::i8));
12174 // Break 256-bit integer vector compare into smaller ones.
12175 if (VT.is256BitVector() && !Subtarget->hasInt256())
12176 return Lower256IntVSETCC(Op, DAG);
12178 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
12179 EVT OpVT = Op1.getValueType();
12180 if (Subtarget->hasAVX512()) {
12181 if (Op1.getValueType().is512BitVector() ||
12182 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
12183 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
12185 // In AVX-512 architecture setcc returns mask with i1 elements,
12186 // But there is no compare instruction for i8 and i16 elements.
12187 // We are not talking about 512-bit operands in this case, these
12188 // types are illegal.
12190 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
12191 OpVT.getVectorElementType().getSizeInBits() >= 8))
12192 return DAG.getNode(ISD::TRUNCATE, dl, VT,
12193 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
12196 // We are handling one of the integer comparisons here. Since SSE only has
12197 // GT and EQ comparisons for integer, swapping operands and multiple
12198 // operations may be required for some comparisons.
12200 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
12201 bool Subus = false;
12203 switch (SetCCOpcode) {
12204 default: llvm_unreachable("Unexpected SETCC condition");
12205 case ISD::SETNE: Invert = true;
12206 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
12207 case ISD::SETLT: Swap = true;
12208 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
12209 case ISD::SETGE: Swap = true;
12210 case ISD::SETLE: Opc = X86ISD::PCMPGT;
12211 Invert = true; break;
12212 case ISD::SETULT: Swap = true;
12213 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
12214 FlipSigns = true; break;
12215 case ISD::SETUGE: Swap = true;
12216 case ISD::SETULE: Opc = X86ISD::PCMPGT;
12217 FlipSigns = true; Invert = true; break;
12220 // Special case: Use min/max operations for SETULE/SETUGE
12221 MVT VET = VT.getVectorElementType();
12223 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
12224 || (Subtarget->hasSSE2() && (VET == MVT::i8));
12227 switch (SetCCOpcode) {
12229 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
12230 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
12233 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
12236 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
12237 if (!MinMax && hasSubus) {
12238 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
12240 // t = psubus Op0, Op1
12241 // pcmpeq t, <0..0>
12242 switch (SetCCOpcode) {
12244 case ISD::SETULT: {
12245 // If the comparison is against a constant we can turn this into a
12246 // setule. With psubus, setule does not require a swap. This is
12247 // beneficial because the constant in the register is no longer
12248 // destructed as the destination so it can be hoisted out of a loop.
12249 // Only do this pre-AVX since vpcmp* is no longer destructive.
12250 if (Subtarget->hasAVX())
12252 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
12253 if (ULEOp1.getNode()) {
12255 Subus = true; Invert = false; Swap = false;
12259 // Psubus is better than flip-sign because it requires no inversion.
12260 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
12261 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
12265 Opc = X86ISD::SUBUS;
12271 std::swap(Op0, Op1);
12273 // Check that the operation in question is available (most are plain SSE2,
12274 // but PCMPGTQ and PCMPEQQ have different requirements).
12275 if (VT == MVT::v2i64) {
12276 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
12277 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
12279 // First cast everything to the right type.
12280 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
12281 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
12283 // Since SSE has no unsigned integer comparisons, we need to flip the sign
12284 // bits of the inputs before performing those operations. The lower
12285 // compare is always unsigned.
12288 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
12290 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
12291 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
12292 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
12293 Sign, Zero, Sign, Zero);
12295 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
12296 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
12298 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
12299 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
12300 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
12302 // Create masks for only the low parts/high parts of the 64 bit integers.
12303 static const int MaskHi[] = { 1, 1, 3, 3 };
12304 static const int MaskLo[] = { 0, 0, 2, 2 };
12305 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
12306 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
12307 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
12309 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
12310 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
12313 Result = DAG.getNOT(dl, Result, MVT::v4i32);
12315 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
12318 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
12319 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
12320 // pcmpeqd + pshufd + pand.
12321 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
12323 // First cast everything to the right type.
12324 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
12325 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
12328 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
12330 // Make sure the lower and upper halves are both all-ones.
12331 static const int Mask[] = { 1, 0, 3, 2 };
12332 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
12333 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
12336 Result = DAG.getNOT(dl, Result, MVT::v4i32);
12338 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
12342 // Since SSE has no unsigned integer comparisons, we need to flip the sign
12343 // bits of the inputs before performing those operations.
12345 EVT EltVT = VT.getVectorElementType();
12346 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
12347 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
12348 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
12351 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
12353 // If the logical-not of the result is required, perform that now.
12355 Result = DAG.getNOT(dl, Result, VT);
12358 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
12361 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
12362 getZeroVector(VT, Subtarget, DAG, dl));
12367 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
12369 MVT VT = Op.getSimpleValueType();
12371 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
12373 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
12374 && "SetCC type must be 8-bit or 1-bit integer");
12375 SDValue Op0 = Op.getOperand(0);
12376 SDValue Op1 = Op.getOperand(1);
12378 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
12380 // Optimize to BT if possible.
12381 // Lower (X & (1 << N)) == 0 to BT(X, N).
12382 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
12383 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
12384 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
12385 Op1.getOpcode() == ISD::Constant &&
12386 cast<ConstantSDNode>(Op1)->isNullValue() &&
12387 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
12388 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
12389 if (NewSetCC.getNode())
12393 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
12395 if (Op1.getOpcode() == ISD::Constant &&
12396 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
12397 cast<ConstantSDNode>(Op1)->isNullValue()) &&
12398 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
12400 // If the input is a setcc, then reuse the input setcc or use a new one with
12401 // the inverted condition.
12402 if (Op0.getOpcode() == X86ISD::SETCC) {
12403 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
12404 bool Invert = (CC == ISD::SETNE) ^
12405 cast<ConstantSDNode>(Op1)->isNullValue();
12409 CCode = X86::GetOppositeBranchCondition(CCode);
12410 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12411 DAG.getConstant(CCode, MVT::i8),
12412 Op0.getOperand(1));
12414 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
12418 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
12419 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
12420 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
12422 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
12423 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
12426 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
12427 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
12428 if (X86CC == X86::COND_INVALID)
12431 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
12432 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
12433 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12434 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
12436 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
12440 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
12441 static bool isX86LogicalCmp(SDValue Op) {
12442 unsigned Opc = Op.getNode()->getOpcode();
12443 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
12444 Opc == X86ISD::SAHF)
12446 if (Op.getResNo() == 1 &&
12447 (Opc == X86ISD::ADD ||
12448 Opc == X86ISD::SUB ||
12449 Opc == X86ISD::ADC ||
12450 Opc == X86ISD::SBB ||
12451 Opc == X86ISD::SMUL ||
12452 Opc == X86ISD::UMUL ||
12453 Opc == X86ISD::INC ||
12454 Opc == X86ISD::DEC ||
12455 Opc == X86ISD::OR ||
12456 Opc == X86ISD::XOR ||
12457 Opc == X86ISD::AND))
12460 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
12466 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
12467 if (V.getOpcode() != ISD::TRUNCATE)
12470 SDValue VOp0 = V.getOperand(0);
12471 unsigned InBits = VOp0.getValueSizeInBits();
12472 unsigned Bits = V.getValueSizeInBits();
12473 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
12476 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
12477 bool addTest = true;
12478 SDValue Cond = Op.getOperand(0);
12479 SDValue Op1 = Op.getOperand(1);
12480 SDValue Op2 = Op.getOperand(2);
12482 EVT VT = Op1.getValueType();
12485 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
12486 // are available. Otherwise fp cmovs get lowered into a less efficient branch
12487 // sequence later on.
12488 if (Cond.getOpcode() == ISD::SETCC &&
12489 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
12490 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
12491 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
12492 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
12493 int SSECC = translateX86FSETCC(
12494 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
12497 if (Subtarget->hasAVX512()) {
12498 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
12499 DAG.getConstant(SSECC, MVT::i8));
12500 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
12502 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
12503 DAG.getConstant(SSECC, MVT::i8));
12504 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
12505 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
12506 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
12510 if (Cond.getOpcode() == ISD::SETCC) {
12511 SDValue NewCond = LowerSETCC(Cond, DAG);
12512 if (NewCond.getNode())
12516 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
12517 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
12518 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
12519 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
12520 if (Cond.getOpcode() == X86ISD::SETCC &&
12521 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
12522 isZero(Cond.getOperand(1).getOperand(1))) {
12523 SDValue Cmp = Cond.getOperand(1);
12525 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
12527 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
12528 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
12529 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
12531 SDValue CmpOp0 = Cmp.getOperand(0);
12532 // Apply further optimizations for special cases
12533 // (select (x != 0), -1, 0) -> neg & sbb
12534 // (select (x == 0), 0, -1) -> neg & sbb
12535 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
12536 if (YC->isNullValue() &&
12537 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
12538 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
12539 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
12540 DAG.getConstant(0, CmpOp0.getValueType()),
12542 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
12543 DAG.getConstant(X86::COND_B, MVT::i8),
12544 SDValue(Neg.getNode(), 1));
12548 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
12549 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
12550 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
12552 SDValue Res = // Res = 0 or -1.
12553 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
12554 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
12556 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
12557 Res = DAG.getNOT(DL, Res, Res.getValueType());
12559 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
12560 if (!N2C || !N2C->isNullValue())
12561 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
12566 // Look past (and (setcc_carry (cmp ...)), 1).
12567 if (Cond.getOpcode() == ISD::AND &&
12568 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
12569 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
12570 if (C && C->getAPIntValue() == 1)
12571 Cond = Cond.getOperand(0);
12574 // If condition flag is set by a X86ISD::CMP, then use it as the condition
12575 // setting operand in place of the X86ISD::SETCC.
12576 unsigned CondOpcode = Cond.getOpcode();
12577 if (CondOpcode == X86ISD::SETCC ||
12578 CondOpcode == X86ISD::SETCC_CARRY) {
12579 CC = Cond.getOperand(0);
12581 SDValue Cmp = Cond.getOperand(1);
12582 unsigned Opc = Cmp.getOpcode();
12583 MVT VT = Op.getSimpleValueType();
12585 bool IllegalFPCMov = false;
12586 if (VT.isFloatingPoint() && !VT.isVector() &&
12587 !isScalarFPTypeInSSEReg(VT)) // FPStack?
12588 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
12590 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
12591 Opc == X86ISD::BT) { // FIXME
12595 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
12596 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
12597 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
12598 Cond.getOperand(0).getValueType() != MVT::i8)) {
12599 SDValue LHS = Cond.getOperand(0);
12600 SDValue RHS = Cond.getOperand(1);
12601 unsigned X86Opcode;
12604 switch (CondOpcode) {
12605 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
12606 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
12607 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
12608 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
12609 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
12610 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
12611 default: llvm_unreachable("unexpected overflowing operator");
12613 if (CondOpcode == ISD::UMULO)
12614 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
12617 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
12619 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
12621 if (CondOpcode == ISD::UMULO)
12622 Cond = X86Op.getValue(2);
12624 Cond = X86Op.getValue(1);
12626 CC = DAG.getConstant(X86Cond, MVT::i8);
12631 // Look pass the truncate if the high bits are known zero.
12632 if (isTruncWithZeroHighBitsInput(Cond, DAG))
12633 Cond = Cond.getOperand(0);
12635 // We know the result of AND is compared against zero. Try to match
12637 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
12638 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
12639 if (NewSetCC.getNode()) {
12640 CC = NewSetCC.getOperand(0);
12641 Cond = NewSetCC.getOperand(1);
12648 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
12649 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
12652 // a < b ? -1 : 0 -> RES = ~setcc_carry
12653 // a < b ? 0 : -1 -> RES = setcc_carry
12654 // a >= b ? -1 : 0 -> RES = setcc_carry
12655 // a >= b ? 0 : -1 -> RES = ~setcc_carry
12656 if (Cond.getOpcode() == X86ISD::SUB) {
12657 Cond = ConvertCmpIfNecessary(Cond, DAG);
12658 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
12660 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
12661 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
12662 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
12663 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
12664 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
12665 return DAG.getNOT(DL, Res, Res.getValueType());
12670 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
12671 // widen the cmov and push the truncate through. This avoids introducing a new
12672 // branch during isel and doesn't add any extensions.
12673 if (Op.getValueType() == MVT::i8 &&
12674 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
12675 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
12676 if (T1.getValueType() == T2.getValueType() &&
12677 // Blacklist CopyFromReg to avoid partial register stalls.
12678 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
12679 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
12680 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
12681 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
12685 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
12686 // condition is true.
12687 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
12688 SDValue Ops[] = { Op2, Op1, CC, Cond };
12689 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
12692 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
12693 MVT VT = Op->getSimpleValueType(0);
12694 SDValue In = Op->getOperand(0);
12695 MVT InVT = In.getSimpleValueType();
12698 unsigned int NumElts = VT.getVectorNumElements();
12699 if (NumElts != 8 && NumElts != 16)
12702 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12703 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
12705 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12706 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12708 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
12709 Constant *C = ConstantInt::get(*DAG.getContext(),
12710 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
12712 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
12713 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
12714 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
12715 MachinePointerInfo::getConstantPool(),
12716 false, false, false, Alignment);
12717 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
12718 if (VT.is512BitVector())
12720 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
12723 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12724 SelectionDAG &DAG) {
12725 MVT VT = Op->getSimpleValueType(0);
12726 SDValue In = Op->getOperand(0);
12727 MVT InVT = In.getSimpleValueType();
12730 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
12731 return LowerSIGN_EXTEND_AVX512(Op, DAG);
12733 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
12734 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
12735 (VT != MVT::v16i16 || InVT != MVT::v16i8))
12738 if (Subtarget->hasInt256())
12739 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
12741 // Optimize vectors in AVX mode
12742 // Sign extend v8i16 to v8i32 and
12745 // Divide input vector into two parts
12746 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
12747 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
12748 // concat the vectors to original VT
12750 unsigned NumElems = InVT.getVectorNumElements();
12751 SDValue Undef = DAG.getUNDEF(InVT);
12753 SmallVector<int,8> ShufMask1(NumElems, -1);
12754 for (unsigned i = 0; i != NumElems/2; ++i)
12757 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
12759 SmallVector<int,8> ShufMask2(NumElems, -1);
12760 for (unsigned i = 0; i != NumElems/2; ++i)
12761 ShufMask2[i] = i + NumElems/2;
12763 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
12765 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
12766 VT.getVectorNumElements()/2);
12768 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
12769 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
12771 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12774 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
12775 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
12776 // from the AND / OR.
12777 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
12778 Opc = Op.getOpcode();
12779 if (Opc != ISD::OR && Opc != ISD::AND)
12781 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
12782 Op.getOperand(0).hasOneUse() &&
12783 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
12784 Op.getOperand(1).hasOneUse());
12787 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
12788 // 1 and that the SETCC node has a single use.
12789 static bool isXor1OfSetCC(SDValue Op) {
12790 if (Op.getOpcode() != ISD::XOR)
12792 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
12793 if (N1C && N1C->getAPIntValue() == 1) {
12794 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
12795 Op.getOperand(0).hasOneUse();
12800 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
12801 bool addTest = true;
12802 SDValue Chain = Op.getOperand(0);
12803 SDValue Cond = Op.getOperand(1);
12804 SDValue Dest = Op.getOperand(2);
12807 bool Inverted = false;
12809 if (Cond.getOpcode() == ISD::SETCC) {
12810 // Check for setcc([su]{add,sub,mul}o == 0).
12811 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
12812 isa<ConstantSDNode>(Cond.getOperand(1)) &&
12813 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
12814 Cond.getOperand(0).getResNo() == 1 &&
12815 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
12816 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
12817 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
12818 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
12819 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
12820 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
12822 Cond = Cond.getOperand(0);
12824 SDValue NewCond = LowerSETCC(Cond, DAG);
12825 if (NewCond.getNode())
12830 // FIXME: LowerXALUO doesn't handle these!!
12831 else if (Cond.getOpcode() == X86ISD::ADD ||
12832 Cond.getOpcode() == X86ISD::SUB ||
12833 Cond.getOpcode() == X86ISD::SMUL ||
12834 Cond.getOpcode() == X86ISD::UMUL)
12835 Cond = LowerXALUO(Cond, DAG);
12838 // Look pass (and (setcc_carry (cmp ...)), 1).
12839 if (Cond.getOpcode() == ISD::AND &&
12840 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
12841 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
12842 if (C && C->getAPIntValue() == 1)
12843 Cond = Cond.getOperand(0);
12846 // If condition flag is set by a X86ISD::CMP, then use it as the condition
12847 // setting operand in place of the X86ISD::SETCC.
12848 unsigned CondOpcode = Cond.getOpcode();
12849 if (CondOpcode == X86ISD::SETCC ||
12850 CondOpcode == X86ISD::SETCC_CARRY) {
12851 CC = Cond.getOperand(0);
12853 SDValue Cmp = Cond.getOperand(1);
12854 unsigned Opc = Cmp.getOpcode();
12855 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
12856 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
12860 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
12864 // These can only come from an arithmetic instruction with overflow,
12865 // e.g. SADDO, UADDO.
12866 Cond = Cond.getNode()->getOperand(1);
12872 CondOpcode = Cond.getOpcode();
12873 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
12874 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
12875 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
12876 Cond.getOperand(0).getValueType() != MVT::i8)) {
12877 SDValue LHS = Cond.getOperand(0);
12878 SDValue RHS = Cond.getOperand(1);
12879 unsigned X86Opcode;
12882 // Keep this in sync with LowerXALUO, otherwise we might create redundant
12883 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
12885 switch (CondOpcode) {
12886 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
12888 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
12890 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
12893 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
12894 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
12896 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
12898 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
12901 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
12902 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
12903 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
12904 default: llvm_unreachable("unexpected overflowing operator");
12907 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
12908 if (CondOpcode == ISD::UMULO)
12909 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
12912 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
12914 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
12916 if (CondOpcode == ISD::UMULO)
12917 Cond = X86Op.getValue(2);
12919 Cond = X86Op.getValue(1);
12921 CC = DAG.getConstant(X86Cond, MVT::i8);
12925 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
12926 SDValue Cmp = Cond.getOperand(0).getOperand(1);
12927 if (CondOpc == ISD::OR) {
12928 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
12929 // two branches instead of an explicit OR instruction with a
12931 if (Cmp == Cond.getOperand(1).getOperand(1) &&
12932 isX86LogicalCmp(Cmp)) {
12933 CC = Cond.getOperand(0).getOperand(0);
12934 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
12935 Chain, Dest, CC, Cmp);
12936 CC = Cond.getOperand(1).getOperand(0);
12940 } else { // ISD::AND
12941 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
12942 // two branches instead of an explicit AND instruction with a
12943 // separate test. However, we only do this if this block doesn't
12944 // have a fall-through edge, because this requires an explicit
12945 // jmp when the condition is false.
12946 if (Cmp == Cond.getOperand(1).getOperand(1) &&
12947 isX86LogicalCmp(Cmp) &&
12948 Op.getNode()->hasOneUse()) {
12949 X86::CondCode CCode =
12950 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
12951 CCode = X86::GetOppositeBranchCondition(CCode);
12952 CC = DAG.getConstant(CCode, MVT::i8);
12953 SDNode *User = *Op.getNode()->use_begin();
12954 // Look for an unconditional branch following this conditional branch.
12955 // We need this because we need to reverse the successors in order
12956 // to implement FCMP_OEQ.
12957 if (User->getOpcode() == ISD::BR) {
12958 SDValue FalseBB = User->getOperand(1);
12960 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
12961 assert(NewBR == User);
12965 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
12966 Chain, Dest, CC, Cmp);
12967 X86::CondCode CCode =
12968 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
12969 CCode = X86::GetOppositeBranchCondition(CCode);
12970 CC = DAG.getConstant(CCode, MVT::i8);
12976 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
12977 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
12978 // It should be transformed during dag combiner except when the condition
12979 // is set by a arithmetics with overflow node.
12980 X86::CondCode CCode =
12981 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
12982 CCode = X86::GetOppositeBranchCondition(CCode);
12983 CC = DAG.getConstant(CCode, MVT::i8);
12984 Cond = Cond.getOperand(0).getOperand(1);
12986 } else if (Cond.getOpcode() == ISD::SETCC &&
12987 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
12988 // For FCMP_OEQ, we can emit
12989 // two branches instead of an explicit AND instruction with a
12990 // separate test. However, we only do this if this block doesn't
12991 // have a fall-through edge, because this requires an explicit
12992 // jmp when the condition is false.
12993 if (Op.getNode()->hasOneUse()) {
12994 SDNode *User = *Op.getNode()->use_begin();
12995 // Look for an unconditional branch following this conditional branch.
12996 // We need this because we need to reverse the successors in order
12997 // to implement FCMP_OEQ.
12998 if (User->getOpcode() == ISD::BR) {
12999 SDValue FalseBB = User->getOperand(1);
13001 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13002 assert(NewBR == User);
13006 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13007 Cond.getOperand(0), Cond.getOperand(1));
13008 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13009 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13010 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13011 Chain, Dest, CC, Cmp);
13012 CC = DAG.getConstant(X86::COND_P, MVT::i8);
13017 } else if (Cond.getOpcode() == ISD::SETCC &&
13018 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
13019 // For FCMP_UNE, we can emit
13020 // two branches instead of an explicit AND instruction with a
13021 // separate test. However, we only do this if this block doesn't
13022 // have a fall-through edge, because this requires an explicit
13023 // jmp when the condition is false.
13024 if (Op.getNode()->hasOneUse()) {
13025 SDNode *User = *Op.getNode()->use_begin();
13026 // Look for an unconditional branch following this conditional branch.
13027 // We need this because we need to reverse the successors in order
13028 // to implement FCMP_UNE.
13029 if (User->getOpcode() == ISD::BR) {
13030 SDValue FalseBB = User->getOperand(1);
13032 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13033 assert(NewBR == User);
13036 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13037 Cond.getOperand(0), Cond.getOperand(1));
13038 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13039 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13040 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13041 Chain, Dest, CC, Cmp);
13042 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
13052 // Look pass the truncate if the high bits are known zero.
13053 if (isTruncWithZeroHighBitsInput(Cond, DAG))
13054 Cond = Cond.getOperand(0);
13056 // We know the result of AND is compared against zero. Try to match
13058 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
13059 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
13060 if (NewSetCC.getNode()) {
13061 CC = NewSetCC.getOperand(0);
13062 Cond = NewSetCC.getOperand(1);
13069 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
13070 CC = DAG.getConstant(X86Cond, MVT::i8);
13071 Cond = EmitTest(Cond, X86Cond, dl, DAG);
13073 Cond = ConvertCmpIfNecessary(Cond, DAG);
13074 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13075 Chain, Dest, CC, Cond);
13078 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
13079 // Calls to _alloca is needed to probe the stack when allocating more than 4k
13080 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
13081 // that the guard pages used by the OS virtual memory manager are allocated in
13082 // correct sequence.
13084 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
13085 SelectionDAG &DAG) const {
13086 MachineFunction &MF = DAG.getMachineFunction();
13087 bool SplitStack = MF.shouldSplitStack();
13088 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
13093 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13094 SDNode* Node = Op.getNode();
13096 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
13097 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
13098 " not tell us which reg is the stack pointer!");
13099 EVT VT = Node->getValueType(0);
13100 SDValue Tmp1 = SDValue(Node, 0);
13101 SDValue Tmp2 = SDValue(Node, 1);
13102 SDValue Tmp3 = Node->getOperand(2);
13103 SDValue Chain = Tmp1.getOperand(0);
13105 // Chain the dynamic stack allocation so that it doesn't modify the stack
13106 // pointer when other instructions are using the stack.
13107 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
13110 SDValue Size = Tmp2.getOperand(1);
13111 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
13112 Chain = SP.getValue(1);
13113 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
13114 const TargetFrameLowering &TFI = *DAG.getTarget().getFrameLowering();
13115 unsigned StackAlign = TFI.getStackAlignment();
13116 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
13117 if (Align > StackAlign)
13118 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
13119 DAG.getConstant(-(uint64_t)Align, VT));
13120 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
13122 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
13123 DAG.getIntPtrConstant(0, true), SDValue(),
13126 SDValue Ops[2] = { Tmp1, Tmp2 };
13127 return DAG.getMergeValues(Ops, dl);
13131 SDValue Chain = Op.getOperand(0);
13132 SDValue Size = Op.getOperand(1);
13133 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
13134 EVT VT = Op.getNode()->getValueType(0);
13136 bool Is64Bit = Subtarget->is64Bit();
13137 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
13140 MachineRegisterInfo &MRI = MF.getRegInfo();
13143 // The 64 bit implementation of segmented stacks needs to clobber both r10
13144 // r11. This makes it impossible to use it along with nested parameters.
13145 const Function *F = MF.getFunction();
13147 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
13149 if (I->hasNestAttr())
13150 report_fatal_error("Cannot use segmented stacks with functions that "
13151 "have nested arguments.");
13154 const TargetRegisterClass *AddrRegClass =
13155 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
13156 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
13157 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
13158 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
13159 DAG.getRegister(Vreg, SPTy));
13160 SDValue Ops1[2] = { Value, Chain };
13161 return DAG.getMergeValues(Ops1, dl);
13164 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
13166 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
13167 Flag = Chain.getValue(1);
13168 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13170 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
13172 const X86RegisterInfo *RegInfo =
13173 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
13174 unsigned SPReg = RegInfo->getStackRegister();
13175 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
13176 Chain = SP.getValue(1);
13179 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
13180 DAG.getConstant(-(uint64_t)Align, VT));
13181 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
13184 SDValue Ops1[2] = { SP, Chain };
13185 return DAG.getMergeValues(Ops1, dl);
13189 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
13190 MachineFunction &MF = DAG.getMachineFunction();
13191 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
13193 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
13196 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
13197 // vastart just stores the address of the VarArgsFrameIndex slot into the
13198 // memory location argument.
13199 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
13201 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
13202 MachinePointerInfo(SV), false, false, 0);
13206 // gp_offset (0 - 6 * 8)
13207 // fp_offset (48 - 48 + 8 * 16)
13208 // overflow_arg_area (point to parameters coming in memory).
13210 SmallVector<SDValue, 8> MemOps;
13211 SDValue FIN = Op.getOperand(1);
13213 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
13214 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
13216 FIN, MachinePointerInfo(SV), false, false, 0);
13217 MemOps.push_back(Store);
13220 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13221 FIN, DAG.getIntPtrConstant(4));
13222 Store = DAG.getStore(Op.getOperand(0), DL,
13223 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
13225 FIN, MachinePointerInfo(SV, 4), false, false, 0);
13226 MemOps.push_back(Store);
13228 // Store ptr to overflow_arg_area
13229 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13230 FIN, DAG.getIntPtrConstant(4));
13231 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
13233 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
13234 MachinePointerInfo(SV, 8),
13236 MemOps.push_back(Store);
13238 // Store ptr to reg_save_area.
13239 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13240 FIN, DAG.getIntPtrConstant(8));
13241 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
13243 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
13244 MachinePointerInfo(SV, 16), false, false, 0);
13245 MemOps.push_back(Store);
13246 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
13249 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
13250 assert(Subtarget->is64Bit() &&
13251 "LowerVAARG only handles 64-bit va_arg!");
13252 assert((Subtarget->isTargetLinux() ||
13253 Subtarget->isTargetDarwin()) &&
13254 "Unhandled target in LowerVAARG");
13255 assert(Op.getNode()->getNumOperands() == 4);
13256 SDValue Chain = Op.getOperand(0);
13257 SDValue SrcPtr = Op.getOperand(1);
13258 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
13259 unsigned Align = Op.getConstantOperandVal(3);
13262 EVT ArgVT = Op.getNode()->getValueType(0);
13263 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
13264 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
13267 // Decide which area this value should be read from.
13268 // TODO: Implement the AMD64 ABI in its entirety. This simple
13269 // selection mechanism works only for the basic types.
13270 if (ArgVT == MVT::f80) {
13271 llvm_unreachable("va_arg for f80 not yet implemented");
13272 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
13273 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
13274 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
13275 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
13277 llvm_unreachable("Unhandled argument type in LowerVAARG");
13280 if (ArgMode == 2) {
13281 // Sanity Check: Make sure using fp_offset makes sense.
13282 assert(!DAG.getTarget().Options.UseSoftFloat &&
13283 !(DAG.getMachineFunction()
13284 .getFunction()->getAttributes()
13285 .hasAttribute(AttributeSet::FunctionIndex,
13286 Attribute::NoImplicitFloat)) &&
13287 Subtarget->hasSSE1());
13290 // Insert VAARG_64 node into the DAG
13291 // VAARG_64 returns two values: Variable Argument Address, Chain
13292 SmallVector<SDValue, 11> InstOps;
13293 InstOps.push_back(Chain);
13294 InstOps.push_back(SrcPtr);
13295 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
13296 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
13297 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
13298 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
13299 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
13300 VTs, InstOps, MVT::i64,
13301 MachinePointerInfo(SV),
13303 /*Volatile=*/false,
13305 /*WriteMem=*/true);
13306 Chain = VAARG.getValue(1);
13308 // Load the next argument and return it
13309 return DAG.getLoad(ArgVT, dl,
13312 MachinePointerInfo(),
13313 false, false, false, 0);
13316 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
13317 SelectionDAG &DAG) {
13318 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
13319 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
13320 SDValue Chain = Op.getOperand(0);
13321 SDValue DstPtr = Op.getOperand(1);
13322 SDValue SrcPtr = Op.getOperand(2);
13323 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
13324 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
13327 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
13328 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
13330 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
13333 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
13334 // amount is a constant. Takes immediate version of shift as input.
13335 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
13336 SDValue SrcOp, uint64_t ShiftAmt,
13337 SelectionDAG &DAG) {
13338 MVT ElementType = VT.getVectorElementType();
13340 // Fold this packed shift into its first operand if ShiftAmt is 0.
13344 // Check for ShiftAmt >= element width
13345 if (ShiftAmt >= ElementType.getSizeInBits()) {
13346 if (Opc == X86ISD::VSRAI)
13347 ShiftAmt = ElementType.getSizeInBits() - 1;
13349 return DAG.getConstant(0, VT);
13352 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
13353 && "Unknown target vector shift-by-constant node");
13355 // Fold this packed vector shift into a build vector if SrcOp is a
13356 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
13357 if (VT == SrcOp.getSimpleValueType() &&
13358 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
13359 SmallVector<SDValue, 8> Elts;
13360 unsigned NumElts = SrcOp->getNumOperands();
13361 ConstantSDNode *ND;
13364 default: llvm_unreachable(nullptr);
13365 case X86ISD::VSHLI:
13366 for (unsigned i=0; i!=NumElts; ++i) {
13367 SDValue CurrentOp = SrcOp->getOperand(i);
13368 if (CurrentOp->getOpcode() == ISD::UNDEF) {
13369 Elts.push_back(CurrentOp);
13372 ND = cast<ConstantSDNode>(CurrentOp);
13373 const APInt &C = ND->getAPIntValue();
13374 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
13377 case X86ISD::VSRLI:
13378 for (unsigned i=0; i!=NumElts; ++i) {
13379 SDValue CurrentOp = SrcOp->getOperand(i);
13380 if (CurrentOp->getOpcode() == ISD::UNDEF) {
13381 Elts.push_back(CurrentOp);
13384 ND = cast<ConstantSDNode>(CurrentOp);
13385 const APInt &C = ND->getAPIntValue();
13386 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
13389 case X86ISD::VSRAI:
13390 for (unsigned i=0; i!=NumElts; ++i) {
13391 SDValue CurrentOp = SrcOp->getOperand(i);
13392 if (CurrentOp->getOpcode() == ISD::UNDEF) {
13393 Elts.push_back(CurrentOp);
13396 ND = cast<ConstantSDNode>(CurrentOp);
13397 const APInt &C = ND->getAPIntValue();
13398 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
13403 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
13406 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
13409 // getTargetVShiftNode - Handle vector element shifts where the shift amount
13410 // may or may not be a constant. Takes immediate version of shift as input.
13411 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
13412 SDValue SrcOp, SDValue ShAmt,
13413 SelectionDAG &DAG) {
13414 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
13416 // Catch shift-by-constant.
13417 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
13418 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
13419 CShAmt->getZExtValue(), DAG);
13421 // Change opcode to non-immediate version
13423 default: llvm_unreachable("Unknown target vector shift node");
13424 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
13425 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
13426 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
13429 // Need to build a vector containing shift amount
13430 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
13433 ShOps[1] = DAG.getConstant(0, MVT::i32);
13434 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
13435 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
13437 // The return type has to be a 128-bit type with the same element
13438 // type as the input type.
13439 MVT EltVT = VT.getVectorElementType();
13440 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
13442 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
13443 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
13446 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
13448 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
13450 default: return SDValue(); // Don't custom lower most intrinsics.
13451 // Comparison intrinsics.
13452 case Intrinsic::x86_sse_comieq_ss:
13453 case Intrinsic::x86_sse_comilt_ss:
13454 case Intrinsic::x86_sse_comile_ss:
13455 case Intrinsic::x86_sse_comigt_ss:
13456 case Intrinsic::x86_sse_comige_ss:
13457 case Intrinsic::x86_sse_comineq_ss:
13458 case Intrinsic::x86_sse_ucomieq_ss:
13459 case Intrinsic::x86_sse_ucomilt_ss:
13460 case Intrinsic::x86_sse_ucomile_ss:
13461 case Intrinsic::x86_sse_ucomigt_ss:
13462 case Intrinsic::x86_sse_ucomige_ss:
13463 case Intrinsic::x86_sse_ucomineq_ss:
13464 case Intrinsic::x86_sse2_comieq_sd:
13465 case Intrinsic::x86_sse2_comilt_sd:
13466 case Intrinsic::x86_sse2_comile_sd:
13467 case Intrinsic::x86_sse2_comigt_sd:
13468 case Intrinsic::x86_sse2_comige_sd:
13469 case Intrinsic::x86_sse2_comineq_sd:
13470 case Intrinsic::x86_sse2_ucomieq_sd:
13471 case Intrinsic::x86_sse2_ucomilt_sd:
13472 case Intrinsic::x86_sse2_ucomile_sd:
13473 case Intrinsic::x86_sse2_ucomigt_sd:
13474 case Intrinsic::x86_sse2_ucomige_sd:
13475 case Intrinsic::x86_sse2_ucomineq_sd: {
13479 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
13480 case Intrinsic::x86_sse_comieq_ss:
13481 case Intrinsic::x86_sse2_comieq_sd:
13482 Opc = X86ISD::COMI;
13485 case Intrinsic::x86_sse_comilt_ss:
13486 case Intrinsic::x86_sse2_comilt_sd:
13487 Opc = X86ISD::COMI;
13490 case Intrinsic::x86_sse_comile_ss:
13491 case Intrinsic::x86_sse2_comile_sd:
13492 Opc = X86ISD::COMI;
13495 case Intrinsic::x86_sse_comigt_ss:
13496 case Intrinsic::x86_sse2_comigt_sd:
13497 Opc = X86ISD::COMI;
13500 case Intrinsic::x86_sse_comige_ss:
13501 case Intrinsic::x86_sse2_comige_sd:
13502 Opc = X86ISD::COMI;
13505 case Intrinsic::x86_sse_comineq_ss:
13506 case Intrinsic::x86_sse2_comineq_sd:
13507 Opc = X86ISD::COMI;
13510 case Intrinsic::x86_sse_ucomieq_ss:
13511 case Intrinsic::x86_sse2_ucomieq_sd:
13512 Opc = X86ISD::UCOMI;
13515 case Intrinsic::x86_sse_ucomilt_ss:
13516 case Intrinsic::x86_sse2_ucomilt_sd:
13517 Opc = X86ISD::UCOMI;
13520 case Intrinsic::x86_sse_ucomile_ss:
13521 case Intrinsic::x86_sse2_ucomile_sd:
13522 Opc = X86ISD::UCOMI;
13525 case Intrinsic::x86_sse_ucomigt_ss:
13526 case Intrinsic::x86_sse2_ucomigt_sd:
13527 Opc = X86ISD::UCOMI;
13530 case Intrinsic::x86_sse_ucomige_ss:
13531 case Intrinsic::x86_sse2_ucomige_sd:
13532 Opc = X86ISD::UCOMI;
13535 case Intrinsic::x86_sse_ucomineq_ss:
13536 case Intrinsic::x86_sse2_ucomineq_sd:
13537 Opc = X86ISD::UCOMI;
13542 SDValue LHS = Op.getOperand(1);
13543 SDValue RHS = Op.getOperand(2);
13544 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
13545 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
13546 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
13547 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13548 DAG.getConstant(X86CC, MVT::i8), Cond);
13549 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
13552 // Arithmetic intrinsics.
13553 case Intrinsic::x86_sse2_pmulu_dq:
13554 case Intrinsic::x86_avx2_pmulu_dq:
13555 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
13556 Op.getOperand(1), Op.getOperand(2));
13558 case Intrinsic::x86_sse41_pmuldq:
13559 case Intrinsic::x86_avx2_pmul_dq:
13560 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
13561 Op.getOperand(1), Op.getOperand(2));
13563 case Intrinsic::x86_sse2_pmulhu_w:
13564 case Intrinsic::x86_avx2_pmulhu_w:
13565 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
13566 Op.getOperand(1), Op.getOperand(2));
13568 case Intrinsic::x86_sse2_pmulh_w:
13569 case Intrinsic::x86_avx2_pmulh_w:
13570 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
13571 Op.getOperand(1), Op.getOperand(2));
13573 // SSE2/AVX2 sub with unsigned saturation intrinsics
13574 case Intrinsic::x86_sse2_psubus_b:
13575 case Intrinsic::x86_sse2_psubus_w:
13576 case Intrinsic::x86_avx2_psubus_b:
13577 case Intrinsic::x86_avx2_psubus_w:
13578 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
13579 Op.getOperand(1), Op.getOperand(2));
13581 // SSE3/AVX horizontal add/sub intrinsics
13582 case Intrinsic::x86_sse3_hadd_ps:
13583 case Intrinsic::x86_sse3_hadd_pd:
13584 case Intrinsic::x86_avx_hadd_ps_256:
13585 case Intrinsic::x86_avx_hadd_pd_256:
13586 case Intrinsic::x86_sse3_hsub_ps:
13587 case Intrinsic::x86_sse3_hsub_pd:
13588 case Intrinsic::x86_avx_hsub_ps_256:
13589 case Intrinsic::x86_avx_hsub_pd_256:
13590 case Intrinsic::x86_ssse3_phadd_w_128:
13591 case Intrinsic::x86_ssse3_phadd_d_128:
13592 case Intrinsic::x86_avx2_phadd_w:
13593 case Intrinsic::x86_avx2_phadd_d:
13594 case Intrinsic::x86_ssse3_phsub_w_128:
13595 case Intrinsic::x86_ssse3_phsub_d_128:
13596 case Intrinsic::x86_avx2_phsub_w:
13597 case Intrinsic::x86_avx2_phsub_d: {
13600 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
13601 case Intrinsic::x86_sse3_hadd_ps:
13602 case Intrinsic::x86_sse3_hadd_pd:
13603 case Intrinsic::x86_avx_hadd_ps_256:
13604 case Intrinsic::x86_avx_hadd_pd_256:
13605 Opcode = X86ISD::FHADD;
13607 case Intrinsic::x86_sse3_hsub_ps:
13608 case Intrinsic::x86_sse3_hsub_pd:
13609 case Intrinsic::x86_avx_hsub_ps_256:
13610 case Intrinsic::x86_avx_hsub_pd_256:
13611 Opcode = X86ISD::FHSUB;
13613 case Intrinsic::x86_ssse3_phadd_w_128:
13614 case Intrinsic::x86_ssse3_phadd_d_128:
13615 case Intrinsic::x86_avx2_phadd_w:
13616 case Intrinsic::x86_avx2_phadd_d:
13617 Opcode = X86ISD::HADD;
13619 case Intrinsic::x86_ssse3_phsub_w_128:
13620 case Intrinsic::x86_ssse3_phsub_d_128:
13621 case Intrinsic::x86_avx2_phsub_w:
13622 case Intrinsic::x86_avx2_phsub_d:
13623 Opcode = X86ISD::HSUB;
13626 return DAG.getNode(Opcode, dl, Op.getValueType(),
13627 Op.getOperand(1), Op.getOperand(2));
13630 // SSE2/SSE41/AVX2 integer max/min intrinsics.
13631 case Intrinsic::x86_sse2_pmaxu_b:
13632 case Intrinsic::x86_sse41_pmaxuw:
13633 case Intrinsic::x86_sse41_pmaxud:
13634 case Intrinsic::x86_avx2_pmaxu_b:
13635 case Intrinsic::x86_avx2_pmaxu_w:
13636 case Intrinsic::x86_avx2_pmaxu_d:
13637 case Intrinsic::x86_sse2_pminu_b:
13638 case Intrinsic::x86_sse41_pminuw:
13639 case Intrinsic::x86_sse41_pminud:
13640 case Intrinsic::x86_avx2_pminu_b:
13641 case Intrinsic::x86_avx2_pminu_w:
13642 case Intrinsic::x86_avx2_pminu_d:
13643 case Intrinsic::x86_sse41_pmaxsb:
13644 case Intrinsic::x86_sse2_pmaxs_w:
13645 case Intrinsic::x86_sse41_pmaxsd:
13646 case Intrinsic::x86_avx2_pmaxs_b:
13647 case Intrinsic::x86_avx2_pmaxs_w:
13648 case Intrinsic::x86_avx2_pmaxs_d:
13649 case Intrinsic::x86_sse41_pminsb:
13650 case Intrinsic::x86_sse2_pmins_w:
13651 case Intrinsic::x86_sse41_pminsd:
13652 case Intrinsic::x86_avx2_pmins_b:
13653 case Intrinsic::x86_avx2_pmins_w:
13654 case Intrinsic::x86_avx2_pmins_d: {
13657 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
13658 case Intrinsic::x86_sse2_pmaxu_b:
13659 case Intrinsic::x86_sse41_pmaxuw:
13660 case Intrinsic::x86_sse41_pmaxud:
13661 case Intrinsic::x86_avx2_pmaxu_b:
13662 case Intrinsic::x86_avx2_pmaxu_w:
13663 case Intrinsic::x86_avx2_pmaxu_d:
13664 Opcode = X86ISD::UMAX;
13666 case Intrinsic::x86_sse2_pminu_b:
13667 case Intrinsic::x86_sse41_pminuw:
13668 case Intrinsic::x86_sse41_pminud:
13669 case Intrinsic::x86_avx2_pminu_b:
13670 case Intrinsic::x86_avx2_pminu_w:
13671 case Intrinsic::x86_avx2_pminu_d:
13672 Opcode = X86ISD::UMIN;
13674 case Intrinsic::x86_sse41_pmaxsb:
13675 case Intrinsic::x86_sse2_pmaxs_w:
13676 case Intrinsic::x86_sse41_pmaxsd:
13677 case Intrinsic::x86_avx2_pmaxs_b:
13678 case Intrinsic::x86_avx2_pmaxs_w:
13679 case Intrinsic::x86_avx2_pmaxs_d:
13680 Opcode = X86ISD::SMAX;
13682 case Intrinsic::x86_sse41_pminsb:
13683 case Intrinsic::x86_sse2_pmins_w:
13684 case Intrinsic::x86_sse41_pminsd:
13685 case Intrinsic::x86_avx2_pmins_b:
13686 case Intrinsic::x86_avx2_pmins_w:
13687 case Intrinsic::x86_avx2_pmins_d:
13688 Opcode = X86ISD::SMIN;
13691 return DAG.getNode(Opcode, dl, Op.getValueType(),
13692 Op.getOperand(1), Op.getOperand(2));
13695 // SSE/SSE2/AVX floating point max/min intrinsics.
13696 case Intrinsic::x86_sse_max_ps:
13697 case Intrinsic::x86_sse2_max_pd:
13698 case Intrinsic::x86_avx_max_ps_256:
13699 case Intrinsic::x86_avx_max_pd_256:
13700 case Intrinsic::x86_sse_min_ps:
13701 case Intrinsic::x86_sse2_min_pd:
13702 case Intrinsic::x86_avx_min_ps_256:
13703 case Intrinsic::x86_avx_min_pd_256: {
13706 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
13707 case Intrinsic::x86_sse_max_ps:
13708 case Intrinsic::x86_sse2_max_pd:
13709 case Intrinsic::x86_avx_max_ps_256:
13710 case Intrinsic::x86_avx_max_pd_256:
13711 Opcode = X86ISD::FMAX;
13713 case Intrinsic::x86_sse_min_ps:
13714 case Intrinsic::x86_sse2_min_pd:
13715 case Intrinsic::x86_avx_min_ps_256:
13716 case Intrinsic::x86_avx_min_pd_256:
13717 Opcode = X86ISD::FMIN;
13720 return DAG.getNode(Opcode, dl, Op.getValueType(),
13721 Op.getOperand(1), Op.getOperand(2));
13724 // AVX2 variable shift intrinsics
13725 case Intrinsic::x86_avx2_psllv_d:
13726 case Intrinsic::x86_avx2_psllv_q:
13727 case Intrinsic::x86_avx2_psllv_d_256:
13728 case Intrinsic::x86_avx2_psllv_q_256:
13729 case Intrinsic::x86_avx2_psrlv_d:
13730 case Intrinsic::x86_avx2_psrlv_q:
13731 case Intrinsic::x86_avx2_psrlv_d_256:
13732 case Intrinsic::x86_avx2_psrlv_q_256:
13733 case Intrinsic::x86_avx2_psrav_d:
13734 case Intrinsic::x86_avx2_psrav_d_256: {
13737 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
13738 case Intrinsic::x86_avx2_psllv_d:
13739 case Intrinsic::x86_avx2_psllv_q:
13740 case Intrinsic::x86_avx2_psllv_d_256:
13741 case Intrinsic::x86_avx2_psllv_q_256:
13744 case Intrinsic::x86_avx2_psrlv_d:
13745 case Intrinsic::x86_avx2_psrlv_q:
13746 case Intrinsic::x86_avx2_psrlv_d_256:
13747 case Intrinsic::x86_avx2_psrlv_q_256:
13750 case Intrinsic::x86_avx2_psrav_d:
13751 case Intrinsic::x86_avx2_psrav_d_256:
13755 return DAG.getNode(Opcode, dl, Op.getValueType(),
13756 Op.getOperand(1), Op.getOperand(2));
13759 case Intrinsic::x86_sse2_packssdw_128:
13760 case Intrinsic::x86_sse2_packsswb_128:
13761 case Intrinsic::x86_avx2_packssdw:
13762 case Intrinsic::x86_avx2_packsswb:
13763 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
13764 Op.getOperand(1), Op.getOperand(2));
13766 case Intrinsic::x86_sse2_packuswb_128:
13767 case Intrinsic::x86_sse41_packusdw:
13768 case Intrinsic::x86_avx2_packuswb:
13769 case Intrinsic::x86_avx2_packusdw:
13770 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
13771 Op.getOperand(1), Op.getOperand(2));
13773 case Intrinsic::x86_ssse3_pshuf_b_128:
13774 case Intrinsic::x86_avx2_pshuf_b:
13775 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
13776 Op.getOperand(1), Op.getOperand(2));
13778 case Intrinsic::x86_sse2_pshuf_d:
13779 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
13780 Op.getOperand(1), Op.getOperand(2));
13782 case Intrinsic::x86_sse2_pshufl_w:
13783 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
13784 Op.getOperand(1), Op.getOperand(2));
13786 case Intrinsic::x86_sse2_pshufh_w:
13787 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
13788 Op.getOperand(1), Op.getOperand(2));
13790 case Intrinsic::x86_ssse3_psign_b_128:
13791 case Intrinsic::x86_ssse3_psign_w_128:
13792 case Intrinsic::x86_ssse3_psign_d_128:
13793 case Intrinsic::x86_avx2_psign_b:
13794 case Intrinsic::x86_avx2_psign_w:
13795 case Intrinsic::x86_avx2_psign_d:
13796 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
13797 Op.getOperand(1), Op.getOperand(2));
13799 case Intrinsic::x86_sse41_insertps:
13800 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
13801 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
13803 case Intrinsic::x86_avx_vperm2f128_ps_256:
13804 case Intrinsic::x86_avx_vperm2f128_pd_256:
13805 case Intrinsic::x86_avx_vperm2f128_si_256:
13806 case Intrinsic::x86_avx2_vperm2i128:
13807 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
13808 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
13810 case Intrinsic::x86_avx2_permd:
13811 case Intrinsic::x86_avx2_permps:
13812 // Operands intentionally swapped. Mask is last operand to intrinsic,
13813 // but second operand for node/instruction.
13814 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
13815 Op.getOperand(2), Op.getOperand(1));
13817 case Intrinsic::x86_sse_sqrt_ps:
13818 case Intrinsic::x86_sse2_sqrt_pd:
13819 case Intrinsic::x86_avx_sqrt_ps_256:
13820 case Intrinsic::x86_avx_sqrt_pd_256:
13821 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
13823 // ptest and testp intrinsics. The intrinsic these come from are designed to
13824 // return an integer value, not just an instruction so lower it to the ptest
13825 // or testp pattern and a setcc for the result.
13826 case Intrinsic::x86_sse41_ptestz:
13827 case Intrinsic::x86_sse41_ptestc:
13828 case Intrinsic::x86_sse41_ptestnzc:
13829 case Intrinsic::x86_avx_ptestz_256:
13830 case Intrinsic::x86_avx_ptestc_256:
13831 case Intrinsic::x86_avx_ptestnzc_256:
13832 case Intrinsic::x86_avx_vtestz_ps:
13833 case Intrinsic::x86_avx_vtestc_ps:
13834 case Intrinsic::x86_avx_vtestnzc_ps:
13835 case Intrinsic::x86_avx_vtestz_pd:
13836 case Intrinsic::x86_avx_vtestc_pd:
13837 case Intrinsic::x86_avx_vtestnzc_pd:
13838 case Intrinsic::x86_avx_vtestz_ps_256:
13839 case Intrinsic::x86_avx_vtestc_ps_256:
13840 case Intrinsic::x86_avx_vtestnzc_ps_256:
13841 case Intrinsic::x86_avx_vtestz_pd_256:
13842 case Intrinsic::x86_avx_vtestc_pd_256:
13843 case Intrinsic::x86_avx_vtestnzc_pd_256: {
13844 bool IsTestPacked = false;
13847 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
13848 case Intrinsic::x86_avx_vtestz_ps:
13849 case Intrinsic::x86_avx_vtestz_pd:
13850 case Intrinsic::x86_avx_vtestz_ps_256:
13851 case Intrinsic::x86_avx_vtestz_pd_256:
13852 IsTestPacked = true; // Fallthrough
13853 case Intrinsic::x86_sse41_ptestz:
13854 case Intrinsic::x86_avx_ptestz_256:
13856 X86CC = X86::COND_E;
13858 case Intrinsic::x86_avx_vtestc_ps:
13859 case Intrinsic::x86_avx_vtestc_pd:
13860 case Intrinsic::x86_avx_vtestc_ps_256:
13861 case Intrinsic::x86_avx_vtestc_pd_256:
13862 IsTestPacked = true; // Fallthrough
13863 case Intrinsic::x86_sse41_ptestc:
13864 case Intrinsic::x86_avx_ptestc_256:
13866 X86CC = X86::COND_B;
13868 case Intrinsic::x86_avx_vtestnzc_ps:
13869 case Intrinsic::x86_avx_vtestnzc_pd:
13870 case Intrinsic::x86_avx_vtestnzc_ps_256:
13871 case Intrinsic::x86_avx_vtestnzc_pd_256:
13872 IsTestPacked = true; // Fallthrough
13873 case Intrinsic::x86_sse41_ptestnzc:
13874 case Intrinsic::x86_avx_ptestnzc_256:
13876 X86CC = X86::COND_A;
13880 SDValue LHS = Op.getOperand(1);
13881 SDValue RHS = Op.getOperand(2);
13882 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
13883 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
13884 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
13885 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
13886 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
13888 case Intrinsic::x86_avx512_kortestz_w:
13889 case Intrinsic::x86_avx512_kortestc_w: {
13890 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
13891 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
13892 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
13893 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
13894 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
13895 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
13896 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
13899 // SSE/AVX shift intrinsics
13900 case Intrinsic::x86_sse2_psll_w:
13901 case Intrinsic::x86_sse2_psll_d:
13902 case Intrinsic::x86_sse2_psll_q:
13903 case Intrinsic::x86_avx2_psll_w:
13904 case Intrinsic::x86_avx2_psll_d:
13905 case Intrinsic::x86_avx2_psll_q:
13906 case Intrinsic::x86_sse2_psrl_w:
13907 case Intrinsic::x86_sse2_psrl_d:
13908 case Intrinsic::x86_sse2_psrl_q:
13909 case Intrinsic::x86_avx2_psrl_w:
13910 case Intrinsic::x86_avx2_psrl_d:
13911 case Intrinsic::x86_avx2_psrl_q:
13912 case Intrinsic::x86_sse2_psra_w:
13913 case Intrinsic::x86_sse2_psra_d:
13914 case Intrinsic::x86_avx2_psra_w:
13915 case Intrinsic::x86_avx2_psra_d: {
13918 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
13919 case Intrinsic::x86_sse2_psll_w:
13920 case Intrinsic::x86_sse2_psll_d:
13921 case Intrinsic::x86_sse2_psll_q:
13922 case Intrinsic::x86_avx2_psll_w:
13923 case Intrinsic::x86_avx2_psll_d:
13924 case Intrinsic::x86_avx2_psll_q:
13925 Opcode = X86ISD::VSHL;
13927 case Intrinsic::x86_sse2_psrl_w:
13928 case Intrinsic::x86_sse2_psrl_d:
13929 case Intrinsic::x86_sse2_psrl_q:
13930 case Intrinsic::x86_avx2_psrl_w:
13931 case Intrinsic::x86_avx2_psrl_d:
13932 case Intrinsic::x86_avx2_psrl_q:
13933 Opcode = X86ISD::VSRL;
13935 case Intrinsic::x86_sse2_psra_w:
13936 case Intrinsic::x86_sse2_psra_d:
13937 case Intrinsic::x86_avx2_psra_w:
13938 case Intrinsic::x86_avx2_psra_d:
13939 Opcode = X86ISD::VSRA;
13942 return DAG.getNode(Opcode, dl, Op.getValueType(),
13943 Op.getOperand(1), Op.getOperand(2));
13946 // SSE/AVX immediate shift intrinsics
13947 case Intrinsic::x86_sse2_pslli_w:
13948 case Intrinsic::x86_sse2_pslli_d:
13949 case Intrinsic::x86_sse2_pslli_q:
13950 case Intrinsic::x86_avx2_pslli_w:
13951 case Intrinsic::x86_avx2_pslli_d:
13952 case Intrinsic::x86_avx2_pslli_q:
13953 case Intrinsic::x86_sse2_psrli_w:
13954 case Intrinsic::x86_sse2_psrli_d:
13955 case Intrinsic::x86_sse2_psrli_q:
13956 case Intrinsic::x86_avx2_psrli_w:
13957 case Intrinsic::x86_avx2_psrli_d:
13958 case Intrinsic::x86_avx2_psrli_q:
13959 case Intrinsic::x86_sse2_psrai_w:
13960 case Intrinsic::x86_sse2_psrai_d:
13961 case Intrinsic::x86_avx2_psrai_w:
13962 case Intrinsic::x86_avx2_psrai_d: {
13965 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
13966 case Intrinsic::x86_sse2_pslli_w:
13967 case Intrinsic::x86_sse2_pslli_d:
13968 case Intrinsic::x86_sse2_pslli_q:
13969 case Intrinsic::x86_avx2_pslli_w:
13970 case Intrinsic::x86_avx2_pslli_d:
13971 case Intrinsic::x86_avx2_pslli_q:
13972 Opcode = X86ISD::VSHLI;
13974 case Intrinsic::x86_sse2_psrli_w:
13975 case Intrinsic::x86_sse2_psrli_d:
13976 case Intrinsic::x86_sse2_psrli_q:
13977 case Intrinsic::x86_avx2_psrli_w:
13978 case Intrinsic::x86_avx2_psrli_d:
13979 case Intrinsic::x86_avx2_psrli_q:
13980 Opcode = X86ISD::VSRLI;
13982 case Intrinsic::x86_sse2_psrai_w:
13983 case Intrinsic::x86_sse2_psrai_d:
13984 case Intrinsic::x86_avx2_psrai_w:
13985 case Intrinsic::x86_avx2_psrai_d:
13986 Opcode = X86ISD::VSRAI;
13989 return getTargetVShiftNode(Opcode, dl, Op.getSimpleValueType(),
13990 Op.getOperand(1), Op.getOperand(2), DAG);
13993 case Intrinsic::x86_sse42_pcmpistria128:
13994 case Intrinsic::x86_sse42_pcmpestria128:
13995 case Intrinsic::x86_sse42_pcmpistric128:
13996 case Intrinsic::x86_sse42_pcmpestric128:
13997 case Intrinsic::x86_sse42_pcmpistrio128:
13998 case Intrinsic::x86_sse42_pcmpestrio128:
13999 case Intrinsic::x86_sse42_pcmpistris128:
14000 case Intrinsic::x86_sse42_pcmpestris128:
14001 case Intrinsic::x86_sse42_pcmpistriz128:
14002 case Intrinsic::x86_sse42_pcmpestriz128: {
14006 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14007 case Intrinsic::x86_sse42_pcmpistria128:
14008 Opcode = X86ISD::PCMPISTRI;
14009 X86CC = X86::COND_A;
14011 case Intrinsic::x86_sse42_pcmpestria128:
14012 Opcode = X86ISD::PCMPESTRI;
14013 X86CC = X86::COND_A;
14015 case Intrinsic::x86_sse42_pcmpistric128:
14016 Opcode = X86ISD::PCMPISTRI;
14017 X86CC = X86::COND_B;
14019 case Intrinsic::x86_sse42_pcmpestric128:
14020 Opcode = X86ISD::PCMPESTRI;
14021 X86CC = X86::COND_B;
14023 case Intrinsic::x86_sse42_pcmpistrio128:
14024 Opcode = X86ISD::PCMPISTRI;
14025 X86CC = X86::COND_O;
14027 case Intrinsic::x86_sse42_pcmpestrio128:
14028 Opcode = X86ISD::PCMPESTRI;
14029 X86CC = X86::COND_O;
14031 case Intrinsic::x86_sse42_pcmpistris128:
14032 Opcode = X86ISD::PCMPISTRI;
14033 X86CC = X86::COND_S;
14035 case Intrinsic::x86_sse42_pcmpestris128:
14036 Opcode = X86ISD::PCMPESTRI;
14037 X86CC = X86::COND_S;
14039 case Intrinsic::x86_sse42_pcmpistriz128:
14040 Opcode = X86ISD::PCMPISTRI;
14041 X86CC = X86::COND_E;
14043 case Intrinsic::x86_sse42_pcmpestriz128:
14044 Opcode = X86ISD::PCMPESTRI;
14045 X86CC = X86::COND_E;
14048 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
14049 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14050 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
14051 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14052 DAG.getConstant(X86CC, MVT::i8),
14053 SDValue(PCMP.getNode(), 1));
14054 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14057 case Intrinsic::x86_sse42_pcmpistri128:
14058 case Intrinsic::x86_sse42_pcmpestri128: {
14060 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
14061 Opcode = X86ISD::PCMPISTRI;
14063 Opcode = X86ISD::PCMPESTRI;
14065 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
14066 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14067 return DAG.getNode(Opcode, dl, VTs, NewOps);
14069 case Intrinsic::x86_fma_vfmadd_ps:
14070 case Intrinsic::x86_fma_vfmadd_pd:
14071 case Intrinsic::x86_fma_vfmsub_ps:
14072 case Intrinsic::x86_fma_vfmsub_pd:
14073 case Intrinsic::x86_fma_vfnmadd_ps:
14074 case Intrinsic::x86_fma_vfnmadd_pd:
14075 case Intrinsic::x86_fma_vfnmsub_ps:
14076 case Intrinsic::x86_fma_vfnmsub_pd:
14077 case Intrinsic::x86_fma_vfmaddsub_ps:
14078 case Intrinsic::x86_fma_vfmaddsub_pd:
14079 case Intrinsic::x86_fma_vfmsubadd_ps:
14080 case Intrinsic::x86_fma_vfmsubadd_pd:
14081 case Intrinsic::x86_fma_vfmadd_ps_256:
14082 case Intrinsic::x86_fma_vfmadd_pd_256:
14083 case Intrinsic::x86_fma_vfmsub_ps_256:
14084 case Intrinsic::x86_fma_vfmsub_pd_256:
14085 case Intrinsic::x86_fma_vfnmadd_ps_256:
14086 case Intrinsic::x86_fma_vfnmadd_pd_256:
14087 case Intrinsic::x86_fma_vfnmsub_ps_256:
14088 case Intrinsic::x86_fma_vfnmsub_pd_256:
14089 case Intrinsic::x86_fma_vfmaddsub_ps_256:
14090 case Intrinsic::x86_fma_vfmaddsub_pd_256:
14091 case Intrinsic::x86_fma_vfmsubadd_ps_256:
14092 case Intrinsic::x86_fma_vfmsubadd_pd_256:
14093 case Intrinsic::x86_fma_vfmadd_ps_512:
14094 case Intrinsic::x86_fma_vfmadd_pd_512:
14095 case Intrinsic::x86_fma_vfmsub_ps_512:
14096 case Intrinsic::x86_fma_vfmsub_pd_512:
14097 case Intrinsic::x86_fma_vfnmadd_ps_512:
14098 case Intrinsic::x86_fma_vfnmadd_pd_512:
14099 case Intrinsic::x86_fma_vfnmsub_ps_512:
14100 case Intrinsic::x86_fma_vfnmsub_pd_512:
14101 case Intrinsic::x86_fma_vfmaddsub_ps_512:
14102 case Intrinsic::x86_fma_vfmaddsub_pd_512:
14103 case Intrinsic::x86_fma_vfmsubadd_ps_512:
14104 case Intrinsic::x86_fma_vfmsubadd_pd_512: {
14107 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14108 case Intrinsic::x86_fma_vfmadd_ps:
14109 case Intrinsic::x86_fma_vfmadd_pd:
14110 case Intrinsic::x86_fma_vfmadd_ps_256:
14111 case Intrinsic::x86_fma_vfmadd_pd_256:
14112 case Intrinsic::x86_fma_vfmadd_ps_512:
14113 case Intrinsic::x86_fma_vfmadd_pd_512:
14114 Opc = X86ISD::FMADD;
14116 case Intrinsic::x86_fma_vfmsub_ps:
14117 case Intrinsic::x86_fma_vfmsub_pd:
14118 case Intrinsic::x86_fma_vfmsub_ps_256:
14119 case Intrinsic::x86_fma_vfmsub_pd_256:
14120 case Intrinsic::x86_fma_vfmsub_ps_512:
14121 case Intrinsic::x86_fma_vfmsub_pd_512:
14122 Opc = X86ISD::FMSUB;
14124 case Intrinsic::x86_fma_vfnmadd_ps:
14125 case Intrinsic::x86_fma_vfnmadd_pd:
14126 case Intrinsic::x86_fma_vfnmadd_ps_256:
14127 case Intrinsic::x86_fma_vfnmadd_pd_256:
14128 case Intrinsic::x86_fma_vfnmadd_ps_512:
14129 case Intrinsic::x86_fma_vfnmadd_pd_512:
14130 Opc = X86ISD::FNMADD;
14132 case Intrinsic::x86_fma_vfnmsub_ps:
14133 case Intrinsic::x86_fma_vfnmsub_pd:
14134 case Intrinsic::x86_fma_vfnmsub_ps_256:
14135 case Intrinsic::x86_fma_vfnmsub_pd_256:
14136 case Intrinsic::x86_fma_vfnmsub_ps_512:
14137 case Intrinsic::x86_fma_vfnmsub_pd_512:
14138 Opc = X86ISD::FNMSUB;
14140 case Intrinsic::x86_fma_vfmaddsub_ps:
14141 case Intrinsic::x86_fma_vfmaddsub_pd:
14142 case Intrinsic::x86_fma_vfmaddsub_ps_256:
14143 case Intrinsic::x86_fma_vfmaddsub_pd_256:
14144 case Intrinsic::x86_fma_vfmaddsub_ps_512:
14145 case Intrinsic::x86_fma_vfmaddsub_pd_512:
14146 Opc = X86ISD::FMADDSUB;
14148 case Intrinsic::x86_fma_vfmsubadd_ps:
14149 case Intrinsic::x86_fma_vfmsubadd_pd:
14150 case Intrinsic::x86_fma_vfmsubadd_ps_256:
14151 case Intrinsic::x86_fma_vfmsubadd_pd_256:
14152 case Intrinsic::x86_fma_vfmsubadd_ps_512:
14153 case Intrinsic::x86_fma_vfmsubadd_pd_512:
14154 Opc = X86ISD::FMSUBADD;
14158 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
14159 Op.getOperand(2), Op.getOperand(3));
14164 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
14165 SDValue Src, SDValue Mask, SDValue Base,
14166 SDValue Index, SDValue ScaleOp, SDValue Chain,
14167 const X86Subtarget * Subtarget) {
14169 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
14170 assert(C && "Invalid scale type");
14171 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
14172 EVT MaskVT = MVT::getVectorVT(MVT::i1,
14173 Index.getSimpleValueType().getVectorNumElements());
14175 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
14177 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
14179 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
14180 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
14181 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
14182 SDValue Segment = DAG.getRegister(0, MVT::i32);
14183 if (Src.getOpcode() == ISD::UNDEF)
14184 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
14185 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
14186 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
14187 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
14188 return DAG.getMergeValues(RetOps, dl);
14191 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
14192 SDValue Src, SDValue Mask, SDValue Base,
14193 SDValue Index, SDValue ScaleOp, SDValue Chain) {
14195 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
14196 assert(C && "Invalid scale type");
14197 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
14198 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
14199 SDValue Segment = DAG.getRegister(0, MVT::i32);
14200 EVT MaskVT = MVT::getVectorVT(MVT::i1,
14201 Index.getSimpleValueType().getVectorNumElements());
14203 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
14205 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
14207 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
14208 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
14209 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
14210 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
14211 return SDValue(Res, 1);
14214 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
14215 SDValue Mask, SDValue Base, SDValue Index,
14216 SDValue ScaleOp, SDValue Chain) {
14218 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
14219 assert(C && "Invalid scale type");
14220 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
14221 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
14222 SDValue Segment = DAG.getRegister(0, MVT::i32);
14224 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
14226 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
14228 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
14230 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
14231 //SDVTList VTs = DAG.getVTList(MVT::Other);
14232 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
14233 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
14234 return SDValue(Res, 0);
14237 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
14238 // read performance monitor counters (x86_rdpmc).
14239 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
14240 SelectionDAG &DAG, const X86Subtarget *Subtarget,
14241 SmallVectorImpl<SDValue> &Results) {
14242 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
14243 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
14246 // The ECX register is used to select the index of the performance counter
14248 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
14250 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
14252 // Reads the content of a 64-bit performance counter and returns it in the
14253 // registers EDX:EAX.
14254 if (Subtarget->is64Bit()) {
14255 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
14256 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
14259 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
14260 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
14263 Chain = HI.getValue(1);
14265 if (Subtarget->is64Bit()) {
14266 // The EAX register is loaded with the low-order 32 bits. The EDX register
14267 // is loaded with the supported high-order bits of the counter.
14268 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
14269 DAG.getConstant(32, MVT::i8));
14270 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
14271 Results.push_back(Chain);
14275 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
14276 SDValue Ops[] = { LO, HI };
14277 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
14278 Results.push_back(Pair);
14279 Results.push_back(Chain);
14282 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
14283 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
14284 // also used to custom lower READCYCLECOUNTER nodes.
14285 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
14286 SelectionDAG &DAG, const X86Subtarget *Subtarget,
14287 SmallVectorImpl<SDValue> &Results) {
14288 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
14289 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
14292 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
14293 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
14294 // and the EAX register is loaded with the low-order 32 bits.
14295 if (Subtarget->is64Bit()) {
14296 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
14297 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
14300 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
14301 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
14304 SDValue Chain = HI.getValue(1);
14306 if (Opcode == X86ISD::RDTSCP_DAG) {
14307 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
14309 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
14310 // the ECX register. Add 'ecx' explicitly to the chain.
14311 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
14313 // Explicitly store the content of ECX at the location passed in input
14314 // to the 'rdtscp' intrinsic.
14315 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
14316 MachinePointerInfo(), false, false, 0);
14319 if (Subtarget->is64Bit()) {
14320 // The EDX register is loaded with the high-order 32 bits of the MSR, and
14321 // the EAX register is loaded with the low-order 32 bits.
14322 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
14323 DAG.getConstant(32, MVT::i8));
14324 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
14325 Results.push_back(Chain);
14329 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
14330 SDValue Ops[] = { LO, HI };
14331 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
14332 Results.push_back(Pair);
14333 Results.push_back(Chain);
14336 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
14337 SelectionDAG &DAG) {
14338 SmallVector<SDValue, 2> Results;
14340 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
14342 return DAG.getMergeValues(Results, DL);
14345 enum IntrinsicType {
14346 GATHER, SCATTER, PREFETCH, RDSEED, RDRAND, RDPMC, RDTSC, XTEST
14349 struct IntrinsicData {
14350 IntrinsicData(IntrinsicType IType, unsigned IOpc0, unsigned IOpc1)
14351 :Type(IType), Opc0(IOpc0), Opc1(IOpc1) {}
14352 IntrinsicType Type;
14357 std::map < unsigned, IntrinsicData> IntrMap;
14358 static void InitIntinsicsMap() {
14359 static bool Initialized = false;
14362 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qps_512,
14363 IntrinsicData(GATHER, X86::VGATHERQPSZrm, 0)));
14364 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qps_512,
14365 IntrinsicData(GATHER, X86::VGATHERQPSZrm, 0)));
14366 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpd_512,
14367 IntrinsicData(GATHER, X86::VGATHERQPDZrm, 0)));
14368 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpd_512,
14369 IntrinsicData(GATHER, X86::VGATHERDPDZrm, 0)));
14370 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dps_512,
14371 IntrinsicData(GATHER, X86::VGATHERDPSZrm, 0)));
14372 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpi_512,
14373 IntrinsicData(GATHER, X86::VPGATHERQDZrm, 0)));
14374 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpq_512,
14375 IntrinsicData(GATHER, X86::VPGATHERQQZrm, 0)));
14376 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpi_512,
14377 IntrinsicData(GATHER, X86::VPGATHERDDZrm, 0)));
14378 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpq_512,
14379 IntrinsicData(GATHER, X86::VPGATHERDQZrm, 0)));
14381 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qps_512,
14382 IntrinsicData(SCATTER, X86::VSCATTERQPSZmr, 0)));
14383 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpd_512,
14384 IntrinsicData(SCATTER, X86::VSCATTERQPDZmr, 0)));
14385 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpd_512,
14386 IntrinsicData(SCATTER, X86::VSCATTERDPDZmr, 0)));
14387 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dps_512,
14388 IntrinsicData(SCATTER, X86::VSCATTERDPSZmr, 0)));
14389 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpi_512,
14390 IntrinsicData(SCATTER, X86::VPSCATTERQDZmr, 0)));
14391 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpq_512,
14392 IntrinsicData(SCATTER, X86::VPSCATTERQQZmr, 0)));
14393 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpi_512,
14394 IntrinsicData(SCATTER, X86::VPSCATTERDDZmr, 0)));
14395 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpq_512,
14396 IntrinsicData(SCATTER, X86::VPSCATTERDQZmr, 0)));
14398 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_qps_512,
14399 IntrinsicData(PREFETCH, X86::VGATHERPF0QPSm,
14400 X86::VGATHERPF1QPSm)));
14401 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_qpd_512,
14402 IntrinsicData(PREFETCH, X86::VGATHERPF0QPDm,
14403 X86::VGATHERPF1QPDm)));
14404 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_dpd_512,
14405 IntrinsicData(PREFETCH, X86::VGATHERPF0DPDm,
14406 X86::VGATHERPF1DPDm)));
14407 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_dps_512,
14408 IntrinsicData(PREFETCH, X86::VGATHERPF0DPSm,
14409 X86::VGATHERPF1DPSm)));
14410 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_qps_512,
14411 IntrinsicData(PREFETCH, X86::VSCATTERPF0QPSm,
14412 X86::VSCATTERPF1QPSm)));
14413 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_qpd_512,
14414 IntrinsicData(PREFETCH, X86::VSCATTERPF0QPDm,
14415 X86::VSCATTERPF1QPDm)));
14416 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_dpd_512,
14417 IntrinsicData(PREFETCH, X86::VSCATTERPF0DPDm,
14418 X86::VSCATTERPF1DPDm)));
14419 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_dps_512,
14420 IntrinsicData(PREFETCH, X86::VSCATTERPF0DPSm,
14421 X86::VSCATTERPF1DPSm)));
14422 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_16,
14423 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
14424 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_32,
14425 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
14426 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_64,
14427 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
14428 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_16,
14429 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
14430 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_32,
14431 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
14432 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_64,
14433 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
14434 IntrMap.insert(std::make_pair(Intrinsic::x86_xtest,
14435 IntrinsicData(XTEST, X86ISD::XTEST, 0)));
14436 IntrMap.insert(std::make_pair(Intrinsic::x86_rdtsc,
14437 IntrinsicData(RDTSC, X86ISD::RDTSC_DAG, 0)));
14438 IntrMap.insert(std::make_pair(Intrinsic::x86_rdtscp,
14439 IntrinsicData(RDTSC, X86ISD::RDTSCP_DAG, 0)));
14440 IntrMap.insert(std::make_pair(Intrinsic::x86_rdpmc,
14441 IntrinsicData(RDPMC, X86ISD::RDPMC_DAG, 0)));
14442 Initialized = true;
14445 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
14446 SelectionDAG &DAG) {
14447 InitIntinsicsMap();
14448 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
14449 std::map < unsigned, IntrinsicData>::const_iterator itr = IntrMap.find(IntNo);
14450 if (itr == IntrMap.end())
14454 IntrinsicData Intr = itr->second;
14455 switch(Intr.Type) {
14458 // Emit the node with the right value type.
14459 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
14460 SDValue Result = DAG.getNode(Intr.Opc0, dl, VTs, Op.getOperand(0));
14462 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
14463 // Otherwise return the value from Rand, which is always 0, casted to i32.
14464 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
14465 DAG.getConstant(1, Op->getValueType(1)),
14466 DAG.getConstant(X86::COND_B, MVT::i32),
14467 SDValue(Result.getNode(), 1) };
14468 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
14469 DAG.getVTList(Op->getValueType(1), MVT::Glue),
14472 // Return { result, isValid, chain }.
14473 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
14474 SDValue(Result.getNode(), 2));
14477 //gather(v1, mask, index, base, scale);
14478 SDValue Chain = Op.getOperand(0);
14479 SDValue Src = Op.getOperand(2);
14480 SDValue Base = Op.getOperand(3);
14481 SDValue Index = Op.getOperand(4);
14482 SDValue Mask = Op.getOperand(5);
14483 SDValue Scale = Op.getOperand(6);
14484 return getGatherNode(Intr.Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
14488 //scatter(base, mask, index, v1, scale);
14489 SDValue Chain = Op.getOperand(0);
14490 SDValue Base = Op.getOperand(2);
14491 SDValue Mask = Op.getOperand(3);
14492 SDValue Index = Op.getOperand(4);
14493 SDValue Src = Op.getOperand(5);
14494 SDValue Scale = Op.getOperand(6);
14495 return getScatterNode(Intr.Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
14498 SDValue Hint = Op.getOperand(6);
14500 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
14501 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
14502 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
14503 unsigned Opcode = (HintVal ? Intr.Opc1 : Intr.Opc0);
14504 SDValue Chain = Op.getOperand(0);
14505 SDValue Mask = Op.getOperand(2);
14506 SDValue Index = Op.getOperand(3);
14507 SDValue Base = Op.getOperand(4);
14508 SDValue Scale = Op.getOperand(5);
14509 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
14511 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
14513 SmallVector<SDValue, 2> Results;
14514 getReadTimeStampCounter(Op.getNode(), dl, Intr.Opc0, DAG, Subtarget, Results);
14515 return DAG.getMergeValues(Results, dl);
14517 // Read Performance Monitoring Counters.
14519 SmallVector<SDValue, 2> Results;
14520 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
14521 return DAG.getMergeValues(Results, dl);
14523 // XTEST intrinsics.
14525 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
14526 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
14527 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14528 DAG.getConstant(X86::COND_NE, MVT::i8),
14530 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
14531 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
14532 Ret, SDValue(InTrans.getNode(), 1));
14535 llvm_unreachable("Unknown Intrinsic Type");
14538 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
14539 SelectionDAG &DAG) const {
14540 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
14541 MFI->setReturnAddressIsTaken(true);
14543 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
14546 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
14548 EVT PtrVT = getPointerTy();
14551 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
14552 const X86RegisterInfo *RegInfo =
14553 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
14554 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
14555 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
14556 DAG.getNode(ISD::ADD, dl, PtrVT,
14557 FrameAddr, Offset),
14558 MachinePointerInfo(), false, false, false, 0);
14561 // Just load the return address.
14562 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
14563 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
14564 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
14567 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
14568 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
14569 MFI->setFrameAddressIsTaken(true);
14571 EVT VT = Op.getValueType();
14572 SDLoc dl(Op); // FIXME probably not meaningful
14573 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
14574 const X86RegisterInfo *RegInfo =
14575 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
14576 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
14577 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
14578 (FrameReg == X86::EBP && VT == MVT::i32)) &&
14579 "Invalid Frame Register!");
14580 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
14582 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
14583 MachinePointerInfo(),
14584 false, false, false, 0);
14588 // FIXME? Maybe this could be a TableGen attribute on some registers and
14589 // this table could be generated automatically from RegInfo.
14590 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
14592 unsigned Reg = StringSwitch<unsigned>(RegName)
14593 .Case("esp", X86::ESP)
14594 .Case("rsp", X86::RSP)
14598 report_fatal_error("Invalid register name global variable");
14601 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
14602 SelectionDAG &DAG) const {
14603 const X86RegisterInfo *RegInfo =
14604 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
14605 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
14608 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
14609 SDValue Chain = Op.getOperand(0);
14610 SDValue Offset = Op.getOperand(1);
14611 SDValue Handler = Op.getOperand(2);
14614 EVT PtrVT = getPointerTy();
14615 const X86RegisterInfo *RegInfo =
14616 static_cast<const X86RegisterInfo*>(DAG.getTarget().getRegisterInfo());
14617 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
14618 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
14619 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
14620 "Invalid Frame Register!");
14621 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
14622 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
14624 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
14625 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
14626 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
14627 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
14629 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
14631 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
14632 DAG.getRegister(StoreAddrReg, PtrVT));
14635 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
14636 SelectionDAG &DAG) const {
14638 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
14639 DAG.getVTList(MVT::i32, MVT::Other),
14640 Op.getOperand(0), Op.getOperand(1));
14643 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
14644 SelectionDAG &DAG) const {
14646 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
14647 Op.getOperand(0), Op.getOperand(1));
14650 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
14651 return Op.getOperand(0);
14654 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
14655 SelectionDAG &DAG) const {
14656 SDValue Root = Op.getOperand(0);
14657 SDValue Trmp = Op.getOperand(1); // trampoline
14658 SDValue FPtr = Op.getOperand(2); // nested function
14659 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
14662 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
14663 const TargetRegisterInfo* TRI = DAG.getTarget().getRegisterInfo();
14665 if (Subtarget->is64Bit()) {
14666 SDValue OutChains[6];
14668 // Large code-model.
14669 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
14670 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
14672 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
14673 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
14675 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
14677 // Load the pointer to the nested function into R11.
14678 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
14679 SDValue Addr = Trmp;
14680 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
14681 Addr, MachinePointerInfo(TrmpAddr),
14684 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
14685 DAG.getConstant(2, MVT::i64));
14686 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
14687 MachinePointerInfo(TrmpAddr, 2),
14690 // Load the 'nest' parameter value into R10.
14691 // R10 is specified in X86CallingConv.td
14692 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
14693 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
14694 DAG.getConstant(10, MVT::i64));
14695 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
14696 Addr, MachinePointerInfo(TrmpAddr, 10),
14699 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
14700 DAG.getConstant(12, MVT::i64));
14701 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
14702 MachinePointerInfo(TrmpAddr, 12),
14705 // Jump to the nested function.
14706 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
14707 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
14708 DAG.getConstant(20, MVT::i64));
14709 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
14710 Addr, MachinePointerInfo(TrmpAddr, 20),
14713 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
14714 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
14715 DAG.getConstant(22, MVT::i64));
14716 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
14717 MachinePointerInfo(TrmpAddr, 22),
14720 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
14722 const Function *Func =
14723 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
14724 CallingConv::ID CC = Func->getCallingConv();
14729 llvm_unreachable("Unsupported calling convention");
14730 case CallingConv::C:
14731 case CallingConv::X86_StdCall: {
14732 // Pass 'nest' parameter in ECX.
14733 // Must be kept in sync with X86CallingConv.td
14734 NestReg = X86::ECX;
14736 // Check that ECX wasn't needed by an 'inreg' parameter.
14737 FunctionType *FTy = Func->getFunctionType();
14738 const AttributeSet &Attrs = Func->getAttributes();
14740 if (!Attrs.isEmpty() && !Func->isVarArg()) {
14741 unsigned InRegCount = 0;
14744 for (FunctionType::param_iterator I = FTy->param_begin(),
14745 E = FTy->param_end(); I != E; ++I, ++Idx)
14746 if (Attrs.hasAttribute(Idx, Attribute::InReg))
14747 // FIXME: should only count parameters that are lowered to integers.
14748 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
14750 if (InRegCount > 2) {
14751 report_fatal_error("Nest register in use - reduce number of inreg"
14757 case CallingConv::X86_FastCall:
14758 case CallingConv::X86_ThisCall:
14759 case CallingConv::Fast:
14760 // Pass 'nest' parameter in EAX.
14761 // Must be kept in sync with X86CallingConv.td
14762 NestReg = X86::EAX;
14766 SDValue OutChains[4];
14767 SDValue Addr, Disp;
14769 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
14770 DAG.getConstant(10, MVT::i32));
14771 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
14773 // This is storing the opcode for MOV32ri.
14774 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
14775 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
14776 OutChains[0] = DAG.getStore(Root, dl,
14777 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
14778 Trmp, MachinePointerInfo(TrmpAddr),
14781 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
14782 DAG.getConstant(1, MVT::i32));
14783 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
14784 MachinePointerInfo(TrmpAddr, 1),
14787 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
14788 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
14789 DAG.getConstant(5, MVT::i32));
14790 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
14791 MachinePointerInfo(TrmpAddr, 5),
14794 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
14795 DAG.getConstant(6, MVT::i32));
14796 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
14797 MachinePointerInfo(TrmpAddr, 6),
14800 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
14804 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
14805 SelectionDAG &DAG) const {
14807 The rounding mode is in bits 11:10 of FPSR, and has the following
14809 00 Round to nearest
14814 FLT_ROUNDS, on the other hand, expects the following:
14821 To perform the conversion, we do:
14822 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
14825 MachineFunction &MF = DAG.getMachineFunction();
14826 const TargetMachine &TM = MF.getTarget();
14827 const TargetFrameLowering &TFI = *TM.getFrameLowering();
14828 unsigned StackAlignment = TFI.getStackAlignment();
14829 MVT VT = Op.getSimpleValueType();
14832 // Save FP Control Word to stack slot
14833 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
14834 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14836 MachineMemOperand *MMO =
14837 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14838 MachineMemOperand::MOStore, 2, 2);
14840 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
14841 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
14842 DAG.getVTList(MVT::Other),
14843 Ops, MVT::i16, MMO);
14845 // Load FP Control Word from stack slot
14846 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
14847 MachinePointerInfo(), false, false, false, 0);
14849 // Transform as necessary
14851 DAG.getNode(ISD::SRL, DL, MVT::i16,
14852 DAG.getNode(ISD::AND, DL, MVT::i16,
14853 CWD, DAG.getConstant(0x800, MVT::i16)),
14854 DAG.getConstant(11, MVT::i8));
14856 DAG.getNode(ISD::SRL, DL, MVT::i16,
14857 DAG.getNode(ISD::AND, DL, MVT::i16,
14858 CWD, DAG.getConstant(0x400, MVT::i16)),
14859 DAG.getConstant(9, MVT::i8));
14862 DAG.getNode(ISD::AND, DL, MVT::i16,
14863 DAG.getNode(ISD::ADD, DL, MVT::i16,
14864 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
14865 DAG.getConstant(1, MVT::i16)),
14866 DAG.getConstant(3, MVT::i16));
14868 return DAG.getNode((VT.getSizeInBits() < 16 ?
14869 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
14872 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
14873 MVT VT = Op.getSimpleValueType();
14875 unsigned NumBits = VT.getSizeInBits();
14878 Op = Op.getOperand(0);
14879 if (VT == MVT::i8) {
14880 // Zero extend to i32 since there is not an i8 bsr.
14882 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
14885 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
14886 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
14887 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
14889 // If src is zero (i.e. bsr sets ZF), returns NumBits.
14892 DAG.getConstant(NumBits+NumBits-1, OpVT),
14893 DAG.getConstant(X86::COND_E, MVT::i8),
14896 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
14898 // Finally xor with NumBits-1.
14899 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
14902 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
14906 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
14907 MVT VT = Op.getSimpleValueType();
14909 unsigned NumBits = VT.getSizeInBits();
14912 Op = Op.getOperand(0);
14913 if (VT == MVT::i8) {
14914 // Zero extend to i32 since there is not an i8 bsr.
14916 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
14919 // Issue a bsr (scan bits in reverse).
14920 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
14921 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
14923 // And xor with NumBits-1.
14924 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
14927 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
14931 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
14932 MVT VT = Op.getSimpleValueType();
14933 unsigned NumBits = VT.getSizeInBits();
14935 Op = Op.getOperand(0);
14937 // Issue a bsf (scan bits forward) which also sets EFLAGS.
14938 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
14939 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
14941 // If src is zero (i.e. bsf sets ZF), returns NumBits.
14944 DAG.getConstant(NumBits, VT),
14945 DAG.getConstant(X86::COND_E, MVT::i8),
14948 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
14951 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
14952 // ones, and then concatenate the result back.
14953 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
14954 MVT VT = Op.getSimpleValueType();
14956 assert(VT.is256BitVector() && VT.isInteger() &&
14957 "Unsupported value type for operation");
14959 unsigned NumElems = VT.getVectorNumElements();
14962 // Extract the LHS vectors
14963 SDValue LHS = Op.getOperand(0);
14964 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14965 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14967 // Extract the RHS vectors
14968 SDValue RHS = Op.getOperand(1);
14969 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14970 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14972 MVT EltVT = VT.getVectorElementType();
14973 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14975 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14976 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
14977 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
14980 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
14981 assert(Op.getSimpleValueType().is256BitVector() &&
14982 Op.getSimpleValueType().isInteger() &&
14983 "Only handle AVX 256-bit vector integer operation");
14984 return Lower256IntArith(Op, DAG);
14987 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
14988 assert(Op.getSimpleValueType().is256BitVector() &&
14989 Op.getSimpleValueType().isInteger() &&
14990 "Only handle AVX 256-bit vector integer operation");
14991 return Lower256IntArith(Op, DAG);
14994 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
14995 SelectionDAG &DAG) {
14997 MVT VT = Op.getSimpleValueType();
14999 // Decompose 256-bit ops into smaller 128-bit ops.
15000 if (VT.is256BitVector() && !Subtarget->hasInt256())
15001 return Lower256IntArith(Op, DAG);
15003 SDValue A = Op.getOperand(0);
15004 SDValue B = Op.getOperand(1);
15006 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
15007 if (VT == MVT::v4i32) {
15008 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
15009 "Should not custom lower when pmuldq is available!");
15011 // Extract the odd parts.
15012 static const int UnpackMask[] = { 1, -1, 3, -1 };
15013 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
15014 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
15016 // Multiply the even parts.
15017 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
15018 // Now multiply odd parts.
15019 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
15021 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
15022 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
15024 // Merge the two vectors back together with a shuffle. This expands into 2
15026 static const int ShufMask[] = { 0, 4, 2, 6 };
15027 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
15030 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
15031 "Only know how to lower V2I64/V4I64/V8I64 multiply");
15033 // Ahi = psrlqi(a, 32);
15034 // Bhi = psrlqi(b, 32);
15036 // AloBlo = pmuludq(a, b);
15037 // AloBhi = pmuludq(a, Bhi);
15038 // AhiBlo = pmuludq(Ahi, b);
15040 // AloBhi = psllqi(AloBhi, 32);
15041 // AhiBlo = psllqi(AhiBlo, 32);
15042 // return AloBlo + AloBhi + AhiBlo;
15044 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
15045 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
15047 // Bit cast to 32-bit vectors for MULUDQ
15048 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
15049 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
15050 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
15051 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
15052 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
15053 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
15055 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
15056 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
15057 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
15059 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
15060 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
15062 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
15063 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
15066 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
15067 assert(Subtarget->isTargetWin64() && "Unexpected target");
15068 EVT VT = Op.getValueType();
15069 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
15070 "Unexpected return type for lowering");
15074 switch (Op->getOpcode()) {
15075 default: llvm_unreachable("Unexpected request for libcall!");
15076 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
15077 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
15078 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
15079 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
15080 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
15081 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
15085 SDValue InChain = DAG.getEntryNode();
15087 TargetLowering::ArgListTy Args;
15088 TargetLowering::ArgListEntry Entry;
15089 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
15090 EVT ArgVT = Op->getOperand(i).getValueType();
15091 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
15092 "Unexpected argument type for lowering");
15093 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
15094 Entry.Node = StackPtr;
15095 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
15097 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15098 Entry.Ty = PointerType::get(ArgTy,0);
15099 Entry.isSExt = false;
15100 Entry.isZExt = false;
15101 Args.push_back(Entry);
15104 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
15107 TargetLowering::CallLoweringInfo CLI(DAG);
15108 CLI.setDebugLoc(dl).setChain(InChain)
15109 .setCallee(getLibcallCallingConv(LC),
15110 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
15111 Callee, std::move(Args), 0)
15112 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
15114 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
15115 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
15118 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
15119 SelectionDAG &DAG) {
15120 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
15121 EVT VT = Op0.getValueType();
15124 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
15125 (VT == MVT::v8i32 && Subtarget->hasInt256()));
15127 // Get the high parts.
15128 const int Mask[] = {1, 2, 3, 4, 5, 6, 7, 8};
15129 SDValue Hi0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
15130 SDValue Hi1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
15132 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
15134 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
15135 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
15137 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
15138 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
15139 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
15140 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
15141 DAG.getNode(Opcode, dl, MulVT, Hi0, Hi1));
15143 // Shuffle it back into the right order.
15144 const int HighMask[] = {1, 5, 3, 7, 9, 13, 11, 15};
15145 SDValue Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
15146 const int LowMask[] = {0, 4, 2, 6, 8, 12, 10, 14};
15147 SDValue Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
15149 // If we have a signed multiply but no PMULDQ fix up the high parts of a
15150 // unsigned multiply.
15151 if (IsSigned && !Subtarget->hasSSE41()) {
15153 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
15154 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
15155 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
15156 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
15157 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
15159 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
15160 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
15163 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getValueType(), Highs, Lows);
15166 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
15167 const X86Subtarget *Subtarget) {
15168 MVT VT = Op.getSimpleValueType();
15170 SDValue R = Op.getOperand(0);
15171 SDValue Amt = Op.getOperand(1);
15173 // Optimize shl/srl/sra with constant shift amount.
15174 if (isSplatVector(Amt.getNode())) {
15175 SDValue SclrAmt = Amt->getOperand(0);
15176 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
15177 uint64_t ShiftAmt = C->getZExtValue();
15179 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
15180 (Subtarget->hasInt256() &&
15181 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
15182 (Subtarget->hasAVX512() &&
15183 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
15184 if (Op.getOpcode() == ISD::SHL)
15185 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
15187 if (Op.getOpcode() == ISD::SRL)
15188 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
15190 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
15191 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
15195 if (VT == MVT::v16i8) {
15196 if (Op.getOpcode() == ISD::SHL) {
15197 // Make a large shift.
15198 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
15199 MVT::v8i16, R, ShiftAmt,
15201 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
15202 // Zero out the rightmost bits.
15203 SmallVector<SDValue, 16> V(16,
15204 DAG.getConstant(uint8_t(-1U << ShiftAmt),
15206 return DAG.getNode(ISD::AND, dl, VT, SHL,
15207 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15209 if (Op.getOpcode() == ISD::SRL) {
15210 // Make a large shift.
15211 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
15212 MVT::v8i16, R, ShiftAmt,
15214 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
15215 // Zero out the leftmost bits.
15216 SmallVector<SDValue, 16> V(16,
15217 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
15219 return DAG.getNode(ISD::AND, dl, VT, SRL,
15220 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15222 if (Op.getOpcode() == ISD::SRA) {
15223 if (ShiftAmt == 7) {
15224 // R s>> 7 === R s< 0
15225 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
15226 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
15229 // R s>> a === ((R u>> a) ^ m) - m
15230 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
15231 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
15233 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
15234 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
15235 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
15238 llvm_unreachable("Unknown shift opcode.");
15241 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
15242 if (Op.getOpcode() == ISD::SHL) {
15243 // Make a large shift.
15244 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
15245 MVT::v16i16, R, ShiftAmt,
15247 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
15248 // Zero out the rightmost bits.
15249 SmallVector<SDValue, 32> V(32,
15250 DAG.getConstant(uint8_t(-1U << ShiftAmt),
15252 return DAG.getNode(ISD::AND, dl, VT, SHL,
15253 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15255 if (Op.getOpcode() == ISD::SRL) {
15256 // Make a large shift.
15257 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
15258 MVT::v16i16, R, ShiftAmt,
15260 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
15261 // Zero out the leftmost bits.
15262 SmallVector<SDValue, 32> V(32,
15263 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
15265 return DAG.getNode(ISD::AND, dl, VT, SRL,
15266 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15268 if (Op.getOpcode() == ISD::SRA) {
15269 if (ShiftAmt == 7) {
15270 // R s>> 7 === R s< 0
15271 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
15272 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
15275 // R s>> a === ((R u>> a) ^ m) - m
15276 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
15277 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
15279 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
15280 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
15281 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
15284 llvm_unreachable("Unknown shift opcode.");
15289 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
15290 if (!Subtarget->is64Bit() &&
15291 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
15292 Amt.getOpcode() == ISD::BITCAST &&
15293 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
15294 Amt = Amt.getOperand(0);
15295 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
15296 VT.getVectorNumElements();
15297 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
15298 uint64_t ShiftAmt = 0;
15299 for (unsigned i = 0; i != Ratio; ++i) {
15300 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
15304 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
15306 // Check remaining shift amounts.
15307 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
15308 uint64_t ShAmt = 0;
15309 for (unsigned j = 0; j != Ratio; ++j) {
15310 ConstantSDNode *C =
15311 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
15315 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
15317 if (ShAmt != ShiftAmt)
15320 switch (Op.getOpcode()) {
15322 llvm_unreachable("Unknown shift opcode!");
15324 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
15327 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
15330 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
15338 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
15339 const X86Subtarget* Subtarget) {
15340 MVT VT = Op.getSimpleValueType();
15342 SDValue R = Op.getOperand(0);
15343 SDValue Amt = Op.getOperand(1);
15345 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
15346 VT == MVT::v4i32 || VT == MVT::v8i16 ||
15347 (Subtarget->hasInt256() &&
15348 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
15349 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
15350 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
15352 EVT EltVT = VT.getVectorElementType();
15354 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
15355 unsigned NumElts = VT.getVectorNumElements();
15357 for (i = 0; i != NumElts; ++i) {
15358 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
15362 for (j = i; j != NumElts; ++j) {
15363 SDValue Arg = Amt.getOperand(j);
15364 if (Arg.getOpcode() == ISD::UNDEF) continue;
15365 if (Arg != Amt.getOperand(i))
15368 if (i != NumElts && j == NumElts)
15369 BaseShAmt = Amt.getOperand(i);
15371 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
15372 Amt = Amt.getOperand(0);
15373 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
15374 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
15375 SDValue InVec = Amt.getOperand(0);
15376 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
15377 unsigned NumElts = InVec.getValueType().getVectorNumElements();
15379 for (; i != NumElts; ++i) {
15380 SDValue Arg = InVec.getOperand(i);
15381 if (Arg.getOpcode() == ISD::UNDEF) continue;
15385 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
15386 if (ConstantSDNode *C =
15387 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
15388 unsigned SplatIdx =
15389 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
15390 if (C->getZExtValue() == SplatIdx)
15391 BaseShAmt = InVec.getOperand(1);
15394 if (!BaseShAmt.getNode())
15395 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
15396 DAG.getIntPtrConstant(0));
15400 if (BaseShAmt.getNode()) {
15401 if (EltVT.bitsGT(MVT::i32))
15402 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
15403 else if (EltVT.bitsLT(MVT::i32))
15404 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
15406 switch (Op.getOpcode()) {
15408 llvm_unreachable("Unknown shift opcode!");
15410 switch (VT.SimpleTy) {
15411 default: return SDValue();
15420 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
15423 switch (VT.SimpleTy) {
15424 default: return SDValue();
15431 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
15434 switch (VT.SimpleTy) {
15435 default: return SDValue();
15444 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
15450 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
15451 if (!Subtarget->is64Bit() &&
15452 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
15453 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
15454 Amt.getOpcode() == ISD::BITCAST &&
15455 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
15456 Amt = Amt.getOperand(0);
15457 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
15458 VT.getVectorNumElements();
15459 std::vector<SDValue> Vals(Ratio);
15460 for (unsigned i = 0; i != Ratio; ++i)
15461 Vals[i] = Amt.getOperand(i);
15462 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
15463 for (unsigned j = 0; j != Ratio; ++j)
15464 if (Vals[j] != Amt.getOperand(i + j))
15467 switch (Op.getOpcode()) {
15469 llvm_unreachable("Unknown shift opcode!");
15471 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
15473 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
15475 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
15482 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
15483 SelectionDAG &DAG) {
15484 MVT VT = Op.getSimpleValueType();
15486 SDValue R = Op.getOperand(0);
15487 SDValue Amt = Op.getOperand(1);
15490 assert(VT.isVector() && "Custom lowering only for vector shifts!");
15491 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
15493 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
15497 V = LowerScalarVariableShift(Op, DAG, Subtarget);
15501 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
15503 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
15504 if (Subtarget->hasInt256()) {
15505 if (Op.getOpcode() == ISD::SRL &&
15506 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
15507 VT == MVT::v4i64 || VT == MVT::v8i32))
15509 if (Op.getOpcode() == ISD::SHL &&
15510 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
15511 VT == MVT::v4i64 || VT == MVT::v8i32))
15513 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
15517 // If possible, lower this packed shift into a vector multiply instead of
15518 // expanding it into a sequence of scalar shifts.
15519 // Do this only if the vector shift count is a constant build_vector.
15520 if (Op.getOpcode() == ISD::SHL &&
15521 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
15522 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
15523 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
15524 SmallVector<SDValue, 8> Elts;
15525 EVT SVT = VT.getScalarType();
15526 unsigned SVTBits = SVT.getSizeInBits();
15527 const APInt &One = APInt(SVTBits, 1);
15528 unsigned NumElems = VT.getVectorNumElements();
15530 for (unsigned i=0; i !=NumElems; ++i) {
15531 SDValue Op = Amt->getOperand(i);
15532 if (Op->getOpcode() == ISD::UNDEF) {
15533 Elts.push_back(Op);
15537 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
15538 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
15539 uint64_t ShAmt = C.getZExtValue();
15540 if (ShAmt >= SVTBits) {
15541 Elts.push_back(DAG.getUNDEF(SVT));
15544 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
15546 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15547 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
15550 // Lower SHL with variable shift amount.
15551 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
15552 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
15554 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
15555 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
15556 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
15557 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
15560 // If possible, lower this shift as a sequence of two shifts by
15561 // constant plus a MOVSS/MOVSD instead of scalarizing it.
15563 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
15565 // Could be rewritten as:
15566 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
15568 // The advantage is that the two shifts from the example would be
15569 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
15570 // the vector shift into four scalar shifts plus four pairs of vector
15572 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
15573 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
15574 unsigned TargetOpcode = X86ISD::MOVSS;
15575 bool CanBeSimplified;
15576 // The splat value for the first packed shift (the 'X' from the example).
15577 SDValue Amt1 = Amt->getOperand(0);
15578 // The splat value for the second packed shift (the 'Y' from the example).
15579 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
15580 Amt->getOperand(2);
15582 // See if it is possible to replace this node with a sequence of
15583 // two shifts followed by a MOVSS/MOVSD
15584 if (VT == MVT::v4i32) {
15585 // Check if it is legal to use a MOVSS.
15586 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
15587 Amt2 == Amt->getOperand(3);
15588 if (!CanBeSimplified) {
15589 // Otherwise, check if we can still simplify this node using a MOVSD.
15590 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
15591 Amt->getOperand(2) == Amt->getOperand(3);
15592 TargetOpcode = X86ISD::MOVSD;
15593 Amt2 = Amt->getOperand(2);
15596 // Do similar checks for the case where the machine value type
15598 CanBeSimplified = Amt1 == Amt->getOperand(1);
15599 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
15600 CanBeSimplified = Amt2 == Amt->getOperand(i);
15602 if (!CanBeSimplified) {
15603 TargetOpcode = X86ISD::MOVSD;
15604 CanBeSimplified = true;
15605 Amt2 = Amt->getOperand(4);
15606 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
15607 CanBeSimplified = Amt1 == Amt->getOperand(i);
15608 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
15609 CanBeSimplified = Amt2 == Amt->getOperand(j);
15613 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
15614 isa<ConstantSDNode>(Amt2)) {
15615 // Replace this node with two shifts followed by a MOVSS/MOVSD.
15616 EVT CastVT = MVT::v4i32;
15618 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
15619 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
15621 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
15622 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
15623 if (TargetOpcode == X86ISD::MOVSD)
15624 CastVT = MVT::v2i64;
15625 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
15626 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
15627 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
15629 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15633 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
15634 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
15637 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
15638 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
15640 // Turn 'a' into a mask suitable for VSELECT
15641 SDValue VSelM = DAG.getConstant(0x80, VT);
15642 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
15643 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
15645 SDValue CM1 = DAG.getConstant(0x0f, VT);
15646 SDValue CM2 = DAG.getConstant(0x3f, VT);
15648 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
15649 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
15650 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
15651 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
15652 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
15655 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
15656 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
15657 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
15659 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
15660 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
15661 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
15662 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
15663 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
15666 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
15667 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
15668 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
15670 // return VSELECT(r, r+r, a);
15671 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
15672 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
15676 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
15677 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
15678 // solution better.
15679 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
15680 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
15682 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
15683 R = DAG.getNode(ExtOpc, dl, NewVT, R);
15684 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
15685 return DAG.getNode(ISD::TRUNCATE, dl, VT,
15686 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
15689 // Decompose 256-bit shifts into smaller 128-bit shifts.
15690 if (VT.is256BitVector()) {
15691 unsigned NumElems = VT.getVectorNumElements();
15692 MVT EltVT = VT.getVectorElementType();
15693 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15695 // Extract the two vectors
15696 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
15697 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
15699 // Recreate the shift amount vectors
15700 SDValue Amt1, Amt2;
15701 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
15702 // Constant shift amount
15703 SmallVector<SDValue, 4> Amt1Csts;
15704 SmallVector<SDValue, 4> Amt2Csts;
15705 for (unsigned i = 0; i != NumElems/2; ++i)
15706 Amt1Csts.push_back(Amt->getOperand(i));
15707 for (unsigned i = NumElems/2; i != NumElems; ++i)
15708 Amt2Csts.push_back(Amt->getOperand(i));
15710 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
15711 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
15713 // Variable shift amount
15714 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
15715 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
15718 // Issue new vector shifts for the smaller types
15719 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
15720 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
15722 // Concatenate the result back
15723 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
15729 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
15730 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
15731 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
15732 // looks for this combo and may remove the "setcc" instruction if the "setcc"
15733 // has only one use.
15734 SDNode *N = Op.getNode();
15735 SDValue LHS = N->getOperand(0);
15736 SDValue RHS = N->getOperand(1);
15737 unsigned BaseOp = 0;
15740 switch (Op.getOpcode()) {
15741 default: llvm_unreachable("Unknown ovf instruction!");
15743 // A subtract of one will be selected as a INC. Note that INC doesn't
15744 // set CF, so we can't do this for UADDO.
15745 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15747 BaseOp = X86ISD::INC;
15748 Cond = X86::COND_O;
15751 BaseOp = X86ISD::ADD;
15752 Cond = X86::COND_O;
15755 BaseOp = X86ISD::ADD;
15756 Cond = X86::COND_B;
15759 // A subtract of one will be selected as a DEC. Note that DEC doesn't
15760 // set CF, so we can't do this for USUBO.
15761 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15763 BaseOp = X86ISD::DEC;
15764 Cond = X86::COND_O;
15767 BaseOp = X86ISD::SUB;
15768 Cond = X86::COND_O;
15771 BaseOp = X86ISD::SUB;
15772 Cond = X86::COND_B;
15775 BaseOp = X86ISD::SMUL;
15776 Cond = X86::COND_O;
15778 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
15779 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
15781 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
15784 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
15785 DAG.getConstant(X86::COND_O, MVT::i32),
15786 SDValue(Sum.getNode(), 2));
15788 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
15792 // Also sets EFLAGS.
15793 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
15794 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
15797 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
15798 DAG.getConstant(Cond, MVT::i32),
15799 SDValue(Sum.getNode(), 1));
15801 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
15804 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
15805 SelectionDAG &DAG) const {
15807 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
15808 MVT VT = Op.getSimpleValueType();
15810 if (!Subtarget->hasSSE2() || !VT.isVector())
15813 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
15814 ExtraVT.getScalarType().getSizeInBits();
15816 switch (VT.SimpleTy) {
15817 default: return SDValue();
15820 if (!Subtarget->hasFp256())
15822 if (!Subtarget->hasInt256()) {
15823 // needs to be split
15824 unsigned NumElems = VT.getVectorNumElements();
15826 // Extract the LHS vectors
15827 SDValue LHS = Op.getOperand(0);
15828 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15829 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15831 MVT EltVT = VT.getVectorElementType();
15832 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15834 EVT ExtraEltVT = ExtraVT.getVectorElementType();
15835 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
15836 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
15838 SDValue Extra = DAG.getValueType(ExtraVT);
15840 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
15841 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
15843 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
15848 SDValue Op0 = Op.getOperand(0);
15849 SDValue Op00 = Op0.getOperand(0);
15851 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
15852 if (Op0.getOpcode() == ISD::BITCAST &&
15853 Op00.getOpcode() == ISD::VECTOR_SHUFFLE) {
15854 // (sext (vzext x)) -> (vsext x)
15855 Tmp1 = LowerVectorIntExtend(Op00, Subtarget, DAG);
15856 if (Tmp1.getNode()) {
15857 EVT ExtraEltVT = ExtraVT.getVectorElementType();
15858 // This folding is only valid when the in-reg type is a vector of i8,
15860 if (ExtraEltVT == MVT::i8 || ExtraEltVT == MVT::i16 ||
15861 ExtraEltVT == MVT::i32) {
15862 SDValue Tmp1Op0 = Tmp1.getOperand(0);
15863 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
15864 "This optimization is invalid without a VZEXT.");
15865 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
15871 // If the above didn't work, then just use Shift-Left + Shift-Right.
15872 Tmp1 = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0, BitsDiff,
15874 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Tmp1, BitsDiff,
15880 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
15881 SelectionDAG &DAG) {
15883 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
15884 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
15885 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
15886 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
15888 // The only fence that needs an instruction is a sequentially-consistent
15889 // cross-thread fence.
15890 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
15891 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
15892 // no-sse2). There isn't any reason to disable it if the target processor
15894 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
15895 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
15897 SDValue Chain = Op.getOperand(0);
15898 SDValue Zero = DAG.getConstant(0, MVT::i32);
15900 DAG.getRegister(X86::ESP, MVT::i32), // Base
15901 DAG.getTargetConstant(1, MVT::i8), // Scale
15902 DAG.getRegister(0, MVT::i32), // Index
15903 DAG.getTargetConstant(0, MVT::i32), // Disp
15904 DAG.getRegister(0, MVT::i32), // Segment.
15908 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
15909 return SDValue(Res, 0);
15912 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
15913 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
15916 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
15917 SelectionDAG &DAG) {
15918 MVT T = Op.getSimpleValueType();
15922 switch(T.SimpleTy) {
15923 default: llvm_unreachable("Invalid value type!");
15924 case MVT::i8: Reg = X86::AL; size = 1; break;
15925 case MVT::i16: Reg = X86::AX; size = 2; break;
15926 case MVT::i32: Reg = X86::EAX; size = 4; break;
15928 assert(Subtarget->is64Bit() && "Node not type legal!");
15929 Reg = X86::RAX; size = 8;
15932 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
15933 Op.getOperand(2), SDValue());
15934 SDValue Ops[] = { cpIn.getValue(0),
15937 DAG.getTargetConstant(size, MVT::i8),
15938 cpIn.getValue(1) };
15939 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15940 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
15941 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
15945 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
15946 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
15947 MVT::i32, cpOut.getValue(2));
15948 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
15949 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
15951 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
15952 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
15953 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
15957 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
15958 SelectionDAG &DAG) {
15959 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
15960 MVT DstVT = Op.getSimpleValueType();
15962 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
15963 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
15964 if (DstVT != MVT::f64)
15965 // This conversion needs to be expanded.
15968 SDValue InVec = Op->getOperand(0);
15970 unsigned NumElts = SrcVT.getVectorNumElements();
15971 EVT SVT = SrcVT.getVectorElementType();
15973 // Widen the vector in input in the case of MVT::v2i32.
15974 // Example: from MVT::v2i32 to MVT::v4i32.
15975 SmallVector<SDValue, 16> Elts;
15976 for (unsigned i = 0, e = NumElts; i != e; ++i)
15977 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
15978 DAG.getIntPtrConstant(i)));
15980 // Explicitly mark the extra elements as Undef.
15981 SDValue Undef = DAG.getUNDEF(SVT);
15982 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
15983 Elts.push_back(Undef);
15985 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
15986 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
15987 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
15988 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
15989 DAG.getIntPtrConstant(0));
15992 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
15993 Subtarget->hasMMX() && "Unexpected custom BITCAST");
15994 assert((DstVT == MVT::i64 ||
15995 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
15996 "Unexpected custom BITCAST");
15997 // i64 <=> MMX conversions are Legal.
15998 if (SrcVT==MVT::i64 && DstVT.isVector())
16000 if (DstVT==MVT::i64 && SrcVT.isVector())
16002 // MMX <=> MMX conversions are Legal.
16003 if (SrcVT.isVector() && DstVT.isVector())
16005 // All other conversions need to be expanded.
16009 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
16010 SDNode *Node = Op.getNode();
16012 EVT T = Node->getValueType(0);
16013 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
16014 DAG.getConstant(0, T), Node->getOperand(2));
16015 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
16016 cast<AtomicSDNode>(Node)->getMemoryVT(),
16017 Node->getOperand(0),
16018 Node->getOperand(1), negOp,
16019 cast<AtomicSDNode>(Node)->getMemOperand(),
16020 cast<AtomicSDNode>(Node)->getOrdering(),
16021 cast<AtomicSDNode>(Node)->getSynchScope());
16024 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
16025 SDNode *Node = Op.getNode();
16027 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
16029 // Convert seq_cst store -> xchg
16030 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
16031 // FIXME: On 32-bit, store -> fist or movq would be more efficient
16032 // (The only way to get a 16-byte store is cmpxchg16b)
16033 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
16034 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
16035 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
16036 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
16037 cast<AtomicSDNode>(Node)->getMemoryVT(),
16038 Node->getOperand(0),
16039 Node->getOperand(1), Node->getOperand(2),
16040 cast<AtomicSDNode>(Node)->getMemOperand(),
16041 cast<AtomicSDNode>(Node)->getOrdering(),
16042 cast<AtomicSDNode>(Node)->getSynchScope());
16043 return Swap.getValue(1);
16045 // Other atomic stores have a simple pattern.
16049 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
16050 EVT VT = Op.getNode()->getSimpleValueType(0);
16052 // Let legalize expand this if it isn't a legal type yet.
16053 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
16056 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16059 bool ExtraOp = false;
16060 switch (Op.getOpcode()) {
16061 default: llvm_unreachable("Invalid code");
16062 case ISD::ADDC: Opc = X86ISD::ADD; break;
16063 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
16064 case ISD::SUBC: Opc = X86ISD::SUB; break;
16065 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
16069 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
16071 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
16072 Op.getOperand(1), Op.getOperand(2));
16075 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
16076 SelectionDAG &DAG) {
16077 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
16079 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
16080 // which returns the values as { float, float } (in XMM0) or
16081 // { double, double } (which is returned in XMM0, XMM1).
16083 SDValue Arg = Op.getOperand(0);
16084 EVT ArgVT = Arg.getValueType();
16085 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16087 TargetLowering::ArgListTy Args;
16088 TargetLowering::ArgListEntry Entry;
16092 Entry.isSExt = false;
16093 Entry.isZExt = false;
16094 Args.push_back(Entry);
16096 bool isF64 = ArgVT == MVT::f64;
16097 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
16098 // the small struct {f32, f32} is returned in (eax, edx). For f64,
16099 // the results are returned via SRet in memory.
16100 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
16101 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16102 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
16104 Type *RetTy = isF64
16105 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
16106 : (Type*)VectorType::get(ArgTy, 4);
16108 TargetLowering::CallLoweringInfo CLI(DAG);
16109 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
16110 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
16112 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
16115 // Returned in xmm0 and xmm1.
16116 return CallResult.first;
16118 // Returned in bits 0:31 and 32:64 xmm0.
16119 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
16120 CallResult.first, DAG.getIntPtrConstant(0));
16121 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
16122 CallResult.first, DAG.getIntPtrConstant(1));
16123 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
16124 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
16127 /// LowerOperation - Provide custom lowering hooks for some operations.
16129 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
16130 switch (Op.getOpcode()) {
16131 default: llvm_unreachable("Should not custom lower this!");
16132 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
16133 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
16134 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
16135 return LowerCMP_SWAP(Op, Subtarget, DAG);
16136 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
16137 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
16138 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
16139 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
16140 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
16141 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
16142 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
16143 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
16144 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
16145 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
16146 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
16147 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
16148 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
16149 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
16150 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
16151 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
16152 case ISD::SHL_PARTS:
16153 case ISD::SRA_PARTS:
16154 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
16155 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
16156 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
16157 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
16158 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
16159 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
16160 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
16161 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
16162 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
16163 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
16164 case ISD::FABS: return LowerFABS(Op, DAG);
16165 case ISD::FNEG: return LowerFNEG(Op, DAG);
16166 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
16167 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
16168 case ISD::SETCC: return LowerSETCC(Op, DAG);
16169 case ISD::SELECT: return LowerSELECT(Op, DAG);
16170 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
16171 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
16172 case ISD::VASTART: return LowerVASTART(Op, DAG);
16173 case ISD::VAARG: return LowerVAARG(Op, DAG);
16174 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
16175 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
16176 case ISD::INTRINSIC_VOID:
16177 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
16178 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
16179 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
16180 case ISD::FRAME_TO_ARGS_OFFSET:
16181 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
16182 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
16183 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
16184 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
16185 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
16186 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
16187 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
16188 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
16189 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
16190 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
16191 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
16192 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
16193 case ISD::UMUL_LOHI:
16194 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
16197 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
16203 case ISD::UMULO: return LowerXALUO(Op, DAG);
16204 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
16205 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
16209 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
16210 case ISD::ADD: return LowerADD(Op, DAG);
16211 case ISD::SUB: return LowerSUB(Op, DAG);
16212 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
16216 static void ReplaceATOMIC_LOAD(SDNode *Node,
16217 SmallVectorImpl<SDValue> &Results,
16218 SelectionDAG &DAG) {
16220 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
16222 // Convert wide load -> cmpxchg8b/cmpxchg16b
16223 // FIXME: On 32-bit, load -> fild or movq would be more efficient
16224 // (The only way to get a 16-byte load is cmpxchg16b)
16225 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
16226 SDValue Zero = DAG.getConstant(0, VT);
16227 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
16229 DAG.getAtomicCmpSwap(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, VT, VTs,
16230 Node->getOperand(0), Node->getOperand(1), Zero, Zero,
16231 cast<AtomicSDNode>(Node)->getMemOperand(),
16232 cast<AtomicSDNode>(Node)->getOrdering(),
16233 cast<AtomicSDNode>(Node)->getOrdering(),
16234 cast<AtomicSDNode>(Node)->getSynchScope());
16235 Results.push_back(Swap.getValue(0));
16236 Results.push_back(Swap.getValue(2));
16239 /// ReplaceNodeResults - Replace a node with an illegal result type
16240 /// with a new node built out of custom code.
16241 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
16242 SmallVectorImpl<SDValue>&Results,
16243 SelectionDAG &DAG) const {
16245 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16246 switch (N->getOpcode()) {
16248 llvm_unreachable("Do not know how to custom type legalize this operation!");
16249 case ISD::SIGN_EXTEND_INREG:
16254 // We don't want to expand or promote these.
16261 case ISD::UDIVREM: {
16262 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
16263 Results.push_back(V);
16266 case ISD::FP_TO_SINT:
16267 case ISD::FP_TO_UINT: {
16268 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
16270 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
16273 std::pair<SDValue,SDValue> Vals =
16274 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
16275 SDValue FIST = Vals.first, StackSlot = Vals.second;
16276 if (FIST.getNode()) {
16277 EVT VT = N->getValueType(0);
16278 // Return a load from the stack slot.
16279 if (StackSlot.getNode())
16280 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
16281 MachinePointerInfo(),
16282 false, false, false, 0));
16284 Results.push_back(FIST);
16288 case ISD::UINT_TO_FP: {
16289 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
16290 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
16291 N->getValueType(0) != MVT::v2f32)
16293 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
16295 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
16297 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
16298 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
16299 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
16300 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
16301 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
16302 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
16305 case ISD::FP_ROUND: {
16306 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
16308 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
16309 Results.push_back(V);
16312 case ISD::INTRINSIC_W_CHAIN: {
16313 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
16315 default : llvm_unreachable("Do not know how to custom type "
16316 "legalize this intrinsic operation!");
16317 case Intrinsic::x86_rdtsc:
16318 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
16320 case Intrinsic::x86_rdtscp:
16321 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
16323 case Intrinsic::x86_rdpmc:
16324 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
16327 case ISD::READCYCLECOUNTER: {
16328 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
16331 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
16332 EVT T = N->getValueType(0);
16333 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
16334 bool Regs64bit = T == MVT::i128;
16335 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
16336 SDValue cpInL, cpInH;
16337 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
16338 DAG.getConstant(0, HalfT));
16339 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
16340 DAG.getConstant(1, HalfT));
16341 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
16342 Regs64bit ? X86::RAX : X86::EAX,
16344 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
16345 Regs64bit ? X86::RDX : X86::EDX,
16346 cpInH, cpInL.getValue(1));
16347 SDValue swapInL, swapInH;
16348 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
16349 DAG.getConstant(0, HalfT));
16350 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
16351 DAG.getConstant(1, HalfT));
16352 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
16353 Regs64bit ? X86::RBX : X86::EBX,
16354 swapInL, cpInH.getValue(1));
16355 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
16356 Regs64bit ? X86::RCX : X86::ECX,
16357 swapInH, swapInL.getValue(1));
16358 SDValue Ops[] = { swapInH.getValue(0),
16360 swapInH.getValue(1) };
16361 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16362 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
16363 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
16364 X86ISD::LCMPXCHG8_DAG;
16365 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
16366 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
16367 Regs64bit ? X86::RAX : X86::EAX,
16368 HalfT, Result.getValue(1));
16369 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
16370 Regs64bit ? X86::RDX : X86::EDX,
16371 HalfT, cpOutL.getValue(2));
16372 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
16374 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
16375 MVT::i32, cpOutH.getValue(2));
16377 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16378 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
16379 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
16381 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
16382 Results.push_back(Success);
16383 Results.push_back(EFLAGS.getValue(1));
16386 case ISD::ATOMIC_SWAP:
16387 case ISD::ATOMIC_LOAD_ADD:
16388 case ISD::ATOMIC_LOAD_SUB:
16389 case ISD::ATOMIC_LOAD_AND:
16390 case ISD::ATOMIC_LOAD_OR:
16391 case ISD::ATOMIC_LOAD_XOR:
16392 case ISD::ATOMIC_LOAD_NAND:
16393 case ISD::ATOMIC_LOAD_MIN:
16394 case ISD::ATOMIC_LOAD_MAX:
16395 case ISD::ATOMIC_LOAD_UMIN:
16396 case ISD::ATOMIC_LOAD_UMAX:
16397 // Delegate to generic TypeLegalization. Situations we can really handle
16398 // should have already been dealt with by X86AtomicExpand.cpp.
16400 case ISD::ATOMIC_LOAD: {
16401 ReplaceATOMIC_LOAD(N, Results, DAG);
16404 case ISD::BITCAST: {
16405 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
16406 EVT DstVT = N->getValueType(0);
16407 EVT SrcVT = N->getOperand(0)->getValueType(0);
16409 if (SrcVT != MVT::f64 ||
16410 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
16413 unsigned NumElts = DstVT.getVectorNumElements();
16414 EVT SVT = DstVT.getVectorElementType();
16415 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
16416 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
16417 MVT::v2f64, N->getOperand(0));
16418 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
16420 if (ExperimentalVectorWideningLegalization) {
16421 // If we are legalizing vectors by widening, we already have the desired
16422 // legal vector type, just return it.
16423 Results.push_back(ToVecInt);
16427 SmallVector<SDValue, 8> Elts;
16428 for (unsigned i = 0, e = NumElts; i != e; ++i)
16429 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
16430 ToVecInt, DAG.getIntPtrConstant(i)));
16432 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
16437 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
16439 default: return nullptr;
16440 case X86ISD::BSF: return "X86ISD::BSF";
16441 case X86ISD::BSR: return "X86ISD::BSR";
16442 case X86ISD::SHLD: return "X86ISD::SHLD";
16443 case X86ISD::SHRD: return "X86ISD::SHRD";
16444 case X86ISD::FAND: return "X86ISD::FAND";
16445 case X86ISD::FANDN: return "X86ISD::FANDN";
16446 case X86ISD::FOR: return "X86ISD::FOR";
16447 case X86ISD::FXOR: return "X86ISD::FXOR";
16448 case X86ISD::FSRL: return "X86ISD::FSRL";
16449 case X86ISD::FILD: return "X86ISD::FILD";
16450 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
16451 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
16452 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
16453 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
16454 case X86ISD::FLD: return "X86ISD::FLD";
16455 case X86ISD::FST: return "X86ISD::FST";
16456 case X86ISD::CALL: return "X86ISD::CALL";
16457 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
16458 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
16459 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
16460 case X86ISD::BT: return "X86ISD::BT";
16461 case X86ISD::CMP: return "X86ISD::CMP";
16462 case X86ISD::COMI: return "X86ISD::COMI";
16463 case X86ISD::UCOMI: return "X86ISD::UCOMI";
16464 case X86ISD::CMPM: return "X86ISD::CMPM";
16465 case X86ISD::CMPMU: return "X86ISD::CMPMU";
16466 case X86ISD::SETCC: return "X86ISD::SETCC";
16467 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
16468 case X86ISD::FSETCC: return "X86ISD::FSETCC";
16469 case X86ISD::CMOV: return "X86ISD::CMOV";
16470 case X86ISD::BRCOND: return "X86ISD::BRCOND";
16471 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
16472 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
16473 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
16474 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
16475 case X86ISD::Wrapper: return "X86ISD::Wrapper";
16476 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
16477 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
16478 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
16479 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
16480 case X86ISD::PINSRB: return "X86ISD::PINSRB";
16481 case X86ISD::PINSRW: return "X86ISD::PINSRW";
16482 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
16483 case X86ISD::ANDNP: return "X86ISD::ANDNP";
16484 case X86ISD::PSIGN: return "X86ISD::PSIGN";
16485 case X86ISD::BLENDV: return "X86ISD::BLENDV";
16486 case X86ISD::BLENDI: return "X86ISD::BLENDI";
16487 case X86ISD::SUBUS: return "X86ISD::SUBUS";
16488 case X86ISD::HADD: return "X86ISD::HADD";
16489 case X86ISD::HSUB: return "X86ISD::HSUB";
16490 case X86ISD::FHADD: return "X86ISD::FHADD";
16491 case X86ISD::FHSUB: return "X86ISD::FHSUB";
16492 case X86ISD::UMAX: return "X86ISD::UMAX";
16493 case X86ISD::UMIN: return "X86ISD::UMIN";
16494 case X86ISD::SMAX: return "X86ISD::SMAX";
16495 case X86ISD::SMIN: return "X86ISD::SMIN";
16496 case X86ISD::FMAX: return "X86ISD::FMAX";
16497 case X86ISD::FMIN: return "X86ISD::FMIN";
16498 case X86ISD::FMAXC: return "X86ISD::FMAXC";
16499 case X86ISD::FMINC: return "X86ISD::FMINC";
16500 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
16501 case X86ISD::FRCP: return "X86ISD::FRCP";
16502 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
16503 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
16504 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
16505 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
16506 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
16507 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
16508 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
16509 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
16510 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
16511 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
16512 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
16513 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
16514 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
16515 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
16516 case X86ISD::VZEXT: return "X86ISD::VZEXT";
16517 case X86ISD::VSEXT: return "X86ISD::VSEXT";
16518 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
16519 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
16520 case X86ISD::VINSERT: return "X86ISD::VINSERT";
16521 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
16522 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
16523 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
16524 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
16525 case X86ISD::VSHL: return "X86ISD::VSHL";
16526 case X86ISD::VSRL: return "X86ISD::VSRL";
16527 case X86ISD::VSRA: return "X86ISD::VSRA";
16528 case X86ISD::VSHLI: return "X86ISD::VSHLI";
16529 case X86ISD::VSRLI: return "X86ISD::VSRLI";
16530 case X86ISD::VSRAI: return "X86ISD::VSRAI";
16531 case X86ISD::CMPP: return "X86ISD::CMPP";
16532 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
16533 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
16534 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
16535 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
16536 case X86ISD::ADD: return "X86ISD::ADD";
16537 case X86ISD::SUB: return "X86ISD::SUB";
16538 case X86ISD::ADC: return "X86ISD::ADC";
16539 case X86ISD::SBB: return "X86ISD::SBB";
16540 case X86ISD::SMUL: return "X86ISD::SMUL";
16541 case X86ISD::UMUL: return "X86ISD::UMUL";
16542 case X86ISD::INC: return "X86ISD::INC";
16543 case X86ISD::DEC: return "X86ISD::DEC";
16544 case X86ISD::OR: return "X86ISD::OR";
16545 case X86ISD::XOR: return "X86ISD::XOR";
16546 case X86ISD::AND: return "X86ISD::AND";
16547 case X86ISD::BEXTR: return "X86ISD::BEXTR";
16548 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
16549 case X86ISD::PTEST: return "X86ISD::PTEST";
16550 case X86ISD::TESTP: return "X86ISD::TESTP";
16551 case X86ISD::TESTM: return "X86ISD::TESTM";
16552 case X86ISD::TESTNM: return "X86ISD::TESTNM";
16553 case X86ISD::KORTEST: return "X86ISD::KORTEST";
16554 case X86ISD::PACKSS: return "X86ISD::PACKSS";
16555 case X86ISD::PACKUS: return "X86ISD::PACKUS";
16556 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
16557 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
16558 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
16559 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
16560 case X86ISD::SHUFP: return "X86ISD::SHUFP";
16561 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
16562 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
16563 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
16564 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
16565 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
16566 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
16567 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
16568 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
16569 case X86ISD::MOVSD: return "X86ISD::MOVSD";
16570 case X86ISD::MOVSS: return "X86ISD::MOVSS";
16571 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
16572 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
16573 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
16574 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
16575 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
16576 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
16577 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
16578 case X86ISD::VPERMV: return "X86ISD::VPERMV";
16579 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
16580 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
16581 case X86ISD::VPERMI: return "X86ISD::VPERMI";
16582 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
16583 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
16584 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
16585 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
16586 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
16587 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
16588 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
16589 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
16590 case X86ISD::SAHF: return "X86ISD::SAHF";
16591 case X86ISD::RDRAND: return "X86ISD::RDRAND";
16592 case X86ISD::RDSEED: return "X86ISD::RDSEED";
16593 case X86ISD::FMADD: return "X86ISD::FMADD";
16594 case X86ISD::FMSUB: return "X86ISD::FMSUB";
16595 case X86ISD::FNMADD: return "X86ISD::FNMADD";
16596 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
16597 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
16598 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
16599 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
16600 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
16601 case X86ISD::XTEST: return "X86ISD::XTEST";
16605 // isLegalAddressingMode - Return true if the addressing mode represented
16606 // by AM is legal for this target, for a load/store of the specified type.
16607 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
16609 // X86 supports extremely general addressing modes.
16610 CodeModel::Model M = getTargetMachine().getCodeModel();
16611 Reloc::Model R = getTargetMachine().getRelocationModel();
16613 // X86 allows a sign-extended 32-bit immediate field as a displacement.
16614 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
16619 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
16621 // If a reference to this global requires an extra load, we can't fold it.
16622 if (isGlobalStubReference(GVFlags))
16625 // If BaseGV requires a register for the PIC base, we cannot also have a
16626 // BaseReg specified.
16627 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
16630 // If lower 4G is not available, then we must use rip-relative addressing.
16631 if ((M != CodeModel::Small || R != Reloc::Static) &&
16632 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
16636 switch (AM.Scale) {
16642 // These scales always work.
16647 // These scales are formed with basereg+scalereg. Only accept if there is
16652 default: // Other stuff never works.
16659 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
16660 unsigned Bits = Ty->getScalarSizeInBits();
16662 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
16663 // particularly cheaper than those without.
16667 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
16668 // variable shifts just as cheap as scalar ones.
16669 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
16672 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
16673 // fully general vector.
16677 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
16678 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
16680 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
16681 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
16682 return NumBits1 > NumBits2;
16685 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
16686 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
16689 if (!isTypeLegal(EVT::getEVT(Ty1)))
16692 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
16694 // Assuming the caller doesn't have a zeroext or signext return parameter,
16695 // truncation all the way down to i1 is valid.
16699 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
16700 return isInt<32>(Imm);
16703 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
16704 // Can also use sub to handle negated immediates.
16705 return isInt<32>(Imm);
16708 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
16709 if (!VT1.isInteger() || !VT2.isInteger())
16711 unsigned NumBits1 = VT1.getSizeInBits();
16712 unsigned NumBits2 = VT2.getSizeInBits();
16713 return NumBits1 > NumBits2;
16716 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
16717 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
16718 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
16721 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
16722 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
16723 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
16726 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
16727 EVT VT1 = Val.getValueType();
16728 if (isZExtFree(VT1, VT2))
16731 if (Val.getOpcode() != ISD::LOAD)
16734 if (!VT1.isSimple() || !VT1.isInteger() ||
16735 !VT2.isSimple() || !VT2.isInteger())
16738 switch (VT1.getSimpleVT().SimpleTy) {
16743 // X86 has 8, 16, and 32-bit zero-extending loads.
16751 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
16752 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
16755 VT = VT.getScalarType();
16757 if (!VT.isSimple())
16760 switch (VT.getSimpleVT().SimpleTy) {
16771 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
16772 // i16 instructions are longer (0x66 prefix) and potentially slower.
16773 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
16776 /// isShuffleMaskLegal - Targets can use this to indicate that they only
16777 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
16778 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
16779 /// are assumed to be legal.
16781 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
16783 if (!VT.isSimple())
16786 MVT SVT = VT.getSimpleVT();
16788 // Very little shuffling can be done for 64-bit vectors right now.
16789 if (VT.getSizeInBits() == 64)
16792 // If this is a single-input shuffle with no 128 bit lane crossings we can
16793 // lower it into pshufb.
16794 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
16795 (SVT.is256BitVector() && Subtarget->hasInt256())) {
16796 bool isLegal = true;
16797 for (unsigned I = 0, E = M.size(); I != E; ++I) {
16798 if (M[I] >= (int)SVT.getVectorNumElements() ||
16799 ShuffleCrosses128bitLane(SVT, I, M[I])) {
16808 // FIXME: blends, shifts.
16809 return (SVT.getVectorNumElements() == 2 ||
16810 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
16811 isMOVLMask(M, SVT) ||
16812 isSHUFPMask(M, SVT) ||
16813 isPSHUFDMask(M, SVT) ||
16814 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
16815 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
16816 isPALIGNRMask(M, SVT, Subtarget) ||
16817 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
16818 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
16819 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
16820 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
16821 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
16825 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
16827 if (!VT.isSimple())
16830 MVT SVT = VT.getSimpleVT();
16831 unsigned NumElts = SVT.getVectorNumElements();
16832 // FIXME: This collection of masks seems suspect.
16835 if (NumElts == 4 && SVT.is128BitVector()) {
16836 return (isMOVLMask(Mask, SVT) ||
16837 isCommutedMOVLMask(Mask, SVT, true) ||
16838 isSHUFPMask(Mask, SVT) ||
16839 isSHUFPMask(Mask, SVT, /* Commuted */ true));
16844 //===----------------------------------------------------------------------===//
16845 // X86 Scheduler Hooks
16846 //===----------------------------------------------------------------------===//
16848 /// Utility function to emit xbegin specifying the start of an RTM region.
16849 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
16850 const TargetInstrInfo *TII) {
16851 DebugLoc DL = MI->getDebugLoc();
16853 const BasicBlock *BB = MBB->getBasicBlock();
16854 MachineFunction::iterator I = MBB;
16857 // For the v = xbegin(), we generate
16868 MachineBasicBlock *thisMBB = MBB;
16869 MachineFunction *MF = MBB->getParent();
16870 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
16871 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
16872 MF->insert(I, mainMBB);
16873 MF->insert(I, sinkMBB);
16875 // Transfer the remainder of BB and its successor edges to sinkMBB.
16876 sinkMBB->splice(sinkMBB->begin(), MBB,
16877 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
16878 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
16882 // # fallthrough to mainMBB
16883 // # abortion to sinkMBB
16884 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
16885 thisMBB->addSuccessor(mainMBB);
16886 thisMBB->addSuccessor(sinkMBB);
16890 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
16891 mainMBB->addSuccessor(sinkMBB);
16894 // EAX is live into the sinkMBB
16895 sinkMBB->addLiveIn(X86::EAX);
16896 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
16897 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
16900 MI->eraseFromParent();
16904 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
16905 // or XMM0_V32I8 in AVX all of this code can be replaced with that
16906 // in the .td file.
16907 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
16908 const TargetInstrInfo *TII) {
16910 switch (MI->getOpcode()) {
16911 default: llvm_unreachable("illegal opcode!");
16912 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
16913 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
16914 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
16915 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
16916 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
16917 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
16918 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
16919 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
16922 DebugLoc dl = MI->getDebugLoc();
16923 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
16925 unsigned NumArgs = MI->getNumOperands();
16926 for (unsigned i = 1; i < NumArgs; ++i) {
16927 MachineOperand &Op = MI->getOperand(i);
16928 if (!(Op.isReg() && Op.isImplicit()))
16929 MIB.addOperand(Op);
16931 if (MI->hasOneMemOperand())
16932 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
16934 BuildMI(*BB, MI, dl,
16935 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
16936 .addReg(X86::XMM0);
16938 MI->eraseFromParent();
16942 // FIXME: Custom handling because TableGen doesn't support multiple implicit
16943 // defs in an instruction pattern
16944 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
16945 const TargetInstrInfo *TII) {
16947 switch (MI->getOpcode()) {
16948 default: llvm_unreachable("illegal opcode!");
16949 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
16950 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
16951 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
16952 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
16953 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
16954 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
16955 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
16956 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
16959 DebugLoc dl = MI->getDebugLoc();
16960 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
16962 unsigned NumArgs = MI->getNumOperands(); // remove the results
16963 for (unsigned i = 1; i < NumArgs; ++i) {
16964 MachineOperand &Op = MI->getOperand(i);
16965 if (!(Op.isReg() && Op.isImplicit()))
16966 MIB.addOperand(Op);
16968 if (MI->hasOneMemOperand())
16969 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
16971 BuildMI(*BB, MI, dl,
16972 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
16975 MI->eraseFromParent();
16979 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
16980 const TargetInstrInfo *TII,
16981 const X86Subtarget* Subtarget) {
16982 DebugLoc dl = MI->getDebugLoc();
16984 // Address into RAX/EAX, other two args into ECX, EDX.
16985 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
16986 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
16987 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
16988 for (int i = 0; i < X86::AddrNumOperands; ++i)
16989 MIB.addOperand(MI->getOperand(i));
16991 unsigned ValOps = X86::AddrNumOperands;
16992 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
16993 .addReg(MI->getOperand(ValOps).getReg());
16994 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
16995 .addReg(MI->getOperand(ValOps+1).getReg());
16997 // The instruction doesn't actually take any operands though.
16998 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
17000 MI->eraseFromParent(); // The pseudo is gone now.
17004 MachineBasicBlock *
17005 X86TargetLowering::EmitVAARG64WithCustomInserter(
17007 MachineBasicBlock *MBB) const {
17008 // Emit va_arg instruction on X86-64.
17010 // Operands to this pseudo-instruction:
17011 // 0 ) Output : destination address (reg)
17012 // 1-5) Input : va_list address (addr, i64mem)
17013 // 6 ) ArgSize : Size (in bytes) of vararg type
17014 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
17015 // 8 ) Align : Alignment of type
17016 // 9 ) EFLAGS (implicit-def)
17018 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
17019 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
17021 unsigned DestReg = MI->getOperand(0).getReg();
17022 MachineOperand &Base = MI->getOperand(1);
17023 MachineOperand &Scale = MI->getOperand(2);
17024 MachineOperand &Index = MI->getOperand(3);
17025 MachineOperand &Disp = MI->getOperand(4);
17026 MachineOperand &Segment = MI->getOperand(5);
17027 unsigned ArgSize = MI->getOperand(6).getImm();
17028 unsigned ArgMode = MI->getOperand(7).getImm();
17029 unsigned Align = MI->getOperand(8).getImm();
17031 // Memory Reference
17032 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
17033 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
17034 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
17036 // Machine Information
17037 const TargetInstrInfo *TII = MBB->getParent()->getTarget().getInstrInfo();
17038 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
17039 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
17040 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
17041 DebugLoc DL = MI->getDebugLoc();
17043 // struct va_list {
17046 // i64 overflow_area (address)
17047 // i64 reg_save_area (address)
17049 // sizeof(va_list) = 24
17050 // alignment(va_list) = 8
17052 unsigned TotalNumIntRegs = 6;
17053 unsigned TotalNumXMMRegs = 8;
17054 bool UseGPOffset = (ArgMode == 1);
17055 bool UseFPOffset = (ArgMode == 2);
17056 unsigned MaxOffset = TotalNumIntRegs * 8 +
17057 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
17059 /* Align ArgSize to a multiple of 8 */
17060 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
17061 bool NeedsAlign = (Align > 8);
17063 MachineBasicBlock *thisMBB = MBB;
17064 MachineBasicBlock *overflowMBB;
17065 MachineBasicBlock *offsetMBB;
17066 MachineBasicBlock *endMBB;
17068 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
17069 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
17070 unsigned OffsetReg = 0;
17072 if (!UseGPOffset && !UseFPOffset) {
17073 // If we only pull from the overflow region, we don't create a branch.
17074 // We don't need to alter control flow.
17075 OffsetDestReg = 0; // unused
17076 OverflowDestReg = DestReg;
17078 offsetMBB = nullptr;
17079 overflowMBB = thisMBB;
17082 // First emit code to check if gp_offset (or fp_offset) is below the bound.
17083 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
17084 // If not, pull from overflow_area. (branch to overflowMBB)
17089 // offsetMBB overflowMBB
17094 // Registers for the PHI in endMBB
17095 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
17096 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
17098 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
17099 MachineFunction *MF = MBB->getParent();
17100 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17101 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17102 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17104 MachineFunction::iterator MBBIter = MBB;
17107 // Insert the new basic blocks
17108 MF->insert(MBBIter, offsetMBB);
17109 MF->insert(MBBIter, overflowMBB);
17110 MF->insert(MBBIter, endMBB);
17112 // Transfer the remainder of MBB and its successor edges to endMBB.
17113 endMBB->splice(endMBB->begin(), thisMBB,
17114 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
17115 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
17117 // Make offsetMBB and overflowMBB successors of thisMBB
17118 thisMBB->addSuccessor(offsetMBB);
17119 thisMBB->addSuccessor(overflowMBB);
17121 // endMBB is a successor of both offsetMBB and overflowMBB
17122 offsetMBB->addSuccessor(endMBB);
17123 overflowMBB->addSuccessor(endMBB);
17125 // Load the offset value into a register
17126 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
17127 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
17131 .addDisp(Disp, UseFPOffset ? 4 : 0)
17132 .addOperand(Segment)
17133 .setMemRefs(MMOBegin, MMOEnd);
17135 // Check if there is enough room left to pull this argument.
17136 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
17138 .addImm(MaxOffset + 8 - ArgSizeA8);
17140 // Branch to "overflowMBB" if offset >= max
17141 // Fall through to "offsetMBB" otherwise
17142 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
17143 .addMBB(overflowMBB);
17146 // In offsetMBB, emit code to use the reg_save_area.
17148 assert(OffsetReg != 0);
17150 // Read the reg_save_area address.
17151 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
17152 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
17157 .addOperand(Segment)
17158 .setMemRefs(MMOBegin, MMOEnd);
17160 // Zero-extend the offset
17161 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
17162 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
17165 .addImm(X86::sub_32bit);
17167 // Add the offset to the reg_save_area to get the final address.
17168 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
17169 .addReg(OffsetReg64)
17170 .addReg(RegSaveReg);
17172 // Compute the offset for the next argument
17173 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
17174 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
17176 .addImm(UseFPOffset ? 16 : 8);
17178 // Store it back into the va_list.
17179 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
17183 .addDisp(Disp, UseFPOffset ? 4 : 0)
17184 .addOperand(Segment)
17185 .addReg(NextOffsetReg)
17186 .setMemRefs(MMOBegin, MMOEnd);
17189 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
17194 // Emit code to use overflow area
17197 // Load the overflow_area address into a register.
17198 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
17199 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
17204 .addOperand(Segment)
17205 .setMemRefs(MMOBegin, MMOEnd);
17207 // If we need to align it, do so. Otherwise, just copy the address
17208 // to OverflowDestReg.
17210 // Align the overflow address
17211 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
17212 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
17214 // aligned_addr = (addr + (align-1)) & ~(align-1)
17215 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
17216 .addReg(OverflowAddrReg)
17219 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
17221 .addImm(~(uint64_t)(Align-1));
17223 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
17224 .addReg(OverflowAddrReg);
17227 // Compute the next overflow address after this argument.
17228 // (the overflow address should be kept 8-byte aligned)
17229 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
17230 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
17231 .addReg(OverflowDestReg)
17232 .addImm(ArgSizeA8);
17234 // Store the new overflow address.
17235 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
17240 .addOperand(Segment)
17241 .addReg(NextAddrReg)
17242 .setMemRefs(MMOBegin, MMOEnd);
17244 // If we branched, emit the PHI to the front of endMBB.
17246 BuildMI(*endMBB, endMBB->begin(), DL,
17247 TII->get(X86::PHI), DestReg)
17248 .addReg(OffsetDestReg).addMBB(offsetMBB)
17249 .addReg(OverflowDestReg).addMBB(overflowMBB);
17252 // Erase the pseudo instruction
17253 MI->eraseFromParent();
17258 MachineBasicBlock *
17259 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
17261 MachineBasicBlock *MBB) const {
17262 // Emit code to save XMM registers to the stack. The ABI says that the
17263 // number of registers to save is given in %al, so it's theoretically
17264 // possible to do an indirect jump trick to avoid saving all of them,
17265 // however this code takes a simpler approach and just executes all
17266 // of the stores if %al is non-zero. It's less code, and it's probably
17267 // easier on the hardware branch predictor, and stores aren't all that
17268 // expensive anyway.
17270 // Create the new basic blocks. One block contains all the XMM stores,
17271 // and one block is the final destination regardless of whether any
17272 // stores were performed.
17273 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
17274 MachineFunction *F = MBB->getParent();
17275 MachineFunction::iterator MBBIter = MBB;
17277 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
17278 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
17279 F->insert(MBBIter, XMMSaveMBB);
17280 F->insert(MBBIter, EndMBB);
17282 // Transfer the remainder of MBB and its successor edges to EndMBB.
17283 EndMBB->splice(EndMBB->begin(), MBB,
17284 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
17285 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
17287 // The original block will now fall through to the XMM save block.
17288 MBB->addSuccessor(XMMSaveMBB);
17289 // The XMMSaveMBB will fall through to the end block.
17290 XMMSaveMBB->addSuccessor(EndMBB);
17292 // Now add the instructions.
17293 const TargetInstrInfo *TII = MBB->getParent()->getTarget().getInstrInfo();
17294 DebugLoc DL = MI->getDebugLoc();
17296 unsigned CountReg = MI->getOperand(0).getReg();
17297 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
17298 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
17300 if (!Subtarget->isTargetWin64()) {
17301 // If %al is 0, branch around the XMM save block.
17302 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
17303 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
17304 MBB->addSuccessor(EndMBB);
17307 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
17308 // that was just emitted, but clearly shouldn't be "saved".
17309 assert((MI->getNumOperands() <= 3 ||
17310 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
17311 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
17312 && "Expected last argument to be EFLAGS");
17313 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
17314 // In the XMM save block, save all the XMM argument registers.
17315 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
17316 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
17317 MachineMemOperand *MMO =
17318 F->getMachineMemOperand(
17319 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
17320 MachineMemOperand::MOStore,
17321 /*Size=*/16, /*Align=*/16);
17322 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
17323 .addFrameIndex(RegSaveFrameIndex)
17324 .addImm(/*Scale=*/1)
17325 .addReg(/*IndexReg=*/0)
17326 .addImm(/*Disp=*/Offset)
17327 .addReg(/*Segment=*/0)
17328 .addReg(MI->getOperand(i).getReg())
17329 .addMemOperand(MMO);
17332 MI->eraseFromParent(); // The pseudo instruction is gone now.
17337 // The EFLAGS operand of SelectItr might be missing a kill marker
17338 // because there were multiple uses of EFLAGS, and ISel didn't know
17339 // which to mark. Figure out whether SelectItr should have had a
17340 // kill marker, and set it if it should. Returns the correct kill
17342 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
17343 MachineBasicBlock* BB,
17344 const TargetRegisterInfo* TRI) {
17345 // Scan forward through BB for a use/def of EFLAGS.
17346 MachineBasicBlock::iterator miI(std::next(SelectItr));
17347 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
17348 const MachineInstr& mi = *miI;
17349 if (mi.readsRegister(X86::EFLAGS))
17351 if (mi.definesRegister(X86::EFLAGS))
17352 break; // Should have kill-flag - update below.
17355 // If we hit the end of the block, check whether EFLAGS is live into a
17357 if (miI == BB->end()) {
17358 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
17359 sEnd = BB->succ_end();
17360 sItr != sEnd; ++sItr) {
17361 MachineBasicBlock* succ = *sItr;
17362 if (succ->isLiveIn(X86::EFLAGS))
17367 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
17368 // out. SelectMI should have a kill flag on EFLAGS.
17369 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
17373 MachineBasicBlock *
17374 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
17375 MachineBasicBlock *BB) const {
17376 const TargetInstrInfo *TII = BB->getParent()->getTarget().getInstrInfo();
17377 DebugLoc DL = MI->getDebugLoc();
17379 // To "insert" a SELECT_CC instruction, we actually have to insert the
17380 // diamond control-flow pattern. The incoming instruction knows the
17381 // destination vreg to set, the condition code register to branch on, the
17382 // true/false values to select between, and a branch opcode to use.
17383 const BasicBlock *LLVM_BB = BB->getBasicBlock();
17384 MachineFunction::iterator It = BB;
17390 // cmpTY ccX, r1, r2
17392 // fallthrough --> copy0MBB
17393 MachineBasicBlock *thisMBB = BB;
17394 MachineFunction *F = BB->getParent();
17395 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
17396 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
17397 F->insert(It, copy0MBB);
17398 F->insert(It, sinkMBB);
17400 // If the EFLAGS register isn't dead in the terminator, then claim that it's
17401 // live into the sink and copy blocks.
17402 const TargetRegisterInfo* TRI = BB->getParent()->getTarget().getRegisterInfo();
17403 if (!MI->killsRegister(X86::EFLAGS) &&
17404 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
17405 copy0MBB->addLiveIn(X86::EFLAGS);
17406 sinkMBB->addLiveIn(X86::EFLAGS);
17409 // Transfer the remainder of BB and its successor edges to sinkMBB.
17410 sinkMBB->splice(sinkMBB->begin(), BB,
17411 std::next(MachineBasicBlock::iterator(MI)), BB->end());
17412 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
17414 // Add the true and fallthrough blocks as its successors.
17415 BB->addSuccessor(copy0MBB);
17416 BB->addSuccessor(sinkMBB);
17418 // Create the conditional branch instruction.
17420 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
17421 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
17424 // %FalseValue = ...
17425 // # fallthrough to sinkMBB
17426 copy0MBB->addSuccessor(sinkMBB);
17429 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
17431 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
17432 TII->get(X86::PHI), MI->getOperand(0).getReg())
17433 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
17434 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
17436 MI->eraseFromParent(); // The pseudo instruction is gone now.
17440 MachineBasicBlock *
17441 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
17442 bool Is64Bit) const {
17443 MachineFunction *MF = BB->getParent();
17444 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
17445 DebugLoc DL = MI->getDebugLoc();
17446 const BasicBlock *LLVM_BB = BB->getBasicBlock();
17448 assert(MF->shouldSplitStack());
17450 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
17451 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
17454 // ... [Till the alloca]
17455 // If stacklet is not large enough, jump to mallocMBB
17458 // Allocate by subtracting from RSP
17459 // Jump to continueMBB
17462 // Allocate by call to runtime
17466 // [rest of original BB]
17469 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17470 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17471 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17473 MachineRegisterInfo &MRI = MF->getRegInfo();
17474 const TargetRegisterClass *AddrRegClass =
17475 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
17477 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
17478 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
17479 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
17480 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
17481 sizeVReg = MI->getOperand(1).getReg(),
17482 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
17484 MachineFunction::iterator MBBIter = BB;
17487 MF->insert(MBBIter, bumpMBB);
17488 MF->insert(MBBIter, mallocMBB);
17489 MF->insert(MBBIter, continueMBB);
17491 continueMBB->splice(continueMBB->begin(), BB,
17492 std::next(MachineBasicBlock::iterator(MI)), BB->end());
17493 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
17495 // Add code to the main basic block to check if the stack limit has been hit,
17496 // and if so, jump to mallocMBB otherwise to bumpMBB.
17497 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
17498 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
17499 .addReg(tmpSPVReg).addReg(sizeVReg);
17500 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
17501 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
17502 .addReg(SPLimitVReg);
17503 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
17505 // bumpMBB simply decreases the stack pointer, since we know the current
17506 // stacklet has enough space.
17507 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
17508 .addReg(SPLimitVReg);
17509 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
17510 .addReg(SPLimitVReg);
17511 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
17513 // Calls into a routine in libgcc to allocate more space from the heap.
17514 const uint32_t *RegMask =
17515 MF->getTarget().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
17517 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
17519 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
17520 .addExternalSymbol("__morestack_allocate_stack_space")
17521 .addRegMask(RegMask)
17522 .addReg(X86::RDI, RegState::Implicit)
17523 .addReg(X86::RAX, RegState::ImplicitDefine);
17525 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
17527 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
17528 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
17529 .addExternalSymbol("__morestack_allocate_stack_space")
17530 .addRegMask(RegMask)
17531 .addReg(X86::EAX, RegState::ImplicitDefine);
17535 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
17538 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
17539 .addReg(Is64Bit ? X86::RAX : X86::EAX);
17540 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
17542 // Set up the CFG correctly.
17543 BB->addSuccessor(bumpMBB);
17544 BB->addSuccessor(mallocMBB);
17545 mallocMBB->addSuccessor(continueMBB);
17546 bumpMBB->addSuccessor(continueMBB);
17548 // Take care of the PHI nodes.
17549 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
17550 MI->getOperand(0).getReg())
17551 .addReg(mallocPtrVReg).addMBB(mallocMBB)
17552 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
17554 // Delete the original pseudo instruction.
17555 MI->eraseFromParent();
17558 return continueMBB;
17561 MachineBasicBlock *
17562 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
17563 MachineBasicBlock *BB) const {
17564 const TargetInstrInfo *TII = BB->getParent()->getTarget().getInstrInfo();
17565 DebugLoc DL = MI->getDebugLoc();
17567 assert(!Subtarget->isTargetMacho());
17569 // The lowering is pretty easy: we're just emitting the call to _alloca. The
17570 // non-trivial part is impdef of ESP.
17572 if (Subtarget->isTargetWin64()) {
17573 if (Subtarget->isTargetCygMing()) {
17574 // ___chkstk(Mingw64):
17575 // Clobbers R10, R11, RAX and EFLAGS.
17577 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
17578 .addExternalSymbol("___chkstk")
17579 .addReg(X86::RAX, RegState::Implicit)
17580 .addReg(X86::RSP, RegState::Implicit)
17581 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
17582 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
17583 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
17585 // __chkstk(MSVCRT): does not update stack pointer.
17586 // Clobbers R10, R11 and EFLAGS.
17587 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
17588 .addExternalSymbol("__chkstk")
17589 .addReg(X86::RAX, RegState::Implicit)
17590 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
17591 // RAX has the offset to be subtracted from RSP.
17592 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
17597 const char *StackProbeSymbol =
17598 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
17600 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
17601 .addExternalSymbol(StackProbeSymbol)
17602 .addReg(X86::EAX, RegState::Implicit)
17603 .addReg(X86::ESP, RegState::Implicit)
17604 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
17605 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
17606 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
17609 MI->eraseFromParent(); // The pseudo instruction is gone now.
17613 MachineBasicBlock *
17614 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
17615 MachineBasicBlock *BB) const {
17616 // This is pretty easy. We're taking the value that we received from
17617 // our load from the relocation, sticking it in either RDI (x86-64)
17618 // or EAX and doing an indirect call. The return value will then
17619 // be in the normal return register.
17620 MachineFunction *F = BB->getParent();
17621 const X86InstrInfo *TII
17622 = static_cast<const X86InstrInfo*>(F->getTarget().getInstrInfo());
17623 DebugLoc DL = MI->getDebugLoc();
17625 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
17626 assert(MI->getOperand(3).isGlobal() && "This should be a global");
17628 // Get a register mask for the lowered call.
17629 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
17630 // proper register mask.
17631 const uint32_t *RegMask =
17632 F->getTarget().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
17633 if (Subtarget->is64Bit()) {
17634 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
17635 TII->get(X86::MOV64rm), X86::RDI)
17637 .addImm(0).addReg(0)
17638 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
17639 MI->getOperand(3).getTargetFlags())
17641 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
17642 addDirectMem(MIB, X86::RDI);
17643 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
17644 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
17645 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
17646 TII->get(X86::MOV32rm), X86::EAX)
17648 .addImm(0).addReg(0)
17649 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
17650 MI->getOperand(3).getTargetFlags())
17652 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
17653 addDirectMem(MIB, X86::EAX);
17654 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
17656 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
17657 TII->get(X86::MOV32rm), X86::EAX)
17658 .addReg(TII->getGlobalBaseReg(F))
17659 .addImm(0).addReg(0)
17660 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
17661 MI->getOperand(3).getTargetFlags())
17663 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
17664 addDirectMem(MIB, X86::EAX);
17665 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
17668 MI->eraseFromParent(); // The pseudo instruction is gone now.
17672 MachineBasicBlock *
17673 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
17674 MachineBasicBlock *MBB) const {
17675 DebugLoc DL = MI->getDebugLoc();
17676 MachineFunction *MF = MBB->getParent();
17677 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
17678 MachineRegisterInfo &MRI = MF->getRegInfo();
17680 const BasicBlock *BB = MBB->getBasicBlock();
17681 MachineFunction::iterator I = MBB;
17684 // Memory Reference
17685 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
17686 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
17689 unsigned MemOpndSlot = 0;
17691 unsigned CurOp = 0;
17693 DstReg = MI->getOperand(CurOp++).getReg();
17694 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
17695 assert(RC->hasType(MVT::i32) && "Invalid destination!");
17696 unsigned mainDstReg = MRI.createVirtualRegister(RC);
17697 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
17699 MemOpndSlot = CurOp;
17701 MVT PVT = getPointerTy();
17702 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
17703 "Invalid Pointer Size!");
17705 // For v = setjmp(buf), we generate
17708 // buf[LabelOffset] = restoreMBB
17709 // SjLjSetup restoreMBB
17715 // v = phi(main, restore)
17720 MachineBasicBlock *thisMBB = MBB;
17721 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
17722 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
17723 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
17724 MF->insert(I, mainMBB);
17725 MF->insert(I, sinkMBB);
17726 MF->push_back(restoreMBB);
17728 MachineInstrBuilder MIB;
17730 // Transfer the remainder of BB and its successor edges to sinkMBB.
17731 sinkMBB->splice(sinkMBB->begin(), MBB,
17732 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
17733 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
17736 unsigned PtrStoreOpc = 0;
17737 unsigned LabelReg = 0;
17738 const int64_t LabelOffset = 1 * PVT.getStoreSize();
17739 Reloc::Model RM = MF->getTarget().getRelocationModel();
17740 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
17741 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
17743 // Prepare IP either in reg or imm.
17744 if (!UseImmLabel) {
17745 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
17746 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
17747 LabelReg = MRI.createVirtualRegister(PtrRC);
17748 if (Subtarget->is64Bit()) {
17749 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
17753 .addMBB(restoreMBB)
17756 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
17757 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
17758 .addReg(XII->getGlobalBaseReg(MF))
17761 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
17765 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
17767 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
17768 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
17769 if (i == X86::AddrDisp)
17770 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
17772 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
17775 MIB.addReg(LabelReg);
17777 MIB.addMBB(restoreMBB);
17778 MIB.setMemRefs(MMOBegin, MMOEnd);
17780 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
17781 .addMBB(restoreMBB);
17783 const X86RegisterInfo *RegInfo =
17784 static_cast<const X86RegisterInfo*>(MF->getTarget().getRegisterInfo());
17785 MIB.addRegMask(RegInfo->getNoPreservedMask());
17786 thisMBB->addSuccessor(mainMBB);
17787 thisMBB->addSuccessor(restoreMBB);
17791 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
17792 mainMBB->addSuccessor(sinkMBB);
17795 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
17796 TII->get(X86::PHI), DstReg)
17797 .addReg(mainDstReg).addMBB(mainMBB)
17798 .addReg(restoreDstReg).addMBB(restoreMBB);
17801 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
17802 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
17803 restoreMBB->addSuccessor(sinkMBB);
17805 MI->eraseFromParent();
17809 MachineBasicBlock *
17810 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
17811 MachineBasicBlock *MBB) const {
17812 DebugLoc DL = MI->getDebugLoc();
17813 MachineFunction *MF = MBB->getParent();
17814 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
17815 MachineRegisterInfo &MRI = MF->getRegInfo();
17817 // Memory Reference
17818 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
17819 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
17821 MVT PVT = getPointerTy();
17822 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
17823 "Invalid Pointer Size!");
17825 const TargetRegisterClass *RC =
17826 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
17827 unsigned Tmp = MRI.createVirtualRegister(RC);
17828 // Since FP is only updated here but NOT referenced, it's treated as GPR.
17829 const X86RegisterInfo *RegInfo =
17830 static_cast<const X86RegisterInfo*>(MF->getTarget().getRegisterInfo());
17831 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
17832 unsigned SP = RegInfo->getStackRegister();
17834 MachineInstrBuilder MIB;
17836 const int64_t LabelOffset = 1 * PVT.getStoreSize();
17837 const int64_t SPOffset = 2 * PVT.getStoreSize();
17839 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
17840 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
17843 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
17844 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
17845 MIB.addOperand(MI->getOperand(i));
17846 MIB.setMemRefs(MMOBegin, MMOEnd);
17848 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
17849 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
17850 if (i == X86::AddrDisp)
17851 MIB.addDisp(MI->getOperand(i), LabelOffset);
17853 MIB.addOperand(MI->getOperand(i));
17855 MIB.setMemRefs(MMOBegin, MMOEnd);
17857 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
17858 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
17859 if (i == X86::AddrDisp)
17860 MIB.addDisp(MI->getOperand(i), SPOffset);
17862 MIB.addOperand(MI->getOperand(i));
17864 MIB.setMemRefs(MMOBegin, MMOEnd);
17866 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
17868 MI->eraseFromParent();
17872 // Replace 213-type (isel default) FMA3 instructions with 231-type for
17873 // accumulator loops. Writing back to the accumulator allows the coalescer
17874 // to remove extra copies in the loop.
17875 MachineBasicBlock *
17876 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
17877 MachineBasicBlock *MBB) const {
17878 MachineOperand &AddendOp = MI->getOperand(3);
17880 // Bail out early if the addend isn't a register - we can't switch these.
17881 if (!AddendOp.isReg())
17884 MachineFunction &MF = *MBB->getParent();
17885 MachineRegisterInfo &MRI = MF.getRegInfo();
17887 // Check whether the addend is defined by a PHI:
17888 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
17889 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
17890 if (!AddendDef.isPHI())
17893 // Look for the following pattern:
17895 // %addend = phi [%entry, 0], [%loop, %result]
17897 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
17901 // %addend = phi [%entry, 0], [%loop, %result]
17903 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
17905 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
17906 assert(AddendDef.getOperand(i).isReg());
17907 MachineOperand PHISrcOp = AddendDef.getOperand(i);
17908 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
17909 if (&PHISrcInst == MI) {
17910 // Found a matching instruction.
17911 unsigned NewFMAOpc = 0;
17912 switch (MI->getOpcode()) {
17913 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
17914 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
17915 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
17916 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
17917 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
17918 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
17919 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
17920 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
17921 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
17922 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
17923 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
17924 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
17925 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
17926 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
17927 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
17928 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
17929 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
17930 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
17931 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
17932 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
17933 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
17934 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
17935 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
17936 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
17937 default: llvm_unreachable("Unrecognized FMA variant.");
17940 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
17941 MachineInstrBuilder MIB =
17942 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
17943 .addOperand(MI->getOperand(0))
17944 .addOperand(MI->getOperand(3))
17945 .addOperand(MI->getOperand(2))
17946 .addOperand(MI->getOperand(1));
17947 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
17948 MI->eraseFromParent();
17955 MachineBasicBlock *
17956 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
17957 MachineBasicBlock *BB) const {
17958 switch (MI->getOpcode()) {
17959 default: llvm_unreachable("Unexpected instr type to insert");
17960 case X86::TAILJMPd64:
17961 case X86::TAILJMPr64:
17962 case X86::TAILJMPm64:
17963 llvm_unreachable("TAILJMP64 would not be touched here.");
17964 case X86::TCRETURNdi64:
17965 case X86::TCRETURNri64:
17966 case X86::TCRETURNmi64:
17968 case X86::WIN_ALLOCA:
17969 return EmitLoweredWinAlloca(MI, BB);
17970 case X86::SEG_ALLOCA_32:
17971 return EmitLoweredSegAlloca(MI, BB, false);
17972 case X86::SEG_ALLOCA_64:
17973 return EmitLoweredSegAlloca(MI, BB, true);
17974 case X86::TLSCall_32:
17975 case X86::TLSCall_64:
17976 return EmitLoweredTLSCall(MI, BB);
17977 case X86::CMOV_GR8:
17978 case X86::CMOV_FR32:
17979 case X86::CMOV_FR64:
17980 case X86::CMOV_V4F32:
17981 case X86::CMOV_V2F64:
17982 case X86::CMOV_V2I64:
17983 case X86::CMOV_V8F32:
17984 case X86::CMOV_V4F64:
17985 case X86::CMOV_V4I64:
17986 case X86::CMOV_V16F32:
17987 case X86::CMOV_V8F64:
17988 case X86::CMOV_V8I64:
17989 case X86::CMOV_GR16:
17990 case X86::CMOV_GR32:
17991 case X86::CMOV_RFP32:
17992 case X86::CMOV_RFP64:
17993 case X86::CMOV_RFP80:
17994 return EmitLoweredSelect(MI, BB);
17996 case X86::FP32_TO_INT16_IN_MEM:
17997 case X86::FP32_TO_INT32_IN_MEM:
17998 case X86::FP32_TO_INT64_IN_MEM:
17999 case X86::FP64_TO_INT16_IN_MEM:
18000 case X86::FP64_TO_INT32_IN_MEM:
18001 case X86::FP64_TO_INT64_IN_MEM:
18002 case X86::FP80_TO_INT16_IN_MEM:
18003 case X86::FP80_TO_INT32_IN_MEM:
18004 case X86::FP80_TO_INT64_IN_MEM: {
18005 MachineFunction *F = BB->getParent();
18006 const TargetInstrInfo *TII = F->getTarget().getInstrInfo();
18007 DebugLoc DL = MI->getDebugLoc();
18009 // Change the floating point control register to use "round towards zero"
18010 // mode when truncating to an integer value.
18011 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
18012 addFrameReference(BuildMI(*BB, MI, DL,
18013 TII->get(X86::FNSTCW16m)), CWFrameIdx);
18015 // Load the old value of the high byte of the control word...
18017 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
18018 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
18021 // Set the high part to be round to zero...
18022 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
18025 // Reload the modified control word now...
18026 addFrameReference(BuildMI(*BB, MI, DL,
18027 TII->get(X86::FLDCW16m)), CWFrameIdx);
18029 // Restore the memory image of control word to original value
18030 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
18033 // Get the X86 opcode to use.
18035 switch (MI->getOpcode()) {
18036 default: llvm_unreachable("illegal opcode!");
18037 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
18038 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
18039 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
18040 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
18041 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
18042 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
18043 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
18044 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
18045 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
18049 MachineOperand &Op = MI->getOperand(0);
18051 AM.BaseType = X86AddressMode::RegBase;
18052 AM.Base.Reg = Op.getReg();
18054 AM.BaseType = X86AddressMode::FrameIndexBase;
18055 AM.Base.FrameIndex = Op.getIndex();
18057 Op = MI->getOperand(1);
18059 AM.Scale = Op.getImm();
18060 Op = MI->getOperand(2);
18062 AM.IndexReg = Op.getImm();
18063 Op = MI->getOperand(3);
18064 if (Op.isGlobal()) {
18065 AM.GV = Op.getGlobal();
18067 AM.Disp = Op.getImm();
18069 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
18070 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
18072 // Reload the original control word now.
18073 addFrameReference(BuildMI(*BB, MI, DL,
18074 TII->get(X86::FLDCW16m)), CWFrameIdx);
18076 MI->eraseFromParent(); // The pseudo instruction is gone now.
18079 // String/text processing lowering.
18080 case X86::PCMPISTRM128REG:
18081 case X86::VPCMPISTRM128REG:
18082 case X86::PCMPISTRM128MEM:
18083 case X86::VPCMPISTRM128MEM:
18084 case X86::PCMPESTRM128REG:
18085 case X86::VPCMPESTRM128REG:
18086 case X86::PCMPESTRM128MEM:
18087 case X86::VPCMPESTRM128MEM:
18088 assert(Subtarget->hasSSE42() &&
18089 "Target must have SSE4.2 or AVX features enabled");
18090 return EmitPCMPSTRM(MI, BB, BB->getParent()->getTarget().getInstrInfo());
18092 // String/text processing lowering.
18093 case X86::PCMPISTRIREG:
18094 case X86::VPCMPISTRIREG:
18095 case X86::PCMPISTRIMEM:
18096 case X86::VPCMPISTRIMEM:
18097 case X86::PCMPESTRIREG:
18098 case X86::VPCMPESTRIREG:
18099 case X86::PCMPESTRIMEM:
18100 case X86::VPCMPESTRIMEM:
18101 assert(Subtarget->hasSSE42() &&
18102 "Target must have SSE4.2 or AVX features enabled");
18103 return EmitPCMPSTRI(MI, BB, BB->getParent()->getTarget().getInstrInfo());
18105 // Thread synchronization.
18107 return EmitMonitor(MI, BB, BB->getParent()->getTarget().getInstrInfo(), Subtarget);
18111 return EmitXBegin(MI, BB, BB->getParent()->getTarget().getInstrInfo());
18113 case X86::VASTART_SAVE_XMM_REGS:
18114 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
18116 case X86::VAARG_64:
18117 return EmitVAARG64WithCustomInserter(MI, BB);
18119 case X86::EH_SjLj_SetJmp32:
18120 case X86::EH_SjLj_SetJmp64:
18121 return emitEHSjLjSetJmp(MI, BB);
18123 case X86::EH_SjLj_LongJmp32:
18124 case X86::EH_SjLj_LongJmp64:
18125 return emitEHSjLjLongJmp(MI, BB);
18127 case TargetOpcode::STACKMAP:
18128 case TargetOpcode::PATCHPOINT:
18129 return emitPatchPoint(MI, BB);
18131 case X86::VFMADDPDr213r:
18132 case X86::VFMADDPSr213r:
18133 case X86::VFMADDSDr213r:
18134 case X86::VFMADDSSr213r:
18135 case X86::VFMSUBPDr213r:
18136 case X86::VFMSUBPSr213r:
18137 case X86::VFMSUBSDr213r:
18138 case X86::VFMSUBSSr213r:
18139 case X86::VFNMADDPDr213r:
18140 case X86::VFNMADDPSr213r:
18141 case X86::VFNMADDSDr213r:
18142 case X86::VFNMADDSSr213r:
18143 case X86::VFNMSUBPDr213r:
18144 case X86::VFNMSUBPSr213r:
18145 case X86::VFNMSUBSDr213r:
18146 case X86::VFNMSUBSSr213r:
18147 case X86::VFMADDPDr213rY:
18148 case X86::VFMADDPSr213rY:
18149 case X86::VFMSUBPDr213rY:
18150 case X86::VFMSUBPSr213rY:
18151 case X86::VFNMADDPDr213rY:
18152 case X86::VFNMADDPSr213rY:
18153 case X86::VFNMSUBPDr213rY:
18154 case X86::VFNMSUBPSr213rY:
18155 return emitFMA3Instr(MI, BB);
18159 //===----------------------------------------------------------------------===//
18160 // X86 Optimization Hooks
18161 //===----------------------------------------------------------------------===//
18163 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
18166 const SelectionDAG &DAG,
18167 unsigned Depth) const {
18168 unsigned BitWidth = KnownZero.getBitWidth();
18169 unsigned Opc = Op.getOpcode();
18170 assert((Opc >= ISD::BUILTIN_OP_END ||
18171 Opc == ISD::INTRINSIC_WO_CHAIN ||
18172 Opc == ISD::INTRINSIC_W_CHAIN ||
18173 Opc == ISD::INTRINSIC_VOID) &&
18174 "Should use MaskedValueIsZero if you don't know whether Op"
18175 " is a target node!");
18177 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
18191 // These nodes' second result is a boolean.
18192 if (Op.getResNo() == 0)
18195 case X86ISD::SETCC:
18196 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
18198 case ISD::INTRINSIC_WO_CHAIN: {
18199 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
18200 unsigned NumLoBits = 0;
18203 case Intrinsic::x86_sse_movmsk_ps:
18204 case Intrinsic::x86_avx_movmsk_ps_256:
18205 case Intrinsic::x86_sse2_movmsk_pd:
18206 case Intrinsic::x86_avx_movmsk_pd_256:
18207 case Intrinsic::x86_mmx_pmovmskb:
18208 case Intrinsic::x86_sse2_pmovmskb_128:
18209 case Intrinsic::x86_avx2_pmovmskb: {
18210 // High bits of movmskp{s|d}, pmovmskb are known zero.
18212 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
18213 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
18214 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
18215 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
18216 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
18217 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
18218 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
18219 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
18221 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
18230 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
18232 const SelectionDAG &,
18233 unsigned Depth) const {
18234 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
18235 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
18236 return Op.getValueType().getScalarType().getSizeInBits();
18242 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
18243 /// node is a GlobalAddress + offset.
18244 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
18245 const GlobalValue* &GA,
18246 int64_t &Offset) const {
18247 if (N->getOpcode() == X86ISD::Wrapper) {
18248 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
18249 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
18250 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
18254 return TargetLowering::isGAPlusOffset(N, GA, Offset);
18257 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
18258 /// same as extracting the high 128-bit part of 256-bit vector and then
18259 /// inserting the result into the low part of a new 256-bit vector
18260 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
18261 EVT VT = SVOp->getValueType(0);
18262 unsigned NumElems = VT.getVectorNumElements();
18264 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
18265 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
18266 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
18267 SVOp->getMaskElt(j) >= 0)
18273 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
18274 /// same as extracting the low 128-bit part of 256-bit vector and then
18275 /// inserting the result into the high part of a new 256-bit vector
18276 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
18277 EVT VT = SVOp->getValueType(0);
18278 unsigned NumElems = VT.getVectorNumElements();
18280 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
18281 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
18282 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
18283 SVOp->getMaskElt(j) >= 0)
18289 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
18290 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
18291 TargetLowering::DAGCombinerInfo &DCI,
18292 const X86Subtarget* Subtarget) {
18294 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
18295 SDValue V1 = SVOp->getOperand(0);
18296 SDValue V2 = SVOp->getOperand(1);
18297 EVT VT = SVOp->getValueType(0);
18298 unsigned NumElems = VT.getVectorNumElements();
18300 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
18301 V2.getOpcode() == ISD::CONCAT_VECTORS) {
18305 // V UNDEF BUILD_VECTOR UNDEF
18307 // CONCAT_VECTOR CONCAT_VECTOR
18310 // RESULT: V + zero extended
18312 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
18313 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
18314 V1.getOperand(1).getOpcode() != ISD::UNDEF)
18317 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
18320 // To match the shuffle mask, the first half of the mask should
18321 // be exactly the first vector, and all the rest a splat with the
18322 // first element of the second one.
18323 for (unsigned i = 0; i != NumElems/2; ++i)
18324 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
18325 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
18328 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
18329 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
18330 if (Ld->hasNUsesOfValue(1, 0)) {
18331 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
18332 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
18334 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
18336 Ld->getPointerInfo(),
18337 Ld->getAlignment(),
18338 false/*isVolatile*/, true/*ReadMem*/,
18339 false/*WriteMem*/);
18341 // Make sure the newly-created LOAD is in the same position as Ld in
18342 // terms of dependency. We create a TokenFactor for Ld and ResNode,
18343 // and update uses of Ld's output chain to use the TokenFactor.
18344 if (Ld->hasAnyUseOfValue(1)) {
18345 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
18346 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
18347 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
18348 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
18349 SDValue(ResNode.getNode(), 1));
18352 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
18356 // Emit a zeroed vector and insert the desired subvector on its
18358 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18359 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
18360 return DCI.CombineTo(N, InsV);
18363 //===--------------------------------------------------------------------===//
18364 // Combine some shuffles into subvector extracts and inserts:
18367 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
18368 if (isShuffleHigh128VectorInsertLow(SVOp)) {
18369 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
18370 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
18371 return DCI.CombineTo(N, InsV);
18374 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
18375 if (isShuffleLow128VectorInsertHigh(SVOp)) {
18376 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
18377 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
18378 return DCI.CombineTo(N, InsV);
18384 /// \brief Get the PSHUF-style mask from PSHUF node.
18386 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
18387 /// PSHUF-style masks that can be reused with such instructions.
18388 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
18389 SmallVector<int, 4> Mask;
18391 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
18395 switch (N.getOpcode()) {
18396 case X86ISD::PSHUFD:
18398 case X86ISD::PSHUFLW:
18401 case X86ISD::PSHUFHW:
18402 Mask.erase(Mask.begin(), Mask.begin() + 4);
18403 for (int &M : Mask)
18407 llvm_unreachable("No valid shuffle instruction found!");
18411 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
18413 /// We walk up the chain and look for a combinable shuffle, skipping over
18414 /// shuffles that we could hoist this shuffle's transformation past without
18415 /// altering anything.
18416 static bool combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
18418 TargetLowering::DAGCombinerInfo &DCI) {
18419 assert(N.getOpcode() == X86ISD::PSHUFD &&
18420 "Called with something other than an x86 128-bit half shuffle!");
18423 // Walk up a single-use chain looking for a combinable shuffle.
18424 SDValue V = N.getOperand(0);
18425 for (; V.hasOneUse(); V = V.getOperand(0)) {
18426 switch (V.getOpcode()) {
18428 return false; // Nothing combined!
18431 // Skip bitcasts as we always know the type for the target specific
18435 case X86ISD::PSHUFD:
18436 // Found another dword shuffle.
18439 case X86ISD::PSHUFLW:
18440 // Check that the low words (being shuffled) are the identity in the
18441 // dword shuffle, and the high words are self-contained.
18442 if (Mask[0] != 0 || Mask[1] != 1 ||
18443 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
18448 case X86ISD::PSHUFHW:
18449 // Check that the high words (being shuffled) are the identity in the
18450 // dword shuffle, and the low words are self-contained.
18451 if (Mask[2] != 2 || Mask[3] != 3 ||
18452 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
18457 // Break out of the loop if we break out of the switch.
18461 if (!V.hasOneUse())
18462 // We fell out of the loop without finding a viable combining instruction.
18465 // Record the old value to use in RAUW-ing.
18468 // Merge this node's mask and our incoming mask.
18469 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
18470 for (int &M : Mask)
18472 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V.getOperand(0),
18473 getV4X86ShuffleImm8ForMask(Mask, DAG));
18475 // It is possible that one of the combinable shuffles was completely absorbed
18476 // by the other, just replace it and revisit all users in that case.
18477 if (Old.getNode() == V.getNode()) {
18478 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo=*/true);
18482 // Replace N with its operand as we're going to combine that shuffle away.
18483 DAG.ReplaceAllUsesWith(N, N.getOperand(0));
18485 // Replace the combinable shuffle with the combined one, updating all users
18486 // so that we re-evaluate the chain here.
18487 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
18491 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
18493 /// We walk up the chain, skipping shuffles of the other half and looking
18494 /// through shuffles which switch halves trying to find a shuffle of the same
18495 /// pair of dwords.
18496 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
18498 TargetLowering::DAGCombinerInfo &DCI) {
18500 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
18501 "Called with something other than an x86 128-bit half shuffle!");
18503 unsigned CombineOpcode = N.getOpcode();
18505 // Walk up a single-use chain looking for a combinable shuffle.
18506 SDValue V = N.getOperand(0);
18507 for (; V.hasOneUse(); V = V.getOperand(0)) {
18508 switch (V.getOpcode()) {
18510 return false; // Nothing combined!
18513 // Skip bitcasts as we always know the type for the target specific
18517 case X86ISD::PSHUFLW:
18518 case X86ISD::PSHUFHW:
18519 if (V.getOpcode() == CombineOpcode)
18522 // Other-half shuffles are no-ops.
18525 case X86ISD::PSHUFD: {
18526 // We can only handle pshufd if the half we are combining either stays in
18527 // its half, or switches to the other half. Bail if one of these isn't
18529 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
18530 int DOffset = CombineOpcode == X86ISD::PSHUFLW ? 0 : 2;
18531 if (!((VMask[DOffset + 0] < 2 && VMask[DOffset + 1] < 2) ||
18532 (VMask[DOffset + 0] >= 2 && VMask[DOffset + 1] >= 2)))
18535 // Map the mask through the pshufd and keep walking up the chain.
18536 for (int i = 0; i < 4; ++i)
18537 Mask[i] = 2 * (VMask[DOffset + Mask[i] / 2] % 2) + Mask[i] % 2;
18539 // Switch halves if the pshufd does.
18541 VMask[DOffset + Mask[0] / 2] < 2 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
18545 // Break out of the loop if we break out of the switch.
18549 if (!V.hasOneUse())
18550 // We fell out of the loop without finding a viable combining instruction.
18553 // Record the old value to use in RAUW-ing.
18556 // Merge this node's mask and our incoming mask (adjusted to account for all
18557 // the pshufd instructions encountered).
18558 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
18559 for (int &M : Mask)
18561 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
18562 getV4X86ShuffleImm8ForMask(Mask, DAG));
18564 // Replace N with its operand as we're going to combine that shuffle away.
18565 DAG.ReplaceAllUsesWith(N, N.getOperand(0));
18567 // Replace the combinable shuffle with the combined one, updating all users
18568 // so that we re-evaluate the chain here.
18569 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
18573 /// \brief Try to combine x86 target specific shuffles.
18574 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
18575 TargetLowering::DAGCombinerInfo &DCI,
18576 const X86Subtarget *Subtarget) {
18578 MVT VT = N.getSimpleValueType();
18579 SmallVector<int, 4> Mask;
18581 switch (N.getOpcode()) {
18582 case X86ISD::PSHUFD:
18583 case X86ISD::PSHUFLW:
18584 case X86ISD::PSHUFHW:
18585 Mask = getPSHUFShuffleMask(N);
18586 assert(Mask.size() == 4);
18592 // Nuke no-op shuffles that show up after combining.
18593 if (isNoopShuffleMask(Mask))
18594 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
18596 // Look for simplifications involving one or two shuffle instructions.
18597 SDValue V = N.getOperand(0);
18598 switch (N.getOpcode()) {
18601 case X86ISD::PSHUFLW:
18602 case X86ISD::PSHUFHW:
18603 assert(VT == MVT::v8i16);
18606 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
18607 return SDValue(); // We combined away this shuffle, so we're done.
18609 // See if this reduces to a PSHUFD which is no more expensive and can
18610 // combine with more operations.
18611 if (Mask[0] % 2 == 0 && Mask[2] % 2 == 0 &&
18612 areAdjacentMasksSequential(Mask)) {
18613 int DMask[] = {-1, -1, -1, -1};
18614 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
18615 DMask[DOffset + 0] = DOffset + Mask[0] / 2;
18616 DMask[DOffset + 1] = DOffset + Mask[2] / 2;
18617 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
18618 DCI.AddToWorklist(V.getNode());
18619 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
18620 getV4X86ShuffleImm8ForMask(DMask, DAG));
18621 DCI.AddToWorklist(V.getNode());
18622 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
18627 case X86ISD::PSHUFD:
18628 if (combineRedundantDWordShuffle(N, Mask, DAG, DCI))
18629 return SDValue(); // We combined away this shuffle.
18637 /// PerformShuffleCombine - Performs several different shuffle combines.
18638 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
18639 TargetLowering::DAGCombinerInfo &DCI,
18640 const X86Subtarget *Subtarget) {
18642 SDValue N0 = N->getOperand(0);
18643 SDValue N1 = N->getOperand(1);
18644 EVT VT = N->getValueType(0);
18646 // Canonicalize shuffles that perform 'addsub' on packed float vectors
18647 // according to the rule:
18648 // (shuffle (FADD A, B), (FSUB A, B), Mask) ->
18649 // (shuffle (FSUB A, -B), (FADD A, -B), Mask)
18651 // Where 'Mask' is:
18652 // <0,5,2,7> -- for v4f32 and v4f64 shuffles;
18653 // <0,3> -- for v2f64 shuffles;
18654 // <0,9,2,11,4,13,6,15> -- for v8f32 shuffles.
18656 // This helps pattern-matching more SSE3/AVX ADDSUB instructions
18657 // during ISel stage.
18658 if (N->getOpcode() == ISD::VECTOR_SHUFFLE &&
18659 ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18660 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18661 N0->getOpcode() == ISD::FADD && N1->getOpcode() == ISD::FSUB &&
18662 // Operands to the FADD and FSUB must be the same.
18663 ((N0->getOperand(0) == N1->getOperand(0) &&
18664 N0->getOperand(1) == N1->getOperand(1)) ||
18665 // FADD is commutable. See if by commuting the operands of the FADD
18666 // we would still be able to match the operands of the FSUB dag node.
18667 (N0->getOperand(1) == N1->getOperand(0) &&
18668 N0->getOperand(0) == N1->getOperand(1))) &&
18669 N0->getOperand(0)->getOpcode() != ISD::UNDEF &&
18670 N0->getOperand(1)->getOpcode() != ISD::UNDEF) {
18672 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
18673 unsigned NumElts = VT.getVectorNumElements();
18674 ArrayRef<int> Mask = SV->getMask();
18675 bool CanFold = true;
18677 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i)
18678 CanFold = Mask[i] == (int)((i & 1) ? i + NumElts : i);
18681 SDValue Op0 = N1->getOperand(0);
18682 SDValue Op1 = DAG.getNode(ISD::FNEG, dl, VT, N1->getOperand(1));
18683 SDValue Sub = DAG.getNode(ISD::FSUB, dl, VT, Op0, Op1);
18684 SDValue Add = DAG.getNode(ISD::FADD, dl, VT, Op0, Op1);
18685 return DAG.getVectorShuffle(VT, dl, Sub, Add, Mask);
18689 // Don't create instructions with illegal types after legalize types has run.
18690 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18691 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
18694 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
18695 if (Subtarget->hasFp256() && VT.is256BitVector() &&
18696 N->getOpcode() == ISD::VECTOR_SHUFFLE)
18697 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
18699 // During Type Legalization, when promoting illegal vector types,
18700 // the backend might introduce new shuffle dag nodes and bitcasts.
18702 // This code performs the following transformation:
18703 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
18704 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
18706 // We do this only if both the bitcast and the BINOP dag nodes have
18707 // one use. Also, perform this transformation only if the new binary
18708 // operation is legal. This is to avoid introducing dag nodes that
18709 // potentially need to be further expanded (or custom lowered) into a
18710 // less optimal sequence of dag nodes.
18711 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
18712 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
18713 N0.getOpcode() == ISD::BITCAST) {
18714 SDValue BC0 = N0.getOperand(0);
18715 EVT SVT = BC0.getValueType();
18716 unsigned Opcode = BC0.getOpcode();
18717 unsigned NumElts = VT.getVectorNumElements();
18719 if (BC0.hasOneUse() && SVT.isVector() &&
18720 SVT.getVectorNumElements() * 2 == NumElts &&
18721 TLI.isOperationLegal(Opcode, VT)) {
18722 bool CanFold = false;
18734 unsigned SVTNumElts = SVT.getVectorNumElements();
18735 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
18736 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
18737 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
18738 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
18739 CanFold = SVOp->getMaskElt(i) < 0;
18742 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
18743 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
18744 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
18745 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
18750 // Only handle 128 wide vector from here on.
18751 if (!VT.is128BitVector())
18754 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
18755 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
18756 // consecutive, non-overlapping, and in the right order.
18757 SmallVector<SDValue, 16> Elts;
18758 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
18759 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
18761 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
18765 if (isTargetShuffle(N->getOpcode())) {
18767 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
18768 if (Shuffle.getNode())
18775 /// PerformTruncateCombine - Converts truncate operation to
18776 /// a sequence of vector shuffle operations.
18777 /// It is possible when we truncate 256-bit vector to 128-bit vector
18778 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
18779 TargetLowering::DAGCombinerInfo &DCI,
18780 const X86Subtarget *Subtarget) {
18784 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
18785 /// specific shuffle of a load can be folded into a single element load.
18786 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
18787 /// shuffles have been customed lowered so we need to handle those here.
18788 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
18789 TargetLowering::DAGCombinerInfo &DCI) {
18790 if (DCI.isBeforeLegalizeOps())
18793 SDValue InVec = N->getOperand(0);
18794 SDValue EltNo = N->getOperand(1);
18796 if (!isa<ConstantSDNode>(EltNo))
18799 EVT VT = InVec.getValueType();
18801 bool HasShuffleIntoBitcast = false;
18802 if (InVec.getOpcode() == ISD::BITCAST) {
18803 // Don't duplicate a load with other uses.
18804 if (!InVec.hasOneUse())
18806 EVT BCVT = InVec.getOperand(0).getValueType();
18807 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
18809 InVec = InVec.getOperand(0);
18810 HasShuffleIntoBitcast = true;
18813 if (!isTargetShuffle(InVec.getOpcode()))
18816 // Don't duplicate a load with other uses.
18817 if (!InVec.hasOneUse())
18820 SmallVector<int, 16> ShuffleMask;
18822 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
18826 // Select the input vector, guarding against out of range extract vector.
18827 unsigned NumElems = VT.getVectorNumElements();
18828 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
18829 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
18830 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
18831 : InVec.getOperand(1);
18833 // If inputs to shuffle are the same for both ops, then allow 2 uses
18834 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
18836 if (LdNode.getOpcode() == ISD::BITCAST) {
18837 // Don't duplicate a load with other uses.
18838 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
18841 AllowedUses = 1; // only allow 1 load use if we have a bitcast
18842 LdNode = LdNode.getOperand(0);
18845 if (!ISD::isNormalLoad(LdNode.getNode()))
18848 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
18850 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
18853 if (HasShuffleIntoBitcast) {
18854 // If there's a bitcast before the shuffle, check if the load type and
18855 // alignment is valid.
18856 unsigned Align = LN0->getAlignment();
18857 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18858 unsigned NewAlign = TLI.getDataLayout()->
18859 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
18861 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
18865 // All checks match so transform back to vector_shuffle so that DAG combiner
18866 // can finish the job
18869 // Create shuffle node taking into account the case that its a unary shuffle
18870 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
18871 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
18872 InVec.getOperand(0), Shuffle,
18874 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
18875 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
18879 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
18880 /// generation and convert it from being a bunch of shuffles and extracts
18881 /// to a simple store and scalar loads to extract the elements.
18882 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
18883 TargetLowering::DAGCombinerInfo &DCI) {
18884 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
18885 if (NewOp.getNode())
18888 SDValue InputVector = N->getOperand(0);
18890 // Detect whether we are trying to convert from mmx to i32 and the bitcast
18891 // from mmx to v2i32 has a single usage.
18892 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
18893 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
18894 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
18895 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
18896 N->getValueType(0),
18897 InputVector.getNode()->getOperand(0));
18899 // Only operate on vectors of 4 elements, where the alternative shuffling
18900 // gets to be more expensive.
18901 if (InputVector.getValueType() != MVT::v4i32)
18904 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
18905 // single use which is a sign-extend or zero-extend, and all elements are
18907 SmallVector<SDNode *, 4> Uses;
18908 unsigned ExtractedElements = 0;
18909 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
18910 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
18911 if (UI.getUse().getResNo() != InputVector.getResNo())
18914 SDNode *Extract = *UI;
18915 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
18918 if (Extract->getValueType(0) != MVT::i32)
18920 if (!Extract->hasOneUse())
18922 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
18923 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
18925 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
18928 // Record which element was extracted.
18929 ExtractedElements |=
18930 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
18932 Uses.push_back(Extract);
18935 // If not all the elements were used, this may not be worthwhile.
18936 if (ExtractedElements != 15)
18939 // Ok, we've now decided to do the transformation.
18940 SDLoc dl(InputVector);
18942 // Store the value to a temporary stack slot.
18943 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
18944 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
18945 MachinePointerInfo(), false, false, 0);
18947 // Replace each use (extract) with a load of the appropriate element.
18948 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
18949 UE = Uses.end(); UI != UE; ++UI) {
18950 SDNode *Extract = *UI;
18952 // cOMpute the element's address.
18953 SDValue Idx = Extract->getOperand(1);
18955 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
18956 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
18957 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18958 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
18960 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
18961 StackPtr, OffsetVal);
18963 // Load the scalar.
18964 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
18965 ScalarAddr, MachinePointerInfo(),
18966 false, false, false, 0);
18968 // Replace the exact with the load.
18969 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
18972 // The replacement was made in place; don't return anything.
18976 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
18977 static std::pair<unsigned, bool>
18978 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
18979 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
18980 if (!VT.isVector())
18981 return std::make_pair(0, false);
18983 bool NeedSplit = false;
18984 switch (VT.getSimpleVT().SimpleTy) {
18985 default: return std::make_pair(0, false);
18989 if (!Subtarget->hasAVX2())
18991 if (!Subtarget->hasAVX())
18992 return std::make_pair(0, false);
18997 if (!Subtarget->hasSSE2())
18998 return std::make_pair(0, false);
19001 // SSE2 has only a small subset of the operations.
19002 bool hasUnsigned = Subtarget->hasSSE41() ||
19003 (Subtarget->hasSSE2() && VT == MVT::v16i8);
19004 bool hasSigned = Subtarget->hasSSE41() ||
19005 (Subtarget->hasSSE2() && VT == MVT::v8i16);
19007 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
19010 // Check for x CC y ? x : y.
19011 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
19012 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
19017 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
19020 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
19023 Opc = hasSigned ? X86ISD::SMIN : 0; break;
19026 Opc = hasSigned ? X86ISD::SMAX : 0; break;
19028 // Check for x CC y ? y : x -- a min/max with reversed arms.
19029 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
19030 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
19035 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
19038 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
19041 Opc = hasSigned ? X86ISD::SMAX : 0; break;
19044 Opc = hasSigned ? X86ISD::SMIN : 0; break;
19048 return std::make_pair(Opc, NeedSplit);
19052 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
19053 const X86Subtarget *Subtarget) {
19055 SDValue Cond = N->getOperand(0);
19056 SDValue LHS = N->getOperand(1);
19057 SDValue RHS = N->getOperand(2);
19059 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
19060 SDValue CondSrc = Cond->getOperand(0);
19061 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
19062 Cond = CondSrc->getOperand(0);
19065 MVT VT = N->getSimpleValueType(0);
19066 MVT EltVT = VT.getVectorElementType();
19067 unsigned NumElems = VT.getVectorNumElements();
19068 // There is no blend with immediate in AVX-512.
19069 if (VT.is512BitVector())
19072 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
19074 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
19077 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
19080 unsigned MaskValue = 0;
19081 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
19084 SmallVector<int, 8> ShuffleMask(NumElems, -1);
19085 for (unsigned i = 0; i < NumElems; ++i) {
19086 // Be sure we emit undef where we can.
19087 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
19088 ShuffleMask[i] = -1;
19090 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
19093 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
19096 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
19098 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
19099 TargetLowering::DAGCombinerInfo &DCI,
19100 const X86Subtarget *Subtarget) {
19102 SDValue Cond = N->getOperand(0);
19103 // Get the LHS/RHS of the select.
19104 SDValue LHS = N->getOperand(1);
19105 SDValue RHS = N->getOperand(2);
19106 EVT VT = LHS.getValueType();
19107 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19109 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
19110 // instructions match the semantics of the common C idiom x<y?x:y but not
19111 // x<=y?x:y, because of how they handle negative zero (which can be
19112 // ignored in unsafe-math mode).
19113 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
19114 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
19115 (Subtarget->hasSSE2() ||
19116 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
19117 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
19119 unsigned Opcode = 0;
19120 // Check for x CC y ? x : y.
19121 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
19122 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
19126 // Converting this to a min would handle NaNs incorrectly, and swapping
19127 // the operands would cause it to handle comparisons between positive
19128 // and negative zero incorrectly.
19129 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
19130 if (!DAG.getTarget().Options.UnsafeFPMath &&
19131 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
19133 std::swap(LHS, RHS);
19135 Opcode = X86ISD::FMIN;
19138 // Converting this to a min would handle comparisons between positive
19139 // and negative zero incorrectly.
19140 if (!DAG.getTarget().Options.UnsafeFPMath &&
19141 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
19143 Opcode = X86ISD::FMIN;
19146 // Converting this to a min would handle both negative zeros and NaNs
19147 // incorrectly, but we can swap the operands to fix both.
19148 std::swap(LHS, RHS);
19152 Opcode = X86ISD::FMIN;
19156 // Converting this to a max would handle comparisons between positive
19157 // and negative zero incorrectly.
19158 if (!DAG.getTarget().Options.UnsafeFPMath &&
19159 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
19161 Opcode = X86ISD::FMAX;
19164 // Converting this to a max would handle NaNs incorrectly, and swapping
19165 // the operands would cause it to handle comparisons between positive
19166 // and negative zero incorrectly.
19167 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
19168 if (!DAG.getTarget().Options.UnsafeFPMath &&
19169 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
19171 std::swap(LHS, RHS);
19173 Opcode = X86ISD::FMAX;
19176 // Converting this to a max would handle both negative zeros and NaNs
19177 // incorrectly, but we can swap the operands to fix both.
19178 std::swap(LHS, RHS);
19182 Opcode = X86ISD::FMAX;
19185 // Check for x CC y ? y : x -- a min/max with reversed arms.
19186 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
19187 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
19191 // Converting this to a min would handle comparisons between positive
19192 // and negative zero incorrectly, and swapping the operands would
19193 // cause it to handle NaNs incorrectly.
19194 if (!DAG.getTarget().Options.UnsafeFPMath &&
19195 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
19196 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
19198 std::swap(LHS, RHS);
19200 Opcode = X86ISD::FMIN;
19203 // Converting this to a min would handle NaNs incorrectly.
19204 if (!DAG.getTarget().Options.UnsafeFPMath &&
19205 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
19207 Opcode = X86ISD::FMIN;
19210 // Converting this to a min would handle both negative zeros and NaNs
19211 // incorrectly, but we can swap the operands to fix both.
19212 std::swap(LHS, RHS);
19216 Opcode = X86ISD::FMIN;
19220 // Converting this to a max would handle NaNs incorrectly.
19221 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
19223 Opcode = X86ISD::FMAX;
19226 // Converting this to a max would handle comparisons between positive
19227 // and negative zero incorrectly, and swapping the operands would
19228 // cause it to handle NaNs incorrectly.
19229 if (!DAG.getTarget().Options.UnsafeFPMath &&
19230 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
19231 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
19233 std::swap(LHS, RHS);
19235 Opcode = X86ISD::FMAX;
19238 // Converting this to a max would handle both negative zeros and NaNs
19239 // incorrectly, but we can swap the operands to fix both.
19240 std::swap(LHS, RHS);
19244 Opcode = X86ISD::FMAX;
19250 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
19253 EVT CondVT = Cond.getValueType();
19254 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
19255 CondVT.getVectorElementType() == MVT::i1) {
19256 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
19257 // lowering on AVX-512. In this case we convert it to
19258 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
19259 // The same situation for all 128 and 256-bit vectors of i8 and i16
19260 EVT OpVT = LHS.getValueType();
19261 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
19262 (OpVT.getVectorElementType() == MVT::i8 ||
19263 OpVT.getVectorElementType() == MVT::i16)) {
19264 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
19265 DCI.AddToWorklist(Cond.getNode());
19266 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
19269 // If this is a select between two integer constants, try to do some
19271 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
19272 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
19273 // Don't do this for crazy integer types.
19274 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
19275 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
19276 // so that TrueC (the true value) is larger than FalseC.
19277 bool NeedsCondInvert = false;
19279 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
19280 // Efficiently invertible.
19281 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
19282 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
19283 isa<ConstantSDNode>(Cond.getOperand(1))))) {
19284 NeedsCondInvert = true;
19285 std::swap(TrueC, FalseC);
19288 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
19289 if (FalseC->getAPIntValue() == 0 &&
19290 TrueC->getAPIntValue().isPowerOf2()) {
19291 if (NeedsCondInvert) // Invert the condition if needed.
19292 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
19293 DAG.getConstant(1, Cond.getValueType()));
19295 // Zero extend the condition if needed.
19296 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
19298 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
19299 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
19300 DAG.getConstant(ShAmt, MVT::i8));
19303 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
19304 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
19305 if (NeedsCondInvert) // Invert the condition if needed.
19306 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
19307 DAG.getConstant(1, Cond.getValueType()));
19309 // Zero extend the condition if needed.
19310 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
19311 FalseC->getValueType(0), Cond);
19312 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
19313 SDValue(FalseC, 0));
19316 // Optimize cases that will turn into an LEA instruction. This requires
19317 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
19318 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
19319 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
19320 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
19322 bool isFastMultiplier = false;
19324 switch ((unsigned char)Diff) {
19326 case 1: // result = add base, cond
19327 case 2: // result = lea base( , cond*2)
19328 case 3: // result = lea base(cond, cond*2)
19329 case 4: // result = lea base( , cond*4)
19330 case 5: // result = lea base(cond, cond*4)
19331 case 8: // result = lea base( , cond*8)
19332 case 9: // result = lea base(cond, cond*8)
19333 isFastMultiplier = true;
19338 if (isFastMultiplier) {
19339 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
19340 if (NeedsCondInvert) // Invert the condition if needed.
19341 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
19342 DAG.getConstant(1, Cond.getValueType()));
19344 // Zero extend the condition if needed.
19345 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
19347 // Scale the condition by the difference.
19349 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
19350 DAG.getConstant(Diff, Cond.getValueType()));
19352 // Add the base if non-zero.
19353 if (FalseC->getAPIntValue() != 0)
19354 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
19355 SDValue(FalseC, 0));
19362 // Canonicalize max and min:
19363 // (x > y) ? x : y -> (x >= y) ? x : y
19364 // (x < y) ? x : y -> (x <= y) ? x : y
19365 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
19366 // the need for an extra compare
19367 // against zero. e.g.
19368 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
19370 // testl %edi, %edi
19372 // cmovgl %edi, %eax
19376 // cmovsl %eax, %edi
19377 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
19378 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
19379 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
19380 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
19385 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
19386 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
19387 Cond.getOperand(0), Cond.getOperand(1), NewCC);
19388 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
19393 // Early exit check
19394 if (!TLI.isTypeLegal(VT))
19397 // Match VSELECTs into subs with unsigned saturation.
19398 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
19399 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
19400 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
19401 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
19402 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
19404 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
19405 // left side invert the predicate to simplify logic below.
19407 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
19409 CC = ISD::getSetCCInverse(CC, true);
19410 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
19414 if (Other.getNode() && Other->getNumOperands() == 2 &&
19415 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
19416 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
19417 SDValue CondRHS = Cond->getOperand(1);
19419 // Look for a general sub with unsigned saturation first.
19420 // x >= y ? x-y : 0 --> subus x, y
19421 // x > y ? x-y : 0 --> subus x, y
19422 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
19423 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
19424 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
19426 // If the RHS is a constant we have to reverse the const canonicalization.
19427 // x > C-1 ? x+-C : 0 --> subus x, C
19428 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
19429 isSplatVector(CondRHS.getNode()) && isSplatVector(OpRHS.getNode())) {
19430 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
19431 if (CondRHS.getConstantOperandVal(0) == -A-1)
19432 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS,
19433 DAG.getConstant(-A, VT));
19436 // Another special case: If C was a sign bit, the sub has been
19437 // canonicalized into a xor.
19438 // FIXME: Would it be better to use computeKnownBits to determine whether
19439 // it's safe to decanonicalize the xor?
19440 // x s< 0 ? x^C : 0 --> subus x, C
19441 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
19442 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
19443 isSplatVector(OpRHS.getNode())) {
19444 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
19446 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
19451 // Try to match a min/max vector operation.
19452 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
19453 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
19454 unsigned Opc = ret.first;
19455 bool NeedSplit = ret.second;
19457 if (Opc && NeedSplit) {
19458 unsigned NumElems = VT.getVectorNumElements();
19459 // Extract the LHS vectors
19460 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
19461 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
19463 // Extract the RHS vectors
19464 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
19465 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
19467 // Create min/max for each subvector
19468 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
19469 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
19471 // Merge the result
19472 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
19474 return DAG.getNode(Opc, DL, VT, LHS, RHS);
19477 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
19478 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
19479 // Check if SETCC has already been promoted
19480 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
19481 // Check that condition value type matches vselect operand type
19484 assert(Cond.getValueType().isVector() &&
19485 "vector select expects a vector selector!");
19487 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
19488 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
19490 if (!TValIsAllOnes && !FValIsAllZeros) {
19491 // Try invert the condition if true value is not all 1s and false value
19493 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
19494 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
19496 if (TValIsAllZeros || FValIsAllOnes) {
19497 SDValue CC = Cond.getOperand(2);
19498 ISD::CondCode NewCC =
19499 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
19500 Cond.getOperand(0).getValueType().isInteger());
19501 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
19502 std::swap(LHS, RHS);
19503 TValIsAllOnes = FValIsAllOnes;
19504 FValIsAllZeros = TValIsAllZeros;
19508 if (TValIsAllOnes || FValIsAllZeros) {
19511 if (TValIsAllOnes && FValIsAllZeros)
19513 else if (TValIsAllOnes)
19514 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
19515 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
19516 else if (FValIsAllZeros)
19517 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
19518 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
19520 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
19524 // Try to fold this VSELECT into a MOVSS/MOVSD
19525 if (N->getOpcode() == ISD::VSELECT &&
19526 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
19527 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
19528 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
19529 bool CanFold = false;
19530 unsigned NumElems = Cond.getNumOperands();
19534 if (isZero(Cond.getOperand(0))) {
19537 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
19538 // fold (vselect <0,-1> -> (movsd A, B)
19539 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
19540 CanFold = isAllOnes(Cond.getOperand(i));
19541 } else if (isAllOnes(Cond.getOperand(0))) {
19545 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
19546 // fold (vselect <-1,0> -> (movsd B, A)
19547 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
19548 CanFold = isZero(Cond.getOperand(i));
19552 if (VT == MVT::v4i32 || VT == MVT::v4f32)
19553 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
19554 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
19557 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
19558 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
19559 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
19560 // (v2i64 (bitcast B)))))
19562 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
19563 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
19564 // (v2f64 (bitcast B)))))
19566 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
19567 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
19568 // (v2i64 (bitcast A)))))
19570 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
19571 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
19572 // (v2f64 (bitcast A)))))
19574 CanFold = (isZero(Cond.getOperand(0)) &&
19575 isZero(Cond.getOperand(1)) &&
19576 isAllOnes(Cond.getOperand(2)) &&
19577 isAllOnes(Cond.getOperand(3)));
19579 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
19580 isAllOnes(Cond.getOperand(1)) &&
19581 isZero(Cond.getOperand(2)) &&
19582 isZero(Cond.getOperand(3))) {
19584 std::swap(LHS, RHS);
19588 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
19589 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
19590 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
19591 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
19593 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
19599 // If we know that this node is legal then we know that it is going to be
19600 // matched by one of the SSE/AVX BLEND instructions. These instructions only
19601 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
19602 // to simplify previous instructions.
19603 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
19604 !DCI.isBeforeLegalize() &&
19605 // We explicitly check against v8i16 and v16i16 because, although
19606 // they're marked as Custom, they might only be legal when Cond is a
19607 // build_vector of constants. This will be taken care in a later
19609 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
19610 VT != MVT::v8i16)) {
19611 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
19613 // Don't optimize vector selects that map to mask-registers.
19617 // Check all uses of that condition operand to check whether it will be
19618 // consumed by non-BLEND instructions, which may depend on all bits are set
19620 for (SDNode::use_iterator I = Cond->use_begin(),
19621 E = Cond->use_end(); I != E; ++I)
19622 if (I->getOpcode() != ISD::VSELECT)
19623 // TODO: Add other opcodes eventually lowered into BLEND.
19626 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
19627 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
19629 APInt KnownZero, KnownOne;
19630 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
19631 DCI.isBeforeLegalizeOps());
19632 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
19633 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
19634 DCI.CommitTargetLoweringOpt(TLO);
19637 // We should generate an X86ISD::BLENDI from a vselect if its argument
19638 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
19639 // constants. This specific pattern gets generated when we split a
19640 // selector for a 512 bit vector in a machine without AVX512 (but with
19641 // 256-bit vectors), during legalization:
19643 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
19645 // Iff we find this pattern and the build_vectors are built from
19646 // constants, we translate the vselect into a shuffle_vector that we
19647 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
19648 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
19649 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
19650 if (Shuffle.getNode())
19657 // Check whether a boolean test is testing a boolean value generated by
19658 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
19661 // Simplify the following patterns:
19662 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
19663 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
19664 // to (Op EFLAGS Cond)
19666 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
19667 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
19668 // to (Op EFLAGS !Cond)
19670 // where Op could be BRCOND or CMOV.
19672 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
19673 // Quit if not CMP and SUB with its value result used.
19674 if (Cmp.getOpcode() != X86ISD::CMP &&
19675 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
19678 // Quit if not used as a boolean value.
19679 if (CC != X86::COND_E && CC != X86::COND_NE)
19682 // Check CMP operands. One of them should be 0 or 1 and the other should be
19683 // an SetCC or extended from it.
19684 SDValue Op1 = Cmp.getOperand(0);
19685 SDValue Op2 = Cmp.getOperand(1);
19688 const ConstantSDNode* C = nullptr;
19689 bool needOppositeCond = (CC == X86::COND_E);
19690 bool checkAgainstTrue = false; // Is it a comparison against 1?
19692 if ((C = dyn_cast<ConstantSDNode>(Op1)))
19694 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
19696 else // Quit if all operands are not constants.
19699 if (C->getZExtValue() == 1) {
19700 needOppositeCond = !needOppositeCond;
19701 checkAgainstTrue = true;
19702 } else if (C->getZExtValue() != 0)
19703 // Quit if the constant is neither 0 or 1.
19706 bool truncatedToBoolWithAnd = false;
19707 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
19708 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
19709 SetCC.getOpcode() == ISD::TRUNCATE ||
19710 SetCC.getOpcode() == ISD::AND) {
19711 if (SetCC.getOpcode() == ISD::AND) {
19713 ConstantSDNode *CS;
19714 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
19715 CS->getZExtValue() == 1)
19717 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
19718 CS->getZExtValue() == 1)
19722 SetCC = SetCC.getOperand(OpIdx);
19723 truncatedToBoolWithAnd = true;
19725 SetCC = SetCC.getOperand(0);
19728 switch (SetCC.getOpcode()) {
19729 case X86ISD::SETCC_CARRY:
19730 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
19731 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
19732 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
19733 // truncated to i1 using 'and'.
19734 if (checkAgainstTrue && !truncatedToBoolWithAnd)
19736 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
19737 "Invalid use of SETCC_CARRY!");
19739 case X86ISD::SETCC:
19740 // Set the condition code or opposite one if necessary.
19741 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
19742 if (needOppositeCond)
19743 CC = X86::GetOppositeBranchCondition(CC);
19744 return SetCC.getOperand(1);
19745 case X86ISD::CMOV: {
19746 // Check whether false/true value has canonical one, i.e. 0 or 1.
19747 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
19748 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
19749 // Quit if true value is not a constant.
19752 // Quit if false value is not a constant.
19754 SDValue Op = SetCC.getOperand(0);
19755 // Skip 'zext' or 'trunc' node.
19756 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
19757 Op.getOpcode() == ISD::TRUNCATE)
19758 Op = Op.getOperand(0);
19759 // A special case for rdrand/rdseed, where 0 is set if false cond is
19761 if ((Op.getOpcode() != X86ISD::RDRAND &&
19762 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
19765 // Quit if false value is not the constant 0 or 1.
19766 bool FValIsFalse = true;
19767 if (FVal && FVal->getZExtValue() != 0) {
19768 if (FVal->getZExtValue() != 1)
19770 // If FVal is 1, opposite cond is needed.
19771 needOppositeCond = !needOppositeCond;
19772 FValIsFalse = false;
19774 // Quit if TVal is not the constant opposite of FVal.
19775 if (FValIsFalse && TVal->getZExtValue() != 1)
19777 if (!FValIsFalse && TVal->getZExtValue() != 0)
19779 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
19780 if (needOppositeCond)
19781 CC = X86::GetOppositeBranchCondition(CC);
19782 return SetCC.getOperand(3);
19789 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
19790 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
19791 TargetLowering::DAGCombinerInfo &DCI,
19792 const X86Subtarget *Subtarget) {
19795 // If the flag operand isn't dead, don't touch this CMOV.
19796 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
19799 SDValue FalseOp = N->getOperand(0);
19800 SDValue TrueOp = N->getOperand(1);
19801 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
19802 SDValue Cond = N->getOperand(3);
19804 if (CC == X86::COND_E || CC == X86::COND_NE) {
19805 switch (Cond.getOpcode()) {
19809 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
19810 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
19811 return (CC == X86::COND_E) ? FalseOp : TrueOp;
19817 Flags = checkBoolTestSetCCCombine(Cond, CC);
19818 if (Flags.getNode() &&
19819 // Extra check as FCMOV only supports a subset of X86 cond.
19820 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
19821 SDValue Ops[] = { FalseOp, TrueOp,
19822 DAG.getConstant(CC, MVT::i8), Flags };
19823 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
19826 // If this is a select between two integer constants, try to do some
19827 // optimizations. Note that the operands are ordered the opposite of SELECT
19829 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
19830 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
19831 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
19832 // larger than FalseC (the false value).
19833 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
19834 CC = X86::GetOppositeBranchCondition(CC);
19835 std::swap(TrueC, FalseC);
19836 std::swap(TrueOp, FalseOp);
19839 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
19840 // This is efficient for any integer data type (including i8/i16) and
19842 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
19843 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
19844 DAG.getConstant(CC, MVT::i8), Cond);
19846 // Zero extend the condition if needed.
19847 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
19849 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
19850 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
19851 DAG.getConstant(ShAmt, MVT::i8));
19852 if (N->getNumValues() == 2) // Dead flag value?
19853 return DCI.CombineTo(N, Cond, SDValue());
19857 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
19858 // for any integer data type, including i8/i16.
19859 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
19860 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
19861 DAG.getConstant(CC, MVT::i8), Cond);
19863 // Zero extend the condition if needed.
19864 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
19865 FalseC->getValueType(0), Cond);
19866 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
19867 SDValue(FalseC, 0));
19869 if (N->getNumValues() == 2) // Dead flag value?
19870 return DCI.CombineTo(N, Cond, SDValue());
19874 // Optimize cases that will turn into an LEA instruction. This requires
19875 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
19876 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
19877 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
19878 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
19880 bool isFastMultiplier = false;
19882 switch ((unsigned char)Diff) {
19884 case 1: // result = add base, cond
19885 case 2: // result = lea base( , cond*2)
19886 case 3: // result = lea base(cond, cond*2)
19887 case 4: // result = lea base( , cond*4)
19888 case 5: // result = lea base(cond, cond*4)
19889 case 8: // result = lea base( , cond*8)
19890 case 9: // result = lea base(cond, cond*8)
19891 isFastMultiplier = true;
19896 if (isFastMultiplier) {
19897 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
19898 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
19899 DAG.getConstant(CC, MVT::i8), Cond);
19900 // Zero extend the condition if needed.
19901 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
19903 // Scale the condition by the difference.
19905 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
19906 DAG.getConstant(Diff, Cond.getValueType()));
19908 // Add the base if non-zero.
19909 if (FalseC->getAPIntValue() != 0)
19910 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
19911 SDValue(FalseC, 0));
19912 if (N->getNumValues() == 2) // Dead flag value?
19913 return DCI.CombineTo(N, Cond, SDValue());
19920 // Handle these cases:
19921 // (select (x != c), e, c) -> select (x != c), e, x),
19922 // (select (x == c), c, e) -> select (x == c), x, e)
19923 // where the c is an integer constant, and the "select" is the combination
19924 // of CMOV and CMP.
19926 // The rationale for this change is that the conditional-move from a constant
19927 // needs two instructions, however, conditional-move from a register needs
19928 // only one instruction.
19930 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
19931 // some instruction-combining opportunities. This opt needs to be
19932 // postponed as late as possible.
19934 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
19935 // the DCI.xxxx conditions are provided to postpone the optimization as
19936 // late as possible.
19938 ConstantSDNode *CmpAgainst = nullptr;
19939 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
19940 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
19941 !isa<ConstantSDNode>(Cond.getOperand(0))) {
19943 if (CC == X86::COND_NE &&
19944 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
19945 CC = X86::GetOppositeBranchCondition(CC);
19946 std::swap(TrueOp, FalseOp);
19949 if (CC == X86::COND_E &&
19950 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
19951 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
19952 DAG.getConstant(CC, MVT::i8), Cond };
19953 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
19961 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
19962 const X86Subtarget *Subtarget) {
19963 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
19965 default: return SDValue();
19966 // SSE/AVX/AVX2 blend intrinsics.
19967 case Intrinsic::x86_avx2_pblendvb:
19968 case Intrinsic::x86_avx2_pblendw:
19969 case Intrinsic::x86_avx2_pblendd_128:
19970 case Intrinsic::x86_avx2_pblendd_256:
19971 // Don't try to simplify this intrinsic if we don't have AVX2.
19972 if (!Subtarget->hasAVX2())
19975 case Intrinsic::x86_avx_blend_pd_256:
19976 case Intrinsic::x86_avx_blend_ps_256:
19977 case Intrinsic::x86_avx_blendv_pd_256:
19978 case Intrinsic::x86_avx_blendv_ps_256:
19979 // Don't try to simplify this intrinsic if we don't have AVX.
19980 if (!Subtarget->hasAVX())
19983 case Intrinsic::x86_sse41_pblendw:
19984 case Intrinsic::x86_sse41_blendpd:
19985 case Intrinsic::x86_sse41_blendps:
19986 case Intrinsic::x86_sse41_blendvps:
19987 case Intrinsic::x86_sse41_blendvpd:
19988 case Intrinsic::x86_sse41_pblendvb: {
19989 SDValue Op0 = N->getOperand(1);
19990 SDValue Op1 = N->getOperand(2);
19991 SDValue Mask = N->getOperand(3);
19993 // Don't try to simplify this intrinsic if we don't have SSE4.1.
19994 if (!Subtarget->hasSSE41())
19997 // fold (blend A, A, Mask) -> A
20000 // fold (blend A, B, allZeros) -> A
20001 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
20003 // fold (blend A, B, allOnes) -> B
20004 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
20007 // Simplify the case where the mask is a constant i32 value.
20008 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
20009 if (C->isNullValue())
20011 if (C->isAllOnesValue())
20018 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
20019 case Intrinsic::x86_sse2_psrai_w:
20020 case Intrinsic::x86_sse2_psrai_d:
20021 case Intrinsic::x86_avx2_psrai_w:
20022 case Intrinsic::x86_avx2_psrai_d:
20023 case Intrinsic::x86_sse2_psra_w:
20024 case Intrinsic::x86_sse2_psra_d:
20025 case Intrinsic::x86_avx2_psra_w:
20026 case Intrinsic::x86_avx2_psra_d: {
20027 SDValue Op0 = N->getOperand(1);
20028 SDValue Op1 = N->getOperand(2);
20029 EVT VT = Op0.getValueType();
20030 assert(VT.isVector() && "Expected a vector type!");
20032 if (isa<BuildVectorSDNode>(Op1))
20033 Op1 = Op1.getOperand(0);
20035 if (!isa<ConstantSDNode>(Op1))
20038 EVT SVT = VT.getVectorElementType();
20039 unsigned SVTBits = SVT.getSizeInBits();
20041 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
20042 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
20043 uint64_t ShAmt = C.getZExtValue();
20045 // Don't try to convert this shift into a ISD::SRA if the shift
20046 // count is bigger than or equal to the element size.
20047 if (ShAmt >= SVTBits)
20050 // Trivial case: if the shift count is zero, then fold this
20051 // into the first operand.
20055 // Replace this packed shift intrinsic with a target independent
20057 SDValue Splat = DAG.getConstant(C, VT);
20058 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
20063 /// PerformMulCombine - Optimize a single multiply with constant into two
20064 /// in order to implement it with two cheaper instructions, e.g.
20065 /// LEA + SHL, LEA + LEA.
20066 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
20067 TargetLowering::DAGCombinerInfo &DCI) {
20068 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
20071 EVT VT = N->getValueType(0);
20072 if (VT != MVT::i64)
20075 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
20078 uint64_t MulAmt = C->getZExtValue();
20079 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
20082 uint64_t MulAmt1 = 0;
20083 uint64_t MulAmt2 = 0;
20084 if ((MulAmt % 9) == 0) {
20086 MulAmt2 = MulAmt / 9;
20087 } else if ((MulAmt % 5) == 0) {
20089 MulAmt2 = MulAmt / 5;
20090 } else if ((MulAmt % 3) == 0) {
20092 MulAmt2 = MulAmt / 3;
20095 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
20098 if (isPowerOf2_64(MulAmt2) &&
20099 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
20100 // If second multiplifer is pow2, issue it first. We want the multiply by
20101 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
20103 std::swap(MulAmt1, MulAmt2);
20106 if (isPowerOf2_64(MulAmt1))
20107 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
20108 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
20110 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
20111 DAG.getConstant(MulAmt1, VT));
20113 if (isPowerOf2_64(MulAmt2))
20114 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
20115 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
20117 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
20118 DAG.getConstant(MulAmt2, VT));
20120 // Do not add new nodes to DAG combiner worklist.
20121 DCI.CombineTo(N, NewMul, false);
20126 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
20127 SDValue N0 = N->getOperand(0);
20128 SDValue N1 = N->getOperand(1);
20129 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
20130 EVT VT = N0.getValueType();
20132 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
20133 // since the result of setcc_c is all zero's or all ones.
20134 if (VT.isInteger() && !VT.isVector() &&
20135 N1C && N0.getOpcode() == ISD::AND &&
20136 N0.getOperand(1).getOpcode() == ISD::Constant) {
20137 SDValue N00 = N0.getOperand(0);
20138 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
20139 ((N00.getOpcode() == ISD::ANY_EXTEND ||
20140 N00.getOpcode() == ISD::ZERO_EXTEND) &&
20141 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
20142 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
20143 APInt ShAmt = N1C->getAPIntValue();
20144 Mask = Mask.shl(ShAmt);
20146 return DAG.getNode(ISD::AND, SDLoc(N), VT,
20147 N00, DAG.getConstant(Mask, VT));
20151 // Hardware support for vector shifts is sparse which makes us scalarize the
20152 // vector operations in many cases. Also, on sandybridge ADD is faster than
20154 // (shl V, 1) -> add V,V
20155 if (isSplatVector(N1.getNode())) {
20156 assert(N0.getValueType().isVector() && "Invalid vector shift type");
20157 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
20158 // We shift all of the values by one. In many cases we do not have
20159 // hardware support for this operation. This is better expressed as an ADD
20161 if (N1C && (1 == N1C->getZExtValue())) {
20162 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
20169 /// \brief Returns a vector of 0s if the node in input is a vector logical
20170 /// shift by a constant amount which is known to be bigger than or equal
20171 /// to the vector element size in bits.
20172 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
20173 const X86Subtarget *Subtarget) {
20174 EVT VT = N->getValueType(0);
20176 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
20177 (!Subtarget->hasInt256() ||
20178 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
20181 SDValue Amt = N->getOperand(1);
20183 if (isSplatVector(Amt.getNode())) {
20184 SDValue SclrAmt = Amt->getOperand(0);
20185 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
20186 APInt ShiftAmt = C->getAPIntValue();
20187 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
20189 // SSE2/AVX2 logical shifts always return a vector of 0s
20190 // if the shift amount is bigger than or equal to
20191 // the element size. The constant shift amount will be
20192 // encoded as a 8-bit immediate.
20193 if (ShiftAmt.trunc(8).uge(MaxAmount))
20194 return getZeroVector(VT, Subtarget, DAG, DL);
20201 /// PerformShiftCombine - Combine shifts.
20202 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
20203 TargetLowering::DAGCombinerInfo &DCI,
20204 const X86Subtarget *Subtarget) {
20205 if (N->getOpcode() == ISD::SHL) {
20206 SDValue V = PerformSHLCombine(N, DAG);
20207 if (V.getNode()) return V;
20210 if (N->getOpcode() != ISD::SRA) {
20211 // Try to fold this logical shift into a zero vector.
20212 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
20213 if (V.getNode()) return V;
20219 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
20220 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
20221 // and friends. Likewise for OR -> CMPNEQSS.
20222 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
20223 TargetLowering::DAGCombinerInfo &DCI,
20224 const X86Subtarget *Subtarget) {
20227 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
20228 // we're requiring SSE2 for both.
20229 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
20230 SDValue N0 = N->getOperand(0);
20231 SDValue N1 = N->getOperand(1);
20232 SDValue CMP0 = N0->getOperand(1);
20233 SDValue CMP1 = N1->getOperand(1);
20236 // The SETCCs should both refer to the same CMP.
20237 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
20240 SDValue CMP00 = CMP0->getOperand(0);
20241 SDValue CMP01 = CMP0->getOperand(1);
20242 EVT VT = CMP00.getValueType();
20244 if (VT == MVT::f32 || VT == MVT::f64) {
20245 bool ExpectingFlags = false;
20246 // Check for any users that want flags:
20247 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
20248 !ExpectingFlags && UI != UE; ++UI)
20249 switch (UI->getOpcode()) {
20254 ExpectingFlags = true;
20256 case ISD::CopyToReg:
20257 case ISD::SIGN_EXTEND:
20258 case ISD::ZERO_EXTEND:
20259 case ISD::ANY_EXTEND:
20263 if (!ExpectingFlags) {
20264 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
20265 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
20267 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
20268 X86::CondCode tmp = cc0;
20273 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
20274 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
20275 // FIXME: need symbolic constants for these magic numbers.
20276 // See X86ATTInstPrinter.cpp:printSSECC().
20277 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
20278 if (Subtarget->hasAVX512()) {
20279 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
20280 CMP01, DAG.getConstant(x86cc, MVT::i8));
20281 if (N->getValueType(0) != MVT::i1)
20282 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
20286 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
20287 CMP00.getValueType(), CMP00, CMP01,
20288 DAG.getConstant(x86cc, MVT::i8));
20290 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
20291 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
20293 if (is64BitFP && !Subtarget->is64Bit()) {
20294 // On a 32-bit target, we cannot bitcast the 64-bit float to a
20295 // 64-bit integer, since that's not a legal type. Since
20296 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
20297 // bits, but can do this little dance to extract the lowest 32 bits
20298 // and work with those going forward.
20299 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
20301 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
20303 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
20304 Vector32, DAG.getIntPtrConstant(0));
20308 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
20309 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
20310 DAG.getConstant(1, IntVT));
20311 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
20312 return OneBitOfTruth;
20320 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
20321 /// so it can be folded inside ANDNP.
20322 static bool CanFoldXORWithAllOnes(const SDNode *N) {
20323 EVT VT = N->getValueType(0);
20325 // Match direct AllOnes for 128 and 256-bit vectors
20326 if (ISD::isBuildVectorAllOnes(N))
20329 // Look through a bit convert.
20330 if (N->getOpcode() == ISD::BITCAST)
20331 N = N->getOperand(0).getNode();
20333 // Sometimes the operand may come from a insert_subvector building a 256-bit
20335 if (VT.is256BitVector() &&
20336 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
20337 SDValue V1 = N->getOperand(0);
20338 SDValue V2 = N->getOperand(1);
20340 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
20341 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
20342 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
20343 ISD::isBuildVectorAllOnes(V2.getNode()))
20350 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
20351 // register. In most cases we actually compare or select YMM-sized registers
20352 // and mixing the two types creates horrible code. This method optimizes
20353 // some of the transition sequences.
20354 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
20355 TargetLowering::DAGCombinerInfo &DCI,
20356 const X86Subtarget *Subtarget) {
20357 EVT VT = N->getValueType(0);
20358 if (!VT.is256BitVector())
20361 assert((N->getOpcode() == ISD::ANY_EXTEND ||
20362 N->getOpcode() == ISD::ZERO_EXTEND ||
20363 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
20365 SDValue Narrow = N->getOperand(0);
20366 EVT NarrowVT = Narrow->getValueType(0);
20367 if (!NarrowVT.is128BitVector())
20370 if (Narrow->getOpcode() != ISD::XOR &&
20371 Narrow->getOpcode() != ISD::AND &&
20372 Narrow->getOpcode() != ISD::OR)
20375 SDValue N0 = Narrow->getOperand(0);
20376 SDValue N1 = Narrow->getOperand(1);
20379 // The Left side has to be a trunc.
20380 if (N0.getOpcode() != ISD::TRUNCATE)
20383 // The type of the truncated inputs.
20384 EVT WideVT = N0->getOperand(0)->getValueType(0);
20388 // The right side has to be a 'trunc' or a constant vector.
20389 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
20390 bool RHSConst = (isSplatVector(N1.getNode()) &&
20391 isa<ConstantSDNode>(N1->getOperand(0)));
20392 if (!RHSTrunc && !RHSConst)
20395 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20397 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
20400 // Set N0 and N1 to hold the inputs to the new wide operation.
20401 N0 = N0->getOperand(0);
20403 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
20404 N1->getOperand(0));
20405 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
20406 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
20407 } else if (RHSTrunc) {
20408 N1 = N1->getOperand(0);
20411 // Generate the wide operation.
20412 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
20413 unsigned Opcode = N->getOpcode();
20415 case ISD::ANY_EXTEND:
20417 case ISD::ZERO_EXTEND: {
20418 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
20419 APInt Mask = APInt::getAllOnesValue(InBits);
20420 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
20421 return DAG.getNode(ISD::AND, DL, VT,
20422 Op, DAG.getConstant(Mask, VT));
20424 case ISD::SIGN_EXTEND:
20425 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
20426 Op, DAG.getValueType(NarrowVT));
20428 llvm_unreachable("Unexpected opcode");
20432 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
20433 TargetLowering::DAGCombinerInfo &DCI,
20434 const X86Subtarget *Subtarget) {
20435 EVT VT = N->getValueType(0);
20436 if (DCI.isBeforeLegalizeOps())
20439 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
20443 // Create BEXTR instructions
20444 // BEXTR is ((X >> imm) & (2**size-1))
20445 if (VT == MVT::i32 || VT == MVT::i64) {
20446 SDValue N0 = N->getOperand(0);
20447 SDValue N1 = N->getOperand(1);
20450 // Check for BEXTR.
20451 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
20452 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
20453 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
20454 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
20455 if (MaskNode && ShiftNode) {
20456 uint64_t Mask = MaskNode->getZExtValue();
20457 uint64_t Shift = ShiftNode->getZExtValue();
20458 if (isMask_64(Mask)) {
20459 uint64_t MaskSize = CountPopulation_64(Mask);
20460 if (Shift + MaskSize <= VT.getSizeInBits())
20461 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
20462 DAG.getConstant(Shift | (MaskSize << 8), VT));
20470 // Want to form ANDNP nodes:
20471 // 1) In the hopes of then easily combining them with OR and AND nodes
20472 // to form PBLEND/PSIGN.
20473 // 2) To match ANDN packed intrinsics
20474 if (VT != MVT::v2i64 && VT != MVT::v4i64)
20477 SDValue N0 = N->getOperand(0);
20478 SDValue N1 = N->getOperand(1);
20481 // Check LHS for vnot
20482 if (N0.getOpcode() == ISD::XOR &&
20483 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
20484 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
20485 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
20487 // Check RHS for vnot
20488 if (N1.getOpcode() == ISD::XOR &&
20489 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
20490 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
20491 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
20496 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
20497 TargetLowering::DAGCombinerInfo &DCI,
20498 const X86Subtarget *Subtarget) {
20499 if (DCI.isBeforeLegalizeOps())
20502 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
20506 SDValue N0 = N->getOperand(0);
20507 SDValue N1 = N->getOperand(1);
20508 EVT VT = N->getValueType(0);
20510 // look for psign/blend
20511 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
20512 if (!Subtarget->hasSSSE3() ||
20513 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
20516 // Canonicalize pandn to RHS
20517 if (N0.getOpcode() == X86ISD::ANDNP)
20519 // or (and (m, y), (pandn m, x))
20520 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
20521 SDValue Mask = N1.getOperand(0);
20522 SDValue X = N1.getOperand(1);
20524 if (N0.getOperand(0) == Mask)
20525 Y = N0.getOperand(1);
20526 if (N0.getOperand(1) == Mask)
20527 Y = N0.getOperand(0);
20529 // Check to see if the mask appeared in both the AND and ANDNP and
20533 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
20534 // Look through mask bitcast.
20535 if (Mask.getOpcode() == ISD::BITCAST)
20536 Mask = Mask.getOperand(0);
20537 if (X.getOpcode() == ISD::BITCAST)
20538 X = X.getOperand(0);
20539 if (Y.getOpcode() == ISD::BITCAST)
20540 Y = Y.getOperand(0);
20542 EVT MaskVT = Mask.getValueType();
20544 // Validate that the Mask operand is a vector sra node.
20545 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
20546 // there is no psrai.b
20547 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
20548 unsigned SraAmt = ~0;
20549 if (Mask.getOpcode() == ISD::SRA) {
20550 SDValue Amt = Mask.getOperand(1);
20551 if (isSplatVector(Amt.getNode())) {
20552 SDValue SclrAmt = Amt->getOperand(0);
20553 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt))
20554 SraAmt = C->getZExtValue();
20556 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
20557 SDValue SraC = Mask.getOperand(1);
20558 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
20560 if ((SraAmt + 1) != EltBits)
20565 // Now we know we at least have a plendvb with the mask val. See if
20566 // we can form a psignb/w/d.
20567 // psign = x.type == y.type == mask.type && y = sub(0, x);
20568 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
20569 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
20570 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
20571 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
20572 "Unsupported VT for PSIGN");
20573 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
20574 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
20576 // PBLENDVB only available on SSE 4.1
20577 if (!Subtarget->hasSSE41())
20580 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
20582 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
20583 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
20584 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
20585 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
20586 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
20590 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
20593 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
20594 MachineFunction &MF = DAG.getMachineFunction();
20595 bool OptForSize = MF.getFunction()->getAttributes().
20596 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
20598 // SHLD/SHRD instructions have lower register pressure, but on some
20599 // platforms they have higher latency than the equivalent
20600 // series of shifts/or that would otherwise be generated.
20601 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
20602 // have higher latencies and we are not optimizing for size.
20603 if (!OptForSize && Subtarget->isSHLDSlow())
20606 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
20608 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
20610 if (!N0.hasOneUse() || !N1.hasOneUse())
20613 SDValue ShAmt0 = N0.getOperand(1);
20614 if (ShAmt0.getValueType() != MVT::i8)
20616 SDValue ShAmt1 = N1.getOperand(1);
20617 if (ShAmt1.getValueType() != MVT::i8)
20619 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
20620 ShAmt0 = ShAmt0.getOperand(0);
20621 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
20622 ShAmt1 = ShAmt1.getOperand(0);
20625 unsigned Opc = X86ISD::SHLD;
20626 SDValue Op0 = N0.getOperand(0);
20627 SDValue Op1 = N1.getOperand(0);
20628 if (ShAmt0.getOpcode() == ISD::SUB) {
20629 Opc = X86ISD::SHRD;
20630 std::swap(Op0, Op1);
20631 std::swap(ShAmt0, ShAmt1);
20634 unsigned Bits = VT.getSizeInBits();
20635 if (ShAmt1.getOpcode() == ISD::SUB) {
20636 SDValue Sum = ShAmt1.getOperand(0);
20637 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
20638 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
20639 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
20640 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
20641 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
20642 return DAG.getNode(Opc, DL, VT,
20644 DAG.getNode(ISD::TRUNCATE, DL,
20647 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
20648 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
20650 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
20651 return DAG.getNode(Opc, DL, VT,
20652 N0.getOperand(0), N1.getOperand(0),
20653 DAG.getNode(ISD::TRUNCATE, DL,
20660 // Generate NEG and CMOV for integer abs.
20661 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
20662 EVT VT = N->getValueType(0);
20664 // Since X86 does not have CMOV for 8-bit integer, we don't convert
20665 // 8-bit integer abs to NEG and CMOV.
20666 if (VT.isInteger() && VT.getSizeInBits() == 8)
20669 SDValue N0 = N->getOperand(0);
20670 SDValue N1 = N->getOperand(1);
20673 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
20674 // and change it to SUB and CMOV.
20675 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
20676 N0.getOpcode() == ISD::ADD &&
20677 N0.getOperand(1) == N1 &&
20678 N1.getOpcode() == ISD::SRA &&
20679 N1.getOperand(0) == N0.getOperand(0))
20680 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
20681 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
20682 // Generate SUB & CMOV.
20683 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
20684 DAG.getConstant(0, VT), N0.getOperand(0));
20686 SDValue Ops[] = { N0.getOperand(0), Neg,
20687 DAG.getConstant(X86::COND_GE, MVT::i8),
20688 SDValue(Neg.getNode(), 1) };
20689 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
20694 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
20695 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
20696 TargetLowering::DAGCombinerInfo &DCI,
20697 const X86Subtarget *Subtarget) {
20698 if (DCI.isBeforeLegalizeOps())
20701 if (Subtarget->hasCMov()) {
20702 SDValue RV = performIntegerAbsCombine(N, DAG);
20710 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
20711 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
20712 TargetLowering::DAGCombinerInfo &DCI,
20713 const X86Subtarget *Subtarget) {
20714 LoadSDNode *Ld = cast<LoadSDNode>(N);
20715 EVT RegVT = Ld->getValueType(0);
20716 EVT MemVT = Ld->getMemoryVT();
20718 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20719 unsigned RegSz = RegVT.getSizeInBits();
20721 // On Sandybridge unaligned 256bit loads are inefficient.
20722 ISD::LoadExtType Ext = Ld->getExtensionType();
20723 unsigned Alignment = Ld->getAlignment();
20724 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
20725 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
20726 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
20727 unsigned NumElems = RegVT.getVectorNumElements();
20731 SDValue Ptr = Ld->getBasePtr();
20732 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
20734 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
20736 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
20737 Ld->getPointerInfo(), Ld->isVolatile(),
20738 Ld->isNonTemporal(), Ld->isInvariant(),
20740 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
20741 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
20742 Ld->getPointerInfo(), Ld->isVolatile(),
20743 Ld->isNonTemporal(), Ld->isInvariant(),
20744 std::min(16U, Alignment));
20745 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
20747 Load2.getValue(1));
20749 SDValue NewVec = DAG.getUNDEF(RegVT);
20750 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
20751 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
20752 return DCI.CombineTo(N, NewVec, TF, true);
20755 // If this is a vector EXT Load then attempt to optimize it using a
20756 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
20757 // expansion is still better than scalar code.
20758 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll
20759 // emit a shuffle and a arithmetic shift.
20760 // TODO: It is possible to support ZExt by zeroing the undef values
20761 // during the shuffle phase or after the shuffle.
20762 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() &&
20763 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) {
20764 assert(MemVT != RegVT && "Cannot extend to the same type");
20765 assert(MemVT.isVector() && "Must load a vector from memory");
20767 unsigned NumElems = RegVT.getVectorNumElements();
20768 unsigned MemSz = MemVT.getSizeInBits();
20769 assert(RegSz > MemSz && "Register size must be greater than the mem size");
20771 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())
20774 // All sizes must be a power of two.
20775 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
20778 // Attempt to load the original value using scalar loads.
20779 // Find the largest scalar type that divides the total loaded size.
20780 MVT SclrLoadTy = MVT::i8;
20781 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
20782 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
20783 MVT Tp = (MVT::SimpleValueType)tp;
20784 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
20789 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
20790 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
20792 SclrLoadTy = MVT::f64;
20794 // Calculate the number of scalar loads that we need to perform
20795 // in order to load our vector from memory.
20796 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
20797 if (Ext == ISD::SEXTLOAD && NumLoads > 1)
20800 unsigned loadRegZize = RegSz;
20801 if (Ext == ISD::SEXTLOAD && RegSz == 256)
20804 // Represent our vector as a sequence of elements which are the
20805 // largest scalar that we can load.
20806 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
20807 loadRegZize/SclrLoadTy.getSizeInBits());
20809 // Represent the data using the same element type that is stored in
20810 // memory. In practice, we ''widen'' MemVT.
20812 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
20813 loadRegZize/MemVT.getScalarType().getSizeInBits());
20815 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
20816 "Invalid vector type");
20818 // We can't shuffle using an illegal type.
20819 if (!TLI.isTypeLegal(WideVecVT))
20822 SmallVector<SDValue, 8> Chains;
20823 SDValue Ptr = Ld->getBasePtr();
20824 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
20825 TLI.getPointerTy());
20826 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
20828 for (unsigned i = 0; i < NumLoads; ++i) {
20829 // Perform a single load.
20830 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
20831 Ptr, Ld->getPointerInfo(),
20832 Ld->isVolatile(), Ld->isNonTemporal(),
20833 Ld->isInvariant(), Ld->getAlignment());
20834 Chains.push_back(ScalarLoad.getValue(1));
20835 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
20836 // another round of DAGCombining.
20838 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
20840 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
20841 ScalarLoad, DAG.getIntPtrConstant(i));
20843 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
20846 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
20848 // Bitcast the loaded value to a vector of the original element type, in
20849 // the size of the target vector type.
20850 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
20851 unsigned SizeRatio = RegSz/MemSz;
20853 if (Ext == ISD::SEXTLOAD) {
20854 // If we have SSE4.1 we can directly emit a VSEXT node.
20855 if (Subtarget->hasSSE41()) {
20856 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
20857 return DCI.CombineTo(N, Sext, TF, true);
20860 // Otherwise we'll shuffle the small elements in the high bits of the
20861 // larger type and perform an arithmetic shift. If the shift is not legal
20862 // it's better to scalarize.
20863 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
20866 // Redistribute the loaded elements into the different locations.
20867 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
20868 for (unsigned i = 0; i != NumElems; ++i)
20869 ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
20871 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
20872 DAG.getUNDEF(WideVecVT),
20875 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
20877 // Build the arithmetic shift.
20878 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
20879 MemVT.getVectorElementType().getSizeInBits();
20880 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
20881 DAG.getConstant(Amt, RegVT));
20883 return DCI.CombineTo(N, Shuff, TF, true);
20886 // Redistribute the loaded elements into the different locations.
20887 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
20888 for (unsigned i = 0; i != NumElems; ++i)
20889 ShuffleVec[i*SizeRatio] = i;
20891 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
20892 DAG.getUNDEF(WideVecVT),
20895 // Bitcast to the requested type.
20896 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
20897 // Replace the original load with the new sequence
20898 // and return the new chain.
20899 return DCI.CombineTo(N, Shuff, TF, true);
20905 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
20906 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
20907 const X86Subtarget *Subtarget) {
20908 StoreSDNode *St = cast<StoreSDNode>(N);
20909 EVT VT = St->getValue().getValueType();
20910 EVT StVT = St->getMemoryVT();
20912 SDValue StoredVal = St->getOperand(1);
20913 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20915 // If we are saving a concatenation of two XMM registers, perform two stores.
20916 // On Sandy Bridge, 256-bit memory operations are executed by two
20917 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
20918 // memory operation.
20919 unsigned Alignment = St->getAlignment();
20920 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
20921 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
20922 StVT == VT && !IsAligned) {
20923 unsigned NumElems = VT.getVectorNumElements();
20927 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
20928 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
20930 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
20931 SDValue Ptr0 = St->getBasePtr();
20932 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
20934 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
20935 St->getPointerInfo(), St->isVolatile(),
20936 St->isNonTemporal(), Alignment);
20937 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
20938 St->getPointerInfo(), St->isVolatile(),
20939 St->isNonTemporal(),
20940 std::min(16U, Alignment));
20941 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
20944 // Optimize trunc store (of multiple scalars) to shuffle and store.
20945 // First, pack all of the elements in one place. Next, store to memory
20946 // in fewer chunks.
20947 if (St->isTruncatingStore() && VT.isVector()) {
20948 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20949 unsigned NumElems = VT.getVectorNumElements();
20950 assert(StVT != VT && "Cannot truncate to the same type");
20951 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
20952 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
20954 // From, To sizes and ElemCount must be pow of two
20955 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
20956 // We are going to use the original vector elt for storing.
20957 // Accumulated smaller vector elements must be a multiple of the store size.
20958 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
20960 unsigned SizeRatio = FromSz / ToSz;
20962 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
20964 // Create a type on which we perform the shuffle
20965 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
20966 StVT.getScalarType(), NumElems*SizeRatio);
20968 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
20970 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
20971 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
20972 for (unsigned i = 0; i != NumElems; ++i)
20973 ShuffleVec[i] = i * SizeRatio;
20975 // Can't shuffle using an illegal type.
20976 if (!TLI.isTypeLegal(WideVecVT))
20979 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
20980 DAG.getUNDEF(WideVecVT),
20982 // At this point all of the data is stored at the bottom of the
20983 // register. We now need to save it to mem.
20985 // Find the largest store unit
20986 MVT StoreType = MVT::i8;
20987 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
20988 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
20989 MVT Tp = (MVT::SimpleValueType)tp;
20990 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
20994 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
20995 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
20996 (64 <= NumElems * ToSz))
20997 StoreType = MVT::f64;
20999 // Bitcast the original vector into a vector of store-size units
21000 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
21001 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
21002 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
21003 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
21004 SmallVector<SDValue, 8> Chains;
21005 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
21006 TLI.getPointerTy());
21007 SDValue Ptr = St->getBasePtr();
21009 // Perform one or more big stores into memory.
21010 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
21011 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
21012 StoreType, ShuffWide,
21013 DAG.getIntPtrConstant(i));
21014 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
21015 St->getPointerInfo(), St->isVolatile(),
21016 St->isNonTemporal(), St->getAlignment());
21017 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
21018 Chains.push_back(Ch);
21021 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
21024 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
21025 // the FP state in cases where an emms may be missing.
21026 // A preferable solution to the general problem is to figure out the right
21027 // places to insert EMMS. This qualifies as a quick hack.
21029 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
21030 if (VT.getSizeInBits() != 64)
21033 const Function *F = DAG.getMachineFunction().getFunction();
21034 bool NoImplicitFloatOps = F->getAttributes().
21035 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
21036 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
21037 && Subtarget->hasSSE2();
21038 if ((VT.isVector() ||
21039 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
21040 isa<LoadSDNode>(St->getValue()) &&
21041 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
21042 St->getChain().hasOneUse() && !St->isVolatile()) {
21043 SDNode* LdVal = St->getValue().getNode();
21044 LoadSDNode *Ld = nullptr;
21045 int TokenFactorIndex = -1;
21046 SmallVector<SDValue, 8> Ops;
21047 SDNode* ChainVal = St->getChain().getNode();
21048 // Must be a store of a load. We currently handle two cases: the load
21049 // is a direct child, and it's under an intervening TokenFactor. It is
21050 // possible to dig deeper under nested TokenFactors.
21051 if (ChainVal == LdVal)
21052 Ld = cast<LoadSDNode>(St->getChain());
21053 else if (St->getValue().hasOneUse() &&
21054 ChainVal->getOpcode() == ISD::TokenFactor) {
21055 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
21056 if (ChainVal->getOperand(i).getNode() == LdVal) {
21057 TokenFactorIndex = i;
21058 Ld = cast<LoadSDNode>(St->getValue());
21060 Ops.push_back(ChainVal->getOperand(i));
21064 if (!Ld || !ISD::isNormalLoad(Ld))
21067 // If this is not the MMX case, i.e. we are just turning i64 load/store
21068 // into f64 load/store, avoid the transformation if there are multiple
21069 // uses of the loaded value.
21070 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
21075 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
21076 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
21078 if (Subtarget->is64Bit() || F64IsLegal) {
21079 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
21080 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
21081 Ld->getPointerInfo(), Ld->isVolatile(),
21082 Ld->isNonTemporal(), Ld->isInvariant(),
21083 Ld->getAlignment());
21084 SDValue NewChain = NewLd.getValue(1);
21085 if (TokenFactorIndex != -1) {
21086 Ops.push_back(NewChain);
21087 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
21089 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
21090 St->getPointerInfo(),
21091 St->isVolatile(), St->isNonTemporal(),
21092 St->getAlignment());
21095 // Otherwise, lower to two pairs of 32-bit loads / stores.
21096 SDValue LoAddr = Ld->getBasePtr();
21097 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
21098 DAG.getConstant(4, MVT::i32));
21100 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
21101 Ld->getPointerInfo(),
21102 Ld->isVolatile(), Ld->isNonTemporal(),
21103 Ld->isInvariant(), Ld->getAlignment());
21104 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
21105 Ld->getPointerInfo().getWithOffset(4),
21106 Ld->isVolatile(), Ld->isNonTemporal(),
21108 MinAlign(Ld->getAlignment(), 4));
21110 SDValue NewChain = LoLd.getValue(1);
21111 if (TokenFactorIndex != -1) {
21112 Ops.push_back(LoLd);
21113 Ops.push_back(HiLd);
21114 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
21117 LoAddr = St->getBasePtr();
21118 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
21119 DAG.getConstant(4, MVT::i32));
21121 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
21122 St->getPointerInfo(),
21123 St->isVolatile(), St->isNonTemporal(),
21124 St->getAlignment());
21125 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
21126 St->getPointerInfo().getWithOffset(4),
21128 St->isNonTemporal(),
21129 MinAlign(St->getAlignment(), 4));
21130 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
21135 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
21136 /// and return the operands for the horizontal operation in LHS and RHS. A
21137 /// horizontal operation performs the binary operation on successive elements
21138 /// of its first operand, then on successive elements of its second operand,
21139 /// returning the resulting values in a vector. For example, if
21140 /// A = < float a0, float a1, float a2, float a3 >
21142 /// B = < float b0, float b1, float b2, float b3 >
21143 /// then the result of doing a horizontal operation on A and B is
21144 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
21145 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
21146 /// A horizontal-op B, for some already available A and B, and if so then LHS is
21147 /// set to A, RHS to B, and the routine returns 'true'.
21148 /// Note that the binary operation should have the property that if one of the
21149 /// operands is UNDEF then the result is UNDEF.
21150 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
21151 // Look for the following pattern: if
21152 // A = < float a0, float a1, float a2, float a3 >
21153 // B = < float b0, float b1, float b2, float b3 >
21155 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
21156 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
21157 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
21158 // which is A horizontal-op B.
21160 // At least one of the operands should be a vector shuffle.
21161 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
21162 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
21165 MVT VT = LHS.getSimpleValueType();
21167 assert((VT.is128BitVector() || VT.is256BitVector()) &&
21168 "Unsupported vector type for horizontal add/sub");
21170 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
21171 // operate independently on 128-bit lanes.
21172 unsigned NumElts = VT.getVectorNumElements();
21173 unsigned NumLanes = VT.getSizeInBits()/128;
21174 unsigned NumLaneElts = NumElts / NumLanes;
21175 assert((NumLaneElts % 2 == 0) &&
21176 "Vector type should have an even number of elements in each lane");
21177 unsigned HalfLaneElts = NumLaneElts/2;
21179 // View LHS in the form
21180 // LHS = VECTOR_SHUFFLE A, B, LMask
21181 // If LHS is not a shuffle then pretend it is the shuffle
21182 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
21183 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
21186 SmallVector<int, 16> LMask(NumElts);
21187 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
21188 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
21189 A = LHS.getOperand(0);
21190 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
21191 B = LHS.getOperand(1);
21192 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
21193 std::copy(Mask.begin(), Mask.end(), LMask.begin());
21195 if (LHS.getOpcode() != ISD::UNDEF)
21197 for (unsigned i = 0; i != NumElts; ++i)
21201 // Likewise, view RHS in the form
21202 // RHS = VECTOR_SHUFFLE C, D, RMask
21204 SmallVector<int, 16> RMask(NumElts);
21205 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
21206 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
21207 C = RHS.getOperand(0);
21208 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
21209 D = RHS.getOperand(1);
21210 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
21211 std::copy(Mask.begin(), Mask.end(), RMask.begin());
21213 if (RHS.getOpcode() != ISD::UNDEF)
21215 for (unsigned i = 0; i != NumElts; ++i)
21219 // Check that the shuffles are both shuffling the same vectors.
21220 if (!(A == C && B == D) && !(A == D && B == C))
21223 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
21224 if (!A.getNode() && !B.getNode())
21227 // If A and B occur in reverse order in RHS, then "swap" them (which means
21228 // rewriting the mask).
21230 CommuteVectorShuffleMask(RMask, NumElts);
21232 // At this point LHS and RHS are equivalent to
21233 // LHS = VECTOR_SHUFFLE A, B, LMask
21234 // RHS = VECTOR_SHUFFLE A, B, RMask
21235 // Check that the masks correspond to performing a horizontal operation.
21236 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
21237 for (unsigned i = 0; i != NumLaneElts; ++i) {
21238 int LIdx = LMask[i+l], RIdx = RMask[i+l];
21240 // Ignore any UNDEF components.
21241 if (LIdx < 0 || RIdx < 0 ||
21242 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
21243 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
21246 // Check that successive elements are being operated on. If not, this is
21247 // not a horizontal operation.
21248 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
21249 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
21250 if (!(LIdx == Index && RIdx == Index + 1) &&
21251 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
21256 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
21257 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
21261 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
21262 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
21263 const X86Subtarget *Subtarget) {
21264 EVT VT = N->getValueType(0);
21265 SDValue LHS = N->getOperand(0);
21266 SDValue RHS = N->getOperand(1);
21268 // Try to synthesize horizontal adds from adds of shuffles.
21269 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
21270 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
21271 isHorizontalBinOp(LHS, RHS, true))
21272 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
21276 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
21277 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
21278 const X86Subtarget *Subtarget) {
21279 EVT VT = N->getValueType(0);
21280 SDValue LHS = N->getOperand(0);
21281 SDValue RHS = N->getOperand(1);
21283 // Try to synthesize horizontal subs from subs of shuffles.
21284 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
21285 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
21286 isHorizontalBinOp(LHS, RHS, false))
21287 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
21291 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
21292 /// X86ISD::FXOR nodes.
21293 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
21294 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
21295 // F[X]OR(0.0, x) -> x
21296 // F[X]OR(x, 0.0) -> x
21297 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
21298 if (C->getValueAPF().isPosZero())
21299 return N->getOperand(1);
21300 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
21301 if (C->getValueAPF().isPosZero())
21302 return N->getOperand(0);
21306 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
21307 /// X86ISD::FMAX nodes.
21308 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
21309 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
21311 // Only perform optimizations if UnsafeMath is used.
21312 if (!DAG.getTarget().Options.UnsafeFPMath)
21315 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
21316 // into FMINC and FMAXC, which are Commutative operations.
21317 unsigned NewOp = 0;
21318 switch (N->getOpcode()) {
21319 default: llvm_unreachable("unknown opcode");
21320 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
21321 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
21324 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
21325 N->getOperand(0), N->getOperand(1));
21328 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
21329 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
21330 // FAND(0.0, x) -> 0.0
21331 // FAND(x, 0.0) -> 0.0
21332 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
21333 if (C->getValueAPF().isPosZero())
21334 return N->getOperand(0);
21335 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
21336 if (C->getValueAPF().isPosZero())
21337 return N->getOperand(1);
21341 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
21342 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
21343 // FANDN(x, 0.0) -> 0.0
21344 // FANDN(0.0, x) -> x
21345 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
21346 if (C->getValueAPF().isPosZero())
21347 return N->getOperand(1);
21348 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
21349 if (C->getValueAPF().isPosZero())
21350 return N->getOperand(1);
21354 static SDValue PerformBTCombine(SDNode *N,
21356 TargetLowering::DAGCombinerInfo &DCI) {
21357 // BT ignores high bits in the bit index operand.
21358 SDValue Op1 = N->getOperand(1);
21359 if (Op1.hasOneUse()) {
21360 unsigned BitWidth = Op1.getValueSizeInBits();
21361 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
21362 APInt KnownZero, KnownOne;
21363 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
21364 !DCI.isBeforeLegalizeOps());
21365 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21366 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
21367 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
21368 DCI.CommitTargetLoweringOpt(TLO);
21373 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
21374 SDValue Op = N->getOperand(0);
21375 if (Op.getOpcode() == ISD::BITCAST)
21376 Op = Op.getOperand(0);
21377 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
21378 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
21379 VT.getVectorElementType().getSizeInBits() ==
21380 OpVT.getVectorElementType().getSizeInBits()) {
21381 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
21386 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
21387 const X86Subtarget *Subtarget) {
21388 EVT VT = N->getValueType(0);
21389 if (!VT.isVector())
21392 SDValue N0 = N->getOperand(0);
21393 SDValue N1 = N->getOperand(1);
21394 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
21397 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
21398 // both SSE and AVX2 since there is no sign-extended shift right
21399 // operation on a vector with 64-bit elements.
21400 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
21401 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
21402 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
21403 N0.getOpcode() == ISD::SIGN_EXTEND)) {
21404 SDValue N00 = N0.getOperand(0);
21406 // EXTLOAD has a better solution on AVX2,
21407 // it may be replaced with X86ISD::VSEXT node.
21408 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
21409 if (!ISD::isNormalLoad(N00.getNode()))
21412 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
21413 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
21415 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
21421 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
21422 TargetLowering::DAGCombinerInfo &DCI,
21423 const X86Subtarget *Subtarget) {
21424 if (!DCI.isBeforeLegalizeOps())
21427 if (!Subtarget->hasFp256())
21430 EVT VT = N->getValueType(0);
21431 if (VT.isVector() && VT.getSizeInBits() == 256) {
21432 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
21440 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
21441 const X86Subtarget* Subtarget) {
21443 EVT VT = N->getValueType(0);
21445 // Let legalize expand this if it isn't a legal type yet.
21446 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
21449 EVT ScalarVT = VT.getScalarType();
21450 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
21451 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
21454 SDValue A = N->getOperand(0);
21455 SDValue B = N->getOperand(1);
21456 SDValue C = N->getOperand(2);
21458 bool NegA = (A.getOpcode() == ISD::FNEG);
21459 bool NegB = (B.getOpcode() == ISD::FNEG);
21460 bool NegC = (C.getOpcode() == ISD::FNEG);
21462 // Negative multiplication when NegA xor NegB
21463 bool NegMul = (NegA != NegB);
21465 A = A.getOperand(0);
21467 B = B.getOperand(0);
21469 C = C.getOperand(0);
21473 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
21475 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
21477 return DAG.getNode(Opcode, dl, VT, A, B, C);
21480 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
21481 TargetLowering::DAGCombinerInfo &DCI,
21482 const X86Subtarget *Subtarget) {
21483 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
21484 // (and (i32 x86isd::setcc_carry), 1)
21485 // This eliminates the zext. This transformation is necessary because
21486 // ISD::SETCC is always legalized to i8.
21488 SDValue N0 = N->getOperand(0);
21489 EVT VT = N->getValueType(0);
21491 if (N0.getOpcode() == ISD::AND &&
21493 N0.getOperand(0).hasOneUse()) {
21494 SDValue N00 = N0.getOperand(0);
21495 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
21496 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
21497 if (!C || C->getZExtValue() != 1)
21499 return DAG.getNode(ISD::AND, dl, VT,
21500 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
21501 N00.getOperand(0), N00.getOperand(1)),
21502 DAG.getConstant(1, VT));
21506 if (N0.getOpcode() == ISD::TRUNCATE &&
21508 N0.getOperand(0).hasOneUse()) {
21509 SDValue N00 = N0.getOperand(0);
21510 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
21511 return DAG.getNode(ISD::AND, dl, VT,
21512 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
21513 N00.getOperand(0), N00.getOperand(1)),
21514 DAG.getConstant(1, VT));
21517 if (VT.is256BitVector()) {
21518 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
21526 // Optimize x == -y --> x+y == 0
21527 // x != -y --> x+y != 0
21528 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
21529 const X86Subtarget* Subtarget) {
21530 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
21531 SDValue LHS = N->getOperand(0);
21532 SDValue RHS = N->getOperand(1);
21533 EVT VT = N->getValueType(0);
21536 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
21537 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
21538 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
21539 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
21540 LHS.getValueType(), RHS, LHS.getOperand(1));
21541 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
21542 addV, DAG.getConstant(0, addV.getValueType()), CC);
21544 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
21545 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
21546 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
21547 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
21548 RHS.getValueType(), LHS, RHS.getOperand(1));
21549 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
21550 addV, DAG.getConstant(0, addV.getValueType()), CC);
21553 if (VT.getScalarType() == MVT::i1) {
21554 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
21555 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
21556 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
21557 if (!IsSEXT0 && !IsVZero0)
21559 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
21560 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
21561 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
21563 if (!IsSEXT1 && !IsVZero1)
21566 if (IsSEXT0 && IsVZero1) {
21567 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
21568 if (CC == ISD::SETEQ)
21569 return DAG.getNOT(DL, LHS.getOperand(0), VT);
21570 return LHS.getOperand(0);
21572 if (IsSEXT1 && IsVZero0) {
21573 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
21574 if (CC == ISD::SETEQ)
21575 return DAG.getNOT(DL, RHS.getOperand(0), VT);
21576 return RHS.getOperand(0);
21583 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
21584 const X86Subtarget *Subtarget) {
21586 MVT VT = N->getOperand(1)->getSimpleValueType(0);
21587 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
21588 "X86insertps is only defined for v4x32");
21590 SDValue Ld = N->getOperand(1);
21591 if (MayFoldLoad(Ld)) {
21592 // Extract the countS bits from the immediate so we can get the proper
21593 // address when narrowing the vector load to a specific element.
21594 // When the second source op is a memory address, interps doesn't use
21595 // countS and just gets an f32 from that address.
21596 unsigned DestIndex =
21597 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
21598 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
21602 // Create this as a scalar to vector to match the instruction pattern.
21603 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
21604 // countS bits are ignored when loading from memory on insertps, which
21605 // means we don't need to explicitly set them to 0.
21606 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
21607 LoadScalarToVector, N->getOperand(2));
21610 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
21611 // as "sbb reg,reg", since it can be extended without zext and produces
21612 // an all-ones bit which is more useful than 0/1 in some cases.
21613 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
21616 return DAG.getNode(ISD::AND, DL, VT,
21617 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
21618 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
21619 DAG.getConstant(1, VT));
21620 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
21621 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
21622 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
21623 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
21626 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
21627 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
21628 TargetLowering::DAGCombinerInfo &DCI,
21629 const X86Subtarget *Subtarget) {
21631 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
21632 SDValue EFLAGS = N->getOperand(1);
21634 if (CC == X86::COND_A) {
21635 // Try to convert COND_A into COND_B in an attempt to facilitate
21636 // materializing "setb reg".
21638 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
21639 // cannot take an immediate as its first operand.
21641 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
21642 EFLAGS.getValueType().isInteger() &&
21643 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
21644 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
21645 EFLAGS.getNode()->getVTList(),
21646 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
21647 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
21648 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
21652 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
21653 // a zext and produces an all-ones bit which is more useful than 0/1 in some
21655 if (CC == X86::COND_B)
21656 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
21660 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
21661 if (Flags.getNode()) {
21662 SDValue Cond = DAG.getConstant(CC, MVT::i8);
21663 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
21669 // Optimize branch condition evaluation.
21671 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
21672 TargetLowering::DAGCombinerInfo &DCI,
21673 const X86Subtarget *Subtarget) {
21675 SDValue Chain = N->getOperand(0);
21676 SDValue Dest = N->getOperand(1);
21677 SDValue EFLAGS = N->getOperand(3);
21678 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
21682 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
21683 if (Flags.getNode()) {
21684 SDValue Cond = DAG.getConstant(CC, MVT::i8);
21685 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
21692 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
21693 const X86TargetLowering *XTLI) {
21694 SDValue Op0 = N->getOperand(0);
21695 EVT InVT = Op0->getValueType(0);
21697 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
21698 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
21700 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
21701 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
21702 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
21705 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
21706 // a 32-bit target where SSE doesn't support i64->FP operations.
21707 if (Op0.getOpcode() == ISD::LOAD) {
21708 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
21709 EVT VT = Ld->getValueType(0);
21710 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
21711 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
21712 !XTLI->getSubtarget()->is64Bit() &&
21714 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
21715 Ld->getChain(), Op0, DAG);
21716 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
21723 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
21724 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
21725 X86TargetLowering::DAGCombinerInfo &DCI) {
21726 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
21727 // the result is either zero or one (depending on the input carry bit).
21728 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
21729 if (X86::isZeroNode(N->getOperand(0)) &&
21730 X86::isZeroNode(N->getOperand(1)) &&
21731 // We don't have a good way to replace an EFLAGS use, so only do this when
21733 SDValue(N, 1).use_empty()) {
21735 EVT VT = N->getValueType(0);
21736 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
21737 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
21738 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
21739 DAG.getConstant(X86::COND_B,MVT::i8),
21741 DAG.getConstant(1, VT));
21742 return DCI.CombineTo(N, Res1, CarryOut);
21748 // fold (add Y, (sete X, 0)) -> adc 0, Y
21749 // (add Y, (setne X, 0)) -> sbb -1, Y
21750 // (sub (sete X, 0), Y) -> sbb 0, Y
21751 // (sub (setne X, 0), Y) -> adc -1, Y
21752 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
21755 // Look through ZExts.
21756 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
21757 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
21760 SDValue SetCC = Ext.getOperand(0);
21761 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
21764 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
21765 if (CC != X86::COND_E && CC != X86::COND_NE)
21768 SDValue Cmp = SetCC.getOperand(1);
21769 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
21770 !X86::isZeroNode(Cmp.getOperand(1)) ||
21771 !Cmp.getOperand(0).getValueType().isInteger())
21774 SDValue CmpOp0 = Cmp.getOperand(0);
21775 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
21776 DAG.getConstant(1, CmpOp0.getValueType()));
21778 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
21779 if (CC == X86::COND_NE)
21780 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
21781 DL, OtherVal.getValueType(), OtherVal,
21782 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
21783 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
21784 DL, OtherVal.getValueType(), OtherVal,
21785 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
21788 /// PerformADDCombine - Do target-specific dag combines on integer adds.
21789 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
21790 const X86Subtarget *Subtarget) {
21791 EVT VT = N->getValueType(0);
21792 SDValue Op0 = N->getOperand(0);
21793 SDValue Op1 = N->getOperand(1);
21795 // Try to synthesize horizontal adds from adds of shuffles.
21796 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
21797 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
21798 isHorizontalBinOp(Op0, Op1, true))
21799 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
21801 return OptimizeConditionalInDecrement(N, DAG);
21804 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
21805 const X86Subtarget *Subtarget) {
21806 SDValue Op0 = N->getOperand(0);
21807 SDValue Op1 = N->getOperand(1);
21809 // X86 can't encode an immediate LHS of a sub. See if we can push the
21810 // negation into a preceding instruction.
21811 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
21812 // If the RHS of the sub is a XOR with one use and a constant, invert the
21813 // immediate. Then add one to the LHS of the sub so we can turn
21814 // X-Y -> X+~Y+1, saving one register.
21815 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
21816 isa<ConstantSDNode>(Op1.getOperand(1))) {
21817 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
21818 EVT VT = Op0.getValueType();
21819 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
21821 DAG.getConstant(~XorC, VT));
21822 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
21823 DAG.getConstant(C->getAPIntValue()+1, VT));
21827 // Try to synthesize horizontal adds from adds of shuffles.
21828 EVT VT = N->getValueType(0);
21829 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
21830 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
21831 isHorizontalBinOp(Op0, Op1, true))
21832 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
21834 return OptimizeConditionalInDecrement(N, DAG);
21837 /// performVZEXTCombine - Performs build vector combines
21838 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
21839 TargetLowering::DAGCombinerInfo &DCI,
21840 const X86Subtarget *Subtarget) {
21841 // (vzext (bitcast (vzext (x)) -> (vzext x)
21842 SDValue In = N->getOperand(0);
21843 while (In.getOpcode() == ISD::BITCAST)
21844 In = In.getOperand(0);
21846 if (In.getOpcode() != X86ISD::VZEXT)
21849 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
21853 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
21854 DAGCombinerInfo &DCI) const {
21855 SelectionDAG &DAG = DCI.DAG;
21856 switch (N->getOpcode()) {
21858 case ISD::EXTRACT_VECTOR_ELT:
21859 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
21861 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
21862 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
21863 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
21864 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
21865 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
21866 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
21869 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
21870 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
21871 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
21872 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
21873 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
21874 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
21875 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
21876 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
21877 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
21879 case X86ISD::FOR: return PerformFORCombine(N, DAG);
21881 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
21882 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
21883 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
21884 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
21885 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
21886 case ISD::ANY_EXTEND:
21887 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
21888 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
21889 case ISD::SIGN_EXTEND_INREG:
21890 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
21891 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
21892 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
21893 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
21894 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
21895 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
21896 case X86ISD::SHUFP: // Handle all target specific shuffles
21897 case X86ISD::PALIGNR:
21898 case X86ISD::UNPCKH:
21899 case X86ISD::UNPCKL:
21900 case X86ISD::MOVHLPS:
21901 case X86ISD::MOVLHPS:
21902 case X86ISD::PSHUFD:
21903 case X86ISD::PSHUFHW:
21904 case X86ISD::PSHUFLW:
21905 case X86ISD::MOVSS:
21906 case X86ISD::MOVSD:
21907 case X86ISD::VPERMILP:
21908 case X86ISD::VPERM2X128:
21909 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
21910 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
21911 case ISD::INTRINSIC_WO_CHAIN:
21912 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
21913 case X86ISD::INSERTPS:
21914 return PerformINSERTPSCombine(N, DAG, Subtarget);
21915 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
21921 /// isTypeDesirableForOp - Return true if the target has native support for
21922 /// the specified value type and it is 'desirable' to use the type for the
21923 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
21924 /// instruction encodings are longer and some i16 instructions are slow.
21925 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
21926 if (!isTypeLegal(VT))
21928 if (VT != MVT::i16)
21935 case ISD::SIGN_EXTEND:
21936 case ISD::ZERO_EXTEND:
21937 case ISD::ANY_EXTEND:
21950 /// IsDesirableToPromoteOp - This method query the target whether it is
21951 /// beneficial for dag combiner to promote the specified node. If true, it
21952 /// should return the desired promotion type by reference.
21953 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
21954 EVT VT = Op.getValueType();
21955 if (VT != MVT::i16)
21958 bool Promote = false;
21959 bool Commute = false;
21960 switch (Op.getOpcode()) {
21963 LoadSDNode *LD = cast<LoadSDNode>(Op);
21964 // If the non-extending load has a single use and it's not live out, then it
21965 // might be folded.
21966 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
21967 Op.hasOneUse()*/) {
21968 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
21969 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
21970 // The only case where we'd want to promote LOAD (rather then it being
21971 // promoted as an operand is when it's only use is liveout.
21972 if (UI->getOpcode() != ISD::CopyToReg)
21979 case ISD::SIGN_EXTEND:
21980 case ISD::ZERO_EXTEND:
21981 case ISD::ANY_EXTEND:
21986 SDValue N0 = Op.getOperand(0);
21987 // Look out for (store (shl (load), x)).
21988 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
22001 SDValue N0 = Op.getOperand(0);
22002 SDValue N1 = Op.getOperand(1);
22003 if (!Commute && MayFoldLoad(N1))
22005 // Avoid disabling potential load folding opportunities.
22006 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
22008 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
22018 //===----------------------------------------------------------------------===//
22019 // X86 Inline Assembly Support
22020 //===----------------------------------------------------------------------===//
22023 // Helper to match a string separated by whitespace.
22024 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
22025 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
22027 for (unsigned i = 0, e = args.size(); i != e; ++i) {
22028 StringRef piece(*args[i]);
22029 if (!s.startswith(piece)) // Check if the piece matches.
22032 s = s.substr(piece.size());
22033 StringRef::size_type pos = s.find_first_not_of(" \t");
22034 if (pos == 0) // We matched a prefix.
22042 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
22045 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
22047 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
22048 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
22049 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
22050 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
22052 if (AsmPieces.size() == 3)
22054 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
22061 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
22062 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
22064 std::string AsmStr = IA->getAsmString();
22066 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
22067 if (!Ty || Ty->getBitWidth() % 16 != 0)
22070 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
22071 SmallVector<StringRef, 4> AsmPieces;
22072 SplitString(AsmStr, AsmPieces, ";\n");
22074 switch (AsmPieces.size()) {
22075 default: return false;
22077 // FIXME: this should verify that we are targeting a 486 or better. If not,
22078 // we will turn this bswap into something that will be lowered to logical
22079 // ops instead of emitting the bswap asm. For now, we don't support 486 or
22080 // lower so don't worry about this.
22082 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
22083 matchAsm(AsmPieces[0], "bswapl", "$0") ||
22084 matchAsm(AsmPieces[0], "bswapq", "$0") ||
22085 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
22086 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
22087 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
22088 // No need to check constraints, nothing other than the equivalent of
22089 // "=r,0" would be valid here.
22090 return IntrinsicLowering::LowerToByteSwap(CI);
22093 // rorw $$8, ${0:w} --> llvm.bswap.i16
22094 if (CI->getType()->isIntegerTy(16) &&
22095 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
22096 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
22097 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
22099 const std::string &ConstraintsStr = IA->getConstraintString();
22100 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
22101 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
22102 if (clobbersFlagRegisters(AsmPieces))
22103 return IntrinsicLowering::LowerToByteSwap(CI);
22107 if (CI->getType()->isIntegerTy(32) &&
22108 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
22109 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
22110 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
22111 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
22113 const std::string &ConstraintsStr = IA->getConstraintString();
22114 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
22115 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
22116 if (clobbersFlagRegisters(AsmPieces))
22117 return IntrinsicLowering::LowerToByteSwap(CI);
22120 if (CI->getType()->isIntegerTy(64)) {
22121 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
22122 if (Constraints.size() >= 2 &&
22123 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
22124 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
22125 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
22126 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
22127 matchAsm(AsmPieces[1], "bswap", "%edx") &&
22128 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
22129 return IntrinsicLowering::LowerToByteSwap(CI);
22137 /// getConstraintType - Given a constraint letter, return the type of
22138 /// constraint it is for this target.
22139 X86TargetLowering::ConstraintType
22140 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
22141 if (Constraint.size() == 1) {
22142 switch (Constraint[0]) {
22153 return C_RegisterClass;
22177 return TargetLowering::getConstraintType(Constraint);
22180 /// Examine constraint type and operand type and determine a weight value.
22181 /// This object must already have been set up with the operand type
22182 /// and the current alternative constraint selected.
22183 TargetLowering::ConstraintWeight
22184 X86TargetLowering::getSingleConstraintMatchWeight(
22185 AsmOperandInfo &info, const char *constraint) const {
22186 ConstraintWeight weight = CW_Invalid;
22187 Value *CallOperandVal = info.CallOperandVal;
22188 // If we don't have a value, we can't do a match,
22189 // but allow it at the lowest weight.
22190 if (!CallOperandVal)
22192 Type *type = CallOperandVal->getType();
22193 // Look at the constraint type.
22194 switch (*constraint) {
22196 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
22207 if (CallOperandVal->getType()->isIntegerTy())
22208 weight = CW_SpecificReg;
22213 if (type->isFloatingPointTy())
22214 weight = CW_SpecificReg;
22217 if (type->isX86_MMXTy() && Subtarget->hasMMX())
22218 weight = CW_SpecificReg;
22222 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
22223 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
22224 weight = CW_Register;
22227 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
22228 if (C->getZExtValue() <= 31)
22229 weight = CW_Constant;
22233 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22234 if (C->getZExtValue() <= 63)
22235 weight = CW_Constant;
22239 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22240 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
22241 weight = CW_Constant;
22245 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22246 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
22247 weight = CW_Constant;
22251 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22252 if (C->getZExtValue() <= 3)
22253 weight = CW_Constant;
22257 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22258 if (C->getZExtValue() <= 0xff)
22259 weight = CW_Constant;
22264 if (dyn_cast<ConstantFP>(CallOperandVal)) {
22265 weight = CW_Constant;
22269 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22270 if ((C->getSExtValue() >= -0x80000000LL) &&
22271 (C->getSExtValue() <= 0x7fffffffLL))
22272 weight = CW_Constant;
22276 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
22277 if (C->getZExtValue() <= 0xffffffff)
22278 weight = CW_Constant;
22285 /// LowerXConstraint - try to replace an X constraint, which matches anything,
22286 /// with another that has more specific requirements based on the type of the
22287 /// corresponding operand.
22288 const char *X86TargetLowering::
22289 LowerXConstraint(EVT ConstraintVT) const {
22290 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
22291 // 'f' like normal targets.
22292 if (ConstraintVT.isFloatingPoint()) {
22293 if (Subtarget->hasSSE2())
22295 if (Subtarget->hasSSE1())
22299 return TargetLowering::LowerXConstraint(ConstraintVT);
22302 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
22303 /// vector. If it is invalid, don't add anything to Ops.
22304 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
22305 std::string &Constraint,
22306 std::vector<SDValue>&Ops,
22307 SelectionDAG &DAG) const {
22310 // Only support length 1 constraints for now.
22311 if (Constraint.length() > 1) return;
22313 char ConstraintLetter = Constraint[0];
22314 switch (ConstraintLetter) {
22317 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
22318 if (C->getZExtValue() <= 31) {
22319 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
22325 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
22326 if (C->getZExtValue() <= 63) {
22327 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
22333 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
22334 if (isInt<8>(C->getSExtValue())) {
22335 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
22341 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
22342 if (C->getZExtValue() <= 255) {
22343 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
22349 // 32-bit signed value
22350 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
22351 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
22352 C->getSExtValue())) {
22353 // Widen to 64 bits here to get it sign extended.
22354 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
22357 // FIXME gcc accepts some relocatable values here too, but only in certain
22358 // memory models; it's complicated.
22363 // 32-bit unsigned value
22364 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
22365 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
22366 C->getZExtValue())) {
22367 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
22371 // FIXME gcc accepts some relocatable values here too, but only in certain
22372 // memory models; it's complicated.
22376 // Literal immediates are always ok.
22377 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
22378 // Widen to 64 bits here to get it sign extended.
22379 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
22383 // In any sort of PIC mode addresses need to be computed at runtime by
22384 // adding in a register or some sort of table lookup. These can't
22385 // be used as immediates.
22386 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
22389 // If we are in non-pic codegen mode, we allow the address of a global (with
22390 // an optional displacement) to be used with 'i'.
22391 GlobalAddressSDNode *GA = nullptr;
22392 int64_t Offset = 0;
22394 // Match either (GA), (GA+C), (GA+C1+C2), etc.
22396 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
22397 Offset += GA->getOffset();
22399 } else if (Op.getOpcode() == ISD::ADD) {
22400 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
22401 Offset += C->getZExtValue();
22402 Op = Op.getOperand(0);
22405 } else if (Op.getOpcode() == ISD::SUB) {
22406 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
22407 Offset += -C->getZExtValue();
22408 Op = Op.getOperand(0);
22413 // Otherwise, this isn't something we can handle, reject it.
22417 const GlobalValue *GV = GA->getGlobal();
22418 // If we require an extra load to get this address, as in PIC mode, we
22419 // can't accept it.
22420 if (isGlobalStubReference(
22421 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
22424 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
22425 GA->getValueType(0), Offset);
22430 if (Result.getNode()) {
22431 Ops.push_back(Result);
22434 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
22437 std::pair<unsigned, const TargetRegisterClass*>
22438 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
22440 // First, see if this is a constraint that directly corresponds to an LLVM
22442 if (Constraint.size() == 1) {
22443 // GCC Constraint Letters
22444 switch (Constraint[0]) {
22446 // TODO: Slight differences here in allocation order and leaving
22447 // RIP in the class. Do they matter any more here than they do
22448 // in the normal allocation?
22449 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
22450 if (Subtarget->is64Bit()) {
22451 if (VT == MVT::i32 || VT == MVT::f32)
22452 return std::make_pair(0U, &X86::GR32RegClass);
22453 if (VT == MVT::i16)
22454 return std::make_pair(0U, &X86::GR16RegClass);
22455 if (VT == MVT::i8 || VT == MVT::i1)
22456 return std::make_pair(0U, &X86::GR8RegClass);
22457 if (VT == MVT::i64 || VT == MVT::f64)
22458 return std::make_pair(0U, &X86::GR64RegClass);
22461 // 32-bit fallthrough
22462 case 'Q': // Q_REGS
22463 if (VT == MVT::i32 || VT == MVT::f32)
22464 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
22465 if (VT == MVT::i16)
22466 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
22467 if (VT == MVT::i8 || VT == MVT::i1)
22468 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
22469 if (VT == MVT::i64)
22470 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
22472 case 'r': // GENERAL_REGS
22473 case 'l': // INDEX_REGS
22474 if (VT == MVT::i8 || VT == MVT::i1)
22475 return std::make_pair(0U, &X86::GR8RegClass);
22476 if (VT == MVT::i16)
22477 return std::make_pair(0U, &X86::GR16RegClass);
22478 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
22479 return std::make_pair(0U, &X86::GR32RegClass);
22480 return std::make_pair(0U, &X86::GR64RegClass);
22481 case 'R': // LEGACY_REGS
22482 if (VT == MVT::i8 || VT == MVT::i1)
22483 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
22484 if (VT == MVT::i16)
22485 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
22486 if (VT == MVT::i32 || !Subtarget->is64Bit())
22487 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
22488 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
22489 case 'f': // FP Stack registers.
22490 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
22491 // value to the correct fpstack register class.
22492 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
22493 return std::make_pair(0U, &X86::RFP32RegClass);
22494 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
22495 return std::make_pair(0U, &X86::RFP64RegClass);
22496 return std::make_pair(0U, &X86::RFP80RegClass);
22497 case 'y': // MMX_REGS if MMX allowed.
22498 if (!Subtarget->hasMMX()) break;
22499 return std::make_pair(0U, &X86::VR64RegClass);
22500 case 'Y': // SSE_REGS if SSE2 allowed
22501 if (!Subtarget->hasSSE2()) break;
22503 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
22504 if (!Subtarget->hasSSE1()) break;
22506 switch (VT.SimpleTy) {
22508 // Scalar SSE types.
22511 return std::make_pair(0U, &X86::FR32RegClass);
22514 return std::make_pair(0U, &X86::FR64RegClass);
22522 return std::make_pair(0U, &X86::VR128RegClass);
22530 return std::make_pair(0U, &X86::VR256RegClass);
22535 return std::make_pair(0U, &X86::VR512RegClass);
22541 // Use the default implementation in TargetLowering to convert the register
22542 // constraint into a member of a register class.
22543 std::pair<unsigned, const TargetRegisterClass*> Res;
22544 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
22546 // Not found as a standard register?
22548 // Map st(0) -> st(7) -> ST0
22549 if (Constraint.size() == 7 && Constraint[0] == '{' &&
22550 tolower(Constraint[1]) == 's' &&
22551 tolower(Constraint[2]) == 't' &&
22552 Constraint[3] == '(' &&
22553 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
22554 Constraint[5] == ')' &&
22555 Constraint[6] == '}') {
22557 Res.first = X86::ST0+Constraint[4]-'0';
22558 Res.second = &X86::RFP80RegClass;
22562 // GCC allows "st(0)" to be called just plain "st".
22563 if (StringRef("{st}").equals_lower(Constraint)) {
22564 Res.first = X86::ST0;
22565 Res.second = &X86::RFP80RegClass;
22570 if (StringRef("{flags}").equals_lower(Constraint)) {
22571 Res.first = X86::EFLAGS;
22572 Res.second = &X86::CCRRegClass;
22576 // 'A' means EAX + EDX.
22577 if (Constraint == "A") {
22578 Res.first = X86::EAX;
22579 Res.second = &X86::GR32_ADRegClass;
22585 // Otherwise, check to see if this is a register class of the wrong value
22586 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
22587 // turn into {ax},{dx}.
22588 if (Res.second->hasType(VT))
22589 return Res; // Correct type already, nothing to do.
22591 // All of the single-register GCC register classes map their values onto
22592 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
22593 // really want an 8-bit or 32-bit register, map to the appropriate register
22594 // class and return the appropriate register.
22595 if (Res.second == &X86::GR16RegClass) {
22596 if (VT == MVT::i8 || VT == MVT::i1) {
22597 unsigned DestReg = 0;
22598 switch (Res.first) {
22600 case X86::AX: DestReg = X86::AL; break;
22601 case X86::DX: DestReg = X86::DL; break;
22602 case X86::CX: DestReg = X86::CL; break;
22603 case X86::BX: DestReg = X86::BL; break;
22606 Res.first = DestReg;
22607 Res.second = &X86::GR8RegClass;
22609 } else if (VT == MVT::i32 || VT == MVT::f32) {
22610 unsigned DestReg = 0;
22611 switch (Res.first) {
22613 case X86::AX: DestReg = X86::EAX; break;
22614 case X86::DX: DestReg = X86::EDX; break;
22615 case X86::CX: DestReg = X86::ECX; break;
22616 case X86::BX: DestReg = X86::EBX; break;
22617 case X86::SI: DestReg = X86::ESI; break;
22618 case X86::DI: DestReg = X86::EDI; break;
22619 case X86::BP: DestReg = X86::EBP; break;
22620 case X86::SP: DestReg = X86::ESP; break;
22623 Res.first = DestReg;
22624 Res.second = &X86::GR32RegClass;
22626 } else if (VT == MVT::i64 || VT == MVT::f64) {
22627 unsigned DestReg = 0;
22628 switch (Res.first) {
22630 case X86::AX: DestReg = X86::RAX; break;
22631 case X86::DX: DestReg = X86::RDX; break;
22632 case X86::CX: DestReg = X86::RCX; break;
22633 case X86::BX: DestReg = X86::RBX; break;
22634 case X86::SI: DestReg = X86::RSI; break;
22635 case X86::DI: DestReg = X86::RDI; break;
22636 case X86::BP: DestReg = X86::RBP; break;
22637 case X86::SP: DestReg = X86::RSP; break;
22640 Res.first = DestReg;
22641 Res.second = &X86::GR64RegClass;
22644 } else if (Res.second == &X86::FR32RegClass ||
22645 Res.second == &X86::FR64RegClass ||
22646 Res.second == &X86::VR128RegClass ||
22647 Res.second == &X86::VR256RegClass ||
22648 Res.second == &X86::FR32XRegClass ||
22649 Res.second == &X86::FR64XRegClass ||
22650 Res.second == &X86::VR128XRegClass ||
22651 Res.second == &X86::VR256XRegClass ||
22652 Res.second == &X86::VR512RegClass) {
22653 // Handle references to XMM physical registers that got mapped into the
22654 // wrong class. This can happen with constraints like {xmm0} where the
22655 // target independent register mapper will just pick the first match it can
22656 // find, ignoring the required type.
22658 if (VT == MVT::f32 || VT == MVT::i32)
22659 Res.second = &X86::FR32RegClass;
22660 else if (VT == MVT::f64 || VT == MVT::i64)
22661 Res.second = &X86::FR64RegClass;
22662 else if (X86::VR128RegClass.hasType(VT))
22663 Res.second = &X86::VR128RegClass;
22664 else if (X86::VR256RegClass.hasType(VT))
22665 Res.second = &X86::VR256RegClass;
22666 else if (X86::VR512RegClass.hasType(VT))
22667 Res.second = &X86::VR512RegClass;
22673 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
22675 // Scaling factors are not free at all.
22676 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
22677 // will take 2 allocations in the out of order engine instead of 1
22678 // for plain addressing mode, i.e. inst (reg1).
22680 // vaddps (%rsi,%drx), %ymm0, %ymm1
22681 // Requires two allocations (one for the load, one for the computation)
22683 // vaddps (%rsi), %ymm0, %ymm1
22684 // Requires just 1 allocation, i.e., freeing allocations for other operations
22685 // and having less micro operations to execute.
22687 // For some X86 architectures, this is even worse because for instance for
22688 // stores, the complex addressing mode forces the instruction to use the
22689 // "load" ports instead of the dedicated "store" port.
22690 // E.g., on Haswell:
22691 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
22692 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
22693 if (isLegalAddressingMode(AM, Ty))
22694 // Scale represents reg2 * scale, thus account for 1
22695 // as soon as we use a second register.
22696 return AM.Scale != 0;
22700 bool X86TargetLowering::isTargetFTOL() const {
22701 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();