1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/MC/MCAsmInfo.h"
40 #include "llvm/MC/MCContext.h"
41 #include "llvm/MC/MCExpr.h"
42 #include "llvm/MC/MCSymbol.h"
43 #include "llvm/ADT/BitVector.h"
44 #include "llvm/ADT/SmallSet.h"
45 #include "llvm/ADT/Statistic.h"
46 #include "llvm/ADT/StringExtras.h"
47 #include "llvm/ADT/VectorExtras.h"
48 #include "llvm/Support/CallSite.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/Dwarf.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
55 using namespace dwarf;
57 STATISTIC(NumTailCalls, "Number of tail calls");
59 // Forward declarations.
60 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
63 static SDValue Insert128BitVector(SDValue Result,
69 static SDValue Extract128BitVector(SDValue Vec,
74 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
75 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
76 /// simple subregister reference. Idx is an index in the 128 bits we
77 /// want. It need not be aligned to a 128-bit bounday. That makes
78 /// lowering EXTRACT_VECTOR_ELT operations easier.
79 static SDValue Extract128BitVector(SDValue Vec,
83 EVT VT = Vec.getValueType();
84 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
85 EVT ElVT = VT.getVectorElementType();
86 int Factor = VT.getSizeInBits()/128;
87 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
88 VT.getVectorNumElements()/Factor);
90 // Extract from UNDEF is UNDEF.
91 if (Vec.getOpcode() == ISD::UNDEF)
92 return DAG.getNode(ISD::UNDEF, dl, ResultVT);
94 if (isa<ConstantSDNode>(Idx)) {
95 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
97 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
98 // we can match to VEXTRACTF128.
99 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
101 // This is the index of the first element of the 128-bit chunk
103 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
106 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
107 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
116 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
117 /// sets things up to match to an AVX VINSERTF128 instruction or a
118 /// simple superregister reference. Idx is an index in the 128 bits
119 /// we want. It need not be aligned to a 128-bit bounday. That makes
120 /// lowering INSERT_VECTOR_ELT operations easier.
121 static SDValue Insert128BitVector(SDValue Result,
126 if (isa<ConstantSDNode>(Idx)) {
127 EVT VT = Vec.getValueType();
128 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
130 EVT ElVT = VT.getVectorElementType();
131 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
132 EVT ResultVT = Result.getValueType();
134 // Insert the relevant 128 bits.
135 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
137 // This is the index of the first element of the 128-bit chunk
139 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
142 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
143 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
151 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
152 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
153 bool is64Bit = Subtarget->is64Bit();
155 if (Subtarget->isTargetEnvMacho()) {
157 return new X8664_MachoTargetObjectFile();
158 return new TargetLoweringObjectFileMachO();
161 if (Subtarget->isTargetELF())
162 return new TargetLoweringObjectFileELF();
163 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
164 return new TargetLoweringObjectFileCOFF();
165 llvm_unreachable("unknown subtarget type");
168 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
169 : TargetLowering(TM, createTLOF(TM)) {
170 Subtarget = &TM.getSubtarget<X86Subtarget>();
171 X86ScalarSSEf64 = Subtarget->hasXMMInt() || Subtarget->hasAVX();
172 X86ScalarSSEf32 = Subtarget->hasXMM() || Subtarget->hasAVX();
173 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
175 RegInfo = TM.getRegisterInfo();
176 TD = getTargetData();
178 // Set up the TargetLowering object.
179 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
181 // X86 is weird, it always uses i8 for shift amounts and setcc results.
182 setBooleanContents(ZeroOrOneBooleanContent);
184 // For 64-bit since we have so many registers use the ILP scheduler, for
185 // 32-bit code use the register pressure specific scheduling.
186 if (Subtarget->is64Bit())
187 setSchedulingPreference(Sched::ILP);
189 setSchedulingPreference(Sched::RegPressure);
190 setStackPointerRegisterToSaveRestore(X86StackPtr);
192 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
193 // Setup Windows compiler runtime calls.
194 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
195 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
196 setLibcallName(RTLIB::SREM_I64, "_allrem");
197 setLibcallName(RTLIB::UREM_I64, "_aullrem");
198 setLibcallName(RTLIB::MUL_I64, "_allmul");
199 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2");
200 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2");
201 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
202 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
203 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
204 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
205 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
206 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C);
207 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C);
210 if (Subtarget->isTargetDarwin()) {
211 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
212 setUseUnderscoreSetJmp(false);
213 setUseUnderscoreLongJmp(false);
214 } else if (Subtarget->isTargetMingw()) {
215 // MS runtime is weird: it exports _setjmp, but longjmp!
216 setUseUnderscoreSetJmp(true);
217 setUseUnderscoreLongJmp(false);
219 setUseUnderscoreSetJmp(true);
220 setUseUnderscoreLongJmp(true);
223 // Set up the register classes.
224 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
225 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
226 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
227 if (Subtarget->is64Bit())
228 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
230 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
232 // We don't accept any truncstore of integer registers.
233 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
234 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
235 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
236 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
237 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
238 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
240 // SETOEQ and SETUNE require checking two conditions.
241 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
242 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
243 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
244 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
245 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
246 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
248 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
250 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
251 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
252 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
254 if (Subtarget->is64Bit()) {
255 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
256 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
257 } else if (!UseSoftFloat) {
258 // We have an algorithm for SSE2->double, and we turn this into a
259 // 64-bit FILD followed by conditional FADD for other targets.
260 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
261 // We have an algorithm for SSE2, and we turn this into a 64-bit
262 // FILD for other targets.
263 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
266 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
268 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
269 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
272 // SSE has no i16 to fp conversion, only i32
273 if (X86ScalarSSEf32) {
274 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
275 // f32 and f64 cases are Legal, f80 case is not
276 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
278 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
279 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
282 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
283 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
286 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
287 // are Legal, f80 is custom lowered.
288 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
289 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
291 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
293 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
294 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
296 if (X86ScalarSSEf32) {
297 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
298 // f32 and f64 cases are Legal, f80 case is not
299 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
301 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
302 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
305 // Handle FP_TO_UINT by promoting the destination to a larger signed
307 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
308 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
309 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
311 if (Subtarget->is64Bit()) {
312 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
313 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
314 } else if (!UseSoftFloat) {
315 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
316 // Expand FP_TO_UINT into a select.
317 // FIXME: We would like to use a Custom expander here eventually to do
318 // the optimal thing for SSE vs. the default expansion in the legalizer.
319 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
321 // With SSE3 we can use fisttpll to convert to a signed i64; without
322 // SSE, we're stuck with a fistpll.
323 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
326 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
327 if (!X86ScalarSSEf64) {
328 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
329 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
330 if (Subtarget->is64Bit()) {
331 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
332 // Without SSE, i64->f64 goes through memory.
333 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
337 // Scalar integer divide and remainder are lowered to use operations that
338 // produce two results, to match the available instructions. This exposes
339 // the two-result form to trivial CSE, which is able to combine x/y and x%y
340 // into a single instruction.
342 // Scalar integer multiply-high is also lowered to use two-result
343 // operations, to match the available instructions. However, plain multiply
344 // (low) operations are left as Legal, as there are single-result
345 // instructions for this in x86. Using the two-result multiply instructions
346 // when both high and low results are needed must be arranged by dagcombine.
347 for (unsigned i = 0, e = 4; i != e; ++i) {
349 setOperationAction(ISD::MULHS, VT, Expand);
350 setOperationAction(ISD::MULHU, VT, Expand);
351 setOperationAction(ISD::SDIV, VT, Expand);
352 setOperationAction(ISD::UDIV, VT, Expand);
353 setOperationAction(ISD::SREM, VT, Expand);
354 setOperationAction(ISD::UREM, VT, Expand);
356 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
357 setOperationAction(ISD::ADDC, VT, Custom);
358 setOperationAction(ISD::ADDE, VT, Custom);
359 setOperationAction(ISD::SUBC, VT, Custom);
360 setOperationAction(ISD::SUBE, VT, Custom);
363 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
364 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
365 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
366 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
367 if (Subtarget->is64Bit())
368 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
369 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
370 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
372 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
373 setOperationAction(ISD::FREM , MVT::f32 , Expand);
374 setOperationAction(ISD::FREM , MVT::f64 , Expand);
375 setOperationAction(ISD::FREM , MVT::f80 , Expand);
376 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
378 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
379 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
380 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
381 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
382 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
383 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
384 if (Subtarget->is64Bit()) {
385 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
386 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
389 if (Subtarget->hasPOPCNT()) {
390 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
392 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
393 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
394 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
395 if (Subtarget->is64Bit())
396 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
399 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
400 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
402 // These should be promoted to a larger select which is supported.
403 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
404 // X86 wants to expand cmov itself.
405 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
406 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
407 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
408 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
409 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
410 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
411 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
412 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
413 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
414 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
415 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
416 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
417 if (Subtarget->is64Bit()) {
418 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
419 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
421 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
424 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
425 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
426 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
427 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
428 if (Subtarget->is64Bit())
429 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
430 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
431 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
432 if (Subtarget->is64Bit()) {
433 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
434 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
435 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
436 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
437 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
439 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
440 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
441 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
442 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
443 if (Subtarget->is64Bit()) {
444 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
445 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
446 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
449 if (Subtarget->hasXMM())
450 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
452 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
453 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
455 // On X86 and X86-64, atomic operations are lowered to locked instructions.
456 // Locked instructions, in turn, have implicit fence semantics (all memory
457 // operations are flushed before issuing the locked instruction, and they
458 // are not buffered), so we can fold away the common pattern of
459 // fence-atomic-fence.
460 setShouldFoldAtomicFences(true);
462 // Expand certain atomics
463 for (unsigned i = 0, e = 4; i != e; ++i) {
465 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
466 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
467 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
470 if (!Subtarget->is64Bit()) {
471 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
472 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
473 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
474 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
475 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
476 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
477 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
478 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
481 // FIXME - use subtarget debug flags
482 if (!Subtarget->isTargetDarwin() &&
483 !Subtarget->isTargetELF() &&
484 !Subtarget->isTargetCygMing()) {
485 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
488 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
489 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
490 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
491 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
492 if (Subtarget->is64Bit()) {
493 setExceptionPointerRegister(X86::RAX);
494 setExceptionSelectorRegister(X86::RDX);
496 setExceptionPointerRegister(X86::EAX);
497 setExceptionSelectorRegister(X86::EDX);
499 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
500 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
502 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
504 setOperationAction(ISD::TRAP, MVT::Other, Legal);
506 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
507 setOperationAction(ISD::VASTART , MVT::Other, Custom);
508 setOperationAction(ISD::VAEND , MVT::Other, Expand);
509 if (Subtarget->is64Bit()) {
510 setOperationAction(ISD::VAARG , MVT::Other, Custom);
511 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
513 setOperationAction(ISD::VAARG , MVT::Other, Expand);
514 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
517 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
518 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
519 setOperationAction(ISD::DYNAMIC_STACKALLOC,
520 (Subtarget->is64Bit() ? MVT::i64 : MVT::i32),
521 (Subtarget->isTargetCOFF()
522 && !Subtarget->isTargetEnvMacho()
525 if (!UseSoftFloat && X86ScalarSSEf64) {
526 // f32 and f64 use SSE.
527 // Set up the FP register classes.
528 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
529 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
531 // Use ANDPD to simulate FABS.
532 setOperationAction(ISD::FABS , MVT::f64, Custom);
533 setOperationAction(ISD::FABS , MVT::f32, Custom);
535 // Use XORP to simulate FNEG.
536 setOperationAction(ISD::FNEG , MVT::f64, Custom);
537 setOperationAction(ISD::FNEG , MVT::f32, Custom);
539 // Use ANDPD and ORPD to simulate FCOPYSIGN.
540 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
541 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
543 // Lower this to FGETSIGNx86 plus an AND.
544 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
545 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
547 // We don't support sin/cos/fmod
548 setOperationAction(ISD::FSIN , MVT::f64, Expand);
549 setOperationAction(ISD::FCOS , MVT::f64, Expand);
550 setOperationAction(ISD::FSIN , MVT::f32, Expand);
551 setOperationAction(ISD::FCOS , MVT::f32, Expand);
553 // Expand FP immediates into loads from the stack, except for the special
555 addLegalFPImmediate(APFloat(+0.0)); // xorpd
556 addLegalFPImmediate(APFloat(+0.0f)); // xorps
557 } else if (!UseSoftFloat && X86ScalarSSEf32) {
558 // Use SSE for f32, x87 for f64.
559 // Set up the FP register classes.
560 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
561 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
563 // Use ANDPS to simulate FABS.
564 setOperationAction(ISD::FABS , MVT::f32, Custom);
566 // Use XORP to simulate FNEG.
567 setOperationAction(ISD::FNEG , MVT::f32, Custom);
569 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
571 // Use ANDPS and ORPS to simulate FCOPYSIGN.
572 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
573 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
575 // We don't support sin/cos/fmod
576 setOperationAction(ISD::FSIN , MVT::f32, Expand);
577 setOperationAction(ISD::FCOS , MVT::f32, Expand);
579 // Special cases we handle for FP constants.
580 addLegalFPImmediate(APFloat(+0.0f)); // xorps
581 addLegalFPImmediate(APFloat(+0.0)); // FLD0
582 addLegalFPImmediate(APFloat(+1.0)); // FLD1
583 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
584 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
587 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
588 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
590 } else if (!UseSoftFloat) {
591 // f32 and f64 in x87.
592 // Set up the FP register classes.
593 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
594 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
596 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
597 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
598 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
599 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
602 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
603 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
605 addLegalFPImmediate(APFloat(+0.0)); // FLD0
606 addLegalFPImmediate(APFloat(+1.0)); // FLD1
607 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
608 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
609 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
610 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
611 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
612 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
615 // We don't support FMA.
616 setOperationAction(ISD::FMA, MVT::f64, Expand);
617 setOperationAction(ISD::FMA, MVT::f32, Expand);
619 // Long double always uses X87.
621 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
622 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
623 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
625 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
626 addLegalFPImmediate(TmpFlt); // FLD0
628 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
631 APFloat TmpFlt2(+1.0);
632 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
634 addLegalFPImmediate(TmpFlt2); // FLD1
635 TmpFlt2.changeSign();
636 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
640 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
641 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
644 setOperationAction(ISD::FMA, MVT::f80, Expand);
647 // Always use a library call for pow.
648 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
649 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
650 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
652 setOperationAction(ISD::FLOG, MVT::f80, Expand);
653 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
654 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
655 setOperationAction(ISD::FEXP, MVT::f80, Expand);
656 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
658 // First set operation action for all vector types to either promote
659 // (for widening) or expand (for scalarization). Then we will selectively
660 // turn on ones that can be effectively codegen'd.
661 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
662 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
663 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
664 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
665 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
666 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
667 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
668 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
669 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
670 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
671 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
672 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
673 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
674 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
675 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
676 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
677 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
678 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
679 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
680 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
681 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
682 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
683 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
684 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
685 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
686 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
687 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
688 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
689 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
690 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
691 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
692 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
693 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
694 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
695 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
696 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
697 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
698 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
699 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
700 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
701 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
702 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
703 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
704 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
705 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
706 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
707 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
708 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
709 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
710 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
711 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
713 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
717 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
718 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
719 setTruncStoreAction((MVT::SimpleValueType)VT,
720 (MVT::SimpleValueType)InnerVT, Expand);
721 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
722 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
723 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
726 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
727 // with -msoft-float, disable use of MMX as well.
728 if (!UseSoftFloat && Subtarget->hasMMX()) {
729 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
730 // No operations on x86mmx supported, everything uses intrinsics.
733 // MMX-sized vectors (other than x86mmx) are expected to be expanded
734 // into smaller operations.
735 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
736 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
737 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
738 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
739 setOperationAction(ISD::AND, MVT::v8i8, Expand);
740 setOperationAction(ISD::AND, MVT::v4i16, Expand);
741 setOperationAction(ISD::AND, MVT::v2i32, Expand);
742 setOperationAction(ISD::AND, MVT::v1i64, Expand);
743 setOperationAction(ISD::OR, MVT::v8i8, Expand);
744 setOperationAction(ISD::OR, MVT::v4i16, Expand);
745 setOperationAction(ISD::OR, MVT::v2i32, Expand);
746 setOperationAction(ISD::OR, MVT::v1i64, Expand);
747 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
748 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
749 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
750 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
751 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
752 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
753 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
754 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
755 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
756 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
757 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
758 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
759 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
760 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
761 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
762 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
763 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
765 if (!UseSoftFloat && Subtarget->hasXMM()) {
766 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
768 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
769 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
770 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
771 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
772 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
773 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
774 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
775 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
776 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
777 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
778 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
779 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
782 if (!UseSoftFloat && Subtarget->hasXMMInt()) {
783 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
785 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
786 // registers cannot be used even for integer operations.
787 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
788 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
789 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
790 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
792 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
793 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
794 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
795 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
796 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
797 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
798 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
799 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
800 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
801 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
802 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
803 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
804 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
805 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
806 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
807 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
809 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
810 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
811 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
812 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
814 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
815 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
816 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
817 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
818 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
820 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
821 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
822 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
823 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
824 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
826 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
827 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
828 EVT VT = (MVT::SimpleValueType)i;
829 // Do not attempt to custom lower non-power-of-2 vectors
830 if (!isPowerOf2_32(VT.getVectorNumElements()))
832 // Do not attempt to custom lower non-128-bit vectors
833 if (!VT.is128BitVector())
835 setOperationAction(ISD::BUILD_VECTOR,
836 VT.getSimpleVT().SimpleTy, Custom);
837 setOperationAction(ISD::VECTOR_SHUFFLE,
838 VT.getSimpleVT().SimpleTy, Custom);
839 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
840 VT.getSimpleVT().SimpleTy, Custom);
843 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
844 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
845 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
846 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
847 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
848 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
850 if (Subtarget->is64Bit()) {
851 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
852 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
855 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
856 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
857 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
860 // Do not attempt to promote non-128-bit vectors
861 if (!VT.is128BitVector())
864 setOperationAction(ISD::AND, SVT, Promote);
865 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
866 setOperationAction(ISD::OR, SVT, Promote);
867 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
868 setOperationAction(ISD::XOR, SVT, Promote);
869 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
870 setOperationAction(ISD::LOAD, SVT, Promote);
871 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
872 setOperationAction(ISD::SELECT, SVT, Promote);
873 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
876 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
878 // Custom lower v2i64 and v2f64 selects.
879 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
880 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
881 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
882 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
884 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
885 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
888 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) {
889 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
890 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
891 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
892 setOperationAction(ISD::FRINT, MVT::f32, Legal);
893 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
894 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
895 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
896 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
897 setOperationAction(ISD::FRINT, MVT::f64, Legal);
898 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
900 // FIXME: Do we need to handle scalar-to-vector here?
901 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
903 // Can turn SHL into an integer multiply.
904 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
905 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
907 // i8 and i16 vectors are custom , because the source register and source
908 // source memory operand types are not the same width. f32 vectors are
909 // custom since the immediate controlling the insert encodes additional
911 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
912 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
913 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
914 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
916 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
917 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
918 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
919 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
921 if (Subtarget->is64Bit()) {
922 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
923 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
927 if (Subtarget->hasSSE2() || Subtarget->hasAVX()) {
928 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
929 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
930 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
931 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
933 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
934 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
935 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
937 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
938 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
941 if (Subtarget->hasSSE42() || Subtarget->hasAVX())
942 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
944 if (!UseSoftFloat && Subtarget->hasAVX()) {
945 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
946 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass);
947 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
948 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
949 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
950 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
952 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
953 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
954 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
956 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
957 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
958 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
959 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
960 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
961 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
963 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
964 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
965 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
966 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
967 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
968 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
970 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
971 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
972 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
974 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
975 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
976 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
977 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
978 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
979 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
981 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
982 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
983 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
984 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
986 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
987 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
988 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
989 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
991 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
992 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
994 setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
995 setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
996 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
997 setOperationAction(ISD::VSETCC, MVT::v4i64, Custom);
999 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1000 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1001 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1003 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1004 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1005 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1006 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1008 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1009 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1010 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1011 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1013 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1014 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1015 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1016 // Don't lower v32i8 because there is no 128-bit byte mul
1018 // Custom lower several nodes for 256-bit types.
1019 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1020 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1021 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1024 // Extract subvector is special because the value type
1025 // (result) is 128-bit but the source is 256-bit wide.
1026 if (VT.is128BitVector())
1027 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1029 // Do not attempt to custom lower other non-256-bit vectors
1030 if (!VT.is256BitVector())
1033 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1034 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1035 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1036 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1037 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1038 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1041 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1042 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) {
1043 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1046 // Do not attempt to promote non-256-bit vectors
1047 if (!VT.is256BitVector())
1050 setOperationAction(ISD::AND, SVT, Promote);
1051 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1052 setOperationAction(ISD::OR, SVT, Promote);
1053 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1054 setOperationAction(ISD::XOR, SVT, Promote);
1055 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1056 setOperationAction(ISD::LOAD, SVT, Promote);
1057 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1058 setOperationAction(ISD::SELECT, SVT, Promote);
1059 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1063 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1064 // of this type with custom code.
1065 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1066 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) {
1067 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, Custom);
1070 // We want to custom lower some of our intrinsics.
1071 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1074 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1075 // handle type legalization for these operations here.
1077 // FIXME: We really should do custom legalization for addition and
1078 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1079 // than generic legalization for 64-bit multiplication-with-overflow, though.
1080 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1081 // Add/Sub/Mul with overflow operations are custom lowered.
1083 setOperationAction(ISD::SADDO, VT, Custom);
1084 setOperationAction(ISD::UADDO, VT, Custom);
1085 setOperationAction(ISD::SSUBO, VT, Custom);
1086 setOperationAction(ISD::USUBO, VT, Custom);
1087 setOperationAction(ISD::SMULO, VT, Custom);
1088 setOperationAction(ISD::UMULO, VT, Custom);
1091 // There are no 8-bit 3-address imul/mul instructions
1092 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1093 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1095 if (!Subtarget->is64Bit()) {
1096 // These libcalls are not available in 32-bit.
1097 setLibcallName(RTLIB::SHL_I128, 0);
1098 setLibcallName(RTLIB::SRL_I128, 0);
1099 setLibcallName(RTLIB::SRA_I128, 0);
1102 // We have target-specific dag combine patterns for the following nodes:
1103 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1104 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1105 setTargetDAGCombine(ISD::BUILD_VECTOR);
1106 setTargetDAGCombine(ISD::SELECT);
1107 setTargetDAGCombine(ISD::SHL);
1108 setTargetDAGCombine(ISD::SRA);
1109 setTargetDAGCombine(ISD::SRL);
1110 setTargetDAGCombine(ISD::OR);
1111 setTargetDAGCombine(ISD::AND);
1112 setTargetDAGCombine(ISD::ADD);
1113 setTargetDAGCombine(ISD::SUB);
1114 setTargetDAGCombine(ISD::STORE);
1115 setTargetDAGCombine(ISD::ZERO_EXTEND);
1116 setTargetDAGCombine(ISD::SINT_TO_FP);
1117 if (Subtarget->is64Bit())
1118 setTargetDAGCombine(ISD::MUL);
1120 computeRegisterProperties();
1122 // On Darwin, -Os means optimize for size without hurting performance,
1123 // do not reduce the limit.
1124 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1125 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1126 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1127 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1128 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1129 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1130 setPrefLoopAlignment(16);
1131 benefitFromCodePlacementOpt = true;
1133 setPrefFunctionAlignment(4);
1137 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
1142 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1143 /// the desired ByVal argument alignment.
1144 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1147 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1148 if (VTy->getBitWidth() == 128)
1150 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1151 unsigned EltAlign = 0;
1152 getMaxByValAlign(ATy->getElementType(), EltAlign);
1153 if (EltAlign > MaxAlign)
1154 MaxAlign = EltAlign;
1155 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1156 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1157 unsigned EltAlign = 0;
1158 getMaxByValAlign(STy->getElementType(i), EltAlign);
1159 if (EltAlign > MaxAlign)
1160 MaxAlign = EltAlign;
1168 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1169 /// function arguments in the caller parameter area. For X86, aggregates
1170 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1171 /// are at 4-byte boundaries.
1172 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1173 if (Subtarget->is64Bit()) {
1174 // Max of 8 and alignment of type.
1175 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1182 if (Subtarget->hasXMM())
1183 getMaxByValAlign(Ty, Align);
1187 /// getOptimalMemOpType - Returns the target specific optimal type for load
1188 /// and store operations as a result of memset, memcpy, and memmove
1189 /// lowering. If DstAlign is zero that means it's safe to destination
1190 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1191 /// means there isn't a need to check it against alignment requirement,
1192 /// probably because the source does not need to be loaded. If
1193 /// 'NonScalarIntSafe' is true, that means it's safe to return a
1194 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1195 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1196 /// constant so it does not need to be loaded.
1197 /// It returns EVT::Other if the type should be determined using generic
1198 /// target-independent logic.
1200 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1201 unsigned DstAlign, unsigned SrcAlign,
1202 bool NonScalarIntSafe,
1204 MachineFunction &MF) const {
1205 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1206 // linux. This is because the stack realignment code can't handle certain
1207 // cases like PR2962. This should be removed when PR2962 is fixed.
1208 const Function *F = MF.getFunction();
1209 if (NonScalarIntSafe &&
1210 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1212 (Subtarget->isUnalignedMemAccessFast() ||
1213 ((DstAlign == 0 || DstAlign >= 16) &&
1214 (SrcAlign == 0 || SrcAlign >= 16))) &&
1215 Subtarget->getStackAlignment() >= 16) {
1216 if (Subtarget->hasSSE2())
1218 if (Subtarget->hasSSE1())
1220 } else if (!MemcpyStrSrc && Size >= 8 &&
1221 !Subtarget->is64Bit() &&
1222 Subtarget->getStackAlignment() >= 8 &&
1223 Subtarget->hasXMMInt()) {
1224 // Do not use f64 to lower memcpy if source is string constant. It's
1225 // better to use i32 to avoid the loads.
1229 if (Subtarget->is64Bit() && Size >= 8)
1234 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1235 /// current function. The returned value is a member of the
1236 /// MachineJumpTableInfo::JTEntryKind enum.
1237 unsigned X86TargetLowering::getJumpTableEncoding() const {
1238 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1240 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1241 Subtarget->isPICStyleGOT())
1242 return MachineJumpTableInfo::EK_Custom32;
1244 // Otherwise, use the normal jump table encoding heuristics.
1245 return TargetLowering::getJumpTableEncoding();
1249 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1250 const MachineBasicBlock *MBB,
1251 unsigned uid,MCContext &Ctx) const{
1252 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1253 Subtarget->isPICStyleGOT());
1254 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1256 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1257 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1260 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1262 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1263 SelectionDAG &DAG) const {
1264 if (!Subtarget->is64Bit())
1265 // This doesn't have DebugLoc associated with it, but is not really the
1266 // same as a Register.
1267 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1271 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1272 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1274 const MCExpr *X86TargetLowering::
1275 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1276 MCContext &Ctx) const {
1277 // X86-64 uses RIP relative addressing based on the jump table label.
1278 if (Subtarget->isPICStyleRIPRel())
1279 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1281 // Otherwise, the reference is relative to the PIC base.
1282 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1285 // FIXME: Why this routine is here? Move to RegInfo!
1286 std::pair<const TargetRegisterClass*, uint8_t>
1287 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1288 const TargetRegisterClass *RRC = 0;
1290 switch (VT.getSimpleVT().SimpleTy) {
1292 return TargetLowering::findRepresentativeClass(VT);
1293 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1294 RRC = (Subtarget->is64Bit()
1295 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1298 RRC = X86::VR64RegisterClass;
1300 case MVT::f32: case MVT::f64:
1301 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1302 case MVT::v4f32: case MVT::v2f64:
1303 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1305 RRC = X86::VR128RegisterClass;
1308 return std::make_pair(RRC, Cost);
1311 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1312 unsigned &Offset) const {
1313 if (!Subtarget->isTargetLinux())
1316 if (Subtarget->is64Bit()) {
1317 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1319 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1332 //===----------------------------------------------------------------------===//
1333 // Return Value Calling Convention Implementation
1334 //===----------------------------------------------------------------------===//
1336 #include "X86GenCallingConv.inc"
1339 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1340 MachineFunction &MF, bool isVarArg,
1341 const SmallVectorImpl<ISD::OutputArg> &Outs,
1342 LLVMContext &Context) const {
1343 SmallVector<CCValAssign, 16> RVLocs;
1344 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1346 return CCInfo.CheckReturn(Outs, RetCC_X86);
1350 X86TargetLowering::LowerReturn(SDValue Chain,
1351 CallingConv::ID CallConv, bool isVarArg,
1352 const SmallVectorImpl<ISD::OutputArg> &Outs,
1353 const SmallVectorImpl<SDValue> &OutVals,
1354 DebugLoc dl, SelectionDAG &DAG) const {
1355 MachineFunction &MF = DAG.getMachineFunction();
1356 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1358 SmallVector<CCValAssign, 16> RVLocs;
1359 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1360 RVLocs, *DAG.getContext());
1361 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1363 // Add the regs to the liveout set for the function.
1364 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1365 for (unsigned i = 0; i != RVLocs.size(); ++i)
1366 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1367 MRI.addLiveOut(RVLocs[i].getLocReg());
1371 SmallVector<SDValue, 6> RetOps;
1372 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1373 // Operand #1 = Bytes To Pop
1374 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1377 // Copy the result values into the output registers.
1378 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1379 CCValAssign &VA = RVLocs[i];
1380 assert(VA.isRegLoc() && "Can only return in registers!");
1381 SDValue ValToCopy = OutVals[i];
1382 EVT ValVT = ValToCopy.getValueType();
1384 // If this is x86-64, and we disabled SSE, we can't return FP values,
1385 // or SSE or MMX vectors.
1386 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1387 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1388 (Subtarget->is64Bit() && !Subtarget->hasXMM())) {
1389 report_fatal_error("SSE register return with SSE disabled");
1391 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1392 // llvm-gcc has never done it right and no one has noticed, so this
1393 // should be OK for now.
1394 if (ValVT == MVT::f64 &&
1395 (Subtarget->is64Bit() && !Subtarget->hasXMMInt()))
1396 report_fatal_error("SSE2 register return with SSE2 disabled");
1398 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1399 // the RET instruction and handled by the FP Stackifier.
1400 if (VA.getLocReg() == X86::ST0 ||
1401 VA.getLocReg() == X86::ST1) {
1402 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1403 // change the value to the FP stack register class.
1404 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1405 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1406 RetOps.push_back(ValToCopy);
1407 // Don't emit a copytoreg.
1411 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1412 // which is returned in RAX / RDX.
1413 if (Subtarget->is64Bit()) {
1414 if (ValVT == MVT::x86mmx) {
1415 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1416 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1417 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1419 // If we don't have SSE2 available, convert to v4f32 so the generated
1420 // register is legal.
1421 if (!Subtarget->hasSSE2())
1422 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1427 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1428 Flag = Chain.getValue(1);
1431 // The x86-64 ABI for returning structs by value requires that we copy
1432 // the sret argument into %rax for the return. We saved the argument into
1433 // a virtual register in the entry block, so now we copy the value out
1435 if (Subtarget->is64Bit() &&
1436 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1437 MachineFunction &MF = DAG.getMachineFunction();
1438 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1439 unsigned Reg = FuncInfo->getSRetReturnReg();
1441 "SRetReturnReg should have been set in LowerFormalArguments().");
1442 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1444 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1445 Flag = Chain.getValue(1);
1447 // RAX now acts like a return value.
1448 MRI.addLiveOut(X86::RAX);
1451 RetOps[0] = Chain; // Update chain.
1453 // Add the flag if we have it.
1455 RetOps.push_back(Flag);
1457 return DAG.getNode(X86ISD::RET_FLAG, dl,
1458 MVT::Other, &RetOps[0], RetOps.size());
1461 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const {
1462 if (N->getNumValues() != 1)
1464 if (!N->hasNUsesOfValue(1, 0))
1467 SDNode *Copy = *N->use_begin();
1468 if (Copy->getOpcode() != ISD::CopyToReg &&
1469 Copy->getOpcode() != ISD::FP_EXTEND)
1472 bool HasRet = false;
1473 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1475 if (UI->getOpcode() != X86ISD::RET_FLAG)
1484 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1485 ISD::NodeType ExtendKind) const {
1487 // TODO: Is this also valid on 32-bit?
1488 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1489 ReturnMVT = MVT::i8;
1491 ReturnMVT = MVT::i32;
1493 EVT MinVT = getRegisterType(Context, ReturnMVT);
1494 return VT.bitsLT(MinVT) ? MinVT : VT;
1497 /// LowerCallResult - Lower the result values of a call into the
1498 /// appropriate copies out of appropriate physical registers.
1501 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1502 CallingConv::ID CallConv, bool isVarArg,
1503 const SmallVectorImpl<ISD::InputArg> &Ins,
1504 DebugLoc dl, SelectionDAG &DAG,
1505 SmallVectorImpl<SDValue> &InVals) const {
1507 // Assign locations to each value returned by this call.
1508 SmallVector<CCValAssign, 16> RVLocs;
1509 bool Is64Bit = Subtarget->is64Bit();
1510 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1511 getTargetMachine(), RVLocs, *DAG.getContext());
1512 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1514 // Copy all of the result registers out of their specified physreg.
1515 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1516 CCValAssign &VA = RVLocs[i];
1517 EVT CopyVT = VA.getValVT();
1519 // If this is x86-64, and we disabled SSE, we can't return FP values
1520 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1521 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasXMM())) {
1522 report_fatal_error("SSE register return with SSE disabled");
1527 // If this is a call to a function that returns an fp value on the floating
1528 // point stack, we must guarantee the the value is popped from the stack, so
1529 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1530 // if the return value is not used. We use the FpPOP_RETVAL instruction
1532 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1533 // If we prefer to use the value in xmm registers, copy it out as f80 and
1534 // use a truncate to move it from fp stack reg to xmm reg.
1535 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1536 SDValue Ops[] = { Chain, InFlag };
1537 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1538 MVT::Other, MVT::Glue, Ops, 2), 1);
1539 Val = Chain.getValue(0);
1541 // Round the f80 to the right size, which also moves it to the appropriate
1543 if (CopyVT != VA.getValVT())
1544 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1545 // This truncation won't change the value.
1546 DAG.getIntPtrConstant(1));
1548 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1549 CopyVT, InFlag).getValue(1);
1550 Val = Chain.getValue(0);
1552 InFlag = Chain.getValue(2);
1553 InVals.push_back(Val);
1560 //===----------------------------------------------------------------------===//
1561 // C & StdCall & Fast Calling Convention implementation
1562 //===----------------------------------------------------------------------===//
1563 // StdCall calling convention seems to be standard for many Windows' API
1564 // routines and around. It differs from C calling convention just a little:
1565 // callee should clean up the stack, not caller. Symbols should be also
1566 // decorated in some fancy way :) It doesn't support any vector arguments.
1567 // For info on fast calling convention see Fast Calling Convention (tail call)
1568 // implementation LowerX86_32FastCCCallTo.
1570 /// CallIsStructReturn - Determines whether a call uses struct return
1572 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1576 return Outs[0].Flags.isSRet();
1579 /// ArgsAreStructReturn - Determines whether a function uses struct
1580 /// return semantics.
1582 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1586 return Ins[0].Flags.isSRet();
1589 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1590 /// by "Src" to address "Dst" with size and alignment information specified by
1591 /// the specific parameter attribute. The copy will be passed as a byval
1592 /// function parameter.
1594 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1595 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1597 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1599 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1600 /*isVolatile*/false, /*AlwaysInline=*/true,
1601 MachinePointerInfo(), MachinePointerInfo());
1604 /// IsTailCallConvention - Return true if the calling convention is one that
1605 /// supports tail call optimization.
1606 static bool IsTailCallConvention(CallingConv::ID CC) {
1607 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1610 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1611 if (!CI->isTailCall())
1615 CallingConv::ID CalleeCC = CS.getCallingConv();
1616 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1622 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1623 /// a tailcall target by changing its ABI.
1624 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1625 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1629 X86TargetLowering::LowerMemArgument(SDValue Chain,
1630 CallingConv::ID CallConv,
1631 const SmallVectorImpl<ISD::InputArg> &Ins,
1632 DebugLoc dl, SelectionDAG &DAG,
1633 const CCValAssign &VA,
1634 MachineFrameInfo *MFI,
1636 // Create the nodes corresponding to a load from this parameter slot.
1637 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1638 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1639 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1642 // If value is passed by pointer we have address passed instead of the value
1644 if (VA.getLocInfo() == CCValAssign::Indirect)
1645 ValVT = VA.getLocVT();
1647 ValVT = VA.getValVT();
1649 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1650 // changed with more analysis.
1651 // In case of tail call optimization mark all arguments mutable. Since they
1652 // could be overwritten by lowering of arguments in case of a tail call.
1653 if (Flags.isByVal()) {
1654 unsigned Bytes = Flags.getByValSize();
1655 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1656 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1657 return DAG.getFrameIndex(FI, getPointerTy());
1659 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1660 VA.getLocMemOffset(), isImmutable);
1661 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1662 return DAG.getLoad(ValVT, dl, Chain, FIN,
1663 MachinePointerInfo::getFixedStack(FI),
1669 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1670 CallingConv::ID CallConv,
1672 const SmallVectorImpl<ISD::InputArg> &Ins,
1675 SmallVectorImpl<SDValue> &InVals)
1677 MachineFunction &MF = DAG.getMachineFunction();
1678 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1680 const Function* Fn = MF.getFunction();
1681 if (Fn->hasExternalLinkage() &&
1682 Subtarget->isTargetCygMing() &&
1683 Fn->getName() == "main")
1684 FuncInfo->setForceFramePointer(true);
1686 MachineFrameInfo *MFI = MF.getFrameInfo();
1687 bool Is64Bit = Subtarget->is64Bit();
1688 bool IsWin64 = Subtarget->isTargetWin64();
1690 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1691 "Var args not supported with calling convention fastcc or ghc");
1693 // Assign locations to all of the incoming arguments.
1694 SmallVector<CCValAssign, 16> ArgLocs;
1695 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1696 ArgLocs, *DAG.getContext());
1698 // Allocate shadow area for Win64
1700 CCInfo.AllocateStack(32, 8);
1703 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1705 unsigned LastVal = ~0U;
1707 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1708 CCValAssign &VA = ArgLocs[i];
1709 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1711 assert(VA.getValNo() != LastVal &&
1712 "Don't support value assigned to multiple locs yet");
1713 LastVal = VA.getValNo();
1715 if (VA.isRegLoc()) {
1716 EVT RegVT = VA.getLocVT();
1717 TargetRegisterClass *RC = NULL;
1718 if (RegVT == MVT::i32)
1719 RC = X86::GR32RegisterClass;
1720 else if (Is64Bit && RegVT == MVT::i64)
1721 RC = X86::GR64RegisterClass;
1722 else if (RegVT == MVT::f32)
1723 RC = X86::FR32RegisterClass;
1724 else if (RegVT == MVT::f64)
1725 RC = X86::FR64RegisterClass;
1726 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1727 RC = X86::VR256RegisterClass;
1728 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1729 RC = X86::VR128RegisterClass;
1730 else if (RegVT == MVT::x86mmx)
1731 RC = X86::VR64RegisterClass;
1733 llvm_unreachable("Unknown argument type!");
1735 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1736 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1738 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1739 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1741 if (VA.getLocInfo() == CCValAssign::SExt)
1742 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1743 DAG.getValueType(VA.getValVT()));
1744 else if (VA.getLocInfo() == CCValAssign::ZExt)
1745 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1746 DAG.getValueType(VA.getValVT()));
1747 else if (VA.getLocInfo() == CCValAssign::BCvt)
1748 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1750 if (VA.isExtInLoc()) {
1751 // Handle MMX values passed in XMM regs.
1752 if (RegVT.isVector()) {
1753 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1756 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1759 assert(VA.isMemLoc());
1760 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1763 // If value is passed via pointer - do a load.
1764 if (VA.getLocInfo() == CCValAssign::Indirect)
1765 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1766 MachinePointerInfo(), false, false, 0);
1768 InVals.push_back(ArgValue);
1771 // The x86-64 ABI for returning structs by value requires that we copy
1772 // the sret argument into %rax for the return. Save the argument into
1773 // a virtual register so that we can access it from the return points.
1774 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1775 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1776 unsigned Reg = FuncInfo->getSRetReturnReg();
1778 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1779 FuncInfo->setSRetReturnReg(Reg);
1781 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1782 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1785 unsigned StackSize = CCInfo.getNextStackOffset();
1786 // Align stack specially for tail calls.
1787 if (FuncIsMadeTailCallSafe(CallConv))
1788 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1790 // If the function takes variable number of arguments, make a frame index for
1791 // the start of the first vararg value... for expansion of llvm.va_start.
1793 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1794 CallConv != CallingConv::X86_ThisCall)) {
1795 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1798 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1800 // FIXME: We should really autogenerate these arrays
1801 static const unsigned GPR64ArgRegsWin64[] = {
1802 X86::RCX, X86::RDX, X86::R8, X86::R9
1804 static const unsigned GPR64ArgRegs64Bit[] = {
1805 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1807 static const unsigned XMMArgRegs64Bit[] = {
1808 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1809 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1811 const unsigned *GPR64ArgRegs;
1812 unsigned NumXMMRegs = 0;
1815 // The XMM registers which might contain var arg parameters are shadowed
1816 // in their paired GPR. So we only need to save the GPR to their home
1818 TotalNumIntRegs = 4;
1819 GPR64ArgRegs = GPR64ArgRegsWin64;
1821 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1822 GPR64ArgRegs = GPR64ArgRegs64Bit;
1824 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, TotalNumXMMRegs);
1826 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1829 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1830 assert(!(NumXMMRegs && !Subtarget->hasXMM()) &&
1831 "SSE register cannot be used when SSE is disabled!");
1832 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1833 "SSE register cannot be used when SSE is disabled!");
1834 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasXMM())
1835 // Kernel mode asks for SSE to be disabled, so don't push them
1837 TotalNumXMMRegs = 0;
1840 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1841 // Get to the caller-allocated home save location. Add 8 to account
1842 // for the return address.
1843 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1844 FuncInfo->setRegSaveFrameIndex(
1845 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1846 // Fixup to set vararg frame on shadow area (4 x i64).
1848 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1850 // For X86-64, if there are vararg parameters that are passed via
1851 // registers, then we must store them to their spots on the stack so they
1852 // may be loaded by deferencing the result of va_next.
1853 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1854 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1855 FuncInfo->setRegSaveFrameIndex(
1856 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1860 // Store the integer parameter registers.
1861 SmallVector<SDValue, 8> MemOps;
1862 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1864 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1865 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1866 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1867 DAG.getIntPtrConstant(Offset));
1868 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1869 X86::GR64RegisterClass);
1870 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1872 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1873 MachinePointerInfo::getFixedStack(
1874 FuncInfo->getRegSaveFrameIndex(), Offset),
1876 MemOps.push_back(Store);
1880 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1881 // Now store the XMM (fp + vector) parameter registers.
1882 SmallVector<SDValue, 11> SaveXMMOps;
1883 SaveXMMOps.push_back(Chain);
1885 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1886 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1887 SaveXMMOps.push_back(ALVal);
1889 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1890 FuncInfo->getRegSaveFrameIndex()));
1891 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1892 FuncInfo->getVarArgsFPOffset()));
1894 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1895 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
1896 X86::VR128RegisterClass);
1897 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1898 SaveXMMOps.push_back(Val);
1900 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1902 &SaveXMMOps[0], SaveXMMOps.size()));
1905 if (!MemOps.empty())
1906 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1907 &MemOps[0], MemOps.size());
1911 // Some CCs need callee pop.
1912 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt)) {
1913 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
1915 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
1916 // If this is an sret function, the return should pop the hidden pointer.
1917 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
1918 FuncInfo->setBytesToPopOnReturn(4);
1922 // RegSaveFrameIndex is X86-64 only.
1923 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
1924 if (CallConv == CallingConv::X86_FastCall ||
1925 CallConv == CallingConv::X86_ThisCall)
1926 // fastcc functions can't have varargs.
1927 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
1934 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1935 SDValue StackPtr, SDValue Arg,
1936 DebugLoc dl, SelectionDAG &DAG,
1937 const CCValAssign &VA,
1938 ISD::ArgFlagsTy Flags) const {
1939 unsigned LocMemOffset = VA.getLocMemOffset();
1940 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1941 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1942 if (Flags.isByVal())
1943 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1945 return DAG.getStore(Chain, dl, Arg, PtrOff,
1946 MachinePointerInfo::getStack(LocMemOffset),
1950 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1951 /// optimization is performed and it is required.
1953 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1954 SDValue &OutRetAddr, SDValue Chain,
1955 bool IsTailCall, bool Is64Bit,
1956 int FPDiff, DebugLoc dl) const {
1957 // Adjust the Return address stack slot.
1958 EVT VT = getPointerTy();
1959 OutRetAddr = getReturnAddressFrameIndex(DAG);
1961 // Load the "old" Return address.
1962 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
1964 return SDValue(OutRetAddr.getNode(), 1);
1967 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
1968 /// optimization is performed and it is required (FPDiff!=0).
1970 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1971 SDValue Chain, SDValue RetAddrFrIdx,
1972 bool Is64Bit, int FPDiff, DebugLoc dl) {
1973 // Store the return address to the appropriate stack slot.
1974 if (!FPDiff) return Chain;
1975 // Calculate the new stack slot for the return address.
1976 int SlotSize = Is64Bit ? 8 : 4;
1977 int NewReturnAddrFI =
1978 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
1979 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1980 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1981 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1982 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
1988 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1989 CallingConv::ID CallConv, bool isVarArg,
1991 const SmallVectorImpl<ISD::OutputArg> &Outs,
1992 const SmallVectorImpl<SDValue> &OutVals,
1993 const SmallVectorImpl<ISD::InputArg> &Ins,
1994 DebugLoc dl, SelectionDAG &DAG,
1995 SmallVectorImpl<SDValue> &InVals) const {
1996 MachineFunction &MF = DAG.getMachineFunction();
1997 bool Is64Bit = Subtarget->is64Bit();
1998 bool IsWin64 = Subtarget->isTargetWin64();
1999 bool IsStructRet = CallIsStructReturn(Outs);
2000 bool IsSibcall = false;
2003 // Check if it's really possible to do a tail call.
2004 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2005 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2006 Outs, OutVals, Ins, DAG);
2008 // Sibcalls are automatically detected tailcalls which do not require
2010 if (!GuaranteedTailCallOpt && isTailCall)
2017 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2018 "Var args not supported with calling convention fastcc or ghc");
2020 // Analyze operands of the call, assigning locations to each operand.
2021 SmallVector<CCValAssign, 16> ArgLocs;
2022 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2023 ArgLocs, *DAG.getContext());
2025 // Allocate shadow area for Win64
2027 CCInfo.AllocateStack(32, 8);
2030 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2032 // Get a count of how many bytes are to be pushed on the stack.
2033 unsigned NumBytes = CCInfo.getNextStackOffset();
2035 // This is a sibcall. The memory operands are available in caller's
2036 // own caller's stack.
2038 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv))
2039 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2042 if (isTailCall && !IsSibcall) {
2043 // Lower arguments at fp - stackoffset + fpdiff.
2044 unsigned NumBytesCallerPushed =
2045 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2046 FPDiff = NumBytesCallerPushed - NumBytes;
2048 // Set the delta of movement of the returnaddr stackslot.
2049 // But only set if delta is greater than previous delta.
2050 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2051 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2055 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2057 SDValue RetAddrFrIdx;
2058 // Load return address for tail calls.
2059 if (isTailCall && FPDiff)
2060 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2061 Is64Bit, FPDiff, dl);
2063 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2064 SmallVector<SDValue, 8> MemOpChains;
2067 // Walk the register/memloc assignments, inserting copies/loads. In the case
2068 // of tail call optimization arguments are handle later.
2069 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2070 CCValAssign &VA = ArgLocs[i];
2071 EVT RegVT = VA.getLocVT();
2072 SDValue Arg = OutVals[i];
2073 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2074 bool isByVal = Flags.isByVal();
2076 // Promote the value if needed.
2077 switch (VA.getLocInfo()) {
2078 default: llvm_unreachable("Unknown loc info!");
2079 case CCValAssign::Full: break;
2080 case CCValAssign::SExt:
2081 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2083 case CCValAssign::ZExt:
2084 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2086 case CCValAssign::AExt:
2087 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2088 // Special case: passing MMX values in XMM registers.
2089 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2090 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2091 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2093 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2095 case CCValAssign::BCvt:
2096 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2098 case CCValAssign::Indirect: {
2099 // Store the argument.
2100 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2101 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2102 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2103 MachinePointerInfo::getFixedStack(FI),
2110 if (VA.isRegLoc()) {
2111 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2112 if (isVarArg && IsWin64) {
2113 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2114 // shadow reg if callee is a varargs function.
2115 unsigned ShadowReg = 0;
2116 switch (VA.getLocReg()) {
2117 case X86::XMM0: ShadowReg = X86::RCX; break;
2118 case X86::XMM1: ShadowReg = X86::RDX; break;
2119 case X86::XMM2: ShadowReg = X86::R8; break;
2120 case X86::XMM3: ShadowReg = X86::R9; break;
2123 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2125 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2126 assert(VA.isMemLoc());
2127 if (StackPtr.getNode() == 0)
2128 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2129 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2130 dl, DAG, VA, Flags));
2134 if (!MemOpChains.empty())
2135 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2136 &MemOpChains[0], MemOpChains.size());
2138 // Build a sequence of copy-to-reg nodes chained together with token chain
2139 // and flag operands which copy the outgoing args into registers.
2141 // Tail call byval lowering might overwrite argument registers so in case of
2142 // tail call optimization the copies to registers are lowered later.
2144 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2145 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2146 RegsToPass[i].second, InFlag);
2147 InFlag = Chain.getValue(1);
2150 if (Subtarget->isPICStyleGOT()) {
2151 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2154 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2155 DAG.getNode(X86ISD::GlobalBaseReg,
2156 DebugLoc(), getPointerTy()),
2158 InFlag = Chain.getValue(1);
2160 // If we are tail calling and generating PIC/GOT style code load the
2161 // address of the callee into ECX. The value in ecx is used as target of
2162 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2163 // for tail calls on PIC/GOT architectures. Normally we would just put the
2164 // address of GOT into ebx and then call target@PLT. But for tail calls
2165 // ebx would be restored (since ebx is callee saved) before jumping to the
2168 // Note: The actual moving to ECX is done further down.
2169 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2170 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2171 !G->getGlobal()->hasProtectedVisibility())
2172 Callee = LowerGlobalAddress(Callee, DAG);
2173 else if (isa<ExternalSymbolSDNode>(Callee))
2174 Callee = LowerExternalSymbol(Callee, DAG);
2178 if (Is64Bit && isVarArg && !IsWin64) {
2179 // From AMD64 ABI document:
2180 // For calls that may call functions that use varargs or stdargs
2181 // (prototype-less calls or calls to functions containing ellipsis (...) in
2182 // the declaration) %al is used as hidden argument to specify the number
2183 // of SSE registers used. The contents of %al do not need to match exactly
2184 // the number of registers, but must be an ubound on the number of SSE
2185 // registers used and is in the range 0 - 8 inclusive.
2187 // Count the number of XMM registers allocated.
2188 static const unsigned XMMArgRegs[] = {
2189 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2190 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2192 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2193 assert((Subtarget->hasXMM() || !NumXMMRegs)
2194 && "SSE registers cannot be used when SSE is disabled");
2196 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2197 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2198 InFlag = Chain.getValue(1);
2202 // For tail calls lower the arguments to the 'real' stack slot.
2204 // Force all the incoming stack arguments to be loaded from the stack
2205 // before any new outgoing arguments are stored to the stack, because the
2206 // outgoing stack slots may alias the incoming argument stack slots, and
2207 // the alias isn't otherwise explicit. This is slightly more conservative
2208 // than necessary, because it means that each store effectively depends
2209 // on every argument instead of just those arguments it would clobber.
2210 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2212 SmallVector<SDValue, 8> MemOpChains2;
2215 // Do not flag preceding copytoreg stuff together with the following stuff.
2217 if (GuaranteedTailCallOpt) {
2218 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2219 CCValAssign &VA = ArgLocs[i];
2222 assert(VA.isMemLoc());
2223 SDValue Arg = OutVals[i];
2224 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2225 // Create frame index.
2226 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2227 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2228 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2229 FIN = DAG.getFrameIndex(FI, getPointerTy());
2231 if (Flags.isByVal()) {
2232 // Copy relative to framepointer.
2233 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2234 if (StackPtr.getNode() == 0)
2235 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2237 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2239 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2243 // Store relative to framepointer.
2244 MemOpChains2.push_back(
2245 DAG.getStore(ArgChain, dl, Arg, FIN,
2246 MachinePointerInfo::getFixedStack(FI),
2252 if (!MemOpChains2.empty())
2253 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2254 &MemOpChains2[0], MemOpChains2.size());
2256 // Copy arguments to their registers.
2257 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2258 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2259 RegsToPass[i].second, InFlag);
2260 InFlag = Chain.getValue(1);
2264 // Store the return address to the appropriate stack slot.
2265 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2269 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2270 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2271 // In the 64-bit large code model, we have to make all calls
2272 // through a register, since the call instruction's 32-bit
2273 // pc-relative offset may not be large enough to hold the whole
2275 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2276 // If the callee is a GlobalAddress node (quite common, every direct call
2277 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2280 // We should use extra load for direct calls to dllimported functions in
2282 const GlobalValue *GV = G->getGlobal();
2283 if (!GV->hasDLLImportLinkage()) {
2284 unsigned char OpFlags = 0;
2285 bool ExtraLoad = false;
2286 unsigned WrapperKind = ISD::DELETED_NODE;
2288 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2289 // external symbols most go through the PLT in PIC mode. If the symbol
2290 // has hidden or protected visibility, or if it is static or local, then
2291 // we don't need to use the PLT - we can directly call it.
2292 if (Subtarget->isTargetELF() &&
2293 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2294 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2295 OpFlags = X86II::MO_PLT;
2296 } else if (Subtarget->isPICStyleStubAny() &&
2297 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2298 (!Subtarget->getTargetTriple().isMacOSX() ||
2299 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2300 // PC-relative references to external symbols should go through $stub,
2301 // unless we're building with the leopard linker or later, which
2302 // automatically synthesizes these stubs.
2303 OpFlags = X86II::MO_DARWIN_STUB;
2304 } else if (Subtarget->isPICStyleRIPRel() &&
2305 isa<Function>(GV) &&
2306 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2307 // If the function is marked as non-lazy, generate an indirect call
2308 // which loads from the GOT directly. This avoids runtime overhead
2309 // at the cost of eager binding (and one extra byte of encoding).
2310 OpFlags = X86II::MO_GOTPCREL;
2311 WrapperKind = X86ISD::WrapperRIP;
2315 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2316 G->getOffset(), OpFlags);
2318 // Add a wrapper if needed.
2319 if (WrapperKind != ISD::DELETED_NODE)
2320 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2321 // Add extra indirection if needed.
2323 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2324 MachinePointerInfo::getGOT(),
2327 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2328 unsigned char OpFlags = 0;
2330 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2331 // external symbols should go through the PLT.
2332 if (Subtarget->isTargetELF() &&
2333 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2334 OpFlags = X86II::MO_PLT;
2335 } else if (Subtarget->isPICStyleStubAny() &&
2336 (!Subtarget->getTargetTriple().isMacOSX() ||
2337 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2338 // PC-relative references to external symbols should go through $stub,
2339 // unless we're building with the leopard linker or later, which
2340 // automatically synthesizes these stubs.
2341 OpFlags = X86II::MO_DARWIN_STUB;
2344 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2348 // Returns a chain & a flag for retval copy to use.
2349 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2350 SmallVector<SDValue, 8> Ops;
2352 if (!IsSibcall && isTailCall) {
2353 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2354 DAG.getIntPtrConstant(0, true), InFlag);
2355 InFlag = Chain.getValue(1);
2358 Ops.push_back(Chain);
2359 Ops.push_back(Callee);
2362 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2364 // Add argument registers to the end of the list so that they are known live
2366 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2367 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2368 RegsToPass[i].second.getValueType()));
2370 // Add an implicit use GOT pointer in EBX.
2371 if (!isTailCall && Subtarget->isPICStyleGOT())
2372 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2374 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2375 if (Is64Bit && isVarArg && !IsWin64)
2376 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2378 if (InFlag.getNode())
2379 Ops.push_back(InFlag);
2383 //// If this is the first return lowered for this function, add the regs
2384 //// to the liveout set for the function.
2385 // This isn't right, although it's probably harmless on x86; liveouts
2386 // should be computed from returns not tail calls. Consider a void
2387 // function making a tail call to a function returning int.
2388 return DAG.getNode(X86ISD::TC_RETURN, dl,
2389 NodeTys, &Ops[0], Ops.size());
2392 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2393 InFlag = Chain.getValue(1);
2395 // Create the CALLSEQ_END node.
2396 unsigned NumBytesForCalleeToPush;
2397 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt))
2398 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2399 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2400 // If this is a call to a struct-return function, the callee
2401 // pops the hidden struct pointer, so we have to push it back.
2402 // This is common for Darwin/X86, Linux & Mingw32 targets.
2403 NumBytesForCalleeToPush = 4;
2405 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2407 // Returns a flag for retval copy to use.
2409 Chain = DAG.getCALLSEQ_END(Chain,
2410 DAG.getIntPtrConstant(NumBytes, true),
2411 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2414 InFlag = Chain.getValue(1);
2417 // Handle result values, copying them out of physregs into vregs that we
2419 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2420 Ins, dl, DAG, InVals);
2424 //===----------------------------------------------------------------------===//
2425 // Fast Calling Convention (tail call) implementation
2426 //===----------------------------------------------------------------------===//
2428 // Like std call, callee cleans arguments, convention except that ECX is
2429 // reserved for storing the tail called function address. Only 2 registers are
2430 // free for argument passing (inreg). Tail call optimization is performed
2432 // * tailcallopt is enabled
2433 // * caller/callee are fastcc
2434 // On X86_64 architecture with GOT-style position independent code only local
2435 // (within module) calls are supported at the moment.
2436 // To keep the stack aligned according to platform abi the function
2437 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2438 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2439 // If a tail called function callee has more arguments than the caller the
2440 // caller needs to make sure that there is room to move the RETADDR to. This is
2441 // achieved by reserving an area the size of the argument delta right after the
2442 // original REtADDR, but before the saved framepointer or the spilled registers
2443 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2455 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2456 /// for a 16 byte align requirement.
2458 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2459 SelectionDAG& DAG) const {
2460 MachineFunction &MF = DAG.getMachineFunction();
2461 const TargetMachine &TM = MF.getTarget();
2462 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2463 unsigned StackAlignment = TFI.getStackAlignment();
2464 uint64_t AlignMask = StackAlignment - 1;
2465 int64_t Offset = StackSize;
2466 uint64_t SlotSize = TD->getPointerSize();
2467 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2468 // Number smaller than 12 so just add the difference.
2469 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2471 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2472 Offset = ((~AlignMask) & Offset) + StackAlignment +
2473 (StackAlignment-SlotSize);
2478 /// MatchingStackOffset - Return true if the given stack call argument is
2479 /// already available in the same position (relatively) of the caller's
2480 /// incoming argument stack.
2482 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2483 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2484 const X86InstrInfo *TII) {
2485 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2487 if (Arg.getOpcode() == ISD::CopyFromReg) {
2488 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2489 if (!TargetRegisterInfo::isVirtualRegister(VR))
2491 MachineInstr *Def = MRI->getVRegDef(VR);
2494 if (!Flags.isByVal()) {
2495 if (!TII->isLoadFromStackSlot(Def, FI))
2498 unsigned Opcode = Def->getOpcode();
2499 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2500 Def->getOperand(1).isFI()) {
2501 FI = Def->getOperand(1).getIndex();
2502 Bytes = Flags.getByValSize();
2506 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2507 if (Flags.isByVal())
2508 // ByVal argument is passed in as a pointer but it's now being
2509 // dereferenced. e.g.
2510 // define @foo(%struct.X* %A) {
2511 // tail call @bar(%struct.X* byval %A)
2514 SDValue Ptr = Ld->getBasePtr();
2515 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2518 FI = FINode->getIndex();
2519 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2520 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2521 FI = FINode->getIndex();
2522 Bytes = Flags.getByValSize();
2526 assert(FI != INT_MAX);
2527 if (!MFI->isFixedObjectIndex(FI))
2529 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2532 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2533 /// for tail call optimization. Targets which want to do tail call
2534 /// optimization should implement this function.
2536 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2537 CallingConv::ID CalleeCC,
2539 bool isCalleeStructRet,
2540 bool isCallerStructRet,
2541 const SmallVectorImpl<ISD::OutputArg> &Outs,
2542 const SmallVectorImpl<SDValue> &OutVals,
2543 const SmallVectorImpl<ISD::InputArg> &Ins,
2544 SelectionDAG& DAG) const {
2545 if (!IsTailCallConvention(CalleeCC) &&
2546 CalleeCC != CallingConv::C)
2549 // If -tailcallopt is specified, make fastcc functions tail-callable.
2550 const MachineFunction &MF = DAG.getMachineFunction();
2551 const Function *CallerF = DAG.getMachineFunction().getFunction();
2552 CallingConv::ID CallerCC = CallerF->getCallingConv();
2553 bool CCMatch = CallerCC == CalleeCC;
2555 if (GuaranteedTailCallOpt) {
2556 if (IsTailCallConvention(CalleeCC) && CCMatch)
2561 // Look for obvious safe cases to perform tail call optimization that do not
2562 // require ABI changes. This is what gcc calls sibcall.
2564 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2565 // emit a special epilogue.
2566 if (RegInfo->needsStackRealignment(MF))
2569 // Also avoid sibcall optimization if either caller or callee uses struct
2570 // return semantics.
2571 if (isCalleeStructRet || isCallerStructRet)
2574 // An stdcall caller is expected to clean up its arguments; the callee
2575 // isn't going to do that.
2576 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2579 // Do not sibcall optimize vararg calls unless all arguments are passed via
2581 if (isVarArg && !Outs.empty()) {
2583 // Optimizing for varargs on Win64 is unlikely to be safe without
2584 // additional testing.
2585 if (Subtarget->isTargetWin64())
2588 SmallVector<CCValAssign, 16> ArgLocs;
2589 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2590 getTargetMachine(), ArgLocs, *DAG.getContext());
2592 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2593 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2594 if (!ArgLocs[i].isRegLoc())
2598 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack.
2599 // Therefore if it's not used by the call it is not safe to optimize this into
2601 bool Unused = false;
2602 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2609 SmallVector<CCValAssign, 16> RVLocs;
2610 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2611 getTargetMachine(), RVLocs, *DAG.getContext());
2612 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2613 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2614 CCValAssign &VA = RVLocs[i];
2615 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2620 // If the calling conventions do not match, then we'd better make sure the
2621 // results are returned in the same way as what the caller expects.
2623 SmallVector<CCValAssign, 16> RVLocs1;
2624 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2625 getTargetMachine(), RVLocs1, *DAG.getContext());
2626 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2628 SmallVector<CCValAssign, 16> RVLocs2;
2629 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2630 getTargetMachine(), RVLocs2, *DAG.getContext());
2631 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2633 if (RVLocs1.size() != RVLocs2.size())
2635 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2636 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2638 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2640 if (RVLocs1[i].isRegLoc()) {
2641 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2644 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2650 // If the callee takes no arguments then go on to check the results of the
2652 if (!Outs.empty()) {
2653 // Check if stack adjustment is needed. For now, do not do this if any
2654 // argument is passed on the stack.
2655 SmallVector<CCValAssign, 16> ArgLocs;
2656 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2657 getTargetMachine(), ArgLocs, *DAG.getContext());
2659 // Allocate shadow area for Win64
2660 if (Subtarget->isTargetWin64()) {
2661 CCInfo.AllocateStack(32, 8);
2664 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2665 if (CCInfo.getNextStackOffset()) {
2666 MachineFunction &MF = DAG.getMachineFunction();
2667 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2670 // Check if the arguments are already laid out in the right way as
2671 // the caller's fixed stack objects.
2672 MachineFrameInfo *MFI = MF.getFrameInfo();
2673 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2674 const X86InstrInfo *TII =
2675 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2676 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2677 CCValAssign &VA = ArgLocs[i];
2678 SDValue Arg = OutVals[i];
2679 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2680 if (VA.getLocInfo() == CCValAssign::Indirect)
2682 if (!VA.isRegLoc()) {
2683 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2690 // If the tailcall address may be in a register, then make sure it's
2691 // possible to register allocate for it. In 32-bit, the call address can
2692 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2693 // callee-saved registers are restored. These happen to be the same
2694 // registers used to pass 'inreg' arguments so watch out for those.
2695 if (!Subtarget->is64Bit() &&
2696 !isa<GlobalAddressSDNode>(Callee) &&
2697 !isa<ExternalSymbolSDNode>(Callee)) {
2698 unsigned NumInRegs = 0;
2699 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2700 CCValAssign &VA = ArgLocs[i];
2703 unsigned Reg = VA.getLocReg();
2706 case X86::EAX: case X86::EDX: case X86::ECX:
2707 if (++NumInRegs == 3)
2719 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2720 return X86::createFastISel(funcInfo);
2724 //===----------------------------------------------------------------------===//
2725 // Other Lowering Hooks
2726 //===----------------------------------------------------------------------===//
2728 static bool MayFoldLoad(SDValue Op) {
2729 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2732 static bool MayFoldIntoStore(SDValue Op) {
2733 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2736 static bool isTargetShuffle(unsigned Opcode) {
2738 default: return false;
2739 case X86ISD::PSHUFD:
2740 case X86ISD::PSHUFHW:
2741 case X86ISD::PSHUFLW:
2742 case X86ISD::SHUFPD:
2743 case X86ISD::PALIGN:
2744 case X86ISD::SHUFPS:
2745 case X86ISD::MOVLHPS:
2746 case X86ISD::MOVLHPD:
2747 case X86ISD::MOVHLPS:
2748 case X86ISD::MOVLPS:
2749 case X86ISD::MOVLPD:
2750 case X86ISD::MOVSHDUP:
2751 case X86ISD::MOVSLDUP:
2752 case X86ISD::MOVDDUP:
2755 case X86ISD::UNPCKLPS:
2756 case X86ISD::UNPCKLPD:
2757 case X86ISD::VUNPCKLPSY:
2758 case X86ISD::VUNPCKLPDY:
2759 case X86ISD::PUNPCKLWD:
2760 case X86ISD::PUNPCKLBW:
2761 case X86ISD::PUNPCKLDQ:
2762 case X86ISD::PUNPCKLQDQ:
2763 case X86ISD::UNPCKHPS:
2764 case X86ISD::UNPCKHPD:
2765 case X86ISD::VUNPCKHPSY:
2766 case X86ISD::VUNPCKHPDY:
2767 case X86ISD::PUNPCKHWD:
2768 case X86ISD::PUNPCKHBW:
2769 case X86ISD::PUNPCKHDQ:
2770 case X86ISD::PUNPCKHQDQ:
2771 case X86ISD::VPERMILPS:
2772 case X86ISD::VPERMILPSY:
2773 case X86ISD::VPERMILPD:
2774 case X86ISD::VPERMILPDY:
2775 case X86ISD::VPERM2F128:
2781 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2782 SDValue V1, SelectionDAG &DAG) {
2784 default: llvm_unreachable("Unknown x86 shuffle node");
2785 case X86ISD::MOVSHDUP:
2786 case X86ISD::MOVSLDUP:
2787 case X86ISD::MOVDDUP:
2788 return DAG.getNode(Opc, dl, VT, V1);
2794 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2795 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2797 default: llvm_unreachable("Unknown x86 shuffle node");
2798 case X86ISD::PSHUFD:
2799 case X86ISD::PSHUFHW:
2800 case X86ISD::PSHUFLW:
2801 case X86ISD::VPERMILPS:
2802 case X86ISD::VPERMILPSY:
2803 case X86ISD::VPERMILPD:
2804 case X86ISD::VPERMILPDY:
2805 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2811 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2812 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2814 default: llvm_unreachable("Unknown x86 shuffle node");
2815 case X86ISD::PALIGN:
2816 case X86ISD::SHUFPD:
2817 case X86ISD::SHUFPS:
2818 case X86ISD::VPERM2F128:
2819 return DAG.getNode(Opc, dl, VT, V1, V2,
2820 DAG.getConstant(TargetMask, MVT::i8));
2825 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2826 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2828 default: llvm_unreachable("Unknown x86 shuffle node");
2829 case X86ISD::MOVLHPS:
2830 case X86ISD::MOVLHPD:
2831 case X86ISD::MOVHLPS:
2832 case X86ISD::MOVLPS:
2833 case X86ISD::MOVLPD:
2836 case X86ISD::UNPCKLPS:
2837 case X86ISD::UNPCKLPD:
2838 case X86ISD::VUNPCKLPSY:
2839 case X86ISD::VUNPCKLPDY:
2840 case X86ISD::PUNPCKLWD:
2841 case X86ISD::PUNPCKLBW:
2842 case X86ISD::PUNPCKLDQ:
2843 case X86ISD::PUNPCKLQDQ:
2844 case X86ISD::UNPCKHPS:
2845 case X86ISD::UNPCKHPD:
2846 case X86ISD::VUNPCKHPSY:
2847 case X86ISD::VUNPCKHPDY:
2848 case X86ISD::PUNPCKHWD:
2849 case X86ISD::PUNPCKHBW:
2850 case X86ISD::PUNPCKHDQ:
2851 case X86ISD::PUNPCKHQDQ:
2852 return DAG.getNode(Opc, dl, VT, V1, V2);
2857 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2858 MachineFunction &MF = DAG.getMachineFunction();
2859 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2860 int ReturnAddrIndex = FuncInfo->getRAIndex();
2862 if (ReturnAddrIndex == 0) {
2863 // Set up a frame object for the return address.
2864 uint64_t SlotSize = TD->getPointerSize();
2865 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2867 FuncInfo->setRAIndex(ReturnAddrIndex);
2870 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2874 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2875 bool hasSymbolicDisplacement) {
2876 // Offset should fit into 32 bit immediate field.
2877 if (!isInt<32>(Offset))
2880 // If we don't have a symbolic displacement - we don't have any extra
2882 if (!hasSymbolicDisplacement)
2885 // FIXME: Some tweaks might be needed for medium code model.
2886 if (M != CodeModel::Small && M != CodeModel::Kernel)
2889 // For small code model we assume that latest object is 16MB before end of 31
2890 // bits boundary. We may also accept pretty large negative constants knowing
2891 // that all objects are in the positive half of address space.
2892 if (M == CodeModel::Small && Offset < 16*1024*1024)
2895 // For kernel code model we know that all object resist in the negative half
2896 // of 32bits address space. We may not accept negative offsets, since they may
2897 // be just off and we may accept pretty large positive ones.
2898 if (M == CodeModel::Kernel && Offset > 0)
2904 /// isCalleePop - Determines whether the callee is required to pop its
2905 /// own arguments. Callee pop is necessary to support tail calls.
2906 bool X86::isCalleePop(CallingConv::ID CallingConv,
2907 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
2911 switch (CallingConv) {
2914 case CallingConv::X86_StdCall:
2916 case CallingConv::X86_FastCall:
2918 case CallingConv::X86_ThisCall:
2920 case CallingConv::Fast:
2922 case CallingConv::GHC:
2927 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2928 /// specific condition code, returning the condition code and the LHS/RHS of the
2929 /// comparison to make.
2930 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2931 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2933 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2934 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2935 // X > -1 -> X == 0, jump !sign.
2936 RHS = DAG.getConstant(0, RHS.getValueType());
2937 return X86::COND_NS;
2938 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2939 // X < 0 -> X == 0, jump on sign.
2941 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2943 RHS = DAG.getConstant(0, RHS.getValueType());
2944 return X86::COND_LE;
2948 switch (SetCCOpcode) {
2949 default: llvm_unreachable("Invalid integer condition!");
2950 case ISD::SETEQ: return X86::COND_E;
2951 case ISD::SETGT: return X86::COND_G;
2952 case ISD::SETGE: return X86::COND_GE;
2953 case ISD::SETLT: return X86::COND_L;
2954 case ISD::SETLE: return X86::COND_LE;
2955 case ISD::SETNE: return X86::COND_NE;
2956 case ISD::SETULT: return X86::COND_B;
2957 case ISD::SETUGT: return X86::COND_A;
2958 case ISD::SETULE: return X86::COND_BE;
2959 case ISD::SETUGE: return X86::COND_AE;
2963 // First determine if it is required or is profitable to flip the operands.
2965 // If LHS is a foldable load, but RHS is not, flip the condition.
2966 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
2967 !ISD::isNON_EXTLoad(RHS.getNode())) {
2968 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2969 std::swap(LHS, RHS);
2972 switch (SetCCOpcode) {
2978 std::swap(LHS, RHS);
2982 // On a floating point condition, the flags are set as follows:
2984 // 0 | 0 | 0 | X > Y
2985 // 0 | 0 | 1 | X < Y
2986 // 1 | 0 | 0 | X == Y
2987 // 1 | 1 | 1 | unordered
2988 switch (SetCCOpcode) {
2989 default: llvm_unreachable("Condcode should be pre-legalized away");
2991 case ISD::SETEQ: return X86::COND_E;
2992 case ISD::SETOLT: // flipped
2994 case ISD::SETGT: return X86::COND_A;
2995 case ISD::SETOLE: // flipped
2997 case ISD::SETGE: return X86::COND_AE;
2998 case ISD::SETUGT: // flipped
3000 case ISD::SETLT: return X86::COND_B;
3001 case ISD::SETUGE: // flipped
3003 case ISD::SETLE: return X86::COND_BE;
3005 case ISD::SETNE: return X86::COND_NE;
3006 case ISD::SETUO: return X86::COND_P;
3007 case ISD::SETO: return X86::COND_NP;
3009 case ISD::SETUNE: return X86::COND_INVALID;
3013 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3014 /// code. Current x86 isa includes the following FP cmov instructions:
3015 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3016 static bool hasFPCMov(unsigned X86CC) {
3032 /// isFPImmLegal - Returns true if the target can instruction select the
3033 /// specified FP immediate natively. If false, the legalizer will
3034 /// materialize the FP immediate as a load from a constant pool.
3035 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3036 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3037 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3043 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3044 /// the specified range (L, H].
3045 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3046 return (Val < 0) || (Val >= Low && Val < Hi);
3049 /// isUndefOrInRange - Return true if every element in Mask, begining
3050 /// from position Pos and ending in Pos+Size, falls within the specified
3051 /// range (L, L+Pos]. or is undef.
3052 static bool isUndefOrInRange(const SmallVectorImpl<int> &Mask,
3053 int Pos, int Size, int Low, int Hi) {
3054 for (int i = Pos, e = Pos+Size; i != e; ++i)
3055 if (!isUndefOrInRange(Mask[i], Low, Hi))
3060 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3061 /// specified value.
3062 static bool isUndefOrEqual(int Val, int CmpVal) {
3063 if (Val < 0 || Val == CmpVal)
3068 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining
3069 /// from position Pos and ending in Pos+Size, falls within the specified
3070 /// sequential range (L, L+Pos]. or is undef.
3071 static bool isSequentialOrUndefInRange(const SmallVectorImpl<int> &Mask,
3072 int Pos, int Size, int Low) {
3073 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3074 if (!isUndefOrEqual(Mask[i], Low))
3079 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3080 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3081 /// the second operand.
3082 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3083 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3084 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3085 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3086 return (Mask[0] < 2 && Mask[1] < 2);
3090 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
3091 SmallVector<int, 8> M;
3093 return ::isPSHUFDMask(M, N->getValueType(0));
3096 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3097 /// is suitable for input to PSHUFHW.
3098 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3099 if (VT != MVT::v8i16)
3102 // Lower quadword copied in order or undef.
3103 for (int i = 0; i != 4; ++i)
3104 if (Mask[i] >= 0 && Mask[i] != i)
3107 // Upper quadword shuffled.
3108 for (int i = 4; i != 8; ++i)
3109 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3115 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
3116 SmallVector<int, 8> M;
3118 return ::isPSHUFHWMask(M, N->getValueType(0));
3121 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3122 /// is suitable for input to PSHUFLW.
3123 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3124 if (VT != MVT::v8i16)
3127 // Upper quadword copied in order.
3128 for (int i = 4; i != 8; ++i)
3129 if (Mask[i] >= 0 && Mask[i] != i)
3132 // Lower quadword shuffled.
3133 for (int i = 0; i != 4; ++i)
3140 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
3141 SmallVector<int, 8> M;
3143 return ::isPSHUFLWMask(M, N->getValueType(0));
3146 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3147 /// is suitable for input to PALIGNR.
3148 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
3150 int i, e = VT.getVectorNumElements();
3151 if (VT.getSizeInBits() != 128 && VT.getSizeInBits() != 64)
3154 // Do not handle v2i64 / v2f64 shuffles with palignr.
3155 if (e < 4 || !hasSSSE3)
3158 for (i = 0; i != e; ++i)
3162 // All undef, not a palignr.
3166 // Make sure we're shifting in the right direction.
3170 int s = Mask[i] - i;
3172 // Check the rest of the elements to see if they are consecutive.
3173 for (++i; i != e; ++i) {
3175 if (m >= 0 && m != s+i)
3181 /// isVSHUFPSYMask - Return true if the specified VECTOR_SHUFFLE operand
3182 /// specifies a shuffle of elements that is suitable for input to 256-bit
3184 static bool isVSHUFPSYMask(const SmallVectorImpl<int> &Mask, EVT VT,
3185 const X86Subtarget *Subtarget) {
3186 int NumElems = VT.getVectorNumElements();
3188 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256)
3194 // VSHUFPSY divides the resulting vector into 4 chunks.
3195 // The sources are also splitted into 4 chunks, and each destination
3196 // chunk must come from a different source chunk.
3198 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3199 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3201 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3202 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3204 int QuarterSize = NumElems/4;
3205 int HalfSize = QuarterSize*2;
3206 for (int i = 0; i < QuarterSize; ++i)
3207 if (!isUndefOrInRange(Mask[i], 0, HalfSize))
3209 for (int i = QuarterSize; i < QuarterSize*2; ++i)
3210 if (!isUndefOrInRange(Mask[i], NumElems, NumElems+HalfSize))
3213 // The mask of the second half must be the same as the first but with
3214 // the appropriate offsets. This works in the same way as VPERMILPS
3215 // works with masks.
3216 for (int i = QuarterSize*2; i < QuarterSize*3; ++i) {
3217 if (!isUndefOrInRange(Mask[i], HalfSize, NumElems))
3219 int FstHalfIdx = i-HalfSize;
3220 if (Mask[FstHalfIdx] < 0)
3222 if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize))
3225 for (int i = QuarterSize*3; i < NumElems; ++i) {
3226 if (!isUndefOrInRange(Mask[i], NumElems+HalfSize, NumElems*2))
3228 int FstHalfIdx = i-HalfSize;
3229 if (Mask[FstHalfIdx] < 0)
3231 if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize))
3239 /// getShuffleVSHUFPSYImmediate - Return the appropriate immediate to shuffle
3240 /// the specified VECTOR_MASK mask with VSHUFPSY instruction.
3241 static unsigned getShuffleVSHUFPSYImmediate(SDNode *N) {
3242 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3243 EVT VT = SVOp->getValueType(0);
3244 int NumElems = VT.getVectorNumElements();
3246 assert(NumElems == 8 && VT.getSizeInBits() == 256 &&
3247 "Only supports v8i32 and v8f32 types");
3249 int HalfSize = NumElems/2;
3251 for (int i = 0; i != NumElems ; ++i) {
3252 if (SVOp->getMaskElt(i) < 0)
3254 // The mask of the first half must be equal to the second one.
3255 unsigned Shamt = (i%HalfSize)*2;
3256 unsigned Elt = SVOp->getMaskElt(i) % HalfSize;
3257 Mask |= Elt << Shamt;
3263 /// isVSHUFPDYMask - Return true if the specified VECTOR_SHUFFLE operand
3264 /// specifies a shuffle of elements that is suitable for input to 256-bit
3265 /// VSHUFPDY. This shuffle doesn't have the same restriction as the PS
3266 /// version and the mask of the second half isn't binded with the first
3268 static bool isVSHUFPDYMask(const SmallVectorImpl<int> &Mask, EVT VT,
3269 const X86Subtarget *Subtarget) {
3270 int NumElems = VT.getVectorNumElements();
3272 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256)
3278 // VSHUFPSY divides the resulting vector into 4 chunks.
3279 // The sources are also splitted into 4 chunks, and each destination
3280 // chunk must come from a different source chunk.
3282 // SRC1 => X3 X2 X1 X0
3283 // SRC2 => Y3 Y2 Y1 Y0
3285 // DST => Y2..Y3, X2..X3, Y1..Y0, X1..X0
3287 int QuarterSize = NumElems/4;
3288 int HalfSize = QuarterSize*2;
3289 for (int i = 0; i < QuarterSize; ++i)
3290 if (!isUndefOrInRange(Mask[i], 0, HalfSize))
3292 for (int i = QuarterSize; i < QuarterSize*2; ++i)
3293 if (!isUndefOrInRange(Mask[i], NumElems, NumElems+HalfSize))
3295 for (int i = QuarterSize*2; i < QuarterSize*3; ++i)
3296 if (!isUndefOrInRange(Mask[i], HalfSize, NumElems))
3298 for (int i = QuarterSize*3; i < NumElems; ++i)
3299 if (!isUndefOrInRange(Mask[i], NumElems+HalfSize, NumElems*2))
3305 /// getShuffleVSHUFPDYImmediate - Return the appropriate immediate to shuffle
3306 /// the specified VECTOR_MASK mask with VSHUFPDY instruction.
3307 static unsigned getShuffleVSHUFPDYImmediate(SDNode *N) {
3308 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3309 EVT VT = SVOp->getValueType(0);
3310 int NumElems = VT.getVectorNumElements();
3312 assert(NumElems == 4 && VT.getSizeInBits() == 256 &&
3313 "Only supports v4i64 and v4f64 types");
3315 int HalfSize = NumElems/2;
3317 for (int i = 0; i != NumElems ; ++i) {
3318 if (SVOp->getMaskElt(i) < 0)
3320 int Elt = SVOp->getMaskElt(i) % HalfSize;
3327 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3328 /// specifies a shuffle of elements that is suitable for input to 128-bit
3329 /// SHUFPS and SHUFPD.
3330 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3331 int NumElems = VT.getVectorNumElements();
3333 if (VT.getSizeInBits() != 128)
3336 if (NumElems != 2 && NumElems != 4)
3339 int Half = NumElems / 2;
3340 for (int i = 0; i < Half; ++i)
3341 if (!isUndefOrInRange(Mask[i], 0, NumElems))
3343 for (int i = Half; i < NumElems; ++i)
3344 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
3350 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
3351 SmallVector<int, 8> M;
3353 return ::isSHUFPMask(M, N->getValueType(0));
3356 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
3357 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
3358 /// half elements to come from vector 1 (which would equal the dest.) and
3359 /// the upper half to come from vector 2.
3360 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3361 int NumElems = VT.getVectorNumElements();
3363 if (NumElems != 2 && NumElems != 4)
3366 int Half = NumElems / 2;
3367 for (int i = 0; i < Half; ++i)
3368 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
3370 for (int i = Half; i < NumElems; ++i)
3371 if (!isUndefOrInRange(Mask[i], 0, NumElems))
3376 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
3377 SmallVector<int, 8> M;
3379 return isCommutedSHUFPMask(M, N->getValueType(0));
3382 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3383 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3384 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
3385 EVT VT = N->getValueType(0);
3386 unsigned NumElems = VT.getVectorNumElements();
3388 if (VT.getSizeInBits() != 128)
3394 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3395 return isUndefOrEqual(N->getMaskElt(0), 6) &&
3396 isUndefOrEqual(N->getMaskElt(1), 7) &&
3397 isUndefOrEqual(N->getMaskElt(2), 2) &&
3398 isUndefOrEqual(N->getMaskElt(3), 3);
3401 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3402 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3404 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
3405 EVT VT = N->getValueType(0);
3406 unsigned NumElems = VT.getVectorNumElements();
3408 if (VT.getSizeInBits() != 128)
3414 return isUndefOrEqual(N->getMaskElt(0), 2) &&
3415 isUndefOrEqual(N->getMaskElt(1), 3) &&
3416 isUndefOrEqual(N->getMaskElt(2), 2) &&
3417 isUndefOrEqual(N->getMaskElt(3), 3);
3420 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3421 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3422 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
3423 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3425 if (NumElems != 2 && NumElems != 4)
3428 for (unsigned i = 0; i < NumElems/2; ++i)
3429 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
3432 for (unsigned i = NumElems/2; i < NumElems; ++i)
3433 if (!isUndefOrEqual(N->getMaskElt(i), i))
3439 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3440 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3441 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
3442 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3444 if ((NumElems != 2 && NumElems != 4)
3445 || N->getValueType(0).getSizeInBits() > 128)
3448 for (unsigned i = 0; i < NumElems/2; ++i)
3449 if (!isUndefOrEqual(N->getMaskElt(i), i))
3452 for (unsigned i = 0; i < NumElems/2; ++i)
3453 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
3459 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3460 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3461 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3462 bool V2IsSplat = false) {
3463 int NumElts = VT.getVectorNumElements();
3465 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3466 "Unsupported vector type for unpckh");
3468 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8)
3471 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3472 // independently on 128-bit lanes.
3473 unsigned NumLanes = VT.getSizeInBits()/128;
3474 unsigned NumLaneElts = NumElts/NumLanes;
3477 unsigned End = NumLaneElts;
3478 for (unsigned s = 0; s < NumLanes; ++s) {
3479 for (unsigned i = Start, j = s * NumLaneElts;
3483 int BitI1 = Mask[i+1];
3484 if (!isUndefOrEqual(BitI, j))
3487 if (!isUndefOrEqual(BitI1, NumElts))
3490 if (!isUndefOrEqual(BitI1, j + NumElts))
3494 // Process the next 128 bits.
3495 Start += NumLaneElts;
3502 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3503 SmallVector<int, 8> M;
3505 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
3508 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3509 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3510 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
3511 bool V2IsSplat = false) {
3512 int NumElts = VT.getVectorNumElements();
3514 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3515 "Unsupported vector type for unpckh");
3517 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8)
3520 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3521 // independently on 128-bit lanes.
3522 unsigned NumLanes = VT.getSizeInBits()/128;
3523 unsigned NumLaneElts = NumElts/NumLanes;
3526 unsigned End = NumLaneElts;
3527 for (unsigned l = 0; l != NumLanes; ++l) {
3528 for (unsigned i = Start, j = (l*NumLaneElts)+NumLaneElts/2;
3529 i != End; i += 2, ++j) {
3531 int BitI1 = Mask[i+1];
3532 if (!isUndefOrEqual(BitI, j))
3535 if (isUndefOrEqual(BitI1, NumElts))
3538 if (!isUndefOrEqual(BitI1, j+NumElts))
3542 // Process the next 128 bits.
3543 Start += NumLaneElts;
3549 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3550 SmallVector<int, 8> M;
3552 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
3555 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3556 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3558 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3559 int NumElems = VT.getVectorNumElements();
3560 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3563 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3564 // independently on 128-bit lanes.
3565 unsigned NumLanes = VT.getSizeInBits() / 128;
3566 unsigned NumLaneElts = NumElems / NumLanes;
3568 for (unsigned s = 0; s < NumLanes; ++s) {
3569 for (unsigned i = s * NumLaneElts, j = s * NumLaneElts;
3570 i != NumLaneElts * (s + 1);
3573 int BitI1 = Mask[i+1];
3575 if (!isUndefOrEqual(BitI, j))
3577 if (!isUndefOrEqual(BitI1, j))
3585 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
3586 SmallVector<int, 8> M;
3588 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
3591 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3592 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3594 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3595 int NumElems = VT.getVectorNumElements();
3596 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3599 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
3601 int BitI1 = Mask[i+1];
3602 if (!isUndefOrEqual(BitI, j))
3604 if (!isUndefOrEqual(BitI1, j))
3610 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
3611 SmallVector<int, 8> M;
3613 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
3616 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3617 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3618 /// MOVSD, and MOVD, i.e. setting the lowest element.
3619 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3620 if (VT.getVectorElementType().getSizeInBits() < 32)
3623 int NumElts = VT.getVectorNumElements();
3625 if (!isUndefOrEqual(Mask[0], NumElts))
3628 for (int i = 1; i < NumElts; ++i)
3629 if (!isUndefOrEqual(Mask[i], i))
3635 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3636 SmallVector<int, 8> M;
3638 return ::isMOVLMask(M, N->getValueType(0));
3641 /// isVPERM2F128Mask - Match 256-bit shuffles where the elements are considered
3642 /// as permutations between 128-bit chunks or halves. As an example: this
3644 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3645 /// The first half comes from the second half of V1 and the second half from the
3646 /// the second half of V2.
3647 static bool isVPERM2F128Mask(const SmallVectorImpl<int> &Mask, EVT VT,
3648 const X86Subtarget *Subtarget) {
3649 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256)
3652 // The shuffle result is divided into half A and half B. In total the two
3653 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3654 // B must come from C, D, E or F.
3655 int HalfSize = VT.getVectorNumElements()/2;
3656 bool MatchA = false, MatchB = false;
3658 // Check if A comes from one of C, D, E, F.
3659 for (int Half = 0; Half < 4; ++Half) {
3660 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3666 // Check if B comes from one of C, D, E, F.
3667 for (int Half = 0; Half < 4; ++Half) {
3668 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3674 return MatchA && MatchB;
3677 /// getShuffleVPERM2F128Immediate - Return the appropriate immediate to shuffle
3678 /// the specified VECTOR_MASK mask with VPERM2F128 instructions.
3679 static unsigned getShuffleVPERM2F128Immediate(SDNode *N) {
3680 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3681 EVT VT = SVOp->getValueType(0);
3683 int HalfSize = VT.getVectorNumElements()/2;
3685 int FstHalf = 0, SndHalf = 0;
3686 for (int i = 0; i < HalfSize; ++i) {
3687 if (SVOp->getMaskElt(i) > 0) {
3688 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3692 for (int i = HalfSize; i < HalfSize*2; ++i) {
3693 if (SVOp->getMaskElt(i) > 0) {
3694 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3699 return (FstHalf | (SndHalf << 4));
3702 /// isVPERMILPDMask - Return true if the specified VECTOR_SHUFFLE operand
3703 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3704 /// Note that VPERMIL mask matching is different depending whether theunderlying
3705 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3706 /// to the same elements of the low, but to the higher half of the source.
3707 /// In VPERMILPD the two lanes could be shuffled independently of each other
3708 /// with the same restriction that lanes can't be crossed.
3709 static bool isVPERMILPDMask(const SmallVectorImpl<int> &Mask, EVT VT,
3710 const X86Subtarget *Subtarget) {
3711 int NumElts = VT.getVectorNumElements();
3712 int NumLanes = VT.getSizeInBits()/128;
3714 if (!Subtarget->hasAVX())
3717 // Match any permutation of 128-bit vector with 64-bit types
3718 if (NumLanes == 1 && NumElts != 2)
3721 // Only match 256-bit with 32 types
3722 if (VT.getSizeInBits() == 256 && NumElts != 4)
3725 // The mask on the high lane is independent of the low. Both can match
3726 // any element in inside its own lane, but can't cross.
3727 int LaneSize = NumElts/NumLanes;
3728 for (int l = 0; l < NumLanes; ++l)
3729 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) {
3730 int LaneStart = l*LaneSize;
3731 if (!isUndefOrInRange(Mask[i], LaneStart, LaneStart+LaneSize))
3738 /// isVPERMILPSMask - Return true if the specified VECTOR_SHUFFLE operand
3739 /// specifies a shuffle of elements that is suitable for input to VPERMILPS*.
3740 /// Note that VPERMIL mask matching is different depending whether theunderlying
3741 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3742 /// to the same elements of the low, but to the higher half of the source.
3743 /// In VPERMILPD the two lanes could be shuffled independently of each other
3744 /// with the same restriction that lanes can't be crossed.
3745 static bool isVPERMILPSMask(const SmallVectorImpl<int> &Mask, EVT VT,
3746 const X86Subtarget *Subtarget) {
3747 unsigned NumElts = VT.getVectorNumElements();
3748 unsigned NumLanes = VT.getSizeInBits()/128;
3750 if (!Subtarget->hasAVX())
3753 // Match any permutation of 128-bit vector with 32-bit types
3754 if (NumLanes == 1 && NumElts != 4)
3757 // Only match 256-bit with 32 types
3758 if (VT.getSizeInBits() == 256 && NumElts != 8)
3761 // The mask on the high lane should be the same as the low. Actually,
3762 // they can differ if any of the corresponding index in a lane is undef
3763 // and the other stays in range.
3764 int LaneSize = NumElts/NumLanes;
3765 for (int i = 0; i < LaneSize; ++i) {
3766 int HighElt = i+LaneSize;
3767 bool HighValid = isUndefOrInRange(Mask[HighElt], LaneSize, NumElts);
3768 bool LowValid = isUndefOrInRange(Mask[i], 0, LaneSize);
3770 if (!HighValid || !LowValid)
3772 if (Mask[i] < 0 || Mask[HighElt] < 0)
3774 if (Mask[HighElt]-Mask[i] != LaneSize)
3781 /// getShuffleVPERMILPSImmediate - Return the appropriate immediate to shuffle
3782 /// the specified VECTOR_MASK mask with VPERMILPS* instructions.
3783 static unsigned getShuffleVPERMILPSImmediate(SDNode *N) {
3784 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3785 EVT VT = SVOp->getValueType(0);
3787 int NumElts = VT.getVectorNumElements();
3788 int NumLanes = VT.getSizeInBits()/128;
3789 int LaneSize = NumElts/NumLanes;
3791 // Although the mask is equal for both lanes do it twice to get the cases
3792 // where a mask will match because the same mask element is undef on the
3793 // first half but valid on the second. This would get pathological cases
3794 // such as: shuffle <u, 0, 1, 2, 4, 4, 5, 6>, which is completely valid.
3796 for (int l = 0; l < NumLanes; ++l) {
3797 for (int i = 0; i < LaneSize; ++i) {
3798 int MaskElt = SVOp->getMaskElt(i+(l*LaneSize));
3801 if (MaskElt >= LaneSize)
3802 MaskElt -= LaneSize;
3803 Mask |= MaskElt << (i*2);
3810 /// getShuffleVPERMILPDImmediate - Return the appropriate immediate to shuffle
3811 /// the specified VECTOR_MASK mask with VPERMILPD* instructions.
3812 static unsigned getShuffleVPERMILPDImmediate(SDNode *N) {
3813 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3814 EVT VT = SVOp->getValueType(0);
3816 int NumElts = VT.getVectorNumElements();
3817 int NumLanes = VT.getSizeInBits()/128;
3820 int LaneSize = NumElts/NumLanes;
3821 for (int l = 0; l < NumLanes; ++l)
3822 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) {
3823 int MaskElt = SVOp->getMaskElt(i);
3826 Mask |= (MaskElt-l*LaneSize) << i;
3832 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3833 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3834 /// element of vector 2 and the other elements to come from vector 1 in order.
3835 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3836 bool V2IsSplat = false, bool V2IsUndef = false) {
3837 int NumOps = VT.getVectorNumElements();
3838 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3841 if (!isUndefOrEqual(Mask[0], 0))
3844 for (int i = 1; i < NumOps; ++i)
3845 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3846 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3847 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3853 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3854 bool V2IsUndef = false) {
3855 SmallVector<int, 8> M;
3857 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
3860 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3861 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3862 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3863 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N,
3864 const X86Subtarget *Subtarget) {
3865 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX())
3868 // The second vector must be undef
3869 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3872 EVT VT = N->getValueType(0);
3873 unsigned NumElems = VT.getVectorNumElements();
3875 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3876 (VT.getSizeInBits() == 256 && NumElems != 8))
3879 // "i+1" is the value the indexed mask element must have
3880 for (unsigned i = 0; i < NumElems; i += 2)
3881 if (!isUndefOrEqual(N->getMaskElt(i), i+1) ||
3882 !isUndefOrEqual(N->getMaskElt(i+1), i+1))
3888 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3889 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3890 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3891 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N,
3892 const X86Subtarget *Subtarget) {
3893 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX())
3896 // The second vector must be undef
3897 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3900 EVT VT = N->getValueType(0);
3901 unsigned NumElems = VT.getVectorNumElements();
3903 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3904 (VT.getSizeInBits() == 256 && NumElems != 8))
3907 // "i" is the value the indexed mask element must have
3908 for (unsigned i = 0; i < NumElems; i += 2)
3909 if (!isUndefOrEqual(N->getMaskElt(i), i) ||
3910 !isUndefOrEqual(N->getMaskElt(i+1), i))
3916 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3917 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
3918 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3919 int e = N->getValueType(0).getVectorNumElements() / 2;
3921 for (int i = 0; i < e; ++i)
3922 if (!isUndefOrEqual(N->getMaskElt(i), i))
3924 for (int i = 0; i < e; ++i)
3925 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3930 /// isVEXTRACTF128Index - Return true if the specified
3931 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3932 /// suitable for input to VEXTRACTF128.
3933 bool X86::isVEXTRACTF128Index(SDNode *N) {
3934 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3937 // The index should be aligned on a 128-bit boundary.
3939 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3941 unsigned VL = N->getValueType(0).getVectorNumElements();
3942 unsigned VBits = N->getValueType(0).getSizeInBits();
3943 unsigned ElSize = VBits / VL;
3944 bool Result = (Index * ElSize) % 128 == 0;
3949 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3950 /// operand specifies a subvector insert that is suitable for input to
3952 bool X86::isVINSERTF128Index(SDNode *N) {
3953 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3956 // The index should be aligned on a 128-bit boundary.
3958 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3960 unsigned VL = N->getValueType(0).getVectorNumElements();
3961 unsigned VBits = N->getValueType(0).getSizeInBits();
3962 unsigned ElSize = VBits / VL;
3963 bool Result = (Index * ElSize) % 128 == 0;
3968 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3969 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3970 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
3971 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3972 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
3974 unsigned Shift = (NumOperands == 4) ? 2 : 1;
3976 for (int i = 0; i < NumOperands; ++i) {
3977 int Val = SVOp->getMaskElt(NumOperands-i-1);
3978 if (Val < 0) Val = 0;
3979 if (Val >= NumOperands) Val -= NumOperands;
3981 if (i != NumOperands - 1)
3987 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3988 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3989 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3990 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3992 // 8 nodes, but we only care about the last 4.
3993 for (unsigned i = 7; i >= 4; --i) {
3994 int Val = SVOp->getMaskElt(i);
4003 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4004 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4005 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
4006 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
4008 // 8 nodes, but we only care about the first 4.
4009 for (int i = 3; i >= 0; --i) {
4010 int Val = SVOp->getMaskElt(i);
4019 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4020 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4021 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
4022 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
4023 EVT VVT = N->getValueType(0);
4024 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
4028 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
4029 Val = SVOp->getMaskElt(i);
4033 assert(Val - i > 0 && "PALIGNR imm should be positive");
4034 return (Val - i) * EltSize;
4037 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
4038 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4040 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
4041 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4042 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
4045 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4047 EVT VecVT = N->getOperand(0).getValueType();
4048 EVT ElVT = VecVT.getVectorElementType();
4050 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4051 return Index / NumElemsPerChunk;
4054 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
4055 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4057 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
4058 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4059 llvm_unreachable("Illegal insert subvector for VINSERTF128");
4062 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4064 EVT VecVT = N->getValueType(0);
4065 EVT ElVT = VecVT.getVectorElementType();
4067 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4068 return Index / NumElemsPerChunk;
4071 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4073 bool X86::isZeroNode(SDValue Elt) {
4074 return ((isa<ConstantSDNode>(Elt) &&
4075 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4076 (isa<ConstantFPSDNode>(Elt) &&
4077 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4080 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4081 /// their permute mask.
4082 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4083 SelectionDAG &DAG) {
4084 EVT VT = SVOp->getValueType(0);
4085 unsigned NumElems = VT.getVectorNumElements();
4086 SmallVector<int, 8> MaskVec;
4088 for (unsigned i = 0; i != NumElems; ++i) {
4089 int idx = SVOp->getMaskElt(i);
4091 MaskVec.push_back(idx);
4092 else if (idx < (int)NumElems)
4093 MaskVec.push_back(idx + NumElems);
4095 MaskVec.push_back(idx - NumElems);
4097 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4098 SVOp->getOperand(0), &MaskVec[0]);
4101 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4102 /// the two vector operands have swapped position.
4103 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
4104 unsigned NumElems = VT.getVectorNumElements();
4105 for (unsigned i = 0; i != NumElems; ++i) {
4109 else if (idx < (int)NumElems)
4110 Mask[i] = idx + NumElems;
4112 Mask[i] = idx - NumElems;
4116 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4117 /// match movhlps. The lower half elements should come from upper half of
4118 /// V1 (and in order), and the upper half elements should come from the upper
4119 /// half of V2 (and in order).
4120 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
4121 EVT VT = Op->getValueType(0);
4122 if (VT.getSizeInBits() != 128)
4124 if (VT.getVectorNumElements() != 4)
4126 for (unsigned i = 0, e = 2; i != e; ++i)
4127 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
4129 for (unsigned i = 2; i != 4; ++i)
4130 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
4135 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4136 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4138 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4139 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4141 N = N->getOperand(0).getNode();
4142 if (!ISD::isNON_EXTLoad(N))
4145 *LD = cast<LoadSDNode>(N);
4149 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4150 /// match movlp{s|d}. The lower half elements should come from lower half of
4151 /// V1 (and in order), and the upper half elements should come from the upper
4152 /// half of V2 (and in order). And since V1 will become the source of the
4153 /// MOVLP, it must be either a vector load or a scalar load to vector.
4154 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4155 ShuffleVectorSDNode *Op) {
4156 EVT VT = Op->getValueType(0);
4157 if (VT.getSizeInBits() != 128)
4160 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4162 // Is V2 is a vector load, don't do this transformation. We will try to use
4163 // load folding shufps op.
4164 if (ISD::isNON_EXTLoad(V2))
4167 unsigned NumElems = VT.getVectorNumElements();
4169 if (NumElems != 2 && NumElems != 4)
4171 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4172 if (!isUndefOrEqual(Op->getMaskElt(i), i))
4174 for (unsigned i = NumElems/2; i != NumElems; ++i)
4175 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
4180 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4182 static bool isSplatVector(SDNode *N) {
4183 if (N->getOpcode() != ISD::BUILD_VECTOR)
4186 SDValue SplatValue = N->getOperand(0);
4187 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4188 if (N->getOperand(i) != SplatValue)
4193 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4194 /// to an zero vector.
4195 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4196 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4197 SDValue V1 = N->getOperand(0);
4198 SDValue V2 = N->getOperand(1);
4199 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4200 for (unsigned i = 0; i != NumElems; ++i) {
4201 int Idx = N->getMaskElt(i);
4202 if (Idx >= (int)NumElems) {
4203 unsigned Opc = V2.getOpcode();
4204 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4206 if (Opc != ISD::BUILD_VECTOR ||
4207 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4209 } else if (Idx >= 0) {
4210 unsigned Opc = V1.getOpcode();
4211 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4213 if (Opc != ISD::BUILD_VECTOR ||
4214 !X86::isZeroNode(V1.getOperand(Idx)))
4221 /// getZeroVector - Returns a vector of specified type with all zero elements.
4223 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
4225 assert(VT.isVector() && "Expected a vector type");
4227 // Always build SSE zero vectors as <4 x i32> bitcasted
4228 // to their dest type. This ensures they get CSE'd.
4230 if (VT.getSizeInBits() == 128) { // SSE
4231 if (HasSSE2) { // SSE2
4232 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4233 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4235 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4236 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4238 } else if (VT.getSizeInBits() == 256) { // AVX
4239 // 256-bit logic and arithmetic instructions in AVX are
4240 // all floating-point, no support for integer ops. Default
4241 // to emitting fp zeroed vectors then.
4242 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4243 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4244 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4246 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4249 /// getOnesVector - Returns a vector of specified type with all bits set.
4250 /// Always build ones vectors as <4 x i32>. For 256-bit types, use two
4251 /// <4 x i32> inserted in a <8 x i32> appropriately. Then bitcast to their
4252 /// original type, ensuring they get CSE'd.
4253 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
4254 assert(VT.isVector() && "Expected a vector type");
4255 assert((VT.is128BitVector() || VT.is256BitVector())
4256 && "Expected a 128-bit or 256-bit vector type");
4258 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4259 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
4260 Cst, Cst, Cst, Cst);
4262 if (VT.is256BitVector()) {
4263 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32),
4264 Vec, DAG.getConstant(0, MVT::i32), DAG, dl);
4265 Vec = Insert128BitVector(InsV, Vec,
4266 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl);
4269 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4272 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4273 /// that point to V2 points to its first element.
4274 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4275 EVT VT = SVOp->getValueType(0);
4276 unsigned NumElems = VT.getVectorNumElements();
4278 bool Changed = false;
4279 SmallVector<int, 8> MaskVec;
4280 SVOp->getMask(MaskVec);
4282 for (unsigned i = 0; i != NumElems; ++i) {
4283 if (MaskVec[i] > (int)NumElems) {
4284 MaskVec[i] = NumElems;
4289 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
4290 SVOp->getOperand(1), &MaskVec[0]);
4291 return SDValue(SVOp, 0);
4294 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4295 /// operation of specified width.
4296 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4298 unsigned NumElems = VT.getVectorNumElements();
4299 SmallVector<int, 8> Mask;
4300 Mask.push_back(NumElems);
4301 for (unsigned i = 1; i != NumElems; ++i)
4303 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4306 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4307 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4309 unsigned NumElems = VT.getVectorNumElements();
4310 SmallVector<int, 8> Mask;
4311 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4313 Mask.push_back(i + NumElems);
4315 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4318 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4319 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4321 unsigned NumElems = VT.getVectorNumElements();
4322 unsigned Half = NumElems/2;
4323 SmallVector<int, 8> Mask;
4324 for (unsigned i = 0; i != Half; ++i) {
4325 Mask.push_back(i + Half);
4326 Mask.push_back(i + NumElems + Half);
4328 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4331 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4332 // a generic shuffle instruction because the target has no such instructions.
4333 // Generate shuffles which repeat i16 and i8 several times until they can be
4334 // represented by v4f32 and then be manipulated by target suported shuffles.
4335 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4336 EVT VT = V.getValueType();
4337 int NumElems = VT.getVectorNumElements();
4338 DebugLoc dl = V.getDebugLoc();
4340 while (NumElems > 4) {
4341 if (EltNo < NumElems/2) {
4342 V = getUnpackl(DAG, dl, VT, V, V);
4344 V = getUnpackh(DAG, dl, VT, V, V);
4345 EltNo -= NumElems/2;
4352 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4353 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4354 EVT VT = V.getValueType();
4355 DebugLoc dl = V.getDebugLoc();
4356 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256)
4357 && "Vector size not supported");
4359 if (VT.getSizeInBits() == 128) {
4360 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4361 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4362 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4365 // To use VPERMILPS to splat scalars, the second half of indicies must
4366 // refer to the higher part, which is a duplication of the lower one,
4367 // because VPERMILPS can only handle in-lane permutations.
4368 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4369 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4371 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4372 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4376 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4379 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4380 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4381 EVT SrcVT = SV->getValueType(0);
4382 SDValue V1 = SV->getOperand(0);
4383 DebugLoc dl = SV->getDebugLoc();
4385 int EltNo = SV->getSplatIndex();
4386 int NumElems = SrcVT.getVectorNumElements();
4387 unsigned Size = SrcVT.getSizeInBits();
4389 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4390 "Unknown how to promote splat for type");
4392 // Extract the 128-bit part containing the splat element and update
4393 // the splat element index when it refers to the higher register.
4395 unsigned Idx = (EltNo > NumElems/2) ? NumElems/2 : 0;
4396 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl);
4398 EltNo -= NumElems/2;
4401 // All i16 and i8 vector types can't be used directly by a generic shuffle
4402 // instruction because the target has no such instruction. Generate shuffles
4403 // which repeat i16 and i8 several times until they fit in i32, and then can
4404 // be manipulated by target suported shuffles.
4405 EVT EltVT = SrcVT.getVectorElementType();
4406 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4407 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4409 // Recreate the 256-bit vector and place the same 128-bit vector
4410 // into the low and high part. This is necessary because we want
4411 // to use VPERM* to shuffle the vectors
4413 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1,
4414 DAG.getConstant(0, MVT::i32), DAG, dl);
4415 V1 = Insert128BitVector(InsV, V1,
4416 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
4419 return getLegalSplat(DAG, V1, EltNo);
4422 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4423 /// vector of zero or undef vector. This produces a shuffle where the low
4424 /// element of V2 is swizzled into the zero/undef vector, landing at element
4425 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4426 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4427 bool isZero, bool HasSSE2,
4428 SelectionDAG &DAG) {
4429 EVT VT = V2.getValueType();
4431 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4432 unsigned NumElems = VT.getVectorNumElements();
4433 SmallVector<int, 16> MaskVec;
4434 for (unsigned i = 0; i != NumElems; ++i)
4435 // If this is the insertion idx, put the low elt of V2 here.
4436 MaskVec.push_back(i == Idx ? NumElems : i);
4437 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4440 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4441 /// element of the result of the vector shuffle.
4442 static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
4445 return SDValue(); // Limit search depth.
4447 SDValue V = SDValue(N, 0);
4448 EVT VT = V.getValueType();
4449 unsigned Opcode = V.getOpcode();
4451 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4452 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4453 Index = SV->getMaskElt(Index);
4456 return DAG.getUNDEF(VT.getVectorElementType());
4458 int NumElems = VT.getVectorNumElements();
4459 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1);
4460 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
4463 // Recurse into target specific vector shuffles to find scalars.
4464 if (isTargetShuffle(Opcode)) {
4465 int NumElems = VT.getVectorNumElements();
4466 SmallVector<unsigned, 16> ShuffleMask;
4470 case X86ISD::SHUFPS:
4471 case X86ISD::SHUFPD:
4472 ImmN = N->getOperand(N->getNumOperands()-1);
4473 DecodeSHUFPSMask(NumElems,
4474 cast<ConstantSDNode>(ImmN)->getZExtValue(),
4477 case X86ISD::PUNPCKHBW:
4478 case X86ISD::PUNPCKHWD:
4479 case X86ISD::PUNPCKHDQ:
4480 case X86ISD::PUNPCKHQDQ:
4481 DecodePUNPCKHMask(NumElems, ShuffleMask);
4483 case X86ISD::UNPCKHPS:
4484 case X86ISD::UNPCKHPD:
4485 case X86ISD::VUNPCKHPSY:
4486 case X86ISD::VUNPCKHPDY:
4487 DecodeUNPCKHPMask(NumElems, ShuffleMask);
4489 case X86ISD::PUNPCKLBW:
4490 case X86ISD::PUNPCKLWD:
4491 case X86ISD::PUNPCKLDQ:
4492 case X86ISD::PUNPCKLQDQ:
4493 DecodePUNPCKLMask(VT, ShuffleMask);
4495 case X86ISD::UNPCKLPS:
4496 case X86ISD::UNPCKLPD:
4497 case X86ISD::VUNPCKLPSY:
4498 case X86ISD::VUNPCKLPDY:
4499 DecodeUNPCKLPMask(VT, ShuffleMask);
4501 case X86ISD::MOVHLPS:
4502 DecodeMOVHLPSMask(NumElems, ShuffleMask);
4504 case X86ISD::MOVLHPS:
4505 DecodeMOVLHPSMask(NumElems, ShuffleMask);
4507 case X86ISD::PSHUFD:
4508 ImmN = N->getOperand(N->getNumOperands()-1);
4509 DecodePSHUFMask(NumElems,
4510 cast<ConstantSDNode>(ImmN)->getZExtValue(),
4513 case X86ISD::PSHUFHW:
4514 ImmN = N->getOperand(N->getNumOperands()-1);
4515 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4518 case X86ISD::PSHUFLW:
4519 ImmN = N->getOperand(N->getNumOperands()-1);
4520 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4524 case X86ISD::MOVSD: {
4525 // The index 0 always comes from the first element of the second source,
4526 // this is why MOVSS and MOVSD are used in the first place. The other
4527 // elements come from the other positions of the first source vector.
4528 unsigned OpNum = (Index == 0) ? 1 : 0;
4529 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
4532 case X86ISD::VPERMILPS:
4533 ImmN = N->getOperand(N->getNumOperands()-1);
4534 DecodeVPERMILPSMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4537 case X86ISD::VPERMILPSY:
4538 ImmN = N->getOperand(N->getNumOperands()-1);
4539 DecodeVPERMILPSMask(8, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4542 case X86ISD::VPERMILPD:
4543 ImmN = N->getOperand(N->getNumOperands()-1);
4544 DecodeVPERMILPDMask(2, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4547 case X86ISD::VPERMILPDY:
4548 ImmN = N->getOperand(N->getNumOperands()-1);
4549 DecodeVPERMILPDMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4552 case X86ISD::VPERM2F128:
4553 ImmN = N->getOperand(N->getNumOperands()-1);
4554 DecodeVPERM2F128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4558 assert("not implemented for target shuffle node");
4562 Index = ShuffleMask[Index];
4564 return DAG.getUNDEF(VT.getVectorElementType());
4566 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
4567 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
4571 // Actual nodes that may contain scalar elements
4572 if (Opcode == ISD::BITCAST) {
4573 V = V.getOperand(0);
4574 EVT SrcVT = V.getValueType();
4575 unsigned NumElems = VT.getVectorNumElements();
4577 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4581 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4582 return (Index == 0) ? V.getOperand(0)
4583 : DAG.getUNDEF(VT.getVectorElementType());
4585 if (V.getOpcode() == ISD::BUILD_VECTOR)
4586 return V.getOperand(Index);
4591 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4592 /// shuffle operation which come from a consecutively from a zero. The
4593 /// search can start in two different directions, from left or right.
4595 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
4596 bool ZerosFromLeft, SelectionDAG &DAG) {
4599 while (i < NumElems) {
4600 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4601 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
4602 if (!(Elt.getNode() &&
4603 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4611 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
4612 /// MaskE correspond consecutively to elements from one of the vector operands,
4613 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4615 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
4616 int OpIdx, int NumElems, unsigned &OpNum) {
4617 bool SeenV1 = false;
4618 bool SeenV2 = false;
4620 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
4621 int Idx = SVOp->getMaskElt(i);
4622 // Ignore undef indicies
4631 // Only accept consecutive elements from the same vector
4632 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4636 OpNum = SeenV1 ? 0 : 1;
4640 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4641 /// logical left shift of a vector.
4642 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4643 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4644 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4645 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4646 false /* check zeros from right */, DAG);
4652 // Considering the elements in the mask that are not consecutive zeros,
4653 // check if they consecutively come from only one of the source vectors.
4655 // V1 = {X, A, B, C} 0
4657 // vector_shuffle V1, V2 <1, 2, 3, X>
4659 if (!isShuffleMaskConsecutive(SVOp,
4660 0, // Mask Start Index
4661 NumElems-NumZeros-1, // Mask End Index
4662 NumZeros, // Where to start looking in the src vector
4663 NumElems, // Number of elements in vector
4664 OpSrc)) // Which source operand ?
4669 ShVal = SVOp->getOperand(OpSrc);
4673 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4674 /// logical left shift of a vector.
4675 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4676 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4677 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4678 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4679 true /* check zeros from left */, DAG);
4685 // Considering the elements in the mask that are not consecutive zeros,
4686 // check if they consecutively come from only one of the source vectors.
4688 // 0 { A, B, X, X } = V2
4690 // vector_shuffle V1, V2 <X, X, 4, 5>
4692 if (!isShuffleMaskConsecutive(SVOp,
4693 NumZeros, // Mask Start Index
4694 NumElems-1, // Mask End Index
4695 0, // Where to start looking in the src vector
4696 NumElems, // Number of elements in vector
4697 OpSrc)) // Which source operand ?
4702 ShVal = SVOp->getOperand(OpSrc);
4706 /// isVectorShift - Returns true if the shuffle can be implemented as a
4707 /// logical left or right shift of a vector.
4708 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4709 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4710 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4711 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4717 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4719 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4720 unsigned NumNonZero, unsigned NumZero,
4722 const TargetLowering &TLI) {
4726 DebugLoc dl = Op.getDebugLoc();
4729 for (unsigned i = 0; i < 16; ++i) {
4730 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4731 if (ThisIsNonZero && First) {
4733 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4735 V = DAG.getUNDEF(MVT::v8i16);
4740 SDValue ThisElt(0, 0), LastElt(0, 0);
4741 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4742 if (LastIsNonZero) {
4743 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4744 MVT::i16, Op.getOperand(i-1));
4746 if (ThisIsNonZero) {
4747 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4748 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4749 ThisElt, DAG.getConstant(8, MVT::i8));
4751 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4755 if (ThisElt.getNode())
4756 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4757 DAG.getIntPtrConstant(i/2));
4761 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4764 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4766 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4767 unsigned NumNonZero, unsigned NumZero,
4769 const TargetLowering &TLI) {
4773 DebugLoc dl = Op.getDebugLoc();
4776 for (unsigned i = 0; i < 8; ++i) {
4777 bool isNonZero = (NonZeros & (1 << i)) != 0;
4781 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4783 V = DAG.getUNDEF(MVT::v8i16);
4786 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4787 MVT::v8i16, V, Op.getOperand(i),
4788 DAG.getIntPtrConstant(i));
4795 /// getVShift - Return a vector logical shift node.
4797 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4798 unsigned NumBits, SelectionDAG &DAG,
4799 const TargetLowering &TLI, DebugLoc dl) {
4800 EVT ShVT = MVT::v2i64;
4801 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
4802 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4803 return DAG.getNode(ISD::BITCAST, dl, VT,
4804 DAG.getNode(Opc, dl, ShVT, SrcOp,
4805 DAG.getConstant(NumBits,
4806 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4810 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4811 SelectionDAG &DAG) const {
4813 // Check if the scalar load can be widened into a vector load. And if
4814 // the address is "base + cst" see if the cst can be "absorbed" into
4815 // the shuffle mask.
4816 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4817 SDValue Ptr = LD->getBasePtr();
4818 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4820 EVT PVT = LD->getValueType(0);
4821 if (PVT != MVT::i32 && PVT != MVT::f32)
4826 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4827 FI = FINode->getIndex();
4829 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4830 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4831 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4832 Offset = Ptr.getConstantOperandVal(1);
4833 Ptr = Ptr.getOperand(0);
4838 // FIXME: 256-bit vector instructions don't require a strict alignment,
4839 // improve this code to support it better.
4840 unsigned RequiredAlign = VT.getSizeInBits()/8;
4841 SDValue Chain = LD->getChain();
4842 // Make sure the stack object alignment is at least 16 or 32.
4843 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4844 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4845 if (MFI->isFixedObjectIndex(FI)) {
4846 // Can't change the alignment. FIXME: It's possible to compute
4847 // the exact stack offset and reference FI + adjust offset instead.
4848 // If someone *really* cares about this. That's the way to implement it.
4851 MFI->setObjectAlignment(FI, RequiredAlign);
4855 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4856 // Ptr + (Offset & ~15).
4859 if ((Offset % RequiredAlign) & 3)
4861 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4863 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4864 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4866 int EltNo = (Offset - StartOffset) >> 2;
4867 int NumElems = VT.getVectorNumElements();
4869 EVT CanonVT = VT.getSizeInBits() == 128 ? MVT::v4i32 : MVT::v8i32;
4870 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4871 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4872 LD->getPointerInfo().getWithOffset(StartOffset),
4875 // Canonicalize it to a v4i32 or v8i32 shuffle.
4876 SmallVector<int, 8> Mask;
4877 for (int i = 0; i < NumElems; ++i)
4878 Mask.push_back(EltNo);
4880 V1 = DAG.getNode(ISD::BITCAST, dl, CanonVT, V1);
4881 return DAG.getNode(ISD::BITCAST, dl, NVT,
4882 DAG.getVectorShuffle(CanonVT, dl, V1,
4883 DAG.getUNDEF(CanonVT),&Mask[0]));
4889 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4890 /// vector of type 'VT', see if the elements can be replaced by a single large
4891 /// load which has the same value as a build_vector whose operands are 'elts'.
4893 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4895 /// FIXME: we'd also like to handle the case where the last elements are zero
4896 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4897 /// There's even a handy isZeroNode for that purpose.
4898 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4899 DebugLoc &DL, SelectionDAG &DAG) {
4900 EVT EltVT = VT.getVectorElementType();
4901 unsigned NumElems = Elts.size();
4903 LoadSDNode *LDBase = NULL;
4904 unsigned LastLoadedElt = -1U;
4906 // For each element in the initializer, see if we've found a load or an undef.
4907 // If we don't find an initial load element, or later load elements are
4908 // non-consecutive, bail out.
4909 for (unsigned i = 0; i < NumElems; ++i) {
4910 SDValue Elt = Elts[i];
4912 if (!Elt.getNode() ||
4913 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4916 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4918 LDBase = cast<LoadSDNode>(Elt.getNode());
4922 if (Elt.getOpcode() == ISD::UNDEF)
4925 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4926 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4931 // If we have found an entire vector of loads and undefs, then return a large
4932 // load of the entire vector width starting at the base pointer. If we found
4933 // consecutive loads for the low half, generate a vzext_load node.
4934 if (LastLoadedElt == NumElems - 1) {
4935 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4936 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4937 LDBase->getPointerInfo(),
4938 LDBase->isVolatile(), LDBase->isNonTemporal(), 0);
4939 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4940 LDBase->getPointerInfo(),
4941 LDBase->isVolatile(), LDBase->isNonTemporal(),
4942 LDBase->getAlignment());
4943 } else if (NumElems == 4 && LastLoadedElt == 1 &&
4944 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4945 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4946 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4947 SDValue ResNode = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys,
4949 LDBase->getMemOperand());
4950 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4956 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
4957 DebugLoc dl = Op.getDebugLoc();
4959 EVT VT = Op.getValueType();
4960 EVT ExtVT = VT.getVectorElementType();
4961 unsigned NumElems = Op.getNumOperands();
4963 // Vectors containing all zeros can be matched by pxor and xorps later
4964 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
4965 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
4966 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
4967 if (Op.getValueType() == MVT::v4i32 ||
4968 Op.getValueType() == MVT::v8i32)
4971 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
4974 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
4975 // vectors or broken into v4i32 operations on 256-bit vectors.
4976 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
4977 if (Op.getValueType() == MVT::v4i32)
4980 return getOnesVector(Op.getValueType(), DAG, dl);
4983 unsigned EVTBits = ExtVT.getSizeInBits();
4985 unsigned NumZero = 0;
4986 unsigned NumNonZero = 0;
4987 unsigned NonZeros = 0;
4988 bool IsAllConstants = true;
4989 SmallSet<SDValue, 8> Values;
4990 for (unsigned i = 0; i < NumElems; ++i) {
4991 SDValue Elt = Op.getOperand(i);
4992 if (Elt.getOpcode() == ISD::UNDEF)
4995 if (Elt.getOpcode() != ISD::Constant &&
4996 Elt.getOpcode() != ISD::ConstantFP)
4997 IsAllConstants = false;
4998 if (X86::isZeroNode(Elt))
5001 NonZeros |= (1 << i);
5006 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5007 if (NumNonZero == 0)
5008 return DAG.getUNDEF(VT);
5010 // Special case for single non-zero, non-undef, element.
5011 if (NumNonZero == 1) {
5012 unsigned Idx = CountTrailingZeros_32(NonZeros);
5013 SDValue Item = Op.getOperand(Idx);
5015 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5016 // the value are obviously zero, truncate the value to i32 and do the
5017 // insertion that way. Only do this if the value is non-constant or if the
5018 // value is a constant being inserted into element 0. It is cheaper to do
5019 // a constant pool load than it is to do a movd + shuffle.
5020 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5021 (!IsAllConstants || Idx == 0)) {
5022 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5024 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5025 EVT VecVT = MVT::v4i32;
5026 unsigned VecElts = 4;
5028 // Truncate the value (which may itself be a constant) to i32, and
5029 // convert it to a vector with movd (S2V+shuffle to zero extend).
5030 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5031 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5032 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
5033 Subtarget->hasSSE2(), DAG);
5035 // Now we have our 32-bit value zero extended in the low element of
5036 // a vector. If Idx != 0, swizzle it into place.
5038 SmallVector<int, 4> Mask;
5039 Mask.push_back(Idx);
5040 for (unsigned i = 1; i != VecElts; ++i)
5042 Item = DAG.getVectorShuffle(VecVT, dl, Item,
5043 DAG.getUNDEF(Item.getValueType()),
5046 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item);
5050 // If we have a constant or non-constant insertion into the low element of
5051 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5052 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5053 // depending on what the source datatype is.
5056 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5057 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5058 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5059 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5060 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5061 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
5063 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5064 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5065 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5066 EVT MiddleVT = MVT::v4i32;
5067 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
5068 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
5069 Subtarget->hasSSE2(), DAG);
5070 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5074 // Is it a vector logical left shift?
5075 if (NumElems == 2 && Idx == 1 &&
5076 X86::isZeroNode(Op.getOperand(0)) &&
5077 !X86::isZeroNode(Op.getOperand(1))) {
5078 unsigned NumBits = VT.getSizeInBits();
5079 return getVShift(true, VT,
5080 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5081 VT, Op.getOperand(1)),
5082 NumBits/2, DAG, *this, dl);
5085 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5088 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5089 // is a non-constant being inserted into an element other than the low one,
5090 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5091 // movd/movss) to move this into the low element, then shuffle it into
5093 if (EVTBits == 32) {
5094 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5096 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5097 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
5098 Subtarget->hasSSE2(), DAG);
5099 SmallVector<int, 8> MaskVec;
5100 for (unsigned i = 0; i < NumElems; i++)
5101 MaskVec.push_back(i == Idx ? 0 : 1);
5102 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5106 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5107 if (Values.size() == 1) {
5108 if (EVTBits == 32) {
5109 // Instead of a shuffle like this:
5110 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5111 // Check if it's possible to issue this instead.
5112 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5113 unsigned Idx = CountTrailingZeros_32(NonZeros);
5114 SDValue Item = Op.getOperand(Idx);
5115 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5116 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5121 // A vector full of immediates; various special cases are already
5122 // handled, so this is best done with a single constant-pool load.
5126 // For AVX-length vectors, build the individual 128-bit pieces and use
5127 // shuffles to put them in place.
5128 if (VT.getSizeInBits() == 256 && !ISD::isBuildVectorAllZeros(Op.getNode())) {
5129 SmallVector<SDValue, 32> V;
5130 for (unsigned i = 0; i < NumElems; ++i)
5131 V.push_back(Op.getOperand(i));
5133 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5135 // Build both the lower and upper subvector.
5136 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5137 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5140 // Recreate the wider vector with the lower and upper part.
5141 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower,
5142 DAG.getConstant(0, MVT::i32), DAG, dl);
5143 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32),
5147 // Let legalizer expand 2-wide build_vectors.
5148 if (EVTBits == 64) {
5149 if (NumNonZero == 1) {
5150 // One half is zero or undef.
5151 unsigned Idx = CountTrailingZeros_32(NonZeros);
5152 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5153 Op.getOperand(Idx));
5154 return getShuffleVectorZeroOrUndef(V2, Idx, true,
5155 Subtarget->hasSSE2(), DAG);
5160 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5161 if (EVTBits == 8 && NumElems == 16) {
5162 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5164 if (V.getNode()) return V;
5167 if (EVTBits == 16 && NumElems == 8) {
5168 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5170 if (V.getNode()) return V;
5173 // If element VT is == 32 bits, turn it into a number of shuffles.
5174 SmallVector<SDValue, 8> V;
5176 if (NumElems == 4 && NumZero > 0) {
5177 for (unsigned i = 0; i < 4; ++i) {
5178 bool isZero = !(NonZeros & (1 << i));
5180 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
5182 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5185 for (unsigned i = 0; i < 2; ++i) {
5186 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5189 V[i] = V[i*2]; // Must be a zero vector.
5192 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5195 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5198 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5203 SmallVector<int, 8> MaskVec;
5204 bool Reverse = (NonZeros & 0x3) == 2;
5205 for (unsigned i = 0; i < 2; ++i)
5206 MaskVec.push_back(Reverse ? 1-i : i);
5207 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5208 for (unsigned i = 0; i < 2; ++i)
5209 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
5210 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5213 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5214 // Check for a build vector of consecutive loads.
5215 for (unsigned i = 0; i < NumElems; ++i)
5216 V[i] = Op.getOperand(i);
5218 // Check for elements which are consecutive loads.
5219 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5223 // For SSE 4.1, use insertps to put the high elements into the low element.
5224 if (getSubtarget()->hasSSE41()) {
5226 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5227 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5229 Result = DAG.getUNDEF(VT);
5231 for (unsigned i = 1; i < NumElems; ++i) {
5232 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5233 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5234 Op.getOperand(i), DAG.getIntPtrConstant(i));
5239 // Otherwise, expand into a number of unpckl*, start by extending each of
5240 // our (non-undef) elements to the full vector width with the element in the
5241 // bottom slot of the vector (which generates no code for SSE).
5242 for (unsigned i = 0; i < NumElems; ++i) {
5243 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5244 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5246 V[i] = DAG.getUNDEF(VT);
5249 // Next, we iteratively mix elements, e.g. for v4f32:
5250 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5251 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5252 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5253 unsigned EltStride = NumElems >> 1;
5254 while (EltStride != 0) {
5255 for (unsigned i = 0; i < EltStride; ++i) {
5256 // If V[i+EltStride] is undef and this is the first round of mixing,
5257 // then it is safe to just drop this shuffle: V[i] is already in the
5258 // right place, the one element (since it's the first round) being
5259 // inserted as undef can be dropped. This isn't safe for successive
5260 // rounds because they will permute elements within both vectors.
5261 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5262 EltStride == NumElems/2)
5265 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5274 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5275 // them in a MMX register. This is better than doing a stack convert.
5276 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5277 DebugLoc dl = Op.getDebugLoc();
5278 EVT ResVT = Op.getValueType();
5280 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5281 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5283 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5284 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5285 InVec = Op.getOperand(1);
5286 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5287 unsigned NumElts = ResVT.getVectorNumElements();
5288 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5289 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5290 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5292 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5293 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5294 Mask[0] = 0; Mask[1] = 2;
5295 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5297 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5300 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5301 // to create 256-bit vectors from two other 128-bit ones.
5302 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5303 DebugLoc dl = Op.getDebugLoc();
5304 EVT ResVT = Op.getValueType();
5306 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5308 SDValue V1 = Op.getOperand(0);
5309 SDValue V2 = Op.getOperand(1);
5310 unsigned NumElems = ResVT.getVectorNumElements();
5312 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1,
5313 DAG.getConstant(0, MVT::i32), DAG, dl);
5314 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5319 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5320 EVT ResVT = Op.getValueType();
5322 assert(Op.getNumOperands() == 2);
5323 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5324 "Unsupported CONCAT_VECTORS for value type");
5326 // We support concatenate two MMX registers and place them in a MMX register.
5327 // This is better than doing a stack convert.
5328 if (ResVT.is128BitVector())
5329 return LowerMMXCONCAT_VECTORS(Op, DAG);
5331 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5332 // from two other 128-bit ones.
5333 return LowerAVXCONCAT_VECTORS(Op, DAG);
5336 // v8i16 shuffles - Prefer shuffles in the following order:
5337 // 1. [all] pshuflw, pshufhw, optional move
5338 // 2. [ssse3] 1 x pshufb
5339 // 3. [ssse3] 2 x pshufb + 1 x por
5340 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5342 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5343 SelectionDAG &DAG) const {
5344 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5345 SDValue V1 = SVOp->getOperand(0);
5346 SDValue V2 = SVOp->getOperand(1);
5347 DebugLoc dl = SVOp->getDebugLoc();
5348 SmallVector<int, 8> MaskVals;
5350 // Determine if more than 1 of the words in each of the low and high quadwords
5351 // of the result come from the same quadword of one of the two inputs. Undef
5352 // mask values count as coming from any quadword, for better codegen.
5353 SmallVector<unsigned, 4> LoQuad(4);
5354 SmallVector<unsigned, 4> HiQuad(4);
5355 BitVector InputQuads(4);
5356 for (unsigned i = 0; i < 8; ++i) {
5357 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
5358 int EltIdx = SVOp->getMaskElt(i);
5359 MaskVals.push_back(EltIdx);
5368 InputQuads.set(EltIdx / 4);
5371 int BestLoQuad = -1;
5372 unsigned MaxQuad = 1;
5373 for (unsigned i = 0; i < 4; ++i) {
5374 if (LoQuad[i] > MaxQuad) {
5376 MaxQuad = LoQuad[i];
5380 int BestHiQuad = -1;
5382 for (unsigned i = 0; i < 4; ++i) {
5383 if (HiQuad[i] > MaxQuad) {
5385 MaxQuad = HiQuad[i];
5389 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5390 // of the two input vectors, shuffle them into one input vector so only a
5391 // single pshufb instruction is necessary. If There are more than 2 input
5392 // quads, disable the next transformation since it does not help SSSE3.
5393 bool V1Used = InputQuads[0] || InputQuads[1];
5394 bool V2Used = InputQuads[2] || InputQuads[3];
5395 if (Subtarget->hasSSSE3()) {
5396 if (InputQuads.count() == 2 && V1Used && V2Used) {
5397 BestLoQuad = InputQuads.find_first();
5398 BestHiQuad = InputQuads.find_next(BestLoQuad);
5400 if (InputQuads.count() > 2) {
5406 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5407 // the shuffle mask. If a quad is scored as -1, that means that it contains
5408 // words from all 4 input quadwords.
5410 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5411 SmallVector<int, 8> MaskV;
5412 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
5413 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
5414 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5415 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5416 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5417 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5419 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5420 // source words for the shuffle, to aid later transformations.
5421 bool AllWordsInNewV = true;
5422 bool InOrder[2] = { true, true };
5423 for (unsigned i = 0; i != 8; ++i) {
5424 int idx = MaskVals[i];
5426 InOrder[i/4] = false;
5427 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5429 AllWordsInNewV = false;
5433 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5434 if (AllWordsInNewV) {
5435 for (int i = 0; i != 8; ++i) {
5436 int idx = MaskVals[i];
5439 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5440 if ((idx != i) && idx < 4)
5442 if ((idx != i) && idx > 3)
5451 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5452 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5453 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5454 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5455 unsigned TargetMask = 0;
5456 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5457 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5458 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()):
5459 X86::getShufflePSHUFLWImmediate(NewV.getNode());
5460 V1 = NewV.getOperand(0);
5461 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5465 // If we have SSSE3, and all words of the result are from 1 input vector,
5466 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5467 // is present, fall back to case 4.
5468 if (Subtarget->hasSSSE3()) {
5469 SmallVector<SDValue,16> pshufbMask;
5471 // If we have elements from both input vectors, set the high bit of the
5472 // shuffle mask element to zero out elements that come from V2 in the V1
5473 // mask, and elements that come from V1 in the V2 mask, so that the two
5474 // results can be OR'd together.
5475 bool TwoInputs = V1Used && V2Used;
5476 for (unsigned i = 0; i != 8; ++i) {
5477 int EltIdx = MaskVals[i] * 2;
5478 if (TwoInputs && (EltIdx >= 16)) {
5479 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5480 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5483 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5484 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
5486 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5487 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5488 DAG.getNode(ISD::BUILD_VECTOR, dl,
5489 MVT::v16i8, &pshufbMask[0], 16));
5491 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5493 // Calculate the shuffle mask for the second input, shuffle it, and
5494 // OR it with the first shuffled input.
5496 for (unsigned i = 0; i != 8; ++i) {
5497 int EltIdx = MaskVals[i] * 2;
5499 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5500 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5503 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5504 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
5506 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5507 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5508 DAG.getNode(ISD::BUILD_VECTOR, dl,
5509 MVT::v16i8, &pshufbMask[0], 16));
5510 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5511 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5514 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5515 // and update MaskVals with new element order.
5516 BitVector InOrder(8);
5517 if (BestLoQuad >= 0) {
5518 SmallVector<int, 8> MaskV;
5519 for (int i = 0; i != 4; ++i) {
5520 int idx = MaskVals[i];
5522 MaskV.push_back(-1);
5524 } else if ((idx / 4) == BestLoQuad) {
5525 MaskV.push_back(idx & 3);
5528 MaskV.push_back(-1);
5531 for (unsigned i = 4; i != 8; ++i)
5533 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5536 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
5537 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5539 X86::getShufflePSHUFLWImmediate(NewV.getNode()),
5543 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5544 // and update MaskVals with the new element order.
5545 if (BestHiQuad >= 0) {
5546 SmallVector<int, 8> MaskV;
5547 for (unsigned i = 0; i != 4; ++i)
5549 for (unsigned i = 4; i != 8; ++i) {
5550 int idx = MaskVals[i];
5552 MaskV.push_back(-1);
5554 } else if ((idx / 4) == BestHiQuad) {
5555 MaskV.push_back((idx & 3) + 4);
5558 MaskV.push_back(-1);
5561 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5564 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
5565 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5567 X86::getShufflePSHUFHWImmediate(NewV.getNode()),
5571 // In case BestHi & BestLo were both -1, which means each quadword has a word
5572 // from each of the four input quadwords, calculate the InOrder bitvector now
5573 // before falling through to the insert/extract cleanup.
5574 if (BestLoQuad == -1 && BestHiQuad == -1) {
5576 for (int i = 0; i != 8; ++i)
5577 if (MaskVals[i] < 0 || MaskVals[i] == i)
5581 // The other elements are put in the right place using pextrw and pinsrw.
5582 for (unsigned i = 0; i != 8; ++i) {
5585 int EltIdx = MaskVals[i];
5588 SDValue ExtOp = (EltIdx < 8)
5589 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5590 DAG.getIntPtrConstant(EltIdx))
5591 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5592 DAG.getIntPtrConstant(EltIdx - 8));
5593 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5594 DAG.getIntPtrConstant(i));
5599 // v16i8 shuffles - Prefer shuffles in the following order:
5600 // 1. [ssse3] 1 x pshufb
5601 // 2. [ssse3] 2 x pshufb + 1 x por
5602 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5604 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5606 const X86TargetLowering &TLI) {
5607 SDValue V1 = SVOp->getOperand(0);
5608 SDValue V2 = SVOp->getOperand(1);
5609 DebugLoc dl = SVOp->getDebugLoc();
5610 SmallVector<int, 16> MaskVals;
5611 SVOp->getMask(MaskVals);
5613 // If we have SSSE3, case 1 is generated when all result bytes come from
5614 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5615 // present, fall back to case 3.
5616 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5619 for (unsigned i = 0; i < 16; ++i) {
5620 int EltIdx = MaskVals[i];
5629 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5630 if (TLI.getSubtarget()->hasSSSE3()) {
5631 SmallVector<SDValue,16> pshufbMask;
5633 // If all result elements are from one input vector, then only translate
5634 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5636 // Otherwise, we have elements from both input vectors, and must zero out
5637 // elements that come from V2 in the first mask, and V1 in the second mask
5638 // so that we can OR them together.
5639 bool TwoInputs = !(V1Only || V2Only);
5640 for (unsigned i = 0; i != 16; ++i) {
5641 int EltIdx = MaskVals[i];
5642 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5643 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5646 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5648 // If all the elements are from V2, assign it to V1 and return after
5649 // building the first pshufb.
5652 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5653 DAG.getNode(ISD::BUILD_VECTOR, dl,
5654 MVT::v16i8, &pshufbMask[0], 16));
5658 // Calculate the shuffle mask for the second input, shuffle it, and
5659 // OR it with the first shuffled input.
5661 for (unsigned i = 0; i != 16; ++i) {
5662 int EltIdx = MaskVals[i];
5664 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5667 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5669 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5670 DAG.getNode(ISD::BUILD_VECTOR, dl,
5671 MVT::v16i8, &pshufbMask[0], 16));
5672 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5675 // No SSSE3 - Calculate in place words and then fix all out of place words
5676 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5677 // the 16 different words that comprise the two doublequadword input vectors.
5678 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5679 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5680 SDValue NewV = V2Only ? V2 : V1;
5681 for (int i = 0; i != 8; ++i) {
5682 int Elt0 = MaskVals[i*2];
5683 int Elt1 = MaskVals[i*2+1];
5685 // This word of the result is all undef, skip it.
5686 if (Elt0 < 0 && Elt1 < 0)
5689 // This word of the result is already in the correct place, skip it.
5690 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5692 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5695 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5696 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5699 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5700 // using a single extract together, load it and store it.
5701 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5702 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5703 DAG.getIntPtrConstant(Elt1 / 2));
5704 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5705 DAG.getIntPtrConstant(i));
5709 // If Elt1 is defined, extract it from the appropriate source. If the
5710 // source byte is not also odd, shift the extracted word left 8 bits
5711 // otherwise clear the bottom 8 bits if we need to do an or.
5713 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5714 DAG.getIntPtrConstant(Elt1 / 2));
5715 if ((Elt1 & 1) == 0)
5716 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5718 TLI.getShiftAmountTy(InsElt.getValueType())));
5720 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5721 DAG.getConstant(0xFF00, MVT::i16));
5723 // If Elt0 is defined, extract it from the appropriate source. If the
5724 // source byte is not also even, shift the extracted word right 8 bits. If
5725 // Elt1 was also defined, OR the extracted values together before
5726 // inserting them in the result.
5728 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5729 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5730 if ((Elt0 & 1) != 0)
5731 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5733 TLI.getShiftAmountTy(InsElt0.getValueType())));
5735 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5736 DAG.getConstant(0x00FF, MVT::i16));
5737 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5740 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5741 DAG.getIntPtrConstant(i));
5743 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5746 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5747 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5748 /// done when every pair / quad of shuffle mask elements point to elements in
5749 /// the right sequence. e.g.
5750 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5752 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5753 SelectionDAG &DAG, DebugLoc dl) {
5754 EVT VT = SVOp->getValueType(0);
5755 SDValue V1 = SVOp->getOperand(0);
5756 SDValue V2 = SVOp->getOperand(1);
5757 unsigned NumElems = VT.getVectorNumElements();
5758 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5760 switch (VT.getSimpleVT().SimpleTy) {
5761 default: assert(false && "Unexpected!");
5762 case MVT::v4f32: NewVT = MVT::v2f64; break;
5763 case MVT::v4i32: NewVT = MVT::v2i64; break;
5764 case MVT::v8i16: NewVT = MVT::v4i32; break;
5765 case MVT::v16i8: NewVT = MVT::v4i32; break;
5768 int Scale = NumElems / NewWidth;
5769 SmallVector<int, 8> MaskVec;
5770 for (unsigned i = 0; i < NumElems; i += Scale) {
5772 for (int j = 0; j < Scale; ++j) {
5773 int EltIdx = SVOp->getMaskElt(i+j);
5777 StartIdx = EltIdx - (EltIdx % Scale);
5778 if (EltIdx != StartIdx + j)
5782 MaskVec.push_back(-1);
5784 MaskVec.push_back(StartIdx / Scale);
5787 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5788 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5789 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5792 /// getVZextMovL - Return a zero-extending vector move low node.
5794 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5795 SDValue SrcOp, SelectionDAG &DAG,
5796 const X86Subtarget *Subtarget, DebugLoc dl) {
5797 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5798 LoadSDNode *LD = NULL;
5799 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5800 LD = dyn_cast<LoadSDNode>(SrcOp);
5802 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5804 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5805 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5806 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5807 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5808 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5810 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5811 return DAG.getNode(ISD::BITCAST, dl, VT,
5812 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5813 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5821 return DAG.getNode(ISD::BITCAST, dl, VT,
5822 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5823 DAG.getNode(ISD::BITCAST, dl,
5827 /// areShuffleHalvesWithinDisjointLanes - Check whether each half of a vector
5828 /// shuffle node referes to only one lane in the sources.
5829 static bool areShuffleHalvesWithinDisjointLanes(ShuffleVectorSDNode *SVOp) {
5830 EVT VT = SVOp->getValueType(0);
5831 int NumElems = VT.getVectorNumElements();
5832 int HalfSize = NumElems/2;
5833 SmallVector<int, 16> M;
5835 bool MatchA = false, MatchB = false;
5837 for (int l = 0; l < NumElems*2; l += HalfSize) {
5838 if (isUndefOrInRange(M, 0, HalfSize, l, l+HalfSize)) {
5844 for (int l = 0; l < NumElems*2; l += HalfSize) {
5845 if (isUndefOrInRange(M, HalfSize, HalfSize, l, l+HalfSize)) {
5851 return MatchA && MatchB;
5854 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5855 /// which could not be matched by any known target speficic shuffle
5857 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5858 if (areShuffleHalvesWithinDisjointLanes(SVOp)) {
5859 // If each half of a vector shuffle node referes to only one lane in the
5860 // source vectors, extract each used 128-bit lane and shuffle them using
5861 // 128-bit shuffles. Then, concatenate the results. Otherwise leave
5862 // the work to the legalizer.
5863 DebugLoc dl = SVOp->getDebugLoc();
5864 EVT VT = SVOp->getValueType(0);
5865 int NumElems = VT.getVectorNumElements();
5866 int HalfSize = NumElems/2;
5868 // Extract the reference for each half
5869 int FstVecExtractIdx = 0, SndVecExtractIdx = 0;
5870 int FstVecOpNum = 0, SndVecOpNum = 0;
5871 for (int i = 0; i < HalfSize; ++i) {
5872 int Elt = SVOp->getMaskElt(i);
5873 if (SVOp->getMaskElt(i) < 0)
5875 FstVecOpNum = Elt/NumElems;
5876 FstVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
5879 for (int i = HalfSize; i < NumElems; ++i) {
5880 int Elt = SVOp->getMaskElt(i);
5881 if (SVOp->getMaskElt(i) < 0)
5883 SndVecOpNum = Elt/NumElems;
5884 SndVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
5888 // Extract the subvectors
5889 SDValue V1 = Extract128BitVector(SVOp->getOperand(FstVecOpNum),
5890 DAG.getConstant(FstVecExtractIdx, MVT::i32), DAG, dl);
5891 SDValue V2 = Extract128BitVector(SVOp->getOperand(SndVecOpNum),
5892 DAG.getConstant(SndVecExtractIdx, MVT::i32), DAG, dl);
5894 // Generate 128-bit shuffles
5895 SmallVector<int, 16> MaskV1, MaskV2;
5896 for (int i = 0; i < HalfSize; ++i) {
5897 int Elt = SVOp->getMaskElt(i);
5898 MaskV1.push_back(Elt < 0 ? Elt : Elt % HalfSize);
5900 for (int i = HalfSize; i < NumElems; ++i) {
5901 int Elt = SVOp->getMaskElt(i);
5902 MaskV2.push_back(Elt < 0 ? Elt : Elt % HalfSize);
5905 EVT NVT = V1.getValueType();
5906 V1 = DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &MaskV1[0]);
5907 V2 = DAG.getVectorShuffle(NVT, dl, V2, DAG.getUNDEF(NVT), &MaskV2[0]);
5909 // Concatenate the result back
5910 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), V1,
5911 DAG.getConstant(0, MVT::i32), DAG, dl);
5912 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5919 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
5920 /// 4 elements, and match them with several different shuffle types.
5922 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5923 SDValue V1 = SVOp->getOperand(0);
5924 SDValue V2 = SVOp->getOperand(1);
5925 DebugLoc dl = SVOp->getDebugLoc();
5926 EVT VT = SVOp->getValueType(0);
5928 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
5930 SmallVector<std::pair<int, int>, 8> Locs;
5932 SmallVector<int, 8> Mask1(4U, -1);
5933 SmallVector<int, 8> PermMask;
5934 SVOp->getMask(PermMask);
5938 for (unsigned i = 0; i != 4; ++i) {
5939 int Idx = PermMask[i];
5941 Locs[i] = std::make_pair(-1, -1);
5943 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
5945 Locs[i] = std::make_pair(0, NumLo);
5949 Locs[i] = std::make_pair(1, NumHi);
5951 Mask1[2+NumHi] = Idx;
5957 if (NumLo <= 2 && NumHi <= 2) {
5958 // If no more than two elements come from either vector. This can be
5959 // implemented with two shuffles. First shuffle gather the elements.
5960 // The second shuffle, which takes the first shuffle as both of its
5961 // vector operands, put the elements into the right order.
5962 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5964 SmallVector<int, 8> Mask2(4U, -1);
5966 for (unsigned i = 0; i != 4; ++i) {
5967 if (Locs[i].first == -1)
5970 unsigned Idx = (i < 2) ? 0 : 4;
5971 Idx += Locs[i].first * 2 + Locs[i].second;
5976 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
5977 } else if (NumLo == 3 || NumHi == 3) {
5978 // Otherwise, we must have three elements from one vector, call it X, and
5979 // one element from the other, call it Y. First, use a shufps to build an
5980 // intermediate vector with the one element from Y and the element from X
5981 // that will be in the same half in the final destination (the indexes don't
5982 // matter). Then, use a shufps to build the final vector, taking the half
5983 // containing the element from Y from the intermediate, and the other half
5986 // Normalize it so the 3 elements come from V1.
5987 CommuteVectorShuffleMask(PermMask, VT);
5991 // Find the element from V2.
5993 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
5994 int Val = PermMask[HiIndex];
6001 Mask1[0] = PermMask[HiIndex];
6003 Mask1[2] = PermMask[HiIndex^1];
6005 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6008 Mask1[0] = PermMask[0];
6009 Mask1[1] = PermMask[1];
6010 Mask1[2] = HiIndex & 1 ? 6 : 4;
6011 Mask1[3] = HiIndex & 1 ? 4 : 6;
6012 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6014 Mask1[0] = HiIndex & 1 ? 2 : 0;
6015 Mask1[1] = HiIndex & 1 ? 0 : 2;
6016 Mask1[2] = PermMask[2];
6017 Mask1[3] = PermMask[3];
6022 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6026 // Break it into (shuffle shuffle_hi, shuffle_lo).
6029 SmallVector<int,8> LoMask(4U, -1);
6030 SmallVector<int,8> HiMask(4U, -1);
6032 SmallVector<int,8> *MaskPtr = &LoMask;
6033 unsigned MaskIdx = 0;
6036 for (unsigned i = 0; i != 4; ++i) {
6043 int Idx = PermMask[i];
6045 Locs[i] = std::make_pair(-1, -1);
6046 } else if (Idx < 4) {
6047 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6048 (*MaskPtr)[LoIdx] = Idx;
6051 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6052 (*MaskPtr)[HiIdx] = Idx;
6057 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6058 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6059 SmallVector<int, 8> MaskOps;
6060 for (unsigned i = 0; i != 4; ++i) {
6061 if (Locs[i].first == -1) {
6062 MaskOps.push_back(-1);
6064 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
6065 MaskOps.push_back(Idx);
6068 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6071 static bool MayFoldVectorLoad(SDValue V) {
6072 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6073 V = V.getOperand(0);
6074 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6075 V = V.getOperand(0);
6081 // FIXME: the version above should always be used. Since there's
6082 // a bug where several vector shuffles can't be folded because the
6083 // DAG is not updated during lowering and a node claims to have two
6084 // uses while it only has one, use this version, and let isel match
6085 // another instruction if the load really happens to have more than
6086 // one use. Remove this version after this bug get fixed.
6087 // rdar://8434668, PR8156
6088 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6089 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6090 V = V.getOperand(0);
6091 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6092 V = V.getOperand(0);
6093 if (ISD::isNormalLoad(V.getNode()))
6098 /// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by
6099 /// a vector extract, and if both can be later optimized into a single load.
6100 /// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked
6101 /// here because otherwise a target specific shuffle node is going to be
6102 /// emitted for this shuffle, and the optimization not done.
6103 /// FIXME: This is probably not the best approach, but fix the problem
6104 /// until the right path is decided.
6106 bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
6107 const TargetLowering &TLI) {
6108 EVT VT = V.getValueType();
6109 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V);
6111 // Be sure that the vector shuffle is present in a pattern like this:
6112 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr)
6116 SDNode *N = *V.getNode()->use_begin();
6117 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
6120 SDValue EltNo = N->getOperand(1);
6121 if (!isa<ConstantSDNode>(EltNo))
6124 // If the bit convert changed the number of elements, it is unsafe
6125 // to examine the mask.
6126 bool HasShuffleIntoBitcast = false;
6127 if (V.getOpcode() == ISD::BITCAST) {
6128 EVT SrcVT = V.getOperand(0).getValueType();
6129 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
6131 V = V.getOperand(0);
6132 HasShuffleIntoBitcast = true;
6135 // Select the input vector, guarding against out of range extract vector.
6136 unsigned NumElems = VT.getVectorNumElements();
6137 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6138 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
6139 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
6141 // Skip one more bit_convert if necessary
6142 if (V.getOpcode() == ISD::BITCAST)
6143 V = V.getOperand(0);
6145 if (ISD::isNormalLoad(V.getNode())) {
6146 // Is the original load suitable?
6147 LoadSDNode *LN0 = cast<LoadSDNode>(V);
6149 // FIXME: avoid the multi-use bug that is preventing lots of
6150 // of foldings to be detected, this is still wrong of course, but
6151 // give the temporary desired behavior, and if it happens that
6152 // the load has real more uses, during isel it will not fold, and
6153 // will generate poor code.
6154 if (!LN0 || LN0->isVolatile()) // || !LN0->hasOneUse()
6157 if (!HasShuffleIntoBitcast)
6160 // If there's a bitcast before the shuffle, check if the load type and
6161 // alignment is valid.
6162 unsigned Align = LN0->getAlignment();
6164 TLI.getTargetData()->getABITypeAlignment(
6165 VT.getTypeForEVT(*DAG.getContext()));
6167 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
6175 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6176 EVT VT = Op.getValueType();
6178 // Canonizalize to v2f64.
6179 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6180 return DAG.getNode(ISD::BITCAST, dl, VT,
6181 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6186 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6188 SDValue V1 = Op.getOperand(0);
6189 SDValue V2 = Op.getOperand(1);
6190 EVT VT = Op.getValueType();
6192 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6194 if (HasSSE2 && VT == MVT::v2f64)
6195 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6198 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V2, DAG);
6202 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6203 SDValue V1 = Op.getOperand(0);
6204 SDValue V2 = Op.getOperand(1);
6205 EVT VT = Op.getValueType();
6207 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6208 "unsupported shuffle type");
6210 if (V2.getOpcode() == ISD::UNDEF)
6214 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6217 static inline unsigned getSHUFPOpcode(EVT VT) {
6218 switch(VT.getSimpleVT().SimpleTy) {
6219 case MVT::v8i32: // Use fp unit for int unpack.
6221 case MVT::v4i32: // Use fp unit for int unpack.
6222 case MVT::v4f32: return X86ISD::SHUFPS;
6223 case MVT::v4i64: // Use fp unit for int unpack.
6225 case MVT::v2i64: // Use fp unit for int unpack.
6226 case MVT::v2f64: return X86ISD::SHUFPD;
6228 llvm_unreachable("Unknown type for shufp*");
6234 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6235 SDValue V1 = Op.getOperand(0);
6236 SDValue V2 = Op.getOperand(1);
6237 EVT VT = Op.getValueType();
6238 unsigned NumElems = VT.getVectorNumElements();
6240 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6241 // operand of these instructions is only memory, so check if there's a
6242 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6244 bool CanFoldLoad = false;
6246 // Trivial case, when V2 comes from a load.
6247 if (MayFoldVectorLoad(V2))
6250 // When V1 is a load, it can be folded later into a store in isel, example:
6251 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6253 // (MOVLPSmr addr:$src1, VR128:$src2)
6254 // So, recognize this potential and also use MOVLPS or MOVLPD
6255 if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6258 // Both of them can't be memory operations though.
6259 if (MayFoldVectorLoad(V1) && MayFoldVectorLoad(V2))
6260 CanFoldLoad = false;
6263 if (HasSSE2 && NumElems == 2)
6264 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6267 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6270 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6271 // movl and movlp will both match v2i64, but v2i64 is never matched by
6272 // movl earlier because we make it strict to avoid messing with the movlp load
6273 // folding logic (see the code above getMOVLP call). Match it here then,
6274 // this is horrible, but will stay like this until we move all shuffle
6275 // matching to x86 specific nodes. Note that for the 1st condition all
6276 // types are matched with movsd.
6277 if ((HasSSE2 && NumElems == 2) || !X86::isMOVLMask(SVOp))
6278 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6280 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6283 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6285 // Invert the operand order and use SHUFPS to match it.
6286 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V2, V1,
6287 X86::getShuffleSHUFImmediate(SVOp), DAG);
6290 static inline unsigned getUNPCKLOpcode(EVT VT) {
6291 switch(VT.getSimpleVT().SimpleTy) {
6292 case MVT::v4i32: return X86ISD::PUNPCKLDQ;
6293 case MVT::v2i64: return X86ISD::PUNPCKLQDQ;
6294 case MVT::v4f32: return X86ISD::UNPCKLPS;
6295 case MVT::v2f64: return X86ISD::UNPCKLPD;
6296 case MVT::v8i32: // Use fp unit for int unpack.
6297 case MVT::v8f32: return X86ISD::VUNPCKLPSY;
6298 case MVT::v4i64: // Use fp unit for int unpack.
6299 case MVT::v4f64: return X86ISD::VUNPCKLPDY;
6300 case MVT::v16i8: return X86ISD::PUNPCKLBW;
6301 case MVT::v8i16: return X86ISD::PUNPCKLWD;
6303 llvm_unreachable("Unknown type for unpckl");
6308 static inline unsigned getUNPCKHOpcode(EVT VT) {
6309 switch(VT.getSimpleVT().SimpleTy) {
6310 case MVT::v4i32: return X86ISD::PUNPCKHDQ;
6311 case MVT::v2i64: return X86ISD::PUNPCKHQDQ;
6312 case MVT::v4f32: return X86ISD::UNPCKHPS;
6313 case MVT::v2f64: return X86ISD::UNPCKHPD;
6314 case MVT::v8i32: // Use fp unit for int unpack.
6315 case MVT::v8f32: return X86ISD::VUNPCKHPSY;
6316 case MVT::v4i64: // Use fp unit for int unpack.
6317 case MVT::v4f64: return X86ISD::VUNPCKHPDY;
6318 case MVT::v16i8: return X86ISD::PUNPCKHBW;
6319 case MVT::v8i16: return X86ISD::PUNPCKHWD;
6321 llvm_unreachable("Unknown type for unpckh");
6326 static inline unsigned getVPERMILOpcode(EVT VT) {
6327 switch(VT.getSimpleVT().SimpleTy) {
6329 case MVT::v4f32: return X86ISD::VPERMILPS;
6331 case MVT::v2f64: return X86ISD::VPERMILPD;
6333 case MVT::v8f32: return X86ISD::VPERMILPSY;
6335 case MVT::v4f64: return X86ISD::VPERMILPDY;
6337 llvm_unreachable("Unknown type for vpermil");
6342 /// isVectorBroadcast - Check if the node chain is suitable to be xformed to
6343 /// a vbroadcast node. The nodes are suitable whenever we can fold a load coming
6344 /// from a 32 or 64 bit scalar. Update Op to the desired load to be folded.
6345 static bool isVectorBroadcast(SDValue &Op) {
6346 EVT VT = Op.getValueType();
6347 bool Is256 = VT.getSizeInBits() == 256;
6349 assert((VT.getSizeInBits() == 128 || Is256) &&
6350 "Unsupported type for vbroadcast node");
6353 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6354 V = V.getOperand(0);
6356 if (Is256 && !(V.hasOneUse() &&
6357 V.getOpcode() == ISD::INSERT_SUBVECTOR &&
6358 V.getOperand(0).getOpcode() == ISD::UNDEF))
6362 V = V.getOperand(1);
6363 if (V.hasOneUse() && V.getOpcode() != ISD::SCALAR_TO_VECTOR)
6366 // Check the source scalar_to_vector type. 256-bit broadcasts are
6367 // supported for 32/64-bit sizes, while 128-bit ones are only supported
6368 // for 32-bit scalars.
6369 unsigned ScalarSize = V.getOperand(0).getValueType().getSizeInBits();
6370 if (ScalarSize != 32 && ScalarSize != 64)
6372 if (!Is256 && ScalarSize == 64)
6375 V = V.getOperand(0);
6376 if (!MayFoldLoad(V))
6379 // Return the load node
6385 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
6386 const TargetLowering &TLI,
6387 const X86Subtarget *Subtarget) {
6388 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6389 EVT VT = Op.getValueType();
6390 DebugLoc dl = Op.getDebugLoc();
6391 SDValue V1 = Op.getOperand(0);
6392 SDValue V2 = Op.getOperand(1);
6394 if (isZeroShuffle(SVOp))
6395 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
6397 // Handle splat operations
6398 if (SVOp->isSplat()) {
6399 unsigned NumElem = VT.getVectorNumElements();
6400 int Size = VT.getSizeInBits();
6401 // Special case, this is the only place now where it's allowed to return
6402 // a vector_shuffle operation without using a target specific node, because
6403 // *hopefully* it will be optimized away by the dag combiner. FIXME: should
6404 // this be moved to DAGCombine instead?
6405 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
6408 // Use vbroadcast whenever the splat comes from a foldable load
6409 if (Subtarget->hasAVX() && isVectorBroadcast(V1))
6410 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, V1);
6412 // Handle splats by matching through known shuffle masks
6413 if ((Size == 128 && NumElem <= 4) ||
6414 (Size == 256 && NumElem < 8))
6417 // All remaning splats are promoted to target supported vector shuffles.
6418 return PromoteSplat(SVOp, DAG);
6421 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6423 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
6424 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6425 if (NewOp.getNode())
6426 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6427 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6428 // FIXME: Figure out a cleaner way to do this.
6429 // Try to make use of movq to zero out the top part.
6430 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6431 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6432 if (NewOp.getNode()) {
6433 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
6434 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
6435 DAG, Subtarget, dl);
6437 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6438 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6439 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
6440 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
6441 DAG, Subtarget, dl);
6448 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6449 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6450 SDValue V1 = Op.getOperand(0);
6451 SDValue V2 = Op.getOperand(1);
6452 EVT VT = Op.getValueType();
6453 DebugLoc dl = Op.getDebugLoc();
6454 unsigned NumElems = VT.getVectorNumElements();
6455 bool isMMX = VT.getSizeInBits() == 64;
6456 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6457 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6458 bool V1IsSplat = false;
6459 bool V2IsSplat = false;
6460 bool HasSSE2 = Subtarget->hasSSE2() || Subtarget->hasAVX();
6461 bool HasSSE3 = Subtarget->hasSSE3() || Subtarget->hasAVX();
6462 bool HasSSSE3 = Subtarget->hasSSSE3() || Subtarget->hasAVX();
6463 MachineFunction &MF = DAG.getMachineFunction();
6464 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6466 // Shuffle operations on MMX not supported.
6470 // Vector shuffle lowering takes 3 steps:
6472 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6473 // narrowing and commutation of operands should be handled.
6474 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6476 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6477 // so the shuffle can be broken into other shuffles and the legalizer can
6478 // try the lowering again.
6480 // The general ideia is that no vector_shuffle operation should be left to
6481 // be matched during isel, all of them must be converted to a target specific
6484 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6485 // narrowing and commutation of operands should be handled. The actual code
6486 // doesn't include all of those, work in progress...
6487 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
6488 if (NewOp.getNode())
6491 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6492 // unpckh_undef). Only use pshufd if speed is more important than size.
6493 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp))
6494 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
6495 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp))
6496 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6498 if (X86::isMOVDDUPMask(SVOp) && HasSSE3 && V2IsUndef &&
6499 RelaxedMayFoldVectorLoad(V1))
6500 return getMOVDDup(Op, dl, V1, DAG);
6502 if (X86::isMOVHLPS_v_undef_Mask(SVOp))
6503 return getMOVHighToLow(Op, dl, DAG);
6505 // Use to match splats
6506 if (HasSSE2 && X86::isUNPCKHMask(SVOp) && V2IsUndef &&
6507 (VT == MVT::v2f64 || VT == MVT::v2i64))
6508 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6510 if (X86::isPSHUFDMask(SVOp)) {
6511 // The actual implementation will match the mask in the if above and then
6512 // during isel it can match several different instructions, not only pshufd
6513 // as its name says, sad but true, emulate the behavior for now...
6514 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6515 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6517 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
6519 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6520 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6522 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V1,
6526 // Check if this can be converted into a logical shift.
6527 bool isLeft = false;
6530 bool isShift = getSubtarget()->hasSSE2() &&
6531 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6532 if (isShift && ShVal.hasOneUse()) {
6533 // If the shifted value has multiple uses, it may be cheaper to use
6534 // v_set0 + movlhps or movhlps, etc.
6535 EVT EltVT = VT.getVectorElementType();
6536 ShAmt *= EltVT.getSizeInBits();
6537 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6540 if (X86::isMOVLMask(SVOp)) {
6543 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6544 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6545 if (!X86::isMOVLPMask(SVOp)) {
6546 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6547 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6549 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6550 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6554 // FIXME: fold these into legal mask.
6555 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp))
6556 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6558 if (X86::isMOVHLPSMask(SVOp))
6559 return getMOVHighToLow(Op, dl, DAG);
6561 if (X86::isMOVSHDUPMask(SVOp, Subtarget))
6562 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6564 if (X86::isMOVSLDUPMask(SVOp, Subtarget))
6565 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6567 if (X86::isMOVLPMask(SVOp))
6568 return getMOVLP(Op, dl, DAG, HasSSE2);
6570 if (ShouldXformToMOVHLPS(SVOp) ||
6571 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
6572 return CommuteVectorShuffle(SVOp, DAG);
6575 // No better options. Use a vshl / vsrl.
6576 EVT EltVT = VT.getVectorElementType();
6577 ShAmt *= EltVT.getSizeInBits();
6578 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6581 bool Commuted = false;
6582 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6583 // 1,1,1,1 -> v8i16 though.
6584 V1IsSplat = isSplatVector(V1.getNode());
6585 V2IsSplat = isSplatVector(V2.getNode());
6587 // Canonicalize the splat or undef, if present, to be on the RHS.
6588 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
6589 Op = CommuteVectorShuffle(SVOp, DAG);
6590 SVOp = cast<ShuffleVectorSDNode>(Op);
6591 V1 = SVOp->getOperand(0);
6592 V2 = SVOp->getOperand(1);
6593 std::swap(V1IsSplat, V2IsSplat);
6594 std::swap(V1IsUndef, V2IsUndef);
6598 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
6599 // Shuffling low element of v1 into undef, just return v1.
6602 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6603 // the instruction selector will not match, so get a canonical MOVL with
6604 // swapped operands to undo the commute.
6605 return getMOVL(DAG, dl, VT, V2, V1);
6608 if (X86::isUNPCKLMask(SVOp))
6609 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG);
6611 if (X86::isUNPCKHMask(SVOp))
6612 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V2, DAG);
6615 // Normalize mask so all entries that point to V2 points to its first
6616 // element then try to match unpck{h|l} again. If match, return a
6617 // new vector_shuffle with the corrected mask.
6618 SDValue NewMask = NormalizeMask(SVOp, DAG);
6619 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
6620 if (NSVOp != SVOp) {
6621 if (X86::isUNPCKLMask(NSVOp, true)) {
6623 } else if (X86::isUNPCKHMask(NSVOp, true)) {
6630 // Commute is back and try unpck* again.
6631 // FIXME: this seems wrong.
6632 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
6633 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
6635 if (X86::isUNPCKLMask(NewSVOp))
6636 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG);
6638 if (X86::isUNPCKHMask(NewSVOp))
6639 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V2, V1, DAG);
6642 // Normalize the node to match x86 shuffle ops if needed
6643 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
6644 return CommuteVectorShuffle(SVOp, DAG);
6646 // The checks below are all present in isShuffleMaskLegal, but they are
6647 // inlined here right now to enable us to directly emit target specific
6648 // nodes, and remove one by one until they don't return Op anymore.
6649 SmallVector<int, 16> M;
6652 if (isPALIGNRMask(M, VT, HasSSSE3))
6653 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6654 X86::getShufflePALIGNRImmediate(SVOp),
6657 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6658 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6659 if (VT == MVT::v2f64)
6660 return getTargetShuffleNode(X86ISD::UNPCKLPD, dl, VT, V1, V1, DAG);
6661 if (VT == MVT::v2i64)
6662 return getTargetShuffleNode(X86ISD::PUNPCKLQDQ, dl, VT, V1, V1, DAG);
6665 if (isPSHUFHWMask(M, VT))
6666 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6667 X86::getShufflePSHUFHWImmediate(SVOp),
6670 if (isPSHUFLWMask(M, VT))
6671 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6672 X86::getShufflePSHUFLWImmediate(SVOp),
6675 if (isSHUFPMask(M, VT))
6676 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2,
6677 X86::getShuffleSHUFImmediate(SVOp), DAG);
6679 if (X86::isUNPCKL_v_undef_Mask(SVOp))
6680 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
6681 if (X86::isUNPCKH_v_undef_Mask(SVOp))
6682 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6684 //===--------------------------------------------------------------------===//
6685 // Generate target specific nodes for 128 or 256-bit shuffles only
6686 // supported in the AVX instruction set.
6689 // Handle VPERMILPS* permutations
6690 if (isVPERMILPSMask(M, VT, Subtarget))
6691 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1,
6692 getShuffleVPERMILPSImmediate(SVOp), DAG);
6694 // Handle VPERMILPD* permutations
6695 if (isVPERMILPDMask(M, VT, Subtarget))
6696 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1,
6697 getShuffleVPERMILPDImmediate(SVOp), DAG);
6699 // Handle VPERM2F128 permutations
6700 if (isVPERM2F128Mask(M, VT, Subtarget))
6701 return getTargetShuffleNode(X86ISD::VPERM2F128, dl, VT, V1, V2,
6702 getShuffleVPERM2F128Immediate(SVOp), DAG);
6704 // Handle VSHUFPSY permutations
6705 if (isVSHUFPSYMask(M, VT, Subtarget))
6706 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2,
6707 getShuffleVSHUFPSYImmediate(SVOp), DAG);
6709 // Handle VSHUFPDY permutations
6710 if (isVSHUFPDYMask(M, VT, Subtarget))
6711 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2,
6712 getShuffleVSHUFPDYImmediate(SVOp), DAG);
6714 //===--------------------------------------------------------------------===//
6715 // Since no target specific shuffle was selected for this generic one,
6716 // lower it into other known shuffles. FIXME: this isn't true yet, but
6717 // this is the plan.
6720 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6721 if (VT == MVT::v8i16) {
6722 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6723 if (NewOp.getNode())
6727 if (VT == MVT::v16i8) {
6728 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6729 if (NewOp.getNode())
6733 // Handle all 128-bit wide vectors with 4 elements, and match them with
6734 // several different shuffle types.
6735 if (NumElems == 4 && VT.getSizeInBits() == 128)
6736 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6738 // Handle general 256-bit shuffles
6739 if (VT.is256BitVector())
6740 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6746 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6747 SelectionDAG &DAG) const {
6748 EVT VT = Op.getValueType();
6749 DebugLoc dl = Op.getDebugLoc();
6751 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6754 if (VT.getSizeInBits() == 8) {
6755 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6756 Op.getOperand(0), Op.getOperand(1));
6757 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6758 DAG.getValueType(VT));
6759 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6760 } else if (VT.getSizeInBits() == 16) {
6761 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6762 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6764 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6765 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6766 DAG.getNode(ISD::BITCAST, dl,
6770 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6771 Op.getOperand(0), Op.getOperand(1));
6772 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6773 DAG.getValueType(VT));
6774 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6775 } else if (VT == MVT::f32) {
6776 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6777 // the result back to FR32 register. It's only worth matching if the
6778 // result has a single use which is a store or a bitcast to i32. And in
6779 // the case of a store, it's not worth it if the index is a constant 0,
6780 // because a MOVSSmr can be used instead, which is smaller and faster.
6781 if (!Op.hasOneUse())
6783 SDNode *User = *Op.getNode()->use_begin();
6784 if ((User->getOpcode() != ISD::STORE ||
6785 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6786 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6787 (User->getOpcode() != ISD::BITCAST ||
6788 User->getValueType(0) != MVT::i32))
6790 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6791 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6794 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6795 } else if (VT == MVT::i32) {
6796 // ExtractPS works with constant index.
6797 if (isa<ConstantSDNode>(Op.getOperand(1)))
6805 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6806 SelectionDAG &DAG) const {
6807 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6810 SDValue Vec = Op.getOperand(0);
6811 EVT VecVT = Vec.getValueType();
6813 // If this is a 256-bit vector result, first extract the 128-bit vector and
6814 // then extract the element from the 128-bit vector.
6815 if (VecVT.getSizeInBits() == 256) {
6816 DebugLoc dl = Op.getNode()->getDebugLoc();
6817 unsigned NumElems = VecVT.getVectorNumElements();
6818 SDValue Idx = Op.getOperand(1);
6819 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6821 // Get the 128-bit vector.
6822 bool Upper = IdxVal >= NumElems/2;
6823 Vec = Extract128BitVector(Vec,
6824 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl);
6826 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6827 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx);
6830 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6832 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) {
6833 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6838 EVT VT = Op.getValueType();
6839 DebugLoc dl = Op.getDebugLoc();
6840 // TODO: handle v16i8.
6841 if (VT.getSizeInBits() == 16) {
6842 SDValue Vec = Op.getOperand(0);
6843 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6845 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6846 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6847 DAG.getNode(ISD::BITCAST, dl,
6850 // Transform it so it match pextrw which produces a 32-bit result.
6851 EVT EltVT = MVT::i32;
6852 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6853 Op.getOperand(0), Op.getOperand(1));
6854 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6855 DAG.getValueType(VT));
6856 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6857 } else if (VT.getSizeInBits() == 32) {
6858 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6862 // SHUFPS the element to the lowest double word, then movss.
6863 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6864 EVT VVT = Op.getOperand(0).getValueType();
6865 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6866 DAG.getUNDEF(VVT), Mask);
6867 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6868 DAG.getIntPtrConstant(0));
6869 } else if (VT.getSizeInBits() == 64) {
6870 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6871 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6872 // to match extract_elt for f64.
6873 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6877 // UNPCKHPD the element to the lowest double word, then movsd.
6878 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6879 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6880 int Mask[2] = { 1, -1 };
6881 EVT VVT = Op.getOperand(0).getValueType();
6882 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6883 DAG.getUNDEF(VVT), Mask);
6884 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6885 DAG.getIntPtrConstant(0));
6892 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6893 SelectionDAG &DAG) const {
6894 EVT VT = Op.getValueType();
6895 EVT EltVT = VT.getVectorElementType();
6896 DebugLoc dl = Op.getDebugLoc();
6898 SDValue N0 = Op.getOperand(0);
6899 SDValue N1 = Op.getOperand(1);
6900 SDValue N2 = Op.getOperand(2);
6902 if (VT.getSizeInBits() == 256)
6905 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6906 isa<ConstantSDNode>(N2)) {
6908 if (VT == MVT::v8i16)
6909 Opc = X86ISD::PINSRW;
6910 else if (VT == MVT::v16i8)
6911 Opc = X86ISD::PINSRB;
6913 Opc = X86ISD::PINSRB;
6915 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6917 if (N1.getValueType() != MVT::i32)
6918 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6919 if (N2.getValueType() != MVT::i32)
6920 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6921 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6922 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6923 // Bits [7:6] of the constant are the source select. This will always be
6924 // zero here. The DAG Combiner may combine an extract_elt index into these
6925 // bits. For example (insert (extract, 3), 2) could be matched by putting
6926 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6927 // Bits [5:4] of the constant are the destination select. This is the
6928 // value of the incoming immediate.
6929 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6930 // combine either bitwise AND or insert of float 0.0 to set these bits.
6931 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6932 // Create this as a scalar to vector..
6933 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6934 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6935 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
6936 // PINSR* works with constant index.
6943 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
6944 EVT VT = Op.getValueType();
6945 EVT EltVT = VT.getVectorElementType();
6947 DebugLoc dl = Op.getDebugLoc();
6948 SDValue N0 = Op.getOperand(0);
6949 SDValue N1 = Op.getOperand(1);
6950 SDValue N2 = Op.getOperand(2);
6952 // If this is a 256-bit vector result, first extract the 128-bit vector,
6953 // insert the element into the extracted half and then place it back.
6954 if (VT.getSizeInBits() == 256) {
6955 if (!isa<ConstantSDNode>(N2))
6958 // Get the desired 128-bit vector half.
6959 unsigned NumElems = VT.getVectorNumElements();
6960 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
6961 bool Upper = IdxVal >= NumElems/2;
6962 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32);
6963 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl);
6965 // Insert the element into the desired half.
6966 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V,
6967 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2);
6969 // Insert the changed part back to the 256-bit vector
6970 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl);
6973 if (Subtarget->hasSSE41() || Subtarget->hasAVX())
6974 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
6976 if (EltVT == MVT::i8)
6979 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
6980 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
6981 // as its second argument.
6982 if (N1.getValueType() != MVT::i32)
6983 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6984 if (N2.getValueType() != MVT::i32)
6985 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6986 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
6992 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6993 LLVMContext *Context = DAG.getContext();
6994 DebugLoc dl = Op.getDebugLoc();
6995 EVT OpVT = Op.getValueType();
6997 // If this is a 256-bit vector result, first insert into a 128-bit
6998 // vector and then insert into the 256-bit vector.
6999 if (OpVT.getSizeInBits() > 128) {
7000 // Insert into a 128-bit vector.
7001 EVT VT128 = EVT::getVectorVT(*Context,
7002 OpVT.getVectorElementType(),
7003 OpVT.getVectorNumElements() / 2);
7005 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7007 // Insert the 128-bit vector.
7008 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op,
7009 DAG.getConstant(0, MVT::i32),
7013 if (Op.getValueType() == MVT::v1i64 &&
7014 Op.getOperand(0).getValueType() == MVT::i64)
7015 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7017 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7018 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
7019 "Expected an SSE type!");
7020 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
7021 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7024 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7025 // a simple subregister reference or explicit instructions to grab
7026 // upper bits of a vector.
7028 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7029 if (Subtarget->hasAVX()) {
7030 DebugLoc dl = Op.getNode()->getDebugLoc();
7031 SDValue Vec = Op.getNode()->getOperand(0);
7032 SDValue Idx = Op.getNode()->getOperand(1);
7034 if (Op.getNode()->getValueType(0).getSizeInBits() == 128
7035 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) {
7036 return Extract128BitVector(Vec, Idx, DAG, dl);
7042 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7043 // simple superregister reference or explicit instructions to insert
7044 // the upper bits of a vector.
7046 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7047 if (Subtarget->hasAVX()) {
7048 DebugLoc dl = Op.getNode()->getDebugLoc();
7049 SDValue Vec = Op.getNode()->getOperand(0);
7050 SDValue SubVec = Op.getNode()->getOperand(1);
7051 SDValue Idx = Op.getNode()->getOperand(2);
7053 if (Op.getNode()->getValueType(0).getSizeInBits() == 256
7054 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) {
7055 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl);
7061 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7062 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7063 // one of the above mentioned nodes. It has to be wrapped because otherwise
7064 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7065 // be used to form addressing mode. These wrapped nodes will be selected
7068 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7069 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7071 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7073 unsigned char OpFlag = 0;
7074 unsigned WrapperKind = X86ISD::Wrapper;
7075 CodeModel::Model M = getTargetMachine().getCodeModel();
7077 if (Subtarget->isPICStyleRIPRel() &&
7078 (M == CodeModel::Small || M == CodeModel::Kernel))
7079 WrapperKind = X86ISD::WrapperRIP;
7080 else if (Subtarget->isPICStyleGOT())
7081 OpFlag = X86II::MO_GOTOFF;
7082 else if (Subtarget->isPICStyleStubPIC())
7083 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7085 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7087 CP->getOffset(), OpFlag);
7088 DebugLoc DL = CP->getDebugLoc();
7089 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7090 // With PIC, the address is actually $g + Offset.
7092 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7093 DAG.getNode(X86ISD::GlobalBaseReg,
7094 DebugLoc(), getPointerTy()),
7101 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7102 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7104 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7106 unsigned char OpFlag = 0;
7107 unsigned WrapperKind = X86ISD::Wrapper;
7108 CodeModel::Model M = getTargetMachine().getCodeModel();
7110 if (Subtarget->isPICStyleRIPRel() &&
7111 (M == CodeModel::Small || M == CodeModel::Kernel))
7112 WrapperKind = X86ISD::WrapperRIP;
7113 else if (Subtarget->isPICStyleGOT())
7114 OpFlag = X86II::MO_GOTOFF;
7115 else if (Subtarget->isPICStyleStubPIC())
7116 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7118 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7120 DebugLoc DL = JT->getDebugLoc();
7121 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7123 // With PIC, the address is actually $g + Offset.
7125 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7126 DAG.getNode(X86ISD::GlobalBaseReg,
7127 DebugLoc(), getPointerTy()),
7134 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7135 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7137 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7139 unsigned char OpFlag = 0;
7140 unsigned WrapperKind = X86ISD::Wrapper;
7141 CodeModel::Model M = getTargetMachine().getCodeModel();
7143 if (Subtarget->isPICStyleRIPRel() &&
7144 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7145 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7146 OpFlag = X86II::MO_GOTPCREL;
7147 WrapperKind = X86ISD::WrapperRIP;
7148 } else if (Subtarget->isPICStyleGOT()) {
7149 OpFlag = X86II::MO_GOT;
7150 } else if (Subtarget->isPICStyleStubPIC()) {
7151 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7152 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7153 OpFlag = X86II::MO_DARWIN_NONLAZY;
7156 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7158 DebugLoc DL = Op.getDebugLoc();
7159 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7162 // With PIC, the address is actually $g + Offset.
7163 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7164 !Subtarget->is64Bit()) {
7165 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7166 DAG.getNode(X86ISD::GlobalBaseReg,
7167 DebugLoc(), getPointerTy()),
7171 // For symbols that require a load from a stub to get the address, emit the
7173 if (isGlobalStubReference(OpFlag))
7174 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7175 MachinePointerInfo::getGOT(), false, false, 0);
7181 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7182 // Create the TargetBlockAddressAddress node.
7183 unsigned char OpFlags =
7184 Subtarget->ClassifyBlockAddressReference();
7185 CodeModel::Model M = getTargetMachine().getCodeModel();
7186 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7187 DebugLoc dl = Op.getDebugLoc();
7188 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7189 /*isTarget=*/true, OpFlags);
7191 if (Subtarget->isPICStyleRIPRel() &&
7192 (M == CodeModel::Small || M == CodeModel::Kernel))
7193 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7195 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7197 // With PIC, the address is actually $g + Offset.
7198 if (isGlobalRelativeToPICBase(OpFlags)) {
7199 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7200 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7208 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7210 SelectionDAG &DAG) const {
7211 // Create the TargetGlobalAddress node, folding in the constant
7212 // offset if it is legal.
7213 unsigned char OpFlags =
7214 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7215 CodeModel::Model M = getTargetMachine().getCodeModel();
7217 if (OpFlags == X86II::MO_NO_FLAG &&
7218 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7219 // A direct static reference to a global.
7220 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7223 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7226 if (Subtarget->isPICStyleRIPRel() &&
7227 (M == CodeModel::Small || M == CodeModel::Kernel))
7228 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7230 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7232 // With PIC, the address is actually $g + Offset.
7233 if (isGlobalRelativeToPICBase(OpFlags)) {
7234 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7235 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7239 // For globals that require a load from a stub to get the address, emit the
7241 if (isGlobalStubReference(OpFlags))
7242 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7243 MachinePointerInfo::getGOT(), false, false, 0);
7245 // If there was a non-zero offset that we didn't fold, create an explicit
7248 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7249 DAG.getConstant(Offset, getPointerTy()));
7255 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7256 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7257 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7258 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7262 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7263 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7264 unsigned char OperandFlags) {
7265 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7266 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7267 DebugLoc dl = GA->getDebugLoc();
7268 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7269 GA->getValueType(0),
7273 SDValue Ops[] = { Chain, TGA, *InFlag };
7274 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
7276 SDValue Ops[] = { Chain, TGA };
7277 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
7280 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7281 MFI->setAdjustsStack(true);
7283 SDValue Flag = Chain.getValue(1);
7284 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7287 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7289 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7292 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7293 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7294 DAG.getNode(X86ISD::GlobalBaseReg,
7295 DebugLoc(), PtrVT), InFlag);
7296 InFlag = Chain.getValue(1);
7298 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7301 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7303 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7305 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7306 X86::RAX, X86II::MO_TLSGD);
7309 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
7310 // "local exec" model.
7311 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7312 const EVT PtrVT, TLSModel::Model model,
7314 DebugLoc dl = GA->getDebugLoc();
7316 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7317 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7318 is64Bit ? 257 : 256));
7320 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7321 DAG.getIntPtrConstant(0),
7322 MachinePointerInfo(Ptr), false, false, 0);
7324 unsigned char OperandFlags = 0;
7325 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7327 unsigned WrapperKind = X86ISD::Wrapper;
7328 if (model == TLSModel::LocalExec) {
7329 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7330 } else if (is64Bit) {
7331 assert(model == TLSModel::InitialExec);
7332 OperandFlags = X86II::MO_GOTTPOFF;
7333 WrapperKind = X86ISD::WrapperRIP;
7335 assert(model == TLSModel::InitialExec);
7336 OperandFlags = X86II::MO_INDNTPOFF;
7339 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
7341 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7342 GA->getValueType(0),
7343 GA->getOffset(), OperandFlags);
7344 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7346 if (model == TLSModel::InitialExec)
7347 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7348 MachinePointerInfo::getGOT(), false, false, 0);
7350 // The address of the thread local variable is the add of the thread
7351 // pointer with the offset of the variable.
7352 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7356 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7358 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7359 const GlobalValue *GV = GA->getGlobal();
7361 if (Subtarget->isTargetELF()) {
7362 // TODO: implement the "local dynamic" model
7363 // TODO: implement the "initial exec"model for pic executables
7365 // If GV is an alias then use the aliasee for determining
7366 // thread-localness.
7367 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7368 GV = GA->resolveAliasedGlobal(false);
7370 TLSModel::Model model
7371 = getTLSModel(GV, getTargetMachine().getRelocationModel());
7374 case TLSModel::GeneralDynamic:
7375 case TLSModel::LocalDynamic: // not implemented
7376 if (Subtarget->is64Bit())
7377 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7378 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7380 case TLSModel::InitialExec:
7381 case TLSModel::LocalExec:
7382 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7383 Subtarget->is64Bit());
7385 } else if (Subtarget->isTargetDarwin()) {
7386 // Darwin only has one model of TLS. Lower to that.
7387 unsigned char OpFlag = 0;
7388 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7389 X86ISD::WrapperRIP : X86ISD::Wrapper;
7391 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7393 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7394 !Subtarget->is64Bit();
7396 OpFlag = X86II::MO_TLVP_PIC_BASE;
7398 OpFlag = X86II::MO_TLVP;
7399 DebugLoc DL = Op.getDebugLoc();
7400 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7401 GA->getValueType(0),
7402 GA->getOffset(), OpFlag);
7403 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7405 // With PIC32, the address is actually $g + Offset.
7407 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7408 DAG.getNode(X86ISD::GlobalBaseReg,
7409 DebugLoc(), getPointerTy()),
7412 // Lowering the machine isd will make sure everything is in the right
7414 SDValue Chain = DAG.getEntryNode();
7415 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7416 SDValue Args[] = { Chain, Offset };
7417 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7419 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7420 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7421 MFI->setAdjustsStack(true);
7423 // And our return value (tls address) is in the standard call return value
7425 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7426 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
7430 "TLS not implemented for this target.");
7432 llvm_unreachable("Unreachable");
7437 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values and
7438 /// take a 2 x i32 value to shift plus a shift amount.
7439 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const {
7440 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7441 EVT VT = Op.getValueType();
7442 unsigned VTBits = VT.getSizeInBits();
7443 DebugLoc dl = Op.getDebugLoc();
7444 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7445 SDValue ShOpLo = Op.getOperand(0);
7446 SDValue ShOpHi = Op.getOperand(1);
7447 SDValue ShAmt = Op.getOperand(2);
7448 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7449 DAG.getConstant(VTBits - 1, MVT::i8))
7450 : DAG.getConstant(0, VT);
7453 if (Op.getOpcode() == ISD::SHL_PARTS) {
7454 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7455 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7457 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7458 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7461 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7462 DAG.getConstant(VTBits, MVT::i8));
7463 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7464 AndNode, DAG.getConstant(0, MVT::i8));
7467 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7468 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7469 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7471 if (Op.getOpcode() == ISD::SHL_PARTS) {
7472 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7473 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7475 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7476 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7479 SDValue Ops[2] = { Lo, Hi };
7480 return DAG.getMergeValues(Ops, 2, dl);
7483 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7484 SelectionDAG &DAG) const {
7485 EVT SrcVT = Op.getOperand(0).getValueType();
7487 if (SrcVT.isVector())
7490 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7491 "Unknown SINT_TO_FP to lower!");
7493 // These are really Legal; return the operand so the caller accepts it as
7495 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7497 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7498 Subtarget->is64Bit()) {
7502 DebugLoc dl = Op.getDebugLoc();
7503 unsigned Size = SrcVT.getSizeInBits()/8;
7504 MachineFunction &MF = DAG.getMachineFunction();
7505 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7506 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7507 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7509 MachinePointerInfo::getFixedStack(SSFI),
7511 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7514 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7516 SelectionDAG &DAG) const {
7518 DebugLoc DL = Op.getDebugLoc();
7520 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7522 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7524 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7526 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7528 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7529 MachineMemOperand *MMO;
7531 int SSFI = FI->getIndex();
7533 DAG.getMachineFunction()
7534 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7535 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7537 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7538 StackSlot = StackSlot.getOperand(1);
7540 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7541 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7543 Tys, Ops, array_lengthof(Ops),
7547 Chain = Result.getValue(1);
7548 SDValue InFlag = Result.getValue(2);
7550 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7551 // shouldn't be necessary except that RFP cannot be live across
7552 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7553 MachineFunction &MF = DAG.getMachineFunction();
7554 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7555 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7556 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7557 Tys = DAG.getVTList(MVT::Other);
7559 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7561 MachineMemOperand *MMO =
7562 DAG.getMachineFunction()
7563 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7564 MachineMemOperand::MOStore, SSFISize, SSFISize);
7566 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7567 Ops, array_lengthof(Ops),
7568 Op.getValueType(), MMO);
7569 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7570 MachinePointerInfo::getFixedStack(SSFI),
7577 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7578 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7579 SelectionDAG &DAG) const {
7580 // This algorithm is not obvious. Here it is in C code, more or less:
7582 double uint64_to_double( uint32_t hi, uint32_t lo ) {
7583 static const __m128i exp = { 0x4330000045300000ULL, 0 };
7584 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
7586 // Copy ints to xmm registers.
7587 __m128i xh = _mm_cvtsi32_si128( hi );
7588 __m128i xl = _mm_cvtsi32_si128( lo );
7590 // Combine into low half of a single xmm register.
7591 __m128i x = _mm_unpacklo_epi32( xh, xl );
7595 // Merge in appropriate exponents to give the integer bits the right
7597 x = _mm_unpacklo_epi32( x, exp );
7599 // Subtract away the biases to deal with the IEEE-754 double precision
7601 d = _mm_sub_pd( (__m128d) x, bias );
7603 // All conversions up to here are exact. The correctly rounded result is
7604 // calculated using the current rounding mode using the following
7606 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
7607 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
7608 // store doesn't really need to be here (except
7609 // maybe to zero the other double)
7614 DebugLoc dl = Op.getDebugLoc();
7615 LLVMContext *Context = DAG.getContext();
7617 // Build some magic constants.
7618 std::vector<Constant*> CV0;
7619 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
7620 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
7621 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7622 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7623 Constant *C0 = ConstantVector::get(CV0);
7624 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7626 std::vector<Constant*> CV1;
7628 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7630 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7631 Constant *C1 = ConstantVector::get(CV1);
7632 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7634 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7635 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7637 DAG.getIntPtrConstant(1)));
7638 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7639 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7641 DAG.getIntPtrConstant(0)));
7642 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
7643 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7644 MachinePointerInfo::getConstantPool(),
7646 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
7647 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck2);
7648 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7649 MachinePointerInfo::getConstantPool(),
7651 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7653 // Add the halves; easiest way is to swap them into another reg first.
7654 int ShufMask[2] = { 1, -1 };
7655 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
7656 DAG.getUNDEF(MVT::v2f64), ShufMask);
7657 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
7658 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
7659 DAG.getIntPtrConstant(0));
7662 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7663 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7664 SelectionDAG &DAG) const {
7665 DebugLoc dl = Op.getDebugLoc();
7666 // FP constant to bias correct the final result.
7667 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7670 // Load the 32-bit value into an XMM register.
7671 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7674 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7675 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7676 DAG.getIntPtrConstant(0));
7678 // Or the load with the bias.
7679 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7680 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7681 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7683 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7684 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7685 MVT::v2f64, Bias)));
7686 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7687 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7688 DAG.getIntPtrConstant(0));
7690 // Subtract the bias.
7691 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7693 // Handle final rounding.
7694 EVT DestVT = Op.getValueType();
7696 if (DestVT.bitsLT(MVT::f64)) {
7697 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7698 DAG.getIntPtrConstant(0));
7699 } else if (DestVT.bitsGT(MVT::f64)) {
7700 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7703 // Handle final rounding.
7707 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7708 SelectionDAG &DAG) const {
7709 SDValue N0 = Op.getOperand(0);
7710 DebugLoc dl = Op.getDebugLoc();
7712 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7713 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7714 // the optimization here.
7715 if (DAG.SignBitIsZero(N0))
7716 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7718 EVT SrcVT = N0.getValueType();
7719 EVT DstVT = Op.getValueType();
7720 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7721 return LowerUINT_TO_FP_i64(Op, DAG);
7722 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7723 return LowerUINT_TO_FP_i32(Op, DAG);
7725 // Make a 64-bit buffer, and use it to build an FILD.
7726 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7727 if (SrcVT == MVT::i32) {
7728 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7729 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7730 getPointerTy(), StackSlot, WordOff);
7731 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7732 StackSlot, MachinePointerInfo(),
7734 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7735 OffsetSlot, MachinePointerInfo(),
7737 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7741 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7742 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7743 StackSlot, MachinePointerInfo(),
7745 // For i64 source, we need to add the appropriate power of 2 if the input
7746 // was negative. This is the same as the optimization in
7747 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7748 // we must be careful to do the computation in x87 extended precision, not
7749 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7750 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7751 MachineMemOperand *MMO =
7752 DAG.getMachineFunction()
7753 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7754 MachineMemOperand::MOLoad, 8, 8);
7756 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7757 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7758 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7761 APInt FF(32, 0x5F800000ULL);
7763 // Check whether the sign bit is set.
7764 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7765 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7768 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7769 SDValue FudgePtr = DAG.getConstantPool(
7770 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7773 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7774 SDValue Zero = DAG.getIntPtrConstant(0);
7775 SDValue Four = DAG.getIntPtrConstant(4);
7776 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7778 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7780 // Load the value out, extending it from f32 to f80.
7781 // FIXME: Avoid the extend by constructing the right constant pool?
7782 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7783 FudgePtr, MachinePointerInfo::getConstantPool(),
7784 MVT::f32, false, false, 4);
7785 // Extend everything to 80 bits to force it to be done on x87.
7786 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7787 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7790 std::pair<SDValue,SDValue> X86TargetLowering::
7791 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
7792 DebugLoc DL = Op.getDebugLoc();
7794 EVT DstTy = Op.getValueType();
7797 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7801 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7802 DstTy.getSimpleVT() >= MVT::i16 &&
7803 "Unknown FP_TO_SINT to lower!");
7805 // These are really Legal.
7806 if (DstTy == MVT::i32 &&
7807 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7808 return std::make_pair(SDValue(), SDValue());
7809 if (Subtarget->is64Bit() &&
7810 DstTy == MVT::i64 &&
7811 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7812 return std::make_pair(SDValue(), SDValue());
7814 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
7816 MachineFunction &MF = DAG.getMachineFunction();
7817 unsigned MemSize = DstTy.getSizeInBits()/8;
7818 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7819 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7824 switch (DstTy.getSimpleVT().SimpleTy) {
7825 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7826 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7827 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7828 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7831 SDValue Chain = DAG.getEntryNode();
7832 SDValue Value = Op.getOperand(0);
7833 EVT TheVT = Op.getOperand(0).getValueType();
7834 if (isScalarFPTypeInSSEReg(TheVT)) {
7835 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7836 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7837 MachinePointerInfo::getFixedStack(SSFI),
7839 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7841 Chain, StackSlot, DAG.getValueType(TheVT)
7844 MachineMemOperand *MMO =
7845 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7846 MachineMemOperand::MOLoad, MemSize, MemSize);
7847 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7849 Chain = Value.getValue(1);
7850 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7851 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7854 MachineMemOperand *MMO =
7855 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7856 MachineMemOperand::MOStore, MemSize, MemSize);
7858 // Build the FP_TO_INT*_IN_MEM
7859 SDValue Ops[] = { Chain, Value, StackSlot };
7860 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7861 Ops, 3, DstTy, MMO);
7863 return std::make_pair(FIST, StackSlot);
7866 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7867 SelectionDAG &DAG) const {
7868 if (Op.getValueType().isVector())
7871 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
7872 SDValue FIST = Vals.first, StackSlot = Vals.second;
7873 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7874 if (FIST.getNode() == 0) return Op;
7877 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7878 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
7881 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7882 SelectionDAG &DAG) const {
7883 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
7884 SDValue FIST = Vals.first, StackSlot = Vals.second;
7885 assert(FIST.getNode() && "Unexpected failure");
7888 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7889 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
7892 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7893 SelectionDAG &DAG) const {
7894 LLVMContext *Context = DAG.getContext();
7895 DebugLoc dl = Op.getDebugLoc();
7896 EVT VT = Op.getValueType();
7899 EltVT = VT.getVectorElementType();
7900 std::vector<Constant*> CV;
7901 if (EltVT == MVT::f64) {
7902 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
7906 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
7912 Constant *C = ConstantVector::get(CV);
7913 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7914 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7915 MachinePointerInfo::getConstantPool(),
7917 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
7920 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
7921 LLVMContext *Context = DAG.getContext();
7922 DebugLoc dl = Op.getDebugLoc();
7923 EVT VT = Op.getValueType();
7926 EltVT = VT.getVectorElementType();
7927 std::vector<Constant*> CV;
7928 if (EltVT == MVT::f64) {
7929 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
7933 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
7939 Constant *C = ConstantVector::get(CV);
7940 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7941 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7942 MachinePointerInfo::getConstantPool(),
7944 if (VT.isVector()) {
7945 return DAG.getNode(ISD::BITCAST, dl, VT,
7946 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
7947 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7949 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Mask)));
7951 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
7955 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
7956 LLVMContext *Context = DAG.getContext();
7957 SDValue Op0 = Op.getOperand(0);
7958 SDValue Op1 = Op.getOperand(1);
7959 DebugLoc dl = Op.getDebugLoc();
7960 EVT VT = Op.getValueType();
7961 EVT SrcVT = Op1.getValueType();
7963 // If second operand is smaller, extend it first.
7964 if (SrcVT.bitsLT(VT)) {
7965 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
7968 // And if it is bigger, shrink it first.
7969 if (SrcVT.bitsGT(VT)) {
7970 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
7974 // At this point the operands and the result should have the same
7975 // type, and that won't be f80 since that is not custom lowered.
7977 // First get the sign bit of second operand.
7978 std::vector<Constant*> CV;
7979 if (SrcVT == MVT::f64) {
7980 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
7981 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7983 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
7984 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7985 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7986 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7988 Constant *C = ConstantVector::get(CV);
7989 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7990 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
7991 MachinePointerInfo::getConstantPool(),
7993 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
7995 // Shift sign bit right or left if the two operands have different types.
7996 if (SrcVT.bitsGT(VT)) {
7997 // Op0 is MVT::f32, Op1 is MVT::f64.
7998 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
7999 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
8000 DAG.getConstant(32, MVT::i32));
8001 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
8002 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
8003 DAG.getIntPtrConstant(0));
8006 // Clear first operand sign bit.
8008 if (VT == MVT::f64) {
8009 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8010 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8012 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8013 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8014 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8015 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8017 C = ConstantVector::get(CV);
8018 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8019 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8020 MachinePointerInfo::getConstantPool(),
8022 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8024 // Or the value with the sign bit.
8025 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8028 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
8029 SDValue N0 = Op.getOperand(0);
8030 DebugLoc dl = Op.getDebugLoc();
8031 EVT VT = Op.getValueType();
8033 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8034 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8035 DAG.getConstant(1, VT));
8036 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8039 /// Emit nodes that will be selected as "test Op0,Op0", or something
8041 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8042 SelectionDAG &DAG) const {
8043 DebugLoc dl = Op.getDebugLoc();
8045 // CF and OF aren't always set the way we want. Determine which
8046 // of these we need.
8047 bool NeedCF = false;
8048 bool NeedOF = false;
8051 case X86::COND_A: case X86::COND_AE:
8052 case X86::COND_B: case X86::COND_BE:
8055 case X86::COND_G: case X86::COND_GE:
8056 case X86::COND_L: case X86::COND_LE:
8057 case X86::COND_O: case X86::COND_NO:
8062 // See if we can use the EFLAGS value from the operand instead of
8063 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8064 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8065 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8066 // Emit a CMP with 0, which is the TEST pattern.
8067 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8068 DAG.getConstant(0, Op.getValueType()));
8070 unsigned Opcode = 0;
8071 unsigned NumOperands = 0;
8072 switch (Op.getNode()->getOpcode()) {
8074 // Due to an isel shortcoming, be conservative if this add is likely to be
8075 // selected as part of a load-modify-store instruction. When the root node
8076 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8077 // uses of other nodes in the match, such as the ADD in this case. This
8078 // leads to the ADD being left around and reselected, with the result being
8079 // two adds in the output. Alas, even if none our users are stores, that
8080 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8081 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8082 // climbing the DAG back to the root, and it doesn't seem to be worth the
8084 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8085 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8086 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
8089 if (ConstantSDNode *C =
8090 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8091 // An add of one will be selected as an INC.
8092 if (C->getAPIntValue() == 1) {
8093 Opcode = X86ISD::INC;
8098 // An add of negative one (subtract of one) will be selected as a DEC.
8099 if (C->getAPIntValue().isAllOnesValue()) {
8100 Opcode = X86ISD::DEC;
8106 // Otherwise use a regular EFLAGS-setting add.
8107 Opcode = X86ISD::ADD;
8111 // If the primary and result isn't used, don't bother using X86ISD::AND,
8112 // because a TEST instruction will be better.
8113 bool NonFlagUse = false;
8114 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8115 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8117 unsigned UOpNo = UI.getOperandNo();
8118 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8119 // Look pass truncate.
8120 UOpNo = User->use_begin().getOperandNo();
8121 User = *User->use_begin();
8124 if (User->getOpcode() != ISD::BRCOND &&
8125 User->getOpcode() != ISD::SETCC &&
8126 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8139 // Due to the ISEL shortcoming noted above, be conservative if this op is
8140 // likely to be selected as part of a load-modify-store instruction.
8141 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8142 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8143 if (UI->getOpcode() == ISD::STORE)
8146 // Otherwise use a regular EFLAGS-setting instruction.
8147 switch (Op.getNode()->getOpcode()) {
8148 default: llvm_unreachable("unexpected operator!");
8149 case ISD::SUB: Opcode = X86ISD::SUB; break;
8150 case ISD::OR: Opcode = X86ISD::OR; break;
8151 case ISD::XOR: Opcode = X86ISD::XOR; break;
8152 case ISD::AND: Opcode = X86ISD::AND; break;
8164 return SDValue(Op.getNode(), 1);
8171 // Emit a CMP with 0, which is the TEST pattern.
8172 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8173 DAG.getConstant(0, Op.getValueType()));
8175 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8176 SmallVector<SDValue, 4> Ops;
8177 for (unsigned i = 0; i != NumOperands; ++i)
8178 Ops.push_back(Op.getOperand(i));
8180 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8181 DAG.ReplaceAllUsesWith(Op, New);
8182 return SDValue(New.getNode(), 1);
8185 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8187 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8188 SelectionDAG &DAG) const {
8189 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8190 if (C->getAPIntValue() == 0)
8191 return EmitTest(Op0, X86CC, DAG);
8193 DebugLoc dl = Op0.getDebugLoc();
8194 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8197 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8198 /// if it's possible.
8199 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8200 DebugLoc dl, SelectionDAG &DAG) const {
8201 SDValue Op0 = And.getOperand(0);
8202 SDValue Op1 = And.getOperand(1);
8203 if (Op0.getOpcode() == ISD::TRUNCATE)
8204 Op0 = Op0.getOperand(0);
8205 if (Op1.getOpcode() == ISD::TRUNCATE)
8206 Op1 = Op1.getOperand(0);
8209 if (Op1.getOpcode() == ISD::SHL)
8210 std::swap(Op0, Op1);
8211 if (Op0.getOpcode() == ISD::SHL) {
8212 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8213 if (And00C->getZExtValue() == 1) {
8214 // If we looked past a truncate, check that it's only truncating away
8216 unsigned BitWidth = Op0.getValueSizeInBits();
8217 unsigned AndBitWidth = And.getValueSizeInBits();
8218 if (BitWidth > AndBitWidth) {
8219 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
8220 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
8221 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8225 RHS = Op0.getOperand(1);
8227 } else if (Op1.getOpcode() == ISD::Constant) {
8228 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8229 SDValue AndLHS = Op0;
8230 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
8231 LHS = AndLHS.getOperand(0);
8232 RHS = AndLHS.getOperand(1);
8236 if (LHS.getNode()) {
8237 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8238 // instruction. Since the shift amount is in-range-or-undefined, we know
8239 // that doing a bittest on the i32 value is ok. We extend to i32 because
8240 // the encoding for the i16 version is larger than the i32 version.
8241 // Also promote i16 to i32 for performance / code size reason.
8242 if (LHS.getValueType() == MVT::i8 ||
8243 LHS.getValueType() == MVT::i16)
8244 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8246 // If the operand types disagree, extend the shift amount to match. Since
8247 // BT ignores high bits (like shifts) we can use anyextend.
8248 if (LHS.getValueType() != RHS.getValueType())
8249 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8251 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8252 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8253 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8254 DAG.getConstant(Cond, MVT::i8), BT);
8260 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8261 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8262 SDValue Op0 = Op.getOperand(0);
8263 SDValue Op1 = Op.getOperand(1);
8264 DebugLoc dl = Op.getDebugLoc();
8265 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8267 // Optimize to BT if possible.
8268 // Lower (X & (1 << N)) == 0 to BT(X, N).
8269 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8270 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8271 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8272 Op1.getOpcode() == ISD::Constant &&
8273 cast<ConstantSDNode>(Op1)->isNullValue() &&
8274 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8275 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8276 if (NewSetCC.getNode())
8280 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8282 if (Op1.getOpcode() == ISD::Constant &&
8283 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8284 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8285 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8287 // If the input is a setcc, then reuse the input setcc or use a new one with
8288 // the inverted condition.
8289 if (Op0.getOpcode() == X86ISD::SETCC) {
8290 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8291 bool Invert = (CC == ISD::SETNE) ^
8292 cast<ConstantSDNode>(Op1)->isNullValue();
8293 if (!Invert) return Op0;
8295 CCode = X86::GetOppositeBranchCondition(CCode);
8296 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8297 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8301 bool isFP = Op1.getValueType().isFloatingPoint();
8302 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8303 if (X86CC == X86::COND_INVALID)
8306 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8307 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8308 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8311 // Lower256IntVETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8312 // ones, and then concatenate the result back.
8313 static SDValue Lower256IntVETCC(SDValue Op, SelectionDAG &DAG) {
8314 EVT VT = Op.getValueType();
8316 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::VSETCC &&
8317 "Unsupported value type for operation");
8319 int NumElems = VT.getVectorNumElements();
8320 DebugLoc dl = Op.getDebugLoc();
8321 SDValue CC = Op.getOperand(2);
8322 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
8323 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
8325 // Extract the LHS vectors
8326 SDValue LHS = Op.getOperand(0);
8327 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
8328 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
8330 // Extract the RHS vectors
8331 SDValue RHS = Op.getOperand(1);
8332 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
8333 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
8335 // Issue the operation on the smaller types and concatenate the result back
8336 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8337 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8338 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8339 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8340 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8344 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8346 SDValue Op0 = Op.getOperand(0);
8347 SDValue Op1 = Op.getOperand(1);
8348 SDValue CC = Op.getOperand(2);
8349 EVT VT = Op.getValueType();
8350 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8351 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8352 DebugLoc dl = Op.getDebugLoc();
8356 EVT EltVT = Op0.getValueType().getVectorElementType();
8357 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
8359 unsigned Opc = EltVT == MVT::f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
8362 switch (SetCCOpcode) {
8365 case ISD::SETEQ: SSECC = 0; break;
8367 case ISD::SETGT: Swap = true; // Fallthrough
8369 case ISD::SETOLT: SSECC = 1; break;
8371 case ISD::SETGE: Swap = true; // Fallthrough
8373 case ISD::SETOLE: SSECC = 2; break;
8374 case ISD::SETUO: SSECC = 3; break;
8376 case ISD::SETNE: SSECC = 4; break;
8377 case ISD::SETULE: Swap = true;
8378 case ISD::SETUGE: SSECC = 5; break;
8379 case ISD::SETULT: Swap = true;
8380 case ISD::SETUGT: SSECC = 6; break;
8381 case ISD::SETO: SSECC = 7; break;
8384 std::swap(Op0, Op1);
8386 // In the two special cases we can't handle, emit two comparisons.
8388 if (SetCCOpcode == ISD::SETUEQ) {
8390 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
8391 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
8392 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8394 else if (SetCCOpcode == ISD::SETONE) {
8396 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
8397 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
8398 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8400 llvm_unreachable("Illegal FP comparison");
8402 // Handle all other FP comparisons here.
8403 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
8406 // Break 256-bit integer vector compare into smaller ones.
8407 if (!isFP && VT.getSizeInBits() == 256)
8408 return Lower256IntVETCC(Op, DAG);
8410 // We are handling one of the integer comparisons here. Since SSE only has
8411 // GT and EQ comparisons for integer, swapping operands and multiple
8412 // operations may be required for some comparisons.
8413 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
8414 bool Swap = false, Invert = false, FlipSigns = false;
8416 switch (VT.getSimpleVT().SimpleTy) {
8418 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
8419 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
8420 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
8421 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
8424 switch (SetCCOpcode) {
8426 case ISD::SETNE: Invert = true;
8427 case ISD::SETEQ: Opc = EQOpc; break;
8428 case ISD::SETLT: Swap = true;
8429 case ISD::SETGT: Opc = GTOpc; break;
8430 case ISD::SETGE: Swap = true;
8431 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
8432 case ISD::SETULT: Swap = true;
8433 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
8434 case ISD::SETUGE: Swap = true;
8435 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
8438 std::swap(Op0, Op1);
8440 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8441 // bits of the inputs before performing those operations.
8443 EVT EltVT = VT.getVectorElementType();
8444 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8446 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8447 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8449 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8450 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8453 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8455 // If the logical-not of the result is required, perform that now.
8457 Result = DAG.getNOT(dl, Result, VT);
8462 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8463 static bool isX86LogicalCmp(SDValue Op) {
8464 unsigned Opc = Op.getNode()->getOpcode();
8465 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
8467 if (Op.getResNo() == 1 &&
8468 (Opc == X86ISD::ADD ||
8469 Opc == X86ISD::SUB ||
8470 Opc == X86ISD::ADC ||
8471 Opc == X86ISD::SBB ||
8472 Opc == X86ISD::SMUL ||
8473 Opc == X86ISD::UMUL ||
8474 Opc == X86ISD::INC ||
8475 Opc == X86ISD::DEC ||
8476 Opc == X86ISD::OR ||
8477 Opc == X86ISD::XOR ||
8478 Opc == X86ISD::AND))
8481 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8487 static bool isZero(SDValue V) {
8488 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8489 return C && C->isNullValue();
8492 static bool isAllOnes(SDValue V) {
8493 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8494 return C && C->isAllOnesValue();
8497 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8498 bool addTest = true;
8499 SDValue Cond = Op.getOperand(0);
8500 SDValue Op1 = Op.getOperand(1);
8501 SDValue Op2 = Op.getOperand(2);
8502 DebugLoc DL = Op.getDebugLoc();
8505 if (Cond.getOpcode() == ISD::SETCC) {
8506 SDValue NewCond = LowerSETCC(Cond, DAG);
8507 if (NewCond.getNode())
8511 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8512 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8513 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8514 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8515 if (Cond.getOpcode() == X86ISD::SETCC &&
8516 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8517 isZero(Cond.getOperand(1).getOperand(1))) {
8518 SDValue Cmp = Cond.getOperand(1);
8520 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8522 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8523 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8524 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8526 SDValue CmpOp0 = Cmp.getOperand(0);
8527 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8528 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8530 SDValue Res = // Res = 0 or -1.
8531 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8532 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8534 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8535 Res = DAG.getNOT(DL, Res, Res.getValueType());
8537 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8538 if (N2C == 0 || !N2C->isNullValue())
8539 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8544 // Look past (and (setcc_carry (cmp ...)), 1).
8545 if (Cond.getOpcode() == ISD::AND &&
8546 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8547 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8548 if (C && C->getAPIntValue() == 1)
8549 Cond = Cond.getOperand(0);
8552 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8553 // setting operand in place of the X86ISD::SETCC.
8554 if (Cond.getOpcode() == X86ISD::SETCC ||
8555 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
8556 CC = Cond.getOperand(0);
8558 SDValue Cmp = Cond.getOperand(1);
8559 unsigned Opc = Cmp.getOpcode();
8560 EVT VT = Op.getValueType();
8562 bool IllegalFPCMov = false;
8563 if (VT.isFloatingPoint() && !VT.isVector() &&
8564 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8565 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8567 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8568 Opc == X86ISD::BT) { // FIXME
8575 // Look pass the truncate.
8576 if (Cond.getOpcode() == ISD::TRUNCATE)
8577 Cond = Cond.getOperand(0);
8579 // We know the result of AND is compared against zero. Try to match
8581 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8582 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8583 if (NewSetCC.getNode()) {
8584 CC = NewSetCC.getOperand(0);
8585 Cond = NewSetCC.getOperand(1);
8592 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8593 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8596 // a < b ? -1 : 0 -> RES = ~setcc_carry
8597 // a < b ? 0 : -1 -> RES = setcc_carry
8598 // a >= b ? -1 : 0 -> RES = setcc_carry
8599 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8600 if (Cond.getOpcode() == X86ISD::CMP) {
8601 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8603 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8604 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8605 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8606 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8607 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8608 return DAG.getNOT(DL, Res, Res.getValueType());
8613 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8614 // condition is true.
8615 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8616 SDValue Ops[] = { Op2, Op1, CC, Cond };
8617 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8620 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8621 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8622 // from the AND / OR.
8623 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8624 Opc = Op.getOpcode();
8625 if (Opc != ISD::OR && Opc != ISD::AND)
8627 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8628 Op.getOperand(0).hasOneUse() &&
8629 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8630 Op.getOperand(1).hasOneUse());
8633 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8634 // 1 and that the SETCC node has a single use.
8635 static bool isXor1OfSetCC(SDValue Op) {
8636 if (Op.getOpcode() != ISD::XOR)
8638 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8639 if (N1C && N1C->getAPIntValue() == 1) {
8640 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8641 Op.getOperand(0).hasOneUse();
8646 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8647 bool addTest = true;
8648 SDValue Chain = Op.getOperand(0);
8649 SDValue Cond = Op.getOperand(1);
8650 SDValue Dest = Op.getOperand(2);
8651 DebugLoc dl = Op.getDebugLoc();
8654 if (Cond.getOpcode() == ISD::SETCC) {
8655 SDValue NewCond = LowerSETCC(Cond, DAG);
8656 if (NewCond.getNode())
8660 // FIXME: LowerXALUO doesn't handle these!!
8661 else if (Cond.getOpcode() == X86ISD::ADD ||
8662 Cond.getOpcode() == X86ISD::SUB ||
8663 Cond.getOpcode() == X86ISD::SMUL ||
8664 Cond.getOpcode() == X86ISD::UMUL)
8665 Cond = LowerXALUO(Cond, DAG);
8668 // Look pass (and (setcc_carry (cmp ...)), 1).
8669 if (Cond.getOpcode() == ISD::AND &&
8670 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8671 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8672 if (C && C->getAPIntValue() == 1)
8673 Cond = Cond.getOperand(0);
8676 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8677 // setting operand in place of the X86ISD::SETCC.
8678 if (Cond.getOpcode() == X86ISD::SETCC ||
8679 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
8680 CC = Cond.getOperand(0);
8682 SDValue Cmp = Cond.getOperand(1);
8683 unsigned Opc = Cmp.getOpcode();
8684 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8685 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8689 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8693 // These can only come from an arithmetic instruction with overflow,
8694 // e.g. SADDO, UADDO.
8695 Cond = Cond.getNode()->getOperand(1);
8702 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8703 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8704 if (CondOpc == ISD::OR) {
8705 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8706 // two branches instead of an explicit OR instruction with a
8708 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8709 isX86LogicalCmp(Cmp)) {
8710 CC = Cond.getOperand(0).getOperand(0);
8711 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8712 Chain, Dest, CC, Cmp);
8713 CC = Cond.getOperand(1).getOperand(0);
8717 } else { // ISD::AND
8718 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8719 // two branches instead of an explicit AND instruction with a
8720 // separate test. However, we only do this if this block doesn't
8721 // have a fall-through edge, because this requires an explicit
8722 // jmp when the condition is false.
8723 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8724 isX86LogicalCmp(Cmp) &&
8725 Op.getNode()->hasOneUse()) {
8726 X86::CondCode CCode =
8727 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8728 CCode = X86::GetOppositeBranchCondition(CCode);
8729 CC = DAG.getConstant(CCode, MVT::i8);
8730 SDNode *User = *Op.getNode()->use_begin();
8731 // Look for an unconditional branch following this conditional branch.
8732 // We need this because we need to reverse the successors in order
8733 // to implement FCMP_OEQ.
8734 if (User->getOpcode() == ISD::BR) {
8735 SDValue FalseBB = User->getOperand(1);
8737 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8738 assert(NewBR == User);
8742 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8743 Chain, Dest, CC, Cmp);
8744 X86::CondCode CCode =
8745 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
8746 CCode = X86::GetOppositeBranchCondition(CCode);
8747 CC = DAG.getConstant(CCode, MVT::i8);
8753 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
8754 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8755 // It should be transformed during dag combiner except when the condition
8756 // is set by a arithmetics with overflow node.
8757 X86::CondCode CCode =
8758 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8759 CCode = X86::GetOppositeBranchCondition(CCode);
8760 CC = DAG.getConstant(CCode, MVT::i8);
8761 Cond = Cond.getOperand(0).getOperand(1);
8767 // Look pass the truncate.
8768 if (Cond.getOpcode() == ISD::TRUNCATE)
8769 Cond = Cond.getOperand(0);
8771 // We know the result of AND is compared against zero. Try to match
8773 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8774 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
8775 if (NewSetCC.getNode()) {
8776 CC = NewSetCC.getOperand(0);
8777 Cond = NewSetCC.getOperand(1);
8784 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8785 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8787 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8788 Chain, Dest, CC, Cond);
8792 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
8793 // Calls to _alloca is needed to probe the stack when allocating more than 4k
8794 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
8795 // that the guard pages used by the OS virtual memory manager are allocated in
8796 // correct sequence.
8798 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
8799 SelectionDAG &DAG) const {
8800 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows()) &&
8801 "This should be used only on Windows targets");
8802 assert(!Subtarget->isTargetEnvMacho());
8803 DebugLoc dl = Op.getDebugLoc();
8806 SDValue Chain = Op.getOperand(0);
8807 SDValue Size = Op.getOperand(1);
8808 // FIXME: Ensure alignment here
8812 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
8813 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
8815 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
8816 Flag = Chain.getValue(1);
8818 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8820 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
8821 Flag = Chain.getValue(1);
8823 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
8825 SDValue Ops1[2] = { Chain.getValue(0), Chain };
8826 return DAG.getMergeValues(Ops1, 2, dl);
8829 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
8830 MachineFunction &MF = DAG.getMachineFunction();
8831 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
8833 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
8834 DebugLoc DL = Op.getDebugLoc();
8836 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
8837 // vastart just stores the address of the VarArgsFrameIndex slot into the
8838 // memory location argument.
8839 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
8841 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
8842 MachinePointerInfo(SV), false, false, 0);
8846 // gp_offset (0 - 6 * 8)
8847 // fp_offset (48 - 48 + 8 * 16)
8848 // overflow_arg_area (point to parameters coming in memory).
8850 SmallVector<SDValue, 8> MemOps;
8851 SDValue FIN = Op.getOperand(1);
8853 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
8854 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
8856 FIN, MachinePointerInfo(SV), false, false, 0);
8857 MemOps.push_back(Store);
8860 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8861 FIN, DAG.getIntPtrConstant(4));
8862 Store = DAG.getStore(Op.getOperand(0), DL,
8863 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
8865 FIN, MachinePointerInfo(SV, 4), false, false, 0);
8866 MemOps.push_back(Store);
8868 // Store ptr to overflow_arg_area
8869 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8870 FIN, DAG.getIntPtrConstant(4));
8871 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
8873 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
8874 MachinePointerInfo(SV, 8),
8876 MemOps.push_back(Store);
8878 // Store ptr to reg_save_area.
8879 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8880 FIN, DAG.getIntPtrConstant(8));
8881 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
8883 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
8884 MachinePointerInfo(SV, 16), false, false, 0);
8885 MemOps.push_back(Store);
8886 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
8887 &MemOps[0], MemOps.size());
8890 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
8891 assert(Subtarget->is64Bit() &&
8892 "LowerVAARG only handles 64-bit va_arg!");
8893 assert((Subtarget->isTargetLinux() ||
8894 Subtarget->isTargetDarwin()) &&
8895 "Unhandled target in LowerVAARG");
8896 assert(Op.getNode()->getNumOperands() == 4);
8897 SDValue Chain = Op.getOperand(0);
8898 SDValue SrcPtr = Op.getOperand(1);
8899 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
8900 unsigned Align = Op.getConstantOperandVal(3);
8901 DebugLoc dl = Op.getDebugLoc();
8903 EVT ArgVT = Op.getNode()->getValueType(0);
8904 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
8905 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
8908 // Decide which area this value should be read from.
8909 // TODO: Implement the AMD64 ABI in its entirety. This simple
8910 // selection mechanism works only for the basic types.
8911 if (ArgVT == MVT::f80) {
8912 llvm_unreachable("va_arg for f80 not yet implemented");
8913 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
8914 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
8915 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
8916 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
8918 llvm_unreachable("Unhandled argument type in LowerVAARG");
8922 // Sanity Check: Make sure using fp_offset makes sense.
8923 assert(!UseSoftFloat &&
8924 !(DAG.getMachineFunction()
8925 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
8926 Subtarget->hasXMM());
8929 // Insert VAARG_64 node into the DAG
8930 // VAARG_64 returns two values: Variable Argument Address, Chain
8931 SmallVector<SDValue, 11> InstOps;
8932 InstOps.push_back(Chain);
8933 InstOps.push_back(SrcPtr);
8934 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
8935 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
8936 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
8937 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
8938 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
8939 VTs, &InstOps[0], InstOps.size(),
8941 MachinePointerInfo(SV),
8946 Chain = VAARG.getValue(1);
8948 // Load the next argument and return it
8949 return DAG.getLoad(ArgVT, dl,
8952 MachinePointerInfo(),
8956 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
8957 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
8958 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
8959 SDValue Chain = Op.getOperand(0);
8960 SDValue DstPtr = Op.getOperand(1);
8961 SDValue SrcPtr = Op.getOperand(2);
8962 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
8963 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
8964 DebugLoc DL = Op.getDebugLoc();
8966 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
8967 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
8969 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
8973 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
8974 DebugLoc dl = Op.getDebugLoc();
8975 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8977 default: return SDValue(); // Don't custom lower most intrinsics.
8978 // Comparison intrinsics.
8979 case Intrinsic::x86_sse_comieq_ss:
8980 case Intrinsic::x86_sse_comilt_ss:
8981 case Intrinsic::x86_sse_comile_ss:
8982 case Intrinsic::x86_sse_comigt_ss:
8983 case Intrinsic::x86_sse_comige_ss:
8984 case Intrinsic::x86_sse_comineq_ss:
8985 case Intrinsic::x86_sse_ucomieq_ss:
8986 case Intrinsic::x86_sse_ucomilt_ss:
8987 case Intrinsic::x86_sse_ucomile_ss:
8988 case Intrinsic::x86_sse_ucomigt_ss:
8989 case Intrinsic::x86_sse_ucomige_ss:
8990 case Intrinsic::x86_sse_ucomineq_ss:
8991 case Intrinsic::x86_sse2_comieq_sd:
8992 case Intrinsic::x86_sse2_comilt_sd:
8993 case Intrinsic::x86_sse2_comile_sd:
8994 case Intrinsic::x86_sse2_comigt_sd:
8995 case Intrinsic::x86_sse2_comige_sd:
8996 case Intrinsic::x86_sse2_comineq_sd:
8997 case Intrinsic::x86_sse2_ucomieq_sd:
8998 case Intrinsic::x86_sse2_ucomilt_sd:
8999 case Intrinsic::x86_sse2_ucomile_sd:
9000 case Intrinsic::x86_sse2_ucomigt_sd:
9001 case Intrinsic::x86_sse2_ucomige_sd:
9002 case Intrinsic::x86_sse2_ucomineq_sd: {
9004 ISD::CondCode CC = ISD::SETCC_INVALID;
9007 case Intrinsic::x86_sse_comieq_ss:
9008 case Intrinsic::x86_sse2_comieq_sd:
9012 case Intrinsic::x86_sse_comilt_ss:
9013 case Intrinsic::x86_sse2_comilt_sd:
9017 case Intrinsic::x86_sse_comile_ss:
9018 case Intrinsic::x86_sse2_comile_sd:
9022 case Intrinsic::x86_sse_comigt_ss:
9023 case Intrinsic::x86_sse2_comigt_sd:
9027 case Intrinsic::x86_sse_comige_ss:
9028 case Intrinsic::x86_sse2_comige_sd:
9032 case Intrinsic::x86_sse_comineq_ss:
9033 case Intrinsic::x86_sse2_comineq_sd:
9037 case Intrinsic::x86_sse_ucomieq_ss:
9038 case Intrinsic::x86_sse2_ucomieq_sd:
9039 Opc = X86ISD::UCOMI;
9042 case Intrinsic::x86_sse_ucomilt_ss:
9043 case Intrinsic::x86_sse2_ucomilt_sd:
9044 Opc = X86ISD::UCOMI;
9047 case Intrinsic::x86_sse_ucomile_ss:
9048 case Intrinsic::x86_sse2_ucomile_sd:
9049 Opc = X86ISD::UCOMI;
9052 case Intrinsic::x86_sse_ucomigt_ss:
9053 case Intrinsic::x86_sse2_ucomigt_sd:
9054 Opc = X86ISD::UCOMI;
9057 case Intrinsic::x86_sse_ucomige_ss:
9058 case Intrinsic::x86_sse2_ucomige_sd:
9059 Opc = X86ISD::UCOMI;
9062 case Intrinsic::x86_sse_ucomineq_ss:
9063 case Intrinsic::x86_sse2_ucomineq_sd:
9064 Opc = X86ISD::UCOMI;
9069 SDValue LHS = Op.getOperand(1);
9070 SDValue RHS = Op.getOperand(2);
9071 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9072 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9073 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9074 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9075 DAG.getConstant(X86CC, MVT::i8), Cond);
9076 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9078 // ptest and testp intrinsics. The intrinsic these come from are designed to
9079 // return an integer value, not just an instruction so lower it to the ptest
9080 // or testp pattern and a setcc for the result.
9081 case Intrinsic::x86_sse41_ptestz:
9082 case Intrinsic::x86_sse41_ptestc:
9083 case Intrinsic::x86_sse41_ptestnzc:
9084 case Intrinsic::x86_avx_ptestz_256:
9085 case Intrinsic::x86_avx_ptestc_256:
9086 case Intrinsic::x86_avx_ptestnzc_256:
9087 case Intrinsic::x86_avx_vtestz_ps:
9088 case Intrinsic::x86_avx_vtestc_ps:
9089 case Intrinsic::x86_avx_vtestnzc_ps:
9090 case Intrinsic::x86_avx_vtestz_pd:
9091 case Intrinsic::x86_avx_vtestc_pd:
9092 case Intrinsic::x86_avx_vtestnzc_pd:
9093 case Intrinsic::x86_avx_vtestz_ps_256:
9094 case Intrinsic::x86_avx_vtestc_ps_256:
9095 case Intrinsic::x86_avx_vtestnzc_ps_256:
9096 case Intrinsic::x86_avx_vtestz_pd_256:
9097 case Intrinsic::x86_avx_vtestc_pd_256:
9098 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9099 bool IsTestPacked = false;
9102 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9103 case Intrinsic::x86_avx_vtestz_ps:
9104 case Intrinsic::x86_avx_vtestz_pd:
9105 case Intrinsic::x86_avx_vtestz_ps_256:
9106 case Intrinsic::x86_avx_vtestz_pd_256:
9107 IsTestPacked = true; // Fallthrough
9108 case Intrinsic::x86_sse41_ptestz:
9109 case Intrinsic::x86_avx_ptestz_256:
9111 X86CC = X86::COND_E;
9113 case Intrinsic::x86_avx_vtestc_ps:
9114 case Intrinsic::x86_avx_vtestc_pd:
9115 case Intrinsic::x86_avx_vtestc_ps_256:
9116 case Intrinsic::x86_avx_vtestc_pd_256:
9117 IsTestPacked = true; // Fallthrough
9118 case Intrinsic::x86_sse41_ptestc:
9119 case Intrinsic::x86_avx_ptestc_256:
9121 X86CC = X86::COND_B;
9123 case Intrinsic::x86_avx_vtestnzc_ps:
9124 case Intrinsic::x86_avx_vtestnzc_pd:
9125 case Intrinsic::x86_avx_vtestnzc_ps_256:
9126 case Intrinsic::x86_avx_vtestnzc_pd_256:
9127 IsTestPacked = true; // Fallthrough
9128 case Intrinsic::x86_sse41_ptestnzc:
9129 case Intrinsic::x86_avx_ptestnzc_256:
9131 X86CC = X86::COND_A;
9135 SDValue LHS = Op.getOperand(1);
9136 SDValue RHS = Op.getOperand(2);
9137 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9138 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9139 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9140 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9141 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9144 // Fix vector shift instructions where the last operand is a non-immediate
9146 case Intrinsic::x86_sse2_pslli_w:
9147 case Intrinsic::x86_sse2_pslli_d:
9148 case Intrinsic::x86_sse2_pslli_q:
9149 case Intrinsic::x86_sse2_psrli_w:
9150 case Intrinsic::x86_sse2_psrli_d:
9151 case Intrinsic::x86_sse2_psrli_q:
9152 case Intrinsic::x86_sse2_psrai_w:
9153 case Intrinsic::x86_sse2_psrai_d:
9154 case Intrinsic::x86_mmx_pslli_w:
9155 case Intrinsic::x86_mmx_pslli_d:
9156 case Intrinsic::x86_mmx_pslli_q:
9157 case Intrinsic::x86_mmx_psrli_w:
9158 case Intrinsic::x86_mmx_psrli_d:
9159 case Intrinsic::x86_mmx_psrli_q:
9160 case Intrinsic::x86_mmx_psrai_w:
9161 case Intrinsic::x86_mmx_psrai_d: {
9162 SDValue ShAmt = Op.getOperand(2);
9163 if (isa<ConstantSDNode>(ShAmt))
9166 unsigned NewIntNo = 0;
9167 EVT ShAmtVT = MVT::v4i32;
9169 case Intrinsic::x86_sse2_pslli_w:
9170 NewIntNo = Intrinsic::x86_sse2_psll_w;
9172 case Intrinsic::x86_sse2_pslli_d:
9173 NewIntNo = Intrinsic::x86_sse2_psll_d;
9175 case Intrinsic::x86_sse2_pslli_q:
9176 NewIntNo = Intrinsic::x86_sse2_psll_q;
9178 case Intrinsic::x86_sse2_psrli_w:
9179 NewIntNo = Intrinsic::x86_sse2_psrl_w;
9181 case Intrinsic::x86_sse2_psrli_d:
9182 NewIntNo = Intrinsic::x86_sse2_psrl_d;
9184 case Intrinsic::x86_sse2_psrli_q:
9185 NewIntNo = Intrinsic::x86_sse2_psrl_q;
9187 case Intrinsic::x86_sse2_psrai_w:
9188 NewIntNo = Intrinsic::x86_sse2_psra_w;
9190 case Intrinsic::x86_sse2_psrai_d:
9191 NewIntNo = Intrinsic::x86_sse2_psra_d;
9194 ShAmtVT = MVT::v2i32;
9196 case Intrinsic::x86_mmx_pslli_w:
9197 NewIntNo = Intrinsic::x86_mmx_psll_w;
9199 case Intrinsic::x86_mmx_pslli_d:
9200 NewIntNo = Intrinsic::x86_mmx_psll_d;
9202 case Intrinsic::x86_mmx_pslli_q:
9203 NewIntNo = Intrinsic::x86_mmx_psll_q;
9205 case Intrinsic::x86_mmx_psrli_w:
9206 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9208 case Intrinsic::x86_mmx_psrli_d:
9209 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9211 case Intrinsic::x86_mmx_psrli_q:
9212 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9214 case Intrinsic::x86_mmx_psrai_w:
9215 NewIntNo = Intrinsic::x86_mmx_psra_w;
9217 case Intrinsic::x86_mmx_psrai_d:
9218 NewIntNo = Intrinsic::x86_mmx_psra_d;
9220 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9226 // The vector shift intrinsics with scalars uses 32b shift amounts but
9227 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9231 ShOps[1] = DAG.getConstant(0, MVT::i32);
9232 if (ShAmtVT == MVT::v4i32) {
9233 ShOps[2] = DAG.getUNDEF(MVT::i32);
9234 ShOps[3] = DAG.getUNDEF(MVT::i32);
9235 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
9237 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
9238 // FIXME this must be lowered to get rid of the invalid type.
9241 EVT VT = Op.getValueType();
9242 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9243 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9244 DAG.getConstant(NewIntNo, MVT::i32),
9245 Op.getOperand(1), ShAmt);
9250 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9251 SelectionDAG &DAG) const {
9252 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9253 MFI->setReturnAddressIsTaken(true);
9255 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9256 DebugLoc dl = Op.getDebugLoc();
9259 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9261 DAG.getConstant(TD->getPointerSize(),
9262 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9263 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9264 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9266 MachinePointerInfo(), false, false, 0);
9269 // Just load the return address.
9270 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9271 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9272 RetAddrFI, MachinePointerInfo(), false, false, 0);
9275 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9276 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9277 MFI->setFrameAddressIsTaken(true);
9279 EVT VT = Op.getValueType();
9280 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9281 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9282 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9283 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9285 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9286 MachinePointerInfo(),
9291 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9292 SelectionDAG &DAG) const {
9293 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9296 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9297 MachineFunction &MF = DAG.getMachineFunction();
9298 SDValue Chain = Op.getOperand(0);
9299 SDValue Offset = Op.getOperand(1);
9300 SDValue Handler = Op.getOperand(2);
9301 DebugLoc dl = Op.getDebugLoc();
9303 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9304 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9306 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9308 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9309 DAG.getIntPtrConstant(TD->getPointerSize()));
9310 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9311 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9313 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9314 MF.getRegInfo().addLiveOut(StoreAddrReg);
9316 return DAG.getNode(X86ISD::EH_RETURN, dl,
9318 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9321 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
9322 SelectionDAG &DAG) const {
9323 SDValue Root = Op.getOperand(0);
9324 SDValue Trmp = Op.getOperand(1); // trampoline
9325 SDValue FPtr = Op.getOperand(2); // nested function
9326 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9327 DebugLoc dl = Op.getDebugLoc();
9329 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9331 if (Subtarget->is64Bit()) {
9332 SDValue OutChains[6];
9334 // Large code-model.
9335 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9336 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9338 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9339 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9341 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9343 // Load the pointer to the nested function into R11.
9344 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9345 SDValue Addr = Trmp;
9346 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9347 Addr, MachinePointerInfo(TrmpAddr),
9350 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9351 DAG.getConstant(2, MVT::i64));
9352 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9353 MachinePointerInfo(TrmpAddr, 2),
9356 // Load the 'nest' parameter value into R10.
9357 // R10 is specified in X86CallingConv.td
9358 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9359 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9360 DAG.getConstant(10, MVT::i64));
9361 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9362 Addr, MachinePointerInfo(TrmpAddr, 10),
9365 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9366 DAG.getConstant(12, MVT::i64));
9367 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9368 MachinePointerInfo(TrmpAddr, 12),
9371 // Jump to the nested function.
9372 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9373 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9374 DAG.getConstant(20, MVT::i64));
9375 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9376 Addr, MachinePointerInfo(TrmpAddr, 20),
9379 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9380 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9381 DAG.getConstant(22, MVT::i64));
9382 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9383 MachinePointerInfo(TrmpAddr, 22),
9387 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
9388 return DAG.getMergeValues(Ops, 2, dl);
9390 const Function *Func =
9391 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
9392 CallingConv::ID CC = Func->getCallingConv();
9397 llvm_unreachable("Unsupported calling convention");
9398 case CallingConv::C:
9399 case CallingConv::X86_StdCall: {
9400 // Pass 'nest' parameter in ECX.
9401 // Must be kept in sync with X86CallingConv.td
9404 // Check that ECX wasn't needed by an 'inreg' parameter.
9405 FunctionType *FTy = Func->getFunctionType();
9406 const AttrListPtr &Attrs = Func->getAttributes();
9408 if (!Attrs.isEmpty() && !Func->isVarArg()) {
9409 unsigned InRegCount = 0;
9412 for (FunctionType::param_iterator I = FTy->param_begin(),
9413 E = FTy->param_end(); I != E; ++I, ++Idx)
9414 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
9415 // FIXME: should only count parameters that are lowered to integers.
9416 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
9418 if (InRegCount > 2) {
9419 report_fatal_error("Nest register in use - reduce number of inreg"
9425 case CallingConv::X86_FastCall:
9426 case CallingConv::X86_ThisCall:
9427 case CallingConv::Fast:
9428 // Pass 'nest' parameter in EAX.
9429 // Must be kept in sync with X86CallingConv.td
9434 SDValue OutChains[4];
9437 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9438 DAG.getConstant(10, MVT::i32));
9439 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
9441 // This is storing the opcode for MOV32ri.
9442 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
9443 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
9444 OutChains[0] = DAG.getStore(Root, dl,
9445 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
9446 Trmp, MachinePointerInfo(TrmpAddr),
9449 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9450 DAG.getConstant(1, MVT::i32));
9451 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
9452 MachinePointerInfo(TrmpAddr, 1),
9455 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
9456 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9457 DAG.getConstant(5, MVT::i32));
9458 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
9459 MachinePointerInfo(TrmpAddr, 5),
9462 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9463 DAG.getConstant(6, MVT::i32));
9464 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
9465 MachinePointerInfo(TrmpAddr, 6),
9469 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
9470 return DAG.getMergeValues(Ops, 2, dl);
9474 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
9475 SelectionDAG &DAG) const {
9477 The rounding mode is in bits 11:10 of FPSR, and has the following
9484 FLT_ROUNDS, on the other hand, expects the following:
9491 To perform the conversion, we do:
9492 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
9495 MachineFunction &MF = DAG.getMachineFunction();
9496 const TargetMachine &TM = MF.getTarget();
9497 const TargetFrameLowering &TFI = *TM.getFrameLowering();
9498 unsigned StackAlignment = TFI.getStackAlignment();
9499 EVT VT = Op.getValueType();
9500 DebugLoc DL = Op.getDebugLoc();
9502 // Save FP Control Word to stack slot
9503 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
9504 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9507 MachineMemOperand *MMO =
9508 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9509 MachineMemOperand::MOStore, 2, 2);
9511 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
9512 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
9513 DAG.getVTList(MVT::Other),
9514 Ops, 2, MVT::i16, MMO);
9516 // Load FP Control Word from stack slot
9517 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
9518 MachinePointerInfo(), false, false, 0);
9520 // Transform as necessary
9522 DAG.getNode(ISD::SRL, DL, MVT::i16,
9523 DAG.getNode(ISD::AND, DL, MVT::i16,
9524 CWD, DAG.getConstant(0x800, MVT::i16)),
9525 DAG.getConstant(11, MVT::i8));
9527 DAG.getNode(ISD::SRL, DL, MVT::i16,
9528 DAG.getNode(ISD::AND, DL, MVT::i16,
9529 CWD, DAG.getConstant(0x400, MVT::i16)),
9530 DAG.getConstant(9, MVT::i8));
9533 DAG.getNode(ISD::AND, DL, MVT::i16,
9534 DAG.getNode(ISD::ADD, DL, MVT::i16,
9535 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
9536 DAG.getConstant(1, MVT::i16)),
9537 DAG.getConstant(3, MVT::i16));
9540 return DAG.getNode((VT.getSizeInBits() < 16 ?
9541 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
9544 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
9545 EVT VT = Op.getValueType();
9547 unsigned NumBits = VT.getSizeInBits();
9548 DebugLoc dl = Op.getDebugLoc();
9550 Op = Op.getOperand(0);
9551 if (VT == MVT::i8) {
9552 // Zero extend to i32 since there is not an i8 bsr.
9554 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9557 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
9558 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9559 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
9561 // If src is zero (i.e. bsr sets ZF), returns NumBits.
9564 DAG.getConstant(NumBits+NumBits-1, OpVT),
9565 DAG.getConstant(X86::COND_E, MVT::i8),
9568 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9570 // Finally xor with NumBits-1.
9571 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
9574 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9578 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
9579 EVT VT = Op.getValueType();
9581 unsigned NumBits = VT.getSizeInBits();
9582 DebugLoc dl = Op.getDebugLoc();
9584 Op = Op.getOperand(0);
9585 if (VT == MVT::i8) {
9587 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9590 // Issue a bsf (scan bits forward) which also sets EFLAGS.
9591 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9592 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
9594 // If src is zero (i.e. bsf sets ZF), returns NumBits.
9597 DAG.getConstant(NumBits, OpVT),
9598 DAG.getConstant(X86::COND_E, MVT::i8),
9601 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9604 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9608 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
9609 // ones, and then concatenate the result back.
9610 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
9611 EVT VT = Op.getValueType();
9613 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
9614 "Unsupported value type for operation");
9616 int NumElems = VT.getVectorNumElements();
9617 DebugLoc dl = Op.getDebugLoc();
9618 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
9619 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
9621 // Extract the LHS vectors
9622 SDValue LHS = Op.getOperand(0);
9623 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
9624 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
9626 // Extract the RHS vectors
9627 SDValue RHS = Op.getOperand(1);
9628 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
9629 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
9631 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9632 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9634 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9635 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
9636 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
9639 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
9640 assert(Op.getValueType().getSizeInBits() == 256 &&
9641 Op.getValueType().isInteger() &&
9642 "Only handle AVX 256-bit vector integer operation");
9643 return Lower256IntArith(Op, DAG);
9646 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
9647 assert(Op.getValueType().getSizeInBits() == 256 &&
9648 Op.getValueType().isInteger() &&
9649 "Only handle AVX 256-bit vector integer operation");
9650 return Lower256IntArith(Op, DAG);
9653 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
9654 EVT VT = Op.getValueType();
9656 // Decompose 256-bit ops into smaller 128-bit ops.
9657 if (VT.getSizeInBits() == 256)
9658 return Lower256IntArith(Op, DAG);
9660 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
9661 DebugLoc dl = Op.getDebugLoc();
9663 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
9664 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
9665 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
9666 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
9667 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
9669 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
9670 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
9671 // return AloBlo + AloBhi + AhiBlo;
9673 SDValue A = Op.getOperand(0);
9674 SDValue B = Op.getOperand(1);
9676 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9677 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9678 A, DAG.getConstant(32, MVT::i32));
9679 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9680 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9681 B, DAG.getConstant(32, MVT::i32));
9682 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9683 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9685 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9686 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9688 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9689 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9691 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9692 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9693 AloBhi, DAG.getConstant(32, MVT::i32));
9694 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9695 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9696 AhiBlo, DAG.getConstant(32, MVT::i32));
9697 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
9698 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
9702 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
9704 EVT VT = Op.getValueType();
9705 DebugLoc dl = Op.getDebugLoc();
9706 SDValue R = Op.getOperand(0);
9707 SDValue Amt = Op.getOperand(1);
9708 LLVMContext *Context = DAG.getContext();
9710 if (!(Subtarget->hasSSE2() || Subtarget->hasAVX()))
9713 // Decompose 256-bit shifts into smaller 128-bit shifts.
9714 if (VT.getSizeInBits() == 256) {
9715 int NumElems = VT.getVectorNumElements();
9716 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9717 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9719 // Extract the two vectors
9720 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl);
9721 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32),
9724 // Recreate the shift amount vectors
9726 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
9727 // Constant shift amount
9728 SmallVector<SDValue, 4> Amt1Csts;
9729 SmallVector<SDValue, 4> Amt2Csts;
9730 for (int i = 0; i < NumElems/2; ++i)
9731 Amt1Csts.push_back(Amt->getOperand(i));
9732 for (int i = NumElems/2; i < NumElems; ++i)
9733 Amt2Csts.push_back(Amt->getOperand(i));
9735 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
9736 &Amt1Csts[0], NumElems/2);
9737 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
9738 &Amt2Csts[0], NumElems/2);
9740 // Variable shift amount
9741 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl);
9742 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32),
9746 // Issue new vector shifts for the smaller types
9747 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
9748 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
9750 // Concatenate the result back
9751 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
9754 // Optimize shl/srl/sra with constant shift amount.
9755 if (isSplatVector(Amt.getNode())) {
9756 SDValue SclrAmt = Amt->getOperand(0);
9757 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
9758 uint64_t ShiftAmt = C->getZExtValue();
9760 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SHL)
9761 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9762 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9763 R, DAG.getConstant(ShiftAmt, MVT::i32));
9765 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SHL)
9766 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9767 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9768 R, DAG.getConstant(ShiftAmt, MVT::i32));
9770 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SHL)
9771 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9772 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9773 R, DAG.getConstant(ShiftAmt, MVT::i32));
9775 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SRL)
9776 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9777 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9778 R, DAG.getConstant(ShiftAmt, MVT::i32));
9780 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRL)
9781 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9782 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
9783 R, DAG.getConstant(ShiftAmt, MVT::i32));
9785 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRL)
9786 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9787 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
9788 R, DAG.getConstant(ShiftAmt, MVT::i32));
9790 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRA)
9791 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9792 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
9793 R, DAG.getConstant(ShiftAmt, MVT::i32));
9795 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRA)
9796 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9797 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
9798 R, DAG.getConstant(ShiftAmt, MVT::i32));
9802 // Lower SHL with variable shift amount.
9803 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
9804 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9805 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9806 Op.getOperand(1), DAG.getConstant(23, MVT::i32));
9808 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
9810 std::vector<Constant*> CV(4, CI);
9811 Constant *C = ConstantVector::get(CV);
9812 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9813 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9814 MachinePointerInfo::getConstantPool(),
9817 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
9818 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
9819 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
9820 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
9822 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
9824 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9825 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9826 Op.getOperand(1), DAG.getConstant(5, MVT::i32));
9828 ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15));
9829 ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63));
9831 std::vector<Constant*> CVM1(16, CM1);
9832 std::vector<Constant*> CVM2(16, CM2);
9833 Constant *C = ConstantVector::get(CVM1);
9834 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9835 SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9836 MachinePointerInfo::getConstantPool(),
9839 // r = pblendv(r, psllw(r & (char16)15, 4), a);
9840 M = DAG.getNode(ISD::AND, dl, VT, R, M);
9841 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9842 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
9843 DAG.getConstant(4, MVT::i32));
9844 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op);
9846 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
9848 C = ConstantVector::get(CVM2);
9849 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9850 M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9851 MachinePointerInfo::getConstantPool(),
9854 // r = pblendv(r, psllw(r & (char16)63, 2), a);
9855 M = DAG.getNode(ISD::AND, dl, VT, R, M);
9856 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9857 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
9858 DAG.getConstant(2, MVT::i32));
9859 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op);
9861 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
9863 // return pblendv(r, r+r, a);
9864 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT,
9865 R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op);
9871 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
9872 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
9873 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
9874 // looks for this combo and may remove the "setcc" instruction if the "setcc"
9875 // has only one use.
9876 SDNode *N = Op.getNode();
9877 SDValue LHS = N->getOperand(0);
9878 SDValue RHS = N->getOperand(1);
9879 unsigned BaseOp = 0;
9881 DebugLoc DL = Op.getDebugLoc();
9882 switch (Op.getOpcode()) {
9883 default: llvm_unreachable("Unknown ovf instruction!");
9885 // A subtract of one will be selected as a INC. Note that INC doesn't
9886 // set CF, so we can't do this for UADDO.
9887 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
9889 BaseOp = X86ISD::INC;
9893 BaseOp = X86ISD::ADD;
9897 BaseOp = X86ISD::ADD;
9901 // A subtract of one will be selected as a DEC. Note that DEC doesn't
9902 // set CF, so we can't do this for USUBO.
9903 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
9905 BaseOp = X86ISD::DEC;
9909 BaseOp = X86ISD::SUB;
9913 BaseOp = X86ISD::SUB;
9917 BaseOp = X86ISD::SMUL;
9920 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
9921 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
9923 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
9926 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
9927 DAG.getConstant(X86::COND_O, MVT::i32),
9928 SDValue(Sum.getNode(), 2));
9930 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
9934 // Also sets EFLAGS.
9935 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
9936 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
9939 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
9940 DAG.getConstant(Cond, MVT::i32),
9941 SDValue(Sum.getNode(), 1));
9943 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
9946 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const{
9947 DebugLoc dl = Op.getDebugLoc();
9948 SDNode* Node = Op.getNode();
9949 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
9950 EVT VT = Node->getValueType(0);
9952 if (Subtarget->hasSSE2() && VT.isVector()) {
9953 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
9954 ExtraVT.getScalarType().getSizeInBits();
9955 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
9957 unsigned SHLIntrinsicsID = 0;
9958 unsigned SRAIntrinsicsID = 0;
9959 switch (VT.getSimpleVT().SimpleTy) {
9963 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_q;
9964 SRAIntrinsicsID = 0;
9968 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_d;
9969 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_d;
9973 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_w;
9974 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_w;
9979 SDValue Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9980 DAG.getConstant(SHLIntrinsicsID, MVT::i32),
9981 Node->getOperand(0), ShAmt);
9983 // In case of 1 bit sext, no need to shr
9984 if (ExtraVT.getScalarType().getSizeInBits() == 1) return Tmp1;
9986 if (SRAIntrinsicsID) {
9987 Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9988 DAG.getConstant(SRAIntrinsicsID, MVT::i32),
9998 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
9999 DebugLoc dl = Op.getDebugLoc();
10001 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10002 // There isn't any reason to disable it if the target processor supports it.
10003 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
10004 SDValue Chain = Op.getOperand(0);
10005 SDValue Zero = DAG.getConstant(0, MVT::i32);
10007 DAG.getRegister(X86::ESP, MVT::i32), // Base
10008 DAG.getTargetConstant(1, MVT::i8), // Scale
10009 DAG.getRegister(0, MVT::i32), // Index
10010 DAG.getTargetConstant(0, MVT::i32), // Disp
10011 DAG.getRegister(0, MVT::i32), // Segment.
10016 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10017 array_lengthof(Ops));
10018 return SDValue(Res, 0);
10021 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10023 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10025 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10026 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10027 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10028 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10030 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10031 if (!Op1 && !Op2 && !Op3 && Op4)
10032 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10034 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10035 if (Op1 && !Op2 && !Op3 && !Op4)
10036 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10038 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10040 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10043 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10044 SelectionDAG &DAG) const {
10045 DebugLoc dl = Op.getDebugLoc();
10046 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10047 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10048 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10049 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10051 // The only fence that needs an instruction is a sequentially-consistent
10052 // cross-thread fence.
10053 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10054 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10055 // no-sse2). There isn't any reason to disable it if the target processor
10057 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
10058 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10060 SDValue Chain = Op.getOperand(0);
10061 SDValue Zero = DAG.getConstant(0, MVT::i32);
10063 DAG.getRegister(X86::ESP, MVT::i32), // Base
10064 DAG.getTargetConstant(1, MVT::i8), // Scale
10065 DAG.getRegister(0, MVT::i32), // Index
10066 DAG.getTargetConstant(0, MVT::i32), // Disp
10067 DAG.getRegister(0, MVT::i32), // Segment.
10072 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10073 array_lengthof(Ops));
10074 return SDValue(Res, 0);
10077 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10078 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10082 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10083 EVT T = Op.getValueType();
10084 DebugLoc DL = Op.getDebugLoc();
10087 switch(T.getSimpleVT().SimpleTy) {
10089 assert(false && "Invalid value type!");
10090 case MVT::i8: Reg = X86::AL; size = 1; break;
10091 case MVT::i16: Reg = X86::AX; size = 2; break;
10092 case MVT::i32: Reg = X86::EAX; size = 4; break;
10094 assert(Subtarget->is64Bit() && "Node not type legal!");
10095 Reg = X86::RAX; size = 8;
10098 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10099 Op.getOperand(2), SDValue());
10100 SDValue Ops[] = { cpIn.getValue(0),
10103 DAG.getTargetConstant(size, MVT::i8),
10104 cpIn.getValue(1) };
10105 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10106 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10107 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10110 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10114 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10115 SelectionDAG &DAG) const {
10116 assert(Subtarget->is64Bit() && "Result not type legalized?");
10117 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10118 SDValue TheChain = Op.getOperand(0);
10119 DebugLoc dl = Op.getDebugLoc();
10120 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10121 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10122 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10124 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10125 DAG.getConstant(32, MVT::i8));
10127 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10130 return DAG.getMergeValues(Ops, 2, dl);
10133 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10134 SelectionDAG &DAG) const {
10135 EVT SrcVT = Op.getOperand(0).getValueType();
10136 EVT DstVT = Op.getValueType();
10137 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
10138 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10139 assert((DstVT == MVT::i64 ||
10140 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10141 "Unexpected custom BITCAST");
10142 // i64 <=> MMX conversions are Legal.
10143 if (SrcVT==MVT::i64 && DstVT.isVector())
10145 if (DstVT==MVT::i64 && SrcVT.isVector())
10147 // MMX <=> MMX conversions are Legal.
10148 if (SrcVT.isVector() && DstVT.isVector())
10150 // All other conversions need to be expanded.
10154 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10155 SDNode *Node = Op.getNode();
10156 DebugLoc dl = Node->getDebugLoc();
10157 EVT T = Node->getValueType(0);
10158 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10159 DAG.getConstant(0, T), Node->getOperand(2));
10160 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10161 cast<AtomicSDNode>(Node)->getMemoryVT(),
10162 Node->getOperand(0),
10163 Node->getOperand(1), negOp,
10164 cast<AtomicSDNode>(Node)->getSrcValue(),
10165 cast<AtomicSDNode>(Node)->getAlignment(),
10166 cast<AtomicSDNode>(Node)->getOrdering(),
10167 cast<AtomicSDNode>(Node)->getSynchScope());
10170 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10171 SDNode *Node = Op.getNode();
10172 DebugLoc dl = Node->getDebugLoc();
10173 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10175 // Convert seq_cst store -> xchg
10176 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10177 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10178 // (The only way to get a 16-byte store is cmpxchg16b)
10179 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10180 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10181 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10182 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10183 cast<AtomicSDNode>(Node)->getMemoryVT(),
10184 Node->getOperand(0),
10185 Node->getOperand(1), Node->getOperand(2),
10186 cast<AtomicSDNode>(Node)->getMemOperand(),
10187 cast<AtomicSDNode>(Node)->getOrdering(),
10188 cast<AtomicSDNode>(Node)->getSynchScope());
10189 return Swap.getValue(1);
10191 // Other atomic stores have a simple pattern.
10195 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10196 EVT VT = Op.getNode()->getValueType(0);
10198 // Let legalize expand this if it isn't a legal type yet.
10199 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10202 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10205 bool ExtraOp = false;
10206 switch (Op.getOpcode()) {
10207 default: assert(0 && "Invalid code");
10208 case ISD::ADDC: Opc = X86ISD::ADD; break;
10209 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10210 case ISD::SUBC: Opc = X86ISD::SUB; break;
10211 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10215 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10217 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10218 Op.getOperand(1), Op.getOperand(2));
10221 /// LowerOperation - Provide custom lowering hooks for some operations.
10223 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10224 switch (Op.getOpcode()) {
10225 default: llvm_unreachable("Should not custom lower this!");
10226 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10227 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10228 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10229 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10230 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10231 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10232 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10233 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10234 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10235 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10236 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10237 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10238 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10239 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10240 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10241 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10242 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10243 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10244 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10245 case ISD::SHL_PARTS:
10246 case ISD::SRA_PARTS:
10247 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10248 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10249 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10250 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10251 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10252 case ISD::FABS: return LowerFABS(Op, DAG);
10253 case ISD::FNEG: return LowerFNEG(Op, DAG);
10254 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10255 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10256 case ISD::SETCC: return LowerSETCC(Op, DAG);
10257 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
10258 case ISD::SELECT: return LowerSELECT(Op, DAG);
10259 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10260 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10261 case ISD::VASTART: return LowerVASTART(Op, DAG);
10262 case ISD::VAARG: return LowerVAARG(Op, DAG);
10263 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10264 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10265 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10266 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10267 case ISD::FRAME_TO_ARGS_OFFSET:
10268 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10269 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10270 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10271 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
10272 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10273 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10274 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10275 case ISD::MUL: return LowerMUL(Op, DAG);
10278 case ISD::SHL: return LowerShift(Op, DAG);
10284 case ISD::UMULO: return LowerXALUO(Op, DAG);
10285 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10286 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10290 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10291 case ISD::ADD: return LowerADD(Op, DAG);
10292 case ISD::SUB: return LowerSUB(Op, DAG);
10296 static void ReplaceATOMIC_LOAD(SDNode *Node,
10297 SmallVectorImpl<SDValue> &Results,
10298 SelectionDAG &DAG) {
10299 DebugLoc dl = Node->getDebugLoc();
10300 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10302 // Convert wide load -> cmpxchg8b/cmpxchg16b
10303 // FIXME: On 32-bit, load -> fild or movq would be more efficient
10304 // (The only way to get a 16-byte load is cmpxchg16b)
10305 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
10306 SDValue Zero = DAG.getConstant(0, cast<AtomicSDNode>(Node)->getMemoryVT());
10307 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
10308 cast<AtomicSDNode>(Node)->getMemoryVT(),
10309 Node->getOperand(0),
10310 Node->getOperand(1), Zero, Zero,
10311 cast<AtomicSDNode>(Node)->getMemOperand(),
10312 cast<AtomicSDNode>(Node)->getOrdering(),
10313 cast<AtomicSDNode>(Node)->getSynchScope());
10314 Results.push_back(Swap.getValue(0));
10315 Results.push_back(Swap.getValue(1));
10318 void X86TargetLowering::
10319 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10320 SelectionDAG &DAG, unsigned NewOp) const {
10321 EVT T = Node->getValueType(0);
10322 DebugLoc dl = Node->getDebugLoc();
10323 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
10325 SDValue Chain = Node->getOperand(0);
10326 SDValue In1 = Node->getOperand(1);
10327 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10328 Node->getOperand(2), DAG.getIntPtrConstant(0));
10329 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10330 Node->getOperand(2), DAG.getIntPtrConstant(1));
10331 SDValue Ops[] = { Chain, In1, In2L, In2H };
10332 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
10334 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
10335 cast<MemSDNode>(Node)->getMemOperand());
10336 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
10337 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10338 Results.push_back(Result.getValue(2));
10341 /// ReplaceNodeResults - Replace a node with an illegal result type
10342 /// with a new node built out of custom code.
10343 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
10344 SmallVectorImpl<SDValue>&Results,
10345 SelectionDAG &DAG) const {
10346 DebugLoc dl = N->getDebugLoc();
10347 switch (N->getOpcode()) {
10349 assert(false && "Do not know how to custom type legalize this operation!");
10351 case ISD::SIGN_EXTEND_INREG:
10356 // We don't want to expand or promote these.
10358 case ISD::FP_TO_SINT: {
10359 std::pair<SDValue,SDValue> Vals =
10360 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
10361 SDValue FIST = Vals.first, StackSlot = Vals.second;
10362 if (FIST.getNode() != 0) {
10363 EVT VT = N->getValueType(0);
10364 // Return a load from the stack slot.
10365 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
10366 MachinePointerInfo(), false, false, 0));
10370 case ISD::READCYCLECOUNTER: {
10371 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10372 SDValue TheChain = N->getOperand(0);
10373 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10374 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
10376 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
10378 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
10379 SDValue Ops[] = { eax, edx };
10380 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
10381 Results.push_back(edx.getValue(1));
10384 case ISD::ATOMIC_CMP_SWAP: {
10385 EVT T = N->getValueType(0);
10386 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
10387 SDValue cpInL, cpInH;
10388 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
10389 DAG.getConstant(0, MVT::i32));
10390 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
10391 DAG.getConstant(1, MVT::i32));
10392 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
10393 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
10394 cpInL.getValue(1));
10395 SDValue swapInL, swapInH;
10396 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
10397 DAG.getConstant(0, MVT::i32));
10398 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
10399 DAG.getConstant(1, MVT::i32));
10400 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
10401 cpInH.getValue(1));
10402 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
10403 swapInL.getValue(1));
10404 SDValue Ops[] = { swapInH.getValue(0),
10406 swapInH.getValue(1) };
10407 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10408 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
10409 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG8_DAG, dl, Tys,
10411 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
10412 MVT::i32, Result.getValue(1));
10413 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
10414 MVT::i32, cpOutL.getValue(2));
10415 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
10416 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10417 Results.push_back(cpOutH.getValue(1));
10420 case ISD::ATOMIC_LOAD_ADD:
10421 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
10423 case ISD::ATOMIC_LOAD_AND:
10424 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
10426 case ISD::ATOMIC_LOAD_NAND:
10427 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
10429 case ISD::ATOMIC_LOAD_OR:
10430 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
10432 case ISD::ATOMIC_LOAD_SUB:
10433 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
10435 case ISD::ATOMIC_LOAD_XOR:
10436 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
10438 case ISD::ATOMIC_SWAP:
10439 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
10441 case ISD::ATOMIC_LOAD:
10442 ReplaceATOMIC_LOAD(N, Results, DAG);
10446 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
10448 default: return NULL;
10449 case X86ISD::BSF: return "X86ISD::BSF";
10450 case X86ISD::BSR: return "X86ISD::BSR";
10451 case X86ISD::SHLD: return "X86ISD::SHLD";
10452 case X86ISD::SHRD: return "X86ISD::SHRD";
10453 case X86ISD::FAND: return "X86ISD::FAND";
10454 case X86ISD::FOR: return "X86ISD::FOR";
10455 case X86ISD::FXOR: return "X86ISD::FXOR";
10456 case X86ISD::FSRL: return "X86ISD::FSRL";
10457 case X86ISD::FILD: return "X86ISD::FILD";
10458 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
10459 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
10460 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
10461 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
10462 case X86ISD::FLD: return "X86ISD::FLD";
10463 case X86ISD::FST: return "X86ISD::FST";
10464 case X86ISD::CALL: return "X86ISD::CALL";
10465 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
10466 case X86ISD::BT: return "X86ISD::BT";
10467 case X86ISD::CMP: return "X86ISD::CMP";
10468 case X86ISD::COMI: return "X86ISD::COMI";
10469 case X86ISD::UCOMI: return "X86ISD::UCOMI";
10470 case X86ISD::SETCC: return "X86ISD::SETCC";
10471 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
10472 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
10473 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
10474 case X86ISD::CMOV: return "X86ISD::CMOV";
10475 case X86ISD::BRCOND: return "X86ISD::BRCOND";
10476 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
10477 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
10478 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
10479 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
10480 case X86ISD::Wrapper: return "X86ISD::Wrapper";
10481 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
10482 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
10483 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
10484 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
10485 case X86ISD::PINSRB: return "X86ISD::PINSRB";
10486 case X86ISD::PINSRW: return "X86ISD::PINSRW";
10487 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
10488 case X86ISD::ANDNP: return "X86ISD::ANDNP";
10489 case X86ISD::PSIGNB: return "X86ISD::PSIGNB";
10490 case X86ISD::PSIGNW: return "X86ISD::PSIGNW";
10491 case X86ISD::PSIGND: return "X86ISD::PSIGND";
10492 case X86ISD::PBLENDVB: return "X86ISD::PBLENDVB";
10493 case X86ISD::FMAX: return "X86ISD::FMAX";
10494 case X86ISD::FMIN: return "X86ISD::FMIN";
10495 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
10496 case X86ISD::FRCP: return "X86ISD::FRCP";
10497 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
10498 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
10499 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
10500 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
10501 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
10502 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
10503 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
10504 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
10505 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
10506 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
10507 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
10508 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
10509 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
10510 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
10511 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
10512 case X86ISD::VSHL: return "X86ISD::VSHL";
10513 case X86ISD::VSRL: return "X86ISD::VSRL";
10514 case X86ISD::CMPPD: return "X86ISD::CMPPD";
10515 case X86ISD::CMPPS: return "X86ISD::CMPPS";
10516 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
10517 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
10518 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
10519 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
10520 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
10521 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
10522 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
10523 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
10524 case X86ISD::ADD: return "X86ISD::ADD";
10525 case X86ISD::SUB: return "X86ISD::SUB";
10526 case X86ISD::ADC: return "X86ISD::ADC";
10527 case X86ISD::SBB: return "X86ISD::SBB";
10528 case X86ISD::SMUL: return "X86ISD::SMUL";
10529 case X86ISD::UMUL: return "X86ISD::UMUL";
10530 case X86ISD::INC: return "X86ISD::INC";
10531 case X86ISD::DEC: return "X86ISD::DEC";
10532 case X86ISD::OR: return "X86ISD::OR";
10533 case X86ISD::XOR: return "X86ISD::XOR";
10534 case X86ISD::AND: return "X86ISD::AND";
10535 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
10536 case X86ISD::PTEST: return "X86ISD::PTEST";
10537 case X86ISD::TESTP: return "X86ISD::TESTP";
10538 case X86ISD::PALIGN: return "X86ISD::PALIGN";
10539 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
10540 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
10541 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD";
10542 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
10543 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD";
10544 case X86ISD::SHUFPS: return "X86ISD::SHUFPS";
10545 case X86ISD::SHUFPD: return "X86ISD::SHUFPD";
10546 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
10547 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
10548 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
10549 case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD";
10550 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
10551 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
10552 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
10553 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
10554 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
10555 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD";
10556 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD";
10557 case X86ISD::MOVSD: return "X86ISD::MOVSD";
10558 case X86ISD::MOVSS: return "X86ISD::MOVSS";
10559 case X86ISD::UNPCKLPS: return "X86ISD::UNPCKLPS";
10560 case X86ISD::UNPCKLPD: return "X86ISD::UNPCKLPD";
10561 case X86ISD::VUNPCKLPDY: return "X86ISD::VUNPCKLPDY";
10562 case X86ISD::UNPCKHPS: return "X86ISD::UNPCKHPS";
10563 case X86ISD::UNPCKHPD: return "X86ISD::UNPCKHPD";
10564 case X86ISD::PUNPCKLBW: return "X86ISD::PUNPCKLBW";
10565 case X86ISD::PUNPCKLWD: return "X86ISD::PUNPCKLWD";
10566 case X86ISD::PUNPCKLDQ: return "X86ISD::PUNPCKLDQ";
10567 case X86ISD::PUNPCKLQDQ: return "X86ISD::PUNPCKLQDQ";
10568 case X86ISD::PUNPCKHBW: return "X86ISD::PUNPCKHBW";
10569 case X86ISD::PUNPCKHWD: return "X86ISD::PUNPCKHWD";
10570 case X86ISD::PUNPCKHDQ: return "X86ISD::PUNPCKHDQ";
10571 case X86ISD::PUNPCKHQDQ: return "X86ISD::PUNPCKHQDQ";
10572 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
10573 case X86ISD::VPERMILPS: return "X86ISD::VPERMILPS";
10574 case X86ISD::VPERMILPSY: return "X86ISD::VPERMILPSY";
10575 case X86ISD::VPERMILPD: return "X86ISD::VPERMILPD";
10576 case X86ISD::VPERMILPDY: return "X86ISD::VPERMILPDY";
10577 case X86ISD::VPERM2F128: return "X86ISD::VPERM2F128";
10578 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
10579 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
10580 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
10581 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
10585 // isLegalAddressingMode - Return true if the addressing mode represented
10586 // by AM is legal for this target, for a load/store of the specified type.
10587 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
10589 // X86 supports extremely general addressing modes.
10590 CodeModel::Model M = getTargetMachine().getCodeModel();
10591 Reloc::Model R = getTargetMachine().getRelocationModel();
10593 // X86 allows a sign-extended 32-bit immediate field as a displacement.
10594 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
10599 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
10601 // If a reference to this global requires an extra load, we can't fold it.
10602 if (isGlobalStubReference(GVFlags))
10605 // If BaseGV requires a register for the PIC base, we cannot also have a
10606 // BaseReg specified.
10607 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
10610 // If lower 4G is not available, then we must use rip-relative addressing.
10611 if ((M != CodeModel::Small || R != Reloc::Static) &&
10612 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
10616 switch (AM.Scale) {
10622 // These scales always work.
10627 // These scales are formed with basereg+scalereg. Only accept if there is
10632 default: // Other stuff never works.
10640 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
10641 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
10643 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
10644 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
10645 if (NumBits1 <= NumBits2)
10650 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
10651 if (!VT1.isInteger() || !VT2.isInteger())
10653 unsigned NumBits1 = VT1.getSizeInBits();
10654 unsigned NumBits2 = VT2.getSizeInBits();
10655 if (NumBits1 <= NumBits2)
10660 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
10661 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
10662 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
10665 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
10666 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
10667 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
10670 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
10671 // i16 instructions are longer (0x66 prefix) and potentially slower.
10672 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
10675 /// isShuffleMaskLegal - Targets can use this to indicate that they only
10676 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
10677 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
10678 /// are assumed to be legal.
10680 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
10682 // Very little shuffling can be done for 64-bit vectors right now.
10683 if (VT.getSizeInBits() == 64)
10684 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3());
10686 // FIXME: pshufb, blends, shifts.
10687 return (VT.getVectorNumElements() == 2 ||
10688 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
10689 isMOVLMask(M, VT) ||
10690 isSHUFPMask(M, VT) ||
10691 isPSHUFDMask(M, VT) ||
10692 isPSHUFHWMask(M, VT) ||
10693 isPSHUFLWMask(M, VT) ||
10694 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
10695 isUNPCKLMask(M, VT) ||
10696 isUNPCKHMask(M, VT) ||
10697 isUNPCKL_v_undef_Mask(M, VT) ||
10698 isUNPCKH_v_undef_Mask(M, VT));
10702 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
10704 unsigned NumElts = VT.getVectorNumElements();
10705 // FIXME: This collection of masks seems suspect.
10708 if (NumElts == 4 && VT.getSizeInBits() == 128) {
10709 return (isMOVLMask(Mask, VT) ||
10710 isCommutedMOVLMask(Mask, VT, true) ||
10711 isSHUFPMask(Mask, VT) ||
10712 isCommutedSHUFPMask(Mask, VT));
10717 //===----------------------------------------------------------------------===//
10718 // X86 Scheduler Hooks
10719 //===----------------------------------------------------------------------===//
10721 // private utility function
10722 MachineBasicBlock *
10723 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
10724 MachineBasicBlock *MBB,
10731 TargetRegisterClass *RC,
10732 bool invSrc) const {
10733 // For the atomic bitwise operator, we generate
10736 // ld t1 = [bitinstr.addr]
10737 // op t2 = t1, [bitinstr.val]
10739 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
10741 // fallthrough -->nextMBB
10742 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10743 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
10744 MachineFunction::iterator MBBIter = MBB;
10747 /// First build the CFG
10748 MachineFunction *F = MBB->getParent();
10749 MachineBasicBlock *thisMBB = MBB;
10750 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
10751 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
10752 F->insert(MBBIter, newMBB);
10753 F->insert(MBBIter, nextMBB);
10755 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
10756 nextMBB->splice(nextMBB->begin(), thisMBB,
10757 llvm::next(MachineBasicBlock::iterator(bInstr)),
10759 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
10761 // Update thisMBB to fall through to newMBB
10762 thisMBB->addSuccessor(newMBB);
10764 // newMBB jumps to itself and fall through to nextMBB
10765 newMBB->addSuccessor(nextMBB);
10766 newMBB->addSuccessor(newMBB);
10768 // Insert instructions into newMBB based on incoming instruction
10769 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
10770 "unexpected number of operands");
10771 DebugLoc dl = bInstr->getDebugLoc();
10772 MachineOperand& destOper = bInstr->getOperand(0);
10773 MachineOperand* argOpers[2 + X86::AddrNumOperands];
10774 int numArgs = bInstr->getNumOperands() - 1;
10775 for (int i=0; i < numArgs; ++i)
10776 argOpers[i] = &bInstr->getOperand(i+1);
10778 // x86 address has 4 operands: base, index, scale, and displacement
10779 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
10780 int valArgIndx = lastAddrIndx + 1;
10782 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
10783 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
10784 for (int i=0; i <= lastAddrIndx; ++i)
10785 (*MIB).addOperand(*argOpers[i]);
10787 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
10789 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
10794 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
10795 assert((argOpers[valArgIndx]->isReg() ||
10796 argOpers[valArgIndx]->isImm()) &&
10797 "invalid operand");
10798 if (argOpers[valArgIndx]->isReg())
10799 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
10801 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
10803 (*MIB).addOperand(*argOpers[valArgIndx]);
10805 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
10808 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
10809 for (int i=0; i <= lastAddrIndx; ++i)
10810 (*MIB).addOperand(*argOpers[i]);
10812 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
10813 (*MIB).setMemRefs(bInstr->memoperands_begin(),
10814 bInstr->memoperands_end());
10816 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
10817 MIB.addReg(EAXreg);
10820 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
10822 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
10826 // private utility function: 64 bit atomics on 32 bit host.
10827 MachineBasicBlock *
10828 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
10829 MachineBasicBlock *MBB,
10834 bool invSrc) const {
10835 // For the atomic bitwise operator, we generate
10836 // thisMBB (instructions are in pairs, except cmpxchg8b)
10837 // ld t1,t2 = [bitinstr.addr]
10839 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
10840 // op t5, t6 <- out1, out2, [bitinstr.val]
10841 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
10842 // mov ECX, EBX <- t5, t6
10843 // mov EAX, EDX <- t1, t2
10844 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
10845 // mov t3, t4 <- EAX, EDX
10847 // result in out1, out2
10848 // fallthrough -->nextMBB
10850 const TargetRegisterClass *RC = X86::GR32RegisterClass;
10851 const unsigned LoadOpc = X86::MOV32rm;
10852 const unsigned NotOpc = X86::NOT32r;
10853 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10854 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
10855 MachineFunction::iterator MBBIter = MBB;
10858 /// First build the CFG
10859 MachineFunction *F = MBB->getParent();
10860 MachineBasicBlock *thisMBB = MBB;
10861 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
10862 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
10863 F->insert(MBBIter, newMBB);
10864 F->insert(MBBIter, nextMBB);
10866 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
10867 nextMBB->splice(nextMBB->begin(), thisMBB,
10868 llvm::next(MachineBasicBlock::iterator(bInstr)),
10870 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
10872 // Update thisMBB to fall through to newMBB
10873 thisMBB->addSuccessor(newMBB);
10875 // newMBB jumps to itself and fall through to nextMBB
10876 newMBB->addSuccessor(nextMBB);
10877 newMBB->addSuccessor(newMBB);
10879 DebugLoc dl = bInstr->getDebugLoc();
10880 // Insert instructions into newMBB based on incoming instruction
10881 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
10882 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
10883 "unexpected number of operands");
10884 MachineOperand& dest1Oper = bInstr->getOperand(0);
10885 MachineOperand& dest2Oper = bInstr->getOperand(1);
10886 MachineOperand* argOpers[2 + X86::AddrNumOperands];
10887 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
10888 argOpers[i] = &bInstr->getOperand(i+2);
10890 // We use some of the operands multiple times, so conservatively just
10891 // clear any kill flags that might be present.
10892 if (argOpers[i]->isReg() && argOpers[i]->isUse())
10893 argOpers[i]->setIsKill(false);
10896 // x86 address has 5 operands: base, index, scale, displacement, and segment.
10897 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
10899 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
10900 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
10901 for (int i=0; i <= lastAddrIndx; ++i)
10902 (*MIB).addOperand(*argOpers[i]);
10903 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
10904 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
10905 // add 4 to displacement.
10906 for (int i=0; i <= lastAddrIndx-2; ++i)
10907 (*MIB).addOperand(*argOpers[i]);
10908 MachineOperand newOp3 = *(argOpers[3]);
10909 if (newOp3.isImm())
10910 newOp3.setImm(newOp3.getImm()+4);
10912 newOp3.setOffset(newOp3.getOffset()+4);
10913 (*MIB).addOperand(newOp3);
10914 (*MIB).addOperand(*argOpers[lastAddrIndx]);
10916 // t3/4 are defined later, at the bottom of the loop
10917 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
10918 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
10919 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
10920 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
10921 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
10922 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
10924 // The subsequent operations should be using the destination registers of
10925 //the PHI instructions.
10927 t1 = F->getRegInfo().createVirtualRegister(RC);
10928 t2 = F->getRegInfo().createVirtualRegister(RC);
10929 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
10930 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
10932 t1 = dest1Oper.getReg();
10933 t2 = dest2Oper.getReg();
10936 int valArgIndx = lastAddrIndx + 1;
10937 assert((argOpers[valArgIndx]->isReg() ||
10938 argOpers[valArgIndx]->isImm()) &&
10939 "invalid operand");
10940 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
10941 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
10942 if (argOpers[valArgIndx]->isReg())
10943 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
10945 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
10946 if (regOpcL != X86::MOV32rr)
10948 (*MIB).addOperand(*argOpers[valArgIndx]);
10949 assert(argOpers[valArgIndx + 1]->isReg() ==
10950 argOpers[valArgIndx]->isReg());
10951 assert(argOpers[valArgIndx + 1]->isImm() ==
10952 argOpers[valArgIndx]->isImm());
10953 if (argOpers[valArgIndx + 1]->isReg())
10954 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
10956 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
10957 if (regOpcH != X86::MOV32rr)
10959 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
10961 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
10963 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
10966 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
10968 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
10971 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
10972 for (int i=0; i <= lastAddrIndx; ++i)
10973 (*MIB).addOperand(*argOpers[i]);
10975 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
10976 (*MIB).setMemRefs(bInstr->memoperands_begin(),
10977 bInstr->memoperands_end());
10979 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
10980 MIB.addReg(X86::EAX);
10981 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
10982 MIB.addReg(X86::EDX);
10985 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
10987 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
10991 // private utility function
10992 MachineBasicBlock *
10993 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
10994 MachineBasicBlock *MBB,
10995 unsigned cmovOpc) const {
10996 // For the atomic min/max operator, we generate
10999 // ld t1 = [min/max.addr]
11000 // mov t2 = [min/max.val]
11002 // cmov[cond] t2 = t1
11004 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11006 // fallthrough -->nextMBB
11008 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11009 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11010 MachineFunction::iterator MBBIter = MBB;
11013 /// First build the CFG
11014 MachineFunction *F = MBB->getParent();
11015 MachineBasicBlock *thisMBB = MBB;
11016 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11017 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11018 F->insert(MBBIter, newMBB);
11019 F->insert(MBBIter, nextMBB);
11021 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11022 nextMBB->splice(nextMBB->begin(), thisMBB,
11023 llvm::next(MachineBasicBlock::iterator(mInstr)),
11025 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11027 // Update thisMBB to fall through to newMBB
11028 thisMBB->addSuccessor(newMBB);
11030 // newMBB jumps to newMBB and fall through to nextMBB
11031 newMBB->addSuccessor(nextMBB);
11032 newMBB->addSuccessor(newMBB);
11034 DebugLoc dl = mInstr->getDebugLoc();
11035 // Insert instructions into newMBB based on incoming instruction
11036 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11037 "unexpected number of operands");
11038 MachineOperand& destOper = mInstr->getOperand(0);
11039 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11040 int numArgs = mInstr->getNumOperands() - 1;
11041 for (int i=0; i < numArgs; ++i)
11042 argOpers[i] = &mInstr->getOperand(i+1);
11044 // x86 address has 4 operands: base, index, scale, and displacement
11045 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11046 int valArgIndx = lastAddrIndx + 1;
11048 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11049 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11050 for (int i=0; i <= lastAddrIndx; ++i)
11051 (*MIB).addOperand(*argOpers[i]);
11053 // We only support register and immediate values
11054 assert((argOpers[valArgIndx]->isReg() ||
11055 argOpers[valArgIndx]->isImm()) &&
11056 "invalid operand");
11058 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11059 if (argOpers[valArgIndx]->isReg())
11060 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11062 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11063 (*MIB).addOperand(*argOpers[valArgIndx]);
11065 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11068 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11073 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11074 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11078 // Cmp and exchange if none has modified the memory location
11079 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11080 for (int i=0; i <= lastAddrIndx; ++i)
11081 (*MIB).addOperand(*argOpers[i]);
11083 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11084 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11085 mInstr->memoperands_end());
11087 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11088 MIB.addReg(X86::EAX);
11091 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11093 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11097 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11098 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11099 // in the .td file.
11100 MachineBasicBlock *
11101 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11102 unsigned numArgs, bool memArg) const {
11103 assert((Subtarget->hasSSE42() || Subtarget->hasAVX()) &&
11104 "Target must have SSE4.2 or AVX features enabled");
11106 DebugLoc dl = MI->getDebugLoc();
11107 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11109 if (!Subtarget->hasAVX()) {
11111 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11113 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11116 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11118 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11121 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11122 for (unsigned i = 0; i < numArgs; ++i) {
11123 MachineOperand &Op = MI->getOperand(i+1);
11124 if (!(Op.isReg() && Op.isImplicit()))
11125 MIB.addOperand(Op);
11127 BuildMI(*BB, MI, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
11128 .addReg(X86::XMM0);
11130 MI->eraseFromParent();
11134 MachineBasicBlock *
11135 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11136 DebugLoc dl = MI->getDebugLoc();
11137 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11139 // Address into RAX/EAX, other two args into ECX, EDX.
11140 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11141 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11142 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11143 for (int i = 0; i < X86::AddrNumOperands; ++i)
11144 MIB.addOperand(MI->getOperand(i));
11146 unsigned ValOps = X86::AddrNumOperands;
11147 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11148 .addReg(MI->getOperand(ValOps).getReg());
11149 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11150 .addReg(MI->getOperand(ValOps+1).getReg());
11152 // The instruction doesn't actually take any operands though.
11153 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11155 MI->eraseFromParent(); // The pseudo is gone now.
11159 MachineBasicBlock *
11160 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
11161 DebugLoc dl = MI->getDebugLoc();
11162 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11164 // First arg in ECX, the second in EAX.
11165 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11166 .addReg(MI->getOperand(0).getReg());
11167 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11168 .addReg(MI->getOperand(1).getReg());
11170 // The instruction doesn't actually take any operands though.
11171 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11173 MI->eraseFromParent(); // The pseudo is gone now.
11177 MachineBasicBlock *
11178 X86TargetLowering::EmitVAARG64WithCustomInserter(
11180 MachineBasicBlock *MBB) const {
11181 // Emit va_arg instruction on X86-64.
11183 // Operands to this pseudo-instruction:
11184 // 0 ) Output : destination address (reg)
11185 // 1-5) Input : va_list address (addr, i64mem)
11186 // 6 ) ArgSize : Size (in bytes) of vararg type
11187 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11188 // 8 ) Align : Alignment of type
11189 // 9 ) EFLAGS (implicit-def)
11191 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11192 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11194 unsigned DestReg = MI->getOperand(0).getReg();
11195 MachineOperand &Base = MI->getOperand(1);
11196 MachineOperand &Scale = MI->getOperand(2);
11197 MachineOperand &Index = MI->getOperand(3);
11198 MachineOperand &Disp = MI->getOperand(4);
11199 MachineOperand &Segment = MI->getOperand(5);
11200 unsigned ArgSize = MI->getOperand(6).getImm();
11201 unsigned ArgMode = MI->getOperand(7).getImm();
11202 unsigned Align = MI->getOperand(8).getImm();
11204 // Memory Reference
11205 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11206 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11207 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11209 // Machine Information
11210 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11211 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11212 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11213 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11214 DebugLoc DL = MI->getDebugLoc();
11216 // struct va_list {
11219 // i64 overflow_area (address)
11220 // i64 reg_save_area (address)
11222 // sizeof(va_list) = 24
11223 // alignment(va_list) = 8
11225 unsigned TotalNumIntRegs = 6;
11226 unsigned TotalNumXMMRegs = 8;
11227 bool UseGPOffset = (ArgMode == 1);
11228 bool UseFPOffset = (ArgMode == 2);
11229 unsigned MaxOffset = TotalNumIntRegs * 8 +
11230 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11232 /* Align ArgSize to a multiple of 8 */
11233 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11234 bool NeedsAlign = (Align > 8);
11236 MachineBasicBlock *thisMBB = MBB;
11237 MachineBasicBlock *overflowMBB;
11238 MachineBasicBlock *offsetMBB;
11239 MachineBasicBlock *endMBB;
11241 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11242 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11243 unsigned OffsetReg = 0;
11245 if (!UseGPOffset && !UseFPOffset) {
11246 // If we only pull from the overflow region, we don't create a branch.
11247 // We don't need to alter control flow.
11248 OffsetDestReg = 0; // unused
11249 OverflowDestReg = DestReg;
11252 overflowMBB = thisMBB;
11255 // First emit code to check if gp_offset (or fp_offset) is below the bound.
11256 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
11257 // If not, pull from overflow_area. (branch to overflowMBB)
11262 // offsetMBB overflowMBB
11267 // Registers for the PHI in endMBB
11268 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
11269 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
11271 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11272 MachineFunction *MF = MBB->getParent();
11273 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11274 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11275 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11277 MachineFunction::iterator MBBIter = MBB;
11280 // Insert the new basic blocks
11281 MF->insert(MBBIter, offsetMBB);
11282 MF->insert(MBBIter, overflowMBB);
11283 MF->insert(MBBIter, endMBB);
11285 // Transfer the remainder of MBB and its successor edges to endMBB.
11286 endMBB->splice(endMBB->begin(), thisMBB,
11287 llvm::next(MachineBasicBlock::iterator(MI)),
11289 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11291 // Make offsetMBB and overflowMBB successors of thisMBB
11292 thisMBB->addSuccessor(offsetMBB);
11293 thisMBB->addSuccessor(overflowMBB);
11295 // endMBB is a successor of both offsetMBB and overflowMBB
11296 offsetMBB->addSuccessor(endMBB);
11297 overflowMBB->addSuccessor(endMBB);
11299 // Load the offset value into a register
11300 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11301 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
11305 .addDisp(Disp, UseFPOffset ? 4 : 0)
11306 .addOperand(Segment)
11307 .setMemRefs(MMOBegin, MMOEnd);
11309 // Check if there is enough room left to pull this argument.
11310 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
11312 .addImm(MaxOffset + 8 - ArgSizeA8);
11314 // Branch to "overflowMBB" if offset >= max
11315 // Fall through to "offsetMBB" otherwise
11316 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
11317 .addMBB(overflowMBB);
11320 // In offsetMBB, emit code to use the reg_save_area.
11322 assert(OffsetReg != 0);
11324 // Read the reg_save_area address.
11325 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
11326 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
11331 .addOperand(Segment)
11332 .setMemRefs(MMOBegin, MMOEnd);
11334 // Zero-extend the offset
11335 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
11336 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
11339 .addImm(X86::sub_32bit);
11341 // Add the offset to the reg_save_area to get the final address.
11342 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
11343 .addReg(OffsetReg64)
11344 .addReg(RegSaveReg);
11346 // Compute the offset for the next argument
11347 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11348 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
11350 .addImm(UseFPOffset ? 16 : 8);
11352 // Store it back into the va_list.
11353 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
11357 .addDisp(Disp, UseFPOffset ? 4 : 0)
11358 .addOperand(Segment)
11359 .addReg(NextOffsetReg)
11360 .setMemRefs(MMOBegin, MMOEnd);
11363 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
11368 // Emit code to use overflow area
11371 // Load the overflow_area address into a register.
11372 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
11373 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
11378 .addOperand(Segment)
11379 .setMemRefs(MMOBegin, MMOEnd);
11381 // If we need to align it, do so. Otherwise, just copy the address
11382 // to OverflowDestReg.
11384 // Align the overflow address
11385 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
11386 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
11388 // aligned_addr = (addr + (align-1)) & ~(align-1)
11389 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
11390 .addReg(OverflowAddrReg)
11393 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
11395 .addImm(~(uint64_t)(Align-1));
11397 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
11398 .addReg(OverflowAddrReg);
11401 // Compute the next overflow address after this argument.
11402 // (the overflow address should be kept 8-byte aligned)
11403 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
11404 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
11405 .addReg(OverflowDestReg)
11406 .addImm(ArgSizeA8);
11408 // Store the new overflow address.
11409 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
11414 .addOperand(Segment)
11415 .addReg(NextAddrReg)
11416 .setMemRefs(MMOBegin, MMOEnd);
11418 // If we branched, emit the PHI to the front of endMBB.
11420 BuildMI(*endMBB, endMBB->begin(), DL,
11421 TII->get(X86::PHI), DestReg)
11422 .addReg(OffsetDestReg).addMBB(offsetMBB)
11423 .addReg(OverflowDestReg).addMBB(overflowMBB);
11426 // Erase the pseudo instruction
11427 MI->eraseFromParent();
11432 MachineBasicBlock *
11433 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
11435 MachineBasicBlock *MBB) const {
11436 // Emit code to save XMM registers to the stack. The ABI says that the
11437 // number of registers to save is given in %al, so it's theoretically
11438 // possible to do an indirect jump trick to avoid saving all of them,
11439 // however this code takes a simpler approach and just executes all
11440 // of the stores if %al is non-zero. It's less code, and it's probably
11441 // easier on the hardware branch predictor, and stores aren't all that
11442 // expensive anyway.
11444 // Create the new basic blocks. One block contains all the XMM stores,
11445 // and one block is the final destination regardless of whether any
11446 // stores were performed.
11447 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11448 MachineFunction *F = MBB->getParent();
11449 MachineFunction::iterator MBBIter = MBB;
11451 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
11452 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
11453 F->insert(MBBIter, XMMSaveMBB);
11454 F->insert(MBBIter, EndMBB);
11456 // Transfer the remainder of MBB and its successor edges to EndMBB.
11457 EndMBB->splice(EndMBB->begin(), MBB,
11458 llvm::next(MachineBasicBlock::iterator(MI)),
11460 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
11462 // The original block will now fall through to the XMM save block.
11463 MBB->addSuccessor(XMMSaveMBB);
11464 // The XMMSaveMBB will fall through to the end block.
11465 XMMSaveMBB->addSuccessor(EndMBB);
11467 // Now add the instructions.
11468 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11469 DebugLoc DL = MI->getDebugLoc();
11471 unsigned CountReg = MI->getOperand(0).getReg();
11472 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
11473 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
11475 if (!Subtarget->isTargetWin64()) {
11476 // If %al is 0, branch around the XMM save block.
11477 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
11478 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
11479 MBB->addSuccessor(EndMBB);
11482 // In the XMM save block, save all the XMM argument registers.
11483 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
11484 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
11485 MachineMemOperand *MMO =
11486 F->getMachineMemOperand(
11487 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
11488 MachineMemOperand::MOStore,
11489 /*Size=*/16, /*Align=*/16);
11490 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
11491 .addFrameIndex(RegSaveFrameIndex)
11492 .addImm(/*Scale=*/1)
11493 .addReg(/*IndexReg=*/0)
11494 .addImm(/*Disp=*/Offset)
11495 .addReg(/*Segment=*/0)
11496 .addReg(MI->getOperand(i).getReg())
11497 .addMemOperand(MMO);
11500 MI->eraseFromParent(); // The pseudo instruction is gone now.
11505 MachineBasicBlock *
11506 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
11507 MachineBasicBlock *BB) const {
11508 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11509 DebugLoc DL = MI->getDebugLoc();
11511 // To "insert" a SELECT_CC instruction, we actually have to insert the
11512 // diamond control-flow pattern. The incoming instruction knows the
11513 // destination vreg to set, the condition code register to branch on, the
11514 // true/false values to select between, and a branch opcode to use.
11515 const BasicBlock *LLVM_BB = BB->getBasicBlock();
11516 MachineFunction::iterator It = BB;
11522 // cmpTY ccX, r1, r2
11524 // fallthrough --> copy0MBB
11525 MachineBasicBlock *thisMBB = BB;
11526 MachineFunction *F = BB->getParent();
11527 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
11528 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
11529 F->insert(It, copy0MBB);
11530 F->insert(It, sinkMBB);
11532 // If the EFLAGS register isn't dead in the terminator, then claim that it's
11533 // live into the sink and copy blocks.
11534 const MachineFunction *MF = BB->getParent();
11535 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
11536 BitVector ReservedRegs = TRI->getReservedRegs(*MF);
11538 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
11539 const MachineOperand &MO = MI->getOperand(I);
11540 if (!MO.isReg() || !MO.isUse() || MO.isKill()) continue;
11541 unsigned Reg = MO.getReg();
11542 if (Reg != X86::EFLAGS) continue;
11543 copy0MBB->addLiveIn(Reg);
11544 sinkMBB->addLiveIn(Reg);
11547 // Transfer the remainder of BB and its successor edges to sinkMBB.
11548 sinkMBB->splice(sinkMBB->begin(), BB,
11549 llvm::next(MachineBasicBlock::iterator(MI)),
11551 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
11553 // Add the true and fallthrough blocks as its successors.
11554 BB->addSuccessor(copy0MBB);
11555 BB->addSuccessor(sinkMBB);
11557 // Create the conditional branch instruction.
11559 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
11560 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
11563 // %FalseValue = ...
11564 // # fallthrough to sinkMBB
11565 copy0MBB->addSuccessor(sinkMBB);
11568 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
11570 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
11571 TII->get(X86::PHI), MI->getOperand(0).getReg())
11572 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
11573 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
11575 MI->eraseFromParent(); // The pseudo instruction is gone now.
11579 MachineBasicBlock *
11580 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
11581 MachineBasicBlock *BB) const {
11582 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11583 DebugLoc DL = MI->getDebugLoc();
11585 assert(!Subtarget->isTargetEnvMacho());
11587 // The lowering is pretty easy: we're just emitting the call to _alloca. The
11588 // non-trivial part is impdef of ESP.
11590 if (Subtarget->isTargetWin64()) {
11591 if (Subtarget->isTargetCygMing()) {
11592 // ___chkstk(Mingw64):
11593 // Clobbers R10, R11, RAX and EFLAGS.
11595 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
11596 .addExternalSymbol("___chkstk")
11597 .addReg(X86::RAX, RegState::Implicit)
11598 .addReg(X86::RSP, RegState::Implicit)
11599 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
11600 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
11601 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
11603 // __chkstk(MSVCRT): does not update stack pointer.
11604 // Clobbers R10, R11 and EFLAGS.
11605 // FIXME: RAX(allocated size) might be reused and not killed.
11606 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
11607 .addExternalSymbol("__chkstk")
11608 .addReg(X86::RAX, RegState::Implicit)
11609 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
11610 // RAX has the offset to subtracted from RSP.
11611 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
11616 const char *StackProbeSymbol =
11617 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
11619 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
11620 .addExternalSymbol(StackProbeSymbol)
11621 .addReg(X86::EAX, RegState::Implicit)
11622 .addReg(X86::ESP, RegState::Implicit)
11623 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
11624 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
11625 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
11628 MI->eraseFromParent(); // The pseudo instruction is gone now.
11632 MachineBasicBlock *
11633 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
11634 MachineBasicBlock *BB) const {
11635 // This is pretty easy. We're taking the value that we received from
11636 // our load from the relocation, sticking it in either RDI (x86-64)
11637 // or EAX and doing an indirect call. The return value will then
11638 // be in the normal return register.
11639 const X86InstrInfo *TII
11640 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
11641 DebugLoc DL = MI->getDebugLoc();
11642 MachineFunction *F = BB->getParent();
11644 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
11645 assert(MI->getOperand(3).isGlobal() && "This should be a global");
11647 if (Subtarget->is64Bit()) {
11648 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
11649 TII->get(X86::MOV64rm), X86::RDI)
11651 .addImm(0).addReg(0)
11652 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
11653 MI->getOperand(3).getTargetFlags())
11655 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
11656 addDirectMem(MIB, X86::RDI);
11657 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
11658 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
11659 TII->get(X86::MOV32rm), X86::EAX)
11661 .addImm(0).addReg(0)
11662 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
11663 MI->getOperand(3).getTargetFlags())
11665 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
11666 addDirectMem(MIB, X86::EAX);
11668 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
11669 TII->get(X86::MOV32rm), X86::EAX)
11670 .addReg(TII->getGlobalBaseReg(F))
11671 .addImm(0).addReg(0)
11672 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
11673 MI->getOperand(3).getTargetFlags())
11675 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
11676 addDirectMem(MIB, X86::EAX);
11679 MI->eraseFromParent(); // The pseudo instruction is gone now.
11683 MachineBasicBlock *
11684 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
11685 MachineBasicBlock *BB) const {
11686 switch (MI->getOpcode()) {
11687 default: assert(false && "Unexpected instr type to insert");
11688 case X86::TAILJMPd64:
11689 case X86::TAILJMPr64:
11690 case X86::TAILJMPm64:
11691 assert(!"TAILJMP64 would not be touched here.");
11692 case X86::TCRETURNdi64:
11693 case X86::TCRETURNri64:
11694 case X86::TCRETURNmi64:
11695 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset.
11696 // On AMD64, additional defs should be added before register allocation.
11697 if (!Subtarget->isTargetWin64()) {
11698 MI->addRegisterDefined(X86::RSI);
11699 MI->addRegisterDefined(X86::RDI);
11700 MI->addRegisterDefined(X86::XMM6);
11701 MI->addRegisterDefined(X86::XMM7);
11702 MI->addRegisterDefined(X86::XMM8);
11703 MI->addRegisterDefined(X86::XMM9);
11704 MI->addRegisterDefined(X86::XMM10);
11705 MI->addRegisterDefined(X86::XMM11);
11706 MI->addRegisterDefined(X86::XMM12);
11707 MI->addRegisterDefined(X86::XMM13);
11708 MI->addRegisterDefined(X86::XMM14);
11709 MI->addRegisterDefined(X86::XMM15);
11712 case X86::WIN_ALLOCA:
11713 return EmitLoweredWinAlloca(MI, BB);
11714 case X86::TLSCall_32:
11715 case X86::TLSCall_64:
11716 return EmitLoweredTLSCall(MI, BB);
11717 case X86::CMOV_GR8:
11718 case X86::CMOV_FR32:
11719 case X86::CMOV_FR64:
11720 case X86::CMOV_V4F32:
11721 case X86::CMOV_V2F64:
11722 case X86::CMOV_V2I64:
11723 case X86::CMOV_V8F32:
11724 case X86::CMOV_V4F64:
11725 case X86::CMOV_V4I64:
11726 case X86::CMOV_GR16:
11727 case X86::CMOV_GR32:
11728 case X86::CMOV_RFP32:
11729 case X86::CMOV_RFP64:
11730 case X86::CMOV_RFP80:
11731 return EmitLoweredSelect(MI, BB);
11733 case X86::FP32_TO_INT16_IN_MEM:
11734 case X86::FP32_TO_INT32_IN_MEM:
11735 case X86::FP32_TO_INT64_IN_MEM:
11736 case X86::FP64_TO_INT16_IN_MEM:
11737 case X86::FP64_TO_INT32_IN_MEM:
11738 case X86::FP64_TO_INT64_IN_MEM:
11739 case X86::FP80_TO_INT16_IN_MEM:
11740 case X86::FP80_TO_INT32_IN_MEM:
11741 case X86::FP80_TO_INT64_IN_MEM: {
11742 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11743 DebugLoc DL = MI->getDebugLoc();
11745 // Change the floating point control register to use "round towards zero"
11746 // mode when truncating to an integer value.
11747 MachineFunction *F = BB->getParent();
11748 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
11749 addFrameReference(BuildMI(*BB, MI, DL,
11750 TII->get(X86::FNSTCW16m)), CWFrameIdx);
11752 // Load the old value of the high byte of the control word...
11754 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
11755 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
11758 // Set the high part to be round to zero...
11759 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
11762 // Reload the modified control word now...
11763 addFrameReference(BuildMI(*BB, MI, DL,
11764 TII->get(X86::FLDCW16m)), CWFrameIdx);
11766 // Restore the memory image of control word to original value
11767 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
11770 // Get the X86 opcode to use.
11772 switch (MI->getOpcode()) {
11773 default: llvm_unreachable("illegal opcode!");
11774 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
11775 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
11776 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
11777 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
11778 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
11779 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
11780 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
11781 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
11782 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
11786 MachineOperand &Op = MI->getOperand(0);
11788 AM.BaseType = X86AddressMode::RegBase;
11789 AM.Base.Reg = Op.getReg();
11791 AM.BaseType = X86AddressMode::FrameIndexBase;
11792 AM.Base.FrameIndex = Op.getIndex();
11794 Op = MI->getOperand(1);
11796 AM.Scale = Op.getImm();
11797 Op = MI->getOperand(2);
11799 AM.IndexReg = Op.getImm();
11800 Op = MI->getOperand(3);
11801 if (Op.isGlobal()) {
11802 AM.GV = Op.getGlobal();
11804 AM.Disp = Op.getImm();
11806 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
11807 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
11809 // Reload the original control word now.
11810 addFrameReference(BuildMI(*BB, MI, DL,
11811 TII->get(X86::FLDCW16m)), CWFrameIdx);
11813 MI->eraseFromParent(); // The pseudo instruction is gone now.
11816 // String/text processing lowering.
11817 case X86::PCMPISTRM128REG:
11818 case X86::VPCMPISTRM128REG:
11819 return EmitPCMP(MI, BB, 3, false /* in-mem */);
11820 case X86::PCMPISTRM128MEM:
11821 case X86::VPCMPISTRM128MEM:
11822 return EmitPCMP(MI, BB, 3, true /* in-mem */);
11823 case X86::PCMPESTRM128REG:
11824 case X86::VPCMPESTRM128REG:
11825 return EmitPCMP(MI, BB, 5, false /* in mem */);
11826 case X86::PCMPESTRM128MEM:
11827 case X86::VPCMPESTRM128MEM:
11828 return EmitPCMP(MI, BB, 5, true /* in mem */);
11830 // Thread synchronization.
11832 return EmitMonitor(MI, BB);
11834 return EmitMwait(MI, BB);
11836 // Atomic Lowering.
11837 case X86::ATOMAND32:
11838 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
11839 X86::AND32ri, X86::MOV32rm,
11841 X86::NOT32r, X86::EAX,
11842 X86::GR32RegisterClass);
11843 case X86::ATOMOR32:
11844 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
11845 X86::OR32ri, X86::MOV32rm,
11847 X86::NOT32r, X86::EAX,
11848 X86::GR32RegisterClass);
11849 case X86::ATOMXOR32:
11850 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
11851 X86::XOR32ri, X86::MOV32rm,
11853 X86::NOT32r, X86::EAX,
11854 X86::GR32RegisterClass);
11855 case X86::ATOMNAND32:
11856 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
11857 X86::AND32ri, X86::MOV32rm,
11859 X86::NOT32r, X86::EAX,
11860 X86::GR32RegisterClass, true);
11861 case X86::ATOMMIN32:
11862 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
11863 case X86::ATOMMAX32:
11864 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
11865 case X86::ATOMUMIN32:
11866 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
11867 case X86::ATOMUMAX32:
11868 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
11870 case X86::ATOMAND16:
11871 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
11872 X86::AND16ri, X86::MOV16rm,
11874 X86::NOT16r, X86::AX,
11875 X86::GR16RegisterClass);
11876 case X86::ATOMOR16:
11877 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
11878 X86::OR16ri, X86::MOV16rm,
11880 X86::NOT16r, X86::AX,
11881 X86::GR16RegisterClass);
11882 case X86::ATOMXOR16:
11883 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
11884 X86::XOR16ri, X86::MOV16rm,
11886 X86::NOT16r, X86::AX,
11887 X86::GR16RegisterClass);
11888 case X86::ATOMNAND16:
11889 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
11890 X86::AND16ri, X86::MOV16rm,
11892 X86::NOT16r, X86::AX,
11893 X86::GR16RegisterClass, true);
11894 case X86::ATOMMIN16:
11895 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
11896 case X86::ATOMMAX16:
11897 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
11898 case X86::ATOMUMIN16:
11899 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
11900 case X86::ATOMUMAX16:
11901 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
11903 case X86::ATOMAND8:
11904 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
11905 X86::AND8ri, X86::MOV8rm,
11907 X86::NOT8r, X86::AL,
11908 X86::GR8RegisterClass);
11910 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
11911 X86::OR8ri, X86::MOV8rm,
11913 X86::NOT8r, X86::AL,
11914 X86::GR8RegisterClass);
11915 case X86::ATOMXOR8:
11916 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
11917 X86::XOR8ri, X86::MOV8rm,
11919 X86::NOT8r, X86::AL,
11920 X86::GR8RegisterClass);
11921 case X86::ATOMNAND8:
11922 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
11923 X86::AND8ri, X86::MOV8rm,
11925 X86::NOT8r, X86::AL,
11926 X86::GR8RegisterClass, true);
11927 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
11928 // This group is for 64-bit host.
11929 case X86::ATOMAND64:
11930 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
11931 X86::AND64ri32, X86::MOV64rm,
11933 X86::NOT64r, X86::RAX,
11934 X86::GR64RegisterClass);
11935 case X86::ATOMOR64:
11936 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
11937 X86::OR64ri32, X86::MOV64rm,
11939 X86::NOT64r, X86::RAX,
11940 X86::GR64RegisterClass);
11941 case X86::ATOMXOR64:
11942 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
11943 X86::XOR64ri32, X86::MOV64rm,
11945 X86::NOT64r, X86::RAX,
11946 X86::GR64RegisterClass);
11947 case X86::ATOMNAND64:
11948 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
11949 X86::AND64ri32, X86::MOV64rm,
11951 X86::NOT64r, X86::RAX,
11952 X86::GR64RegisterClass, true);
11953 case X86::ATOMMIN64:
11954 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
11955 case X86::ATOMMAX64:
11956 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
11957 case X86::ATOMUMIN64:
11958 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
11959 case X86::ATOMUMAX64:
11960 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
11962 // This group does 64-bit operations on a 32-bit host.
11963 case X86::ATOMAND6432:
11964 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11965 X86::AND32rr, X86::AND32rr,
11966 X86::AND32ri, X86::AND32ri,
11968 case X86::ATOMOR6432:
11969 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11970 X86::OR32rr, X86::OR32rr,
11971 X86::OR32ri, X86::OR32ri,
11973 case X86::ATOMXOR6432:
11974 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11975 X86::XOR32rr, X86::XOR32rr,
11976 X86::XOR32ri, X86::XOR32ri,
11978 case X86::ATOMNAND6432:
11979 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11980 X86::AND32rr, X86::AND32rr,
11981 X86::AND32ri, X86::AND32ri,
11983 case X86::ATOMADD6432:
11984 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11985 X86::ADD32rr, X86::ADC32rr,
11986 X86::ADD32ri, X86::ADC32ri,
11988 case X86::ATOMSUB6432:
11989 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11990 X86::SUB32rr, X86::SBB32rr,
11991 X86::SUB32ri, X86::SBB32ri,
11993 case X86::ATOMSWAP6432:
11994 return EmitAtomicBit6432WithCustomInserter(MI, BB,
11995 X86::MOV32rr, X86::MOV32rr,
11996 X86::MOV32ri, X86::MOV32ri,
11998 case X86::VASTART_SAVE_XMM_REGS:
11999 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12001 case X86::VAARG_64:
12002 return EmitVAARG64WithCustomInserter(MI, BB);
12006 //===----------------------------------------------------------------------===//
12007 // X86 Optimization Hooks
12008 //===----------------------------------------------------------------------===//
12010 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12014 const SelectionDAG &DAG,
12015 unsigned Depth) const {
12016 unsigned Opc = Op.getOpcode();
12017 assert((Opc >= ISD::BUILTIN_OP_END ||
12018 Opc == ISD::INTRINSIC_WO_CHAIN ||
12019 Opc == ISD::INTRINSIC_W_CHAIN ||
12020 Opc == ISD::INTRINSIC_VOID) &&
12021 "Should use MaskedValueIsZero if you don't know whether Op"
12022 " is a target node!");
12024 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
12038 // These nodes' second result is a boolean.
12039 if (Op.getResNo() == 0)
12042 case X86ISD::SETCC:
12043 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
12044 Mask.getBitWidth() - 1);
12049 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12050 unsigned Depth) const {
12051 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12052 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12053 return Op.getValueType().getScalarType().getSizeInBits();
12059 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12060 /// node is a GlobalAddress + offset.
12061 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12062 const GlobalValue* &GA,
12063 int64_t &Offset) const {
12064 if (N->getOpcode() == X86ISD::Wrapper) {
12065 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12066 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12067 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12071 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12074 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12075 /// same as extracting the high 128-bit part of 256-bit vector and then
12076 /// inserting the result into the low part of a new 256-bit vector
12077 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12078 EVT VT = SVOp->getValueType(0);
12079 int NumElems = VT.getVectorNumElements();
12081 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12082 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j)
12083 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12084 SVOp->getMaskElt(j) >= 0)
12090 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
12091 /// same as extracting the low 128-bit part of 256-bit vector and then
12092 /// inserting the result into the high part of a new 256-bit vector
12093 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
12094 EVT VT = SVOp->getValueType(0);
12095 int NumElems = VT.getVectorNumElements();
12097 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12098 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j)
12099 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12100 SVOp->getMaskElt(j) >= 0)
12106 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
12107 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
12108 TargetLowering::DAGCombinerInfo &DCI) {
12109 DebugLoc dl = N->getDebugLoc();
12110 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
12111 SDValue V1 = SVOp->getOperand(0);
12112 SDValue V2 = SVOp->getOperand(1);
12113 EVT VT = SVOp->getValueType(0);
12114 int NumElems = VT.getVectorNumElements();
12116 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
12117 V2.getOpcode() == ISD::CONCAT_VECTORS) {
12121 // V UNDEF BUILD_VECTOR UNDEF
12123 // CONCAT_VECTOR CONCAT_VECTOR
12126 // RESULT: V + zero extended
12128 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
12129 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
12130 V1.getOperand(1).getOpcode() != ISD::UNDEF)
12133 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
12136 // To match the shuffle mask, the first half of the mask should
12137 // be exactly the first vector, and all the rest a splat with the
12138 // first element of the second one.
12139 for (int i = 0; i < NumElems/2; ++i)
12140 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
12141 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
12144 // Emit a zeroed vector and insert the desired subvector on its
12146 SDValue Zeros = getZeroVector(VT, true /* HasSSE2 */, DAG, dl);
12147 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0),
12148 DAG.getConstant(0, MVT::i32), DAG, dl);
12149 return DCI.CombineTo(N, InsV);
12152 //===--------------------------------------------------------------------===//
12153 // Combine some shuffles into subvector extracts and inserts:
12156 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12157 if (isShuffleHigh128VectorInsertLow(SVOp)) {
12158 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32),
12160 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12161 V, DAG.getConstant(0, MVT::i32), DAG, dl);
12162 return DCI.CombineTo(N, InsV);
12165 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12166 if (isShuffleLow128VectorInsertHigh(SVOp)) {
12167 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl);
12168 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12169 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
12170 return DCI.CombineTo(N, InsV);
12176 /// PerformShuffleCombine - Performs several different shuffle combines.
12177 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
12178 TargetLowering::DAGCombinerInfo &DCI,
12179 const X86Subtarget *Subtarget) {
12180 DebugLoc dl = N->getDebugLoc();
12181 EVT VT = N->getValueType(0);
12183 // Don't create instructions with illegal types after legalize types has run.
12184 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12185 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
12188 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
12189 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
12190 N->getOpcode() == ISD::VECTOR_SHUFFLE)
12191 return PerformShuffleCombine256(N, DAG, DCI);
12193 // Only handle 128 wide vector from here on.
12194 if (VT.getSizeInBits() != 128)
12197 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
12198 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
12199 // consecutive, non-overlapping, and in the right order.
12200 SmallVector<SDValue, 16> Elts;
12201 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
12202 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
12204 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
12207 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
12208 /// generation and convert it from being a bunch of shuffles and extracts
12209 /// to a simple store and scalar loads to extract the elements.
12210 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
12211 const TargetLowering &TLI) {
12212 SDValue InputVector = N->getOperand(0);
12214 // Only operate on vectors of 4 elements, where the alternative shuffling
12215 // gets to be more expensive.
12216 if (InputVector.getValueType() != MVT::v4i32)
12219 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
12220 // single use which is a sign-extend or zero-extend, and all elements are
12222 SmallVector<SDNode *, 4> Uses;
12223 unsigned ExtractedElements = 0;
12224 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
12225 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
12226 if (UI.getUse().getResNo() != InputVector.getResNo())
12229 SDNode *Extract = *UI;
12230 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12233 if (Extract->getValueType(0) != MVT::i32)
12235 if (!Extract->hasOneUse())
12237 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
12238 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
12240 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
12243 // Record which element was extracted.
12244 ExtractedElements |=
12245 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
12247 Uses.push_back(Extract);
12250 // If not all the elements were used, this may not be worthwhile.
12251 if (ExtractedElements != 15)
12254 // Ok, we've now decided to do the transformation.
12255 DebugLoc dl = InputVector.getDebugLoc();
12257 // Store the value to a temporary stack slot.
12258 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
12259 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
12260 MachinePointerInfo(), false, false, 0);
12262 // Replace each use (extract) with a load of the appropriate element.
12263 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
12264 UE = Uses.end(); UI != UE; ++UI) {
12265 SDNode *Extract = *UI;
12267 // cOMpute the element's address.
12268 SDValue Idx = Extract->getOperand(1);
12270 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
12271 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
12272 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
12274 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
12275 StackPtr, OffsetVal);
12277 // Load the scalar.
12278 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
12279 ScalarAddr, MachinePointerInfo(),
12282 // Replace the exact with the load.
12283 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
12286 // The replacement was made in place; don't return anything.
12290 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
12291 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
12292 const X86Subtarget *Subtarget) {
12293 DebugLoc DL = N->getDebugLoc();
12294 SDValue Cond = N->getOperand(0);
12295 // Get the LHS/RHS of the select.
12296 SDValue LHS = N->getOperand(1);
12297 SDValue RHS = N->getOperand(2);
12299 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
12300 // instructions match the semantics of the common C idiom x<y?x:y but not
12301 // x<=y?x:y, because of how they handle negative zero (which can be
12302 // ignored in unsafe-math mode).
12303 if (Subtarget->hasSSE2() &&
12304 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
12305 Cond.getOpcode() == ISD::SETCC) {
12306 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
12308 unsigned Opcode = 0;
12309 // Check for x CC y ? x : y.
12310 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
12311 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
12315 // Converting this to a min would handle NaNs incorrectly, and swapping
12316 // the operands would cause it to handle comparisons between positive
12317 // and negative zero incorrectly.
12318 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12319 if (!UnsafeFPMath &&
12320 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12322 std::swap(LHS, RHS);
12324 Opcode = X86ISD::FMIN;
12327 // Converting this to a min would handle comparisons between positive
12328 // and negative zero incorrectly.
12329 if (!UnsafeFPMath &&
12330 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12332 Opcode = X86ISD::FMIN;
12335 // Converting this to a min would handle both negative zeros and NaNs
12336 // incorrectly, but we can swap the operands to fix both.
12337 std::swap(LHS, RHS);
12341 Opcode = X86ISD::FMIN;
12345 // Converting this to a max would handle comparisons between positive
12346 // and negative zero incorrectly.
12347 if (!UnsafeFPMath &&
12348 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12350 Opcode = X86ISD::FMAX;
12353 // Converting this to a max would handle NaNs incorrectly, and swapping
12354 // the operands would cause it to handle comparisons between positive
12355 // and negative zero incorrectly.
12356 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12357 if (!UnsafeFPMath &&
12358 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12360 std::swap(LHS, RHS);
12362 Opcode = X86ISD::FMAX;
12365 // Converting this to a max would handle both negative zeros and NaNs
12366 // incorrectly, but we can swap the operands to fix both.
12367 std::swap(LHS, RHS);
12371 Opcode = X86ISD::FMAX;
12374 // Check for x CC y ? y : x -- a min/max with reversed arms.
12375 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
12376 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
12380 // Converting this to a min would handle comparisons between positive
12381 // and negative zero incorrectly, and swapping the operands would
12382 // cause it to handle NaNs incorrectly.
12383 if (!UnsafeFPMath &&
12384 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
12385 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12387 std::swap(LHS, RHS);
12389 Opcode = X86ISD::FMIN;
12392 // Converting this to a min would handle NaNs incorrectly.
12393 if (!UnsafeFPMath &&
12394 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
12396 Opcode = X86ISD::FMIN;
12399 // Converting this to a min would handle both negative zeros and NaNs
12400 // incorrectly, but we can swap the operands to fix both.
12401 std::swap(LHS, RHS);
12405 Opcode = X86ISD::FMIN;
12409 // Converting this to a max would handle NaNs incorrectly.
12410 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12412 Opcode = X86ISD::FMAX;
12415 // Converting this to a max would handle comparisons between positive
12416 // and negative zero incorrectly, and swapping the operands would
12417 // cause it to handle NaNs incorrectly.
12418 if (!UnsafeFPMath &&
12419 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
12420 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12422 std::swap(LHS, RHS);
12424 Opcode = X86ISD::FMAX;
12427 // Converting this to a max would handle both negative zeros and NaNs
12428 // incorrectly, but we can swap the operands to fix both.
12429 std::swap(LHS, RHS);
12433 Opcode = X86ISD::FMAX;
12439 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
12442 // If this is a select between two integer constants, try to do some
12444 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
12445 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
12446 // Don't do this for crazy integer types.
12447 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
12448 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
12449 // so that TrueC (the true value) is larger than FalseC.
12450 bool NeedsCondInvert = false;
12452 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
12453 // Efficiently invertible.
12454 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
12455 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
12456 isa<ConstantSDNode>(Cond.getOperand(1))))) {
12457 NeedsCondInvert = true;
12458 std::swap(TrueC, FalseC);
12461 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
12462 if (FalseC->getAPIntValue() == 0 &&
12463 TrueC->getAPIntValue().isPowerOf2()) {
12464 if (NeedsCondInvert) // Invert the condition if needed.
12465 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
12466 DAG.getConstant(1, Cond.getValueType()));
12468 // Zero extend the condition if needed.
12469 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
12471 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
12472 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
12473 DAG.getConstant(ShAmt, MVT::i8));
12476 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
12477 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
12478 if (NeedsCondInvert) // Invert the condition if needed.
12479 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
12480 DAG.getConstant(1, Cond.getValueType()));
12482 // Zero extend the condition if needed.
12483 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
12484 FalseC->getValueType(0), Cond);
12485 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12486 SDValue(FalseC, 0));
12489 // Optimize cases that will turn into an LEA instruction. This requires
12490 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
12491 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
12492 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
12493 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
12495 bool isFastMultiplier = false;
12497 switch ((unsigned char)Diff) {
12499 case 1: // result = add base, cond
12500 case 2: // result = lea base( , cond*2)
12501 case 3: // result = lea base(cond, cond*2)
12502 case 4: // result = lea base( , cond*4)
12503 case 5: // result = lea base(cond, cond*4)
12504 case 8: // result = lea base( , cond*8)
12505 case 9: // result = lea base(cond, cond*8)
12506 isFastMultiplier = true;
12511 if (isFastMultiplier) {
12512 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
12513 if (NeedsCondInvert) // Invert the condition if needed.
12514 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
12515 DAG.getConstant(1, Cond.getValueType()));
12517 // Zero extend the condition if needed.
12518 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
12520 // Scale the condition by the difference.
12522 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
12523 DAG.getConstant(Diff, Cond.getValueType()));
12525 // Add the base if non-zero.
12526 if (FalseC->getAPIntValue() != 0)
12527 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12528 SDValue(FalseC, 0));
12538 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
12539 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
12540 TargetLowering::DAGCombinerInfo &DCI) {
12541 DebugLoc DL = N->getDebugLoc();
12543 // If the flag operand isn't dead, don't touch this CMOV.
12544 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
12547 SDValue FalseOp = N->getOperand(0);
12548 SDValue TrueOp = N->getOperand(1);
12549 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
12550 SDValue Cond = N->getOperand(3);
12551 if (CC == X86::COND_E || CC == X86::COND_NE) {
12552 switch (Cond.getOpcode()) {
12556 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
12557 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
12558 return (CC == X86::COND_E) ? FalseOp : TrueOp;
12562 // If this is a select between two integer constants, try to do some
12563 // optimizations. Note that the operands are ordered the opposite of SELECT
12565 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
12566 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
12567 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
12568 // larger than FalseC (the false value).
12569 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
12570 CC = X86::GetOppositeBranchCondition(CC);
12571 std::swap(TrueC, FalseC);
12574 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
12575 // This is efficient for any integer data type (including i8/i16) and
12577 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
12578 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12579 DAG.getConstant(CC, MVT::i8), Cond);
12581 // Zero extend the condition if needed.
12582 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
12584 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
12585 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
12586 DAG.getConstant(ShAmt, MVT::i8));
12587 if (N->getNumValues() == 2) // Dead flag value?
12588 return DCI.CombineTo(N, Cond, SDValue());
12592 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
12593 // for any integer data type, including i8/i16.
12594 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
12595 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12596 DAG.getConstant(CC, MVT::i8), Cond);
12598 // Zero extend the condition if needed.
12599 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
12600 FalseC->getValueType(0), Cond);
12601 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12602 SDValue(FalseC, 0));
12604 if (N->getNumValues() == 2) // Dead flag value?
12605 return DCI.CombineTo(N, Cond, SDValue());
12609 // Optimize cases that will turn into an LEA instruction. This requires
12610 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
12611 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
12612 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
12613 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
12615 bool isFastMultiplier = false;
12617 switch ((unsigned char)Diff) {
12619 case 1: // result = add base, cond
12620 case 2: // result = lea base( , cond*2)
12621 case 3: // result = lea base(cond, cond*2)
12622 case 4: // result = lea base( , cond*4)
12623 case 5: // result = lea base(cond, cond*4)
12624 case 8: // result = lea base( , cond*8)
12625 case 9: // result = lea base(cond, cond*8)
12626 isFastMultiplier = true;
12631 if (isFastMultiplier) {
12632 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
12633 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12634 DAG.getConstant(CC, MVT::i8), Cond);
12635 // Zero extend the condition if needed.
12636 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
12638 // Scale the condition by the difference.
12640 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
12641 DAG.getConstant(Diff, Cond.getValueType()));
12643 // Add the base if non-zero.
12644 if (FalseC->getAPIntValue() != 0)
12645 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12646 SDValue(FalseC, 0));
12647 if (N->getNumValues() == 2) // Dead flag value?
12648 return DCI.CombineTo(N, Cond, SDValue());
12658 /// PerformMulCombine - Optimize a single multiply with constant into two
12659 /// in order to implement it with two cheaper instructions, e.g.
12660 /// LEA + SHL, LEA + LEA.
12661 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
12662 TargetLowering::DAGCombinerInfo &DCI) {
12663 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
12666 EVT VT = N->getValueType(0);
12667 if (VT != MVT::i64)
12670 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
12673 uint64_t MulAmt = C->getZExtValue();
12674 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
12677 uint64_t MulAmt1 = 0;
12678 uint64_t MulAmt2 = 0;
12679 if ((MulAmt % 9) == 0) {
12681 MulAmt2 = MulAmt / 9;
12682 } else if ((MulAmt % 5) == 0) {
12684 MulAmt2 = MulAmt / 5;
12685 } else if ((MulAmt % 3) == 0) {
12687 MulAmt2 = MulAmt / 3;
12690 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
12691 DebugLoc DL = N->getDebugLoc();
12693 if (isPowerOf2_64(MulAmt2) &&
12694 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
12695 // If second multiplifer is pow2, issue it first. We want the multiply by
12696 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
12698 std::swap(MulAmt1, MulAmt2);
12701 if (isPowerOf2_64(MulAmt1))
12702 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
12703 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
12705 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
12706 DAG.getConstant(MulAmt1, VT));
12708 if (isPowerOf2_64(MulAmt2))
12709 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
12710 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
12712 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
12713 DAG.getConstant(MulAmt2, VT));
12715 // Do not add new nodes to DAG combiner worklist.
12716 DCI.CombineTo(N, NewMul, false);
12721 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
12722 SDValue N0 = N->getOperand(0);
12723 SDValue N1 = N->getOperand(1);
12724 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
12725 EVT VT = N0.getValueType();
12727 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
12728 // since the result of setcc_c is all zero's or all ones.
12729 if (N1C && N0.getOpcode() == ISD::AND &&
12730 N0.getOperand(1).getOpcode() == ISD::Constant) {
12731 SDValue N00 = N0.getOperand(0);
12732 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
12733 ((N00.getOpcode() == ISD::ANY_EXTEND ||
12734 N00.getOpcode() == ISD::ZERO_EXTEND) &&
12735 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
12736 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
12737 APInt ShAmt = N1C->getAPIntValue();
12738 Mask = Mask.shl(ShAmt);
12740 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
12741 N00, DAG.getConstant(Mask, VT));
12748 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
12750 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
12751 const X86Subtarget *Subtarget) {
12752 EVT VT = N->getValueType(0);
12753 if (!VT.isVector() && VT.isInteger() &&
12754 N->getOpcode() == ISD::SHL)
12755 return PerformSHLCombine(N, DAG);
12757 // On X86 with SSE2 support, we can transform this to a vector shift if
12758 // all elements are shifted by the same amount. We can't do this in legalize
12759 // because the a constant vector is typically transformed to a constant pool
12760 // so we have no knowledge of the shift amount.
12761 if (!(Subtarget->hasSSE2() || Subtarget->hasAVX()))
12764 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
12767 SDValue ShAmtOp = N->getOperand(1);
12768 EVT EltVT = VT.getVectorElementType();
12769 DebugLoc DL = N->getDebugLoc();
12770 SDValue BaseShAmt = SDValue();
12771 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
12772 unsigned NumElts = VT.getVectorNumElements();
12774 for (; i != NumElts; ++i) {
12775 SDValue Arg = ShAmtOp.getOperand(i);
12776 if (Arg.getOpcode() == ISD::UNDEF) continue;
12780 for (; i != NumElts; ++i) {
12781 SDValue Arg = ShAmtOp.getOperand(i);
12782 if (Arg.getOpcode() == ISD::UNDEF) continue;
12783 if (Arg != BaseShAmt) {
12787 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
12788 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
12789 SDValue InVec = ShAmtOp.getOperand(0);
12790 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
12791 unsigned NumElts = InVec.getValueType().getVectorNumElements();
12793 for (; i != NumElts; ++i) {
12794 SDValue Arg = InVec.getOperand(i);
12795 if (Arg.getOpcode() == ISD::UNDEF) continue;
12799 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
12800 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
12801 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
12802 if (C->getZExtValue() == SplatIdx)
12803 BaseShAmt = InVec.getOperand(1);
12806 if (BaseShAmt.getNode() == 0)
12807 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
12808 DAG.getIntPtrConstant(0));
12812 // The shift amount is an i32.
12813 if (EltVT.bitsGT(MVT::i32))
12814 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
12815 else if (EltVT.bitsLT(MVT::i32))
12816 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
12818 // The shift amount is identical so we can do a vector shift.
12819 SDValue ValOp = N->getOperand(0);
12820 switch (N->getOpcode()) {
12822 llvm_unreachable("Unknown shift opcode!");
12825 if (VT == MVT::v2i64)
12826 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12827 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
12829 if (VT == MVT::v4i32)
12830 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12831 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
12833 if (VT == MVT::v8i16)
12834 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12835 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
12839 if (VT == MVT::v4i32)
12840 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12841 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
12843 if (VT == MVT::v8i16)
12844 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12845 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
12849 if (VT == MVT::v2i64)
12850 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12851 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
12853 if (VT == MVT::v4i32)
12854 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12855 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
12857 if (VT == MVT::v8i16)
12858 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
12859 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
12867 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
12868 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
12869 // and friends. Likewise for OR -> CMPNEQSS.
12870 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
12871 TargetLowering::DAGCombinerInfo &DCI,
12872 const X86Subtarget *Subtarget) {
12875 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
12876 // we're requiring SSE2 for both.
12877 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
12878 SDValue N0 = N->getOperand(0);
12879 SDValue N1 = N->getOperand(1);
12880 SDValue CMP0 = N0->getOperand(1);
12881 SDValue CMP1 = N1->getOperand(1);
12882 DebugLoc DL = N->getDebugLoc();
12884 // The SETCCs should both refer to the same CMP.
12885 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
12888 SDValue CMP00 = CMP0->getOperand(0);
12889 SDValue CMP01 = CMP0->getOperand(1);
12890 EVT VT = CMP00.getValueType();
12892 if (VT == MVT::f32 || VT == MVT::f64) {
12893 bool ExpectingFlags = false;
12894 // Check for any users that want flags:
12895 for (SDNode::use_iterator UI = N->use_begin(),
12897 !ExpectingFlags && UI != UE; ++UI)
12898 switch (UI->getOpcode()) {
12903 ExpectingFlags = true;
12905 case ISD::CopyToReg:
12906 case ISD::SIGN_EXTEND:
12907 case ISD::ZERO_EXTEND:
12908 case ISD::ANY_EXTEND:
12912 if (!ExpectingFlags) {
12913 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
12914 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
12916 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
12917 X86::CondCode tmp = cc0;
12922 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
12923 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
12924 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
12925 X86ISD::NodeType NTOperator = is64BitFP ?
12926 X86ISD::FSETCCsd : X86ISD::FSETCCss;
12927 // FIXME: need symbolic constants for these magic numbers.
12928 // See X86ATTInstPrinter.cpp:printSSECC().
12929 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
12930 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
12931 DAG.getConstant(x86cc, MVT::i8));
12932 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
12934 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
12935 DAG.getConstant(1, MVT::i32));
12936 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
12937 return OneBitOfTruth;
12945 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
12946 /// so it can be folded inside ANDNP.
12947 static bool CanFoldXORWithAllOnes(const SDNode *N) {
12948 EVT VT = N->getValueType(0);
12950 // Match direct AllOnes for 128 and 256-bit vectors
12951 if (ISD::isBuildVectorAllOnes(N))
12954 // Look through a bit convert.
12955 if (N->getOpcode() == ISD::BITCAST)
12956 N = N->getOperand(0).getNode();
12958 // Sometimes the operand may come from a insert_subvector building a 256-bit
12960 if (VT.getSizeInBits() == 256 &&
12961 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
12962 SDValue V1 = N->getOperand(0);
12963 SDValue V2 = N->getOperand(1);
12965 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
12966 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
12967 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
12968 ISD::isBuildVectorAllOnes(V2.getNode()))
12975 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
12976 TargetLowering::DAGCombinerInfo &DCI,
12977 const X86Subtarget *Subtarget) {
12978 if (DCI.isBeforeLegalizeOps())
12981 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
12985 // Want to form ANDNP nodes:
12986 // 1) In the hopes of then easily combining them with OR and AND nodes
12987 // to form PBLEND/PSIGN.
12988 // 2) To match ANDN packed intrinsics
12989 EVT VT = N->getValueType(0);
12990 if (VT != MVT::v2i64 && VT != MVT::v4i64)
12993 SDValue N0 = N->getOperand(0);
12994 SDValue N1 = N->getOperand(1);
12995 DebugLoc DL = N->getDebugLoc();
12997 // Check LHS for vnot
12998 if (N0.getOpcode() == ISD::XOR &&
12999 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
13000 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
13001 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
13003 // Check RHS for vnot
13004 if (N1.getOpcode() == ISD::XOR &&
13005 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
13006 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
13007 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
13012 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
13013 TargetLowering::DAGCombinerInfo &DCI,
13014 const X86Subtarget *Subtarget) {
13015 if (DCI.isBeforeLegalizeOps())
13018 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13022 EVT VT = N->getValueType(0);
13023 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64 && VT != MVT::v2i64)
13026 SDValue N0 = N->getOperand(0);
13027 SDValue N1 = N->getOperand(1);
13029 // look for psign/blend
13030 if (Subtarget->hasSSSE3()) {
13031 if (VT == MVT::v2i64) {
13032 // Canonicalize pandn to RHS
13033 if (N0.getOpcode() == X86ISD::ANDNP)
13035 // or (and (m, x), (pandn m, y))
13036 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
13037 SDValue Mask = N1.getOperand(0);
13038 SDValue X = N1.getOperand(1);
13040 if (N0.getOperand(0) == Mask)
13041 Y = N0.getOperand(1);
13042 if (N0.getOperand(1) == Mask)
13043 Y = N0.getOperand(0);
13045 // Check to see if the mask appeared in both the AND and ANDNP and
13049 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
13050 if (Mask.getOpcode() != ISD::BITCAST ||
13051 X.getOpcode() != ISD::BITCAST ||
13052 Y.getOpcode() != ISD::BITCAST)
13055 // Look through mask bitcast.
13056 Mask = Mask.getOperand(0);
13057 EVT MaskVT = Mask.getValueType();
13059 // Validate that the Mask operand is a vector sra node. The sra node
13060 // will be an intrinsic.
13061 if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN)
13064 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
13065 // there is no psrai.b
13066 switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) {
13067 case Intrinsic::x86_sse2_psrai_w:
13068 case Intrinsic::x86_sse2_psrai_d:
13070 default: return SDValue();
13073 // Check that the SRA is all signbits.
13074 SDValue SraC = Mask.getOperand(2);
13075 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
13076 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
13077 if ((SraAmt + 1) != EltBits)
13080 DebugLoc DL = N->getDebugLoc();
13082 // Now we know we at least have a plendvb with the mask val. See if
13083 // we can form a psignb/w/d.
13084 // psign = x.type == y.type == mask.type && y = sub(0, x);
13085 X = X.getOperand(0);
13086 Y = Y.getOperand(0);
13087 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
13088 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
13089 X.getValueType() == MaskVT && X.getValueType() == Y.getValueType()){
13092 case 8: Opc = X86ISD::PSIGNB; break;
13093 case 16: Opc = X86ISD::PSIGNW; break;
13094 case 32: Opc = X86ISD::PSIGND; break;
13098 SDValue Sign = DAG.getNode(Opc, DL, MaskVT, X, Mask.getOperand(1));
13099 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Sign);
13102 // PBLENDVB only available on SSE 4.1
13103 if (!Subtarget->hasSSE41())
13106 X = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, X);
13107 Y = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Y);
13108 Mask = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Mask);
13109 Mask = DAG.getNode(X86ISD::PBLENDVB, DL, MVT::v16i8, X, Y, Mask);
13110 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Mask);
13115 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
13116 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
13118 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
13120 if (!N0.hasOneUse() || !N1.hasOneUse())
13123 SDValue ShAmt0 = N0.getOperand(1);
13124 if (ShAmt0.getValueType() != MVT::i8)
13126 SDValue ShAmt1 = N1.getOperand(1);
13127 if (ShAmt1.getValueType() != MVT::i8)
13129 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
13130 ShAmt0 = ShAmt0.getOperand(0);
13131 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
13132 ShAmt1 = ShAmt1.getOperand(0);
13134 DebugLoc DL = N->getDebugLoc();
13135 unsigned Opc = X86ISD::SHLD;
13136 SDValue Op0 = N0.getOperand(0);
13137 SDValue Op1 = N1.getOperand(0);
13138 if (ShAmt0.getOpcode() == ISD::SUB) {
13139 Opc = X86ISD::SHRD;
13140 std::swap(Op0, Op1);
13141 std::swap(ShAmt0, ShAmt1);
13144 unsigned Bits = VT.getSizeInBits();
13145 if (ShAmt1.getOpcode() == ISD::SUB) {
13146 SDValue Sum = ShAmt1.getOperand(0);
13147 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
13148 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
13149 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
13150 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
13151 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
13152 return DAG.getNode(Opc, DL, VT,
13154 DAG.getNode(ISD::TRUNCATE, DL,
13157 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
13158 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
13160 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
13161 return DAG.getNode(Opc, DL, VT,
13162 N0.getOperand(0), N1.getOperand(0),
13163 DAG.getNode(ISD::TRUNCATE, DL,
13170 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
13171 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
13172 const X86Subtarget *Subtarget) {
13173 StoreSDNode *St = cast<StoreSDNode>(N);
13174 EVT VT = St->getValue().getValueType();
13175 EVT StVT = St->getMemoryVT();
13176 DebugLoc dl = St->getDebugLoc();
13177 SDValue StoredVal = St->getOperand(1);
13178 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13180 // If we are saving a concatination of two XMM registers, perform two stores.
13181 // This is better in Sandy Bridge cause one 256-bit mem op is done via two
13182 // 128-bit ones. If in the future the cost becomes only one memory access the
13183 // first version would be better.
13184 if (VT.getSizeInBits() == 256 &&
13185 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
13186 StoredVal.getNumOperands() == 2) {
13188 SDValue Value0 = StoredVal.getOperand(0);
13189 SDValue Value1 = StoredVal.getOperand(1);
13191 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
13192 SDValue Ptr0 = St->getBasePtr();
13193 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
13195 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
13196 St->getPointerInfo(), St->isVolatile(),
13197 St->isNonTemporal(), St->getAlignment());
13198 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
13199 St->getPointerInfo(), St->isVolatile(),
13200 St->isNonTemporal(), St->getAlignment());
13201 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
13204 // Optimize trunc store (of multiple scalars) to shuffle and store.
13205 // First, pack all of the elements in one place. Next, store to memory
13206 // in fewer chunks.
13207 if (St->isTruncatingStore() && VT.isVector()) {
13208 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13209 unsigned NumElems = VT.getVectorNumElements();
13210 assert(StVT != VT && "Cannot truncate to the same type");
13211 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
13212 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
13214 // From, To sizes and ElemCount must be pow of two
13215 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
13216 // We are going to use the original vector elt for storing.
13217 // accumulated smaller vector elements must be a multiple of bigger size.
13218 if (0 != (NumElems * ToSz) % FromSz) return SDValue();
13219 unsigned SizeRatio = FromSz / ToSz;
13221 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
13223 // Create a type on which we perform the shuffle
13224 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
13225 StVT.getScalarType(), NumElems*SizeRatio);
13227 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
13229 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
13230 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
13231 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio;
13233 // Can't shuffle using an illegal type
13234 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
13236 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
13237 DAG.getUNDEF(WideVec.getValueType()),
13238 ShuffleVec.data());
13239 // At this point all of the data is stored at the bottom of the
13240 // register. We now need to save it to mem.
13242 // Find the largest store unit
13243 MVT StoreType = MVT::i8;
13244 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
13245 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
13246 MVT Tp = (MVT::SimpleValueType)tp;
13247 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
13251 // Bitcast the original vector into a vector of store-size units
13252 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
13253 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
13254 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
13255 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
13256 SmallVector<SDValue, 8> Chains;
13257 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
13258 TLI.getPointerTy());
13259 SDValue Ptr = St->getBasePtr();
13261 // Perform one or more big stores into memory.
13262 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) {
13263 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
13264 StoreType, ShuffWide,
13265 DAG.getIntPtrConstant(i));
13266 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
13267 St->getPointerInfo(), St->isVolatile(),
13268 St->isNonTemporal(), St->getAlignment());
13269 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
13270 Chains.push_back(Ch);
13273 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
13278 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
13279 // the FP state in cases where an emms may be missing.
13280 // A preferable solution to the general problem is to figure out the right
13281 // places to insert EMMS. This qualifies as a quick hack.
13283 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
13284 if (VT.getSizeInBits() != 64)
13287 const Function *F = DAG.getMachineFunction().getFunction();
13288 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
13289 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
13290 && Subtarget->hasSSE2();
13291 if ((VT.isVector() ||
13292 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
13293 isa<LoadSDNode>(St->getValue()) &&
13294 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
13295 St->getChain().hasOneUse() && !St->isVolatile()) {
13296 SDNode* LdVal = St->getValue().getNode();
13297 LoadSDNode *Ld = 0;
13298 int TokenFactorIndex = -1;
13299 SmallVector<SDValue, 8> Ops;
13300 SDNode* ChainVal = St->getChain().getNode();
13301 // Must be a store of a load. We currently handle two cases: the load
13302 // is a direct child, and it's under an intervening TokenFactor. It is
13303 // possible to dig deeper under nested TokenFactors.
13304 if (ChainVal == LdVal)
13305 Ld = cast<LoadSDNode>(St->getChain());
13306 else if (St->getValue().hasOneUse() &&
13307 ChainVal->getOpcode() == ISD::TokenFactor) {
13308 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
13309 if (ChainVal->getOperand(i).getNode() == LdVal) {
13310 TokenFactorIndex = i;
13311 Ld = cast<LoadSDNode>(St->getValue());
13313 Ops.push_back(ChainVal->getOperand(i));
13317 if (!Ld || !ISD::isNormalLoad(Ld))
13320 // If this is not the MMX case, i.e. we are just turning i64 load/store
13321 // into f64 load/store, avoid the transformation if there are multiple
13322 // uses of the loaded value.
13323 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
13326 DebugLoc LdDL = Ld->getDebugLoc();
13327 DebugLoc StDL = N->getDebugLoc();
13328 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
13329 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
13331 if (Subtarget->is64Bit() || F64IsLegal) {
13332 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
13333 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
13334 Ld->getPointerInfo(), Ld->isVolatile(),
13335 Ld->isNonTemporal(), Ld->getAlignment());
13336 SDValue NewChain = NewLd.getValue(1);
13337 if (TokenFactorIndex != -1) {
13338 Ops.push_back(NewChain);
13339 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
13342 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
13343 St->getPointerInfo(),
13344 St->isVolatile(), St->isNonTemporal(),
13345 St->getAlignment());
13348 // Otherwise, lower to two pairs of 32-bit loads / stores.
13349 SDValue LoAddr = Ld->getBasePtr();
13350 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
13351 DAG.getConstant(4, MVT::i32));
13353 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
13354 Ld->getPointerInfo(),
13355 Ld->isVolatile(), Ld->isNonTemporal(),
13356 Ld->getAlignment());
13357 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
13358 Ld->getPointerInfo().getWithOffset(4),
13359 Ld->isVolatile(), Ld->isNonTemporal(),
13360 MinAlign(Ld->getAlignment(), 4));
13362 SDValue NewChain = LoLd.getValue(1);
13363 if (TokenFactorIndex != -1) {
13364 Ops.push_back(LoLd);
13365 Ops.push_back(HiLd);
13366 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
13370 LoAddr = St->getBasePtr();
13371 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
13372 DAG.getConstant(4, MVT::i32));
13374 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
13375 St->getPointerInfo(),
13376 St->isVolatile(), St->isNonTemporal(),
13377 St->getAlignment());
13378 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
13379 St->getPointerInfo().getWithOffset(4),
13381 St->isNonTemporal(),
13382 MinAlign(St->getAlignment(), 4));
13383 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
13388 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
13389 /// X86ISD::FXOR nodes.
13390 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
13391 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
13392 // F[X]OR(0.0, x) -> x
13393 // F[X]OR(x, 0.0) -> x
13394 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
13395 if (C->getValueAPF().isPosZero())
13396 return N->getOperand(1);
13397 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
13398 if (C->getValueAPF().isPosZero())
13399 return N->getOperand(0);
13403 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
13404 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
13405 // FAND(0.0, x) -> 0.0
13406 // FAND(x, 0.0) -> 0.0
13407 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
13408 if (C->getValueAPF().isPosZero())
13409 return N->getOperand(0);
13410 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
13411 if (C->getValueAPF().isPosZero())
13412 return N->getOperand(1);
13416 static SDValue PerformBTCombine(SDNode *N,
13418 TargetLowering::DAGCombinerInfo &DCI) {
13419 // BT ignores high bits in the bit index operand.
13420 SDValue Op1 = N->getOperand(1);
13421 if (Op1.hasOneUse()) {
13422 unsigned BitWidth = Op1.getValueSizeInBits();
13423 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
13424 APInt KnownZero, KnownOne;
13425 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
13426 !DCI.isBeforeLegalizeOps());
13427 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13428 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
13429 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
13430 DCI.CommitTargetLoweringOpt(TLO);
13435 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
13436 SDValue Op = N->getOperand(0);
13437 if (Op.getOpcode() == ISD::BITCAST)
13438 Op = Op.getOperand(0);
13439 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
13440 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
13441 VT.getVectorElementType().getSizeInBits() ==
13442 OpVT.getVectorElementType().getSizeInBits()) {
13443 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
13448 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
13449 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
13450 // (and (i32 x86isd::setcc_carry), 1)
13451 // This eliminates the zext. This transformation is necessary because
13452 // ISD::SETCC is always legalized to i8.
13453 DebugLoc dl = N->getDebugLoc();
13454 SDValue N0 = N->getOperand(0);
13455 EVT VT = N->getValueType(0);
13456 if (N0.getOpcode() == ISD::AND &&
13458 N0.getOperand(0).hasOneUse()) {
13459 SDValue N00 = N0.getOperand(0);
13460 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
13462 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
13463 if (!C || C->getZExtValue() != 1)
13465 return DAG.getNode(ISD::AND, dl, VT,
13466 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
13467 N00.getOperand(0), N00.getOperand(1)),
13468 DAG.getConstant(1, VT));
13474 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
13475 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
13476 unsigned X86CC = N->getConstantOperandVal(0);
13477 SDValue EFLAG = N->getOperand(1);
13478 DebugLoc DL = N->getDebugLoc();
13480 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
13481 // a zext and produces an all-ones bit which is more useful than 0/1 in some
13483 if (X86CC == X86::COND_B)
13484 return DAG.getNode(ISD::AND, DL, MVT::i8,
13485 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
13486 DAG.getConstant(X86CC, MVT::i8), EFLAG),
13487 DAG.getConstant(1, MVT::i8));
13492 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
13493 const X86TargetLowering *XTLI) {
13494 SDValue Op0 = N->getOperand(0);
13495 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
13496 // a 32-bit target where SSE doesn't support i64->FP operations.
13497 if (Op0.getOpcode() == ISD::LOAD) {
13498 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
13499 EVT VT = Ld->getValueType(0);
13500 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
13501 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
13502 !XTLI->getSubtarget()->is64Bit() &&
13503 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
13504 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
13505 Ld->getChain(), Op0, DAG);
13506 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
13513 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
13514 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
13515 X86TargetLowering::DAGCombinerInfo &DCI) {
13516 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
13517 // the result is either zero or one (depending on the input carry bit).
13518 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
13519 if (X86::isZeroNode(N->getOperand(0)) &&
13520 X86::isZeroNode(N->getOperand(1)) &&
13521 // We don't have a good way to replace an EFLAGS use, so only do this when
13523 SDValue(N, 1).use_empty()) {
13524 DebugLoc DL = N->getDebugLoc();
13525 EVT VT = N->getValueType(0);
13526 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
13527 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
13528 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
13529 DAG.getConstant(X86::COND_B,MVT::i8),
13531 DAG.getConstant(1, VT));
13532 return DCI.CombineTo(N, Res1, CarryOut);
13538 // fold (add Y, (sete X, 0)) -> adc 0, Y
13539 // (add Y, (setne X, 0)) -> sbb -1, Y
13540 // (sub (sete X, 0), Y) -> sbb 0, Y
13541 // (sub (setne X, 0), Y) -> adc -1, Y
13542 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
13543 DebugLoc DL = N->getDebugLoc();
13545 // Look through ZExts.
13546 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
13547 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
13550 SDValue SetCC = Ext.getOperand(0);
13551 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
13554 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
13555 if (CC != X86::COND_E && CC != X86::COND_NE)
13558 SDValue Cmp = SetCC.getOperand(1);
13559 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
13560 !X86::isZeroNode(Cmp.getOperand(1)) ||
13561 !Cmp.getOperand(0).getValueType().isInteger())
13564 SDValue CmpOp0 = Cmp.getOperand(0);
13565 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
13566 DAG.getConstant(1, CmpOp0.getValueType()));
13568 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
13569 if (CC == X86::COND_NE)
13570 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
13571 DL, OtherVal.getValueType(), OtherVal,
13572 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
13573 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
13574 DL, OtherVal.getValueType(), OtherVal,
13575 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
13578 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG) {
13579 SDValue Op0 = N->getOperand(0);
13580 SDValue Op1 = N->getOperand(1);
13582 // X86 can't encode an immediate LHS of a sub. See if we can push the
13583 // negation into a preceding instruction.
13584 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
13585 // If the RHS of the sub is a XOR with one use and a constant, invert the
13586 // immediate. Then add one to the LHS of the sub so we can turn
13587 // X-Y -> X+~Y+1, saving one register.
13588 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
13589 isa<ConstantSDNode>(Op1.getOperand(1))) {
13590 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
13591 EVT VT = Op0.getValueType();
13592 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
13594 DAG.getConstant(~XorC, VT));
13595 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
13596 DAG.getConstant(C->getAPIntValue()+1, VT));
13600 return OptimizeConditionalInDecrement(N, DAG);
13603 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
13604 DAGCombinerInfo &DCI) const {
13605 SelectionDAG &DAG = DCI.DAG;
13606 switch (N->getOpcode()) {
13608 case ISD::EXTRACT_VECTOR_ELT:
13609 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
13610 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
13611 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
13612 case ISD::ADD: return OptimizeConditionalInDecrement(N, DAG);
13613 case ISD::SUB: return PerformSubCombine(N, DAG);
13614 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
13615 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
13618 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
13619 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
13620 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
13621 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
13622 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
13624 case X86ISD::FOR: return PerformFORCombine(N, DAG);
13625 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
13626 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
13627 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
13628 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
13629 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
13630 case X86ISD::SHUFPS: // Handle all target specific shuffles
13631 case X86ISD::SHUFPD:
13632 case X86ISD::PALIGN:
13633 case X86ISD::PUNPCKHBW:
13634 case X86ISD::PUNPCKHWD:
13635 case X86ISD::PUNPCKHDQ:
13636 case X86ISD::PUNPCKHQDQ:
13637 case X86ISD::UNPCKHPS:
13638 case X86ISD::UNPCKHPD:
13639 case X86ISD::VUNPCKHPSY:
13640 case X86ISD::VUNPCKHPDY:
13641 case X86ISD::PUNPCKLBW:
13642 case X86ISD::PUNPCKLWD:
13643 case X86ISD::PUNPCKLDQ:
13644 case X86ISD::PUNPCKLQDQ:
13645 case X86ISD::UNPCKLPS:
13646 case X86ISD::UNPCKLPD:
13647 case X86ISD::VUNPCKLPSY:
13648 case X86ISD::VUNPCKLPDY:
13649 case X86ISD::MOVHLPS:
13650 case X86ISD::MOVLHPS:
13651 case X86ISD::PSHUFD:
13652 case X86ISD::PSHUFHW:
13653 case X86ISD::PSHUFLW:
13654 case X86ISD::MOVSS:
13655 case X86ISD::MOVSD:
13656 case X86ISD::VPERMILPS:
13657 case X86ISD::VPERMILPSY:
13658 case X86ISD::VPERMILPD:
13659 case X86ISD::VPERMILPDY:
13660 case X86ISD::VPERM2F128:
13661 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
13667 /// isTypeDesirableForOp - Return true if the target has native support for
13668 /// the specified value type and it is 'desirable' to use the type for the
13669 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
13670 /// instruction encodings are longer and some i16 instructions are slow.
13671 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
13672 if (!isTypeLegal(VT))
13674 if (VT != MVT::i16)
13681 case ISD::SIGN_EXTEND:
13682 case ISD::ZERO_EXTEND:
13683 case ISD::ANY_EXTEND:
13696 /// IsDesirableToPromoteOp - This method query the target whether it is
13697 /// beneficial for dag combiner to promote the specified node. If true, it
13698 /// should return the desired promotion type by reference.
13699 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
13700 EVT VT = Op.getValueType();
13701 if (VT != MVT::i16)
13704 bool Promote = false;
13705 bool Commute = false;
13706 switch (Op.getOpcode()) {
13709 LoadSDNode *LD = cast<LoadSDNode>(Op);
13710 // If the non-extending load has a single use and it's not live out, then it
13711 // might be folded.
13712 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
13713 Op.hasOneUse()*/) {
13714 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13715 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
13716 // The only case where we'd want to promote LOAD (rather then it being
13717 // promoted as an operand is when it's only use is liveout.
13718 if (UI->getOpcode() != ISD::CopyToReg)
13725 case ISD::SIGN_EXTEND:
13726 case ISD::ZERO_EXTEND:
13727 case ISD::ANY_EXTEND:
13732 SDValue N0 = Op.getOperand(0);
13733 // Look out for (store (shl (load), x)).
13734 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
13747 SDValue N0 = Op.getOperand(0);
13748 SDValue N1 = Op.getOperand(1);
13749 if (!Commute && MayFoldLoad(N1))
13751 // Avoid disabling potential load folding opportunities.
13752 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
13754 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
13764 //===----------------------------------------------------------------------===//
13765 // X86 Inline Assembly Support
13766 //===----------------------------------------------------------------------===//
13768 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
13769 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
13771 std::string AsmStr = IA->getAsmString();
13773 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
13774 SmallVector<StringRef, 4> AsmPieces;
13775 SplitString(AsmStr, AsmPieces, ";\n");
13777 switch (AsmPieces.size()) {
13778 default: return false;
13780 AsmStr = AsmPieces[0];
13782 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
13784 // FIXME: this should verify that we are targeting a 486 or better. If not,
13785 // we will turn this bswap into something that will be lowered to logical ops
13786 // instead of emitting the bswap asm. For now, we don't support 486 or lower
13787 // so don't worry about this.
13789 if (AsmPieces.size() == 2 &&
13790 (AsmPieces[0] == "bswap" ||
13791 AsmPieces[0] == "bswapq" ||
13792 AsmPieces[0] == "bswapl") &&
13793 (AsmPieces[1] == "$0" ||
13794 AsmPieces[1] == "${0:q}")) {
13795 // No need to check constraints, nothing other than the equivalent of
13796 // "=r,0" would be valid here.
13797 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
13798 if (!Ty || Ty->getBitWidth() % 16 != 0)
13800 return IntrinsicLowering::LowerToByteSwap(CI);
13802 // rorw $$8, ${0:w} --> llvm.bswap.i16
13803 if (CI->getType()->isIntegerTy(16) &&
13804 AsmPieces.size() == 3 &&
13805 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") &&
13806 AsmPieces[1] == "$$8," &&
13807 AsmPieces[2] == "${0:w}" &&
13808 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
13810 const std::string &ConstraintsStr = IA->getConstraintString();
13811 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
13812 std::sort(AsmPieces.begin(), AsmPieces.end());
13813 if (AsmPieces.size() == 4 &&
13814 AsmPieces[0] == "~{cc}" &&
13815 AsmPieces[1] == "~{dirflag}" &&
13816 AsmPieces[2] == "~{flags}" &&
13817 AsmPieces[3] == "~{fpsr}") {
13818 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
13819 if (!Ty || Ty->getBitWidth() % 16 != 0)
13821 return IntrinsicLowering::LowerToByteSwap(CI);
13826 if (CI->getType()->isIntegerTy(32) &&
13827 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
13828 SmallVector<StringRef, 4> Words;
13829 SplitString(AsmPieces[0], Words, " \t,");
13830 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
13831 Words[2] == "${0:w}") {
13833 SplitString(AsmPieces[1], Words, " \t,");
13834 if (Words.size() == 3 && Words[0] == "rorl" && Words[1] == "$$16" &&
13835 Words[2] == "$0") {
13837 SplitString(AsmPieces[2], Words, " \t,");
13838 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
13839 Words[2] == "${0:w}") {
13841 const std::string &ConstraintsStr = IA->getConstraintString();
13842 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
13843 std::sort(AsmPieces.begin(), AsmPieces.end());
13844 if (AsmPieces.size() == 4 &&
13845 AsmPieces[0] == "~{cc}" &&
13846 AsmPieces[1] == "~{dirflag}" &&
13847 AsmPieces[2] == "~{flags}" &&
13848 AsmPieces[3] == "~{fpsr}") {
13849 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
13850 if (!Ty || Ty->getBitWidth() % 16 != 0)
13852 return IntrinsicLowering::LowerToByteSwap(CI);
13859 if (CI->getType()->isIntegerTy(64)) {
13860 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
13861 if (Constraints.size() >= 2 &&
13862 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
13863 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
13864 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
13865 SmallVector<StringRef, 4> Words;
13866 SplitString(AsmPieces[0], Words, " \t");
13867 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
13869 SplitString(AsmPieces[1], Words, " \t");
13870 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
13872 SplitString(AsmPieces[2], Words, " \t,");
13873 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
13874 Words[2] == "%edx") {
13875 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
13876 if (!Ty || Ty->getBitWidth() % 16 != 0)
13878 return IntrinsicLowering::LowerToByteSwap(CI);
13891 /// getConstraintType - Given a constraint letter, return the type of
13892 /// constraint it is for this target.
13893 X86TargetLowering::ConstraintType
13894 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
13895 if (Constraint.size() == 1) {
13896 switch (Constraint[0]) {
13907 return C_RegisterClass;
13931 return TargetLowering::getConstraintType(Constraint);
13934 /// Examine constraint type and operand type and determine a weight value.
13935 /// This object must already have been set up with the operand type
13936 /// and the current alternative constraint selected.
13937 TargetLowering::ConstraintWeight
13938 X86TargetLowering::getSingleConstraintMatchWeight(
13939 AsmOperandInfo &info, const char *constraint) const {
13940 ConstraintWeight weight = CW_Invalid;
13941 Value *CallOperandVal = info.CallOperandVal;
13942 // If we don't have a value, we can't do a match,
13943 // but allow it at the lowest weight.
13944 if (CallOperandVal == NULL)
13946 Type *type = CallOperandVal->getType();
13947 // Look at the constraint type.
13948 switch (*constraint) {
13950 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
13961 if (CallOperandVal->getType()->isIntegerTy())
13962 weight = CW_SpecificReg;
13967 if (type->isFloatingPointTy())
13968 weight = CW_SpecificReg;
13971 if (type->isX86_MMXTy() && Subtarget->hasMMX())
13972 weight = CW_SpecificReg;
13976 if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM())
13977 weight = CW_Register;
13980 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
13981 if (C->getZExtValue() <= 31)
13982 weight = CW_Constant;
13986 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13987 if (C->getZExtValue() <= 63)
13988 weight = CW_Constant;
13992 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13993 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
13994 weight = CW_Constant;
13998 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
13999 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
14000 weight = CW_Constant;
14004 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14005 if (C->getZExtValue() <= 3)
14006 weight = CW_Constant;
14010 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14011 if (C->getZExtValue() <= 0xff)
14012 weight = CW_Constant;
14017 if (dyn_cast<ConstantFP>(CallOperandVal)) {
14018 weight = CW_Constant;
14022 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14023 if ((C->getSExtValue() >= -0x80000000LL) &&
14024 (C->getSExtValue() <= 0x7fffffffLL))
14025 weight = CW_Constant;
14029 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14030 if (C->getZExtValue() <= 0xffffffff)
14031 weight = CW_Constant;
14038 /// LowerXConstraint - try to replace an X constraint, which matches anything,
14039 /// with another that has more specific requirements based on the type of the
14040 /// corresponding operand.
14041 const char *X86TargetLowering::
14042 LowerXConstraint(EVT ConstraintVT) const {
14043 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
14044 // 'f' like normal targets.
14045 if (ConstraintVT.isFloatingPoint()) {
14046 if (Subtarget->hasXMMInt())
14048 if (Subtarget->hasXMM())
14052 return TargetLowering::LowerXConstraint(ConstraintVT);
14055 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
14056 /// vector. If it is invalid, don't add anything to Ops.
14057 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
14058 std::string &Constraint,
14059 std::vector<SDValue>&Ops,
14060 SelectionDAG &DAG) const {
14061 SDValue Result(0, 0);
14063 // Only support length 1 constraints for now.
14064 if (Constraint.length() > 1) return;
14066 char ConstraintLetter = Constraint[0];
14067 switch (ConstraintLetter) {
14070 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14071 if (C->getZExtValue() <= 31) {
14072 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14078 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14079 if (C->getZExtValue() <= 63) {
14080 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14086 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14087 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
14088 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14094 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14095 if (C->getZExtValue() <= 255) {
14096 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14102 // 32-bit signed value
14103 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14104 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
14105 C->getSExtValue())) {
14106 // Widen to 64 bits here to get it sign extended.
14107 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
14110 // FIXME gcc accepts some relocatable values here too, but only in certain
14111 // memory models; it's complicated.
14116 // 32-bit unsigned value
14117 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14118 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
14119 C->getZExtValue())) {
14120 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14124 // FIXME gcc accepts some relocatable values here too, but only in certain
14125 // memory models; it's complicated.
14129 // Literal immediates are always ok.
14130 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
14131 // Widen to 64 bits here to get it sign extended.
14132 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
14136 // In any sort of PIC mode addresses need to be computed at runtime by
14137 // adding in a register or some sort of table lookup. These can't
14138 // be used as immediates.
14139 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
14142 // If we are in non-pic codegen mode, we allow the address of a global (with
14143 // an optional displacement) to be used with 'i'.
14144 GlobalAddressSDNode *GA = 0;
14145 int64_t Offset = 0;
14147 // Match either (GA), (GA+C), (GA+C1+C2), etc.
14149 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
14150 Offset += GA->getOffset();
14152 } else if (Op.getOpcode() == ISD::ADD) {
14153 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
14154 Offset += C->getZExtValue();
14155 Op = Op.getOperand(0);
14158 } else if (Op.getOpcode() == ISD::SUB) {
14159 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
14160 Offset += -C->getZExtValue();
14161 Op = Op.getOperand(0);
14166 // Otherwise, this isn't something we can handle, reject it.
14170 const GlobalValue *GV = GA->getGlobal();
14171 // If we require an extra load to get this address, as in PIC mode, we
14172 // can't accept it.
14173 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
14174 getTargetMachine())))
14177 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
14178 GA->getValueType(0), Offset);
14183 if (Result.getNode()) {
14184 Ops.push_back(Result);
14187 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
14190 std::pair<unsigned, const TargetRegisterClass*>
14191 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
14193 // First, see if this is a constraint that directly corresponds to an LLVM
14195 if (Constraint.size() == 1) {
14196 // GCC Constraint Letters
14197 switch (Constraint[0]) {
14199 // TODO: Slight differences here in allocation order and leaving
14200 // RIP in the class. Do they matter any more here than they do
14201 // in the normal allocation?
14202 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
14203 if (Subtarget->is64Bit()) {
14204 if (VT == MVT::i32 || VT == MVT::f32)
14205 return std::make_pair(0U, X86::GR32RegisterClass);
14206 else if (VT == MVT::i16)
14207 return std::make_pair(0U, X86::GR16RegisterClass);
14208 else if (VT == MVT::i8 || VT == MVT::i1)
14209 return std::make_pair(0U, X86::GR8RegisterClass);
14210 else if (VT == MVT::i64 || VT == MVT::f64)
14211 return std::make_pair(0U, X86::GR64RegisterClass);
14214 // 32-bit fallthrough
14215 case 'Q': // Q_REGS
14216 if (VT == MVT::i32 || VT == MVT::f32)
14217 return std::make_pair(0U, X86::GR32_ABCDRegisterClass);
14218 else if (VT == MVT::i16)
14219 return std::make_pair(0U, X86::GR16_ABCDRegisterClass);
14220 else if (VT == MVT::i8 || VT == MVT::i1)
14221 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass);
14222 else if (VT == MVT::i64)
14223 return std::make_pair(0U, X86::GR64_ABCDRegisterClass);
14225 case 'r': // GENERAL_REGS
14226 case 'l': // INDEX_REGS
14227 if (VT == MVT::i8 || VT == MVT::i1)
14228 return std::make_pair(0U, X86::GR8RegisterClass);
14229 if (VT == MVT::i16)
14230 return std::make_pair(0U, X86::GR16RegisterClass);
14231 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
14232 return std::make_pair(0U, X86::GR32RegisterClass);
14233 return std::make_pair(0U, X86::GR64RegisterClass);
14234 case 'R': // LEGACY_REGS
14235 if (VT == MVT::i8 || VT == MVT::i1)
14236 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
14237 if (VT == MVT::i16)
14238 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
14239 if (VT == MVT::i32 || !Subtarget->is64Bit())
14240 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
14241 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
14242 case 'f': // FP Stack registers.
14243 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
14244 // value to the correct fpstack register class.
14245 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
14246 return std::make_pair(0U, X86::RFP32RegisterClass);
14247 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
14248 return std::make_pair(0U, X86::RFP64RegisterClass);
14249 return std::make_pair(0U, X86::RFP80RegisterClass);
14250 case 'y': // MMX_REGS if MMX allowed.
14251 if (!Subtarget->hasMMX()) break;
14252 return std::make_pair(0U, X86::VR64RegisterClass);
14253 case 'Y': // SSE_REGS if SSE2 allowed
14254 if (!Subtarget->hasXMMInt()) break;
14256 case 'x': // SSE_REGS if SSE1 allowed
14257 if (!Subtarget->hasXMM()) break;
14259 switch (VT.getSimpleVT().SimpleTy) {
14261 // Scalar SSE types.
14264 return std::make_pair(0U, X86::FR32RegisterClass);
14267 return std::make_pair(0U, X86::FR64RegisterClass);
14275 return std::make_pair(0U, X86::VR128RegisterClass);
14281 // Use the default implementation in TargetLowering to convert the register
14282 // constraint into a member of a register class.
14283 std::pair<unsigned, const TargetRegisterClass*> Res;
14284 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
14286 // Not found as a standard register?
14287 if (Res.second == 0) {
14288 // Map st(0) -> st(7) -> ST0
14289 if (Constraint.size() == 7 && Constraint[0] == '{' &&
14290 tolower(Constraint[1]) == 's' &&
14291 tolower(Constraint[2]) == 't' &&
14292 Constraint[3] == '(' &&
14293 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
14294 Constraint[5] == ')' &&
14295 Constraint[6] == '}') {
14297 Res.first = X86::ST0+Constraint[4]-'0';
14298 Res.second = X86::RFP80RegisterClass;
14302 // GCC allows "st(0)" to be called just plain "st".
14303 if (StringRef("{st}").equals_lower(Constraint)) {
14304 Res.first = X86::ST0;
14305 Res.second = X86::RFP80RegisterClass;
14310 if (StringRef("{flags}").equals_lower(Constraint)) {
14311 Res.first = X86::EFLAGS;
14312 Res.second = X86::CCRRegisterClass;
14316 // 'A' means EAX + EDX.
14317 if (Constraint == "A") {
14318 Res.first = X86::EAX;
14319 Res.second = X86::GR32_ADRegisterClass;
14325 // Otherwise, check to see if this is a register class of the wrong value
14326 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
14327 // turn into {ax},{dx}.
14328 if (Res.second->hasType(VT))
14329 return Res; // Correct type already, nothing to do.
14331 // All of the single-register GCC register classes map their values onto
14332 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
14333 // really want an 8-bit or 32-bit register, map to the appropriate register
14334 // class and return the appropriate register.
14335 if (Res.second == X86::GR16RegisterClass) {
14336 if (VT == MVT::i8) {
14337 unsigned DestReg = 0;
14338 switch (Res.first) {
14340 case X86::AX: DestReg = X86::AL; break;
14341 case X86::DX: DestReg = X86::DL; break;
14342 case X86::CX: DestReg = X86::CL; break;
14343 case X86::BX: DestReg = X86::BL; break;
14346 Res.first = DestReg;
14347 Res.second = X86::GR8RegisterClass;
14349 } else if (VT == MVT::i32) {
14350 unsigned DestReg = 0;
14351 switch (Res.first) {
14353 case X86::AX: DestReg = X86::EAX; break;
14354 case X86::DX: DestReg = X86::EDX; break;
14355 case X86::CX: DestReg = X86::ECX; break;
14356 case X86::BX: DestReg = X86::EBX; break;
14357 case X86::SI: DestReg = X86::ESI; break;
14358 case X86::DI: DestReg = X86::EDI; break;
14359 case X86::BP: DestReg = X86::EBP; break;
14360 case X86::SP: DestReg = X86::ESP; break;
14363 Res.first = DestReg;
14364 Res.second = X86::GR32RegisterClass;
14366 } else if (VT == MVT::i64) {
14367 unsigned DestReg = 0;
14368 switch (Res.first) {
14370 case X86::AX: DestReg = X86::RAX; break;
14371 case X86::DX: DestReg = X86::RDX; break;
14372 case X86::CX: DestReg = X86::RCX; break;
14373 case X86::BX: DestReg = X86::RBX; break;
14374 case X86::SI: DestReg = X86::RSI; break;
14375 case X86::DI: DestReg = X86::RDI; break;
14376 case X86::BP: DestReg = X86::RBP; break;
14377 case X86::SP: DestReg = X86::RSP; break;
14380 Res.first = DestReg;
14381 Res.second = X86::GR64RegisterClass;
14384 } else if (Res.second == X86::FR32RegisterClass ||
14385 Res.second == X86::FR64RegisterClass ||
14386 Res.second == X86::VR128RegisterClass) {
14387 // Handle references to XMM physical registers that got mapped into the
14388 // wrong class. This can happen with constraints like {xmm0} where the
14389 // target independent register mapper will just pick the first match it can
14390 // find, ignoring the required type.
14391 if (VT == MVT::f32)
14392 Res.second = X86::FR32RegisterClass;
14393 else if (VT == MVT::f64)
14394 Res.second = X86::FR64RegisterClass;
14395 else if (X86::VR128RegisterClass->hasType(VT))
14396 Res.second = X86::VR128RegisterClass;