1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86TargetMachine.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Function.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/SSARegMap.h"
26 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Support/CommandLine.h"
31 static cl::opt<bool> EnableFastCC("enable-x86-fastcc", cl::Hidden,
32 cl::desc("Enable fastcc on X86"));
34 X86TargetLowering::X86TargetLowering(TargetMachine &TM)
35 : TargetLowering(TM) {
36 // Set up the TargetLowering object.
38 // X86 is weird, it always uses i8 for shift amounts and setcc results.
39 setShiftAmountType(MVT::i8);
40 setSetCCResultType(MVT::i8);
41 setSetCCResultContents(ZeroOrOneSetCCResult);
42 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
43 setStackPointerRegisterToSaveRestore(X86::ESP);
45 // Set up the register classes.
46 addRegisterClass(MVT::i8, X86::R8RegisterClass);
47 addRegisterClass(MVT::i16, X86::R16RegisterClass);
48 addRegisterClass(MVT::i32, X86::R32RegisterClass);
50 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
52 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
53 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
54 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
55 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
57 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
59 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
60 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
63 // We can handle SINT_TO_FP and FP_TO_SINT from/TO i64 even though i64
65 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
66 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
67 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
68 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
71 // Handle FP_TO_UINT by promoting the destination to a larger signed
73 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
74 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
75 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
78 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
80 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
82 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
83 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
84 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
86 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
87 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
90 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
92 setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
93 setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
94 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
95 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
96 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
97 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
98 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
99 setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
100 setOperationAction(ISD::FREM , MVT::f64 , Expand);
101 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
102 setOperationAction(ISD::CTTZ , MVT::i8 , Expand);
103 setOperationAction(ISD::CTLZ , MVT::i8 , Expand);
104 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
105 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
106 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
107 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
108 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
109 setOperationAction(ISD::CTLZ , MVT::i32 , Expand);
110 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
113 setOperationAction(ISD::BSWAP , MVT::i32 , Expand);
114 setOperationAction(ISD::ROTL , MVT::i8 , Expand);
115 setOperationAction(ISD::ROTR , MVT::i8 , Expand);
116 setOperationAction(ISD::ROTL , MVT::i16 , Expand);
117 setOperationAction(ISD::ROTR , MVT::i16 , Expand);
118 setOperationAction(ISD::ROTL , MVT::i32 , Expand);
119 setOperationAction(ISD::ROTR , MVT::i32 , Expand);
121 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
123 setOperationAction(ISD::READIO , MVT::i1 , Expand);
124 setOperationAction(ISD::READIO , MVT::i8 , Expand);
125 setOperationAction(ISD::READIO , MVT::i16 , Expand);
126 setOperationAction(ISD::READIO , MVT::i32 , Expand);
127 setOperationAction(ISD::WRITEIO , MVT::i1 , Expand);
128 setOperationAction(ISD::WRITEIO , MVT::i8 , Expand);
129 setOperationAction(ISD::WRITEIO , MVT::i16 , Expand);
130 setOperationAction(ISD::WRITEIO , MVT::i32 , Expand);
132 // These should be promoted to a larger select which is supported.
133 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
134 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
136 // X86 wants to expand cmov itself.
137 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
138 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
139 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
140 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
141 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
142 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
143 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
144 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
145 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
146 // X86 ret instruction may pop stack.
147 setOperationAction(ISD::RET , MVT::Other, Custom);
149 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
150 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
151 setOperationAction(ISD::ADD_PARTS , MVT::i32 , Custom);
152 setOperationAction(ISD::SUB_PARTS , MVT::i32 , Custom);
153 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
154 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
155 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
156 // X86 wants to expand memset / memcpy itself.
157 setOperationAction(ISD::MEMSET , MVT::Other, Custom);
158 setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
161 // We don't have line number support yet.
162 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
163 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
164 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
166 // Expand to the default code.
167 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
168 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
169 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
172 // Set up the FP register classes.
173 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
174 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
176 // SSE has no load+extend ops
177 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
178 setOperationAction(ISD::ZEXTLOAD, MVT::f32, Expand);
180 // SSE has no i16 to fp conversion, only i32
181 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
182 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
184 // Expand FP_TO_UINT into a select.
185 // FIXME: We would like to use a Custom expander here eventually to do
186 // the optimal thing for SSE vs. the default expansion in the legalizer.
187 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
189 // We don't support sin/cos/sqrt/fmod
190 setOperationAction(ISD::FSIN , MVT::f64, Expand);
191 setOperationAction(ISD::FCOS , MVT::f64, Expand);
192 setOperationAction(ISD::FABS , MVT::f64, Expand);
193 setOperationAction(ISD::FNEG , MVT::f64, Expand);
194 setOperationAction(ISD::FREM , MVT::f64, Expand);
195 setOperationAction(ISD::FSIN , MVT::f32, Expand);
196 setOperationAction(ISD::FCOS , MVT::f32, Expand);
197 setOperationAction(ISD::FABS , MVT::f32, Expand);
198 setOperationAction(ISD::FNEG , MVT::f32, Expand);
199 setOperationAction(ISD::FREM , MVT::f32, Expand);
201 addLegalFPImmediate(+0.0); // xorps / xorpd
203 // Set up the FP register classes.
204 addRegisterClass(MVT::f64, X86::RFPRegisterClass);
207 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Custom);
208 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
212 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
213 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
216 addLegalFPImmediate(+0.0); // FLD0
217 addLegalFPImmediate(+1.0); // FLD1
218 addLegalFPImmediate(-0.0); // FLD0/FCHS
219 addLegalFPImmediate(-1.0); // FLD1/FCHS
221 computeRegisterProperties();
223 maxStoresPerMemSet = 8; // For %llvm.memset -> sequence of stores
224 maxStoresPerMemCpy = 8; // For %llvm.memcpy -> sequence of stores
225 maxStoresPerMemMove = 8; // For %llvm.memmove -> sequence of stores
226 allowUnalignedMemoryAccesses = true; // x86 supports it!
229 std::vector<SDOperand>
230 X86TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
231 if (F.getCallingConv() == CallingConv::Fast && EnableFastCC)
232 return LowerFastCCArguments(F, DAG);
233 return LowerCCCArguments(F, DAG);
236 std::pair<SDOperand, SDOperand>
237 X86TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
238 bool isVarArg, unsigned CallingConv,
240 SDOperand Callee, ArgListTy &Args,
242 assert((!isVarArg || CallingConv == CallingConv::C) &&
243 "Only C takes varargs!");
245 // If the callee is a GlobalAddress node (quite common, every direct call is)
246 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
247 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
248 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
249 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
250 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
252 if (CallingConv == CallingConv::Fast && EnableFastCC)
253 return LowerFastCCCallTo(Chain, RetTy, isTailCall, Callee, Args, DAG);
254 return LowerCCCCallTo(Chain, RetTy, isVarArg, isTailCall, Callee, Args, DAG);
257 SDOperand X86TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
260 return DAG.getNode(ISD::RET, MVT::Other, Chain, Op);
263 MVT::ValueType OpVT = Op.getValueType();
265 default: assert(0 && "Unknown type to return!");
267 Copy = DAG.getCopyToReg(Chain, X86::EAX, Op, SDOperand());
270 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
271 DAG.getConstant(1, MVT::i32));
272 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
273 DAG.getConstant(0, MVT::i32));
274 Copy = DAG.getCopyToReg(Chain, X86::EDX, Hi, SDOperand());
275 Copy = DAG.getCopyToReg(Copy, X86::EAX, Lo, Copy.getValue(1));
281 if (OpVT == MVT::f32)
282 Op = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Op);
283 std::vector<MVT::ValueType> Tys;
284 Tys.push_back(MVT::Other);
285 Tys.push_back(MVT::Flag);
286 std::vector<SDOperand> Ops;
287 Ops.push_back(Chain);
289 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
291 // Spill the value to memory and reload it into top of stack.
292 unsigned Size = MVT::getSizeInBits(OpVT)/8;
293 MachineFunction &MF = DAG.getMachineFunction();
294 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
295 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
296 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Op,
297 StackSlot, DAG.getSrcValue(NULL));
298 std::vector<MVT::ValueType> Tys;
299 Tys.push_back(MVT::f64);
300 Tys.push_back(MVT::Other);
301 std::vector<SDOperand> Ops;
302 Ops.push_back(Chain);
303 Ops.push_back(StackSlot);
304 Ops.push_back(DAG.getValueType(OpVT));
305 Copy = DAG.getNode(X86ISD::FLD, Tys, Ops);
307 Tys.push_back(MVT::Other);
308 Tys.push_back(MVT::Flag);
310 Ops.push_back(Copy.getValue(1));
312 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
317 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other,
318 Copy, DAG.getConstant(getBytesToPopOnReturn(), MVT::i16),
322 //===----------------------------------------------------------------------===//
323 // C Calling Convention implementation
324 //===----------------------------------------------------------------------===//
326 std::vector<SDOperand>
327 X86TargetLowering::LowerCCCArguments(Function &F, SelectionDAG &DAG) {
328 std::vector<SDOperand> ArgValues;
330 MachineFunction &MF = DAG.getMachineFunction();
331 MachineFrameInfo *MFI = MF.getFrameInfo();
333 // Add DAG nodes to load the arguments... On entry to a function on the X86,
334 // the stack frame looks like this:
336 // [ESP] -- return address
337 // [ESP + 4] -- first argument (leftmost lexically)
338 // [ESP + 8] -- second argument, if first argument is four bytes in size
341 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
342 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
343 MVT::ValueType ObjectVT = getValueType(I->getType());
344 unsigned ArgIncrement = 4;
347 default: assert(0 && "Unhandled argument type!");
349 case MVT::i8: ObjSize = 1; break;
350 case MVT::i16: ObjSize = 2; break;
351 case MVT::i32: ObjSize = 4; break;
352 case MVT::i64: ObjSize = ArgIncrement = 8; break;
353 case MVT::f32: ObjSize = 4; break;
354 case MVT::f64: ObjSize = ArgIncrement = 8; break;
356 // Create the frame index object for this incoming parameter...
357 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
359 // Create the SelectionDAG nodes corresponding to a load from this parameter
360 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
362 // Don't codegen dead arguments. FIXME: remove this check when we can nuke
366 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
367 DAG.getSrcValue(NULL));
369 if (MVT::isInteger(ObjectVT))
370 ArgValue = DAG.getConstant(0, ObjectVT);
372 ArgValue = DAG.getConstantFP(0, ObjectVT);
374 ArgValues.push_back(ArgValue);
376 ArgOffset += ArgIncrement; // Move on to the next argument...
379 // If the function takes variable number of arguments, make a frame index for
380 // the start of the first vararg value... for expansion of llvm.va_start.
382 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
383 ReturnAddrIndex = 0; // No return address slot generated yet.
384 BytesToPopOnReturn = 0; // Callee pops nothing.
385 BytesCallerReserves = ArgOffset;
387 // Finally, inform the code generator which regs we return values in.
388 switch (getValueType(F.getReturnType())) {
389 default: assert(0 && "Unknown type!");
390 case MVT::isVoid: break;
395 MF.addLiveOut(X86::EAX);
398 MF.addLiveOut(X86::EAX);
399 MF.addLiveOut(X86::EDX);
403 MF.addLiveOut(X86::ST0);
409 std::pair<SDOperand, SDOperand>
410 X86TargetLowering::LowerCCCCallTo(SDOperand Chain, const Type *RetTy,
411 bool isVarArg, bool isTailCall,
412 SDOperand Callee, ArgListTy &Args,
414 // Count how many bytes are to be pushed on the stack.
415 unsigned NumBytes = 0;
419 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
420 DAG.getConstant(0, getPointerTy()));
422 for (unsigned i = 0, e = Args.size(); i != e; ++i)
423 switch (getValueType(Args[i].second)) {
424 default: assert(0 && "Unknown value type!");
438 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
439 DAG.getConstant(NumBytes, getPointerTy()));
441 // Arguments go on the stack in reverse order, as specified by the ABI.
442 unsigned ArgOffset = 0;
443 SDOperand StackPtr = DAG.getRegister(X86::ESP, MVT::i32);
444 std::vector<SDOperand> Stores;
446 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
447 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
448 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
450 switch (getValueType(Args[i].second)) {
451 default: assert(0 && "Unexpected ValueType for argument!");
455 // Promote the integer to 32 bits. If the input type is signed use a
456 // sign extend, otherwise use a zero extend.
457 if (Args[i].second->isSigned())
458 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
460 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
465 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
466 Args[i].first, PtrOff,
467 DAG.getSrcValue(NULL)));
472 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
473 Args[i].first, PtrOff,
474 DAG.getSrcValue(NULL)));
479 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
482 std::vector<MVT::ValueType> RetVals;
483 MVT::ValueType RetTyVT = getValueType(RetTy);
484 RetVals.push_back(MVT::Other);
486 // The result values produced have to be legal. Promote the result.
488 case MVT::isVoid: break;
490 RetVals.push_back(RetTyVT);
495 RetVals.push_back(MVT::i32);
499 RetVals.push_back(MVT::f32);
501 RetVals.push_back(MVT::f64);
504 RetVals.push_back(MVT::i32);
505 RetVals.push_back(MVT::i32);
510 std::vector<MVT::ValueType> NodeTys;
511 NodeTys.push_back(MVT::Other); // Returns a chain
512 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
513 std::vector<SDOperand> Ops;
514 Ops.push_back(Chain);
515 Ops.push_back(Callee);
517 // FIXME: Do not generate X86ISD::TAILCALL for now.
518 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops);
519 SDOperand InFlag = Chain.getValue(1);
522 if (RetTyVT != MVT::isVoid) {
524 default: assert(0 && "Unknown value type to return!");
527 RetVal = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag);
528 Chain = RetVal.getValue(1);
531 RetVal = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag);
532 Chain = RetVal.getValue(1);
535 RetVal = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
536 Chain = RetVal.getValue(1);
539 SDOperand Lo = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
540 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), X86::EDX, MVT::i32,
542 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
543 Chain = Hi.getValue(1);
548 std::vector<MVT::ValueType> Tys;
549 Tys.push_back(MVT::f64);
550 Tys.push_back(MVT::Other);
551 std::vector<SDOperand> Ops;
552 Ops.push_back(Chain);
553 Ops.push_back(InFlag);
554 RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops);
555 Chain = RetVal.getValue(1);
557 unsigned Size = MVT::getSizeInBits(MVT::f64)/8;
558 MachineFunction &MF = DAG.getMachineFunction();
559 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
560 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
562 Tys.push_back(MVT::Other);
564 Ops.push_back(Chain);
565 Ops.push_back(RetVal);
566 Ops.push_back(StackSlot);
567 Ops.push_back(DAG.getValueType(RetTyVT));
568 Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
569 RetVal = DAG.getLoad(RetTyVT, Chain, StackSlot,
570 DAG.getSrcValue(NULL));
571 Chain = RetVal.getValue(1);
572 } else if (RetTyVT == MVT::f32)
573 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
579 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
580 DAG.getConstant(NumBytes, getPointerTy()),
581 DAG.getConstant(0, getPointerTy()));
582 return std::make_pair(RetVal, Chain);
584 std::vector<SDOperand> Ops;
585 Ops.push_back(Chain);
586 Ops.push_back(Callee);
587 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
588 Ops.push_back(DAG.getConstant(0, getPointerTy()));
590 SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
595 case MVT::isVoid: break;
597 ResultVal = TheCall.getValue(1);
602 ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1));
605 // FIXME: we would really like to remember that this FP_ROUND operation is
606 // okay to eliminate if we allow excess FP precision.
607 ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1));
610 ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1),
611 TheCall.getValue(2));
615 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall);
616 return std::make_pair(ResultVal, Chain);
621 X86TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
622 Value *VAListV, SelectionDAG &DAG) {
623 // vastart just stores the address of the VarArgsFrameIndex slot.
624 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
625 return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
626 DAG.getSrcValue(VAListV));
630 std::pair<SDOperand,SDOperand>
631 X86TargetLowering::LowerVAArg(SDOperand Chain, SDOperand VAListP,
632 Value *VAListV, const Type *ArgTy,
634 MVT::ValueType ArgVT = getValueType(ArgTy);
635 SDOperand Val = DAG.getLoad(MVT::i32, Chain,
636 VAListP, DAG.getSrcValue(VAListV));
637 SDOperand Result = DAG.getLoad(ArgVT, Chain, Val,
638 DAG.getSrcValue(NULL));
640 if (ArgVT == MVT::i32)
643 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
644 "Other types should have been promoted for varargs!");
647 Val = DAG.getNode(ISD::ADD, Val.getValueType(), Val,
648 DAG.getConstant(Amt, Val.getValueType()));
649 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
650 Val, VAListP, DAG.getSrcValue(VAListV));
651 return std::make_pair(Result, Chain);
654 //===----------------------------------------------------------------------===//
655 // Fast Calling Convention implementation
656 //===----------------------------------------------------------------------===//
658 // The X86 'fast' calling convention passes up to two integer arguments in
659 // registers (an appropriate portion of EAX/EDX), passes arguments in C order,
660 // and requires that the callee pop its arguments off the stack (allowing proper
661 // tail calls), and has the same return value conventions as C calling convs.
663 // This calling convention always arranges for the callee pop value to be 8n+4
664 // bytes, which is needed for tail recursion elimination and stack alignment
667 // Note that this can be enhanced in the future to pass fp vals in registers
668 // (when we have a global fp allocator) and do other tricks.
671 /// AddLiveIn - This helper function adds the specified physical register to the
672 /// MachineFunction as a live in value. It also creates a corresponding virtual
674 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
675 TargetRegisterClass *RC) {
676 assert(RC->contains(PReg) && "Not the correct regclass!");
677 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
678 MF.addLiveIn(PReg, VReg);
683 std::vector<SDOperand>
684 X86TargetLowering::LowerFastCCArguments(Function &F, SelectionDAG &DAG) {
685 std::vector<SDOperand> ArgValues;
687 MachineFunction &MF = DAG.getMachineFunction();
688 MachineFrameInfo *MFI = MF.getFrameInfo();
690 // Add DAG nodes to load the arguments... On entry to a function the stack
691 // frame looks like this:
693 // [ESP] -- return address
694 // [ESP + 4] -- first nonreg argument (leftmost lexically)
695 // [ESP + 8] -- second nonreg argument, if first argument is 4 bytes in size
697 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
699 // Keep track of the number of integer regs passed so far. This can be either
700 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
702 unsigned NumIntRegs = 0;
704 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
705 MVT::ValueType ObjectVT = getValueType(I->getType());
706 unsigned ArgIncrement = 4;
707 unsigned ObjSize = 0;
711 default: assert(0 && "Unhandled argument type!");
714 if (NumIntRegs < 2) {
715 if (!I->use_empty()) {
716 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::AL,
717 X86::R8RegisterClass);
718 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i8);
719 DAG.setRoot(ArgValue.getValue(1));
720 if (ObjectVT == MVT::i1)
721 // FIXME: Should insert a assertzext here.
722 ArgValue = DAG.getNode(ISD::TRUNCATE, MVT::i1, ArgValue);
731 if (NumIntRegs < 2) {
732 if (!I->use_empty()) {
733 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::AX,
734 X86::R16RegisterClass);
735 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i16);
736 DAG.setRoot(ArgValue.getValue(1));
744 if (NumIntRegs < 2) {
745 if (!I->use_empty()) {
746 unsigned VReg = AddLiveIn(MF,NumIntRegs ? X86::EDX : X86::EAX,
747 X86::R32RegisterClass);
748 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
749 DAG.setRoot(ArgValue.getValue(1));
757 if (NumIntRegs == 0) {
758 if (!I->use_empty()) {
759 unsigned BotReg = AddLiveIn(MF, X86::EAX, X86::R32RegisterClass);
760 unsigned TopReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
762 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
763 SDOperand Hi = DAG.getCopyFromReg(Low.getValue(1), TopReg, MVT::i32);
764 DAG.setRoot(Hi.getValue(1));
766 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
770 } else if (NumIntRegs == 1) {
771 if (!I->use_empty()) {
772 unsigned BotReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
773 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
774 DAG.setRoot(Low.getValue(1));
776 // Load the high part from memory.
777 // Create the frame index object for this incoming parameter...
778 int FI = MFI->CreateFixedObject(4, ArgOffset);
779 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
780 SDOperand Hi = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
781 DAG.getSrcValue(NULL));
782 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
788 ObjSize = ArgIncrement = 8;
790 case MVT::f32: ObjSize = 4; break;
791 case MVT::f64: ObjSize = ArgIncrement = 8; break;
794 // Don't codegen dead arguments. FIXME: remove this check when we can nuke
796 if (ObjSize && !I->use_empty()) {
797 // Create the frame index object for this incoming parameter...
798 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
800 // Create the SelectionDAG nodes corresponding to a load from this
802 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
804 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
805 DAG.getSrcValue(NULL));
806 } else if (ArgValue.Val == 0) {
807 if (MVT::isInteger(ObjectVT))
808 ArgValue = DAG.getConstant(0, ObjectVT);
810 ArgValue = DAG.getConstantFP(0, ObjectVT);
812 ArgValues.push_back(ArgValue);
815 ArgOffset += ArgIncrement; // Move on to the next argument.
818 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
819 // arguments and the arguments after the retaddr has been pushed are aligned.
820 if ((ArgOffset & 7) == 0)
823 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
824 ReturnAddrIndex = 0; // No return address slot generated yet.
825 BytesToPopOnReturn = ArgOffset; // Callee pops all stack arguments.
826 BytesCallerReserves = 0;
828 // Finally, inform the code generator which regs we return values in.
829 switch (getValueType(F.getReturnType())) {
830 default: assert(0 && "Unknown type!");
831 case MVT::isVoid: break;
836 MF.addLiveOut(X86::EAX);
839 MF.addLiveOut(X86::EAX);
840 MF.addLiveOut(X86::EDX);
844 MF.addLiveOut(X86::ST0);
850 std::pair<SDOperand, SDOperand>
851 X86TargetLowering::LowerFastCCCallTo(SDOperand Chain, const Type *RetTy,
852 bool isTailCall, SDOperand Callee,
853 ArgListTy &Args, SelectionDAG &DAG) {
854 // Count how many bytes are to be pushed on the stack.
855 unsigned NumBytes = 0;
857 // Keep track of the number of integer regs passed so far. This can be either
858 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
860 unsigned NumIntRegs = 0;
862 for (unsigned i = 0, e = Args.size(); i != e; ++i)
863 switch (getValueType(Args[i].second)) {
864 default: assert(0 && "Unknown value type!");
869 if (NumIntRegs < 2) {
878 if (NumIntRegs == 0) {
881 } else if (NumIntRegs == 1) {
893 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
894 // arguments and the arguments after the retaddr has been pushed are aligned.
895 if ((NumBytes & 7) == 0)
898 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
899 DAG.getConstant(NumBytes, getPointerTy()));
901 // Arguments go on the stack in reverse order, as specified by the ABI.
902 unsigned ArgOffset = 0;
903 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
906 std::vector<SDOperand> Stores;
907 std::vector<SDOperand> RegValuesToPass;
908 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
909 switch (getValueType(Args[i].second)) {
910 default: assert(0 && "Unexpected ValueType for argument!");
912 Args[i].first = DAG.getNode(ISD::ANY_EXTEND, MVT::i8, Args[i].first);
917 if (NumIntRegs < 2) {
918 RegValuesToPass.push_back(Args[i].first);
924 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
925 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
926 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
927 Args[i].first, PtrOff,
928 DAG.getSrcValue(NULL)));
933 if (NumIntRegs < 2) { // Can pass part of it in regs?
934 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
935 Args[i].first, DAG.getConstant(1, MVT::i32));
936 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
937 Args[i].first, DAG.getConstant(0, MVT::i32));
938 RegValuesToPass.push_back(Lo);
940 if (NumIntRegs < 2) { // Pass both parts in regs?
941 RegValuesToPass.push_back(Hi);
944 // Pass the high part in memory.
945 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
946 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
947 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
948 Hi, PtrOff, DAG.getSrcValue(NULL)));
955 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
956 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
957 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
958 Args[i].first, PtrOff,
959 DAG.getSrcValue(NULL)));
965 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
967 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
968 // arguments and the arguments after the retaddr has been pushed are aligned.
969 if ((ArgOffset & 7) == 0)
972 std::vector<MVT::ValueType> RetVals;
973 MVT::ValueType RetTyVT = getValueType(RetTy);
975 RetVals.push_back(MVT::Other);
977 // The result values produced have to be legal. Promote the result.
979 case MVT::isVoid: break;
981 RetVals.push_back(RetTyVT);
986 RetVals.push_back(MVT::i32);
990 RetVals.push_back(MVT::f32);
992 RetVals.push_back(MVT::f64);
995 RetVals.push_back(MVT::i32);
996 RetVals.push_back(MVT::i32);
1001 // Build a sequence of copy-to-reg nodes chained together with token chain
1002 // and flag operands which copy the outgoing args into registers.
1004 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
1006 SDOperand RegToPass = RegValuesToPass[i];
1007 switch (RegToPass.getValueType()) {
1008 default: assert(0 && "Bad thing to pass in regs");
1010 CCReg = (i == 0) ? X86::AL : X86::DL;
1013 CCReg = (i == 0) ? X86::AX : X86::DX;
1016 CCReg = (i == 0) ? X86::EAX : X86::EDX;
1020 Chain = DAG.getCopyToReg(Chain, CCReg, RegToPass, InFlag);
1021 InFlag = Chain.getValue(1);
1024 std::vector<MVT::ValueType> NodeTys;
1025 NodeTys.push_back(MVT::Other); // Returns a chain
1026 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
1027 std::vector<SDOperand> Ops;
1028 Ops.push_back(Chain);
1029 Ops.push_back(Callee);
1031 Ops.push_back(InFlag);
1033 // FIXME: Do not generate X86ISD::TAILCALL for now.
1034 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops);
1035 InFlag = Chain.getValue(1);
1038 if (RetTyVT != MVT::isVoid) {
1040 default: assert(0 && "Unknown value type to return!");
1043 RetVal = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag);
1044 Chain = RetVal.getValue(1);
1047 RetVal = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag);
1048 Chain = RetVal.getValue(1);
1051 RetVal = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
1052 Chain = RetVal.getValue(1);
1055 SDOperand Lo = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
1056 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), X86::EDX, MVT::i32,
1058 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
1059 Chain = Hi.getValue(1);
1064 std::vector<MVT::ValueType> Tys;
1065 Tys.push_back(MVT::f64);
1066 Tys.push_back(MVT::Other);
1067 std::vector<SDOperand> Ops;
1068 Ops.push_back(Chain);
1069 Ops.push_back(InFlag);
1070 RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops);
1071 Chain = RetVal.getValue(1);
1073 unsigned Size = MVT::getSizeInBits(MVT::f64)/8;
1074 MachineFunction &MF = DAG.getMachineFunction();
1075 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
1076 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1078 Tys.push_back(MVT::Other);
1080 Ops.push_back(Chain);
1081 Ops.push_back(RetVal);
1082 Ops.push_back(StackSlot);
1083 Ops.push_back(DAG.getValueType(RetTyVT));
1084 Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
1085 RetVal = DAG.getLoad(RetTyVT, Chain, StackSlot,
1086 DAG.getSrcValue(NULL));
1087 Chain = RetVal.getValue(1);
1088 } else if (RetTyVT == MVT::f32)
1089 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
1095 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
1096 DAG.getConstant(ArgOffset, getPointerTy()),
1097 DAG.getConstant(ArgOffset, getPointerTy()));
1098 return std::make_pair(RetVal, Chain);
1100 std::vector<SDOperand> Ops;
1101 Ops.push_back(Chain);
1102 Ops.push_back(Callee);
1103 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
1104 // Callee pops all arg values on the stack.
1105 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
1107 // Pass register arguments as needed.
1108 Ops.insert(Ops.end(), RegValuesToPass.begin(), RegValuesToPass.end());
1110 SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
1112 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall);
1114 SDOperand ResultVal;
1116 case MVT::isVoid: break;
1118 ResultVal = TheCall.getValue(1);
1123 ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1));
1126 // FIXME: we would really like to remember that this FP_ROUND operation is
1127 // okay to eliminate if we allow excess FP precision.
1128 ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1));
1131 ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1),
1132 TheCall.getValue(2));
1136 return std::make_pair(ResultVal, Chain);
1140 SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1141 if (ReturnAddrIndex == 0) {
1142 // Set up a frame object for the return address.
1143 MachineFunction &MF = DAG.getMachineFunction();
1144 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
1147 return DAG.getFrameIndex(ReturnAddrIndex, MVT::i32);
1152 std::pair<SDOperand, SDOperand> X86TargetLowering::
1153 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
1154 SelectionDAG &DAG) {
1156 if (Depth) // Depths > 0 not supported yet!
1157 Result = DAG.getConstant(0, getPointerTy());
1159 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
1160 if (!isFrameAddress)
1161 // Just load the return address
1162 Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(), RetAddrFI,
1163 DAG.getSrcValue(NULL));
1165 Result = DAG.getNode(ISD::SUB, MVT::i32, RetAddrFI,
1166 DAG.getConstant(4, MVT::i32));
1168 return std::make_pair(Result, Chain);
1171 /// getCondBrOpcodeForX86CC - Returns the X86 conditional branch opcode
1172 /// which corresponds to the condition code.
1173 static unsigned getCondBrOpcodeForX86CC(unsigned X86CC) {
1175 default: assert(0 && "Unknown X86 conditional code!");
1176 case X86ISD::COND_A: return X86::JA;
1177 case X86ISD::COND_AE: return X86::JAE;
1178 case X86ISD::COND_B: return X86::JB;
1179 case X86ISD::COND_BE: return X86::JBE;
1180 case X86ISD::COND_E: return X86::JE;
1181 case X86ISD::COND_G: return X86::JG;
1182 case X86ISD::COND_GE: return X86::JGE;
1183 case X86ISD::COND_L: return X86::JL;
1184 case X86ISD::COND_LE: return X86::JLE;
1185 case X86ISD::COND_NE: return X86::JNE;
1186 case X86ISD::COND_NO: return X86::JNO;
1187 case X86ISD::COND_NP: return X86::JNP;
1188 case X86ISD::COND_NS: return X86::JNS;
1189 case X86ISD::COND_O: return X86::JO;
1190 case X86ISD::COND_P: return X86::JP;
1191 case X86ISD::COND_S: return X86::JS;
1195 /// getX86CC - do a one to one translation of a ISD::CondCode to the X86
1196 /// specific condition code. It returns a X86ISD::COND_INVALID if it cannot
1197 /// do a direct translation.
1198 static unsigned getX86CC(SDOperand CC, bool isFP) {
1199 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
1200 unsigned X86CC = X86ISD::COND_INVALID;
1202 switch (SetCCOpcode) {
1204 case ISD::SETEQ: X86CC = X86ISD::COND_E; break;
1205 case ISD::SETGT: X86CC = X86ISD::COND_G; break;
1206 case ISD::SETGE: X86CC = X86ISD::COND_GE; break;
1207 case ISD::SETLT: X86CC = X86ISD::COND_L; break;
1208 case ISD::SETLE: X86CC = X86ISD::COND_LE; break;
1209 case ISD::SETNE: X86CC = X86ISD::COND_NE; break;
1210 case ISD::SETULT: X86CC = X86ISD::COND_B; break;
1211 case ISD::SETUGT: X86CC = X86ISD::COND_A; break;
1212 case ISD::SETULE: X86CC = X86ISD::COND_BE; break;
1213 case ISD::SETUGE: X86CC = X86ISD::COND_AE; break;
1216 // On a floating point condition, the flags are set as follows:
1218 // 0 | 0 | 0 | X > Y
1219 // 0 | 0 | 1 | X < Y
1220 // 1 | 0 | 0 | X == Y
1221 // 1 | 1 | 1 | unordered
1222 switch (SetCCOpcode) {
1225 case ISD::SETEQ: X86CC = X86ISD::COND_E; break;
1227 case ISD::SETGT: X86CC = X86ISD::COND_A; break;
1229 case ISD::SETGE: X86CC = X86ISD::COND_AE; break;
1231 case ISD::SETLT: X86CC = X86ISD::COND_B; break;
1233 case ISD::SETLE: X86CC = X86ISD::COND_BE; break;
1235 case ISD::SETNE: X86CC = X86ISD::COND_NE; break;
1236 case ISD::SETUO: X86CC = X86ISD::COND_P; break;
1237 case ISD::SETO: X86CC = X86ISD::COND_NP; break;
1243 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
1244 /// code. Current x86 isa includes the following FP cmov instructions:
1245 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
1246 static bool hasFPCMov(unsigned X86CC) {
1250 case X86ISD::COND_B:
1251 case X86ISD::COND_BE:
1252 case X86ISD::COND_E:
1253 case X86ISD::COND_P:
1254 case X86ISD::COND_A:
1255 case X86ISD::COND_AE:
1256 case X86ISD::COND_NE:
1257 case X86ISD::COND_NP:
1263 X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
1264 MachineBasicBlock *BB) {
1265 switch (MI->getOpcode()) {
1266 default: assert(false && "Unexpected instr type to insert");
1267 case X86::CMOV_FR32:
1268 case X86::CMOV_FR64: {
1269 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
1270 // control-flow pattern. The incoming instruction knows the destination vreg
1271 // to set, the condition code register to branch on, the true/false values to
1272 // select between, and a branch opcode to use.
1273 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1274 ilist<MachineBasicBlock>::iterator It = BB;
1280 // cmpTY ccX, r1, r2
1282 // fallthrough --> copy0MBB
1283 MachineBasicBlock *thisMBB = BB;
1284 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
1285 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
1286 unsigned Opc = getCondBrOpcodeForX86CC(MI->getOperand(3).getImmedValue());
1287 BuildMI(BB, Opc, 1).addMBB(sinkMBB);
1288 MachineFunction *F = BB->getParent();
1289 F->getBasicBlockList().insert(It, copy0MBB);
1290 F->getBasicBlockList().insert(It, sinkMBB);
1291 // Update machine-CFG edges
1292 BB->addSuccessor(copy0MBB);
1293 BB->addSuccessor(sinkMBB);
1296 // %FalseValue = ...
1297 // # fallthrough to sinkMBB
1300 // Update machine-CFG edges
1301 BB->addSuccessor(sinkMBB);
1304 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1307 BuildMI(BB, X86::PHI, 4, MI->getOperand(0).getReg())
1308 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
1309 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
1311 delete MI; // The pseudo instruction is gone now.
1315 case X86::FP_TO_INT16_IN_MEM:
1316 case X86::FP_TO_INT32_IN_MEM:
1317 case X86::FP_TO_INT64_IN_MEM: {
1318 // Change the floating point control register to use "round towards zero"
1319 // mode when truncating to an integer value.
1320 MachineFunction *F = BB->getParent();
1321 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
1322 addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
1324 // Load the old value of the high byte of the control word...
1326 F->getSSARegMap()->createVirtualRegister(X86::R16RegisterClass);
1327 addFrameReference(BuildMI(BB, X86::MOV16rm, 4, OldCW), CWFrameIdx);
1329 // Set the high part to be round to zero...
1330 addFrameReference(BuildMI(BB, X86::MOV16mi, 5), CWFrameIdx).addImm(0xC7F);
1332 // Reload the modified control word now...
1333 addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
1335 // Restore the memory image of control word to original value
1336 addFrameReference(BuildMI(BB, X86::MOV16mr, 5), CWFrameIdx).addReg(OldCW);
1338 // Get the X86 opcode to use.
1340 switch (MI->getOpcode()) {
1341 case X86::FP_TO_INT16_IN_MEM: Opc = X86::FpIST16m; break;
1342 case X86::FP_TO_INT32_IN_MEM: Opc = X86::FpIST32m; break;
1343 case X86::FP_TO_INT64_IN_MEM: Opc = X86::FpIST64m; break;
1347 MachineOperand &Op = MI->getOperand(0);
1348 if (Op.isRegister()) {
1349 AM.BaseType = X86AddressMode::RegBase;
1350 AM.Base.Reg = Op.getReg();
1352 AM.BaseType = X86AddressMode::FrameIndexBase;
1353 AM.Base.FrameIndex = Op.getFrameIndex();
1355 Op = MI->getOperand(1);
1356 if (Op.isImmediate())
1357 AM.Scale = Op.getImmedValue();
1358 Op = MI->getOperand(2);
1359 if (Op.isImmediate())
1360 AM.IndexReg = Op.getImmedValue();
1361 Op = MI->getOperand(3);
1362 if (Op.isGlobalAddress()) {
1363 AM.GV = Op.getGlobal();
1365 AM.Disp = Op.getImmedValue();
1367 addFullAddress(BuildMI(BB, Opc, 5), AM).addReg(MI->getOperand(4).getReg());
1369 // Reload the original control word now.
1370 addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
1372 delete MI; // The pseudo instruction is gone now.
1379 //===----------------------------------------------------------------------===//
1380 // X86 Custom Lowering Hooks
1381 //===----------------------------------------------------------------------===//
1383 /// LowerOperation - Provide custom lowering hooks for some operations.
1385 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
1386 switch (Op.getOpcode()) {
1387 default: assert(0 && "Should not custom lower this!");
1388 case ISD::ADD_PARTS:
1389 case ISD::SUB_PARTS: {
1390 assert(Op.getNumOperands() == 4 && Op.getValueType() == MVT::i32 &&
1391 "Not an i64 add/sub!");
1392 bool isAdd = Op.getOpcode() == ISD::ADD_PARTS;
1393 std::vector<MVT::ValueType> Tys;
1394 Tys.push_back(MVT::i32);
1395 Tys.push_back(MVT::Flag);
1396 std::vector<SDOperand> Ops;
1397 Ops.push_back(Op.getOperand(0));
1398 Ops.push_back(Op.getOperand(2));
1399 SDOperand Lo = DAG.getNode(isAdd ? X86ISD::ADD_FLAG : X86ISD::SUB_FLAG,
1401 SDOperand Hi = DAG.getNode(isAdd ? X86ISD::ADC : X86ISD::SBB, MVT::i32,
1402 Op.getOperand(1), Op.getOperand(3),
1405 Tys.push_back(MVT::i32);
1406 Tys.push_back(MVT::i32);
1410 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
1412 case ISD::SHL_PARTS:
1413 case ISD::SRA_PARTS:
1414 case ISD::SRL_PARTS: {
1415 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
1416 "Not an i64 shift!");
1417 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
1418 SDOperand ShOpLo = Op.getOperand(0);
1419 SDOperand ShOpHi = Op.getOperand(1);
1420 SDOperand ShAmt = Op.getOperand(2);
1421 SDOperand Tmp1 = isSRA ? DAG.getNode(ISD::SRA, MVT::i32, ShOpHi,
1422 DAG.getConstant(31, MVT::i32))
1423 : DAG.getConstant(0, MVT::i32);
1425 SDOperand Tmp2, Tmp3;
1426 if (Op.getOpcode() == ISD::SHL_PARTS) {
1427 Tmp2 = DAG.getNode(X86ISD::SHLD, MVT::i32, ShOpHi, ShOpLo, ShAmt);
1428 Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt);
1430 Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt);
1431 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SHL, MVT::i32, ShOpHi, ShAmt);
1434 SDOperand InFlag = DAG.getNode(X86ISD::TEST, MVT::Flag,
1435 ShAmt, DAG.getConstant(32, MVT::i8));
1438 SDOperand CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
1440 std::vector<MVT::ValueType> Tys;
1441 Tys.push_back(MVT::i32);
1442 Tys.push_back(MVT::Flag);
1443 std::vector<SDOperand> Ops;
1444 if (Op.getOpcode() == ISD::SHL_PARTS) {
1445 Ops.push_back(Tmp2);
1446 Ops.push_back(Tmp3);
1448 Ops.push_back(InFlag);
1449 Hi = DAG.getNode(X86ISD::CMOV, Tys, Ops);
1450 InFlag = Hi.getValue(1);
1453 Ops.push_back(Tmp3);
1454 Ops.push_back(Tmp1);
1456 Ops.push_back(InFlag);
1457 Lo = DAG.getNode(X86ISD::CMOV, Tys, Ops);
1459 Ops.push_back(Tmp2);
1460 Ops.push_back(Tmp3);
1462 Ops.push_back(InFlag);
1463 Lo = DAG.getNode(X86ISD::CMOV, Tys, Ops);
1464 InFlag = Lo.getValue(1);
1467 Ops.push_back(Tmp3);
1468 Ops.push_back(Tmp1);
1470 Ops.push_back(InFlag);
1471 Hi = DAG.getNode(X86ISD::CMOV, Tys, Ops);
1475 Tys.push_back(MVT::i32);
1476 Tys.push_back(MVT::i32);
1480 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
1482 case ISD::SINT_TO_FP: {
1483 assert(Op.getValueType() == MVT::f64 &&
1484 Op.getOperand(0).getValueType() <= MVT::i64 &&
1485 Op.getOperand(0).getValueType() >= MVT::i16 &&
1486 "Unknown SINT_TO_FP to lower!");
1489 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
1490 unsigned Size = MVT::getSizeInBits(SrcVT)/8;
1491 MachineFunction &MF = DAG.getMachineFunction();
1492 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
1493 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1494 SDOperand Chain = DAG.getNode(ISD::STORE, MVT::Other,
1495 DAG.getEntryNode(), Op.getOperand(0),
1496 StackSlot, DAG.getSrcValue(NULL));
1499 std::vector<MVT::ValueType> Tys;
1500 Tys.push_back(MVT::f64);
1501 Tys.push_back(MVT::Flag);
1502 std::vector<SDOperand> Ops;
1503 Ops.push_back(Chain);
1504 Ops.push_back(StackSlot);
1505 Ops.push_back(DAG.getValueType(SrcVT));
1506 Result = DAG.getNode(X86ISD::FILD, Tys, Ops);
1509 case ISD::FP_TO_SINT: {
1510 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
1511 Op.getOperand(0).getValueType() == MVT::f64 &&
1512 "Unknown FP_TO_SINT to lower!");
1513 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
1515 MachineFunction &MF = DAG.getMachineFunction();
1516 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
1517 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
1518 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1521 switch (Op.getValueType()) {
1522 default: assert(0 && "Invalid FP_TO_SINT to lower!");
1523 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
1524 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
1525 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
1528 // Build the FP_TO_INT*_IN_MEM
1529 std::vector<SDOperand> Ops;
1530 Ops.push_back(DAG.getEntryNode());
1531 Ops.push_back(Op.getOperand(0));
1532 Ops.push_back(StackSlot);
1533 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops);
1536 return DAG.getLoad(Op.getValueType(), FIST, StackSlot,
1537 DAG.getSrcValue(NULL));
1539 case ISD::READCYCLECOUNTER: {
1540 std::vector<MVT::ValueType> Tys;
1541 Tys.push_back(MVT::Other);
1542 Tys.push_back(MVT::Flag);
1543 std::vector<SDOperand> Ops;
1544 Ops.push_back(Op.getOperand(0));
1545 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, Ops);
1547 Ops.push_back(DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1)));
1548 Ops.push_back(DAG.getCopyFromReg(Ops[0].getValue(1), X86::EDX,
1549 MVT::i32, Ops[0].getValue(2)));
1550 Ops.push_back(Ops[1].getValue(1));
1551 Tys[0] = Tys[1] = MVT::i32;
1552 Tys.push_back(MVT::Other);
1553 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
1556 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
1557 SDOperand CC = Op.getOperand(2);
1558 SDOperand Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1559 Op.getOperand(0), Op.getOperand(1));
1560 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
1561 bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType());
1562 unsigned X86CC = getX86CC(CC, isFP);
1563 if (X86CC != X86ISD::COND_INVALID) {
1564 return DAG.getNode(X86ISD::SETCC, MVT::i8,
1565 DAG.getConstant(X86CC, MVT::i8), Cond);
1567 assert(isFP && "Illegal integer SetCC!");
1569 std::vector<MVT::ValueType> Tys;
1570 std::vector<SDOperand> Ops;
1571 switch (SetCCOpcode) {
1572 default: assert(false && "Illegal floating point SetCC!");
1573 case ISD::SETOEQ: { // !PF & ZF
1574 Tys.push_back(MVT::i8);
1575 Tys.push_back(MVT::Flag);
1576 Ops.push_back(DAG.getConstant(X86ISD::COND_NP, MVT::i8));
1577 Ops.push_back(Cond);
1578 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1579 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1580 DAG.getConstant(X86ISD::COND_E, MVT::i8),
1582 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
1584 case ISD::SETOLT: { // !PF & CF
1585 Tys.push_back(MVT::i8);
1586 Tys.push_back(MVT::Flag);
1587 Ops.push_back(DAG.getConstant(X86ISD::COND_NP, MVT::i8));
1588 Ops.push_back(Cond);
1589 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1590 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1591 DAG.getConstant(X86ISD::COND_B, MVT::i8),
1593 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
1595 case ISD::SETOLE: { // !PF & (CF || ZF)
1596 Tys.push_back(MVT::i8);
1597 Tys.push_back(MVT::Flag);
1598 Ops.push_back(DAG.getConstant(X86ISD::COND_NP, MVT::i8));
1599 Ops.push_back(Cond);
1600 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1601 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1602 DAG.getConstant(X86ISD::COND_BE, MVT::i8),
1604 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
1606 case ISD::SETUGT: { // PF | (!ZF & !CF)
1607 Tys.push_back(MVT::i8);
1608 Tys.push_back(MVT::Flag);
1609 Ops.push_back(DAG.getConstant(X86ISD::COND_P, MVT::i8));
1610 Ops.push_back(Cond);
1611 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1612 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1613 DAG.getConstant(X86ISD::COND_A, MVT::i8),
1615 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
1617 case ISD::SETUGE: { // PF | !CF
1618 Tys.push_back(MVT::i8);
1619 Tys.push_back(MVT::Flag);
1620 Ops.push_back(DAG.getConstant(X86ISD::COND_P, MVT::i8));
1621 Ops.push_back(Cond);
1622 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1623 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1624 DAG.getConstant(X86ISD::COND_AE, MVT::i8),
1626 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
1628 case ISD::SETUNE: { // PF | !ZF
1629 Tys.push_back(MVT::i8);
1630 Tys.push_back(MVT::Flag);
1631 Ops.push_back(DAG.getConstant(X86ISD::COND_P, MVT::i8));
1632 Ops.push_back(Cond);
1633 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1634 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1635 DAG.getConstant(X86ISD::COND_NE, MVT::i8),
1637 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
1643 MVT::ValueType VT = Op.getValueType();
1644 bool isFP = MVT::isFloatingPoint(VT);
1645 bool isFPStack = isFP && (X86Vector < SSE2);
1646 bool isFPSSE = isFP && (X86Vector >= SSE2);
1647 bool addTest = false;
1648 SDOperand Op0 = Op.getOperand(0);
1650 if (Op0.getOpcode() == X86ISD::SETCC) {
1651 // If condition flag is set by a X86ISD::CMP, then make a copy of it
1652 // (since flag operand cannot be shared). If the X86ISD::SETCC does not
1653 // have another use it will be eliminated.
1654 // If the X86ISD::SETCC has more than one use, then it's probably better
1655 // to use a test instead of duplicating the X86ISD::CMP (for register
1656 // pressure reason).
1657 if (Op0.hasOneUse() && Op0.getOperand(1).getOpcode() == X86ISD::CMP) {
1658 CC = Op0.getOperand(0);
1659 Cond = Op0.getOperand(1);
1661 isFPStack && !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
1664 } else if (Op0.getOpcode() == ISD::SETCC) {
1665 CC = Op0.getOperand(2);
1666 bool isFP = MVT::isFloatingPoint(Op0.getOperand(1).getValueType());
1667 unsigned X86CC = getX86CC(CC, isFP);
1668 CC = DAG.getConstant(X86CC, MVT::i8);
1669 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1670 Op0.getOperand(0), Op0.getOperand(1));
1676 CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
1677 Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Op0, Op0);
1680 std::vector<MVT::ValueType> Tys;
1681 Tys.push_back(Op.getValueType());
1682 Tys.push_back(MVT::Flag);
1683 std::vector<SDOperand> Ops;
1684 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
1685 // condition is true.
1686 Ops.push_back(Op.getOperand(2));
1687 Ops.push_back(Op.getOperand(1));
1689 Ops.push_back(Cond);
1690 return DAG.getNode(X86ISD::CMOV, Tys, Ops);
1693 bool addTest = false;
1694 SDOperand Cond = Op.getOperand(1);
1695 SDOperand Dest = Op.getOperand(2);
1697 if (Cond.getOpcode() == X86ISD::SETCC) {
1698 // If condition flag is set by a X86ISD::CMP, then make a copy of it
1699 // (since flag operand cannot be shared). If the X86ISD::SETCC does not
1700 // have another use it will be eliminated.
1701 // If the X86ISD::SETCC has more than one use, then it's probably better
1702 // to use a test instead of duplicating the X86ISD::CMP (for register
1703 // pressure reason).
1704 if (Cond.hasOneUse() && Cond.getOperand(1).getOpcode() == X86ISD::CMP) {
1705 CC = Cond.getOperand(0);
1706 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1707 Cond.getOperand(1).getOperand(0),
1708 Cond.getOperand(1).getOperand(1));
1711 } else if (Cond.getOpcode() == ISD::SETCC) {
1712 CC = Cond.getOperand(2);
1713 bool isFP = MVT::isFloatingPoint(Cond.getOperand(1).getValueType());
1714 unsigned X86CC = getX86CC(CC, isFP);
1715 CC = DAG.getConstant(X86CC, MVT::i8);
1716 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1717 Cond.getOperand(0), Cond.getOperand(1));
1722 CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
1723 Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Cond, Cond);
1725 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
1726 Op.getOperand(0), Op.getOperand(2), CC, Cond);
1729 // Can only be return void.
1730 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Op.getOperand(0),
1731 DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
1735 SDOperand Chain = Op.getOperand(0);
1737 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
1738 if (Align == 0) Align = 1;
1742 if (ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Op.getOperand(2))) {
1744 unsigned Val = ValC->getValue() & 255;
1746 // If the value is a constant, then we can potentially use larger sets.
1747 switch (Align & 3) {
1748 case 2: // WORD aligned
1750 if (ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3)))
1751 Count = DAG.getConstant(I->getValue() / 2, MVT::i32);
1753 Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3),
1754 DAG.getConstant(1, MVT::i8));
1755 Val = (Val << 8) | Val;
1758 case 0: // DWORD aligned
1760 if (ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3)))
1761 Count = DAG.getConstant(I->getValue() / 4, MVT::i32);
1763 Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3),
1764 DAG.getConstant(2, MVT::i8));
1765 Val = (Val << 8) | Val;
1766 Val = (Val << 16) | Val;
1769 default: // Byte aligned
1771 Count = Op.getOperand(3);
1776 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
1778 InFlag = Chain.getValue(1);
1781 Count = Op.getOperand(3);
1782 Chain = DAG.getCopyToReg(Chain, X86::AL, Op.getOperand(2), InFlag);
1783 InFlag = Chain.getValue(1);
1786 Chain = DAG.getCopyToReg(Chain, X86::ECX, Count, InFlag);
1787 InFlag = Chain.getValue(1);
1788 Chain = DAG.getCopyToReg(Chain, X86::EDI, Op.getOperand(1), InFlag);
1789 InFlag = Chain.getValue(1);
1791 return DAG.getNode(X86ISD::REP_STOS, MVT::Other, Chain,
1792 DAG.getValueType(AVT), InFlag);
1795 SDOperand Chain = Op.getOperand(0);
1797 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
1798 if (Align == 0) Align = 1;
1802 switch (Align & 3) {
1803 case 2: // WORD aligned
1805 if (ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3)))
1806 Count = DAG.getConstant(I->getValue() / 2, MVT::i32);
1808 Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3),
1809 DAG.getConstant(1, MVT::i8));
1811 case 0: // DWORD aligned
1813 if (ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3)))
1814 Count = DAG.getConstant(I->getValue() / 4, MVT::i32);
1816 Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3),
1817 DAG.getConstant(2, MVT::i8));
1819 default: // Byte aligned
1821 Count = Op.getOperand(3);
1826 Chain = DAG.getCopyToReg(Chain, X86::ECX, Count, InFlag);
1827 InFlag = Chain.getValue(1);
1828 Chain = DAG.getCopyToReg(Chain, X86::EDI, Op.getOperand(1), InFlag);
1829 InFlag = Chain.getValue(1);
1830 Chain = DAG.getCopyToReg(Chain, X86::ESI, Op.getOperand(2), InFlag);
1831 InFlag = Chain.getValue(1);
1833 return DAG.getNode(X86ISD::REP_MOVS, MVT::Other, Chain,
1834 DAG.getValueType(AVT), InFlag);
1836 case ISD::GlobalAddress: {
1838 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1839 // For Darwin, external and weak symbols are indirect, so we want to load
1840 // the value at address GV, not the value of GV itself. This means that
1841 // the GlobalAddress must be in the base or index register of the address,
1842 // not the GV offset field.
1843 if (getTargetMachine().
1844 getSubtarget<X86Subtarget>().getIndirectExternAndWeakGlobals() &&
1845 (GV->hasWeakLinkage() || GV->isExternal()))
1846 Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(),
1847 DAG.getTargetGlobalAddress(GV, getPointerTy()),
1848 DAG.getSrcValue(NULL));
1854 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
1856 default: return NULL;
1857 case X86ISD::ADD_FLAG: return "X86ISD::ADD_FLAG";
1858 case X86ISD::SUB_FLAG: return "X86ISD::SUB_FLAG";
1859 case X86ISD::ADC: return "X86ISD::ADC";
1860 case X86ISD::SBB: return "X86ISD::SBB";
1861 case X86ISD::SHLD: return "X86ISD::SHLD";
1862 case X86ISD::SHRD: return "X86ISD::SHRD";
1863 case X86ISD::FILD: return "X86ISD::FILD";
1864 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
1865 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
1866 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
1867 case X86ISD::FLD: return "X86ISD::FLD";
1868 case X86ISD::FST: return "X86ISD::FST";
1869 case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT";
1870 case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT";
1871 case X86ISD::CALL: return "X86ISD::CALL";
1872 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
1873 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
1874 case X86ISD::CMP: return "X86ISD::CMP";
1875 case X86ISD::TEST: return "X86ISD::TEST";
1876 case X86ISD::SETCC: return "X86ISD::SETCC";
1877 case X86ISD::CMOV: return "X86ISD::CMOV";
1878 case X86ISD::BRCOND: return "X86ISD::BRCOND";
1879 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
1880 case X86ISD::REP_STOS: return "X86ISD::RET_STOS";
1881 case X86ISD::REP_MOVS: return "X86ISD::RET_MOVS";
1885 bool X86TargetLowering::isMaskedValueZeroForTargetNode(const SDOperand &Op,
1886 uint64_t Mask) const {
1888 unsigned Opc = Op.getOpcode();
1892 assert(Opc >= ISD::BUILTIN_OP_END && "Expected a target specific node");
1894 case X86ISD::SETCC: return (Mask & 1) == 0;