1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/WinEHFuncInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 // Forward declarations.
71 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
74 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
75 const X86Subtarget &STI)
76 : TargetLowering(TM), Subtarget(&STI) {
77 X86ScalarSSEf64 = Subtarget->hasSSE2();
78 X86ScalarSSEf32 = Subtarget->hasSSE1();
79 TD = TM.getDataLayout();
81 // Set up the TargetLowering object.
82 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
84 // X86 is weird. It always uses i8 for shift amounts and setcc results.
85 setBooleanContents(ZeroOrOneBooleanContent);
86 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
87 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
89 // For 64-bit, since we have so many registers, use the ILP scheduler.
90 // For 32-bit, use the register pressure specific scheduling.
91 // For Atom, always use ILP scheduling.
92 if (Subtarget->isAtom())
93 setSchedulingPreference(Sched::ILP);
94 else if (Subtarget->is64Bit())
95 setSchedulingPreference(Sched::ILP);
97 setSchedulingPreference(Sched::RegPressure);
98 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
99 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
101 // Bypass expensive divides on Atom when compiling with O2.
102 if (TM.getOptLevel() >= CodeGenOpt::Default) {
103 if (Subtarget->hasSlowDivide32())
104 addBypassSlowDiv(32, 8);
105 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
106 addBypassSlowDiv(64, 16);
109 if (Subtarget->isTargetKnownWindowsMSVC()) {
110 // Setup Windows compiler runtime calls.
111 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
112 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
113 setLibcallName(RTLIB::SREM_I64, "_allrem");
114 setLibcallName(RTLIB::UREM_I64, "_aullrem");
115 setLibcallName(RTLIB::MUL_I64, "_allmul");
116 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
117 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
118 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
119 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
120 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
122 // The _ftol2 runtime function has an unusual calling conv, which
123 // is modeled by a special pseudo-instruction.
124 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
125 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
126 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
127 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
130 if (Subtarget->isTargetDarwin()) {
131 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
132 setUseUnderscoreSetJmp(false);
133 setUseUnderscoreLongJmp(false);
134 } else if (Subtarget->isTargetWindowsGNU()) {
135 // MS runtime is weird: it exports _setjmp, but longjmp!
136 setUseUnderscoreSetJmp(true);
137 setUseUnderscoreLongJmp(false);
139 setUseUnderscoreSetJmp(true);
140 setUseUnderscoreLongJmp(true);
143 // Set up the register classes.
144 addRegisterClass(MVT::i8, &X86::GR8RegClass);
145 addRegisterClass(MVT::i16, &X86::GR16RegClass);
146 addRegisterClass(MVT::i32, &X86::GR32RegClass);
147 if (Subtarget->is64Bit())
148 addRegisterClass(MVT::i64, &X86::GR64RegClass);
150 for (MVT VT : MVT::integer_valuetypes())
151 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
153 // We don't accept any truncstore of integer registers.
154 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
155 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
156 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
157 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
158 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
159 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
161 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
163 // SETOEQ and SETUNE require checking two conditions.
164 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
165 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
166 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
167 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
168 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
169 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
171 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
173 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
174 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
175 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
177 if (Subtarget->is64Bit()) {
178 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
179 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
180 } else if (!Subtarget->useSoftFloat()) {
181 // We have an algorithm for SSE2->double, and we turn this into a
182 // 64-bit FILD followed by conditional FADD for other targets.
183 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
184 // We have an algorithm for SSE2, and we turn this into a 64-bit
185 // FILD for other targets.
186 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
189 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
191 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
192 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
194 if (!Subtarget->useSoftFloat()) {
195 // SSE has no i16 to fp conversion, only i32
196 if (X86ScalarSSEf32) {
197 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
198 // f32 and f64 cases are Legal, f80 case is not
199 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
201 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
202 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
205 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
206 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
209 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
210 // are Legal, f80 is custom lowered.
211 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
212 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
214 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
216 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
217 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
219 if (X86ScalarSSEf32) {
220 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
221 // f32 and f64 cases are Legal, f80 case is not
222 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
224 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
225 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
228 // Handle FP_TO_UINT by promoting the destination to a larger signed
230 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
231 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
232 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
234 if (Subtarget->is64Bit()) {
235 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
236 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
237 } else if (!Subtarget->useSoftFloat()) {
238 // Since AVX is a superset of SSE3, only check for SSE here.
239 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
240 // Expand FP_TO_UINT into a select.
241 // FIXME: We would like to use a Custom expander here eventually to do
242 // the optimal thing for SSE vs. the default expansion in the legalizer.
243 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
245 // With SSE3 we can use fisttpll to convert to a signed i64; without
246 // SSE, we're stuck with a fistpll.
247 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
250 if (isTargetFTOL()) {
251 // Use the _ftol2 runtime function, which has a pseudo-instruction
252 // to handle its weird calling convention.
253 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
256 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
257 if (!X86ScalarSSEf64) {
258 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
259 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
260 if (Subtarget->is64Bit()) {
261 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
262 // Without SSE, i64->f64 goes through memory.
263 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
267 // Scalar integer divide and remainder are lowered to use operations that
268 // produce two results, to match the available instructions. This exposes
269 // the two-result form to trivial CSE, which is able to combine x/y and x%y
270 // into a single instruction.
272 // Scalar integer multiply-high is also lowered to use two-result
273 // operations, to match the available instructions. However, plain multiply
274 // (low) operations are left as Legal, as there are single-result
275 // instructions for this in x86. Using the two-result multiply instructions
276 // when both high and low results are needed must be arranged by dagcombine.
277 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
279 setOperationAction(ISD::MULHS, VT, Expand);
280 setOperationAction(ISD::MULHU, VT, Expand);
281 setOperationAction(ISD::SDIV, VT, Expand);
282 setOperationAction(ISD::UDIV, VT, Expand);
283 setOperationAction(ISD::SREM, VT, Expand);
284 setOperationAction(ISD::UREM, VT, Expand);
286 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
287 setOperationAction(ISD::ADDC, VT, Custom);
288 setOperationAction(ISD::ADDE, VT, Custom);
289 setOperationAction(ISD::SUBC, VT, Custom);
290 setOperationAction(ISD::SUBE, VT, Custom);
293 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
294 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
295 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
296 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
297 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
298 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
299 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
300 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
301 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
302 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
303 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
304 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
305 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
306 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
307 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
308 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
309 if (Subtarget->is64Bit())
310 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
311 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
312 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
313 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
314 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
315 setOperationAction(ISD::FREM , MVT::f32 , Expand);
316 setOperationAction(ISD::FREM , MVT::f64 , Expand);
317 setOperationAction(ISD::FREM , MVT::f80 , Expand);
318 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
320 // Promote the i8 variants and force them on up to i32 which has a shorter
322 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
323 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
324 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
325 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
326 if (Subtarget->hasBMI()) {
327 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
328 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
329 if (Subtarget->is64Bit())
330 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
332 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
333 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
334 if (Subtarget->is64Bit())
335 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
338 if (Subtarget->hasLZCNT()) {
339 // When promoting the i8 variants, force them to i32 for a shorter
341 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
342 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
343 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
344 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
345 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
346 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
347 if (Subtarget->is64Bit())
348 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
350 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
351 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
352 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
353 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
355 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
356 if (Subtarget->is64Bit()) {
357 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
358 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
362 // Special handling for half-precision floating point conversions.
363 // If we don't have F16C support, then lower half float conversions
364 // into library calls.
365 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
366 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
367 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
370 // There's never any support for operations beyond MVT::f32.
371 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
372 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
373 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
374 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
376 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
377 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
378 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
379 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
380 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
381 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
383 if (Subtarget->hasPOPCNT()) {
384 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
386 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
387 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
388 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
389 if (Subtarget->is64Bit())
390 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
393 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
395 if (!Subtarget->hasMOVBE())
396 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
398 // These should be promoted to a larger select which is supported.
399 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
400 // X86 wants to expand cmov itself.
401 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
402 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
403 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
404 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
405 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
406 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
407 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
408 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
409 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
410 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
411 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
412 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
413 if (Subtarget->is64Bit()) {
414 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
415 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
417 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
418 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
419 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
420 // support continuation, user-level threading, and etc.. As a result, no
421 // other SjLj exception interfaces are implemented and please don't build
422 // your own exception handling based on them.
423 // LLVM/Clang supports zero-cost DWARF exception handling.
424 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
425 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
428 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
429 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
430 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
431 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
432 if (Subtarget->is64Bit())
433 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
434 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
435 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
436 if (Subtarget->is64Bit()) {
437 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
438 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
439 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
440 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
441 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
443 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
444 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
445 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
446 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
447 if (Subtarget->is64Bit()) {
448 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
449 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
450 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
453 if (Subtarget->hasSSE1())
454 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
456 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
458 // Expand certain atomics
459 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
461 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
462 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
463 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
466 if (Subtarget->hasCmpxchg16b()) {
467 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
470 // FIXME - use subtarget debug flags
471 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
472 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
473 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
476 if (Subtarget->is64Bit()) {
477 setExceptionPointerRegister(X86::RAX);
478 setExceptionSelectorRegister(X86::RDX);
480 setExceptionPointerRegister(X86::EAX);
481 setExceptionSelectorRegister(X86::EDX);
483 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
484 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
486 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
487 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
489 setOperationAction(ISD::TRAP, MVT::Other, Legal);
490 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
492 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
493 setOperationAction(ISD::VASTART , MVT::Other, Custom);
494 setOperationAction(ISD::VAEND , MVT::Other, Expand);
495 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
496 // TargetInfo::X86_64ABIBuiltinVaList
497 setOperationAction(ISD::VAARG , MVT::Other, Custom);
498 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
500 // TargetInfo::CharPtrBuiltinVaList
501 setOperationAction(ISD::VAARG , MVT::Other, Expand);
502 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
505 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
506 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
508 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(*TD), Custom);
510 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
511 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
512 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
514 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
515 // f32 and f64 use SSE.
516 // Set up the FP register classes.
517 addRegisterClass(MVT::f32, &X86::FR32RegClass);
518 addRegisterClass(MVT::f64, &X86::FR64RegClass);
520 // Use ANDPD to simulate FABS.
521 setOperationAction(ISD::FABS , MVT::f64, Custom);
522 setOperationAction(ISD::FABS , MVT::f32, Custom);
524 // Use XORP to simulate FNEG.
525 setOperationAction(ISD::FNEG , MVT::f64, Custom);
526 setOperationAction(ISD::FNEG , MVT::f32, Custom);
528 // Use ANDPD and ORPD to simulate FCOPYSIGN.
529 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
530 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
532 // Lower this to FGETSIGNx86 plus an AND.
533 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
534 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
536 // We don't support sin/cos/fmod
537 setOperationAction(ISD::FSIN , MVT::f64, Expand);
538 setOperationAction(ISD::FCOS , MVT::f64, Expand);
539 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
540 setOperationAction(ISD::FSIN , MVT::f32, Expand);
541 setOperationAction(ISD::FCOS , MVT::f32, Expand);
542 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
544 // Expand FP immediates into loads from the stack, except for the special
546 addLegalFPImmediate(APFloat(+0.0)); // xorpd
547 addLegalFPImmediate(APFloat(+0.0f)); // xorps
548 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
549 // Use SSE for f32, x87 for f64.
550 // Set up the FP register classes.
551 addRegisterClass(MVT::f32, &X86::FR32RegClass);
552 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
554 // Use ANDPS to simulate FABS.
555 setOperationAction(ISD::FABS , MVT::f32, Custom);
557 // Use XORP to simulate FNEG.
558 setOperationAction(ISD::FNEG , MVT::f32, Custom);
560 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
562 // Use ANDPS and ORPS to simulate FCOPYSIGN.
563 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
564 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
566 // We don't support sin/cos/fmod
567 setOperationAction(ISD::FSIN , MVT::f32, Expand);
568 setOperationAction(ISD::FCOS , MVT::f32, Expand);
569 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
571 // Special cases we handle for FP constants.
572 addLegalFPImmediate(APFloat(+0.0f)); // xorps
573 addLegalFPImmediate(APFloat(+0.0)); // FLD0
574 addLegalFPImmediate(APFloat(+1.0)); // FLD1
575 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
576 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
578 if (!TM.Options.UnsafeFPMath) {
579 setOperationAction(ISD::FSIN , MVT::f64, Expand);
580 setOperationAction(ISD::FCOS , MVT::f64, Expand);
581 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
583 } else if (!Subtarget->useSoftFloat()) {
584 // f32 and f64 in x87.
585 // Set up the FP register classes.
586 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
587 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
589 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
590 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
591 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
592 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
594 if (!TM.Options.UnsafeFPMath) {
595 setOperationAction(ISD::FSIN , MVT::f64, Expand);
596 setOperationAction(ISD::FSIN , MVT::f32, Expand);
597 setOperationAction(ISD::FCOS , MVT::f64, Expand);
598 setOperationAction(ISD::FCOS , MVT::f32, Expand);
599 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
600 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
602 addLegalFPImmediate(APFloat(+0.0)); // FLD0
603 addLegalFPImmediate(APFloat(+1.0)); // FLD1
604 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
605 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
606 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
607 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
608 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
609 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
612 // We don't support FMA.
613 setOperationAction(ISD::FMA, MVT::f64, Expand);
614 setOperationAction(ISD::FMA, MVT::f32, Expand);
616 // Long double always uses X87.
617 if (!Subtarget->useSoftFloat()) {
618 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
619 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
620 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
622 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
623 addLegalFPImmediate(TmpFlt); // FLD0
625 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
628 APFloat TmpFlt2(+1.0);
629 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
631 addLegalFPImmediate(TmpFlt2); // FLD1
632 TmpFlt2.changeSign();
633 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
636 if (!TM.Options.UnsafeFPMath) {
637 setOperationAction(ISD::FSIN , MVT::f80, Expand);
638 setOperationAction(ISD::FCOS , MVT::f80, Expand);
639 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
642 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
643 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
644 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
645 setOperationAction(ISD::FRINT, MVT::f80, Expand);
646 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
647 setOperationAction(ISD::FMA, MVT::f80, Expand);
650 // Always use a library call for pow.
651 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
652 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
653 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
655 setOperationAction(ISD::FLOG, MVT::f80, Expand);
656 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
657 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
658 setOperationAction(ISD::FEXP, MVT::f80, Expand);
659 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
660 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
661 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
663 // First set operation action for all vector types to either promote
664 // (for widening) or expand (for scalarization). Then we will selectively
665 // turn on ones that can be effectively codegen'd.
666 for (MVT VT : MVT::vector_valuetypes()) {
667 setOperationAction(ISD::ADD , VT, Expand);
668 setOperationAction(ISD::SUB , VT, Expand);
669 setOperationAction(ISD::FADD, VT, Expand);
670 setOperationAction(ISD::FNEG, VT, Expand);
671 setOperationAction(ISD::FSUB, VT, Expand);
672 setOperationAction(ISD::MUL , VT, Expand);
673 setOperationAction(ISD::FMUL, VT, Expand);
674 setOperationAction(ISD::SDIV, VT, Expand);
675 setOperationAction(ISD::UDIV, VT, Expand);
676 setOperationAction(ISD::FDIV, VT, Expand);
677 setOperationAction(ISD::SREM, VT, Expand);
678 setOperationAction(ISD::UREM, VT, Expand);
679 setOperationAction(ISD::LOAD, VT, Expand);
680 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
681 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
682 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
683 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
684 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
685 setOperationAction(ISD::FABS, VT, Expand);
686 setOperationAction(ISD::FSIN, VT, Expand);
687 setOperationAction(ISD::FSINCOS, VT, Expand);
688 setOperationAction(ISD::FCOS, VT, Expand);
689 setOperationAction(ISD::FSINCOS, VT, Expand);
690 setOperationAction(ISD::FREM, VT, Expand);
691 setOperationAction(ISD::FMA, VT, Expand);
692 setOperationAction(ISD::FPOWI, VT, Expand);
693 setOperationAction(ISD::FSQRT, VT, Expand);
694 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
695 setOperationAction(ISD::FFLOOR, VT, Expand);
696 setOperationAction(ISD::FCEIL, VT, Expand);
697 setOperationAction(ISD::FTRUNC, VT, Expand);
698 setOperationAction(ISD::FRINT, VT, Expand);
699 setOperationAction(ISD::FNEARBYINT, VT, Expand);
700 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
701 setOperationAction(ISD::MULHS, VT, Expand);
702 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
703 setOperationAction(ISD::MULHU, VT, Expand);
704 setOperationAction(ISD::SDIVREM, VT, Expand);
705 setOperationAction(ISD::UDIVREM, VT, Expand);
706 setOperationAction(ISD::FPOW, VT, Expand);
707 setOperationAction(ISD::CTPOP, VT, Expand);
708 setOperationAction(ISD::CTTZ, VT, Expand);
709 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
710 setOperationAction(ISD::CTLZ, VT, Expand);
711 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
712 setOperationAction(ISD::SHL, VT, Expand);
713 setOperationAction(ISD::SRA, VT, Expand);
714 setOperationAction(ISD::SRL, VT, Expand);
715 setOperationAction(ISD::ROTL, VT, Expand);
716 setOperationAction(ISD::ROTR, VT, Expand);
717 setOperationAction(ISD::BSWAP, VT, Expand);
718 setOperationAction(ISD::SETCC, VT, Expand);
719 setOperationAction(ISD::FLOG, VT, Expand);
720 setOperationAction(ISD::FLOG2, VT, Expand);
721 setOperationAction(ISD::FLOG10, VT, Expand);
722 setOperationAction(ISD::FEXP, VT, Expand);
723 setOperationAction(ISD::FEXP2, VT, Expand);
724 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
725 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
726 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
727 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
728 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
729 setOperationAction(ISD::TRUNCATE, VT, Expand);
730 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
731 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
732 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
733 setOperationAction(ISD::VSELECT, VT, Expand);
734 setOperationAction(ISD::SELECT_CC, VT, Expand);
735 for (MVT InnerVT : MVT::vector_valuetypes()) {
736 setTruncStoreAction(InnerVT, VT, Expand);
738 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
739 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
741 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
742 // types, we have to deal with them whether we ask for Expansion or not.
743 // Setting Expand causes its own optimisation problems though, so leave
745 if (VT.getVectorElementType() == MVT::i1)
746 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
748 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
749 // split/scalarized right now.
750 if (VT.getVectorElementType() == MVT::f16)
751 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
755 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
756 // with -msoft-float, disable use of MMX as well.
757 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
758 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
759 // No operations on x86mmx supported, everything uses intrinsics.
762 // MMX-sized vectors (other than x86mmx) are expected to be expanded
763 // into smaller operations.
764 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
765 setOperationAction(ISD::MULHS, MMXTy, Expand);
766 setOperationAction(ISD::AND, MMXTy, Expand);
767 setOperationAction(ISD::OR, MMXTy, Expand);
768 setOperationAction(ISD::XOR, MMXTy, Expand);
769 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
770 setOperationAction(ISD::SELECT, MMXTy, Expand);
771 setOperationAction(ISD::BITCAST, MMXTy, Expand);
773 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
775 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
776 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
778 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
779 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
780 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
781 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
782 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
783 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
784 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
785 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
786 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
787 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
788 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
789 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
790 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
791 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
794 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
795 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
797 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
798 // registers cannot be used even for integer operations.
799 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
800 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
801 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
802 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
804 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
805 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
806 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
807 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
808 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
809 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
810 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
811 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
812 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
813 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
814 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
815 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
816 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
817 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
818 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
819 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
820 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
821 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
822 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
823 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
824 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
825 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
826 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
828 setOperationAction(ISD::SMAX, MVT::v8i16, Legal);
829 setOperationAction(ISD::UMAX, MVT::v16i8, Legal);
830 setOperationAction(ISD::SMIN, MVT::v8i16, Legal);
831 setOperationAction(ISD::UMIN, MVT::v16i8, Legal);
833 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
834 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
835 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
836 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
838 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
839 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
840 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
841 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
842 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
844 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
845 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
846 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
847 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
849 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
850 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
851 MVT VT = (MVT::SimpleValueType)i;
852 // Do not attempt to custom lower non-power-of-2 vectors
853 if (!isPowerOf2_32(VT.getVectorNumElements()))
855 // Do not attempt to custom lower non-128-bit vectors
856 if (!VT.is128BitVector())
858 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
859 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
860 setOperationAction(ISD::VSELECT, VT, Custom);
861 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
864 // We support custom legalizing of sext and anyext loads for specific
865 // memory vector types which we can load as a scalar (or sequence of
866 // scalars) and extend in-register to a legal 128-bit vector type. For sext
867 // loads these must work with a single scalar load.
868 for (MVT VT : MVT::integer_vector_valuetypes()) {
869 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
870 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
871 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
872 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
873 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
874 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
875 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
876 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
877 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
880 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
881 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
882 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
883 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
884 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
885 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
886 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
887 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
889 if (Subtarget->is64Bit()) {
890 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
891 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
894 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
895 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
896 MVT VT = (MVT::SimpleValueType)i;
898 // Do not attempt to promote non-128-bit vectors
899 if (!VT.is128BitVector())
902 setOperationAction(ISD::AND, VT, Promote);
903 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
904 setOperationAction(ISD::OR, VT, Promote);
905 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
906 setOperationAction(ISD::XOR, VT, Promote);
907 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
908 setOperationAction(ISD::LOAD, VT, Promote);
909 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
910 setOperationAction(ISD::SELECT, VT, Promote);
911 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
914 // Custom lower v2i64 and v2f64 selects.
915 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
916 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
917 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
918 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
920 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
921 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
923 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
925 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
926 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
927 // As there is no 64-bit GPR available, we need build a special custom
928 // sequence to convert from v2i32 to v2f32.
929 if (!Subtarget->is64Bit())
930 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
932 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
933 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
935 for (MVT VT : MVT::fp_vector_valuetypes())
936 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
938 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
939 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
940 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
943 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
944 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
945 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
946 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
947 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
948 setOperationAction(ISD::FRINT, RoundedTy, Legal);
949 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
952 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
953 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
954 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
955 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
956 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
957 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
958 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
959 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
961 // FIXME: Do we need to handle scalar-to-vector here?
962 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
964 // We directly match byte blends in the backend as they match the VSELECT
966 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
968 // SSE41 brings specific instructions for doing vector sign extend even in
969 // cases where we don't have SRA.
970 for (MVT VT : MVT::integer_vector_valuetypes()) {
971 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
972 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
973 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
976 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
977 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
978 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
979 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
980 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
981 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
982 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
984 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
985 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
986 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
987 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
988 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
989 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
991 // i8 and i16 vectors are custom because the source register and source
992 // source memory operand types are not the same width. f32 vectors are
993 // custom since the immediate controlling the insert encodes additional
995 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
996 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
997 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
998 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1000 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1001 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1002 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1003 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1005 // FIXME: these should be Legal, but that's only for the case where
1006 // the index is constant. For now custom expand to deal with that.
1007 if (Subtarget->is64Bit()) {
1008 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1009 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1013 if (Subtarget->hasSSE2()) {
1014 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1015 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1016 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1018 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1019 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1021 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1022 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1024 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1025 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1027 // In the customized shift lowering, the legal cases in AVX2 will be
1029 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1030 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1032 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1033 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1035 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1036 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1039 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1040 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1041 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1042 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1043 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1044 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1045 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1047 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1048 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1049 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1051 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1052 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1053 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1054 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1055 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1056 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1057 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1058 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1059 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1060 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1061 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1062 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1064 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1065 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1066 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1067 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1068 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1069 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1070 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1071 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1072 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1073 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1074 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1075 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1077 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1078 // even though v8i16 is a legal type.
1079 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1080 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1081 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1083 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1084 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1085 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1087 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1088 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1090 for (MVT VT : MVT::fp_vector_valuetypes())
1091 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1093 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1094 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1096 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1097 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1099 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1100 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1102 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1103 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1104 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1105 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1107 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1108 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1109 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1111 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1112 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1113 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1114 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1115 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1116 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1117 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1118 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1119 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1120 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1121 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1122 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1124 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1125 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1126 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1127 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1129 if (Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()) {
1130 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1131 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1132 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1133 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1134 setOperationAction(ISD::FMA, MVT::f32, Legal);
1135 setOperationAction(ISD::FMA, MVT::f64, Legal);
1138 if (Subtarget->hasInt256()) {
1139 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1140 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1141 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1142 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1144 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1145 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1146 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1147 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1149 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1150 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1151 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1152 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1154 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1155 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1156 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1157 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1159 setOperationAction(ISD::SMAX, MVT::v32i8, Legal);
1160 setOperationAction(ISD::SMAX, MVT::v16i16, Legal);
1161 setOperationAction(ISD::SMAX, MVT::v8i32, Legal);
1162 setOperationAction(ISD::UMAX, MVT::v32i8, Legal);
1163 setOperationAction(ISD::UMAX, MVT::v16i16, Legal);
1164 setOperationAction(ISD::UMAX, MVT::v8i32, Legal);
1165 setOperationAction(ISD::SMIN, MVT::v32i8, Legal);
1166 setOperationAction(ISD::SMIN, MVT::v16i16, Legal);
1167 setOperationAction(ISD::SMIN, MVT::v8i32, Legal);
1168 setOperationAction(ISD::UMIN, MVT::v32i8, Legal);
1169 setOperationAction(ISD::UMIN, MVT::v16i16, Legal);
1170 setOperationAction(ISD::UMIN, MVT::v8i32, Legal);
1172 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1173 // when we have a 256bit-wide blend with immediate.
1174 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1176 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1177 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1178 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1179 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1180 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1181 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1182 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1184 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1185 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1186 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1187 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1188 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1189 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1191 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1192 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1193 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1194 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1196 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1197 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1198 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1199 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1201 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1202 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1203 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1204 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1207 // In the customized shift lowering, the legal cases in AVX2 will be
1209 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1210 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1212 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1213 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1215 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1216 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1218 // Custom lower several nodes for 256-bit types.
1219 for (MVT VT : MVT::vector_valuetypes()) {
1220 if (VT.getScalarSizeInBits() >= 32) {
1221 setOperationAction(ISD::MLOAD, VT, Legal);
1222 setOperationAction(ISD::MSTORE, VT, Legal);
1224 // Extract subvector is special because the value type
1225 // (result) is 128-bit but the source is 256-bit wide.
1226 if (VT.is128BitVector()) {
1227 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1229 // Do not attempt to custom lower other non-256-bit vectors
1230 if (!VT.is256BitVector())
1233 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1234 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1235 setOperationAction(ISD::VSELECT, VT, Custom);
1236 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1237 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1238 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1239 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1240 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1243 if (Subtarget->hasInt256())
1244 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1247 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1248 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1249 MVT VT = (MVT::SimpleValueType)i;
1251 // Do not attempt to promote non-256-bit vectors
1252 if (!VT.is256BitVector())
1255 setOperationAction(ISD::AND, VT, Promote);
1256 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1257 setOperationAction(ISD::OR, VT, Promote);
1258 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1259 setOperationAction(ISD::XOR, VT, Promote);
1260 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1261 setOperationAction(ISD::LOAD, VT, Promote);
1262 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1263 setOperationAction(ISD::SELECT, VT, Promote);
1264 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1268 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1269 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1270 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1271 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1272 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1274 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1275 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1276 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1278 for (MVT VT : MVT::fp_vector_valuetypes())
1279 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1281 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1282 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1283 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1284 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1285 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1286 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1287 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1288 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1289 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1290 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1291 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1292 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1294 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1295 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1296 setOperationAction(ISD::XOR, MVT::i1, Legal);
1297 setOperationAction(ISD::OR, MVT::i1, Legal);
1298 setOperationAction(ISD::AND, MVT::i1, Legal);
1299 setOperationAction(ISD::SUB, MVT::i1, Custom);
1300 setOperationAction(ISD::ADD, MVT::i1, Custom);
1301 setOperationAction(ISD::MUL, MVT::i1, Custom);
1302 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1303 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1304 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1305 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1306 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1308 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1309 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1310 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1311 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1312 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1313 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1315 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1316 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1317 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1318 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1319 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1320 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1321 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1322 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1324 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1325 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1326 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1327 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1328 if (Subtarget->is64Bit()) {
1329 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1330 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1331 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1332 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1334 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1335 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1336 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1337 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1338 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1339 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1340 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1341 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1342 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1343 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1344 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1345 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1346 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1347 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1348 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1349 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1351 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1352 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1353 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1354 if (Subtarget->hasDQI()) {
1355 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1356 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1358 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1359 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1360 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1361 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1362 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1363 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1364 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1365 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1366 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1367 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1368 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1369 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1370 if (Subtarget->hasDQI()) {
1371 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1372 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1374 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1375 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1376 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1377 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1378 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1379 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1380 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1381 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1382 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1383 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1385 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1386 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1387 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1388 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1389 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1391 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1392 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1394 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1396 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1397 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1398 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1399 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1400 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1401 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1402 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1403 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1404 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1405 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1406 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1408 setOperationAction(ISD::SMAX, MVT::v16i32, Legal);
1409 setOperationAction(ISD::SMAX, MVT::v8i64, Legal);
1410 setOperationAction(ISD::UMAX, MVT::v16i32, Legal);
1411 setOperationAction(ISD::UMAX, MVT::v8i64, Legal);
1412 setOperationAction(ISD::SMIN, MVT::v16i32, Legal);
1413 setOperationAction(ISD::SMIN, MVT::v8i64, Legal);
1414 setOperationAction(ISD::UMIN, MVT::v16i32, Legal);
1415 setOperationAction(ISD::UMIN, MVT::v8i64, Legal);
1417 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1418 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1420 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1421 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1423 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1425 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1426 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1428 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1429 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1431 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1434 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1435 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1436 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1437 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1438 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1439 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1441 if (Subtarget->hasCDI()) {
1442 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1443 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1445 if (Subtarget->hasDQI()) {
1446 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1447 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1448 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1450 // Custom lower several nodes.
1451 for (MVT VT : MVT::vector_valuetypes()) {
1452 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1454 setOperationAction(ISD::AND, VT, Legal);
1455 setOperationAction(ISD::OR, VT, Legal);
1456 setOperationAction(ISD::XOR, VT, Legal);
1458 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1459 setOperationAction(ISD::MGATHER, VT, Custom);
1460 setOperationAction(ISD::MSCATTER, VT, Custom);
1462 // Extract subvector is special because the value type
1463 // (result) is 256/128-bit but the source is 512-bit wide.
1464 if (VT.is128BitVector() || VT.is256BitVector()) {
1465 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1467 if (VT.getVectorElementType() == MVT::i1)
1468 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1470 // Do not attempt to custom lower other non-512-bit vectors
1471 if (!VT.is512BitVector())
1474 if (EltSize >= 32) {
1475 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1476 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1477 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1478 setOperationAction(ISD::VSELECT, VT, Legal);
1479 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1480 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1481 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1482 setOperationAction(ISD::MLOAD, VT, Legal);
1483 setOperationAction(ISD::MSTORE, VT, Legal);
1486 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1487 MVT VT = (MVT::SimpleValueType)i;
1489 // Do not attempt to promote non-512-bit vectors.
1490 if (!VT.is512BitVector())
1493 setOperationAction(ISD::SELECT, VT, Promote);
1494 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1498 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1499 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1500 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1502 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1503 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1505 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1506 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1507 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1508 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1509 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1510 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1511 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1512 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1513 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1514 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1515 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1516 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1517 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1518 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1519 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1520 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1521 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1522 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1523 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1524 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1525 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1526 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1527 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1528 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1529 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1530 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1531 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1532 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1533 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1535 setOperationAction(ISD::SMAX, MVT::v64i8, Legal);
1536 setOperationAction(ISD::SMAX, MVT::v32i16, Legal);
1537 setOperationAction(ISD::UMAX, MVT::v64i8, Legal);
1538 setOperationAction(ISD::UMAX, MVT::v32i16, Legal);
1539 setOperationAction(ISD::SMIN, MVT::v64i8, Legal);
1540 setOperationAction(ISD::SMIN, MVT::v32i16, Legal);
1541 setOperationAction(ISD::UMIN, MVT::v64i8, Legal);
1542 setOperationAction(ISD::UMIN, MVT::v32i16, Legal);
1544 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1545 const MVT VT = (MVT::SimpleValueType)i;
1547 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1549 // Do not attempt to promote non-512-bit vectors.
1550 if (!VT.is512BitVector())
1554 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1555 setOperationAction(ISD::VSELECT, VT, Legal);
1560 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1561 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1562 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1564 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1565 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1566 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1567 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1568 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1569 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1570 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1571 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1572 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1573 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1575 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1576 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1577 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1578 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1579 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1580 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1581 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1582 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1584 setOperationAction(ISD::SMAX, MVT::v2i64, Legal);
1585 setOperationAction(ISD::SMAX, MVT::v4i64, Legal);
1586 setOperationAction(ISD::UMAX, MVT::v2i64, Legal);
1587 setOperationAction(ISD::UMAX, MVT::v4i64, Legal);
1588 setOperationAction(ISD::SMIN, MVT::v2i64, Legal);
1589 setOperationAction(ISD::SMIN, MVT::v4i64, Legal);
1590 setOperationAction(ISD::UMIN, MVT::v2i64, Legal);
1591 setOperationAction(ISD::UMIN, MVT::v4i64, Legal);
1594 // We want to custom lower some of our intrinsics.
1595 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1596 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1597 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1598 if (!Subtarget->is64Bit())
1599 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1601 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1602 // handle type legalization for these operations here.
1604 // FIXME: We really should do custom legalization for addition and
1605 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1606 // than generic legalization for 64-bit multiplication-with-overflow, though.
1607 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1608 // Add/Sub/Mul with overflow operations are custom lowered.
1610 setOperationAction(ISD::SADDO, VT, Custom);
1611 setOperationAction(ISD::UADDO, VT, Custom);
1612 setOperationAction(ISD::SSUBO, VT, Custom);
1613 setOperationAction(ISD::USUBO, VT, Custom);
1614 setOperationAction(ISD::SMULO, VT, Custom);
1615 setOperationAction(ISD::UMULO, VT, Custom);
1619 if (!Subtarget->is64Bit()) {
1620 // These libcalls are not available in 32-bit.
1621 setLibcallName(RTLIB::SHL_I128, nullptr);
1622 setLibcallName(RTLIB::SRL_I128, nullptr);
1623 setLibcallName(RTLIB::SRA_I128, nullptr);
1626 // Combine sin / cos into one node or libcall if possible.
1627 if (Subtarget->hasSinCos()) {
1628 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1629 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1630 if (Subtarget->isTargetDarwin()) {
1631 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1632 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1633 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1634 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1638 if (Subtarget->isTargetWin64()) {
1639 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1640 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1641 setOperationAction(ISD::SREM, MVT::i128, Custom);
1642 setOperationAction(ISD::UREM, MVT::i128, Custom);
1643 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1644 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1647 // We have target-specific dag combine patterns for the following nodes:
1648 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1649 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1650 setTargetDAGCombine(ISD::BITCAST);
1651 setTargetDAGCombine(ISD::VSELECT);
1652 setTargetDAGCombine(ISD::SELECT);
1653 setTargetDAGCombine(ISD::SHL);
1654 setTargetDAGCombine(ISD::SRA);
1655 setTargetDAGCombine(ISD::SRL);
1656 setTargetDAGCombine(ISD::OR);
1657 setTargetDAGCombine(ISD::AND);
1658 setTargetDAGCombine(ISD::ADD);
1659 setTargetDAGCombine(ISD::FADD);
1660 setTargetDAGCombine(ISD::FSUB);
1661 setTargetDAGCombine(ISD::FMA);
1662 setTargetDAGCombine(ISD::SUB);
1663 setTargetDAGCombine(ISD::LOAD);
1664 setTargetDAGCombine(ISD::MLOAD);
1665 setTargetDAGCombine(ISD::STORE);
1666 setTargetDAGCombine(ISD::MSTORE);
1667 setTargetDAGCombine(ISD::ZERO_EXTEND);
1668 setTargetDAGCombine(ISD::ANY_EXTEND);
1669 setTargetDAGCombine(ISD::SIGN_EXTEND);
1670 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1671 setTargetDAGCombine(ISD::SINT_TO_FP);
1672 setTargetDAGCombine(ISD::UINT_TO_FP);
1673 setTargetDAGCombine(ISD::SETCC);
1674 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1675 setTargetDAGCombine(ISD::BUILD_VECTOR);
1676 setTargetDAGCombine(ISD::MUL);
1677 setTargetDAGCombine(ISD::XOR);
1679 computeRegisterProperties(Subtarget->getRegisterInfo());
1681 // On Darwin, -Os means optimize for size without hurting performance,
1682 // do not reduce the limit.
1683 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1684 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1685 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1686 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1687 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1688 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1689 setPrefLoopAlignment(4); // 2^4 bytes.
1691 // Predictable cmov don't hurt on atom because it's in-order.
1692 PredictableSelectIsExpensive = !Subtarget->isAtom();
1693 EnableExtLdPromotion = true;
1694 setPrefFunctionAlignment(4); // 2^4 bytes.
1696 verifyIntrinsicTables();
1699 // This has so far only been implemented for 64-bit MachO.
1700 bool X86TargetLowering::useLoadStackGuardNode() const {
1701 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1704 TargetLoweringBase::LegalizeTypeAction
1705 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1706 if (ExperimentalVectorWideningLegalization &&
1707 VT.getVectorNumElements() != 1 &&
1708 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1709 return TypeWidenVector;
1711 return TargetLoweringBase::getPreferredVectorAction(VT);
1714 EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1717 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1719 const unsigned NumElts = VT.getVectorNumElements();
1720 const EVT EltVT = VT.getVectorElementType();
1721 if (VT.is512BitVector()) {
1722 if (Subtarget->hasAVX512())
1723 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1724 EltVT == MVT::f32 || EltVT == MVT::f64)
1726 case 8: return MVT::v8i1;
1727 case 16: return MVT::v16i1;
1729 if (Subtarget->hasBWI())
1730 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1732 case 32: return MVT::v32i1;
1733 case 64: return MVT::v64i1;
1737 if (VT.is256BitVector() || VT.is128BitVector()) {
1738 if (Subtarget->hasVLX())
1739 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1740 EltVT == MVT::f32 || EltVT == MVT::f64)
1742 case 2: return MVT::v2i1;
1743 case 4: return MVT::v4i1;
1744 case 8: return MVT::v8i1;
1746 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1747 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1749 case 8: return MVT::v8i1;
1750 case 16: return MVT::v16i1;
1751 case 32: return MVT::v32i1;
1755 return VT.changeVectorElementTypeToInteger();
1758 /// Helper for getByValTypeAlignment to determine
1759 /// the desired ByVal argument alignment.
1760 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1763 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1764 if (VTy->getBitWidth() == 128)
1766 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1767 unsigned EltAlign = 0;
1768 getMaxByValAlign(ATy->getElementType(), EltAlign);
1769 if (EltAlign > MaxAlign)
1770 MaxAlign = EltAlign;
1771 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1772 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1773 unsigned EltAlign = 0;
1774 getMaxByValAlign(STy->getElementType(i), EltAlign);
1775 if (EltAlign > MaxAlign)
1776 MaxAlign = EltAlign;
1783 /// Return the desired alignment for ByVal aggregate
1784 /// function arguments in the caller parameter area. For X86, aggregates
1785 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1786 /// are at 4-byte boundaries.
1787 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,
1788 const DataLayout &DL) const {
1789 if (Subtarget->is64Bit()) {
1790 // Max of 8 and alignment of type.
1791 unsigned TyAlign = DL.getABITypeAlignment(Ty);
1798 if (Subtarget->hasSSE1())
1799 getMaxByValAlign(Ty, Align);
1803 /// Returns the target specific optimal type for load
1804 /// and store operations as a result of memset, memcpy, and memmove
1805 /// lowering. If DstAlign is zero that means it's safe to destination
1806 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1807 /// means there isn't a need to check it against alignment requirement,
1808 /// probably because the source does not need to be loaded. If 'IsMemset' is
1809 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1810 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1811 /// source is constant so it does not need to be loaded.
1812 /// It returns EVT::Other if the type should be determined using generic
1813 /// target-independent logic.
1815 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1816 unsigned DstAlign, unsigned SrcAlign,
1817 bool IsMemset, bool ZeroMemset,
1819 MachineFunction &MF) const {
1820 const Function *F = MF.getFunction();
1821 if ((!IsMemset || ZeroMemset) &&
1822 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1824 (Subtarget->isUnalignedMemAccessFast() ||
1825 ((DstAlign == 0 || DstAlign >= 16) &&
1826 (SrcAlign == 0 || SrcAlign >= 16)))) {
1828 if (Subtarget->hasInt256())
1830 if (Subtarget->hasFp256())
1833 if (Subtarget->hasSSE2())
1835 if (Subtarget->hasSSE1())
1837 } else if (!MemcpyStrSrc && Size >= 8 &&
1838 !Subtarget->is64Bit() &&
1839 Subtarget->hasSSE2()) {
1840 // Do not use f64 to lower memcpy if source is string constant. It's
1841 // better to use i32 to avoid the loads.
1845 if (Subtarget->is64Bit() && Size >= 8)
1850 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1852 return X86ScalarSSEf32;
1853 else if (VT == MVT::f64)
1854 return X86ScalarSSEf64;
1859 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1864 *Fast = Subtarget->isUnalignedMemAccessFast();
1868 /// Return the entry encoding for a jump table in the
1869 /// current function. The returned value is a member of the
1870 /// MachineJumpTableInfo::JTEntryKind enum.
1871 unsigned X86TargetLowering::getJumpTableEncoding() const {
1872 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1874 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1875 Subtarget->isPICStyleGOT())
1876 return MachineJumpTableInfo::EK_Custom32;
1878 // Otherwise, use the normal jump table encoding heuristics.
1879 return TargetLowering::getJumpTableEncoding();
1882 bool X86TargetLowering::useSoftFloat() const {
1883 return Subtarget->useSoftFloat();
1887 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1888 const MachineBasicBlock *MBB,
1889 unsigned uid,MCContext &Ctx) const{
1890 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1891 Subtarget->isPICStyleGOT());
1892 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1894 return MCSymbolRefExpr::create(MBB->getSymbol(),
1895 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1898 /// Returns relocation base for the given PIC jumptable.
1899 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1900 SelectionDAG &DAG) const {
1901 if (!Subtarget->is64Bit())
1902 // This doesn't have SDLoc associated with it, but is not really the
1903 // same as a Register.
1904 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
1905 getPointerTy(DAG.getDataLayout()));
1909 /// This returns the relocation base for the given PIC jumptable,
1910 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
1911 const MCExpr *X86TargetLowering::
1912 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1913 MCContext &Ctx) const {
1914 // X86-64 uses RIP relative addressing based on the jump table label.
1915 if (Subtarget->isPICStyleRIPRel())
1916 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1918 // Otherwise, the reference is relative to the PIC base.
1919 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
1922 std::pair<const TargetRegisterClass *, uint8_t>
1923 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1925 const TargetRegisterClass *RRC = nullptr;
1927 switch (VT.SimpleTy) {
1929 return TargetLowering::findRepresentativeClass(TRI, VT);
1930 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1931 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1934 RRC = &X86::VR64RegClass;
1936 case MVT::f32: case MVT::f64:
1937 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1938 case MVT::v4f32: case MVT::v2f64:
1939 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1941 RRC = &X86::VR128RegClass;
1944 return std::make_pair(RRC, Cost);
1947 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1948 unsigned &Offset) const {
1949 if (!Subtarget->isTargetLinux())
1952 if (Subtarget->is64Bit()) {
1953 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1955 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1967 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1968 unsigned DestAS) const {
1969 assert(SrcAS != DestAS && "Expected different address spaces!");
1971 return SrcAS < 256 && DestAS < 256;
1974 //===----------------------------------------------------------------------===//
1975 // Return Value Calling Convention Implementation
1976 //===----------------------------------------------------------------------===//
1978 #include "X86GenCallingConv.inc"
1981 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1982 MachineFunction &MF, bool isVarArg,
1983 const SmallVectorImpl<ISD::OutputArg> &Outs,
1984 LLVMContext &Context) const {
1985 SmallVector<CCValAssign, 16> RVLocs;
1986 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1987 return CCInfo.CheckReturn(Outs, RetCC_X86);
1990 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1991 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1996 X86TargetLowering::LowerReturn(SDValue Chain,
1997 CallingConv::ID CallConv, bool isVarArg,
1998 const SmallVectorImpl<ISD::OutputArg> &Outs,
1999 const SmallVectorImpl<SDValue> &OutVals,
2000 SDLoc dl, SelectionDAG &DAG) const {
2001 MachineFunction &MF = DAG.getMachineFunction();
2002 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2004 SmallVector<CCValAssign, 16> RVLocs;
2005 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2006 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2009 SmallVector<SDValue, 6> RetOps;
2010 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2011 // Operand #1 = Bytes To Pop
2012 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2015 // Copy the result values into the output registers.
2016 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2017 CCValAssign &VA = RVLocs[i];
2018 assert(VA.isRegLoc() && "Can only return in registers!");
2019 SDValue ValToCopy = OutVals[i];
2020 EVT ValVT = ValToCopy.getValueType();
2022 // Promote values to the appropriate types.
2023 if (VA.getLocInfo() == CCValAssign::SExt)
2024 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2025 else if (VA.getLocInfo() == CCValAssign::ZExt)
2026 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2027 else if (VA.getLocInfo() == CCValAssign::AExt) {
2028 if (ValVT.isVector() && ValVT.getScalarType() == MVT::i1)
2029 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2031 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2033 else if (VA.getLocInfo() == CCValAssign::BCvt)
2034 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2036 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2037 "Unexpected FP-extend for return value.");
2039 // If this is x86-64, and we disabled SSE, we can't return FP values,
2040 // or SSE or MMX vectors.
2041 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2042 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2043 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2044 report_fatal_error("SSE register return with SSE disabled");
2046 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2047 // llvm-gcc has never done it right and no one has noticed, so this
2048 // should be OK for now.
2049 if (ValVT == MVT::f64 &&
2050 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2051 report_fatal_error("SSE2 register return with SSE2 disabled");
2053 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2054 // the RET instruction and handled by the FP Stackifier.
2055 if (VA.getLocReg() == X86::FP0 ||
2056 VA.getLocReg() == X86::FP1) {
2057 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2058 // change the value to the FP stack register class.
2059 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2060 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2061 RetOps.push_back(ValToCopy);
2062 // Don't emit a copytoreg.
2066 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2067 // which is returned in RAX / RDX.
2068 if (Subtarget->is64Bit()) {
2069 if (ValVT == MVT::x86mmx) {
2070 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2071 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2072 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2074 // If we don't have SSE2 available, convert to v4f32 so the generated
2075 // register is legal.
2076 if (!Subtarget->hasSSE2())
2077 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2082 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2083 Flag = Chain.getValue(1);
2084 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2087 // All x86 ABIs require that for returning structs by value we copy
2088 // the sret argument into %rax/%eax (depending on ABI) for the return.
2089 // We saved the argument into a virtual register in the entry block,
2090 // so now we copy the value out and into %rax/%eax.
2092 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2093 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2094 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2095 // either case FuncInfo->setSRetReturnReg() will have been called.
2096 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2097 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg,
2098 getPointerTy(MF.getDataLayout()));
2101 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2102 X86::RAX : X86::EAX;
2103 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2104 Flag = Chain.getValue(1);
2106 // RAX/EAX now acts like a return value.
2108 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2111 RetOps[0] = Chain; // Update chain.
2113 // Add the flag if we have it.
2115 RetOps.push_back(Flag);
2117 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2120 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2121 if (N->getNumValues() != 1)
2123 if (!N->hasNUsesOfValue(1, 0))
2126 SDValue TCChain = Chain;
2127 SDNode *Copy = *N->use_begin();
2128 if (Copy->getOpcode() == ISD::CopyToReg) {
2129 // If the copy has a glue operand, we conservatively assume it isn't safe to
2130 // perform a tail call.
2131 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2133 TCChain = Copy->getOperand(0);
2134 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2137 bool HasRet = false;
2138 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2140 if (UI->getOpcode() != X86ISD::RET_FLAG)
2142 // If we are returning more than one value, we can definitely
2143 // not make a tail call see PR19530
2144 if (UI->getNumOperands() > 4)
2146 if (UI->getNumOperands() == 4 &&
2147 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2160 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2161 ISD::NodeType ExtendKind) const {
2163 // TODO: Is this also valid on 32-bit?
2164 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2165 ReturnMVT = MVT::i8;
2167 ReturnMVT = MVT::i32;
2169 EVT MinVT = getRegisterType(Context, ReturnMVT);
2170 return VT.bitsLT(MinVT) ? MinVT : VT;
2173 /// Lower the result values of a call into the
2174 /// appropriate copies out of appropriate physical registers.
2177 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2178 CallingConv::ID CallConv, bool isVarArg,
2179 const SmallVectorImpl<ISD::InputArg> &Ins,
2180 SDLoc dl, SelectionDAG &DAG,
2181 SmallVectorImpl<SDValue> &InVals) const {
2183 // Assign locations to each value returned by this call.
2184 SmallVector<CCValAssign, 16> RVLocs;
2185 bool Is64Bit = Subtarget->is64Bit();
2186 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2188 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2190 // Copy all of the result registers out of their specified physreg.
2191 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2192 CCValAssign &VA = RVLocs[i];
2193 EVT CopyVT = VA.getLocVT();
2195 // If this is x86-64, and we disabled SSE, we can't return FP values
2196 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2197 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2198 report_fatal_error("SSE register return with SSE disabled");
2201 // If we prefer to use the value in xmm registers, copy it out as f80 and
2202 // use a truncate to move it from fp stack reg to xmm reg.
2203 bool RoundAfterCopy = false;
2204 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2205 isScalarFPTypeInSSEReg(VA.getValVT())) {
2207 RoundAfterCopy = (CopyVT != VA.getLocVT());
2210 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2211 CopyVT, InFlag).getValue(1);
2212 SDValue Val = Chain.getValue(0);
2215 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2216 // This truncation won't change the value.
2217 DAG.getIntPtrConstant(1, dl));
2219 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2220 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2222 InFlag = Chain.getValue(2);
2223 InVals.push_back(Val);
2229 //===----------------------------------------------------------------------===//
2230 // C & StdCall & Fast Calling Convention implementation
2231 //===----------------------------------------------------------------------===//
2232 // StdCall calling convention seems to be standard for many Windows' API
2233 // routines and around. It differs from C calling convention just a little:
2234 // callee should clean up the stack, not caller. Symbols should be also
2235 // decorated in some fancy way :) It doesn't support any vector arguments.
2236 // For info on fast calling convention see Fast Calling Convention (tail call)
2237 // implementation LowerX86_32FastCCCallTo.
2239 /// CallIsStructReturn - Determines whether a call uses struct return
2241 enum StructReturnType {
2246 static StructReturnType
2247 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2249 return NotStructReturn;
2251 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2252 if (!Flags.isSRet())
2253 return NotStructReturn;
2254 if (Flags.isInReg())
2255 return RegStructReturn;
2256 return StackStructReturn;
2259 /// Determines whether a function uses struct return semantics.
2260 static StructReturnType
2261 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2263 return NotStructReturn;
2265 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2266 if (!Flags.isSRet())
2267 return NotStructReturn;
2268 if (Flags.isInReg())
2269 return RegStructReturn;
2270 return StackStructReturn;
2273 /// Make a copy of an aggregate at address specified by "Src" to address
2274 /// "Dst" with size and alignment information specified by the specific
2275 /// parameter attribute. The copy will be passed as a byval function parameter.
2277 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2278 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2280 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2282 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2283 /*isVolatile*/false, /*AlwaysInline=*/true,
2284 /*isTailCall*/false,
2285 MachinePointerInfo(), MachinePointerInfo());
2288 /// Return true if the calling convention is one that
2289 /// supports tail call optimization.
2290 static bool IsTailCallConvention(CallingConv::ID CC) {
2291 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2292 CC == CallingConv::HiPE);
2295 /// \brief Return true if the calling convention is a C calling convention.
2296 static bool IsCCallConvention(CallingConv::ID CC) {
2297 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2298 CC == CallingConv::X86_64_SysV);
2301 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2303 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2304 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2308 CallingConv::ID CalleeCC = CS.getCallingConv();
2309 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2315 /// Return true if the function is being made into
2316 /// a tailcall target by changing its ABI.
2317 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2318 bool GuaranteedTailCallOpt) {
2319 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2323 X86TargetLowering::LowerMemArgument(SDValue Chain,
2324 CallingConv::ID CallConv,
2325 const SmallVectorImpl<ISD::InputArg> &Ins,
2326 SDLoc dl, SelectionDAG &DAG,
2327 const CCValAssign &VA,
2328 MachineFrameInfo *MFI,
2330 // Create the nodes corresponding to a load from this parameter slot.
2331 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2332 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2333 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2334 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2337 // If value is passed by pointer we have address passed instead of the value
2339 bool ExtendedInMem = VA.isExtInLoc() &&
2340 VA.getValVT().getScalarType() == MVT::i1;
2342 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2343 ValVT = VA.getLocVT();
2345 ValVT = VA.getValVT();
2347 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2348 // changed with more analysis.
2349 // In case of tail call optimization mark all arguments mutable. Since they
2350 // could be overwritten by lowering of arguments in case of a tail call.
2351 if (Flags.isByVal()) {
2352 unsigned Bytes = Flags.getByValSize();
2353 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2354 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2355 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2357 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2358 VA.getLocMemOffset(), isImmutable);
2359 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2360 SDValue Val = DAG.getLoad(ValVT, dl, Chain, FIN,
2361 MachinePointerInfo::getFixedStack(FI),
2362 false, false, false, 0);
2363 return ExtendedInMem ?
2364 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2368 // FIXME: Get this from tablegen.
2369 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2370 const X86Subtarget *Subtarget) {
2371 assert(Subtarget->is64Bit());
2373 if (Subtarget->isCallingConvWin64(CallConv)) {
2374 static const MCPhysReg GPR64ArgRegsWin64[] = {
2375 X86::RCX, X86::RDX, X86::R8, X86::R9
2377 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2380 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2381 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2383 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2386 // FIXME: Get this from tablegen.
2387 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2388 CallingConv::ID CallConv,
2389 const X86Subtarget *Subtarget) {
2390 assert(Subtarget->is64Bit());
2391 if (Subtarget->isCallingConvWin64(CallConv)) {
2392 // The XMM registers which might contain var arg parameters are shadowed
2393 // in their paired GPR. So we only need to save the GPR to their home
2395 // TODO: __vectorcall will change this.
2399 const Function *Fn = MF.getFunction();
2400 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2401 bool isSoftFloat = Subtarget->useSoftFloat();
2402 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2403 "SSE register cannot be used when SSE is disabled!");
2404 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2405 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2409 static const MCPhysReg XMMArgRegs64Bit[] = {
2410 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2411 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2413 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2417 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2418 CallingConv::ID CallConv,
2420 const SmallVectorImpl<ISD::InputArg> &Ins,
2423 SmallVectorImpl<SDValue> &InVals)
2425 MachineFunction &MF = DAG.getMachineFunction();
2426 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2427 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2429 const Function* Fn = MF.getFunction();
2430 if (Fn->hasExternalLinkage() &&
2431 Subtarget->isTargetCygMing() &&
2432 Fn->getName() == "main")
2433 FuncInfo->setForceFramePointer(true);
2435 MachineFrameInfo *MFI = MF.getFrameInfo();
2436 bool Is64Bit = Subtarget->is64Bit();
2437 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2439 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2440 "Var args not supported with calling convention fastcc, ghc or hipe");
2442 // Assign locations to all of the incoming arguments.
2443 SmallVector<CCValAssign, 16> ArgLocs;
2444 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2446 // Allocate shadow area for Win64
2448 CCInfo.AllocateStack(32, 8);
2450 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2452 unsigned LastVal = ~0U;
2454 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2455 CCValAssign &VA = ArgLocs[i];
2456 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2458 assert(VA.getValNo() != LastVal &&
2459 "Don't support value assigned to multiple locs yet");
2461 LastVal = VA.getValNo();
2463 if (VA.isRegLoc()) {
2464 EVT RegVT = VA.getLocVT();
2465 const TargetRegisterClass *RC;
2466 if (RegVT == MVT::i32)
2467 RC = &X86::GR32RegClass;
2468 else if (Is64Bit && RegVT == MVT::i64)
2469 RC = &X86::GR64RegClass;
2470 else if (RegVT == MVT::f32)
2471 RC = &X86::FR32RegClass;
2472 else if (RegVT == MVT::f64)
2473 RC = &X86::FR64RegClass;
2474 else if (RegVT.is512BitVector())
2475 RC = &X86::VR512RegClass;
2476 else if (RegVT.is256BitVector())
2477 RC = &X86::VR256RegClass;
2478 else if (RegVT.is128BitVector())
2479 RC = &X86::VR128RegClass;
2480 else if (RegVT == MVT::x86mmx)
2481 RC = &X86::VR64RegClass;
2482 else if (RegVT == MVT::i1)
2483 RC = &X86::VK1RegClass;
2484 else if (RegVT == MVT::v8i1)
2485 RC = &X86::VK8RegClass;
2486 else if (RegVT == MVT::v16i1)
2487 RC = &X86::VK16RegClass;
2488 else if (RegVT == MVT::v32i1)
2489 RC = &X86::VK32RegClass;
2490 else if (RegVT == MVT::v64i1)
2491 RC = &X86::VK64RegClass;
2493 llvm_unreachable("Unknown argument type!");
2495 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2496 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2498 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2499 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2501 if (VA.getLocInfo() == CCValAssign::SExt)
2502 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2503 DAG.getValueType(VA.getValVT()));
2504 else if (VA.getLocInfo() == CCValAssign::ZExt)
2505 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2506 DAG.getValueType(VA.getValVT()));
2507 else if (VA.getLocInfo() == CCValAssign::BCvt)
2508 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2510 if (VA.isExtInLoc()) {
2511 // Handle MMX values passed in XMM regs.
2512 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2513 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2515 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2518 assert(VA.isMemLoc());
2519 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2522 // If value is passed via pointer - do a load.
2523 if (VA.getLocInfo() == CCValAssign::Indirect)
2524 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2525 MachinePointerInfo(), false, false, false, 0);
2527 InVals.push_back(ArgValue);
2530 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2531 // All x86 ABIs require that for returning structs by value we copy the
2532 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2533 // the argument into a virtual register so that we can access it from the
2535 if (Ins[i].Flags.isSRet()) {
2536 unsigned Reg = FuncInfo->getSRetReturnReg();
2538 MVT PtrTy = getPointerTy(DAG.getDataLayout());
2539 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2540 FuncInfo->setSRetReturnReg(Reg);
2542 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2543 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2548 unsigned StackSize = CCInfo.getNextStackOffset();
2549 // Align stack specially for tail calls.
2550 if (FuncIsMadeTailCallSafe(CallConv,
2551 MF.getTarget().Options.GuaranteedTailCallOpt))
2552 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2554 // If the function takes variable number of arguments, make a frame index for
2555 // the start of the first vararg value... for expansion of llvm.va_start. We
2556 // can skip this if there are no va_start calls.
2557 if (MFI->hasVAStart() &&
2558 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2559 CallConv != CallingConv::X86_ThisCall))) {
2560 FuncInfo->setVarArgsFrameIndex(
2561 MFI->CreateFixedObject(1, StackSize, true));
2564 MachineModuleInfo &MMI = MF.getMMI();
2565 const Function *WinEHParent = nullptr;
2566 if (MMI.hasWinEHFuncInfo(Fn))
2567 WinEHParent = MMI.getWinEHParent(Fn);
2568 bool IsWinEHOutlined = WinEHParent && WinEHParent != Fn;
2569 bool IsWinEHParent = WinEHParent && WinEHParent == Fn;
2571 // Figure out if XMM registers are in use.
2572 assert(!(Subtarget->useSoftFloat() &&
2573 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2574 "SSE register cannot be used when SSE is disabled!");
2576 // 64-bit calling conventions support varargs and register parameters, so we
2577 // have to do extra work to spill them in the prologue.
2578 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2579 // Find the first unallocated argument registers.
2580 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2581 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2582 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2583 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2584 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2585 "SSE register cannot be used when SSE is disabled!");
2587 // Gather all the live in physical registers.
2588 SmallVector<SDValue, 6> LiveGPRs;
2589 SmallVector<SDValue, 8> LiveXMMRegs;
2591 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2592 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2594 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2596 if (!ArgXMMs.empty()) {
2597 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2598 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2599 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2600 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2601 LiveXMMRegs.push_back(
2602 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2607 // Get to the caller-allocated home save location. Add 8 to account
2608 // for the return address.
2609 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2610 FuncInfo->setRegSaveFrameIndex(
2611 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2612 // Fixup to set vararg frame on shadow area (4 x i64).
2614 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2616 // For X86-64, if there are vararg parameters that are passed via
2617 // registers, then we must store them to their spots on the stack so
2618 // they may be loaded by deferencing the result of va_next.
2619 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2620 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2621 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2622 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2625 // Store the integer parameter registers.
2626 SmallVector<SDValue, 8> MemOps;
2627 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2628 getPointerTy(DAG.getDataLayout()));
2629 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2630 for (SDValue Val : LiveGPRs) {
2631 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2632 RSFIN, DAG.getIntPtrConstant(Offset, dl));
2634 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2635 MachinePointerInfo::getFixedStack(
2636 FuncInfo->getRegSaveFrameIndex(), Offset),
2638 MemOps.push_back(Store);
2642 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2643 // Now store the XMM (fp + vector) parameter registers.
2644 SmallVector<SDValue, 12> SaveXMMOps;
2645 SaveXMMOps.push_back(Chain);
2646 SaveXMMOps.push_back(ALVal);
2647 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2648 FuncInfo->getRegSaveFrameIndex(), dl));
2649 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2650 FuncInfo->getVarArgsFPOffset(), dl));
2651 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2653 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2654 MVT::Other, SaveXMMOps));
2657 if (!MemOps.empty())
2658 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2659 } else if (IsWin64 && IsWinEHOutlined) {
2660 // Get to the caller-allocated home save location. Add 8 to account
2661 // for the return address.
2662 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2663 FuncInfo->setRegSaveFrameIndex(MFI->CreateFixedObject(
2664 /*Size=*/1, /*SPOffset=*/HomeOffset + 8, /*Immutable=*/false));
2666 MMI.getWinEHFuncInfo(Fn)
2667 .CatchHandlerParentFrameObjIdx[const_cast<Function *>(Fn)] =
2668 FuncInfo->getRegSaveFrameIndex();
2670 // Store the second integer parameter (rdx) into rsp+16 relative to the
2671 // stack pointer at the entry of the function.
2672 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2673 getPointerTy(DAG.getDataLayout()));
2674 unsigned GPR = MF.addLiveIn(X86::RDX, &X86::GR64RegClass);
2675 SDValue Val = DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64);
2676 Chain = DAG.getStore(
2677 Val.getValue(1), dl, Val, RSFIN,
2678 MachinePointerInfo::getFixedStack(FuncInfo->getRegSaveFrameIndex()),
2679 /*isVolatile=*/true, /*isNonTemporal=*/false, /*Alignment=*/0);
2682 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2683 // Find the largest legal vector type.
2684 MVT VecVT = MVT::Other;
2685 // FIXME: Only some x86_32 calling conventions support AVX512.
2686 if (Subtarget->hasAVX512() &&
2687 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2688 CallConv == CallingConv::Intel_OCL_BI)))
2689 VecVT = MVT::v16f32;
2690 else if (Subtarget->hasAVX())
2692 else if (Subtarget->hasSSE2())
2695 // We forward some GPRs and some vector types.
2696 SmallVector<MVT, 2> RegParmTypes;
2697 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2698 RegParmTypes.push_back(IntVT);
2699 if (VecVT != MVT::Other)
2700 RegParmTypes.push_back(VecVT);
2702 // Compute the set of forwarded registers. The rest are scratch.
2703 SmallVectorImpl<ForwardedRegister> &Forwards =
2704 FuncInfo->getForwardedMustTailRegParms();
2705 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2707 // Conservatively forward AL on x86_64, since it might be used for varargs.
2708 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2709 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2710 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2713 // Copy all forwards from physical to virtual registers.
2714 for (ForwardedRegister &F : Forwards) {
2715 // FIXME: Can we use a less constrained schedule?
2716 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2717 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2718 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2722 // Some CCs need callee pop.
2723 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2724 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2725 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2727 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2728 // If this is an sret function, the return should pop the hidden pointer.
2729 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2730 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2731 argsAreStructReturn(Ins) == StackStructReturn)
2732 FuncInfo->setBytesToPopOnReturn(4);
2736 // RegSaveFrameIndex is X86-64 only.
2737 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2738 if (CallConv == CallingConv::X86_FastCall ||
2739 CallConv == CallingConv::X86_ThisCall)
2740 // fastcc functions can't have varargs.
2741 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2744 FuncInfo->setArgumentStackSize(StackSize);
2746 if (IsWinEHParent) {
2748 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2749 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2750 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2751 SDValue Neg2 = DAG.getConstant(-2, dl, MVT::i64);
2752 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2753 MachinePointerInfo::getFixedStack(UnwindHelpFI),
2754 /*isVolatile=*/true,
2755 /*isNonTemporal=*/false, /*Alignment=*/0);
2757 // Functions using Win32 EH are considered to have opaque SP adjustments
2758 // to force local variables to be addressed from the frame or base
2760 MFI->setHasOpaqueSPAdjustment(true);
2768 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2769 SDValue StackPtr, SDValue Arg,
2770 SDLoc dl, SelectionDAG &DAG,
2771 const CCValAssign &VA,
2772 ISD::ArgFlagsTy Flags) const {
2773 unsigned LocMemOffset = VA.getLocMemOffset();
2774 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2775 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2777 if (Flags.isByVal())
2778 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2780 return DAG.getStore(Chain, dl, Arg, PtrOff,
2781 MachinePointerInfo::getStack(LocMemOffset),
2785 /// Emit a load of return address if tail call
2786 /// optimization is performed and it is required.
2788 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2789 SDValue &OutRetAddr, SDValue Chain,
2790 bool IsTailCall, bool Is64Bit,
2791 int FPDiff, SDLoc dl) const {
2792 // Adjust the Return address stack slot.
2793 EVT VT = getPointerTy(DAG.getDataLayout());
2794 OutRetAddr = getReturnAddressFrameIndex(DAG);
2796 // Load the "old" Return address.
2797 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2798 false, false, false, 0);
2799 return SDValue(OutRetAddr.getNode(), 1);
2802 /// Emit a store of the return address if tail call
2803 /// optimization is performed and it is required (FPDiff!=0).
2804 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2805 SDValue Chain, SDValue RetAddrFrIdx,
2806 EVT PtrVT, unsigned SlotSize,
2807 int FPDiff, SDLoc dl) {
2808 // Store the return address to the appropriate stack slot.
2809 if (!FPDiff) return Chain;
2810 // Calculate the new stack slot for the return address.
2811 int NewReturnAddrFI =
2812 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2814 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2815 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2816 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2822 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2823 SmallVectorImpl<SDValue> &InVals) const {
2824 SelectionDAG &DAG = CLI.DAG;
2826 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2827 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2828 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2829 SDValue Chain = CLI.Chain;
2830 SDValue Callee = CLI.Callee;
2831 CallingConv::ID CallConv = CLI.CallConv;
2832 bool &isTailCall = CLI.IsTailCall;
2833 bool isVarArg = CLI.IsVarArg;
2835 MachineFunction &MF = DAG.getMachineFunction();
2836 bool Is64Bit = Subtarget->is64Bit();
2837 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2838 StructReturnType SR = callIsStructReturn(Outs);
2839 bool IsSibcall = false;
2840 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2841 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
2843 if (Attr.getValueAsString() == "true")
2846 if (Subtarget->isPICStyleGOT() &&
2847 !MF.getTarget().Options.GuaranteedTailCallOpt) {
2848 // If we are using a GOT, disable tail calls to external symbols with
2849 // default visibility. Tail calling such a symbol requires using a GOT
2850 // relocation, which forces early binding of the symbol. This breaks code
2851 // that require lazy function symbol resolution. Using musttail or
2852 // GuaranteedTailCallOpt will override this.
2853 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2854 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
2855 G->getGlobal()->hasDefaultVisibility()))
2859 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2861 // Force this to be a tail call. The verifier rules are enough to ensure
2862 // that we can lower this successfully without moving the return address
2865 } else if (isTailCall) {
2866 // Check if it's really possible to do a tail call.
2867 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2868 isVarArg, SR != NotStructReturn,
2869 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2870 Outs, OutVals, Ins, DAG);
2872 // Sibcalls are automatically detected tailcalls which do not require
2874 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2881 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2882 "Var args not supported with calling convention fastcc, ghc or hipe");
2884 // Analyze operands of the call, assigning locations to each operand.
2885 SmallVector<CCValAssign, 16> ArgLocs;
2886 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2888 // Allocate shadow area for Win64
2890 CCInfo.AllocateStack(32, 8);
2892 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2894 // Get a count of how many bytes are to be pushed on the stack.
2895 unsigned NumBytes = CCInfo.getNextStackOffset();
2897 // This is a sibcall. The memory operands are available in caller's
2898 // own caller's stack.
2900 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2901 IsTailCallConvention(CallConv))
2902 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2905 if (isTailCall && !IsSibcall && !IsMustTail) {
2906 // Lower arguments at fp - stackoffset + fpdiff.
2907 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2909 FPDiff = NumBytesCallerPushed - NumBytes;
2911 // Set the delta of movement of the returnaddr stackslot.
2912 // But only set if delta is greater than previous delta.
2913 if (FPDiff < X86Info->getTCReturnAddrDelta())
2914 X86Info->setTCReturnAddrDelta(FPDiff);
2917 unsigned NumBytesToPush = NumBytes;
2918 unsigned NumBytesToPop = NumBytes;
2920 // If we have an inalloca argument, all stack space has already been allocated
2921 // for us and be right at the top of the stack. We don't support multiple
2922 // arguments passed in memory when using inalloca.
2923 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2925 if (!ArgLocs.back().isMemLoc())
2926 report_fatal_error("cannot use inalloca attribute on a register "
2928 if (ArgLocs.back().getLocMemOffset() != 0)
2929 report_fatal_error("any parameter with the inalloca attribute must be "
2930 "the only memory argument");
2934 Chain = DAG.getCALLSEQ_START(
2935 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
2937 SDValue RetAddrFrIdx;
2938 // Load return address for tail calls.
2939 if (isTailCall && FPDiff)
2940 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2941 Is64Bit, FPDiff, dl);
2943 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2944 SmallVector<SDValue, 8> MemOpChains;
2947 // Walk the register/memloc assignments, inserting copies/loads. In the case
2948 // of tail call optimization arguments are handle later.
2949 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
2950 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2951 // Skip inalloca arguments, they have already been written.
2952 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2953 if (Flags.isInAlloca())
2956 CCValAssign &VA = ArgLocs[i];
2957 EVT RegVT = VA.getLocVT();
2958 SDValue Arg = OutVals[i];
2959 bool isByVal = Flags.isByVal();
2961 // Promote the value if needed.
2962 switch (VA.getLocInfo()) {
2963 default: llvm_unreachable("Unknown loc info!");
2964 case CCValAssign::Full: break;
2965 case CCValAssign::SExt:
2966 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2968 case CCValAssign::ZExt:
2969 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2971 case CCValAssign::AExt:
2972 if (Arg.getValueType().isVector() &&
2973 Arg.getValueType().getScalarType() == MVT::i1)
2974 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2975 else if (RegVT.is128BitVector()) {
2976 // Special case: passing MMX values in XMM registers.
2977 Arg = DAG.getBitcast(MVT::i64, Arg);
2978 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2979 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2981 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2983 case CCValAssign::BCvt:
2984 Arg = DAG.getBitcast(RegVT, Arg);
2986 case CCValAssign::Indirect: {
2987 // Store the argument.
2988 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2989 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2990 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2991 MachinePointerInfo::getFixedStack(FI),
2998 if (VA.isRegLoc()) {
2999 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3000 if (isVarArg && IsWin64) {
3001 // Win64 ABI requires argument XMM reg to be copied to the corresponding
3002 // shadow reg if callee is a varargs function.
3003 unsigned ShadowReg = 0;
3004 switch (VA.getLocReg()) {
3005 case X86::XMM0: ShadowReg = X86::RCX; break;
3006 case X86::XMM1: ShadowReg = X86::RDX; break;
3007 case X86::XMM2: ShadowReg = X86::R8; break;
3008 case X86::XMM3: ShadowReg = X86::R9; break;
3011 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
3013 } else if (!IsSibcall && (!isTailCall || isByVal)) {
3014 assert(VA.isMemLoc());
3015 if (!StackPtr.getNode())
3016 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3017 getPointerTy(DAG.getDataLayout()));
3018 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3019 dl, DAG, VA, Flags));
3023 if (!MemOpChains.empty())
3024 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3026 if (Subtarget->isPICStyleGOT()) {
3027 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3030 RegsToPass.push_back(std::make_pair(
3031 unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
3032 getPointerTy(DAG.getDataLayout()))));
3034 // If we are tail calling and generating PIC/GOT style code load the
3035 // address of the callee into ECX. The value in ecx is used as target of
3036 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3037 // for tail calls on PIC/GOT architectures. Normally we would just put the
3038 // address of GOT into ebx and then call target@PLT. But for tail calls
3039 // ebx would be restored (since ebx is callee saved) before jumping to the
3042 // Note: The actual moving to ECX is done further down.
3043 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3044 if (G && !G->getGlobal()->hasLocalLinkage() &&
3045 G->getGlobal()->hasDefaultVisibility())
3046 Callee = LowerGlobalAddress(Callee, DAG);
3047 else if (isa<ExternalSymbolSDNode>(Callee))
3048 Callee = LowerExternalSymbol(Callee, DAG);
3052 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3053 // From AMD64 ABI document:
3054 // For calls that may call functions that use varargs or stdargs
3055 // (prototype-less calls or calls to functions containing ellipsis (...) in
3056 // the declaration) %al is used as hidden argument to specify the number
3057 // of SSE registers used. The contents of %al do not need to match exactly
3058 // the number of registers, but must be an ubound on the number of SSE
3059 // registers used and is in the range 0 - 8 inclusive.
3061 // Count the number of XMM registers allocated.
3062 static const MCPhysReg XMMArgRegs[] = {
3063 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3064 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3066 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3067 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3068 && "SSE registers cannot be used when SSE is disabled");
3070 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3071 DAG.getConstant(NumXMMRegs, dl,
3075 if (isVarArg && IsMustTail) {
3076 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3077 for (const auto &F : Forwards) {
3078 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3079 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3083 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3084 // don't need this because the eligibility check rejects calls that require
3085 // shuffling arguments passed in memory.
3086 if (!IsSibcall && isTailCall) {
3087 // Force all the incoming stack arguments to be loaded from the stack
3088 // before any new outgoing arguments are stored to the stack, because the
3089 // outgoing stack slots may alias the incoming argument stack slots, and
3090 // the alias isn't otherwise explicit. This is slightly more conservative
3091 // than necessary, because it means that each store effectively depends
3092 // on every argument instead of just those arguments it would clobber.
3093 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3095 SmallVector<SDValue, 8> MemOpChains2;
3098 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3099 CCValAssign &VA = ArgLocs[i];
3102 assert(VA.isMemLoc());
3103 SDValue Arg = OutVals[i];
3104 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3105 // Skip inalloca arguments. They don't require any work.
3106 if (Flags.isInAlloca())
3108 // Create frame index.
3109 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3110 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3111 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3112 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3114 if (Flags.isByVal()) {
3115 // Copy relative to framepointer.
3116 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3117 if (!StackPtr.getNode())
3118 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3119 getPointerTy(DAG.getDataLayout()));
3120 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3123 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3127 // Store relative to framepointer.
3128 MemOpChains2.push_back(
3129 DAG.getStore(ArgChain, dl, Arg, FIN,
3130 MachinePointerInfo::getFixedStack(FI),
3135 if (!MemOpChains2.empty())
3136 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3138 // Store the return address to the appropriate stack slot.
3139 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3140 getPointerTy(DAG.getDataLayout()),
3141 RegInfo->getSlotSize(), FPDiff, dl);
3144 // Build a sequence of copy-to-reg nodes chained together with token chain
3145 // and flag operands which copy the outgoing args into registers.
3147 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3148 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3149 RegsToPass[i].second, InFlag);
3150 InFlag = Chain.getValue(1);
3153 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3154 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3155 // In the 64-bit large code model, we have to make all calls
3156 // through a register, since the call instruction's 32-bit
3157 // pc-relative offset may not be large enough to hold the whole
3159 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3160 // If the callee is a GlobalAddress node (quite common, every direct call
3161 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3163 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3165 // We should use extra load for direct calls to dllimported functions in
3167 const GlobalValue *GV = G->getGlobal();
3168 if (!GV->hasDLLImportStorageClass()) {
3169 unsigned char OpFlags = 0;
3170 bool ExtraLoad = false;
3171 unsigned WrapperKind = ISD::DELETED_NODE;
3173 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3174 // external symbols most go through the PLT in PIC mode. If the symbol
3175 // has hidden or protected visibility, or if it is static or local, then
3176 // we don't need to use the PLT - we can directly call it.
3177 if (Subtarget->isTargetELF() &&
3178 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3179 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3180 OpFlags = X86II::MO_PLT;
3181 } else if (Subtarget->isPICStyleStubAny() &&
3182 !GV->isStrongDefinitionForLinker() &&
3183 (!Subtarget->getTargetTriple().isMacOSX() ||
3184 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3185 // PC-relative references to external symbols should go through $stub,
3186 // unless we're building with the leopard linker or later, which
3187 // automatically synthesizes these stubs.
3188 OpFlags = X86II::MO_DARWIN_STUB;
3189 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3190 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3191 // If the function is marked as non-lazy, generate an indirect call
3192 // which loads from the GOT directly. This avoids runtime overhead
3193 // at the cost of eager binding (and one extra byte of encoding).
3194 OpFlags = X86II::MO_GOTPCREL;
3195 WrapperKind = X86ISD::WrapperRIP;
3199 Callee = DAG.getTargetGlobalAddress(
3200 GV, dl, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
3202 // Add a wrapper if needed.
3203 if (WrapperKind != ISD::DELETED_NODE)
3204 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3205 getPointerTy(DAG.getDataLayout()), Callee);
3206 // Add extra indirection if needed.
3208 Callee = DAG.getLoad(
3209 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3210 MachinePointerInfo::getGOT(), false, false, false, 0);
3212 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3213 unsigned char OpFlags = 0;
3215 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3216 // external symbols should go through the PLT.
3217 if (Subtarget->isTargetELF() &&
3218 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3219 OpFlags = X86II::MO_PLT;
3220 } else if (Subtarget->isPICStyleStubAny() &&
3221 (!Subtarget->getTargetTriple().isMacOSX() ||
3222 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3223 // PC-relative references to external symbols should go through $stub,
3224 // unless we're building with the leopard linker or later, which
3225 // automatically synthesizes these stubs.
3226 OpFlags = X86II::MO_DARWIN_STUB;
3229 Callee = DAG.getTargetExternalSymbol(
3230 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
3231 } else if (Subtarget->isTarget64BitILP32() &&
3232 Callee->getValueType(0) == MVT::i32) {
3233 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3234 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3237 // Returns a chain & a flag for retval copy to use.
3238 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3239 SmallVector<SDValue, 8> Ops;
3241 if (!IsSibcall && isTailCall) {
3242 Chain = DAG.getCALLSEQ_END(Chain,
3243 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3244 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3245 InFlag = Chain.getValue(1);
3248 Ops.push_back(Chain);
3249 Ops.push_back(Callee);
3252 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3254 // Add argument registers to the end of the list so that they are known live
3256 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3257 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3258 RegsToPass[i].second.getValueType()));
3260 // Add a register mask operand representing the call-preserved registers.
3261 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
3262 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
3263 assert(Mask && "Missing call preserved mask for calling convention");
3264 Ops.push_back(DAG.getRegisterMask(Mask));
3266 if (InFlag.getNode())
3267 Ops.push_back(InFlag);
3271 //// If this is the first return lowered for this function, add the regs
3272 //// to the liveout set for the function.
3273 // This isn't right, although it's probably harmless on x86; liveouts
3274 // should be computed from returns not tail calls. Consider a void
3275 // function making a tail call to a function returning int.
3276 MF.getFrameInfo()->setHasTailCall();
3277 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3280 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3281 InFlag = Chain.getValue(1);
3283 // Create the CALLSEQ_END node.
3284 unsigned NumBytesForCalleeToPop;
3285 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3286 DAG.getTarget().Options.GuaranteedTailCallOpt))
3287 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3288 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3289 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3290 SR == StackStructReturn)
3291 // If this is a call to a struct-return function, the callee
3292 // pops the hidden struct pointer, so we have to push it back.
3293 // This is common for Darwin/X86, Linux & Mingw32 targets.
3294 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3295 NumBytesForCalleeToPop = 4;
3297 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3299 // Returns a flag for retval copy to use.
3301 Chain = DAG.getCALLSEQ_END(Chain,
3302 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3303 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3306 InFlag = Chain.getValue(1);
3309 // Handle result values, copying them out of physregs into vregs that we
3311 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3312 Ins, dl, DAG, InVals);
3315 //===----------------------------------------------------------------------===//
3316 // Fast Calling Convention (tail call) implementation
3317 //===----------------------------------------------------------------------===//
3319 // Like std call, callee cleans arguments, convention except that ECX is
3320 // reserved for storing the tail called function address. Only 2 registers are
3321 // free for argument passing (inreg). Tail call optimization is performed
3323 // * tailcallopt is enabled
3324 // * caller/callee are fastcc
3325 // On X86_64 architecture with GOT-style position independent code only local
3326 // (within module) calls are supported at the moment.
3327 // To keep the stack aligned according to platform abi the function
3328 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3329 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3330 // If a tail called function callee has more arguments than the caller the
3331 // caller needs to make sure that there is room to move the RETADDR to. This is
3332 // achieved by reserving an area the size of the argument delta right after the
3333 // original RETADDR, but before the saved framepointer or the spilled registers
3334 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3346 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3347 /// for a 16 byte align requirement.
3349 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3350 SelectionDAG& DAG) const {
3351 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3352 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3353 unsigned StackAlignment = TFI.getStackAlignment();
3354 uint64_t AlignMask = StackAlignment - 1;
3355 int64_t Offset = StackSize;
3356 unsigned SlotSize = RegInfo->getSlotSize();
3357 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3358 // Number smaller than 12 so just add the difference.
3359 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3361 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3362 Offset = ((~AlignMask) & Offset) + StackAlignment +
3363 (StackAlignment-SlotSize);
3368 /// MatchingStackOffset - Return true if the given stack call argument is
3369 /// already available in the same position (relatively) of the caller's
3370 /// incoming argument stack.
3372 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3373 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3374 const X86InstrInfo *TII) {
3375 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3377 if (Arg.getOpcode() == ISD::CopyFromReg) {
3378 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3379 if (!TargetRegisterInfo::isVirtualRegister(VR))
3381 MachineInstr *Def = MRI->getVRegDef(VR);
3384 if (!Flags.isByVal()) {
3385 if (!TII->isLoadFromStackSlot(Def, FI))
3388 unsigned Opcode = Def->getOpcode();
3389 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3390 Opcode == X86::LEA64_32r) &&
3391 Def->getOperand(1).isFI()) {
3392 FI = Def->getOperand(1).getIndex();
3393 Bytes = Flags.getByValSize();
3397 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3398 if (Flags.isByVal())
3399 // ByVal argument is passed in as a pointer but it's now being
3400 // dereferenced. e.g.
3401 // define @foo(%struct.X* %A) {
3402 // tail call @bar(%struct.X* byval %A)
3405 SDValue Ptr = Ld->getBasePtr();
3406 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3409 FI = FINode->getIndex();
3410 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3411 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3412 FI = FINode->getIndex();
3413 Bytes = Flags.getByValSize();
3417 assert(FI != INT_MAX);
3418 if (!MFI->isFixedObjectIndex(FI))
3420 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3423 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3424 /// for tail call optimization. Targets which want to do tail call
3425 /// optimization should implement this function.
3427 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3428 CallingConv::ID CalleeCC,
3430 bool isCalleeStructRet,
3431 bool isCallerStructRet,
3433 const SmallVectorImpl<ISD::OutputArg> &Outs,
3434 const SmallVectorImpl<SDValue> &OutVals,
3435 const SmallVectorImpl<ISD::InputArg> &Ins,
3436 SelectionDAG &DAG) const {
3437 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3440 // If -tailcallopt is specified, make fastcc functions tail-callable.
3441 const MachineFunction &MF = DAG.getMachineFunction();
3442 const Function *CallerF = MF.getFunction();
3444 // If the function return type is x86_fp80 and the callee return type is not,
3445 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3446 // perform a tailcall optimization here.
3447 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3450 CallingConv::ID CallerCC = CallerF->getCallingConv();
3451 bool CCMatch = CallerCC == CalleeCC;
3452 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3453 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3455 // Win64 functions have extra shadow space for argument homing. Don't do the
3456 // sibcall if the caller and callee have mismatched expectations for this
3458 if (IsCalleeWin64 != IsCallerWin64)
3461 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3462 if (IsTailCallConvention(CalleeCC) && CCMatch)
3467 // Look for obvious safe cases to perform tail call optimization that do not
3468 // require ABI changes. This is what gcc calls sibcall.
3470 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3471 // emit a special epilogue.
3472 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3473 if (RegInfo->needsStackRealignment(MF))
3476 // Also avoid sibcall optimization if either caller or callee uses struct
3477 // return semantics.
3478 if (isCalleeStructRet || isCallerStructRet)
3481 // An stdcall/thiscall caller is expected to clean up its arguments; the
3482 // callee isn't going to do that.
3483 // FIXME: this is more restrictive than needed. We could produce a tailcall
3484 // when the stack adjustment matches. For example, with a thiscall that takes
3485 // only one argument.
3486 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3487 CallerCC == CallingConv::X86_ThisCall))
3490 // Do not sibcall optimize vararg calls unless all arguments are passed via
3492 if (isVarArg && !Outs.empty()) {
3494 // Optimizing for varargs on Win64 is unlikely to be safe without
3495 // additional testing.
3496 if (IsCalleeWin64 || IsCallerWin64)
3499 SmallVector<CCValAssign, 16> ArgLocs;
3500 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3503 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3504 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3505 if (!ArgLocs[i].isRegLoc())
3509 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3510 // stack. Therefore, if it's not used by the call it is not safe to optimize
3511 // this into a sibcall.
3512 bool Unused = false;
3513 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3520 SmallVector<CCValAssign, 16> RVLocs;
3521 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3523 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3524 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3525 CCValAssign &VA = RVLocs[i];
3526 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3531 // If the calling conventions do not match, then we'd better make sure the
3532 // results are returned in the same way as what the caller expects.
3534 SmallVector<CCValAssign, 16> RVLocs1;
3535 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3537 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3539 SmallVector<CCValAssign, 16> RVLocs2;
3540 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3542 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3544 if (RVLocs1.size() != RVLocs2.size())
3546 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3547 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3549 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3551 if (RVLocs1[i].isRegLoc()) {
3552 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3555 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3561 // If the callee takes no arguments then go on to check the results of the
3563 if (!Outs.empty()) {
3564 // Check if stack adjustment is needed. For now, do not do this if any
3565 // argument is passed on the stack.
3566 SmallVector<CCValAssign, 16> ArgLocs;
3567 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3570 // Allocate shadow area for Win64
3572 CCInfo.AllocateStack(32, 8);
3574 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3575 if (CCInfo.getNextStackOffset()) {
3576 MachineFunction &MF = DAG.getMachineFunction();
3577 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3580 // Check if the arguments are already laid out in the right way as
3581 // the caller's fixed stack objects.
3582 MachineFrameInfo *MFI = MF.getFrameInfo();
3583 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3584 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3585 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3586 CCValAssign &VA = ArgLocs[i];
3587 SDValue Arg = OutVals[i];
3588 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3589 if (VA.getLocInfo() == CCValAssign::Indirect)
3591 if (!VA.isRegLoc()) {
3592 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3599 // If the tailcall address may be in a register, then make sure it's
3600 // possible to register allocate for it. In 32-bit, the call address can
3601 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3602 // callee-saved registers are restored. These happen to be the same
3603 // registers used to pass 'inreg' arguments so watch out for those.
3604 if (!Subtarget->is64Bit() &&
3605 ((!isa<GlobalAddressSDNode>(Callee) &&
3606 !isa<ExternalSymbolSDNode>(Callee)) ||
3607 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3608 unsigned NumInRegs = 0;
3609 // In PIC we need an extra register to formulate the address computation
3611 unsigned MaxInRegs =
3612 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3614 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3615 CCValAssign &VA = ArgLocs[i];
3618 unsigned Reg = VA.getLocReg();
3621 case X86::EAX: case X86::EDX: case X86::ECX:
3622 if (++NumInRegs == MaxInRegs)
3634 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3635 const TargetLibraryInfo *libInfo) const {
3636 return X86::createFastISel(funcInfo, libInfo);
3639 //===----------------------------------------------------------------------===//
3640 // Other Lowering Hooks
3641 //===----------------------------------------------------------------------===//
3643 static bool MayFoldLoad(SDValue Op) {
3644 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3647 static bool MayFoldIntoStore(SDValue Op) {
3648 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3651 static bool isTargetShuffle(unsigned Opcode) {
3653 default: return false;
3654 case X86ISD::BLENDI:
3655 case X86ISD::PSHUFB:
3656 case X86ISD::PSHUFD:
3657 case X86ISD::PSHUFHW:
3658 case X86ISD::PSHUFLW:
3660 case X86ISD::PALIGNR:
3661 case X86ISD::MOVLHPS:
3662 case X86ISD::MOVLHPD:
3663 case X86ISD::MOVHLPS:
3664 case X86ISD::MOVLPS:
3665 case X86ISD::MOVLPD:
3666 case X86ISD::MOVSHDUP:
3667 case X86ISD::MOVSLDUP:
3668 case X86ISD::MOVDDUP:
3671 case X86ISD::UNPCKL:
3672 case X86ISD::UNPCKH:
3673 case X86ISD::VPERMILPI:
3674 case X86ISD::VPERM2X128:
3675 case X86ISD::VPERMI:
3680 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3681 SDValue V1, unsigned TargetMask,
3682 SelectionDAG &DAG) {
3684 default: llvm_unreachable("Unknown x86 shuffle node");
3685 case X86ISD::PSHUFD:
3686 case X86ISD::PSHUFHW:
3687 case X86ISD::PSHUFLW:
3688 case X86ISD::VPERMILPI:
3689 case X86ISD::VPERMI:
3690 return DAG.getNode(Opc, dl, VT, V1,
3691 DAG.getConstant(TargetMask, dl, MVT::i8));
3695 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3696 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3698 default: llvm_unreachable("Unknown x86 shuffle node");
3699 case X86ISD::MOVLHPS:
3700 case X86ISD::MOVLHPD:
3701 case X86ISD::MOVHLPS:
3702 case X86ISD::MOVLPS:
3703 case X86ISD::MOVLPD:
3706 case X86ISD::UNPCKL:
3707 case X86ISD::UNPCKH:
3708 return DAG.getNode(Opc, dl, VT, V1, V2);
3712 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3713 MachineFunction &MF = DAG.getMachineFunction();
3714 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3715 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3716 int ReturnAddrIndex = FuncInfo->getRAIndex();
3718 if (ReturnAddrIndex == 0) {
3719 // Set up a frame object for the return address.
3720 unsigned SlotSize = RegInfo->getSlotSize();
3721 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3724 FuncInfo->setRAIndex(ReturnAddrIndex);
3727 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
3730 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3731 bool hasSymbolicDisplacement) {
3732 // Offset should fit into 32 bit immediate field.
3733 if (!isInt<32>(Offset))
3736 // If we don't have a symbolic displacement - we don't have any extra
3738 if (!hasSymbolicDisplacement)
3741 // FIXME: Some tweaks might be needed for medium code model.
3742 if (M != CodeModel::Small && M != CodeModel::Kernel)
3745 // For small code model we assume that latest object is 16MB before end of 31
3746 // bits boundary. We may also accept pretty large negative constants knowing
3747 // that all objects are in the positive half of address space.
3748 if (M == CodeModel::Small && Offset < 16*1024*1024)
3751 // For kernel code model we know that all object resist in the negative half
3752 // of 32bits address space. We may not accept negative offsets, since they may
3753 // be just off and we may accept pretty large positive ones.
3754 if (M == CodeModel::Kernel && Offset >= 0)
3760 /// isCalleePop - Determines whether the callee is required to pop its
3761 /// own arguments. Callee pop is necessary to support tail calls.
3762 bool X86::isCalleePop(CallingConv::ID CallingConv,
3763 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3764 switch (CallingConv) {
3767 case CallingConv::X86_StdCall:
3768 case CallingConv::X86_FastCall:
3769 case CallingConv::X86_ThisCall:
3771 case CallingConv::Fast:
3772 case CallingConv::GHC:
3773 case CallingConv::HiPE:
3780 /// \brief Return true if the condition is an unsigned comparison operation.
3781 static bool isX86CCUnsigned(unsigned X86CC) {
3783 default: llvm_unreachable("Invalid integer condition!");
3784 case X86::COND_E: return true;
3785 case X86::COND_G: return false;
3786 case X86::COND_GE: return false;
3787 case X86::COND_L: return false;
3788 case X86::COND_LE: return false;
3789 case X86::COND_NE: return true;
3790 case X86::COND_B: return true;
3791 case X86::COND_A: return true;
3792 case X86::COND_BE: return true;
3793 case X86::COND_AE: return true;
3795 llvm_unreachable("covered switch fell through?!");
3798 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3799 /// specific condition code, returning the condition code and the LHS/RHS of the
3800 /// comparison to make.
3801 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3802 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3804 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3805 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3806 // X > -1 -> X == 0, jump !sign.
3807 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3808 return X86::COND_NS;
3810 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3811 // X < 0 -> X == 0, jump on sign.
3814 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3816 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3817 return X86::COND_LE;
3821 switch (SetCCOpcode) {
3822 default: llvm_unreachable("Invalid integer condition!");
3823 case ISD::SETEQ: return X86::COND_E;
3824 case ISD::SETGT: return X86::COND_G;
3825 case ISD::SETGE: return X86::COND_GE;
3826 case ISD::SETLT: return X86::COND_L;
3827 case ISD::SETLE: return X86::COND_LE;
3828 case ISD::SETNE: return X86::COND_NE;
3829 case ISD::SETULT: return X86::COND_B;
3830 case ISD::SETUGT: return X86::COND_A;
3831 case ISD::SETULE: return X86::COND_BE;
3832 case ISD::SETUGE: return X86::COND_AE;
3836 // First determine if it is required or is profitable to flip the operands.
3838 // If LHS is a foldable load, but RHS is not, flip the condition.
3839 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3840 !ISD::isNON_EXTLoad(RHS.getNode())) {
3841 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3842 std::swap(LHS, RHS);
3845 switch (SetCCOpcode) {
3851 std::swap(LHS, RHS);
3855 // On a floating point condition, the flags are set as follows:
3857 // 0 | 0 | 0 | X > Y
3858 // 0 | 0 | 1 | X < Y
3859 // 1 | 0 | 0 | X == Y
3860 // 1 | 1 | 1 | unordered
3861 switch (SetCCOpcode) {
3862 default: llvm_unreachable("Condcode should be pre-legalized away");
3864 case ISD::SETEQ: return X86::COND_E;
3865 case ISD::SETOLT: // flipped
3867 case ISD::SETGT: return X86::COND_A;
3868 case ISD::SETOLE: // flipped
3870 case ISD::SETGE: return X86::COND_AE;
3871 case ISD::SETUGT: // flipped
3873 case ISD::SETLT: return X86::COND_B;
3874 case ISD::SETUGE: // flipped
3876 case ISD::SETLE: return X86::COND_BE;
3878 case ISD::SETNE: return X86::COND_NE;
3879 case ISD::SETUO: return X86::COND_P;
3880 case ISD::SETO: return X86::COND_NP;
3882 case ISD::SETUNE: return X86::COND_INVALID;
3886 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3887 /// code. Current x86 isa includes the following FP cmov instructions:
3888 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3889 static bool hasFPCMov(unsigned X86CC) {
3905 /// isFPImmLegal - Returns true if the target can instruction select the
3906 /// specified FP immediate natively. If false, the legalizer will
3907 /// materialize the FP immediate as a load from a constant pool.
3908 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3909 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3910 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3916 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
3917 ISD::LoadExtType ExtTy,
3919 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
3920 // relocation target a movq or addq instruction: don't let the load shrink.
3921 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
3922 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
3923 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
3924 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
3928 /// \brief Returns true if it is beneficial to convert a load of a constant
3929 /// to just the constant itself.
3930 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3932 assert(Ty->isIntegerTy());
3934 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3935 if (BitSize == 0 || BitSize > 64)
3940 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
3941 unsigned Index) const {
3942 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
3945 return (Index == 0 || Index == ResVT.getVectorNumElements());
3948 bool X86TargetLowering::isCheapToSpeculateCttz() const {
3949 // Speculate cttz only if we can directly use TZCNT.
3950 return Subtarget->hasBMI();
3953 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
3954 // Speculate ctlz only if we can directly use LZCNT.
3955 return Subtarget->hasLZCNT();
3958 /// isUndefInRange - Return true if every element in Mask, beginning
3959 /// from position Pos and ending in Pos+Size is undef.
3960 static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
3961 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
3967 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3968 /// the specified range (L, H].
3969 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3970 return (Val < 0) || (Val >= Low && Val < Hi);
3973 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3974 /// specified value.
3975 static bool isUndefOrEqual(int Val, int CmpVal) {
3976 return (Val < 0 || Val == CmpVal);
3979 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3980 /// from position Pos and ending in Pos+Size, falls within the specified
3981 /// sequential range (Low, Low+Size]. or is undef.
3982 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3983 unsigned Pos, unsigned Size, int Low) {
3984 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3985 if (!isUndefOrEqual(Mask[i], Low))
3990 /// isVEXTRACTIndex - Return true if the specified
3991 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3992 /// suitable for instruction that extract 128 or 256 bit vectors
3993 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
3994 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3995 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3998 // The index should be aligned on a vecWidth-bit boundary.
4000 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4002 MVT VT = N->getSimpleValueType(0);
4003 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4004 bool Result = (Index * ElSize) % vecWidth == 0;
4009 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4010 /// operand specifies a subvector insert that is suitable for input to
4011 /// insertion of 128 or 256-bit subvectors
4012 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4013 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4014 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4016 // The index should be aligned on a vecWidth-bit boundary.
4018 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4020 MVT VT = N->getSimpleValueType(0);
4021 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4022 bool Result = (Index * ElSize) % vecWidth == 0;
4027 bool X86::isVINSERT128Index(SDNode *N) {
4028 return isVINSERTIndex(N, 128);
4031 bool X86::isVINSERT256Index(SDNode *N) {
4032 return isVINSERTIndex(N, 256);
4035 bool X86::isVEXTRACT128Index(SDNode *N) {
4036 return isVEXTRACTIndex(N, 128);
4039 bool X86::isVEXTRACT256Index(SDNode *N) {
4040 return isVEXTRACTIndex(N, 256);
4043 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4044 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4045 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4046 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4049 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4051 MVT VecVT = N->getOperand(0).getSimpleValueType();
4052 MVT ElVT = VecVT.getVectorElementType();
4054 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4055 return Index / NumElemsPerChunk;
4058 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4059 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4060 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4061 llvm_unreachable("Illegal insert subvector for VINSERT");
4064 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4066 MVT VecVT = N->getSimpleValueType(0);
4067 MVT ElVT = VecVT.getVectorElementType();
4069 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4070 return Index / NumElemsPerChunk;
4073 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4074 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4075 /// and VINSERTI128 instructions.
4076 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4077 return getExtractVEXTRACTImmediate(N, 128);
4080 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4081 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4082 /// and VINSERTI64x4 instructions.
4083 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4084 return getExtractVEXTRACTImmediate(N, 256);
4087 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4088 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4089 /// and VINSERTI128 instructions.
4090 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4091 return getInsertVINSERTImmediate(N, 128);
4094 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4095 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4096 /// and VINSERTI64x4 instructions.
4097 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4098 return getInsertVINSERTImmediate(N, 256);
4101 /// isZero - Returns true if Elt is a constant integer zero
4102 static bool isZero(SDValue V) {
4103 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4104 return C && C->isNullValue();
4107 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4109 bool X86::isZeroNode(SDValue Elt) {
4112 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4113 return CFP->getValueAPF().isPosZero();
4117 /// getZeroVector - Returns a vector of specified type with all zero elements.
4119 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4120 SelectionDAG &DAG, SDLoc dl) {
4121 assert(VT.isVector() && "Expected a vector type");
4123 // Always build SSE zero vectors as <4 x i32> bitcasted
4124 // to their dest type. This ensures they get CSE'd.
4126 if (VT.is128BitVector()) { // SSE
4127 if (Subtarget->hasSSE2()) { // SSE2
4128 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4129 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4131 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4132 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4134 } else if (VT.is256BitVector()) { // AVX
4135 if (Subtarget->hasInt256()) { // AVX2
4136 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4137 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4138 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4140 // 256-bit logic and arithmetic instructions in AVX are all
4141 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4142 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4143 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4144 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4146 } else if (VT.is512BitVector()) { // AVX-512
4147 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4148 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4149 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4150 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4151 } else if (VT.getScalarType() == MVT::i1) {
4153 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4154 && "Unexpected vector type");
4155 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4156 && "Unexpected vector type");
4157 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4158 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4159 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4161 llvm_unreachable("Unexpected vector type");
4163 return DAG.getBitcast(VT, Vec);
4166 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4167 SelectionDAG &DAG, SDLoc dl,
4168 unsigned vectorWidth) {
4169 assert((vectorWidth == 128 || vectorWidth == 256) &&
4170 "Unsupported vector width");
4171 EVT VT = Vec.getValueType();
4172 EVT ElVT = VT.getVectorElementType();
4173 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4174 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4175 VT.getVectorNumElements()/Factor);
4177 // Extract from UNDEF is UNDEF.
4178 if (Vec.getOpcode() == ISD::UNDEF)
4179 return DAG.getUNDEF(ResultVT);
4181 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4182 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4184 // This is the index of the first element of the vectorWidth-bit chunk
4186 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
4189 // If the input is a buildvector just emit a smaller one.
4190 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4191 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4192 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
4195 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4196 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4199 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4200 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4201 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4202 /// instructions or a simple subregister reference. Idx is an index in the
4203 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4204 /// lowering EXTRACT_VECTOR_ELT operations easier.
4205 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4206 SelectionDAG &DAG, SDLoc dl) {
4207 assert((Vec.getValueType().is256BitVector() ||
4208 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4209 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4212 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4213 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4214 SelectionDAG &DAG, SDLoc dl) {
4215 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4216 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4219 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4220 unsigned IdxVal, SelectionDAG &DAG,
4221 SDLoc dl, unsigned vectorWidth) {
4222 assert((vectorWidth == 128 || vectorWidth == 256) &&
4223 "Unsupported vector width");
4224 // Inserting UNDEF is Result
4225 if (Vec.getOpcode() == ISD::UNDEF)
4227 EVT VT = Vec.getValueType();
4228 EVT ElVT = VT.getVectorElementType();
4229 EVT ResultVT = Result.getValueType();
4231 // Insert the relevant vectorWidth bits.
4232 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4234 // This is the index of the first element of the vectorWidth-bit chunk
4236 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
4239 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4240 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4243 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4244 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4245 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4246 /// simple superregister reference. Idx is an index in the 128 bits
4247 /// we want. It need not be aligned to a 128-bit boundary. That makes
4248 /// lowering INSERT_VECTOR_ELT operations easier.
4249 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4250 SelectionDAG &DAG, SDLoc dl) {
4251 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4253 // For insertion into the zero index (low half) of a 256-bit vector, it is
4254 // more efficient to generate a blend with immediate instead of an insert*128.
4255 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4256 // extend the subvector to the size of the result vector. Make sure that
4257 // we are not recursing on that node by checking for undef here.
4258 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4259 Result.getOpcode() != ISD::UNDEF) {
4260 EVT ResultVT = Result.getValueType();
4261 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4262 SDValue Undef = DAG.getUNDEF(ResultVT);
4263 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4266 // The blend instruction, and therefore its mask, depend on the data type.
4267 MVT ScalarType = ResultVT.getScalarType().getSimpleVT();
4268 if (ScalarType.isFloatingPoint()) {
4269 // Choose either vblendps (float) or vblendpd (double).
4270 unsigned ScalarSize = ScalarType.getSizeInBits();
4271 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4272 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4273 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4274 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4277 const X86Subtarget &Subtarget =
4278 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4280 // AVX2 is needed for 256-bit integer blend support.
4281 // Integers must be cast to 32-bit because there is only vpblendd;
4282 // vpblendw can't be used for this because it has a handicapped mask.
4284 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4285 // is still more efficient than using the wrong domain vinsertf128 that
4286 // will be created by InsertSubVector().
4287 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4289 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4290 Vec256 = DAG.getBitcast(CastVT, Vec256);
4291 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4292 return DAG.getBitcast(ResultVT, Vec256);
4295 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4298 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4299 SelectionDAG &DAG, SDLoc dl) {
4300 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4301 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4304 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4305 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4306 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4307 /// large BUILD_VECTORS.
4308 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4309 unsigned NumElems, SelectionDAG &DAG,
4311 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4312 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4315 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4316 unsigned NumElems, SelectionDAG &DAG,
4318 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4319 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4322 /// getOnesVector - Returns a vector of specified type with all bits set.
4323 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4324 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4325 /// Then bitcast to their original type, ensuring they get CSE'd.
4326 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4328 assert(VT.isVector() && "Expected a vector type");
4330 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4332 if (VT.is256BitVector()) {
4333 if (HasInt256) { // AVX2
4334 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4335 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4337 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4338 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4340 } else if (VT.is128BitVector()) {
4341 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4343 llvm_unreachable("Unexpected vector type");
4345 return DAG.getBitcast(VT, Vec);
4348 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4349 /// operation of specified width.
4350 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4352 unsigned NumElems = VT.getVectorNumElements();
4353 SmallVector<int, 8> Mask;
4354 Mask.push_back(NumElems);
4355 for (unsigned i = 1; i != NumElems; ++i)
4357 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4360 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4361 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4363 unsigned NumElems = VT.getVectorNumElements();
4364 SmallVector<int, 8> Mask;
4365 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4367 Mask.push_back(i + NumElems);
4369 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4372 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4373 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4375 unsigned NumElems = VT.getVectorNumElements();
4376 SmallVector<int, 8> Mask;
4377 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4378 Mask.push_back(i + Half);
4379 Mask.push_back(i + NumElems + Half);
4381 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4384 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4385 /// vector of zero or undef vector. This produces a shuffle where the low
4386 /// element of V2 is swizzled into the zero/undef vector, landing at element
4387 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4388 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4390 const X86Subtarget *Subtarget,
4391 SelectionDAG &DAG) {
4392 MVT VT = V2.getSimpleValueType();
4394 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4395 unsigned NumElems = VT.getVectorNumElements();
4396 SmallVector<int, 16> MaskVec;
4397 for (unsigned i = 0; i != NumElems; ++i)
4398 // If this is the insertion idx, put the low elt of V2 here.
4399 MaskVec.push_back(i == Idx ? NumElems : i);
4400 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4403 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4404 /// target specific opcode. Returns true if the Mask could be calculated. Sets
4405 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
4406 /// shuffles which use a single input multiple times, and in those cases it will
4407 /// adjust the mask to only have indices within that single input.
4408 /// FIXME: Add support for Decode*Mask functions that return SM_SentinelZero.
4409 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4410 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4411 unsigned NumElems = VT.getVectorNumElements();
4415 bool IsFakeUnary = false;
4416 switch(N->getOpcode()) {
4417 case X86ISD::BLENDI:
4418 ImmN = N->getOperand(N->getNumOperands()-1);
4419 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4422 ImmN = N->getOperand(N->getNumOperands()-1);
4423 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4424 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4426 case X86ISD::UNPCKH:
4427 DecodeUNPCKHMask(VT, Mask);
4428 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4430 case X86ISD::UNPCKL:
4431 DecodeUNPCKLMask(VT, Mask);
4432 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4434 case X86ISD::MOVHLPS:
4435 DecodeMOVHLPSMask(NumElems, Mask);
4436 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4438 case X86ISD::MOVLHPS:
4439 DecodeMOVLHPSMask(NumElems, Mask);
4440 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4442 case X86ISD::PALIGNR:
4443 ImmN = N->getOperand(N->getNumOperands()-1);
4444 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4446 case X86ISD::PSHUFD:
4447 case X86ISD::VPERMILPI:
4448 ImmN = N->getOperand(N->getNumOperands()-1);
4449 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4452 case X86ISD::PSHUFHW:
4453 ImmN = N->getOperand(N->getNumOperands()-1);
4454 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4457 case X86ISD::PSHUFLW:
4458 ImmN = N->getOperand(N->getNumOperands()-1);
4459 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4462 case X86ISD::PSHUFB: {
4464 SDValue MaskNode = N->getOperand(1);
4465 while (MaskNode->getOpcode() == ISD::BITCAST)
4466 MaskNode = MaskNode->getOperand(0);
4468 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4469 // If we have a build-vector, then things are easy.
4470 EVT VT = MaskNode.getValueType();
4471 assert(VT.isVector() &&
4472 "Can't produce a non-vector with a build_vector!");
4473 if (!VT.isInteger())
4476 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4478 SmallVector<uint64_t, 32> RawMask;
4479 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4480 SDValue Op = MaskNode->getOperand(i);
4481 if (Op->getOpcode() == ISD::UNDEF) {
4482 RawMask.push_back((uint64_t)SM_SentinelUndef);
4485 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4488 APInt MaskElement = CN->getAPIntValue();
4490 // We now have to decode the element which could be any integer size and
4491 // extract each byte of it.
4492 for (int j = 0; j < NumBytesPerElement; ++j) {
4493 // Note that this is x86 and so always little endian: the low byte is
4494 // the first byte of the mask.
4495 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4496 MaskElement = MaskElement.lshr(8);
4499 DecodePSHUFBMask(RawMask, Mask);
4503 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4507 SDValue Ptr = MaskLoad->getBasePtr();
4508 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4509 Ptr->getOpcode() == X86ISD::WrapperRIP)
4510 Ptr = Ptr->getOperand(0);
4512 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4513 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4516 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4517 DecodePSHUFBMask(C, Mask);
4525 case X86ISD::VPERMI:
4526 ImmN = N->getOperand(N->getNumOperands()-1);
4527 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4532 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4534 case X86ISD::VPERM2X128:
4535 ImmN = N->getOperand(N->getNumOperands()-1);
4536 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4537 if (Mask.empty()) return false;
4538 // Mask only contains negative index if an element is zero.
4539 if (std::any_of(Mask.begin(), Mask.end(),
4540 [](int M){ return M == SM_SentinelZero; }))
4543 case X86ISD::MOVSLDUP:
4544 DecodeMOVSLDUPMask(VT, Mask);
4547 case X86ISD::MOVSHDUP:
4548 DecodeMOVSHDUPMask(VT, Mask);
4551 case X86ISD::MOVDDUP:
4552 DecodeMOVDDUPMask(VT, Mask);
4555 case X86ISD::MOVLHPD:
4556 case X86ISD::MOVLPD:
4557 case X86ISD::MOVLPS:
4558 // Not yet implemented
4560 default: llvm_unreachable("unknown target shuffle node");
4563 // If we have a fake unary shuffle, the shuffle mask is spread across two
4564 // inputs that are actually the same node. Re-map the mask to always point
4565 // into the first input.
4568 if (M >= (int)Mask.size())
4574 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4575 /// element of the result of the vector shuffle.
4576 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4579 return SDValue(); // Limit search depth.
4581 SDValue V = SDValue(N, 0);
4582 EVT VT = V.getValueType();
4583 unsigned Opcode = V.getOpcode();
4585 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4586 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4587 int Elt = SV->getMaskElt(Index);
4590 return DAG.getUNDEF(VT.getVectorElementType());
4592 unsigned NumElems = VT.getVectorNumElements();
4593 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4594 : SV->getOperand(1);
4595 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4598 // Recurse into target specific vector shuffles to find scalars.
4599 if (isTargetShuffle(Opcode)) {
4600 MVT ShufVT = V.getSimpleValueType();
4601 unsigned NumElems = ShufVT.getVectorNumElements();
4602 SmallVector<int, 16> ShuffleMask;
4605 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4608 int Elt = ShuffleMask[Index];
4610 return DAG.getUNDEF(ShufVT.getVectorElementType());
4612 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4614 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4618 // Actual nodes that may contain scalar elements
4619 if (Opcode == ISD::BITCAST) {
4620 V = V.getOperand(0);
4621 EVT SrcVT = V.getValueType();
4622 unsigned NumElems = VT.getVectorNumElements();
4624 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4628 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4629 return (Index == 0) ? V.getOperand(0)
4630 : DAG.getUNDEF(VT.getVectorElementType());
4632 if (V.getOpcode() == ISD::BUILD_VECTOR)
4633 return V.getOperand(Index);
4638 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4640 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4641 unsigned NumNonZero, unsigned NumZero,
4643 const X86Subtarget* Subtarget,
4644 const TargetLowering &TLI) {
4652 // SSE4.1 - use PINSRB to insert each byte directly.
4653 if (Subtarget->hasSSE41()) {
4654 for (unsigned i = 0; i < 16; ++i) {
4655 bool isNonZero = (NonZeros & (1 << i)) != 0;
4659 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4661 V = DAG.getUNDEF(MVT::v16i8);
4664 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4665 MVT::v16i8, V, Op.getOperand(i),
4666 DAG.getIntPtrConstant(i, dl));
4673 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4674 for (unsigned i = 0; i < 16; ++i) {
4675 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4676 if (ThisIsNonZero && First) {
4678 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4680 V = DAG.getUNDEF(MVT::v8i16);
4685 SDValue ThisElt, LastElt;
4686 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4687 if (LastIsNonZero) {
4688 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4689 MVT::i16, Op.getOperand(i-1));
4691 if (ThisIsNonZero) {
4692 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4693 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4694 ThisElt, DAG.getConstant(8, dl, MVT::i8));
4696 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4700 if (ThisElt.getNode())
4701 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4702 DAG.getIntPtrConstant(i/2, dl));
4706 return DAG.getBitcast(MVT::v16i8, V);
4709 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4711 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4712 unsigned NumNonZero, unsigned NumZero,
4714 const X86Subtarget* Subtarget,
4715 const TargetLowering &TLI) {
4722 for (unsigned i = 0; i < 8; ++i) {
4723 bool isNonZero = (NonZeros & (1 << i)) != 0;
4727 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4729 V = DAG.getUNDEF(MVT::v8i16);
4732 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4733 MVT::v8i16, V, Op.getOperand(i),
4734 DAG.getIntPtrConstant(i, dl));
4741 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
4742 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
4743 const X86Subtarget *Subtarget,
4744 const TargetLowering &TLI) {
4745 // Find all zeroable elements.
4746 std::bitset<4> Zeroable;
4747 for (int i=0; i < 4; ++i) {
4748 SDValue Elt = Op->getOperand(i);
4749 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
4751 assert(Zeroable.size() - Zeroable.count() > 1 &&
4752 "We expect at least two non-zero elements!");
4754 // We only know how to deal with build_vector nodes where elements are either
4755 // zeroable or extract_vector_elt with constant index.
4756 SDValue FirstNonZero;
4757 unsigned FirstNonZeroIdx;
4758 for (unsigned i=0; i < 4; ++i) {
4761 SDValue Elt = Op->getOperand(i);
4762 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4763 !isa<ConstantSDNode>(Elt.getOperand(1)))
4765 // Make sure that this node is extracting from a 128-bit vector.
4766 MVT VT = Elt.getOperand(0).getSimpleValueType();
4767 if (!VT.is128BitVector())
4769 if (!FirstNonZero.getNode()) {
4771 FirstNonZeroIdx = i;
4775 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
4776 SDValue V1 = FirstNonZero.getOperand(0);
4777 MVT VT = V1.getSimpleValueType();
4779 // See if this build_vector can be lowered as a blend with zero.
4781 unsigned EltMaskIdx, EltIdx;
4783 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
4784 if (Zeroable[EltIdx]) {
4785 // The zero vector will be on the right hand side.
4786 Mask[EltIdx] = EltIdx+4;
4790 Elt = Op->getOperand(EltIdx);
4791 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
4792 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
4793 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
4795 Mask[EltIdx] = EltIdx;
4799 // Let the shuffle legalizer deal with blend operations.
4800 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
4801 if (V1.getSimpleValueType() != VT)
4802 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
4803 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
4806 // See if we can lower this build_vector to a INSERTPS.
4807 if (!Subtarget->hasSSE41())
4810 SDValue V2 = Elt.getOperand(0);
4811 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
4814 bool CanFold = true;
4815 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
4819 SDValue Current = Op->getOperand(i);
4820 SDValue SrcVector = Current->getOperand(0);
4823 CanFold = SrcVector == V1 &&
4824 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
4830 assert(V1.getNode() && "Expected at least two non-zero elements!");
4831 if (V1.getSimpleValueType() != MVT::v4f32)
4832 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
4833 if (V2.getSimpleValueType() != MVT::v4f32)
4834 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
4836 // Ok, we can emit an INSERTPS instruction.
4837 unsigned ZMask = Zeroable.to_ulong();
4839 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
4840 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
4842 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
4843 DAG.getIntPtrConstant(InsertPSMask, DL));
4844 return DAG.getBitcast(VT, Result);
4847 /// Return a vector logical shift node.
4848 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4849 unsigned NumBits, SelectionDAG &DAG,
4850 const TargetLowering &TLI, SDLoc dl) {
4851 assert(VT.is128BitVector() && "Unknown type for VShift");
4852 MVT ShVT = MVT::v2i64;
4853 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4854 SrcOp = DAG.getBitcast(ShVT, SrcOp);
4855 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(DAG.getDataLayout());
4856 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
4857 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
4858 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
4862 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
4864 // Check if the scalar load can be widened into a vector load. And if
4865 // the address is "base + cst" see if the cst can be "absorbed" into
4866 // the shuffle mask.
4867 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4868 SDValue Ptr = LD->getBasePtr();
4869 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4871 EVT PVT = LD->getValueType(0);
4872 if (PVT != MVT::i32 && PVT != MVT::f32)
4877 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4878 FI = FINode->getIndex();
4880 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4881 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4882 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4883 Offset = Ptr.getConstantOperandVal(1);
4884 Ptr = Ptr.getOperand(0);
4889 // FIXME: 256-bit vector instructions don't require a strict alignment,
4890 // improve this code to support it better.
4891 unsigned RequiredAlign = VT.getSizeInBits()/8;
4892 SDValue Chain = LD->getChain();
4893 // Make sure the stack object alignment is at least 16 or 32.
4894 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4895 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4896 if (MFI->isFixedObjectIndex(FI)) {
4897 // Can't change the alignment. FIXME: It's possible to compute
4898 // the exact stack offset and reference FI + adjust offset instead.
4899 // If someone *really* cares about this. That's the way to implement it.
4902 MFI->setObjectAlignment(FI, RequiredAlign);
4906 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4907 // Ptr + (Offset & ~15).
4910 if ((Offset % RequiredAlign) & 3)
4912 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4915 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
4916 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
4919 int EltNo = (Offset - StartOffset) >> 2;
4920 unsigned NumElems = VT.getVectorNumElements();
4922 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4923 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4924 LD->getPointerInfo().getWithOffset(StartOffset),
4925 false, false, false, 0);
4927 SmallVector<int, 8> Mask(NumElems, EltNo);
4929 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4935 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
4936 /// elements can be replaced by a single large load which has the same value as
4937 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
4939 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4941 /// FIXME: we'd also like to handle the case where the last elements are zero
4942 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4943 /// There's even a handy isZeroNode for that purpose.
4944 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
4945 SDLoc &DL, SelectionDAG &DAG,
4946 bool isAfterLegalize) {
4947 unsigned NumElems = Elts.size();
4949 LoadSDNode *LDBase = nullptr;
4950 unsigned LastLoadedElt = -1U;
4952 // For each element in the initializer, see if we've found a load or an undef.
4953 // If we don't find an initial load element, or later load elements are
4954 // non-consecutive, bail out.
4955 for (unsigned i = 0; i < NumElems; ++i) {
4956 SDValue Elt = Elts[i];
4957 // Look through a bitcast.
4958 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
4959 Elt = Elt.getOperand(0);
4960 if (!Elt.getNode() ||
4961 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4964 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4966 LDBase = cast<LoadSDNode>(Elt.getNode());
4970 if (Elt.getOpcode() == ISD::UNDEF)
4973 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4974 EVT LdVT = Elt.getValueType();
4975 // Each loaded element must be the correct fractional portion of the
4976 // requested vector load.
4977 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
4979 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
4984 // If we have found an entire vector of loads and undefs, then return a large
4985 // load of the entire vector width starting at the base pointer. If we found
4986 // consecutive loads for the low half, generate a vzext_load node.
4987 if (LastLoadedElt == NumElems - 1) {
4988 assert(LDBase && "Did not find base load for merging consecutive loads");
4989 EVT EltVT = LDBase->getValueType(0);
4990 // Ensure that the input vector size for the merged loads matches the
4991 // cumulative size of the input elements.
4992 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
4995 if (isAfterLegalize &&
4996 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
4999 SDValue NewLd = SDValue();
5001 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5002 LDBase->getPointerInfo(), LDBase->isVolatile(),
5003 LDBase->isNonTemporal(), LDBase->isInvariant(),
5004 LDBase->getAlignment());
5006 if (LDBase->hasAnyUseOfValue(1)) {
5007 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5009 SDValue(NewLd.getNode(), 1));
5010 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5011 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5012 SDValue(NewLd.getNode(), 1));
5018 //TODO: The code below fires only for for loading the low v2i32 / v2f32
5019 //of a v4i32 / v4f32. It's probably worth generalizing.
5020 EVT EltVT = VT.getVectorElementType();
5021 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
5022 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5023 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5024 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5026 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5027 LDBase->getPointerInfo(),
5028 LDBase->getAlignment(),
5029 false/*isVolatile*/, true/*ReadMem*/,
5032 // Make sure the newly-created LOAD is in the same position as LDBase in
5033 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5034 // update uses of LDBase's output chain to use the TokenFactor.
5035 if (LDBase->hasAnyUseOfValue(1)) {
5036 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5037 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5038 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5039 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5040 SDValue(ResNode.getNode(), 1));
5043 return DAG.getBitcast(VT, ResNode);
5048 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5049 /// to generate a splat value for the following cases:
5050 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5051 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5052 /// a scalar load, or a constant.
5053 /// The VBROADCAST node is returned when a pattern is found,
5054 /// or SDValue() otherwise.
5055 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5056 SelectionDAG &DAG) {
5057 // VBROADCAST requires AVX.
5058 // TODO: Splats could be generated for non-AVX CPUs using SSE
5059 // instructions, but there's less potential gain for only 128-bit vectors.
5060 if (!Subtarget->hasAVX())
5063 MVT VT = Op.getSimpleValueType();
5066 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5067 "Unsupported vector type for broadcast.");
5072 switch (Op.getOpcode()) {
5074 // Unknown pattern found.
5077 case ISD::BUILD_VECTOR: {
5078 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5079 BitVector UndefElements;
5080 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5082 // We need a splat of a single value to use broadcast, and it doesn't
5083 // make any sense if the value is only in one element of the vector.
5084 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5088 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5089 Ld.getOpcode() == ISD::ConstantFP);
5091 // Make sure that all of the users of a non-constant load are from the
5092 // BUILD_VECTOR node.
5093 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5098 case ISD::VECTOR_SHUFFLE: {
5099 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5101 // Shuffles must have a splat mask where the first element is
5103 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5106 SDValue Sc = Op.getOperand(0);
5107 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5108 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5110 if (!Subtarget->hasInt256())
5113 // Use the register form of the broadcast instruction available on AVX2.
5114 if (VT.getSizeInBits() >= 256)
5115 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5116 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5119 Ld = Sc.getOperand(0);
5120 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5121 Ld.getOpcode() == ISD::ConstantFP);
5123 // The scalar_to_vector node and the suspected
5124 // load node must have exactly one user.
5125 // Constants may have multiple users.
5127 // AVX-512 has register version of the broadcast
5128 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5129 Ld.getValueType().getSizeInBits() >= 32;
5130 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5137 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5138 bool IsGE256 = (VT.getSizeInBits() >= 256);
5140 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5141 // instruction to save 8 or more bytes of constant pool data.
5142 // TODO: If multiple splats are generated to load the same constant,
5143 // it may be detrimental to overall size. There needs to be a way to detect
5144 // that condition to know if this is truly a size win.
5145 const Function *F = DAG.getMachineFunction().getFunction();
5146 bool OptForSize = F->hasFnAttribute(Attribute::OptimizeForSize);
5148 // Handle broadcasting a single constant scalar from the constant pool
5150 // On Sandybridge (no AVX2), it is still better to load a constant vector
5151 // from the constant pool and not to broadcast it from a scalar.
5152 // But override that restriction when optimizing for size.
5153 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5154 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5155 EVT CVT = Ld.getValueType();
5156 assert(!CVT.isVector() && "Must not broadcast a vector type");
5158 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5159 // For size optimization, also splat v2f64 and v2i64, and for size opt
5160 // with AVX2, also splat i8 and i16.
5161 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5162 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5163 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5164 const Constant *C = nullptr;
5165 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5166 C = CI->getConstantIntValue();
5167 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5168 C = CF->getConstantFPValue();
5170 assert(C && "Invalid constant type");
5172 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5174 DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
5175 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5176 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5177 MachinePointerInfo::getConstantPool(),
5178 false, false, false, Alignment);
5180 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5184 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5186 // Handle AVX2 in-register broadcasts.
5187 if (!IsLoad && Subtarget->hasInt256() &&
5188 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5189 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5191 // The scalar source must be a normal load.
5195 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5196 (Subtarget->hasVLX() && ScalarSize == 64))
5197 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5199 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5200 // double since there is no vbroadcastsd xmm
5201 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5202 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5203 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5206 // Unsupported broadcast.
5210 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5211 /// underlying vector and index.
5213 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5215 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5217 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5218 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5221 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5223 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5225 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5226 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5229 // In this case the vector is the extract_subvector expression and the index
5230 // is 2, as specified by the shuffle.
5231 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5232 SDValue ShuffleVec = SVOp->getOperand(0);
5233 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5234 assert(ShuffleVecVT.getVectorElementType() ==
5235 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5237 int ShuffleIdx = SVOp->getMaskElt(Idx);
5238 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5239 ExtractedFromVec = ShuffleVec;
5245 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5246 MVT VT = Op.getSimpleValueType();
5248 // Skip if insert_vec_elt is not supported.
5249 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5250 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5254 unsigned NumElems = Op.getNumOperands();
5258 SmallVector<unsigned, 4> InsertIndices;
5259 SmallVector<int, 8> Mask(NumElems, -1);
5261 for (unsigned i = 0; i != NumElems; ++i) {
5262 unsigned Opc = Op.getOperand(i).getOpcode();
5264 if (Opc == ISD::UNDEF)
5267 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5268 // Quit if more than 1 elements need inserting.
5269 if (InsertIndices.size() > 1)
5272 InsertIndices.push_back(i);
5276 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5277 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5278 // Quit if non-constant index.
5279 if (!isa<ConstantSDNode>(ExtIdx))
5281 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5283 // Quit if extracted from vector of different type.
5284 if (ExtractedFromVec.getValueType() != VT)
5287 if (!VecIn1.getNode())
5288 VecIn1 = ExtractedFromVec;
5289 else if (VecIn1 != ExtractedFromVec) {
5290 if (!VecIn2.getNode())
5291 VecIn2 = ExtractedFromVec;
5292 else if (VecIn2 != ExtractedFromVec)
5293 // Quit if more than 2 vectors to shuffle
5297 if (ExtractedFromVec == VecIn1)
5299 else if (ExtractedFromVec == VecIn2)
5300 Mask[i] = Idx + NumElems;
5303 if (!VecIn1.getNode())
5306 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5307 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5308 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5309 unsigned Idx = InsertIndices[i];
5310 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5311 DAG.getIntPtrConstant(Idx, DL));
5317 static SDValue ConvertI1VectorToInterger(SDValue Op, SelectionDAG &DAG) {
5318 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5319 Op.getScalarValueSizeInBits() == 1 &&
5320 "Can not convert non-constant vector");
5321 uint64_t Immediate = 0;
5322 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5323 SDValue In = Op.getOperand(idx);
5324 if (In.getOpcode() != ISD::UNDEF)
5325 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5329 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5330 return DAG.getConstant(Immediate, dl, VT);
5332 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5334 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5336 MVT VT = Op.getSimpleValueType();
5337 assert((VT.getVectorElementType() == MVT::i1) &&
5338 "Unexpected type in LowerBUILD_VECTORvXi1!");
5341 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5342 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5343 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5344 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5347 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5348 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5349 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5350 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5353 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5354 SDValue Imm = ConvertI1VectorToInterger(Op, DAG);
5355 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5356 return DAG.getBitcast(VT, Imm);
5357 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5358 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5359 DAG.getIntPtrConstant(0, dl));
5362 // Vector has one or more non-const elements
5363 uint64_t Immediate = 0;
5364 SmallVector<unsigned, 16> NonConstIdx;
5365 bool IsSplat = true;
5366 bool HasConstElts = false;
5368 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5369 SDValue In = Op.getOperand(idx);
5370 if (In.getOpcode() == ISD::UNDEF)
5372 if (!isa<ConstantSDNode>(In))
5373 NonConstIdx.push_back(idx);
5375 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5376 HasConstElts = true;
5380 else if (In != Op.getOperand(SplatIdx))
5384 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5386 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5387 DAG.getConstant(1, dl, VT),
5388 DAG.getConstant(0, dl, VT));
5390 // insert elements one by one
5394 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5395 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5397 else if (HasConstElts)
5398 Imm = DAG.getConstant(0, dl, VT);
5400 Imm = DAG.getUNDEF(VT);
5401 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5402 DstVec = DAG.getBitcast(VT, Imm);
5404 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5405 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5406 DAG.getIntPtrConstant(0, dl));
5409 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5410 unsigned InsertIdx = NonConstIdx[i];
5411 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5412 Op.getOperand(InsertIdx),
5413 DAG.getIntPtrConstant(InsertIdx, dl));
5418 /// \brief Return true if \p N implements a horizontal binop and return the
5419 /// operands for the horizontal binop into V0 and V1.
5421 /// This is a helper function of LowerToHorizontalOp().
5422 /// This function checks that the build_vector \p N in input implements a
5423 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5424 /// operation to match.
5425 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5426 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5427 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5430 /// This function only analyzes elements of \p N whose indices are
5431 /// in range [BaseIdx, LastIdx).
5432 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5434 unsigned BaseIdx, unsigned LastIdx,
5435 SDValue &V0, SDValue &V1) {
5436 EVT VT = N->getValueType(0);
5438 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5439 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5440 "Invalid Vector in input!");
5442 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5443 bool CanFold = true;
5444 unsigned ExpectedVExtractIdx = BaseIdx;
5445 unsigned NumElts = LastIdx - BaseIdx;
5446 V0 = DAG.getUNDEF(VT);
5447 V1 = DAG.getUNDEF(VT);
5449 // Check if N implements a horizontal binop.
5450 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5451 SDValue Op = N->getOperand(i + BaseIdx);
5454 if (Op->getOpcode() == ISD::UNDEF) {
5455 // Update the expected vector extract index.
5456 if (i * 2 == NumElts)
5457 ExpectedVExtractIdx = BaseIdx;
5458 ExpectedVExtractIdx += 2;
5462 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5467 SDValue Op0 = Op.getOperand(0);
5468 SDValue Op1 = Op.getOperand(1);
5470 // Try to match the following pattern:
5471 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5472 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5473 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5474 Op0.getOperand(0) == Op1.getOperand(0) &&
5475 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5476 isa<ConstantSDNode>(Op1.getOperand(1)));
5480 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5481 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5483 if (i * 2 < NumElts) {
5484 if (V0.getOpcode() == ISD::UNDEF) {
5485 V0 = Op0.getOperand(0);
5486 if (V0.getValueType() != VT)
5490 if (V1.getOpcode() == ISD::UNDEF) {
5491 V1 = Op0.getOperand(0);
5492 if (V1.getValueType() != VT)
5495 if (i * 2 == NumElts)
5496 ExpectedVExtractIdx = BaseIdx;
5499 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5500 if (I0 == ExpectedVExtractIdx)
5501 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5502 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5503 // Try to match the following dag sequence:
5504 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5505 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5509 ExpectedVExtractIdx += 2;
5515 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5516 /// a concat_vector.
5518 /// This is a helper function of LowerToHorizontalOp().
5519 /// This function expects two 256-bit vectors called V0 and V1.
5520 /// At first, each vector is split into two separate 128-bit vectors.
5521 /// Then, the resulting 128-bit vectors are used to implement two
5522 /// horizontal binary operations.
5524 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5526 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5527 /// the two new horizontal binop.
5528 /// When Mode is set, the first horizontal binop dag node would take as input
5529 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5530 /// horizontal binop dag node would take as input the lower 128-bit of V1
5531 /// and the upper 128-bit of V1.
5533 /// HADD V0_LO, V0_HI
5534 /// HADD V1_LO, V1_HI
5536 /// Otherwise, the first horizontal binop dag node takes as input the lower
5537 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5538 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
5540 /// HADD V0_LO, V1_LO
5541 /// HADD V0_HI, V1_HI
5543 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5544 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5545 /// the upper 128-bits of the result.
5546 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5547 SDLoc DL, SelectionDAG &DAG,
5548 unsigned X86Opcode, bool Mode,
5549 bool isUndefLO, bool isUndefHI) {
5550 EVT VT = V0.getValueType();
5551 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5552 "Invalid nodes in input!");
5554 unsigned NumElts = VT.getVectorNumElements();
5555 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5556 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5557 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5558 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5559 EVT NewVT = V0_LO.getValueType();
5561 SDValue LO = DAG.getUNDEF(NewVT);
5562 SDValue HI = DAG.getUNDEF(NewVT);
5565 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5566 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5567 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5568 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5569 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5571 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5572 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5573 V1_LO->getOpcode() != ISD::UNDEF))
5574 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5576 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5577 V1_HI->getOpcode() != ISD::UNDEF))
5578 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5581 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5584 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5586 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5587 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5588 EVT VT = BV->getValueType(0);
5589 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5590 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5594 unsigned NumElts = VT.getVectorNumElements();
5595 SDValue InVec0 = DAG.getUNDEF(VT);
5596 SDValue InVec1 = DAG.getUNDEF(VT);
5598 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5599 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5601 // Odd-numbered elements in the input build vector are obtained from
5602 // adding two integer/float elements.
5603 // Even-numbered elements in the input build vector are obtained from
5604 // subtracting two integer/float elements.
5605 unsigned ExpectedOpcode = ISD::FSUB;
5606 unsigned NextExpectedOpcode = ISD::FADD;
5607 bool AddFound = false;
5608 bool SubFound = false;
5610 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5611 SDValue Op = BV->getOperand(i);
5613 // Skip 'undef' values.
5614 unsigned Opcode = Op.getOpcode();
5615 if (Opcode == ISD::UNDEF) {
5616 std::swap(ExpectedOpcode, NextExpectedOpcode);
5620 // Early exit if we found an unexpected opcode.
5621 if (Opcode != ExpectedOpcode)
5624 SDValue Op0 = Op.getOperand(0);
5625 SDValue Op1 = Op.getOperand(1);
5627 // Try to match the following pattern:
5628 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5629 // Early exit if we cannot match that sequence.
5630 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5631 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5632 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5633 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5634 Op0.getOperand(1) != Op1.getOperand(1))
5637 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5641 // We found a valid add/sub node. Update the information accordingly.
5647 // Update InVec0 and InVec1.
5648 if (InVec0.getOpcode() == ISD::UNDEF) {
5649 InVec0 = Op0.getOperand(0);
5650 if (InVec0.getValueType() != VT)
5653 if (InVec1.getOpcode() == ISD::UNDEF) {
5654 InVec1 = Op1.getOperand(0);
5655 if (InVec1.getValueType() != VT)
5659 // Make sure that operands in input to each add/sub node always
5660 // come from a same pair of vectors.
5661 if (InVec0 != Op0.getOperand(0)) {
5662 if (ExpectedOpcode == ISD::FSUB)
5665 // FADD is commutable. Try to commute the operands
5666 // and then test again.
5667 std::swap(Op0, Op1);
5668 if (InVec0 != Op0.getOperand(0))
5672 if (InVec1 != Op1.getOperand(0))
5675 // Update the pair of expected opcodes.
5676 std::swap(ExpectedOpcode, NextExpectedOpcode);
5679 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5680 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5681 InVec1.getOpcode() != ISD::UNDEF)
5682 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5687 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
5688 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
5689 const X86Subtarget *Subtarget,
5690 SelectionDAG &DAG) {
5691 EVT VT = BV->getValueType(0);
5692 unsigned NumElts = VT.getVectorNumElements();
5693 unsigned NumUndefsLO = 0;
5694 unsigned NumUndefsHI = 0;
5695 unsigned Half = NumElts/2;
5697 // Count the number of UNDEF operands in the build_vector in input.
5698 for (unsigned i = 0, e = Half; i != e; ++i)
5699 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5702 for (unsigned i = Half, e = NumElts; i != e; ++i)
5703 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5706 // Early exit if this is either a build_vector of all UNDEFs or all the
5707 // operands but one are UNDEF.
5708 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
5712 SDValue InVec0, InVec1;
5713 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
5714 // Try to match an SSE3 float HADD/HSUB.
5715 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5716 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5718 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5719 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5720 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
5721 // Try to match an SSSE3 integer HADD/HSUB.
5722 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5723 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
5725 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5726 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
5729 if (!Subtarget->hasAVX())
5732 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
5733 // Try to match an AVX horizontal add/sub of packed single/double
5734 // precision floating point values from 256-bit vectors.
5735 SDValue InVec2, InVec3;
5736 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
5737 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
5738 ((InVec0.getOpcode() == ISD::UNDEF ||
5739 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5740 ((InVec1.getOpcode() == ISD::UNDEF ||
5741 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5742 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5744 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
5745 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
5746 ((InVec0.getOpcode() == ISD::UNDEF ||
5747 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5748 ((InVec1.getOpcode() == ISD::UNDEF ||
5749 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5750 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5751 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
5752 // Try to match an AVX2 horizontal add/sub of signed integers.
5753 SDValue InVec2, InVec3;
5755 bool CanFold = true;
5757 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
5758 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
5759 ((InVec0.getOpcode() == ISD::UNDEF ||
5760 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5761 ((InVec1.getOpcode() == ISD::UNDEF ||
5762 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5763 X86Opcode = X86ISD::HADD;
5764 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
5765 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
5766 ((InVec0.getOpcode() == ISD::UNDEF ||
5767 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5768 ((InVec1.getOpcode() == ISD::UNDEF ||
5769 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5770 X86Opcode = X86ISD::HSUB;
5775 // Fold this build_vector into a single horizontal add/sub.
5776 // Do this only if the target has AVX2.
5777 if (Subtarget->hasAVX2())
5778 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
5780 // Do not try to expand this build_vector into a pair of horizontal
5781 // add/sub if we can emit a pair of scalar add/sub.
5782 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5785 // Convert this build_vector into a pair of horizontal binop followed by
5787 bool isUndefLO = NumUndefsLO == Half;
5788 bool isUndefHI = NumUndefsHI == Half;
5789 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
5790 isUndefLO, isUndefHI);
5794 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
5795 VT == MVT::v16i16) && Subtarget->hasAVX()) {
5797 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5798 X86Opcode = X86ISD::HADD;
5799 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5800 X86Opcode = X86ISD::HSUB;
5801 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5802 X86Opcode = X86ISD::FHADD;
5803 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5804 X86Opcode = X86ISD::FHSUB;
5808 // Don't try to expand this build_vector into a pair of horizontal add/sub
5809 // if we can simply emit a pair of scalar add/sub.
5810 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5813 // Convert this build_vector into two horizontal add/sub followed by
5815 bool isUndefLO = NumUndefsLO == Half;
5816 bool isUndefHI = NumUndefsHI == Half;
5817 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
5818 isUndefLO, isUndefHI);
5825 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5828 MVT VT = Op.getSimpleValueType();
5829 MVT ExtVT = VT.getVectorElementType();
5830 unsigned NumElems = Op.getNumOperands();
5832 // Generate vectors for predicate vectors.
5833 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5834 return LowerBUILD_VECTORvXi1(Op, DAG);
5836 // Vectors containing all zeros can be matched by pxor and xorps later
5837 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5838 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5839 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5840 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5843 return getZeroVector(VT, Subtarget, DAG, dl);
5846 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5847 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5848 // vpcmpeqd on 256-bit vectors.
5849 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5850 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5853 if (!VT.is512BitVector())
5854 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5857 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
5858 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
5860 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
5861 return HorizontalOp;
5862 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
5865 unsigned EVTBits = ExtVT.getSizeInBits();
5867 unsigned NumZero = 0;
5868 unsigned NumNonZero = 0;
5869 unsigned NonZeros = 0;
5870 bool IsAllConstants = true;
5871 SmallSet<SDValue, 8> Values;
5872 for (unsigned i = 0; i < NumElems; ++i) {
5873 SDValue Elt = Op.getOperand(i);
5874 if (Elt.getOpcode() == ISD::UNDEF)
5877 if (Elt.getOpcode() != ISD::Constant &&
5878 Elt.getOpcode() != ISD::ConstantFP)
5879 IsAllConstants = false;
5880 if (X86::isZeroNode(Elt))
5883 NonZeros |= (1 << i);
5888 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5889 if (NumNonZero == 0)
5890 return DAG.getUNDEF(VT);
5892 // Special case for single non-zero, non-undef, element.
5893 if (NumNonZero == 1) {
5894 unsigned Idx = countTrailingZeros(NonZeros);
5895 SDValue Item = Op.getOperand(Idx);
5897 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5898 // the value are obviously zero, truncate the value to i32 and do the
5899 // insertion that way. Only do this if the value is non-constant or if the
5900 // value is a constant being inserted into element 0. It is cheaper to do
5901 // a constant pool load than it is to do a movd + shuffle.
5902 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5903 (!IsAllConstants || Idx == 0)) {
5904 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5906 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5907 EVT VecVT = MVT::v4i32;
5909 // Truncate the value (which may itself be a constant) to i32, and
5910 // convert it to a vector with movd (S2V+shuffle to zero extend).
5911 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5912 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5913 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
5914 Item, Idx * 2, true, Subtarget, DAG));
5918 // If we have a constant or non-constant insertion into the low element of
5919 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5920 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5921 // depending on what the source datatype is.
5924 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5926 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5927 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5928 if (VT.is512BitVector()) {
5929 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5930 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5931 Item, DAG.getIntPtrConstant(0, dl));
5933 assert((VT.is128BitVector() || VT.is256BitVector()) &&
5934 "Expected an SSE value type!");
5935 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5936 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5937 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5940 // We can't directly insert an i8 or i16 into a vector, so zero extend
5942 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5943 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5944 if (VT.is256BitVector()) {
5945 if (Subtarget->hasAVX()) {
5946 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
5947 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5949 // Without AVX, we need to extend to a 128-bit vector and then
5950 // insert into the 256-bit vector.
5951 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5952 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5953 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5956 assert(VT.is128BitVector() && "Expected an SSE value type!");
5957 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5958 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5960 return DAG.getBitcast(VT, Item);
5964 // Is it a vector logical left shift?
5965 if (NumElems == 2 && Idx == 1 &&
5966 X86::isZeroNode(Op.getOperand(0)) &&
5967 !X86::isZeroNode(Op.getOperand(1))) {
5968 unsigned NumBits = VT.getSizeInBits();
5969 return getVShift(true, VT,
5970 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5971 VT, Op.getOperand(1)),
5972 NumBits/2, DAG, *this, dl);
5975 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5978 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5979 // is a non-constant being inserted into an element other than the low one,
5980 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5981 // movd/movss) to move this into the low element, then shuffle it into
5983 if (EVTBits == 32) {
5984 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5985 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
5989 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5990 if (Values.size() == 1) {
5991 if (EVTBits == 32) {
5992 // Instead of a shuffle like this:
5993 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5994 // Check if it's possible to issue this instead.
5995 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5996 unsigned Idx = countTrailingZeros(NonZeros);
5997 SDValue Item = Op.getOperand(Idx);
5998 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5999 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6004 // A vector full of immediates; various special cases are already
6005 // handled, so this is best done with a single constant-pool load.
6009 // For AVX-length vectors, see if we can use a vector load to get all of the
6010 // elements, otherwise build the individual 128-bit pieces and use
6011 // shuffles to put them in place.
6012 if (VT.is256BitVector() || VT.is512BitVector()) {
6013 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
6015 // Check for a build vector of consecutive loads.
6016 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6019 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6021 // Build both the lower and upper subvector.
6022 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6023 makeArrayRef(&V[0], NumElems/2));
6024 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6025 makeArrayRef(&V[NumElems / 2], NumElems/2));
6027 // Recreate the wider vector with the lower and upper part.
6028 if (VT.is256BitVector())
6029 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6030 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6033 // Let legalizer expand 2-wide build_vectors.
6034 if (EVTBits == 64) {
6035 if (NumNonZero == 1) {
6036 // One half is zero or undef.
6037 unsigned Idx = countTrailingZeros(NonZeros);
6038 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6039 Op.getOperand(Idx));
6040 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6045 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6046 if (EVTBits == 8 && NumElems == 16)
6047 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6051 if (EVTBits == 16 && NumElems == 8)
6052 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6056 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6057 if (EVTBits == 32 && NumElems == 4)
6058 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
6061 // If element VT is == 32 bits, turn it into a number of shuffles.
6062 SmallVector<SDValue, 8> V(NumElems);
6063 if (NumElems == 4 && NumZero > 0) {
6064 for (unsigned i = 0; i < 4; ++i) {
6065 bool isZero = !(NonZeros & (1 << i));
6067 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6069 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6072 for (unsigned i = 0; i < 2; ++i) {
6073 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6076 V[i] = V[i*2]; // Must be a zero vector.
6079 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6082 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6085 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6090 bool Reverse1 = (NonZeros & 0x3) == 2;
6091 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6095 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6096 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6098 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6101 if (Values.size() > 1 && VT.is128BitVector()) {
6102 // Check for a build vector of consecutive loads.
6103 for (unsigned i = 0; i < NumElems; ++i)
6104 V[i] = Op.getOperand(i);
6106 // Check for elements which are consecutive loads.
6107 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6110 // Check for a build vector from mostly shuffle plus few inserting.
6111 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6114 // For SSE 4.1, use insertps to put the high elements into the low element.
6115 if (Subtarget->hasSSE41()) {
6117 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6118 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6120 Result = DAG.getUNDEF(VT);
6122 for (unsigned i = 1; i < NumElems; ++i) {
6123 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6124 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6125 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6130 // Otherwise, expand into a number of unpckl*, start by extending each of
6131 // our (non-undef) elements to the full vector width with the element in the
6132 // bottom slot of the vector (which generates no code for SSE).
6133 for (unsigned i = 0; i < NumElems; ++i) {
6134 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6135 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6137 V[i] = DAG.getUNDEF(VT);
6140 // Next, we iteratively mix elements, e.g. for v4f32:
6141 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6142 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6143 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6144 unsigned EltStride = NumElems >> 1;
6145 while (EltStride != 0) {
6146 for (unsigned i = 0; i < EltStride; ++i) {
6147 // If V[i+EltStride] is undef and this is the first round of mixing,
6148 // then it is safe to just drop this shuffle: V[i] is already in the
6149 // right place, the one element (since it's the first round) being
6150 // inserted as undef can be dropped. This isn't safe for successive
6151 // rounds because they will permute elements within both vectors.
6152 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6153 EltStride == NumElems/2)
6156 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6165 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6166 // to create 256-bit vectors from two other 128-bit ones.
6167 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6169 MVT ResVT = Op.getSimpleValueType();
6171 assert((ResVT.is256BitVector() ||
6172 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6174 SDValue V1 = Op.getOperand(0);
6175 SDValue V2 = Op.getOperand(1);
6176 unsigned NumElems = ResVT.getVectorNumElements();
6177 if (ResVT.is256BitVector())
6178 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6180 if (Op.getNumOperands() == 4) {
6181 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6182 ResVT.getVectorNumElements()/2);
6183 SDValue V3 = Op.getOperand(2);
6184 SDValue V4 = Op.getOperand(3);
6185 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6186 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6188 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6191 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6192 const X86Subtarget *Subtarget,
6193 SelectionDAG & DAG) {
6195 MVT ResVT = Op.getSimpleValueType();
6196 unsigned NumOfOperands = Op.getNumOperands();
6198 assert(isPowerOf2_32(NumOfOperands) &&
6199 "Unexpected number of operands in CONCAT_VECTORS");
6201 if (NumOfOperands > 2) {
6202 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6203 ResVT.getVectorNumElements()/2);
6204 SmallVector<SDValue, 2> Ops;
6205 for (unsigned i = 0; i < NumOfOperands/2; i++)
6206 Ops.push_back(Op.getOperand(i));
6207 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6209 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6210 Ops.push_back(Op.getOperand(i));
6211 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6212 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6215 SDValue V1 = Op.getOperand(0);
6216 SDValue V2 = Op.getOperand(1);
6217 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6218 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6220 if (IsZeroV1 && IsZeroV2)
6221 return getZeroVector(ResVT, Subtarget, DAG, dl);
6223 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6224 SDValue Undef = DAG.getUNDEF(ResVT);
6225 unsigned NumElems = ResVT.getVectorNumElements();
6226 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
6228 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6229 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6233 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6234 // Zero the upper bits of V1
6235 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6236 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6239 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6242 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6243 const X86Subtarget *Subtarget,
6244 SelectionDAG &DAG) {
6245 MVT VT = Op.getSimpleValueType();
6246 if (VT.getVectorElementType() == MVT::i1)
6247 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6249 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6250 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6251 Op.getNumOperands() == 4)));
6253 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6254 // from two other 128-bit ones.
6256 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6257 return LowerAVXCONCAT_VECTORS(Op, DAG);
6261 //===----------------------------------------------------------------------===//
6262 // Vector shuffle lowering
6264 // This is an experimental code path for lowering vector shuffles on x86. It is
6265 // designed to handle arbitrary vector shuffles and blends, gracefully
6266 // degrading performance as necessary. It works hard to recognize idiomatic
6267 // shuffles and lower them to optimal instruction patterns without leaving
6268 // a framework that allows reasonably efficient handling of all vector shuffle
6270 //===----------------------------------------------------------------------===//
6272 /// \brief Tiny helper function to identify a no-op mask.
6274 /// This is a somewhat boring predicate function. It checks whether the mask
6275 /// array input, which is assumed to be a single-input shuffle mask of the kind
6276 /// used by the X86 shuffle instructions (not a fully general
6277 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6278 /// in-place shuffle are 'no-op's.
6279 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6280 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6281 if (Mask[i] != -1 && Mask[i] != i)
6286 /// \brief Helper function to classify a mask as a single-input mask.
6288 /// This isn't a generic single-input test because in the vector shuffle
6289 /// lowering we canonicalize single inputs to be the first input operand. This
6290 /// means we can more quickly test for a single input by only checking whether
6291 /// an input from the second operand exists. We also assume that the size of
6292 /// mask corresponds to the size of the input vectors which isn't true in the
6293 /// fully general case.
6294 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6296 if (M >= (int)Mask.size())
6301 /// \brief Test whether there are elements crossing 128-bit lanes in this
6304 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6305 /// and we routinely test for these.
6306 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6307 int LaneSize = 128 / VT.getScalarSizeInBits();
6308 int Size = Mask.size();
6309 for (int i = 0; i < Size; ++i)
6310 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6315 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6317 /// This checks a shuffle mask to see if it is performing the same
6318 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6319 /// that it is also not lane-crossing. It may however involve a blend from the
6320 /// same lane of a second vector.
6322 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6323 /// non-trivial to compute in the face of undef lanes. The representation is
6324 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6325 /// entries from both V1 and V2 inputs to the wider mask.
6327 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6328 SmallVectorImpl<int> &RepeatedMask) {
6329 int LaneSize = 128 / VT.getScalarSizeInBits();
6330 RepeatedMask.resize(LaneSize, -1);
6331 int Size = Mask.size();
6332 for (int i = 0; i < Size; ++i) {
6335 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6336 // This entry crosses lanes, so there is no way to model this shuffle.
6339 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6340 if (RepeatedMask[i % LaneSize] == -1)
6341 // This is the first non-undef entry in this slot of a 128-bit lane.
6342 RepeatedMask[i % LaneSize] =
6343 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6344 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6345 // Found a mismatch with the repeated mask.
6351 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6354 /// This is a fast way to test a shuffle mask against a fixed pattern:
6356 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6358 /// It returns true if the mask is exactly as wide as the argument list, and
6359 /// each element of the mask is either -1 (signifying undef) or the value given
6360 /// in the argument.
6361 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6362 ArrayRef<int> ExpectedMask) {
6363 if (Mask.size() != ExpectedMask.size())
6366 int Size = Mask.size();
6368 // If the values are build vectors, we can look through them to find
6369 // equivalent inputs that make the shuffles equivalent.
6370 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6371 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6373 for (int i = 0; i < Size; ++i)
6374 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6375 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6376 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6377 if (!MaskBV || !ExpectedBV ||
6378 MaskBV->getOperand(Mask[i] % Size) !=
6379 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6386 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6388 /// This helper function produces an 8-bit shuffle immediate corresponding to
6389 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6390 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6393 /// NB: We rely heavily on "undef" masks preserving the input lane.
6394 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6395 SelectionDAG &DAG) {
6396 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6397 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6398 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6399 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6400 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6403 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6404 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6405 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6406 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6407 return DAG.getConstant(Imm, DL, MVT::i8);
6410 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6412 /// This is used as a fallback approach when first class blend instructions are
6413 /// unavailable. Currently it is only suitable for integer vectors, but could
6414 /// be generalized for floating point vectors if desirable.
6415 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6416 SDValue V2, ArrayRef<int> Mask,
6417 SelectionDAG &DAG) {
6418 assert(VT.isInteger() && "Only supports integer vector types!");
6419 MVT EltVT = VT.getScalarType();
6420 int NumEltBits = EltVT.getSizeInBits();
6421 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6422 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6424 SmallVector<SDValue, 16> MaskOps;
6425 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6426 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6427 return SDValue(); // Shuffled input!
6428 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6431 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6432 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6433 // We have to cast V2 around.
6434 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6435 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6436 DAG.getBitcast(MaskVT, V1Mask),
6437 DAG.getBitcast(MaskVT, V2)));
6438 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6441 /// \brief Try to emit a blend instruction for a shuffle.
6443 /// This doesn't do any checks for the availability of instructions for blending
6444 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6445 /// be matched in the backend with the type given. What it does check for is
6446 /// that the shuffle mask is in fact a blend.
6447 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6448 SDValue V2, ArrayRef<int> Mask,
6449 const X86Subtarget *Subtarget,
6450 SelectionDAG &DAG) {
6451 unsigned BlendMask = 0;
6452 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6453 if (Mask[i] >= Size) {
6454 if (Mask[i] != i + Size)
6455 return SDValue(); // Shuffled V2 input!
6456 BlendMask |= 1u << i;
6459 if (Mask[i] >= 0 && Mask[i] != i)
6460 return SDValue(); // Shuffled V1 input!
6462 switch (VT.SimpleTy) {
6467 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6468 DAG.getConstant(BlendMask, DL, MVT::i8));
6472 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6476 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6477 // that instruction.
6478 if (Subtarget->hasAVX2()) {
6479 // Scale the blend by the number of 32-bit dwords per element.
6480 int Scale = VT.getScalarSizeInBits() / 32;
6482 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6483 if (Mask[i] >= Size)
6484 for (int j = 0; j < Scale; ++j)
6485 BlendMask |= 1u << (i * Scale + j);
6487 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6488 V1 = DAG.getBitcast(BlendVT, V1);
6489 V2 = DAG.getBitcast(BlendVT, V2);
6490 return DAG.getBitcast(
6491 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6492 DAG.getConstant(BlendMask, DL, MVT::i8)));
6496 // For integer shuffles we need to expand the mask and cast the inputs to
6497 // v8i16s prior to blending.
6498 int Scale = 8 / VT.getVectorNumElements();
6500 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6501 if (Mask[i] >= Size)
6502 for (int j = 0; j < Scale; ++j)
6503 BlendMask |= 1u << (i * Scale + j);
6505 V1 = DAG.getBitcast(MVT::v8i16, V1);
6506 V2 = DAG.getBitcast(MVT::v8i16, V2);
6507 return DAG.getBitcast(VT,
6508 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6509 DAG.getConstant(BlendMask, DL, MVT::i8)));
6513 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6514 SmallVector<int, 8> RepeatedMask;
6515 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6516 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6517 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6519 for (int i = 0; i < 8; ++i)
6520 if (RepeatedMask[i] >= 16)
6521 BlendMask |= 1u << i;
6522 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6523 DAG.getConstant(BlendMask, DL, MVT::i8));
6529 assert((VT.getSizeInBits() == 128 || Subtarget->hasAVX2()) &&
6530 "256-bit byte-blends require AVX2 support!");
6532 // Scale the blend by the number of bytes per element.
6533 int Scale = VT.getScalarSizeInBits() / 8;
6535 // This form of blend is always done on bytes. Compute the byte vector
6537 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6539 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6540 // mix of LLVM's code generator and the x86 backend. We tell the code
6541 // generator that boolean values in the elements of an x86 vector register
6542 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6543 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6544 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6545 // of the element (the remaining are ignored) and 0 in that high bit would
6546 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6547 // the LLVM model for boolean values in vector elements gets the relevant
6548 // bit set, it is set backwards and over constrained relative to x86's
6550 SmallVector<SDValue, 32> VSELECTMask;
6551 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6552 for (int j = 0; j < Scale; ++j)
6553 VSELECTMask.push_back(
6554 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
6555 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
6558 V1 = DAG.getBitcast(BlendVT, V1);
6559 V2 = DAG.getBitcast(BlendVT, V2);
6560 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
6561 DAG.getNode(ISD::BUILD_VECTOR, DL,
6562 BlendVT, VSELECTMask),
6567 llvm_unreachable("Not a supported integer vector type!");
6571 /// \brief Try to lower as a blend of elements from two inputs followed by
6572 /// a single-input permutation.
6574 /// This matches the pattern where we can blend elements from two inputs and
6575 /// then reduce the shuffle to a single-input permutation.
6576 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
6579 SelectionDAG &DAG) {
6580 // We build up the blend mask while checking whether a blend is a viable way
6581 // to reduce the shuffle.
6582 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6583 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
6585 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6589 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
6591 if (BlendMask[Mask[i] % Size] == -1)
6592 BlendMask[Mask[i] % Size] = Mask[i];
6593 else if (BlendMask[Mask[i] % Size] != Mask[i])
6594 return SDValue(); // Can't blend in the needed input!
6596 PermuteMask[i] = Mask[i] % Size;
6599 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6600 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
6603 /// \brief Generic routine to decompose a shuffle and blend into indepndent
6604 /// blends and permutes.
6606 /// This matches the extremely common pattern for handling combined
6607 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
6608 /// operations. It will try to pick the best arrangement of shuffles and
6610 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
6614 SelectionDAG &DAG) {
6615 // Shuffle the input elements into the desired positions in V1 and V2 and
6616 // blend them together.
6617 SmallVector<int, 32> V1Mask(Mask.size(), -1);
6618 SmallVector<int, 32> V2Mask(Mask.size(), -1);
6619 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6620 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6621 if (Mask[i] >= 0 && Mask[i] < Size) {
6622 V1Mask[i] = Mask[i];
6624 } else if (Mask[i] >= Size) {
6625 V2Mask[i] = Mask[i] - Size;
6626 BlendMask[i] = i + Size;
6629 // Try to lower with the simpler initial blend strategy unless one of the
6630 // input shuffles would be a no-op. We prefer to shuffle inputs as the
6631 // shuffle may be able to fold with a load or other benefit. However, when
6632 // we'll have to do 2x as many shuffles in order to achieve this, blending
6633 // first is a better strategy.
6634 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
6635 if (SDValue BlendPerm =
6636 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
6639 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
6640 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
6641 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6644 /// \brief Try to lower a vector shuffle as a byte rotation.
6646 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
6647 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
6648 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
6649 /// try to generically lower a vector shuffle through such an pattern. It
6650 /// does not check for the profitability of lowering either as PALIGNR or
6651 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
6652 /// This matches shuffle vectors that look like:
6654 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
6656 /// Essentially it concatenates V1 and V2, shifts right by some number of
6657 /// elements, and takes the low elements as the result. Note that while this is
6658 /// specified as a *right shift* because x86 is little-endian, it is a *left
6659 /// rotate* of the vector lanes.
6660 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
6663 const X86Subtarget *Subtarget,
6664 SelectionDAG &DAG) {
6665 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
6667 int NumElts = Mask.size();
6668 int NumLanes = VT.getSizeInBits() / 128;
6669 int NumLaneElts = NumElts / NumLanes;
6671 // We need to detect various ways of spelling a rotation:
6672 // [11, 12, 13, 14, 15, 0, 1, 2]
6673 // [-1, 12, 13, 14, -1, -1, 1, -1]
6674 // [-1, -1, -1, -1, -1, -1, 1, 2]
6675 // [ 3, 4, 5, 6, 7, 8, 9, 10]
6676 // [-1, 4, 5, 6, -1, -1, 9, -1]
6677 // [-1, 4, 5, 6, -1, -1, -1, -1]
6680 for (int l = 0; l < NumElts; l += NumLaneElts) {
6681 for (int i = 0; i < NumLaneElts; ++i) {
6682 if (Mask[l + i] == -1)
6684 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
6686 // Get the mod-Size index and lane correct it.
6687 int LaneIdx = (Mask[l + i] % NumElts) - l;
6688 // Make sure it was in this lane.
6689 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
6692 // Determine where a rotated vector would have started.
6693 int StartIdx = i - LaneIdx;
6695 // The identity rotation isn't interesting, stop.
6698 // If we found the tail of a vector the rotation must be the missing
6699 // front. If we found the head of a vector, it must be how much of the
6701 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
6704 Rotation = CandidateRotation;
6705 else if (Rotation != CandidateRotation)
6706 // The rotations don't match, so we can't match this mask.
6709 // Compute which value this mask is pointing at.
6710 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
6712 // Compute which of the two target values this index should be assigned
6713 // to. This reflects whether the high elements are remaining or the low
6714 // elements are remaining.
6715 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
6717 // Either set up this value if we've not encountered it before, or check
6718 // that it remains consistent.
6721 else if (TargetV != MaskV)
6722 // This may be a rotation, but it pulls from the inputs in some
6723 // unsupported interleaving.
6728 // Check that we successfully analyzed the mask, and normalize the results.
6729 assert(Rotation != 0 && "Failed to locate a viable rotation!");
6730 assert((Lo || Hi) && "Failed to find a rotated input vector!");
6736 // The actual rotate instruction rotates bytes, so we need to scale the
6737 // rotation based on how many bytes are in the vector lane.
6738 int Scale = 16 / NumLaneElts;
6740 // SSSE3 targets can use the palignr instruction.
6741 if (Subtarget->hasSSSE3()) {
6742 // Cast the inputs to i8 vector of correct length to match PALIGNR.
6743 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
6744 Lo = DAG.getBitcast(AlignVT, Lo);
6745 Hi = DAG.getBitcast(AlignVT, Hi);
6747 return DAG.getBitcast(
6748 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Hi, Lo,
6749 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
6752 assert(VT.getSizeInBits() == 128 &&
6753 "Rotate-based lowering only supports 128-bit lowering!");
6754 assert(Mask.size() <= 16 &&
6755 "Can shuffle at most 16 bytes in a 128-bit vector!");
6757 // Default SSE2 implementation
6758 int LoByteShift = 16 - Rotation * Scale;
6759 int HiByteShift = Rotation * Scale;
6761 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
6762 Lo = DAG.getBitcast(MVT::v2i64, Lo);
6763 Hi = DAG.getBitcast(MVT::v2i64, Hi);
6765 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
6766 DAG.getConstant(LoByteShift, DL, MVT::i8));
6767 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
6768 DAG.getConstant(HiByteShift, DL, MVT::i8));
6769 return DAG.getBitcast(VT,
6770 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
6773 /// \brief Compute whether each element of a shuffle is zeroable.
6775 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6776 /// Either it is an undef element in the shuffle mask, the element of the input
6777 /// referenced is undef, or the element of the input referenced is known to be
6778 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6779 /// as many lanes with this technique as possible to simplify the remaining
6781 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6782 SDValue V1, SDValue V2) {
6783 SmallBitVector Zeroable(Mask.size(), false);
6785 while (V1.getOpcode() == ISD::BITCAST)
6786 V1 = V1->getOperand(0);
6787 while (V2.getOpcode() == ISD::BITCAST)
6788 V2 = V2->getOperand(0);
6790 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6791 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6793 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6795 // Handle the easy cases.
6796 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6801 // If this is an index into a build_vector node (which has the same number
6802 // of elements), dig out the input value and use it.
6803 SDValue V = M < Size ? V1 : V2;
6804 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6807 SDValue Input = V.getOperand(M % Size);
6808 // The UNDEF opcode check really should be dead code here, but not quite
6809 // worth asserting on (it isn't invalid, just unexpected).
6810 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6817 /// \brief Try to emit a bitmask instruction for a shuffle.
6819 /// This handles cases where we can model a blend exactly as a bitmask due to
6820 /// one of the inputs being zeroable.
6821 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6822 SDValue V2, ArrayRef<int> Mask,
6823 SelectionDAG &DAG) {
6824 MVT EltVT = VT.getScalarType();
6825 int NumEltBits = EltVT.getSizeInBits();
6826 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6827 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6828 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6830 if (EltVT.isFloatingPoint()) {
6831 Zero = DAG.getBitcast(EltVT, Zero);
6832 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6834 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6835 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6837 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6840 if (Mask[i] % Size != i)
6841 return SDValue(); // Not a blend.
6843 V = Mask[i] < Size ? V1 : V2;
6844 else if (V != (Mask[i] < Size ? V1 : V2))
6845 return SDValue(); // Can only let one input through the mask.
6847 VMaskOps[i] = AllOnes;
6850 return SDValue(); // No non-zeroable elements!
6852 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6853 V = DAG.getNode(VT.isFloatingPoint()
6854 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6859 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
6861 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
6862 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
6863 /// matches elements from one of the input vectors shuffled to the left or
6864 /// right with zeroable elements 'shifted in'. It handles both the strictly
6865 /// bit-wise element shifts and the byte shift across an entire 128-bit double
6868 /// PSHL : (little-endian) left bit shift.
6869 /// [ zz, 0, zz, 2 ]
6870 /// [ -1, 4, zz, -1 ]
6871 /// PSRL : (little-endian) right bit shift.
6873 /// [ -1, -1, 7, zz]
6874 /// PSLLDQ : (little-endian) left byte shift
6875 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
6876 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
6877 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
6878 /// PSRLDQ : (little-endian) right byte shift
6879 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
6880 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
6881 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
6882 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
6883 SDValue V2, ArrayRef<int> Mask,
6884 SelectionDAG &DAG) {
6885 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6887 int Size = Mask.size();
6888 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
6890 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
6891 for (int i = 0; i < Size; i += Scale)
6892 for (int j = 0; j < Shift; ++j)
6893 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
6899 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
6900 for (int i = 0; i != Size; i += Scale) {
6901 unsigned Pos = Left ? i + Shift : i;
6902 unsigned Low = Left ? i : i + Shift;
6903 unsigned Len = Scale - Shift;
6904 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
6905 Low + (V == V1 ? 0 : Size)))
6909 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
6910 bool ByteShift = ShiftEltBits > 64;
6911 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
6912 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
6913 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
6915 // Normalize the scale for byte shifts to still produce an i64 element
6917 Scale = ByteShift ? Scale / 2 : Scale;
6919 // We need to round trip through the appropriate type for the shift.
6920 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
6921 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
6922 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
6923 "Illegal integer vector type");
6924 V = DAG.getBitcast(ShiftVT, V);
6926 V = DAG.getNode(OpCode, DL, ShiftVT, V,
6927 DAG.getConstant(ShiftAmt, DL, MVT::i8));
6928 return DAG.getBitcast(VT, V);
6931 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
6932 // keep doubling the size of the integer elements up to that. We can
6933 // then shift the elements of the integer vector by whole multiples of
6934 // their width within the elements of the larger integer vector. Test each
6935 // multiple to see if we can find a match with the moved element indices
6936 // and that the shifted in elements are all zeroable.
6937 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
6938 for (int Shift = 1; Shift != Scale; ++Shift)
6939 for (bool Left : {true, false})
6940 if (CheckZeros(Shift, Scale, Left))
6941 for (SDValue V : {V1, V2})
6942 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
6949 /// \brief Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ.
6950 static SDValue lowerVectorShuffleWithSSE4A(SDLoc DL, MVT VT, SDValue V1,
6951 SDValue V2, ArrayRef<int> Mask,
6952 SelectionDAG &DAG) {
6953 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6954 assert(!Zeroable.all() && "Fully zeroable shuffle mask");
6956 int Size = Mask.size();
6957 int HalfSize = Size / 2;
6958 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
6960 // Upper half must be undefined.
6961 if (!isUndefInRange(Mask, HalfSize, HalfSize))
6964 // EXTRQ: Extract Len elements from lower half of source, starting at Idx.
6965 // Remainder of lower half result is zero and upper half is all undef.
6966 auto LowerAsEXTRQ = [&]() {
6967 // Determine the extraction length from the part of the
6968 // lower half that isn't zeroable.
6970 for (; Len >= 0; --Len)
6971 if (!Zeroable[Len - 1])
6973 assert(Len > 0 && "Zeroable shuffle mask");
6975 // Attempt to match first Len sequential elements from the lower half.
6978 for (int i = 0; i != Len; ++i) {
6982 SDValue &V = (M < Size ? V1 : V2);
6985 // All mask elements must be in the lower half.
6989 if (Idx < 0 || (Src == V && Idx == (M - i))) {
7000 assert((Idx + Len) <= HalfSize && "Illegal extraction mask");
7001 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7002 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7003 return DAG.getNode(X86ISD::EXTRQI, DL, VT, Src,
7004 DAG.getConstant(BitLen, DL, MVT::i8),
7005 DAG.getConstant(BitIdx, DL, MVT::i8));
7008 if (SDValue ExtrQ = LowerAsEXTRQ())
7011 // INSERTQ: Extract lowest Len elements from lower half of second source and
7012 // insert over first source, starting at Idx.
7013 // { A[0], .., A[Idx-1], B[0], .., B[Len-1], A[Idx+Len], .., UNDEF, ... }
7014 auto LowerAsInsertQ = [&]() {
7015 for (int Idx = 0; Idx != HalfSize; ++Idx) {
7018 // Attempt to match first source from mask before insertion point.
7019 if (isUndefInRange(Mask, 0, Idx)) {
7021 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, 0)) {
7023 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, Size)) {
7029 // Extend the extraction length looking to match both the insertion of
7030 // the second source and the remaining elements of the first.
7031 for (int Hi = Idx + 1; Hi <= HalfSize; ++Hi) {
7036 if (isSequentialOrUndefInRange(Mask, Idx, Len, 0)) {
7038 } else if (isSequentialOrUndefInRange(Mask, Idx, Len, Size)) {
7044 // Match the remaining elements of the lower half.
7045 if (isUndefInRange(Mask, Hi, HalfSize - Hi)) {
7047 } else if ((!Base || (Base == V1)) &&
7048 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi, Hi)) {
7050 } else if ((!Base || (Base == V2)) &&
7051 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi,
7058 // We may not have a base (first source) - this can safely be undefined.
7060 Base = DAG.getUNDEF(VT);
7062 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7063 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7064 return DAG.getNode(X86ISD::INSERTQI, DL, VT, Base, Insert,
7065 DAG.getConstant(BitLen, DL, MVT::i8),
7066 DAG.getConstant(BitIdx, DL, MVT::i8));
7073 if (SDValue InsertQ = LowerAsInsertQ())
7079 /// \brief Lower a vector shuffle as a zero or any extension.
7081 /// Given a specific number of elements, element bit width, and extension
7082 /// stride, produce either a zero or any extension based on the available
7083 /// features of the subtarget.
7084 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7085 SDLoc DL, MVT VT, int Scale, bool AnyExt, SDValue InputV,
7086 ArrayRef<int> Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7087 assert(Scale > 1 && "Need a scale to extend.");
7088 int NumElements = VT.getVectorNumElements();
7089 int EltBits = VT.getScalarSizeInBits();
7090 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7091 "Only 8, 16, and 32 bit elements can be extended.");
7092 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7094 // Found a valid zext mask! Try various lowering strategies based on the
7095 // input type and available ISA extensions.
7096 if (Subtarget->hasSSE41()) {
7097 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7098 NumElements / Scale);
7099 return DAG.getBitcast(VT, DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7102 // For any extends we can cheat for larger element sizes and use shuffle
7103 // instructions that can fold with a load and/or copy.
7104 if (AnyExt && EltBits == 32) {
7105 int PSHUFDMask[4] = {0, -1, 1, -1};
7106 return DAG.getBitcast(
7107 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7108 DAG.getBitcast(MVT::v4i32, InputV),
7109 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
7111 if (AnyExt && EltBits == 16 && Scale > 2) {
7112 int PSHUFDMask[4] = {0, -1, 0, -1};
7113 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7114 DAG.getBitcast(MVT::v4i32, InputV),
7115 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
7116 int PSHUFHWMask[4] = {1, -1, -1, -1};
7117 return DAG.getBitcast(
7118 VT, DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7119 DAG.getBitcast(MVT::v8i16, InputV),
7120 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DL, DAG)));
7123 // The SSE4A EXTRQ instruction can efficiently extend the first 2 lanes
7125 if ((Scale * EltBits) == 64 && EltBits < 32 && Subtarget->hasSSE4A()) {
7126 assert(NumElements == (int)Mask.size() && "Unexpected shuffle mask size!");
7127 assert(VT.getSizeInBits() == 128 && "Unexpected vector width!");
7129 SDValue Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7130 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7131 DAG.getConstant(EltBits, DL, MVT::i8),
7132 DAG.getConstant(0, DL, MVT::i8)));
7133 if (isUndefInRange(Mask, NumElements/2, NumElements/2))
7134 return DAG.getNode(ISD::BITCAST, DL, VT, Lo);
7137 DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7138 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7139 DAG.getConstant(EltBits, DL, MVT::i8),
7140 DAG.getConstant(EltBits, DL, MVT::i8)));
7141 return DAG.getNode(ISD::BITCAST, DL, VT,
7142 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));
7145 // If this would require more than 2 unpack instructions to expand, use
7146 // pshufb when available. We can only use more than 2 unpack instructions
7147 // when zero extending i8 elements which also makes it easier to use pshufb.
7148 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7149 assert(NumElements == 16 && "Unexpected byte vector width!");
7150 SDValue PSHUFBMask[16];
7151 for (int i = 0; i < 16; ++i)
7153 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, DL, MVT::i8);
7154 InputV = DAG.getBitcast(MVT::v16i8, InputV);
7155 return DAG.getBitcast(VT,
7156 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7157 DAG.getNode(ISD::BUILD_VECTOR, DL,
7158 MVT::v16i8, PSHUFBMask)));
7161 // Otherwise emit a sequence of unpacks.
7163 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7164 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7165 : getZeroVector(InputVT, Subtarget, DAG, DL);
7166 InputV = DAG.getBitcast(InputVT, InputV);
7167 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7171 } while (Scale > 1);
7172 return DAG.getBitcast(VT, InputV);
7175 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
7177 /// This routine will try to do everything in its power to cleverly lower
7178 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7179 /// check for the profitability of this lowering, it tries to aggressively
7180 /// match this pattern. It will use all of the micro-architectural details it
7181 /// can to emit an efficient lowering. It handles both blends with all-zero
7182 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7183 /// masking out later).
7185 /// The reason we have dedicated lowering for zext-style shuffles is that they
7186 /// are both incredibly common and often quite performance sensitive.
7187 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7188 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7189 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7190 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7192 int Bits = VT.getSizeInBits();
7193 int NumElements = VT.getVectorNumElements();
7194 assert(VT.getScalarSizeInBits() <= 32 &&
7195 "Exceeds 32-bit integer zero extension limit");
7196 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7198 // Define a helper function to check a particular ext-scale and lower to it if
7200 auto Lower = [&](int Scale) -> SDValue {
7203 for (int i = 0; i < NumElements; ++i) {
7205 continue; // Valid anywhere but doesn't tell us anything.
7206 if (i % Scale != 0) {
7207 // Each of the extended elements need to be zeroable.
7211 // We no longer are in the anyext case.
7216 // Each of the base elements needs to be consecutive indices into the
7217 // same input vector.
7218 SDValue V = Mask[i] < NumElements ? V1 : V2;
7221 else if (InputV != V)
7222 return SDValue(); // Flip-flopping inputs.
7224 if (Mask[i] % NumElements != i / Scale)
7225 return SDValue(); // Non-consecutive strided elements.
7228 // If we fail to find an input, we have a zero-shuffle which should always
7229 // have already been handled.
7230 // FIXME: Maybe handle this here in case during blending we end up with one?
7234 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7235 DL, VT, Scale, AnyExt, InputV, Mask, Subtarget, DAG);
7238 // The widest scale possible for extending is to a 64-bit integer.
7239 assert(Bits % 64 == 0 &&
7240 "The number of bits in a vector must be divisible by 64 on x86!");
7241 int NumExtElements = Bits / 64;
7243 // Each iteration, try extending the elements half as much, but into twice as
7245 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7246 assert(NumElements % NumExtElements == 0 &&
7247 "The input vector size must be divisible by the extended size.");
7248 if (SDValue V = Lower(NumElements / NumExtElements))
7252 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7256 // Returns one of the source operands if the shuffle can be reduced to a
7257 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7258 auto CanZExtLowHalf = [&]() {
7259 for (int i = NumElements / 2; i != NumElements; ++i)
7262 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7264 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7269 if (SDValue V = CanZExtLowHalf()) {
7270 V = DAG.getBitcast(MVT::v2i64, V);
7271 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7272 return DAG.getBitcast(VT, V);
7275 // No viable ext lowering found.
7279 /// \brief Try to get a scalar value for a specific element of a vector.
7281 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7282 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7283 SelectionDAG &DAG) {
7284 MVT VT = V.getSimpleValueType();
7285 MVT EltVT = VT.getVectorElementType();
7286 while (V.getOpcode() == ISD::BITCAST)
7287 V = V.getOperand(0);
7288 // If the bitcasts shift the element size, we can't extract an equivalent
7290 MVT NewVT = V.getSimpleValueType();
7291 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7294 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7295 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7296 // Ensure the scalar operand is the same size as the destination.
7297 // FIXME: Add support for scalar truncation where possible.
7298 SDValue S = V.getOperand(Idx);
7299 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7300 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7306 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7308 /// This is particularly important because the set of instructions varies
7309 /// significantly based on whether the operand is a load or not.
7310 static bool isShuffleFoldableLoad(SDValue V) {
7311 while (V.getOpcode() == ISD::BITCAST)
7312 V = V.getOperand(0);
7314 return ISD::isNON_EXTLoad(V.getNode());
7317 /// \brief Try to lower insertion of a single element into a zero vector.
7319 /// This is a common pattern that we have especially efficient patterns to lower
7320 /// across all subtarget feature sets.
7321 static SDValue lowerVectorShuffleAsElementInsertion(
7322 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7323 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7324 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7326 MVT EltVT = VT.getVectorElementType();
7328 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7329 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7331 bool IsV1Zeroable = true;
7332 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7333 if (i != V2Index && !Zeroable[i]) {
7334 IsV1Zeroable = false;
7338 // Check for a single input from a SCALAR_TO_VECTOR node.
7339 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7340 // all the smarts here sunk into that routine. However, the current
7341 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7342 // vector shuffle lowering is dead.
7343 if (SDValue V2S = getScalarValueForVectorElement(
7344 V2, Mask[V2Index] - Mask.size(), DAG)) {
7345 // We need to zext the scalar if it is smaller than an i32.
7346 V2S = DAG.getBitcast(EltVT, V2S);
7347 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7348 // Using zext to expand a narrow element won't work for non-zero
7353 // Zero-extend directly to i32.
7355 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7357 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7358 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7359 EltVT == MVT::i16) {
7360 // Either not inserting from the low element of the input or the input
7361 // element size is too small to use VZEXT_MOVL to clear the high bits.
7365 if (!IsV1Zeroable) {
7366 // If V1 can't be treated as a zero vector we have fewer options to lower
7367 // this. We can't support integer vectors or non-zero targets cheaply, and
7368 // the V1 elements can't be permuted in any way.
7369 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7370 if (!VT.isFloatingPoint() || V2Index != 0)
7372 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7373 V1Mask[V2Index] = -1;
7374 if (!isNoopShuffleMask(V1Mask))
7376 // This is essentially a special case blend operation, but if we have
7377 // general purpose blend operations, they are always faster. Bail and let
7378 // the rest of the lowering handle these as blends.
7379 if (Subtarget->hasSSE41())
7382 // Otherwise, use MOVSD or MOVSS.
7383 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7384 "Only two types of floating point element types to handle!");
7385 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7389 // This lowering only works for the low element with floating point vectors.
7390 if (VT.isFloatingPoint() && V2Index != 0)
7393 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7395 V2 = DAG.getBitcast(VT, V2);
7398 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7399 // the desired position. Otherwise it is more efficient to do a vector
7400 // shift left. We know that we can do a vector shift left because all
7401 // the inputs are zero.
7402 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7403 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7404 V2Shuffle[V2Index] = 0;
7405 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7407 V2 = DAG.getBitcast(MVT::v2i64, V2);
7409 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7410 DAG.getConstant(V2Index * EltVT.getSizeInBits() / 8, DL,
7411 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(
7412 DAG.getDataLayout())));
7413 V2 = DAG.getBitcast(VT, V2);
7419 /// \brief Try to lower broadcast of a single element.
7421 /// For convenience, this code also bundles all of the subtarget feature set
7422 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7423 /// a convenient way to factor it out.
7424 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7426 const X86Subtarget *Subtarget,
7427 SelectionDAG &DAG) {
7428 if (!Subtarget->hasAVX())
7430 if (VT.isInteger() && !Subtarget->hasAVX2())
7433 // Check that the mask is a broadcast.
7434 int BroadcastIdx = -1;
7436 if (M >= 0 && BroadcastIdx == -1)
7438 else if (M >= 0 && M != BroadcastIdx)
7441 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7442 "a sorted mask where the broadcast "
7445 // Go up the chain of (vector) values to find a scalar load that we can
7446 // combine with the broadcast.
7448 switch (V.getOpcode()) {
7449 case ISD::CONCAT_VECTORS: {
7450 int OperandSize = Mask.size() / V.getNumOperands();
7451 V = V.getOperand(BroadcastIdx / OperandSize);
7452 BroadcastIdx %= OperandSize;
7456 case ISD::INSERT_SUBVECTOR: {
7457 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7458 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7462 int BeginIdx = (int)ConstantIdx->getZExtValue();
7464 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7465 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7466 BroadcastIdx -= BeginIdx;
7477 // Check if this is a broadcast of a scalar. We special case lowering
7478 // for scalars so that we can more effectively fold with loads.
7479 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7480 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7481 V = V.getOperand(BroadcastIdx);
7483 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7484 // Only AVX2 has register broadcasts.
7485 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7487 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7488 // We can't broadcast from a vector register without AVX2, and we can only
7489 // broadcast from the zero-element of a vector register.
7493 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7496 // Check for whether we can use INSERTPS to perform the shuffle. We only use
7497 // INSERTPS when the V1 elements are already in the correct locations
7498 // because otherwise we can just always use two SHUFPS instructions which
7499 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
7500 // perform INSERTPS if a single V1 element is out of place and all V2
7501 // elements are zeroable.
7502 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
7504 SelectionDAG &DAG) {
7505 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7506 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7507 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7508 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7510 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7513 int V1DstIndex = -1;
7514 int V2DstIndex = -1;
7515 bool V1UsedInPlace = false;
7517 for (int i = 0; i < 4; ++i) {
7518 // Synthesize a zero mask from the zeroable elements (includes undefs).
7524 // Flag if we use any V1 inputs in place.
7526 V1UsedInPlace = true;
7530 // We can only insert a single non-zeroable element.
7531 if (V1DstIndex != -1 || V2DstIndex != -1)
7535 // V1 input out of place for insertion.
7538 // V2 input for insertion.
7543 // Don't bother if we have no (non-zeroable) element for insertion.
7544 if (V1DstIndex == -1 && V2DstIndex == -1)
7547 // Determine element insertion src/dst indices. The src index is from the
7548 // start of the inserted vector, not the start of the concatenated vector.
7549 unsigned V2SrcIndex = 0;
7550 if (V1DstIndex != -1) {
7551 // If we have a V1 input out of place, we use V1 as the V2 element insertion
7552 // and don't use the original V2 at all.
7553 V2SrcIndex = Mask[V1DstIndex];
7554 V2DstIndex = V1DstIndex;
7557 V2SrcIndex = Mask[V2DstIndex] - 4;
7560 // If no V1 inputs are used in place, then the result is created only from
7561 // the zero mask and the V2 insertion - so remove V1 dependency.
7563 V1 = DAG.getUNDEF(MVT::v4f32);
7565 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
7566 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7568 // Insert the V2 element into the desired position.
7570 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7571 DAG.getConstant(InsertPSMask, DL, MVT::i8));
7574 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
7575 /// UNPCK instruction.
7577 /// This specifically targets cases where we end up with alternating between
7578 /// the two inputs, and so can permute them into something that feeds a single
7579 /// UNPCK instruction. Note that this routine only targets integer vectors
7580 /// because for floating point vectors we have a generalized SHUFPS lowering
7581 /// strategy that handles everything that doesn't *exactly* match an unpack,
7582 /// making this clever lowering unnecessary.
7583 static SDValue lowerVectorShuffleAsUnpack(SDLoc DL, MVT VT, SDValue V1,
7584 SDValue V2, ArrayRef<int> Mask,
7585 SelectionDAG &DAG) {
7586 assert(!VT.isFloatingPoint() &&
7587 "This routine only supports integer vectors.");
7588 assert(!isSingleInputShuffleMask(Mask) &&
7589 "This routine should only be used when blending two inputs.");
7590 assert(Mask.size() >= 2 && "Single element masks are invalid.");
7592 int Size = Mask.size();
7594 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
7595 return M >= 0 && M % Size < Size / 2;
7597 int NumHiInputs = std::count_if(
7598 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
7600 bool UnpackLo = NumLoInputs >= NumHiInputs;
7602 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
7603 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7604 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7606 for (int i = 0; i < Size; ++i) {
7610 // Each element of the unpack contains Scale elements from this mask.
7611 int UnpackIdx = i / Scale;
7613 // We only handle the case where V1 feeds the first slots of the unpack.
7614 // We rely on canonicalization to ensure this is the case.
7615 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
7618 // Setup the mask for this input. The indexing is tricky as we have to
7619 // handle the unpack stride.
7620 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
7621 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
7625 // If we will have to shuffle both inputs to use the unpack, check whether
7626 // we can just unpack first and shuffle the result. If so, skip this unpack.
7627 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
7628 !isNoopShuffleMask(V2Mask))
7631 // Shuffle the inputs into place.
7632 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7633 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7635 // Cast the inputs to the type we will use to unpack them.
7636 V1 = DAG.getBitcast(UnpackVT, V1);
7637 V2 = DAG.getBitcast(UnpackVT, V2);
7639 // Unpack the inputs and cast the result back to the desired type.
7640 return DAG.getBitcast(
7641 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
7645 // We try each unpack from the largest to the smallest to try and find one
7646 // that fits this mask.
7647 int OrigNumElements = VT.getVectorNumElements();
7648 int OrigScalarSize = VT.getScalarSizeInBits();
7649 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
7650 int Scale = ScalarSize / OrigScalarSize;
7651 int NumElements = OrigNumElements / Scale;
7652 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
7653 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
7657 // If none of the unpack-rooted lowerings worked (or were profitable) try an
7659 if (NumLoInputs == 0 || NumHiInputs == 0) {
7660 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
7661 "We have to have *some* inputs!");
7662 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
7664 // FIXME: We could consider the total complexity of the permute of each
7665 // possible unpacking. Or at the least we should consider how many
7666 // half-crossings are created.
7667 // FIXME: We could consider commuting the unpacks.
7669 SmallVector<int, 32> PermMask;
7670 PermMask.assign(Size, -1);
7671 for (int i = 0; i < Size; ++i) {
7675 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
7678 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
7680 return DAG.getVectorShuffle(
7681 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
7683 DAG.getUNDEF(VT), PermMask);
7689 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7691 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7692 /// support for floating point shuffles but not integer shuffles. These
7693 /// instructions will incur a domain crossing penalty on some chips though so
7694 /// it is better to avoid lowering through this for integer vectors where
7696 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7697 const X86Subtarget *Subtarget,
7698 SelectionDAG &DAG) {
7700 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7701 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7702 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7703 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7704 ArrayRef<int> Mask = SVOp->getMask();
7705 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7707 if (isSingleInputShuffleMask(Mask)) {
7708 // Use low duplicate instructions for masks that match their pattern.
7709 if (Subtarget->hasSSE3())
7710 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
7711 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
7713 // Straight shuffle of a single input vector. Simulate this by using the
7714 // single input as both of the "inputs" to this instruction..
7715 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7717 if (Subtarget->hasAVX()) {
7718 // If we have AVX, we can use VPERMILPS which will allow folding a load
7719 // into the shuffle.
7720 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7721 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7724 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
7725 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7727 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7728 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7730 // If we have a single input, insert that into V1 if we can do so cheaply.
7731 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
7732 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7733 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
7735 // Try inverting the insertion since for v2 masks it is easy to do and we
7736 // can't reliably sort the mask one way or the other.
7737 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7738 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7739 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7740 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
7744 // Try to use one of the special instruction patterns to handle two common
7745 // blend patterns if a zero-blend above didn't work.
7746 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
7747 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7748 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
7749 // We can either use a special instruction to load over the low double or
7750 // to move just the low double.
7752 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
7754 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
7756 if (Subtarget->hasSSE41())
7757 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7761 // Use dedicated unpack instructions for masks that match their pattern.
7762 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7763 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7764 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7765 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7767 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7768 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
7769 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7772 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7774 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7775 /// the integer unit to minimize domain crossing penalties. However, for blends
7776 /// it falls back to the floating point shuffle operation with appropriate bit
7778 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7779 const X86Subtarget *Subtarget,
7780 SelectionDAG &DAG) {
7782 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7783 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7784 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7785 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7786 ArrayRef<int> Mask = SVOp->getMask();
7787 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7789 if (isSingleInputShuffleMask(Mask)) {
7790 // Check for being able to broadcast a single element.
7791 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
7792 Mask, Subtarget, DAG))
7795 // Straight shuffle of a single input vector. For everything from SSE2
7796 // onward this has a single fast instruction with no scary immediates.
7797 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7798 V1 = DAG.getBitcast(MVT::v4i32, V1);
7799 int WidenedMask[4] = {
7800 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7801 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7802 return DAG.getBitcast(
7804 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7805 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
7807 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
7808 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
7809 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
7810 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
7812 // If we have a blend of two PACKUS operations an the blend aligns with the
7813 // low and half halves, we can just merge the PACKUS operations. This is
7814 // particularly important as it lets us merge shuffles that this routine itself
7816 auto GetPackNode = [](SDValue V) {
7817 while (V.getOpcode() == ISD::BITCAST)
7818 V = V.getOperand(0);
7820 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
7822 if (SDValue V1Pack = GetPackNode(V1))
7823 if (SDValue V2Pack = GetPackNode(V2))
7824 return DAG.getBitcast(MVT::v2i64,
7825 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
7826 Mask[0] == 0 ? V1Pack.getOperand(0)
7827 : V1Pack.getOperand(1),
7828 Mask[1] == 2 ? V2Pack.getOperand(0)
7829 : V2Pack.getOperand(1)));
7831 // Try to use shift instructions.
7833 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
7836 // When loading a scalar and then shuffling it into a vector we can often do
7837 // the insertion cheaply.
7838 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7839 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7841 // Try inverting the insertion since for v2 masks it is easy to do and we
7842 // can't reliably sort the mask one way or the other.
7843 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
7844 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7845 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
7848 // We have different paths for blend lowering, but they all must use the
7849 // *exact* same predicate.
7850 bool IsBlendSupported = Subtarget->hasSSE41();
7851 if (IsBlendSupported)
7852 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
7856 // Use dedicated unpack instructions for masks that match their pattern.
7857 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7858 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7859 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7860 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7862 // Try to use byte rotation instructions.
7863 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7864 if (Subtarget->hasSSSE3())
7865 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7866 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7869 // If we have direct support for blends, we should lower by decomposing into
7870 // a permute. That will be faster than the domain cross.
7871 if (IsBlendSupported)
7872 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
7875 // We implement this with SHUFPD which is pretty lame because it will likely
7876 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7877 // However, all the alternatives are still more cycles and newer chips don't
7878 // have this problem. It would be really nice if x86 had better shuffles here.
7879 V1 = DAG.getBitcast(MVT::v2f64, V1);
7880 V2 = DAG.getBitcast(MVT::v2f64, V2);
7881 return DAG.getBitcast(MVT::v2i64,
7882 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7885 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
7887 /// This is used to disable more specialized lowerings when the shufps lowering
7888 /// will happen to be efficient.
7889 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
7890 // This routine only handles 128-bit shufps.
7891 assert(Mask.size() == 4 && "Unsupported mask size!");
7893 // To lower with a single SHUFPS we need to have the low half and high half
7894 // each requiring a single input.
7895 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
7897 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
7903 /// \brief Lower a vector shuffle using the SHUFPS instruction.
7905 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
7906 /// It makes no assumptions about whether this is the *best* lowering, it simply
7908 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
7909 ArrayRef<int> Mask, SDValue V1,
7910 SDValue V2, SelectionDAG &DAG) {
7911 SDValue LowV = V1, HighV = V2;
7912 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7915 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7917 if (NumV2Elements == 1) {
7919 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7922 // Compute the index adjacent to V2Index and in the same half by toggling
7924 int V2AdjIndex = V2Index ^ 1;
7926 if (Mask[V2AdjIndex] == -1) {
7927 // Handles all the cases where we have a single V2 element and an undef.
7928 // This will only ever happen in the high lanes because we commute the
7929 // vector otherwise.
7931 std::swap(LowV, HighV);
7932 NewMask[V2Index] -= 4;
7934 // Handle the case where the V2 element ends up adjacent to a V1 element.
7935 // To make this work, blend them together as the first step.
7936 int V1Index = V2AdjIndex;
7937 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7938 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
7939 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
7941 // Now proceed to reconstruct the final blend as we have the necessary
7942 // high or low half formed.
7949 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7950 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7952 } else if (NumV2Elements == 2) {
7953 if (Mask[0] < 4 && Mask[1] < 4) {
7954 // Handle the easy case where we have V1 in the low lanes and V2 in the
7958 } else if (Mask[2] < 4 && Mask[3] < 4) {
7959 // We also handle the reversed case because this utility may get called
7960 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
7961 // arrange things in the right direction.
7967 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7968 // trying to place elements directly, just blend them and set up the final
7969 // shuffle to place them.
7971 // The first two blend mask elements are for V1, the second two are for
7973 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7974 Mask[2] < 4 ? Mask[2] : Mask[3],
7975 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7976 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7977 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
7978 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
7980 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7983 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7984 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7985 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7986 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7989 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
7990 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
7993 /// \brief Lower 4-lane 32-bit floating point shuffles.
7995 /// Uses instructions exclusively from the floating point unit to minimize
7996 /// domain crossing penalties, as these are sufficient to implement all v4f32
7998 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7999 const X86Subtarget *Subtarget,
8000 SelectionDAG &DAG) {
8002 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8003 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8004 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8005 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8006 ArrayRef<int> Mask = SVOp->getMask();
8007 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8010 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8012 if (NumV2Elements == 0) {
8013 // Check for being able to broadcast a single element.
8014 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
8015 Mask, Subtarget, DAG))
8018 // Use even/odd duplicate instructions for masks that match their pattern.
8019 if (Subtarget->hasSSE3()) {
8020 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
8021 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
8022 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
8023 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
8026 if (Subtarget->hasAVX()) {
8027 // If we have AVX, we can use VPERMILPS which will allow folding a load
8028 // into the shuffle.
8029 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8030 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8033 // Otherwise, use a straight shuffle of a single input vector. We pass the
8034 // input vector to both operands to simulate this with a SHUFPS.
8035 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8036 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8039 // There are special ways we can lower some single-element blends. However, we
8040 // have custom ways we can lower more complex single-element blends below that
8041 // we defer to if both this and BLENDPS fail to match, so restrict this to
8042 // when the V2 input is targeting element 0 of the mask -- that is the fast
8044 if (NumV2Elements == 1 && Mask[0] >= 4)
8045 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
8046 Mask, Subtarget, DAG))
8049 if (Subtarget->hasSSE41()) {
8050 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8054 // Use INSERTPS if we can complete the shuffle efficiently.
8055 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8058 if (!isSingleSHUFPSMask(Mask))
8059 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
8060 DL, MVT::v4f32, V1, V2, Mask, DAG))
8064 // Use dedicated unpack instructions for masks that match their pattern.
8065 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8066 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8067 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8068 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8069 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8070 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V2, V1);
8071 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8072 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V2, V1);
8074 // Otherwise fall back to a SHUFPS lowering strategy.
8075 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8078 /// \brief Lower 4-lane i32 vector shuffles.
8080 /// We try to handle these with integer-domain shuffles where we can, but for
8081 /// blends we use the floating point domain blend instructions.
8082 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8083 const X86Subtarget *Subtarget,
8084 SelectionDAG &DAG) {
8086 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8087 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8088 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8089 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8090 ArrayRef<int> Mask = SVOp->getMask();
8091 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8093 // Whenever we can lower this as a zext, that instruction is strictly faster
8094 // than any alternative. It also allows us to fold memory operands into the
8095 // shuffle in many cases.
8096 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8097 Mask, Subtarget, DAG))
8101 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8103 if (NumV2Elements == 0) {
8104 // Check for being able to broadcast a single element.
8105 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
8106 Mask, Subtarget, DAG))
8109 // Straight shuffle of a single input vector. For everything from SSE2
8110 // onward this has a single fast instruction with no scary immediates.
8111 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8112 // but we aren't actually going to use the UNPCK instruction because doing
8113 // so prevents folding a load into this instruction or making a copy.
8114 const int UnpackLoMask[] = {0, 0, 1, 1};
8115 const int UnpackHiMask[] = {2, 2, 3, 3};
8116 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
8117 Mask = UnpackLoMask;
8118 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
8119 Mask = UnpackHiMask;
8121 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8122 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8125 // Try to use shift instructions.
8127 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
8130 // There are special ways we can lower some single-element blends.
8131 if (NumV2Elements == 1)
8132 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
8133 Mask, Subtarget, DAG))
8136 // We have different paths for blend lowering, but they all must use the
8137 // *exact* same predicate.
8138 bool IsBlendSupported = Subtarget->hasSSE41();
8139 if (IsBlendSupported)
8140 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8144 if (SDValue Masked =
8145 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
8148 // Use dedicated unpack instructions for masks that match their pattern.
8149 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8150 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8151 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8152 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8153 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8154 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
8155 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8156 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
8158 // Try to use byte rotation instructions.
8159 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8160 if (Subtarget->hasSSSE3())
8161 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8162 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8165 // If we have direct support for blends, we should lower by decomposing into
8166 // a permute. That will be faster than the domain cross.
8167 if (IsBlendSupported)
8168 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
8171 // Try to lower by permuting the inputs into an unpack instruction.
8172 if (SDValue Unpack =
8173 lowerVectorShuffleAsUnpack(DL, MVT::v4i32, V1, V2, Mask, DAG))
8176 // We implement this with SHUFPS because it can blend from two vectors.
8177 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8178 // up the inputs, bypassing domain shift penalties that we would encur if we
8179 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8181 return DAG.getBitcast(
8183 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
8184 DAG.getBitcast(MVT::v4f32, V2), Mask));
8187 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8188 /// shuffle lowering, and the most complex part.
8190 /// The lowering strategy is to try to form pairs of input lanes which are
8191 /// targeted at the same half of the final vector, and then use a dword shuffle
8192 /// to place them onto the right half, and finally unpack the paired lanes into
8193 /// their final position.
8195 /// The exact breakdown of how to form these dword pairs and align them on the
8196 /// correct sides is really tricky. See the comments within the function for
8197 /// more of the details.
8199 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8200 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8201 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8202 /// vector, form the analogous 128-bit 8-element Mask.
8203 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8204 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8205 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8206 assert(VT.getScalarType() == MVT::i16 && "Bad input type!");
8207 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8209 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8210 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8211 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8213 SmallVector<int, 4> LoInputs;
8214 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8215 [](int M) { return M >= 0; });
8216 std::sort(LoInputs.begin(), LoInputs.end());
8217 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8218 SmallVector<int, 4> HiInputs;
8219 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8220 [](int M) { return M >= 0; });
8221 std::sort(HiInputs.begin(), HiInputs.end());
8222 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8224 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8225 int NumHToL = LoInputs.size() - NumLToL;
8227 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8228 int NumHToH = HiInputs.size() - NumLToH;
8229 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8230 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8231 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8232 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8234 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8235 // such inputs we can swap two of the dwords across the half mark and end up
8236 // with <=2 inputs to each half in each half. Once there, we can fall through
8237 // to the generic code below. For example:
8239 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8240 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8242 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8243 // and an existing 2-into-2 on the other half. In this case we may have to
8244 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8245 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8246 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8247 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8248 // half than the one we target for fixing) will be fixed when we re-enter this
8249 // path. We will also combine away any sequence of PSHUFD instructions that
8250 // result into a single instruction. Here is an example of the tricky case:
8252 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8253 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8255 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8257 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8258 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8260 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8261 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8263 // The result is fine to be handled by the generic logic.
8264 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8265 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8266 int AOffset, int BOffset) {
8267 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8268 "Must call this with A having 3 or 1 inputs from the A half.");
8269 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8270 "Must call this with B having 1 or 3 inputs from the B half.");
8271 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8272 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8274 // Compute the index of dword with only one word among the three inputs in
8275 // a half by taking the sum of the half with three inputs and subtracting
8276 // the sum of the actual three inputs. The difference is the remaining
8279 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8280 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8281 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8282 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8283 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8284 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8285 int TripleNonInputIdx =
8286 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8287 TripleDWord = TripleNonInputIdx / 2;
8289 // We use xor with one to compute the adjacent DWord to whichever one the
8291 OneInputDWord = (OneInput / 2) ^ 1;
8293 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8294 // and BToA inputs. If there is also such a problem with the BToB and AToB
8295 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8296 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8297 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8298 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8299 // Compute how many inputs will be flipped by swapping these DWords. We
8301 // to balance this to ensure we don't form a 3-1 shuffle in the other
8303 int NumFlippedAToBInputs =
8304 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8305 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8306 int NumFlippedBToBInputs =
8307 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8308 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8309 if ((NumFlippedAToBInputs == 1 &&
8310 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8311 (NumFlippedBToBInputs == 1 &&
8312 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8313 // We choose whether to fix the A half or B half based on whether that
8314 // half has zero flipped inputs. At zero, we may not be able to fix it
8315 // with that half. We also bias towards fixing the B half because that
8316 // will more commonly be the high half, and we have to bias one way.
8317 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8318 ArrayRef<int> Inputs) {
8319 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8320 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8321 PinnedIdx ^ 1) != Inputs.end();
8322 // Determine whether the free index is in the flipped dword or the
8323 // unflipped dword based on where the pinned index is. We use this bit
8324 // in an xor to conditionally select the adjacent dword.
8325 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8326 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8327 FixFreeIdx) != Inputs.end();
8328 if (IsFixIdxInput == IsFixFreeIdxInput)
8330 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8331 FixFreeIdx) != Inputs.end();
8332 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8333 "We need to be changing the number of flipped inputs!");
8334 int PSHUFHalfMask[] = {0, 1, 2, 3};
8335 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8336 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8338 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8341 if (M != -1 && M == FixIdx)
8343 else if (M != -1 && M == FixFreeIdx)
8346 if (NumFlippedBToBInputs != 0) {
8348 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8349 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8351 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8353 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8354 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8359 int PSHUFDMask[] = {0, 1, 2, 3};
8360 PSHUFDMask[ADWord] = BDWord;
8361 PSHUFDMask[BDWord] = ADWord;
8364 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8365 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8367 // Adjust the mask to match the new locations of A and B.
8369 if (M != -1 && M/2 == ADWord)
8370 M = 2 * BDWord + M % 2;
8371 else if (M != -1 && M/2 == BDWord)
8372 M = 2 * ADWord + M % 2;
8374 // Recurse back into this routine to re-compute state now that this isn't
8375 // a 3 and 1 problem.
8376 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8379 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8380 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8381 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8382 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8384 // At this point there are at most two inputs to the low and high halves from
8385 // each half. That means the inputs can always be grouped into dwords and
8386 // those dwords can then be moved to the correct half with a dword shuffle.
8387 // We use at most one low and one high word shuffle to collect these paired
8388 // inputs into dwords, and finally a dword shuffle to place them.
8389 int PSHUFLMask[4] = {-1, -1, -1, -1};
8390 int PSHUFHMask[4] = {-1, -1, -1, -1};
8391 int PSHUFDMask[4] = {-1, -1, -1, -1};
8393 // First fix the masks for all the inputs that are staying in their
8394 // original halves. This will then dictate the targets of the cross-half
8396 auto fixInPlaceInputs =
8397 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8398 MutableArrayRef<int> SourceHalfMask,
8399 MutableArrayRef<int> HalfMask, int HalfOffset) {
8400 if (InPlaceInputs.empty())
8402 if (InPlaceInputs.size() == 1) {
8403 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8404 InPlaceInputs[0] - HalfOffset;
8405 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8408 if (IncomingInputs.empty()) {
8409 // Just fix all of the in place inputs.
8410 for (int Input : InPlaceInputs) {
8411 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8412 PSHUFDMask[Input / 2] = Input / 2;
8417 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8418 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8419 InPlaceInputs[0] - HalfOffset;
8420 // Put the second input next to the first so that they are packed into
8421 // a dword. We find the adjacent index by toggling the low bit.
8422 int AdjIndex = InPlaceInputs[0] ^ 1;
8423 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8424 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8425 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8427 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8428 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8430 // Now gather the cross-half inputs and place them into a free dword of
8431 // their target half.
8432 // FIXME: This operation could almost certainly be simplified dramatically to
8433 // look more like the 3-1 fixing operation.
8434 auto moveInputsToRightHalf = [&PSHUFDMask](
8435 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8436 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8437 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8439 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8440 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8442 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8444 int LowWord = Word & ~1;
8445 int HighWord = Word | 1;
8446 return isWordClobbered(SourceHalfMask, LowWord) ||
8447 isWordClobbered(SourceHalfMask, HighWord);
8450 if (IncomingInputs.empty())
8453 if (ExistingInputs.empty()) {
8454 // Map any dwords with inputs from them into the right half.
8455 for (int Input : IncomingInputs) {
8456 // If the source half mask maps over the inputs, turn those into
8457 // swaps and use the swapped lane.
8458 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8459 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8460 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8461 Input - SourceOffset;
8462 // We have to swap the uses in our half mask in one sweep.
8463 for (int &M : HalfMask)
8464 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8466 else if (M == Input)
8467 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8469 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8470 Input - SourceOffset &&
8471 "Previous placement doesn't match!");
8473 // Note that this correctly re-maps both when we do a swap and when
8474 // we observe the other side of the swap above. We rely on that to
8475 // avoid swapping the members of the input list directly.
8476 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8479 // Map the input's dword into the correct half.
8480 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8481 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8483 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8485 "Previous placement doesn't match!");
8488 // And just directly shift any other-half mask elements to be same-half
8489 // as we will have mirrored the dword containing the element into the
8490 // same position within that half.
8491 for (int &M : HalfMask)
8492 if (M >= SourceOffset && M < SourceOffset + 4) {
8493 M = M - SourceOffset + DestOffset;
8494 assert(M >= 0 && "This should never wrap below zero!");
8499 // Ensure we have the input in a viable dword of its current half. This
8500 // is particularly tricky because the original position may be clobbered
8501 // by inputs being moved and *staying* in that half.
8502 if (IncomingInputs.size() == 1) {
8503 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8504 int InputFixed = std::find(std::begin(SourceHalfMask),
8505 std::end(SourceHalfMask), -1) -
8506 std::begin(SourceHalfMask) + SourceOffset;
8507 SourceHalfMask[InputFixed - SourceOffset] =
8508 IncomingInputs[0] - SourceOffset;
8509 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8511 IncomingInputs[0] = InputFixed;
8513 } else if (IncomingInputs.size() == 2) {
8514 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8515 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8516 // We have two non-adjacent or clobbered inputs we need to extract from
8517 // the source half. To do this, we need to map them into some adjacent
8518 // dword slot in the source mask.
8519 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8520 IncomingInputs[1] - SourceOffset};
8522 // If there is a free slot in the source half mask adjacent to one of
8523 // the inputs, place the other input in it. We use (Index XOR 1) to
8524 // compute an adjacent index.
8525 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8526 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8527 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8528 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8529 InputsFixed[1] = InputsFixed[0] ^ 1;
8530 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8531 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8532 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8533 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8534 InputsFixed[0] = InputsFixed[1] ^ 1;
8535 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8536 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8537 // The two inputs are in the same DWord but it is clobbered and the
8538 // adjacent DWord isn't used at all. Move both inputs to the free
8540 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8541 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8542 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8543 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8545 // The only way we hit this point is if there is no clobbering
8546 // (because there are no off-half inputs to this half) and there is no
8547 // free slot adjacent to one of the inputs. In this case, we have to
8548 // swap an input with a non-input.
8549 for (int i = 0; i < 4; ++i)
8550 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8551 "We can't handle any clobbers here!");
8552 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8553 "Cannot have adjacent inputs here!");
8555 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8556 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8558 // We also have to update the final source mask in this case because
8559 // it may need to undo the above swap.
8560 for (int &M : FinalSourceHalfMask)
8561 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8562 M = InputsFixed[1] + SourceOffset;
8563 else if (M == InputsFixed[1] + SourceOffset)
8564 M = (InputsFixed[0] ^ 1) + SourceOffset;
8566 InputsFixed[1] = InputsFixed[0] ^ 1;
8569 // Point everything at the fixed inputs.
8570 for (int &M : HalfMask)
8571 if (M == IncomingInputs[0])
8572 M = InputsFixed[0] + SourceOffset;
8573 else if (M == IncomingInputs[1])
8574 M = InputsFixed[1] + SourceOffset;
8576 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8577 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8580 llvm_unreachable("Unhandled input size!");
8583 // Now hoist the DWord down to the right half.
8584 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8585 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8586 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8587 for (int &M : HalfMask)
8588 for (int Input : IncomingInputs)
8590 M = FreeDWord * 2 + Input % 2;
8592 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8593 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8594 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8595 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8597 // Now enact all the shuffles we've computed to move the inputs into their
8599 if (!isNoopShuffleMask(PSHUFLMask))
8600 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8601 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
8602 if (!isNoopShuffleMask(PSHUFHMask))
8603 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8604 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
8605 if (!isNoopShuffleMask(PSHUFDMask))
8608 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8609 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8611 // At this point, each half should contain all its inputs, and we can then
8612 // just shuffle them into their final position.
8613 assert(std::count_if(LoMask.begin(), LoMask.end(),
8614 [](int M) { return M >= 4; }) == 0 &&
8615 "Failed to lift all the high half inputs to the low mask!");
8616 assert(std::count_if(HiMask.begin(), HiMask.end(),
8617 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8618 "Failed to lift all the low half inputs to the high mask!");
8620 // Do a half shuffle for the low mask.
8621 if (!isNoopShuffleMask(LoMask))
8622 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8623 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
8625 // Do a half shuffle with the high mask after shifting its values down.
8626 for (int &M : HiMask)
8629 if (!isNoopShuffleMask(HiMask))
8630 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8631 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
8636 /// \brief Helper to form a PSHUFB-based shuffle+blend.
8637 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
8638 SDValue V2, ArrayRef<int> Mask,
8639 SelectionDAG &DAG, bool &V1InUse,
8641 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8647 int Size = Mask.size();
8648 int Scale = 16 / Size;
8649 for (int i = 0; i < 16; ++i) {
8650 if (Mask[i / Scale] == -1) {
8651 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
8653 const int ZeroMask = 0x80;
8654 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
8656 int V2Idx = Mask[i / Scale] < Size
8658 : (Mask[i / Scale] - Size) * Scale + i % Scale;
8659 if (Zeroable[i / Scale])
8660 V1Idx = V2Idx = ZeroMask;
8661 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
8662 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
8663 V1InUse |= (ZeroMask != V1Idx);
8664 V2InUse |= (ZeroMask != V2Idx);
8669 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8670 DAG.getBitcast(MVT::v16i8, V1),
8671 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
8673 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8674 DAG.getBitcast(MVT::v16i8, V2),
8675 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
8677 // If we need shuffled inputs from both, blend the two.
8679 if (V1InUse && V2InUse)
8680 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
8682 V = V1InUse ? V1 : V2;
8684 // Cast the result back to the correct type.
8685 return DAG.getBitcast(VT, V);
8688 /// \brief Generic lowering of 8-lane i16 shuffles.
8690 /// This handles both single-input shuffles and combined shuffle/blends with
8691 /// two inputs. The single input shuffles are immediately delegated to
8692 /// a dedicated lowering routine.
8694 /// The blends are lowered in one of three fundamental ways. If there are few
8695 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8696 /// of the input is significantly cheaper when lowered as an interleaving of
8697 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8698 /// halves of the inputs separately (making them have relatively few inputs)
8699 /// and then concatenate them.
8700 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8701 const X86Subtarget *Subtarget,
8702 SelectionDAG &DAG) {
8704 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8705 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8706 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8707 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8708 ArrayRef<int> OrigMask = SVOp->getMask();
8709 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8710 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8711 MutableArrayRef<int> Mask(MaskStorage);
8713 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8715 // Whenever we can lower this as a zext, that instruction is strictly faster
8716 // than any alternative.
8717 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8718 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8721 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8723 auto isV2 = [](int M) { return M >= 8; };
8725 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8727 if (NumV2Inputs == 0) {
8728 // Check for being able to broadcast a single element.
8729 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
8730 Mask, Subtarget, DAG))
8733 // Try to use shift instructions.
8735 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
8738 // Use dedicated unpack instructions for masks that match their pattern.
8739 if (isShuffleEquivalent(V1, V1, Mask, {0, 0, 1, 1, 2, 2, 3, 3}))
8740 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V1);
8741 if (isShuffleEquivalent(V1, V1, Mask, {4, 4, 5, 5, 6, 6, 7, 7}))
8742 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V1);
8744 // Try to use byte rotation instructions.
8745 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
8746 Mask, Subtarget, DAG))
8749 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
8753 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
8754 "All single-input shuffles should be canonicalized to be V1-input "
8757 // Try to use shift instructions.
8759 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
8762 // See if we can use SSE4A Extraction / Insertion.
8763 if (Subtarget->hasSSE4A())
8764 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v8i16, V1, V2, Mask, DAG))
8767 // There are special ways we can lower some single-element blends.
8768 if (NumV2Inputs == 1)
8769 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
8770 Mask, Subtarget, DAG))
8773 // We have different paths for blend lowering, but they all must use the
8774 // *exact* same predicate.
8775 bool IsBlendSupported = Subtarget->hasSSE41();
8776 if (IsBlendSupported)
8777 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
8781 if (SDValue Masked =
8782 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
8785 // Use dedicated unpack instructions for masks that match their pattern.
8786 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 2, 10, 3, 11}))
8787 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
8788 if (isShuffleEquivalent(V1, V2, Mask, {4, 12, 5, 13, 6, 14, 7, 15}))
8789 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
8791 // Try to use byte rotation instructions.
8792 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8793 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
8796 if (SDValue BitBlend =
8797 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
8800 if (SDValue Unpack =
8801 lowerVectorShuffleAsUnpack(DL, MVT::v8i16, V1, V2, Mask, DAG))
8804 // If we can't directly blend but can use PSHUFB, that will be better as it
8805 // can both shuffle and set up the inefficient blend.
8806 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
8807 bool V1InUse, V2InUse;
8808 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
8812 // We can always bit-blend if we have to so the fallback strategy is to
8813 // decompose into single-input permutes and blends.
8814 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
8818 /// \brief Check whether a compaction lowering can be done by dropping even
8819 /// elements and compute how many times even elements must be dropped.
8821 /// This handles shuffles which take every Nth element where N is a power of
8822 /// two. Example shuffle masks:
8824 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8825 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8826 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8827 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8828 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8829 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8831 /// Any of these lanes can of course be undef.
8833 /// This routine only supports N <= 3.
8834 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8837 /// \returns N above, or the number of times even elements must be dropped if
8838 /// there is such a number. Otherwise returns zero.
8839 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8840 // Figure out whether we're looping over two inputs or just one.
8841 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8843 // The modulus for the shuffle vector entries is based on whether this is
8844 // a single input or not.
8845 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8846 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8847 "We should only be called with masks with a power-of-2 size!");
8849 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8851 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8852 // and 2^3 simultaneously. This is because we may have ambiguity with
8853 // partially undef inputs.
8854 bool ViableForN[3] = {true, true, true};
8856 for (int i = 0, e = Mask.size(); i < e; ++i) {
8857 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8862 bool IsAnyViable = false;
8863 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8864 if (ViableForN[j]) {
8867 // The shuffle mask must be equal to (i * 2^N) % M.
8868 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8871 ViableForN[j] = false;
8873 // Early exit if we exhaust the possible powers of two.
8878 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8882 // Return 0 as there is no viable power of two.
8886 /// \brief Generic lowering of v16i8 shuffles.
8888 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8889 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8890 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8891 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8893 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8894 const X86Subtarget *Subtarget,
8895 SelectionDAG &DAG) {
8897 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8898 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8899 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8900 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8901 ArrayRef<int> Mask = SVOp->getMask();
8902 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8904 // Try to use shift instructions.
8906 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
8909 // Try to use byte rotation instructions.
8910 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8911 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8914 // Try to use a zext lowering.
8915 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8916 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8919 // See if we can use SSE4A Extraction / Insertion.
8920 if (Subtarget->hasSSE4A())
8921 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v16i8, V1, V2, Mask, DAG))
8925 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
8927 // For single-input shuffles, there are some nicer lowering tricks we can use.
8928 if (NumV2Elements == 0) {
8929 // Check for being able to broadcast a single element.
8930 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
8931 Mask, Subtarget, DAG))
8934 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
8935 // Notably, this handles splat and partial-splat shuffles more efficiently.
8936 // However, it only makes sense if the pre-duplication shuffle simplifies
8937 // things significantly. Currently, this means we need to be able to
8938 // express the pre-duplication shuffle as an i16 shuffle.
8940 // FIXME: We should check for other patterns which can be widened into an
8941 // i16 shuffle as well.
8942 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
8943 for (int i = 0; i < 16; i += 2)
8944 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
8949 auto tryToWidenViaDuplication = [&]() -> SDValue {
8950 if (!canWidenViaDuplication(Mask))
8952 SmallVector<int, 4> LoInputs;
8953 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
8954 [](int M) { return M >= 0 && M < 8; });
8955 std::sort(LoInputs.begin(), LoInputs.end());
8956 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
8958 SmallVector<int, 4> HiInputs;
8959 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
8960 [](int M) { return M >= 8; });
8961 std::sort(HiInputs.begin(), HiInputs.end());
8962 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
8965 bool TargetLo = LoInputs.size() >= HiInputs.size();
8966 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
8967 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
8969 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8970 SmallDenseMap<int, int, 8> LaneMap;
8971 for (int I : InPlaceInputs) {
8972 PreDupI16Shuffle[I/2] = I/2;
8975 int j = TargetLo ? 0 : 4, je = j + 4;
8976 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8977 // Check if j is already a shuffle of this input. This happens when
8978 // there are two adjacent bytes after we move the low one.
8979 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
8980 // If we haven't yet mapped the input, search for a slot into which
8982 while (j < je && PreDupI16Shuffle[j] != -1)
8986 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
8989 // Map this input with the i16 shuffle.
8990 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
8993 // Update the lane map based on the mapping we ended up with.
8994 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
8996 V1 = DAG.getBitcast(
8998 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
8999 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9001 // Unpack the bytes to form the i16s that will be shuffled into place.
9002 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9003 MVT::v16i8, V1, V1);
9005 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9006 for (int i = 0; i < 16; ++i)
9007 if (Mask[i] != -1) {
9008 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9009 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9010 if (PostDupI16Shuffle[i / 2] == -1)
9011 PostDupI16Shuffle[i / 2] = MappedMask;
9013 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9014 "Conflicting entrties in the original shuffle!");
9016 return DAG.getBitcast(
9018 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9019 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9021 if (SDValue V = tryToWidenViaDuplication())
9025 // Use dedicated unpack instructions for masks that match their pattern.
9026 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9027 0, 16, 1, 17, 2, 18, 3, 19,
9029 4, 20, 5, 21, 6, 22, 7, 23}))
9030 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, V2);
9031 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9032 8, 24, 9, 25, 10, 26, 11, 27,
9034 12, 28, 13, 29, 14, 30, 15, 31}))
9035 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, V2);
9037 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9038 // with PSHUFB. It is important to do this before we attempt to generate any
9039 // blends but after all of the single-input lowerings. If the single input
9040 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9041 // want to preserve that and we can DAG combine any longer sequences into
9042 // a PSHUFB in the end. But once we start blending from multiple inputs,
9043 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9044 // and there are *very* few patterns that would actually be faster than the
9045 // PSHUFB approach because of its ability to zero lanes.
9047 // FIXME: The only exceptions to the above are blends which are exact
9048 // interleavings with direct instructions supporting them. We currently don't
9049 // handle those well here.
9050 if (Subtarget->hasSSSE3()) {
9051 bool V1InUse = false;
9052 bool V2InUse = false;
9054 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
9055 DAG, V1InUse, V2InUse);
9057 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
9058 // do so. This avoids using them to handle blends-with-zero which is
9059 // important as a single pshufb is significantly faster for that.
9060 if (V1InUse && V2InUse) {
9061 if (Subtarget->hasSSE41())
9062 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
9063 Mask, Subtarget, DAG))
9066 // We can use an unpack to do the blending rather than an or in some
9067 // cases. Even though the or may be (very minorly) more efficient, we
9068 // preference this lowering because there are common cases where part of
9069 // the complexity of the shuffles goes away when we do the final blend as
9071 // FIXME: It might be worth trying to detect if the unpack-feeding
9072 // shuffles will both be pshufb, in which case we shouldn't bother with
9074 if (SDValue Unpack =
9075 lowerVectorShuffleAsUnpack(DL, MVT::v16i8, V1, V2, Mask, DAG))
9082 // There are special ways we can lower some single-element blends.
9083 if (NumV2Elements == 1)
9084 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
9085 Mask, Subtarget, DAG))
9088 if (SDValue BitBlend =
9089 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
9092 // Check whether a compaction lowering can be done. This handles shuffles
9093 // which take every Nth element for some even N. See the helper function for
9096 // We special case these as they can be particularly efficiently handled with
9097 // the PACKUSB instruction on x86 and they show up in common patterns of
9098 // rearranging bytes to truncate wide elements.
9099 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9100 // NumEvenDrops is the power of two stride of the elements. Another way of
9101 // thinking about it is that we need to drop the even elements this many
9102 // times to get the original input.
9103 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9105 // First we need to zero all the dropped bytes.
9106 assert(NumEvenDrops <= 3 &&
9107 "No support for dropping even elements more than 3 times.");
9108 // We use the mask type to pick which bytes are preserved based on how many
9109 // elements are dropped.
9110 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9111 SDValue ByteClearMask = DAG.getBitcast(
9112 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
9113 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9115 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9117 // Now pack things back together.
9118 V1 = DAG.getBitcast(MVT::v8i16, V1);
9119 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
9120 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9121 for (int i = 1; i < NumEvenDrops; ++i) {
9122 Result = DAG.getBitcast(MVT::v8i16, Result);
9123 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9129 // Handle multi-input cases by blending single-input shuffles.
9130 if (NumV2Elements > 0)
9131 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
9134 // The fallback path for single-input shuffles widens this into two v8i16
9135 // vectors with unpacks, shuffles those, and then pulls them back together
9139 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9140 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9141 for (int i = 0; i < 16; ++i)
9143 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
9145 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9147 SDValue VLoHalf, VHiHalf;
9148 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9149 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9151 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
9152 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9153 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
9154 [](int M) { return M >= 0 && M % 2 == 1; })) {
9155 // Use a mask to drop the high bytes.
9156 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
9157 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
9158 DAG.getConstant(0x00FF, DL, MVT::v8i16));
9160 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
9161 VHiHalf = DAG.getUNDEF(MVT::v8i16);
9163 // Squash the masks to point directly into VLoHalf.
9164 for (int &M : LoBlendMask)
9167 for (int &M : HiBlendMask)
9171 // Otherwise just unpack the low half of V into VLoHalf and the high half into
9172 // VHiHalf so that we can blend them as i16s.
9173 VLoHalf = DAG.getBitcast(
9174 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9175 VHiHalf = DAG.getBitcast(
9176 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9179 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
9180 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
9182 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9185 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9187 /// This routine breaks down the specific type of 128-bit shuffle and
9188 /// dispatches to the lowering routines accordingly.
9189 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9190 MVT VT, const X86Subtarget *Subtarget,
9191 SelectionDAG &DAG) {
9192 switch (VT.SimpleTy) {
9194 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9196 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9198 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9200 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9202 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9204 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9207 llvm_unreachable("Unimplemented!");
9211 /// \brief Helper function to test whether a shuffle mask could be
9212 /// simplified by widening the elements being shuffled.
9214 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9215 /// leaves it in an unspecified state.
9217 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9218 /// shuffle masks. The latter have the special property of a '-2' representing
9219 /// a zero-ed lane of a vector.
9220 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9221 SmallVectorImpl<int> &WidenedMask) {
9222 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9223 // If both elements are undef, its trivial.
9224 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9225 WidenedMask.push_back(SM_SentinelUndef);
9229 // Check for an undef mask and a mask value properly aligned to fit with
9230 // a pair of values. If we find such a case, use the non-undef mask's value.
9231 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9232 WidenedMask.push_back(Mask[i + 1] / 2);
9235 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9236 WidenedMask.push_back(Mask[i] / 2);
9240 // When zeroing, we need to spread the zeroing across both lanes to widen.
9241 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9242 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9243 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9244 WidenedMask.push_back(SM_SentinelZero);
9250 // Finally check if the two mask values are adjacent and aligned with
9252 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9253 WidenedMask.push_back(Mask[i] / 2);
9257 // Otherwise we can't safely widen the elements used in this shuffle.
9260 assert(WidenedMask.size() == Mask.size() / 2 &&
9261 "Incorrect size of mask after widening the elements!");
9266 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9268 /// This routine just extracts two subvectors, shuffles them independently, and
9269 /// then concatenates them back together. This should work effectively with all
9270 /// AVX vector shuffle types.
9271 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9272 SDValue V2, ArrayRef<int> Mask,
9273 SelectionDAG &DAG) {
9274 assert(VT.getSizeInBits() >= 256 &&
9275 "Only for 256-bit or wider vector shuffles!");
9276 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9277 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9279 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9280 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9282 int NumElements = VT.getVectorNumElements();
9283 int SplitNumElements = NumElements / 2;
9284 MVT ScalarVT = VT.getScalarType();
9285 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9287 // Rather than splitting build-vectors, just build two narrower build
9288 // vectors. This helps shuffling with splats and zeros.
9289 auto SplitVector = [&](SDValue V) {
9290 while (V.getOpcode() == ISD::BITCAST)
9291 V = V->getOperand(0);
9293 MVT OrigVT = V.getSimpleValueType();
9294 int OrigNumElements = OrigVT.getVectorNumElements();
9295 int OrigSplitNumElements = OrigNumElements / 2;
9296 MVT OrigScalarVT = OrigVT.getScalarType();
9297 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9301 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9303 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9304 DAG.getIntPtrConstant(0, DL));
9305 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9306 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9309 SmallVector<SDValue, 16> LoOps, HiOps;
9310 for (int i = 0; i < OrigSplitNumElements; ++i) {
9311 LoOps.push_back(BV->getOperand(i));
9312 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9314 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9315 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9317 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
9318 DAG.getBitcast(SplitVT, HiV));
9321 SDValue LoV1, HiV1, LoV2, HiV2;
9322 std::tie(LoV1, HiV1) = SplitVector(V1);
9323 std::tie(LoV2, HiV2) = SplitVector(V2);
9325 // Now create two 4-way blends of these half-width vectors.
9326 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9327 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9328 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9329 for (int i = 0; i < SplitNumElements; ++i) {
9330 int M = HalfMask[i];
9331 if (M >= NumElements) {
9332 if (M >= NumElements + SplitNumElements)
9336 V2BlendMask.push_back(M - NumElements);
9337 V1BlendMask.push_back(-1);
9338 BlendMask.push_back(SplitNumElements + i);
9339 } else if (M >= 0) {
9340 if (M >= SplitNumElements)
9344 V2BlendMask.push_back(-1);
9345 V1BlendMask.push_back(M);
9346 BlendMask.push_back(i);
9348 V2BlendMask.push_back(-1);
9349 V1BlendMask.push_back(-1);
9350 BlendMask.push_back(-1);
9354 // Because the lowering happens after all combining takes place, we need to
9355 // manually combine these blend masks as much as possible so that we create
9356 // a minimal number of high-level vector shuffle nodes.
9358 // First try just blending the halves of V1 or V2.
9359 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9360 return DAG.getUNDEF(SplitVT);
9361 if (!UseLoV2 && !UseHiV2)
9362 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9363 if (!UseLoV1 && !UseHiV1)
9364 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9366 SDValue V1Blend, V2Blend;
9367 if (UseLoV1 && UseHiV1) {
9369 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9371 // We only use half of V1 so map the usage down into the final blend mask.
9372 V1Blend = UseLoV1 ? LoV1 : HiV1;
9373 for (int i = 0; i < SplitNumElements; ++i)
9374 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9375 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9377 if (UseLoV2 && UseHiV2) {
9379 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9381 // We only use half of V2 so map the usage down into the final blend mask.
9382 V2Blend = UseLoV2 ? LoV2 : HiV2;
9383 for (int i = 0; i < SplitNumElements; ++i)
9384 if (BlendMask[i] >= SplitNumElements)
9385 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9387 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9389 SDValue Lo = HalfBlend(LoMask);
9390 SDValue Hi = HalfBlend(HiMask);
9391 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9394 /// \brief Either split a vector in halves or decompose the shuffles and the
9397 /// This is provided as a good fallback for many lowerings of non-single-input
9398 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9399 /// between splitting the shuffle into 128-bit components and stitching those
9400 /// back together vs. extracting the single-input shuffles and blending those
9402 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9403 SDValue V2, ArrayRef<int> Mask,
9404 SelectionDAG &DAG) {
9405 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9406 "lower single-input shuffles as it "
9407 "could then recurse on itself.");
9408 int Size = Mask.size();
9410 // If this can be modeled as a broadcast of two elements followed by a blend,
9411 // prefer that lowering. This is especially important because broadcasts can
9412 // often fold with memory operands.
9413 auto DoBothBroadcast = [&] {
9414 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9417 if (V2BroadcastIdx == -1)
9418 V2BroadcastIdx = M - Size;
9419 else if (M - Size != V2BroadcastIdx)
9421 } else if (M >= 0) {
9422 if (V1BroadcastIdx == -1)
9424 else if (M != V1BroadcastIdx)
9429 if (DoBothBroadcast())
9430 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9433 // If the inputs all stem from a single 128-bit lane of each input, then we
9434 // split them rather than blending because the split will decompose to
9435 // unusually few instructions.
9436 int LaneCount = VT.getSizeInBits() / 128;
9437 int LaneSize = Size / LaneCount;
9438 SmallBitVector LaneInputs[2];
9439 LaneInputs[0].resize(LaneCount, false);
9440 LaneInputs[1].resize(LaneCount, false);
9441 for (int i = 0; i < Size; ++i)
9443 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9444 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9445 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9447 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9448 // that the decomposed single-input shuffles don't end up here.
9449 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9452 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9453 /// a permutation and blend of those lanes.
9455 /// This essentially blends the out-of-lane inputs to each lane into the lane
9456 /// from a permuted copy of the vector. This lowering strategy results in four
9457 /// instructions in the worst case for a single-input cross lane shuffle which
9458 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9459 /// of. Special cases for each particular shuffle pattern should be handled
9460 /// prior to trying this lowering.
9461 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9462 SDValue V1, SDValue V2,
9464 SelectionDAG &DAG) {
9465 // FIXME: This should probably be generalized for 512-bit vectors as well.
9466 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9467 int LaneSize = Mask.size() / 2;
9469 // If there are only inputs from one 128-bit lane, splitting will in fact be
9470 // less expensive. The flags track whether the given lane contains an element
9471 // that crosses to another lane.
9472 bool LaneCrossing[2] = {false, false};
9473 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9474 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9475 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9476 if (!LaneCrossing[0] || !LaneCrossing[1])
9477 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9479 if (isSingleInputShuffleMask(Mask)) {
9480 SmallVector<int, 32> FlippedBlendMask;
9481 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9482 FlippedBlendMask.push_back(
9483 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9485 : Mask[i] % LaneSize +
9486 (i / LaneSize) * LaneSize + Size));
9488 // Flip the vector, and blend the results which should now be in-lane. The
9489 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9490 // 5 for the high source. The value 3 selects the high half of source 2 and
9491 // the value 2 selects the low half of source 2. We only use source 2 to
9492 // allow folding it into a memory operand.
9493 unsigned PERMMask = 3 | 2 << 4;
9494 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9495 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
9496 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9499 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9500 // will be handled by the above logic and a blend of the results, much like
9501 // other patterns in AVX.
9502 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9505 /// \brief Handle lowering 2-lane 128-bit shuffles.
9506 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9507 SDValue V2, ArrayRef<int> Mask,
9508 const X86Subtarget *Subtarget,
9509 SelectionDAG &DAG) {
9510 // TODO: If minimizing size and one of the inputs is a zero vector and the
9511 // the zero vector has only one use, we could use a VPERM2X128 to save the
9512 // instruction bytes needed to explicitly generate the zero vector.
9514 // Blends are faster and handle all the non-lane-crossing cases.
9515 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9519 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
9520 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
9522 // If either input operand is a zero vector, use VPERM2X128 because its mask
9523 // allows us to replace the zero input with an implicit zero.
9524 if (!IsV1Zero && !IsV2Zero) {
9525 // Check for patterns which can be matched with a single insert of a 128-bit
9527 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
9528 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
9529 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9530 VT.getVectorNumElements() / 2);
9531 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9532 DAG.getIntPtrConstant(0, DL));
9533 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9534 OnlyUsesV1 ? V1 : V2,
9535 DAG.getIntPtrConstant(0, DL));
9536 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9540 // Otherwise form a 128-bit permutation. After accounting for undefs,
9541 // convert the 64-bit shuffle mask selection values into 128-bit
9542 // selection bits by dividing the indexes by 2 and shifting into positions
9543 // defined by a vperm2*128 instruction's immediate control byte.
9545 // The immediate permute control byte looks like this:
9546 // [1:0] - select 128 bits from sources for low half of destination
9548 // [3] - zero low half of destination
9549 // [5:4] - select 128 bits from sources for high half of destination
9551 // [7] - zero high half of destination
9553 int MaskLO = Mask[0];
9554 if (MaskLO == SM_SentinelUndef)
9555 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
9557 int MaskHI = Mask[2];
9558 if (MaskHI == SM_SentinelUndef)
9559 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
9561 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
9563 // If either input is a zero vector, replace it with an undef input.
9564 // Shuffle mask values < 4 are selecting elements of V1.
9565 // Shuffle mask values >= 4 are selecting elements of V2.
9566 // Adjust each half of the permute mask by clearing the half that was
9567 // selecting the zero vector and setting the zero mask bit.
9569 V1 = DAG.getUNDEF(VT);
9571 PermMask = (PermMask & 0xf0) | 0x08;
9573 PermMask = (PermMask & 0x0f) | 0x80;
9576 V2 = DAG.getUNDEF(VT);
9578 PermMask = (PermMask & 0xf0) | 0x08;
9580 PermMask = (PermMask & 0x0f) | 0x80;
9583 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9584 DAG.getConstant(PermMask, DL, MVT::i8));
9587 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
9588 /// shuffling each lane.
9590 /// This will only succeed when the result of fixing the 128-bit lanes results
9591 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
9592 /// each 128-bit lanes. This handles many cases where we can quickly blend away
9593 /// the lane crosses early and then use simpler shuffles within each lane.
9595 /// FIXME: It might be worthwhile at some point to support this without
9596 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
9597 /// in x86 only floating point has interesting non-repeating shuffles, and even
9598 /// those are still *marginally* more expensive.
9599 static SDValue lowerVectorShuffleByMerging128BitLanes(
9600 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
9601 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
9602 assert(!isSingleInputShuffleMask(Mask) &&
9603 "This is only useful with multiple inputs.");
9605 int Size = Mask.size();
9606 int LaneSize = 128 / VT.getScalarSizeInBits();
9607 int NumLanes = Size / LaneSize;
9608 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
9610 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
9611 // check whether the in-128-bit lane shuffles share a repeating pattern.
9612 SmallVector<int, 4> Lanes;
9613 Lanes.resize(NumLanes, -1);
9614 SmallVector<int, 4> InLaneMask;
9615 InLaneMask.resize(LaneSize, -1);
9616 for (int i = 0; i < Size; ++i) {
9620 int j = i / LaneSize;
9623 // First entry we've seen for this lane.
9624 Lanes[j] = Mask[i] / LaneSize;
9625 } else if (Lanes[j] != Mask[i] / LaneSize) {
9626 // This doesn't match the lane selected previously!
9630 // Check that within each lane we have a consistent shuffle mask.
9631 int k = i % LaneSize;
9632 if (InLaneMask[k] < 0) {
9633 InLaneMask[k] = Mask[i] % LaneSize;
9634 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
9635 // This doesn't fit a repeating in-lane mask.
9640 // First shuffle the lanes into place.
9641 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
9642 VT.getSizeInBits() / 64);
9643 SmallVector<int, 8> LaneMask;
9644 LaneMask.resize(NumLanes * 2, -1);
9645 for (int i = 0; i < NumLanes; ++i)
9646 if (Lanes[i] >= 0) {
9647 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
9648 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
9651 V1 = DAG.getBitcast(LaneVT, V1);
9652 V2 = DAG.getBitcast(LaneVT, V2);
9653 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
9655 // Cast it back to the type we actually want.
9656 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
9658 // Now do a simple shuffle that isn't lane crossing.
9659 SmallVector<int, 8> NewMask;
9660 NewMask.resize(Size, -1);
9661 for (int i = 0; i < Size; ++i)
9663 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
9664 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
9665 "Must not introduce lane crosses at this point!");
9667 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
9670 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
9673 /// This returns true if the elements from a particular input are already in the
9674 /// slot required by the given mask and require no permutation.
9675 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
9676 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
9677 int Size = Mask.size();
9678 for (int i = 0; i < Size; ++i)
9679 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
9685 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
9686 ArrayRef<int> Mask, SDValue V1,
9687 SDValue V2, SelectionDAG &DAG) {
9689 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
9690 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
9691 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
9692 int NumElts = VT.getVectorNumElements();
9693 bool ShufpdMask = true;
9694 bool CommutableMask = true;
9695 unsigned Immediate = 0;
9696 for (int i = 0; i < NumElts; ++i) {
9699 int Val = (i & 6) + NumElts * (i & 1);
9700 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
9701 if (Mask[i] < Val || Mask[i] > Val + 1)
9703 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
9704 CommutableMask = false;
9705 Immediate |= (Mask[i] % 2) << i;
9708 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
9709 DAG.getConstant(Immediate, DL, MVT::i8));
9711 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
9712 DAG.getConstant(Immediate, DL, MVT::i8));
9716 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9718 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9719 /// isn't available.
9720 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9721 const X86Subtarget *Subtarget,
9722 SelectionDAG &DAG) {
9724 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9725 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9726 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9727 ArrayRef<int> Mask = SVOp->getMask();
9728 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9730 SmallVector<int, 4> WidenedMask;
9731 if (canWidenShuffleElements(Mask, WidenedMask))
9732 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
9735 if (isSingleInputShuffleMask(Mask)) {
9736 // Check for being able to broadcast a single element.
9737 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
9738 Mask, Subtarget, DAG))
9741 // Use low duplicate instructions for masks that match their pattern.
9742 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
9743 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
9745 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9746 // Non-half-crossing single input shuffles can be lowerid with an
9747 // interleaved permutation.
9748 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9749 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9750 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9751 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
9754 // With AVX2 we have direct support for this permutation.
9755 if (Subtarget->hasAVX2())
9756 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9757 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
9759 // Otherwise, fall back.
9760 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9764 // X86 has dedicated unpack instructions that can handle specific blend
9765 // operations: UNPCKH and UNPCKL.
9766 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9767 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9768 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9769 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9770 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9771 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
9772 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9773 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
9775 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9779 // Check if the blend happens to exactly fit that of SHUFPD.
9781 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
9784 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9785 // shuffle. However, if we have AVX2 and either inputs are already in place,
9786 // we will be able to shuffle even across lanes the other input in a single
9787 // instruction so skip this pattern.
9788 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9789 isShuffleMaskInputInPlace(1, Mask))))
9790 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9791 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
9794 // If we have AVX2 then we always want to lower with a blend because an v4 we
9795 // can fully permute the elements.
9796 if (Subtarget->hasAVX2())
9797 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9800 // Otherwise fall back on generic lowering.
9801 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
9804 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9806 /// This routine is only called when we have AVX2 and thus a reasonable
9807 /// instruction set for v4i64 shuffling..
9808 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9809 const X86Subtarget *Subtarget,
9810 SelectionDAG &DAG) {
9812 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9813 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9814 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9815 ArrayRef<int> Mask = SVOp->getMask();
9816 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9817 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9819 SmallVector<int, 4> WidenedMask;
9820 if (canWidenShuffleElements(Mask, WidenedMask))
9821 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
9824 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9828 // Check for being able to broadcast a single element.
9829 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
9830 Mask, Subtarget, DAG))
9833 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9834 // use lower latency instructions that will operate on both 128-bit lanes.
9835 SmallVector<int, 2> RepeatedMask;
9836 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9837 if (isSingleInputShuffleMask(Mask)) {
9838 int PSHUFDMask[] = {-1, -1, -1, -1};
9839 for (int i = 0; i < 2; ++i)
9840 if (RepeatedMask[i] >= 0) {
9841 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9842 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9844 return DAG.getBitcast(
9846 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9847 DAG.getBitcast(MVT::v8i32, V1),
9848 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9852 // AVX2 provides a direct instruction for permuting a single input across
9854 if (isSingleInputShuffleMask(Mask))
9855 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9856 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
9858 // Try to use shift instructions.
9860 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
9863 // Use dedicated unpack instructions for masks that match their pattern.
9864 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9865 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9866 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9867 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9868 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9869 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V2, V1);
9870 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9871 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V2, V1);
9873 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9874 // shuffle. However, if we have AVX2 and either inputs are already in place,
9875 // we will be able to shuffle even across lanes the other input in a single
9876 // instruction so skip this pattern.
9877 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9878 isShuffleMaskInputInPlace(1, Mask))))
9879 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9880 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
9883 // Otherwise fall back on generic blend lowering.
9884 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9888 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9890 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9891 /// isn't available.
9892 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9893 const X86Subtarget *Subtarget,
9894 SelectionDAG &DAG) {
9896 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9897 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9898 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9899 ArrayRef<int> Mask = SVOp->getMask();
9900 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9902 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9906 // Check for being able to broadcast a single element.
9907 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
9908 Mask, Subtarget, DAG))
9911 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9912 // options to efficiently lower the shuffle.
9913 SmallVector<int, 4> RepeatedMask;
9914 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9915 assert(RepeatedMask.size() == 4 &&
9916 "Repeated masks must be half the mask width!");
9918 // Use even/odd duplicate instructions for masks that match their pattern.
9919 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
9920 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
9921 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
9922 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
9924 if (isSingleInputShuffleMask(Mask))
9925 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9926 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
9928 // Use dedicated unpack instructions for masks that match their pattern.
9929 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9930 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9931 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9932 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9933 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9934 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V2, V1);
9935 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9936 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V2, V1);
9938 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9939 // have already handled any direct blends. We also need to squash the
9940 // repeated mask into a simulated v4f32 mask.
9941 for (int i = 0; i < 4; ++i)
9942 if (RepeatedMask[i] >= 8)
9943 RepeatedMask[i] -= 4;
9944 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
9947 // If we have a single input shuffle with different shuffle patterns in the
9948 // two 128-bit lanes use the variable mask to VPERMILPS.
9949 if (isSingleInputShuffleMask(Mask)) {
9950 SDValue VPermMask[8];
9951 for (int i = 0; i < 8; ++i)
9952 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9953 : DAG.getConstant(Mask[i], DL, MVT::i32);
9954 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9956 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9957 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9959 if (Subtarget->hasAVX2())
9961 X86ISD::VPERMV, DL, MVT::v8f32,
9962 DAG.getBitcast(MVT::v8f32, DAG.getNode(ISD::BUILD_VECTOR, DL,
9963 MVT::v8i32, VPermMask)),
9966 // Otherwise, fall back.
9967 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
9971 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9973 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9974 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
9977 // If we have AVX2 then we always want to lower with a blend because at v8 we
9978 // can fully permute the elements.
9979 if (Subtarget->hasAVX2())
9980 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9983 // Otherwise fall back on generic lowering.
9984 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
9987 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9989 /// This routine is only called when we have AVX2 and thus a reasonable
9990 /// instruction set for v8i32 shuffling..
9991 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9992 const X86Subtarget *Subtarget,
9993 SelectionDAG &DAG) {
9995 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9996 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9997 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9998 ArrayRef<int> Mask = SVOp->getMask();
9999 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10000 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10002 // Whenever we can lower this as a zext, that instruction is strictly faster
10003 // than any alternative. It also allows us to fold memory operands into the
10004 // shuffle in many cases.
10005 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
10006 Mask, Subtarget, DAG))
10009 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10013 // Check for being able to broadcast a single element.
10014 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
10015 Mask, Subtarget, DAG))
10018 // If the shuffle mask is repeated in each 128-bit lane we can use more
10019 // efficient instructions that mirror the shuffles across the two 128-bit
10021 SmallVector<int, 4> RepeatedMask;
10022 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10023 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10024 if (isSingleInputShuffleMask(Mask))
10025 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10026 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10028 // Use dedicated unpack instructions for masks that match their pattern.
10029 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
10030 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10031 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
10032 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10033 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
10034 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V2, V1);
10035 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
10036 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V2, V1);
10039 // Try to use shift instructions.
10040 if (SDValue Shift =
10041 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
10044 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10045 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10048 // If the shuffle patterns aren't repeated but it is a single input, directly
10049 // generate a cross-lane VPERMD instruction.
10050 if (isSingleInputShuffleMask(Mask)) {
10051 SDValue VPermMask[8];
10052 for (int i = 0; i < 8; ++i)
10053 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10054 : DAG.getConstant(Mask[i], DL, MVT::i32);
10055 return DAG.getNode(
10056 X86ISD::VPERMV, DL, MVT::v8i32,
10057 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10060 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10062 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10063 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10066 // Otherwise fall back on generic blend lowering.
10067 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10071 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10073 /// This routine is only called when we have AVX2 and thus a reasonable
10074 /// instruction set for v16i16 shuffling..
10075 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10076 const X86Subtarget *Subtarget,
10077 SelectionDAG &DAG) {
10079 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10080 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10081 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10082 ArrayRef<int> Mask = SVOp->getMask();
10083 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10084 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10086 // Whenever we can lower this as a zext, that instruction is strictly faster
10087 // than any alternative. It also allows us to fold memory operands into the
10088 // shuffle in many cases.
10089 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
10090 Mask, Subtarget, DAG))
10093 // Check for being able to broadcast a single element.
10094 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
10095 Mask, Subtarget, DAG))
10098 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10102 // Use dedicated unpack instructions for masks that match their pattern.
10103 if (isShuffleEquivalent(V1, V2, Mask,
10104 {// First 128-bit lane:
10105 0, 16, 1, 17, 2, 18, 3, 19,
10106 // Second 128-bit lane:
10107 8, 24, 9, 25, 10, 26, 11, 27}))
10108 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10109 if (isShuffleEquivalent(V1, V2, Mask,
10110 {// First 128-bit lane:
10111 4, 20, 5, 21, 6, 22, 7, 23,
10112 // Second 128-bit lane:
10113 12, 28, 13, 29, 14, 30, 15, 31}))
10114 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10116 // Try to use shift instructions.
10117 if (SDValue Shift =
10118 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
10121 // Try to use byte rotation instructions.
10122 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10123 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10126 if (isSingleInputShuffleMask(Mask)) {
10127 // There are no generalized cross-lane shuffle operations available on i16
10129 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10130 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10133 SmallVector<int, 8> RepeatedMask;
10134 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
10135 // As this is a single-input shuffle, the repeated mask should be
10136 // a strictly valid v8i16 mask that we can pass through to the v8i16
10137 // lowering to handle even the v16 case.
10138 return lowerV8I16GeneralSingleInputVectorShuffle(
10139 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
10142 SDValue PSHUFBMask[32];
10143 for (int i = 0; i < 16; ++i) {
10144 if (Mask[i] == -1) {
10145 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10149 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10150 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10151 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
10152 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
10154 return DAG.getBitcast(MVT::v16i16,
10155 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
10156 DAG.getBitcast(MVT::v32i8, V1),
10157 DAG.getNode(ISD::BUILD_VECTOR, DL,
10158 MVT::v32i8, PSHUFBMask)));
10161 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10163 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10164 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10167 // Otherwise fall back on generic lowering.
10168 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10171 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10173 /// This routine is only called when we have AVX2 and thus a reasonable
10174 /// instruction set for v32i8 shuffling..
10175 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10176 const X86Subtarget *Subtarget,
10177 SelectionDAG &DAG) {
10179 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10180 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10181 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10182 ArrayRef<int> Mask = SVOp->getMask();
10183 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10184 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10186 // Whenever we can lower this as a zext, that instruction is strictly faster
10187 // than any alternative. It also allows us to fold memory operands into the
10188 // shuffle in many cases.
10189 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
10190 Mask, Subtarget, DAG))
10193 // Check for being able to broadcast a single element.
10194 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
10195 Mask, Subtarget, DAG))
10198 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10202 // Use dedicated unpack instructions for masks that match their pattern.
10203 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10205 if (isShuffleEquivalent(
10207 {// First 128-bit lane:
10208 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10209 // Second 128-bit lane:
10210 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55}))
10211 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10212 if (isShuffleEquivalent(
10214 {// First 128-bit lane:
10215 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10216 // Second 128-bit lane:
10217 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63}))
10218 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10220 // Try to use shift instructions.
10221 if (SDValue Shift =
10222 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10225 // Try to use byte rotation instructions.
10226 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10227 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10230 if (isSingleInputShuffleMask(Mask)) {
10231 // There are no generalized cross-lane shuffle operations available on i8
10233 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10234 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10237 SDValue PSHUFBMask[32];
10238 for (int i = 0; i < 32; ++i)
10241 ? DAG.getUNDEF(MVT::i8)
10242 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10245 return DAG.getNode(
10246 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10247 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10250 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10252 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10253 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10256 // Otherwise fall back on generic lowering.
10257 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10260 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10262 /// This routine either breaks down the specific type of a 256-bit x86 vector
10263 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10264 /// together based on the available instructions.
10265 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10266 MVT VT, const X86Subtarget *Subtarget,
10267 SelectionDAG &DAG) {
10269 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10270 ArrayRef<int> Mask = SVOp->getMask();
10272 // If we have a single input to the zero element, insert that into V1 if we
10273 // can do so cheaply.
10274 int NumElts = VT.getVectorNumElements();
10275 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10276 return M >= NumElts;
10279 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10280 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10281 DL, VT, V1, V2, Mask, Subtarget, DAG))
10284 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10285 // check for those subtargets here and avoid much of the subtarget querying in
10286 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10287 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10288 // floating point types there eventually, just immediately cast everything to
10289 // a float and operate entirely in that domain.
10290 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10291 int ElementBits = VT.getScalarSizeInBits();
10292 if (ElementBits < 32)
10293 // No floating point type available, decompose into 128-bit vectors.
10294 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10296 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10297 VT.getVectorNumElements());
10298 V1 = DAG.getBitcast(FpVT, V1);
10299 V2 = DAG.getBitcast(FpVT, V2);
10300 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10303 switch (VT.SimpleTy) {
10305 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10307 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10309 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10311 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10313 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10315 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10318 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10322 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10323 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10324 const X86Subtarget *Subtarget,
10325 SelectionDAG &DAG) {
10327 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10328 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10329 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10330 ArrayRef<int> Mask = SVOp->getMask();
10331 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10333 // X86 has dedicated unpack instructions that can handle specific blend
10334 // operations: UNPCKH and UNPCKL.
10335 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
10336 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f64, V1, V2);
10337 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
10338 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f64, V1, V2);
10340 // FIXME: Implement direct support for this type!
10341 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10344 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10345 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10346 const X86Subtarget *Subtarget,
10347 SelectionDAG &DAG) {
10349 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10350 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10351 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10352 ArrayRef<int> Mask = SVOp->getMask();
10353 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10355 // Use dedicated unpack instructions for masks that match their pattern.
10356 if (isShuffleEquivalent(V1, V2, Mask,
10357 {// First 128-bit lane.
10358 0, 16, 1, 17, 4, 20, 5, 21,
10359 // Second 128-bit lane.
10360 8, 24, 9, 25, 12, 28, 13, 29}))
10361 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16f32, V1, V2);
10362 if (isShuffleEquivalent(V1, V2, Mask,
10363 {// First 128-bit lane.
10364 2, 18, 3, 19, 6, 22, 7, 23,
10365 // Second 128-bit lane.
10366 10, 26, 11, 27, 14, 30, 15, 31}))
10367 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16f32, V1, V2);
10369 // FIXME: Implement direct support for this type!
10370 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10373 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10374 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10375 const X86Subtarget *Subtarget,
10376 SelectionDAG &DAG) {
10378 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10379 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10380 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10381 ArrayRef<int> Mask = SVOp->getMask();
10382 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10384 // X86 has dedicated unpack instructions that can handle specific blend
10385 // operations: UNPCKH and UNPCKL.
10386 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
10387 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i64, V1, V2);
10388 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
10389 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i64, V1, V2);
10391 // FIXME: Implement direct support for this type!
10392 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10395 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10396 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10397 const X86Subtarget *Subtarget,
10398 SelectionDAG &DAG) {
10400 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10401 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10402 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10403 ArrayRef<int> Mask = SVOp->getMask();
10404 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10406 // Use dedicated unpack instructions for masks that match their pattern.
10407 if (isShuffleEquivalent(V1, V2, Mask,
10408 {// First 128-bit lane.
10409 0, 16, 1, 17, 4, 20, 5, 21,
10410 // Second 128-bit lane.
10411 8, 24, 9, 25, 12, 28, 13, 29}))
10412 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i32, V1, V2);
10413 if (isShuffleEquivalent(V1, V2, Mask,
10414 {// First 128-bit lane.
10415 2, 18, 3, 19, 6, 22, 7, 23,
10416 // Second 128-bit lane.
10417 10, 26, 11, 27, 14, 30, 15, 31}))
10418 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i32, V1, V2);
10420 // FIXME: Implement direct support for this type!
10421 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10424 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10425 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10426 const X86Subtarget *Subtarget,
10427 SelectionDAG &DAG) {
10429 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10430 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10431 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10432 ArrayRef<int> Mask = SVOp->getMask();
10433 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10434 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10436 // FIXME: Implement direct support for this type!
10437 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10440 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10441 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10442 const X86Subtarget *Subtarget,
10443 SelectionDAG &DAG) {
10445 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10446 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10447 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10448 ArrayRef<int> Mask = SVOp->getMask();
10449 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10450 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10452 // FIXME: Implement direct support for this type!
10453 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10456 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10458 /// This routine either breaks down the specific type of a 512-bit x86 vector
10459 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10460 /// together based on the available instructions.
10461 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10462 MVT VT, const X86Subtarget *Subtarget,
10463 SelectionDAG &DAG) {
10465 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10466 ArrayRef<int> Mask = SVOp->getMask();
10467 assert(Subtarget->hasAVX512() &&
10468 "Cannot lower 512-bit vectors w/ basic ISA!");
10470 // Check for being able to broadcast a single element.
10471 if (SDValue Broadcast =
10472 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10475 // Dispatch to each element type for lowering. If we don't have supprot for
10476 // specific element type shuffles at 512 bits, immediately split them and
10477 // lower them. Each lowering routine of a given type is allowed to assume that
10478 // the requisite ISA extensions for that element type are available.
10479 switch (VT.SimpleTy) {
10481 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10483 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10485 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10487 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10489 if (Subtarget->hasBWI())
10490 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10493 if (Subtarget->hasBWI())
10494 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10498 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10501 // Otherwise fall back on splitting.
10502 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10505 /// \brief Top-level lowering for x86 vector shuffles.
10507 /// This handles decomposition, canonicalization, and lowering of all x86
10508 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10509 /// above in helper routines. The canonicalization attempts to widen shuffles
10510 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10511 /// s.t. only one of the two inputs needs to be tested, etc.
10512 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10513 SelectionDAG &DAG) {
10514 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10515 ArrayRef<int> Mask = SVOp->getMask();
10516 SDValue V1 = Op.getOperand(0);
10517 SDValue V2 = Op.getOperand(1);
10518 MVT VT = Op.getSimpleValueType();
10519 int NumElements = VT.getVectorNumElements();
10522 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10524 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10525 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10526 if (V1IsUndef && V2IsUndef)
10527 return DAG.getUNDEF(VT);
10529 // When we create a shuffle node we put the UNDEF node to second operand,
10530 // but in some cases the first operand may be transformed to UNDEF.
10531 // In this case we should just commute the node.
10533 return DAG.getCommutedVectorShuffle(*SVOp);
10535 // Check for non-undef masks pointing at an undef vector and make the masks
10536 // undef as well. This makes it easier to match the shuffle based solely on
10540 if (M >= NumElements) {
10541 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10542 for (int &M : NewMask)
10543 if (M >= NumElements)
10545 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10548 // We actually see shuffles that are entirely re-arrangements of a set of
10549 // zero inputs. This mostly happens while decomposing complex shuffles into
10550 // simple ones. Directly lower these as a buildvector of zeros.
10551 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
10552 if (Zeroable.all())
10553 return getZeroVector(VT, Subtarget, DAG, dl);
10555 // Try to collapse shuffles into using a vector type with fewer elements but
10556 // wider element types. We cap this to not form integers or floating point
10557 // elements wider than 64 bits, but it might be interesting to form i128
10558 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10559 SmallVector<int, 16> WidenedMask;
10560 if (VT.getScalarSizeInBits() < 64 &&
10561 canWidenShuffleElements(Mask, WidenedMask)) {
10562 MVT NewEltVT = VT.isFloatingPoint()
10563 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10564 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10565 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10566 // Make sure that the new vector type is legal. For example, v2f64 isn't
10568 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10569 V1 = DAG.getBitcast(NewVT, V1);
10570 V2 = DAG.getBitcast(NewVT, V2);
10571 return DAG.getBitcast(
10572 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10576 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10577 for (int M : SVOp->getMask())
10579 ++NumUndefElements;
10580 else if (M < NumElements)
10585 // Commute the shuffle as needed such that more elements come from V1 than
10586 // V2. This allows us to match the shuffle pattern strictly on how many
10587 // elements come from V1 without handling the symmetric cases.
10588 if (NumV2Elements > NumV1Elements)
10589 return DAG.getCommutedVectorShuffle(*SVOp);
10591 // When the number of V1 and V2 elements are the same, try to minimize the
10592 // number of uses of V2 in the low half of the vector. When that is tied,
10593 // ensure that the sum of indices for V1 is equal to or lower than the sum
10594 // indices for V2. When those are equal, try to ensure that the number of odd
10595 // indices for V1 is lower than the number of odd indices for V2.
10596 if (NumV1Elements == NumV2Elements) {
10597 int LowV1Elements = 0, LowV2Elements = 0;
10598 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10599 if (M >= NumElements)
10603 if (LowV2Elements > LowV1Elements) {
10604 return DAG.getCommutedVectorShuffle(*SVOp);
10605 } else if (LowV2Elements == LowV1Elements) {
10606 int SumV1Indices = 0, SumV2Indices = 0;
10607 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10608 if (SVOp->getMask()[i] >= NumElements)
10610 else if (SVOp->getMask()[i] >= 0)
10612 if (SumV2Indices < SumV1Indices) {
10613 return DAG.getCommutedVectorShuffle(*SVOp);
10614 } else if (SumV2Indices == SumV1Indices) {
10615 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10616 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10617 if (SVOp->getMask()[i] >= NumElements)
10618 NumV2OddIndices += i % 2;
10619 else if (SVOp->getMask()[i] >= 0)
10620 NumV1OddIndices += i % 2;
10621 if (NumV2OddIndices < NumV1OddIndices)
10622 return DAG.getCommutedVectorShuffle(*SVOp);
10627 // For each vector width, delegate to a specialized lowering routine.
10628 if (VT.getSizeInBits() == 128)
10629 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10631 if (VT.getSizeInBits() == 256)
10632 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10634 // Force AVX-512 vectors to be scalarized for now.
10635 // FIXME: Implement AVX-512 support!
10636 if (VT.getSizeInBits() == 512)
10637 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10639 llvm_unreachable("Unimplemented!");
10642 // This function assumes its argument is a BUILD_VECTOR of constants or
10643 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
10645 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
10646 unsigned &MaskValue) {
10648 unsigned NumElems = BuildVector->getNumOperands();
10649 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10650 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10651 unsigned NumElemsInLane = NumElems / NumLanes;
10653 // Blend for v16i16 should be symetric for the both lanes.
10654 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10655 SDValue EltCond = BuildVector->getOperand(i);
10656 SDValue SndLaneEltCond =
10657 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
10659 int Lane1Cond = -1, Lane2Cond = -1;
10660 if (isa<ConstantSDNode>(EltCond))
10661 Lane1Cond = !isZero(EltCond);
10662 if (isa<ConstantSDNode>(SndLaneEltCond))
10663 Lane2Cond = !isZero(SndLaneEltCond);
10665 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
10666 // Lane1Cond != 0, means we want the first argument.
10667 // Lane1Cond == 0, means we want the second argument.
10668 // The encoding of this argument is 0 for the first argument, 1
10669 // for the second. Therefore, invert the condition.
10670 MaskValue |= !Lane1Cond << i;
10671 else if (Lane1Cond < 0)
10672 MaskValue |= !Lane2Cond << i;
10679 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
10680 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
10681 const X86Subtarget *Subtarget,
10682 SelectionDAG &DAG) {
10683 SDValue Cond = Op.getOperand(0);
10684 SDValue LHS = Op.getOperand(1);
10685 SDValue RHS = Op.getOperand(2);
10687 MVT VT = Op.getSimpleValueType();
10689 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
10691 auto *CondBV = cast<BuildVectorSDNode>(Cond);
10693 // Only non-legal VSELECTs reach this lowering, convert those into generic
10694 // shuffles and re-use the shuffle lowering path for blends.
10695 SmallVector<int, 32> Mask;
10696 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
10697 SDValue CondElt = CondBV->getOperand(i);
10699 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
10701 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
10704 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
10705 // A vselect where all conditions and data are constants can be optimized into
10706 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
10707 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
10708 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
10709 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
10712 // Try to lower this to a blend-style vector shuffle. This can handle all
10713 // constant condition cases.
10714 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
10717 // Variable blends are only legal from SSE4.1 onward.
10718 if (!Subtarget->hasSSE41())
10721 // Only some types will be legal on some subtargets. If we can emit a legal
10722 // VSELECT-matching blend, return Op, and but if we need to expand, return
10724 switch (Op.getSimpleValueType().SimpleTy) {
10726 // Most of the vector types have blends past SSE4.1.
10730 // The byte blends for AVX vectors were introduced only in AVX2.
10731 if (Subtarget->hasAVX2())
10738 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
10739 if (Subtarget->hasBWI() && Subtarget->hasVLX())
10742 // FIXME: We should custom lower this by fixing the condition and using i8
10748 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
10749 MVT VT = Op.getSimpleValueType();
10752 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
10755 if (VT.getSizeInBits() == 8) {
10756 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
10757 Op.getOperand(0), Op.getOperand(1));
10758 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10759 DAG.getValueType(VT));
10760 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10763 if (VT.getSizeInBits() == 16) {
10764 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10765 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
10767 return DAG.getNode(
10768 ISD::TRUNCATE, dl, MVT::i16,
10769 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10770 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
10771 Op.getOperand(1)));
10772 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
10773 Op.getOperand(0), Op.getOperand(1));
10774 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10775 DAG.getValueType(VT));
10776 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10779 if (VT == MVT::f32) {
10780 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
10781 // the result back to FR32 register. It's only worth matching if the
10782 // result has a single use which is a store or a bitcast to i32. And in
10783 // the case of a store, it's not worth it if the index is a constant 0,
10784 // because a MOVSSmr can be used instead, which is smaller and faster.
10785 if (!Op.hasOneUse())
10787 SDNode *User = *Op.getNode()->use_begin();
10788 if ((User->getOpcode() != ISD::STORE ||
10789 (isa<ConstantSDNode>(Op.getOperand(1)) &&
10790 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
10791 (User->getOpcode() != ISD::BITCAST ||
10792 User->getValueType(0) != MVT::i32))
10794 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10795 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
10797 return DAG.getBitcast(MVT::f32, Extract);
10800 if (VT == MVT::i32 || VT == MVT::i64) {
10801 // ExtractPS/pextrq works with constant index.
10802 if (isa<ConstantSDNode>(Op.getOperand(1)))
10808 /// Extract one bit from mask vector, like v16i1 or v8i1.
10809 /// AVX-512 feature.
10811 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
10812 SDValue Vec = Op.getOperand(0);
10814 MVT VecVT = Vec.getSimpleValueType();
10815 SDValue Idx = Op.getOperand(1);
10816 MVT EltVT = Op.getSimpleValueType();
10818 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
10819 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
10820 "Unexpected vector type in ExtractBitFromMaskVector");
10822 // variable index can't be handled in mask registers,
10823 // extend vector to VR512
10824 if (!isa<ConstantSDNode>(Idx)) {
10825 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10826 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
10827 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
10828 ExtVT.getVectorElementType(), Ext, Idx);
10829 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
10832 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10833 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10834 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
10835 rc = getRegClassFor(MVT::v16i1);
10836 unsigned MaxSift = rc->getSize()*8 - 1;
10837 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
10838 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
10839 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
10840 DAG.getConstant(MaxSift, dl, MVT::i8));
10841 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
10842 DAG.getIntPtrConstant(0, dl));
10846 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
10847 SelectionDAG &DAG) const {
10849 SDValue Vec = Op.getOperand(0);
10850 MVT VecVT = Vec.getSimpleValueType();
10851 SDValue Idx = Op.getOperand(1);
10853 if (Op.getSimpleValueType() == MVT::i1)
10854 return ExtractBitFromMaskVector(Op, DAG);
10856 if (!isa<ConstantSDNode>(Idx)) {
10857 if (VecVT.is512BitVector() ||
10858 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
10859 VecVT.getVectorElementType().getSizeInBits() == 32)) {
10862 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
10863 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
10864 MaskEltVT.getSizeInBits());
10866 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
10867 auto PtrVT = getPointerTy(DAG.getDataLayout());
10868 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
10869 getZeroVector(MaskVT, Subtarget, DAG, dl), Idx,
10870 DAG.getConstant(0, dl, PtrVT));
10871 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
10872 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Perm,
10873 DAG.getConstant(0, dl, PtrVT));
10878 // If this is a 256-bit vector result, first extract the 128-bit vector and
10879 // then extract the element from the 128-bit vector.
10880 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
10882 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10883 // Get the 128-bit vector.
10884 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
10885 MVT EltVT = VecVT.getVectorElementType();
10887 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
10889 //if (IdxVal >= NumElems/2)
10890 // IdxVal -= NumElems/2;
10891 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
10892 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
10893 DAG.getConstant(IdxVal, dl, MVT::i32));
10896 assert(VecVT.is128BitVector() && "Unexpected vector length");
10898 if (Subtarget->hasSSE41())
10899 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG))
10902 MVT VT = Op.getSimpleValueType();
10903 // TODO: handle v16i8.
10904 if (VT.getSizeInBits() == 16) {
10905 SDValue Vec = Op.getOperand(0);
10906 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10908 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10909 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10910 DAG.getBitcast(MVT::v4i32, Vec),
10911 Op.getOperand(1)));
10912 // Transform it so it match pextrw which produces a 32-bit result.
10913 MVT EltVT = MVT::i32;
10914 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
10915 Op.getOperand(0), Op.getOperand(1));
10916 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
10917 DAG.getValueType(VT));
10918 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10921 if (VT.getSizeInBits() == 32) {
10922 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10926 // SHUFPS the element to the lowest double word, then movss.
10927 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
10928 MVT VVT = Op.getOperand(0).getSimpleValueType();
10929 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10930 DAG.getUNDEF(VVT), Mask);
10931 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10932 DAG.getIntPtrConstant(0, dl));
10935 if (VT.getSizeInBits() == 64) {
10936 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
10937 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
10938 // to match extract_elt for f64.
10939 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10943 // UNPCKHPD the element to the lowest double word, then movsd.
10944 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
10945 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
10946 int Mask[2] = { 1, -1 };
10947 MVT VVT = Op.getOperand(0).getSimpleValueType();
10948 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10949 DAG.getUNDEF(VVT), Mask);
10950 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10951 DAG.getIntPtrConstant(0, dl));
10957 /// Insert one bit to mask vector, like v16i1 or v8i1.
10958 /// AVX-512 feature.
10960 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
10962 SDValue Vec = Op.getOperand(0);
10963 SDValue Elt = Op.getOperand(1);
10964 SDValue Idx = Op.getOperand(2);
10965 MVT VecVT = Vec.getSimpleValueType();
10967 if (!isa<ConstantSDNode>(Idx)) {
10968 // Non constant index. Extend source and destination,
10969 // insert element and then truncate the result.
10970 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10971 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
10972 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
10973 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
10974 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
10975 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
10978 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10979 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
10981 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10982 DAG.getConstant(IdxVal, dl, MVT::i8));
10983 if (Vec.getOpcode() == ISD::UNDEF)
10985 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
10988 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
10989 SelectionDAG &DAG) const {
10990 MVT VT = Op.getSimpleValueType();
10991 MVT EltVT = VT.getVectorElementType();
10993 if (EltVT == MVT::i1)
10994 return InsertBitToMaskVector(Op, DAG);
10997 SDValue N0 = Op.getOperand(0);
10998 SDValue N1 = Op.getOperand(1);
10999 SDValue N2 = Op.getOperand(2);
11000 if (!isa<ConstantSDNode>(N2))
11002 auto *N2C = cast<ConstantSDNode>(N2);
11003 unsigned IdxVal = N2C->getZExtValue();
11005 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11006 // into that, and then insert the subvector back into the result.
11007 if (VT.is256BitVector() || VT.is512BitVector()) {
11008 // With a 256-bit vector, we can insert into the zero element efficiently
11009 // using a blend if we have AVX or AVX2 and the right data type.
11010 if (VT.is256BitVector() && IdxVal == 0) {
11011 // TODO: It is worthwhile to cast integer to floating point and back
11012 // and incur a domain crossing penalty if that's what we'll end up
11013 // doing anyway after extracting to a 128-bit vector.
11014 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
11015 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
11016 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
11017 N2 = DAG.getIntPtrConstant(1, dl);
11018 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
11022 // Get the desired 128-bit vector chunk.
11023 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11025 // Insert the element into the desired chunk.
11026 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11027 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
11029 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11030 DAG.getConstant(IdxIn128, dl, MVT::i32));
11032 // Insert the changed part back into the bigger vector
11033 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11035 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11037 if (Subtarget->hasSSE41()) {
11038 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11040 if (VT == MVT::v8i16) {
11041 Opc = X86ISD::PINSRW;
11043 assert(VT == MVT::v16i8);
11044 Opc = X86ISD::PINSRB;
11047 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11049 if (N1.getValueType() != MVT::i32)
11050 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11051 if (N2.getValueType() != MVT::i32)
11052 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11053 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11056 if (EltVT == MVT::f32) {
11057 // Bits [7:6] of the constant are the source select. This will always be
11058 // zero here. The DAG Combiner may combine an extract_elt index into
11059 // these bits. For example (insert (extract, 3), 2) could be matched by
11060 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
11061 // Bits [5:4] of the constant are the destination select. This is the
11062 // value of the incoming immediate.
11063 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11064 // combine either bitwise AND or insert of float 0.0 to set these bits.
11066 const Function *F = DAG.getMachineFunction().getFunction();
11067 bool MinSize = F->hasFnAttribute(Attribute::MinSize);
11068 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
11069 // If this is an insertion of 32-bits into the low 32-bits of
11070 // a vector, we prefer to generate a blend with immediate rather
11071 // than an insertps. Blends are simpler operations in hardware and so
11072 // will always have equal or better performance than insertps.
11073 // But if optimizing for size and there's a load folding opportunity,
11074 // generate insertps because blendps does not have a 32-bit memory
11076 N2 = DAG.getIntPtrConstant(1, dl);
11077 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11078 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
11080 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
11081 // Create this as a scalar to vector..
11082 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11083 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11086 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11087 // PINSR* works with constant index.
11092 if (EltVT == MVT::i8)
11095 if (EltVT.getSizeInBits() == 16) {
11096 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11097 // as its second argument.
11098 if (N1.getValueType() != MVT::i32)
11099 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11100 if (N2.getValueType() != MVT::i32)
11101 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11102 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11107 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11109 MVT OpVT = Op.getSimpleValueType();
11111 // If this is a 256-bit vector result, first insert into a 128-bit
11112 // vector and then insert into the 256-bit vector.
11113 if (!OpVT.is128BitVector()) {
11114 // Insert into a 128-bit vector.
11115 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11116 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11117 OpVT.getVectorNumElements() / SizeFactor);
11119 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11121 // Insert the 128-bit vector.
11122 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11125 if (OpVT == MVT::v1i64 &&
11126 Op.getOperand(0).getValueType() == MVT::i64)
11127 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11129 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11130 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11131 return DAG.getBitcast(
11132 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
11135 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11136 // a simple subregister reference or explicit instructions to grab
11137 // upper bits of a vector.
11138 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11139 SelectionDAG &DAG) {
11141 SDValue In = Op.getOperand(0);
11142 SDValue Idx = Op.getOperand(1);
11143 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11144 MVT ResVT = Op.getSimpleValueType();
11145 MVT InVT = In.getSimpleValueType();
11147 if (Subtarget->hasFp256()) {
11148 if (ResVT.is128BitVector() &&
11149 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11150 isa<ConstantSDNode>(Idx)) {
11151 return Extract128BitVector(In, IdxVal, DAG, dl);
11153 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11154 isa<ConstantSDNode>(Idx)) {
11155 return Extract256BitVector(In, IdxVal, DAG, dl);
11161 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11162 // simple superregister reference or explicit instructions to insert
11163 // the upper bits of a vector.
11164 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11165 SelectionDAG &DAG) {
11166 if (!Subtarget->hasAVX())
11170 SDValue Vec = Op.getOperand(0);
11171 SDValue SubVec = Op.getOperand(1);
11172 SDValue Idx = Op.getOperand(2);
11174 if (!isa<ConstantSDNode>(Idx))
11177 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11178 MVT OpVT = Op.getSimpleValueType();
11179 MVT SubVecVT = SubVec.getSimpleValueType();
11181 // Fold two 16-byte subvector loads into one 32-byte load:
11182 // (insert_subvector (insert_subvector undef, (load addr), 0),
11183 // (load addr + 16), Elts/2)
11185 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
11186 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
11187 OpVT.is256BitVector() && SubVecVT.is128BitVector() &&
11188 !Subtarget->isUnalignedMem32Slow()) {
11189 SDValue SubVec2 = Vec.getOperand(1);
11190 if (auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2))) {
11191 if (Idx2->getZExtValue() == 0) {
11192 SDValue Ops[] = { SubVec2, SubVec };
11193 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))
11199 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
11200 SubVecVT.is128BitVector())
11201 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11203 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
11204 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11206 if (OpVT.getVectorElementType() == MVT::i1) {
11207 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
11209 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
11210 SDValue Undef = DAG.getUNDEF(OpVT);
11211 unsigned NumElems = OpVT.getVectorNumElements();
11212 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
11214 if (IdxVal == OpVT.getVectorNumElements() / 2) {
11215 // Zero upper bits of the Vec
11216 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11217 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11219 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11221 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11222 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11225 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11227 // Zero upper bits of the Vec2
11228 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11229 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
11230 // Zero lower bits of the Vec
11231 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11232 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11233 // Merge them together
11234 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11240 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11241 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11242 // one of the above mentioned nodes. It has to be wrapped because otherwise
11243 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11244 // be used to form addressing mode. These wrapped nodes will be selected
11247 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11248 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11250 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11251 // global base reg.
11252 unsigned char OpFlag = 0;
11253 unsigned WrapperKind = X86ISD::Wrapper;
11254 CodeModel::Model M = DAG.getTarget().getCodeModel();
11256 if (Subtarget->isPICStyleRIPRel() &&
11257 (M == CodeModel::Small || M == CodeModel::Kernel))
11258 WrapperKind = X86ISD::WrapperRIP;
11259 else if (Subtarget->isPICStyleGOT())
11260 OpFlag = X86II::MO_GOTOFF;
11261 else if (Subtarget->isPICStyleStubPIC())
11262 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11264 auto PtrVT = getPointerTy(DAG.getDataLayout());
11265 SDValue Result = DAG.getTargetConstantPool(
11266 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(), OpFlag);
11268 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11269 // With PIC, the address is actually $g + Offset.
11272 DAG.getNode(ISD::ADD, DL, PtrVT,
11273 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11279 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11280 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11282 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11283 // global base reg.
11284 unsigned char OpFlag = 0;
11285 unsigned WrapperKind = X86ISD::Wrapper;
11286 CodeModel::Model M = DAG.getTarget().getCodeModel();
11288 if (Subtarget->isPICStyleRIPRel() &&
11289 (M == CodeModel::Small || M == CodeModel::Kernel))
11290 WrapperKind = X86ISD::WrapperRIP;
11291 else if (Subtarget->isPICStyleGOT())
11292 OpFlag = X86II::MO_GOTOFF;
11293 else if (Subtarget->isPICStyleStubPIC())
11294 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11296 auto PtrVT = getPointerTy(DAG.getDataLayout());
11297 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
11299 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11301 // With PIC, the address is actually $g + Offset.
11304 DAG.getNode(ISD::ADD, DL, PtrVT,
11305 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11311 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11312 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11314 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11315 // global base reg.
11316 unsigned char OpFlag = 0;
11317 unsigned WrapperKind = X86ISD::Wrapper;
11318 CodeModel::Model M = DAG.getTarget().getCodeModel();
11320 if (Subtarget->isPICStyleRIPRel() &&
11321 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11322 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11323 OpFlag = X86II::MO_GOTPCREL;
11324 WrapperKind = X86ISD::WrapperRIP;
11325 } else if (Subtarget->isPICStyleGOT()) {
11326 OpFlag = X86II::MO_GOT;
11327 } else if (Subtarget->isPICStyleStubPIC()) {
11328 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11329 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11330 OpFlag = X86II::MO_DARWIN_NONLAZY;
11333 auto PtrVT = getPointerTy(DAG.getDataLayout());
11334 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
11337 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11339 // With PIC, the address is actually $g + Offset.
11340 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11341 !Subtarget->is64Bit()) {
11343 DAG.getNode(ISD::ADD, DL, PtrVT,
11344 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11347 // For symbols that require a load from a stub to get the address, emit the
11349 if (isGlobalStubReference(OpFlag))
11350 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
11351 MachinePointerInfo::getGOT(), false, false, false, 0);
11357 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11358 // Create the TargetBlockAddressAddress node.
11359 unsigned char OpFlags =
11360 Subtarget->ClassifyBlockAddressReference();
11361 CodeModel::Model M = DAG.getTarget().getCodeModel();
11362 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11363 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11365 auto PtrVT = getPointerTy(DAG.getDataLayout());
11366 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
11368 if (Subtarget->isPICStyleRIPRel() &&
11369 (M == CodeModel::Small || M == CodeModel::Kernel))
11370 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11372 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11374 // With PIC, the address is actually $g + Offset.
11375 if (isGlobalRelativeToPICBase(OpFlags)) {
11376 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11377 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11384 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11385 int64_t Offset, SelectionDAG &DAG) const {
11386 // Create the TargetGlobalAddress node, folding in the constant
11387 // offset if it is legal.
11388 unsigned char OpFlags =
11389 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11390 CodeModel::Model M = DAG.getTarget().getCodeModel();
11391 auto PtrVT = getPointerTy(DAG.getDataLayout());
11393 if (OpFlags == X86II::MO_NO_FLAG &&
11394 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11395 // A direct static reference to a global.
11396 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
11399 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, OpFlags);
11402 if (Subtarget->isPICStyleRIPRel() &&
11403 (M == CodeModel::Small || M == CodeModel::Kernel))
11404 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11406 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11408 // With PIC, the address is actually $g + Offset.
11409 if (isGlobalRelativeToPICBase(OpFlags)) {
11410 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11411 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11414 // For globals that require a load from a stub to get the address, emit the
11416 if (isGlobalStubReference(OpFlags))
11417 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
11418 MachinePointerInfo::getGOT(), false, false, false, 0);
11420 // If there was a non-zero offset that we didn't fold, create an explicit
11421 // addition for it.
11423 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result,
11424 DAG.getConstant(Offset, dl, PtrVT));
11430 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11431 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11432 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11433 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11437 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11438 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11439 unsigned char OperandFlags, bool LocalDynamic = false) {
11440 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11441 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11443 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11444 GA->getValueType(0),
11448 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11452 SDValue Ops[] = { Chain, TGA, *InFlag };
11453 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11455 SDValue Ops[] = { Chain, TGA };
11456 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11459 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11460 MFI->setAdjustsStack(true);
11461 MFI->setHasCalls(true);
11463 SDValue Flag = Chain.getValue(1);
11464 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11467 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11469 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11472 SDLoc dl(GA); // ? function entry point might be better
11473 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11474 DAG.getNode(X86ISD::GlobalBaseReg,
11475 SDLoc(), PtrVT), InFlag);
11476 InFlag = Chain.getValue(1);
11478 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11481 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11483 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11485 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11486 X86::RAX, X86II::MO_TLSGD);
11489 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11495 // Get the start address of the TLS block for this module.
11496 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11497 .getInfo<X86MachineFunctionInfo>();
11498 MFI->incNumLocalDynamicTLSAccesses();
11502 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11503 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11506 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11507 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
11508 InFlag = Chain.getValue(1);
11509 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
11510 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
11513 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
11517 unsigned char OperandFlags = X86II::MO_DTPOFF;
11518 unsigned WrapperKind = X86ISD::Wrapper;
11519 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11520 GA->getValueType(0),
11521 GA->getOffset(), OperandFlags);
11522 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11524 // Add x@dtpoff with the base.
11525 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
11528 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
11529 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11530 const EVT PtrVT, TLSModel::Model model,
11531 bool is64Bit, bool isPIC) {
11534 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
11535 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
11536 is64Bit ? 257 : 256));
11538 SDValue ThreadPointer =
11539 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
11540 MachinePointerInfo(Ptr), false, false, false, 0);
11542 unsigned char OperandFlags = 0;
11543 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
11545 unsigned WrapperKind = X86ISD::Wrapper;
11546 if (model == TLSModel::LocalExec) {
11547 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
11548 } else if (model == TLSModel::InitialExec) {
11550 OperandFlags = X86II::MO_GOTTPOFF;
11551 WrapperKind = X86ISD::WrapperRIP;
11553 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
11556 llvm_unreachable("Unexpected model");
11559 // emit "addl x@ntpoff,%eax" (local exec)
11560 // or "addl x@indntpoff,%eax" (initial exec)
11561 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
11563 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
11564 GA->getOffset(), OperandFlags);
11565 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11567 if (model == TLSModel::InitialExec) {
11568 if (isPIC && !is64Bit) {
11569 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
11570 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11574 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
11575 MachinePointerInfo::getGOT(), false, false, false, 0);
11578 // The address of the thread local variable is the add of the thread
11579 // pointer with the offset of the variable.
11580 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
11584 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
11586 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
11587 const GlobalValue *GV = GA->getGlobal();
11588 auto PtrVT = getPointerTy(DAG.getDataLayout());
11590 if (Subtarget->isTargetELF()) {
11591 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
11593 case TLSModel::GeneralDynamic:
11594 if (Subtarget->is64Bit())
11595 return LowerToTLSGeneralDynamicModel64(GA, DAG, PtrVT);
11596 return LowerToTLSGeneralDynamicModel32(GA, DAG, PtrVT);
11597 case TLSModel::LocalDynamic:
11598 return LowerToTLSLocalDynamicModel(GA, DAG, PtrVT,
11599 Subtarget->is64Bit());
11600 case TLSModel::InitialExec:
11601 case TLSModel::LocalExec:
11602 return LowerToTLSExecModel(GA, DAG, PtrVT, model, Subtarget->is64Bit(),
11603 DAG.getTarget().getRelocationModel() ==
11606 llvm_unreachable("Unknown TLS model.");
11609 if (Subtarget->isTargetDarwin()) {
11610 // Darwin only has one model of TLS. Lower to that.
11611 unsigned char OpFlag = 0;
11612 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
11613 X86ISD::WrapperRIP : X86ISD::Wrapper;
11615 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11616 // global base reg.
11617 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
11618 !Subtarget->is64Bit();
11620 OpFlag = X86II::MO_TLVP_PIC_BASE;
11622 OpFlag = X86II::MO_TLVP;
11624 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
11625 GA->getValueType(0),
11626 GA->getOffset(), OpFlag);
11627 SDValue Offset = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11629 // With PIC32, the address is actually $g + Offset.
11631 Offset = DAG.getNode(ISD::ADD, DL, PtrVT,
11632 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11635 // Lowering the machine isd will make sure everything is in the right
11637 SDValue Chain = DAG.getEntryNode();
11638 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11639 SDValue Args[] = { Chain, Offset };
11640 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
11642 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
11643 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11644 MFI->setAdjustsStack(true);
11646 // And our return value (tls address) is in the standard call return value
11648 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11649 return DAG.getCopyFromReg(Chain, DL, Reg, PtrVT, Chain.getValue(1));
11652 if (Subtarget->isTargetKnownWindowsMSVC() ||
11653 Subtarget->isTargetWindowsGNU()) {
11654 // Just use the implicit TLS architecture
11655 // Need to generate someting similar to:
11656 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
11658 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
11659 // mov rcx, qword [rdx+rcx*8]
11660 // mov eax, .tls$:tlsvar
11661 // [rax+rcx] contains the address
11662 // Windows 64bit: gs:0x58
11663 // Windows 32bit: fs:__tls_array
11666 SDValue Chain = DAG.getEntryNode();
11668 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
11669 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
11670 // use its literal value of 0x2C.
11671 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
11672 ? Type::getInt8PtrTy(*DAG.getContext(),
11674 : Type::getInt32PtrTy(*DAG.getContext(),
11677 SDValue TlsArray = Subtarget->is64Bit()
11678 ? DAG.getIntPtrConstant(0x58, dl)
11679 : (Subtarget->isTargetWindowsGNU()
11680 ? DAG.getIntPtrConstant(0x2C, dl)
11681 : DAG.getExternalSymbol("_tls_array", PtrVT));
11683 SDValue ThreadPointer =
11684 DAG.getLoad(PtrVT, dl, Chain, TlsArray, MachinePointerInfo(Ptr), false,
11688 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
11689 res = ThreadPointer;
11691 // Load the _tls_index variable
11692 SDValue IDX = DAG.getExternalSymbol("_tls_index", PtrVT);
11693 if (Subtarget->is64Bit())
11694 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, IDX,
11695 MachinePointerInfo(), MVT::i32, false, false,
11698 IDX = DAG.getLoad(PtrVT, dl, Chain, IDX, MachinePointerInfo(), false,
11701 auto &DL = DAG.getDataLayout();
11703 DAG.getConstant(Log2_64_Ceil(DL.getPointerSize()), dl, PtrVT);
11704 IDX = DAG.getNode(ISD::SHL, dl, PtrVT, IDX, Scale);
11706 res = DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, IDX);
11709 res = DAG.getLoad(PtrVT, dl, Chain, res, MachinePointerInfo(), false, false,
11712 // Get the offset of start of .tls section
11713 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11714 GA->getValueType(0),
11715 GA->getOffset(), X86II::MO_SECREL);
11716 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
11718 // The address of the thread local variable is the add of the thread
11719 // pointer with the offset of the variable.
11720 return DAG.getNode(ISD::ADD, dl, PtrVT, res, Offset);
11723 llvm_unreachable("TLS not implemented for this target.");
11726 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
11727 /// and take a 2 x i32 value to shift plus a shift amount.
11728 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
11729 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
11730 MVT VT = Op.getSimpleValueType();
11731 unsigned VTBits = VT.getSizeInBits();
11733 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
11734 SDValue ShOpLo = Op.getOperand(0);
11735 SDValue ShOpHi = Op.getOperand(1);
11736 SDValue ShAmt = Op.getOperand(2);
11737 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
11738 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
11740 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11741 DAG.getConstant(VTBits - 1, dl, MVT::i8));
11742 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
11743 DAG.getConstant(VTBits - 1, dl, MVT::i8))
11744 : DAG.getConstant(0, dl, VT);
11746 SDValue Tmp2, Tmp3;
11747 if (Op.getOpcode() == ISD::SHL_PARTS) {
11748 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
11749 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
11751 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
11752 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
11755 // If the shift amount is larger or equal than the width of a part we can't
11756 // rely on the results of shld/shrd. Insert a test and select the appropriate
11757 // values for large shift amounts.
11758 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11759 DAG.getConstant(VTBits, dl, MVT::i8));
11760 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
11761 AndNode, DAG.getConstant(0, dl, MVT::i8));
11764 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
11765 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
11766 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
11768 if (Op.getOpcode() == ISD::SHL_PARTS) {
11769 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11770 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11772 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11773 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11776 SDValue Ops[2] = { Lo, Hi };
11777 return DAG.getMergeValues(Ops, dl);
11780 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
11781 SelectionDAG &DAG) const {
11782 SDValue Src = Op.getOperand(0);
11783 MVT SrcVT = Src.getSimpleValueType();
11784 MVT VT = Op.getSimpleValueType();
11787 if (SrcVT.isVector()) {
11788 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
11789 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
11790 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
11791 DAG.getUNDEF(SrcVT)));
11793 if (SrcVT.getVectorElementType() == MVT::i1) {
11794 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
11795 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11796 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
11801 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
11802 "Unknown SINT_TO_FP to lower!");
11804 // These are really Legal; return the operand so the caller accepts it as
11806 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
11808 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
11809 Subtarget->is64Bit()) {
11813 unsigned Size = SrcVT.getSizeInBits()/8;
11814 MachineFunction &MF = DAG.getMachineFunction();
11815 auto PtrVT = getPointerTy(MF.getDataLayout());
11816 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
11817 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
11818 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11820 MachinePointerInfo::getFixedStack(SSFI),
11822 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
11825 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
11827 SelectionDAG &DAG) const {
11831 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
11833 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
11835 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
11837 unsigned ByteSize = SrcVT.getSizeInBits()/8;
11839 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
11840 MachineMemOperand *MMO;
11842 int SSFI = FI->getIndex();
11844 DAG.getMachineFunction()
11845 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11846 MachineMemOperand::MOLoad, ByteSize, ByteSize);
11848 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
11849 StackSlot = StackSlot.getOperand(1);
11851 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
11852 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
11854 Tys, Ops, SrcVT, MMO);
11857 Chain = Result.getValue(1);
11858 SDValue InFlag = Result.getValue(2);
11860 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
11861 // shouldn't be necessary except that RFP cannot be live across
11862 // multiple blocks. When stackifier is fixed, they can be uncoupled.
11863 MachineFunction &MF = DAG.getMachineFunction();
11864 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
11865 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
11866 auto PtrVT = getPointerTy(MF.getDataLayout());
11867 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
11868 Tys = DAG.getVTList(MVT::Other);
11870 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
11872 MachineMemOperand *MMO =
11873 DAG.getMachineFunction()
11874 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11875 MachineMemOperand::MOStore, SSFISize, SSFISize);
11877 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
11878 Ops, Op.getValueType(), MMO);
11879 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
11880 MachinePointerInfo::getFixedStack(SSFI),
11881 false, false, false, 0);
11887 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
11888 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
11889 SelectionDAG &DAG) const {
11890 // This algorithm is not obvious. Here it is what we're trying to output:
11893 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
11894 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
11896 haddpd %xmm0, %xmm0
11898 pshufd $0x4e, %xmm0, %xmm1
11904 LLVMContext *Context = DAG.getContext();
11906 // Build some magic constants.
11907 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
11908 Constant *C0 = ConstantDataVector::get(*Context, CV0);
11909 auto PtrVT = getPointerTy(DAG.getDataLayout());
11910 SDValue CPIdx0 = DAG.getConstantPool(C0, PtrVT, 16);
11912 SmallVector<Constant*,2> CV1;
11914 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11915 APInt(64, 0x4330000000000000ULL))));
11917 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11918 APInt(64, 0x4530000000000000ULL))));
11919 Constant *C1 = ConstantVector::get(CV1);
11920 SDValue CPIdx1 = DAG.getConstantPool(C1, PtrVT, 16);
11922 // Load the 64-bit value into an XMM register.
11923 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
11925 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
11926 MachinePointerInfo::getConstantPool(),
11927 false, false, false, 16);
11929 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
11931 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
11932 MachinePointerInfo::getConstantPool(),
11933 false, false, false, 16);
11934 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
11935 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
11938 if (Subtarget->hasSSE3()) {
11939 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
11940 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
11942 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
11943 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
11945 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
11946 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
11949 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
11950 DAG.getIntPtrConstant(0, dl));
11953 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
11954 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
11955 SelectionDAG &DAG) const {
11957 // FP constant to bias correct the final result.
11958 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
11961 // Load the 32-bit value into an XMM register.
11962 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
11965 // Zero out the upper parts of the register.
11966 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
11968 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11969 DAG.getBitcast(MVT::v2f64, Load),
11970 DAG.getIntPtrConstant(0, dl));
11972 // Or the load with the bias.
11973 SDValue Or = DAG.getNode(
11974 ISD::OR, dl, MVT::v2i64,
11975 DAG.getBitcast(MVT::v2i64,
11976 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
11977 DAG.getBitcast(MVT::v2i64,
11978 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
11980 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11981 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
11983 // Subtract the bias.
11984 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
11986 // Handle final rounding.
11987 EVT DestVT = Op.getValueType();
11989 if (DestVT.bitsLT(MVT::f64))
11990 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
11991 DAG.getIntPtrConstant(0, dl));
11992 if (DestVT.bitsGT(MVT::f64))
11993 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
11995 // Handle final rounding.
11999 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
12000 const X86Subtarget &Subtarget) {
12001 // The algorithm is the following:
12002 // #ifdef __SSE4_1__
12003 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12004 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12005 // (uint4) 0x53000000, 0xaa);
12007 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12008 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12010 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12011 // return (float4) lo + fhi;
12014 SDValue V = Op->getOperand(0);
12015 EVT VecIntVT = V.getValueType();
12016 bool Is128 = VecIntVT == MVT::v4i32;
12017 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
12018 // If we convert to something else than the supported type, e.g., to v4f64,
12020 if (VecFloatVT != Op->getValueType(0))
12023 unsigned NumElts = VecIntVT.getVectorNumElements();
12024 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
12025 "Unsupported custom type");
12026 assert(NumElts <= 8 && "The size of the constant array must be fixed");
12028 // In the #idef/#else code, we have in common:
12029 // - The vector of constants:
12035 // Create the splat vector for 0x4b000000.
12036 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
12037 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
12038 CstLow, CstLow, CstLow, CstLow};
12039 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12040 makeArrayRef(&CstLowArray[0], NumElts));
12041 // Create the splat vector for 0x53000000.
12042 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
12043 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
12044 CstHigh, CstHigh, CstHigh, CstHigh};
12045 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12046 makeArrayRef(&CstHighArray[0], NumElts));
12048 // Create the right shift.
12049 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
12050 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
12051 CstShift, CstShift, CstShift, CstShift};
12052 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12053 makeArrayRef(&CstShiftArray[0], NumElts));
12054 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
12057 if (Subtarget.hasSSE41()) {
12058 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
12059 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12060 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
12061 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
12062 // Low will be bitcasted right away, so do not bother bitcasting back to its
12064 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
12065 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12066 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12067 // (uint4) 0x53000000, 0xaa);
12068 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
12069 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
12070 // High will be bitcasted right away, so do not bother bitcasting back to
12071 // its original type.
12072 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
12073 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12075 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
12076 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
12077 CstMask, CstMask, CstMask);
12078 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12079 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
12080 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
12082 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12083 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
12086 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
12087 SDValue CstFAdd = DAG.getConstantFP(
12088 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
12089 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
12090 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
12091 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
12092 makeArrayRef(&CstFAddArray[0], NumElts));
12094 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12095 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
12097 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
12098 // return (float4) lo + fhi;
12099 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
12100 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
12103 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12104 SelectionDAG &DAG) const {
12105 SDValue N0 = Op.getOperand(0);
12106 MVT SVT = N0.getSimpleValueType();
12109 switch (SVT.SimpleTy) {
12111 llvm_unreachable("Custom UINT_TO_FP is not supported!");
12116 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12117 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12118 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12122 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
12125 if (Subtarget->hasAVX512())
12126 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
12127 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
12129 llvm_unreachable(nullptr);
12132 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12133 SelectionDAG &DAG) const {
12134 SDValue N0 = Op.getOperand(0);
12136 auto PtrVT = getPointerTy(DAG.getDataLayout());
12138 if (Op.getValueType().isVector())
12139 return lowerUINT_TO_FP_vec(Op, DAG);
12141 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12142 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12143 // the optimization here.
12144 if (DAG.SignBitIsZero(N0))
12145 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12147 MVT SrcVT = N0.getSimpleValueType();
12148 MVT DstVT = Op.getSimpleValueType();
12149 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12150 return LowerUINT_TO_FP_i64(Op, DAG);
12151 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12152 return LowerUINT_TO_FP_i32(Op, DAG);
12153 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12156 // Make a 64-bit buffer, and use it to build an FILD.
12157 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12158 if (SrcVT == MVT::i32) {
12159 SDValue WordOff = DAG.getConstant(4, dl, PtrVT);
12160 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, WordOff);
12161 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12162 StackSlot, MachinePointerInfo(),
12164 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
12165 OffsetSlot, MachinePointerInfo(),
12167 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12171 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12172 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12173 StackSlot, MachinePointerInfo(),
12175 // For i64 source, we need to add the appropriate power of 2 if the input
12176 // was negative. This is the same as the optimization in
12177 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12178 // we must be careful to do the computation in x87 extended precision, not
12179 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12180 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12181 MachineMemOperand *MMO =
12182 DAG.getMachineFunction()
12183 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12184 MachineMemOperand::MOLoad, 8, 8);
12186 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12187 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12188 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12191 APInt FF(32, 0x5F800000ULL);
12193 // Check whether the sign bit is set.
12194 SDValue SignSet = DAG.getSetCC(
12195 dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64),
12196 Op.getOperand(0), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
12198 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12199 SDValue FudgePtr = DAG.getConstantPool(
12200 ConstantInt::get(*DAG.getContext(), FF.zext(64)), PtrVT);
12202 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12203 SDValue Zero = DAG.getIntPtrConstant(0, dl);
12204 SDValue Four = DAG.getIntPtrConstant(4, dl);
12205 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12207 FudgePtr = DAG.getNode(ISD::ADD, dl, PtrVT, FudgePtr, Offset);
12209 // Load the value out, extending it from f32 to f80.
12210 // FIXME: Avoid the extend by constructing the right constant pool?
12211 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
12212 FudgePtr, MachinePointerInfo::getConstantPool(),
12213 MVT::f32, false, false, false, 4);
12214 // Extend everything to 80 bits to force it to be done on x87.
12215 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12216 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
12217 DAG.getIntPtrConstant(0, dl));
12220 std::pair<SDValue,SDValue>
12221 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12222 bool IsSigned, bool IsReplace) const {
12225 EVT DstTy = Op.getValueType();
12226 auto PtrVT = getPointerTy(DAG.getDataLayout());
12228 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
12229 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12233 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12234 DstTy.getSimpleVT() >= MVT::i16 &&
12235 "Unknown FP_TO_INT to lower!");
12237 // These are really Legal.
12238 if (DstTy == MVT::i32 &&
12239 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12240 return std::make_pair(SDValue(), SDValue());
12241 if (Subtarget->is64Bit() &&
12242 DstTy == MVT::i64 &&
12243 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12244 return std::make_pair(SDValue(), SDValue());
12246 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
12247 // stack slot, or into the FTOL runtime function.
12248 MachineFunction &MF = DAG.getMachineFunction();
12249 unsigned MemSize = DstTy.getSizeInBits()/8;
12250 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12251 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12254 if (!IsSigned && isIntegerTypeFTOL(DstTy))
12255 Opc = X86ISD::WIN_FTOL;
12257 switch (DstTy.getSimpleVT().SimpleTy) {
12258 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12259 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12260 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12261 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12264 SDValue Chain = DAG.getEntryNode();
12265 SDValue Value = Op.getOperand(0);
12266 EVT TheVT = Op.getOperand(0).getValueType();
12267 // FIXME This causes a redundant load/store if the SSE-class value is already
12268 // in memory, such as if it is on the callstack.
12269 if (isScalarFPTypeInSSEReg(TheVT)) {
12270 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12271 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12272 MachinePointerInfo::getFixedStack(SSFI),
12274 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12276 Chain, StackSlot, DAG.getValueType(TheVT)
12279 MachineMemOperand *MMO =
12280 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12281 MachineMemOperand::MOLoad, MemSize, MemSize);
12282 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12283 Chain = Value.getValue(1);
12284 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12285 StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12288 MachineMemOperand *MMO =
12289 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12290 MachineMemOperand::MOStore, MemSize, MemSize);
12292 if (Opc != X86ISD::WIN_FTOL) {
12293 // Build the FP_TO_INT*_IN_MEM
12294 SDValue Ops[] = { Chain, Value, StackSlot };
12295 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12297 return std::make_pair(FIST, StackSlot);
12299 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
12300 DAG.getVTList(MVT::Other, MVT::Glue),
12302 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
12303 MVT::i32, ftol.getValue(1));
12304 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
12305 MVT::i32, eax.getValue(2));
12306 SDValue Ops[] = { eax, edx };
12307 SDValue pair = IsReplace
12308 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
12309 : DAG.getMergeValues(Ops, DL);
12310 return std::make_pair(pair, SDValue());
12314 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12315 const X86Subtarget *Subtarget) {
12316 MVT VT = Op->getSimpleValueType(0);
12317 SDValue In = Op->getOperand(0);
12318 MVT InVT = In.getSimpleValueType();
12321 if (VT.is512BitVector() || InVT.getScalarType() == MVT::i1)
12322 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
12324 // Optimize vectors in AVX mode:
12327 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12328 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12329 // Concat upper and lower parts.
12332 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12333 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12334 // Concat upper and lower parts.
12337 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12338 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12339 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12342 if (Subtarget->hasInt256())
12343 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12345 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12346 SDValue Undef = DAG.getUNDEF(InVT);
12347 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12348 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12349 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12351 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12352 VT.getVectorNumElements()/2);
12354 OpLo = DAG.getBitcast(HVT, OpLo);
12355 OpHi = DAG.getBitcast(HVT, OpHi);
12357 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12360 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12361 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
12362 MVT VT = Op->getSimpleValueType(0);
12363 SDValue In = Op->getOperand(0);
12364 MVT InVT = In.getSimpleValueType();
12366 unsigned int NumElts = VT.getVectorNumElements();
12367 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
12370 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12371 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
12373 assert(InVT.getVectorElementType() == MVT::i1);
12374 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
12376 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
12378 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
12380 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
12381 if (VT.is512BitVector())
12383 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
12386 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12387 SelectionDAG &DAG) {
12388 if (Subtarget->hasFp256())
12389 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
12395 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12396 SelectionDAG &DAG) {
12398 MVT VT = Op.getSimpleValueType();
12399 SDValue In = Op.getOperand(0);
12400 MVT SVT = In.getSimpleValueType();
12402 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12403 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
12405 if (Subtarget->hasFp256())
12406 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
12409 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12410 VT.getVectorNumElements() != SVT.getVectorNumElements());
12414 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
12416 MVT VT = Op.getSimpleValueType();
12417 SDValue In = Op.getOperand(0);
12418 MVT InVT = In.getSimpleValueType();
12420 if (VT == MVT::i1) {
12421 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
12422 "Invalid scalar TRUNCATE operation");
12423 if (InVT.getSizeInBits() >= 32)
12425 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
12426 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
12428 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
12429 "Invalid TRUNCATE operation");
12431 // move vector to mask - truncate solution for SKX
12432 if (VT.getVectorElementType() == MVT::i1) {
12433 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
12434 Subtarget->hasBWI())
12435 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12436 if ((InVT.is256BitVector() || InVT.is128BitVector())
12437 && InVT.getScalarSizeInBits() <= 16 &&
12438 Subtarget->hasBWI() && Subtarget->hasVLX())
12439 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12440 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
12441 Subtarget->hasDQI())
12442 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
12443 if ((InVT.is256BitVector() || InVT.is128BitVector())
12444 && InVT.getScalarSizeInBits() >= 32 &&
12445 Subtarget->hasDQI() && Subtarget->hasVLX())
12446 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
12448 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
12449 if (VT.getVectorElementType().getSizeInBits() >=8)
12450 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
12452 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12453 unsigned NumElts = InVT.getVectorNumElements();
12454 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
12455 if (InVT.getSizeInBits() < 512) {
12456 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
12457 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
12462 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
12463 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
12464 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
12467 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
12468 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
12469 if (Subtarget->hasInt256()) {
12470 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
12471 In = DAG.getBitcast(MVT::v8i32, In);
12472 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
12474 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
12475 DAG.getIntPtrConstant(0, DL));
12478 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12479 DAG.getIntPtrConstant(0, DL));
12480 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12481 DAG.getIntPtrConstant(2, DL));
12482 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
12483 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
12484 static const int ShufMask[] = {0, 2, 4, 6};
12485 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
12488 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
12489 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
12490 if (Subtarget->hasInt256()) {
12491 In = DAG.getBitcast(MVT::v32i8, In);
12493 SmallVector<SDValue,32> pshufbMask;
12494 for (unsigned i = 0; i < 2; ++i) {
12495 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
12496 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
12497 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
12498 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
12499 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
12500 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
12501 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
12502 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
12503 for (unsigned j = 0; j < 8; ++j)
12504 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
12506 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
12507 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
12508 In = DAG.getBitcast(MVT::v4i64, In);
12510 static const int ShufMask[] = {0, 2, -1, -1};
12511 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
12513 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12514 DAG.getIntPtrConstant(0, DL));
12515 return DAG.getBitcast(VT, In);
12518 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12519 DAG.getIntPtrConstant(0, DL));
12521 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12522 DAG.getIntPtrConstant(4, DL));
12524 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
12525 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
12527 // The PSHUFB mask:
12528 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12529 -1, -1, -1, -1, -1, -1, -1, -1};
12531 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
12532 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
12533 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
12535 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
12536 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
12538 // The MOVLHPS Mask:
12539 static const int ShufMask2[] = {0, 1, 4, 5};
12540 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
12541 return DAG.getBitcast(MVT::v8i16, res);
12544 // Handle truncation of V256 to V128 using shuffles.
12545 if (!VT.is128BitVector() || !InVT.is256BitVector())
12548 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
12550 unsigned NumElems = VT.getVectorNumElements();
12551 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
12553 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
12554 // Prepare truncation shuffle mask
12555 for (unsigned i = 0; i != NumElems; ++i)
12556 MaskVec[i] = i * 2;
12557 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
12558 DAG.getUNDEF(NVT), &MaskVec[0]);
12559 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
12560 DAG.getIntPtrConstant(0, DL));
12563 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
12564 SelectionDAG &DAG) const {
12565 assert(!Op.getSimpleValueType().isVector());
12567 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12568 /*IsSigned=*/ true, /*IsReplace=*/ false);
12569 SDValue FIST = Vals.first, StackSlot = Vals.second;
12570 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
12571 if (!FIST.getNode()) return Op;
12573 if (StackSlot.getNode())
12574 // Load the result.
12575 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12576 FIST, StackSlot, MachinePointerInfo(),
12577 false, false, false, 0);
12579 // The node is the result.
12583 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
12584 SelectionDAG &DAG) const {
12585 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12586 /*IsSigned=*/ false, /*IsReplace=*/ false);
12587 SDValue FIST = Vals.first, StackSlot = Vals.second;
12588 assert(FIST.getNode() && "Unexpected failure");
12590 if (StackSlot.getNode())
12591 // Load the result.
12592 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12593 FIST, StackSlot, MachinePointerInfo(),
12594 false, false, false, 0);
12596 // The node is the result.
12600 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
12602 MVT VT = Op.getSimpleValueType();
12603 SDValue In = Op.getOperand(0);
12604 MVT SVT = In.getSimpleValueType();
12606 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
12608 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
12609 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
12610 In, DAG.getUNDEF(SVT)));
12613 /// The only differences between FABS and FNEG are the mask and the logic op.
12614 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
12615 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
12616 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
12617 "Wrong opcode for lowering FABS or FNEG.");
12619 bool IsFABS = (Op.getOpcode() == ISD::FABS);
12621 // If this is a FABS and it has an FNEG user, bail out to fold the combination
12622 // into an FNABS. We'll lower the FABS after that if it is still in use.
12624 for (SDNode *User : Op->uses())
12625 if (User->getOpcode() == ISD::FNEG)
12628 SDValue Op0 = Op.getOperand(0);
12629 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
12632 MVT VT = Op.getSimpleValueType();
12633 // Assume scalar op for initialization; update for vector if needed.
12634 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
12635 // generate a 16-byte vector constant and logic op even for the scalar case.
12636 // Using a 16-byte mask allows folding the load of the mask with
12637 // the logic op, so it can save (~4 bytes) on code size.
12639 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
12640 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
12641 // decide if we should generate a 16-byte constant mask when we only need 4 or
12642 // 8 bytes for the scalar case.
12643 if (VT.isVector()) {
12644 EltVT = VT.getVectorElementType();
12645 NumElts = VT.getVectorNumElements();
12648 unsigned EltBits = EltVT.getSizeInBits();
12649 LLVMContext *Context = DAG.getContext();
12650 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
12652 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
12653 Constant *C = ConstantInt::get(*Context, MaskElt);
12654 C = ConstantVector::getSplat(NumElts, C);
12655 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12656 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
12657 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
12658 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12659 MachinePointerInfo::getConstantPool(),
12660 false, false, false, Alignment);
12662 if (VT.isVector()) {
12663 // For a vector, cast operands to a vector type, perform the logic op,
12664 // and cast the result back to the original value type.
12665 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
12666 SDValue MaskCasted = DAG.getBitcast(VecVT, Mask);
12667 SDValue Operand = IsFNABS ? DAG.getBitcast(VecVT, Op0.getOperand(0))
12668 : DAG.getBitcast(VecVT, Op0);
12669 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
12670 return DAG.getBitcast(VT,
12671 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
12674 // If not vector, then scalar.
12675 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
12676 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
12677 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
12680 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
12681 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12682 LLVMContext *Context = DAG.getContext();
12683 SDValue Op0 = Op.getOperand(0);
12684 SDValue Op1 = Op.getOperand(1);
12686 MVT VT = Op.getSimpleValueType();
12687 MVT SrcVT = Op1.getSimpleValueType();
12689 // If second operand is smaller, extend it first.
12690 if (SrcVT.bitsLT(VT)) {
12691 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
12694 // And if it is bigger, shrink it first.
12695 if (SrcVT.bitsGT(VT)) {
12696 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
12700 // At this point the operands and the result should have the same
12701 // type, and that won't be f80 since that is not custom lowered.
12703 const fltSemantics &Sem =
12704 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
12705 const unsigned SizeInBits = VT.getSizeInBits();
12707 SmallVector<Constant *, 4> CV(
12708 VT == MVT::f64 ? 2 : 4,
12709 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
12711 // First, clear all bits but the sign bit from the second operand (sign).
12712 CV[0] = ConstantFP::get(*Context,
12713 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
12714 Constant *C = ConstantVector::get(CV);
12715 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
12716 SDValue CPIdx = DAG.getConstantPool(C, PtrVT, 16);
12717 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
12718 MachinePointerInfo::getConstantPool(),
12719 false, false, false, 16);
12720 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
12722 // Next, clear the sign bit from the first operand (magnitude).
12723 // If it's a constant, we can clear it here.
12724 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
12725 APFloat APF = Op0CN->getValueAPF();
12726 // If the magnitude is a positive zero, the sign bit alone is enough.
12727 if (APF.isPosZero())
12730 CV[0] = ConstantFP::get(*Context, APF);
12732 CV[0] = ConstantFP::get(
12734 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
12736 C = ConstantVector::get(CV);
12737 CPIdx = DAG.getConstantPool(C, PtrVT, 16);
12738 SDValue Val = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12739 MachinePointerInfo::getConstantPool(),
12740 false, false, false, 16);
12741 // If the magnitude operand wasn't a constant, we need to AND out the sign.
12742 if (!isa<ConstantFPSDNode>(Op0))
12743 Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Val);
12745 // OR the magnitude value with the sign bit.
12746 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
12749 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
12750 SDValue N0 = Op.getOperand(0);
12752 MVT VT = Op.getSimpleValueType();
12754 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
12755 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
12756 DAG.getConstant(1, dl, VT));
12757 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
12760 // Check whether an OR'd tree is PTEST-able.
12761 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
12762 SelectionDAG &DAG) {
12763 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
12765 if (!Subtarget->hasSSE41())
12768 if (!Op->hasOneUse())
12771 SDNode *N = Op.getNode();
12774 SmallVector<SDValue, 8> Opnds;
12775 DenseMap<SDValue, unsigned> VecInMap;
12776 SmallVector<SDValue, 8> VecIns;
12777 EVT VT = MVT::Other;
12779 // Recognize a special case where a vector is casted into wide integer to
12781 Opnds.push_back(N->getOperand(0));
12782 Opnds.push_back(N->getOperand(1));
12784 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
12785 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
12786 // BFS traverse all OR'd operands.
12787 if (I->getOpcode() == ISD::OR) {
12788 Opnds.push_back(I->getOperand(0));
12789 Opnds.push_back(I->getOperand(1));
12790 // Re-evaluate the number of nodes to be traversed.
12791 e += 2; // 2 more nodes (LHS and RHS) are pushed.
12795 // Quit if a non-EXTRACT_VECTOR_ELT
12796 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12799 // Quit if without a constant index.
12800 SDValue Idx = I->getOperand(1);
12801 if (!isa<ConstantSDNode>(Idx))
12804 SDValue ExtractedFromVec = I->getOperand(0);
12805 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
12806 if (M == VecInMap.end()) {
12807 VT = ExtractedFromVec.getValueType();
12808 // Quit if not 128/256-bit vector.
12809 if (!VT.is128BitVector() && !VT.is256BitVector())
12811 // Quit if not the same type.
12812 if (VecInMap.begin() != VecInMap.end() &&
12813 VT != VecInMap.begin()->first.getValueType())
12815 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
12816 VecIns.push_back(ExtractedFromVec);
12818 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
12821 assert((VT.is128BitVector() || VT.is256BitVector()) &&
12822 "Not extracted from 128-/256-bit vector.");
12824 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
12826 for (DenseMap<SDValue, unsigned>::const_iterator
12827 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
12828 // Quit if not all elements are used.
12829 if (I->second != FullMask)
12833 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
12835 // Cast all vectors into TestVT for PTEST.
12836 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
12837 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
12839 // If more than one full vectors are evaluated, OR them first before PTEST.
12840 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
12841 // Each iteration will OR 2 nodes and append the result until there is only
12842 // 1 node left, i.e. the final OR'd value of all vectors.
12843 SDValue LHS = VecIns[Slot];
12844 SDValue RHS = VecIns[Slot + 1];
12845 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
12848 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
12849 VecIns.back(), VecIns.back());
12852 /// \brief return true if \c Op has a use that doesn't just read flags.
12853 static bool hasNonFlagsUse(SDValue Op) {
12854 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
12856 SDNode *User = *UI;
12857 unsigned UOpNo = UI.getOperandNo();
12858 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
12859 // Look pass truncate.
12860 UOpNo = User->use_begin().getOperandNo();
12861 User = *User->use_begin();
12864 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
12865 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
12871 /// Emit nodes that will be selected as "test Op0,Op0", or something
12873 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
12874 SelectionDAG &DAG) const {
12875 if (Op.getValueType() == MVT::i1) {
12876 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
12877 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
12878 DAG.getConstant(0, dl, MVT::i8));
12880 // CF and OF aren't always set the way we want. Determine which
12881 // of these we need.
12882 bool NeedCF = false;
12883 bool NeedOF = false;
12886 case X86::COND_A: case X86::COND_AE:
12887 case X86::COND_B: case X86::COND_BE:
12890 case X86::COND_G: case X86::COND_GE:
12891 case X86::COND_L: case X86::COND_LE:
12892 case X86::COND_O: case X86::COND_NO: {
12893 // Check if we really need to set the
12894 // Overflow flag. If NoSignedWrap is present
12895 // that is not actually needed.
12896 switch (Op->getOpcode()) {
12901 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
12902 if (BinNode->Flags.hasNoSignedWrap())
12912 // See if we can use the EFLAGS value from the operand instead of
12913 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
12914 // we prove that the arithmetic won't overflow, we can't use OF or CF.
12915 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
12916 // Emit a CMP with 0, which is the TEST pattern.
12917 //if (Op.getValueType() == MVT::i1)
12918 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
12919 // DAG.getConstant(0, MVT::i1));
12920 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12921 DAG.getConstant(0, dl, Op.getValueType()));
12923 unsigned Opcode = 0;
12924 unsigned NumOperands = 0;
12926 // Truncate operations may prevent the merge of the SETCC instruction
12927 // and the arithmetic instruction before it. Attempt to truncate the operands
12928 // of the arithmetic instruction and use a reduced bit-width instruction.
12929 bool NeedTruncation = false;
12930 SDValue ArithOp = Op;
12931 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
12932 SDValue Arith = Op->getOperand(0);
12933 // Both the trunc and the arithmetic op need to have one user each.
12934 if (Arith->hasOneUse())
12935 switch (Arith.getOpcode()) {
12942 NeedTruncation = true;
12948 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
12949 // which may be the result of a CAST. We use the variable 'Op', which is the
12950 // non-casted variable when we check for possible users.
12951 switch (ArithOp.getOpcode()) {
12953 // Due to an isel shortcoming, be conservative if this add is likely to be
12954 // selected as part of a load-modify-store instruction. When the root node
12955 // in a match is a store, isel doesn't know how to remap non-chain non-flag
12956 // uses of other nodes in the match, such as the ADD in this case. This
12957 // leads to the ADD being left around and reselected, with the result being
12958 // two adds in the output. Alas, even if none our users are stores, that
12959 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
12960 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
12961 // climbing the DAG back to the root, and it doesn't seem to be worth the
12963 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12964 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12965 if (UI->getOpcode() != ISD::CopyToReg &&
12966 UI->getOpcode() != ISD::SETCC &&
12967 UI->getOpcode() != ISD::STORE)
12970 if (ConstantSDNode *C =
12971 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
12972 // An add of one will be selected as an INC.
12973 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
12974 Opcode = X86ISD::INC;
12979 // An add of negative one (subtract of one) will be selected as a DEC.
12980 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
12981 Opcode = X86ISD::DEC;
12987 // Otherwise use a regular EFLAGS-setting add.
12988 Opcode = X86ISD::ADD;
12993 // If we have a constant logical shift that's only used in a comparison
12994 // against zero turn it into an equivalent AND. This allows turning it into
12995 // a TEST instruction later.
12996 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
12997 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
12998 EVT VT = Op.getValueType();
12999 unsigned BitWidth = VT.getSizeInBits();
13000 unsigned ShAmt = Op->getConstantOperandVal(1);
13001 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13003 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13004 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13005 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13006 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13008 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13009 DAG.getConstant(Mask, dl, VT));
13010 DAG.ReplaceAllUsesWith(Op, New);
13016 // If the primary and result isn't used, don't bother using X86ISD::AND,
13017 // because a TEST instruction will be better.
13018 if (!hasNonFlagsUse(Op))
13024 // Due to the ISEL shortcoming noted above, be conservative if this op is
13025 // likely to be selected as part of a load-modify-store instruction.
13026 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13027 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13028 if (UI->getOpcode() == ISD::STORE)
13031 // Otherwise use a regular EFLAGS-setting instruction.
13032 switch (ArithOp.getOpcode()) {
13033 default: llvm_unreachable("unexpected operator!");
13034 case ISD::SUB: Opcode = X86ISD::SUB; break;
13035 case ISD::XOR: Opcode = X86ISD::XOR; break;
13036 case ISD::AND: Opcode = X86ISD::AND; break;
13038 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13039 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13040 if (EFLAGS.getNode())
13043 Opcode = X86ISD::OR;
13057 return SDValue(Op.getNode(), 1);
13063 // If we found that truncation is beneficial, perform the truncation and
13065 if (NeedTruncation) {
13066 EVT VT = Op.getValueType();
13067 SDValue WideVal = Op->getOperand(0);
13068 EVT WideVT = WideVal.getValueType();
13069 unsigned ConvertedOp = 0;
13070 // Use a target machine opcode to prevent further DAGCombine
13071 // optimizations that may separate the arithmetic operations
13072 // from the setcc node.
13073 switch (WideVal.getOpcode()) {
13075 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13076 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13077 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13078 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13079 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13083 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13084 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13085 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13086 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13087 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13093 // Emit a CMP with 0, which is the TEST pattern.
13094 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13095 DAG.getConstant(0, dl, Op.getValueType()));
13097 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13098 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
13100 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13101 DAG.ReplaceAllUsesWith(Op, New);
13102 return SDValue(New.getNode(), 1);
13105 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13107 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13108 SDLoc dl, SelectionDAG &DAG) const {
13109 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13110 if (C->getAPIntValue() == 0)
13111 return EmitTest(Op0, X86CC, dl, DAG);
13113 if (Op0.getValueType() == MVT::i1)
13114 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
13117 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13118 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13119 // Do the comparison at i32 if it's smaller, besides the Atom case.
13120 // This avoids subregister aliasing issues. Keep the smaller reference
13121 // if we're optimizing for size, however, as that'll allow better folding
13122 // of memory operations.
13123 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13124 !DAG.getMachineFunction().getFunction()->hasFnAttribute(
13125 Attribute::MinSize) &&
13126 !Subtarget->isAtom()) {
13127 unsigned ExtendOp =
13128 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13129 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13130 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13132 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13133 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13134 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13136 return SDValue(Sub.getNode(), 1);
13138 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13141 /// Convert a comparison if required by the subtarget.
13142 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13143 SelectionDAG &DAG) const {
13144 // If the subtarget does not support the FUCOMI instruction, floating-point
13145 // comparisons have to be converted.
13146 if (Subtarget->hasCMov() ||
13147 Cmp.getOpcode() != X86ISD::CMP ||
13148 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13149 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13152 // The instruction selector will select an FUCOM instruction instead of
13153 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13154 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13155 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13157 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13158 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13159 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13160 DAG.getConstant(8, dl, MVT::i8));
13161 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13162 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13165 /// The minimum architected relative accuracy is 2^-12. We need one
13166 /// Newton-Raphson step to have a good float result (24 bits of precision).
13167 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
13168 DAGCombinerInfo &DCI,
13169 unsigned &RefinementSteps,
13170 bool &UseOneConstNR) const {
13171 EVT VT = Op.getValueType();
13172 const char *RecipOp;
13174 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
13175 // TODO: Add support for AVX512 (v16f32).
13176 // It is likely not profitable to do this for f64 because a double-precision
13177 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
13178 // instructions: convert to single, rsqrtss, convert back to double, refine
13179 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
13180 // along with FMA, this could be a throughput win.
13181 if (VT == MVT::f32 && Subtarget->hasSSE1())
13183 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13184 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13185 RecipOp = "vec-sqrtf";
13189 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13190 if (!Recips.isEnabled(RecipOp))
13193 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13194 UseOneConstNR = false;
13195 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
13198 /// The minimum architected relative accuracy is 2^-12. We need one
13199 /// Newton-Raphson step to have a good float result (24 bits of precision).
13200 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
13201 DAGCombinerInfo &DCI,
13202 unsigned &RefinementSteps) const {
13203 EVT VT = Op.getValueType();
13204 const char *RecipOp;
13206 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
13207 // TODO: Add support for AVX512 (v16f32).
13208 // It is likely not profitable to do this for f64 because a double-precision
13209 // reciprocal estimate with refinement on x86 prior to FMA requires
13210 // 15 instructions: convert to single, rcpss, convert back to double, refine
13211 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
13212 // along with FMA, this could be a throughput win.
13213 if (VT == MVT::f32 && Subtarget->hasSSE1())
13215 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13216 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13217 RecipOp = "vec-divf";
13221 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13222 if (!Recips.isEnabled(RecipOp))
13225 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13226 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
13229 /// If we have at least two divisions that use the same divisor, convert to
13230 /// multplication by a reciprocal. This may need to be adjusted for a given
13231 /// CPU if a division's cost is not at least twice the cost of a multiplication.
13232 /// This is because we still need one division to calculate the reciprocal and
13233 /// then we need two multiplies by that reciprocal as replacements for the
13234 /// original divisions.
13235 bool X86TargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
13236 return NumUsers > 1;
13239 static bool isAllOnes(SDValue V) {
13240 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13241 return C && C->isAllOnesValue();
13244 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13245 /// if it's possible.
13246 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13247 SDLoc dl, SelectionDAG &DAG) const {
13248 SDValue Op0 = And.getOperand(0);
13249 SDValue Op1 = And.getOperand(1);
13250 if (Op0.getOpcode() == ISD::TRUNCATE)
13251 Op0 = Op0.getOperand(0);
13252 if (Op1.getOpcode() == ISD::TRUNCATE)
13253 Op1 = Op1.getOperand(0);
13256 if (Op1.getOpcode() == ISD::SHL)
13257 std::swap(Op0, Op1);
13258 if (Op0.getOpcode() == ISD::SHL) {
13259 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13260 if (And00C->getZExtValue() == 1) {
13261 // If we looked past a truncate, check that it's only truncating away
13263 unsigned BitWidth = Op0.getValueSizeInBits();
13264 unsigned AndBitWidth = And.getValueSizeInBits();
13265 if (BitWidth > AndBitWidth) {
13267 DAG.computeKnownBits(Op0, Zeros, Ones);
13268 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13272 RHS = Op0.getOperand(1);
13274 } else if (Op1.getOpcode() == ISD::Constant) {
13275 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13276 uint64_t AndRHSVal = AndRHS->getZExtValue();
13277 SDValue AndLHS = Op0;
13279 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13280 LHS = AndLHS.getOperand(0);
13281 RHS = AndLHS.getOperand(1);
13284 // Use BT if the immediate can't be encoded in a TEST instruction.
13285 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13287 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
13291 if (LHS.getNode()) {
13292 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13293 // instruction. Since the shift amount is in-range-or-undefined, we know
13294 // that doing a bittest on the i32 value is ok. We extend to i32 because
13295 // the encoding for the i16 version is larger than the i32 version.
13296 // Also promote i16 to i32 for performance / code size reason.
13297 if (LHS.getValueType() == MVT::i8 ||
13298 LHS.getValueType() == MVT::i16)
13299 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13301 // If the operand types disagree, extend the shift amount to match. Since
13302 // BT ignores high bits (like shifts) we can use anyextend.
13303 if (LHS.getValueType() != RHS.getValueType())
13304 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13306 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13307 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13308 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13309 DAG.getConstant(Cond, dl, MVT::i8), BT);
13315 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13317 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13322 // SSE Condition code mapping:
13331 switch (SetCCOpcode) {
13332 default: llvm_unreachable("Unexpected SETCC condition");
13334 case ISD::SETEQ: SSECC = 0; break;
13336 case ISD::SETGT: Swap = true; // Fallthrough
13338 case ISD::SETOLT: SSECC = 1; break;
13340 case ISD::SETGE: Swap = true; // Fallthrough
13342 case ISD::SETOLE: SSECC = 2; break;
13343 case ISD::SETUO: SSECC = 3; break;
13345 case ISD::SETNE: SSECC = 4; break;
13346 case ISD::SETULE: Swap = true; // Fallthrough
13347 case ISD::SETUGE: SSECC = 5; break;
13348 case ISD::SETULT: Swap = true; // Fallthrough
13349 case ISD::SETUGT: SSECC = 6; break;
13350 case ISD::SETO: SSECC = 7; break;
13352 case ISD::SETONE: SSECC = 8; break;
13355 std::swap(Op0, Op1);
13360 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13361 // ones, and then concatenate the result back.
13362 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13363 MVT VT = Op.getSimpleValueType();
13365 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13366 "Unsupported value type for operation");
13368 unsigned NumElems = VT.getVectorNumElements();
13370 SDValue CC = Op.getOperand(2);
13372 // Extract the LHS vectors
13373 SDValue LHS = Op.getOperand(0);
13374 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13375 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13377 // Extract the RHS vectors
13378 SDValue RHS = Op.getOperand(1);
13379 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13380 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13382 // Issue the operation on the smaller types and concatenate the result back
13383 MVT EltVT = VT.getVectorElementType();
13384 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13385 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13386 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
13387 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
13390 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
13391 SDValue Op0 = Op.getOperand(0);
13392 SDValue Op1 = Op.getOperand(1);
13393 SDValue CC = Op.getOperand(2);
13394 MVT VT = Op.getSimpleValueType();
13397 assert(Op0.getValueType().getVectorElementType() == MVT::i1 &&
13398 "Unexpected type for boolean compare operation");
13399 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13400 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
13401 DAG.getConstant(-1, dl, VT));
13402 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
13403 DAG.getConstant(-1, dl, VT));
13404 switch (SetCCOpcode) {
13405 default: llvm_unreachable("Unexpected SETCC condition");
13407 // (x == y) -> ~(x ^ y)
13408 return DAG.getNode(ISD::XOR, dl, VT,
13409 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
13410 DAG.getConstant(-1, dl, VT));
13412 // (x != y) -> (x ^ y)
13413 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
13416 // (x > y) -> (x & ~y)
13417 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
13420 // (x < y) -> (~x & y)
13421 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
13424 // (x <= y) -> (~x | y)
13425 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
13428 // (x >=y) -> (x | ~y)
13429 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
13433 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
13434 const X86Subtarget *Subtarget) {
13435 SDValue Op0 = Op.getOperand(0);
13436 SDValue Op1 = Op.getOperand(1);
13437 SDValue CC = Op.getOperand(2);
13438 MVT VT = Op.getSimpleValueType();
13441 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
13442 Op.getValueType().getScalarType() == MVT::i1 &&
13443 "Cannot set masked compare for this operation");
13445 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13447 bool Unsigned = false;
13450 switch (SetCCOpcode) {
13451 default: llvm_unreachable("Unexpected SETCC condition");
13452 case ISD::SETNE: SSECC = 4; break;
13453 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
13454 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
13455 case ISD::SETLT: Swap = true; //fall-through
13456 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
13457 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
13458 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
13459 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
13460 case ISD::SETULE: Unsigned = true; //fall-through
13461 case ISD::SETLE: SSECC = 2; break;
13465 std::swap(Op0, Op1);
13467 return DAG.getNode(Opc, dl, VT, Op0, Op1);
13468 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
13469 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13470 DAG.getConstant(SSECC, dl, MVT::i8));
13473 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
13474 /// operand \p Op1. If non-trivial (for example because it's not constant)
13475 /// return an empty value.
13476 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
13478 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
13482 MVT VT = Op1.getSimpleValueType();
13483 MVT EVT = VT.getVectorElementType();
13484 unsigned n = VT.getVectorNumElements();
13485 SmallVector<SDValue, 8> ULTOp1;
13487 for (unsigned i = 0; i < n; ++i) {
13488 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
13489 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
13492 // Avoid underflow.
13493 APInt Val = Elt->getAPIntValue();
13497 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
13500 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
13503 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
13504 SelectionDAG &DAG) {
13505 SDValue Op0 = Op.getOperand(0);
13506 SDValue Op1 = Op.getOperand(1);
13507 SDValue CC = Op.getOperand(2);
13508 MVT VT = Op.getSimpleValueType();
13509 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13510 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
13515 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
13516 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
13519 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
13520 unsigned Opc = X86ISD::CMPP;
13521 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
13522 assert(VT.getVectorNumElements() <= 16);
13523 Opc = X86ISD::CMPM;
13525 // In the two special cases we can't handle, emit two comparisons.
13528 unsigned CombineOpc;
13529 if (SetCCOpcode == ISD::SETUEQ) {
13530 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
13532 assert(SetCCOpcode == ISD::SETONE);
13533 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
13536 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13537 DAG.getConstant(CC0, dl, MVT::i8));
13538 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13539 DAG.getConstant(CC1, dl, MVT::i8));
13540 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
13542 // Handle all other FP comparisons here.
13543 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13544 DAG.getConstant(SSECC, dl, MVT::i8));
13547 // Break 256-bit integer vector compare into smaller ones.
13548 if (VT.is256BitVector() && !Subtarget->hasInt256())
13549 return Lower256IntVSETCC(Op, DAG);
13551 EVT OpVT = Op1.getValueType();
13552 if (OpVT.getVectorElementType() == MVT::i1)
13553 return LowerBoolVSETCC_AVX512(Op, DAG);
13555 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
13556 if (Subtarget->hasAVX512()) {
13557 if (Op1.getValueType().is512BitVector() ||
13558 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
13559 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
13560 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
13562 // In AVX-512 architecture setcc returns mask with i1 elements,
13563 // But there is no compare instruction for i8 and i16 elements in KNL.
13564 // We are not talking about 512-bit operands in this case, these
13565 // types are illegal.
13567 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
13568 OpVT.getVectorElementType().getSizeInBits() >= 8))
13569 return DAG.getNode(ISD::TRUNCATE, dl, VT,
13570 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
13573 // We are handling one of the integer comparisons here. Since SSE only has
13574 // GT and EQ comparisons for integer, swapping operands and multiple
13575 // operations may be required for some comparisons.
13577 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
13578 bool Subus = false;
13580 switch (SetCCOpcode) {
13581 default: llvm_unreachable("Unexpected SETCC condition");
13582 case ISD::SETNE: Invert = true;
13583 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
13584 case ISD::SETLT: Swap = true;
13585 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
13586 case ISD::SETGE: Swap = true;
13587 case ISD::SETLE: Opc = X86ISD::PCMPGT;
13588 Invert = true; break;
13589 case ISD::SETULT: Swap = true;
13590 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
13591 FlipSigns = true; break;
13592 case ISD::SETUGE: Swap = true;
13593 case ISD::SETULE: Opc = X86ISD::PCMPGT;
13594 FlipSigns = true; Invert = true; break;
13597 // Special case: Use min/max operations for SETULE/SETUGE
13598 MVT VET = VT.getVectorElementType();
13600 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
13601 || (Subtarget->hasSSE2() && (VET == MVT::i8));
13604 switch (SetCCOpcode) {
13606 case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break;
13607 case ISD::SETUGE: Opc = ISD::UMAX; MinMax = true; break;
13610 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
13613 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
13614 if (!MinMax && hasSubus) {
13615 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
13617 // t = psubus Op0, Op1
13618 // pcmpeq t, <0..0>
13619 switch (SetCCOpcode) {
13621 case ISD::SETULT: {
13622 // If the comparison is against a constant we can turn this into a
13623 // setule. With psubus, setule does not require a swap. This is
13624 // beneficial because the constant in the register is no longer
13625 // destructed as the destination so it can be hoisted out of a loop.
13626 // Only do this pre-AVX since vpcmp* is no longer destructive.
13627 if (Subtarget->hasAVX())
13629 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
13630 if (ULEOp1.getNode()) {
13632 Subus = true; Invert = false; Swap = false;
13636 // Psubus is better than flip-sign because it requires no inversion.
13637 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
13638 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
13642 Opc = X86ISD::SUBUS;
13648 std::swap(Op0, Op1);
13650 // Check that the operation in question is available (most are plain SSE2,
13651 // but PCMPGTQ and PCMPEQQ have different requirements).
13652 if (VT == MVT::v2i64) {
13653 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
13654 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
13656 // First cast everything to the right type.
13657 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
13658 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
13660 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13661 // bits of the inputs before performing those operations. The lower
13662 // compare is always unsigned.
13665 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
13667 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
13668 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
13669 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
13670 Sign, Zero, Sign, Zero);
13672 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
13673 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
13675 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
13676 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
13677 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
13679 // Create masks for only the low parts/high parts of the 64 bit integers.
13680 static const int MaskHi[] = { 1, 1, 3, 3 };
13681 static const int MaskLo[] = { 0, 0, 2, 2 };
13682 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
13683 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
13684 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
13686 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
13687 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
13690 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13692 return DAG.getBitcast(VT, Result);
13695 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
13696 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
13697 // pcmpeqd + pshufd + pand.
13698 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
13700 // First cast everything to the right type.
13701 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
13702 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
13705 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
13707 // Make sure the lower and upper halves are both all-ones.
13708 static const int Mask[] = { 1, 0, 3, 2 };
13709 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
13710 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
13713 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13715 return DAG.getBitcast(VT, Result);
13719 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13720 // bits of the inputs before performing those operations.
13722 EVT EltVT = VT.getVectorElementType();
13723 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
13725 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
13726 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
13729 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
13731 // If the logical-not of the result is required, perform that now.
13733 Result = DAG.getNOT(dl, Result, VT);
13736 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
13739 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
13740 getZeroVector(VT, Subtarget, DAG, dl));
13745 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
13747 MVT VT = Op.getSimpleValueType();
13749 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
13751 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
13752 && "SetCC type must be 8-bit or 1-bit integer");
13753 SDValue Op0 = Op.getOperand(0);
13754 SDValue Op1 = Op.getOperand(1);
13756 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
13758 // Optimize to BT if possible.
13759 // Lower (X & (1 << N)) == 0 to BT(X, N).
13760 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
13761 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
13762 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
13763 Op1.getOpcode() == ISD::Constant &&
13764 cast<ConstantSDNode>(Op1)->isNullValue() &&
13765 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13766 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
13767 if (NewSetCC.getNode()) {
13769 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
13774 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
13776 if (Op1.getOpcode() == ISD::Constant &&
13777 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
13778 cast<ConstantSDNode>(Op1)->isNullValue()) &&
13779 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13781 // If the input is a setcc, then reuse the input setcc or use a new one with
13782 // the inverted condition.
13783 if (Op0.getOpcode() == X86ISD::SETCC) {
13784 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
13785 bool Invert = (CC == ISD::SETNE) ^
13786 cast<ConstantSDNode>(Op1)->isNullValue();
13790 CCode = X86::GetOppositeBranchCondition(CCode);
13791 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13792 DAG.getConstant(CCode, dl, MVT::i8),
13793 Op0.getOperand(1));
13795 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13799 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
13800 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
13801 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13803 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
13804 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
13807 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
13808 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
13809 if (X86CC == X86::COND_INVALID)
13812 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
13813 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
13814 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13815 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
13817 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13821 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
13822 static bool isX86LogicalCmp(SDValue Op) {
13823 unsigned Opc = Op.getNode()->getOpcode();
13824 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
13825 Opc == X86ISD::SAHF)
13827 if (Op.getResNo() == 1 &&
13828 (Opc == X86ISD::ADD ||
13829 Opc == X86ISD::SUB ||
13830 Opc == X86ISD::ADC ||
13831 Opc == X86ISD::SBB ||
13832 Opc == X86ISD::SMUL ||
13833 Opc == X86ISD::UMUL ||
13834 Opc == X86ISD::INC ||
13835 Opc == X86ISD::DEC ||
13836 Opc == X86ISD::OR ||
13837 Opc == X86ISD::XOR ||
13838 Opc == X86ISD::AND))
13841 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
13847 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
13848 if (V.getOpcode() != ISD::TRUNCATE)
13851 SDValue VOp0 = V.getOperand(0);
13852 unsigned InBits = VOp0.getValueSizeInBits();
13853 unsigned Bits = V.getValueSizeInBits();
13854 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
13857 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
13858 bool addTest = true;
13859 SDValue Cond = Op.getOperand(0);
13860 SDValue Op1 = Op.getOperand(1);
13861 SDValue Op2 = Op.getOperand(2);
13863 EVT VT = Op1.getValueType();
13866 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
13867 // are available or VBLENDV if AVX is available.
13868 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
13869 if (Cond.getOpcode() == ISD::SETCC &&
13870 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
13871 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
13872 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
13873 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
13874 int SSECC = translateX86FSETCC(
13875 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
13878 if (Subtarget->hasAVX512()) {
13879 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
13880 DAG.getConstant(SSECC, DL, MVT::i8));
13881 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
13884 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
13885 DAG.getConstant(SSECC, DL, MVT::i8));
13887 // If we have AVX, we can use a variable vector select (VBLENDV) instead
13888 // of 3 logic instructions for size savings and potentially speed.
13889 // Unfortunately, there is no scalar form of VBLENDV.
13891 // If either operand is a constant, don't try this. We can expect to
13892 // optimize away at least one of the logic instructions later in that
13893 // case, so that sequence would be faster than a variable blend.
13895 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
13896 // uses XMM0 as the selection register. That may need just as many
13897 // instructions as the AND/ANDN/OR sequence due to register moves, so
13900 if (Subtarget->hasAVX() &&
13901 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
13903 // Convert to vectors, do a VSELECT, and convert back to scalar.
13904 // All of the conversions should be optimized away.
13906 EVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
13907 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
13908 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
13909 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
13911 EVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
13912 VCmp = DAG.getBitcast(VCmpVT, VCmp);
13914 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
13916 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
13917 VSel, DAG.getIntPtrConstant(0, DL));
13919 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
13920 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
13921 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
13925 if (VT.isVector() && VT.getScalarType() == MVT::i1) {
13927 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
13928 Op1Scalar = ConvertI1VectorToInterger(Op1, DAG);
13929 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
13930 Op1Scalar = Op1.getOperand(0);
13932 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
13933 Op2Scalar = ConvertI1VectorToInterger(Op2, DAG);
13934 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
13935 Op2Scalar = Op2.getOperand(0);
13936 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
13937 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
13938 Op1Scalar.getValueType(),
13939 Cond, Op1Scalar, Op2Scalar);
13940 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
13941 return DAG.getBitcast(VT, newSelect);
13942 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
13943 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
13944 DAG.getIntPtrConstant(0, DL));
13948 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
13949 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
13950 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
13951 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
13952 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
13953 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
13954 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
13956 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
13959 if (Cond.getOpcode() == ISD::SETCC) {
13960 SDValue NewCond = LowerSETCC(Cond, DAG);
13961 if (NewCond.getNode())
13965 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
13966 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
13967 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
13968 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
13969 if (Cond.getOpcode() == X86ISD::SETCC &&
13970 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
13971 isZero(Cond.getOperand(1).getOperand(1))) {
13972 SDValue Cmp = Cond.getOperand(1);
13974 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
13976 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
13977 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
13978 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
13980 SDValue CmpOp0 = Cmp.getOperand(0);
13981 // Apply further optimizations for special cases
13982 // (select (x != 0), -1, 0) -> neg & sbb
13983 // (select (x == 0), 0, -1) -> neg & sbb
13984 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
13985 if (YC->isNullValue() &&
13986 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
13987 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
13988 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
13989 DAG.getConstant(0, DL,
13990 CmpOp0.getValueType()),
13992 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13993 DAG.getConstant(X86::COND_B, DL, MVT::i8),
13994 SDValue(Neg.getNode(), 1));
13998 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
13999 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
14000 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14002 SDValue Res = // Res = 0 or -1.
14003 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14004 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
14006 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14007 Res = DAG.getNOT(DL, Res, Res.getValueType());
14009 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14010 if (!N2C || !N2C->isNullValue())
14011 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14016 // Look past (and (setcc_carry (cmp ...)), 1).
14017 if (Cond.getOpcode() == ISD::AND &&
14018 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14019 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14020 if (C && C->getAPIntValue() == 1)
14021 Cond = Cond.getOperand(0);
14024 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14025 // setting operand in place of the X86ISD::SETCC.
14026 unsigned CondOpcode = Cond.getOpcode();
14027 if (CondOpcode == X86ISD::SETCC ||
14028 CondOpcode == X86ISD::SETCC_CARRY) {
14029 CC = Cond.getOperand(0);
14031 SDValue Cmp = Cond.getOperand(1);
14032 unsigned Opc = Cmp.getOpcode();
14033 MVT VT = Op.getSimpleValueType();
14035 bool IllegalFPCMov = false;
14036 if (VT.isFloatingPoint() && !VT.isVector() &&
14037 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14038 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14040 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14041 Opc == X86ISD::BT) { // FIXME
14045 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14046 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14047 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14048 Cond.getOperand(0).getValueType() != MVT::i8)) {
14049 SDValue LHS = Cond.getOperand(0);
14050 SDValue RHS = Cond.getOperand(1);
14051 unsigned X86Opcode;
14054 switch (CondOpcode) {
14055 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14056 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14057 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14058 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14059 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14060 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14061 default: llvm_unreachable("unexpected overflowing operator");
14063 if (CondOpcode == ISD::UMULO)
14064 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14067 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14069 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14071 if (CondOpcode == ISD::UMULO)
14072 Cond = X86Op.getValue(2);
14074 Cond = X86Op.getValue(1);
14076 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
14081 // Look pass the truncate if the high bits are known zero.
14082 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14083 Cond = Cond.getOperand(0);
14085 // We know the result of AND is compared against zero. Try to match
14087 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14088 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14089 if (NewSetCC.getNode()) {
14090 CC = NewSetCC.getOperand(0);
14091 Cond = NewSetCC.getOperand(1);
14098 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
14099 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14102 // a < b ? -1 : 0 -> RES = ~setcc_carry
14103 // a < b ? 0 : -1 -> RES = setcc_carry
14104 // a >= b ? -1 : 0 -> RES = setcc_carry
14105 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14106 if (Cond.getOpcode() == X86ISD::SUB) {
14107 Cond = ConvertCmpIfNecessary(Cond, DAG);
14108 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14110 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14111 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14112 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14113 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14115 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14116 return DAG.getNOT(DL, Res, Res.getValueType());
14121 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14122 // widen the cmov and push the truncate through. This avoids introducing a new
14123 // branch during isel and doesn't add any extensions.
14124 if (Op.getValueType() == MVT::i8 &&
14125 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14126 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14127 if (T1.getValueType() == T2.getValueType() &&
14128 // Blacklist CopyFromReg to avoid partial register stalls.
14129 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14130 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14131 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14132 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14136 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14137 // condition is true.
14138 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14139 SDValue Ops[] = { Op2, Op1, CC, Cond };
14140 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14143 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
14144 const X86Subtarget *Subtarget,
14145 SelectionDAG &DAG) {
14146 MVT VT = Op->getSimpleValueType(0);
14147 SDValue In = Op->getOperand(0);
14148 MVT InVT = In.getSimpleValueType();
14149 MVT VTElt = VT.getVectorElementType();
14150 MVT InVTElt = InVT.getVectorElementType();
14154 if ((InVTElt == MVT::i1) &&
14155 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
14156 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
14158 ((Subtarget->hasBWI() && VT.is512BitVector() &&
14159 VTElt.getSizeInBits() <= 16)) ||
14161 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
14162 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
14164 ((Subtarget->hasDQI() && VT.is512BitVector() &&
14165 VTElt.getSizeInBits() >= 32))))
14166 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14168 unsigned int NumElts = VT.getVectorNumElements();
14170 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
14173 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
14174 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
14175 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
14176 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14179 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14180 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
14182 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
14185 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
14187 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
14188 if (VT.is512BitVector())
14190 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
14193 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
14194 const X86Subtarget *Subtarget,
14195 SelectionDAG &DAG) {
14196 SDValue In = Op->getOperand(0);
14197 MVT VT = Op->getSimpleValueType(0);
14198 MVT InVT = In.getSimpleValueType();
14199 assert(VT.getSizeInBits() == InVT.getSizeInBits());
14201 MVT InSVT = InVT.getScalarType();
14202 assert(VT.getScalarType().getScalarSizeInBits() > InSVT.getScalarSizeInBits());
14204 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
14206 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
14211 // SSE41 targets can use the pmovsx* instructions directly.
14212 if (Subtarget->hasSSE41())
14213 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14215 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
14219 // As SRAI is only available on i16/i32 types, we expand only up to i32
14220 // and handle i64 separately.
14221 while (CurrVT != VT && CurrVT.getScalarType() != MVT::i32) {
14222 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
14223 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
14224 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
14225 Curr = DAG.getBitcast(CurrVT, Curr);
14228 SDValue SignExt = Curr;
14229 if (CurrVT != InVT) {
14230 unsigned SignExtShift =
14231 CurrVT.getScalarSizeInBits() - InSVT.getScalarSizeInBits();
14232 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14233 DAG.getConstant(SignExtShift, dl, MVT::i8));
14239 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
14240 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14241 DAG.getConstant(31, dl, MVT::i8));
14242 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
14243 return DAG.getBitcast(VT, Ext);
14249 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14250 SelectionDAG &DAG) {
14251 MVT VT = Op->getSimpleValueType(0);
14252 SDValue In = Op->getOperand(0);
14253 MVT InVT = In.getSimpleValueType();
14256 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14257 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
14259 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14260 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14261 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14264 if (Subtarget->hasInt256())
14265 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14267 // Optimize vectors in AVX mode
14268 // Sign extend v8i16 to v8i32 and
14271 // Divide input vector into two parts
14272 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14273 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14274 // concat the vectors to original VT
14276 unsigned NumElems = InVT.getVectorNumElements();
14277 SDValue Undef = DAG.getUNDEF(InVT);
14279 SmallVector<int,8> ShufMask1(NumElems, -1);
14280 for (unsigned i = 0; i != NumElems/2; ++i)
14283 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14285 SmallVector<int,8> ShufMask2(NumElems, -1);
14286 for (unsigned i = 0; i != NumElems/2; ++i)
14287 ShufMask2[i] = i + NumElems/2;
14289 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14291 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14292 VT.getVectorNumElements()/2);
14294 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14295 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14297 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14300 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14301 // may emit an illegal shuffle but the expansion is still better than scalar
14302 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14303 // we'll emit a shuffle and a arithmetic shift.
14304 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
14305 // TODO: It is possible to support ZExt by zeroing the undef values during
14306 // the shuffle phase or after the shuffle.
14307 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14308 SelectionDAG &DAG) {
14309 MVT RegVT = Op.getSimpleValueType();
14310 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14311 assert(RegVT.isInteger() &&
14312 "We only custom lower integer vector sext loads.");
14314 // Nothing useful we can do without SSE2 shuffles.
14315 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
14317 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
14319 EVT MemVT = Ld->getMemoryVT();
14320 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14321 unsigned RegSz = RegVT.getSizeInBits();
14323 ISD::LoadExtType Ext = Ld->getExtensionType();
14325 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
14326 && "Only anyext and sext are currently implemented.");
14327 assert(MemVT != RegVT && "Cannot extend to the same type");
14328 assert(MemVT.isVector() && "Must load a vector from memory");
14330 unsigned NumElems = RegVT.getVectorNumElements();
14331 unsigned MemSz = MemVT.getSizeInBits();
14332 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14334 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
14335 // The only way in which we have a legal 256-bit vector result but not the
14336 // integer 256-bit operations needed to directly lower a sextload is if we
14337 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
14338 // a 128-bit vector and a normal sign_extend to 256-bits that should get
14339 // correctly legalized. We do this late to allow the canonical form of
14340 // sextload to persist throughout the rest of the DAG combiner -- it wants
14341 // to fold together any extensions it can, and so will fuse a sign_extend
14342 // of an sextload into a sextload targeting a wider value.
14344 if (MemSz == 128) {
14345 // Just switch this to a normal load.
14346 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
14347 "it must be a legal 128-bit vector "
14349 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
14350 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
14351 Ld->isInvariant(), Ld->getAlignment());
14353 assert(MemSz < 128 &&
14354 "Can't extend a type wider than 128 bits to a 256 bit vector!");
14355 // Do an sext load to a 128-bit vector type. We want to use the same
14356 // number of elements, but elements half as wide. This will end up being
14357 // recursively lowered by this routine, but will succeed as we definitely
14358 // have all the necessary features if we're using AVX1.
14360 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
14361 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
14363 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
14364 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
14365 Ld->isNonTemporal(), Ld->isInvariant(),
14366 Ld->getAlignment());
14369 // Replace chain users with the new chain.
14370 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
14371 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
14373 // Finally, do a normal sign-extend to the desired register.
14374 return DAG.getSExtOrTrunc(Load, dl, RegVT);
14377 // All sizes must be a power of two.
14378 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
14379 "Non-power-of-two elements are not custom lowered!");
14381 // Attempt to load the original value using scalar loads.
14382 // Find the largest scalar type that divides the total loaded size.
14383 MVT SclrLoadTy = MVT::i8;
14384 for (MVT Tp : MVT::integer_valuetypes()) {
14385 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14390 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14391 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14393 SclrLoadTy = MVT::f64;
14395 // Calculate the number of scalar loads that we need to perform
14396 // in order to load our vector from memory.
14397 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14399 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
14400 "Can only lower sext loads with a single scalar load!");
14402 unsigned loadRegZize = RegSz;
14403 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
14406 // Represent our vector as a sequence of elements which are the
14407 // largest scalar that we can load.
14408 EVT LoadUnitVecVT = EVT::getVectorVT(
14409 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
14411 // Represent the data using the same element type that is stored in
14412 // memory. In practice, we ''widen'' MemVT.
14414 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14415 loadRegZize / MemVT.getScalarType().getSizeInBits());
14417 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14418 "Invalid vector type");
14420 // We can't shuffle using an illegal type.
14421 assert(TLI.isTypeLegal(WideVecVT) &&
14422 "We only lower types that form legal widened vector types");
14424 SmallVector<SDValue, 8> Chains;
14425 SDValue Ptr = Ld->getBasePtr();
14426 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl,
14427 TLI.getPointerTy(DAG.getDataLayout()));
14428 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14430 for (unsigned i = 0; i < NumLoads; ++i) {
14431 // Perform a single load.
14432 SDValue ScalarLoad =
14433 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
14434 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
14435 Ld->getAlignment());
14436 Chains.push_back(ScalarLoad.getValue(1));
14437 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14438 // another round of DAGCombining.
14440 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14442 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14443 ScalarLoad, DAG.getIntPtrConstant(i, dl));
14445 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14448 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
14450 // Bitcast the loaded value to a vector of the original element type, in
14451 // the size of the target vector type.
14452 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
14453 unsigned SizeRatio = RegSz / MemSz;
14455 if (Ext == ISD::SEXTLOAD) {
14456 // If we have SSE4.1, we can directly emit a VSEXT node.
14457 if (Subtarget->hasSSE41()) {
14458 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
14459 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14463 // Otherwise we'll shuffle the small elements in the high bits of the
14464 // larger type and perform an arithmetic shift. If the shift is not legal
14465 // it's better to scalarize.
14466 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
14467 "We can't implement a sext load without an arithmetic right shift!");
14469 // Redistribute the loaded elements into the different locations.
14470 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14471 for (unsigned i = 0; i != NumElems; ++i)
14472 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
14474 SDValue Shuff = DAG.getVectorShuffle(
14475 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14477 Shuff = DAG.getBitcast(RegVT, Shuff);
14479 // Build the arithmetic shift.
14480 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
14481 MemVT.getVectorElementType().getSizeInBits();
14483 DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
14484 DAG.getConstant(Amt, dl, RegVT));
14486 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14490 // Redistribute the loaded elements into the different locations.
14491 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14492 for (unsigned i = 0; i != NumElems; ++i)
14493 ShuffleVec[i * SizeRatio] = i;
14495 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14496 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14498 // Bitcast to the requested type.
14499 Shuff = DAG.getBitcast(RegVT, Shuff);
14500 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14504 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
14505 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
14506 // from the AND / OR.
14507 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
14508 Opc = Op.getOpcode();
14509 if (Opc != ISD::OR && Opc != ISD::AND)
14511 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14512 Op.getOperand(0).hasOneUse() &&
14513 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
14514 Op.getOperand(1).hasOneUse());
14517 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
14518 // 1 and that the SETCC node has a single use.
14519 static bool isXor1OfSetCC(SDValue Op) {
14520 if (Op.getOpcode() != ISD::XOR)
14522 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
14523 if (N1C && N1C->getAPIntValue() == 1) {
14524 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14525 Op.getOperand(0).hasOneUse();
14530 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
14531 bool addTest = true;
14532 SDValue Chain = Op.getOperand(0);
14533 SDValue Cond = Op.getOperand(1);
14534 SDValue Dest = Op.getOperand(2);
14537 bool Inverted = false;
14539 if (Cond.getOpcode() == ISD::SETCC) {
14540 // Check for setcc([su]{add,sub,mul}o == 0).
14541 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
14542 isa<ConstantSDNode>(Cond.getOperand(1)) &&
14543 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
14544 Cond.getOperand(0).getResNo() == 1 &&
14545 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
14546 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
14547 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
14548 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
14549 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
14550 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
14552 Cond = Cond.getOperand(0);
14554 SDValue NewCond = LowerSETCC(Cond, DAG);
14555 if (NewCond.getNode())
14560 // FIXME: LowerXALUO doesn't handle these!!
14561 else if (Cond.getOpcode() == X86ISD::ADD ||
14562 Cond.getOpcode() == X86ISD::SUB ||
14563 Cond.getOpcode() == X86ISD::SMUL ||
14564 Cond.getOpcode() == X86ISD::UMUL)
14565 Cond = LowerXALUO(Cond, DAG);
14568 // Look pass (and (setcc_carry (cmp ...)), 1).
14569 if (Cond.getOpcode() == ISD::AND &&
14570 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14571 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14572 if (C && C->getAPIntValue() == 1)
14573 Cond = Cond.getOperand(0);
14576 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14577 // setting operand in place of the X86ISD::SETCC.
14578 unsigned CondOpcode = Cond.getOpcode();
14579 if (CondOpcode == X86ISD::SETCC ||
14580 CondOpcode == X86ISD::SETCC_CARRY) {
14581 CC = Cond.getOperand(0);
14583 SDValue Cmp = Cond.getOperand(1);
14584 unsigned Opc = Cmp.getOpcode();
14585 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
14586 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
14590 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
14594 // These can only come from an arithmetic instruction with overflow,
14595 // e.g. SADDO, UADDO.
14596 Cond = Cond.getNode()->getOperand(1);
14602 CondOpcode = Cond.getOpcode();
14603 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14604 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14605 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14606 Cond.getOperand(0).getValueType() != MVT::i8)) {
14607 SDValue LHS = Cond.getOperand(0);
14608 SDValue RHS = Cond.getOperand(1);
14609 unsigned X86Opcode;
14612 // Keep this in sync with LowerXALUO, otherwise we might create redundant
14613 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
14615 switch (CondOpcode) {
14616 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14618 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14620 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
14623 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14624 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14626 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14628 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
14631 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14632 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14633 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14634 default: llvm_unreachable("unexpected overflowing operator");
14637 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
14638 if (CondOpcode == ISD::UMULO)
14639 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14642 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14644 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
14646 if (CondOpcode == ISD::UMULO)
14647 Cond = X86Op.getValue(2);
14649 Cond = X86Op.getValue(1);
14651 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
14655 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
14656 SDValue Cmp = Cond.getOperand(0).getOperand(1);
14657 if (CondOpc == ISD::OR) {
14658 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
14659 // two branches instead of an explicit OR instruction with a
14661 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14662 isX86LogicalCmp(Cmp)) {
14663 CC = Cond.getOperand(0).getOperand(0);
14664 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14665 Chain, Dest, CC, Cmp);
14666 CC = Cond.getOperand(1).getOperand(0);
14670 } else { // ISD::AND
14671 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
14672 // two branches instead of an explicit AND instruction with a
14673 // separate test. However, we only do this if this block doesn't
14674 // have a fall-through edge, because this requires an explicit
14675 // jmp when the condition is false.
14676 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14677 isX86LogicalCmp(Cmp) &&
14678 Op.getNode()->hasOneUse()) {
14679 X86::CondCode CCode =
14680 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14681 CCode = X86::GetOppositeBranchCondition(CCode);
14682 CC = DAG.getConstant(CCode, dl, MVT::i8);
14683 SDNode *User = *Op.getNode()->use_begin();
14684 // Look for an unconditional branch following this conditional branch.
14685 // We need this because we need to reverse the successors in order
14686 // to implement FCMP_OEQ.
14687 if (User->getOpcode() == ISD::BR) {
14688 SDValue FalseBB = User->getOperand(1);
14690 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14691 assert(NewBR == User);
14695 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14696 Chain, Dest, CC, Cmp);
14697 X86::CondCode CCode =
14698 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
14699 CCode = X86::GetOppositeBranchCondition(CCode);
14700 CC = DAG.getConstant(CCode, dl, MVT::i8);
14706 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
14707 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
14708 // It should be transformed during dag combiner except when the condition
14709 // is set by a arithmetics with overflow node.
14710 X86::CondCode CCode =
14711 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14712 CCode = X86::GetOppositeBranchCondition(CCode);
14713 CC = DAG.getConstant(CCode, dl, MVT::i8);
14714 Cond = Cond.getOperand(0).getOperand(1);
14716 } else if (Cond.getOpcode() == ISD::SETCC &&
14717 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
14718 // For FCMP_OEQ, we can emit
14719 // two branches instead of an explicit AND instruction with a
14720 // separate test. However, we only do this if this block doesn't
14721 // have a fall-through edge, because this requires an explicit
14722 // jmp when the condition is false.
14723 if (Op.getNode()->hasOneUse()) {
14724 SDNode *User = *Op.getNode()->use_begin();
14725 // Look for an unconditional branch following this conditional branch.
14726 // We need this because we need to reverse the successors in order
14727 // to implement FCMP_OEQ.
14728 if (User->getOpcode() == ISD::BR) {
14729 SDValue FalseBB = User->getOperand(1);
14731 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14732 assert(NewBR == User);
14736 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14737 Cond.getOperand(0), Cond.getOperand(1));
14738 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14739 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
14740 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14741 Chain, Dest, CC, Cmp);
14742 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
14747 } else if (Cond.getOpcode() == ISD::SETCC &&
14748 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
14749 // For FCMP_UNE, we can emit
14750 // two branches instead of an explicit AND instruction with a
14751 // separate test. However, we only do this if this block doesn't
14752 // have a fall-through edge, because this requires an explicit
14753 // jmp when the condition is false.
14754 if (Op.getNode()->hasOneUse()) {
14755 SDNode *User = *Op.getNode()->use_begin();
14756 // Look for an unconditional branch following this conditional branch.
14757 // We need this because we need to reverse the successors in order
14758 // to implement FCMP_UNE.
14759 if (User->getOpcode() == ISD::BR) {
14760 SDValue FalseBB = User->getOperand(1);
14762 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14763 assert(NewBR == User);
14766 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14767 Cond.getOperand(0), Cond.getOperand(1));
14768 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14769 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
14770 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14771 Chain, Dest, CC, Cmp);
14772 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
14782 // Look pass the truncate if the high bits are known zero.
14783 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14784 Cond = Cond.getOperand(0);
14786 // We know the result of AND is compared against zero. Try to match
14788 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14789 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
14790 if (NewSetCC.getNode()) {
14791 CC = NewSetCC.getOperand(0);
14792 Cond = NewSetCC.getOperand(1);
14799 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
14800 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
14801 Cond = EmitTest(Cond, X86Cond, dl, DAG);
14803 Cond = ConvertCmpIfNecessary(Cond, DAG);
14804 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14805 Chain, Dest, CC, Cond);
14808 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
14809 // Calls to _alloca are needed to probe the stack when allocating more than 4k
14810 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
14811 // that the guard pages used by the OS virtual memory manager are allocated in
14812 // correct sequence.
14814 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
14815 SelectionDAG &DAG) const {
14816 MachineFunction &MF = DAG.getMachineFunction();
14817 bool SplitStack = MF.shouldSplitStack();
14818 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
14823 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14824 SDNode* Node = Op.getNode();
14826 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
14827 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
14828 " not tell us which reg is the stack pointer!");
14829 EVT VT = Node->getValueType(0);
14830 SDValue Tmp1 = SDValue(Node, 0);
14831 SDValue Tmp2 = SDValue(Node, 1);
14832 SDValue Tmp3 = Node->getOperand(2);
14833 SDValue Chain = Tmp1.getOperand(0);
14835 // Chain the dynamic stack allocation so that it doesn't modify the stack
14836 // pointer when other instructions are using the stack.
14837 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
14840 SDValue Size = Tmp2.getOperand(1);
14841 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
14842 Chain = SP.getValue(1);
14843 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
14844 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
14845 unsigned StackAlign = TFI.getStackAlignment();
14846 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
14847 if (Align > StackAlign)
14848 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
14849 DAG.getConstant(-(uint64_t)Align, dl, VT));
14850 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
14852 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
14853 DAG.getIntPtrConstant(0, dl, true), SDValue(),
14856 SDValue Ops[2] = { Tmp1, Tmp2 };
14857 return DAG.getMergeValues(Ops, dl);
14861 SDValue Chain = Op.getOperand(0);
14862 SDValue Size = Op.getOperand(1);
14863 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
14864 EVT VT = Op.getNode()->getValueType(0);
14866 bool Is64Bit = Subtarget->is64Bit();
14867 MVT SPTy = getPointerTy(DAG.getDataLayout());
14870 MachineRegisterInfo &MRI = MF.getRegInfo();
14873 // The 64 bit implementation of segmented stacks needs to clobber both r10
14874 // r11. This makes it impossible to use it along with nested parameters.
14875 const Function *F = MF.getFunction();
14877 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
14879 if (I->hasNestAttr())
14880 report_fatal_error("Cannot use segmented stacks with functions that "
14881 "have nested arguments.");
14884 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
14885 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
14886 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
14887 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
14888 DAG.getRegister(Vreg, SPTy));
14889 SDValue Ops1[2] = { Value, Chain };
14890 return DAG.getMergeValues(Ops1, dl);
14893 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
14895 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
14896 Flag = Chain.getValue(1);
14897 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
14899 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
14901 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
14902 unsigned SPReg = RegInfo->getStackRegister();
14903 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
14904 Chain = SP.getValue(1);
14907 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
14908 DAG.getConstant(-(uint64_t)Align, dl, VT));
14909 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
14912 SDValue Ops1[2] = { SP, Chain };
14913 return DAG.getMergeValues(Ops1, dl);
14917 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
14918 MachineFunction &MF = DAG.getMachineFunction();
14919 auto PtrVT = getPointerTy(MF.getDataLayout());
14920 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
14922 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14925 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
14926 // vastart just stores the address of the VarArgsFrameIndex slot into the
14927 // memory location argument.
14928 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
14929 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
14930 MachinePointerInfo(SV), false, false, 0);
14934 // gp_offset (0 - 6 * 8)
14935 // fp_offset (48 - 48 + 8 * 16)
14936 // overflow_arg_area (point to parameters coming in memory).
14938 SmallVector<SDValue, 8> MemOps;
14939 SDValue FIN = Op.getOperand(1);
14941 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
14942 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
14944 FIN, MachinePointerInfo(SV), false, false, 0);
14945 MemOps.push_back(Store);
14948 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
14949 Store = DAG.getStore(Op.getOperand(0), DL,
14950 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
14952 FIN, MachinePointerInfo(SV, 4), false, false, 0);
14953 MemOps.push_back(Store);
14955 // Store ptr to overflow_arg_area
14956 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
14957 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
14958 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
14959 MachinePointerInfo(SV, 8),
14961 MemOps.push_back(Store);
14963 // Store ptr to reg_save_area.
14964 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(8, DL));
14965 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT);
14966 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
14967 MachinePointerInfo(SV, 16), false, false, 0);
14968 MemOps.push_back(Store);
14969 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
14972 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
14973 assert(Subtarget->is64Bit() &&
14974 "LowerVAARG only handles 64-bit va_arg!");
14975 assert((Subtarget->isTargetLinux() ||
14976 Subtarget->isTargetDarwin()) &&
14977 "Unhandled target in LowerVAARG");
14978 assert(Op.getNode()->getNumOperands() == 4);
14979 SDValue Chain = Op.getOperand(0);
14980 SDValue SrcPtr = Op.getOperand(1);
14981 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14982 unsigned Align = Op.getConstantOperandVal(3);
14985 EVT ArgVT = Op.getNode()->getValueType(0);
14986 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
14987 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
14990 // Decide which area this value should be read from.
14991 // TODO: Implement the AMD64 ABI in its entirety. This simple
14992 // selection mechanism works only for the basic types.
14993 if (ArgVT == MVT::f80) {
14994 llvm_unreachable("va_arg for f80 not yet implemented");
14995 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
14996 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
14997 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
14998 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15000 llvm_unreachable("Unhandled argument type in LowerVAARG");
15003 if (ArgMode == 2) {
15004 // Sanity Check: Make sure using fp_offset makes sense.
15005 assert(!Subtarget->useSoftFloat() &&
15006 !(DAG.getMachineFunction().getFunction()->hasFnAttribute(
15007 Attribute::NoImplicitFloat)) &&
15008 Subtarget->hasSSE1());
15011 // Insert VAARG_64 node into the DAG
15012 // VAARG_64 returns two values: Variable Argument Address, Chain
15013 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
15014 DAG.getConstant(ArgMode, dl, MVT::i8),
15015 DAG.getConstant(Align, dl, MVT::i32)};
15016 SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
15017 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15018 VTs, InstOps, MVT::i64,
15019 MachinePointerInfo(SV),
15021 /*Volatile=*/false,
15023 /*WriteMem=*/true);
15024 Chain = VAARG.getValue(1);
15026 // Load the next argument and return it
15027 return DAG.getLoad(ArgVT, dl,
15030 MachinePointerInfo(),
15031 false, false, false, 0);
15034 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15035 SelectionDAG &DAG) {
15036 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
15037 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15038 SDValue Chain = Op.getOperand(0);
15039 SDValue DstPtr = Op.getOperand(1);
15040 SDValue SrcPtr = Op.getOperand(2);
15041 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15042 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15045 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15046 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
15048 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15051 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15052 // amount is a constant. Takes immediate version of shift as input.
15053 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15054 SDValue SrcOp, uint64_t ShiftAmt,
15055 SelectionDAG &DAG) {
15056 MVT ElementType = VT.getVectorElementType();
15058 // Fold this packed shift into its first operand if ShiftAmt is 0.
15062 // Check for ShiftAmt >= element width
15063 if (ShiftAmt >= ElementType.getSizeInBits()) {
15064 if (Opc == X86ISD::VSRAI)
15065 ShiftAmt = ElementType.getSizeInBits() - 1;
15067 return DAG.getConstant(0, dl, VT);
15070 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15071 && "Unknown target vector shift-by-constant node");
15073 // Fold this packed vector shift into a build vector if SrcOp is a
15074 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15075 if (VT == SrcOp.getSimpleValueType() &&
15076 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15077 SmallVector<SDValue, 8> Elts;
15078 unsigned NumElts = SrcOp->getNumOperands();
15079 ConstantSDNode *ND;
15082 default: llvm_unreachable(nullptr);
15083 case X86ISD::VSHLI:
15084 for (unsigned i=0; i!=NumElts; ++i) {
15085 SDValue CurrentOp = SrcOp->getOperand(i);
15086 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15087 Elts.push_back(CurrentOp);
15090 ND = cast<ConstantSDNode>(CurrentOp);
15091 const APInt &C = ND->getAPIntValue();
15092 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
15095 case X86ISD::VSRLI:
15096 for (unsigned i=0; i!=NumElts; ++i) {
15097 SDValue CurrentOp = SrcOp->getOperand(i);
15098 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15099 Elts.push_back(CurrentOp);
15102 ND = cast<ConstantSDNode>(CurrentOp);
15103 const APInt &C = ND->getAPIntValue();
15104 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
15107 case X86ISD::VSRAI:
15108 for (unsigned i=0; i!=NumElts; ++i) {
15109 SDValue CurrentOp = SrcOp->getOperand(i);
15110 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15111 Elts.push_back(CurrentOp);
15114 ND = cast<ConstantSDNode>(CurrentOp);
15115 const APInt &C = ND->getAPIntValue();
15116 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
15121 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15124 return DAG.getNode(Opc, dl, VT, SrcOp,
15125 DAG.getConstant(ShiftAmt, dl, MVT::i8));
15128 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15129 // may or may not be a constant. Takes immediate version of shift as input.
15130 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15131 SDValue SrcOp, SDValue ShAmt,
15132 SelectionDAG &DAG) {
15133 MVT SVT = ShAmt.getSimpleValueType();
15134 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
15136 // Catch shift-by-constant.
15137 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15138 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15139 CShAmt->getZExtValue(), DAG);
15141 // Change opcode to non-immediate version
15143 default: llvm_unreachable("Unknown target vector shift node");
15144 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15145 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15146 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15149 const X86Subtarget &Subtarget =
15150 static_cast<const X86Subtarget &>(DAG.getSubtarget());
15151 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
15152 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
15153 // Let the shuffle legalizer expand this shift amount node.
15154 SDValue Op0 = ShAmt.getOperand(0);
15155 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
15156 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
15158 // Need to build a vector containing shift amount.
15159 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
15160 SmallVector<SDValue, 4> ShOps;
15161 ShOps.push_back(ShAmt);
15162 if (SVT == MVT::i32) {
15163 ShOps.push_back(DAG.getConstant(0, dl, SVT));
15164 ShOps.push_back(DAG.getUNDEF(SVT));
15166 ShOps.push_back(DAG.getUNDEF(SVT));
15168 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
15169 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
15172 // The return type has to be a 128-bit type with the same element
15173 // type as the input type.
15174 MVT EltVT = VT.getVectorElementType();
15175 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15177 ShAmt = DAG.getBitcast(ShVT, ShAmt);
15178 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15181 /// \brief Return (and \p Op, \p Mask) for compare instructions or
15182 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
15183 /// necessary casting for \p Mask when lowering masking intrinsics.
15184 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15185 SDValue PreservedSrc,
15186 const X86Subtarget *Subtarget,
15187 SelectionDAG &DAG) {
15188 EVT VT = Op.getValueType();
15189 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15190 MVT::i1, VT.getVectorNumElements());
15191 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15192 Mask.getValueType().getSizeInBits());
15195 assert(MaskVT.isSimple() && "invalid mask type");
15197 if (isAllOnes(Mask))
15200 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15201 // are extracted by EXTRACT_SUBVECTOR.
15202 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15203 DAG.getBitcast(BitcastVT, Mask),
15204 DAG.getIntPtrConstant(0, dl));
15206 switch (Op.getOpcode()) {
15208 case X86ISD::PCMPEQM:
15209 case X86ISD::PCMPGTM:
15211 case X86ISD::CMPMU:
15212 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
15214 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15215 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15216 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
15219 /// \brief Creates an SDNode for a predicated scalar operation.
15220 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
15221 /// The mask is comming as MVT::i8 and it should be truncated
15222 /// to MVT::i1 while lowering masking intrinsics.
15223 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
15224 /// "X86select" instead of "vselect". We just can't create the "vselect" node for
15225 /// a scalar instruction.
15226 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
15227 SDValue PreservedSrc,
15228 const X86Subtarget *Subtarget,
15229 SelectionDAG &DAG) {
15230 if (isAllOnes(Mask))
15233 EVT VT = Op.getValueType();
15235 // The mask should be of type MVT::i1
15236 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
15238 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15239 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15240 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
15243 static int getSEHRegistrationNodeSize(const Function *Fn) {
15244 if (!Fn->hasPersonalityFn())
15245 report_fatal_error(
15246 "querying registration node size for function without personality");
15247 // The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See
15248 // WinEHStatePass for the full struct definition.
15249 switch (classifyEHPersonality(Fn->getPersonalityFn())) {
15250 case EHPersonality::MSVC_X86SEH: return 24;
15251 case EHPersonality::MSVC_CXX: return 16;
15254 report_fatal_error("can only recover FP for MSVC EH personality functions");
15257 /// When the 32-bit MSVC runtime transfers control to us, either to an outlined
15258 /// function or when returning to a parent frame after catching an exception, we
15259 /// recover the parent frame pointer by doing arithmetic on the incoming EBP.
15260 /// Here's the math:
15261 /// RegNodeBase = EntryEBP - RegNodeSize
15262 /// ParentFP = RegNodeBase - RegNodeFrameOffset
15263 /// Subtracting RegNodeSize takes us to the offset of the registration node, and
15264 /// subtracting the offset (negative on x86) takes us back to the parent FP.
15265 static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,
15266 SDValue EntryEBP) {
15267 MachineFunction &MF = DAG.getMachineFunction();
15270 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15271 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
15273 // It's possible that the parent function no longer has a personality function
15274 // if the exceptional code was optimized away, in which case we just return
15275 // the incoming EBP.
15276 if (!Fn->hasPersonalityFn())
15279 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
15281 // Get an MCSymbol that will ultimately resolve to the frame offset of the EH
15283 MCSymbol *OffsetSym =
15284 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
15285 GlobalValue::getRealLinkageName(Fn->getName()));
15286 SDValue OffsetSymVal = DAG.getMCSymbol(OffsetSym, PtrVT);
15287 SDValue RegNodeFrameOffset =
15288 DAG.getNode(ISD::LOCAL_RECOVER, dl, PtrVT, OffsetSymVal);
15290 // RegNodeBase = EntryEBP - RegNodeSize
15291 // ParentFP = RegNodeBase - RegNodeFrameOffset
15292 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
15293 DAG.getConstant(RegNodeSize, dl, PtrVT));
15294 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, RegNodeFrameOffset);
15297 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15298 SelectionDAG &DAG) {
15300 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15301 EVT VT = Op.getValueType();
15302 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15304 switch(IntrData->Type) {
15305 case INTR_TYPE_1OP:
15306 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15307 case INTR_TYPE_2OP:
15308 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15310 case INTR_TYPE_3OP:
15311 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15312 Op.getOperand(2), Op.getOperand(3));
15313 case INTR_TYPE_4OP:
15314 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15315 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4));
15316 case INTR_TYPE_1OP_MASK_RM: {
15317 SDValue Src = Op.getOperand(1);
15318 SDValue PassThru = Op.getOperand(2);
15319 SDValue Mask = Op.getOperand(3);
15320 SDValue RoundingMode;
15321 if (Op.getNumOperands() == 4)
15322 RoundingMode = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
15324 RoundingMode = Op.getOperand(4);
15325 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15326 if (IntrWithRoundingModeOpcode != 0) {
15327 unsigned Round = cast<ConstantSDNode>(RoundingMode)->getZExtValue();
15328 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION)
15329 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15330 dl, Op.getValueType(), Src, RoundingMode),
15331 Mask, PassThru, Subtarget, DAG);
15333 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
15335 Mask, PassThru, Subtarget, DAG);
15337 case INTR_TYPE_1OP_MASK: {
15338 SDValue Src = Op.getOperand(1);
15339 SDValue Passthru = Op.getOperand(2);
15340 SDValue Mask = Op.getOperand(3);
15341 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
15342 Mask, Passthru, Subtarget, DAG);
15344 case INTR_TYPE_SCALAR_MASK_RM: {
15345 SDValue Src1 = Op.getOperand(1);
15346 SDValue Src2 = Op.getOperand(2);
15347 SDValue Src0 = Op.getOperand(3);
15348 SDValue Mask = Op.getOperand(4);
15349 // There are 2 kinds of intrinsics in this group:
15350 // (1) With supress-all-exceptions (sae) or rounding mode- 6 operands
15351 // (2) With rounding mode and sae - 7 operands.
15352 if (Op.getNumOperands() == 6) {
15353 SDValue Sae = Op.getOperand(5);
15354 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
15355 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
15357 Mask, Src0, Subtarget, DAG);
15359 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
15360 SDValue RoundingMode = Op.getOperand(5);
15361 SDValue Sae = Op.getOperand(6);
15362 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
15363 RoundingMode, Sae),
15364 Mask, Src0, Subtarget, DAG);
15366 case INTR_TYPE_2OP_MASK: {
15367 SDValue Src1 = Op.getOperand(1);
15368 SDValue Src2 = Op.getOperand(2);
15369 SDValue PassThru = Op.getOperand(3);
15370 SDValue Mask = Op.getOperand(4);
15371 // We specify 2 possible opcodes for intrinsics with rounding modes.
15372 // First, we check if the intrinsic may have non-default rounding mode,
15373 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15374 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15375 if (IntrWithRoundingModeOpcode != 0) {
15376 SDValue Rnd = Op.getOperand(5);
15377 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
15378 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
15379 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15380 dl, Op.getValueType(),
15382 Mask, PassThru, Subtarget, DAG);
15385 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15387 Mask, PassThru, Subtarget, DAG);
15389 case INTR_TYPE_2OP_MASK_RM: {
15390 SDValue Src1 = Op.getOperand(1);
15391 SDValue Src2 = Op.getOperand(2);
15392 SDValue PassThru = Op.getOperand(3);
15393 SDValue Mask = Op.getOperand(4);
15394 // We specify 2 possible modes for intrinsics, with/without rounding modes.
15395 // First, we check if the intrinsic have rounding mode (6 operands),
15396 // if not, we set rounding mode to "current".
15398 if (Op.getNumOperands() == 6)
15399 Rnd = Op.getOperand(5);
15401 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
15402 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15404 Mask, PassThru, Subtarget, DAG);
15406 case INTR_TYPE_3OP_MASK: {
15407 SDValue Src1 = Op.getOperand(1);
15408 SDValue Src2 = Op.getOperand(2);
15409 SDValue Src3 = Op.getOperand(3);
15410 SDValue PassThru = Op.getOperand(4);
15411 SDValue Mask = Op.getOperand(5);
15412 // We specify 2 possible opcodes for intrinsics with rounding modes.
15413 // First, we check if the intrinsic may have non-default rounding mode,
15414 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15415 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15416 if (IntrWithRoundingModeOpcode != 0) {
15417 SDValue Rnd = Op.getOperand(6);
15418 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
15419 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
15420 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15421 dl, Op.getValueType(),
15422 Src1, Src2, Src3, Rnd),
15423 Mask, PassThru, Subtarget, DAG);
15426 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15428 Mask, PassThru, Subtarget, DAG);
15430 case VPERM_3OP_MASKZ:
15431 case VPERM_3OP_MASK:
15434 case FMA_OP_MASK: {
15435 SDValue Src1 = Op.getOperand(1);
15436 SDValue Src2 = Op.getOperand(2);
15437 SDValue Src3 = Op.getOperand(3);
15438 SDValue Mask = Op.getOperand(4);
15439 EVT VT = Op.getValueType();
15440 SDValue PassThru = SDValue();
15442 // set PassThru element
15443 if (IntrData->Type == VPERM_3OP_MASKZ || IntrData->Type == FMA_OP_MASKZ)
15444 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
15445 else if (IntrData->Type == FMA_OP_MASK3)
15450 // We specify 2 possible opcodes for intrinsics with rounding modes.
15451 // First, we check if the intrinsic may have non-default rounding mode,
15452 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15453 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15454 if (IntrWithRoundingModeOpcode != 0) {
15455 SDValue Rnd = Op.getOperand(5);
15456 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
15457 X86::STATIC_ROUNDING::CUR_DIRECTION)
15458 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15459 dl, Op.getValueType(),
15460 Src1, Src2, Src3, Rnd),
15461 Mask, PassThru, Subtarget, DAG);
15463 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
15464 dl, Op.getValueType(),
15466 Mask, PassThru, Subtarget, DAG);
15469 case CMP_MASK_CC: {
15470 // Comparison intrinsics with masks.
15471 // Example of transformation:
15472 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
15473 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
15475 // (v8i1 (insert_subvector undef,
15476 // (v2i1 (and (PCMPEQM %a, %b),
15477 // (extract_subvector
15478 // (v8i1 (bitcast %mask)), 0))), 0))))
15479 EVT VT = Op.getOperand(1).getValueType();
15480 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15481 VT.getVectorNumElements());
15482 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
15483 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15484 Mask.getValueType().getSizeInBits());
15486 if (IntrData->Type == CMP_MASK_CC) {
15487 SDValue CC = Op.getOperand(3);
15488 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
15489 // We specify 2 possible opcodes for intrinsics with rounding modes.
15490 // First, we check if the intrinsic may have non-default rounding mode,
15491 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15492 if (IntrData->Opc1 != 0) {
15493 SDValue Rnd = Op.getOperand(5);
15494 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
15495 X86::STATIC_ROUNDING::CUR_DIRECTION)
15496 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
15497 Op.getOperand(2), CC, Rnd);
15499 //default rounding mode
15501 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
15502 Op.getOperand(2), CC);
15505 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
15506 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
15509 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
15510 DAG.getTargetConstant(0, dl,
15513 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
15514 DAG.getUNDEF(BitcastVT), CmpMask,
15515 DAG.getIntPtrConstant(0, dl));
15516 return DAG.getBitcast(Op.getValueType(), Res);
15518 case COMI: { // Comparison intrinsics
15519 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
15520 SDValue LHS = Op.getOperand(1);
15521 SDValue RHS = Op.getOperand(2);
15522 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
15523 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
15524 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
15525 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15526 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
15527 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15530 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
15531 Op.getOperand(1), Op.getOperand(2), DAG);
15533 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
15534 Op.getSimpleValueType(),
15536 Op.getOperand(2), DAG),
15537 Op.getOperand(4), Op.getOperand(3), Subtarget,
15539 case COMPRESS_EXPAND_IN_REG: {
15540 SDValue Mask = Op.getOperand(3);
15541 SDValue DataToCompress = Op.getOperand(1);
15542 SDValue PassThru = Op.getOperand(2);
15543 if (isAllOnes(Mask)) // return data as is
15544 return Op.getOperand(1);
15546 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15548 Mask, PassThru, Subtarget, DAG);
15551 SDValue Mask = Op.getOperand(3);
15552 EVT VT = Op.getValueType();
15553 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15554 VT.getVectorNumElements());
15555 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15556 Mask.getValueType().getSizeInBits());
15558 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15559 DAG.getBitcast(BitcastVT, Mask),
15560 DAG.getIntPtrConstant(0, dl));
15561 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
15570 default: return SDValue(); // Don't custom lower most intrinsics.
15572 case Intrinsic::x86_avx2_permd:
15573 case Intrinsic::x86_avx2_permps:
15574 // Operands intentionally swapped. Mask is last operand to intrinsic,
15575 // but second operand for node/instruction.
15576 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
15577 Op.getOperand(2), Op.getOperand(1));
15579 // ptest and testp intrinsics. The intrinsic these come from are designed to
15580 // return an integer value, not just an instruction so lower it to the ptest
15581 // or testp pattern and a setcc for the result.
15582 case Intrinsic::x86_sse41_ptestz:
15583 case Intrinsic::x86_sse41_ptestc:
15584 case Intrinsic::x86_sse41_ptestnzc:
15585 case Intrinsic::x86_avx_ptestz_256:
15586 case Intrinsic::x86_avx_ptestc_256:
15587 case Intrinsic::x86_avx_ptestnzc_256:
15588 case Intrinsic::x86_avx_vtestz_ps:
15589 case Intrinsic::x86_avx_vtestc_ps:
15590 case Intrinsic::x86_avx_vtestnzc_ps:
15591 case Intrinsic::x86_avx_vtestz_pd:
15592 case Intrinsic::x86_avx_vtestc_pd:
15593 case Intrinsic::x86_avx_vtestnzc_pd:
15594 case Intrinsic::x86_avx_vtestz_ps_256:
15595 case Intrinsic::x86_avx_vtestc_ps_256:
15596 case Intrinsic::x86_avx_vtestnzc_ps_256:
15597 case Intrinsic::x86_avx_vtestz_pd_256:
15598 case Intrinsic::x86_avx_vtestc_pd_256:
15599 case Intrinsic::x86_avx_vtestnzc_pd_256: {
15600 bool IsTestPacked = false;
15603 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
15604 case Intrinsic::x86_avx_vtestz_ps:
15605 case Intrinsic::x86_avx_vtestz_pd:
15606 case Intrinsic::x86_avx_vtestz_ps_256:
15607 case Intrinsic::x86_avx_vtestz_pd_256:
15608 IsTestPacked = true; // Fallthrough
15609 case Intrinsic::x86_sse41_ptestz:
15610 case Intrinsic::x86_avx_ptestz_256:
15612 X86CC = X86::COND_E;
15614 case Intrinsic::x86_avx_vtestc_ps:
15615 case Intrinsic::x86_avx_vtestc_pd:
15616 case Intrinsic::x86_avx_vtestc_ps_256:
15617 case Intrinsic::x86_avx_vtestc_pd_256:
15618 IsTestPacked = true; // Fallthrough
15619 case Intrinsic::x86_sse41_ptestc:
15620 case Intrinsic::x86_avx_ptestc_256:
15622 X86CC = X86::COND_B;
15624 case Intrinsic::x86_avx_vtestnzc_ps:
15625 case Intrinsic::x86_avx_vtestnzc_pd:
15626 case Intrinsic::x86_avx_vtestnzc_ps_256:
15627 case Intrinsic::x86_avx_vtestnzc_pd_256:
15628 IsTestPacked = true; // Fallthrough
15629 case Intrinsic::x86_sse41_ptestnzc:
15630 case Intrinsic::x86_avx_ptestnzc_256:
15632 X86CC = X86::COND_A;
15636 SDValue LHS = Op.getOperand(1);
15637 SDValue RHS = Op.getOperand(2);
15638 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
15639 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
15640 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
15641 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
15642 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15644 case Intrinsic::x86_avx512_kortestz_w:
15645 case Intrinsic::x86_avx512_kortestc_w: {
15646 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
15647 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
15648 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
15649 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
15650 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
15651 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
15652 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15655 case Intrinsic::x86_sse42_pcmpistria128:
15656 case Intrinsic::x86_sse42_pcmpestria128:
15657 case Intrinsic::x86_sse42_pcmpistric128:
15658 case Intrinsic::x86_sse42_pcmpestric128:
15659 case Intrinsic::x86_sse42_pcmpistrio128:
15660 case Intrinsic::x86_sse42_pcmpestrio128:
15661 case Intrinsic::x86_sse42_pcmpistris128:
15662 case Intrinsic::x86_sse42_pcmpestris128:
15663 case Intrinsic::x86_sse42_pcmpistriz128:
15664 case Intrinsic::x86_sse42_pcmpestriz128: {
15668 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15669 case Intrinsic::x86_sse42_pcmpistria128:
15670 Opcode = X86ISD::PCMPISTRI;
15671 X86CC = X86::COND_A;
15673 case Intrinsic::x86_sse42_pcmpestria128:
15674 Opcode = X86ISD::PCMPESTRI;
15675 X86CC = X86::COND_A;
15677 case Intrinsic::x86_sse42_pcmpistric128:
15678 Opcode = X86ISD::PCMPISTRI;
15679 X86CC = X86::COND_B;
15681 case Intrinsic::x86_sse42_pcmpestric128:
15682 Opcode = X86ISD::PCMPESTRI;
15683 X86CC = X86::COND_B;
15685 case Intrinsic::x86_sse42_pcmpistrio128:
15686 Opcode = X86ISD::PCMPISTRI;
15687 X86CC = X86::COND_O;
15689 case Intrinsic::x86_sse42_pcmpestrio128:
15690 Opcode = X86ISD::PCMPESTRI;
15691 X86CC = X86::COND_O;
15693 case Intrinsic::x86_sse42_pcmpistris128:
15694 Opcode = X86ISD::PCMPISTRI;
15695 X86CC = X86::COND_S;
15697 case Intrinsic::x86_sse42_pcmpestris128:
15698 Opcode = X86ISD::PCMPESTRI;
15699 X86CC = X86::COND_S;
15701 case Intrinsic::x86_sse42_pcmpistriz128:
15702 Opcode = X86ISD::PCMPISTRI;
15703 X86CC = X86::COND_E;
15705 case Intrinsic::x86_sse42_pcmpestriz128:
15706 Opcode = X86ISD::PCMPESTRI;
15707 X86CC = X86::COND_E;
15710 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15711 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15712 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
15713 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15714 DAG.getConstant(X86CC, dl, MVT::i8),
15715 SDValue(PCMP.getNode(), 1));
15716 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15719 case Intrinsic::x86_sse42_pcmpistri128:
15720 case Intrinsic::x86_sse42_pcmpestri128: {
15722 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
15723 Opcode = X86ISD::PCMPISTRI;
15725 Opcode = X86ISD::PCMPESTRI;
15727 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15728 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15729 return DAG.getNode(Opcode, dl, VTs, NewOps);
15732 case Intrinsic::x86_seh_lsda: {
15733 // Compute the symbol for the LSDA. We know it'll get emitted later.
15734 MachineFunction &MF = DAG.getMachineFunction();
15735 SDValue Op1 = Op.getOperand(1);
15736 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
15737 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
15738 GlobalValue::getRealLinkageName(Fn->getName()));
15740 // Generate a simple absolute symbol reference. This intrinsic is only
15741 // supported on 32-bit Windows, which isn't PIC.
15742 SDValue Result = DAG.getMCSymbol(LSDASym, VT);
15743 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
15746 case Intrinsic::x86_seh_recoverfp: {
15747 SDValue FnOp = Op.getOperand(1);
15748 SDValue IncomingFPOp = Op.getOperand(2);
15749 GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(FnOp);
15750 auto *Fn = dyn_cast_or_null<Function>(GSD ? GSD->getGlobal() : nullptr);
15752 report_fatal_error(
15753 "llvm.x86.seh.recoverfp must take a function as the first argument");
15754 return recoverFramePointer(DAG, Fn, IncomingFPOp);
15757 case Intrinsic::localaddress: {
15758 // Returns one of the stack, base, or frame pointer registers, depending on
15759 // which is used to reference local variables.
15760 MachineFunction &MF = DAG.getMachineFunction();
15761 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15763 if (RegInfo->hasBasePointer(MF))
15764 Reg = RegInfo->getBaseRegister();
15765 else // This function handles the SP or FP case.
15766 Reg = RegInfo->getPtrSizedFrameRegister(MF);
15767 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
15772 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15773 SDValue Src, SDValue Mask, SDValue Base,
15774 SDValue Index, SDValue ScaleOp, SDValue Chain,
15775 const X86Subtarget * Subtarget) {
15777 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15779 llvm_unreachable("Invalid scale type");
15780 unsigned ScaleVal = C->getZExtValue();
15781 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
15782 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
15784 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15785 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15786 Index.getSimpleValueType().getVectorNumElements());
15788 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15790 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15792 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15793 Mask.getValueType().getSizeInBits());
15795 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15796 // are extracted by EXTRACT_SUBVECTOR.
15797 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15798 DAG.getBitcast(BitcastVT, Mask),
15799 DAG.getIntPtrConstant(0, dl));
15801 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
15802 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15803 SDValue Segment = DAG.getRegister(0, MVT::i32);
15804 if (Src.getOpcode() == ISD::UNDEF)
15805 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
15806 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15807 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15808 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
15809 return DAG.getMergeValues(RetOps, dl);
15812 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15813 SDValue Src, SDValue Mask, SDValue Base,
15814 SDValue Index, SDValue ScaleOp, SDValue Chain) {
15816 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15818 llvm_unreachable("Invalid scale type");
15819 unsigned ScaleVal = C->getZExtValue();
15820 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
15821 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
15823 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15824 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15825 SDValue Segment = DAG.getRegister(0, MVT::i32);
15826 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15827 Index.getSimpleValueType().getVectorNumElements());
15829 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15831 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15833 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15834 Mask.getValueType().getSizeInBits());
15836 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15837 // are extracted by EXTRACT_SUBVECTOR.
15838 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15839 DAG.getBitcast(BitcastVT, Mask),
15840 DAG.getIntPtrConstant(0, dl));
15842 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
15843 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
15844 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15845 return SDValue(Res, 1);
15848 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15849 SDValue Mask, SDValue Base, SDValue Index,
15850 SDValue ScaleOp, SDValue Chain) {
15852 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15853 assert(C && "Invalid scale type");
15854 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15855 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15856 SDValue Segment = DAG.getRegister(0, MVT::i32);
15858 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
15860 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15862 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15864 MaskInReg = DAG.getBitcast(MaskVT, Mask);
15865 //SDVTList VTs = DAG.getVTList(MVT::Other);
15866 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15867 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
15868 return SDValue(Res, 0);
15871 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
15872 // read performance monitor counters (x86_rdpmc).
15873 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
15874 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15875 SmallVectorImpl<SDValue> &Results) {
15876 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15877 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15880 // The ECX register is used to select the index of the performance counter
15882 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
15884 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
15886 // Reads the content of a 64-bit performance counter and returns it in the
15887 // registers EDX:EAX.
15888 if (Subtarget->is64Bit()) {
15889 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15890 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15893 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15894 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15897 Chain = HI.getValue(1);
15899 if (Subtarget->is64Bit()) {
15900 // The EAX register is loaded with the low-order 32 bits. The EDX register
15901 // is loaded with the supported high-order bits of the counter.
15902 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15903 DAG.getConstant(32, DL, MVT::i8));
15904 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15905 Results.push_back(Chain);
15909 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15910 SDValue Ops[] = { LO, HI };
15911 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15912 Results.push_back(Pair);
15913 Results.push_back(Chain);
15916 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
15917 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
15918 // also used to custom lower READCYCLECOUNTER nodes.
15919 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
15920 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15921 SmallVectorImpl<SDValue> &Results) {
15922 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15923 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
15926 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
15927 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
15928 // and the EAX register is loaded with the low-order 32 bits.
15929 if (Subtarget->is64Bit()) {
15930 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15931 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15934 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15935 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15938 SDValue Chain = HI.getValue(1);
15940 if (Opcode == X86ISD::RDTSCP_DAG) {
15941 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15943 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
15944 // the ECX register. Add 'ecx' explicitly to the chain.
15945 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
15947 // Explicitly store the content of ECX at the location passed in input
15948 // to the 'rdtscp' intrinsic.
15949 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
15950 MachinePointerInfo(), false, false, 0);
15953 if (Subtarget->is64Bit()) {
15954 // The EDX register is loaded with the high-order 32 bits of the MSR, and
15955 // the EAX register is loaded with the low-order 32 bits.
15956 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15957 DAG.getConstant(32, DL, MVT::i8));
15958 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15959 Results.push_back(Chain);
15963 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15964 SDValue Ops[] = { LO, HI };
15965 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15966 Results.push_back(Pair);
15967 Results.push_back(Chain);
15970 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
15971 SelectionDAG &DAG) {
15972 SmallVector<SDValue, 2> Results;
15974 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
15976 return DAG.getMergeValues(Results, DL);
15979 static SDValue LowerSEHRESTOREFRAME(SDValue Op, const X86Subtarget *Subtarget,
15980 SelectionDAG &DAG) {
15981 MachineFunction &MF = DAG.getMachineFunction();
15982 const Function *Fn = MF.getFunction();
15984 SDValue Chain = Op.getOperand(0);
15986 assert(Subtarget->getFrameLowering()->hasFP(MF) &&
15987 "using llvm.x86.seh.restoreframe requires a frame pointer");
15989 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15990 MVT VT = TLI.getPointerTy(DAG.getDataLayout());
15992 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15993 unsigned FrameReg =
15994 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
15995 unsigned SPReg = RegInfo->getStackRegister();
15996 unsigned SlotSize = RegInfo->getSlotSize();
15998 // Get incoming EBP.
15999 SDValue IncomingEBP =
16000 DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
16002 // SP is saved in the first field of every registration node, so load
16003 // [EBP-RegNodeSize] into SP.
16004 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16005 SDValue SPAddr = DAG.getNode(ISD::ADD, dl, VT, IncomingEBP,
16006 DAG.getConstant(-RegNodeSize, dl, VT));
16008 DAG.getLoad(VT, dl, Chain, SPAddr, MachinePointerInfo(), false, false,
16009 false, VT.getScalarSizeInBits() / 8);
16010 Chain = DAG.getCopyToReg(Chain, dl, SPReg, NewSP);
16012 if (!RegInfo->needsStackRealignment(MF)) {
16013 // Adjust EBP to point back to the original frame position.
16014 SDValue NewFP = recoverFramePointer(DAG, Fn, IncomingEBP);
16015 Chain = DAG.getCopyToReg(Chain, dl, FrameReg, NewFP);
16017 assert(RegInfo->hasBasePointer(MF) &&
16018 "functions with Win32 EH must use frame or base pointer register");
16020 // Reload the base pointer (ESI) with the adjusted incoming EBP.
16021 SDValue NewBP = recoverFramePointer(DAG, Fn, IncomingEBP);
16022 Chain = DAG.getCopyToReg(Chain, dl, RegInfo->getBaseRegister(), NewBP);
16024 // Reload the spilled EBP value, now that the stack and base pointers are
16026 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
16027 X86FI->setHasSEHFramePtrSave(true);
16028 int FI = MF.getFrameInfo()->CreateSpillStackObject(SlotSize, SlotSize);
16029 X86FI->setSEHFramePtrSaveIndex(FI);
16030 SDValue NewFP = DAG.getLoad(VT, dl, Chain, DAG.getFrameIndex(FI, VT),
16031 MachinePointerInfo(), false, false, false,
16032 VT.getScalarSizeInBits() / 8);
16033 Chain = DAG.getCopyToReg(NewFP, dl, FrameReg, NewFP);
16039 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16040 SelectionDAG &DAG) {
16041 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
16043 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
16045 if (IntNo == llvm::Intrinsic::x86_seh_restoreframe)
16046 return LowerSEHRESTOREFRAME(Op, Subtarget, DAG);
16051 switch(IntrData->Type) {
16053 llvm_unreachable("Unknown Intrinsic Type");
16057 // Emit the node with the right value type.
16058 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16059 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16061 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16062 // Otherwise return the value from Rand, which is always 0, casted to i32.
16063 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16064 DAG.getConstant(1, dl, Op->getValueType(1)),
16065 DAG.getConstant(X86::COND_B, dl, MVT::i32),
16066 SDValue(Result.getNode(), 1) };
16067 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
16068 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16071 // Return { result, isValid, chain }.
16072 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16073 SDValue(Result.getNode(), 2));
16076 //gather(v1, mask, index, base, scale);
16077 SDValue Chain = Op.getOperand(0);
16078 SDValue Src = Op.getOperand(2);
16079 SDValue Base = Op.getOperand(3);
16080 SDValue Index = Op.getOperand(4);
16081 SDValue Mask = Op.getOperand(5);
16082 SDValue Scale = Op.getOperand(6);
16083 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
16087 //scatter(base, mask, index, v1, scale);
16088 SDValue Chain = Op.getOperand(0);
16089 SDValue Base = Op.getOperand(2);
16090 SDValue Mask = Op.getOperand(3);
16091 SDValue Index = Op.getOperand(4);
16092 SDValue Src = Op.getOperand(5);
16093 SDValue Scale = Op.getOperand(6);
16094 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
16098 SDValue Hint = Op.getOperand(6);
16099 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
16100 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
16101 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
16102 SDValue Chain = Op.getOperand(0);
16103 SDValue Mask = Op.getOperand(2);
16104 SDValue Index = Op.getOperand(3);
16105 SDValue Base = Op.getOperand(4);
16106 SDValue Scale = Op.getOperand(5);
16107 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
16109 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
16111 SmallVector<SDValue, 2> Results;
16112 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
16114 return DAG.getMergeValues(Results, dl);
16116 // Read Performance Monitoring Counters.
16118 SmallVector<SDValue, 2> Results;
16119 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
16120 return DAG.getMergeValues(Results, dl);
16122 // XTEST intrinsics.
16124 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16125 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16126 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16127 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
16129 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
16130 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
16131 Ret, SDValue(InTrans.getNode(), 1));
16135 SmallVector<SDValue, 2> Results;
16136 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16137 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
16138 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
16139 DAG.getConstant(-1, dl, MVT::i8));
16140 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
16141 Op.getOperand(4), GenCF.getValue(1));
16142 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
16143 Op.getOperand(5), MachinePointerInfo(),
16145 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16146 DAG.getConstant(X86::COND_B, dl, MVT::i8),
16148 Results.push_back(SetCC);
16149 Results.push_back(Store);
16150 return DAG.getMergeValues(Results, dl);
16152 case COMPRESS_TO_MEM: {
16154 SDValue Mask = Op.getOperand(4);
16155 SDValue DataToCompress = Op.getOperand(3);
16156 SDValue Addr = Op.getOperand(2);
16157 SDValue Chain = Op.getOperand(0);
16159 EVT VT = DataToCompress.getValueType();
16160 if (isAllOnes(Mask)) // return just a store
16161 return DAG.getStore(Chain, dl, DataToCompress, Addr,
16162 MachinePointerInfo(), false, false,
16163 VT.getScalarSizeInBits()/8);
16165 SDValue Compressed =
16166 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToCompress),
16167 Mask, DAG.getUNDEF(VT), Subtarget, DAG);
16168 return DAG.getStore(Chain, dl, Compressed, Addr,
16169 MachinePointerInfo(), false, false,
16170 VT.getScalarSizeInBits()/8);
16172 case EXPAND_FROM_MEM: {
16174 SDValue Mask = Op.getOperand(4);
16175 SDValue PassThru = Op.getOperand(3);
16176 SDValue Addr = Op.getOperand(2);
16177 SDValue Chain = Op.getOperand(0);
16178 EVT VT = Op.getValueType();
16180 if (isAllOnes(Mask)) // return just a load
16181 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
16182 false, VT.getScalarSizeInBits()/8);
16184 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
16185 false, false, false,
16186 VT.getScalarSizeInBits()/8);
16188 SDValue Results[] = {
16189 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToExpand),
16190 Mask, PassThru, Subtarget, DAG), Chain};
16191 return DAG.getMergeValues(Results, dl);
16196 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
16197 SelectionDAG &DAG) const {
16198 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16199 MFI->setReturnAddressIsTaken(true);
16201 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
16204 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16206 EVT PtrVT = getPointerTy(DAG.getDataLayout());
16209 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
16210 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16211 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
16212 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16213 DAG.getNode(ISD::ADD, dl, PtrVT,
16214 FrameAddr, Offset),
16215 MachinePointerInfo(), false, false, false, 0);
16218 // Just load the return address.
16219 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
16220 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16221 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
16224 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
16225 MachineFunction &MF = DAG.getMachineFunction();
16226 MachineFrameInfo *MFI = MF.getFrameInfo();
16227 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16228 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16229 EVT VT = Op.getValueType();
16231 MFI->setFrameAddressIsTaken(true);
16233 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
16234 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
16235 // is not possible to crawl up the stack without looking at the unwind codes
16237 int FrameAddrIndex = FuncInfo->getFAIndex();
16238 if (!FrameAddrIndex) {
16239 // Set up a frame object for the return address.
16240 unsigned SlotSize = RegInfo->getSlotSize();
16241 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
16242 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
16243 FuncInfo->setFAIndex(FrameAddrIndex);
16245 return DAG.getFrameIndex(FrameAddrIndex, VT);
16248 unsigned FrameReg =
16249 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
16250 SDLoc dl(Op); // FIXME probably not meaningful
16251 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16252 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
16253 (FrameReg == X86::EBP && VT == MVT::i32)) &&
16254 "Invalid Frame Register!");
16255 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
16257 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
16258 MachinePointerInfo(),
16259 false, false, false, 0);
16263 // FIXME? Maybe this could be a TableGen attribute on some registers and
16264 // this table could be generated automatically from RegInfo.
16265 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
16267 unsigned Reg = StringSwitch<unsigned>(RegName)
16268 .Case("esp", X86::ESP)
16269 .Case("rsp", X86::RSP)
16273 report_fatal_error("Invalid register name global variable");
16276 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
16277 SelectionDAG &DAG) const {
16278 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16279 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
16282 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
16283 SDValue Chain = Op.getOperand(0);
16284 SDValue Offset = Op.getOperand(1);
16285 SDValue Handler = Op.getOperand(2);
16288 EVT PtrVT = getPointerTy(DAG.getDataLayout());
16289 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16290 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16291 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
16292 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
16293 "Invalid Frame Register!");
16294 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
16295 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
16297 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
16298 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
16300 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
16301 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
16303 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
16305 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
16306 DAG.getRegister(StoreAddrReg, PtrVT));
16309 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
16310 SelectionDAG &DAG) const {
16312 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
16313 DAG.getVTList(MVT::i32, MVT::Other),
16314 Op.getOperand(0), Op.getOperand(1));
16317 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
16318 SelectionDAG &DAG) const {
16320 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
16321 Op.getOperand(0), Op.getOperand(1));
16324 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
16325 return Op.getOperand(0);
16328 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
16329 SelectionDAG &DAG) const {
16330 SDValue Root = Op.getOperand(0);
16331 SDValue Trmp = Op.getOperand(1); // trampoline
16332 SDValue FPtr = Op.getOperand(2); // nested function
16333 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
16336 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16337 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
16339 if (Subtarget->is64Bit()) {
16340 SDValue OutChains[6];
16342 // Large code-model.
16343 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
16344 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
16346 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
16347 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
16349 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
16351 // Load the pointer to the nested function into R11.
16352 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
16353 SDValue Addr = Trmp;
16354 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
16355 Addr, MachinePointerInfo(TrmpAddr),
16358 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16359 DAG.getConstant(2, dl, MVT::i64));
16360 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
16361 MachinePointerInfo(TrmpAddr, 2),
16364 // Load the 'nest' parameter value into R10.
16365 // R10 is specified in X86CallingConv.td
16366 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
16367 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16368 DAG.getConstant(10, dl, MVT::i64));
16369 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
16370 Addr, MachinePointerInfo(TrmpAddr, 10),
16373 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16374 DAG.getConstant(12, dl, MVT::i64));
16375 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
16376 MachinePointerInfo(TrmpAddr, 12),
16379 // Jump to the nested function.
16380 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
16381 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16382 DAG.getConstant(20, dl, MVT::i64));
16383 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
16384 Addr, MachinePointerInfo(TrmpAddr, 20),
16387 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
16388 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16389 DAG.getConstant(22, dl, MVT::i64));
16390 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
16391 Addr, MachinePointerInfo(TrmpAddr, 22),
16394 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16396 const Function *Func =
16397 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
16398 CallingConv::ID CC = Func->getCallingConv();
16403 llvm_unreachable("Unsupported calling convention");
16404 case CallingConv::C:
16405 case CallingConv::X86_StdCall: {
16406 // Pass 'nest' parameter in ECX.
16407 // Must be kept in sync with X86CallingConv.td
16408 NestReg = X86::ECX;
16410 // Check that ECX wasn't needed by an 'inreg' parameter.
16411 FunctionType *FTy = Func->getFunctionType();
16412 const AttributeSet &Attrs = Func->getAttributes();
16414 if (!Attrs.isEmpty() && !Func->isVarArg()) {
16415 unsigned InRegCount = 0;
16418 for (FunctionType::param_iterator I = FTy->param_begin(),
16419 E = FTy->param_end(); I != E; ++I, ++Idx)
16420 if (Attrs.hasAttribute(Idx, Attribute::InReg))
16421 // FIXME: should only count parameters that are lowered to integers.
16422 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
16424 if (InRegCount > 2) {
16425 report_fatal_error("Nest register in use - reduce number of inreg"
16431 case CallingConv::X86_FastCall:
16432 case CallingConv::X86_ThisCall:
16433 case CallingConv::Fast:
16434 // Pass 'nest' parameter in EAX.
16435 // Must be kept in sync with X86CallingConv.td
16436 NestReg = X86::EAX;
16440 SDValue OutChains[4];
16441 SDValue Addr, Disp;
16443 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16444 DAG.getConstant(10, dl, MVT::i32));
16445 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
16447 // This is storing the opcode for MOV32ri.
16448 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
16449 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
16450 OutChains[0] = DAG.getStore(Root, dl,
16451 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
16452 Trmp, MachinePointerInfo(TrmpAddr),
16455 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16456 DAG.getConstant(1, dl, MVT::i32));
16457 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
16458 MachinePointerInfo(TrmpAddr, 1),
16461 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
16462 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16463 DAG.getConstant(5, dl, MVT::i32));
16464 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
16465 Addr, MachinePointerInfo(TrmpAddr, 5),
16468 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16469 DAG.getConstant(6, dl, MVT::i32));
16470 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
16471 MachinePointerInfo(TrmpAddr, 6),
16474 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16478 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
16479 SelectionDAG &DAG) const {
16481 The rounding mode is in bits 11:10 of FPSR, and has the following
16483 00 Round to nearest
16488 FLT_ROUNDS, on the other hand, expects the following:
16495 To perform the conversion, we do:
16496 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
16499 MachineFunction &MF = DAG.getMachineFunction();
16500 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
16501 unsigned StackAlignment = TFI.getStackAlignment();
16502 MVT VT = Op.getSimpleValueType();
16505 // Save FP Control Word to stack slot
16506 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
16507 SDValue StackSlot =
16508 DAG.getFrameIndex(SSFI, getPointerTy(DAG.getDataLayout()));
16510 MachineMemOperand *MMO =
16511 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
16512 MachineMemOperand::MOStore, 2, 2);
16514 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
16515 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
16516 DAG.getVTList(MVT::Other),
16517 Ops, MVT::i16, MMO);
16519 // Load FP Control Word from stack slot
16520 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
16521 MachinePointerInfo(), false, false, false, 0);
16523 // Transform as necessary
16525 DAG.getNode(ISD::SRL, DL, MVT::i16,
16526 DAG.getNode(ISD::AND, DL, MVT::i16,
16527 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
16528 DAG.getConstant(11, DL, MVT::i8));
16530 DAG.getNode(ISD::SRL, DL, MVT::i16,
16531 DAG.getNode(ISD::AND, DL, MVT::i16,
16532 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
16533 DAG.getConstant(9, DL, MVT::i8));
16536 DAG.getNode(ISD::AND, DL, MVT::i16,
16537 DAG.getNode(ISD::ADD, DL, MVT::i16,
16538 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
16539 DAG.getConstant(1, DL, MVT::i16)),
16540 DAG.getConstant(3, DL, MVT::i16));
16542 return DAG.getNode((VT.getSizeInBits() < 16 ?
16543 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
16546 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
16547 MVT VT = Op.getSimpleValueType();
16549 unsigned NumBits = VT.getSizeInBits();
16552 Op = Op.getOperand(0);
16553 if (VT == MVT::i8) {
16554 // Zero extend to i32 since there is not an i8 bsr.
16556 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16559 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
16560 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16561 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16563 // If src is zero (i.e. bsr sets ZF), returns NumBits.
16566 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
16567 DAG.getConstant(X86::COND_E, dl, MVT::i8),
16570 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
16572 // Finally xor with NumBits-1.
16573 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
16574 DAG.getConstant(NumBits - 1, dl, OpVT));
16577 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16581 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
16582 MVT VT = Op.getSimpleValueType();
16584 unsigned NumBits = VT.getSizeInBits();
16587 Op = Op.getOperand(0);
16588 if (VT == MVT::i8) {
16589 // Zero extend to i32 since there is not an i8 bsr.
16591 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16594 // Issue a bsr (scan bits in reverse).
16595 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16596 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16598 // And xor with NumBits-1.
16599 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
16600 DAG.getConstant(NumBits - 1, dl, OpVT));
16603 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16607 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
16608 MVT VT = Op.getSimpleValueType();
16609 unsigned NumBits = VT.getSizeInBits();
16611 Op = Op.getOperand(0);
16613 // Issue a bsf (scan bits forward) which also sets EFLAGS.
16614 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16615 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
16617 // If src is zero (i.e. bsf sets ZF), returns NumBits.
16620 DAG.getConstant(NumBits, dl, VT),
16621 DAG.getConstant(X86::COND_E, dl, MVT::i8),
16624 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
16627 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
16628 // ones, and then concatenate the result back.
16629 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
16630 MVT VT = Op.getSimpleValueType();
16632 assert(VT.is256BitVector() && VT.isInteger() &&
16633 "Unsupported value type for operation");
16635 unsigned NumElems = VT.getVectorNumElements();
16638 // Extract the LHS vectors
16639 SDValue LHS = Op.getOperand(0);
16640 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16641 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16643 // Extract the RHS vectors
16644 SDValue RHS = Op.getOperand(1);
16645 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
16646 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
16648 MVT EltVT = VT.getVectorElementType();
16649 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16651 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16652 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
16653 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
16656 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
16657 if (Op.getValueType() == MVT::i1)
16658 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
16659 Op.getOperand(0), Op.getOperand(1));
16660 assert(Op.getSimpleValueType().is256BitVector() &&
16661 Op.getSimpleValueType().isInteger() &&
16662 "Only handle AVX 256-bit vector integer operation");
16663 return Lower256IntArith(Op, DAG);
16666 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
16667 if (Op.getValueType() == MVT::i1)
16668 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
16669 Op.getOperand(0), Op.getOperand(1));
16670 assert(Op.getSimpleValueType().is256BitVector() &&
16671 Op.getSimpleValueType().isInteger() &&
16672 "Only handle AVX 256-bit vector integer operation");
16673 return Lower256IntArith(Op, DAG);
16676 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
16677 SelectionDAG &DAG) {
16679 MVT VT = Op.getSimpleValueType();
16682 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
16684 // Decompose 256-bit ops into smaller 128-bit ops.
16685 if (VT.is256BitVector() && !Subtarget->hasInt256())
16686 return Lower256IntArith(Op, DAG);
16688 SDValue A = Op.getOperand(0);
16689 SDValue B = Op.getOperand(1);
16691 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
16692 // pairs, multiply and truncate.
16693 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
16694 if (Subtarget->hasInt256()) {
16695 if (VT == MVT::v32i8) {
16696 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
16697 SDValue Lo = DAG.getIntPtrConstant(0, dl);
16698 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
16699 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
16700 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
16701 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
16702 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
16703 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16704 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
16705 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
16708 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
16709 return DAG.getNode(
16710 ISD::TRUNCATE, dl, VT,
16711 DAG.getNode(ISD::MUL, dl, ExVT,
16712 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
16713 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
16716 assert(VT == MVT::v16i8 &&
16717 "Pre-AVX2 support only supports v16i8 multiplication");
16718 MVT ExVT = MVT::v8i16;
16720 // Extract the lo parts and sign extend to i16
16722 if (Subtarget->hasSSE41()) {
16723 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
16724 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
16726 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
16727 -1, 4, -1, 5, -1, 6, -1, 7};
16728 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16729 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16730 ALo = DAG.getBitcast(ExVT, ALo);
16731 BLo = DAG.getBitcast(ExVT, BLo);
16732 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
16733 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
16736 // Extract the hi parts and sign extend to i16
16738 if (Subtarget->hasSSE41()) {
16739 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
16740 -1, -1, -1, -1, -1, -1, -1, -1};
16741 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16742 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16743 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
16744 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
16746 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
16747 -1, 12, -1, 13, -1, 14, -1, 15};
16748 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16749 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16750 AHi = DAG.getBitcast(ExVT, AHi);
16751 BHi = DAG.getBitcast(ExVT, BHi);
16752 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
16753 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
16756 // Multiply, mask the lower 8bits of the lo/hi results and pack
16757 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
16758 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
16759 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
16760 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
16761 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
16764 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
16765 if (VT == MVT::v4i32) {
16766 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
16767 "Should not custom lower when pmuldq is available!");
16769 // Extract the odd parts.
16770 static const int UnpackMask[] = { 1, -1, 3, -1 };
16771 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
16772 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
16774 // Multiply the even parts.
16775 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
16776 // Now multiply odd parts.
16777 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
16779 Evens = DAG.getBitcast(VT, Evens);
16780 Odds = DAG.getBitcast(VT, Odds);
16782 // Merge the two vectors back together with a shuffle. This expands into 2
16784 static const int ShufMask[] = { 0, 4, 2, 6 };
16785 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
16788 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
16789 "Only know how to lower V2I64/V4I64/V8I64 multiply");
16791 // Ahi = psrlqi(a, 32);
16792 // Bhi = psrlqi(b, 32);
16794 // AloBlo = pmuludq(a, b);
16795 // AloBhi = pmuludq(a, Bhi);
16796 // AhiBlo = pmuludq(Ahi, b);
16798 // AloBhi = psllqi(AloBhi, 32);
16799 // AhiBlo = psllqi(AhiBlo, 32);
16800 // return AloBlo + AloBhi + AhiBlo;
16802 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
16803 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
16805 SDValue AhiBlo = Ahi;
16806 SDValue AloBhi = Bhi;
16807 // Bit cast to 32-bit vectors for MULUDQ
16808 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
16809 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
16810 A = DAG.getBitcast(MulVT, A);
16811 B = DAG.getBitcast(MulVT, B);
16812 Ahi = DAG.getBitcast(MulVT, Ahi);
16813 Bhi = DAG.getBitcast(MulVT, Bhi);
16815 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
16816 // After shifting right const values the result may be all-zero.
16817 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
16818 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
16819 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
16821 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
16822 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
16823 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
16826 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
16827 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
16830 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
16831 assert(Subtarget->isTargetWin64() && "Unexpected target");
16832 EVT VT = Op.getValueType();
16833 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
16834 "Unexpected return type for lowering");
16838 switch (Op->getOpcode()) {
16839 default: llvm_unreachable("Unexpected request for libcall!");
16840 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
16841 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
16842 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
16843 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
16844 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
16845 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
16849 SDValue InChain = DAG.getEntryNode();
16851 TargetLowering::ArgListTy Args;
16852 TargetLowering::ArgListEntry Entry;
16853 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
16854 EVT ArgVT = Op->getOperand(i).getValueType();
16855 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
16856 "Unexpected argument type for lowering");
16857 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
16858 Entry.Node = StackPtr;
16859 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
16861 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16862 Entry.Ty = PointerType::get(ArgTy,0);
16863 Entry.isSExt = false;
16864 Entry.isZExt = false;
16865 Args.push_back(Entry);
16868 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
16869 getPointerTy(DAG.getDataLayout()));
16871 TargetLowering::CallLoweringInfo CLI(DAG);
16872 CLI.setDebugLoc(dl).setChain(InChain)
16873 .setCallee(getLibcallCallingConv(LC),
16874 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
16875 Callee, std::move(Args), 0)
16876 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
16878 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
16879 return DAG.getBitcast(VT, CallInfo.first);
16882 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
16883 SelectionDAG &DAG) {
16884 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
16885 EVT VT = Op0.getValueType();
16888 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
16889 (VT == MVT::v8i32 && Subtarget->hasInt256()));
16891 // PMULxD operations multiply each even value (starting at 0) of LHS with
16892 // the related value of RHS and produce a widen result.
16893 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16894 // => <2 x i64> <ae|cg>
16896 // In other word, to have all the results, we need to perform two PMULxD:
16897 // 1. one with the even values.
16898 // 2. one with the odd values.
16899 // To achieve #2, with need to place the odd values at an even position.
16901 // Place the odd value at an even position (basically, shift all values 1
16902 // step to the left):
16903 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
16904 // <a|b|c|d> => <b|undef|d|undef>
16905 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
16906 // <e|f|g|h> => <f|undef|h|undef>
16907 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
16909 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
16911 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
16912 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
16914 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
16915 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16916 // => <2 x i64> <ae|cg>
16917 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
16918 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
16919 // => <2 x i64> <bf|dh>
16920 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
16922 // Shuffle it back into the right order.
16923 SDValue Highs, Lows;
16924 if (VT == MVT::v8i32) {
16925 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
16926 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16927 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
16928 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16930 const int HighMask[] = {1, 5, 3, 7};
16931 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16932 const int LowMask[] = {0, 4, 2, 6};
16933 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16936 // If we have a signed multiply but no PMULDQ fix up the high parts of a
16937 // unsigned multiply.
16938 if (IsSigned && !Subtarget->hasSSE41()) {
16939 SDValue ShAmt = DAG.getConstant(
16941 DAG.getTargetLoweringInfo().getShiftAmountTy(VT, DAG.getDataLayout()));
16942 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
16943 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
16944 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
16945 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
16947 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
16948 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
16951 // The first result of MUL_LOHI is actually the low value, followed by the
16953 SDValue Ops[] = {Lows, Highs};
16954 return DAG.getMergeValues(Ops, dl);
16957 // Return true if the requred (according to Opcode) shift-imm form is natively
16958 // supported by the Subtarget
16959 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
16961 if (VT.getScalarSizeInBits() < 16)
16964 if (VT.is512BitVector() &&
16965 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
16968 bool LShift = VT.is128BitVector() ||
16969 (VT.is256BitVector() && Subtarget->hasInt256());
16971 bool AShift = LShift && (Subtarget->hasVLX() ||
16972 (VT != MVT::v2i64 && VT != MVT::v4i64));
16973 return (Opcode == ISD::SRA) ? AShift : LShift;
16976 // The shift amount is a variable, but it is the same for all vector lanes.
16977 // These instrcutions are defined together with shift-immediate.
16979 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
16981 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
16984 // Return true if the requred (according to Opcode) variable-shift form is
16985 // natively supported by the Subtarget
16986 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
16989 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
16992 // vXi16 supported only on AVX-512, BWI
16993 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
16996 if (VT.is512BitVector() || Subtarget->hasVLX())
16999 bool LShift = VT.is128BitVector() || VT.is256BitVector();
17000 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
17001 return (Opcode == ISD::SRA) ? AShift : LShift;
17004 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
17005 const X86Subtarget *Subtarget) {
17006 MVT VT = Op.getSimpleValueType();
17008 SDValue R = Op.getOperand(0);
17009 SDValue Amt = Op.getOperand(1);
17011 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
17012 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
17014 auto ArithmeticShiftRight64 = [&](uint64_t ShiftAmt) {
17015 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
17016 MVT ExVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2);
17017 SDValue Ex = DAG.getBitcast(ExVT, R);
17019 if (ShiftAmt >= 32) {
17020 // Splat sign to upper i32 dst, and SRA upper i32 src to lower i32.
17022 getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex, 31, DAG);
17023 SDValue Lower = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
17024 ShiftAmt - 32, DAG);
17025 if (VT == MVT::v2i64)
17026 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {5, 1, 7, 3});
17027 if (VT == MVT::v4i64)
17028 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
17029 {9, 1, 11, 3, 13, 5, 15, 7});
17031 // SRA upper i32, SHL whole i64 and select lower i32.
17032 SDValue Upper = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
17035 getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);
17036 Lower = DAG.getBitcast(ExVT, Lower);
17037 if (VT == MVT::v2i64)
17038 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {4, 1, 6, 3});
17039 if (VT == MVT::v4i64)
17040 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
17041 {8, 1, 10, 3, 12, 5, 14, 7});
17043 return DAG.getBitcast(VT, Ex);
17046 // Optimize shl/srl/sra with constant shift amount.
17047 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
17048 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
17049 uint64_t ShiftAmt = ShiftConst->getZExtValue();
17051 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
17052 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
17054 // i64 SRA needs to be performed as partial shifts.
17055 if ((VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
17056 Op.getOpcode() == ISD::SRA)
17057 return ArithmeticShiftRight64(ShiftAmt);
17059 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
17060 unsigned NumElts = VT.getVectorNumElements();
17061 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
17063 if (Op.getOpcode() == ISD::SHL) {
17064 // Simple i8 add case
17066 return DAG.getNode(ISD::ADD, dl, VT, R, R);
17068 // Make a large shift.
17069 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
17071 SHL = DAG.getBitcast(VT, SHL);
17072 // Zero out the rightmost bits.
17073 SmallVector<SDValue, 32> V(
17074 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
17075 return DAG.getNode(ISD::AND, dl, VT, SHL,
17076 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17078 if (Op.getOpcode() == ISD::SRL) {
17079 // Make a large shift.
17080 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
17082 SRL = DAG.getBitcast(VT, SRL);
17083 // Zero out the leftmost bits.
17084 SmallVector<SDValue, 32> V(
17085 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
17086 return DAG.getNode(ISD::AND, dl, VT, SRL,
17087 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17089 if (Op.getOpcode() == ISD::SRA) {
17090 if (ShiftAmt == 7) {
17091 // R s>> 7 === R s< 0
17092 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17093 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17096 // R s>> a === ((R u>> a) ^ m) - m
17097 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17098 SmallVector<SDValue, 32> V(NumElts,
17099 DAG.getConstant(128 >> ShiftAmt, dl,
17101 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17102 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17103 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17106 llvm_unreachable("Unknown shift opcode.");
17111 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17112 if (!Subtarget->is64Bit() &&
17113 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
17114 Amt.getOpcode() == ISD::BITCAST &&
17115 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17116 Amt = Amt.getOperand(0);
17117 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17118 VT.getVectorNumElements();
17119 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
17120 uint64_t ShiftAmt = 0;
17121 for (unsigned i = 0; i != Ratio; ++i) {
17122 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
17126 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
17128 // Check remaining shift amounts.
17129 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17130 uint64_t ShAmt = 0;
17131 for (unsigned j = 0; j != Ratio; ++j) {
17132 ConstantSDNode *C =
17133 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
17137 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
17139 if (ShAmt != ShiftAmt)
17143 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
17144 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
17146 if (Op.getOpcode() == ISD::SRA)
17147 return ArithmeticShiftRight64(ShiftAmt);
17153 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
17154 const X86Subtarget* Subtarget) {
17155 MVT VT = Op.getSimpleValueType();
17157 SDValue R = Op.getOperand(0);
17158 SDValue Amt = Op.getOperand(1);
17160 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
17161 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
17163 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
17164 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
17166 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
17168 EVT EltVT = VT.getVectorElementType();
17170 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
17171 // Check if this build_vector node is doing a splat.
17172 // If so, then set BaseShAmt equal to the splat value.
17173 BaseShAmt = BV->getSplatValue();
17174 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
17175 BaseShAmt = SDValue();
17177 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
17178 Amt = Amt.getOperand(0);
17180 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
17181 if (SVN && SVN->isSplat()) {
17182 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
17183 SDValue InVec = Amt.getOperand(0);
17184 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
17185 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
17186 "Unexpected shuffle index found!");
17187 BaseShAmt = InVec.getOperand(SplatIdx);
17188 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
17189 if (ConstantSDNode *C =
17190 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
17191 if (C->getZExtValue() == SplatIdx)
17192 BaseShAmt = InVec.getOperand(1);
17197 // Avoid introducing an extract element from a shuffle.
17198 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
17199 DAG.getIntPtrConstant(SplatIdx, dl));
17203 if (BaseShAmt.getNode()) {
17204 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
17205 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
17206 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
17207 else if (EltVT.bitsLT(MVT::i32))
17208 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
17210 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
17214 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17215 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
17216 Amt.getOpcode() == ISD::BITCAST &&
17217 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17218 Amt = Amt.getOperand(0);
17219 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17220 VT.getVectorNumElements();
17221 std::vector<SDValue> Vals(Ratio);
17222 for (unsigned i = 0; i != Ratio; ++i)
17223 Vals[i] = Amt.getOperand(i);
17224 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17225 for (unsigned j = 0; j != Ratio; ++j)
17226 if (Vals[j] != Amt.getOperand(i + j))
17230 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
17231 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
17236 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
17237 SelectionDAG &DAG) {
17238 MVT VT = Op.getSimpleValueType();
17240 SDValue R = Op.getOperand(0);
17241 SDValue Amt = Op.getOperand(1);
17243 assert(VT.isVector() && "Custom lowering only for vector shifts!");
17244 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
17246 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
17249 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
17252 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
17255 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
17256 // shifts per-lane and then shuffle the partial results back together.
17257 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
17258 // Splat the shift amounts so the scalar shifts above will catch it.
17259 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
17260 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
17261 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
17262 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
17263 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
17266 // If possible, lower this packed shift into a vector multiply instead of
17267 // expanding it into a sequence of scalar shifts.
17268 // Do this only if the vector shift count is a constant build_vector.
17269 if (Op.getOpcode() == ISD::SHL &&
17270 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
17271 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
17272 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17273 SmallVector<SDValue, 8> Elts;
17274 EVT SVT = VT.getScalarType();
17275 unsigned SVTBits = SVT.getSizeInBits();
17276 const APInt &One = APInt(SVTBits, 1);
17277 unsigned NumElems = VT.getVectorNumElements();
17279 for (unsigned i=0; i !=NumElems; ++i) {
17280 SDValue Op = Amt->getOperand(i);
17281 if (Op->getOpcode() == ISD::UNDEF) {
17282 Elts.push_back(Op);
17286 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
17287 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
17288 uint64_t ShAmt = C.getZExtValue();
17289 if (ShAmt >= SVTBits) {
17290 Elts.push_back(DAG.getUNDEF(SVT));
17293 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
17295 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
17296 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
17299 // Lower SHL with variable shift amount.
17300 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
17301 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
17303 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
17304 DAG.getConstant(0x3f800000U, dl, VT));
17305 Op = DAG.getBitcast(MVT::v4f32, Op);
17306 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
17307 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
17310 // If possible, lower this shift as a sequence of two shifts by
17311 // constant plus a MOVSS/MOVSD instead of scalarizing it.
17313 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
17315 // Could be rewritten as:
17316 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
17318 // The advantage is that the two shifts from the example would be
17319 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
17320 // the vector shift into four scalar shifts plus four pairs of vector
17322 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
17323 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17324 unsigned TargetOpcode = X86ISD::MOVSS;
17325 bool CanBeSimplified;
17326 // The splat value for the first packed shift (the 'X' from the example).
17327 SDValue Amt1 = Amt->getOperand(0);
17328 // The splat value for the second packed shift (the 'Y' from the example).
17329 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
17330 Amt->getOperand(2);
17332 // See if it is possible to replace this node with a sequence of
17333 // two shifts followed by a MOVSS/MOVSD
17334 if (VT == MVT::v4i32) {
17335 // Check if it is legal to use a MOVSS.
17336 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
17337 Amt2 == Amt->getOperand(3);
17338 if (!CanBeSimplified) {
17339 // Otherwise, check if we can still simplify this node using a MOVSD.
17340 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
17341 Amt->getOperand(2) == Amt->getOperand(3);
17342 TargetOpcode = X86ISD::MOVSD;
17343 Amt2 = Amt->getOperand(2);
17346 // Do similar checks for the case where the machine value type
17348 CanBeSimplified = Amt1 == Amt->getOperand(1);
17349 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
17350 CanBeSimplified = Amt2 == Amt->getOperand(i);
17352 if (!CanBeSimplified) {
17353 TargetOpcode = X86ISD::MOVSD;
17354 CanBeSimplified = true;
17355 Amt2 = Amt->getOperand(4);
17356 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
17357 CanBeSimplified = Amt1 == Amt->getOperand(i);
17358 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
17359 CanBeSimplified = Amt2 == Amt->getOperand(j);
17363 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
17364 isa<ConstantSDNode>(Amt2)) {
17365 // Replace this node with two shifts followed by a MOVSS/MOVSD.
17366 EVT CastVT = MVT::v4i32;
17368 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
17369 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
17371 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
17372 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
17373 if (TargetOpcode == X86ISD::MOVSD)
17374 CastVT = MVT::v2i64;
17375 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
17376 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
17377 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
17379 return DAG.getBitcast(VT, Result);
17383 if (VT == MVT::v16i8 || (VT == MVT::v32i8 && Subtarget->hasInt256())) {
17384 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
17385 unsigned ShiftOpcode = Op->getOpcode();
17387 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
17388 // On SSE41 targets we make use of the fact that VSELECT lowers
17389 // to PBLENDVB which selects bytes based just on the sign bit.
17390 if (Subtarget->hasSSE41()) {
17391 V0 = DAG.getBitcast(VT, V0);
17392 V1 = DAG.getBitcast(VT, V1);
17393 Sel = DAG.getBitcast(VT, Sel);
17394 return DAG.getBitcast(SelVT,
17395 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
17397 // On pre-SSE41 targets we test for the sign bit by comparing to
17398 // zero - a negative value will set all bits of the lanes to true
17399 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
17400 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
17401 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
17402 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
17405 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
17406 // We can safely do this using i16 shifts as we're only interested in
17407 // the 3 lower bits of each byte.
17408 Amt = DAG.getBitcast(ExtVT, Amt);
17409 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
17410 Amt = DAG.getBitcast(VT, Amt);
17412 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
17413 // r = VSELECT(r, shift(r, 4), a);
17415 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
17416 R = SignBitSelect(VT, Amt, M, R);
17419 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17421 // r = VSELECT(r, shift(r, 2), a);
17422 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
17423 R = SignBitSelect(VT, Amt, M, R);
17426 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17428 // return VSELECT(r, shift(r, 1), a);
17429 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
17430 R = SignBitSelect(VT, Amt, M, R);
17434 if (Op->getOpcode() == ISD::SRA) {
17435 // For SRA we need to unpack each byte to the higher byte of a i16 vector
17436 // so we can correctly sign extend. We don't care what happens to the
17438 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
17439 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
17440 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
17441 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
17442 ALo = DAG.getBitcast(ExtVT, ALo);
17443 AHi = DAG.getBitcast(ExtVT, AHi);
17444 RLo = DAG.getBitcast(ExtVT, RLo);
17445 RHi = DAG.getBitcast(ExtVT, RHi);
17447 // r = VSELECT(r, shift(r, 4), a);
17448 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
17449 DAG.getConstant(4, dl, ExtVT));
17450 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
17451 DAG.getConstant(4, dl, ExtVT));
17452 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
17453 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
17456 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
17457 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
17459 // r = VSELECT(r, shift(r, 2), a);
17460 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
17461 DAG.getConstant(2, dl, ExtVT));
17462 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
17463 DAG.getConstant(2, dl, ExtVT));
17464 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
17465 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
17468 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
17469 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
17471 // r = VSELECT(r, shift(r, 1), a);
17472 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
17473 DAG.getConstant(1, dl, ExtVT));
17474 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
17475 DAG.getConstant(1, dl, ExtVT));
17476 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
17477 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
17479 // Logical shift the result back to the lower byte, leaving a zero upper
17481 // meaning that we can safely pack with PACKUSWB.
17483 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
17485 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
17486 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
17490 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
17491 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
17492 // solution better.
17493 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
17494 MVT ExtVT = MVT::v8i32;
17496 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
17497 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
17498 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
17499 return DAG.getNode(ISD::TRUNCATE, dl, VT,
17500 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
17503 if (Subtarget->hasInt256() && VT == MVT::v16i16) {
17504 MVT ExtVT = MVT::v8i32;
17505 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
17506 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
17507 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
17508 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
17509 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
17510 ALo = DAG.getBitcast(ExtVT, ALo);
17511 AHi = DAG.getBitcast(ExtVT, AHi);
17512 RLo = DAG.getBitcast(ExtVT, RLo);
17513 RHi = DAG.getBitcast(ExtVT, RHi);
17514 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
17515 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
17516 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
17517 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
17518 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
17521 if (VT == MVT::v8i16) {
17522 unsigned ShiftOpcode = Op->getOpcode();
17524 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
17525 // On SSE41 targets we make use of the fact that VSELECT lowers
17526 // to PBLENDVB which selects bytes based just on the sign bit.
17527 if (Subtarget->hasSSE41()) {
17528 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
17529 V0 = DAG.getBitcast(ExtVT, V0);
17530 V1 = DAG.getBitcast(ExtVT, V1);
17531 Sel = DAG.getBitcast(ExtVT, Sel);
17532 return DAG.getBitcast(
17533 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
17535 // On pre-SSE41 targets we splat the sign bit - a negative value will
17536 // set all bits of the lanes to true and VSELECT uses that in
17537 // its OR(AND(V0,C),AND(V1,~C)) lowering.
17539 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
17540 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
17543 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
17544 if (Subtarget->hasSSE41()) {
17545 // On SSE41 targets we need to replicate the shift mask in both
17546 // bytes for PBLENDVB.
17549 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
17550 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
17552 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
17555 // r = VSELECT(r, shift(r, 8), a);
17556 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
17557 R = SignBitSelect(Amt, M, R);
17560 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17562 // r = VSELECT(r, shift(r, 4), a);
17563 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
17564 R = SignBitSelect(Amt, M, R);
17567 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17569 // r = VSELECT(r, shift(r, 2), a);
17570 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
17571 R = SignBitSelect(Amt, M, R);
17574 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17576 // return VSELECT(r, shift(r, 1), a);
17577 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
17578 R = SignBitSelect(Amt, M, R);
17582 // Decompose 256-bit shifts into smaller 128-bit shifts.
17583 if (VT.is256BitVector()) {
17584 unsigned NumElems = VT.getVectorNumElements();
17585 MVT EltVT = VT.getVectorElementType();
17586 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17588 // Extract the two vectors
17589 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
17590 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
17592 // Recreate the shift amount vectors
17593 SDValue Amt1, Amt2;
17594 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17595 // Constant shift amount
17596 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
17597 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
17598 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
17600 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
17601 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
17603 // Variable shift amount
17604 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
17605 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
17608 // Issue new vector shifts for the smaller types
17609 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
17610 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
17612 // Concatenate the result back
17613 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
17619 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
17620 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
17621 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
17622 // looks for this combo and may remove the "setcc" instruction if the "setcc"
17623 // has only one use.
17624 SDNode *N = Op.getNode();
17625 SDValue LHS = N->getOperand(0);
17626 SDValue RHS = N->getOperand(1);
17627 unsigned BaseOp = 0;
17630 switch (Op.getOpcode()) {
17631 default: llvm_unreachable("Unknown ovf instruction!");
17633 // A subtract of one will be selected as a INC. Note that INC doesn't
17634 // set CF, so we can't do this for UADDO.
17635 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17637 BaseOp = X86ISD::INC;
17638 Cond = X86::COND_O;
17641 BaseOp = X86ISD::ADD;
17642 Cond = X86::COND_O;
17645 BaseOp = X86ISD::ADD;
17646 Cond = X86::COND_B;
17649 // A subtract of one will be selected as a DEC. Note that DEC doesn't
17650 // set CF, so we can't do this for USUBO.
17651 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17653 BaseOp = X86ISD::DEC;
17654 Cond = X86::COND_O;
17657 BaseOp = X86ISD::SUB;
17658 Cond = X86::COND_O;
17661 BaseOp = X86ISD::SUB;
17662 Cond = X86::COND_B;
17665 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
17666 Cond = X86::COND_O;
17668 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
17669 if (N->getValueType(0) == MVT::i8) {
17670 BaseOp = X86ISD::UMUL8;
17671 Cond = X86::COND_O;
17674 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
17676 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
17679 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17680 DAG.getConstant(X86::COND_O, DL, MVT::i32),
17681 SDValue(Sum.getNode(), 2));
17683 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17687 // Also sets EFLAGS.
17688 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
17689 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
17692 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
17693 DAG.getConstant(Cond, DL, MVT::i32),
17694 SDValue(Sum.getNode(), 1));
17696 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17699 /// Returns true if the operand type is exactly twice the native width, and
17700 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
17701 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
17702 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
17703 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
17704 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
17707 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
17708 else if (OpWidth == 128)
17709 return Subtarget->hasCmpxchg16b();
17714 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
17715 return needsCmpXchgNb(SI->getValueOperand()->getType());
17718 // Note: this turns large loads into lock cmpxchg8b/16b.
17719 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
17720 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
17721 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
17722 return needsCmpXchgNb(PTy->getElementType());
17725 TargetLoweringBase::AtomicRMWExpansionKind
17726 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
17727 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
17728 const Type *MemType = AI->getType();
17730 // If the operand is too big, we must see if cmpxchg8/16b is available
17731 // and default to library calls otherwise.
17732 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
17733 return needsCmpXchgNb(MemType) ? AtomicRMWExpansionKind::CmpXChg
17734 : AtomicRMWExpansionKind::None;
17737 AtomicRMWInst::BinOp Op = AI->getOperation();
17740 llvm_unreachable("Unknown atomic operation");
17741 case AtomicRMWInst::Xchg:
17742 case AtomicRMWInst::Add:
17743 case AtomicRMWInst::Sub:
17744 // It's better to use xadd, xsub or xchg for these in all cases.
17745 return AtomicRMWExpansionKind::None;
17746 case AtomicRMWInst::Or:
17747 case AtomicRMWInst::And:
17748 case AtomicRMWInst::Xor:
17749 // If the atomicrmw's result isn't actually used, we can just add a "lock"
17750 // prefix to a normal instruction for these operations.
17751 return !AI->use_empty() ? AtomicRMWExpansionKind::CmpXChg
17752 : AtomicRMWExpansionKind::None;
17753 case AtomicRMWInst::Nand:
17754 case AtomicRMWInst::Max:
17755 case AtomicRMWInst::Min:
17756 case AtomicRMWInst::UMax:
17757 case AtomicRMWInst::UMin:
17758 // These always require a non-trivial set of data operations on x86. We must
17759 // use a cmpxchg loop.
17760 return AtomicRMWExpansionKind::CmpXChg;
17764 static bool hasMFENCE(const X86Subtarget& Subtarget) {
17765 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
17766 // no-sse2). There isn't any reason to disable it if the target processor
17768 return Subtarget.hasSSE2() || Subtarget.is64Bit();
17772 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
17773 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
17774 const Type *MemType = AI->getType();
17775 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
17776 // there is no benefit in turning such RMWs into loads, and it is actually
17777 // harmful as it introduces a mfence.
17778 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
17781 auto Builder = IRBuilder<>(AI);
17782 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
17783 auto SynchScope = AI->getSynchScope();
17784 // We must restrict the ordering to avoid generating loads with Release or
17785 // ReleaseAcquire orderings.
17786 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
17787 auto Ptr = AI->getPointerOperand();
17789 // Before the load we need a fence. Here is an example lifted from
17790 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
17793 // x.store(1, relaxed);
17794 // r1 = y.fetch_add(0, release);
17796 // y.fetch_add(42, acquire);
17797 // r2 = x.load(relaxed);
17798 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
17799 // lowered to just a load without a fence. A mfence flushes the store buffer,
17800 // making the optimization clearly correct.
17801 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
17802 // otherwise, we might be able to be more agressive on relaxed idempotent
17803 // rmw. In practice, they do not look useful, so we don't try to be
17804 // especially clever.
17805 if (SynchScope == SingleThread)
17806 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
17807 // the IR level, so we must wrap it in an intrinsic.
17810 if (!hasMFENCE(*Subtarget))
17811 // FIXME: it might make sense to use a locked operation here but on a
17812 // different cache-line to prevent cache-line bouncing. In practice it
17813 // is probably a small win, and x86 processors without mfence are rare
17814 // enough that we do not bother.
17818 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
17819 Builder.CreateCall(MFence, {});
17821 // Finally we can emit the atomic load.
17822 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
17823 AI->getType()->getPrimitiveSizeInBits());
17824 Loaded->setAtomic(Order, SynchScope);
17825 AI->replaceAllUsesWith(Loaded);
17826 AI->eraseFromParent();
17830 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
17831 SelectionDAG &DAG) {
17833 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
17834 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
17835 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
17836 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
17838 // The only fence that needs an instruction is a sequentially-consistent
17839 // cross-thread fence.
17840 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
17841 if (hasMFENCE(*Subtarget))
17842 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
17844 SDValue Chain = Op.getOperand(0);
17845 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
17847 DAG.getRegister(X86::ESP, MVT::i32), // Base
17848 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
17849 DAG.getRegister(0, MVT::i32), // Index
17850 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
17851 DAG.getRegister(0, MVT::i32), // Segment.
17855 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
17856 return SDValue(Res, 0);
17859 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
17860 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
17863 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
17864 SelectionDAG &DAG) {
17865 MVT T = Op.getSimpleValueType();
17869 switch(T.SimpleTy) {
17870 default: llvm_unreachable("Invalid value type!");
17871 case MVT::i8: Reg = X86::AL; size = 1; break;
17872 case MVT::i16: Reg = X86::AX; size = 2; break;
17873 case MVT::i32: Reg = X86::EAX; size = 4; break;
17875 assert(Subtarget->is64Bit() && "Node not type legal!");
17876 Reg = X86::RAX; size = 8;
17879 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
17880 Op.getOperand(2), SDValue());
17881 SDValue Ops[] = { cpIn.getValue(0),
17884 DAG.getTargetConstant(size, DL, MVT::i8),
17885 cpIn.getValue(1) };
17886 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17887 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
17888 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
17892 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
17893 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
17894 MVT::i32, cpOut.getValue(2));
17895 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
17896 DAG.getConstant(X86::COND_E, DL, MVT::i8),
17899 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
17900 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
17901 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
17905 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
17906 SelectionDAG &DAG) {
17907 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
17908 MVT DstVT = Op.getSimpleValueType();
17910 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
17911 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17912 if (DstVT != MVT::f64)
17913 // This conversion needs to be expanded.
17916 SDValue InVec = Op->getOperand(0);
17918 unsigned NumElts = SrcVT.getVectorNumElements();
17919 EVT SVT = SrcVT.getVectorElementType();
17921 // Widen the vector in input in the case of MVT::v2i32.
17922 // Example: from MVT::v2i32 to MVT::v4i32.
17923 SmallVector<SDValue, 16> Elts;
17924 for (unsigned i = 0, e = NumElts; i != e; ++i)
17925 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
17926 DAG.getIntPtrConstant(i, dl)));
17928 // Explicitly mark the extra elements as Undef.
17929 Elts.append(NumElts, DAG.getUNDEF(SVT));
17931 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17932 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
17933 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
17934 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
17935 DAG.getIntPtrConstant(0, dl));
17938 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
17939 Subtarget->hasMMX() && "Unexpected custom BITCAST");
17940 assert((DstVT == MVT::i64 ||
17941 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
17942 "Unexpected custom BITCAST");
17943 // i64 <=> MMX conversions are Legal.
17944 if (SrcVT==MVT::i64 && DstVT.isVector())
17946 if (DstVT==MVT::i64 && SrcVT.isVector())
17948 // MMX <=> MMX conversions are Legal.
17949 if (SrcVT.isVector() && DstVT.isVector())
17951 // All other conversions need to be expanded.
17955 /// Compute the horizontal sum of bytes in V for the elements of VT.
17957 /// Requires V to be a byte vector and VT to be an integer vector type with
17958 /// wider elements than V's type. The width of the elements of VT determines
17959 /// how many bytes of V are summed horizontally to produce each element of the
17961 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
17962 const X86Subtarget *Subtarget,
17963 SelectionDAG &DAG) {
17965 MVT ByteVecVT = V.getSimpleValueType();
17966 MVT EltVT = VT.getVectorElementType();
17967 int NumElts = VT.getVectorNumElements();
17968 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
17969 "Expected value to have byte element type.");
17970 assert(EltVT != MVT::i8 &&
17971 "Horizontal byte sum only makes sense for wider elements!");
17972 unsigned VecSize = VT.getSizeInBits();
17973 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
17975 // PSADBW instruction horizontally add all bytes and leave the result in i64
17976 // chunks, thus directly computes the pop count for v2i64 and v4i64.
17977 if (EltVT == MVT::i64) {
17978 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
17979 V = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT, V, Zeros);
17980 return DAG.getBitcast(VT, V);
17983 if (EltVT == MVT::i32) {
17984 // We unpack the low half and high half into i32s interleaved with zeros so
17985 // that we can use PSADBW to horizontally sum them. The most useful part of
17986 // this is that it lines up the results of two PSADBW instructions to be
17987 // two v2i64 vectors which concatenated are the 4 population counts. We can
17988 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
17989 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
17990 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
17991 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
17993 // Do the horizontal sums into two v2i64s.
17994 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
17995 Low = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
17996 DAG.getBitcast(ByteVecVT, Low), Zeros);
17997 High = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
17998 DAG.getBitcast(ByteVecVT, High), Zeros);
18000 // Merge them together.
18001 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
18002 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
18003 DAG.getBitcast(ShortVecVT, Low),
18004 DAG.getBitcast(ShortVecVT, High));
18006 return DAG.getBitcast(VT, V);
18009 // The only element type left is i16.
18010 assert(EltVT == MVT::i16 && "Unknown how to handle type");
18012 // To obtain pop count for each i16 element starting from the pop count for
18013 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
18014 // right by 8. It is important to shift as i16s as i8 vector shift isn't
18015 // directly supported.
18016 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
18017 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
18018 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
18019 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
18020 DAG.getBitcast(ByteVecVT, V));
18021 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
18024 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
18025 const X86Subtarget *Subtarget,
18026 SelectionDAG &DAG) {
18027 MVT VT = Op.getSimpleValueType();
18028 MVT EltVT = VT.getVectorElementType();
18029 unsigned VecSize = VT.getSizeInBits();
18031 // Implement a lookup table in register by using an algorithm based on:
18032 // http://wm.ite.pl/articles/sse-popcount.html
18034 // The general idea is that every lower byte nibble in the input vector is an
18035 // index into a in-register pre-computed pop count table. We then split up the
18036 // input vector in two new ones: (1) a vector with only the shifted-right
18037 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
18038 // masked out higher ones) for each byte. PSHUB is used separately with both
18039 // to index the in-register table. Next, both are added and the result is a
18040 // i8 vector where each element contains the pop count for input byte.
18042 // To obtain the pop count for elements != i8, we follow up with the same
18043 // approach and use additional tricks as described below.
18045 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
18046 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
18047 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
18048 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
18050 int NumByteElts = VecSize / 8;
18051 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
18052 SDValue In = DAG.getBitcast(ByteVecVT, Op);
18053 SmallVector<SDValue, 16> LUTVec;
18054 for (int i = 0; i < NumByteElts; ++i)
18055 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
18056 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
18057 SmallVector<SDValue, 16> Mask0F(NumByteElts,
18058 DAG.getConstant(0x0F, DL, MVT::i8));
18059 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
18062 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
18063 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
18064 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
18067 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
18069 // The input vector is used as the shuffle mask that index elements into the
18070 // LUT. After counting low and high nibbles, add the vector to obtain the
18071 // final pop count per i8 element.
18072 SDValue HighPopCnt =
18073 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
18074 SDValue LowPopCnt =
18075 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
18076 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
18078 if (EltVT == MVT::i8)
18081 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
18084 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
18085 const X86Subtarget *Subtarget,
18086 SelectionDAG &DAG) {
18087 MVT VT = Op.getSimpleValueType();
18088 assert(VT.is128BitVector() &&
18089 "Only 128-bit vector bitmath lowering supported.");
18091 int VecSize = VT.getSizeInBits();
18092 MVT EltVT = VT.getVectorElementType();
18093 int Len = EltVT.getSizeInBits();
18095 // This is the vectorized version of the "best" algorithm from
18096 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
18097 // with a minor tweak to use a series of adds + shifts instead of vector
18098 // multiplications. Implemented for all integer vector types. We only use
18099 // this when we don't have SSSE3 which allows a LUT-based lowering that is
18100 // much faster, even faster than using native popcnt instructions.
18102 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
18103 MVT VT = V.getSimpleValueType();
18104 SmallVector<SDValue, 32> Shifters(
18105 VT.getVectorNumElements(),
18106 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
18107 return DAG.getNode(OpCode, DL, VT, V,
18108 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
18110 auto GetMask = [&](SDValue V, APInt Mask) {
18111 MVT VT = V.getSimpleValueType();
18112 SmallVector<SDValue, 32> Masks(
18113 VT.getVectorNumElements(),
18114 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
18115 return DAG.getNode(ISD::AND, DL, VT, V,
18116 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
18119 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
18120 // x86, so set the SRL type to have elements at least i16 wide. This is
18121 // correct because all of our SRLs are followed immediately by a mask anyways
18122 // that handles any bits that sneak into the high bits of the byte elements.
18123 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
18127 // v = v - ((v >> 1) & 0x55555555...)
18129 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
18130 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
18131 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
18133 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
18134 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
18135 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
18136 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
18137 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
18139 // v = (v + (v >> 4)) & 0x0F0F0F0F...
18140 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
18141 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
18142 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
18144 // At this point, V contains the byte-wise population count, and we are
18145 // merely doing a horizontal sum if necessary to get the wider element
18147 if (EltVT == MVT::i8)
18150 return LowerHorizontalByteSum(
18151 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
18155 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
18156 SelectionDAG &DAG) {
18157 MVT VT = Op.getSimpleValueType();
18158 // FIXME: Need to add AVX-512 support here!
18159 assert((VT.is256BitVector() || VT.is128BitVector()) &&
18160 "Unknown CTPOP type to handle");
18161 SDLoc DL(Op.getNode());
18162 SDValue Op0 = Op.getOperand(0);
18164 if (!Subtarget->hasSSSE3()) {
18165 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
18166 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
18167 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
18170 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
18171 unsigned NumElems = VT.getVectorNumElements();
18173 // Extract each 128-bit vector, compute pop count and concat the result.
18174 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
18175 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
18177 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
18178 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
18179 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
18182 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
18185 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
18186 SelectionDAG &DAG) {
18187 assert(Op.getValueType().isVector() &&
18188 "We only do custom lowering for vector population count.");
18189 return LowerVectorCTPOP(Op, Subtarget, DAG);
18192 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
18193 SDNode *Node = Op.getNode();
18195 EVT T = Node->getValueType(0);
18196 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
18197 DAG.getConstant(0, dl, T), Node->getOperand(2));
18198 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
18199 cast<AtomicSDNode>(Node)->getMemoryVT(),
18200 Node->getOperand(0),
18201 Node->getOperand(1), negOp,
18202 cast<AtomicSDNode>(Node)->getMemOperand(),
18203 cast<AtomicSDNode>(Node)->getOrdering(),
18204 cast<AtomicSDNode>(Node)->getSynchScope());
18207 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
18208 SDNode *Node = Op.getNode();
18210 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
18212 // Convert seq_cst store -> xchg
18213 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
18214 // FIXME: On 32-bit, store -> fist or movq would be more efficient
18215 // (The only way to get a 16-byte store is cmpxchg16b)
18216 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
18217 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
18218 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
18219 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
18220 cast<AtomicSDNode>(Node)->getMemoryVT(),
18221 Node->getOperand(0),
18222 Node->getOperand(1), Node->getOperand(2),
18223 cast<AtomicSDNode>(Node)->getMemOperand(),
18224 cast<AtomicSDNode>(Node)->getOrdering(),
18225 cast<AtomicSDNode>(Node)->getSynchScope());
18226 return Swap.getValue(1);
18228 // Other atomic stores have a simple pattern.
18232 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
18233 EVT VT = Op.getNode()->getSimpleValueType(0);
18235 // Let legalize expand this if it isn't a legal type yet.
18236 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18239 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18242 bool ExtraOp = false;
18243 switch (Op.getOpcode()) {
18244 default: llvm_unreachable("Invalid code");
18245 case ISD::ADDC: Opc = X86ISD::ADD; break;
18246 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
18247 case ISD::SUBC: Opc = X86ISD::SUB; break;
18248 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
18252 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18254 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18255 Op.getOperand(1), Op.getOperand(2));
18258 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
18259 SelectionDAG &DAG) {
18260 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
18262 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
18263 // which returns the values as { float, float } (in XMM0) or
18264 // { double, double } (which is returned in XMM0, XMM1).
18266 SDValue Arg = Op.getOperand(0);
18267 EVT ArgVT = Arg.getValueType();
18268 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18270 TargetLowering::ArgListTy Args;
18271 TargetLowering::ArgListEntry Entry;
18275 Entry.isSExt = false;
18276 Entry.isZExt = false;
18277 Args.push_back(Entry);
18279 bool isF64 = ArgVT == MVT::f64;
18280 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
18281 // the small struct {f32, f32} is returned in (eax, edx). For f64,
18282 // the results are returned via SRet in memory.
18283 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
18284 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18286 DAG.getExternalSymbol(LibcallName, TLI.getPointerTy(DAG.getDataLayout()));
18288 Type *RetTy = isF64
18289 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
18290 : (Type*)VectorType::get(ArgTy, 4);
18292 TargetLowering::CallLoweringInfo CLI(DAG);
18293 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
18294 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
18296 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
18299 // Returned in xmm0 and xmm1.
18300 return CallResult.first;
18302 // Returned in bits 0:31 and 32:64 xmm0.
18303 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18304 CallResult.first, DAG.getIntPtrConstant(0, dl));
18305 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18306 CallResult.first, DAG.getIntPtrConstant(1, dl));
18307 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
18308 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
18311 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
18312 SelectionDAG &DAG) {
18313 assert(Subtarget->hasAVX512() &&
18314 "MGATHER/MSCATTER are supported on AVX-512 arch only");
18316 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
18317 EVT VT = N->getValue().getValueType();
18318 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
18321 // X86 scatter kills mask register, so its type should be added to
18322 // the list of return values
18323 if (N->getNumValues() == 1) {
18324 SDValue Index = N->getIndex();
18325 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
18326 !Index.getValueType().is512BitVector())
18327 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
18329 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
18330 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
18331 N->getOperand(3), Index };
18333 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
18334 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
18335 return SDValue(NewScatter.getNode(), 0);
18340 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
18341 SelectionDAG &DAG) {
18342 assert(Subtarget->hasAVX512() &&
18343 "MGATHER/MSCATTER are supported on AVX-512 arch only");
18345 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
18346 EVT VT = Op.getValueType();
18347 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
18350 SDValue Index = N->getIndex();
18351 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
18352 !Index.getValueType().is512BitVector()) {
18353 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
18354 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
18355 N->getOperand(3), Index };
18356 DAG.UpdateNodeOperands(N, Ops);
18361 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
18362 SelectionDAG &DAG) const {
18363 // TODO: Eventually, the lowering of these nodes should be informed by or
18364 // deferred to the GC strategy for the function in which they appear. For
18365 // now, however, they must be lowered to something. Since they are logically
18366 // no-ops in the case of a null GC strategy (or a GC strategy which does not
18367 // require special handling for these nodes), lower them as literal NOOPs for
18369 SmallVector<SDValue, 2> Ops;
18371 Ops.push_back(Op.getOperand(0));
18372 if (Op->getGluedNode())
18373 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
18376 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
18377 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
18382 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
18383 SelectionDAG &DAG) const {
18384 // TODO: Eventually, the lowering of these nodes should be informed by or
18385 // deferred to the GC strategy for the function in which they appear. For
18386 // now, however, they must be lowered to something. Since they are logically
18387 // no-ops in the case of a null GC strategy (or a GC strategy which does not
18388 // require special handling for these nodes), lower them as literal NOOPs for
18390 SmallVector<SDValue, 2> Ops;
18392 Ops.push_back(Op.getOperand(0));
18393 if (Op->getGluedNode())
18394 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
18397 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
18398 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
18403 /// LowerOperation - Provide custom lowering hooks for some operations.
18405 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
18406 switch (Op.getOpcode()) {
18407 default: llvm_unreachable("Should not custom lower this!");
18408 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
18409 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
18410 return LowerCMP_SWAP(Op, Subtarget, DAG);
18411 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
18412 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
18413 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
18414 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
18415 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
18416 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
18417 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
18418 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
18419 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
18420 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
18421 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
18422 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
18423 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
18424 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
18425 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
18426 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
18427 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
18428 case ISD::SHL_PARTS:
18429 case ISD::SRA_PARTS:
18430 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
18431 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
18432 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
18433 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
18434 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
18435 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
18436 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
18437 case ISD::SIGN_EXTEND_VECTOR_INREG:
18438 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
18439 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
18440 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
18441 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
18442 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
18444 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
18445 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
18446 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
18447 case ISD::SETCC: return LowerSETCC(Op, DAG);
18448 case ISD::SELECT: return LowerSELECT(Op, DAG);
18449 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
18450 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
18451 case ISD::VASTART: return LowerVASTART(Op, DAG);
18452 case ISD::VAARG: return LowerVAARG(Op, DAG);
18453 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
18454 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
18455 case ISD::INTRINSIC_VOID:
18456 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
18457 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
18458 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
18459 case ISD::FRAME_TO_ARGS_OFFSET:
18460 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
18461 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
18462 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
18463 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
18464 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
18465 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
18466 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
18467 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
18468 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
18469 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
18470 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
18471 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
18472 case ISD::UMUL_LOHI:
18473 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
18476 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
18482 case ISD::UMULO: return LowerXALUO(Op, DAG);
18483 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
18484 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
18488 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
18489 case ISD::ADD: return LowerADD(Op, DAG);
18490 case ISD::SUB: return LowerSUB(Op, DAG);
18491 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
18492 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
18493 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
18494 case ISD::GC_TRANSITION_START:
18495 return LowerGC_TRANSITION_START(Op, DAG);
18496 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
18500 /// ReplaceNodeResults - Replace a node with an illegal result type
18501 /// with a new node built out of custom code.
18502 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
18503 SmallVectorImpl<SDValue>&Results,
18504 SelectionDAG &DAG) const {
18506 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18507 switch (N->getOpcode()) {
18509 llvm_unreachable("Do not know how to custom type legalize this operation!");
18510 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
18511 case X86ISD::FMINC:
18513 case X86ISD::FMAXC:
18514 case X86ISD::FMAX: {
18515 EVT VT = N->getValueType(0);
18516 if (VT != MVT::v2f32)
18517 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
18518 SDValue UNDEF = DAG.getUNDEF(VT);
18519 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
18520 N->getOperand(0), UNDEF);
18521 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
18522 N->getOperand(1), UNDEF);
18523 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
18526 case ISD::SIGN_EXTEND_INREG:
18531 // We don't want to expand or promote these.
18538 case ISD::UDIVREM: {
18539 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
18540 Results.push_back(V);
18543 case ISD::FP_TO_SINT:
18544 // FP_TO_INT*_IN_MEM is not legal for f16 inputs. Do not convert
18545 // (FP_TO_SINT (load f16)) to FP_TO_INT*.
18546 if (N->getOperand(0).getValueType() == MVT::f16)
18549 case ISD::FP_TO_UINT: {
18550 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
18552 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
18555 std::pair<SDValue,SDValue> Vals =
18556 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
18557 SDValue FIST = Vals.first, StackSlot = Vals.second;
18558 if (FIST.getNode()) {
18559 EVT VT = N->getValueType(0);
18560 // Return a load from the stack slot.
18561 if (StackSlot.getNode())
18562 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
18563 MachinePointerInfo(),
18564 false, false, false, 0));
18566 Results.push_back(FIST);
18570 case ISD::UINT_TO_FP: {
18571 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18572 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
18573 N->getValueType(0) != MVT::v2f32)
18575 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
18577 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
18579 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
18580 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
18581 DAG.getBitcast(MVT::v2i64, VBias));
18582 Or = DAG.getBitcast(MVT::v2f64, Or);
18583 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
18584 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
18587 case ISD::FP_ROUND: {
18588 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
18590 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
18591 Results.push_back(V);
18594 case ISD::FP_EXTEND: {
18595 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
18596 // No other ValueType for FP_EXTEND should reach this point.
18597 assert(N->getValueType(0) == MVT::v2f32 &&
18598 "Do not know how to legalize this Node");
18601 case ISD::INTRINSIC_W_CHAIN: {
18602 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
18604 default : llvm_unreachable("Do not know how to custom type "
18605 "legalize this intrinsic operation!");
18606 case Intrinsic::x86_rdtsc:
18607 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18609 case Intrinsic::x86_rdtscp:
18610 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
18612 case Intrinsic::x86_rdpmc:
18613 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
18616 case ISD::READCYCLECOUNTER: {
18617 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18620 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
18621 EVT T = N->getValueType(0);
18622 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
18623 bool Regs64bit = T == MVT::i128;
18624 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
18625 SDValue cpInL, cpInH;
18626 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18627 DAG.getConstant(0, dl, HalfT));
18628 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18629 DAG.getConstant(1, dl, HalfT));
18630 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
18631 Regs64bit ? X86::RAX : X86::EAX,
18633 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
18634 Regs64bit ? X86::RDX : X86::EDX,
18635 cpInH, cpInL.getValue(1));
18636 SDValue swapInL, swapInH;
18637 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18638 DAG.getConstant(0, dl, HalfT));
18639 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18640 DAG.getConstant(1, dl, HalfT));
18641 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
18642 Regs64bit ? X86::RBX : X86::EBX,
18643 swapInL, cpInH.getValue(1));
18644 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
18645 Regs64bit ? X86::RCX : X86::ECX,
18646 swapInH, swapInL.getValue(1));
18647 SDValue Ops[] = { swapInH.getValue(0),
18649 swapInH.getValue(1) };
18650 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18651 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
18652 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
18653 X86ISD::LCMPXCHG8_DAG;
18654 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
18655 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
18656 Regs64bit ? X86::RAX : X86::EAX,
18657 HalfT, Result.getValue(1));
18658 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
18659 Regs64bit ? X86::RDX : X86::EDX,
18660 HalfT, cpOutL.getValue(2));
18661 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
18663 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
18664 MVT::i32, cpOutH.getValue(2));
18666 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
18667 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
18668 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
18670 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
18671 Results.push_back(Success);
18672 Results.push_back(EFLAGS.getValue(1));
18675 case ISD::ATOMIC_SWAP:
18676 case ISD::ATOMIC_LOAD_ADD:
18677 case ISD::ATOMIC_LOAD_SUB:
18678 case ISD::ATOMIC_LOAD_AND:
18679 case ISD::ATOMIC_LOAD_OR:
18680 case ISD::ATOMIC_LOAD_XOR:
18681 case ISD::ATOMIC_LOAD_NAND:
18682 case ISD::ATOMIC_LOAD_MIN:
18683 case ISD::ATOMIC_LOAD_MAX:
18684 case ISD::ATOMIC_LOAD_UMIN:
18685 case ISD::ATOMIC_LOAD_UMAX:
18686 case ISD::ATOMIC_LOAD: {
18687 // Delegate to generic TypeLegalization. Situations we can really handle
18688 // should have already been dealt with by AtomicExpandPass.cpp.
18691 case ISD::BITCAST: {
18692 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18693 EVT DstVT = N->getValueType(0);
18694 EVT SrcVT = N->getOperand(0)->getValueType(0);
18696 if (SrcVT != MVT::f64 ||
18697 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
18700 unsigned NumElts = DstVT.getVectorNumElements();
18701 EVT SVT = DstVT.getVectorElementType();
18702 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18703 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
18704 MVT::v2f64, N->getOperand(0));
18705 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
18707 if (ExperimentalVectorWideningLegalization) {
18708 // If we are legalizing vectors by widening, we already have the desired
18709 // legal vector type, just return it.
18710 Results.push_back(ToVecInt);
18714 SmallVector<SDValue, 8> Elts;
18715 for (unsigned i = 0, e = NumElts; i != e; ++i)
18716 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
18717 ToVecInt, DAG.getIntPtrConstant(i, dl)));
18719 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
18724 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
18725 switch ((X86ISD::NodeType)Opcode) {
18726 case X86ISD::FIRST_NUMBER: break;
18727 case X86ISD::BSF: return "X86ISD::BSF";
18728 case X86ISD::BSR: return "X86ISD::BSR";
18729 case X86ISD::SHLD: return "X86ISD::SHLD";
18730 case X86ISD::SHRD: return "X86ISD::SHRD";
18731 case X86ISD::FAND: return "X86ISD::FAND";
18732 case X86ISD::FANDN: return "X86ISD::FANDN";
18733 case X86ISD::FOR: return "X86ISD::FOR";
18734 case X86ISD::FXOR: return "X86ISD::FXOR";
18735 case X86ISD::FILD: return "X86ISD::FILD";
18736 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
18737 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
18738 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
18739 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
18740 case X86ISD::FLD: return "X86ISD::FLD";
18741 case X86ISD::FST: return "X86ISD::FST";
18742 case X86ISD::CALL: return "X86ISD::CALL";
18743 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
18744 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
18745 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
18746 case X86ISD::BT: return "X86ISD::BT";
18747 case X86ISD::CMP: return "X86ISD::CMP";
18748 case X86ISD::COMI: return "X86ISD::COMI";
18749 case X86ISD::UCOMI: return "X86ISD::UCOMI";
18750 case X86ISD::CMPM: return "X86ISD::CMPM";
18751 case X86ISD::CMPMU: return "X86ISD::CMPMU";
18752 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
18753 case X86ISD::SETCC: return "X86ISD::SETCC";
18754 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
18755 case X86ISD::FSETCC: return "X86ISD::FSETCC";
18756 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
18757 case X86ISD::CMOV: return "X86ISD::CMOV";
18758 case X86ISD::BRCOND: return "X86ISD::BRCOND";
18759 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
18760 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
18761 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
18762 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
18763 case X86ISD::Wrapper: return "X86ISD::Wrapper";
18764 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
18765 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
18766 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
18767 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
18768 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
18769 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
18770 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
18771 case X86ISD::PINSRB: return "X86ISD::PINSRB";
18772 case X86ISD::PINSRW: return "X86ISD::PINSRW";
18773 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
18774 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
18775 case X86ISD::ANDNP: return "X86ISD::ANDNP";
18776 case X86ISD::PSIGN: return "X86ISD::PSIGN";
18777 case X86ISD::BLENDI: return "X86ISD::BLENDI";
18778 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
18779 case X86ISD::ADDUS: return "X86ISD::ADDUS";
18780 case X86ISD::SUBUS: return "X86ISD::SUBUS";
18781 case X86ISD::HADD: return "X86ISD::HADD";
18782 case X86ISD::HSUB: return "X86ISD::HSUB";
18783 case X86ISD::FHADD: return "X86ISD::FHADD";
18784 case X86ISD::FHSUB: return "X86ISD::FHSUB";
18785 case X86ISD::ABS: return "X86ISD::ABS";
18786 case X86ISD::FMAX: return "X86ISD::FMAX";
18787 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
18788 case X86ISD::FMIN: return "X86ISD::FMIN";
18789 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
18790 case X86ISD::FMAXC: return "X86ISD::FMAXC";
18791 case X86ISD::FMINC: return "X86ISD::FMINC";
18792 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
18793 case X86ISD::FRCP: return "X86ISD::FRCP";
18794 case X86ISD::EXTRQI: return "X86ISD::EXTRQI";
18795 case X86ISD::INSERTQI: return "X86ISD::INSERTQI";
18796 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
18797 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
18798 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
18799 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
18800 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
18801 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
18802 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
18803 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
18804 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
18805 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
18806 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
18807 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
18808 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
18809 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
18810 case X86ISD::VZEXT: return "X86ISD::VZEXT";
18811 case X86ISD::VSEXT: return "X86ISD::VSEXT";
18812 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
18813 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
18814 case X86ISD::VINSERT: return "X86ISD::VINSERT";
18815 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
18816 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
18817 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
18818 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
18819 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
18820 case X86ISD::VSHL: return "X86ISD::VSHL";
18821 case X86ISD::VSRL: return "X86ISD::VSRL";
18822 case X86ISD::VSRA: return "X86ISD::VSRA";
18823 case X86ISD::VSHLI: return "X86ISD::VSHLI";
18824 case X86ISD::VSRLI: return "X86ISD::VSRLI";
18825 case X86ISD::VSRAI: return "X86ISD::VSRAI";
18826 case X86ISD::CMPP: return "X86ISD::CMPP";
18827 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
18828 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
18829 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
18830 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
18831 case X86ISD::ADD: return "X86ISD::ADD";
18832 case X86ISD::SUB: return "X86ISD::SUB";
18833 case X86ISD::ADC: return "X86ISD::ADC";
18834 case X86ISD::SBB: return "X86ISD::SBB";
18835 case X86ISD::SMUL: return "X86ISD::SMUL";
18836 case X86ISD::UMUL: return "X86ISD::UMUL";
18837 case X86ISD::SMUL8: return "X86ISD::SMUL8";
18838 case X86ISD::UMUL8: return "X86ISD::UMUL8";
18839 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
18840 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
18841 case X86ISD::INC: return "X86ISD::INC";
18842 case X86ISD::DEC: return "X86ISD::DEC";
18843 case X86ISD::OR: return "X86ISD::OR";
18844 case X86ISD::XOR: return "X86ISD::XOR";
18845 case X86ISD::AND: return "X86ISD::AND";
18846 case X86ISD::BEXTR: return "X86ISD::BEXTR";
18847 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
18848 case X86ISD::PTEST: return "X86ISD::PTEST";
18849 case X86ISD::TESTP: return "X86ISD::TESTP";
18850 case X86ISD::TESTM: return "X86ISD::TESTM";
18851 case X86ISD::TESTNM: return "X86ISD::TESTNM";
18852 case X86ISD::KORTEST: return "X86ISD::KORTEST";
18853 case X86ISD::PACKSS: return "X86ISD::PACKSS";
18854 case X86ISD::PACKUS: return "X86ISD::PACKUS";
18855 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
18856 case X86ISD::VALIGN: return "X86ISD::VALIGN";
18857 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
18858 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
18859 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
18860 case X86ISD::SHUFP: return "X86ISD::SHUFP";
18861 case X86ISD::SHUF128: return "X86ISD::SHUF128";
18862 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
18863 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
18864 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
18865 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
18866 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
18867 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
18868 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
18869 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
18870 case X86ISD::MOVSD: return "X86ISD::MOVSD";
18871 case X86ISD::MOVSS: return "X86ISD::MOVSS";
18872 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
18873 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
18874 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
18875 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
18876 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
18877 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
18878 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
18879 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
18880 case X86ISD::VPERMV: return "X86ISD::VPERMV";
18881 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
18882 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
18883 case X86ISD::VPERMI: return "X86ISD::VPERMI";
18884 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
18885 case X86ISD::VRANGE: return "X86ISD::VRANGE";
18886 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
18887 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
18888 case X86ISD::PSADBW: return "X86ISD::PSADBW";
18889 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
18890 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
18891 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
18892 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
18893 case X86ISD::MFENCE: return "X86ISD::MFENCE";
18894 case X86ISD::SFENCE: return "X86ISD::SFENCE";
18895 case X86ISD::LFENCE: return "X86ISD::LFENCE";
18896 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
18897 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
18898 case X86ISD::SAHF: return "X86ISD::SAHF";
18899 case X86ISD::RDRAND: return "X86ISD::RDRAND";
18900 case X86ISD::RDSEED: return "X86ISD::RDSEED";
18901 case X86ISD::FMADD: return "X86ISD::FMADD";
18902 case X86ISD::FMSUB: return "X86ISD::FMSUB";
18903 case X86ISD::FNMADD: return "X86ISD::FNMADD";
18904 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
18905 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
18906 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
18907 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
18908 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
18909 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
18910 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
18911 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
18912 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
18913 case X86ISD::RNDSCALE: return "X86ISD::RNDSCALE";
18914 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
18915 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
18916 case X86ISD::XTEST: return "X86ISD::XTEST";
18917 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
18918 case X86ISD::EXPAND: return "X86ISD::EXPAND";
18919 case X86ISD::SELECT: return "X86ISD::SELECT";
18920 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
18921 case X86ISD::RCP28: return "X86ISD::RCP28";
18922 case X86ISD::EXP2: return "X86ISD::EXP2";
18923 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
18924 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
18925 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
18926 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
18927 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
18928 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
18929 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
18930 case X86ISD::SCALEF: return "X86ISD::SCALEF";
18931 case X86ISD::ADDS: return "X86ISD::ADDS";
18932 case X86ISD::SUBS: return "X86ISD::SUBS";
18933 case X86ISD::AVG: return "X86ISD::AVG";
18934 case X86ISD::MULHRS: return "X86ISD::MULHRS";
18935 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
18936 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
18941 // isLegalAddressingMode - Return true if the addressing mode represented
18942 // by AM is legal for this target, for a load/store of the specified type.
18943 bool X86TargetLowering::isLegalAddressingMode(const DataLayout &DL,
18944 const AddrMode &AM, Type *Ty,
18945 unsigned AS) const {
18946 // X86 supports extremely general addressing modes.
18947 CodeModel::Model M = getTargetMachine().getCodeModel();
18948 Reloc::Model R = getTargetMachine().getRelocationModel();
18950 // X86 allows a sign-extended 32-bit immediate field as a displacement.
18951 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
18956 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
18958 // If a reference to this global requires an extra load, we can't fold it.
18959 if (isGlobalStubReference(GVFlags))
18962 // If BaseGV requires a register for the PIC base, we cannot also have a
18963 // BaseReg specified.
18964 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
18967 // If lower 4G is not available, then we must use rip-relative addressing.
18968 if ((M != CodeModel::Small || R != Reloc::Static) &&
18969 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
18973 switch (AM.Scale) {
18979 // These scales always work.
18984 // These scales are formed with basereg+scalereg. Only accept if there is
18989 default: // Other stuff never works.
18996 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
18997 unsigned Bits = Ty->getScalarSizeInBits();
18999 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19000 // particularly cheaper than those without.
19004 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19005 // variable shifts just as cheap as scalar ones.
19006 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19009 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19010 // fully general vector.
19014 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19015 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19017 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19018 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19019 return NumBits1 > NumBits2;
19022 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19023 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19026 if (!isTypeLegal(EVT::getEVT(Ty1)))
19029 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19031 // Assuming the caller doesn't have a zeroext or signext return parameter,
19032 // truncation all the way down to i1 is valid.
19036 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19037 return isInt<32>(Imm);
19040 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19041 // Can also use sub to handle negated immediates.
19042 return isInt<32>(Imm);
19045 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
19046 if (!VT1.isInteger() || !VT2.isInteger())
19048 unsigned NumBits1 = VT1.getSizeInBits();
19049 unsigned NumBits2 = VT2.getSizeInBits();
19050 return NumBits1 > NumBits2;
19053 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19054 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19055 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19058 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19059 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19060 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19063 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19064 EVT VT1 = Val.getValueType();
19065 if (isZExtFree(VT1, VT2))
19068 if (Val.getOpcode() != ISD::LOAD)
19071 if (!VT1.isSimple() || !VT1.isInteger() ||
19072 !VT2.isSimple() || !VT2.isInteger())
19075 switch (VT1.getSimpleVT().SimpleTy) {
19080 // X86 has 8, 16, and 32-bit zero-extending loads.
19087 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
19090 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
19091 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()))
19094 VT = VT.getScalarType();
19096 if (!VT.isSimple())
19099 switch (VT.getSimpleVT().SimpleTy) {
19110 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
19111 // i16 instructions are longer (0x66 prefix) and potentially slower.
19112 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19115 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19116 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19117 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19118 /// are assumed to be legal.
19120 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19122 if (!VT.isSimple())
19125 // Not for i1 vectors
19126 if (VT.getScalarType() == MVT::i1)
19129 // Very little shuffling can be done for 64-bit vectors right now.
19130 if (VT.getSizeInBits() == 64)
19133 // We only care that the types being shuffled are legal. The lowering can
19134 // handle any possible shuffle mask that results.
19135 return isTypeLegal(VT.getSimpleVT());
19139 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
19141 // Just delegate to the generic legality, clear masks aren't special.
19142 return isShuffleMaskLegal(Mask, VT);
19145 //===----------------------------------------------------------------------===//
19146 // X86 Scheduler Hooks
19147 //===----------------------------------------------------------------------===//
19149 /// Utility function to emit xbegin specifying the start of an RTM region.
19150 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
19151 const TargetInstrInfo *TII) {
19152 DebugLoc DL = MI->getDebugLoc();
19154 const BasicBlock *BB = MBB->getBasicBlock();
19155 MachineFunction::iterator I = MBB;
19158 // For the v = xbegin(), we generate
19169 MachineBasicBlock *thisMBB = MBB;
19170 MachineFunction *MF = MBB->getParent();
19171 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19172 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19173 MF->insert(I, mainMBB);
19174 MF->insert(I, sinkMBB);
19176 // Transfer the remainder of BB and its successor edges to sinkMBB.
19177 sinkMBB->splice(sinkMBB->begin(), MBB,
19178 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19179 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19183 // # fallthrough to mainMBB
19184 // # abortion to sinkMBB
19185 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
19186 thisMBB->addSuccessor(mainMBB);
19187 thisMBB->addSuccessor(sinkMBB);
19191 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
19192 mainMBB->addSuccessor(sinkMBB);
19195 // EAX is live into the sinkMBB
19196 sinkMBB->addLiveIn(X86::EAX);
19197 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19198 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19201 MI->eraseFromParent();
19205 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
19206 // or XMM0_V32I8 in AVX all of this code can be replaced with that
19207 // in the .td file.
19208 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
19209 const TargetInstrInfo *TII) {
19211 switch (MI->getOpcode()) {
19212 default: llvm_unreachable("illegal opcode!");
19213 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
19214 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
19215 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
19216 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
19217 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
19218 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
19219 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
19220 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
19223 DebugLoc dl = MI->getDebugLoc();
19224 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19226 unsigned NumArgs = MI->getNumOperands();
19227 for (unsigned i = 1; i < NumArgs; ++i) {
19228 MachineOperand &Op = MI->getOperand(i);
19229 if (!(Op.isReg() && Op.isImplicit()))
19230 MIB.addOperand(Op);
19232 if (MI->hasOneMemOperand())
19233 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19235 BuildMI(*BB, MI, dl,
19236 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19237 .addReg(X86::XMM0);
19239 MI->eraseFromParent();
19243 // FIXME: Custom handling because TableGen doesn't support multiple implicit
19244 // defs in an instruction pattern
19245 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
19246 const TargetInstrInfo *TII) {
19248 switch (MI->getOpcode()) {
19249 default: llvm_unreachable("illegal opcode!");
19250 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
19251 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
19252 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
19253 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
19254 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
19255 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
19256 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
19257 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
19260 DebugLoc dl = MI->getDebugLoc();
19261 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19263 unsigned NumArgs = MI->getNumOperands(); // remove the results
19264 for (unsigned i = 1; i < NumArgs; ++i) {
19265 MachineOperand &Op = MI->getOperand(i);
19266 if (!(Op.isReg() && Op.isImplicit()))
19267 MIB.addOperand(Op);
19269 if (MI->hasOneMemOperand())
19270 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19272 BuildMI(*BB, MI, dl,
19273 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19276 MI->eraseFromParent();
19280 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
19281 const X86Subtarget *Subtarget) {
19282 DebugLoc dl = MI->getDebugLoc();
19283 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19284 // Address into RAX/EAX, other two args into ECX, EDX.
19285 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
19286 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
19287 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
19288 for (int i = 0; i < X86::AddrNumOperands; ++i)
19289 MIB.addOperand(MI->getOperand(i));
19291 unsigned ValOps = X86::AddrNumOperands;
19292 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
19293 .addReg(MI->getOperand(ValOps).getReg());
19294 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
19295 .addReg(MI->getOperand(ValOps+1).getReg());
19297 // The instruction doesn't actually take any operands though.
19298 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
19300 MI->eraseFromParent(); // The pseudo is gone now.
19304 MachineBasicBlock *
19305 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
19306 MachineBasicBlock *MBB) const {
19307 // Emit va_arg instruction on X86-64.
19309 // Operands to this pseudo-instruction:
19310 // 0 ) Output : destination address (reg)
19311 // 1-5) Input : va_list address (addr, i64mem)
19312 // 6 ) ArgSize : Size (in bytes) of vararg type
19313 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
19314 // 8 ) Align : Alignment of type
19315 // 9 ) EFLAGS (implicit-def)
19317 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
19318 static_assert(X86::AddrNumOperands == 5,
19319 "VAARG_64 assumes 5 address operands");
19321 unsigned DestReg = MI->getOperand(0).getReg();
19322 MachineOperand &Base = MI->getOperand(1);
19323 MachineOperand &Scale = MI->getOperand(2);
19324 MachineOperand &Index = MI->getOperand(3);
19325 MachineOperand &Disp = MI->getOperand(4);
19326 MachineOperand &Segment = MI->getOperand(5);
19327 unsigned ArgSize = MI->getOperand(6).getImm();
19328 unsigned ArgMode = MI->getOperand(7).getImm();
19329 unsigned Align = MI->getOperand(8).getImm();
19331 // Memory Reference
19332 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
19333 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19334 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19336 // Machine Information
19337 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19338 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
19339 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
19340 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
19341 DebugLoc DL = MI->getDebugLoc();
19343 // struct va_list {
19346 // i64 overflow_area (address)
19347 // i64 reg_save_area (address)
19349 // sizeof(va_list) = 24
19350 // alignment(va_list) = 8
19352 unsigned TotalNumIntRegs = 6;
19353 unsigned TotalNumXMMRegs = 8;
19354 bool UseGPOffset = (ArgMode == 1);
19355 bool UseFPOffset = (ArgMode == 2);
19356 unsigned MaxOffset = TotalNumIntRegs * 8 +
19357 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
19359 /* Align ArgSize to a multiple of 8 */
19360 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
19361 bool NeedsAlign = (Align > 8);
19363 MachineBasicBlock *thisMBB = MBB;
19364 MachineBasicBlock *overflowMBB;
19365 MachineBasicBlock *offsetMBB;
19366 MachineBasicBlock *endMBB;
19368 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
19369 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
19370 unsigned OffsetReg = 0;
19372 if (!UseGPOffset && !UseFPOffset) {
19373 // If we only pull from the overflow region, we don't create a branch.
19374 // We don't need to alter control flow.
19375 OffsetDestReg = 0; // unused
19376 OverflowDestReg = DestReg;
19378 offsetMBB = nullptr;
19379 overflowMBB = thisMBB;
19382 // First emit code to check if gp_offset (or fp_offset) is below the bound.
19383 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
19384 // If not, pull from overflow_area. (branch to overflowMBB)
19389 // offsetMBB overflowMBB
19394 // Registers for the PHI in endMBB
19395 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
19396 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
19398 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19399 MachineFunction *MF = MBB->getParent();
19400 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19401 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19402 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19404 MachineFunction::iterator MBBIter = MBB;
19407 // Insert the new basic blocks
19408 MF->insert(MBBIter, offsetMBB);
19409 MF->insert(MBBIter, overflowMBB);
19410 MF->insert(MBBIter, endMBB);
19412 // Transfer the remainder of MBB and its successor edges to endMBB.
19413 endMBB->splice(endMBB->begin(), thisMBB,
19414 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
19415 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
19417 // Make offsetMBB and overflowMBB successors of thisMBB
19418 thisMBB->addSuccessor(offsetMBB);
19419 thisMBB->addSuccessor(overflowMBB);
19421 // endMBB is a successor of both offsetMBB and overflowMBB
19422 offsetMBB->addSuccessor(endMBB);
19423 overflowMBB->addSuccessor(endMBB);
19425 // Load the offset value into a register
19426 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19427 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
19431 .addDisp(Disp, UseFPOffset ? 4 : 0)
19432 .addOperand(Segment)
19433 .setMemRefs(MMOBegin, MMOEnd);
19435 // Check if there is enough room left to pull this argument.
19436 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
19438 .addImm(MaxOffset + 8 - ArgSizeA8);
19440 // Branch to "overflowMBB" if offset >= max
19441 // Fall through to "offsetMBB" otherwise
19442 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
19443 .addMBB(overflowMBB);
19446 // In offsetMBB, emit code to use the reg_save_area.
19448 assert(OffsetReg != 0);
19450 // Read the reg_save_area address.
19451 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
19452 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
19457 .addOperand(Segment)
19458 .setMemRefs(MMOBegin, MMOEnd);
19460 // Zero-extend the offset
19461 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
19462 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
19465 .addImm(X86::sub_32bit);
19467 // Add the offset to the reg_save_area to get the final address.
19468 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
19469 .addReg(OffsetReg64)
19470 .addReg(RegSaveReg);
19472 // Compute the offset for the next argument
19473 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19474 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
19476 .addImm(UseFPOffset ? 16 : 8);
19478 // Store it back into the va_list.
19479 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
19483 .addDisp(Disp, UseFPOffset ? 4 : 0)
19484 .addOperand(Segment)
19485 .addReg(NextOffsetReg)
19486 .setMemRefs(MMOBegin, MMOEnd);
19489 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
19494 // Emit code to use overflow area
19497 // Load the overflow_area address into a register.
19498 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
19499 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
19504 .addOperand(Segment)
19505 .setMemRefs(MMOBegin, MMOEnd);
19507 // If we need to align it, do so. Otherwise, just copy the address
19508 // to OverflowDestReg.
19510 // Align the overflow address
19511 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
19512 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
19514 // aligned_addr = (addr + (align-1)) & ~(align-1)
19515 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
19516 .addReg(OverflowAddrReg)
19519 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
19521 .addImm(~(uint64_t)(Align-1));
19523 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
19524 .addReg(OverflowAddrReg);
19527 // Compute the next overflow address after this argument.
19528 // (the overflow address should be kept 8-byte aligned)
19529 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
19530 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
19531 .addReg(OverflowDestReg)
19532 .addImm(ArgSizeA8);
19534 // Store the new overflow address.
19535 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
19540 .addOperand(Segment)
19541 .addReg(NextAddrReg)
19542 .setMemRefs(MMOBegin, MMOEnd);
19544 // If we branched, emit the PHI to the front of endMBB.
19546 BuildMI(*endMBB, endMBB->begin(), DL,
19547 TII->get(X86::PHI), DestReg)
19548 .addReg(OffsetDestReg).addMBB(offsetMBB)
19549 .addReg(OverflowDestReg).addMBB(overflowMBB);
19552 // Erase the pseudo instruction
19553 MI->eraseFromParent();
19558 MachineBasicBlock *
19559 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
19561 MachineBasicBlock *MBB) const {
19562 // Emit code to save XMM registers to the stack. The ABI says that the
19563 // number of registers to save is given in %al, so it's theoretically
19564 // possible to do an indirect jump trick to avoid saving all of them,
19565 // however this code takes a simpler approach and just executes all
19566 // of the stores if %al is non-zero. It's less code, and it's probably
19567 // easier on the hardware branch predictor, and stores aren't all that
19568 // expensive anyway.
19570 // Create the new basic blocks. One block contains all the XMM stores,
19571 // and one block is the final destination regardless of whether any
19572 // stores were performed.
19573 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19574 MachineFunction *F = MBB->getParent();
19575 MachineFunction::iterator MBBIter = MBB;
19577 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
19578 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
19579 F->insert(MBBIter, XMMSaveMBB);
19580 F->insert(MBBIter, EndMBB);
19582 // Transfer the remainder of MBB and its successor edges to EndMBB.
19583 EndMBB->splice(EndMBB->begin(), MBB,
19584 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19585 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
19587 // The original block will now fall through to the XMM save block.
19588 MBB->addSuccessor(XMMSaveMBB);
19589 // The XMMSaveMBB will fall through to the end block.
19590 XMMSaveMBB->addSuccessor(EndMBB);
19592 // Now add the instructions.
19593 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19594 DebugLoc DL = MI->getDebugLoc();
19596 unsigned CountReg = MI->getOperand(0).getReg();
19597 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
19598 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
19600 if (!Subtarget->isTargetWin64()) {
19601 // If %al is 0, branch around the XMM save block.
19602 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
19603 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
19604 MBB->addSuccessor(EndMBB);
19607 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
19608 // that was just emitted, but clearly shouldn't be "saved".
19609 assert((MI->getNumOperands() <= 3 ||
19610 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
19611 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
19612 && "Expected last argument to be EFLAGS");
19613 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
19614 // In the XMM save block, save all the XMM argument registers.
19615 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
19616 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
19617 MachineMemOperand *MMO =
19618 F->getMachineMemOperand(
19619 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
19620 MachineMemOperand::MOStore,
19621 /*Size=*/16, /*Align=*/16);
19622 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
19623 .addFrameIndex(RegSaveFrameIndex)
19624 .addImm(/*Scale=*/1)
19625 .addReg(/*IndexReg=*/0)
19626 .addImm(/*Disp=*/Offset)
19627 .addReg(/*Segment=*/0)
19628 .addReg(MI->getOperand(i).getReg())
19629 .addMemOperand(MMO);
19632 MI->eraseFromParent(); // The pseudo instruction is gone now.
19637 // The EFLAGS operand of SelectItr might be missing a kill marker
19638 // because there were multiple uses of EFLAGS, and ISel didn't know
19639 // which to mark. Figure out whether SelectItr should have had a
19640 // kill marker, and set it if it should. Returns the correct kill
19642 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
19643 MachineBasicBlock* BB,
19644 const TargetRegisterInfo* TRI) {
19645 // Scan forward through BB for a use/def of EFLAGS.
19646 MachineBasicBlock::iterator miI(std::next(SelectItr));
19647 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
19648 const MachineInstr& mi = *miI;
19649 if (mi.readsRegister(X86::EFLAGS))
19651 if (mi.definesRegister(X86::EFLAGS))
19652 break; // Should have kill-flag - update below.
19655 // If we hit the end of the block, check whether EFLAGS is live into a
19657 if (miI == BB->end()) {
19658 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
19659 sEnd = BB->succ_end();
19660 sItr != sEnd; ++sItr) {
19661 MachineBasicBlock* succ = *sItr;
19662 if (succ->isLiveIn(X86::EFLAGS))
19667 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
19668 // out. SelectMI should have a kill flag on EFLAGS.
19669 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
19673 MachineBasicBlock *
19674 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
19675 MachineBasicBlock *BB) const {
19676 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19677 DebugLoc DL = MI->getDebugLoc();
19679 // To "insert" a SELECT_CC instruction, we actually have to insert the
19680 // diamond control-flow pattern. The incoming instruction knows the
19681 // destination vreg to set, the condition code register to branch on, the
19682 // true/false values to select between, and a branch opcode to use.
19683 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19684 MachineFunction::iterator It = BB;
19690 // cmpTY ccX, r1, r2
19692 // fallthrough --> copy0MBB
19693 MachineBasicBlock *thisMBB = BB;
19694 MachineFunction *F = BB->getParent();
19696 // We also lower double CMOVs:
19697 // (CMOV (CMOV F, T, cc1), T, cc2)
19698 // to two successives branches. For that, we look for another CMOV as the
19699 // following instruction.
19701 // Without this, we would add a PHI between the two jumps, which ends up
19702 // creating a few copies all around. For instance, for
19704 // (sitofp (zext (fcmp une)))
19706 // we would generate:
19708 // ucomiss %xmm1, %xmm0
19709 // movss <1.0f>, %xmm0
19710 // movaps %xmm0, %xmm1
19712 // xorps %xmm1, %xmm1
19715 // movaps %xmm1, %xmm0
19719 // because this custom-inserter would have generated:
19731 // A: X = ...; Y = ...
19733 // C: Z = PHI [X, A], [Y, B]
19735 // E: PHI [X, C], [Z, D]
19737 // If we lower both CMOVs in a single step, we can instead generate:
19749 // A: X = ...; Y = ...
19751 // E: PHI [X, A], [X, C], [Y, D]
19753 // Which, in our sitofp/fcmp example, gives us something like:
19755 // ucomiss %xmm1, %xmm0
19756 // movss <1.0f>, %xmm0
19759 // xorps %xmm0, %xmm0
19763 MachineInstr *NextCMOV = nullptr;
19764 MachineBasicBlock::iterator NextMIIt =
19765 std::next(MachineBasicBlock::iterator(MI));
19766 if (NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
19767 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
19768 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg())
19769 NextCMOV = &*NextMIIt;
19771 MachineBasicBlock *jcc1MBB = nullptr;
19773 // If we have a double CMOV, we lower it to two successive branches to
19774 // the same block. EFLAGS is used by both, so mark it as live in the second.
19776 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
19777 F->insert(It, jcc1MBB);
19778 jcc1MBB->addLiveIn(X86::EFLAGS);
19781 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
19782 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
19783 F->insert(It, copy0MBB);
19784 F->insert(It, sinkMBB);
19786 // If the EFLAGS register isn't dead in the terminator, then claim that it's
19787 // live into the sink and copy blocks.
19788 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
19790 MachineInstr *LastEFLAGSUser = NextCMOV ? NextCMOV : MI;
19791 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
19792 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
19793 copy0MBB->addLiveIn(X86::EFLAGS);
19794 sinkMBB->addLiveIn(X86::EFLAGS);
19797 // Transfer the remainder of BB and its successor edges to sinkMBB.
19798 sinkMBB->splice(sinkMBB->begin(), BB,
19799 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19800 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
19802 // Add the true and fallthrough blocks as its successors.
19804 // The fallthrough block may be jcc1MBB, if we have a double CMOV.
19805 BB->addSuccessor(jcc1MBB);
19807 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
19808 // jump to the sinkMBB.
19809 jcc1MBB->addSuccessor(copy0MBB);
19810 jcc1MBB->addSuccessor(sinkMBB);
19812 BB->addSuccessor(copy0MBB);
19815 // The true block target of the first (or only) branch is always sinkMBB.
19816 BB->addSuccessor(sinkMBB);
19818 // Create the conditional branch instruction.
19820 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
19821 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
19824 unsigned Opc2 = X86::GetCondBranchFromCond(
19825 (X86::CondCode)NextCMOV->getOperand(3).getImm());
19826 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
19830 // %FalseValue = ...
19831 // # fallthrough to sinkMBB
19832 copy0MBB->addSuccessor(sinkMBB);
19835 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
19837 MachineInstrBuilder MIB =
19838 BuildMI(*sinkMBB, sinkMBB->begin(), DL, TII->get(X86::PHI),
19839 MI->getOperand(0).getReg())
19840 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
19841 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
19843 // If we have a double CMOV, the second Jcc provides the same incoming
19844 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
19846 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
19847 // Copy the PHI result to the register defined by the second CMOV.
19848 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
19849 DL, TII->get(TargetOpcode::COPY), NextCMOV->getOperand(0).getReg())
19850 .addReg(MI->getOperand(0).getReg());
19851 NextCMOV->eraseFromParent();
19854 MI->eraseFromParent(); // The pseudo instruction is gone now.
19858 MachineBasicBlock *
19859 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
19860 MachineBasicBlock *BB) const {
19861 MachineFunction *MF = BB->getParent();
19862 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19863 DebugLoc DL = MI->getDebugLoc();
19864 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19866 assert(MF->shouldSplitStack());
19868 const bool Is64Bit = Subtarget->is64Bit();
19869 const bool IsLP64 = Subtarget->isTarget64BitLP64();
19871 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
19872 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
19875 // ... [Till the alloca]
19876 // If stacklet is not large enough, jump to mallocMBB
19879 // Allocate by subtracting from RSP
19880 // Jump to continueMBB
19883 // Allocate by call to runtime
19887 // [rest of original BB]
19890 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19891 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19892 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19894 MachineRegisterInfo &MRI = MF->getRegInfo();
19895 const TargetRegisterClass *AddrRegClass =
19896 getRegClassFor(getPointerTy(MF->getDataLayout()));
19898 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19899 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19900 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
19901 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
19902 sizeVReg = MI->getOperand(1).getReg(),
19903 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
19905 MachineFunction::iterator MBBIter = BB;
19908 MF->insert(MBBIter, bumpMBB);
19909 MF->insert(MBBIter, mallocMBB);
19910 MF->insert(MBBIter, continueMBB);
19912 continueMBB->splice(continueMBB->begin(), BB,
19913 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19914 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
19916 // Add code to the main basic block to check if the stack limit has been hit,
19917 // and if so, jump to mallocMBB otherwise to bumpMBB.
19918 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
19919 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
19920 .addReg(tmpSPVReg).addReg(sizeVReg);
19921 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
19922 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
19923 .addReg(SPLimitVReg);
19924 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
19926 // bumpMBB simply decreases the stack pointer, since we know the current
19927 // stacklet has enough space.
19928 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
19929 .addReg(SPLimitVReg);
19930 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
19931 .addReg(SPLimitVReg);
19932 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
19934 // Calls into a routine in libgcc to allocate more space from the heap.
19935 const uint32_t *RegMask =
19936 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
19938 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
19940 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19941 .addExternalSymbol("__morestack_allocate_stack_space")
19942 .addRegMask(RegMask)
19943 .addReg(X86::RDI, RegState::Implicit)
19944 .addReg(X86::RAX, RegState::ImplicitDefine);
19945 } else if (Is64Bit) {
19946 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
19948 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19949 .addExternalSymbol("__morestack_allocate_stack_space")
19950 .addRegMask(RegMask)
19951 .addReg(X86::EDI, RegState::Implicit)
19952 .addReg(X86::EAX, RegState::ImplicitDefine);
19954 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
19956 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
19957 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
19958 .addExternalSymbol("__morestack_allocate_stack_space")
19959 .addRegMask(RegMask)
19960 .addReg(X86::EAX, RegState::ImplicitDefine);
19964 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
19967 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
19968 .addReg(IsLP64 ? X86::RAX : X86::EAX);
19969 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
19971 // Set up the CFG correctly.
19972 BB->addSuccessor(bumpMBB);
19973 BB->addSuccessor(mallocMBB);
19974 mallocMBB->addSuccessor(continueMBB);
19975 bumpMBB->addSuccessor(continueMBB);
19977 // Take care of the PHI nodes.
19978 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
19979 MI->getOperand(0).getReg())
19980 .addReg(mallocPtrVReg).addMBB(mallocMBB)
19981 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
19983 // Delete the original pseudo instruction.
19984 MI->eraseFromParent();
19987 return continueMBB;
19990 MachineBasicBlock *
19991 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
19992 MachineBasicBlock *BB) const {
19993 DebugLoc DL = MI->getDebugLoc();
19995 assert(!Subtarget->isTargetMachO());
19997 Subtarget->getFrameLowering()->emitStackProbeCall(*BB->getParent(), *BB, MI,
20000 MI->eraseFromParent(); // The pseudo instruction is gone now.
20004 MachineBasicBlock *
20005 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20006 MachineBasicBlock *BB) const {
20007 // This is pretty easy. We're taking the value that we received from
20008 // our load from the relocation, sticking it in either RDI (x86-64)
20009 // or EAX and doing an indirect call. The return value will then
20010 // be in the normal return register.
20011 MachineFunction *F = BB->getParent();
20012 const X86InstrInfo *TII = Subtarget->getInstrInfo();
20013 DebugLoc DL = MI->getDebugLoc();
20015 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
20016 assert(MI->getOperand(3).isGlobal() && "This should be a global");
20018 // Get a register mask for the lowered call.
20019 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
20020 // proper register mask.
20021 const uint32_t *RegMask =
20022 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
20023 if (Subtarget->is64Bit()) {
20024 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20025 TII->get(X86::MOV64rm), X86::RDI)
20027 .addImm(0).addReg(0)
20028 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20029 MI->getOperand(3).getTargetFlags())
20031 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
20032 addDirectMem(MIB, X86::RDI);
20033 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
20034 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
20035 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20036 TII->get(X86::MOV32rm), X86::EAX)
20038 .addImm(0).addReg(0)
20039 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20040 MI->getOperand(3).getTargetFlags())
20042 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20043 addDirectMem(MIB, X86::EAX);
20044 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20046 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20047 TII->get(X86::MOV32rm), X86::EAX)
20048 .addReg(TII->getGlobalBaseReg(F))
20049 .addImm(0).addReg(0)
20050 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20051 MI->getOperand(3).getTargetFlags())
20053 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20054 addDirectMem(MIB, X86::EAX);
20055 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20058 MI->eraseFromParent(); // The pseudo instruction is gone now.
20062 MachineBasicBlock *
20063 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
20064 MachineBasicBlock *MBB) const {
20065 DebugLoc DL = MI->getDebugLoc();
20066 MachineFunction *MF = MBB->getParent();
20067 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20068 MachineRegisterInfo &MRI = MF->getRegInfo();
20070 const BasicBlock *BB = MBB->getBasicBlock();
20071 MachineFunction::iterator I = MBB;
20074 // Memory Reference
20075 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20076 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20079 unsigned MemOpndSlot = 0;
20081 unsigned CurOp = 0;
20083 DstReg = MI->getOperand(CurOp++).getReg();
20084 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
20085 assert(RC->hasType(MVT::i32) && "Invalid destination!");
20086 unsigned mainDstReg = MRI.createVirtualRegister(RC);
20087 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
20089 MemOpndSlot = CurOp;
20091 MVT PVT = getPointerTy(MF->getDataLayout());
20092 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20093 "Invalid Pointer Size!");
20095 // For v = setjmp(buf), we generate
20098 // buf[LabelOffset] = restoreMBB
20099 // SjLjSetup restoreMBB
20105 // v = phi(main, restore)
20108 // if base pointer being used, load it from frame
20111 MachineBasicBlock *thisMBB = MBB;
20112 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20113 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20114 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
20115 MF->insert(I, mainMBB);
20116 MF->insert(I, sinkMBB);
20117 MF->push_back(restoreMBB);
20119 MachineInstrBuilder MIB;
20121 // Transfer the remainder of BB and its successor edges to sinkMBB.
20122 sinkMBB->splice(sinkMBB->begin(), MBB,
20123 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20124 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20127 unsigned PtrStoreOpc = 0;
20128 unsigned LabelReg = 0;
20129 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20130 Reloc::Model RM = MF->getTarget().getRelocationModel();
20131 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
20132 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
20134 // Prepare IP either in reg or imm.
20135 if (!UseImmLabel) {
20136 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
20137 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
20138 LabelReg = MRI.createVirtualRegister(PtrRC);
20139 if (Subtarget->is64Bit()) {
20140 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
20144 .addMBB(restoreMBB)
20147 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
20148 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
20149 .addReg(XII->getGlobalBaseReg(MF))
20152 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
20156 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
20158 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
20159 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20160 if (i == X86::AddrDisp)
20161 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
20163 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
20166 MIB.addReg(LabelReg);
20168 MIB.addMBB(restoreMBB);
20169 MIB.setMemRefs(MMOBegin, MMOEnd);
20171 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
20172 .addMBB(restoreMBB);
20174 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
20175 MIB.addRegMask(RegInfo->getNoPreservedMask());
20176 thisMBB->addSuccessor(mainMBB);
20177 thisMBB->addSuccessor(restoreMBB);
20181 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
20182 mainMBB->addSuccessor(sinkMBB);
20185 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20186 TII->get(X86::PHI), DstReg)
20187 .addReg(mainDstReg).addMBB(mainMBB)
20188 .addReg(restoreDstReg).addMBB(restoreMBB);
20191 if (RegInfo->hasBasePointer(*MF)) {
20192 const bool Uses64BitFramePtr =
20193 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
20194 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
20195 X86FI->setRestoreBasePointer(MF);
20196 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
20197 unsigned BasePtr = RegInfo->getBaseRegister();
20198 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
20199 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
20200 FramePtr, true, X86FI->getRestoreBasePointerOffset())
20201 .setMIFlag(MachineInstr::FrameSetup);
20203 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
20204 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
20205 restoreMBB->addSuccessor(sinkMBB);
20207 MI->eraseFromParent();
20211 MachineBasicBlock *
20212 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
20213 MachineBasicBlock *MBB) const {
20214 DebugLoc DL = MI->getDebugLoc();
20215 MachineFunction *MF = MBB->getParent();
20216 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20217 MachineRegisterInfo &MRI = MF->getRegInfo();
20219 // Memory Reference
20220 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20221 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20223 MVT PVT = getPointerTy(MF->getDataLayout());
20224 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20225 "Invalid Pointer Size!");
20227 const TargetRegisterClass *RC =
20228 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
20229 unsigned Tmp = MRI.createVirtualRegister(RC);
20230 // Since FP is only updated here but NOT referenced, it's treated as GPR.
20231 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
20232 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
20233 unsigned SP = RegInfo->getStackRegister();
20235 MachineInstrBuilder MIB;
20237 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20238 const int64_t SPOffset = 2 * PVT.getStoreSize();
20240 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
20241 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
20244 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
20245 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
20246 MIB.addOperand(MI->getOperand(i));
20247 MIB.setMemRefs(MMOBegin, MMOEnd);
20249 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
20250 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20251 if (i == X86::AddrDisp)
20252 MIB.addDisp(MI->getOperand(i), LabelOffset);
20254 MIB.addOperand(MI->getOperand(i));
20256 MIB.setMemRefs(MMOBegin, MMOEnd);
20258 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
20259 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20260 if (i == X86::AddrDisp)
20261 MIB.addDisp(MI->getOperand(i), SPOffset);
20263 MIB.addOperand(MI->getOperand(i));
20265 MIB.setMemRefs(MMOBegin, MMOEnd);
20267 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
20269 MI->eraseFromParent();
20273 // Replace 213-type (isel default) FMA3 instructions with 231-type for
20274 // accumulator loops. Writing back to the accumulator allows the coalescer
20275 // to remove extra copies in the loop.
20276 // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
20277 MachineBasicBlock *
20278 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
20279 MachineBasicBlock *MBB) const {
20280 MachineOperand &AddendOp = MI->getOperand(3);
20282 // Bail out early if the addend isn't a register - we can't switch these.
20283 if (!AddendOp.isReg())
20286 MachineFunction &MF = *MBB->getParent();
20287 MachineRegisterInfo &MRI = MF.getRegInfo();
20289 // Check whether the addend is defined by a PHI:
20290 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
20291 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
20292 if (!AddendDef.isPHI())
20295 // Look for the following pattern:
20297 // %addend = phi [%entry, 0], [%loop, %result]
20299 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
20303 // %addend = phi [%entry, 0], [%loop, %result]
20305 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
20307 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
20308 assert(AddendDef.getOperand(i).isReg());
20309 MachineOperand PHISrcOp = AddendDef.getOperand(i);
20310 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
20311 if (&PHISrcInst == MI) {
20312 // Found a matching instruction.
20313 unsigned NewFMAOpc = 0;
20314 switch (MI->getOpcode()) {
20315 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
20316 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
20317 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
20318 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
20319 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
20320 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
20321 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
20322 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
20323 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
20324 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
20325 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
20326 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
20327 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
20328 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
20329 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
20330 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
20331 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
20332 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
20333 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
20334 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
20336 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
20337 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
20338 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
20339 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
20340 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
20341 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
20342 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
20343 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
20344 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
20345 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
20346 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
20347 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
20348 default: llvm_unreachable("Unrecognized FMA variant.");
20351 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
20352 MachineInstrBuilder MIB =
20353 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
20354 .addOperand(MI->getOperand(0))
20355 .addOperand(MI->getOperand(3))
20356 .addOperand(MI->getOperand(2))
20357 .addOperand(MI->getOperand(1));
20358 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
20359 MI->eraseFromParent();
20366 MachineBasicBlock *
20367 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
20368 MachineBasicBlock *BB) const {
20369 switch (MI->getOpcode()) {
20370 default: llvm_unreachable("Unexpected instr type to insert");
20371 case X86::TAILJMPd64:
20372 case X86::TAILJMPr64:
20373 case X86::TAILJMPm64:
20374 case X86::TAILJMPd64_REX:
20375 case X86::TAILJMPr64_REX:
20376 case X86::TAILJMPm64_REX:
20377 llvm_unreachable("TAILJMP64 would not be touched here.");
20378 case X86::TCRETURNdi64:
20379 case X86::TCRETURNri64:
20380 case X86::TCRETURNmi64:
20382 case X86::WIN_ALLOCA:
20383 return EmitLoweredWinAlloca(MI, BB);
20384 case X86::SEG_ALLOCA_32:
20385 case X86::SEG_ALLOCA_64:
20386 return EmitLoweredSegAlloca(MI, BB);
20387 case X86::TLSCall_32:
20388 case X86::TLSCall_64:
20389 return EmitLoweredTLSCall(MI, BB);
20390 case X86::CMOV_GR8:
20391 case X86::CMOV_FR32:
20392 case X86::CMOV_FR64:
20393 case X86::CMOV_V4F32:
20394 case X86::CMOV_V2F64:
20395 case X86::CMOV_V2I64:
20396 case X86::CMOV_V8F32:
20397 case X86::CMOV_V4F64:
20398 case X86::CMOV_V4I64:
20399 case X86::CMOV_V16F32:
20400 case X86::CMOV_V8F64:
20401 case X86::CMOV_V8I64:
20402 case X86::CMOV_GR16:
20403 case X86::CMOV_GR32:
20404 case X86::CMOV_RFP32:
20405 case X86::CMOV_RFP64:
20406 case X86::CMOV_RFP80:
20407 case X86::CMOV_V8I1:
20408 case X86::CMOV_V16I1:
20409 case X86::CMOV_V32I1:
20410 case X86::CMOV_V64I1:
20411 return EmitLoweredSelect(MI, BB);
20413 case X86::FP32_TO_INT16_IN_MEM:
20414 case X86::FP32_TO_INT32_IN_MEM:
20415 case X86::FP32_TO_INT64_IN_MEM:
20416 case X86::FP64_TO_INT16_IN_MEM:
20417 case X86::FP64_TO_INT32_IN_MEM:
20418 case X86::FP64_TO_INT64_IN_MEM:
20419 case X86::FP80_TO_INT16_IN_MEM:
20420 case X86::FP80_TO_INT32_IN_MEM:
20421 case X86::FP80_TO_INT64_IN_MEM: {
20422 MachineFunction *F = BB->getParent();
20423 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20424 DebugLoc DL = MI->getDebugLoc();
20426 // Change the floating point control register to use "round towards zero"
20427 // mode when truncating to an integer value.
20428 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
20429 addFrameReference(BuildMI(*BB, MI, DL,
20430 TII->get(X86::FNSTCW16m)), CWFrameIdx);
20432 // Load the old value of the high byte of the control word...
20434 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
20435 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
20438 // Set the high part to be round to zero...
20439 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
20442 // Reload the modified control word now...
20443 addFrameReference(BuildMI(*BB, MI, DL,
20444 TII->get(X86::FLDCW16m)), CWFrameIdx);
20446 // Restore the memory image of control word to original value
20447 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
20450 // Get the X86 opcode to use.
20452 switch (MI->getOpcode()) {
20453 default: llvm_unreachable("illegal opcode!");
20454 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
20455 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
20456 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
20457 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
20458 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
20459 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
20460 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
20461 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
20462 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
20466 MachineOperand &Op = MI->getOperand(0);
20468 AM.BaseType = X86AddressMode::RegBase;
20469 AM.Base.Reg = Op.getReg();
20471 AM.BaseType = X86AddressMode::FrameIndexBase;
20472 AM.Base.FrameIndex = Op.getIndex();
20474 Op = MI->getOperand(1);
20476 AM.Scale = Op.getImm();
20477 Op = MI->getOperand(2);
20479 AM.IndexReg = Op.getImm();
20480 Op = MI->getOperand(3);
20481 if (Op.isGlobal()) {
20482 AM.GV = Op.getGlobal();
20484 AM.Disp = Op.getImm();
20486 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
20487 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
20489 // Reload the original control word now.
20490 addFrameReference(BuildMI(*BB, MI, DL,
20491 TII->get(X86::FLDCW16m)), CWFrameIdx);
20493 MI->eraseFromParent(); // The pseudo instruction is gone now.
20496 // String/text processing lowering.
20497 case X86::PCMPISTRM128REG:
20498 case X86::VPCMPISTRM128REG:
20499 case X86::PCMPISTRM128MEM:
20500 case X86::VPCMPISTRM128MEM:
20501 case X86::PCMPESTRM128REG:
20502 case X86::VPCMPESTRM128REG:
20503 case X86::PCMPESTRM128MEM:
20504 case X86::VPCMPESTRM128MEM:
20505 assert(Subtarget->hasSSE42() &&
20506 "Target must have SSE4.2 or AVX features enabled");
20507 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
20509 // String/text processing lowering.
20510 case X86::PCMPISTRIREG:
20511 case X86::VPCMPISTRIREG:
20512 case X86::PCMPISTRIMEM:
20513 case X86::VPCMPISTRIMEM:
20514 case X86::PCMPESTRIREG:
20515 case X86::VPCMPESTRIREG:
20516 case X86::PCMPESTRIMEM:
20517 case X86::VPCMPESTRIMEM:
20518 assert(Subtarget->hasSSE42() &&
20519 "Target must have SSE4.2 or AVX features enabled");
20520 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
20522 // Thread synchronization.
20524 return EmitMonitor(MI, BB, Subtarget);
20528 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
20530 case X86::VASTART_SAVE_XMM_REGS:
20531 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
20533 case X86::VAARG_64:
20534 return EmitVAARG64WithCustomInserter(MI, BB);
20536 case X86::EH_SjLj_SetJmp32:
20537 case X86::EH_SjLj_SetJmp64:
20538 return emitEHSjLjSetJmp(MI, BB);
20540 case X86::EH_SjLj_LongJmp32:
20541 case X86::EH_SjLj_LongJmp64:
20542 return emitEHSjLjLongJmp(MI, BB);
20544 case TargetOpcode::STATEPOINT:
20545 // As an implementation detail, STATEPOINT shares the STACKMAP format at
20546 // this point in the process. We diverge later.
20547 return emitPatchPoint(MI, BB);
20549 case TargetOpcode::STACKMAP:
20550 case TargetOpcode::PATCHPOINT:
20551 return emitPatchPoint(MI, BB);
20553 case X86::VFMADDPDr213r:
20554 case X86::VFMADDPSr213r:
20555 case X86::VFMADDSDr213r:
20556 case X86::VFMADDSSr213r:
20557 case X86::VFMSUBPDr213r:
20558 case X86::VFMSUBPSr213r:
20559 case X86::VFMSUBSDr213r:
20560 case X86::VFMSUBSSr213r:
20561 case X86::VFNMADDPDr213r:
20562 case X86::VFNMADDPSr213r:
20563 case X86::VFNMADDSDr213r:
20564 case X86::VFNMADDSSr213r:
20565 case X86::VFNMSUBPDr213r:
20566 case X86::VFNMSUBPSr213r:
20567 case X86::VFNMSUBSDr213r:
20568 case X86::VFNMSUBSSr213r:
20569 case X86::VFMADDSUBPDr213r:
20570 case X86::VFMADDSUBPSr213r:
20571 case X86::VFMSUBADDPDr213r:
20572 case X86::VFMSUBADDPSr213r:
20573 case X86::VFMADDPDr213rY:
20574 case X86::VFMADDPSr213rY:
20575 case X86::VFMSUBPDr213rY:
20576 case X86::VFMSUBPSr213rY:
20577 case X86::VFNMADDPDr213rY:
20578 case X86::VFNMADDPSr213rY:
20579 case X86::VFNMSUBPDr213rY:
20580 case X86::VFNMSUBPSr213rY:
20581 case X86::VFMADDSUBPDr213rY:
20582 case X86::VFMADDSUBPSr213rY:
20583 case X86::VFMSUBADDPDr213rY:
20584 case X86::VFMSUBADDPSr213rY:
20585 return emitFMA3Instr(MI, BB);
20589 //===----------------------------------------------------------------------===//
20590 // X86 Optimization Hooks
20591 //===----------------------------------------------------------------------===//
20593 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
20596 const SelectionDAG &DAG,
20597 unsigned Depth) const {
20598 unsigned BitWidth = KnownZero.getBitWidth();
20599 unsigned Opc = Op.getOpcode();
20600 assert((Opc >= ISD::BUILTIN_OP_END ||
20601 Opc == ISD::INTRINSIC_WO_CHAIN ||
20602 Opc == ISD::INTRINSIC_W_CHAIN ||
20603 Opc == ISD::INTRINSIC_VOID) &&
20604 "Should use MaskedValueIsZero if you don't know whether Op"
20605 " is a target node!");
20607 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
20621 // These nodes' second result is a boolean.
20622 if (Op.getResNo() == 0)
20625 case X86ISD::SETCC:
20626 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
20628 case ISD::INTRINSIC_WO_CHAIN: {
20629 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
20630 unsigned NumLoBits = 0;
20633 case Intrinsic::x86_sse_movmsk_ps:
20634 case Intrinsic::x86_avx_movmsk_ps_256:
20635 case Intrinsic::x86_sse2_movmsk_pd:
20636 case Intrinsic::x86_avx_movmsk_pd_256:
20637 case Intrinsic::x86_mmx_pmovmskb:
20638 case Intrinsic::x86_sse2_pmovmskb_128:
20639 case Intrinsic::x86_avx2_pmovmskb: {
20640 // High bits of movmskp{s|d}, pmovmskb are known zero.
20642 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
20643 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
20644 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
20645 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
20646 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
20647 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
20648 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
20649 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
20651 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
20660 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
20662 const SelectionDAG &,
20663 unsigned Depth) const {
20664 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
20665 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
20666 return Op.getValueType().getScalarType().getSizeInBits();
20672 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
20673 /// node is a GlobalAddress + offset.
20674 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
20675 const GlobalValue* &GA,
20676 int64_t &Offset) const {
20677 if (N->getOpcode() == X86ISD::Wrapper) {
20678 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
20679 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
20680 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
20684 return TargetLowering::isGAPlusOffset(N, GA, Offset);
20687 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
20688 /// same as extracting the high 128-bit part of 256-bit vector and then
20689 /// inserting the result into the low part of a new 256-bit vector
20690 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
20691 EVT VT = SVOp->getValueType(0);
20692 unsigned NumElems = VT.getVectorNumElements();
20694 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20695 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
20696 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20697 SVOp->getMaskElt(j) >= 0)
20703 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
20704 /// same as extracting the low 128-bit part of 256-bit vector and then
20705 /// inserting the result into the high part of a new 256-bit vector
20706 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
20707 EVT VT = SVOp->getValueType(0);
20708 unsigned NumElems = VT.getVectorNumElements();
20710 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20711 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
20712 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20713 SVOp->getMaskElt(j) >= 0)
20719 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
20720 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
20721 TargetLowering::DAGCombinerInfo &DCI,
20722 const X86Subtarget* Subtarget) {
20724 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20725 SDValue V1 = SVOp->getOperand(0);
20726 SDValue V2 = SVOp->getOperand(1);
20727 EVT VT = SVOp->getValueType(0);
20728 unsigned NumElems = VT.getVectorNumElements();
20730 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
20731 V2.getOpcode() == ISD::CONCAT_VECTORS) {
20735 // V UNDEF BUILD_VECTOR UNDEF
20737 // CONCAT_VECTOR CONCAT_VECTOR
20740 // RESULT: V + zero extended
20742 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
20743 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
20744 V1.getOperand(1).getOpcode() != ISD::UNDEF)
20747 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
20750 // To match the shuffle mask, the first half of the mask should
20751 // be exactly the first vector, and all the rest a splat with the
20752 // first element of the second one.
20753 for (unsigned i = 0; i != NumElems/2; ++i)
20754 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
20755 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
20758 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
20759 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
20760 if (Ld->hasNUsesOfValue(1, 0)) {
20761 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
20762 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
20764 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
20766 Ld->getPointerInfo(),
20767 Ld->getAlignment(),
20768 false/*isVolatile*/, true/*ReadMem*/,
20769 false/*WriteMem*/);
20771 // Make sure the newly-created LOAD is in the same position as Ld in
20772 // terms of dependency. We create a TokenFactor for Ld and ResNode,
20773 // and update uses of Ld's output chain to use the TokenFactor.
20774 if (Ld->hasAnyUseOfValue(1)) {
20775 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
20776 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
20777 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
20778 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
20779 SDValue(ResNode.getNode(), 1));
20782 return DAG.getBitcast(VT, ResNode);
20786 // Emit a zeroed vector and insert the desired subvector on its
20788 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
20789 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
20790 return DCI.CombineTo(N, InsV);
20793 //===--------------------------------------------------------------------===//
20794 // Combine some shuffles into subvector extracts and inserts:
20797 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20798 if (isShuffleHigh128VectorInsertLow(SVOp)) {
20799 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
20800 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
20801 return DCI.CombineTo(N, InsV);
20804 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20805 if (isShuffleLow128VectorInsertHigh(SVOp)) {
20806 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
20807 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
20808 return DCI.CombineTo(N, InsV);
20814 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
20817 /// This is the leaf of the recursive combinine below. When we have found some
20818 /// chain of single-use x86 shuffle instructions and accumulated the combined
20819 /// shuffle mask represented by them, this will try to pattern match that mask
20820 /// into either a single instruction if there is a special purpose instruction
20821 /// for this operation, or into a PSHUFB instruction which is a fully general
20822 /// instruction but should only be used to replace chains over a certain depth.
20823 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
20824 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
20825 TargetLowering::DAGCombinerInfo &DCI,
20826 const X86Subtarget *Subtarget) {
20827 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
20829 // Find the operand that enters the chain. Note that multiple uses are OK
20830 // here, we're not going to remove the operand we find.
20831 SDValue Input = Op.getOperand(0);
20832 while (Input.getOpcode() == ISD::BITCAST)
20833 Input = Input.getOperand(0);
20835 MVT VT = Input.getSimpleValueType();
20836 MVT RootVT = Root.getSimpleValueType();
20839 // Just remove no-op shuffle masks.
20840 if (Mask.size() == 1) {
20841 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
20846 // Use the float domain if the operand type is a floating point type.
20847 bool FloatDomain = VT.isFloatingPoint();
20849 // For floating point shuffles, we don't have free copies in the shuffle
20850 // instructions or the ability to load as part of the instruction, so
20851 // canonicalize their shuffles to UNPCK or MOV variants.
20853 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
20854 // vectors because it can have a load folded into it that UNPCK cannot. This
20855 // doesn't preclude something switching to the shorter encoding post-RA.
20857 // FIXME: Should teach these routines about AVX vector widths.
20858 if (FloatDomain && VT.getSizeInBits() == 128) {
20859 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
20860 bool Lo = Mask.equals({0, 0});
20863 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
20864 // is no slower than UNPCKLPD but has the option to fold the input operand
20865 // into even an unaligned memory load.
20866 if (Lo && Subtarget->hasSSE3()) {
20867 Shuffle = X86ISD::MOVDDUP;
20868 ShuffleVT = MVT::v2f64;
20870 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
20871 // than the UNPCK variants.
20872 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
20873 ShuffleVT = MVT::v4f32;
20875 if (Depth == 1 && Root->getOpcode() == Shuffle)
20876 return false; // Nothing to do!
20877 Op = DAG.getBitcast(ShuffleVT, Input);
20878 DCI.AddToWorklist(Op.getNode());
20879 if (Shuffle == X86ISD::MOVDDUP)
20880 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20882 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20883 DCI.AddToWorklist(Op.getNode());
20884 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20888 if (Subtarget->hasSSE3() &&
20889 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
20890 bool Lo = Mask.equals({0, 0, 2, 2});
20891 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
20892 MVT ShuffleVT = MVT::v4f32;
20893 if (Depth == 1 && Root->getOpcode() == Shuffle)
20894 return false; // Nothing to do!
20895 Op = DAG.getBitcast(ShuffleVT, Input);
20896 DCI.AddToWorklist(Op.getNode());
20897 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20898 DCI.AddToWorklist(Op.getNode());
20899 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20903 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
20904 bool Lo = Mask.equals({0, 0, 1, 1});
20905 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20906 MVT ShuffleVT = MVT::v4f32;
20907 if (Depth == 1 && Root->getOpcode() == Shuffle)
20908 return false; // Nothing to do!
20909 Op = DAG.getBitcast(ShuffleVT, Input);
20910 DCI.AddToWorklist(Op.getNode());
20911 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20912 DCI.AddToWorklist(Op.getNode());
20913 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20919 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
20920 // variants as none of these have single-instruction variants that are
20921 // superior to the UNPCK formulation.
20922 if (!FloatDomain && VT.getSizeInBits() == 128 &&
20923 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
20924 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
20925 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
20927 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
20928 bool Lo = Mask[0] == 0;
20929 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20930 if (Depth == 1 && Root->getOpcode() == Shuffle)
20931 return false; // Nothing to do!
20933 switch (Mask.size()) {
20935 ShuffleVT = MVT::v8i16;
20938 ShuffleVT = MVT::v16i8;
20941 llvm_unreachable("Impossible mask size!");
20943 Op = DAG.getBitcast(ShuffleVT, Input);
20944 DCI.AddToWorklist(Op.getNode());
20945 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20946 DCI.AddToWorklist(Op.getNode());
20947 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20952 // Don't try to re-form single instruction chains under any circumstances now
20953 // that we've done encoding canonicalization for them.
20957 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
20958 // can replace them with a single PSHUFB instruction profitably. Intel's
20959 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
20960 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
20961 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
20962 SmallVector<SDValue, 16> PSHUFBMask;
20963 int NumBytes = VT.getSizeInBits() / 8;
20964 int Ratio = NumBytes / Mask.size();
20965 for (int i = 0; i < NumBytes; ++i) {
20966 if (Mask[i / Ratio] == SM_SentinelUndef) {
20967 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
20970 int M = Mask[i / Ratio] != SM_SentinelZero
20971 ? Ratio * Mask[i / Ratio] + i % Ratio
20973 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
20975 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
20976 Op = DAG.getBitcast(ByteVT, Input);
20977 DCI.AddToWorklist(Op.getNode());
20978 SDValue PSHUFBMaskOp =
20979 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
20980 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
20981 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
20982 DCI.AddToWorklist(Op.getNode());
20983 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20988 // Failed to find any combines.
20992 /// \brief Fully generic combining of x86 shuffle instructions.
20994 /// This should be the last combine run over the x86 shuffle instructions. Once
20995 /// they have been fully optimized, this will recursively consider all chains
20996 /// of single-use shuffle instructions, build a generic model of the cumulative
20997 /// shuffle operation, and check for simpler instructions which implement this
20998 /// operation. We use this primarily for two purposes:
21000 /// 1) Collapse generic shuffles to specialized single instructions when
21001 /// equivalent. In most cases, this is just an encoding size win, but
21002 /// sometimes we will collapse multiple generic shuffles into a single
21003 /// special-purpose shuffle.
21004 /// 2) Look for sequences of shuffle instructions with 3 or more total
21005 /// instructions, and replace them with the slightly more expensive SSSE3
21006 /// PSHUFB instruction if available. We do this as the last combining step
21007 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
21008 /// a suitable short sequence of other instructions. The PHUFB will either
21009 /// use a register or have to read from memory and so is slightly (but only
21010 /// slightly) more expensive than the other shuffle instructions.
21012 /// Because this is inherently a quadratic operation (for each shuffle in
21013 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
21014 /// This should never be an issue in practice as the shuffle lowering doesn't
21015 /// produce sequences of more than 8 instructions.
21017 /// FIXME: We will currently miss some cases where the redundant shuffling
21018 /// would simplify under the threshold for PSHUFB formation because of
21019 /// combine-ordering. To fix this, we should do the redundant instruction
21020 /// combining in this recursive walk.
21021 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
21022 ArrayRef<int> RootMask,
21023 int Depth, bool HasPSHUFB,
21025 TargetLowering::DAGCombinerInfo &DCI,
21026 const X86Subtarget *Subtarget) {
21027 // Bound the depth of our recursive combine because this is ultimately
21028 // quadratic in nature.
21032 // Directly rip through bitcasts to find the underlying operand.
21033 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
21034 Op = Op.getOperand(0);
21036 MVT VT = Op.getSimpleValueType();
21037 if (!VT.isVector())
21038 return false; // Bail if we hit a non-vector.
21040 assert(Root.getSimpleValueType().isVector() &&
21041 "Shuffles operate on vector types!");
21042 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
21043 "Can only combine shuffles of the same vector register size.");
21045 if (!isTargetShuffle(Op.getOpcode()))
21047 SmallVector<int, 16> OpMask;
21049 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
21050 // We only can combine unary shuffles which we can decode the mask for.
21051 if (!HaveMask || !IsUnary)
21054 assert(VT.getVectorNumElements() == OpMask.size() &&
21055 "Different mask size from vector size!");
21056 assert(((RootMask.size() > OpMask.size() &&
21057 RootMask.size() % OpMask.size() == 0) ||
21058 (OpMask.size() > RootMask.size() &&
21059 OpMask.size() % RootMask.size() == 0) ||
21060 OpMask.size() == RootMask.size()) &&
21061 "The smaller number of elements must divide the larger.");
21062 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
21063 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
21064 assert(((RootRatio == 1 && OpRatio == 1) ||
21065 (RootRatio == 1) != (OpRatio == 1)) &&
21066 "Must not have a ratio for both incoming and op masks!");
21068 SmallVector<int, 16> Mask;
21069 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
21071 // Merge this shuffle operation's mask into our accumulated mask. Note that
21072 // this shuffle's mask will be the first applied to the input, followed by the
21073 // root mask to get us all the way to the root value arrangement. The reason
21074 // for this order is that we are recursing up the operation chain.
21075 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
21076 int RootIdx = i / RootRatio;
21077 if (RootMask[RootIdx] < 0) {
21078 // This is a zero or undef lane, we're done.
21079 Mask.push_back(RootMask[RootIdx]);
21083 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
21084 int OpIdx = RootMaskedIdx / OpRatio;
21085 if (OpMask[OpIdx] < 0) {
21086 // The incoming lanes are zero or undef, it doesn't matter which ones we
21088 Mask.push_back(OpMask[OpIdx]);
21092 // Ok, we have non-zero lanes, map them through.
21093 Mask.push_back(OpMask[OpIdx] * OpRatio +
21094 RootMaskedIdx % OpRatio);
21097 // See if we can recurse into the operand to combine more things.
21098 switch (Op.getOpcode()) {
21099 case X86ISD::PSHUFB:
21101 case X86ISD::PSHUFD:
21102 case X86ISD::PSHUFHW:
21103 case X86ISD::PSHUFLW:
21104 if (Op.getOperand(0).hasOneUse() &&
21105 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21106 HasPSHUFB, DAG, DCI, Subtarget))
21110 case X86ISD::UNPCKL:
21111 case X86ISD::UNPCKH:
21112 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
21113 // We can't check for single use, we have to check that this shuffle is the only user.
21114 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
21115 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21116 HasPSHUFB, DAG, DCI, Subtarget))
21121 // Minor canonicalization of the accumulated shuffle mask to make it easier
21122 // to match below. All this does is detect masks with squential pairs of
21123 // elements, and shrink them to the half-width mask. It does this in a loop
21124 // so it will reduce the size of the mask to the minimal width mask which
21125 // performs an equivalent shuffle.
21126 SmallVector<int, 16> WidenedMask;
21127 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
21128 Mask = std::move(WidenedMask);
21129 WidenedMask.clear();
21132 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
21136 /// \brief Get the PSHUF-style mask from PSHUF node.
21138 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
21139 /// PSHUF-style masks that can be reused with such instructions.
21140 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
21141 MVT VT = N.getSimpleValueType();
21142 SmallVector<int, 4> Mask;
21144 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
21148 // If we have more than 128-bits, only the low 128-bits of shuffle mask
21149 // matter. Check that the upper masks are repeats and remove them.
21150 if (VT.getSizeInBits() > 128) {
21151 int LaneElts = 128 / VT.getScalarSizeInBits();
21153 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
21154 for (int j = 0; j < LaneElts; ++j)
21155 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
21156 "Mask doesn't repeat in high 128-bit lanes!");
21158 Mask.resize(LaneElts);
21161 switch (N.getOpcode()) {
21162 case X86ISD::PSHUFD:
21164 case X86ISD::PSHUFLW:
21167 case X86ISD::PSHUFHW:
21168 Mask.erase(Mask.begin(), Mask.begin() + 4);
21169 for (int &M : Mask)
21173 llvm_unreachable("No valid shuffle instruction found!");
21177 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
21179 /// We walk up the chain and look for a combinable shuffle, skipping over
21180 /// shuffles that we could hoist this shuffle's transformation past without
21181 /// altering anything.
21183 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
21185 TargetLowering::DAGCombinerInfo &DCI) {
21186 assert(N.getOpcode() == X86ISD::PSHUFD &&
21187 "Called with something other than an x86 128-bit half shuffle!");
21190 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
21191 // of the shuffles in the chain so that we can form a fresh chain to replace
21193 SmallVector<SDValue, 8> Chain;
21194 SDValue V = N.getOperand(0);
21195 for (; V.hasOneUse(); V = V.getOperand(0)) {
21196 switch (V.getOpcode()) {
21198 return SDValue(); // Nothing combined!
21201 // Skip bitcasts as we always know the type for the target specific
21205 case X86ISD::PSHUFD:
21206 // Found another dword shuffle.
21209 case X86ISD::PSHUFLW:
21210 // Check that the low words (being shuffled) are the identity in the
21211 // dword shuffle, and the high words are self-contained.
21212 if (Mask[0] != 0 || Mask[1] != 1 ||
21213 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
21216 Chain.push_back(V);
21219 case X86ISD::PSHUFHW:
21220 // Check that the high words (being shuffled) are the identity in the
21221 // dword shuffle, and the low words are self-contained.
21222 if (Mask[2] != 2 || Mask[3] != 3 ||
21223 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
21226 Chain.push_back(V);
21229 case X86ISD::UNPCKL:
21230 case X86ISD::UNPCKH:
21231 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
21232 // shuffle into a preceding word shuffle.
21233 if (V.getSimpleValueType().getScalarType() != MVT::i8 &&
21234 V.getSimpleValueType().getScalarType() != MVT::i16)
21237 // Search for a half-shuffle which we can combine with.
21238 unsigned CombineOp =
21239 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
21240 if (V.getOperand(0) != V.getOperand(1) ||
21241 !V->isOnlyUserOf(V.getOperand(0).getNode()))
21243 Chain.push_back(V);
21244 V = V.getOperand(0);
21246 switch (V.getOpcode()) {
21248 return SDValue(); // Nothing to combine.
21250 case X86ISD::PSHUFLW:
21251 case X86ISD::PSHUFHW:
21252 if (V.getOpcode() == CombineOp)
21255 Chain.push_back(V);
21259 V = V.getOperand(0);
21263 } while (V.hasOneUse());
21266 // Break out of the loop if we break out of the switch.
21270 if (!V.hasOneUse())
21271 // We fell out of the loop without finding a viable combining instruction.
21274 // Merge this node's mask and our incoming mask.
21275 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21276 for (int &M : Mask)
21278 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
21279 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
21281 // Rebuild the chain around this new shuffle.
21282 while (!Chain.empty()) {
21283 SDValue W = Chain.pop_back_val();
21285 if (V.getValueType() != W.getOperand(0).getValueType())
21286 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
21288 switch (W.getOpcode()) {
21290 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
21292 case X86ISD::UNPCKL:
21293 case X86ISD::UNPCKH:
21294 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
21297 case X86ISD::PSHUFD:
21298 case X86ISD::PSHUFLW:
21299 case X86ISD::PSHUFHW:
21300 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
21304 if (V.getValueType() != N.getValueType())
21305 V = DAG.getBitcast(N.getValueType(), V);
21307 // Return the new chain to replace N.
21311 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
21313 /// We walk up the chain, skipping shuffles of the other half and looking
21314 /// through shuffles which switch halves trying to find a shuffle of the same
21315 /// pair of dwords.
21316 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
21318 TargetLowering::DAGCombinerInfo &DCI) {
21320 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
21321 "Called with something other than an x86 128-bit half shuffle!");
21323 unsigned CombineOpcode = N.getOpcode();
21325 // Walk up a single-use chain looking for a combinable shuffle.
21326 SDValue V = N.getOperand(0);
21327 for (; V.hasOneUse(); V = V.getOperand(0)) {
21328 switch (V.getOpcode()) {
21330 return false; // Nothing combined!
21333 // Skip bitcasts as we always know the type for the target specific
21337 case X86ISD::PSHUFLW:
21338 case X86ISD::PSHUFHW:
21339 if (V.getOpcode() == CombineOpcode)
21342 // Other-half shuffles are no-ops.
21345 // Break out of the loop if we break out of the switch.
21349 if (!V.hasOneUse())
21350 // We fell out of the loop without finding a viable combining instruction.
21353 // Combine away the bottom node as its shuffle will be accumulated into
21354 // a preceding shuffle.
21355 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21357 // Record the old value.
21360 // Merge this node's mask and our incoming mask (adjusted to account for all
21361 // the pshufd instructions encountered).
21362 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21363 for (int &M : Mask)
21365 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
21366 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
21368 // Check that the shuffles didn't cancel each other out. If not, we need to
21369 // combine to the new one.
21371 // Replace the combinable shuffle with the combined one, updating all users
21372 // so that we re-evaluate the chain here.
21373 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
21378 /// \brief Try to combine x86 target specific shuffles.
21379 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
21380 TargetLowering::DAGCombinerInfo &DCI,
21381 const X86Subtarget *Subtarget) {
21383 MVT VT = N.getSimpleValueType();
21384 SmallVector<int, 4> Mask;
21386 switch (N.getOpcode()) {
21387 case X86ISD::PSHUFD:
21388 case X86ISD::PSHUFLW:
21389 case X86ISD::PSHUFHW:
21390 Mask = getPSHUFShuffleMask(N);
21391 assert(Mask.size() == 4);
21397 // Nuke no-op shuffles that show up after combining.
21398 if (isNoopShuffleMask(Mask))
21399 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21401 // Look for simplifications involving one or two shuffle instructions.
21402 SDValue V = N.getOperand(0);
21403 switch (N.getOpcode()) {
21406 case X86ISD::PSHUFLW:
21407 case X86ISD::PSHUFHW:
21408 assert(VT.getScalarType() == MVT::i16 && "Bad word shuffle type!");
21410 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
21411 return SDValue(); // We combined away this shuffle, so we're done.
21413 // See if this reduces to a PSHUFD which is no more expensive and can
21414 // combine with more operations. Note that it has to at least flip the
21415 // dwords as otherwise it would have been removed as a no-op.
21416 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
21417 int DMask[] = {0, 1, 2, 3};
21418 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
21419 DMask[DOffset + 0] = DOffset + 1;
21420 DMask[DOffset + 1] = DOffset + 0;
21421 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
21422 V = DAG.getBitcast(DVT, V);
21423 DCI.AddToWorklist(V.getNode());
21424 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
21425 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
21426 DCI.AddToWorklist(V.getNode());
21427 return DAG.getBitcast(VT, V);
21430 // Look for shuffle patterns which can be implemented as a single unpack.
21431 // FIXME: This doesn't handle the location of the PSHUFD generically, and
21432 // only works when we have a PSHUFD followed by two half-shuffles.
21433 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
21434 (V.getOpcode() == X86ISD::PSHUFLW ||
21435 V.getOpcode() == X86ISD::PSHUFHW) &&
21436 V.getOpcode() != N.getOpcode() &&
21438 SDValue D = V.getOperand(0);
21439 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
21440 D = D.getOperand(0);
21441 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
21442 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21443 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
21444 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21445 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21447 for (int i = 0; i < 4; ++i) {
21448 WordMask[i + NOffset] = Mask[i] + NOffset;
21449 WordMask[i + VOffset] = VMask[i] + VOffset;
21451 // Map the word mask through the DWord mask.
21453 for (int i = 0; i < 8; ++i)
21454 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
21455 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
21456 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
21457 // We can replace all three shuffles with an unpack.
21458 V = DAG.getBitcast(VT, D.getOperand(0));
21459 DCI.AddToWorklist(V.getNode());
21460 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
21469 case X86ISD::PSHUFD:
21470 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
21479 /// \brief Try to combine a shuffle into a target-specific add-sub node.
21481 /// We combine this directly on the abstract vector shuffle nodes so it is
21482 /// easier to generically match. We also insert dummy vector shuffle nodes for
21483 /// the operands which explicitly discard the lanes which are unused by this
21484 /// operation to try to flow through the rest of the combiner the fact that
21485 /// they're unused.
21486 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
21488 EVT VT = N->getValueType(0);
21490 // We only handle target-independent shuffles.
21491 // FIXME: It would be easy and harmless to use the target shuffle mask
21492 // extraction tool to support more.
21493 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
21496 auto *SVN = cast<ShuffleVectorSDNode>(N);
21497 ArrayRef<int> Mask = SVN->getMask();
21498 SDValue V1 = N->getOperand(0);
21499 SDValue V2 = N->getOperand(1);
21501 // We require the first shuffle operand to be the SUB node, and the second to
21502 // be the ADD node.
21503 // FIXME: We should support the commuted patterns.
21504 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
21507 // If there are other uses of these operations we can't fold them.
21508 if (!V1->hasOneUse() || !V2->hasOneUse())
21511 // Ensure that both operations have the same operands. Note that we can
21512 // commute the FADD operands.
21513 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
21514 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
21515 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
21518 // We're looking for blends between FADD and FSUB nodes. We insist on these
21519 // nodes being lined up in a specific expected pattern.
21520 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
21521 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
21522 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
21525 // Only specific types are legal at this point, assert so we notice if and
21526 // when these change.
21527 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
21528 VT == MVT::v4f64) &&
21529 "Unknown vector type encountered!");
21531 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
21534 /// PerformShuffleCombine - Performs several different shuffle combines.
21535 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
21536 TargetLowering::DAGCombinerInfo &DCI,
21537 const X86Subtarget *Subtarget) {
21539 SDValue N0 = N->getOperand(0);
21540 SDValue N1 = N->getOperand(1);
21541 EVT VT = N->getValueType(0);
21543 // Don't create instructions with illegal types after legalize types has run.
21544 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21545 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
21548 // If we have legalized the vector types, look for blends of FADD and FSUB
21549 // nodes that we can fuse into an ADDSUB node.
21550 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
21551 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
21554 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
21555 if (Subtarget->hasFp256() && VT.is256BitVector() &&
21556 N->getOpcode() == ISD::VECTOR_SHUFFLE)
21557 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
21559 // During Type Legalization, when promoting illegal vector types,
21560 // the backend might introduce new shuffle dag nodes and bitcasts.
21562 // This code performs the following transformation:
21563 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
21564 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
21566 // We do this only if both the bitcast and the BINOP dag nodes have
21567 // one use. Also, perform this transformation only if the new binary
21568 // operation is legal. This is to avoid introducing dag nodes that
21569 // potentially need to be further expanded (or custom lowered) into a
21570 // less optimal sequence of dag nodes.
21571 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
21572 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
21573 N0.getOpcode() == ISD::BITCAST) {
21574 SDValue BC0 = N0.getOperand(0);
21575 EVT SVT = BC0.getValueType();
21576 unsigned Opcode = BC0.getOpcode();
21577 unsigned NumElts = VT.getVectorNumElements();
21579 if (BC0.hasOneUse() && SVT.isVector() &&
21580 SVT.getVectorNumElements() * 2 == NumElts &&
21581 TLI.isOperationLegal(Opcode, VT)) {
21582 bool CanFold = false;
21594 unsigned SVTNumElts = SVT.getVectorNumElements();
21595 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21596 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
21597 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
21598 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
21599 CanFold = SVOp->getMaskElt(i) < 0;
21602 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
21603 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
21604 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
21605 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
21610 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
21611 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
21612 // consecutive, non-overlapping, and in the right order.
21613 SmallVector<SDValue, 16> Elts;
21614 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
21615 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
21617 if (SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true))
21620 if (isTargetShuffle(N->getOpcode())) {
21622 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
21623 if (Shuffle.getNode())
21626 // Try recursively combining arbitrary sequences of x86 shuffle
21627 // instructions into higher-order shuffles. We do this after combining
21628 // specific PSHUF instruction sequences into their minimal form so that we
21629 // can evaluate how many specialized shuffle instructions are involved in
21630 // a particular chain.
21631 SmallVector<int, 1> NonceMask; // Just a placeholder.
21632 NonceMask.push_back(0);
21633 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
21634 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
21636 return SDValue(); // This routine will use CombineTo to replace N.
21642 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
21643 /// specific shuffle of a load can be folded into a single element load.
21644 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
21645 /// shuffles have been custom lowered so we need to handle those here.
21646 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
21647 TargetLowering::DAGCombinerInfo &DCI) {
21648 if (DCI.isBeforeLegalizeOps())
21651 SDValue InVec = N->getOperand(0);
21652 SDValue EltNo = N->getOperand(1);
21654 if (!isa<ConstantSDNode>(EltNo))
21657 EVT OriginalVT = InVec.getValueType();
21659 if (InVec.getOpcode() == ISD::BITCAST) {
21660 // Don't duplicate a load with other uses.
21661 if (!InVec.hasOneUse())
21663 EVT BCVT = InVec.getOperand(0).getValueType();
21664 if (!BCVT.isVector() ||
21665 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
21667 InVec = InVec.getOperand(0);
21670 EVT CurrentVT = InVec.getValueType();
21672 if (!isTargetShuffle(InVec.getOpcode()))
21675 // Don't duplicate a load with other uses.
21676 if (!InVec.hasOneUse())
21679 SmallVector<int, 16> ShuffleMask;
21681 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
21682 ShuffleMask, UnaryShuffle))
21685 // Select the input vector, guarding against out of range extract vector.
21686 unsigned NumElems = CurrentVT.getVectorNumElements();
21687 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
21688 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
21689 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
21690 : InVec.getOperand(1);
21692 // If inputs to shuffle are the same for both ops, then allow 2 uses
21693 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
21694 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
21696 if (LdNode.getOpcode() == ISD::BITCAST) {
21697 // Don't duplicate a load with other uses.
21698 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
21701 AllowedUses = 1; // only allow 1 load use if we have a bitcast
21702 LdNode = LdNode.getOperand(0);
21705 if (!ISD::isNormalLoad(LdNode.getNode()))
21708 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
21710 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
21713 EVT EltVT = N->getValueType(0);
21714 // If there's a bitcast before the shuffle, check if the load type and
21715 // alignment is valid.
21716 unsigned Align = LN0->getAlignment();
21717 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21718 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
21719 EltVT.getTypeForEVT(*DAG.getContext()));
21721 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
21724 // All checks match so transform back to vector_shuffle so that DAG combiner
21725 // can finish the job
21728 // Create shuffle node taking into account the case that its a unary shuffle
21729 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
21730 : InVec.getOperand(1);
21731 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
21732 InVec.getOperand(0), Shuffle,
21734 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
21735 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
21739 /// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
21740 /// special and don't usually play with other vector types, it's better to
21741 /// handle them early to be sure we emit efficient code by avoiding
21742 /// store-load conversions.
21743 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
21744 if (N->getValueType(0) != MVT::x86mmx ||
21745 N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
21746 N->getOperand(0)->getValueType(0) != MVT::v2i32)
21749 SDValue V = N->getOperand(0);
21750 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
21751 if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
21752 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
21753 N->getValueType(0), V.getOperand(0));
21758 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
21759 /// generation and convert it from being a bunch of shuffles and extracts
21760 /// into a somewhat faster sequence. For i686, the best sequence is apparently
21761 /// storing the value and loading scalars back, while for x64 we should
21762 /// use 64-bit extracts and shifts.
21763 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
21764 TargetLowering::DAGCombinerInfo &DCI) {
21765 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
21768 SDValue InputVector = N->getOperand(0);
21769 SDLoc dl(InputVector);
21770 // Detect mmx to i32 conversion through a v2i32 elt extract.
21771 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
21772 N->getValueType(0) == MVT::i32 &&
21773 InputVector.getValueType() == MVT::v2i32) {
21775 // The bitcast source is a direct mmx result.
21776 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
21777 if (MMXSrc.getValueType() == MVT::x86mmx)
21778 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21779 N->getValueType(0),
21780 InputVector.getNode()->getOperand(0));
21782 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
21783 SDValue MMXSrcOp = MMXSrc.getOperand(0);
21784 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
21785 MMXSrc.getValueType() == MVT::i64 && MMXSrcOp.hasOneUse() &&
21786 MMXSrcOp.getOpcode() == ISD::BITCAST &&
21787 MMXSrcOp.getValueType() == MVT::v1i64 &&
21788 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
21789 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21790 N->getValueType(0),
21791 MMXSrcOp.getOperand(0));
21794 EVT VT = N->getValueType(0);
21796 if (VT == MVT::i1 && dyn_cast<ConstantSDNode>(N->getOperand(1)) &&
21797 InputVector.getOpcode() == ISD::BITCAST &&
21798 dyn_cast<ConstantSDNode>(InputVector.getOperand(0))) {
21799 uint64_t ExtractedElt =
21800 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
21801 uint64_t InputValue =
21802 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
21803 uint64_t Res = (InputValue >> ExtractedElt) & 1;
21804 return DAG.getConstant(Res, dl, MVT::i1);
21806 // Only operate on vectors of 4 elements, where the alternative shuffling
21807 // gets to be more expensive.
21808 if (InputVector.getValueType() != MVT::v4i32)
21811 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
21812 // single use which is a sign-extend or zero-extend, and all elements are
21814 SmallVector<SDNode *, 4> Uses;
21815 unsigned ExtractedElements = 0;
21816 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
21817 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
21818 if (UI.getUse().getResNo() != InputVector.getResNo())
21821 SDNode *Extract = *UI;
21822 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
21825 if (Extract->getValueType(0) != MVT::i32)
21827 if (!Extract->hasOneUse())
21829 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
21830 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
21832 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
21835 // Record which element was extracted.
21836 ExtractedElements |=
21837 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
21839 Uses.push_back(Extract);
21842 // If not all the elements were used, this may not be worthwhile.
21843 if (ExtractedElements != 15)
21846 // Ok, we've now decided to do the transformation.
21847 // If 64-bit shifts are legal, use the extract-shift sequence,
21848 // otherwise bounce the vector off the cache.
21849 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21852 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
21853 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
21854 auto &DL = DAG.getDataLayout();
21855 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy(DL);
21856 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
21857 DAG.getConstant(0, dl, VecIdxTy));
21858 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
21859 DAG.getConstant(1, dl, VecIdxTy));
21861 SDValue ShAmt = DAG.getConstant(
21862 32, dl, DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64, DL));
21863 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
21864 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
21865 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
21866 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
21867 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
21868 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
21870 // Store the value to a temporary stack slot.
21871 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
21872 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
21873 MachinePointerInfo(), false, false, 0);
21875 EVT ElementType = InputVector.getValueType().getVectorElementType();
21876 unsigned EltSize = ElementType.getSizeInBits() / 8;
21878 // Replace each use (extract) with a load of the appropriate element.
21879 for (unsigned i = 0; i < 4; ++i) {
21880 uint64_t Offset = EltSize * i;
21881 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
21882 SDValue OffsetVal = DAG.getConstant(Offset, dl, PtrVT);
21884 SDValue ScalarAddr =
21885 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, OffsetVal);
21887 // Load the scalar.
21888 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
21889 ScalarAddr, MachinePointerInfo(),
21890 false, false, false, 0);
21895 // Replace the extracts
21896 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
21897 UE = Uses.end(); UI != UE; ++UI) {
21898 SDNode *Extract = *UI;
21900 SDValue Idx = Extract->getOperand(1);
21901 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
21902 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
21905 // The replacement was made in place; don't return anything.
21909 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
21910 static std::pair<unsigned, bool>
21911 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
21912 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
21913 if (!VT.isVector())
21914 return std::make_pair(0, false);
21916 bool NeedSplit = false;
21917 switch (VT.getSimpleVT().SimpleTy) {
21918 default: return std::make_pair(0, false);
21921 if (!Subtarget->hasVLX())
21922 return std::make_pair(0, false);
21926 if (!Subtarget->hasBWI())
21927 return std::make_pair(0, false);
21931 if (!Subtarget->hasAVX512())
21932 return std::make_pair(0, false);
21937 if (!Subtarget->hasAVX2())
21939 if (!Subtarget->hasAVX())
21940 return std::make_pair(0, false);
21945 if (!Subtarget->hasSSE2())
21946 return std::make_pair(0, false);
21949 // SSE2 has only a small subset of the operations.
21950 bool hasUnsigned = Subtarget->hasSSE41() ||
21951 (Subtarget->hasSSE2() && VT == MVT::v16i8);
21952 bool hasSigned = Subtarget->hasSSE41() ||
21953 (Subtarget->hasSSE2() && VT == MVT::v8i16);
21955 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21958 // Check for x CC y ? x : y.
21959 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21960 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21965 Opc = hasUnsigned ? ISD::UMIN : 0; break;
21968 Opc = hasUnsigned ? ISD::UMAX : 0; break;
21971 Opc = hasSigned ? ISD::SMIN : 0; break;
21974 Opc = hasSigned ? ISD::SMAX : 0; break;
21976 // Check for x CC y ? y : x -- a min/max with reversed arms.
21977 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21978 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21983 Opc = hasUnsigned ? ISD::UMAX : 0; break;
21986 Opc = hasUnsigned ? ISD::UMIN : 0; break;
21989 Opc = hasSigned ? ISD::SMAX : 0; break;
21992 Opc = hasSigned ? ISD::SMIN : 0; break;
21996 return std::make_pair(Opc, NeedSplit);
22000 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22001 const X86Subtarget *Subtarget) {
22003 SDValue Cond = N->getOperand(0);
22004 SDValue LHS = N->getOperand(1);
22005 SDValue RHS = N->getOperand(2);
22007 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22008 SDValue CondSrc = Cond->getOperand(0);
22009 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22010 Cond = CondSrc->getOperand(0);
22013 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
22016 // A vselect where all conditions and data are constants can be optimized into
22017 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
22018 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
22019 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
22022 unsigned MaskValue = 0;
22023 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22026 MVT VT = N->getSimpleValueType(0);
22027 unsigned NumElems = VT.getVectorNumElements();
22028 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22029 for (unsigned i = 0; i < NumElems; ++i) {
22030 // Be sure we emit undef where we can.
22031 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
22032 ShuffleMask[i] = -1;
22034 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
22037 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22038 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
22040 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
22043 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
22045 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
22046 TargetLowering::DAGCombinerInfo &DCI,
22047 const X86Subtarget *Subtarget) {
22049 SDValue Cond = N->getOperand(0);
22050 // Get the LHS/RHS of the select.
22051 SDValue LHS = N->getOperand(1);
22052 SDValue RHS = N->getOperand(2);
22053 EVT VT = LHS.getValueType();
22054 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22056 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
22057 // instructions match the semantics of the common C idiom x<y?x:y but not
22058 // x<=y?x:y, because of how they handle negative zero (which can be
22059 // ignored in unsafe-math mode).
22060 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
22061 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
22062 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
22063 (Subtarget->hasSSE2() ||
22064 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
22065 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22067 unsigned Opcode = 0;
22068 // Check for x CC y ? x : y.
22069 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22070 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22074 // Converting this to a min would handle NaNs incorrectly, and swapping
22075 // the operands would cause it to handle comparisons between positive
22076 // and negative zero incorrectly.
22077 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22078 if (!DAG.getTarget().Options.UnsafeFPMath &&
22079 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22081 std::swap(LHS, RHS);
22083 Opcode = X86ISD::FMIN;
22086 // Converting this to a min would handle comparisons between positive
22087 // and negative zero incorrectly.
22088 if (!DAG.getTarget().Options.UnsafeFPMath &&
22089 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22091 Opcode = X86ISD::FMIN;
22094 // Converting this to a min would handle both negative zeros and NaNs
22095 // incorrectly, but we can swap the operands to fix both.
22096 std::swap(LHS, RHS);
22100 Opcode = X86ISD::FMIN;
22104 // Converting this to a max would handle comparisons between positive
22105 // and negative zero incorrectly.
22106 if (!DAG.getTarget().Options.UnsafeFPMath &&
22107 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22109 Opcode = X86ISD::FMAX;
22112 // Converting this to a max would handle NaNs incorrectly, and swapping
22113 // the operands would cause it to handle comparisons between positive
22114 // and negative zero incorrectly.
22115 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22116 if (!DAG.getTarget().Options.UnsafeFPMath &&
22117 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22119 std::swap(LHS, RHS);
22121 Opcode = X86ISD::FMAX;
22124 // Converting this to a max would handle both negative zeros and NaNs
22125 // incorrectly, but we can swap the operands to fix both.
22126 std::swap(LHS, RHS);
22130 Opcode = X86ISD::FMAX;
22133 // Check for x CC y ? y : x -- a min/max with reversed arms.
22134 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22135 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22139 // Converting this to a min would handle comparisons between positive
22140 // and negative zero incorrectly, and swapping the operands would
22141 // cause it to handle NaNs incorrectly.
22142 if (!DAG.getTarget().Options.UnsafeFPMath &&
22143 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
22144 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22146 std::swap(LHS, RHS);
22148 Opcode = X86ISD::FMIN;
22151 // Converting this to a min would handle NaNs incorrectly.
22152 if (!DAG.getTarget().Options.UnsafeFPMath &&
22153 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
22155 Opcode = X86ISD::FMIN;
22158 // Converting this to a min would handle both negative zeros and NaNs
22159 // incorrectly, but we can swap the operands to fix both.
22160 std::swap(LHS, RHS);
22164 Opcode = X86ISD::FMIN;
22168 // Converting this to a max would handle NaNs incorrectly.
22169 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22171 Opcode = X86ISD::FMAX;
22174 // Converting this to a max would handle comparisons between positive
22175 // and negative zero incorrectly, and swapping the operands would
22176 // cause it to handle NaNs incorrectly.
22177 if (!DAG.getTarget().Options.UnsafeFPMath &&
22178 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
22179 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22181 std::swap(LHS, RHS);
22183 Opcode = X86ISD::FMAX;
22186 // Converting this to a max would handle both negative zeros and NaNs
22187 // incorrectly, but we can swap the operands to fix both.
22188 std::swap(LHS, RHS);
22192 Opcode = X86ISD::FMAX;
22198 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
22201 EVT CondVT = Cond.getValueType();
22202 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
22203 CondVT.getVectorElementType() == MVT::i1) {
22204 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
22205 // lowering on KNL. In this case we convert it to
22206 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
22207 // The same situation for all 128 and 256-bit vectors of i8 and i16.
22208 // Since SKX these selects have a proper lowering.
22209 EVT OpVT = LHS.getValueType();
22210 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
22211 (OpVT.getVectorElementType() == MVT::i8 ||
22212 OpVT.getVectorElementType() == MVT::i16) &&
22213 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
22214 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
22215 DCI.AddToWorklist(Cond.getNode());
22216 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
22219 // If this is a select between two integer constants, try to do some
22221 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
22222 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
22223 // Don't do this for crazy integer types.
22224 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
22225 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
22226 // so that TrueC (the true value) is larger than FalseC.
22227 bool NeedsCondInvert = false;
22229 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
22230 // Efficiently invertible.
22231 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
22232 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
22233 isa<ConstantSDNode>(Cond.getOperand(1))))) {
22234 NeedsCondInvert = true;
22235 std::swap(TrueC, FalseC);
22238 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
22239 if (FalseC->getAPIntValue() == 0 &&
22240 TrueC->getAPIntValue().isPowerOf2()) {
22241 if (NeedsCondInvert) // Invert the condition if needed.
22242 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22243 DAG.getConstant(1, DL, Cond.getValueType()));
22245 // Zero extend the condition if needed.
22246 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
22248 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22249 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
22250 DAG.getConstant(ShAmt, DL, MVT::i8));
22253 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
22254 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22255 if (NeedsCondInvert) // Invert the condition if needed.
22256 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22257 DAG.getConstant(1, DL, Cond.getValueType()));
22259 // Zero extend the condition if needed.
22260 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22261 FalseC->getValueType(0), Cond);
22262 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22263 SDValue(FalseC, 0));
22266 // Optimize cases that will turn into an LEA instruction. This requires
22267 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22268 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22269 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22270 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22272 bool isFastMultiplier = false;
22274 switch ((unsigned char)Diff) {
22276 case 1: // result = add base, cond
22277 case 2: // result = lea base( , cond*2)
22278 case 3: // result = lea base(cond, cond*2)
22279 case 4: // result = lea base( , cond*4)
22280 case 5: // result = lea base(cond, cond*4)
22281 case 8: // result = lea base( , cond*8)
22282 case 9: // result = lea base(cond, cond*8)
22283 isFastMultiplier = true;
22288 if (isFastMultiplier) {
22289 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22290 if (NeedsCondInvert) // Invert the condition if needed.
22291 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22292 DAG.getConstant(1, DL, Cond.getValueType()));
22294 // Zero extend the condition if needed.
22295 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22297 // Scale the condition by the difference.
22299 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22300 DAG.getConstant(Diff, DL,
22301 Cond.getValueType()));
22303 // Add the base if non-zero.
22304 if (FalseC->getAPIntValue() != 0)
22305 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22306 SDValue(FalseC, 0));
22313 // Canonicalize max and min:
22314 // (x > y) ? x : y -> (x >= y) ? x : y
22315 // (x < y) ? x : y -> (x <= y) ? x : y
22316 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
22317 // the need for an extra compare
22318 // against zero. e.g.
22319 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
22321 // testl %edi, %edi
22323 // cmovgl %edi, %eax
22327 // cmovsl %eax, %edi
22328 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
22329 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22330 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22331 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22336 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
22337 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
22338 Cond.getOperand(0), Cond.getOperand(1), NewCC);
22339 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
22344 // Early exit check
22345 if (!TLI.isTypeLegal(VT))
22348 // Match VSELECTs into subs with unsigned saturation.
22349 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
22350 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
22351 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
22352 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
22353 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22355 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
22356 // left side invert the predicate to simplify logic below.
22358 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
22360 CC = ISD::getSetCCInverse(CC, true);
22361 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
22365 if (Other.getNode() && Other->getNumOperands() == 2 &&
22366 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
22367 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
22368 SDValue CondRHS = Cond->getOperand(1);
22370 // Look for a general sub with unsigned saturation first.
22371 // x >= y ? x-y : 0 --> subus x, y
22372 // x > y ? x-y : 0 --> subus x, y
22373 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
22374 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
22375 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
22377 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
22378 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
22379 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
22380 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
22381 // If the RHS is a constant we have to reverse the const
22382 // canonicalization.
22383 // x > C-1 ? x+-C : 0 --> subus x, C
22384 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
22385 CondRHSConst->getAPIntValue() ==
22386 (-OpRHSConst->getAPIntValue() - 1))
22387 return DAG.getNode(
22388 X86ISD::SUBUS, DL, VT, OpLHS,
22389 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
22391 // Another special case: If C was a sign bit, the sub has been
22392 // canonicalized into a xor.
22393 // FIXME: Would it be better to use computeKnownBits to determine
22394 // whether it's safe to decanonicalize the xor?
22395 // x s< 0 ? x^C : 0 --> subus x, C
22396 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
22397 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
22398 OpRHSConst->getAPIntValue().isSignBit())
22399 // Note that we have to rebuild the RHS constant here to ensure we
22400 // don't rely on particular values of undef lanes.
22401 return DAG.getNode(
22402 X86ISD::SUBUS, DL, VT, OpLHS,
22403 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
22408 // Try to match a min/max vector operation.
22409 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
22410 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
22411 unsigned Opc = ret.first;
22412 bool NeedSplit = ret.second;
22414 if (Opc && NeedSplit) {
22415 unsigned NumElems = VT.getVectorNumElements();
22416 // Extract the LHS vectors
22417 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
22418 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
22420 // Extract the RHS vectors
22421 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
22422 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
22424 // Create min/max for each subvector
22425 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
22426 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
22428 // Merge the result
22429 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
22431 return DAG.getNode(Opc, DL, VT, LHS, RHS);
22434 // Simplify vector selection if condition value type matches vselect
22436 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
22437 assert(Cond.getValueType().isVector() &&
22438 "vector select expects a vector selector!");
22440 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
22441 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
22443 // Try invert the condition if true value is not all 1s and false value
22445 if (!TValIsAllOnes && !FValIsAllZeros &&
22446 // Check if the selector will be produced by CMPP*/PCMP*
22447 Cond.getOpcode() == ISD::SETCC &&
22448 // Check if SETCC has already been promoted
22449 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT) ==
22451 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
22452 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
22454 if (TValIsAllZeros || FValIsAllOnes) {
22455 SDValue CC = Cond.getOperand(2);
22456 ISD::CondCode NewCC =
22457 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
22458 Cond.getOperand(0).getValueType().isInteger());
22459 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
22460 std::swap(LHS, RHS);
22461 TValIsAllOnes = FValIsAllOnes;
22462 FValIsAllZeros = TValIsAllZeros;
22466 if (TValIsAllOnes || FValIsAllZeros) {
22469 if (TValIsAllOnes && FValIsAllZeros)
22471 else if (TValIsAllOnes)
22473 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
22474 else if (FValIsAllZeros)
22475 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
22476 DAG.getBitcast(CondVT, LHS));
22478 return DAG.getBitcast(VT, Ret);
22482 // We should generate an X86ISD::BLENDI from a vselect if its argument
22483 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
22484 // constants. This specific pattern gets generated when we split a
22485 // selector for a 512 bit vector in a machine without AVX512 (but with
22486 // 256-bit vectors), during legalization:
22488 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
22490 // Iff we find this pattern and the build_vectors are built from
22491 // constants, we translate the vselect into a shuffle_vector that we
22492 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
22493 if ((N->getOpcode() == ISD::VSELECT ||
22494 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
22495 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
22496 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
22497 if (Shuffle.getNode())
22501 // If this is a *dynamic* select (non-constant condition) and we can match
22502 // this node with one of the variable blend instructions, restructure the
22503 // condition so that the blends can use the high bit of each element and use
22504 // SimplifyDemandedBits to simplify the condition operand.
22505 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
22506 !DCI.isBeforeLegalize() &&
22507 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
22508 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
22510 // Don't optimize vector selects that map to mask-registers.
22514 // We can only handle the cases where VSELECT is directly legal on the
22515 // subtarget. We custom lower VSELECT nodes with constant conditions and
22516 // this makes it hard to see whether a dynamic VSELECT will correctly
22517 // lower, so we both check the operation's status and explicitly handle the
22518 // cases where a *dynamic* blend will fail even though a constant-condition
22519 // blend could be custom lowered.
22520 // FIXME: We should find a better way to handle this class of problems.
22521 // Potentially, we should combine constant-condition vselect nodes
22522 // pre-legalization into shuffles and not mark as many types as custom
22524 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
22526 // FIXME: We don't support i16-element blends currently. We could and
22527 // should support them by making *all* the bits in the condition be set
22528 // rather than just the high bit and using an i8-element blend.
22529 if (VT.getScalarType() == MVT::i16)
22531 // Dynamic blending was only available from SSE4.1 onward.
22532 if (VT.getSizeInBits() == 128 && !Subtarget->hasSSE41())
22534 // Byte blends are only available in AVX2
22535 if (VT.getSizeInBits() == 256 && VT.getScalarType() == MVT::i8 &&
22536 !Subtarget->hasAVX2())
22539 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
22540 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
22542 APInt KnownZero, KnownOne;
22543 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
22544 DCI.isBeforeLegalizeOps());
22545 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
22546 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
22548 // If we changed the computation somewhere in the DAG, this change
22549 // will affect all users of Cond.
22550 // Make sure it is fine and update all the nodes so that we do not
22551 // use the generic VSELECT anymore. Otherwise, we may perform
22552 // wrong optimizations as we messed up with the actual expectation
22553 // for the vector boolean values.
22554 if (Cond != TLO.Old) {
22555 // Check all uses of that condition operand to check whether it will be
22556 // consumed by non-BLEND instructions, which may depend on all bits are
22558 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
22560 if (I->getOpcode() != ISD::VSELECT)
22561 // TODO: Add other opcodes eventually lowered into BLEND.
22564 // Update all the users of the condition, before committing the change,
22565 // so that the VSELECT optimizations that expect the correct vector
22566 // boolean value will not be triggered.
22567 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
22569 DAG.ReplaceAllUsesOfValueWith(
22571 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
22572 Cond, I->getOperand(1), I->getOperand(2)));
22573 DCI.CommitTargetLoweringOpt(TLO);
22576 // At this point, only Cond is changed. Change the condition
22577 // just for N to keep the opportunity to optimize all other
22578 // users their own way.
22579 DAG.ReplaceAllUsesOfValueWith(
22581 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
22582 TLO.New, N->getOperand(1), N->getOperand(2)));
22590 // Check whether a boolean test is testing a boolean value generated by
22591 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
22594 // Simplify the following patterns:
22595 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
22596 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
22597 // to (Op EFLAGS Cond)
22599 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
22600 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
22601 // to (Op EFLAGS !Cond)
22603 // where Op could be BRCOND or CMOV.
22605 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
22606 // Quit if not CMP and SUB with its value result used.
22607 if (Cmp.getOpcode() != X86ISD::CMP &&
22608 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
22611 // Quit if not used as a boolean value.
22612 if (CC != X86::COND_E && CC != X86::COND_NE)
22615 // Check CMP operands. One of them should be 0 or 1 and the other should be
22616 // an SetCC or extended from it.
22617 SDValue Op1 = Cmp.getOperand(0);
22618 SDValue Op2 = Cmp.getOperand(1);
22621 const ConstantSDNode* C = nullptr;
22622 bool needOppositeCond = (CC == X86::COND_E);
22623 bool checkAgainstTrue = false; // Is it a comparison against 1?
22625 if ((C = dyn_cast<ConstantSDNode>(Op1)))
22627 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
22629 else // Quit if all operands are not constants.
22632 if (C->getZExtValue() == 1) {
22633 needOppositeCond = !needOppositeCond;
22634 checkAgainstTrue = true;
22635 } else if (C->getZExtValue() != 0)
22636 // Quit if the constant is neither 0 or 1.
22639 bool truncatedToBoolWithAnd = false;
22640 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
22641 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
22642 SetCC.getOpcode() == ISD::TRUNCATE ||
22643 SetCC.getOpcode() == ISD::AND) {
22644 if (SetCC.getOpcode() == ISD::AND) {
22646 ConstantSDNode *CS;
22647 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
22648 CS->getZExtValue() == 1)
22650 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
22651 CS->getZExtValue() == 1)
22655 SetCC = SetCC.getOperand(OpIdx);
22656 truncatedToBoolWithAnd = true;
22658 SetCC = SetCC.getOperand(0);
22661 switch (SetCC.getOpcode()) {
22662 case X86ISD::SETCC_CARRY:
22663 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
22664 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
22665 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
22666 // truncated to i1 using 'and'.
22667 if (checkAgainstTrue && !truncatedToBoolWithAnd)
22669 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
22670 "Invalid use of SETCC_CARRY!");
22672 case X86ISD::SETCC:
22673 // Set the condition code or opposite one if necessary.
22674 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
22675 if (needOppositeCond)
22676 CC = X86::GetOppositeBranchCondition(CC);
22677 return SetCC.getOperand(1);
22678 case X86ISD::CMOV: {
22679 // Check whether false/true value has canonical one, i.e. 0 or 1.
22680 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
22681 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
22682 // Quit if true value is not a constant.
22685 // Quit if false value is not a constant.
22687 SDValue Op = SetCC.getOperand(0);
22688 // Skip 'zext' or 'trunc' node.
22689 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
22690 Op.getOpcode() == ISD::TRUNCATE)
22691 Op = Op.getOperand(0);
22692 // A special case for rdrand/rdseed, where 0 is set if false cond is
22694 if ((Op.getOpcode() != X86ISD::RDRAND &&
22695 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
22698 // Quit if false value is not the constant 0 or 1.
22699 bool FValIsFalse = true;
22700 if (FVal && FVal->getZExtValue() != 0) {
22701 if (FVal->getZExtValue() != 1)
22703 // If FVal is 1, opposite cond is needed.
22704 needOppositeCond = !needOppositeCond;
22705 FValIsFalse = false;
22707 // Quit if TVal is not the constant opposite of FVal.
22708 if (FValIsFalse && TVal->getZExtValue() != 1)
22710 if (!FValIsFalse && TVal->getZExtValue() != 0)
22712 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
22713 if (needOppositeCond)
22714 CC = X86::GetOppositeBranchCondition(CC);
22715 return SetCC.getOperand(3);
22722 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
22724 /// (X86or (X86setcc) (X86setcc))
22725 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
22726 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
22727 X86::CondCode &CC1, SDValue &Flags,
22729 if (Cond->getOpcode() == X86ISD::CMP) {
22730 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
22731 if (!CondOp1C || !CondOp1C->isNullValue())
22734 Cond = Cond->getOperand(0);
22739 SDValue SetCC0, SetCC1;
22740 switch (Cond->getOpcode()) {
22741 default: return false;
22748 SetCC0 = Cond->getOperand(0);
22749 SetCC1 = Cond->getOperand(1);
22753 // Make sure we have SETCC nodes, using the same flags value.
22754 if (SetCC0.getOpcode() != X86ISD::SETCC ||
22755 SetCC1.getOpcode() != X86ISD::SETCC ||
22756 SetCC0->getOperand(1) != SetCC1->getOperand(1))
22759 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
22760 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
22761 Flags = SetCC0->getOperand(1);
22765 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
22766 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
22767 TargetLowering::DAGCombinerInfo &DCI,
22768 const X86Subtarget *Subtarget) {
22771 // If the flag operand isn't dead, don't touch this CMOV.
22772 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
22775 SDValue FalseOp = N->getOperand(0);
22776 SDValue TrueOp = N->getOperand(1);
22777 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
22778 SDValue Cond = N->getOperand(3);
22780 if (CC == X86::COND_E || CC == X86::COND_NE) {
22781 switch (Cond.getOpcode()) {
22785 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
22786 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
22787 return (CC == X86::COND_E) ? FalseOp : TrueOp;
22793 Flags = checkBoolTestSetCCCombine(Cond, CC);
22794 if (Flags.getNode() &&
22795 // Extra check as FCMOV only supports a subset of X86 cond.
22796 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
22797 SDValue Ops[] = { FalseOp, TrueOp,
22798 DAG.getConstant(CC, DL, MVT::i8), Flags };
22799 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22802 // If this is a select between two integer constants, try to do some
22803 // optimizations. Note that the operands are ordered the opposite of SELECT
22805 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
22806 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
22807 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
22808 // larger than FalseC (the false value).
22809 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
22810 CC = X86::GetOppositeBranchCondition(CC);
22811 std::swap(TrueC, FalseC);
22812 std::swap(TrueOp, FalseOp);
22815 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
22816 // This is efficient for any integer data type (including i8/i16) and
22818 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
22819 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22820 DAG.getConstant(CC, DL, MVT::i8), Cond);
22822 // Zero extend the condition if needed.
22823 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
22825 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22826 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
22827 DAG.getConstant(ShAmt, DL, MVT::i8));
22828 if (N->getNumValues() == 2) // Dead flag value?
22829 return DCI.CombineTo(N, Cond, SDValue());
22833 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
22834 // for any integer data type, including i8/i16.
22835 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22836 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22837 DAG.getConstant(CC, DL, MVT::i8), Cond);
22839 // Zero extend the condition if needed.
22840 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22841 FalseC->getValueType(0), Cond);
22842 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22843 SDValue(FalseC, 0));
22845 if (N->getNumValues() == 2) // Dead flag value?
22846 return DCI.CombineTo(N, Cond, SDValue());
22850 // Optimize cases that will turn into an LEA instruction. This requires
22851 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22852 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22853 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22854 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22856 bool isFastMultiplier = false;
22858 switch ((unsigned char)Diff) {
22860 case 1: // result = add base, cond
22861 case 2: // result = lea base( , cond*2)
22862 case 3: // result = lea base(cond, cond*2)
22863 case 4: // result = lea base( , cond*4)
22864 case 5: // result = lea base(cond, cond*4)
22865 case 8: // result = lea base( , cond*8)
22866 case 9: // result = lea base(cond, cond*8)
22867 isFastMultiplier = true;
22872 if (isFastMultiplier) {
22873 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22874 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22875 DAG.getConstant(CC, DL, MVT::i8), Cond);
22876 // Zero extend the condition if needed.
22877 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22879 // Scale the condition by the difference.
22881 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22882 DAG.getConstant(Diff, DL, Cond.getValueType()));
22884 // Add the base if non-zero.
22885 if (FalseC->getAPIntValue() != 0)
22886 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22887 SDValue(FalseC, 0));
22888 if (N->getNumValues() == 2) // Dead flag value?
22889 return DCI.CombineTo(N, Cond, SDValue());
22896 // Handle these cases:
22897 // (select (x != c), e, c) -> select (x != c), e, x),
22898 // (select (x == c), c, e) -> select (x == c), x, e)
22899 // where the c is an integer constant, and the "select" is the combination
22900 // of CMOV and CMP.
22902 // The rationale for this change is that the conditional-move from a constant
22903 // needs two instructions, however, conditional-move from a register needs
22904 // only one instruction.
22906 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
22907 // some instruction-combining opportunities. This opt needs to be
22908 // postponed as late as possible.
22910 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
22911 // the DCI.xxxx conditions are provided to postpone the optimization as
22912 // late as possible.
22914 ConstantSDNode *CmpAgainst = nullptr;
22915 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
22916 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
22917 !isa<ConstantSDNode>(Cond.getOperand(0))) {
22919 if (CC == X86::COND_NE &&
22920 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
22921 CC = X86::GetOppositeBranchCondition(CC);
22922 std::swap(TrueOp, FalseOp);
22925 if (CC == X86::COND_E &&
22926 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
22927 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
22928 DAG.getConstant(CC, DL, MVT::i8), Cond };
22929 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
22934 // Fold and/or of setcc's to double CMOV:
22935 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
22936 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
22938 // This combine lets us generate:
22939 // cmovcc1 (jcc1 if we don't have CMOV)
22945 // cmovne (jne if we don't have CMOV)
22946 // When we can't use the CMOV instruction, it might increase branch
22948 // When we can use CMOV, or when there is no mispredict, this improves
22949 // throughput and reduces register pressure.
22951 if (CC == X86::COND_NE) {
22953 X86::CondCode CC0, CC1;
22955 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
22957 std::swap(FalseOp, TrueOp);
22958 CC0 = X86::GetOppositeBranchCondition(CC0);
22959 CC1 = X86::GetOppositeBranchCondition(CC1);
22962 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
22964 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
22965 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
22966 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22967 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
22975 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
22976 const X86Subtarget *Subtarget) {
22977 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
22979 default: return SDValue();
22980 // SSE/AVX/AVX2 blend intrinsics.
22981 case Intrinsic::x86_avx2_pblendvb:
22982 // Don't try to simplify this intrinsic if we don't have AVX2.
22983 if (!Subtarget->hasAVX2())
22986 case Intrinsic::x86_avx_blendv_pd_256:
22987 case Intrinsic::x86_avx_blendv_ps_256:
22988 // Don't try to simplify this intrinsic if we don't have AVX.
22989 if (!Subtarget->hasAVX())
22992 case Intrinsic::x86_sse41_blendvps:
22993 case Intrinsic::x86_sse41_blendvpd:
22994 case Intrinsic::x86_sse41_pblendvb: {
22995 SDValue Op0 = N->getOperand(1);
22996 SDValue Op1 = N->getOperand(2);
22997 SDValue Mask = N->getOperand(3);
22999 // Don't try to simplify this intrinsic if we don't have SSE4.1.
23000 if (!Subtarget->hasSSE41())
23003 // fold (blend A, A, Mask) -> A
23006 // fold (blend A, B, allZeros) -> A
23007 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
23009 // fold (blend A, B, allOnes) -> B
23010 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
23013 // Simplify the case where the mask is a constant i32 value.
23014 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
23015 if (C->isNullValue())
23017 if (C->isAllOnesValue())
23024 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
23025 case Intrinsic::x86_sse2_psrai_w:
23026 case Intrinsic::x86_sse2_psrai_d:
23027 case Intrinsic::x86_avx2_psrai_w:
23028 case Intrinsic::x86_avx2_psrai_d:
23029 case Intrinsic::x86_sse2_psra_w:
23030 case Intrinsic::x86_sse2_psra_d:
23031 case Intrinsic::x86_avx2_psra_w:
23032 case Intrinsic::x86_avx2_psra_d: {
23033 SDValue Op0 = N->getOperand(1);
23034 SDValue Op1 = N->getOperand(2);
23035 EVT VT = Op0.getValueType();
23036 assert(VT.isVector() && "Expected a vector type!");
23038 if (isa<BuildVectorSDNode>(Op1))
23039 Op1 = Op1.getOperand(0);
23041 if (!isa<ConstantSDNode>(Op1))
23044 EVT SVT = VT.getVectorElementType();
23045 unsigned SVTBits = SVT.getSizeInBits();
23047 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
23048 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
23049 uint64_t ShAmt = C.getZExtValue();
23051 // Don't try to convert this shift into a ISD::SRA if the shift
23052 // count is bigger than or equal to the element size.
23053 if (ShAmt >= SVTBits)
23056 // Trivial case: if the shift count is zero, then fold this
23057 // into the first operand.
23061 // Replace this packed shift intrinsic with a target independent
23064 SDValue Splat = DAG.getConstant(C, DL, VT);
23065 return DAG.getNode(ISD::SRA, DL, VT, Op0, Splat);
23070 /// PerformMulCombine - Optimize a single multiply with constant into two
23071 /// in order to implement it with two cheaper instructions, e.g.
23072 /// LEA + SHL, LEA + LEA.
23073 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23074 TargetLowering::DAGCombinerInfo &DCI) {
23075 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23078 EVT VT = N->getValueType(0);
23079 if (VT != MVT::i64 && VT != MVT::i32)
23082 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23085 uint64_t MulAmt = C->getZExtValue();
23086 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23089 uint64_t MulAmt1 = 0;
23090 uint64_t MulAmt2 = 0;
23091 if ((MulAmt % 9) == 0) {
23093 MulAmt2 = MulAmt / 9;
23094 } else if ((MulAmt % 5) == 0) {
23096 MulAmt2 = MulAmt / 5;
23097 } else if ((MulAmt % 3) == 0) {
23099 MulAmt2 = MulAmt / 3;
23102 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23105 if (isPowerOf2_64(MulAmt2) &&
23106 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23107 // If second multiplifer is pow2, issue it first. We want the multiply by
23108 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23110 std::swap(MulAmt1, MulAmt2);
23113 if (isPowerOf2_64(MulAmt1))
23114 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23115 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
23117 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23118 DAG.getConstant(MulAmt1, DL, VT));
23120 if (isPowerOf2_64(MulAmt2))
23121 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23122 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
23124 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23125 DAG.getConstant(MulAmt2, DL, VT));
23127 // Do not add new nodes to DAG combiner worklist.
23128 DCI.CombineTo(N, NewMul, false);
23133 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23134 SDValue N0 = N->getOperand(0);
23135 SDValue N1 = N->getOperand(1);
23136 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23137 EVT VT = N0.getValueType();
23139 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23140 // since the result of setcc_c is all zero's or all ones.
23141 if (VT.isInteger() && !VT.isVector() &&
23142 N1C && N0.getOpcode() == ISD::AND &&
23143 N0.getOperand(1).getOpcode() == ISD::Constant) {
23144 SDValue N00 = N0.getOperand(0);
23145 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
23146 ((N00.getOpcode() == ISD::ANY_EXTEND ||
23147 N00.getOpcode() == ISD::ZERO_EXTEND) &&
23148 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
23149 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
23150 APInt ShAmt = N1C->getAPIntValue();
23151 Mask = Mask.shl(ShAmt);
23154 return DAG.getNode(ISD::AND, DL, VT,
23155 N00, DAG.getConstant(Mask, DL, VT));
23160 // Hardware support for vector shifts is sparse which makes us scalarize the
23161 // vector operations in many cases. Also, on sandybridge ADD is faster than
23163 // (shl V, 1) -> add V,V
23164 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23165 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23166 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23167 // We shift all of the values by one. In many cases we do not have
23168 // hardware support for this operation. This is better expressed as an ADD
23170 if (N1SplatC->getZExtValue() == 1)
23171 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
23177 /// \brief Returns a vector of 0s if the node in input is a vector logical
23178 /// shift by a constant amount which is known to be bigger than or equal
23179 /// to the vector element size in bits.
23180 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
23181 const X86Subtarget *Subtarget) {
23182 EVT VT = N->getValueType(0);
23184 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
23185 (!Subtarget->hasInt256() ||
23186 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
23189 SDValue Amt = N->getOperand(1);
23191 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
23192 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
23193 APInt ShiftAmt = AmtSplat->getAPIntValue();
23194 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
23196 // SSE2/AVX2 logical shifts always return a vector of 0s
23197 // if the shift amount is bigger than or equal to
23198 // the element size. The constant shift amount will be
23199 // encoded as a 8-bit immediate.
23200 if (ShiftAmt.trunc(8).uge(MaxAmount))
23201 return getZeroVector(VT, Subtarget, DAG, DL);
23207 /// PerformShiftCombine - Combine shifts.
23208 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
23209 TargetLowering::DAGCombinerInfo &DCI,
23210 const X86Subtarget *Subtarget) {
23211 if (N->getOpcode() == ISD::SHL)
23212 if (SDValue V = PerformSHLCombine(N, DAG))
23215 // Try to fold this logical shift into a zero vector.
23216 if (N->getOpcode() != ISD::SRA)
23217 if (SDValue V = performShiftToAllZeros(N, DAG, Subtarget))
23223 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
23224 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
23225 // and friends. Likewise for OR -> CMPNEQSS.
23226 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
23227 TargetLowering::DAGCombinerInfo &DCI,
23228 const X86Subtarget *Subtarget) {
23231 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
23232 // we're requiring SSE2 for both.
23233 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
23234 SDValue N0 = N->getOperand(0);
23235 SDValue N1 = N->getOperand(1);
23236 SDValue CMP0 = N0->getOperand(1);
23237 SDValue CMP1 = N1->getOperand(1);
23240 // The SETCCs should both refer to the same CMP.
23241 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
23244 SDValue CMP00 = CMP0->getOperand(0);
23245 SDValue CMP01 = CMP0->getOperand(1);
23246 EVT VT = CMP00.getValueType();
23248 if (VT == MVT::f32 || VT == MVT::f64) {
23249 bool ExpectingFlags = false;
23250 // Check for any users that want flags:
23251 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
23252 !ExpectingFlags && UI != UE; ++UI)
23253 switch (UI->getOpcode()) {
23258 ExpectingFlags = true;
23260 case ISD::CopyToReg:
23261 case ISD::SIGN_EXTEND:
23262 case ISD::ZERO_EXTEND:
23263 case ISD::ANY_EXTEND:
23267 if (!ExpectingFlags) {
23268 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
23269 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
23271 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
23272 X86::CondCode tmp = cc0;
23277 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
23278 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
23279 // FIXME: need symbolic constants for these magic numbers.
23280 // See X86ATTInstPrinter.cpp:printSSECC().
23281 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
23282 if (Subtarget->hasAVX512()) {
23283 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
23285 DAG.getConstant(x86cc, DL, MVT::i8));
23286 if (N->getValueType(0) != MVT::i1)
23287 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
23291 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
23292 CMP00.getValueType(), CMP00, CMP01,
23293 DAG.getConstant(x86cc, DL,
23296 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
23297 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
23299 if (is64BitFP && !Subtarget->is64Bit()) {
23300 // On a 32-bit target, we cannot bitcast the 64-bit float to a
23301 // 64-bit integer, since that's not a legal type. Since
23302 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
23303 // bits, but can do this little dance to extract the lowest 32 bits
23304 // and work with those going forward.
23305 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
23307 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
23308 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
23309 Vector32, DAG.getIntPtrConstant(0, DL));
23313 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
23314 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
23315 DAG.getConstant(1, DL, IntVT));
23316 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
23318 return OneBitOfTruth;
23326 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
23327 /// so it can be folded inside ANDNP.
23328 static bool CanFoldXORWithAllOnes(const SDNode *N) {
23329 EVT VT = N->getValueType(0);
23331 // Match direct AllOnes for 128 and 256-bit vectors
23332 if (ISD::isBuildVectorAllOnes(N))
23335 // Look through a bit convert.
23336 if (N->getOpcode() == ISD::BITCAST)
23337 N = N->getOperand(0).getNode();
23339 // Sometimes the operand may come from a insert_subvector building a 256-bit
23341 if (VT.is256BitVector() &&
23342 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
23343 SDValue V1 = N->getOperand(0);
23344 SDValue V2 = N->getOperand(1);
23346 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
23347 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
23348 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
23349 ISD::isBuildVectorAllOnes(V2.getNode()))
23356 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
23357 // register. In most cases we actually compare or select YMM-sized registers
23358 // and mixing the two types creates horrible code. This method optimizes
23359 // some of the transition sequences.
23360 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
23361 TargetLowering::DAGCombinerInfo &DCI,
23362 const X86Subtarget *Subtarget) {
23363 EVT VT = N->getValueType(0);
23364 if (!VT.is256BitVector())
23367 assert((N->getOpcode() == ISD::ANY_EXTEND ||
23368 N->getOpcode() == ISD::ZERO_EXTEND ||
23369 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
23371 SDValue Narrow = N->getOperand(0);
23372 EVT NarrowVT = Narrow->getValueType(0);
23373 if (!NarrowVT.is128BitVector())
23376 if (Narrow->getOpcode() != ISD::XOR &&
23377 Narrow->getOpcode() != ISD::AND &&
23378 Narrow->getOpcode() != ISD::OR)
23381 SDValue N0 = Narrow->getOperand(0);
23382 SDValue N1 = Narrow->getOperand(1);
23385 // The Left side has to be a trunc.
23386 if (N0.getOpcode() != ISD::TRUNCATE)
23389 // The type of the truncated inputs.
23390 EVT WideVT = N0->getOperand(0)->getValueType(0);
23394 // The right side has to be a 'trunc' or a constant vector.
23395 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
23396 ConstantSDNode *RHSConstSplat = nullptr;
23397 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
23398 RHSConstSplat = RHSBV->getConstantSplatNode();
23399 if (!RHSTrunc && !RHSConstSplat)
23402 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23404 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
23407 // Set N0 and N1 to hold the inputs to the new wide operation.
23408 N0 = N0->getOperand(0);
23409 if (RHSConstSplat) {
23410 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
23411 SDValue(RHSConstSplat, 0));
23412 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
23413 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
23414 } else if (RHSTrunc) {
23415 N1 = N1->getOperand(0);
23418 // Generate the wide operation.
23419 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
23420 unsigned Opcode = N->getOpcode();
23422 case ISD::ANY_EXTEND:
23424 case ISD::ZERO_EXTEND: {
23425 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
23426 APInt Mask = APInt::getAllOnesValue(InBits);
23427 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
23428 return DAG.getNode(ISD::AND, DL, VT,
23429 Op, DAG.getConstant(Mask, DL, VT));
23431 case ISD::SIGN_EXTEND:
23432 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
23433 Op, DAG.getValueType(NarrowVT));
23435 llvm_unreachable("Unexpected opcode");
23439 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
23440 TargetLowering::DAGCombinerInfo &DCI,
23441 const X86Subtarget *Subtarget) {
23442 SDValue N0 = N->getOperand(0);
23443 SDValue N1 = N->getOperand(1);
23446 // A vector zext_in_reg may be represented as a shuffle,
23447 // feeding into a bitcast (this represents anyext) feeding into
23448 // an and with a mask.
23449 // We'd like to try to combine that into a shuffle with zero
23450 // plus a bitcast, removing the and.
23451 if (N0.getOpcode() != ISD::BITCAST ||
23452 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
23455 // The other side of the AND should be a splat of 2^C, where C
23456 // is the number of bits in the source type.
23457 if (N1.getOpcode() == ISD::BITCAST)
23458 N1 = N1.getOperand(0);
23459 if (N1.getOpcode() != ISD::BUILD_VECTOR)
23461 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
23463 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
23464 EVT SrcType = Shuffle->getValueType(0);
23466 // We expect a single-source shuffle
23467 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
23470 unsigned SrcSize = SrcType.getScalarSizeInBits();
23472 APInt SplatValue, SplatUndef;
23473 unsigned SplatBitSize;
23475 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
23476 SplatBitSize, HasAnyUndefs))
23479 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
23480 // Make sure the splat matches the mask we expect
23481 if (SplatBitSize > ResSize ||
23482 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
23485 // Make sure the input and output size make sense
23486 if (SrcSize >= ResSize || ResSize % SrcSize)
23489 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
23490 // The number of u's between each two values depends on the ratio between
23491 // the source and dest type.
23492 unsigned ZextRatio = ResSize / SrcSize;
23493 bool IsZext = true;
23494 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
23495 if (i % ZextRatio) {
23496 if (Shuffle->getMaskElt(i) > 0) {
23502 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
23503 // Expected element number
23513 // Ok, perform the transformation - replace the shuffle with
23514 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
23515 // (instead of undef) where the k elements come from the zero vector.
23516 SmallVector<int, 8> Mask;
23517 unsigned NumElems = SrcType.getVectorNumElements();
23518 for (unsigned i = 0; i < NumElems; ++i)
23520 Mask.push_back(NumElems);
23522 Mask.push_back(i / ZextRatio);
23524 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
23525 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
23526 return DAG.getBitcast(N0.getValueType(), NewShuffle);
23529 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
23530 TargetLowering::DAGCombinerInfo &DCI,
23531 const X86Subtarget *Subtarget) {
23532 if (DCI.isBeforeLegalizeOps())
23535 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
23538 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
23541 EVT VT = N->getValueType(0);
23542 SDValue N0 = N->getOperand(0);
23543 SDValue N1 = N->getOperand(1);
23546 // Create BEXTR instructions
23547 // BEXTR is ((X >> imm) & (2**size-1))
23548 if (VT == MVT::i32 || VT == MVT::i64) {
23549 // Check for BEXTR.
23550 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
23551 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
23552 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
23553 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23554 if (MaskNode && ShiftNode) {
23555 uint64_t Mask = MaskNode->getZExtValue();
23556 uint64_t Shift = ShiftNode->getZExtValue();
23557 if (isMask_64(Mask)) {
23558 uint64_t MaskSize = countPopulation(Mask);
23559 if (Shift + MaskSize <= VT.getSizeInBits())
23560 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
23561 DAG.getConstant(Shift | (MaskSize << 8), DL,
23570 // Want to form ANDNP nodes:
23571 // 1) In the hopes of then easily combining them with OR and AND nodes
23572 // to form PBLEND/PSIGN.
23573 // 2) To match ANDN packed intrinsics
23574 if (VT != MVT::v2i64 && VT != MVT::v4i64)
23577 // Check LHS for vnot
23578 if (N0.getOpcode() == ISD::XOR &&
23579 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
23580 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
23581 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
23583 // Check RHS for vnot
23584 if (N1.getOpcode() == ISD::XOR &&
23585 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
23586 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
23587 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
23592 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
23593 TargetLowering::DAGCombinerInfo &DCI,
23594 const X86Subtarget *Subtarget) {
23595 if (DCI.isBeforeLegalizeOps())
23598 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
23601 SDValue N0 = N->getOperand(0);
23602 SDValue N1 = N->getOperand(1);
23603 EVT VT = N->getValueType(0);
23605 // look for psign/blend
23606 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
23607 if (!Subtarget->hasSSSE3() ||
23608 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
23611 // Canonicalize pandn to RHS
23612 if (N0.getOpcode() == X86ISD::ANDNP)
23614 // or (and (m, y), (pandn m, x))
23615 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
23616 SDValue Mask = N1.getOperand(0);
23617 SDValue X = N1.getOperand(1);
23619 if (N0.getOperand(0) == Mask)
23620 Y = N0.getOperand(1);
23621 if (N0.getOperand(1) == Mask)
23622 Y = N0.getOperand(0);
23624 // Check to see if the mask appeared in both the AND and ANDNP and
23628 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
23629 // Look through mask bitcast.
23630 if (Mask.getOpcode() == ISD::BITCAST)
23631 Mask = Mask.getOperand(0);
23632 if (X.getOpcode() == ISD::BITCAST)
23633 X = X.getOperand(0);
23634 if (Y.getOpcode() == ISD::BITCAST)
23635 Y = Y.getOperand(0);
23637 EVT MaskVT = Mask.getValueType();
23639 // Validate that the Mask operand is a vector sra node.
23640 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
23641 // there is no psrai.b
23642 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
23643 unsigned SraAmt = ~0;
23644 if (Mask.getOpcode() == ISD::SRA) {
23645 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
23646 if (auto *AmtConst = AmtBV->getConstantSplatNode())
23647 SraAmt = AmtConst->getZExtValue();
23648 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
23649 SDValue SraC = Mask.getOperand(1);
23650 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
23652 if ((SraAmt + 1) != EltBits)
23657 // Now we know we at least have a plendvb with the mask val. See if
23658 // we can form a psignb/w/d.
23659 // psign = x.type == y.type == mask.type && y = sub(0, x);
23660 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
23661 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
23662 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
23663 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
23664 "Unsupported VT for PSIGN");
23665 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
23666 return DAG.getBitcast(VT, Mask);
23668 // PBLENDVB only available on SSE 4.1
23669 if (!Subtarget->hasSSE41())
23672 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
23674 X = DAG.getBitcast(BlendVT, X);
23675 Y = DAG.getBitcast(BlendVT, Y);
23676 Mask = DAG.getBitcast(BlendVT, Mask);
23677 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
23678 return DAG.getBitcast(VT, Mask);
23682 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
23685 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
23686 MachineFunction &MF = DAG.getMachineFunction();
23688 MF.getFunction()->hasFnAttribute(Attribute::OptimizeForSize);
23690 // SHLD/SHRD instructions have lower register pressure, but on some
23691 // platforms they have higher latency than the equivalent
23692 // series of shifts/or that would otherwise be generated.
23693 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
23694 // have higher latencies and we are not optimizing for size.
23695 if (!OptForSize && Subtarget->isSHLDSlow())
23698 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
23700 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
23702 if (!N0.hasOneUse() || !N1.hasOneUse())
23705 SDValue ShAmt0 = N0.getOperand(1);
23706 if (ShAmt0.getValueType() != MVT::i8)
23708 SDValue ShAmt1 = N1.getOperand(1);
23709 if (ShAmt1.getValueType() != MVT::i8)
23711 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
23712 ShAmt0 = ShAmt0.getOperand(0);
23713 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
23714 ShAmt1 = ShAmt1.getOperand(0);
23717 unsigned Opc = X86ISD::SHLD;
23718 SDValue Op0 = N0.getOperand(0);
23719 SDValue Op1 = N1.getOperand(0);
23720 if (ShAmt0.getOpcode() == ISD::SUB) {
23721 Opc = X86ISD::SHRD;
23722 std::swap(Op0, Op1);
23723 std::swap(ShAmt0, ShAmt1);
23726 unsigned Bits = VT.getSizeInBits();
23727 if (ShAmt1.getOpcode() == ISD::SUB) {
23728 SDValue Sum = ShAmt1.getOperand(0);
23729 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
23730 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
23731 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
23732 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
23733 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
23734 return DAG.getNode(Opc, DL, VT,
23736 DAG.getNode(ISD::TRUNCATE, DL,
23739 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
23740 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
23742 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
23743 return DAG.getNode(Opc, DL, VT,
23744 N0.getOperand(0), N1.getOperand(0),
23745 DAG.getNode(ISD::TRUNCATE, DL,
23752 // Generate NEG and CMOV for integer abs.
23753 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
23754 EVT VT = N->getValueType(0);
23756 // Since X86 does not have CMOV for 8-bit integer, we don't convert
23757 // 8-bit integer abs to NEG and CMOV.
23758 if (VT.isInteger() && VT.getSizeInBits() == 8)
23761 SDValue N0 = N->getOperand(0);
23762 SDValue N1 = N->getOperand(1);
23765 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
23766 // and change it to SUB and CMOV.
23767 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
23768 N0.getOpcode() == ISD::ADD &&
23769 N0.getOperand(1) == N1 &&
23770 N1.getOpcode() == ISD::SRA &&
23771 N1.getOperand(0) == N0.getOperand(0))
23772 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
23773 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
23774 // Generate SUB & CMOV.
23775 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
23776 DAG.getConstant(0, DL, VT), N0.getOperand(0));
23778 SDValue Ops[] = { N0.getOperand(0), Neg,
23779 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
23780 SDValue(Neg.getNode(), 1) };
23781 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
23786 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
23787 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
23788 TargetLowering::DAGCombinerInfo &DCI,
23789 const X86Subtarget *Subtarget) {
23790 if (DCI.isBeforeLegalizeOps())
23793 if (Subtarget->hasCMov())
23794 if (SDValue RV = performIntegerAbsCombine(N, DAG))
23800 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
23801 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
23802 TargetLowering::DAGCombinerInfo &DCI,
23803 const X86Subtarget *Subtarget) {
23804 LoadSDNode *Ld = cast<LoadSDNode>(N);
23805 EVT RegVT = Ld->getValueType(0);
23806 EVT MemVT = Ld->getMemoryVT();
23808 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23810 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
23811 // into two 16-byte operations.
23812 ISD::LoadExtType Ext = Ld->getExtensionType();
23813 unsigned Alignment = Ld->getAlignment();
23814 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
23815 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
23816 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
23817 unsigned NumElems = RegVT.getVectorNumElements();
23821 SDValue Ptr = Ld->getBasePtr();
23822 SDValue Increment =
23823 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
23825 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
23827 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23828 Ld->getPointerInfo(), Ld->isVolatile(),
23829 Ld->isNonTemporal(), Ld->isInvariant(),
23831 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23832 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23833 Ld->getPointerInfo(), Ld->isVolatile(),
23834 Ld->isNonTemporal(), Ld->isInvariant(),
23835 std::min(16U, Alignment));
23836 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
23838 Load2.getValue(1));
23840 SDValue NewVec = DAG.getUNDEF(RegVT);
23841 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
23842 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
23843 return DCI.CombineTo(N, NewVec, TF, true);
23849 /// PerformMLOADCombine - Resolve extending loads
23850 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
23851 TargetLowering::DAGCombinerInfo &DCI,
23852 const X86Subtarget *Subtarget) {
23853 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
23854 if (Mld->getExtensionType() != ISD::SEXTLOAD)
23857 EVT VT = Mld->getValueType(0);
23858 unsigned NumElems = VT.getVectorNumElements();
23859 EVT LdVT = Mld->getMemoryVT();
23862 assert(LdVT != VT && "Cannot extend to the same type");
23863 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
23864 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
23865 // From, To sizes and ElemCount must be pow of two
23866 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
23867 "Unexpected size for extending masked load");
23869 unsigned SizeRatio = ToSz / FromSz;
23870 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
23872 // Create a type on which we perform the shuffle
23873 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23874 LdVT.getScalarType(), NumElems*SizeRatio);
23875 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23877 // Convert Src0 value
23878 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
23879 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
23880 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23881 for (unsigned i = 0; i != NumElems; ++i)
23882 ShuffleVec[i] = i * SizeRatio;
23884 // Can't shuffle using an illegal type.
23885 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
23886 && "WideVecVT should be legal");
23887 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
23888 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
23890 // Prepare the new mask
23892 SDValue Mask = Mld->getMask();
23893 if (Mask.getValueType() == VT) {
23894 // Mask and original value have the same type
23895 NewMask = DAG.getBitcast(WideVecVT, Mask);
23896 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23897 for (unsigned i = 0; i != NumElems; ++i)
23898 ShuffleVec[i] = i * SizeRatio;
23899 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
23900 ShuffleVec[i] = NumElems*SizeRatio;
23901 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
23902 DAG.getConstant(0, dl, WideVecVT),
23906 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
23907 unsigned WidenNumElts = NumElems*SizeRatio;
23908 unsigned MaskNumElts = VT.getVectorNumElements();
23909 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
23912 unsigned NumConcat = WidenNumElts / MaskNumElts;
23913 SmallVector<SDValue, 16> Ops(NumConcat);
23914 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
23916 for (unsigned i = 1; i != NumConcat; ++i)
23919 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
23922 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
23923 Mld->getBasePtr(), NewMask, WideSrc0,
23924 Mld->getMemoryVT(), Mld->getMemOperand(),
23926 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
23927 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
23930 /// PerformMSTORECombine - Resolve truncating stores
23931 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
23932 const X86Subtarget *Subtarget) {
23933 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
23934 if (!Mst->isTruncatingStore())
23937 EVT VT = Mst->getValue().getValueType();
23938 unsigned NumElems = VT.getVectorNumElements();
23939 EVT StVT = Mst->getMemoryVT();
23942 assert(StVT != VT && "Cannot truncate to the same type");
23943 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23944 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23946 // From, To sizes and ElemCount must be pow of two
23947 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
23948 "Unexpected size for truncating masked store");
23949 // We are going to use the original vector elt for storing.
23950 // Accumulated smaller vector elements must be a multiple of the store size.
23951 assert (((NumElems * FromSz) % ToSz) == 0 &&
23952 "Unexpected ratio for truncating masked store");
23954 unsigned SizeRatio = FromSz / ToSz;
23955 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23957 // Create a type on which we perform the shuffle
23958 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23959 StVT.getScalarType(), NumElems*SizeRatio);
23961 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23963 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
23964 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23965 for (unsigned i = 0; i != NumElems; ++i)
23966 ShuffleVec[i] = i * SizeRatio;
23968 // Can't shuffle using an illegal type.
23969 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
23970 && "WideVecVT should be legal");
23972 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23973 DAG.getUNDEF(WideVecVT),
23977 SDValue Mask = Mst->getMask();
23978 if (Mask.getValueType() == VT) {
23979 // Mask and original value have the same type
23980 NewMask = DAG.getBitcast(WideVecVT, Mask);
23981 for (unsigned i = 0; i != NumElems; ++i)
23982 ShuffleVec[i] = i * SizeRatio;
23983 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
23984 ShuffleVec[i] = NumElems*SizeRatio;
23985 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
23986 DAG.getConstant(0, dl, WideVecVT),
23990 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
23991 unsigned WidenNumElts = NumElems*SizeRatio;
23992 unsigned MaskNumElts = VT.getVectorNumElements();
23993 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
23996 unsigned NumConcat = WidenNumElts / MaskNumElts;
23997 SmallVector<SDValue, 16> Ops(NumConcat);
23998 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
24000 for (unsigned i = 1; i != NumConcat; ++i)
24003 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
24006 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
24007 NewMask, StVT, Mst->getMemOperand(), false);
24009 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
24010 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
24011 const X86Subtarget *Subtarget) {
24012 StoreSDNode *St = cast<StoreSDNode>(N);
24013 EVT VT = St->getValue().getValueType();
24014 EVT StVT = St->getMemoryVT();
24016 SDValue StoredVal = St->getOperand(1);
24017 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24019 // If we are saving a concatenation of two XMM registers and 32-byte stores
24020 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
24021 unsigned Alignment = St->getAlignment();
24022 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
24023 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24024 StVT == VT && !IsAligned) {
24025 unsigned NumElems = VT.getVectorNumElements();
24029 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24030 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24033 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
24034 SDValue Ptr0 = St->getBasePtr();
24035 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
24037 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
24038 St->getPointerInfo(), St->isVolatile(),
24039 St->isNonTemporal(), Alignment);
24040 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
24041 St->getPointerInfo(), St->isVolatile(),
24042 St->isNonTemporal(),
24043 std::min(16U, Alignment));
24044 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
24047 // Optimize trunc store (of multiple scalars) to shuffle and store.
24048 // First, pack all of the elements in one place. Next, store to memory
24049 // in fewer chunks.
24050 if (St->isTruncatingStore() && VT.isVector()) {
24051 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24052 unsigned NumElems = VT.getVectorNumElements();
24053 assert(StVT != VT && "Cannot truncate to the same type");
24054 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24055 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24057 // From, To sizes and ElemCount must be pow of two
24058 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24059 // We are going to use the original vector elt for storing.
24060 // Accumulated smaller vector elements must be a multiple of the store size.
24061 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24063 unsigned SizeRatio = FromSz / ToSz;
24065 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24067 // Create a type on which we perform the shuffle
24068 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24069 StVT.getScalarType(), NumElems*SizeRatio);
24071 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24073 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
24074 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24075 for (unsigned i = 0; i != NumElems; ++i)
24076 ShuffleVec[i] = i * SizeRatio;
24078 // Can't shuffle using an illegal type.
24079 if (!TLI.isTypeLegal(WideVecVT))
24082 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24083 DAG.getUNDEF(WideVecVT),
24085 // At this point all of the data is stored at the bottom of the
24086 // register. We now need to save it to mem.
24088 // Find the largest store unit
24089 MVT StoreType = MVT::i8;
24090 for (MVT Tp : MVT::integer_valuetypes()) {
24091 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24095 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24096 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24097 (64 <= NumElems * ToSz))
24098 StoreType = MVT::f64;
24100 // Bitcast the original vector into a vector of store-size units
24101 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24102 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24103 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24104 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
24105 SmallVector<SDValue, 8> Chains;
24106 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, dl,
24107 TLI.getPointerTy(DAG.getDataLayout()));
24108 SDValue Ptr = St->getBasePtr();
24110 // Perform one or more big stores into memory.
24111 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24112 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24113 StoreType, ShuffWide,
24114 DAG.getIntPtrConstant(i, dl));
24115 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24116 St->getPointerInfo(), St->isVolatile(),
24117 St->isNonTemporal(), St->getAlignment());
24118 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24119 Chains.push_back(Ch);
24122 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24125 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24126 // the FP state in cases where an emms may be missing.
24127 // A preferable solution to the general problem is to figure out the right
24128 // places to insert EMMS. This qualifies as a quick hack.
24130 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24131 if (VT.getSizeInBits() != 64)
24134 const Function *F = DAG.getMachineFunction().getFunction();
24135 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
24137 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
24138 if ((VT.isVector() ||
24139 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24140 isa<LoadSDNode>(St->getValue()) &&
24141 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24142 St->getChain().hasOneUse() && !St->isVolatile()) {
24143 SDNode* LdVal = St->getValue().getNode();
24144 LoadSDNode *Ld = nullptr;
24145 int TokenFactorIndex = -1;
24146 SmallVector<SDValue, 8> Ops;
24147 SDNode* ChainVal = St->getChain().getNode();
24148 // Must be a store of a load. We currently handle two cases: the load
24149 // is a direct child, and it's under an intervening TokenFactor. It is
24150 // possible to dig deeper under nested TokenFactors.
24151 if (ChainVal == LdVal)
24152 Ld = cast<LoadSDNode>(St->getChain());
24153 else if (St->getValue().hasOneUse() &&
24154 ChainVal->getOpcode() == ISD::TokenFactor) {
24155 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24156 if (ChainVal->getOperand(i).getNode() == LdVal) {
24157 TokenFactorIndex = i;
24158 Ld = cast<LoadSDNode>(St->getValue());
24160 Ops.push_back(ChainVal->getOperand(i));
24164 if (!Ld || !ISD::isNormalLoad(Ld))
24167 // If this is not the MMX case, i.e. we are just turning i64 load/store
24168 // into f64 load/store, avoid the transformation if there are multiple
24169 // uses of the loaded value.
24170 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24175 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24176 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24178 if (Subtarget->is64Bit() || F64IsLegal) {
24179 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24180 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24181 Ld->getPointerInfo(), Ld->isVolatile(),
24182 Ld->isNonTemporal(), Ld->isInvariant(),
24183 Ld->getAlignment());
24184 SDValue NewChain = NewLd.getValue(1);
24185 if (TokenFactorIndex != -1) {
24186 Ops.push_back(NewChain);
24187 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24189 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24190 St->getPointerInfo(),
24191 St->isVolatile(), St->isNonTemporal(),
24192 St->getAlignment());
24195 // Otherwise, lower to two pairs of 32-bit loads / stores.
24196 SDValue LoAddr = Ld->getBasePtr();
24197 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24198 DAG.getConstant(4, LdDL, MVT::i32));
24200 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24201 Ld->getPointerInfo(),
24202 Ld->isVolatile(), Ld->isNonTemporal(),
24203 Ld->isInvariant(), Ld->getAlignment());
24204 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24205 Ld->getPointerInfo().getWithOffset(4),
24206 Ld->isVolatile(), Ld->isNonTemporal(),
24208 MinAlign(Ld->getAlignment(), 4));
24210 SDValue NewChain = LoLd.getValue(1);
24211 if (TokenFactorIndex != -1) {
24212 Ops.push_back(LoLd);
24213 Ops.push_back(HiLd);
24214 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24217 LoAddr = St->getBasePtr();
24218 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24219 DAG.getConstant(4, StDL, MVT::i32));
24221 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24222 St->getPointerInfo(),
24223 St->isVolatile(), St->isNonTemporal(),
24224 St->getAlignment());
24225 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24226 St->getPointerInfo().getWithOffset(4),
24228 St->isNonTemporal(),
24229 MinAlign(St->getAlignment(), 4));
24230 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24233 // This is similar to the above case, but here we handle a scalar 64-bit
24234 // integer store that is extracted from a vector on a 32-bit target.
24235 // If we have SSE2, then we can treat it like a floating-point double
24236 // to get past legalization. The execution dependencies fixup pass will
24237 // choose the optimal machine instruction for the store if this really is
24238 // an integer or v2f32 rather than an f64.
24239 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
24240 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
24241 SDValue OldExtract = St->getOperand(1);
24242 SDValue ExtOp0 = OldExtract.getOperand(0);
24243 unsigned VecSize = ExtOp0.getValueSizeInBits();
24244 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
24245 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
24246 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
24247 BitCast, OldExtract.getOperand(1));
24248 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
24249 St->getPointerInfo(), St->isVolatile(),
24250 St->isNonTemporal(), St->getAlignment());
24256 /// Return 'true' if this vector operation is "horizontal"
24257 /// and return the operands for the horizontal operation in LHS and RHS. A
24258 /// horizontal operation performs the binary operation on successive elements
24259 /// of its first operand, then on successive elements of its second operand,
24260 /// returning the resulting values in a vector. For example, if
24261 /// A = < float a0, float a1, float a2, float a3 >
24263 /// B = < float b0, float b1, float b2, float b3 >
24264 /// then the result of doing a horizontal operation on A and B is
24265 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
24266 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
24267 /// A horizontal-op B, for some already available A and B, and if so then LHS is
24268 /// set to A, RHS to B, and the routine returns 'true'.
24269 /// Note that the binary operation should have the property that if one of the
24270 /// operands is UNDEF then the result is UNDEF.
24271 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
24272 // Look for the following pattern: if
24273 // A = < float a0, float a1, float a2, float a3 >
24274 // B = < float b0, float b1, float b2, float b3 >
24276 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
24277 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
24278 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
24279 // which is A horizontal-op B.
24281 // At least one of the operands should be a vector shuffle.
24282 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
24283 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
24286 MVT VT = LHS.getSimpleValueType();
24288 assert((VT.is128BitVector() || VT.is256BitVector()) &&
24289 "Unsupported vector type for horizontal add/sub");
24291 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
24292 // operate independently on 128-bit lanes.
24293 unsigned NumElts = VT.getVectorNumElements();
24294 unsigned NumLanes = VT.getSizeInBits()/128;
24295 unsigned NumLaneElts = NumElts / NumLanes;
24296 assert((NumLaneElts % 2 == 0) &&
24297 "Vector type should have an even number of elements in each lane");
24298 unsigned HalfLaneElts = NumLaneElts/2;
24300 // View LHS in the form
24301 // LHS = VECTOR_SHUFFLE A, B, LMask
24302 // If LHS is not a shuffle then pretend it is the shuffle
24303 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24304 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24307 SmallVector<int, 16> LMask(NumElts);
24308 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24309 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24310 A = LHS.getOperand(0);
24311 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24312 B = LHS.getOperand(1);
24313 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24314 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24316 if (LHS.getOpcode() != ISD::UNDEF)
24318 for (unsigned i = 0; i != NumElts; ++i)
24322 // Likewise, view RHS in the form
24323 // RHS = VECTOR_SHUFFLE C, D, RMask
24325 SmallVector<int, 16> RMask(NumElts);
24326 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24327 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24328 C = RHS.getOperand(0);
24329 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24330 D = RHS.getOperand(1);
24331 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24332 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24334 if (RHS.getOpcode() != ISD::UNDEF)
24336 for (unsigned i = 0; i != NumElts; ++i)
24340 // Check that the shuffles are both shuffling the same vectors.
24341 if (!(A == C && B == D) && !(A == D && B == C))
24344 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24345 if (!A.getNode() && !B.getNode())
24348 // If A and B occur in reverse order in RHS, then "swap" them (which means
24349 // rewriting the mask).
24351 ShuffleVectorSDNode::commuteMask(RMask);
24353 // At this point LHS and RHS are equivalent to
24354 // LHS = VECTOR_SHUFFLE A, B, LMask
24355 // RHS = VECTOR_SHUFFLE A, B, RMask
24356 // Check that the masks correspond to performing a horizontal operation.
24357 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24358 for (unsigned i = 0; i != NumLaneElts; ++i) {
24359 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24361 // Ignore any UNDEF components.
24362 if (LIdx < 0 || RIdx < 0 ||
24363 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24364 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24367 // Check that successive elements are being operated on. If not, this is
24368 // not a horizontal operation.
24369 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24370 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24371 if (!(LIdx == Index && RIdx == Index + 1) &&
24372 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24377 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24378 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24382 /// Do target-specific dag combines on floating point adds.
24383 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24384 const X86Subtarget *Subtarget) {
24385 EVT VT = N->getValueType(0);
24386 SDValue LHS = N->getOperand(0);
24387 SDValue RHS = N->getOperand(1);
24389 // Try to synthesize horizontal adds from adds of shuffles.
24390 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24391 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24392 isHorizontalBinOp(LHS, RHS, true))
24393 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24397 /// Do target-specific dag combines on floating point subs.
24398 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24399 const X86Subtarget *Subtarget) {
24400 EVT VT = N->getValueType(0);
24401 SDValue LHS = N->getOperand(0);
24402 SDValue RHS = N->getOperand(1);
24404 // Try to synthesize horizontal subs from subs of shuffles.
24405 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24406 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24407 isHorizontalBinOp(LHS, RHS, false))
24408 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24412 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
24413 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24414 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24416 // F[X]OR(0.0, x) -> x
24417 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24418 if (C->getValueAPF().isPosZero())
24419 return N->getOperand(1);
24421 // F[X]OR(x, 0.0) -> x
24422 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24423 if (C->getValueAPF().isPosZero())
24424 return N->getOperand(0);
24428 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
24429 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24430 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24432 // Only perform optimizations if UnsafeMath is used.
24433 if (!DAG.getTarget().Options.UnsafeFPMath)
24436 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24437 // into FMINC and FMAXC, which are Commutative operations.
24438 unsigned NewOp = 0;
24439 switch (N->getOpcode()) {
24440 default: llvm_unreachable("unknown opcode");
24441 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24442 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
24445 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
24446 N->getOperand(0), N->getOperand(1));
24449 /// Do target-specific dag combines on X86ISD::FAND nodes.
24450 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
24451 // FAND(0.0, x) -> 0.0
24452 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24453 if (C->getValueAPF().isPosZero())
24454 return N->getOperand(0);
24456 // FAND(x, 0.0) -> 0.0
24457 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24458 if (C->getValueAPF().isPosZero())
24459 return N->getOperand(1);
24464 /// Do target-specific dag combines on X86ISD::FANDN nodes
24465 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
24466 // FANDN(0.0, x) -> x
24467 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24468 if (C->getValueAPF().isPosZero())
24469 return N->getOperand(1);
24471 // FANDN(x, 0.0) -> 0.0
24472 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24473 if (C->getValueAPF().isPosZero())
24474 return N->getOperand(1);
24479 static SDValue PerformBTCombine(SDNode *N,
24481 TargetLowering::DAGCombinerInfo &DCI) {
24482 // BT ignores high bits in the bit index operand.
24483 SDValue Op1 = N->getOperand(1);
24484 if (Op1.hasOneUse()) {
24485 unsigned BitWidth = Op1.getValueSizeInBits();
24486 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
24487 APInt KnownZero, KnownOne;
24488 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
24489 !DCI.isBeforeLegalizeOps());
24490 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24491 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
24492 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
24493 DCI.CommitTargetLoweringOpt(TLO);
24498 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
24499 SDValue Op = N->getOperand(0);
24500 if (Op.getOpcode() == ISD::BITCAST)
24501 Op = Op.getOperand(0);
24502 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
24503 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
24504 VT.getVectorElementType().getSizeInBits() ==
24505 OpVT.getVectorElementType().getSizeInBits()) {
24506 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
24511 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
24512 const X86Subtarget *Subtarget) {
24513 EVT VT = N->getValueType(0);
24514 if (!VT.isVector())
24517 SDValue N0 = N->getOperand(0);
24518 SDValue N1 = N->getOperand(1);
24519 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
24522 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
24523 // both SSE and AVX2 since there is no sign-extended shift right
24524 // operation on a vector with 64-bit elements.
24525 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
24526 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
24527 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
24528 N0.getOpcode() == ISD::SIGN_EXTEND)) {
24529 SDValue N00 = N0.getOperand(0);
24531 // EXTLOAD has a better solution on AVX2,
24532 // it may be replaced with X86ISD::VSEXT node.
24533 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
24534 if (!ISD::isNormalLoad(N00.getNode()))
24537 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
24538 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
24540 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24546 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24547 TargetLowering::DAGCombinerInfo &DCI,
24548 const X86Subtarget *Subtarget) {
24549 SDValue N0 = N->getOperand(0);
24550 EVT VT = N->getValueType(0);
24551 EVT SVT = VT.getScalarType();
24552 EVT InVT = N0.getValueType();
24553 EVT InSVT = InVT.getScalarType();
24556 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
24557 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
24558 // This exposes the sext to the sdivrem lowering, so that it directly extends
24559 // from AH (which we otherwise need to do contortions to access).
24560 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
24561 InVT == MVT::i8 && VT == MVT::i32) {
24562 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24563 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
24564 N0.getOperand(0), N0.getOperand(1));
24565 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24566 return R.getValue(1);
24569 if (!DCI.isBeforeLegalizeOps()) {
24570 if (InVT == MVT::i1) {
24571 SDValue Zero = DAG.getConstant(0, DL, VT);
24573 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
24574 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
24579 if (VT.isVector() && Subtarget->hasSSE2()) {
24580 auto ExtendVecSize = [&DAG](SDLoc DL, SDValue N, unsigned Size) {
24581 EVT InVT = N.getValueType();
24582 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
24583 Size / InVT.getScalarSizeInBits());
24584 SmallVector<SDValue, 8> Opnds(Size / InVT.getSizeInBits(),
24585 DAG.getUNDEF(InVT));
24587 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
24590 // If target-size is less than 128-bits, extend to a type that would extend
24591 // to 128 bits, extend that and extract the original target vector.
24592 if (VT.getSizeInBits() < 128 && !(128 % VT.getSizeInBits()) &&
24593 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
24594 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
24595 unsigned Scale = 128 / VT.getSizeInBits();
24597 EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits());
24598 SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits());
24599 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);
24600 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SExt,
24601 DAG.getIntPtrConstant(0, DL));
24604 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
24605 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
24606 if (VT.getSizeInBits() == 128 &&
24607 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
24608 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
24609 SDValue ExOp = ExtendVecSize(DL, N0, 128);
24610 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
24613 // On pre-AVX2 targets, split into 128-bit nodes of
24614 // ISD::SIGN_EXTEND_VECTOR_INREG.
24615 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
24616 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
24617 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
24618 unsigned NumVecs = VT.getSizeInBits() / 128;
24619 unsigned NumSubElts = 128 / SVT.getSizeInBits();
24620 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
24621 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
24623 SmallVector<SDValue, 8> Opnds;
24624 for (unsigned i = 0, Offset = 0; i != NumVecs;
24625 ++i, Offset += NumSubElts) {
24626 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
24627 DAG.getIntPtrConstant(Offset, DL));
24628 SrcVec = ExtendVecSize(DL, SrcVec, 128);
24629 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
24630 Opnds.push_back(SrcVec);
24632 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
24636 if (!Subtarget->hasFp256())
24639 if (VT.isVector() && VT.getSizeInBits() == 256)
24640 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
24646 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24647 const X86Subtarget* Subtarget) {
24649 EVT VT = N->getValueType(0);
24651 // Let legalize expand this if it isn't a legal type yet.
24652 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
24655 EVT ScalarVT = VT.getScalarType();
24656 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
24657 (!Subtarget->hasFMA() && !Subtarget->hasFMA4() &&
24658 !Subtarget->hasAVX512()))
24661 SDValue A = N->getOperand(0);
24662 SDValue B = N->getOperand(1);
24663 SDValue C = N->getOperand(2);
24665 bool NegA = (A.getOpcode() == ISD::FNEG);
24666 bool NegB = (B.getOpcode() == ISD::FNEG);
24667 bool NegC = (C.getOpcode() == ISD::FNEG);
24669 // Negative multiplication when NegA xor NegB
24670 bool NegMul = (NegA != NegB);
24672 A = A.getOperand(0);
24674 B = B.getOperand(0);
24676 C = C.getOperand(0);
24680 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
24682 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
24684 return DAG.getNode(Opcode, dl, VT, A, B, C);
24687 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
24688 TargetLowering::DAGCombinerInfo &DCI,
24689 const X86Subtarget *Subtarget) {
24690 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
24691 // (and (i32 x86isd::setcc_carry), 1)
24692 // This eliminates the zext. This transformation is necessary because
24693 // ISD::SETCC is always legalized to i8.
24695 SDValue N0 = N->getOperand(0);
24696 EVT VT = N->getValueType(0);
24698 if (N0.getOpcode() == ISD::AND &&
24700 N0.getOperand(0).hasOneUse()) {
24701 SDValue N00 = N0.getOperand(0);
24702 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24703 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24704 if (!C || C->getZExtValue() != 1)
24706 return DAG.getNode(ISD::AND, dl, VT,
24707 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24708 N00.getOperand(0), N00.getOperand(1)),
24709 DAG.getConstant(1, dl, VT));
24713 if (N0.getOpcode() == ISD::TRUNCATE &&
24715 N0.getOperand(0).hasOneUse()) {
24716 SDValue N00 = N0.getOperand(0);
24717 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24718 return DAG.getNode(ISD::AND, dl, VT,
24719 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24720 N00.getOperand(0), N00.getOperand(1)),
24721 DAG.getConstant(1, dl, VT));
24725 if (VT.is256BitVector())
24726 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
24729 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
24730 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
24731 // This exposes the zext to the udivrem lowering, so that it directly extends
24732 // from AH (which we otherwise need to do contortions to access).
24733 if (N0.getOpcode() == ISD::UDIVREM &&
24734 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
24735 (VT == MVT::i32 || VT == MVT::i64)) {
24736 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24737 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
24738 N0.getOperand(0), N0.getOperand(1));
24739 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24740 return R.getValue(1);
24746 // Optimize x == -y --> x+y == 0
24747 // x != -y --> x+y != 0
24748 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
24749 const X86Subtarget* Subtarget) {
24750 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
24751 SDValue LHS = N->getOperand(0);
24752 SDValue RHS = N->getOperand(1);
24753 EVT VT = N->getValueType(0);
24756 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
24757 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
24758 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
24759 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
24760 LHS.getOperand(1));
24761 return DAG.getSetCC(DL, N->getValueType(0), addV,
24762 DAG.getConstant(0, DL, addV.getValueType()), CC);
24764 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
24765 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
24766 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
24767 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
24768 RHS.getOperand(1));
24769 return DAG.getSetCC(DL, N->getValueType(0), addV,
24770 DAG.getConstant(0, DL, addV.getValueType()), CC);
24773 if (VT.getScalarType() == MVT::i1 &&
24774 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
24776 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24777 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24778 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24780 if (!IsSEXT0 || !IsVZero1) {
24781 // Swap the operands and update the condition code.
24782 std::swap(LHS, RHS);
24783 CC = ISD::getSetCCSwappedOperands(CC);
24785 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24786 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24787 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24790 if (IsSEXT0 && IsVZero1) {
24791 assert(VT == LHS.getOperand(0).getValueType() &&
24792 "Uexpected operand type");
24793 if (CC == ISD::SETGT)
24794 return DAG.getConstant(0, DL, VT);
24795 if (CC == ISD::SETLE)
24796 return DAG.getConstant(1, DL, VT);
24797 if (CC == ISD::SETEQ || CC == ISD::SETGE)
24798 return DAG.getNOT(DL, LHS.getOperand(0), VT);
24800 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
24801 "Unexpected condition code!");
24802 return LHS.getOperand(0);
24809 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
24810 SelectionDAG &DAG) {
24812 MVT VT = Load->getSimpleValueType(0);
24813 MVT EVT = VT.getVectorElementType();
24814 SDValue Addr = Load->getOperand(1);
24815 SDValue NewAddr = DAG.getNode(
24816 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
24817 DAG.getConstant(Index * EVT.getStoreSize(), dl,
24818 Addr.getSimpleValueType()));
24821 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
24822 DAG.getMachineFunction().getMachineMemOperand(
24823 Load->getMemOperand(), 0, EVT.getStoreSize()));
24827 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
24828 const X86Subtarget *Subtarget) {
24830 MVT VT = N->getOperand(1)->getSimpleValueType(0);
24831 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
24832 "X86insertps is only defined for v4x32");
24834 SDValue Ld = N->getOperand(1);
24835 if (MayFoldLoad(Ld)) {
24836 // Extract the countS bits from the immediate so we can get the proper
24837 // address when narrowing the vector load to a specific element.
24838 // When the second source op is a memory address, insertps doesn't use
24839 // countS and just gets an f32 from that address.
24840 unsigned DestIndex =
24841 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
24843 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
24845 // Create this as a scalar to vector to match the instruction pattern.
24846 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
24847 // countS bits are ignored when loading from memory on insertps, which
24848 // means we don't need to explicitly set them to 0.
24849 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
24850 LoadScalarToVector, N->getOperand(2));
24855 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
24856 SDValue V0 = N->getOperand(0);
24857 SDValue V1 = N->getOperand(1);
24859 EVT VT = N->getValueType(0);
24861 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
24862 // operands and changing the mask to 1. This saves us a bunch of
24863 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
24864 // x86InstrInfo knows how to commute this back after instruction selection
24865 // if it would help register allocation.
24867 // TODO: If optimizing for size or a processor that doesn't suffer from
24868 // partial register update stalls, this should be transformed into a MOVSD
24869 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
24871 if (VT == MVT::v2f64)
24872 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
24873 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
24874 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
24875 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
24881 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
24882 // as "sbb reg,reg", since it can be extended without zext and produces
24883 // an all-ones bit which is more useful than 0/1 in some cases.
24884 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
24887 return DAG.getNode(ISD::AND, DL, VT,
24888 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24889 DAG.getConstant(X86::COND_B, DL, MVT::i8),
24891 DAG.getConstant(1, DL, VT));
24892 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
24893 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
24894 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24895 DAG.getConstant(X86::COND_B, DL, MVT::i8),
24899 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
24900 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
24901 TargetLowering::DAGCombinerInfo &DCI,
24902 const X86Subtarget *Subtarget) {
24904 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
24905 SDValue EFLAGS = N->getOperand(1);
24907 if (CC == X86::COND_A) {
24908 // Try to convert COND_A into COND_B in an attempt to facilitate
24909 // materializing "setb reg".
24911 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
24912 // cannot take an immediate as its first operand.
24914 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
24915 EFLAGS.getValueType().isInteger() &&
24916 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
24917 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
24918 EFLAGS.getNode()->getVTList(),
24919 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
24920 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
24921 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
24925 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
24926 // a zext and produces an all-ones bit which is more useful than 0/1 in some
24928 if (CC == X86::COND_B)
24929 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
24931 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
24932 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
24933 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
24939 // Optimize branch condition evaluation.
24941 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
24942 TargetLowering::DAGCombinerInfo &DCI,
24943 const X86Subtarget *Subtarget) {
24945 SDValue Chain = N->getOperand(0);
24946 SDValue Dest = N->getOperand(1);
24947 SDValue EFLAGS = N->getOperand(3);
24948 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
24950 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
24951 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
24952 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
24959 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
24960 SelectionDAG &DAG) {
24961 // Take advantage of vector comparisons producing 0 or -1 in each lane to
24962 // optimize away operation when it's from a constant.
24964 // The general transformation is:
24965 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
24966 // AND(VECTOR_CMP(x,y), constant2)
24967 // constant2 = UNARYOP(constant)
24969 // Early exit if this isn't a vector operation, the operand of the
24970 // unary operation isn't a bitwise AND, or if the sizes of the operations
24971 // aren't the same.
24972 EVT VT = N->getValueType(0);
24973 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
24974 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
24975 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
24978 // Now check that the other operand of the AND is a constant. We could
24979 // make the transformation for non-constant splats as well, but it's unclear
24980 // that would be a benefit as it would not eliminate any operations, just
24981 // perform one more step in scalar code before moving to the vector unit.
24982 if (BuildVectorSDNode *BV =
24983 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
24984 // Bail out if the vector isn't a constant.
24985 if (!BV->isConstant())
24988 // Everything checks out. Build up the new and improved node.
24990 EVT IntVT = BV->getValueType(0);
24991 // Create a new constant of the appropriate type for the transformed
24993 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
24994 // The AND node needs bitcasts to/from an integer vector type around it.
24995 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
24996 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
24997 N->getOperand(0)->getOperand(0), MaskConst);
24998 SDValue Res = DAG.getBitcast(VT, NewAnd);
25005 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25006 const X86Subtarget *Subtarget) {
25007 SDValue Op0 = N->getOperand(0);
25008 EVT VT = N->getValueType(0);
25009 EVT InVT = Op0.getValueType();
25010 EVT InSVT = InVT.getScalarType();
25011 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25013 // UINT_TO_FP(vXi8) -> SINT_TO_FP(ZEXT(vXi8 to vXi32))
25014 // UINT_TO_FP(vXi16) -> SINT_TO_FP(ZEXT(vXi16 to vXi32))
25015 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
25017 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
25018 InVT.getVectorNumElements());
25019 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
25021 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
25022 return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P);
25024 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
25030 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25031 const X86Subtarget *Subtarget) {
25032 // First try to optimize away the conversion entirely when it's
25033 // conditionally from a constant. Vectors only.
25034 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
25037 // Now move on to more general possibilities.
25038 SDValue Op0 = N->getOperand(0);
25039 EVT VT = N->getValueType(0);
25040 EVT InVT = Op0.getValueType();
25041 EVT InSVT = InVT.getScalarType();
25043 // SINT_TO_FP(vXi8) -> SINT_TO_FP(SEXT(vXi8 to vXi32))
25044 // SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
25045 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
25047 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
25048 InVT.getVectorNumElements());
25049 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
25050 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
25053 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
25054 // a 32-bit target where SSE doesn't support i64->FP operations.
25055 if (Op0.getOpcode() == ISD::LOAD) {
25056 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
25057 EVT LdVT = Ld->getValueType(0);
25059 // This transformation is not supported if the result type is f16
25060 if (VT == MVT::f16)
25063 if (!Ld->isVolatile() && !VT.isVector() &&
25064 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
25065 !Subtarget->is64Bit() && LdVT == MVT::i64) {
25066 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
25067 SDValue(N, 0), LdVT, Ld->getChain(), Op0, DAG);
25068 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
25075 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
25076 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
25077 X86TargetLowering::DAGCombinerInfo &DCI) {
25078 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
25079 // the result is either zero or one (depending on the input carry bit).
25080 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
25081 if (X86::isZeroNode(N->getOperand(0)) &&
25082 X86::isZeroNode(N->getOperand(1)) &&
25083 // We don't have a good way to replace an EFLAGS use, so only do this when
25085 SDValue(N, 1).use_empty()) {
25087 EVT VT = N->getValueType(0);
25088 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
25089 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
25090 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
25091 DAG.getConstant(X86::COND_B, DL,
25094 DAG.getConstant(1, DL, VT));
25095 return DCI.CombineTo(N, Res1, CarryOut);
25101 // fold (add Y, (sete X, 0)) -> adc 0, Y
25102 // (add Y, (setne X, 0)) -> sbb -1, Y
25103 // (sub (sete X, 0), Y) -> sbb 0, Y
25104 // (sub (setne X, 0), Y) -> adc -1, Y
25105 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
25108 // Look through ZExts.
25109 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
25110 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25113 SDValue SetCC = Ext.getOperand(0);
25114 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25117 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25118 if (CC != X86::COND_E && CC != X86::COND_NE)
25121 SDValue Cmp = SetCC.getOperand(1);
25122 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25123 !X86::isZeroNode(Cmp.getOperand(1)) ||
25124 !Cmp.getOperand(0).getValueType().isInteger())
25127 SDValue CmpOp0 = Cmp.getOperand(0);
25128 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25129 DAG.getConstant(1, DL, CmpOp0.getValueType()));
25131 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25132 if (CC == X86::COND_NE)
25133 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25134 DL, OtherVal.getValueType(), OtherVal,
25135 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
25137 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25138 DL, OtherVal.getValueType(), OtherVal,
25139 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
25142 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25143 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25144 const X86Subtarget *Subtarget) {
25145 EVT VT = N->getValueType(0);
25146 SDValue Op0 = N->getOperand(0);
25147 SDValue Op1 = N->getOperand(1);
25149 // Try to synthesize horizontal adds from adds of shuffles.
25150 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25151 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25152 isHorizontalBinOp(Op0, Op1, true))
25153 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25155 return OptimizeConditionalInDecrement(N, DAG);
25158 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25159 const X86Subtarget *Subtarget) {
25160 SDValue Op0 = N->getOperand(0);
25161 SDValue Op1 = N->getOperand(1);
25163 // X86 can't encode an immediate LHS of a sub. See if we can push the
25164 // negation into a preceding instruction.
25165 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25166 // If the RHS of the sub is a XOR with one use and a constant, invert the
25167 // immediate. Then add one to the LHS of the sub so we can turn
25168 // X-Y -> X+~Y+1, saving one register.
25169 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25170 isa<ConstantSDNode>(Op1.getOperand(1))) {
25171 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25172 EVT VT = Op0.getValueType();
25173 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25175 DAG.getConstant(~XorC, SDLoc(Op1), VT));
25176 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25177 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
25181 // Try to synthesize horizontal adds from adds of shuffles.
25182 EVT VT = N->getValueType(0);
25183 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25184 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25185 isHorizontalBinOp(Op0, Op1, true))
25186 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25188 return OptimizeConditionalInDecrement(N, DAG);
25191 /// performVZEXTCombine - Performs build vector combines
25192 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25193 TargetLowering::DAGCombinerInfo &DCI,
25194 const X86Subtarget *Subtarget) {
25196 MVT VT = N->getSimpleValueType(0);
25197 SDValue Op = N->getOperand(0);
25198 MVT OpVT = Op.getSimpleValueType();
25199 MVT OpEltVT = OpVT.getVectorElementType();
25200 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25202 // (vzext (bitcast (vzext (x)) -> (vzext x)
25204 while (V.getOpcode() == ISD::BITCAST)
25205 V = V.getOperand(0);
25207 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25208 MVT InnerVT = V.getSimpleValueType();
25209 MVT InnerEltVT = InnerVT.getVectorElementType();
25211 // If the element sizes match exactly, we can just do one larger vzext. This
25212 // is always an exact type match as vzext operates on integer types.
25213 if (OpEltVT == InnerEltVT) {
25214 assert(OpVT == InnerVT && "Types must match for vzext!");
25215 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25218 // The only other way we can combine them is if only a single element of the
25219 // inner vzext is used in the input to the outer vzext.
25220 if (InnerEltVT.getSizeInBits() < InputBits)
25223 // In this case, the inner vzext is completely dead because we're going to
25224 // only look at bits inside of the low element. Just do the outer vzext on
25225 // a bitcast of the input to the inner.
25226 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
25229 // Check if we can bypass extracting and re-inserting an element of an input
25230 // vector. Essentialy:
25231 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25232 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25233 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25234 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25235 SDValue ExtractedV = V.getOperand(0);
25236 SDValue OrigV = ExtractedV.getOperand(0);
25237 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25238 if (ExtractIdx->getZExtValue() == 0) {
25239 MVT OrigVT = OrigV.getSimpleValueType();
25240 // Extract a subvector if necessary...
25241 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25242 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25243 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25244 OrigVT.getVectorNumElements() / Ratio);
25245 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25246 DAG.getIntPtrConstant(0, DL));
25248 Op = DAG.getBitcast(OpVT, OrigV);
25249 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25256 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25257 DAGCombinerInfo &DCI) const {
25258 SelectionDAG &DAG = DCI.DAG;
25259 switch (N->getOpcode()) {
25261 case ISD::EXTRACT_VECTOR_ELT:
25262 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
25265 case X86ISD::SHRUNKBLEND:
25266 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
25267 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG);
25268 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
25269 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
25270 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
25271 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
25272 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
25275 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
25276 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
25277 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
25278 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
25279 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
25280 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
25281 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
25282 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
25283 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
25284 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, Subtarget);
25285 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
25286 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
25288 case X86ISD::FOR: return PerformFORCombine(N, DAG);
25290 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
25291 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
25292 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
25293 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
25294 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
25295 case ISD::ANY_EXTEND:
25296 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
25297 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
25298 case ISD::SIGN_EXTEND_INREG:
25299 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
25300 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
25301 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
25302 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
25303 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
25304 case X86ISD::SHUFP: // Handle all target specific shuffles
25305 case X86ISD::PALIGNR:
25306 case X86ISD::UNPCKH:
25307 case X86ISD::UNPCKL:
25308 case X86ISD::MOVHLPS:
25309 case X86ISD::MOVLHPS:
25310 case X86ISD::PSHUFB:
25311 case X86ISD::PSHUFD:
25312 case X86ISD::PSHUFHW:
25313 case X86ISD::PSHUFLW:
25314 case X86ISD::MOVSS:
25315 case X86ISD::MOVSD:
25316 case X86ISD::VPERMILPI:
25317 case X86ISD::VPERM2X128:
25318 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
25319 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
25320 case ISD::INTRINSIC_WO_CHAIN:
25321 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
25322 case X86ISD::INSERTPS: {
25323 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
25324 return PerformINSERTPSCombine(N, DAG, Subtarget);
25327 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
25333 /// isTypeDesirableForOp - Return true if the target has native support for
25334 /// the specified value type and it is 'desirable' to use the type for the
25335 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
25336 /// instruction encodings are longer and some i16 instructions are slow.
25337 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
25338 if (!isTypeLegal(VT))
25340 if (VT != MVT::i16)
25347 case ISD::SIGN_EXTEND:
25348 case ISD::ZERO_EXTEND:
25349 case ISD::ANY_EXTEND:
25362 /// IsDesirableToPromoteOp - This method query the target whether it is
25363 /// beneficial for dag combiner to promote the specified node. If true, it
25364 /// should return the desired promotion type by reference.
25365 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25366 EVT VT = Op.getValueType();
25367 if (VT != MVT::i16)
25370 bool Promote = false;
25371 bool Commute = false;
25372 switch (Op.getOpcode()) {
25375 LoadSDNode *LD = cast<LoadSDNode>(Op);
25376 // If the non-extending load has a single use and it's not live out, then it
25377 // might be folded.
25378 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25379 Op.hasOneUse()*/) {
25380 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25381 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25382 // The only case where we'd want to promote LOAD (rather then it being
25383 // promoted as an operand is when it's only use is liveout.
25384 if (UI->getOpcode() != ISD::CopyToReg)
25391 case ISD::SIGN_EXTEND:
25392 case ISD::ZERO_EXTEND:
25393 case ISD::ANY_EXTEND:
25398 SDValue N0 = Op.getOperand(0);
25399 // Look out for (store (shl (load), x)).
25400 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25413 SDValue N0 = Op.getOperand(0);
25414 SDValue N1 = Op.getOperand(1);
25415 if (!Commute && MayFoldLoad(N1))
25417 // Avoid disabling potential load folding opportunities.
25418 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25420 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25430 //===----------------------------------------------------------------------===//
25431 // X86 Inline Assembly Support
25432 //===----------------------------------------------------------------------===//
25434 // Helper to match a string separated by whitespace.
25435 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
25436 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
25438 for (StringRef Piece : Pieces) {
25439 if (!S.startswith(Piece)) // Check if the piece matches.
25442 S = S.substr(Piece.size());
25443 StringRef::size_type Pos = S.find_first_not_of(" \t");
25444 if (Pos == 0) // We matched a prefix.
25453 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25455 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25456 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25457 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25458 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25460 if (AsmPieces.size() == 3)
25462 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25469 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25470 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25472 std::string AsmStr = IA->getAsmString();
25474 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25475 if (!Ty || Ty->getBitWidth() % 16 != 0)
25478 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25479 SmallVector<StringRef, 4> AsmPieces;
25480 SplitString(AsmStr, AsmPieces, ";\n");
25482 switch (AsmPieces.size()) {
25483 default: return false;
25485 // FIXME: this should verify that we are targeting a 486 or better. If not,
25486 // we will turn this bswap into something that will be lowered to logical
25487 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25488 // lower so don't worry about this.
25490 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
25491 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
25492 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
25493 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
25494 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
25495 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
25496 // No need to check constraints, nothing other than the equivalent of
25497 // "=r,0" would be valid here.
25498 return IntrinsicLowering::LowerToByteSwap(CI);
25501 // rorw $$8, ${0:w} --> llvm.bswap.i16
25502 if (CI->getType()->isIntegerTy(16) &&
25503 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25504 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
25505 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
25507 StringRef ConstraintsStr = IA->getConstraintString();
25508 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25509 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25510 if (clobbersFlagRegisters(AsmPieces))
25511 return IntrinsicLowering::LowerToByteSwap(CI);
25515 if (CI->getType()->isIntegerTy(32) &&
25516 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25517 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
25518 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
25519 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
25521 StringRef ConstraintsStr = IA->getConstraintString();
25522 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25523 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25524 if (clobbersFlagRegisters(AsmPieces))
25525 return IntrinsicLowering::LowerToByteSwap(CI);
25528 if (CI->getType()->isIntegerTy(64)) {
25529 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25530 if (Constraints.size() >= 2 &&
25531 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25532 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25533 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25534 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
25535 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
25536 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
25537 return IntrinsicLowering::LowerToByteSwap(CI);
25545 /// getConstraintType - Given a constraint letter, return the type of
25546 /// constraint it is for this target.
25547 X86TargetLowering::ConstraintType
25548 X86TargetLowering::getConstraintType(StringRef Constraint) const {
25549 if (Constraint.size() == 1) {
25550 switch (Constraint[0]) {
25561 return C_RegisterClass;
25585 return TargetLowering::getConstraintType(Constraint);
25588 /// Examine constraint type and operand type and determine a weight value.
25589 /// This object must already have been set up with the operand type
25590 /// and the current alternative constraint selected.
25591 TargetLowering::ConstraintWeight
25592 X86TargetLowering::getSingleConstraintMatchWeight(
25593 AsmOperandInfo &info, const char *constraint) const {
25594 ConstraintWeight weight = CW_Invalid;
25595 Value *CallOperandVal = info.CallOperandVal;
25596 // If we don't have a value, we can't do a match,
25597 // but allow it at the lowest weight.
25598 if (!CallOperandVal)
25600 Type *type = CallOperandVal->getType();
25601 // Look at the constraint type.
25602 switch (*constraint) {
25604 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
25615 if (CallOperandVal->getType()->isIntegerTy())
25616 weight = CW_SpecificReg;
25621 if (type->isFloatingPointTy())
25622 weight = CW_SpecificReg;
25625 if (type->isX86_MMXTy() && Subtarget->hasMMX())
25626 weight = CW_SpecificReg;
25630 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
25631 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
25632 weight = CW_Register;
25635 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
25636 if (C->getZExtValue() <= 31)
25637 weight = CW_Constant;
25641 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25642 if (C->getZExtValue() <= 63)
25643 weight = CW_Constant;
25647 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25648 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
25649 weight = CW_Constant;
25653 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25654 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
25655 weight = CW_Constant;
25659 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25660 if (C->getZExtValue() <= 3)
25661 weight = CW_Constant;
25665 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25666 if (C->getZExtValue() <= 0xff)
25667 weight = CW_Constant;
25672 if (isa<ConstantFP>(CallOperandVal)) {
25673 weight = CW_Constant;
25677 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25678 if ((C->getSExtValue() >= -0x80000000LL) &&
25679 (C->getSExtValue() <= 0x7fffffffLL))
25680 weight = CW_Constant;
25684 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25685 if (C->getZExtValue() <= 0xffffffff)
25686 weight = CW_Constant;
25693 /// LowerXConstraint - try to replace an X constraint, which matches anything,
25694 /// with another that has more specific requirements based on the type of the
25695 /// corresponding operand.
25696 const char *X86TargetLowering::
25697 LowerXConstraint(EVT ConstraintVT) const {
25698 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
25699 // 'f' like normal targets.
25700 if (ConstraintVT.isFloatingPoint()) {
25701 if (Subtarget->hasSSE2())
25703 if (Subtarget->hasSSE1())
25707 return TargetLowering::LowerXConstraint(ConstraintVT);
25710 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
25711 /// vector. If it is invalid, don't add anything to Ops.
25712 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
25713 std::string &Constraint,
25714 std::vector<SDValue>&Ops,
25715 SelectionDAG &DAG) const {
25718 // Only support length 1 constraints for now.
25719 if (Constraint.length() > 1) return;
25721 char ConstraintLetter = Constraint[0];
25722 switch (ConstraintLetter) {
25725 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25726 if (C->getZExtValue() <= 31) {
25727 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25728 Op.getValueType());
25734 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25735 if (C->getZExtValue() <= 63) {
25736 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25737 Op.getValueType());
25743 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25744 if (isInt<8>(C->getSExtValue())) {
25745 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25746 Op.getValueType());
25752 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25753 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
25754 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
25755 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
25756 Op.getValueType());
25762 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25763 if (C->getZExtValue() <= 3) {
25764 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25765 Op.getValueType());
25771 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25772 if (C->getZExtValue() <= 255) {
25773 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25774 Op.getValueType());
25780 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25781 if (C->getZExtValue() <= 127) {
25782 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25783 Op.getValueType());
25789 // 32-bit signed value
25790 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25791 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25792 C->getSExtValue())) {
25793 // Widen to 64 bits here to get it sign extended.
25794 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
25797 // FIXME gcc accepts some relocatable values here too, but only in certain
25798 // memory models; it's complicated.
25803 // 32-bit unsigned value
25804 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25805 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25806 C->getZExtValue())) {
25807 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25808 Op.getValueType());
25812 // FIXME gcc accepts some relocatable values here too, but only in certain
25813 // memory models; it's complicated.
25817 // Literal immediates are always ok.
25818 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
25819 // Widen to 64 bits here to get it sign extended.
25820 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
25824 // In any sort of PIC mode addresses need to be computed at runtime by
25825 // adding in a register or some sort of table lookup. These can't
25826 // be used as immediates.
25827 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
25830 // If we are in non-pic codegen mode, we allow the address of a global (with
25831 // an optional displacement) to be used with 'i'.
25832 GlobalAddressSDNode *GA = nullptr;
25833 int64_t Offset = 0;
25835 // Match either (GA), (GA+C), (GA+C1+C2), etc.
25837 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
25838 Offset += GA->getOffset();
25840 } else if (Op.getOpcode() == ISD::ADD) {
25841 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25842 Offset += C->getZExtValue();
25843 Op = Op.getOperand(0);
25846 } else if (Op.getOpcode() == ISD::SUB) {
25847 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25848 Offset += -C->getZExtValue();
25849 Op = Op.getOperand(0);
25854 // Otherwise, this isn't something we can handle, reject it.
25858 const GlobalValue *GV = GA->getGlobal();
25859 // If we require an extra load to get this address, as in PIC mode, we
25860 // can't accept it.
25861 if (isGlobalStubReference(
25862 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
25865 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
25866 GA->getValueType(0), Offset);
25871 if (Result.getNode()) {
25872 Ops.push_back(Result);
25875 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
25878 std::pair<unsigned, const TargetRegisterClass *>
25879 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
25880 StringRef Constraint,
25882 // First, see if this is a constraint that directly corresponds to an LLVM
25884 if (Constraint.size() == 1) {
25885 // GCC Constraint Letters
25886 switch (Constraint[0]) {
25888 // TODO: Slight differences here in allocation order and leaving
25889 // RIP in the class. Do they matter any more here than they do
25890 // in the normal allocation?
25891 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
25892 if (Subtarget->is64Bit()) {
25893 if (VT == MVT::i32 || VT == MVT::f32)
25894 return std::make_pair(0U, &X86::GR32RegClass);
25895 if (VT == MVT::i16)
25896 return std::make_pair(0U, &X86::GR16RegClass);
25897 if (VT == MVT::i8 || VT == MVT::i1)
25898 return std::make_pair(0U, &X86::GR8RegClass);
25899 if (VT == MVT::i64 || VT == MVT::f64)
25900 return std::make_pair(0U, &X86::GR64RegClass);
25903 // 32-bit fallthrough
25904 case 'Q': // Q_REGS
25905 if (VT == MVT::i32 || VT == MVT::f32)
25906 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
25907 if (VT == MVT::i16)
25908 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
25909 if (VT == MVT::i8 || VT == MVT::i1)
25910 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
25911 if (VT == MVT::i64)
25912 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
25914 case 'r': // GENERAL_REGS
25915 case 'l': // INDEX_REGS
25916 if (VT == MVT::i8 || VT == MVT::i1)
25917 return std::make_pair(0U, &X86::GR8RegClass);
25918 if (VT == MVT::i16)
25919 return std::make_pair(0U, &X86::GR16RegClass);
25920 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
25921 return std::make_pair(0U, &X86::GR32RegClass);
25922 return std::make_pair(0U, &X86::GR64RegClass);
25923 case 'R': // LEGACY_REGS
25924 if (VT == MVT::i8 || VT == MVT::i1)
25925 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
25926 if (VT == MVT::i16)
25927 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
25928 if (VT == MVT::i32 || !Subtarget->is64Bit())
25929 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
25930 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
25931 case 'f': // FP Stack registers.
25932 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
25933 // value to the correct fpstack register class.
25934 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
25935 return std::make_pair(0U, &X86::RFP32RegClass);
25936 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
25937 return std::make_pair(0U, &X86::RFP64RegClass);
25938 return std::make_pair(0U, &X86::RFP80RegClass);
25939 case 'y': // MMX_REGS if MMX allowed.
25940 if (!Subtarget->hasMMX()) break;
25941 return std::make_pair(0U, &X86::VR64RegClass);
25942 case 'Y': // SSE_REGS if SSE2 allowed
25943 if (!Subtarget->hasSSE2()) break;
25945 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
25946 if (!Subtarget->hasSSE1()) break;
25948 switch (VT.SimpleTy) {
25950 // Scalar SSE types.
25953 return std::make_pair(0U, &X86::FR32RegClass);
25956 return std::make_pair(0U, &X86::FR64RegClass);
25964 return std::make_pair(0U, &X86::VR128RegClass);
25972 return std::make_pair(0U, &X86::VR256RegClass);
25977 return std::make_pair(0U, &X86::VR512RegClass);
25983 // Use the default implementation in TargetLowering to convert the register
25984 // constraint into a member of a register class.
25985 std::pair<unsigned, const TargetRegisterClass*> Res;
25986 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
25988 // Not found as a standard register?
25990 // Map st(0) -> st(7) -> ST0
25991 if (Constraint.size() == 7 && Constraint[0] == '{' &&
25992 tolower(Constraint[1]) == 's' &&
25993 tolower(Constraint[2]) == 't' &&
25994 Constraint[3] == '(' &&
25995 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
25996 Constraint[5] == ')' &&
25997 Constraint[6] == '}') {
25999 Res.first = X86::FP0+Constraint[4]-'0';
26000 Res.second = &X86::RFP80RegClass;
26004 // GCC allows "st(0)" to be called just plain "st".
26005 if (StringRef("{st}").equals_lower(Constraint)) {
26006 Res.first = X86::FP0;
26007 Res.second = &X86::RFP80RegClass;
26012 if (StringRef("{flags}").equals_lower(Constraint)) {
26013 Res.first = X86::EFLAGS;
26014 Res.second = &X86::CCRRegClass;
26018 // 'A' means EAX + EDX.
26019 if (Constraint == "A") {
26020 Res.first = X86::EAX;
26021 Res.second = &X86::GR32_ADRegClass;
26027 // Otherwise, check to see if this is a register class of the wrong value
26028 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
26029 // turn into {ax},{dx}.
26030 // MVT::Other is used to specify clobber names.
26031 if (Res.second->hasType(VT) || VT == MVT::Other)
26032 return Res; // Correct type already, nothing to do.
26034 // Get a matching integer of the correct size. i.e. "ax" with MVT::32 should
26035 // return "eax". This should even work for things like getting 64bit integer
26036 // registers when given an f64 type.
26037 const TargetRegisterClass *Class = Res.second;
26038 if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
26039 Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
26040 unsigned Size = VT.getSizeInBits();
26041 MVT::SimpleValueType SimpleTy = Size == 1 || Size == 8 ? MVT::i8
26042 : Size == 16 ? MVT::i16
26043 : Size == 32 ? MVT::i32
26044 : Size == 64 ? MVT::i64
26046 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, SimpleTy);
26048 Res.first = DestReg;
26049 Res.second = SimpleTy == MVT::i8 ? &X86::GR8RegClass
26050 : SimpleTy == MVT::i16 ? &X86::GR16RegClass
26051 : SimpleTy == MVT::i32 ? &X86::GR32RegClass
26052 : &X86::GR64RegClass;
26053 assert(Res.second->contains(Res.first) && "Register in register class");
26055 // No register found/type mismatch.
26057 Res.second = nullptr;
26059 } else if (Class == &X86::FR32RegClass || Class == &X86::FR64RegClass ||
26060 Class == &X86::VR128RegClass || Class == &X86::VR256RegClass ||
26061 Class == &X86::FR32XRegClass || Class == &X86::FR64XRegClass ||
26062 Class == &X86::VR128XRegClass || Class == &X86::VR256XRegClass ||
26063 Class == &X86::VR512RegClass) {
26064 // Handle references to XMM physical registers that got mapped into the
26065 // wrong class. This can happen with constraints like {xmm0} where the
26066 // target independent register mapper will just pick the first match it can
26067 // find, ignoring the required type.
26069 if (VT == MVT::f32 || VT == MVT::i32)
26070 Res.second = &X86::FR32RegClass;
26071 else if (VT == MVT::f64 || VT == MVT::i64)
26072 Res.second = &X86::FR64RegClass;
26073 else if (X86::VR128RegClass.hasType(VT))
26074 Res.second = &X86::VR128RegClass;
26075 else if (X86::VR256RegClass.hasType(VT))
26076 Res.second = &X86::VR256RegClass;
26077 else if (X86::VR512RegClass.hasType(VT))
26078 Res.second = &X86::VR512RegClass;
26080 // Type mismatch and not a clobber: Return an error;
26082 Res.second = nullptr;
26089 int X86TargetLowering::getScalingFactorCost(const DataLayout &DL,
26090 const AddrMode &AM, Type *Ty,
26091 unsigned AS) const {
26092 // Scaling factors are not free at all.
26093 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
26094 // will take 2 allocations in the out of order engine instead of 1
26095 // for plain addressing mode, i.e. inst (reg1).
26097 // vaddps (%rsi,%drx), %ymm0, %ymm1
26098 // Requires two allocations (one for the load, one for the computation)
26100 // vaddps (%rsi), %ymm0, %ymm1
26101 // Requires just 1 allocation, i.e., freeing allocations for other operations
26102 // and having less micro operations to execute.
26104 // For some X86 architectures, this is even worse because for instance for
26105 // stores, the complex addressing mode forces the instruction to use the
26106 // "load" ports instead of the dedicated "store" port.
26107 // E.g., on Haswell:
26108 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
26109 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
26110 if (isLegalAddressingMode(DL, AM, Ty, AS))
26111 // Scale represents reg2 * scale, thus account for 1
26112 // as soon as we use a second register.
26113 return AM.Scale != 0;
26117 bool X86TargetLowering::isTargetFTOL() const {
26118 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();