1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/MC/MCAsmInfo.h"
40 #include "llvm/MC/MCContext.h"
41 #include "llvm/MC/MCExpr.h"
42 #include "llvm/MC/MCSymbol.h"
43 #include "llvm/ADT/BitVector.h"
44 #include "llvm/ADT/SmallSet.h"
45 #include "llvm/ADT/Statistic.h"
46 #include "llvm/ADT/StringExtras.h"
47 #include "llvm/ADT/VectorExtras.h"
48 #include "llvm/Support/CallSite.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/Dwarf.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
55 using namespace dwarf;
57 STATISTIC(NumTailCalls, "Number of tail calls");
59 // Forward declarations.
60 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
63 static SDValue Insert128BitVector(SDValue Result,
69 static SDValue Extract128BitVector(SDValue Vec,
74 static SDValue ConcatVectors(SDValue Lower, SDValue Upper, SelectionDAG &DAG);
77 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
78 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
79 /// simple subregister reference. Idx is an index in the 128 bits we
80 /// want. It need not be aligned to a 128-bit bounday. That makes
81 /// lowering EXTRACT_VECTOR_ELT operations easier.
82 static SDValue Extract128BitVector(SDValue Vec,
86 EVT VT = Vec.getValueType();
87 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
89 EVT ElVT = VT.getVectorElementType();
91 int Factor = VT.getSizeInBits() / 128;
93 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(),
95 VT.getVectorNumElements() / Factor);
97 // Extract from UNDEF is UNDEF.
98 if (Vec.getOpcode() == ISD::UNDEF)
99 return DAG.getNode(ISD::UNDEF, dl, ResultVT);
101 if (isa<ConstantSDNode>(Idx)) {
102 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
104 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
105 // we can match to VEXTRACTF128.
106 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
108 // This is the index of the first element of the 128-bit chunk
110 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
113 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
115 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
124 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
125 /// sets things up to match to an AVX VINSERTF128 instruction or a
126 /// simple superregister reference. Idx is an index in the 128 bits
127 /// we want. It need not be aligned to a 128-bit bounday. That makes
128 /// lowering INSERT_VECTOR_ELT operations easier.
129 static SDValue Insert128BitVector(SDValue Result,
134 if (isa<ConstantSDNode>(Idx)) {
135 EVT VT = Vec.getValueType();
136 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
138 EVT ElVT = VT.getVectorElementType();
140 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
142 EVT ResultVT = Result.getValueType();
144 // Insert the relevant 128 bits.
145 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
147 // This is the index of the first element of the 128-bit chunk
149 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
152 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
154 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
162 /// Given two vectors, concat them.
163 static SDValue ConcatVectors(SDValue Lower, SDValue Upper, SelectionDAG &DAG) {
164 DebugLoc dl = Lower.getDebugLoc();
166 assert(Lower.getValueType() == Upper.getValueType() && "Mismatched vectors!");
168 EVT VT = EVT::getVectorVT(*DAG.getContext(),
169 Lower.getValueType().getVectorElementType(),
170 Lower.getValueType().getVectorNumElements() * 2);
172 // TODO: Generalize to arbitrary vector length (this assumes 256-bit vectors).
173 assert(VT.getSizeInBits() == 256 && "Unsupported vector concat!");
175 // Insert the upper subvector.
176 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Upper,
178 // This is half the length of the result
179 // vector. Start inserting the upper 128
181 Lower.getValueType().getVectorNumElements(),
185 // Insert the lower subvector.
186 Vec = Insert128BitVector(Vec, Lower, DAG.getConstant(0, MVT::i32), DAG, dl);
190 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
191 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
192 bool is64Bit = Subtarget->is64Bit();
194 if (Subtarget->isTargetEnvMacho()) {
196 return new X8664_MachoTargetObjectFile();
197 return new TargetLoweringObjectFileMachO();
200 if (Subtarget->isTargetELF()) {
202 return new X8664_ELFTargetObjectFile(TM);
203 return new X8632_ELFTargetObjectFile(TM);
205 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
206 return new TargetLoweringObjectFileCOFF();
207 llvm_unreachable("unknown subtarget type");
210 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
211 : TargetLowering(TM, createTLOF(TM)) {
212 Subtarget = &TM.getSubtarget<X86Subtarget>();
213 X86ScalarSSEf64 = Subtarget->hasXMMInt();
214 X86ScalarSSEf32 = Subtarget->hasXMM();
215 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
217 RegInfo = TM.getRegisterInfo();
218 TD = getTargetData();
220 // Set up the TargetLowering object.
221 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
223 // X86 is weird, it always uses i8 for shift amounts and setcc results.
224 setBooleanContents(ZeroOrOneBooleanContent);
226 // For 64-bit since we have so many registers use the ILP scheduler, for
227 // 32-bit code use the register pressure specific scheduling.
228 if (Subtarget->is64Bit())
229 setSchedulingPreference(Sched::ILP);
231 setSchedulingPreference(Sched::RegPressure);
232 setStackPointerRegisterToSaveRestore(X86StackPtr);
234 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
235 // Setup Windows compiler runtime calls.
236 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
237 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
238 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2");
239 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2");
240 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
241 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
242 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C);
243 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C);
246 if (Subtarget->isTargetDarwin()) {
247 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
248 setUseUnderscoreSetJmp(false);
249 setUseUnderscoreLongJmp(false);
250 } else if (Subtarget->isTargetMingw()) {
251 // MS runtime is weird: it exports _setjmp, but longjmp!
252 setUseUnderscoreSetJmp(true);
253 setUseUnderscoreLongJmp(false);
255 setUseUnderscoreSetJmp(true);
256 setUseUnderscoreLongJmp(true);
259 // Set up the register classes.
260 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
261 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
262 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
263 if (Subtarget->is64Bit())
264 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
266 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
268 // We don't accept any truncstore of integer registers.
269 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
270 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
271 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
272 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
273 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
274 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
276 // SETOEQ and SETUNE require checking two conditions.
277 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
278 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
279 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
280 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
281 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
282 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
284 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
286 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
287 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
288 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
290 if (Subtarget->is64Bit()) {
291 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
292 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
293 } else if (!UseSoftFloat) {
294 // We have an algorithm for SSE2->double, and we turn this into a
295 // 64-bit FILD followed by conditional FADD for other targets.
296 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
297 // We have an algorithm for SSE2, and we turn this into a 64-bit
298 // FILD for other targets.
299 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
302 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
304 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
305 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
308 // SSE has no i16 to fp conversion, only i32
309 if (X86ScalarSSEf32) {
310 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
311 // f32 and f64 cases are Legal, f80 case is not
312 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
314 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
315 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
318 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
319 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
322 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
323 // are Legal, f80 is custom lowered.
324 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
325 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
327 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
329 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
330 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
332 if (X86ScalarSSEf32) {
333 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
334 // f32 and f64 cases are Legal, f80 case is not
335 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
337 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
338 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
341 // Handle FP_TO_UINT by promoting the destination to a larger signed
343 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
344 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
345 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
347 if (Subtarget->is64Bit()) {
348 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
349 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
350 } else if (!UseSoftFloat) {
351 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
352 // Expand FP_TO_UINT into a select.
353 // FIXME: We would like to use a Custom expander here eventually to do
354 // the optimal thing for SSE vs. the default expansion in the legalizer.
355 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
357 // With SSE3 we can use fisttpll to convert to a signed i64; without
358 // SSE, we're stuck with a fistpll.
359 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
362 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
363 if (!X86ScalarSSEf64) {
364 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
365 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
366 if (Subtarget->is64Bit()) {
367 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
368 // Without SSE, i64->f64 goes through memory.
369 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
373 // Scalar integer divide and remainder are lowered to use operations that
374 // produce two results, to match the available instructions. This exposes
375 // the two-result form to trivial CSE, which is able to combine x/y and x%y
376 // into a single instruction.
378 // Scalar integer multiply-high is also lowered to use two-result
379 // operations, to match the available instructions. However, plain multiply
380 // (low) operations are left as Legal, as there are single-result
381 // instructions for this in x86. Using the two-result multiply instructions
382 // when both high and low results are needed must be arranged by dagcombine.
383 for (unsigned i = 0, e = 4; i != e; ++i) {
385 setOperationAction(ISD::MULHS, VT, Expand);
386 setOperationAction(ISD::MULHU, VT, Expand);
387 setOperationAction(ISD::SDIV, VT, Expand);
388 setOperationAction(ISD::UDIV, VT, Expand);
389 setOperationAction(ISD::SREM, VT, Expand);
390 setOperationAction(ISD::UREM, VT, Expand);
392 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
393 setOperationAction(ISD::ADDC, VT, Custom);
394 setOperationAction(ISD::ADDE, VT, Custom);
395 setOperationAction(ISD::SUBC, VT, Custom);
396 setOperationAction(ISD::SUBE, VT, Custom);
399 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
400 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
401 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
402 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
403 if (Subtarget->is64Bit())
404 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
405 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
406 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
407 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
408 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
409 setOperationAction(ISD::FREM , MVT::f32 , Expand);
410 setOperationAction(ISD::FREM , MVT::f64 , Expand);
411 setOperationAction(ISD::FREM , MVT::f80 , Expand);
412 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
414 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
415 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
416 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
417 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
418 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
419 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
420 if (Subtarget->is64Bit()) {
421 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
422 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
425 if (Subtarget->hasPOPCNT()) {
426 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
428 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
429 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
430 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
431 if (Subtarget->is64Bit())
432 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
435 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
436 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
438 // These should be promoted to a larger select which is supported.
439 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
440 // X86 wants to expand cmov itself.
441 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
442 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
443 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
444 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
445 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
446 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
447 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
448 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
449 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
450 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
451 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
452 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
453 if (Subtarget->is64Bit()) {
454 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
455 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
457 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
460 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
461 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
462 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
463 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
464 if (Subtarget->is64Bit())
465 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
466 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
467 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
468 if (Subtarget->is64Bit()) {
469 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
470 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
471 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
472 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
473 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
475 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
476 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
477 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
478 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
479 if (Subtarget->is64Bit()) {
480 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
481 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
482 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
485 if (Subtarget->hasXMM())
486 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
488 // We may not have a libcall for MEMBARRIER so we should lower this.
489 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
491 // On X86 and X86-64, atomic operations are lowered to locked instructions.
492 // Locked instructions, in turn, have implicit fence semantics (all memory
493 // operations are flushed before issuing the locked instruction, and they
494 // are not buffered), so we can fold away the common pattern of
495 // fence-atomic-fence.
496 setShouldFoldAtomicFences(true);
498 // Expand certain atomics
499 for (unsigned i = 0, e = 4; i != e; ++i) {
501 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
502 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
505 if (!Subtarget->is64Bit()) {
506 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
507 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
508 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
509 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
510 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
511 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
512 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
515 // FIXME - use subtarget debug flags
516 if (!Subtarget->isTargetDarwin() &&
517 !Subtarget->isTargetELF() &&
518 !Subtarget->isTargetCygMing()) {
519 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
522 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
523 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
524 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
525 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
526 if (Subtarget->is64Bit()) {
527 setExceptionPointerRegister(X86::RAX);
528 setExceptionSelectorRegister(X86::RDX);
530 setExceptionPointerRegister(X86::EAX);
531 setExceptionSelectorRegister(X86::EDX);
533 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
534 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
536 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
538 setOperationAction(ISD::TRAP, MVT::Other, Legal);
540 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
541 setOperationAction(ISD::VASTART , MVT::Other, Custom);
542 setOperationAction(ISD::VAEND , MVT::Other, Expand);
543 if (Subtarget->is64Bit()) {
544 setOperationAction(ISD::VAARG , MVT::Other, Custom);
545 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
547 setOperationAction(ISD::VAARG , MVT::Other, Expand);
548 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
551 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
552 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
553 setOperationAction(ISD::DYNAMIC_STACKALLOC,
554 (Subtarget->is64Bit() ? MVT::i64 : MVT::i32),
555 (Subtarget->isTargetCOFF()
556 && !Subtarget->isTargetEnvMacho()
559 if (!UseSoftFloat && X86ScalarSSEf64) {
560 // f32 and f64 use SSE.
561 // Set up the FP register classes.
562 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
563 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
565 // Use ANDPD to simulate FABS.
566 setOperationAction(ISD::FABS , MVT::f64, Custom);
567 setOperationAction(ISD::FABS , MVT::f32, Custom);
569 // Use XORP to simulate FNEG.
570 setOperationAction(ISD::FNEG , MVT::f64, Custom);
571 setOperationAction(ISD::FNEG , MVT::f32, Custom);
573 // Use ANDPD and ORPD to simulate FCOPYSIGN.
574 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
575 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
577 // We don't support sin/cos/fmod
578 setOperationAction(ISD::FSIN , MVT::f64, Expand);
579 setOperationAction(ISD::FCOS , MVT::f64, Expand);
580 setOperationAction(ISD::FSIN , MVT::f32, Expand);
581 setOperationAction(ISD::FCOS , MVT::f32, Expand);
583 // Expand FP immediates into loads from the stack, except for the special
585 addLegalFPImmediate(APFloat(+0.0)); // xorpd
586 addLegalFPImmediate(APFloat(+0.0f)); // xorps
587 } else if (!UseSoftFloat && X86ScalarSSEf32) {
588 // Use SSE for f32, x87 for f64.
589 // Set up the FP register classes.
590 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
591 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
593 // Use ANDPS to simulate FABS.
594 setOperationAction(ISD::FABS , MVT::f32, Custom);
596 // Use XORP to simulate FNEG.
597 setOperationAction(ISD::FNEG , MVT::f32, Custom);
599 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
601 // Use ANDPS and ORPS to simulate FCOPYSIGN.
602 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
603 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
605 // We don't support sin/cos/fmod
606 setOperationAction(ISD::FSIN , MVT::f32, Expand);
607 setOperationAction(ISD::FCOS , MVT::f32, Expand);
609 // Special cases we handle for FP constants.
610 addLegalFPImmediate(APFloat(+0.0f)); // xorps
611 addLegalFPImmediate(APFloat(+0.0)); // FLD0
612 addLegalFPImmediate(APFloat(+1.0)); // FLD1
613 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
614 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
617 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
618 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
620 } else if (!UseSoftFloat) {
621 // f32 and f64 in x87.
622 // Set up the FP register classes.
623 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
624 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
626 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
627 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
628 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
629 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
632 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
633 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
635 addLegalFPImmediate(APFloat(+0.0)); // FLD0
636 addLegalFPImmediate(APFloat(+1.0)); // FLD1
637 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
638 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
639 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
640 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
641 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
642 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
645 // Long double always uses X87.
647 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
648 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
649 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
651 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
652 addLegalFPImmediate(TmpFlt); // FLD0
654 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
657 APFloat TmpFlt2(+1.0);
658 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
660 addLegalFPImmediate(TmpFlt2); // FLD1
661 TmpFlt2.changeSign();
662 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
666 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
667 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
671 // Always use a library call for pow.
672 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
673 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
674 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
676 setOperationAction(ISD::FLOG, MVT::f80, Expand);
677 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
678 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
679 setOperationAction(ISD::FEXP, MVT::f80, Expand);
680 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
682 // First set operation action for all vector types to either promote
683 // (for widening) or expand (for scalarization). Then we will selectively
684 // turn on ones that can be effectively codegen'd.
685 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
686 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
687 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
688 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
689 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
690 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
691 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
692 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
693 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
694 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
695 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
696 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
697 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
698 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
699 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
700 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
701 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
702 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
703 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
704 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
705 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
706 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
707 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
708 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
709 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
710 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
711 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
721 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
723 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
724 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
725 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
726 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
727 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
728 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
729 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
730 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
731 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
732 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
733 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
734 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
735 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
736 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
737 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
738 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
740 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
741 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
742 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
743 setTruncStoreAction((MVT::SimpleValueType)VT,
744 (MVT::SimpleValueType)InnerVT, Expand);
745 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
746 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
747 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
750 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
751 // with -msoft-float, disable use of MMX as well.
752 if (!UseSoftFloat && Subtarget->hasMMX()) {
753 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
754 // No operations on x86mmx supported, everything uses intrinsics.
757 // MMX-sized vectors (other than x86mmx) are expected to be expanded
758 // into smaller operations.
759 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
760 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
761 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
762 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
763 setOperationAction(ISD::AND, MVT::v8i8, Expand);
764 setOperationAction(ISD::AND, MVT::v4i16, Expand);
765 setOperationAction(ISD::AND, MVT::v2i32, Expand);
766 setOperationAction(ISD::AND, MVT::v1i64, Expand);
767 setOperationAction(ISD::OR, MVT::v8i8, Expand);
768 setOperationAction(ISD::OR, MVT::v4i16, Expand);
769 setOperationAction(ISD::OR, MVT::v2i32, Expand);
770 setOperationAction(ISD::OR, MVT::v1i64, Expand);
771 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
772 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
773 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
774 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
775 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
776 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
777 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
778 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
779 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
780 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
781 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
782 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
783 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
784 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
785 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
786 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
787 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
789 if (!UseSoftFloat && Subtarget->hasXMM()) {
790 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
792 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
793 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
794 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
795 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
796 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
797 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
798 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
799 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
800 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
801 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
802 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
803 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
806 if (!UseSoftFloat && Subtarget->hasXMMInt()) {
807 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
809 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
810 // registers cannot be used even for integer operations.
811 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
812 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
813 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
814 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
816 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
817 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
818 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
819 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
820 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
821 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
822 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
823 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
824 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
825 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
826 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
827 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
828 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
829 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
830 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
831 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
833 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
834 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
835 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
836 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
838 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
839 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
840 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
841 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
842 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
844 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
845 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
846 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
847 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
848 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
850 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
851 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
852 EVT VT = (MVT::SimpleValueType)i;
853 // Do not attempt to custom lower non-power-of-2 vectors
854 if (!isPowerOf2_32(VT.getVectorNumElements()))
856 // Do not attempt to custom lower non-128-bit vectors
857 if (!VT.is128BitVector())
859 setOperationAction(ISD::BUILD_VECTOR,
860 VT.getSimpleVT().SimpleTy, Custom);
861 setOperationAction(ISD::VECTOR_SHUFFLE,
862 VT.getSimpleVT().SimpleTy, Custom);
863 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
864 VT.getSimpleVT().SimpleTy, Custom);
867 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
868 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
869 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
870 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
871 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
872 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
874 if (Subtarget->is64Bit()) {
875 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
876 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
879 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
880 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
881 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
884 // Do not attempt to promote non-128-bit vectors
885 if (!VT.is128BitVector())
888 setOperationAction(ISD::AND, SVT, Promote);
889 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
890 setOperationAction(ISD::OR, SVT, Promote);
891 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
892 setOperationAction(ISD::XOR, SVT, Promote);
893 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
894 setOperationAction(ISD::LOAD, SVT, Promote);
895 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
896 setOperationAction(ISD::SELECT, SVT, Promote);
897 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
900 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
902 // Custom lower v2i64 and v2f64 selects.
903 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
904 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
905 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
906 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
908 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
909 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
912 if (Subtarget->hasSSE41()) {
913 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
914 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
915 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
916 setOperationAction(ISD::FRINT, MVT::f32, Legal);
917 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
918 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
919 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
920 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
921 setOperationAction(ISD::FRINT, MVT::f64, Legal);
922 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
924 // FIXME: Do we need to handle scalar-to-vector here?
925 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
927 // Can turn SHL into an integer multiply.
928 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
929 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
931 // i8 and i16 vectors are custom , because the source register and source
932 // source memory operand types are not the same width. f32 vectors are
933 // custom since the immediate controlling the insert encodes additional
935 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
936 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
937 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
938 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
940 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
941 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
942 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
943 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
945 if (Subtarget->is64Bit()) {
946 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
947 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
951 if (Subtarget->hasSSE2()) {
952 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
953 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
954 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
956 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
957 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
958 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
960 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
961 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
964 if (Subtarget->hasSSE42())
965 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
967 if (!UseSoftFloat && Subtarget->hasAVX()) {
968 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
969 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
970 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
971 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
972 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
974 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
975 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
976 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
977 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
979 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
980 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
981 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
982 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
983 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
984 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
986 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
987 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
988 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
989 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
990 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
991 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
993 // Custom lower build_vector, vector_shuffle, scalar_to_vector,
994 // insert_vector_elt extract_subvector and extract_vector_elt for
996 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
997 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE;
999 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
1000 // Do not attempt to custom lower non-256-bit vectors
1001 if (!isPowerOf2_32(MVT(VT).getVectorNumElements())
1002 || (MVT(VT).getSizeInBits() < 256))
1004 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1005 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1006 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1007 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1008 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1010 // Custom-lower insert_subvector and extract_subvector based on
1012 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1013 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE;
1015 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
1016 // Do not attempt to custom lower non-256-bit vectors
1017 if (!isPowerOf2_32(MVT(VT).getVectorNumElements()))
1020 if (MVT(VT).getSizeInBits() == 128) {
1021 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1023 else if (MVT(VT).getSizeInBits() == 256) {
1024 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1028 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1029 // Don't promote loads because we need them for VPERM vector index versions.
1031 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1032 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE;
1034 if (!isPowerOf2_32(MVT((MVT::SimpleValueType)VT).getVectorNumElements())
1035 || (MVT((MVT::SimpleValueType)VT).getSizeInBits() < 256))
1037 setOperationAction(ISD::AND, (MVT::SimpleValueType)VT, Promote);
1038 AddPromotedToType (ISD::AND, (MVT::SimpleValueType)VT, MVT::v4i64);
1039 setOperationAction(ISD::OR, (MVT::SimpleValueType)VT, Promote);
1040 AddPromotedToType (ISD::OR, (MVT::SimpleValueType)VT, MVT::v4i64);
1041 setOperationAction(ISD::XOR, (MVT::SimpleValueType)VT, Promote);
1042 AddPromotedToType (ISD::XOR, (MVT::SimpleValueType)VT, MVT::v4i64);
1043 //setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Promote);
1044 //AddPromotedToType (ISD::LOAD, (MVT::SimpleValueType)VT, MVT::v4i64);
1045 setOperationAction(ISD::SELECT, (MVT::SimpleValueType)VT, Promote);
1046 AddPromotedToType (ISD::SELECT, (MVT::SimpleValueType)VT, MVT::v4i64);
1050 // We want to custom lower some of our intrinsics.
1051 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1054 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1055 // handle type legalization for these operations here.
1057 // FIXME: We really should do custom legalization for addition and
1058 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1059 // than generic legalization for 64-bit multiplication-with-overflow, though.
1060 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1061 // Add/Sub/Mul with overflow operations are custom lowered.
1063 setOperationAction(ISD::SADDO, VT, Custom);
1064 setOperationAction(ISD::UADDO, VT, Custom);
1065 setOperationAction(ISD::SSUBO, VT, Custom);
1066 setOperationAction(ISD::USUBO, VT, Custom);
1067 setOperationAction(ISD::SMULO, VT, Custom);
1068 setOperationAction(ISD::UMULO, VT, Custom);
1071 // There are no 8-bit 3-address imul/mul instructions
1072 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1073 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1075 if (!Subtarget->is64Bit()) {
1076 // These libcalls are not available in 32-bit.
1077 setLibcallName(RTLIB::SHL_I128, 0);
1078 setLibcallName(RTLIB::SRL_I128, 0);
1079 setLibcallName(RTLIB::SRA_I128, 0);
1082 // We have target-specific dag combine patterns for the following nodes:
1083 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1084 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1085 setTargetDAGCombine(ISD::BUILD_VECTOR);
1086 setTargetDAGCombine(ISD::SELECT);
1087 setTargetDAGCombine(ISD::SHL);
1088 setTargetDAGCombine(ISD::SRA);
1089 setTargetDAGCombine(ISD::SRL);
1090 setTargetDAGCombine(ISD::OR);
1091 setTargetDAGCombine(ISD::AND);
1092 setTargetDAGCombine(ISD::ADD);
1093 setTargetDAGCombine(ISD::SUB);
1094 setTargetDAGCombine(ISD::STORE);
1095 setTargetDAGCombine(ISD::ZERO_EXTEND);
1096 if (Subtarget->is64Bit())
1097 setTargetDAGCombine(ISD::MUL);
1099 computeRegisterProperties();
1101 // On Darwin, -Os means optimize for size without hurting performance,
1102 // do not reduce the limit.
1103 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1104 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1105 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1106 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1107 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1108 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1109 setPrefLoopAlignment(16);
1110 benefitFromCodePlacementOpt = true;
1112 setPrefFunctionAlignment(4);
1116 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
1121 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1122 /// the desired ByVal argument alignment.
1123 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
1126 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1127 if (VTy->getBitWidth() == 128)
1129 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1130 unsigned EltAlign = 0;
1131 getMaxByValAlign(ATy->getElementType(), EltAlign);
1132 if (EltAlign > MaxAlign)
1133 MaxAlign = EltAlign;
1134 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
1135 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1136 unsigned EltAlign = 0;
1137 getMaxByValAlign(STy->getElementType(i), EltAlign);
1138 if (EltAlign > MaxAlign)
1139 MaxAlign = EltAlign;
1147 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1148 /// function arguments in the caller parameter area. For X86, aggregates
1149 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1150 /// are at 4-byte boundaries.
1151 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1152 if (Subtarget->is64Bit()) {
1153 // Max of 8 and alignment of type.
1154 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1161 if (Subtarget->hasXMM())
1162 getMaxByValAlign(Ty, Align);
1166 /// getOptimalMemOpType - Returns the target specific optimal type for load
1167 /// and store operations as a result of memset, memcpy, and memmove
1168 /// lowering. If DstAlign is zero that means it's safe to destination
1169 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1170 /// means there isn't a need to check it against alignment requirement,
1171 /// probably because the source does not need to be loaded. If
1172 /// 'NonScalarIntSafe' is true, that means it's safe to return a
1173 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1174 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1175 /// constant so it does not need to be loaded.
1176 /// It returns EVT::Other if the type should be determined using generic
1177 /// target-independent logic.
1179 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1180 unsigned DstAlign, unsigned SrcAlign,
1181 bool NonScalarIntSafe,
1183 MachineFunction &MF) const {
1184 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1185 // linux. This is because the stack realignment code can't handle certain
1186 // cases like PR2962. This should be removed when PR2962 is fixed.
1187 const Function *F = MF.getFunction();
1188 if (NonScalarIntSafe &&
1189 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1191 (Subtarget->isUnalignedMemAccessFast() ||
1192 ((DstAlign == 0 || DstAlign >= 16) &&
1193 (SrcAlign == 0 || SrcAlign >= 16))) &&
1194 Subtarget->getStackAlignment() >= 16) {
1195 if (Subtarget->hasSSE2())
1197 if (Subtarget->hasSSE1())
1199 } else if (!MemcpyStrSrc && Size >= 8 &&
1200 !Subtarget->is64Bit() &&
1201 Subtarget->getStackAlignment() >= 8 &&
1202 Subtarget->hasXMMInt()) {
1203 // Do not use f64 to lower memcpy if source is string constant. It's
1204 // better to use i32 to avoid the loads.
1208 if (Subtarget->is64Bit() && Size >= 8)
1213 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1214 /// current function. The returned value is a member of the
1215 /// MachineJumpTableInfo::JTEntryKind enum.
1216 unsigned X86TargetLowering::getJumpTableEncoding() const {
1217 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1219 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1220 Subtarget->isPICStyleGOT())
1221 return MachineJumpTableInfo::EK_Custom32;
1223 // Otherwise, use the normal jump table encoding heuristics.
1224 return TargetLowering::getJumpTableEncoding();
1228 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1229 const MachineBasicBlock *MBB,
1230 unsigned uid,MCContext &Ctx) const{
1231 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1232 Subtarget->isPICStyleGOT());
1233 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1235 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1236 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1239 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1241 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1242 SelectionDAG &DAG) const {
1243 if (!Subtarget->is64Bit())
1244 // This doesn't have DebugLoc associated with it, but is not really the
1245 // same as a Register.
1246 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1250 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1251 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1253 const MCExpr *X86TargetLowering::
1254 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1255 MCContext &Ctx) const {
1256 // X86-64 uses RIP relative addressing based on the jump table label.
1257 if (Subtarget->isPICStyleRIPRel())
1258 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1260 // Otherwise, the reference is relative to the PIC base.
1261 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1264 // FIXME: Why this routine is here? Move to RegInfo!
1265 std::pair<const TargetRegisterClass*, uint8_t>
1266 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1267 const TargetRegisterClass *RRC = 0;
1269 switch (VT.getSimpleVT().SimpleTy) {
1271 return TargetLowering::findRepresentativeClass(VT);
1272 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1273 RRC = (Subtarget->is64Bit()
1274 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1277 RRC = X86::VR64RegisterClass;
1279 case MVT::f32: case MVT::f64:
1280 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1281 case MVT::v4f32: case MVT::v2f64:
1282 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1284 RRC = X86::VR128RegisterClass;
1287 return std::make_pair(RRC, Cost);
1290 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1291 unsigned &Offset) const {
1292 if (!Subtarget->isTargetLinux())
1295 if (Subtarget->is64Bit()) {
1296 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1298 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1311 //===----------------------------------------------------------------------===//
1312 // Return Value Calling Convention Implementation
1313 //===----------------------------------------------------------------------===//
1315 #include "X86GenCallingConv.inc"
1318 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1319 const SmallVectorImpl<ISD::OutputArg> &Outs,
1320 LLVMContext &Context) const {
1321 SmallVector<CCValAssign, 16> RVLocs;
1322 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1324 return CCInfo.CheckReturn(Outs, RetCC_X86);
1328 X86TargetLowering::LowerReturn(SDValue Chain,
1329 CallingConv::ID CallConv, bool isVarArg,
1330 const SmallVectorImpl<ISD::OutputArg> &Outs,
1331 const SmallVectorImpl<SDValue> &OutVals,
1332 DebugLoc dl, SelectionDAG &DAG) const {
1333 MachineFunction &MF = DAG.getMachineFunction();
1334 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1336 SmallVector<CCValAssign, 16> RVLocs;
1337 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1338 RVLocs, *DAG.getContext());
1339 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1341 // Add the regs to the liveout set for the function.
1342 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1343 for (unsigned i = 0; i != RVLocs.size(); ++i)
1344 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1345 MRI.addLiveOut(RVLocs[i].getLocReg());
1349 SmallVector<SDValue, 6> RetOps;
1350 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1351 // Operand #1 = Bytes To Pop
1352 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1355 // Copy the result values into the output registers.
1356 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1357 CCValAssign &VA = RVLocs[i];
1358 assert(VA.isRegLoc() && "Can only return in registers!");
1359 SDValue ValToCopy = OutVals[i];
1360 EVT ValVT = ValToCopy.getValueType();
1362 // If this is x86-64, and we disabled SSE, we can't return FP values,
1363 // or SSE or MMX vectors.
1364 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1365 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1366 (Subtarget->is64Bit() && !Subtarget->hasXMM())) {
1367 report_fatal_error("SSE register return with SSE disabled");
1369 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1370 // llvm-gcc has never done it right and no one has noticed, so this
1371 // should be OK for now.
1372 if (ValVT == MVT::f64 &&
1373 (Subtarget->is64Bit() && !Subtarget->hasXMMInt()))
1374 report_fatal_error("SSE2 register return with SSE2 disabled");
1376 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1377 // the RET instruction and handled by the FP Stackifier.
1378 if (VA.getLocReg() == X86::ST0 ||
1379 VA.getLocReg() == X86::ST1) {
1380 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1381 // change the value to the FP stack register class.
1382 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1383 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1384 RetOps.push_back(ValToCopy);
1385 // Don't emit a copytoreg.
1389 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1390 // which is returned in RAX / RDX.
1391 if (Subtarget->is64Bit()) {
1392 if (ValVT == MVT::x86mmx) {
1393 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1394 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1395 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1397 // If we don't have SSE2 available, convert to v4f32 so the generated
1398 // register is legal.
1399 if (!Subtarget->hasSSE2())
1400 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1405 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1406 Flag = Chain.getValue(1);
1409 // The x86-64 ABI for returning structs by value requires that we copy
1410 // the sret argument into %rax for the return. We saved the argument into
1411 // a virtual register in the entry block, so now we copy the value out
1413 if (Subtarget->is64Bit() &&
1414 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1415 MachineFunction &MF = DAG.getMachineFunction();
1416 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1417 unsigned Reg = FuncInfo->getSRetReturnReg();
1419 "SRetReturnReg should have been set in LowerFormalArguments().");
1420 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1422 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1423 Flag = Chain.getValue(1);
1425 // RAX now acts like a return value.
1426 MRI.addLiveOut(X86::RAX);
1429 RetOps[0] = Chain; // Update chain.
1431 // Add the flag if we have it.
1433 RetOps.push_back(Flag);
1435 return DAG.getNode(X86ISD::RET_FLAG, dl,
1436 MVT::Other, &RetOps[0], RetOps.size());
1439 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const {
1440 if (N->getNumValues() != 1)
1442 if (!N->hasNUsesOfValue(1, 0))
1445 SDNode *Copy = *N->use_begin();
1446 if (Copy->getOpcode() != ISD::CopyToReg &&
1447 Copy->getOpcode() != ISD::FP_EXTEND)
1450 bool HasRet = false;
1451 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1453 if (UI->getOpcode() != X86ISD::RET_FLAG)
1462 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1463 ISD::NodeType ExtendKind) const {
1465 // TODO: Is this also valid on 32-bit?
1466 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1467 ReturnMVT = MVT::i8;
1469 ReturnMVT = MVT::i32;
1471 EVT MinVT = getRegisterType(Context, ReturnMVT);
1472 return VT.bitsLT(MinVT) ? MinVT : VT;
1475 /// LowerCallResult - Lower the result values of a call into the
1476 /// appropriate copies out of appropriate physical registers.
1479 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1480 CallingConv::ID CallConv, bool isVarArg,
1481 const SmallVectorImpl<ISD::InputArg> &Ins,
1482 DebugLoc dl, SelectionDAG &DAG,
1483 SmallVectorImpl<SDValue> &InVals) const {
1485 // Assign locations to each value returned by this call.
1486 SmallVector<CCValAssign, 16> RVLocs;
1487 bool Is64Bit = Subtarget->is64Bit();
1488 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1489 RVLocs, *DAG.getContext());
1490 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1492 // Copy all of the result registers out of their specified physreg.
1493 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1494 CCValAssign &VA = RVLocs[i];
1495 EVT CopyVT = VA.getValVT();
1497 // If this is x86-64, and we disabled SSE, we can't return FP values
1498 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1499 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasXMM())) {
1500 report_fatal_error("SSE register return with SSE disabled");
1505 // If this is a call to a function that returns an fp value on the floating
1506 // point stack, we must guarantee the the value is popped from the stack, so
1507 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1508 // if the return value is not used. We use the FpGET_ST0 instructions
1510 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1511 // If we prefer to use the value in xmm registers, copy it out as f80 and
1512 // use a truncate to move it from fp stack reg to xmm reg.
1513 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1514 bool isST0 = VA.getLocReg() == X86::ST0;
1516 if (CopyVT == MVT::f32) Opc = isST0 ? X86::FpGET_ST0_32:X86::FpGET_ST1_32;
1517 if (CopyVT == MVT::f64) Opc = isST0 ? X86::FpGET_ST0_64:X86::FpGET_ST1_64;
1518 if (CopyVT == MVT::f80) Opc = isST0 ? X86::FpGET_ST0_80:X86::FpGET_ST1_80;
1519 SDValue Ops[] = { Chain, InFlag };
1520 Chain = SDValue(DAG.getMachineNode(Opc, dl, CopyVT, MVT::Other, MVT::Glue,
1522 Val = Chain.getValue(0);
1524 // Round the f80 to the right size, which also moves it to the appropriate
1526 if (CopyVT != VA.getValVT())
1527 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1528 // This truncation won't change the value.
1529 DAG.getIntPtrConstant(1));
1531 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1532 CopyVT, InFlag).getValue(1);
1533 Val = Chain.getValue(0);
1535 InFlag = Chain.getValue(2);
1536 InVals.push_back(Val);
1543 //===----------------------------------------------------------------------===//
1544 // C & StdCall & Fast Calling Convention implementation
1545 //===----------------------------------------------------------------------===//
1546 // StdCall calling convention seems to be standard for many Windows' API
1547 // routines and around. It differs from C calling convention just a little:
1548 // callee should clean up the stack, not caller. Symbols should be also
1549 // decorated in some fancy way :) It doesn't support any vector arguments.
1550 // For info on fast calling convention see Fast Calling Convention (tail call)
1551 // implementation LowerX86_32FastCCCallTo.
1553 /// CallIsStructReturn - Determines whether a call uses struct return
1555 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1559 return Outs[0].Flags.isSRet();
1562 /// ArgsAreStructReturn - Determines whether a function uses struct
1563 /// return semantics.
1565 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1569 return Ins[0].Flags.isSRet();
1572 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1573 /// by "Src" to address "Dst" with size and alignment information specified by
1574 /// the specific parameter attribute. The copy will be passed as a byval
1575 /// function parameter.
1577 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1578 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1580 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1582 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1583 /*isVolatile*/false, /*AlwaysInline=*/true,
1584 MachinePointerInfo(), MachinePointerInfo());
1587 /// IsTailCallConvention - Return true if the calling convention is one that
1588 /// supports tail call optimization.
1589 static bool IsTailCallConvention(CallingConv::ID CC) {
1590 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1593 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1594 if (!CI->isTailCall())
1598 CallingConv::ID CalleeCC = CS.getCallingConv();
1599 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1605 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1606 /// a tailcall target by changing its ABI.
1607 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1608 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1612 X86TargetLowering::LowerMemArgument(SDValue Chain,
1613 CallingConv::ID CallConv,
1614 const SmallVectorImpl<ISD::InputArg> &Ins,
1615 DebugLoc dl, SelectionDAG &DAG,
1616 const CCValAssign &VA,
1617 MachineFrameInfo *MFI,
1619 // Create the nodes corresponding to a load from this parameter slot.
1620 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1621 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1622 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1625 // If value is passed by pointer we have address passed instead of the value
1627 if (VA.getLocInfo() == CCValAssign::Indirect)
1628 ValVT = VA.getLocVT();
1630 ValVT = VA.getValVT();
1632 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1633 // changed with more analysis.
1634 // In case of tail call optimization mark all arguments mutable. Since they
1635 // could be overwritten by lowering of arguments in case of a tail call.
1636 if (Flags.isByVal()) {
1637 unsigned Bytes = Flags.getByValSize();
1638 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1639 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1640 return DAG.getFrameIndex(FI, getPointerTy());
1642 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1643 VA.getLocMemOffset(), isImmutable);
1644 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1645 return DAG.getLoad(ValVT, dl, Chain, FIN,
1646 MachinePointerInfo::getFixedStack(FI),
1652 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1653 CallingConv::ID CallConv,
1655 const SmallVectorImpl<ISD::InputArg> &Ins,
1658 SmallVectorImpl<SDValue> &InVals)
1660 MachineFunction &MF = DAG.getMachineFunction();
1661 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1663 const Function* Fn = MF.getFunction();
1664 if (Fn->hasExternalLinkage() &&
1665 Subtarget->isTargetCygMing() &&
1666 Fn->getName() == "main")
1667 FuncInfo->setForceFramePointer(true);
1669 MachineFrameInfo *MFI = MF.getFrameInfo();
1670 bool Is64Bit = Subtarget->is64Bit();
1671 bool IsWin64 = Subtarget->isTargetWin64();
1673 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1674 "Var args not supported with calling convention fastcc or ghc");
1676 // Assign locations to all of the incoming arguments.
1677 SmallVector<CCValAssign, 16> ArgLocs;
1678 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1679 ArgLocs, *DAG.getContext());
1681 // Allocate shadow area for Win64
1683 CCInfo.AllocateStack(32, 8);
1686 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1688 unsigned LastVal = ~0U;
1690 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1691 CCValAssign &VA = ArgLocs[i];
1692 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1694 assert(VA.getValNo() != LastVal &&
1695 "Don't support value assigned to multiple locs yet");
1696 LastVal = VA.getValNo();
1698 if (VA.isRegLoc()) {
1699 EVT RegVT = VA.getLocVT();
1700 TargetRegisterClass *RC = NULL;
1701 if (RegVT == MVT::i32)
1702 RC = X86::GR32RegisterClass;
1703 else if (Is64Bit && RegVT == MVT::i64)
1704 RC = X86::GR64RegisterClass;
1705 else if (RegVT == MVT::f32)
1706 RC = X86::FR32RegisterClass;
1707 else if (RegVT == MVT::f64)
1708 RC = X86::FR64RegisterClass;
1709 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1710 RC = X86::VR256RegisterClass;
1711 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1712 RC = X86::VR128RegisterClass;
1713 else if (RegVT == MVT::x86mmx)
1714 RC = X86::VR64RegisterClass;
1716 llvm_unreachable("Unknown argument type!");
1718 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1719 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1721 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1722 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1724 if (VA.getLocInfo() == CCValAssign::SExt)
1725 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1726 DAG.getValueType(VA.getValVT()));
1727 else if (VA.getLocInfo() == CCValAssign::ZExt)
1728 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1729 DAG.getValueType(VA.getValVT()));
1730 else if (VA.getLocInfo() == CCValAssign::BCvt)
1731 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1733 if (VA.isExtInLoc()) {
1734 // Handle MMX values passed in XMM regs.
1735 if (RegVT.isVector()) {
1736 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1739 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1742 assert(VA.isMemLoc());
1743 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1746 // If value is passed via pointer - do a load.
1747 if (VA.getLocInfo() == CCValAssign::Indirect)
1748 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1749 MachinePointerInfo(), false, false, 0);
1751 InVals.push_back(ArgValue);
1754 // The x86-64 ABI for returning structs by value requires that we copy
1755 // the sret argument into %rax for the return. Save the argument into
1756 // a virtual register so that we can access it from the return points.
1757 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1758 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1759 unsigned Reg = FuncInfo->getSRetReturnReg();
1761 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1762 FuncInfo->setSRetReturnReg(Reg);
1764 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1765 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1768 unsigned StackSize = CCInfo.getNextStackOffset();
1769 // Align stack specially for tail calls.
1770 if (FuncIsMadeTailCallSafe(CallConv))
1771 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1773 // If the function takes variable number of arguments, make a frame index for
1774 // the start of the first vararg value... for expansion of llvm.va_start.
1776 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1777 CallConv != CallingConv::X86_ThisCall)) {
1778 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1781 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1783 // FIXME: We should really autogenerate these arrays
1784 static const unsigned GPR64ArgRegsWin64[] = {
1785 X86::RCX, X86::RDX, X86::R8, X86::R9
1787 static const unsigned GPR64ArgRegs64Bit[] = {
1788 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1790 static const unsigned XMMArgRegs64Bit[] = {
1791 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1792 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1794 const unsigned *GPR64ArgRegs;
1795 unsigned NumXMMRegs = 0;
1798 // The XMM registers which might contain var arg parameters are shadowed
1799 // in their paired GPR. So we only need to save the GPR to their home
1801 TotalNumIntRegs = 4;
1802 GPR64ArgRegs = GPR64ArgRegsWin64;
1804 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1805 GPR64ArgRegs = GPR64ArgRegs64Bit;
1807 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, TotalNumXMMRegs);
1809 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1812 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1813 assert(!(NumXMMRegs && !Subtarget->hasXMM()) &&
1814 "SSE register cannot be used when SSE is disabled!");
1815 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1816 "SSE register cannot be used when SSE is disabled!");
1817 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasXMM())
1818 // Kernel mode asks for SSE to be disabled, so don't push them
1820 TotalNumXMMRegs = 0;
1823 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1824 // Get to the caller-allocated home save location. Add 8 to account
1825 // for the return address.
1826 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1827 FuncInfo->setRegSaveFrameIndex(
1828 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1829 // Fixup to set vararg frame on shadow area (4 x i64).
1831 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1833 // For X86-64, if there are vararg parameters that are passed via
1834 // registers, then we must store them to their spots on the stack so they
1835 // may be loaded by deferencing the result of va_next.
1836 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1837 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1838 FuncInfo->setRegSaveFrameIndex(
1839 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1843 // Store the integer parameter registers.
1844 SmallVector<SDValue, 8> MemOps;
1845 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1847 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1848 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1849 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1850 DAG.getIntPtrConstant(Offset));
1851 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1852 X86::GR64RegisterClass);
1853 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1855 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1856 MachinePointerInfo::getFixedStack(
1857 FuncInfo->getRegSaveFrameIndex(), Offset),
1859 MemOps.push_back(Store);
1863 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1864 // Now store the XMM (fp + vector) parameter registers.
1865 SmallVector<SDValue, 11> SaveXMMOps;
1866 SaveXMMOps.push_back(Chain);
1868 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1869 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1870 SaveXMMOps.push_back(ALVal);
1872 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1873 FuncInfo->getRegSaveFrameIndex()));
1874 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1875 FuncInfo->getVarArgsFPOffset()));
1877 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1878 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
1879 X86::VR128RegisterClass);
1880 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1881 SaveXMMOps.push_back(Val);
1883 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1885 &SaveXMMOps[0], SaveXMMOps.size()));
1888 if (!MemOps.empty())
1889 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1890 &MemOps[0], MemOps.size());
1894 // Some CCs need callee pop.
1895 if (Subtarget->IsCalleePop(isVarArg, CallConv)) {
1896 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
1898 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
1899 // If this is an sret function, the return should pop the hidden pointer.
1900 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
1901 FuncInfo->setBytesToPopOnReturn(4);
1905 // RegSaveFrameIndex is X86-64 only.
1906 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
1907 if (CallConv == CallingConv::X86_FastCall ||
1908 CallConv == CallingConv::X86_ThisCall)
1909 // fastcc functions can't have varargs.
1910 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
1917 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1918 SDValue StackPtr, SDValue Arg,
1919 DebugLoc dl, SelectionDAG &DAG,
1920 const CCValAssign &VA,
1921 ISD::ArgFlagsTy Flags) const {
1922 unsigned LocMemOffset = VA.getLocMemOffset();
1923 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1924 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1925 if (Flags.isByVal())
1926 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1928 return DAG.getStore(Chain, dl, Arg, PtrOff,
1929 MachinePointerInfo::getStack(LocMemOffset),
1933 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1934 /// optimization is performed and it is required.
1936 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1937 SDValue &OutRetAddr, SDValue Chain,
1938 bool IsTailCall, bool Is64Bit,
1939 int FPDiff, DebugLoc dl) const {
1940 // Adjust the Return address stack slot.
1941 EVT VT = getPointerTy();
1942 OutRetAddr = getReturnAddressFrameIndex(DAG);
1944 // Load the "old" Return address.
1945 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
1947 return SDValue(OutRetAddr.getNode(), 1);
1950 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
1951 /// optimization is performed and it is required (FPDiff!=0).
1953 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1954 SDValue Chain, SDValue RetAddrFrIdx,
1955 bool Is64Bit, int FPDiff, DebugLoc dl) {
1956 // Store the return address to the appropriate stack slot.
1957 if (!FPDiff) return Chain;
1958 // Calculate the new stack slot for the return address.
1959 int SlotSize = Is64Bit ? 8 : 4;
1960 int NewReturnAddrFI =
1961 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
1962 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1963 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1964 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1965 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
1971 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1972 CallingConv::ID CallConv, bool isVarArg,
1974 const SmallVectorImpl<ISD::OutputArg> &Outs,
1975 const SmallVectorImpl<SDValue> &OutVals,
1976 const SmallVectorImpl<ISD::InputArg> &Ins,
1977 DebugLoc dl, SelectionDAG &DAG,
1978 SmallVectorImpl<SDValue> &InVals) const {
1979 MachineFunction &MF = DAG.getMachineFunction();
1980 bool Is64Bit = Subtarget->is64Bit();
1981 bool IsWin64 = Subtarget->isTargetWin64();
1982 bool IsStructRet = CallIsStructReturn(Outs);
1983 bool IsSibcall = false;
1986 // Check if it's really possible to do a tail call.
1987 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1988 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1989 Outs, OutVals, Ins, DAG);
1991 // Sibcalls are automatically detected tailcalls which do not require
1993 if (!GuaranteedTailCallOpt && isTailCall)
2000 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2001 "Var args not supported with calling convention fastcc or ghc");
2003 // Analyze operands of the call, assigning locations to each operand.
2004 SmallVector<CCValAssign, 16> ArgLocs;
2005 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
2006 ArgLocs, *DAG.getContext());
2008 // Allocate shadow area for Win64
2010 CCInfo.AllocateStack(32, 8);
2013 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2015 // Get a count of how many bytes are to be pushed on the stack.
2016 unsigned NumBytes = CCInfo.getNextStackOffset();
2018 // This is a sibcall. The memory operands are available in caller's
2019 // own caller's stack.
2021 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv))
2022 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2025 if (isTailCall && !IsSibcall) {
2026 // Lower arguments at fp - stackoffset + fpdiff.
2027 unsigned NumBytesCallerPushed =
2028 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2029 FPDiff = NumBytesCallerPushed - NumBytes;
2031 // Set the delta of movement of the returnaddr stackslot.
2032 // But only set if delta is greater than previous delta.
2033 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2034 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2038 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2040 SDValue RetAddrFrIdx;
2041 // Load return address for tail calls.
2042 if (isTailCall && FPDiff)
2043 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2044 Is64Bit, FPDiff, dl);
2046 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2047 SmallVector<SDValue, 8> MemOpChains;
2050 // Walk the register/memloc assignments, inserting copies/loads. In the case
2051 // of tail call optimization arguments are handle later.
2052 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2053 CCValAssign &VA = ArgLocs[i];
2054 EVT RegVT = VA.getLocVT();
2055 SDValue Arg = OutVals[i];
2056 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2057 bool isByVal = Flags.isByVal();
2059 // Promote the value if needed.
2060 switch (VA.getLocInfo()) {
2061 default: llvm_unreachable("Unknown loc info!");
2062 case CCValAssign::Full: break;
2063 case CCValAssign::SExt:
2064 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2066 case CCValAssign::ZExt:
2067 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2069 case CCValAssign::AExt:
2070 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2071 // Special case: passing MMX values in XMM registers.
2072 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2073 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2074 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2076 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2078 case CCValAssign::BCvt:
2079 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2081 case CCValAssign::Indirect: {
2082 // Store the argument.
2083 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2084 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2085 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2086 MachinePointerInfo::getFixedStack(FI),
2093 if (VA.isRegLoc()) {
2094 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2095 if (isVarArg && IsWin64) {
2096 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2097 // shadow reg if callee is a varargs function.
2098 unsigned ShadowReg = 0;
2099 switch (VA.getLocReg()) {
2100 case X86::XMM0: ShadowReg = X86::RCX; break;
2101 case X86::XMM1: ShadowReg = X86::RDX; break;
2102 case X86::XMM2: ShadowReg = X86::R8; break;
2103 case X86::XMM3: ShadowReg = X86::R9; break;
2106 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2108 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2109 assert(VA.isMemLoc());
2110 if (StackPtr.getNode() == 0)
2111 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2112 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2113 dl, DAG, VA, Flags));
2117 if (!MemOpChains.empty())
2118 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2119 &MemOpChains[0], MemOpChains.size());
2121 // Build a sequence of copy-to-reg nodes chained together with token chain
2122 // and flag operands which copy the outgoing args into registers.
2124 // Tail call byval lowering might overwrite argument registers so in case of
2125 // tail call optimization the copies to registers are lowered later.
2127 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2128 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2129 RegsToPass[i].second, InFlag);
2130 InFlag = Chain.getValue(1);
2133 if (Subtarget->isPICStyleGOT()) {
2134 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2137 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2138 DAG.getNode(X86ISD::GlobalBaseReg,
2139 DebugLoc(), getPointerTy()),
2141 InFlag = Chain.getValue(1);
2143 // If we are tail calling and generating PIC/GOT style code load the
2144 // address of the callee into ECX. The value in ecx is used as target of
2145 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2146 // for tail calls on PIC/GOT architectures. Normally we would just put the
2147 // address of GOT into ebx and then call target@PLT. But for tail calls
2148 // ebx would be restored (since ebx is callee saved) before jumping to the
2151 // Note: The actual moving to ECX is done further down.
2152 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2153 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2154 !G->getGlobal()->hasProtectedVisibility())
2155 Callee = LowerGlobalAddress(Callee, DAG);
2156 else if (isa<ExternalSymbolSDNode>(Callee))
2157 Callee = LowerExternalSymbol(Callee, DAG);
2161 if (Is64Bit && isVarArg && !IsWin64) {
2162 // From AMD64 ABI document:
2163 // For calls that may call functions that use varargs or stdargs
2164 // (prototype-less calls or calls to functions containing ellipsis (...) in
2165 // the declaration) %al is used as hidden argument to specify the number
2166 // of SSE registers used. The contents of %al do not need to match exactly
2167 // the number of registers, but must be an ubound on the number of SSE
2168 // registers used and is in the range 0 - 8 inclusive.
2170 // Count the number of XMM registers allocated.
2171 static const unsigned XMMArgRegs[] = {
2172 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2173 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2175 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2176 assert((Subtarget->hasXMM() || !NumXMMRegs)
2177 && "SSE registers cannot be used when SSE is disabled");
2179 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2180 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2181 InFlag = Chain.getValue(1);
2185 // For tail calls lower the arguments to the 'real' stack slot.
2187 // Force all the incoming stack arguments to be loaded from the stack
2188 // before any new outgoing arguments are stored to the stack, because the
2189 // outgoing stack slots may alias the incoming argument stack slots, and
2190 // the alias isn't otherwise explicit. This is slightly more conservative
2191 // than necessary, because it means that each store effectively depends
2192 // on every argument instead of just those arguments it would clobber.
2193 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2195 SmallVector<SDValue, 8> MemOpChains2;
2198 // Do not flag preceding copytoreg stuff together with the following stuff.
2200 if (GuaranteedTailCallOpt) {
2201 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2202 CCValAssign &VA = ArgLocs[i];
2205 assert(VA.isMemLoc());
2206 SDValue Arg = OutVals[i];
2207 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2208 // Create frame index.
2209 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2210 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2211 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2212 FIN = DAG.getFrameIndex(FI, getPointerTy());
2214 if (Flags.isByVal()) {
2215 // Copy relative to framepointer.
2216 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2217 if (StackPtr.getNode() == 0)
2218 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2220 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2222 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2226 // Store relative to framepointer.
2227 MemOpChains2.push_back(
2228 DAG.getStore(ArgChain, dl, Arg, FIN,
2229 MachinePointerInfo::getFixedStack(FI),
2235 if (!MemOpChains2.empty())
2236 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2237 &MemOpChains2[0], MemOpChains2.size());
2239 // Copy arguments to their registers.
2240 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2241 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2242 RegsToPass[i].second, InFlag);
2243 InFlag = Chain.getValue(1);
2247 // Store the return address to the appropriate stack slot.
2248 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2252 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2253 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2254 // In the 64-bit large code model, we have to make all calls
2255 // through a register, since the call instruction's 32-bit
2256 // pc-relative offset may not be large enough to hold the whole
2258 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2259 // If the callee is a GlobalAddress node (quite common, every direct call
2260 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2263 // We should use extra load for direct calls to dllimported functions in
2265 const GlobalValue *GV = G->getGlobal();
2266 if (!GV->hasDLLImportLinkage()) {
2267 unsigned char OpFlags = 0;
2269 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2270 // external symbols most go through the PLT in PIC mode. If the symbol
2271 // has hidden or protected visibility, or if it is static or local, then
2272 // we don't need to use the PLT - we can directly call it.
2273 if (Subtarget->isTargetELF() &&
2274 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2275 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2276 OpFlags = X86II::MO_PLT;
2277 } else if (Subtarget->isPICStyleStubAny() &&
2278 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2279 (!Subtarget->getTargetTriple().isMacOSX() ||
2280 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2281 // PC-relative references to external symbols should go through $stub,
2282 // unless we're building with the leopard linker or later, which
2283 // automatically synthesizes these stubs.
2284 OpFlags = X86II::MO_DARWIN_STUB;
2287 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2288 G->getOffset(), OpFlags);
2290 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2291 unsigned char OpFlags = 0;
2293 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2294 // external symbols should go through the PLT.
2295 if (Subtarget->isTargetELF() &&
2296 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2297 OpFlags = X86II::MO_PLT;
2298 } else if (Subtarget->isPICStyleStubAny() &&
2299 (!Subtarget->getTargetTriple().isMacOSX() ||
2300 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2301 // PC-relative references to external symbols should go through $stub,
2302 // unless we're building with the leopard linker or later, which
2303 // automatically synthesizes these stubs.
2304 OpFlags = X86II::MO_DARWIN_STUB;
2307 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2311 // Returns a chain & a flag for retval copy to use.
2312 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2313 SmallVector<SDValue, 8> Ops;
2315 if (!IsSibcall && isTailCall) {
2316 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2317 DAG.getIntPtrConstant(0, true), InFlag);
2318 InFlag = Chain.getValue(1);
2321 Ops.push_back(Chain);
2322 Ops.push_back(Callee);
2325 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2327 // Add argument registers to the end of the list so that they are known live
2329 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2330 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2331 RegsToPass[i].second.getValueType()));
2333 // Add an implicit use GOT pointer in EBX.
2334 if (!isTailCall && Subtarget->isPICStyleGOT())
2335 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2337 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2338 if (Is64Bit && isVarArg && !IsWin64)
2339 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2341 if (InFlag.getNode())
2342 Ops.push_back(InFlag);
2346 //// If this is the first return lowered for this function, add the regs
2347 //// to the liveout set for the function.
2348 // This isn't right, although it's probably harmless on x86; liveouts
2349 // should be computed from returns not tail calls. Consider a void
2350 // function making a tail call to a function returning int.
2351 return DAG.getNode(X86ISD::TC_RETURN, dl,
2352 NodeTys, &Ops[0], Ops.size());
2355 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2356 InFlag = Chain.getValue(1);
2358 // Create the CALLSEQ_END node.
2359 unsigned NumBytesForCalleeToPush;
2360 if (Subtarget->IsCalleePop(isVarArg, CallConv))
2361 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2362 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2363 // If this is a call to a struct-return function, the callee
2364 // pops the hidden struct pointer, so we have to push it back.
2365 // This is common for Darwin/X86, Linux & Mingw32 targets.
2366 NumBytesForCalleeToPush = 4;
2368 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2370 // Returns a flag for retval copy to use.
2372 Chain = DAG.getCALLSEQ_END(Chain,
2373 DAG.getIntPtrConstant(NumBytes, true),
2374 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2377 InFlag = Chain.getValue(1);
2380 // Handle result values, copying them out of physregs into vregs that we
2382 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2383 Ins, dl, DAG, InVals);
2387 //===----------------------------------------------------------------------===//
2388 // Fast Calling Convention (tail call) implementation
2389 //===----------------------------------------------------------------------===//
2391 // Like std call, callee cleans arguments, convention except that ECX is
2392 // reserved for storing the tail called function address. Only 2 registers are
2393 // free for argument passing (inreg). Tail call optimization is performed
2395 // * tailcallopt is enabled
2396 // * caller/callee are fastcc
2397 // On X86_64 architecture with GOT-style position independent code only local
2398 // (within module) calls are supported at the moment.
2399 // To keep the stack aligned according to platform abi the function
2400 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2401 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2402 // If a tail called function callee has more arguments than the caller the
2403 // caller needs to make sure that there is room to move the RETADDR to. This is
2404 // achieved by reserving an area the size of the argument delta right after the
2405 // original REtADDR, but before the saved framepointer or the spilled registers
2406 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2418 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2419 /// for a 16 byte align requirement.
2421 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2422 SelectionDAG& DAG) const {
2423 MachineFunction &MF = DAG.getMachineFunction();
2424 const TargetMachine &TM = MF.getTarget();
2425 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2426 unsigned StackAlignment = TFI.getStackAlignment();
2427 uint64_t AlignMask = StackAlignment - 1;
2428 int64_t Offset = StackSize;
2429 uint64_t SlotSize = TD->getPointerSize();
2430 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2431 // Number smaller than 12 so just add the difference.
2432 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2434 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2435 Offset = ((~AlignMask) & Offset) + StackAlignment +
2436 (StackAlignment-SlotSize);
2441 /// MatchingStackOffset - Return true if the given stack call argument is
2442 /// already available in the same position (relatively) of the caller's
2443 /// incoming argument stack.
2445 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2446 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2447 const X86InstrInfo *TII) {
2448 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2450 if (Arg.getOpcode() == ISD::CopyFromReg) {
2451 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2452 if (!TargetRegisterInfo::isVirtualRegister(VR))
2454 MachineInstr *Def = MRI->getVRegDef(VR);
2457 if (!Flags.isByVal()) {
2458 if (!TII->isLoadFromStackSlot(Def, FI))
2461 unsigned Opcode = Def->getOpcode();
2462 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2463 Def->getOperand(1).isFI()) {
2464 FI = Def->getOperand(1).getIndex();
2465 Bytes = Flags.getByValSize();
2469 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2470 if (Flags.isByVal())
2471 // ByVal argument is passed in as a pointer but it's now being
2472 // dereferenced. e.g.
2473 // define @foo(%struct.X* %A) {
2474 // tail call @bar(%struct.X* byval %A)
2477 SDValue Ptr = Ld->getBasePtr();
2478 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2481 FI = FINode->getIndex();
2485 assert(FI != INT_MAX);
2486 if (!MFI->isFixedObjectIndex(FI))
2488 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2491 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2492 /// for tail call optimization. Targets which want to do tail call
2493 /// optimization should implement this function.
2495 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2496 CallingConv::ID CalleeCC,
2498 bool isCalleeStructRet,
2499 bool isCallerStructRet,
2500 const SmallVectorImpl<ISD::OutputArg> &Outs,
2501 const SmallVectorImpl<SDValue> &OutVals,
2502 const SmallVectorImpl<ISD::InputArg> &Ins,
2503 SelectionDAG& DAG) const {
2504 if (!IsTailCallConvention(CalleeCC) &&
2505 CalleeCC != CallingConv::C)
2508 // If -tailcallopt is specified, make fastcc functions tail-callable.
2509 const MachineFunction &MF = DAG.getMachineFunction();
2510 const Function *CallerF = DAG.getMachineFunction().getFunction();
2511 CallingConv::ID CallerCC = CallerF->getCallingConv();
2512 bool CCMatch = CallerCC == CalleeCC;
2514 if (GuaranteedTailCallOpt) {
2515 if (IsTailCallConvention(CalleeCC) && CCMatch)
2520 // Look for obvious safe cases to perform tail call optimization that do not
2521 // require ABI changes. This is what gcc calls sibcall.
2523 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2524 // emit a special epilogue.
2525 if (RegInfo->needsStackRealignment(MF))
2528 // Also avoid sibcall optimization if either caller or callee uses struct
2529 // return semantics.
2530 if (isCalleeStructRet || isCallerStructRet)
2533 // Do not sibcall optimize vararg calls unless all arguments are passed via
2535 if (isVarArg && !Outs.empty()) {
2536 SmallVector<CCValAssign, 16> ArgLocs;
2537 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
2538 ArgLocs, *DAG.getContext());
2540 // Allocate shadow area for Win64
2541 if (Subtarget->isTargetWin64()) {
2542 CCInfo.AllocateStack(32, 8);
2545 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2546 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2547 if (!ArgLocs[i].isRegLoc())
2551 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack.
2552 // Therefore if it's not used by the call it is not safe to optimize this into
2554 bool Unused = false;
2555 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2562 SmallVector<CCValAssign, 16> RVLocs;
2563 CCState CCInfo(CalleeCC, false, getTargetMachine(),
2564 RVLocs, *DAG.getContext());
2565 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2566 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2567 CCValAssign &VA = RVLocs[i];
2568 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2573 // If the calling conventions do not match, then we'd better make sure the
2574 // results are returned in the same way as what the caller expects.
2576 SmallVector<CCValAssign, 16> RVLocs1;
2577 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
2578 RVLocs1, *DAG.getContext());
2579 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2581 SmallVector<CCValAssign, 16> RVLocs2;
2582 CCState CCInfo2(CallerCC, false, getTargetMachine(),
2583 RVLocs2, *DAG.getContext());
2584 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2586 if (RVLocs1.size() != RVLocs2.size())
2588 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2589 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2591 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2593 if (RVLocs1[i].isRegLoc()) {
2594 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2597 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2603 // If the callee takes no arguments then go on to check the results of the
2605 if (!Outs.empty()) {
2606 // Check if stack adjustment is needed. For now, do not do this if any
2607 // argument is passed on the stack.
2608 SmallVector<CCValAssign, 16> ArgLocs;
2609 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
2610 ArgLocs, *DAG.getContext());
2612 // Allocate shadow area for Win64
2613 if (Subtarget->isTargetWin64()) {
2614 CCInfo.AllocateStack(32, 8);
2617 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2618 if (CCInfo.getNextStackOffset()) {
2619 MachineFunction &MF = DAG.getMachineFunction();
2620 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2623 // Check if the arguments are already laid out in the right way as
2624 // the caller's fixed stack objects.
2625 MachineFrameInfo *MFI = MF.getFrameInfo();
2626 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2627 const X86InstrInfo *TII =
2628 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2629 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2630 CCValAssign &VA = ArgLocs[i];
2631 SDValue Arg = OutVals[i];
2632 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2633 if (VA.getLocInfo() == CCValAssign::Indirect)
2635 if (!VA.isRegLoc()) {
2636 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2643 // If the tailcall address may be in a register, then make sure it's
2644 // possible to register allocate for it. In 32-bit, the call address can
2645 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2646 // callee-saved registers are restored. These happen to be the same
2647 // registers used to pass 'inreg' arguments so watch out for those.
2648 if (!Subtarget->is64Bit() &&
2649 !isa<GlobalAddressSDNode>(Callee) &&
2650 !isa<ExternalSymbolSDNode>(Callee)) {
2651 unsigned NumInRegs = 0;
2652 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2653 CCValAssign &VA = ArgLocs[i];
2656 unsigned Reg = VA.getLocReg();
2659 case X86::EAX: case X86::EDX: case X86::ECX:
2660 if (++NumInRegs == 3)
2668 // An stdcall caller is expected to clean up its arguments; the callee
2669 // isn't going to do that.
2670 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2677 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2678 return X86::createFastISel(funcInfo);
2682 //===----------------------------------------------------------------------===//
2683 // Other Lowering Hooks
2684 //===----------------------------------------------------------------------===//
2686 static bool MayFoldLoad(SDValue Op) {
2687 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2690 static bool MayFoldIntoStore(SDValue Op) {
2691 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2694 static bool isTargetShuffle(unsigned Opcode) {
2696 default: return false;
2697 case X86ISD::PSHUFD:
2698 case X86ISD::PSHUFHW:
2699 case X86ISD::PSHUFLW:
2700 case X86ISD::SHUFPD:
2701 case X86ISD::PALIGN:
2702 case X86ISD::SHUFPS:
2703 case X86ISD::MOVLHPS:
2704 case X86ISD::MOVLHPD:
2705 case X86ISD::MOVHLPS:
2706 case X86ISD::MOVLPS:
2707 case X86ISD::MOVLPD:
2708 case X86ISD::MOVSHDUP:
2709 case X86ISD::MOVSLDUP:
2710 case X86ISD::MOVDDUP:
2713 case X86ISD::UNPCKLPS:
2714 case X86ISD::UNPCKLPD:
2715 case X86ISD::VUNPCKLPS:
2716 case X86ISD::VUNPCKLPD:
2717 case X86ISD::VUNPCKLPSY:
2718 case X86ISD::VUNPCKLPDY:
2719 case X86ISD::PUNPCKLWD:
2720 case X86ISD::PUNPCKLBW:
2721 case X86ISD::PUNPCKLDQ:
2722 case X86ISD::PUNPCKLQDQ:
2723 case X86ISD::UNPCKHPS:
2724 case X86ISD::UNPCKHPD:
2725 case X86ISD::PUNPCKHWD:
2726 case X86ISD::PUNPCKHBW:
2727 case X86ISD::PUNPCKHDQ:
2728 case X86ISD::PUNPCKHQDQ:
2734 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2735 SDValue V1, SelectionDAG &DAG) {
2737 default: llvm_unreachable("Unknown x86 shuffle node");
2738 case X86ISD::MOVSHDUP:
2739 case X86ISD::MOVSLDUP:
2740 case X86ISD::MOVDDUP:
2741 return DAG.getNode(Opc, dl, VT, V1);
2747 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2748 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2750 default: llvm_unreachable("Unknown x86 shuffle node");
2751 case X86ISD::PSHUFD:
2752 case X86ISD::PSHUFHW:
2753 case X86ISD::PSHUFLW:
2754 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2760 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2761 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2763 default: llvm_unreachable("Unknown x86 shuffle node");
2764 case X86ISD::PALIGN:
2765 case X86ISD::SHUFPD:
2766 case X86ISD::SHUFPS:
2767 return DAG.getNode(Opc, dl, VT, V1, V2,
2768 DAG.getConstant(TargetMask, MVT::i8));
2773 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2774 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2776 default: llvm_unreachable("Unknown x86 shuffle node");
2777 case X86ISD::MOVLHPS:
2778 case X86ISD::MOVLHPD:
2779 case X86ISD::MOVHLPS:
2780 case X86ISD::MOVLPS:
2781 case X86ISD::MOVLPD:
2784 case X86ISD::UNPCKLPS:
2785 case X86ISD::UNPCKLPD:
2786 case X86ISD::VUNPCKLPS:
2787 case X86ISD::VUNPCKLPD:
2788 case X86ISD::VUNPCKLPSY:
2789 case X86ISD::VUNPCKLPDY:
2790 case X86ISD::PUNPCKLWD:
2791 case X86ISD::PUNPCKLBW:
2792 case X86ISD::PUNPCKLDQ:
2793 case X86ISD::PUNPCKLQDQ:
2794 case X86ISD::UNPCKHPS:
2795 case X86ISD::UNPCKHPD:
2796 case X86ISD::PUNPCKHWD:
2797 case X86ISD::PUNPCKHBW:
2798 case X86ISD::PUNPCKHDQ:
2799 case X86ISD::PUNPCKHQDQ:
2800 return DAG.getNode(Opc, dl, VT, V1, V2);
2805 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2806 MachineFunction &MF = DAG.getMachineFunction();
2807 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2808 int ReturnAddrIndex = FuncInfo->getRAIndex();
2810 if (ReturnAddrIndex == 0) {
2811 // Set up a frame object for the return address.
2812 uint64_t SlotSize = TD->getPointerSize();
2813 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2815 FuncInfo->setRAIndex(ReturnAddrIndex);
2818 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2822 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2823 bool hasSymbolicDisplacement) {
2824 // Offset should fit into 32 bit immediate field.
2825 if (!isInt<32>(Offset))
2828 // If we don't have a symbolic displacement - we don't have any extra
2830 if (!hasSymbolicDisplacement)
2833 // FIXME: Some tweaks might be needed for medium code model.
2834 if (M != CodeModel::Small && M != CodeModel::Kernel)
2837 // For small code model we assume that latest object is 16MB before end of 31
2838 // bits boundary. We may also accept pretty large negative constants knowing
2839 // that all objects are in the positive half of address space.
2840 if (M == CodeModel::Small && Offset < 16*1024*1024)
2843 // For kernel code model we know that all object resist in the negative half
2844 // of 32bits address space. We may not accept negative offsets, since they may
2845 // be just off and we may accept pretty large positive ones.
2846 if (M == CodeModel::Kernel && Offset > 0)
2852 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2853 /// specific condition code, returning the condition code and the LHS/RHS of the
2854 /// comparison to make.
2855 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2856 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2858 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2859 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2860 // X > -1 -> X == 0, jump !sign.
2861 RHS = DAG.getConstant(0, RHS.getValueType());
2862 return X86::COND_NS;
2863 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2864 // X < 0 -> X == 0, jump on sign.
2866 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2868 RHS = DAG.getConstant(0, RHS.getValueType());
2869 return X86::COND_LE;
2873 switch (SetCCOpcode) {
2874 default: llvm_unreachable("Invalid integer condition!");
2875 case ISD::SETEQ: return X86::COND_E;
2876 case ISD::SETGT: return X86::COND_G;
2877 case ISD::SETGE: return X86::COND_GE;
2878 case ISD::SETLT: return X86::COND_L;
2879 case ISD::SETLE: return X86::COND_LE;
2880 case ISD::SETNE: return X86::COND_NE;
2881 case ISD::SETULT: return X86::COND_B;
2882 case ISD::SETUGT: return X86::COND_A;
2883 case ISD::SETULE: return X86::COND_BE;
2884 case ISD::SETUGE: return X86::COND_AE;
2888 // First determine if it is required or is profitable to flip the operands.
2890 // If LHS is a foldable load, but RHS is not, flip the condition.
2891 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
2892 !ISD::isNON_EXTLoad(RHS.getNode())) {
2893 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2894 std::swap(LHS, RHS);
2897 switch (SetCCOpcode) {
2903 std::swap(LHS, RHS);
2907 // On a floating point condition, the flags are set as follows:
2909 // 0 | 0 | 0 | X > Y
2910 // 0 | 0 | 1 | X < Y
2911 // 1 | 0 | 0 | X == Y
2912 // 1 | 1 | 1 | unordered
2913 switch (SetCCOpcode) {
2914 default: llvm_unreachable("Condcode should be pre-legalized away");
2916 case ISD::SETEQ: return X86::COND_E;
2917 case ISD::SETOLT: // flipped
2919 case ISD::SETGT: return X86::COND_A;
2920 case ISD::SETOLE: // flipped
2922 case ISD::SETGE: return X86::COND_AE;
2923 case ISD::SETUGT: // flipped
2925 case ISD::SETLT: return X86::COND_B;
2926 case ISD::SETUGE: // flipped
2928 case ISD::SETLE: return X86::COND_BE;
2930 case ISD::SETNE: return X86::COND_NE;
2931 case ISD::SETUO: return X86::COND_P;
2932 case ISD::SETO: return X86::COND_NP;
2934 case ISD::SETUNE: return X86::COND_INVALID;
2938 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2939 /// code. Current x86 isa includes the following FP cmov instructions:
2940 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2941 static bool hasFPCMov(unsigned X86CC) {
2957 /// isFPImmLegal - Returns true if the target can instruction select the
2958 /// specified FP immediate natively. If false, the legalizer will
2959 /// materialize the FP immediate as a load from a constant pool.
2960 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2961 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
2962 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
2968 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2969 /// the specified range (L, H].
2970 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2971 return (Val < 0) || (Val >= Low && Val < Hi);
2974 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2975 /// specified value.
2976 static bool isUndefOrEqual(int Val, int CmpVal) {
2977 if (Val < 0 || Val == CmpVal)
2982 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2983 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2984 /// the second operand.
2985 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2986 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
2987 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2988 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2989 return (Mask[0] < 2 && Mask[1] < 2);
2993 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2994 SmallVector<int, 8> M;
2996 return ::isPSHUFDMask(M, N->getValueType(0));
2999 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3000 /// is suitable for input to PSHUFHW.
3001 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3002 if (VT != MVT::v8i16)
3005 // Lower quadword copied in order or undef.
3006 for (int i = 0; i != 4; ++i)
3007 if (Mask[i] >= 0 && Mask[i] != i)
3010 // Upper quadword shuffled.
3011 for (int i = 4; i != 8; ++i)
3012 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3018 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
3019 SmallVector<int, 8> M;
3021 return ::isPSHUFHWMask(M, N->getValueType(0));
3024 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3025 /// is suitable for input to PSHUFLW.
3026 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3027 if (VT != MVT::v8i16)
3030 // Upper quadword copied in order.
3031 for (int i = 4; i != 8; ++i)
3032 if (Mask[i] >= 0 && Mask[i] != i)
3035 // Lower quadword shuffled.
3036 for (int i = 0; i != 4; ++i)
3043 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
3044 SmallVector<int, 8> M;
3046 return ::isPSHUFLWMask(M, N->getValueType(0));
3049 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3050 /// is suitable for input to PALIGNR.
3051 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
3053 int i, e = VT.getVectorNumElements();
3055 // Do not handle v2i64 / v2f64 shuffles with palignr.
3056 if (e < 4 || !hasSSSE3)
3059 for (i = 0; i != e; ++i)
3063 // All undef, not a palignr.
3067 // Determine if it's ok to perform a palignr with only the LHS, since we
3068 // don't have access to the actual shuffle elements to see if RHS is undef.
3069 bool Unary = Mask[i] < (int)e;
3070 bool NeedsUnary = false;
3072 int s = Mask[i] - i;
3074 // Check the rest of the elements to see if they are consecutive.
3075 for (++i; i != e; ++i) {
3080 Unary = Unary && (m < (int)e);
3081 NeedsUnary = NeedsUnary || (m < s);
3083 if (NeedsUnary && !Unary)
3085 if (Unary && m != ((s+i) & (e-1)))
3087 if (!Unary && m != (s+i))
3093 bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) {
3094 SmallVector<int, 8> M;
3096 return ::isPALIGNRMask(M, N->getValueType(0), true);
3099 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3100 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
3101 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3102 int NumElems = VT.getVectorNumElements();
3103 if (NumElems != 2 && NumElems != 4)
3106 int Half = NumElems / 2;
3107 for (int i = 0; i < Half; ++i)
3108 if (!isUndefOrInRange(Mask[i], 0, NumElems))
3110 for (int i = Half; i < NumElems; ++i)
3111 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
3117 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
3118 SmallVector<int, 8> M;
3120 return ::isSHUFPMask(M, N->getValueType(0));
3123 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
3124 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
3125 /// half elements to come from vector 1 (which would equal the dest.) and
3126 /// the upper half to come from vector 2.
3127 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3128 int NumElems = VT.getVectorNumElements();
3130 if (NumElems != 2 && NumElems != 4)
3133 int Half = NumElems / 2;
3134 for (int i = 0; i < Half; ++i)
3135 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
3137 for (int i = Half; i < NumElems; ++i)
3138 if (!isUndefOrInRange(Mask[i], 0, NumElems))
3143 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
3144 SmallVector<int, 8> M;
3146 return isCommutedSHUFPMask(M, N->getValueType(0));
3149 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3150 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3151 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
3152 if (N->getValueType(0).getVectorNumElements() != 4)
3155 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3156 return isUndefOrEqual(N->getMaskElt(0), 6) &&
3157 isUndefOrEqual(N->getMaskElt(1), 7) &&
3158 isUndefOrEqual(N->getMaskElt(2), 2) &&
3159 isUndefOrEqual(N->getMaskElt(3), 3);
3162 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3163 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3165 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
3166 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3171 return isUndefOrEqual(N->getMaskElt(0), 2) &&
3172 isUndefOrEqual(N->getMaskElt(1), 3) &&
3173 isUndefOrEqual(N->getMaskElt(2), 2) &&
3174 isUndefOrEqual(N->getMaskElt(3), 3);
3177 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3178 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3179 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
3180 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3182 if (NumElems != 2 && NumElems != 4)
3185 for (unsigned i = 0; i < NumElems/2; ++i)
3186 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
3189 for (unsigned i = NumElems/2; i < NumElems; ++i)
3190 if (!isUndefOrEqual(N->getMaskElt(i), i))
3196 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3197 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3198 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
3199 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3201 if ((NumElems != 2 && NumElems != 4)
3202 || N->getValueType(0).getSizeInBits() > 128)
3205 for (unsigned i = 0; i < NumElems/2; ++i)
3206 if (!isUndefOrEqual(N->getMaskElt(i), i))
3209 for (unsigned i = 0; i < NumElems/2; ++i)
3210 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
3216 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3217 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3218 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3219 bool V2IsSplat = false) {
3220 int NumElts = VT.getVectorNumElements();
3221 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
3224 // Handle vector lengths > 128 bits. Define a "section" as a set of
3225 // 128 bits. AVX defines UNPCK* to operate independently on 128-bit
3227 unsigned NumSections = VT.getSizeInBits() / 128;
3228 if (NumSections == 0 ) NumSections = 1; // Handle MMX
3229 unsigned NumSectionElts = NumElts / NumSections;
3232 unsigned End = NumSectionElts;
3233 for (unsigned s = 0; s < NumSections; ++s) {
3234 for (unsigned i = Start, j = s * NumSectionElts;
3238 int BitI1 = Mask[i+1];
3239 if (!isUndefOrEqual(BitI, j))
3242 if (!isUndefOrEqual(BitI1, NumElts))
3245 if (!isUndefOrEqual(BitI1, j + NumElts))
3249 // Process the next 128 bits.
3250 Start += NumSectionElts;
3251 End += NumSectionElts;
3257 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3258 SmallVector<int, 8> M;
3260 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
3263 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3264 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3265 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
3266 bool V2IsSplat = false) {
3267 int NumElts = VT.getVectorNumElements();
3268 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
3271 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
3273 int BitI1 = Mask[i+1];
3274 if (!isUndefOrEqual(BitI, j + NumElts/2))
3277 if (isUndefOrEqual(BitI1, NumElts))
3280 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
3287 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3288 SmallVector<int, 8> M;
3290 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
3293 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3294 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3296 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3297 int NumElems = VT.getVectorNumElements();
3298 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3301 // Handle vector lengths > 128 bits. Define a "section" as a set of
3302 // 128 bits. AVX defines UNPCK* to operate independently on 128-bit
3304 unsigned NumSections = VT.getSizeInBits() / 128;
3305 if (NumSections == 0 ) NumSections = 1; // Handle MMX
3306 unsigned NumSectionElts = NumElems / NumSections;
3308 for (unsigned s = 0; s < NumSections; ++s) {
3309 for (unsigned i = s * NumSectionElts, j = s * NumSectionElts;
3310 i != NumSectionElts * (s + 1);
3313 int BitI1 = Mask[i+1];
3315 if (!isUndefOrEqual(BitI, j))
3317 if (!isUndefOrEqual(BitI1, j))
3325 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
3326 SmallVector<int, 8> M;
3328 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
3331 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3332 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3334 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3335 int NumElems = VT.getVectorNumElements();
3336 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3339 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
3341 int BitI1 = Mask[i+1];
3342 if (!isUndefOrEqual(BitI, j))
3344 if (!isUndefOrEqual(BitI1, j))
3350 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
3351 SmallVector<int, 8> M;
3353 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
3356 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3357 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3358 /// MOVSD, and MOVD, i.e. setting the lowest element.
3359 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3360 if (VT.getVectorElementType().getSizeInBits() < 32)
3363 int NumElts = VT.getVectorNumElements();
3365 if (!isUndefOrEqual(Mask[0], NumElts))
3368 for (int i = 1; i < NumElts; ++i)
3369 if (!isUndefOrEqual(Mask[i], i))
3375 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3376 SmallVector<int, 8> M;
3378 return ::isMOVLMask(M, N->getValueType(0));
3381 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3382 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3383 /// element of vector 2 and the other elements to come from vector 1 in order.
3384 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3385 bool V2IsSplat = false, bool V2IsUndef = false) {
3386 int NumOps = VT.getVectorNumElements();
3387 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3390 if (!isUndefOrEqual(Mask[0], 0))
3393 for (int i = 1; i < NumOps; ++i)
3394 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3395 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3396 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3402 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3403 bool V2IsUndef = false) {
3404 SmallVector<int, 8> M;
3406 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
3409 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3410 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3411 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
3412 if (N->getValueType(0).getVectorNumElements() != 4)
3415 // Expect 1, 1, 3, 3
3416 for (unsigned i = 0; i < 2; ++i) {
3417 int Elt = N->getMaskElt(i);
3418 if (Elt >= 0 && Elt != 1)
3423 for (unsigned i = 2; i < 4; ++i) {
3424 int Elt = N->getMaskElt(i);
3425 if (Elt >= 0 && Elt != 3)
3430 // Don't use movshdup if it can be done with a shufps.
3431 // FIXME: verify that matching u, u, 3, 3 is what we want.
3435 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3436 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3437 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
3438 if (N->getValueType(0).getVectorNumElements() != 4)
3441 // Expect 0, 0, 2, 2
3442 for (unsigned i = 0; i < 2; ++i)
3443 if (N->getMaskElt(i) > 0)
3447 for (unsigned i = 2; i < 4; ++i) {
3448 int Elt = N->getMaskElt(i);
3449 if (Elt >= 0 && Elt != 2)
3454 // Don't use movsldup if it can be done with a shufps.
3458 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3459 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
3460 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3461 int e = N->getValueType(0).getVectorNumElements() / 2;
3463 for (int i = 0; i < e; ++i)
3464 if (!isUndefOrEqual(N->getMaskElt(i), i))
3466 for (int i = 0; i < e; ++i)
3467 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3472 /// isVEXTRACTF128Index - Return true if the specified
3473 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3474 /// suitable for input to VEXTRACTF128.
3475 bool X86::isVEXTRACTF128Index(SDNode *N) {
3476 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3479 // The index should be aligned on a 128-bit boundary.
3481 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3483 unsigned VL = N->getValueType(0).getVectorNumElements();
3484 unsigned VBits = N->getValueType(0).getSizeInBits();
3485 unsigned ElSize = VBits / VL;
3486 bool Result = (Index * ElSize) % 128 == 0;
3491 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3492 /// operand specifies a subvector insert that is suitable for input to
3494 bool X86::isVINSERTF128Index(SDNode *N) {
3495 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3498 // The index should be aligned on a 128-bit boundary.
3500 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3502 unsigned VL = N->getValueType(0).getVectorNumElements();
3503 unsigned VBits = N->getValueType(0).getSizeInBits();
3504 unsigned ElSize = VBits / VL;
3505 bool Result = (Index * ElSize) % 128 == 0;
3510 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3511 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3512 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
3513 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3514 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
3516 unsigned Shift = (NumOperands == 4) ? 2 : 1;
3518 for (int i = 0; i < NumOperands; ++i) {
3519 int Val = SVOp->getMaskElt(NumOperands-i-1);
3520 if (Val < 0) Val = 0;
3521 if (Val >= NumOperands) Val -= NumOperands;
3523 if (i != NumOperands - 1)
3529 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3530 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3531 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3532 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3534 // 8 nodes, but we only care about the last 4.
3535 for (unsigned i = 7; i >= 4; --i) {
3536 int Val = SVOp->getMaskElt(i);
3545 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3546 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3547 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3548 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3550 // 8 nodes, but we only care about the first 4.
3551 for (int i = 3; i >= 0; --i) {
3552 int Val = SVOp->getMaskElt(i);
3561 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3562 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3563 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
3564 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3565 EVT VVT = N->getValueType(0);
3566 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
3570 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
3571 Val = SVOp->getMaskElt(i);
3575 return (Val - i) * EltSize;
3578 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
3579 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
3581 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
3582 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3583 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
3586 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3588 EVT VecVT = N->getOperand(0).getValueType();
3589 EVT ElVT = VecVT.getVectorElementType();
3591 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
3593 return Index / NumElemsPerChunk;
3596 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
3597 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
3599 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
3600 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3601 llvm_unreachable("Illegal insert subvector for VINSERTF128");
3604 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3606 EVT VecVT = N->getValueType(0);
3607 EVT ElVT = VecVT.getVectorElementType();
3609 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
3611 return Index / NumElemsPerChunk;
3614 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3616 bool X86::isZeroNode(SDValue Elt) {
3617 return ((isa<ConstantSDNode>(Elt) &&
3618 cast<ConstantSDNode>(Elt)->isNullValue()) ||
3619 (isa<ConstantFPSDNode>(Elt) &&
3620 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
3623 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
3624 /// their permute mask.
3625 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
3626 SelectionDAG &DAG) {
3627 EVT VT = SVOp->getValueType(0);
3628 unsigned NumElems = VT.getVectorNumElements();
3629 SmallVector<int, 8> MaskVec;
3631 for (unsigned i = 0; i != NumElems; ++i) {
3632 int idx = SVOp->getMaskElt(i);
3634 MaskVec.push_back(idx);
3635 else if (idx < (int)NumElems)
3636 MaskVec.push_back(idx + NumElems);
3638 MaskVec.push_back(idx - NumElems);
3640 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
3641 SVOp->getOperand(0), &MaskVec[0]);
3644 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3645 /// the two vector operands have swapped position.
3646 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
3647 unsigned NumElems = VT.getVectorNumElements();
3648 for (unsigned i = 0; i != NumElems; ++i) {
3652 else if (idx < (int)NumElems)
3653 Mask[i] = idx + NumElems;
3655 Mask[i] = idx - NumElems;
3659 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
3660 /// match movhlps. The lower half elements should come from upper half of
3661 /// V1 (and in order), and the upper half elements should come from the upper
3662 /// half of V2 (and in order).
3663 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
3664 if (Op->getValueType(0).getVectorNumElements() != 4)
3666 for (unsigned i = 0, e = 2; i != e; ++i)
3667 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
3669 for (unsigned i = 2; i != 4; ++i)
3670 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
3675 /// isScalarLoadToVector - Returns true if the node is a scalar load that
3676 /// is promoted to a vector. It also returns the LoadSDNode by reference if
3678 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
3679 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
3681 N = N->getOperand(0).getNode();
3682 if (!ISD::isNON_EXTLoad(N))
3685 *LD = cast<LoadSDNode>(N);
3689 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
3690 /// match movlp{s|d}. The lower half elements should come from lower half of
3691 /// V1 (and in order), and the upper half elements should come from the upper
3692 /// half of V2 (and in order). And since V1 will become the source of the
3693 /// MOVLP, it must be either a vector load or a scalar load to vector.
3694 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
3695 ShuffleVectorSDNode *Op) {
3696 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
3698 // Is V2 is a vector load, don't do this transformation. We will try to use
3699 // load folding shufps op.
3700 if (ISD::isNON_EXTLoad(V2))
3703 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
3705 if (NumElems != 2 && NumElems != 4)
3707 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3708 if (!isUndefOrEqual(Op->getMaskElt(i), i))
3710 for (unsigned i = NumElems/2; i != NumElems; ++i)
3711 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
3716 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
3718 static bool isSplatVector(SDNode *N) {
3719 if (N->getOpcode() != ISD::BUILD_VECTOR)
3722 SDValue SplatValue = N->getOperand(0);
3723 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
3724 if (N->getOperand(i) != SplatValue)
3729 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
3730 /// to an zero vector.
3731 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
3732 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
3733 SDValue V1 = N->getOperand(0);
3734 SDValue V2 = N->getOperand(1);
3735 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3736 for (unsigned i = 0; i != NumElems; ++i) {
3737 int Idx = N->getMaskElt(i);
3738 if (Idx >= (int)NumElems) {
3739 unsigned Opc = V2.getOpcode();
3740 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
3742 if (Opc != ISD::BUILD_VECTOR ||
3743 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
3745 } else if (Idx >= 0) {
3746 unsigned Opc = V1.getOpcode();
3747 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
3749 if (Opc != ISD::BUILD_VECTOR ||
3750 !X86::isZeroNode(V1.getOperand(Idx)))
3757 /// getZeroVector - Returns a vector of specified type with all zero elements.
3759 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
3761 assert(VT.isVector() && "Expected a vector type");
3763 // Always build SSE zero vectors as <4 x i32> bitcasted
3764 // to their dest type. This ensures they get CSE'd.
3766 if (VT.getSizeInBits() == 128) { // SSE
3767 if (HasSSE2) { // SSE2
3768 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3769 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3771 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3772 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3774 } else if (VT.getSizeInBits() == 256) { // AVX
3775 // 256-bit logic and arithmetic instructions in AVX are
3776 // all floating-point, no support for integer ops. Default
3777 // to emitting fp zeroed vectors then.
3778 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3779 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
3780 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
3782 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
3785 /// getOnesVector - Returns a vector of specified type with all bits set.
3787 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3788 assert(VT.isVector() && "Expected a vector type");
3790 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3791 // type. This ensures they get CSE'd.
3792 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
3794 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3795 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
3799 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
3800 /// that point to V2 points to its first element.
3801 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3802 EVT VT = SVOp->getValueType(0);
3803 unsigned NumElems = VT.getVectorNumElements();
3805 bool Changed = false;
3806 SmallVector<int, 8> MaskVec;
3807 SVOp->getMask(MaskVec);
3809 for (unsigned i = 0; i != NumElems; ++i) {
3810 if (MaskVec[i] > (int)NumElems) {
3811 MaskVec[i] = NumElems;
3816 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
3817 SVOp->getOperand(1), &MaskVec[0]);
3818 return SDValue(SVOp, 0);
3821 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
3822 /// operation of specified width.
3823 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3825 unsigned NumElems = VT.getVectorNumElements();
3826 SmallVector<int, 8> Mask;
3827 Mask.push_back(NumElems);
3828 for (unsigned i = 1; i != NumElems; ++i)
3830 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3833 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
3834 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3836 unsigned NumElems = VT.getVectorNumElements();
3837 SmallVector<int, 8> Mask;
3838 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3840 Mask.push_back(i + NumElems);
3842 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3845 /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
3846 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3848 unsigned NumElems = VT.getVectorNumElements();
3849 unsigned Half = NumElems/2;
3850 SmallVector<int, 8> Mask;
3851 for (unsigned i = 0; i != Half; ++i) {
3852 Mask.push_back(i + Half);
3853 Mask.push_back(i + NumElems + Half);
3855 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3858 /// PromoteSplat - Promote a splat of v4i32, v8i16 or v16i8 to v4f32.
3859 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
3860 EVT PVT = MVT::v4f32;
3861 EVT VT = SV->getValueType(0);
3862 DebugLoc dl = SV->getDebugLoc();
3863 SDValue V1 = SV->getOperand(0);
3864 int NumElems = VT.getVectorNumElements();
3865 int EltNo = SV->getSplatIndex();
3867 // unpack elements to the correct location
3868 while (NumElems > 4) {
3869 if (EltNo < NumElems/2) {
3870 V1 = getUnpackl(DAG, dl, VT, V1, V1);
3872 V1 = getUnpackh(DAG, dl, VT, V1, V1);
3873 EltNo -= NumElems/2;
3878 // Perform the splat.
3879 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
3880 V1 = DAG.getNode(ISD::BITCAST, dl, PVT, V1);
3881 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3882 return DAG.getNode(ISD::BITCAST, dl, VT, V1);
3885 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3886 /// vector of zero or undef vector. This produces a shuffle where the low
3887 /// element of V2 is swizzled into the zero/undef vector, landing at element
3888 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3889 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3890 bool isZero, bool HasSSE2,
3891 SelectionDAG &DAG) {
3892 EVT VT = V2.getValueType();
3894 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3895 unsigned NumElems = VT.getVectorNumElements();
3896 SmallVector<int, 16> MaskVec;
3897 for (unsigned i = 0; i != NumElems; ++i)
3898 // If this is the insertion idx, put the low elt of V2 here.
3899 MaskVec.push_back(i == Idx ? NumElems : i);
3900 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3903 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
3904 /// element of the result of the vector shuffle.
3905 static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
3908 return SDValue(); // Limit search depth.
3910 SDValue V = SDValue(N, 0);
3911 EVT VT = V.getValueType();
3912 unsigned Opcode = V.getOpcode();
3914 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
3915 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
3916 Index = SV->getMaskElt(Index);
3919 return DAG.getUNDEF(VT.getVectorElementType());
3921 int NumElems = VT.getVectorNumElements();
3922 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1);
3923 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
3926 // Recurse into target specific vector shuffles to find scalars.
3927 if (isTargetShuffle(Opcode)) {
3928 int NumElems = VT.getVectorNumElements();
3929 SmallVector<unsigned, 16> ShuffleMask;
3933 case X86ISD::SHUFPS:
3934 case X86ISD::SHUFPD:
3935 ImmN = N->getOperand(N->getNumOperands()-1);
3936 DecodeSHUFPSMask(NumElems,
3937 cast<ConstantSDNode>(ImmN)->getZExtValue(),
3940 case X86ISD::PUNPCKHBW:
3941 case X86ISD::PUNPCKHWD:
3942 case X86ISD::PUNPCKHDQ:
3943 case X86ISD::PUNPCKHQDQ:
3944 DecodePUNPCKHMask(NumElems, ShuffleMask);
3946 case X86ISD::UNPCKHPS:
3947 case X86ISD::UNPCKHPD:
3948 DecodeUNPCKHPMask(NumElems, ShuffleMask);
3950 case X86ISD::PUNPCKLBW:
3951 case X86ISD::PUNPCKLWD:
3952 case X86ISD::PUNPCKLDQ:
3953 case X86ISD::PUNPCKLQDQ:
3954 DecodePUNPCKLMask(VT, ShuffleMask);
3956 case X86ISD::UNPCKLPS:
3957 case X86ISD::UNPCKLPD:
3958 case X86ISD::VUNPCKLPS:
3959 case X86ISD::VUNPCKLPD:
3960 case X86ISD::VUNPCKLPSY:
3961 case X86ISD::VUNPCKLPDY:
3962 DecodeUNPCKLPMask(VT, ShuffleMask);
3964 case X86ISD::MOVHLPS:
3965 DecodeMOVHLPSMask(NumElems, ShuffleMask);
3967 case X86ISD::MOVLHPS:
3968 DecodeMOVLHPSMask(NumElems, ShuffleMask);
3970 case X86ISD::PSHUFD:
3971 ImmN = N->getOperand(N->getNumOperands()-1);
3972 DecodePSHUFMask(NumElems,
3973 cast<ConstantSDNode>(ImmN)->getZExtValue(),
3976 case X86ISD::PSHUFHW:
3977 ImmN = N->getOperand(N->getNumOperands()-1);
3978 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
3981 case X86ISD::PSHUFLW:
3982 ImmN = N->getOperand(N->getNumOperands()-1);
3983 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
3987 case X86ISD::MOVSD: {
3988 // The index 0 always comes from the first element of the second source,
3989 // this is why MOVSS and MOVSD are used in the first place. The other
3990 // elements come from the other positions of the first source vector.
3991 unsigned OpNum = (Index == 0) ? 1 : 0;
3992 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
3996 assert("not implemented for target shuffle node");
4000 Index = ShuffleMask[Index];
4002 return DAG.getUNDEF(VT.getVectorElementType());
4004 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
4005 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
4009 // Actual nodes that may contain scalar elements
4010 if (Opcode == ISD::BITCAST) {
4011 V = V.getOperand(0);
4012 EVT SrcVT = V.getValueType();
4013 unsigned NumElems = VT.getVectorNumElements();
4015 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4019 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4020 return (Index == 0) ? V.getOperand(0)
4021 : DAG.getUNDEF(VT.getVectorElementType());
4023 if (V.getOpcode() == ISD::BUILD_VECTOR)
4024 return V.getOperand(Index);
4029 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4030 /// shuffle operation which come from a consecutively from a zero. The
4031 /// search can start in two different directions, from left or right.
4033 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
4034 bool ZerosFromLeft, SelectionDAG &DAG) {
4037 while (i < NumElems) {
4038 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4039 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
4040 if (!(Elt.getNode() &&
4041 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4049 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
4050 /// MaskE correspond consecutively to elements from one of the vector operands,
4051 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4053 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
4054 int OpIdx, int NumElems, unsigned &OpNum) {
4055 bool SeenV1 = false;
4056 bool SeenV2 = false;
4058 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
4059 int Idx = SVOp->getMaskElt(i);
4060 // Ignore undef indicies
4069 // Only accept consecutive elements from the same vector
4070 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4074 OpNum = SeenV1 ? 0 : 1;
4078 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4079 /// logical left shift of a vector.
4080 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4081 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4082 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4083 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4084 false /* check zeros from right */, DAG);
4090 // Considering the elements in the mask that are not consecutive zeros,
4091 // check if they consecutively come from only one of the source vectors.
4093 // V1 = {X, A, B, C} 0
4095 // vector_shuffle V1, V2 <1, 2, 3, X>
4097 if (!isShuffleMaskConsecutive(SVOp,
4098 0, // Mask Start Index
4099 NumElems-NumZeros-1, // Mask End Index
4100 NumZeros, // Where to start looking in the src vector
4101 NumElems, // Number of elements in vector
4102 OpSrc)) // Which source operand ?
4107 ShVal = SVOp->getOperand(OpSrc);
4111 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4112 /// logical left shift of a vector.
4113 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4114 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4115 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4116 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4117 true /* check zeros from left */, DAG);
4123 // Considering the elements in the mask that are not consecutive zeros,
4124 // check if they consecutively come from only one of the source vectors.
4126 // 0 { A, B, X, X } = V2
4128 // vector_shuffle V1, V2 <X, X, 4, 5>
4130 if (!isShuffleMaskConsecutive(SVOp,
4131 NumZeros, // Mask Start Index
4132 NumElems-1, // Mask End Index
4133 0, // Where to start looking in the src vector
4134 NumElems, // Number of elements in vector
4135 OpSrc)) // Which source operand ?
4140 ShVal = SVOp->getOperand(OpSrc);
4144 /// isVectorShift - Returns true if the shuffle can be implemented as a
4145 /// logical left or right shift of a vector.
4146 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4147 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4148 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4149 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4155 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4157 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4158 unsigned NumNonZero, unsigned NumZero,
4160 const TargetLowering &TLI) {
4164 DebugLoc dl = Op.getDebugLoc();
4167 for (unsigned i = 0; i < 16; ++i) {
4168 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4169 if (ThisIsNonZero && First) {
4171 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4173 V = DAG.getUNDEF(MVT::v8i16);
4178 SDValue ThisElt(0, 0), LastElt(0, 0);
4179 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4180 if (LastIsNonZero) {
4181 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4182 MVT::i16, Op.getOperand(i-1));
4184 if (ThisIsNonZero) {
4185 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4186 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4187 ThisElt, DAG.getConstant(8, MVT::i8));
4189 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4193 if (ThisElt.getNode())
4194 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4195 DAG.getIntPtrConstant(i/2));
4199 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4202 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4204 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4205 unsigned NumNonZero, unsigned NumZero,
4207 const TargetLowering &TLI) {
4211 DebugLoc dl = Op.getDebugLoc();
4214 for (unsigned i = 0; i < 8; ++i) {
4215 bool isNonZero = (NonZeros & (1 << i)) != 0;
4219 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4221 V = DAG.getUNDEF(MVT::v8i16);
4224 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4225 MVT::v8i16, V, Op.getOperand(i),
4226 DAG.getIntPtrConstant(i));
4233 /// getVShift - Return a vector logical shift node.
4235 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4236 unsigned NumBits, SelectionDAG &DAG,
4237 const TargetLowering &TLI, DebugLoc dl) {
4238 EVT ShVT = MVT::v2i64;
4239 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
4240 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4241 return DAG.getNode(ISD::BITCAST, dl, VT,
4242 DAG.getNode(Opc, dl, ShVT, SrcOp,
4243 DAG.getConstant(NumBits,
4244 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4248 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4249 SelectionDAG &DAG) const {
4251 // Check if the scalar load can be widened into a vector load. And if
4252 // the address is "base + cst" see if the cst can be "absorbed" into
4253 // the shuffle mask.
4254 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4255 SDValue Ptr = LD->getBasePtr();
4256 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4258 EVT PVT = LD->getValueType(0);
4259 if (PVT != MVT::i32 && PVT != MVT::f32)
4264 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4265 FI = FINode->getIndex();
4267 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4268 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4269 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4270 Offset = Ptr.getConstantOperandVal(1);
4271 Ptr = Ptr.getOperand(0);
4276 SDValue Chain = LD->getChain();
4277 // Make sure the stack object alignment is at least 16.
4278 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4279 if (DAG.InferPtrAlignment(Ptr) < 16) {
4280 if (MFI->isFixedObjectIndex(FI)) {
4281 // Can't change the alignment. FIXME: It's possible to compute
4282 // the exact stack offset and reference FI + adjust offset instead.
4283 // If someone *really* cares about this. That's the way to implement it.
4286 MFI->setObjectAlignment(FI, 16);
4290 // (Offset % 16) must be multiple of 4. Then address is then
4291 // Ptr + (Offset & ~15).
4294 if ((Offset % 16) & 3)
4296 int64_t StartOffset = Offset & ~15;
4298 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4299 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4301 int EltNo = (Offset - StartOffset) >> 2;
4302 int Mask[4] = { EltNo, EltNo, EltNo, EltNo };
4303 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32;
4304 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,
4305 LD->getPointerInfo().getWithOffset(StartOffset),
4307 // Canonicalize it to a v4i32 shuffle.
4308 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1);
4309 return DAG.getNode(ISD::BITCAST, dl, VT,
4310 DAG.getVectorShuffle(MVT::v4i32, dl, V1,
4311 DAG.getUNDEF(MVT::v4i32),&Mask[0]));
4317 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4318 /// vector of type 'VT', see if the elements can be replaced by a single large
4319 /// load which has the same value as a build_vector whose operands are 'elts'.
4321 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4323 /// FIXME: we'd also like to handle the case where the last elements are zero
4324 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4325 /// There's even a handy isZeroNode for that purpose.
4326 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4327 DebugLoc &DL, SelectionDAG &DAG) {
4328 EVT EltVT = VT.getVectorElementType();
4329 unsigned NumElems = Elts.size();
4331 LoadSDNode *LDBase = NULL;
4332 unsigned LastLoadedElt = -1U;
4334 // For each element in the initializer, see if we've found a load or an undef.
4335 // If we don't find an initial load element, or later load elements are
4336 // non-consecutive, bail out.
4337 for (unsigned i = 0; i < NumElems; ++i) {
4338 SDValue Elt = Elts[i];
4340 if (!Elt.getNode() ||
4341 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4344 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4346 LDBase = cast<LoadSDNode>(Elt.getNode());
4350 if (Elt.getOpcode() == ISD::UNDEF)
4353 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4354 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4359 // If we have found an entire vector of loads and undefs, then return a large
4360 // load of the entire vector width starting at the base pointer. If we found
4361 // consecutive loads for the low half, generate a vzext_load node.
4362 if (LastLoadedElt == NumElems - 1) {
4363 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4364 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4365 LDBase->getPointerInfo(),
4366 LDBase->isVolatile(), LDBase->isNonTemporal(), 0);
4367 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4368 LDBase->getPointerInfo(),
4369 LDBase->isVolatile(), LDBase->isNonTemporal(),
4370 LDBase->getAlignment());
4371 } else if (NumElems == 4 && LastLoadedElt == 1) {
4372 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4373 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4374 SDValue ResNode = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys,
4376 LDBase->getMemOperand());
4377 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4383 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
4384 DebugLoc dl = Op.getDebugLoc();
4386 EVT VT = Op.getValueType();
4387 EVT ExtVT = VT.getVectorElementType();
4389 unsigned NumElems = Op.getNumOperands();
4391 // For AVX-length vectors, build the individual 128-bit pieces and
4392 // use shuffles to put them in place.
4393 if (VT.getSizeInBits() > 256 &&
4394 Subtarget->hasAVX() &&
4395 !ISD::isBuildVectorAllZeros(Op.getNode())) {
4396 SmallVector<SDValue, 8> V;
4398 for (unsigned i = 0; i < NumElems; ++i) {
4399 V[i] = Op.getOperand(i);
4402 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
4404 // Build the lower subvector.
4405 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
4406 // Build the upper subvector.
4407 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
4410 return ConcatVectors(Lower, Upper, DAG);
4413 // All zero's are handled with pxor in SSE2 and above, xorps in SSE1.
4414 // All one's are handled with pcmpeqd. In AVX, zero's are handled with
4415 // vpxor in 128-bit and xor{pd,ps} in 256-bit, but no 256 version of pcmpeqd
4416 // is present, so AllOnes is ignored.
4417 if (ISD::isBuildVectorAllZeros(Op.getNode()) ||
4418 (Op.getValueType().getSizeInBits() != 256 &&
4419 ISD::isBuildVectorAllOnes(Op.getNode()))) {
4420 // Canonicalize this to <4 x i32> (SSE) to
4421 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
4422 // eliminated on x86-32 hosts.
4423 if (Op.getValueType() == MVT::v4i32)
4426 if (ISD::isBuildVectorAllOnes(Op.getNode()))
4427 return getOnesVector(Op.getValueType(), DAG, dl);
4428 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
4431 unsigned EVTBits = ExtVT.getSizeInBits();
4433 unsigned NumZero = 0;
4434 unsigned NumNonZero = 0;
4435 unsigned NonZeros = 0;
4436 bool IsAllConstants = true;
4437 SmallSet<SDValue, 8> Values;
4438 for (unsigned i = 0; i < NumElems; ++i) {
4439 SDValue Elt = Op.getOperand(i);
4440 if (Elt.getOpcode() == ISD::UNDEF)
4443 if (Elt.getOpcode() != ISD::Constant &&
4444 Elt.getOpcode() != ISD::ConstantFP)
4445 IsAllConstants = false;
4446 if (X86::isZeroNode(Elt))
4449 NonZeros |= (1 << i);
4454 // All undef vector. Return an UNDEF. All zero vectors were handled above.
4455 if (NumNonZero == 0)
4456 return DAG.getUNDEF(VT);
4458 // Special case for single non-zero, non-undef, element.
4459 if (NumNonZero == 1) {
4460 unsigned Idx = CountTrailingZeros_32(NonZeros);
4461 SDValue Item = Op.getOperand(Idx);
4463 // If this is an insertion of an i64 value on x86-32, and if the top bits of
4464 // the value are obviously zero, truncate the value to i32 and do the
4465 // insertion that way. Only do this if the value is non-constant or if the
4466 // value is a constant being inserted into element 0. It is cheaper to do
4467 // a constant pool load than it is to do a movd + shuffle.
4468 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
4469 (!IsAllConstants || Idx == 0)) {
4470 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
4472 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
4473 EVT VecVT = MVT::v4i32;
4474 unsigned VecElts = 4;
4476 // Truncate the value (which may itself be a constant) to i32, and
4477 // convert it to a vector with movd (S2V+shuffle to zero extend).
4478 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
4479 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
4480 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
4481 Subtarget->hasSSE2(), DAG);
4483 // Now we have our 32-bit value zero extended in the low element of
4484 // a vector. If Idx != 0, swizzle it into place.
4486 SmallVector<int, 4> Mask;
4487 Mask.push_back(Idx);
4488 for (unsigned i = 1; i != VecElts; ++i)
4490 Item = DAG.getVectorShuffle(VecVT, dl, Item,
4491 DAG.getUNDEF(Item.getValueType()),
4494 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item);
4498 // If we have a constant or non-constant insertion into the low element of
4499 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
4500 // the rest of the elements. This will be matched as movd/movq/movss/movsd
4501 // depending on what the source datatype is.
4504 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4505 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
4506 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
4507 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4508 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
4509 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
4511 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
4512 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
4513 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
4514 EVT MiddleVT = MVT::v4i32;
4515 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
4516 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
4517 Subtarget->hasSSE2(), DAG);
4518 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
4522 // Is it a vector logical left shift?
4523 if (NumElems == 2 && Idx == 1 &&
4524 X86::isZeroNode(Op.getOperand(0)) &&
4525 !X86::isZeroNode(Op.getOperand(1))) {
4526 unsigned NumBits = VT.getSizeInBits();
4527 return getVShift(true, VT,
4528 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4529 VT, Op.getOperand(1)),
4530 NumBits/2, DAG, *this, dl);
4533 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
4536 // Otherwise, if this is a vector with i32 or f32 elements, and the element
4537 // is a non-constant being inserted into an element other than the low one,
4538 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
4539 // movd/movss) to move this into the low element, then shuffle it into
4541 if (EVTBits == 32) {
4542 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4544 // Turn it into a shuffle of zero and zero-extended scalar to vector.
4545 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
4546 Subtarget->hasSSE2(), DAG);
4547 SmallVector<int, 8> MaskVec;
4548 for (unsigned i = 0; i < NumElems; i++)
4549 MaskVec.push_back(i == Idx ? 0 : 1);
4550 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
4554 // Splat is obviously ok. Let legalizer expand it to a shuffle.
4555 if (Values.size() == 1) {
4556 if (EVTBits == 32) {
4557 // Instead of a shuffle like this:
4558 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
4559 // Check if it's possible to issue this instead.
4560 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
4561 unsigned Idx = CountTrailingZeros_32(NonZeros);
4562 SDValue Item = Op.getOperand(Idx);
4563 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
4564 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
4569 // A vector full of immediates; various special cases are already
4570 // handled, so this is best done with a single constant-pool load.
4574 // Let legalizer expand 2-wide build_vectors.
4575 if (EVTBits == 64) {
4576 if (NumNonZero == 1) {
4577 // One half is zero or undef.
4578 unsigned Idx = CountTrailingZeros_32(NonZeros);
4579 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
4580 Op.getOperand(Idx));
4581 return getShuffleVectorZeroOrUndef(V2, Idx, true,
4582 Subtarget->hasSSE2(), DAG);
4587 // If element VT is < 32 bits, convert it to inserts into a zero vector.
4588 if (EVTBits == 8 && NumElems == 16) {
4589 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
4591 if (V.getNode()) return V;
4594 if (EVTBits == 16 && NumElems == 8) {
4595 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
4597 if (V.getNode()) return V;
4600 // If element VT is == 32 bits, turn it into a number of shuffles.
4601 SmallVector<SDValue, 8> V;
4603 if (NumElems == 4 && NumZero > 0) {
4604 for (unsigned i = 0; i < 4; ++i) {
4605 bool isZero = !(NonZeros & (1 << i));
4607 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4609 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
4612 for (unsigned i = 0; i < 2; ++i) {
4613 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
4616 V[i] = V[i*2]; // Must be a zero vector.
4619 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
4622 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
4625 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
4630 SmallVector<int, 8> MaskVec;
4631 bool Reverse = (NonZeros & 0x3) == 2;
4632 for (unsigned i = 0; i < 2; ++i)
4633 MaskVec.push_back(Reverse ? 1-i : i);
4634 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
4635 for (unsigned i = 0; i < 2; ++i)
4636 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
4637 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
4640 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
4641 // Check for a build vector of consecutive loads.
4642 for (unsigned i = 0; i < NumElems; ++i)
4643 V[i] = Op.getOperand(i);
4645 // Check for elements which are consecutive loads.
4646 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
4650 // For SSE 4.1, use insertps to put the high elements into the low element.
4651 if (getSubtarget()->hasSSE41()) {
4653 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
4654 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
4656 Result = DAG.getUNDEF(VT);
4658 for (unsigned i = 1; i < NumElems; ++i) {
4659 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
4660 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
4661 Op.getOperand(i), DAG.getIntPtrConstant(i));
4666 // Otherwise, expand into a number of unpckl*, start by extending each of
4667 // our (non-undef) elements to the full vector width with the element in the
4668 // bottom slot of the vector (which generates no code for SSE).
4669 for (unsigned i = 0; i < NumElems; ++i) {
4670 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
4671 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
4673 V[i] = DAG.getUNDEF(VT);
4676 // Next, we iteratively mix elements, e.g. for v4f32:
4677 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
4678 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
4679 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
4680 unsigned EltStride = NumElems >> 1;
4681 while (EltStride != 0) {
4682 for (unsigned i = 0; i < EltStride; ++i) {
4683 // If V[i+EltStride] is undef and this is the first round of mixing,
4684 // then it is safe to just drop this shuffle: V[i] is already in the
4685 // right place, the one element (since it's the first round) being
4686 // inserted as undef can be dropped. This isn't safe for successive
4687 // rounds because they will permute elements within both vectors.
4688 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
4689 EltStride == NumElems/2)
4692 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
4702 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
4703 // We support concatenate two MMX registers and place them in a MMX
4704 // register. This is better than doing a stack convert.
4705 DebugLoc dl = Op.getDebugLoc();
4706 EVT ResVT = Op.getValueType();
4707 assert(Op.getNumOperands() == 2);
4708 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
4709 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
4711 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
4712 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4713 InVec = Op.getOperand(1);
4714 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4715 unsigned NumElts = ResVT.getVectorNumElements();
4716 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
4717 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
4718 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
4720 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
4721 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4722 Mask[0] = 0; Mask[1] = 2;
4723 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
4725 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
4728 // v8i16 shuffles - Prefer shuffles in the following order:
4729 // 1. [all] pshuflw, pshufhw, optional move
4730 // 2. [ssse3] 1 x pshufb
4731 // 3. [ssse3] 2 x pshufb + 1 x por
4732 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
4734 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
4735 SelectionDAG &DAG) const {
4736 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4737 SDValue V1 = SVOp->getOperand(0);
4738 SDValue V2 = SVOp->getOperand(1);
4739 DebugLoc dl = SVOp->getDebugLoc();
4740 SmallVector<int, 8> MaskVals;
4742 // Determine if more than 1 of the words in each of the low and high quadwords
4743 // of the result come from the same quadword of one of the two inputs. Undef
4744 // mask values count as coming from any quadword, for better codegen.
4745 SmallVector<unsigned, 4> LoQuad(4);
4746 SmallVector<unsigned, 4> HiQuad(4);
4747 BitVector InputQuads(4);
4748 for (unsigned i = 0; i < 8; ++i) {
4749 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
4750 int EltIdx = SVOp->getMaskElt(i);
4751 MaskVals.push_back(EltIdx);
4760 InputQuads.set(EltIdx / 4);
4763 int BestLoQuad = -1;
4764 unsigned MaxQuad = 1;
4765 for (unsigned i = 0; i < 4; ++i) {
4766 if (LoQuad[i] > MaxQuad) {
4768 MaxQuad = LoQuad[i];
4772 int BestHiQuad = -1;
4774 for (unsigned i = 0; i < 4; ++i) {
4775 if (HiQuad[i] > MaxQuad) {
4777 MaxQuad = HiQuad[i];
4781 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
4782 // of the two input vectors, shuffle them into one input vector so only a
4783 // single pshufb instruction is necessary. If There are more than 2 input
4784 // quads, disable the next transformation since it does not help SSSE3.
4785 bool V1Used = InputQuads[0] || InputQuads[1];
4786 bool V2Used = InputQuads[2] || InputQuads[3];
4787 if (Subtarget->hasSSSE3()) {
4788 if (InputQuads.count() == 2 && V1Used && V2Used) {
4789 BestLoQuad = InputQuads.find_first();
4790 BestHiQuad = InputQuads.find_next(BestLoQuad);
4792 if (InputQuads.count() > 2) {
4798 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
4799 // the shuffle mask. If a quad is scored as -1, that means that it contains
4800 // words from all 4 input quadwords.
4802 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
4803 SmallVector<int, 8> MaskV;
4804 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
4805 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
4806 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
4807 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
4808 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
4809 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
4811 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
4812 // source words for the shuffle, to aid later transformations.
4813 bool AllWordsInNewV = true;
4814 bool InOrder[2] = { true, true };
4815 for (unsigned i = 0; i != 8; ++i) {
4816 int idx = MaskVals[i];
4818 InOrder[i/4] = false;
4819 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
4821 AllWordsInNewV = false;
4825 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
4826 if (AllWordsInNewV) {
4827 for (int i = 0; i != 8; ++i) {
4828 int idx = MaskVals[i];
4831 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
4832 if ((idx != i) && idx < 4)
4834 if ((idx != i) && idx > 3)
4843 // If we've eliminated the use of V2, and the new mask is a pshuflw or
4844 // pshufhw, that's as cheap as it gets. Return the new shuffle.
4845 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
4846 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
4847 unsigned TargetMask = 0;
4848 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
4849 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
4850 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()):
4851 X86::getShufflePSHUFLWImmediate(NewV.getNode());
4852 V1 = NewV.getOperand(0);
4853 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
4857 // If we have SSSE3, and all words of the result are from 1 input vector,
4858 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
4859 // is present, fall back to case 4.
4860 if (Subtarget->hasSSSE3()) {
4861 SmallVector<SDValue,16> pshufbMask;
4863 // If we have elements from both input vectors, set the high bit of the
4864 // shuffle mask element to zero out elements that come from V2 in the V1
4865 // mask, and elements that come from V1 in the V2 mask, so that the two
4866 // results can be OR'd together.
4867 bool TwoInputs = V1Used && V2Used;
4868 for (unsigned i = 0; i != 8; ++i) {
4869 int EltIdx = MaskVals[i] * 2;
4870 if (TwoInputs && (EltIdx >= 16)) {
4871 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4872 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4875 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4876 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
4878 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
4879 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4880 DAG.getNode(ISD::BUILD_VECTOR, dl,
4881 MVT::v16i8, &pshufbMask[0], 16));
4883 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
4885 // Calculate the shuffle mask for the second input, shuffle it, and
4886 // OR it with the first shuffled input.
4888 for (unsigned i = 0; i != 8; ++i) {
4889 int EltIdx = MaskVals[i] * 2;
4891 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4892 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4895 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4896 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
4898 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
4899 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4900 DAG.getNode(ISD::BUILD_VECTOR, dl,
4901 MVT::v16i8, &pshufbMask[0], 16));
4902 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4903 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
4906 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
4907 // and update MaskVals with new element order.
4908 BitVector InOrder(8);
4909 if (BestLoQuad >= 0) {
4910 SmallVector<int, 8> MaskV;
4911 for (int i = 0; i != 4; ++i) {
4912 int idx = MaskVals[i];
4914 MaskV.push_back(-1);
4916 } else if ((idx / 4) == BestLoQuad) {
4917 MaskV.push_back(idx & 3);
4920 MaskV.push_back(-1);
4923 for (unsigned i = 4; i != 8; ++i)
4925 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4928 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
4929 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
4931 X86::getShufflePSHUFLWImmediate(NewV.getNode()),
4935 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
4936 // and update MaskVals with the new element order.
4937 if (BestHiQuad >= 0) {
4938 SmallVector<int, 8> MaskV;
4939 for (unsigned i = 0; i != 4; ++i)
4941 for (unsigned i = 4; i != 8; ++i) {
4942 int idx = MaskVals[i];
4944 MaskV.push_back(-1);
4946 } else if ((idx / 4) == BestHiQuad) {
4947 MaskV.push_back((idx & 3) + 4);
4950 MaskV.push_back(-1);
4953 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4956 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
4957 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
4959 X86::getShufflePSHUFHWImmediate(NewV.getNode()),
4963 // In case BestHi & BestLo were both -1, which means each quadword has a word
4964 // from each of the four input quadwords, calculate the InOrder bitvector now
4965 // before falling through to the insert/extract cleanup.
4966 if (BestLoQuad == -1 && BestHiQuad == -1) {
4968 for (int i = 0; i != 8; ++i)
4969 if (MaskVals[i] < 0 || MaskVals[i] == i)
4973 // The other elements are put in the right place using pextrw and pinsrw.
4974 for (unsigned i = 0; i != 8; ++i) {
4977 int EltIdx = MaskVals[i];
4980 SDValue ExtOp = (EltIdx < 8)
4981 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
4982 DAG.getIntPtrConstant(EltIdx))
4983 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
4984 DAG.getIntPtrConstant(EltIdx - 8));
4985 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
4986 DAG.getIntPtrConstant(i));
4991 // v16i8 shuffles - Prefer shuffles in the following order:
4992 // 1. [ssse3] 1 x pshufb
4993 // 2. [ssse3] 2 x pshufb + 1 x por
4994 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
4996 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
4998 const X86TargetLowering &TLI) {
4999 SDValue V1 = SVOp->getOperand(0);
5000 SDValue V2 = SVOp->getOperand(1);
5001 DebugLoc dl = SVOp->getDebugLoc();
5002 SmallVector<int, 16> MaskVals;
5003 SVOp->getMask(MaskVals);
5005 // If we have SSSE3, case 1 is generated when all result bytes come from
5006 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5007 // present, fall back to case 3.
5008 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5011 for (unsigned i = 0; i < 16; ++i) {
5012 int EltIdx = MaskVals[i];
5021 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5022 if (TLI.getSubtarget()->hasSSSE3()) {
5023 SmallVector<SDValue,16> pshufbMask;
5025 // If all result elements are from one input vector, then only translate
5026 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5028 // Otherwise, we have elements from both input vectors, and must zero out
5029 // elements that come from V2 in the first mask, and V1 in the second mask
5030 // so that we can OR them together.
5031 bool TwoInputs = !(V1Only || V2Only);
5032 for (unsigned i = 0; i != 16; ++i) {
5033 int EltIdx = MaskVals[i];
5034 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5035 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5038 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5040 // If all the elements are from V2, assign it to V1 and return after
5041 // building the first pshufb.
5044 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5045 DAG.getNode(ISD::BUILD_VECTOR, dl,
5046 MVT::v16i8, &pshufbMask[0], 16));
5050 // Calculate the shuffle mask for the second input, shuffle it, and
5051 // OR it with the first shuffled input.
5053 for (unsigned i = 0; i != 16; ++i) {
5054 int EltIdx = MaskVals[i];
5056 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5059 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5061 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5062 DAG.getNode(ISD::BUILD_VECTOR, dl,
5063 MVT::v16i8, &pshufbMask[0], 16));
5064 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5067 // No SSSE3 - Calculate in place words and then fix all out of place words
5068 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5069 // the 16 different words that comprise the two doublequadword input vectors.
5070 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5071 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5072 SDValue NewV = V2Only ? V2 : V1;
5073 for (int i = 0; i != 8; ++i) {
5074 int Elt0 = MaskVals[i*2];
5075 int Elt1 = MaskVals[i*2+1];
5077 // This word of the result is all undef, skip it.
5078 if (Elt0 < 0 && Elt1 < 0)
5081 // This word of the result is already in the correct place, skip it.
5082 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5084 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5087 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5088 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5091 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5092 // using a single extract together, load it and store it.
5093 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5094 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5095 DAG.getIntPtrConstant(Elt1 / 2));
5096 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5097 DAG.getIntPtrConstant(i));
5101 // If Elt1 is defined, extract it from the appropriate source. If the
5102 // source byte is not also odd, shift the extracted word left 8 bits
5103 // otherwise clear the bottom 8 bits if we need to do an or.
5105 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5106 DAG.getIntPtrConstant(Elt1 / 2));
5107 if ((Elt1 & 1) == 0)
5108 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5110 TLI.getShiftAmountTy(InsElt.getValueType())));
5112 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5113 DAG.getConstant(0xFF00, MVT::i16));
5115 // If Elt0 is defined, extract it from the appropriate source. If the
5116 // source byte is not also even, shift the extracted word right 8 bits. If
5117 // Elt1 was also defined, OR the extracted values together before
5118 // inserting them in the result.
5120 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5121 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5122 if ((Elt0 & 1) != 0)
5123 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5125 TLI.getShiftAmountTy(InsElt0.getValueType())));
5127 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5128 DAG.getConstant(0x00FF, MVT::i16));
5129 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5132 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5133 DAG.getIntPtrConstant(i));
5135 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5138 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5139 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5140 /// done when every pair / quad of shuffle mask elements point to elements in
5141 /// the right sequence. e.g.
5142 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5144 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5145 SelectionDAG &DAG, DebugLoc dl) {
5146 EVT VT = SVOp->getValueType(0);
5147 SDValue V1 = SVOp->getOperand(0);
5148 SDValue V2 = SVOp->getOperand(1);
5149 unsigned NumElems = VT.getVectorNumElements();
5150 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5152 switch (VT.getSimpleVT().SimpleTy) {
5153 default: assert(false && "Unexpected!");
5154 case MVT::v4f32: NewVT = MVT::v2f64; break;
5155 case MVT::v4i32: NewVT = MVT::v2i64; break;
5156 case MVT::v8i16: NewVT = MVT::v4i32; break;
5157 case MVT::v16i8: NewVT = MVT::v4i32; break;
5160 int Scale = NumElems / NewWidth;
5161 SmallVector<int, 8> MaskVec;
5162 for (unsigned i = 0; i < NumElems; i += Scale) {
5164 for (int j = 0; j < Scale; ++j) {
5165 int EltIdx = SVOp->getMaskElt(i+j);
5169 StartIdx = EltIdx - (EltIdx % Scale);
5170 if (EltIdx != StartIdx + j)
5174 MaskVec.push_back(-1);
5176 MaskVec.push_back(StartIdx / Scale);
5179 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5180 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5181 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5184 /// getVZextMovL - Return a zero-extending vector move low node.
5186 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5187 SDValue SrcOp, SelectionDAG &DAG,
5188 const X86Subtarget *Subtarget, DebugLoc dl) {
5189 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5190 LoadSDNode *LD = NULL;
5191 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5192 LD = dyn_cast<LoadSDNode>(SrcOp);
5194 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5196 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5197 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5198 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5199 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5200 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5202 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5203 return DAG.getNode(ISD::BITCAST, dl, VT,
5204 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5205 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5213 return DAG.getNode(ISD::BITCAST, dl, VT,
5214 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5215 DAG.getNode(ISD::BITCAST, dl,
5219 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
5222 LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5223 SDValue V1 = SVOp->getOperand(0);
5224 SDValue V2 = SVOp->getOperand(1);
5225 DebugLoc dl = SVOp->getDebugLoc();
5226 EVT VT = SVOp->getValueType(0);
5228 SmallVector<std::pair<int, int>, 8> Locs;
5230 SmallVector<int, 8> Mask1(4U, -1);
5231 SmallVector<int, 8> PermMask;
5232 SVOp->getMask(PermMask);
5236 for (unsigned i = 0; i != 4; ++i) {
5237 int Idx = PermMask[i];
5239 Locs[i] = std::make_pair(-1, -1);
5241 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
5243 Locs[i] = std::make_pair(0, NumLo);
5247 Locs[i] = std::make_pair(1, NumHi);
5249 Mask1[2+NumHi] = Idx;
5255 if (NumLo <= 2 && NumHi <= 2) {
5256 // If no more than two elements come from either vector. This can be
5257 // implemented with two shuffles. First shuffle gather the elements.
5258 // The second shuffle, which takes the first shuffle as both of its
5259 // vector operands, put the elements into the right order.
5260 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5262 SmallVector<int, 8> Mask2(4U, -1);
5264 for (unsigned i = 0; i != 4; ++i) {
5265 if (Locs[i].first == -1)
5268 unsigned Idx = (i < 2) ? 0 : 4;
5269 Idx += Locs[i].first * 2 + Locs[i].second;
5274 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
5275 } else if (NumLo == 3 || NumHi == 3) {
5276 // Otherwise, we must have three elements from one vector, call it X, and
5277 // one element from the other, call it Y. First, use a shufps to build an
5278 // intermediate vector with the one element from Y and the element from X
5279 // that will be in the same half in the final destination (the indexes don't
5280 // matter). Then, use a shufps to build the final vector, taking the half
5281 // containing the element from Y from the intermediate, and the other half
5284 // Normalize it so the 3 elements come from V1.
5285 CommuteVectorShuffleMask(PermMask, VT);
5289 // Find the element from V2.
5291 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
5292 int Val = PermMask[HiIndex];
5299 Mask1[0] = PermMask[HiIndex];
5301 Mask1[2] = PermMask[HiIndex^1];
5303 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5306 Mask1[0] = PermMask[0];
5307 Mask1[1] = PermMask[1];
5308 Mask1[2] = HiIndex & 1 ? 6 : 4;
5309 Mask1[3] = HiIndex & 1 ? 4 : 6;
5310 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5312 Mask1[0] = HiIndex & 1 ? 2 : 0;
5313 Mask1[1] = HiIndex & 1 ? 0 : 2;
5314 Mask1[2] = PermMask[2];
5315 Mask1[3] = PermMask[3];
5320 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
5324 // Break it into (shuffle shuffle_hi, shuffle_lo).
5327 SmallVector<int,8> LoMask(4U, -1);
5328 SmallVector<int,8> HiMask(4U, -1);
5330 SmallVector<int,8> *MaskPtr = &LoMask;
5331 unsigned MaskIdx = 0;
5334 for (unsigned i = 0; i != 4; ++i) {
5341 int Idx = PermMask[i];
5343 Locs[i] = std::make_pair(-1, -1);
5344 } else if (Idx < 4) {
5345 Locs[i] = std::make_pair(MaskIdx, LoIdx);
5346 (*MaskPtr)[LoIdx] = Idx;
5349 Locs[i] = std::make_pair(MaskIdx, HiIdx);
5350 (*MaskPtr)[HiIdx] = Idx;
5355 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
5356 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
5357 SmallVector<int, 8> MaskOps;
5358 for (unsigned i = 0; i != 4; ++i) {
5359 if (Locs[i].first == -1) {
5360 MaskOps.push_back(-1);
5362 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
5363 MaskOps.push_back(Idx);
5366 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
5369 static bool MayFoldVectorLoad(SDValue V) {
5370 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
5371 V = V.getOperand(0);
5372 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5373 V = V.getOperand(0);
5379 // FIXME: the version above should always be used. Since there's
5380 // a bug where several vector shuffles can't be folded because the
5381 // DAG is not updated during lowering and a node claims to have two
5382 // uses while it only has one, use this version, and let isel match
5383 // another instruction if the load really happens to have more than
5384 // one use. Remove this version after this bug get fixed.
5385 // rdar://8434668, PR8156
5386 static bool RelaxedMayFoldVectorLoad(SDValue V) {
5387 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
5388 V = V.getOperand(0);
5389 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5390 V = V.getOperand(0);
5391 if (ISD::isNormalLoad(V.getNode()))
5396 /// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by
5397 /// a vector extract, and if both can be later optimized into a single load.
5398 /// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked
5399 /// here because otherwise a target specific shuffle node is going to be
5400 /// emitted for this shuffle, and the optimization not done.
5401 /// FIXME: This is probably not the best approach, but fix the problem
5402 /// until the right path is decided.
5404 bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
5405 const TargetLowering &TLI) {
5406 EVT VT = V.getValueType();
5407 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V);
5409 // Be sure that the vector shuffle is present in a pattern like this:
5410 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr)
5414 SDNode *N = *V.getNode()->use_begin();
5415 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5418 SDValue EltNo = N->getOperand(1);
5419 if (!isa<ConstantSDNode>(EltNo))
5422 // If the bit convert changed the number of elements, it is unsafe
5423 // to examine the mask.
5424 bool HasShuffleIntoBitcast = false;
5425 if (V.getOpcode() == ISD::BITCAST) {
5426 EVT SrcVT = V.getOperand(0).getValueType();
5427 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
5429 V = V.getOperand(0);
5430 HasShuffleIntoBitcast = true;
5433 // Select the input vector, guarding against out of range extract vector.
5434 unsigned NumElems = VT.getVectorNumElements();
5435 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5436 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
5437 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
5439 // Skip one more bit_convert if necessary
5440 if (V.getOpcode() == ISD::BITCAST)
5441 V = V.getOperand(0);
5443 if (ISD::isNormalLoad(V.getNode())) {
5444 // Is the original load suitable?
5445 LoadSDNode *LN0 = cast<LoadSDNode>(V);
5447 // FIXME: avoid the multi-use bug that is preventing lots of
5448 // of foldings to be detected, this is still wrong of course, but
5449 // give the temporary desired behavior, and if it happens that
5450 // the load has real more uses, during isel it will not fold, and
5451 // will generate poor code.
5452 if (!LN0 || LN0->isVolatile()) // || !LN0->hasOneUse()
5455 if (!HasShuffleIntoBitcast)
5458 // If there's a bitcast before the shuffle, check if the load type and
5459 // alignment is valid.
5460 unsigned Align = LN0->getAlignment();
5462 TLI.getTargetData()->getABITypeAlignment(
5463 VT.getTypeForEVT(*DAG.getContext()));
5465 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
5473 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
5474 EVT VT = Op.getValueType();
5476 // Canonizalize to v2f64.
5477 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
5478 return DAG.getNode(ISD::BITCAST, dl, VT,
5479 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
5484 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
5486 SDValue V1 = Op.getOperand(0);
5487 SDValue V2 = Op.getOperand(1);
5488 EVT VT = Op.getValueType();
5490 assert(VT != MVT::v2i64 && "unsupported shuffle type");
5492 if (HasSSE2 && VT == MVT::v2f64)
5493 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
5496 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V2, DAG);
5500 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
5501 SDValue V1 = Op.getOperand(0);
5502 SDValue V2 = Op.getOperand(1);
5503 EVT VT = Op.getValueType();
5505 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
5506 "unsupported shuffle type");
5508 if (V2.getOpcode() == ISD::UNDEF)
5512 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
5516 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
5517 SDValue V1 = Op.getOperand(0);
5518 SDValue V2 = Op.getOperand(1);
5519 EVT VT = Op.getValueType();
5520 unsigned NumElems = VT.getVectorNumElements();
5522 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
5523 // operand of these instructions is only memory, so check if there's a
5524 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
5526 bool CanFoldLoad = false;
5528 // Trivial case, when V2 comes from a load.
5529 if (MayFoldVectorLoad(V2))
5532 // When V1 is a load, it can be folded later into a store in isel, example:
5533 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
5535 // (MOVLPSmr addr:$src1, VR128:$src2)
5536 // So, recognize this potential and also use MOVLPS or MOVLPD
5537 if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
5540 // Both of them can't be memory operations though.
5541 if (MayFoldVectorLoad(V1) && MayFoldVectorLoad(V2))
5542 CanFoldLoad = false;
5545 if (HasSSE2 && NumElems == 2)
5546 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
5549 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
5552 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5553 // movl and movlp will both match v2i64, but v2i64 is never matched by
5554 // movl earlier because we make it strict to avoid messing with the movlp load
5555 // folding logic (see the code above getMOVLP call). Match it here then,
5556 // this is horrible, but will stay like this until we move all shuffle
5557 // matching to x86 specific nodes. Note that for the 1st condition all
5558 // types are matched with movsd.
5559 if ((HasSSE2 && NumElems == 2) || !X86::isMOVLMask(SVOp))
5560 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
5562 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
5565 assert(VT != MVT::v4i32 && "unsupported shuffle type");
5567 // Invert the operand order and use SHUFPS to match it.
5568 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V2, V1,
5569 X86::getShuffleSHUFImmediate(SVOp), DAG);
5572 static inline unsigned getUNPCKLOpcode(EVT VT, const X86Subtarget *Subtarget) {
5573 switch(VT.getSimpleVT().SimpleTy) {
5574 case MVT::v4i32: return X86ISD::PUNPCKLDQ;
5575 case MVT::v2i64: return X86ISD::PUNPCKLQDQ;
5577 return Subtarget->hasAVX() ? X86ISD::VUNPCKLPS : X86ISD::UNPCKLPS;
5579 return Subtarget->hasAVX() ? X86ISD::VUNPCKLPD : X86ISD::UNPCKLPD;
5580 case MVT::v8f32: return X86ISD::VUNPCKLPSY;
5581 case MVT::v4f64: return X86ISD::VUNPCKLPDY;
5582 case MVT::v16i8: return X86ISD::PUNPCKLBW;
5583 case MVT::v8i16: return X86ISD::PUNPCKLWD;
5585 llvm_unreachable("Unknown type for unpckl");
5590 static inline unsigned getUNPCKHOpcode(EVT VT) {
5591 switch(VT.getSimpleVT().SimpleTy) {
5592 case MVT::v4i32: return X86ISD::PUNPCKHDQ;
5593 case MVT::v2i64: return X86ISD::PUNPCKHQDQ;
5594 case MVT::v4f32: return X86ISD::UNPCKHPS;
5595 case MVT::v2f64: return X86ISD::UNPCKHPD;
5596 case MVT::v16i8: return X86ISD::PUNPCKHBW;
5597 case MVT::v8i16: return X86ISD::PUNPCKHWD;
5599 llvm_unreachable("Unknown type for unpckh");
5605 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
5606 const TargetLowering &TLI,
5607 const X86Subtarget *Subtarget) {
5608 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5609 EVT VT = Op.getValueType();
5610 DebugLoc dl = Op.getDebugLoc();
5611 SDValue V1 = Op.getOperand(0);
5612 SDValue V2 = Op.getOperand(1);
5614 if (isZeroShuffle(SVOp))
5615 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
5617 // Handle splat operations
5618 if (SVOp->isSplat()) {
5619 // Special case, this is the only place now where it's
5620 // allowed to return a vector_shuffle operation without
5621 // using a target specific node, because *hopefully* it
5622 // will be optimized away by the dag combiner.
5623 if (VT.getVectorNumElements() <= 4 &&
5624 CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
5627 // Handle splats by matching through known masks
5628 if (VT.getVectorNumElements() <= 4)
5631 // Canonicalize all of the remaining to v4f32.
5632 return PromoteSplat(SVOp, DAG);
5635 // If the shuffle can be profitably rewritten as a narrower shuffle, then
5637 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
5638 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
5639 if (NewOp.getNode())
5640 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
5641 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
5642 // FIXME: Figure out a cleaner way to do this.
5643 // Try to make use of movq to zero out the top part.
5644 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
5645 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
5646 if (NewOp.getNode()) {
5647 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
5648 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
5649 DAG, Subtarget, dl);
5651 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
5652 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
5653 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
5654 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
5655 DAG, Subtarget, dl);
5662 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
5663 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5664 SDValue V1 = Op.getOperand(0);
5665 SDValue V2 = Op.getOperand(1);
5666 EVT VT = Op.getValueType();
5667 DebugLoc dl = Op.getDebugLoc();
5668 unsigned NumElems = VT.getVectorNumElements();
5669 bool isMMX = VT.getSizeInBits() == 64;
5670 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
5671 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
5672 bool V1IsSplat = false;
5673 bool V2IsSplat = false;
5674 bool HasSSE2 = Subtarget->hasSSE2() || Subtarget->hasAVX();
5675 bool HasSSE3 = Subtarget->hasSSE3() || Subtarget->hasAVX();
5676 bool HasSSSE3 = Subtarget->hasSSSE3() || Subtarget->hasAVX();
5677 MachineFunction &MF = DAG.getMachineFunction();
5678 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
5680 // Shuffle operations on MMX not supported.
5684 // Vector shuffle lowering takes 3 steps:
5686 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
5687 // narrowing and commutation of operands should be handled.
5688 // 2) Matching of shuffles with known shuffle masks to x86 target specific
5690 // 3) Rewriting of unmatched masks into new generic shuffle operations,
5691 // so the shuffle can be broken into other shuffles and the legalizer can
5692 // try the lowering again.
5694 // The general ideia is that no vector_shuffle operation should be left to
5695 // be matched during isel, all of them must be converted to a target specific
5698 // Normalize the input vectors. Here splats, zeroed vectors, profitable
5699 // narrowing and commutation of operands should be handled. The actual code
5700 // doesn't include all of those, work in progress...
5701 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
5702 if (NewOp.getNode())
5705 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
5706 // unpckh_undef). Only use pshufd if speed is more important than size.
5707 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp))
5708 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5709 return getTargetShuffleNode(getUNPCKLOpcode(VT, getSubtarget()), dl, VT, V1, V1, DAG);
5710 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp))
5711 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5712 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
5714 if (X86::isMOVDDUPMask(SVOp) && HasSSE3 && V2IsUndef &&
5715 RelaxedMayFoldVectorLoad(V1))
5716 return getMOVDDup(Op, dl, V1, DAG);
5718 if (X86::isMOVHLPS_v_undef_Mask(SVOp))
5719 return getMOVHighToLow(Op, dl, DAG);
5721 // Use to match splats
5722 if (HasSSE2 && X86::isUNPCKHMask(SVOp) && V2IsUndef &&
5723 (VT == MVT::v2f64 || VT == MVT::v2i64))
5724 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
5726 if (X86::isPSHUFDMask(SVOp)) {
5727 // The actual implementation will match the mask in the if above and then
5728 // during isel it can match several different instructions, not only pshufd
5729 // as its name says, sad but true, emulate the behavior for now...
5730 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
5731 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
5733 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
5735 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
5736 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
5738 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
5739 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V1,
5742 if (VT == MVT::v4f32)
5743 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V1,
5747 // Check if this can be converted into a logical shift.
5748 bool isLeft = false;
5751 bool isShift = getSubtarget()->hasSSE2() &&
5752 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
5753 if (isShift && ShVal.hasOneUse()) {
5754 // If the shifted value has multiple uses, it may be cheaper to use
5755 // v_set0 + movlhps or movhlps, etc.
5756 EVT EltVT = VT.getVectorElementType();
5757 ShAmt *= EltVT.getSizeInBits();
5758 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
5761 if (X86::isMOVLMask(SVOp)) {
5764 if (ISD::isBuildVectorAllZeros(V1.getNode()))
5765 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
5766 if (!X86::isMOVLPMask(SVOp)) {
5767 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
5768 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
5770 if (VT == MVT::v4i32 || VT == MVT::v4f32)
5771 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
5775 // FIXME: fold these into legal mask.
5776 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp))
5777 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
5779 if (X86::isMOVHLPSMask(SVOp))
5780 return getMOVHighToLow(Op, dl, DAG);
5782 if (X86::isMOVSHDUPMask(SVOp) && HasSSE3 && V2IsUndef && NumElems == 4)
5783 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
5785 if (X86::isMOVSLDUPMask(SVOp) && HasSSE3 && V2IsUndef && NumElems == 4)
5786 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
5788 if (X86::isMOVLPMask(SVOp))
5789 return getMOVLP(Op, dl, DAG, HasSSE2);
5791 if (ShouldXformToMOVHLPS(SVOp) ||
5792 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
5793 return CommuteVectorShuffle(SVOp, DAG);
5796 // No better options. Use a vshl / vsrl.
5797 EVT EltVT = VT.getVectorElementType();
5798 ShAmt *= EltVT.getSizeInBits();
5799 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
5802 bool Commuted = false;
5803 // FIXME: This should also accept a bitcast of a splat? Be careful, not
5804 // 1,1,1,1 -> v8i16 though.
5805 V1IsSplat = isSplatVector(V1.getNode());
5806 V2IsSplat = isSplatVector(V2.getNode());
5808 // Canonicalize the splat or undef, if present, to be on the RHS.
5809 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
5810 Op = CommuteVectorShuffle(SVOp, DAG);
5811 SVOp = cast<ShuffleVectorSDNode>(Op);
5812 V1 = SVOp->getOperand(0);
5813 V2 = SVOp->getOperand(1);
5814 std::swap(V1IsSplat, V2IsSplat);
5815 std::swap(V1IsUndef, V2IsUndef);
5819 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
5820 // Shuffling low element of v1 into undef, just return v1.
5823 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
5824 // the instruction selector will not match, so get a canonical MOVL with
5825 // swapped operands to undo the commute.
5826 return getMOVL(DAG, dl, VT, V2, V1);
5829 if (X86::isUNPCKLMask(SVOp))
5830 return getTargetShuffleNode(getUNPCKLOpcode(VT, getSubtarget()),
5831 dl, VT, V1, V2, DAG);
5833 if (X86::isUNPCKHMask(SVOp))
5834 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V2, DAG);
5837 // Normalize mask so all entries that point to V2 points to its first
5838 // element then try to match unpck{h|l} again. If match, return a
5839 // new vector_shuffle with the corrected mask.
5840 SDValue NewMask = NormalizeMask(SVOp, DAG);
5841 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
5842 if (NSVOp != SVOp) {
5843 if (X86::isUNPCKLMask(NSVOp, true)) {
5845 } else if (X86::isUNPCKHMask(NSVOp, true)) {
5852 // Commute is back and try unpck* again.
5853 // FIXME: this seems wrong.
5854 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
5855 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
5857 if (X86::isUNPCKLMask(NewSVOp))
5858 return getTargetShuffleNode(getUNPCKLOpcode(VT, getSubtarget()),
5859 dl, VT, V2, V1, DAG);
5861 if (X86::isUNPCKHMask(NewSVOp))
5862 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V2, V1, DAG);
5865 // Normalize the node to match x86 shuffle ops if needed
5866 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
5867 return CommuteVectorShuffle(SVOp, DAG);
5869 // The checks below are all present in isShuffleMaskLegal, but they are
5870 // inlined here right now to enable us to directly emit target specific
5871 // nodes, and remove one by one until they don't return Op anymore.
5872 SmallVector<int, 16> M;
5875 if (isPALIGNRMask(M, VT, HasSSSE3))
5876 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
5877 X86::getShufflePALIGNRImmediate(SVOp),
5880 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
5881 SVOp->getSplatIndex() == 0 && V2IsUndef) {
5882 if (VT == MVT::v2f64) {
5883 X86ISD::NodeType Opcode =
5884 getSubtarget()->hasAVX() ? X86ISD::VUNPCKLPD : X86ISD::UNPCKLPD;
5885 return getTargetShuffleNode(Opcode, dl, VT, V1, V1, DAG);
5887 if (VT == MVT::v2i64)
5888 return getTargetShuffleNode(X86ISD::PUNPCKLQDQ, dl, VT, V1, V1, DAG);
5891 if (isPSHUFHWMask(M, VT))
5892 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
5893 X86::getShufflePSHUFHWImmediate(SVOp),
5896 if (isPSHUFLWMask(M, VT))
5897 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
5898 X86::getShufflePSHUFLWImmediate(SVOp),
5901 if (isSHUFPMask(M, VT)) {
5902 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
5903 if (VT == MVT::v4f32 || VT == MVT::v4i32)
5904 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V2,
5906 if (VT == MVT::v2f64 || VT == MVT::v2i64)
5907 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V2,
5911 if (X86::isUNPCKL_v_undef_Mask(SVOp))
5912 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5913 return getTargetShuffleNode(getUNPCKLOpcode(VT, getSubtarget()),
5914 dl, VT, V1, V1, DAG);
5915 if (X86::isUNPCKH_v_undef_Mask(SVOp))
5916 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5917 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
5919 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
5920 if (VT == MVT::v8i16) {
5921 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
5922 if (NewOp.getNode())
5926 if (VT == MVT::v16i8) {
5927 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
5928 if (NewOp.getNode())
5932 // Handle all 4 wide cases with a number of shuffles.
5934 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
5940 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
5941 SelectionDAG &DAG) const {
5942 EVT VT = Op.getValueType();
5943 DebugLoc dl = Op.getDebugLoc();
5944 if (VT.getSizeInBits() == 8) {
5945 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
5946 Op.getOperand(0), Op.getOperand(1));
5947 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
5948 DAG.getValueType(VT));
5949 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
5950 } else if (VT.getSizeInBits() == 16) {
5951 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5952 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
5954 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
5955 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
5956 DAG.getNode(ISD::BITCAST, dl,
5960 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
5961 Op.getOperand(0), Op.getOperand(1));
5962 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
5963 DAG.getValueType(VT));
5964 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
5965 } else if (VT == MVT::f32) {
5966 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
5967 // the result back to FR32 register. It's only worth matching if the
5968 // result has a single use which is a store or a bitcast to i32. And in
5969 // the case of a store, it's not worth it if the index is a constant 0,
5970 // because a MOVSSmr can be used instead, which is smaller and faster.
5971 if (!Op.hasOneUse())
5973 SDNode *User = *Op.getNode()->use_begin();
5974 if ((User->getOpcode() != ISD::STORE ||
5975 (isa<ConstantSDNode>(Op.getOperand(1)) &&
5976 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
5977 (User->getOpcode() != ISD::BITCAST ||
5978 User->getValueType(0) != MVT::i32))
5980 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
5981 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
5984 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
5985 } else if (VT == MVT::i32) {
5986 // ExtractPS works with constant index.
5987 if (isa<ConstantSDNode>(Op.getOperand(1)))
5995 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
5996 SelectionDAG &DAG) const {
5997 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6000 SDValue Vec = Op.getOperand(0);
6001 EVT VecVT = Vec.getValueType();
6003 // If this is a 256-bit vector result, first extract the 128-bit
6004 // vector and then extract from the 128-bit vector.
6005 if (VecVT.getSizeInBits() > 128) {
6006 DebugLoc dl = Op.getNode()->getDebugLoc();
6007 unsigned NumElems = VecVT.getVectorNumElements();
6008 SDValue Idx = Op.getOperand(1);
6010 if (!isa<ConstantSDNode>(Idx))
6013 unsigned ExtractNumElems = NumElems / (VecVT.getSizeInBits() / 128);
6014 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6016 // Get the 128-bit vector.
6017 bool Upper = IdxVal >= ExtractNumElems;
6018 Vec = Extract128BitVector(Vec, Idx, DAG, dl);
6021 SDValue ScaledIdx = Idx;
6023 ScaledIdx = DAG.getNode(ISD::SUB, dl, Idx.getValueType(), Idx,
6024 DAG.getConstant(ExtractNumElems,
6025 Idx.getValueType()));
6026 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6030 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6032 if (Subtarget->hasSSE41()) {
6033 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6038 EVT VT = Op.getValueType();
6039 DebugLoc dl = Op.getDebugLoc();
6040 // TODO: handle v16i8.
6041 if (VT.getSizeInBits() == 16) {
6042 SDValue Vec = Op.getOperand(0);
6043 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6045 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6046 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6047 DAG.getNode(ISD::BITCAST, dl,
6050 // Transform it so it match pextrw which produces a 32-bit result.
6051 EVT EltVT = MVT::i32;
6052 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6053 Op.getOperand(0), Op.getOperand(1));
6054 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6055 DAG.getValueType(VT));
6056 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6057 } else if (VT.getSizeInBits() == 32) {
6058 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6062 // SHUFPS the element to the lowest double word, then movss.
6063 int Mask[4] = { Idx, -1, -1, -1 };
6064 EVT VVT = Op.getOperand(0).getValueType();
6065 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6066 DAG.getUNDEF(VVT), Mask);
6067 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6068 DAG.getIntPtrConstant(0));
6069 } else if (VT.getSizeInBits() == 64) {
6070 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6071 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6072 // to match extract_elt for f64.
6073 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6077 // UNPCKHPD the element to the lowest double word, then movsd.
6078 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6079 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6080 int Mask[2] = { 1, -1 };
6081 EVT VVT = Op.getOperand(0).getValueType();
6082 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6083 DAG.getUNDEF(VVT), Mask);
6084 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6085 DAG.getIntPtrConstant(0));
6092 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6093 SelectionDAG &DAG) const {
6094 EVT VT = Op.getValueType();
6095 EVT EltVT = VT.getVectorElementType();
6096 DebugLoc dl = Op.getDebugLoc();
6098 SDValue N0 = Op.getOperand(0);
6099 SDValue N1 = Op.getOperand(1);
6100 SDValue N2 = Op.getOperand(2);
6102 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6103 isa<ConstantSDNode>(N2)) {
6105 if (VT == MVT::v8i16)
6106 Opc = X86ISD::PINSRW;
6107 else if (VT == MVT::v16i8)
6108 Opc = X86ISD::PINSRB;
6110 Opc = X86ISD::PINSRB;
6112 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6114 if (N1.getValueType() != MVT::i32)
6115 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6116 if (N2.getValueType() != MVT::i32)
6117 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6118 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6119 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6120 // Bits [7:6] of the constant are the source select. This will always be
6121 // zero here. The DAG Combiner may combine an extract_elt index into these
6122 // bits. For example (insert (extract, 3), 2) could be matched by putting
6123 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6124 // Bits [5:4] of the constant are the destination select. This is the
6125 // value of the incoming immediate.
6126 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6127 // combine either bitwise AND or insert of float 0.0 to set these bits.
6128 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6129 // Create this as a scalar to vector..
6130 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6131 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6132 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
6133 // PINSR* works with constant index.
6140 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
6141 EVT VT = Op.getValueType();
6142 EVT EltVT = VT.getVectorElementType();
6144 DebugLoc dl = Op.getDebugLoc();
6145 SDValue N0 = Op.getOperand(0);
6146 SDValue N1 = Op.getOperand(1);
6147 SDValue N2 = Op.getOperand(2);
6149 // If this is a 256-bit vector result, first insert into a 128-bit
6150 // vector and then insert into the 256-bit vector.
6151 if (VT.getSizeInBits() > 128) {
6152 if (!isa<ConstantSDNode>(N2))
6155 // Get the 128-bit vector.
6156 unsigned NumElems = VT.getVectorNumElements();
6157 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
6158 bool Upper = IdxVal >= NumElems / 2;
6160 SDValue SubN0 = Extract128BitVector(N0, N2, DAG, dl);
6163 SDValue ScaledN2 = N2;
6165 ScaledN2 = DAG.getNode(ISD::SUB, dl, N2.getValueType(), N2,
6166 DAG.getConstant(NumElems /
6167 (VT.getSizeInBits() / 128),
6168 N2.getValueType()));
6169 Op = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, SubN0.getValueType(), SubN0,
6172 // Insert the 128-bit vector
6173 // FIXME: Why UNDEF?
6174 return Insert128BitVector(N0, Op, N2, DAG, dl);
6177 if (Subtarget->hasSSE41())
6178 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
6180 if (EltVT == MVT::i8)
6183 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
6184 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
6185 // as its second argument.
6186 if (N1.getValueType() != MVT::i32)
6187 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6188 if (N2.getValueType() != MVT::i32)
6189 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6190 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
6196 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6197 LLVMContext *Context = DAG.getContext();
6198 DebugLoc dl = Op.getDebugLoc();
6199 EVT OpVT = Op.getValueType();
6201 // If this is a 256-bit vector result, first insert into a 128-bit
6202 // vector and then insert into the 256-bit vector.
6203 if (OpVT.getSizeInBits() > 128) {
6204 // Insert into a 128-bit vector.
6205 EVT VT128 = EVT::getVectorVT(*Context,
6206 OpVT.getVectorElementType(),
6207 OpVT.getVectorNumElements() / 2);
6209 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
6211 // Insert the 128-bit vector.
6212 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op,
6213 DAG.getConstant(0, MVT::i32),
6217 if (Op.getValueType() == MVT::v1i64 &&
6218 Op.getOperand(0).getValueType() == MVT::i64)
6219 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
6221 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
6222 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
6223 "Expected an SSE type!");
6224 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
6225 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
6228 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
6229 // a simple subregister reference or explicit instructions to grab
6230 // upper bits of a vector.
6232 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
6233 if (Subtarget->hasAVX()) {
6234 DebugLoc dl = Op.getNode()->getDebugLoc();
6235 SDValue Vec = Op.getNode()->getOperand(0);
6236 SDValue Idx = Op.getNode()->getOperand(1);
6238 if (Op.getNode()->getValueType(0).getSizeInBits() == 128
6239 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) {
6240 return Extract128BitVector(Vec, Idx, DAG, dl);
6246 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
6247 // simple superregister reference or explicit instructions to insert
6248 // the upper bits of a vector.
6250 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
6251 if (Subtarget->hasAVX()) {
6252 DebugLoc dl = Op.getNode()->getDebugLoc();
6253 SDValue Vec = Op.getNode()->getOperand(0);
6254 SDValue SubVec = Op.getNode()->getOperand(1);
6255 SDValue Idx = Op.getNode()->getOperand(2);
6257 if (Op.getNode()->getValueType(0).getSizeInBits() == 256
6258 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) {
6259 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl);
6265 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
6266 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
6267 // one of the above mentioned nodes. It has to be wrapped because otherwise
6268 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
6269 // be used to form addressing mode. These wrapped nodes will be selected
6272 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
6273 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
6275 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6277 unsigned char OpFlag = 0;
6278 unsigned WrapperKind = X86ISD::Wrapper;
6279 CodeModel::Model M = getTargetMachine().getCodeModel();
6281 if (Subtarget->isPICStyleRIPRel() &&
6282 (M == CodeModel::Small || M == CodeModel::Kernel))
6283 WrapperKind = X86ISD::WrapperRIP;
6284 else if (Subtarget->isPICStyleGOT())
6285 OpFlag = X86II::MO_GOTOFF;
6286 else if (Subtarget->isPICStyleStubPIC())
6287 OpFlag = X86II::MO_PIC_BASE_OFFSET;
6289 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
6291 CP->getOffset(), OpFlag);
6292 DebugLoc DL = CP->getDebugLoc();
6293 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6294 // With PIC, the address is actually $g + Offset.
6296 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
6297 DAG.getNode(X86ISD::GlobalBaseReg,
6298 DebugLoc(), getPointerTy()),
6305 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
6306 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
6308 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6310 unsigned char OpFlag = 0;
6311 unsigned WrapperKind = X86ISD::Wrapper;
6312 CodeModel::Model M = getTargetMachine().getCodeModel();
6314 if (Subtarget->isPICStyleRIPRel() &&
6315 (M == CodeModel::Small || M == CodeModel::Kernel))
6316 WrapperKind = X86ISD::WrapperRIP;
6317 else if (Subtarget->isPICStyleGOT())
6318 OpFlag = X86II::MO_GOTOFF;
6319 else if (Subtarget->isPICStyleStubPIC())
6320 OpFlag = X86II::MO_PIC_BASE_OFFSET;
6322 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
6324 DebugLoc DL = JT->getDebugLoc();
6325 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6327 // With PIC, the address is actually $g + Offset.
6329 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
6330 DAG.getNode(X86ISD::GlobalBaseReg,
6331 DebugLoc(), getPointerTy()),
6338 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
6339 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
6341 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6343 unsigned char OpFlag = 0;
6344 unsigned WrapperKind = X86ISD::Wrapper;
6345 CodeModel::Model M = getTargetMachine().getCodeModel();
6347 if (Subtarget->isPICStyleRIPRel() &&
6348 (M == CodeModel::Small || M == CodeModel::Kernel))
6349 WrapperKind = X86ISD::WrapperRIP;
6350 else if (Subtarget->isPICStyleGOT())
6351 OpFlag = X86II::MO_GOTOFF;
6352 else if (Subtarget->isPICStyleStubPIC())
6353 OpFlag = X86II::MO_PIC_BASE_OFFSET;
6355 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
6357 DebugLoc DL = Op.getDebugLoc();
6358 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6361 // With PIC, the address is actually $g + Offset.
6362 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
6363 !Subtarget->is64Bit()) {
6364 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
6365 DAG.getNode(X86ISD::GlobalBaseReg,
6366 DebugLoc(), getPointerTy()),
6374 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
6375 // Create the TargetBlockAddressAddress node.
6376 unsigned char OpFlags =
6377 Subtarget->ClassifyBlockAddressReference();
6378 CodeModel::Model M = getTargetMachine().getCodeModel();
6379 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
6380 DebugLoc dl = Op.getDebugLoc();
6381 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
6382 /*isTarget=*/true, OpFlags);
6384 if (Subtarget->isPICStyleRIPRel() &&
6385 (M == CodeModel::Small || M == CodeModel::Kernel))
6386 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
6388 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
6390 // With PIC, the address is actually $g + Offset.
6391 if (isGlobalRelativeToPICBase(OpFlags)) {
6392 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6393 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
6401 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
6403 SelectionDAG &DAG) const {
6404 // Create the TargetGlobalAddress node, folding in the constant
6405 // offset if it is legal.
6406 unsigned char OpFlags =
6407 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
6408 CodeModel::Model M = getTargetMachine().getCodeModel();
6410 if (OpFlags == X86II::MO_NO_FLAG &&
6411 X86::isOffsetSuitableForCodeModel(Offset, M)) {
6412 // A direct static reference to a global.
6413 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
6416 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
6419 if (Subtarget->isPICStyleRIPRel() &&
6420 (M == CodeModel::Small || M == CodeModel::Kernel))
6421 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
6423 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
6425 // With PIC, the address is actually $g + Offset.
6426 if (isGlobalRelativeToPICBase(OpFlags)) {
6427 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6428 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
6432 // For globals that require a load from a stub to get the address, emit the
6434 if (isGlobalStubReference(OpFlags))
6435 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
6436 MachinePointerInfo::getGOT(), false, false, 0);
6438 // If there was a non-zero offset that we didn't fold, create an explicit
6441 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
6442 DAG.getConstant(Offset, getPointerTy()));
6448 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
6449 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
6450 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
6451 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
6455 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
6456 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
6457 unsigned char OperandFlags) {
6458 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6459 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6460 DebugLoc dl = GA->getDebugLoc();
6461 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
6462 GA->getValueType(0),
6466 SDValue Ops[] = { Chain, TGA, *InFlag };
6467 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
6469 SDValue Ops[] = { Chain, TGA };
6470 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
6473 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
6474 MFI->setAdjustsStack(true);
6476 SDValue Flag = Chain.getValue(1);
6477 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
6480 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
6482 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
6485 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
6486 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
6487 DAG.getNode(X86ISD::GlobalBaseReg,
6488 DebugLoc(), PtrVT), InFlag);
6489 InFlag = Chain.getValue(1);
6491 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
6494 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
6496 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
6498 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
6499 X86::RAX, X86II::MO_TLSGD);
6502 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
6503 // "local exec" model.
6504 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
6505 const EVT PtrVT, TLSModel::Model model,
6507 DebugLoc dl = GA->getDebugLoc();
6509 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
6510 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
6511 is64Bit ? 257 : 256));
6513 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
6514 DAG.getIntPtrConstant(0),
6515 MachinePointerInfo(Ptr), false, false, 0);
6517 unsigned char OperandFlags = 0;
6518 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
6520 unsigned WrapperKind = X86ISD::Wrapper;
6521 if (model == TLSModel::LocalExec) {
6522 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
6523 } else if (is64Bit) {
6524 assert(model == TLSModel::InitialExec);
6525 OperandFlags = X86II::MO_GOTTPOFF;
6526 WrapperKind = X86ISD::WrapperRIP;
6528 assert(model == TLSModel::InitialExec);
6529 OperandFlags = X86II::MO_INDNTPOFF;
6532 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
6534 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
6535 GA->getValueType(0),
6536 GA->getOffset(), OperandFlags);
6537 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
6539 if (model == TLSModel::InitialExec)
6540 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
6541 MachinePointerInfo::getGOT(), false, false, 0);
6543 // The address of the thread local variable is the add of the thread
6544 // pointer with the offset of the variable.
6545 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
6549 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
6551 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
6552 const GlobalValue *GV = GA->getGlobal();
6554 if (Subtarget->isTargetELF()) {
6555 // TODO: implement the "local dynamic" model
6556 // TODO: implement the "initial exec"model for pic executables
6558 // If GV is an alias then use the aliasee for determining
6559 // thread-localness.
6560 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
6561 GV = GA->resolveAliasedGlobal(false);
6563 TLSModel::Model model
6564 = getTLSModel(GV, getTargetMachine().getRelocationModel());
6567 case TLSModel::GeneralDynamic:
6568 case TLSModel::LocalDynamic: // not implemented
6569 if (Subtarget->is64Bit())
6570 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
6571 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
6573 case TLSModel::InitialExec:
6574 case TLSModel::LocalExec:
6575 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
6576 Subtarget->is64Bit());
6578 } else if (Subtarget->isTargetDarwin()) {
6579 // Darwin only has one model of TLS. Lower to that.
6580 unsigned char OpFlag = 0;
6581 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
6582 X86ISD::WrapperRIP : X86ISD::Wrapper;
6584 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6586 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
6587 !Subtarget->is64Bit();
6589 OpFlag = X86II::MO_TLVP_PIC_BASE;
6591 OpFlag = X86II::MO_TLVP;
6592 DebugLoc DL = Op.getDebugLoc();
6593 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
6594 GA->getValueType(0),
6595 GA->getOffset(), OpFlag);
6596 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6598 // With PIC32, the address is actually $g + Offset.
6600 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
6601 DAG.getNode(X86ISD::GlobalBaseReg,
6602 DebugLoc(), getPointerTy()),
6605 // Lowering the machine isd will make sure everything is in the right
6607 SDValue Chain = DAG.getEntryNode();
6608 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6609 SDValue Args[] = { Chain, Offset };
6610 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
6612 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
6613 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6614 MFI->setAdjustsStack(true);
6616 // And our return value (tls address) is in the standard call return value
6618 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
6619 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
6623 "TLS not implemented for this target.");
6625 llvm_unreachable("Unreachable");
6630 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values and
6631 /// take a 2 x i32 value to shift plus a shift amount.
6632 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const {
6633 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
6634 EVT VT = Op.getValueType();
6635 unsigned VTBits = VT.getSizeInBits();
6636 DebugLoc dl = Op.getDebugLoc();
6637 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
6638 SDValue ShOpLo = Op.getOperand(0);
6639 SDValue ShOpHi = Op.getOperand(1);
6640 SDValue ShAmt = Op.getOperand(2);
6641 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
6642 DAG.getConstant(VTBits - 1, MVT::i8))
6643 : DAG.getConstant(0, VT);
6646 if (Op.getOpcode() == ISD::SHL_PARTS) {
6647 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
6648 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
6650 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
6651 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
6654 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
6655 DAG.getConstant(VTBits, MVT::i8));
6656 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
6657 AndNode, DAG.getConstant(0, MVT::i8));
6660 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6661 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
6662 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
6664 if (Op.getOpcode() == ISD::SHL_PARTS) {
6665 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
6666 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
6668 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
6669 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
6672 SDValue Ops[2] = { Lo, Hi };
6673 return DAG.getMergeValues(Ops, 2, dl);
6676 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
6677 SelectionDAG &DAG) const {
6678 EVT SrcVT = Op.getOperand(0).getValueType();
6680 if (SrcVT.isVector())
6683 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
6684 "Unknown SINT_TO_FP to lower!");
6686 // These are really Legal; return the operand so the caller accepts it as
6688 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
6690 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
6691 Subtarget->is64Bit()) {
6695 DebugLoc dl = Op.getDebugLoc();
6696 unsigned Size = SrcVT.getSizeInBits()/8;
6697 MachineFunction &MF = DAG.getMachineFunction();
6698 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
6699 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6700 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
6702 MachinePointerInfo::getFixedStack(SSFI),
6704 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
6707 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
6709 SelectionDAG &DAG) const {
6711 DebugLoc DL = Op.getDebugLoc();
6713 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
6715 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
6717 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
6719 unsigned ByteSize = SrcVT.getSizeInBits()/8;
6721 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
6722 MachineMemOperand *MMO =
6723 DAG.getMachineFunction()
6724 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6725 MachineMemOperand::MOLoad, ByteSize, ByteSize);
6727 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
6728 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
6730 Tys, Ops, array_lengthof(Ops),
6734 Chain = Result.getValue(1);
6735 SDValue InFlag = Result.getValue(2);
6737 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
6738 // shouldn't be necessary except that RFP cannot be live across
6739 // multiple blocks. When stackifier is fixed, they can be uncoupled.
6740 MachineFunction &MF = DAG.getMachineFunction();
6741 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
6742 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
6743 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6744 Tys = DAG.getVTList(MVT::Other);
6746 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
6748 MachineMemOperand *MMO =
6749 DAG.getMachineFunction()
6750 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6751 MachineMemOperand::MOStore, SSFISize, SSFISize);
6753 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
6754 Ops, array_lengthof(Ops),
6755 Op.getValueType(), MMO);
6756 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
6757 MachinePointerInfo::getFixedStack(SSFI),
6764 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
6765 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
6766 SelectionDAG &DAG) const {
6767 // This algorithm is not obvious. Here it is in C code, more or less:
6769 double uint64_to_double( uint32_t hi, uint32_t lo ) {
6770 static const __m128i exp = { 0x4330000045300000ULL, 0 };
6771 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
6773 // Copy ints to xmm registers.
6774 __m128i xh = _mm_cvtsi32_si128( hi );
6775 __m128i xl = _mm_cvtsi32_si128( lo );
6777 // Combine into low half of a single xmm register.
6778 __m128i x = _mm_unpacklo_epi32( xh, xl );
6782 // Merge in appropriate exponents to give the integer bits the right
6784 x = _mm_unpacklo_epi32( x, exp );
6786 // Subtract away the biases to deal with the IEEE-754 double precision
6788 d = _mm_sub_pd( (__m128d) x, bias );
6790 // All conversions up to here are exact. The correctly rounded result is
6791 // calculated using the current rounding mode using the following
6793 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
6794 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
6795 // store doesn't really need to be here (except
6796 // maybe to zero the other double)
6801 DebugLoc dl = Op.getDebugLoc();
6802 LLVMContext *Context = DAG.getContext();
6804 // Build some magic constants.
6805 std::vector<Constant*> CV0;
6806 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
6807 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
6808 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
6809 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
6810 Constant *C0 = ConstantVector::get(CV0);
6811 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
6813 std::vector<Constant*> CV1;
6815 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
6817 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
6818 Constant *C1 = ConstantVector::get(CV1);
6819 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
6821 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
6822 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6824 DAG.getIntPtrConstant(1)));
6825 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
6826 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6828 DAG.getIntPtrConstant(0)));
6829 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
6830 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
6831 MachinePointerInfo::getConstantPool(),
6833 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
6834 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck2);
6835 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
6836 MachinePointerInfo::getConstantPool(),
6838 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
6840 // Add the halves; easiest way is to swap them into another reg first.
6841 int ShufMask[2] = { 1, -1 };
6842 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
6843 DAG.getUNDEF(MVT::v2f64), ShufMask);
6844 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
6845 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
6846 DAG.getIntPtrConstant(0));
6849 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
6850 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
6851 SelectionDAG &DAG) const {
6852 DebugLoc dl = Op.getDebugLoc();
6853 // FP constant to bias correct the final result.
6854 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
6857 // Load the 32-bit value into an XMM register.
6858 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
6859 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6861 DAG.getIntPtrConstant(0)));
6863 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
6864 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
6865 DAG.getIntPtrConstant(0));
6867 // Or the load with the bias.
6868 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
6869 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
6870 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6872 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
6873 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6874 MVT::v2f64, Bias)));
6875 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
6876 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
6877 DAG.getIntPtrConstant(0));
6879 // Subtract the bias.
6880 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
6882 // Handle final rounding.
6883 EVT DestVT = Op.getValueType();
6885 if (DestVT.bitsLT(MVT::f64)) {
6886 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
6887 DAG.getIntPtrConstant(0));
6888 } else if (DestVT.bitsGT(MVT::f64)) {
6889 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
6892 // Handle final rounding.
6896 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
6897 SelectionDAG &DAG) const {
6898 SDValue N0 = Op.getOperand(0);
6899 DebugLoc dl = Op.getDebugLoc();
6901 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
6902 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
6903 // the optimization here.
6904 if (DAG.SignBitIsZero(N0))
6905 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
6907 EVT SrcVT = N0.getValueType();
6908 EVT DstVT = Op.getValueType();
6909 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
6910 return LowerUINT_TO_FP_i64(Op, DAG);
6911 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
6912 return LowerUINT_TO_FP_i32(Op, DAG);
6914 // Make a 64-bit buffer, and use it to build an FILD.
6915 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
6916 if (SrcVT == MVT::i32) {
6917 SDValue WordOff = DAG.getConstant(4, getPointerTy());
6918 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
6919 getPointerTy(), StackSlot, WordOff);
6920 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
6921 StackSlot, MachinePointerInfo(),
6923 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
6924 OffsetSlot, MachinePointerInfo(),
6926 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
6930 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
6931 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
6932 StackSlot, MachinePointerInfo(),
6934 // For i64 source, we need to add the appropriate power of 2 if the input
6935 // was negative. This is the same as the optimization in
6936 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
6937 // we must be careful to do the computation in x87 extended precision, not
6938 // in SSE. (The generic code can't know it's OK to do this, or how to.)
6939 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
6940 MachineMemOperand *MMO =
6941 DAG.getMachineFunction()
6942 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6943 MachineMemOperand::MOLoad, 8, 8);
6945 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
6946 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
6947 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
6950 APInt FF(32, 0x5F800000ULL);
6952 // Check whether the sign bit is set.
6953 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
6954 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
6957 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
6958 SDValue FudgePtr = DAG.getConstantPool(
6959 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
6962 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
6963 SDValue Zero = DAG.getIntPtrConstant(0);
6964 SDValue Four = DAG.getIntPtrConstant(4);
6965 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
6967 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
6969 // Load the value out, extending it from f32 to f80.
6970 // FIXME: Avoid the extend by constructing the right constant pool?
6971 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
6972 FudgePtr, MachinePointerInfo::getConstantPool(),
6973 MVT::f32, false, false, 4);
6974 // Extend everything to 80 bits to force it to be done on x87.
6975 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
6976 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
6979 std::pair<SDValue,SDValue> X86TargetLowering::
6980 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
6981 DebugLoc DL = Op.getDebugLoc();
6983 EVT DstTy = Op.getValueType();
6986 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
6990 assert(DstTy.getSimpleVT() <= MVT::i64 &&
6991 DstTy.getSimpleVT() >= MVT::i16 &&
6992 "Unknown FP_TO_SINT to lower!");
6994 // These are really Legal.
6995 if (DstTy == MVT::i32 &&
6996 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
6997 return std::make_pair(SDValue(), SDValue());
6998 if (Subtarget->is64Bit() &&
6999 DstTy == MVT::i64 &&
7000 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7001 return std::make_pair(SDValue(), SDValue());
7003 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
7005 MachineFunction &MF = DAG.getMachineFunction();
7006 unsigned MemSize = DstTy.getSizeInBits()/8;
7007 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7008 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7013 switch (DstTy.getSimpleVT().SimpleTy) {
7014 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7015 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7016 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7017 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7020 SDValue Chain = DAG.getEntryNode();
7021 SDValue Value = Op.getOperand(0);
7022 EVT TheVT = Op.getOperand(0).getValueType();
7023 if (isScalarFPTypeInSSEReg(TheVT)) {
7024 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7025 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7026 MachinePointerInfo::getFixedStack(SSFI),
7028 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7030 Chain, StackSlot, DAG.getValueType(TheVT)
7033 MachineMemOperand *MMO =
7034 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7035 MachineMemOperand::MOLoad, MemSize, MemSize);
7036 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7038 Chain = Value.getValue(1);
7039 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7040 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7043 MachineMemOperand *MMO =
7044 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7045 MachineMemOperand::MOStore, MemSize, MemSize);
7047 // Build the FP_TO_INT*_IN_MEM
7048 SDValue Ops[] = { Chain, Value, StackSlot };
7049 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7050 Ops, 3, DstTy, MMO);
7052 return std::make_pair(FIST, StackSlot);
7055 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7056 SelectionDAG &DAG) const {
7057 if (Op.getValueType().isVector())
7060 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
7061 SDValue FIST = Vals.first, StackSlot = Vals.second;
7062 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7063 if (FIST.getNode() == 0) return Op;
7066 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7067 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
7070 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7071 SelectionDAG &DAG) const {
7072 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
7073 SDValue FIST = Vals.first, StackSlot = Vals.second;
7074 assert(FIST.getNode() && "Unexpected failure");
7077 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7078 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
7081 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7082 SelectionDAG &DAG) const {
7083 LLVMContext *Context = DAG.getContext();
7084 DebugLoc dl = Op.getDebugLoc();
7085 EVT VT = Op.getValueType();
7088 EltVT = VT.getVectorElementType();
7089 std::vector<Constant*> CV;
7090 if (EltVT == MVT::f64) {
7091 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
7095 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
7101 Constant *C = ConstantVector::get(CV);
7102 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7103 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7104 MachinePointerInfo::getConstantPool(),
7106 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
7109 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
7110 LLVMContext *Context = DAG.getContext();
7111 DebugLoc dl = Op.getDebugLoc();
7112 EVT VT = Op.getValueType();
7115 EltVT = VT.getVectorElementType();
7116 std::vector<Constant*> CV;
7117 if (EltVT == MVT::f64) {
7118 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
7122 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
7128 Constant *C = ConstantVector::get(CV);
7129 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7130 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7131 MachinePointerInfo::getConstantPool(),
7133 if (VT.isVector()) {
7134 return DAG.getNode(ISD::BITCAST, dl, VT,
7135 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
7136 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7138 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Mask)));
7140 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
7144 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
7145 LLVMContext *Context = DAG.getContext();
7146 SDValue Op0 = Op.getOperand(0);
7147 SDValue Op1 = Op.getOperand(1);
7148 DebugLoc dl = Op.getDebugLoc();
7149 EVT VT = Op.getValueType();
7150 EVT SrcVT = Op1.getValueType();
7152 // If second operand is smaller, extend it first.
7153 if (SrcVT.bitsLT(VT)) {
7154 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
7157 // And if it is bigger, shrink it first.
7158 if (SrcVT.bitsGT(VT)) {
7159 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
7163 // At this point the operands and the result should have the same
7164 // type, and that won't be f80 since that is not custom lowered.
7166 // First get the sign bit of second operand.
7167 std::vector<Constant*> CV;
7168 if (SrcVT == MVT::f64) {
7169 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
7170 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7172 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
7173 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7174 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7175 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7177 Constant *C = ConstantVector::get(CV);
7178 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7179 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
7180 MachinePointerInfo::getConstantPool(),
7182 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
7184 // Shift sign bit right or left if the two operands have different types.
7185 if (SrcVT.bitsGT(VT)) {
7186 // Op0 is MVT::f32, Op1 is MVT::f64.
7187 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
7188 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
7189 DAG.getConstant(32, MVT::i32));
7190 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
7191 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
7192 DAG.getIntPtrConstant(0));
7195 // Clear first operand sign bit.
7197 if (VT == MVT::f64) {
7198 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
7199 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7201 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
7202 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7203 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7204 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7206 C = ConstantVector::get(CV);
7207 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7208 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7209 MachinePointerInfo::getConstantPool(),
7211 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
7213 // Or the value with the sign bit.
7214 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
7217 /// Emit nodes that will be selected as "test Op0,Op0", or something
7219 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
7220 SelectionDAG &DAG) const {
7221 DebugLoc dl = Op.getDebugLoc();
7223 // CF and OF aren't always set the way we want. Determine which
7224 // of these we need.
7225 bool NeedCF = false;
7226 bool NeedOF = false;
7229 case X86::COND_A: case X86::COND_AE:
7230 case X86::COND_B: case X86::COND_BE:
7233 case X86::COND_G: case X86::COND_GE:
7234 case X86::COND_L: case X86::COND_LE:
7235 case X86::COND_O: case X86::COND_NO:
7240 // See if we can use the EFLAGS value from the operand instead of
7241 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
7242 // we prove that the arithmetic won't overflow, we can't use OF or CF.
7243 if (Op.getResNo() != 0 || NeedOF || NeedCF)
7244 // Emit a CMP with 0, which is the TEST pattern.
7245 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
7246 DAG.getConstant(0, Op.getValueType()));
7248 unsigned Opcode = 0;
7249 unsigned NumOperands = 0;
7250 switch (Op.getNode()->getOpcode()) {
7252 // Due to an isel shortcoming, be conservative if this add is likely to be
7253 // selected as part of a load-modify-store instruction. When the root node
7254 // in a match is a store, isel doesn't know how to remap non-chain non-flag
7255 // uses of other nodes in the match, such as the ADD in this case. This
7256 // leads to the ADD being left around and reselected, with the result being
7257 // two adds in the output. Alas, even if none our users are stores, that
7258 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
7259 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
7260 // climbing the DAG back to the root, and it doesn't seem to be worth the
7262 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
7263 UE = Op.getNode()->use_end(); UI != UE; ++UI)
7264 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
7267 if (ConstantSDNode *C =
7268 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
7269 // An add of one will be selected as an INC.
7270 if (C->getAPIntValue() == 1) {
7271 Opcode = X86ISD::INC;
7276 // An add of negative one (subtract of one) will be selected as a DEC.
7277 if (C->getAPIntValue().isAllOnesValue()) {
7278 Opcode = X86ISD::DEC;
7284 // Otherwise use a regular EFLAGS-setting add.
7285 Opcode = X86ISD::ADD;
7289 // If the primary and result isn't used, don't bother using X86ISD::AND,
7290 // because a TEST instruction will be better.
7291 bool NonFlagUse = false;
7292 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
7293 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
7295 unsigned UOpNo = UI.getOperandNo();
7296 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
7297 // Look pass truncate.
7298 UOpNo = User->use_begin().getOperandNo();
7299 User = *User->use_begin();
7302 if (User->getOpcode() != ISD::BRCOND &&
7303 User->getOpcode() != ISD::SETCC &&
7304 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
7317 // Due to the ISEL shortcoming noted above, be conservative if this op is
7318 // likely to be selected as part of a load-modify-store instruction.
7319 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
7320 UE = Op.getNode()->use_end(); UI != UE; ++UI)
7321 if (UI->getOpcode() == ISD::STORE)
7324 // Otherwise use a regular EFLAGS-setting instruction.
7325 switch (Op.getNode()->getOpcode()) {
7326 default: llvm_unreachable("unexpected operator!");
7327 case ISD::SUB: Opcode = X86ISD::SUB; break;
7328 case ISD::OR: Opcode = X86ISD::OR; break;
7329 case ISD::XOR: Opcode = X86ISD::XOR; break;
7330 case ISD::AND: Opcode = X86ISD::AND; break;
7342 return SDValue(Op.getNode(), 1);
7349 // Emit a CMP with 0, which is the TEST pattern.
7350 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
7351 DAG.getConstant(0, Op.getValueType()));
7353 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
7354 SmallVector<SDValue, 4> Ops;
7355 for (unsigned i = 0; i != NumOperands; ++i)
7356 Ops.push_back(Op.getOperand(i));
7358 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
7359 DAG.ReplaceAllUsesWith(Op, New);
7360 return SDValue(New.getNode(), 1);
7363 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
7365 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
7366 SelectionDAG &DAG) const {
7367 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
7368 if (C->getAPIntValue() == 0)
7369 return EmitTest(Op0, X86CC, DAG);
7371 DebugLoc dl = Op0.getDebugLoc();
7372 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
7375 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
7376 /// if it's possible.
7377 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
7378 DebugLoc dl, SelectionDAG &DAG) const {
7379 SDValue Op0 = And.getOperand(0);
7380 SDValue Op1 = And.getOperand(1);
7381 if (Op0.getOpcode() == ISD::TRUNCATE)
7382 Op0 = Op0.getOperand(0);
7383 if (Op1.getOpcode() == ISD::TRUNCATE)
7384 Op1 = Op1.getOperand(0);
7387 if (Op1.getOpcode() == ISD::SHL)
7388 std::swap(Op0, Op1);
7389 if (Op0.getOpcode() == ISD::SHL) {
7390 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
7391 if (And00C->getZExtValue() == 1) {
7392 // If we looked past a truncate, check that it's only truncating away
7394 unsigned BitWidth = Op0.getValueSizeInBits();
7395 unsigned AndBitWidth = And.getValueSizeInBits();
7396 if (BitWidth > AndBitWidth) {
7397 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
7398 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
7399 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
7403 RHS = Op0.getOperand(1);
7405 } else if (Op1.getOpcode() == ISD::Constant) {
7406 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
7407 SDValue AndLHS = Op0;
7408 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
7409 LHS = AndLHS.getOperand(0);
7410 RHS = AndLHS.getOperand(1);
7414 if (LHS.getNode()) {
7415 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
7416 // instruction. Since the shift amount is in-range-or-undefined, we know
7417 // that doing a bittest on the i32 value is ok. We extend to i32 because
7418 // the encoding for the i16 version is larger than the i32 version.
7419 // Also promote i16 to i32 for performance / code size reason.
7420 if (LHS.getValueType() == MVT::i8 ||
7421 LHS.getValueType() == MVT::i16)
7422 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
7424 // If the operand types disagree, extend the shift amount to match. Since
7425 // BT ignores high bits (like shifts) we can use anyextend.
7426 if (LHS.getValueType() != RHS.getValueType())
7427 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
7429 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
7430 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
7431 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7432 DAG.getConstant(Cond, MVT::i8), BT);
7438 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
7439 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
7440 SDValue Op0 = Op.getOperand(0);
7441 SDValue Op1 = Op.getOperand(1);
7442 DebugLoc dl = Op.getDebugLoc();
7443 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
7445 // Optimize to BT if possible.
7446 // Lower (X & (1 << N)) == 0 to BT(X, N).
7447 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
7448 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
7449 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
7450 Op1.getOpcode() == ISD::Constant &&
7451 cast<ConstantSDNode>(Op1)->isNullValue() &&
7452 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
7453 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
7454 if (NewSetCC.getNode())
7458 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
7460 if (Op1.getOpcode() == ISD::Constant &&
7461 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
7462 cast<ConstantSDNode>(Op1)->isNullValue()) &&
7463 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
7465 // If the input is a setcc, then reuse the input setcc or use a new one with
7466 // the inverted condition.
7467 if (Op0.getOpcode() == X86ISD::SETCC) {
7468 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
7469 bool Invert = (CC == ISD::SETNE) ^
7470 cast<ConstantSDNode>(Op1)->isNullValue();
7471 if (!Invert) return Op0;
7473 CCode = X86::GetOppositeBranchCondition(CCode);
7474 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7475 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
7479 bool isFP = Op1.getValueType().isFloatingPoint();
7480 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
7481 if (X86CC == X86::COND_INVALID)
7484 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
7485 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7486 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
7489 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
7491 SDValue Op0 = Op.getOperand(0);
7492 SDValue Op1 = Op.getOperand(1);
7493 SDValue CC = Op.getOperand(2);
7494 EVT VT = Op.getValueType();
7495 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
7496 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
7497 DebugLoc dl = Op.getDebugLoc();
7501 EVT VT0 = Op0.getValueType();
7502 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
7503 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
7506 switch (SetCCOpcode) {
7509 case ISD::SETEQ: SSECC = 0; break;
7511 case ISD::SETGT: Swap = true; // Fallthrough
7513 case ISD::SETOLT: SSECC = 1; break;
7515 case ISD::SETGE: Swap = true; // Fallthrough
7517 case ISD::SETOLE: SSECC = 2; break;
7518 case ISD::SETUO: SSECC = 3; break;
7520 case ISD::SETNE: SSECC = 4; break;
7521 case ISD::SETULE: Swap = true;
7522 case ISD::SETUGE: SSECC = 5; break;
7523 case ISD::SETULT: Swap = true;
7524 case ISD::SETUGT: SSECC = 6; break;
7525 case ISD::SETO: SSECC = 7; break;
7528 std::swap(Op0, Op1);
7530 // In the two special cases we can't handle, emit two comparisons.
7532 if (SetCCOpcode == ISD::SETUEQ) {
7534 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
7535 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
7536 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
7538 else if (SetCCOpcode == ISD::SETONE) {
7540 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
7541 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
7542 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
7544 llvm_unreachable("Illegal FP comparison");
7546 // Handle all other FP comparisons here.
7547 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
7550 // We are handling one of the integer comparisons here. Since SSE only has
7551 // GT and EQ comparisons for integer, swapping operands and multiple
7552 // operations may be required for some comparisons.
7553 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
7554 bool Swap = false, Invert = false, FlipSigns = false;
7556 switch (VT.getSimpleVT().SimpleTy) {
7558 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
7559 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
7560 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
7561 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
7564 switch (SetCCOpcode) {
7566 case ISD::SETNE: Invert = true;
7567 case ISD::SETEQ: Opc = EQOpc; break;
7568 case ISD::SETLT: Swap = true;
7569 case ISD::SETGT: Opc = GTOpc; break;
7570 case ISD::SETGE: Swap = true;
7571 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
7572 case ISD::SETULT: Swap = true;
7573 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
7574 case ISD::SETUGE: Swap = true;
7575 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
7578 std::swap(Op0, Op1);
7580 // Since SSE has no unsigned integer comparisons, we need to flip the sign
7581 // bits of the inputs before performing those operations.
7583 EVT EltVT = VT.getVectorElementType();
7584 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
7586 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
7587 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
7589 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
7590 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
7593 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
7595 // If the logical-not of the result is required, perform that now.
7597 Result = DAG.getNOT(dl, Result, VT);
7602 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
7603 static bool isX86LogicalCmp(SDValue Op) {
7604 unsigned Opc = Op.getNode()->getOpcode();
7605 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
7607 if (Op.getResNo() == 1 &&
7608 (Opc == X86ISD::ADD ||
7609 Opc == X86ISD::SUB ||
7610 Opc == X86ISD::ADC ||
7611 Opc == X86ISD::SBB ||
7612 Opc == X86ISD::SMUL ||
7613 Opc == X86ISD::UMUL ||
7614 Opc == X86ISD::INC ||
7615 Opc == X86ISD::DEC ||
7616 Opc == X86ISD::OR ||
7617 Opc == X86ISD::XOR ||
7618 Opc == X86ISD::AND))
7621 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
7627 static bool isZero(SDValue V) {
7628 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
7629 return C && C->isNullValue();
7632 static bool isAllOnes(SDValue V) {
7633 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
7634 return C && C->isAllOnesValue();
7637 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
7638 bool addTest = true;
7639 SDValue Cond = Op.getOperand(0);
7640 SDValue Op1 = Op.getOperand(1);
7641 SDValue Op2 = Op.getOperand(2);
7642 DebugLoc DL = Op.getDebugLoc();
7645 if (Cond.getOpcode() == ISD::SETCC) {
7646 SDValue NewCond = LowerSETCC(Cond, DAG);
7647 if (NewCond.getNode())
7651 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
7652 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
7653 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
7654 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
7655 if (Cond.getOpcode() == X86ISD::SETCC &&
7656 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
7657 isZero(Cond.getOperand(1).getOperand(1))) {
7658 SDValue Cmp = Cond.getOperand(1);
7660 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
7662 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
7663 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
7664 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
7666 SDValue CmpOp0 = Cmp.getOperand(0);
7667 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
7668 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
7670 SDValue Res = // Res = 0 or -1.
7671 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
7672 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
7674 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
7675 Res = DAG.getNOT(DL, Res, Res.getValueType());
7677 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
7678 if (N2C == 0 || !N2C->isNullValue())
7679 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
7684 // Look past (and (setcc_carry (cmp ...)), 1).
7685 if (Cond.getOpcode() == ISD::AND &&
7686 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
7687 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
7688 if (C && C->getAPIntValue() == 1)
7689 Cond = Cond.getOperand(0);
7692 // If condition flag is set by a X86ISD::CMP, then use it as the condition
7693 // setting operand in place of the X86ISD::SETCC.
7694 if (Cond.getOpcode() == X86ISD::SETCC ||
7695 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
7696 CC = Cond.getOperand(0);
7698 SDValue Cmp = Cond.getOperand(1);
7699 unsigned Opc = Cmp.getOpcode();
7700 EVT VT = Op.getValueType();
7702 bool IllegalFPCMov = false;
7703 if (VT.isFloatingPoint() && !VT.isVector() &&
7704 !isScalarFPTypeInSSEReg(VT)) // FPStack?
7705 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
7707 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
7708 Opc == X86ISD::BT) { // FIXME
7715 // Look pass the truncate.
7716 if (Cond.getOpcode() == ISD::TRUNCATE)
7717 Cond = Cond.getOperand(0);
7719 // We know the result of AND is compared against zero. Try to match
7721 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
7722 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
7723 if (NewSetCC.getNode()) {
7724 CC = NewSetCC.getOperand(0);
7725 Cond = NewSetCC.getOperand(1);
7732 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7733 Cond = EmitTest(Cond, X86::COND_NE, DAG);
7736 // a < b ? -1 : 0 -> RES = ~setcc_carry
7737 // a < b ? 0 : -1 -> RES = setcc_carry
7738 // a >= b ? -1 : 0 -> RES = setcc_carry
7739 // a >= b ? 0 : -1 -> RES = ~setcc_carry
7740 if (Cond.getOpcode() == X86ISD::CMP) {
7741 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
7743 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
7744 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
7745 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
7746 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
7747 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
7748 return DAG.getNOT(DL, Res, Res.getValueType());
7753 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
7754 // condition is true.
7755 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
7756 SDValue Ops[] = { Op2, Op1, CC, Cond };
7757 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
7760 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
7761 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
7762 // from the AND / OR.
7763 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
7764 Opc = Op.getOpcode();
7765 if (Opc != ISD::OR && Opc != ISD::AND)
7767 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
7768 Op.getOperand(0).hasOneUse() &&
7769 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
7770 Op.getOperand(1).hasOneUse());
7773 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
7774 // 1 and that the SETCC node has a single use.
7775 static bool isXor1OfSetCC(SDValue Op) {
7776 if (Op.getOpcode() != ISD::XOR)
7778 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7779 if (N1C && N1C->getAPIntValue() == 1) {
7780 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
7781 Op.getOperand(0).hasOneUse();
7786 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
7787 bool addTest = true;
7788 SDValue Chain = Op.getOperand(0);
7789 SDValue Cond = Op.getOperand(1);
7790 SDValue Dest = Op.getOperand(2);
7791 DebugLoc dl = Op.getDebugLoc();
7794 if (Cond.getOpcode() == ISD::SETCC) {
7795 SDValue NewCond = LowerSETCC(Cond, DAG);
7796 if (NewCond.getNode())
7800 // FIXME: LowerXALUO doesn't handle these!!
7801 else if (Cond.getOpcode() == X86ISD::ADD ||
7802 Cond.getOpcode() == X86ISD::SUB ||
7803 Cond.getOpcode() == X86ISD::SMUL ||
7804 Cond.getOpcode() == X86ISD::UMUL)
7805 Cond = LowerXALUO(Cond, DAG);
7808 // Look pass (and (setcc_carry (cmp ...)), 1).
7809 if (Cond.getOpcode() == ISD::AND &&
7810 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
7811 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
7812 if (C && C->getAPIntValue() == 1)
7813 Cond = Cond.getOperand(0);
7816 // If condition flag is set by a X86ISD::CMP, then use it as the condition
7817 // setting operand in place of the X86ISD::SETCC.
7818 if (Cond.getOpcode() == X86ISD::SETCC ||
7819 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
7820 CC = Cond.getOperand(0);
7822 SDValue Cmp = Cond.getOperand(1);
7823 unsigned Opc = Cmp.getOpcode();
7824 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
7825 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
7829 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
7833 // These can only come from an arithmetic instruction with overflow,
7834 // e.g. SADDO, UADDO.
7835 Cond = Cond.getNode()->getOperand(1);
7842 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
7843 SDValue Cmp = Cond.getOperand(0).getOperand(1);
7844 if (CondOpc == ISD::OR) {
7845 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
7846 // two branches instead of an explicit OR instruction with a
7848 if (Cmp == Cond.getOperand(1).getOperand(1) &&
7849 isX86LogicalCmp(Cmp)) {
7850 CC = Cond.getOperand(0).getOperand(0);
7851 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
7852 Chain, Dest, CC, Cmp);
7853 CC = Cond.getOperand(1).getOperand(0);
7857 } else { // ISD::AND
7858 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
7859 // two branches instead of an explicit AND instruction with a
7860 // separate test. However, we only do this if this block doesn't
7861 // have a fall-through edge, because this requires an explicit
7862 // jmp when the condition is false.
7863 if (Cmp == Cond.getOperand(1).getOperand(1) &&
7864 isX86LogicalCmp(Cmp) &&
7865 Op.getNode()->hasOneUse()) {
7866 X86::CondCode CCode =
7867 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
7868 CCode = X86::GetOppositeBranchCondition(CCode);
7869 CC = DAG.getConstant(CCode, MVT::i8);
7870 SDNode *User = *Op.getNode()->use_begin();
7871 // Look for an unconditional branch following this conditional branch.
7872 // We need this because we need to reverse the successors in order
7873 // to implement FCMP_OEQ.
7874 if (User->getOpcode() == ISD::BR) {
7875 SDValue FalseBB = User->getOperand(1);
7877 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
7878 assert(NewBR == User);
7882 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
7883 Chain, Dest, CC, Cmp);
7884 X86::CondCode CCode =
7885 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
7886 CCode = X86::GetOppositeBranchCondition(CCode);
7887 CC = DAG.getConstant(CCode, MVT::i8);
7893 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
7894 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
7895 // It should be transformed during dag combiner except when the condition
7896 // is set by a arithmetics with overflow node.
7897 X86::CondCode CCode =
7898 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
7899 CCode = X86::GetOppositeBranchCondition(CCode);
7900 CC = DAG.getConstant(CCode, MVT::i8);
7901 Cond = Cond.getOperand(0).getOperand(1);
7907 // Look pass the truncate.
7908 if (Cond.getOpcode() == ISD::TRUNCATE)
7909 Cond = Cond.getOperand(0);
7911 // We know the result of AND is compared against zero. Try to match
7913 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
7914 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
7915 if (NewSetCC.getNode()) {
7916 CC = NewSetCC.getOperand(0);
7917 Cond = NewSetCC.getOperand(1);
7924 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7925 Cond = EmitTest(Cond, X86::COND_NE, DAG);
7927 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
7928 Chain, Dest, CC, Cond);
7932 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
7933 // Calls to _alloca is needed to probe the stack when allocating more than 4k
7934 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
7935 // that the guard pages used by the OS virtual memory manager are allocated in
7936 // correct sequence.
7938 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
7939 SelectionDAG &DAG) const {
7940 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows()) &&
7941 "This should be used only on Windows targets");
7942 assert(!Subtarget->isTargetEnvMacho());
7943 DebugLoc dl = Op.getDebugLoc();
7946 SDValue Chain = Op.getOperand(0);
7947 SDValue Size = Op.getOperand(1);
7948 // FIXME: Ensure alignment here
7952 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
7953 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
7955 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
7956 Flag = Chain.getValue(1);
7958 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7960 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
7961 Flag = Chain.getValue(1);
7963 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
7965 SDValue Ops1[2] = { Chain.getValue(0), Chain };
7966 return DAG.getMergeValues(Ops1, 2, dl);
7969 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
7970 MachineFunction &MF = DAG.getMachineFunction();
7971 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
7973 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
7974 DebugLoc DL = Op.getDebugLoc();
7976 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
7977 // vastart just stores the address of the VarArgsFrameIndex slot into the
7978 // memory location argument.
7979 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
7981 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
7982 MachinePointerInfo(SV), false, false, 0);
7986 // gp_offset (0 - 6 * 8)
7987 // fp_offset (48 - 48 + 8 * 16)
7988 // overflow_arg_area (point to parameters coming in memory).
7990 SmallVector<SDValue, 8> MemOps;
7991 SDValue FIN = Op.getOperand(1);
7993 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
7994 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
7996 FIN, MachinePointerInfo(SV), false, false, 0);
7997 MemOps.push_back(Store);
8000 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8001 FIN, DAG.getIntPtrConstant(4));
8002 Store = DAG.getStore(Op.getOperand(0), DL,
8003 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
8005 FIN, MachinePointerInfo(SV, 4), false, false, 0);
8006 MemOps.push_back(Store);
8008 // Store ptr to overflow_arg_area
8009 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8010 FIN, DAG.getIntPtrConstant(4));
8011 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
8013 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
8014 MachinePointerInfo(SV, 8),
8016 MemOps.push_back(Store);
8018 // Store ptr to reg_save_area.
8019 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8020 FIN, DAG.getIntPtrConstant(8));
8021 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
8023 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
8024 MachinePointerInfo(SV, 16), false, false, 0);
8025 MemOps.push_back(Store);
8026 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
8027 &MemOps[0], MemOps.size());
8030 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
8031 assert(Subtarget->is64Bit() &&
8032 "LowerVAARG only handles 64-bit va_arg!");
8033 assert((Subtarget->isTargetLinux() ||
8034 Subtarget->isTargetDarwin()) &&
8035 "Unhandled target in LowerVAARG");
8036 assert(Op.getNode()->getNumOperands() == 4);
8037 SDValue Chain = Op.getOperand(0);
8038 SDValue SrcPtr = Op.getOperand(1);
8039 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
8040 unsigned Align = Op.getConstantOperandVal(3);
8041 DebugLoc dl = Op.getDebugLoc();
8043 EVT ArgVT = Op.getNode()->getValueType(0);
8044 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
8045 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
8048 // Decide which area this value should be read from.
8049 // TODO: Implement the AMD64 ABI in its entirety. This simple
8050 // selection mechanism works only for the basic types.
8051 if (ArgVT == MVT::f80) {
8052 llvm_unreachable("va_arg for f80 not yet implemented");
8053 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
8054 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
8055 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
8056 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
8058 llvm_unreachable("Unhandled argument type in LowerVAARG");
8062 // Sanity Check: Make sure using fp_offset makes sense.
8063 assert(!UseSoftFloat &&
8064 !(DAG.getMachineFunction()
8065 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
8066 Subtarget->hasXMM());
8069 // Insert VAARG_64 node into the DAG
8070 // VAARG_64 returns two values: Variable Argument Address, Chain
8071 SmallVector<SDValue, 11> InstOps;
8072 InstOps.push_back(Chain);
8073 InstOps.push_back(SrcPtr);
8074 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
8075 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
8076 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
8077 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
8078 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
8079 VTs, &InstOps[0], InstOps.size(),
8081 MachinePointerInfo(SV),
8086 Chain = VAARG.getValue(1);
8088 // Load the next argument and return it
8089 return DAG.getLoad(ArgVT, dl,
8092 MachinePointerInfo(),
8096 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
8097 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
8098 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
8099 SDValue Chain = Op.getOperand(0);
8100 SDValue DstPtr = Op.getOperand(1);
8101 SDValue SrcPtr = Op.getOperand(2);
8102 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
8103 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
8104 DebugLoc DL = Op.getDebugLoc();
8106 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
8107 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
8109 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
8113 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
8114 DebugLoc dl = Op.getDebugLoc();
8115 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8117 default: return SDValue(); // Don't custom lower most intrinsics.
8118 // Comparison intrinsics.
8119 case Intrinsic::x86_sse_comieq_ss:
8120 case Intrinsic::x86_sse_comilt_ss:
8121 case Intrinsic::x86_sse_comile_ss:
8122 case Intrinsic::x86_sse_comigt_ss:
8123 case Intrinsic::x86_sse_comige_ss:
8124 case Intrinsic::x86_sse_comineq_ss:
8125 case Intrinsic::x86_sse_ucomieq_ss:
8126 case Intrinsic::x86_sse_ucomilt_ss:
8127 case Intrinsic::x86_sse_ucomile_ss:
8128 case Intrinsic::x86_sse_ucomigt_ss:
8129 case Intrinsic::x86_sse_ucomige_ss:
8130 case Intrinsic::x86_sse_ucomineq_ss:
8131 case Intrinsic::x86_sse2_comieq_sd:
8132 case Intrinsic::x86_sse2_comilt_sd:
8133 case Intrinsic::x86_sse2_comile_sd:
8134 case Intrinsic::x86_sse2_comigt_sd:
8135 case Intrinsic::x86_sse2_comige_sd:
8136 case Intrinsic::x86_sse2_comineq_sd:
8137 case Intrinsic::x86_sse2_ucomieq_sd:
8138 case Intrinsic::x86_sse2_ucomilt_sd:
8139 case Intrinsic::x86_sse2_ucomile_sd:
8140 case Intrinsic::x86_sse2_ucomigt_sd:
8141 case Intrinsic::x86_sse2_ucomige_sd:
8142 case Intrinsic::x86_sse2_ucomineq_sd: {
8144 ISD::CondCode CC = ISD::SETCC_INVALID;
8147 case Intrinsic::x86_sse_comieq_ss:
8148 case Intrinsic::x86_sse2_comieq_sd:
8152 case Intrinsic::x86_sse_comilt_ss:
8153 case Intrinsic::x86_sse2_comilt_sd:
8157 case Intrinsic::x86_sse_comile_ss:
8158 case Intrinsic::x86_sse2_comile_sd:
8162 case Intrinsic::x86_sse_comigt_ss:
8163 case Intrinsic::x86_sse2_comigt_sd:
8167 case Intrinsic::x86_sse_comige_ss:
8168 case Intrinsic::x86_sse2_comige_sd:
8172 case Intrinsic::x86_sse_comineq_ss:
8173 case Intrinsic::x86_sse2_comineq_sd:
8177 case Intrinsic::x86_sse_ucomieq_ss:
8178 case Intrinsic::x86_sse2_ucomieq_sd:
8179 Opc = X86ISD::UCOMI;
8182 case Intrinsic::x86_sse_ucomilt_ss:
8183 case Intrinsic::x86_sse2_ucomilt_sd:
8184 Opc = X86ISD::UCOMI;
8187 case Intrinsic::x86_sse_ucomile_ss:
8188 case Intrinsic::x86_sse2_ucomile_sd:
8189 Opc = X86ISD::UCOMI;
8192 case Intrinsic::x86_sse_ucomigt_ss:
8193 case Intrinsic::x86_sse2_ucomigt_sd:
8194 Opc = X86ISD::UCOMI;
8197 case Intrinsic::x86_sse_ucomige_ss:
8198 case Intrinsic::x86_sse2_ucomige_sd:
8199 Opc = X86ISD::UCOMI;
8202 case Intrinsic::x86_sse_ucomineq_ss:
8203 case Intrinsic::x86_sse2_ucomineq_sd:
8204 Opc = X86ISD::UCOMI;
8209 SDValue LHS = Op.getOperand(1);
8210 SDValue RHS = Op.getOperand(2);
8211 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
8212 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
8213 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
8214 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8215 DAG.getConstant(X86CC, MVT::i8), Cond);
8216 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
8218 // ptest and testp intrinsics. The intrinsic these come from are designed to
8219 // return an integer value, not just an instruction so lower it to the ptest
8220 // or testp pattern and a setcc for the result.
8221 case Intrinsic::x86_sse41_ptestz:
8222 case Intrinsic::x86_sse41_ptestc:
8223 case Intrinsic::x86_sse41_ptestnzc:
8224 case Intrinsic::x86_avx_ptestz_256:
8225 case Intrinsic::x86_avx_ptestc_256:
8226 case Intrinsic::x86_avx_ptestnzc_256:
8227 case Intrinsic::x86_avx_vtestz_ps:
8228 case Intrinsic::x86_avx_vtestc_ps:
8229 case Intrinsic::x86_avx_vtestnzc_ps:
8230 case Intrinsic::x86_avx_vtestz_pd:
8231 case Intrinsic::x86_avx_vtestc_pd:
8232 case Intrinsic::x86_avx_vtestnzc_pd:
8233 case Intrinsic::x86_avx_vtestz_ps_256:
8234 case Intrinsic::x86_avx_vtestc_ps_256:
8235 case Intrinsic::x86_avx_vtestnzc_ps_256:
8236 case Intrinsic::x86_avx_vtestz_pd_256:
8237 case Intrinsic::x86_avx_vtestc_pd_256:
8238 case Intrinsic::x86_avx_vtestnzc_pd_256: {
8239 bool IsTestPacked = false;
8242 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
8243 case Intrinsic::x86_avx_vtestz_ps:
8244 case Intrinsic::x86_avx_vtestz_pd:
8245 case Intrinsic::x86_avx_vtestz_ps_256:
8246 case Intrinsic::x86_avx_vtestz_pd_256:
8247 IsTestPacked = true; // Fallthrough
8248 case Intrinsic::x86_sse41_ptestz:
8249 case Intrinsic::x86_avx_ptestz_256:
8251 X86CC = X86::COND_E;
8253 case Intrinsic::x86_avx_vtestc_ps:
8254 case Intrinsic::x86_avx_vtestc_pd:
8255 case Intrinsic::x86_avx_vtestc_ps_256:
8256 case Intrinsic::x86_avx_vtestc_pd_256:
8257 IsTestPacked = true; // Fallthrough
8258 case Intrinsic::x86_sse41_ptestc:
8259 case Intrinsic::x86_avx_ptestc_256:
8261 X86CC = X86::COND_B;
8263 case Intrinsic::x86_avx_vtestnzc_ps:
8264 case Intrinsic::x86_avx_vtestnzc_pd:
8265 case Intrinsic::x86_avx_vtestnzc_ps_256:
8266 case Intrinsic::x86_avx_vtestnzc_pd_256:
8267 IsTestPacked = true; // Fallthrough
8268 case Intrinsic::x86_sse41_ptestnzc:
8269 case Intrinsic::x86_avx_ptestnzc_256:
8271 X86CC = X86::COND_A;
8275 SDValue LHS = Op.getOperand(1);
8276 SDValue RHS = Op.getOperand(2);
8277 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
8278 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
8279 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
8280 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
8281 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
8284 // Fix vector shift instructions where the last operand is a non-immediate
8286 case Intrinsic::x86_sse2_pslli_w:
8287 case Intrinsic::x86_sse2_pslli_d:
8288 case Intrinsic::x86_sse2_pslli_q:
8289 case Intrinsic::x86_sse2_psrli_w:
8290 case Intrinsic::x86_sse2_psrli_d:
8291 case Intrinsic::x86_sse2_psrli_q:
8292 case Intrinsic::x86_sse2_psrai_w:
8293 case Intrinsic::x86_sse2_psrai_d:
8294 case Intrinsic::x86_mmx_pslli_w:
8295 case Intrinsic::x86_mmx_pslli_d:
8296 case Intrinsic::x86_mmx_pslli_q:
8297 case Intrinsic::x86_mmx_psrli_w:
8298 case Intrinsic::x86_mmx_psrli_d:
8299 case Intrinsic::x86_mmx_psrli_q:
8300 case Intrinsic::x86_mmx_psrai_w:
8301 case Intrinsic::x86_mmx_psrai_d: {
8302 SDValue ShAmt = Op.getOperand(2);
8303 if (isa<ConstantSDNode>(ShAmt))
8306 unsigned NewIntNo = 0;
8307 EVT ShAmtVT = MVT::v4i32;
8309 case Intrinsic::x86_sse2_pslli_w:
8310 NewIntNo = Intrinsic::x86_sse2_psll_w;
8312 case Intrinsic::x86_sse2_pslli_d:
8313 NewIntNo = Intrinsic::x86_sse2_psll_d;
8315 case Intrinsic::x86_sse2_pslli_q:
8316 NewIntNo = Intrinsic::x86_sse2_psll_q;
8318 case Intrinsic::x86_sse2_psrli_w:
8319 NewIntNo = Intrinsic::x86_sse2_psrl_w;
8321 case Intrinsic::x86_sse2_psrli_d:
8322 NewIntNo = Intrinsic::x86_sse2_psrl_d;
8324 case Intrinsic::x86_sse2_psrli_q:
8325 NewIntNo = Intrinsic::x86_sse2_psrl_q;
8327 case Intrinsic::x86_sse2_psrai_w:
8328 NewIntNo = Intrinsic::x86_sse2_psra_w;
8330 case Intrinsic::x86_sse2_psrai_d:
8331 NewIntNo = Intrinsic::x86_sse2_psra_d;
8334 ShAmtVT = MVT::v2i32;
8336 case Intrinsic::x86_mmx_pslli_w:
8337 NewIntNo = Intrinsic::x86_mmx_psll_w;
8339 case Intrinsic::x86_mmx_pslli_d:
8340 NewIntNo = Intrinsic::x86_mmx_psll_d;
8342 case Intrinsic::x86_mmx_pslli_q:
8343 NewIntNo = Intrinsic::x86_mmx_psll_q;
8345 case Intrinsic::x86_mmx_psrli_w:
8346 NewIntNo = Intrinsic::x86_mmx_psrl_w;
8348 case Intrinsic::x86_mmx_psrli_d:
8349 NewIntNo = Intrinsic::x86_mmx_psrl_d;
8351 case Intrinsic::x86_mmx_psrli_q:
8352 NewIntNo = Intrinsic::x86_mmx_psrl_q;
8354 case Intrinsic::x86_mmx_psrai_w:
8355 NewIntNo = Intrinsic::x86_mmx_psra_w;
8357 case Intrinsic::x86_mmx_psrai_d:
8358 NewIntNo = Intrinsic::x86_mmx_psra_d;
8360 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
8366 // The vector shift intrinsics with scalars uses 32b shift amounts but
8367 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
8371 ShOps[1] = DAG.getConstant(0, MVT::i32);
8372 if (ShAmtVT == MVT::v4i32) {
8373 ShOps[2] = DAG.getUNDEF(MVT::i32);
8374 ShOps[3] = DAG.getUNDEF(MVT::i32);
8375 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
8377 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
8378 // FIXME this must be lowered to get rid of the invalid type.
8381 EVT VT = Op.getValueType();
8382 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
8383 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8384 DAG.getConstant(NewIntNo, MVT::i32),
8385 Op.getOperand(1), ShAmt);
8390 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
8391 SelectionDAG &DAG) const {
8392 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8393 MFI->setReturnAddressIsTaken(true);
8395 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8396 DebugLoc dl = Op.getDebugLoc();
8399 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
8401 DAG.getConstant(TD->getPointerSize(),
8402 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
8403 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
8404 DAG.getNode(ISD::ADD, dl, getPointerTy(),
8406 MachinePointerInfo(), false, false, 0);
8409 // Just load the return address.
8410 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
8411 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
8412 RetAddrFI, MachinePointerInfo(), false, false, 0);
8415 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
8416 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8417 MFI->setFrameAddressIsTaken(true);
8419 EVT VT = Op.getValueType();
8420 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
8421 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8422 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
8423 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
8425 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
8426 MachinePointerInfo(),
8431 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
8432 SelectionDAG &DAG) const {
8433 return DAG.getIntPtrConstant(2*TD->getPointerSize());
8436 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
8437 MachineFunction &MF = DAG.getMachineFunction();
8438 SDValue Chain = Op.getOperand(0);
8439 SDValue Offset = Op.getOperand(1);
8440 SDValue Handler = Op.getOperand(2);
8441 DebugLoc dl = Op.getDebugLoc();
8443 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
8444 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
8446 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
8448 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
8449 DAG.getIntPtrConstant(TD->getPointerSize()));
8450 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
8451 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
8453 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
8454 MF.getRegInfo().addLiveOut(StoreAddrReg);
8456 return DAG.getNode(X86ISD::EH_RETURN, dl,
8458 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
8461 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
8462 SelectionDAG &DAG) const {
8463 SDValue Root = Op.getOperand(0);
8464 SDValue Trmp = Op.getOperand(1); // trampoline
8465 SDValue FPtr = Op.getOperand(2); // nested function
8466 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
8467 DebugLoc dl = Op.getDebugLoc();
8469 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
8471 if (Subtarget->is64Bit()) {
8472 SDValue OutChains[6];
8474 // Large code-model.
8475 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
8476 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
8478 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
8479 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
8481 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
8483 // Load the pointer to the nested function into R11.
8484 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
8485 SDValue Addr = Trmp;
8486 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
8487 Addr, MachinePointerInfo(TrmpAddr),
8490 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8491 DAG.getConstant(2, MVT::i64));
8492 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
8493 MachinePointerInfo(TrmpAddr, 2),
8496 // Load the 'nest' parameter value into R10.
8497 // R10 is specified in X86CallingConv.td
8498 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
8499 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8500 DAG.getConstant(10, MVT::i64));
8501 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
8502 Addr, MachinePointerInfo(TrmpAddr, 10),
8505 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8506 DAG.getConstant(12, MVT::i64));
8507 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
8508 MachinePointerInfo(TrmpAddr, 12),
8511 // Jump to the nested function.
8512 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
8513 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8514 DAG.getConstant(20, MVT::i64));
8515 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
8516 Addr, MachinePointerInfo(TrmpAddr, 20),
8519 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
8520 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8521 DAG.getConstant(22, MVT::i64));
8522 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
8523 MachinePointerInfo(TrmpAddr, 22),
8527 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
8528 return DAG.getMergeValues(Ops, 2, dl);
8530 const Function *Func =
8531 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
8532 CallingConv::ID CC = Func->getCallingConv();
8537 llvm_unreachable("Unsupported calling convention");
8538 case CallingConv::C:
8539 case CallingConv::X86_StdCall: {
8540 // Pass 'nest' parameter in ECX.
8541 // Must be kept in sync with X86CallingConv.td
8544 // Check that ECX wasn't needed by an 'inreg' parameter.
8545 const FunctionType *FTy = Func->getFunctionType();
8546 const AttrListPtr &Attrs = Func->getAttributes();
8548 if (!Attrs.isEmpty() && !Func->isVarArg()) {
8549 unsigned InRegCount = 0;
8552 for (FunctionType::param_iterator I = FTy->param_begin(),
8553 E = FTy->param_end(); I != E; ++I, ++Idx)
8554 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
8555 // FIXME: should only count parameters that are lowered to integers.
8556 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
8558 if (InRegCount > 2) {
8559 report_fatal_error("Nest register in use - reduce number of inreg"
8565 case CallingConv::X86_FastCall:
8566 case CallingConv::X86_ThisCall:
8567 case CallingConv::Fast:
8568 // Pass 'nest' parameter in EAX.
8569 // Must be kept in sync with X86CallingConv.td
8574 SDValue OutChains[4];
8577 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8578 DAG.getConstant(10, MVT::i32));
8579 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
8581 // This is storing the opcode for MOV32ri.
8582 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
8583 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
8584 OutChains[0] = DAG.getStore(Root, dl,
8585 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
8586 Trmp, MachinePointerInfo(TrmpAddr),
8589 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8590 DAG.getConstant(1, MVT::i32));
8591 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
8592 MachinePointerInfo(TrmpAddr, 1),
8595 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
8596 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8597 DAG.getConstant(5, MVT::i32));
8598 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
8599 MachinePointerInfo(TrmpAddr, 5),
8602 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8603 DAG.getConstant(6, MVT::i32));
8604 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
8605 MachinePointerInfo(TrmpAddr, 6),
8609 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
8610 return DAG.getMergeValues(Ops, 2, dl);
8614 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
8615 SelectionDAG &DAG) const {
8617 The rounding mode is in bits 11:10 of FPSR, and has the following
8624 FLT_ROUNDS, on the other hand, expects the following:
8631 To perform the conversion, we do:
8632 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
8635 MachineFunction &MF = DAG.getMachineFunction();
8636 const TargetMachine &TM = MF.getTarget();
8637 const TargetFrameLowering &TFI = *TM.getFrameLowering();
8638 unsigned StackAlignment = TFI.getStackAlignment();
8639 EVT VT = Op.getValueType();
8640 DebugLoc DL = Op.getDebugLoc();
8642 // Save FP Control Word to stack slot
8643 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
8644 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8647 MachineMemOperand *MMO =
8648 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8649 MachineMemOperand::MOStore, 2, 2);
8651 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
8652 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
8653 DAG.getVTList(MVT::Other),
8654 Ops, 2, MVT::i16, MMO);
8656 // Load FP Control Word from stack slot
8657 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
8658 MachinePointerInfo(), false, false, 0);
8660 // Transform as necessary
8662 DAG.getNode(ISD::SRL, DL, MVT::i16,
8663 DAG.getNode(ISD::AND, DL, MVT::i16,
8664 CWD, DAG.getConstant(0x800, MVT::i16)),
8665 DAG.getConstant(11, MVT::i8));
8667 DAG.getNode(ISD::SRL, DL, MVT::i16,
8668 DAG.getNode(ISD::AND, DL, MVT::i16,
8669 CWD, DAG.getConstant(0x400, MVT::i16)),
8670 DAG.getConstant(9, MVT::i8));
8673 DAG.getNode(ISD::AND, DL, MVT::i16,
8674 DAG.getNode(ISD::ADD, DL, MVT::i16,
8675 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
8676 DAG.getConstant(1, MVT::i16)),
8677 DAG.getConstant(3, MVT::i16));
8680 return DAG.getNode((VT.getSizeInBits() < 16 ?
8681 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
8684 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
8685 EVT VT = Op.getValueType();
8687 unsigned NumBits = VT.getSizeInBits();
8688 DebugLoc dl = Op.getDebugLoc();
8690 Op = Op.getOperand(0);
8691 if (VT == MVT::i8) {
8692 // Zero extend to i32 since there is not an i8 bsr.
8694 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
8697 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
8698 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
8699 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
8701 // If src is zero (i.e. bsr sets ZF), returns NumBits.
8704 DAG.getConstant(NumBits+NumBits-1, OpVT),
8705 DAG.getConstant(X86::COND_E, MVT::i8),
8708 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
8710 // Finally xor with NumBits-1.
8711 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
8714 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
8718 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
8719 EVT VT = Op.getValueType();
8721 unsigned NumBits = VT.getSizeInBits();
8722 DebugLoc dl = Op.getDebugLoc();
8724 Op = Op.getOperand(0);
8725 if (VT == MVT::i8) {
8727 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
8730 // Issue a bsf (scan bits forward) which also sets EFLAGS.
8731 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
8732 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
8734 // If src is zero (i.e. bsf sets ZF), returns NumBits.
8737 DAG.getConstant(NumBits, OpVT),
8738 DAG.getConstant(X86::COND_E, MVT::i8),
8741 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
8744 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
8748 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const {
8749 EVT VT = Op.getValueType();
8750 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
8751 DebugLoc dl = Op.getDebugLoc();
8753 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
8754 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
8755 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
8756 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
8757 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
8759 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
8760 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
8761 // return AloBlo + AloBhi + AhiBlo;
8763 SDValue A = Op.getOperand(0);
8764 SDValue B = Op.getOperand(1);
8766 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8767 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
8768 A, DAG.getConstant(32, MVT::i32));
8769 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8770 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
8771 B, DAG.getConstant(32, MVT::i32));
8772 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8773 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
8775 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8776 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
8778 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8779 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
8781 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8782 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
8783 AloBhi, DAG.getConstant(32, MVT::i32));
8784 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8785 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
8786 AhiBlo, DAG.getConstant(32, MVT::i32));
8787 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
8788 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
8792 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
8794 EVT VT = Op.getValueType();
8795 DebugLoc dl = Op.getDebugLoc();
8796 SDValue R = Op.getOperand(0);
8797 SDValue Amt = Op.getOperand(1);
8799 LLVMContext *Context = DAG.getContext();
8802 if (!Subtarget->hasSSE2()) return SDValue();
8804 // Optimize shl/srl/sra with constant shift amount.
8805 if (isSplatVector(Amt.getNode())) {
8806 SDValue SclrAmt = Amt->getOperand(0);
8807 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
8808 uint64_t ShiftAmt = C->getZExtValue();
8810 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SHL)
8811 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8812 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
8813 R, DAG.getConstant(ShiftAmt, MVT::i32));
8815 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SHL)
8816 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8817 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
8818 R, DAG.getConstant(ShiftAmt, MVT::i32));
8820 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SHL)
8821 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8822 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
8823 R, DAG.getConstant(ShiftAmt, MVT::i32));
8825 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SRL)
8826 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8827 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
8828 R, DAG.getConstant(ShiftAmt, MVT::i32));
8830 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRL)
8831 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8832 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
8833 R, DAG.getConstant(ShiftAmt, MVT::i32));
8835 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRL)
8836 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8837 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
8838 R, DAG.getConstant(ShiftAmt, MVT::i32));
8840 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRA)
8841 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8842 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
8843 R, DAG.getConstant(ShiftAmt, MVT::i32));
8845 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRA)
8846 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8847 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
8848 R, DAG.getConstant(ShiftAmt, MVT::i32));
8852 // Lower SHL with variable shift amount.
8853 // Cannot lower SHL without SSE4.1 or later.
8854 if (!Subtarget->hasSSE41()) return SDValue();
8856 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
8857 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8858 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
8859 Op.getOperand(1), DAG.getConstant(23, MVT::i32));
8861 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
8863 std::vector<Constant*> CV(4, CI);
8864 Constant *C = ConstantVector::get(CV);
8865 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8866 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8867 MachinePointerInfo::getConstantPool(),
8870 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
8871 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
8872 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
8873 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
8875 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
8877 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8878 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
8879 Op.getOperand(1), DAG.getConstant(5, MVT::i32));
8881 ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15));
8882 ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63));
8884 std::vector<Constant*> CVM1(16, CM1);
8885 std::vector<Constant*> CVM2(16, CM2);
8886 Constant *C = ConstantVector::get(CVM1);
8887 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8888 SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8889 MachinePointerInfo::getConstantPool(),
8892 // r = pblendv(r, psllw(r & (char16)15, 4), a);
8893 M = DAG.getNode(ISD::AND, dl, VT, R, M);
8894 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8895 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
8896 DAG.getConstant(4, MVT::i32));
8897 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op);
8899 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
8901 C = ConstantVector::get(CVM2);
8902 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8903 M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8904 MachinePointerInfo::getConstantPool(),
8907 // r = pblendv(r, psllw(r & (char16)63, 2), a);
8908 M = DAG.getNode(ISD::AND, dl, VT, R, M);
8909 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8910 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
8911 DAG.getConstant(2, MVT::i32));
8912 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op);
8914 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
8916 // return pblendv(r, r+r, a);
8917 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT,
8918 R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op);
8924 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
8925 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
8926 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
8927 // looks for this combo and may remove the "setcc" instruction if the "setcc"
8928 // has only one use.
8929 SDNode *N = Op.getNode();
8930 SDValue LHS = N->getOperand(0);
8931 SDValue RHS = N->getOperand(1);
8932 unsigned BaseOp = 0;
8934 DebugLoc DL = Op.getDebugLoc();
8935 switch (Op.getOpcode()) {
8936 default: llvm_unreachable("Unknown ovf instruction!");
8938 // A subtract of one will be selected as a INC. Note that INC doesn't
8939 // set CF, so we can't do this for UADDO.
8940 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
8942 BaseOp = X86ISD::INC;
8946 BaseOp = X86ISD::ADD;
8950 BaseOp = X86ISD::ADD;
8954 // A subtract of one will be selected as a DEC. Note that DEC doesn't
8955 // set CF, so we can't do this for USUBO.
8956 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
8958 BaseOp = X86ISD::DEC;
8962 BaseOp = X86ISD::SUB;
8966 BaseOp = X86ISD::SUB;
8970 BaseOp = X86ISD::SMUL;
8973 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
8974 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
8976 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
8979 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8980 DAG.getConstant(X86::COND_O, MVT::i32),
8981 SDValue(Sum.getNode(), 2));
8983 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
8988 // Also sets EFLAGS.
8989 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
8990 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
8993 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
8994 DAG.getConstant(Cond, MVT::i32),
8995 SDValue(Sum.getNode(), 1));
8997 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
9001 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
9002 DebugLoc dl = Op.getDebugLoc();
9004 if (!Subtarget->hasSSE2()) {
9005 SDValue Chain = Op.getOperand(0);
9006 SDValue Zero = DAG.getConstant(0,
9007 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9009 DAG.getRegister(X86::ESP, MVT::i32), // Base
9010 DAG.getTargetConstant(1, MVT::i8), // Scale
9011 DAG.getRegister(0, MVT::i32), // Index
9012 DAG.getTargetConstant(0, MVT::i32), // Disp
9013 DAG.getRegister(0, MVT::i32), // Segment.
9018 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
9019 array_lengthof(Ops));
9020 return SDValue(Res, 0);
9023 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
9025 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
9027 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
9028 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
9029 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
9030 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
9032 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
9033 if (!Op1 && !Op2 && !Op3 && Op4)
9034 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
9036 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
9037 if (Op1 && !Op2 && !Op3 && !Op4)
9038 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
9040 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
9042 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
9045 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
9046 EVT T = Op.getValueType();
9047 DebugLoc DL = Op.getDebugLoc();
9050 switch(T.getSimpleVT().SimpleTy) {
9052 assert(false && "Invalid value type!");
9053 case MVT::i8: Reg = X86::AL; size = 1; break;
9054 case MVT::i16: Reg = X86::AX; size = 2; break;
9055 case MVT::i32: Reg = X86::EAX; size = 4; break;
9057 assert(Subtarget->is64Bit() && "Node not type legal!");
9058 Reg = X86::RAX; size = 8;
9061 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
9062 Op.getOperand(2), SDValue());
9063 SDValue Ops[] = { cpIn.getValue(0),
9066 DAG.getTargetConstant(size, MVT::i8),
9068 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
9069 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
9070 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
9073 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
9077 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
9078 SelectionDAG &DAG) const {
9079 assert(Subtarget->is64Bit() && "Result not type legalized?");
9080 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
9081 SDValue TheChain = Op.getOperand(0);
9082 DebugLoc dl = Op.getDebugLoc();
9083 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
9084 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
9085 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
9087 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
9088 DAG.getConstant(32, MVT::i8));
9090 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
9093 return DAG.getMergeValues(Ops, 2, dl);
9096 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
9097 SelectionDAG &DAG) const {
9098 EVT SrcVT = Op.getOperand(0).getValueType();
9099 EVT DstVT = Op.getValueType();
9100 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
9101 Subtarget->hasMMX() && "Unexpected custom BITCAST");
9102 assert((DstVT == MVT::i64 ||
9103 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
9104 "Unexpected custom BITCAST");
9105 // i64 <=> MMX conversions are Legal.
9106 if (SrcVT==MVT::i64 && DstVT.isVector())
9108 if (DstVT==MVT::i64 && SrcVT.isVector())
9110 // MMX <=> MMX conversions are Legal.
9111 if (SrcVT.isVector() && DstVT.isVector())
9113 // All other conversions need to be expanded.
9117 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
9118 SDNode *Node = Op.getNode();
9119 DebugLoc dl = Node->getDebugLoc();
9120 EVT T = Node->getValueType(0);
9121 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
9122 DAG.getConstant(0, T), Node->getOperand(2));
9123 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
9124 cast<AtomicSDNode>(Node)->getMemoryVT(),
9125 Node->getOperand(0),
9126 Node->getOperand(1), negOp,
9127 cast<AtomicSDNode>(Node)->getSrcValue(),
9128 cast<AtomicSDNode>(Node)->getAlignment());
9131 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
9132 EVT VT = Op.getNode()->getValueType(0);
9134 // Let legalize expand this if it isn't a legal type yet.
9135 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
9138 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
9141 bool ExtraOp = false;
9142 switch (Op.getOpcode()) {
9143 default: assert(0 && "Invalid code");
9144 case ISD::ADDC: Opc = X86ISD::ADD; break;
9145 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
9146 case ISD::SUBC: Opc = X86ISD::SUB; break;
9147 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
9151 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
9153 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
9154 Op.getOperand(1), Op.getOperand(2));
9157 /// LowerOperation - Provide custom lowering hooks for some operations.
9159 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
9160 switch (Op.getOpcode()) {
9161 default: llvm_unreachable("Should not custom lower this!");
9162 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
9163 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
9164 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
9165 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
9166 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
9167 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
9168 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
9169 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
9170 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
9171 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
9172 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
9173 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
9174 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
9175 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
9176 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
9177 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
9178 case ISD::SHL_PARTS:
9179 case ISD::SRA_PARTS:
9180 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
9181 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
9182 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
9183 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
9184 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
9185 case ISD::FABS: return LowerFABS(Op, DAG);
9186 case ISD::FNEG: return LowerFNEG(Op, DAG);
9187 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
9188 case ISD::SETCC: return LowerSETCC(Op, DAG);
9189 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
9190 case ISD::SELECT: return LowerSELECT(Op, DAG);
9191 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
9192 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
9193 case ISD::VASTART: return LowerVASTART(Op, DAG);
9194 case ISD::VAARG: return LowerVAARG(Op, DAG);
9195 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
9196 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
9197 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
9198 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
9199 case ISD::FRAME_TO_ARGS_OFFSET:
9200 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
9201 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
9202 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
9203 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
9204 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
9205 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
9206 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
9207 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
9210 case ISD::SHL: return LowerShift(Op, DAG);
9216 case ISD::UMULO: return LowerXALUO(Op, DAG);
9217 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
9218 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
9222 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
9226 void X86TargetLowering::
9227 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
9228 SelectionDAG &DAG, unsigned NewOp) const {
9229 EVT T = Node->getValueType(0);
9230 DebugLoc dl = Node->getDebugLoc();
9231 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
9233 SDValue Chain = Node->getOperand(0);
9234 SDValue In1 = Node->getOperand(1);
9235 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
9236 Node->getOperand(2), DAG.getIntPtrConstant(0));
9237 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
9238 Node->getOperand(2), DAG.getIntPtrConstant(1));
9239 SDValue Ops[] = { Chain, In1, In2L, In2H };
9240 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
9242 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
9243 cast<MemSDNode>(Node)->getMemOperand());
9244 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
9245 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
9246 Results.push_back(Result.getValue(2));
9249 /// ReplaceNodeResults - Replace a node with an illegal result type
9250 /// with a new node built out of custom code.
9251 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
9252 SmallVectorImpl<SDValue>&Results,
9253 SelectionDAG &DAG) const {
9254 DebugLoc dl = N->getDebugLoc();
9255 switch (N->getOpcode()) {
9257 assert(false && "Do not know how to custom type legalize this operation!");
9263 // We don't want to expand or promote these.
9265 case ISD::FP_TO_SINT: {
9266 std::pair<SDValue,SDValue> Vals =
9267 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
9268 SDValue FIST = Vals.first, StackSlot = Vals.second;
9269 if (FIST.getNode() != 0) {
9270 EVT VT = N->getValueType(0);
9271 // Return a load from the stack slot.
9272 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
9273 MachinePointerInfo(), false, false, 0));
9277 case ISD::READCYCLECOUNTER: {
9278 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
9279 SDValue TheChain = N->getOperand(0);
9280 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
9281 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
9283 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
9285 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
9286 SDValue Ops[] = { eax, edx };
9287 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
9288 Results.push_back(edx.getValue(1));
9291 case ISD::ATOMIC_CMP_SWAP: {
9292 EVT T = N->getValueType(0);
9293 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
9294 SDValue cpInL, cpInH;
9295 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
9296 DAG.getConstant(0, MVT::i32));
9297 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
9298 DAG.getConstant(1, MVT::i32));
9299 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
9300 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
9302 SDValue swapInL, swapInH;
9303 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
9304 DAG.getConstant(0, MVT::i32));
9305 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
9306 DAG.getConstant(1, MVT::i32));
9307 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
9309 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
9310 swapInL.getValue(1));
9311 SDValue Ops[] = { swapInH.getValue(0),
9313 swapInH.getValue(1) };
9314 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
9315 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
9316 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG8_DAG, dl, Tys,
9318 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
9319 MVT::i32, Result.getValue(1));
9320 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
9321 MVT::i32, cpOutL.getValue(2));
9322 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
9323 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
9324 Results.push_back(cpOutH.getValue(1));
9327 case ISD::ATOMIC_LOAD_ADD:
9328 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
9330 case ISD::ATOMIC_LOAD_AND:
9331 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
9333 case ISD::ATOMIC_LOAD_NAND:
9334 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
9336 case ISD::ATOMIC_LOAD_OR:
9337 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
9339 case ISD::ATOMIC_LOAD_SUB:
9340 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
9342 case ISD::ATOMIC_LOAD_XOR:
9343 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
9345 case ISD::ATOMIC_SWAP:
9346 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
9351 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
9353 default: return NULL;
9354 case X86ISD::BSF: return "X86ISD::BSF";
9355 case X86ISD::BSR: return "X86ISD::BSR";
9356 case X86ISD::SHLD: return "X86ISD::SHLD";
9357 case X86ISD::SHRD: return "X86ISD::SHRD";
9358 case X86ISD::FAND: return "X86ISD::FAND";
9359 case X86ISD::FOR: return "X86ISD::FOR";
9360 case X86ISD::FXOR: return "X86ISD::FXOR";
9361 case X86ISD::FSRL: return "X86ISD::FSRL";
9362 case X86ISD::FILD: return "X86ISD::FILD";
9363 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
9364 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
9365 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
9366 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
9367 case X86ISD::FLD: return "X86ISD::FLD";
9368 case X86ISD::FST: return "X86ISD::FST";
9369 case X86ISD::CALL: return "X86ISD::CALL";
9370 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
9371 case X86ISD::BT: return "X86ISD::BT";
9372 case X86ISD::CMP: return "X86ISD::CMP";
9373 case X86ISD::COMI: return "X86ISD::COMI";
9374 case X86ISD::UCOMI: return "X86ISD::UCOMI";
9375 case X86ISD::SETCC: return "X86ISD::SETCC";
9376 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
9377 case X86ISD::CMOV: return "X86ISD::CMOV";
9378 case X86ISD::BRCOND: return "X86ISD::BRCOND";
9379 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
9380 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
9381 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
9382 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
9383 case X86ISD::Wrapper: return "X86ISD::Wrapper";
9384 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
9385 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
9386 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
9387 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
9388 case X86ISD::PINSRB: return "X86ISD::PINSRB";
9389 case X86ISD::PINSRW: return "X86ISD::PINSRW";
9390 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
9391 case X86ISD::PANDN: return "X86ISD::PANDN";
9392 case X86ISD::PSIGNB: return "X86ISD::PSIGNB";
9393 case X86ISD::PSIGNW: return "X86ISD::PSIGNW";
9394 case X86ISD::PSIGND: return "X86ISD::PSIGND";
9395 case X86ISD::PBLENDVB: return "X86ISD::PBLENDVB";
9396 case X86ISD::FMAX: return "X86ISD::FMAX";
9397 case X86ISD::FMIN: return "X86ISD::FMIN";
9398 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
9399 case X86ISD::FRCP: return "X86ISD::FRCP";
9400 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
9401 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
9402 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
9403 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
9404 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
9405 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
9406 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
9407 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
9408 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
9409 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
9410 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
9411 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
9412 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
9413 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
9414 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
9415 case X86ISD::VSHL: return "X86ISD::VSHL";
9416 case X86ISD::VSRL: return "X86ISD::VSRL";
9417 case X86ISD::CMPPD: return "X86ISD::CMPPD";
9418 case X86ISD::CMPPS: return "X86ISD::CMPPS";
9419 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
9420 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
9421 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
9422 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
9423 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
9424 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
9425 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
9426 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
9427 case X86ISD::ADD: return "X86ISD::ADD";
9428 case X86ISD::SUB: return "X86ISD::SUB";
9429 case X86ISD::ADC: return "X86ISD::ADC";
9430 case X86ISD::SBB: return "X86ISD::SBB";
9431 case X86ISD::SMUL: return "X86ISD::SMUL";
9432 case X86ISD::UMUL: return "X86ISD::UMUL";
9433 case X86ISD::INC: return "X86ISD::INC";
9434 case X86ISD::DEC: return "X86ISD::DEC";
9435 case X86ISD::OR: return "X86ISD::OR";
9436 case X86ISD::XOR: return "X86ISD::XOR";
9437 case X86ISD::AND: return "X86ISD::AND";
9438 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
9439 case X86ISD::PTEST: return "X86ISD::PTEST";
9440 case X86ISD::TESTP: return "X86ISD::TESTP";
9441 case X86ISD::PALIGN: return "X86ISD::PALIGN";
9442 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
9443 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
9444 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD";
9445 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
9446 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD";
9447 case X86ISD::SHUFPS: return "X86ISD::SHUFPS";
9448 case X86ISD::SHUFPD: return "X86ISD::SHUFPD";
9449 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
9450 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
9451 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
9452 case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD";
9453 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
9454 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
9455 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
9456 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
9457 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
9458 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD";
9459 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD";
9460 case X86ISD::MOVSD: return "X86ISD::MOVSD";
9461 case X86ISD::MOVSS: return "X86ISD::MOVSS";
9462 case X86ISD::UNPCKLPS: return "X86ISD::UNPCKLPS";
9463 case X86ISD::UNPCKLPD: return "X86ISD::UNPCKLPD";
9464 case X86ISD::VUNPCKLPS: return "X86ISD::VUNPCKLPS";
9465 case X86ISD::VUNPCKLPD: return "X86ISD::VUNPCKLPD";
9466 case X86ISD::VUNPCKLPSY: return "X86ISD::VUNPCKLPSY";
9467 case X86ISD::VUNPCKLPDY: return "X86ISD::VUNPCKLPDY";
9468 case X86ISD::UNPCKHPS: return "X86ISD::UNPCKHPS";
9469 case X86ISD::UNPCKHPD: return "X86ISD::UNPCKHPD";
9470 case X86ISD::PUNPCKLBW: return "X86ISD::PUNPCKLBW";
9471 case X86ISD::PUNPCKLWD: return "X86ISD::PUNPCKLWD";
9472 case X86ISD::PUNPCKLDQ: return "X86ISD::PUNPCKLDQ";
9473 case X86ISD::PUNPCKLQDQ: return "X86ISD::PUNPCKLQDQ";
9474 case X86ISD::PUNPCKHBW: return "X86ISD::PUNPCKHBW";
9475 case X86ISD::PUNPCKHWD: return "X86ISD::PUNPCKHWD";
9476 case X86ISD::PUNPCKHDQ: return "X86ISD::PUNPCKHDQ";
9477 case X86ISD::PUNPCKHQDQ: return "X86ISD::PUNPCKHQDQ";
9478 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
9479 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
9480 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
9484 // isLegalAddressingMode - Return true if the addressing mode represented
9485 // by AM is legal for this target, for a load/store of the specified type.
9486 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
9487 const Type *Ty) const {
9488 // X86 supports extremely general addressing modes.
9489 CodeModel::Model M = getTargetMachine().getCodeModel();
9490 Reloc::Model R = getTargetMachine().getRelocationModel();
9492 // X86 allows a sign-extended 32-bit immediate field as a displacement.
9493 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
9498 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
9500 // If a reference to this global requires an extra load, we can't fold it.
9501 if (isGlobalStubReference(GVFlags))
9504 // If BaseGV requires a register for the PIC base, we cannot also have a
9505 // BaseReg specified.
9506 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
9509 // If lower 4G is not available, then we must use rip-relative addressing.
9510 if ((M != CodeModel::Small || R != Reloc::Static) &&
9511 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
9521 // These scales always work.
9526 // These scales are formed with basereg+scalereg. Only accept if there is
9531 default: // Other stuff never works.
9539 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
9540 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
9542 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
9543 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
9544 if (NumBits1 <= NumBits2)
9549 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
9550 if (!VT1.isInteger() || !VT2.isInteger())
9552 unsigned NumBits1 = VT1.getSizeInBits();
9553 unsigned NumBits2 = VT2.getSizeInBits();
9554 if (NumBits1 <= NumBits2)
9559 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
9560 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
9561 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
9564 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
9565 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
9566 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
9569 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
9570 // i16 instructions are longer (0x66 prefix) and potentially slower.
9571 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
9574 /// isShuffleMaskLegal - Targets can use this to indicate that they only
9575 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
9576 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
9577 /// are assumed to be legal.
9579 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
9581 // Very little shuffling can be done for 64-bit vectors right now.
9582 if (VT.getSizeInBits() == 64)
9583 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3());
9585 // FIXME: pshufb, blends, shifts.
9586 return (VT.getVectorNumElements() == 2 ||
9587 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
9588 isMOVLMask(M, VT) ||
9589 isSHUFPMask(M, VT) ||
9590 isPSHUFDMask(M, VT) ||
9591 isPSHUFHWMask(M, VT) ||
9592 isPSHUFLWMask(M, VT) ||
9593 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
9594 isUNPCKLMask(M, VT) ||
9595 isUNPCKHMask(M, VT) ||
9596 isUNPCKL_v_undef_Mask(M, VT) ||
9597 isUNPCKH_v_undef_Mask(M, VT));
9601 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
9603 unsigned NumElts = VT.getVectorNumElements();
9604 // FIXME: This collection of masks seems suspect.
9607 if (NumElts == 4 && VT.getSizeInBits() == 128) {
9608 return (isMOVLMask(Mask, VT) ||
9609 isCommutedMOVLMask(Mask, VT, true) ||
9610 isSHUFPMask(Mask, VT) ||
9611 isCommutedSHUFPMask(Mask, VT));
9616 //===----------------------------------------------------------------------===//
9617 // X86 Scheduler Hooks
9618 //===----------------------------------------------------------------------===//
9620 // private utility function
9622 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
9623 MachineBasicBlock *MBB,
9630 TargetRegisterClass *RC,
9631 bool invSrc) const {
9632 // For the atomic bitwise operator, we generate
9635 // ld t1 = [bitinstr.addr]
9636 // op t2 = t1, [bitinstr.val]
9638 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
9640 // fallthrough -->nextMBB
9641 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9642 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9643 MachineFunction::iterator MBBIter = MBB;
9646 /// First build the CFG
9647 MachineFunction *F = MBB->getParent();
9648 MachineBasicBlock *thisMBB = MBB;
9649 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
9650 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
9651 F->insert(MBBIter, newMBB);
9652 F->insert(MBBIter, nextMBB);
9654 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
9655 nextMBB->splice(nextMBB->begin(), thisMBB,
9656 llvm::next(MachineBasicBlock::iterator(bInstr)),
9658 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
9660 // Update thisMBB to fall through to newMBB
9661 thisMBB->addSuccessor(newMBB);
9663 // newMBB jumps to itself and fall through to nextMBB
9664 newMBB->addSuccessor(nextMBB);
9665 newMBB->addSuccessor(newMBB);
9667 // Insert instructions into newMBB based on incoming instruction
9668 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
9669 "unexpected number of operands");
9670 DebugLoc dl = bInstr->getDebugLoc();
9671 MachineOperand& destOper = bInstr->getOperand(0);
9672 MachineOperand* argOpers[2 + X86::AddrNumOperands];
9673 int numArgs = bInstr->getNumOperands() - 1;
9674 for (int i=0; i < numArgs; ++i)
9675 argOpers[i] = &bInstr->getOperand(i+1);
9677 // x86 address has 4 operands: base, index, scale, and displacement
9678 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
9679 int valArgIndx = lastAddrIndx + 1;
9681 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
9682 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
9683 for (int i=0; i <= lastAddrIndx; ++i)
9684 (*MIB).addOperand(*argOpers[i]);
9686 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
9688 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
9693 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
9694 assert((argOpers[valArgIndx]->isReg() ||
9695 argOpers[valArgIndx]->isImm()) &&
9697 if (argOpers[valArgIndx]->isReg())
9698 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
9700 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
9702 (*MIB).addOperand(*argOpers[valArgIndx]);
9704 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
9707 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
9708 for (int i=0; i <= lastAddrIndx; ++i)
9709 (*MIB).addOperand(*argOpers[i]);
9711 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
9712 (*MIB).setMemRefs(bInstr->memoperands_begin(),
9713 bInstr->memoperands_end());
9715 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
9719 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
9721 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
9725 // private utility function: 64 bit atomics on 32 bit host.
9727 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
9728 MachineBasicBlock *MBB,
9733 bool invSrc) const {
9734 // For the atomic bitwise operator, we generate
9735 // thisMBB (instructions are in pairs, except cmpxchg8b)
9736 // ld t1,t2 = [bitinstr.addr]
9738 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
9739 // op t5, t6 <- out1, out2, [bitinstr.val]
9740 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
9741 // mov ECX, EBX <- t5, t6
9742 // mov EAX, EDX <- t1, t2
9743 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
9744 // mov t3, t4 <- EAX, EDX
9746 // result in out1, out2
9747 // fallthrough -->nextMBB
9749 const TargetRegisterClass *RC = X86::GR32RegisterClass;
9750 const unsigned LoadOpc = X86::MOV32rm;
9751 const unsigned NotOpc = X86::NOT32r;
9752 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9753 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9754 MachineFunction::iterator MBBIter = MBB;
9757 /// First build the CFG
9758 MachineFunction *F = MBB->getParent();
9759 MachineBasicBlock *thisMBB = MBB;
9760 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
9761 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
9762 F->insert(MBBIter, newMBB);
9763 F->insert(MBBIter, nextMBB);
9765 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
9766 nextMBB->splice(nextMBB->begin(), thisMBB,
9767 llvm::next(MachineBasicBlock::iterator(bInstr)),
9769 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
9771 // Update thisMBB to fall through to newMBB
9772 thisMBB->addSuccessor(newMBB);
9774 // newMBB jumps to itself and fall through to nextMBB
9775 newMBB->addSuccessor(nextMBB);
9776 newMBB->addSuccessor(newMBB);
9778 DebugLoc dl = bInstr->getDebugLoc();
9779 // Insert instructions into newMBB based on incoming instruction
9780 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
9781 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
9782 "unexpected number of operands");
9783 MachineOperand& dest1Oper = bInstr->getOperand(0);
9784 MachineOperand& dest2Oper = bInstr->getOperand(1);
9785 MachineOperand* argOpers[2 + X86::AddrNumOperands];
9786 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
9787 argOpers[i] = &bInstr->getOperand(i+2);
9789 // We use some of the operands multiple times, so conservatively just
9790 // clear any kill flags that might be present.
9791 if (argOpers[i]->isReg() && argOpers[i]->isUse())
9792 argOpers[i]->setIsKill(false);
9795 // x86 address has 5 operands: base, index, scale, displacement, and segment.
9796 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
9798 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
9799 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
9800 for (int i=0; i <= lastAddrIndx; ++i)
9801 (*MIB).addOperand(*argOpers[i]);
9802 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
9803 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
9804 // add 4 to displacement.
9805 for (int i=0; i <= lastAddrIndx-2; ++i)
9806 (*MIB).addOperand(*argOpers[i]);
9807 MachineOperand newOp3 = *(argOpers[3]);
9809 newOp3.setImm(newOp3.getImm()+4);
9811 newOp3.setOffset(newOp3.getOffset()+4);
9812 (*MIB).addOperand(newOp3);
9813 (*MIB).addOperand(*argOpers[lastAddrIndx]);
9815 // t3/4 are defined later, at the bottom of the loop
9816 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
9817 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
9818 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
9819 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
9820 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
9821 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
9823 // The subsequent operations should be using the destination registers of
9824 //the PHI instructions.
9826 t1 = F->getRegInfo().createVirtualRegister(RC);
9827 t2 = F->getRegInfo().createVirtualRegister(RC);
9828 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
9829 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
9831 t1 = dest1Oper.getReg();
9832 t2 = dest2Oper.getReg();
9835 int valArgIndx = lastAddrIndx + 1;
9836 assert((argOpers[valArgIndx]->isReg() ||
9837 argOpers[valArgIndx]->isImm()) &&
9839 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
9840 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
9841 if (argOpers[valArgIndx]->isReg())
9842 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
9844 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
9845 if (regOpcL != X86::MOV32rr)
9847 (*MIB).addOperand(*argOpers[valArgIndx]);
9848 assert(argOpers[valArgIndx + 1]->isReg() ==
9849 argOpers[valArgIndx]->isReg());
9850 assert(argOpers[valArgIndx + 1]->isImm() ==
9851 argOpers[valArgIndx]->isImm());
9852 if (argOpers[valArgIndx + 1]->isReg())
9853 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
9855 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
9856 if (regOpcH != X86::MOV32rr)
9858 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
9860 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
9862 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
9865 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
9867 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
9870 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
9871 for (int i=0; i <= lastAddrIndx; ++i)
9872 (*MIB).addOperand(*argOpers[i]);
9874 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
9875 (*MIB).setMemRefs(bInstr->memoperands_begin(),
9876 bInstr->memoperands_end());
9878 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
9879 MIB.addReg(X86::EAX);
9880 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
9881 MIB.addReg(X86::EDX);
9884 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
9886 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
9890 // private utility function
9892 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
9893 MachineBasicBlock *MBB,
9894 unsigned cmovOpc) const {
9895 // For the atomic min/max operator, we generate
9898 // ld t1 = [min/max.addr]
9899 // mov t2 = [min/max.val]
9901 // cmov[cond] t2 = t1
9903 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
9905 // fallthrough -->nextMBB
9907 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9908 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9909 MachineFunction::iterator MBBIter = MBB;
9912 /// First build the CFG
9913 MachineFunction *F = MBB->getParent();
9914 MachineBasicBlock *thisMBB = MBB;
9915 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
9916 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
9917 F->insert(MBBIter, newMBB);
9918 F->insert(MBBIter, nextMBB);
9920 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
9921 nextMBB->splice(nextMBB->begin(), thisMBB,
9922 llvm::next(MachineBasicBlock::iterator(mInstr)),
9924 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
9926 // Update thisMBB to fall through to newMBB
9927 thisMBB->addSuccessor(newMBB);
9929 // newMBB jumps to newMBB and fall through to nextMBB
9930 newMBB->addSuccessor(nextMBB);
9931 newMBB->addSuccessor(newMBB);
9933 DebugLoc dl = mInstr->getDebugLoc();
9934 // Insert instructions into newMBB based on incoming instruction
9935 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
9936 "unexpected number of operands");
9937 MachineOperand& destOper = mInstr->getOperand(0);
9938 MachineOperand* argOpers[2 + X86::AddrNumOperands];
9939 int numArgs = mInstr->getNumOperands() - 1;
9940 for (int i=0; i < numArgs; ++i)
9941 argOpers[i] = &mInstr->getOperand(i+1);
9943 // x86 address has 4 operands: base, index, scale, and displacement
9944 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
9945 int valArgIndx = lastAddrIndx + 1;
9947 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
9948 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
9949 for (int i=0; i <= lastAddrIndx; ++i)
9950 (*MIB).addOperand(*argOpers[i]);
9952 // We only support register and immediate values
9953 assert((argOpers[valArgIndx]->isReg() ||
9954 argOpers[valArgIndx]->isImm()) &&
9957 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
9958 if (argOpers[valArgIndx]->isReg())
9959 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
9961 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
9962 (*MIB).addOperand(*argOpers[valArgIndx]);
9964 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
9967 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
9972 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
9973 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
9977 // Cmp and exchange if none has modified the memory location
9978 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
9979 for (int i=0; i <= lastAddrIndx; ++i)
9980 (*MIB).addOperand(*argOpers[i]);
9982 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
9983 (*MIB).setMemRefs(mInstr->memoperands_begin(),
9984 mInstr->memoperands_end());
9986 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
9987 MIB.addReg(X86::EAX);
9990 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
9992 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
9996 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
9997 // or XMM0_V32I8 in AVX all of this code can be replaced with that
10000 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
10001 unsigned numArgs, bool memArg) const {
10002 assert((Subtarget->hasSSE42() || Subtarget->hasAVX()) &&
10003 "Target must have SSE4.2 or AVX features enabled");
10005 DebugLoc dl = MI->getDebugLoc();
10006 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10008 if (!Subtarget->hasAVX()) {
10010 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
10012 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
10015 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
10017 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
10020 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
10021 for (unsigned i = 0; i < numArgs; ++i) {
10022 MachineOperand &Op = MI->getOperand(i+1);
10023 if (!(Op.isReg() && Op.isImplicit()))
10024 MIB.addOperand(Op);
10026 BuildMI(*BB, MI, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
10027 .addReg(X86::XMM0);
10029 MI->eraseFromParent();
10033 MachineBasicBlock *
10034 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
10035 DebugLoc dl = MI->getDebugLoc();
10036 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10038 // Address into RAX/EAX, other two args into ECX, EDX.
10039 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
10040 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
10041 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
10042 for (int i = 0; i < X86::AddrNumOperands; ++i)
10043 MIB.addOperand(MI->getOperand(i));
10045 unsigned ValOps = X86::AddrNumOperands;
10046 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
10047 .addReg(MI->getOperand(ValOps).getReg());
10048 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
10049 .addReg(MI->getOperand(ValOps+1).getReg());
10051 // The instruction doesn't actually take any operands though.
10052 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
10054 MI->eraseFromParent(); // The pseudo is gone now.
10058 MachineBasicBlock *
10059 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
10060 DebugLoc dl = MI->getDebugLoc();
10061 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10063 // First arg in ECX, the second in EAX.
10064 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
10065 .addReg(MI->getOperand(0).getReg());
10066 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
10067 .addReg(MI->getOperand(1).getReg());
10069 // The instruction doesn't actually take any operands though.
10070 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
10072 MI->eraseFromParent(); // The pseudo is gone now.
10076 MachineBasicBlock *
10077 X86TargetLowering::EmitVAARG64WithCustomInserter(
10079 MachineBasicBlock *MBB) const {
10080 // Emit va_arg instruction on X86-64.
10082 // Operands to this pseudo-instruction:
10083 // 0 ) Output : destination address (reg)
10084 // 1-5) Input : va_list address (addr, i64mem)
10085 // 6 ) ArgSize : Size (in bytes) of vararg type
10086 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
10087 // 8 ) Align : Alignment of type
10088 // 9 ) EFLAGS (implicit-def)
10090 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
10091 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
10093 unsigned DestReg = MI->getOperand(0).getReg();
10094 MachineOperand &Base = MI->getOperand(1);
10095 MachineOperand &Scale = MI->getOperand(2);
10096 MachineOperand &Index = MI->getOperand(3);
10097 MachineOperand &Disp = MI->getOperand(4);
10098 MachineOperand &Segment = MI->getOperand(5);
10099 unsigned ArgSize = MI->getOperand(6).getImm();
10100 unsigned ArgMode = MI->getOperand(7).getImm();
10101 unsigned Align = MI->getOperand(8).getImm();
10103 // Memory Reference
10104 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
10105 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
10106 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
10108 // Machine Information
10109 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10110 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
10111 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
10112 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
10113 DebugLoc DL = MI->getDebugLoc();
10115 // struct va_list {
10118 // i64 overflow_area (address)
10119 // i64 reg_save_area (address)
10121 // sizeof(va_list) = 24
10122 // alignment(va_list) = 8
10124 unsigned TotalNumIntRegs = 6;
10125 unsigned TotalNumXMMRegs = 8;
10126 bool UseGPOffset = (ArgMode == 1);
10127 bool UseFPOffset = (ArgMode == 2);
10128 unsigned MaxOffset = TotalNumIntRegs * 8 +
10129 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
10131 /* Align ArgSize to a multiple of 8 */
10132 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
10133 bool NeedsAlign = (Align > 8);
10135 MachineBasicBlock *thisMBB = MBB;
10136 MachineBasicBlock *overflowMBB;
10137 MachineBasicBlock *offsetMBB;
10138 MachineBasicBlock *endMBB;
10140 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
10141 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
10142 unsigned OffsetReg = 0;
10144 if (!UseGPOffset && !UseFPOffset) {
10145 // If we only pull from the overflow region, we don't create a branch.
10146 // We don't need to alter control flow.
10147 OffsetDestReg = 0; // unused
10148 OverflowDestReg = DestReg;
10151 overflowMBB = thisMBB;
10154 // First emit code to check if gp_offset (or fp_offset) is below the bound.
10155 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
10156 // If not, pull from overflow_area. (branch to overflowMBB)
10161 // offsetMBB overflowMBB
10166 // Registers for the PHI in endMBB
10167 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
10168 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
10170 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
10171 MachineFunction *MF = MBB->getParent();
10172 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
10173 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
10174 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
10176 MachineFunction::iterator MBBIter = MBB;
10179 // Insert the new basic blocks
10180 MF->insert(MBBIter, offsetMBB);
10181 MF->insert(MBBIter, overflowMBB);
10182 MF->insert(MBBIter, endMBB);
10184 // Transfer the remainder of MBB and its successor edges to endMBB.
10185 endMBB->splice(endMBB->begin(), thisMBB,
10186 llvm::next(MachineBasicBlock::iterator(MI)),
10188 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
10190 // Make offsetMBB and overflowMBB successors of thisMBB
10191 thisMBB->addSuccessor(offsetMBB);
10192 thisMBB->addSuccessor(overflowMBB);
10194 // endMBB is a successor of both offsetMBB and overflowMBB
10195 offsetMBB->addSuccessor(endMBB);
10196 overflowMBB->addSuccessor(endMBB);
10198 // Load the offset value into a register
10199 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
10200 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
10204 .addDisp(Disp, UseFPOffset ? 4 : 0)
10205 .addOperand(Segment)
10206 .setMemRefs(MMOBegin, MMOEnd);
10208 // Check if there is enough room left to pull this argument.
10209 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
10211 .addImm(MaxOffset + 8 - ArgSizeA8);
10213 // Branch to "overflowMBB" if offset >= max
10214 // Fall through to "offsetMBB" otherwise
10215 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
10216 .addMBB(overflowMBB);
10219 // In offsetMBB, emit code to use the reg_save_area.
10221 assert(OffsetReg != 0);
10223 // Read the reg_save_area address.
10224 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
10225 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
10230 .addOperand(Segment)
10231 .setMemRefs(MMOBegin, MMOEnd);
10233 // Zero-extend the offset
10234 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
10235 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
10238 .addImm(X86::sub_32bit);
10240 // Add the offset to the reg_save_area to get the final address.
10241 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
10242 .addReg(OffsetReg64)
10243 .addReg(RegSaveReg);
10245 // Compute the offset for the next argument
10246 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
10247 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
10249 .addImm(UseFPOffset ? 16 : 8);
10251 // Store it back into the va_list.
10252 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
10256 .addDisp(Disp, UseFPOffset ? 4 : 0)
10257 .addOperand(Segment)
10258 .addReg(NextOffsetReg)
10259 .setMemRefs(MMOBegin, MMOEnd);
10262 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
10267 // Emit code to use overflow area
10270 // Load the overflow_area address into a register.
10271 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
10272 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
10277 .addOperand(Segment)
10278 .setMemRefs(MMOBegin, MMOEnd);
10280 // If we need to align it, do so. Otherwise, just copy the address
10281 // to OverflowDestReg.
10283 // Align the overflow address
10284 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
10285 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
10287 // aligned_addr = (addr + (align-1)) & ~(align-1)
10288 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
10289 .addReg(OverflowAddrReg)
10292 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
10294 .addImm(~(uint64_t)(Align-1));
10296 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
10297 .addReg(OverflowAddrReg);
10300 // Compute the next overflow address after this argument.
10301 // (the overflow address should be kept 8-byte aligned)
10302 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
10303 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
10304 .addReg(OverflowDestReg)
10305 .addImm(ArgSizeA8);
10307 // Store the new overflow address.
10308 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
10313 .addOperand(Segment)
10314 .addReg(NextAddrReg)
10315 .setMemRefs(MMOBegin, MMOEnd);
10317 // If we branched, emit the PHI to the front of endMBB.
10319 BuildMI(*endMBB, endMBB->begin(), DL,
10320 TII->get(X86::PHI), DestReg)
10321 .addReg(OffsetDestReg).addMBB(offsetMBB)
10322 .addReg(OverflowDestReg).addMBB(overflowMBB);
10325 // Erase the pseudo instruction
10326 MI->eraseFromParent();
10331 MachineBasicBlock *
10332 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
10334 MachineBasicBlock *MBB) const {
10335 // Emit code to save XMM registers to the stack. The ABI says that the
10336 // number of registers to save is given in %al, so it's theoretically
10337 // possible to do an indirect jump trick to avoid saving all of them,
10338 // however this code takes a simpler approach and just executes all
10339 // of the stores if %al is non-zero. It's less code, and it's probably
10340 // easier on the hardware branch predictor, and stores aren't all that
10341 // expensive anyway.
10343 // Create the new basic blocks. One block contains all the XMM stores,
10344 // and one block is the final destination regardless of whether any
10345 // stores were performed.
10346 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
10347 MachineFunction *F = MBB->getParent();
10348 MachineFunction::iterator MBBIter = MBB;
10350 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
10351 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
10352 F->insert(MBBIter, XMMSaveMBB);
10353 F->insert(MBBIter, EndMBB);
10355 // Transfer the remainder of MBB and its successor edges to EndMBB.
10356 EndMBB->splice(EndMBB->begin(), MBB,
10357 llvm::next(MachineBasicBlock::iterator(MI)),
10359 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
10361 // The original block will now fall through to the XMM save block.
10362 MBB->addSuccessor(XMMSaveMBB);
10363 // The XMMSaveMBB will fall through to the end block.
10364 XMMSaveMBB->addSuccessor(EndMBB);
10366 // Now add the instructions.
10367 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10368 DebugLoc DL = MI->getDebugLoc();
10370 unsigned CountReg = MI->getOperand(0).getReg();
10371 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
10372 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
10374 if (!Subtarget->isTargetWin64()) {
10375 // If %al is 0, branch around the XMM save block.
10376 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
10377 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
10378 MBB->addSuccessor(EndMBB);
10381 // In the XMM save block, save all the XMM argument registers.
10382 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
10383 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
10384 MachineMemOperand *MMO =
10385 F->getMachineMemOperand(
10386 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
10387 MachineMemOperand::MOStore,
10388 /*Size=*/16, /*Align=*/16);
10389 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
10390 .addFrameIndex(RegSaveFrameIndex)
10391 .addImm(/*Scale=*/1)
10392 .addReg(/*IndexReg=*/0)
10393 .addImm(/*Disp=*/Offset)
10394 .addReg(/*Segment=*/0)
10395 .addReg(MI->getOperand(i).getReg())
10396 .addMemOperand(MMO);
10399 MI->eraseFromParent(); // The pseudo instruction is gone now.
10404 MachineBasicBlock *
10405 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
10406 MachineBasicBlock *BB) const {
10407 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10408 DebugLoc DL = MI->getDebugLoc();
10410 // To "insert" a SELECT_CC instruction, we actually have to insert the
10411 // diamond control-flow pattern. The incoming instruction knows the
10412 // destination vreg to set, the condition code register to branch on, the
10413 // true/false values to select between, and a branch opcode to use.
10414 const BasicBlock *LLVM_BB = BB->getBasicBlock();
10415 MachineFunction::iterator It = BB;
10421 // cmpTY ccX, r1, r2
10423 // fallthrough --> copy0MBB
10424 MachineBasicBlock *thisMBB = BB;
10425 MachineFunction *F = BB->getParent();
10426 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
10427 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
10428 F->insert(It, copy0MBB);
10429 F->insert(It, sinkMBB);
10431 // If the EFLAGS register isn't dead in the terminator, then claim that it's
10432 // live into the sink and copy blocks.
10433 const MachineFunction *MF = BB->getParent();
10434 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
10435 BitVector ReservedRegs = TRI->getReservedRegs(*MF);
10437 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
10438 const MachineOperand &MO = MI->getOperand(I);
10439 if (!MO.isReg() || !MO.isUse() || MO.isKill()) continue;
10440 unsigned Reg = MO.getReg();
10441 if (Reg != X86::EFLAGS) continue;
10442 copy0MBB->addLiveIn(Reg);
10443 sinkMBB->addLiveIn(Reg);
10446 // Transfer the remainder of BB and its successor edges to sinkMBB.
10447 sinkMBB->splice(sinkMBB->begin(), BB,
10448 llvm::next(MachineBasicBlock::iterator(MI)),
10450 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
10452 // Add the true and fallthrough blocks as its successors.
10453 BB->addSuccessor(copy0MBB);
10454 BB->addSuccessor(sinkMBB);
10456 // Create the conditional branch instruction.
10458 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
10459 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
10462 // %FalseValue = ...
10463 // # fallthrough to sinkMBB
10464 copy0MBB->addSuccessor(sinkMBB);
10467 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
10469 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
10470 TII->get(X86::PHI), MI->getOperand(0).getReg())
10471 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
10472 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
10474 MI->eraseFromParent(); // The pseudo instruction is gone now.
10478 MachineBasicBlock *
10479 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
10480 MachineBasicBlock *BB) const {
10481 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10482 DebugLoc DL = MI->getDebugLoc();
10484 assert(!Subtarget->isTargetEnvMacho());
10486 // The lowering is pretty easy: we're just emitting the call to _alloca. The
10487 // non-trivial part is impdef of ESP.
10489 if (Subtarget->isTargetWin64()) {
10490 if (Subtarget->isTargetCygMing()) {
10491 // ___chkstk(Mingw64):
10492 // Clobbers R10, R11, RAX and EFLAGS.
10494 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
10495 .addExternalSymbol("___chkstk")
10496 .addReg(X86::RAX, RegState::Implicit)
10497 .addReg(X86::RSP, RegState::Implicit)
10498 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
10499 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
10500 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
10502 // __chkstk(MSVCRT): does not update stack pointer.
10503 // Clobbers R10, R11 and EFLAGS.
10504 // FIXME: RAX(allocated size) might be reused and not killed.
10505 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
10506 .addExternalSymbol("__chkstk")
10507 .addReg(X86::RAX, RegState::Implicit)
10508 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
10509 // RAX has the offset to subtracted from RSP.
10510 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
10515 const char *StackProbeSymbol =
10516 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
10518 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
10519 .addExternalSymbol(StackProbeSymbol)
10520 .addReg(X86::EAX, RegState::Implicit)
10521 .addReg(X86::ESP, RegState::Implicit)
10522 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
10523 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
10524 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
10527 MI->eraseFromParent(); // The pseudo instruction is gone now.
10531 MachineBasicBlock *
10532 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
10533 MachineBasicBlock *BB) const {
10534 // This is pretty easy. We're taking the value that we received from
10535 // our load from the relocation, sticking it in either RDI (x86-64)
10536 // or EAX and doing an indirect call. The return value will then
10537 // be in the normal return register.
10538 const X86InstrInfo *TII
10539 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
10540 DebugLoc DL = MI->getDebugLoc();
10541 MachineFunction *F = BB->getParent();
10543 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
10544 assert(MI->getOperand(3).isGlobal() && "This should be a global");
10546 if (Subtarget->is64Bit()) {
10547 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
10548 TII->get(X86::MOV64rm), X86::RDI)
10550 .addImm(0).addReg(0)
10551 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
10552 MI->getOperand(3).getTargetFlags())
10554 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
10555 addDirectMem(MIB, X86::RDI);
10556 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
10557 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
10558 TII->get(X86::MOV32rm), X86::EAX)
10560 .addImm(0).addReg(0)
10561 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
10562 MI->getOperand(3).getTargetFlags())
10564 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
10565 addDirectMem(MIB, X86::EAX);
10567 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
10568 TII->get(X86::MOV32rm), X86::EAX)
10569 .addReg(TII->getGlobalBaseReg(F))
10570 .addImm(0).addReg(0)
10571 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
10572 MI->getOperand(3).getTargetFlags())
10574 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
10575 addDirectMem(MIB, X86::EAX);
10578 MI->eraseFromParent(); // The pseudo instruction is gone now.
10582 MachineBasicBlock *
10583 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
10584 MachineBasicBlock *BB) const {
10585 switch (MI->getOpcode()) {
10586 default: assert(false && "Unexpected instr type to insert");
10587 case X86::TAILJMPd64:
10588 case X86::TAILJMPr64:
10589 case X86::TAILJMPm64:
10590 assert(!"TAILJMP64 would not be touched here.");
10591 case X86::TCRETURNdi64:
10592 case X86::TCRETURNri64:
10593 case X86::TCRETURNmi64:
10594 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset.
10595 // On AMD64, additional defs should be added before register allocation.
10596 if (!Subtarget->isTargetWin64()) {
10597 MI->addRegisterDefined(X86::RSI);
10598 MI->addRegisterDefined(X86::RDI);
10599 MI->addRegisterDefined(X86::XMM6);
10600 MI->addRegisterDefined(X86::XMM7);
10601 MI->addRegisterDefined(X86::XMM8);
10602 MI->addRegisterDefined(X86::XMM9);
10603 MI->addRegisterDefined(X86::XMM10);
10604 MI->addRegisterDefined(X86::XMM11);
10605 MI->addRegisterDefined(X86::XMM12);
10606 MI->addRegisterDefined(X86::XMM13);
10607 MI->addRegisterDefined(X86::XMM14);
10608 MI->addRegisterDefined(X86::XMM15);
10611 case X86::WIN_ALLOCA:
10612 return EmitLoweredWinAlloca(MI, BB);
10613 case X86::TLSCall_32:
10614 case X86::TLSCall_64:
10615 return EmitLoweredTLSCall(MI, BB);
10616 case X86::CMOV_GR8:
10617 case X86::CMOV_FR32:
10618 case X86::CMOV_FR64:
10619 case X86::CMOV_V4F32:
10620 case X86::CMOV_V2F64:
10621 case X86::CMOV_V2I64:
10622 case X86::CMOV_GR16:
10623 case X86::CMOV_GR32:
10624 case X86::CMOV_RFP32:
10625 case X86::CMOV_RFP64:
10626 case X86::CMOV_RFP80:
10627 return EmitLoweredSelect(MI, BB);
10629 case X86::FP32_TO_INT16_IN_MEM:
10630 case X86::FP32_TO_INT32_IN_MEM:
10631 case X86::FP32_TO_INT64_IN_MEM:
10632 case X86::FP64_TO_INT16_IN_MEM:
10633 case X86::FP64_TO_INT32_IN_MEM:
10634 case X86::FP64_TO_INT64_IN_MEM:
10635 case X86::FP80_TO_INT16_IN_MEM:
10636 case X86::FP80_TO_INT32_IN_MEM:
10637 case X86::FP80_TO_INT64_IN_MEM: {
10638 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10639 DebugLoc DL = MI->getDebugLoc();
10641 // Change the floating point control register to use "round towards zero"
10642 // mode when truncating to an integer value.
10643 MachineFunction *F = BB->getParent();
10644 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
10645 addFrameReference(BuildMI(*BB, MI, DL,
10646 TII->get(X86::FNSTCW16m)), CWFrameIdx);
10648 // Load the old value of the high byte of the control word...
10650 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
10651 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
10654 // Set the high part to be round to zero...
10655 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
10658 // Reload the modified control word now...
10659 addFrameReference(BuildMI(*BB, MI, DL,
10660 TII->get(X86::FLDCW16m)), CWFrameIdx);
10662 // Restore the memory image of control word to original value
10663 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
10666 // Get the X86 opcode to use.
10668 switch (MI->getOpcode()) {
10669 default: llvm_unreachable("illegal opcode!");
10670 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
10671 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
10672 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
10673 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
10674 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
10675 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
10676 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
10677 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
10678 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
10682 MachineOperand &Op = MI->getOperand(0);
10684 AM.BaseType = X86AddressMode::RegBase;
10685 AM.Base.Reg = Op.getReg();
10687 AM.BaseType = X86AddressMode::FrameIndexBase;
10688 AM.Base.FrameIndex = Op.getIndex();
10690 Op = MI->getOperand(1);
10692 AM.Scale = Op.getImm();
10693 Op = MI->getOperand(2);
10695 AM.IndexReg = Op.getImm();
10696 Op = MI->getOperand(3);
10697 if (Op.isGlobal()) {
10698 AM.GV = Op.getGlobal();
10700 AM.Disp = Op.getImm();
10702 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
10703 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
10705 // Reload the original control word now.
10706 addFrameReference(BuildMI(*BB, MI, DL,
10707 TII->get(X86::FLDCW16m)), CWFrameIdx);
10709 MI->eraseFromParent(); // The pseudo instruction is gone now.
10712 // String/text processing lowering.
10713 case X86::PCMPISTRM128REG:
10714 case X86::VPCMPISTRM128REG:
10715 return EmitPCMP(MI, BB, 3, false /* in-mem */);
10716 case X86::PCMPISTRM128MEM:
10717 case X86::VPCMPISTRM128MEM:
10718 return EmitPCMP(MI, BB, 3, true /* in-mem */);
10719 case X86::PCMPESTRM128REG:
10720 case X86::VPCMPESTRM128REG:
10721 return EmitPCMP(MI, BB, 5, false /* in mem */);
10722 case X86::PCMPESTRM128MEM:
10723 case X86::VPCMPESTRM128MEM:
10724 return EmitPCMP(MI, BB, 5, true /* in mem */);
10726 // Thread synchronization.
10728 return EmitMonitor(MI, BB);
10730 return EmitMwait(MI, BB);
10732 // Atomic Lowering.
10733 case X86::ATOMAND32:
10734 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
10735 X86::AND32ri, X86::MOV32rm,
10737 X86::NOT32r, X86::EAX,
10738 X86::GR32RegisterClass);
10739 case X86::ATOMOR32:
10740 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
10741 X86::OR32ri, X86::MOV32rm,
10743 X86::NOT32r, X86::EAX,
10744 X86::GR32RegisterClass);
10745 case X86::ATOMXOR32:
10746 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
10747 X86::XOR32ri, X86::MOV32rm,
10749 X86::NOT32r, X86::EAX,
10750 X86::GR32RegisterClass);
10751 case X86::ATOMNAND32:
10752 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
10753 X86::AND32ri, X86::MOV32rm,
10755 X86::NOT32r, X86::EAX,
10756 X86::GR32RegisterClass, true);
10757 case X86::ATOMMIN32:
10758 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
10759 case X86::ATOMMAX32:
10760 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
10761 case X86::ATOMUMIN32:
10762 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
10763 case X86::ATOMUMAX32:
10764 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
10766 case X86::ATOMAND16:
10767 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
10768 X86::AND16ri, X86::MOV16rm,
10770 X86::NOT16r, X86::AX,
10771 X86::GR16RegisterClass);
10772 case X86::ATOMOR16:
10773 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
10774 X86::OR16ri, X86::MOV16rm,
10776 X86::NOT16r, X86::AX,
10777 X86::GR16RegisterClass);
10778 case X86::ATOMXOR16:
10779 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
10780 X86::XOR16ri, X86::MOV16rm,
10782 X86::NOT16r, X86::AX,
10783 X86::GR16RegisterClass);
10784 case X86::ATOMNAND16:
10785 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
10786 X86::AND16ri, X86::MOV16rm,
10788 X86::NOT16r, X86::AX,
10789 X86::GR16RegisterClass, true);
10790 case X86::ATOMMIN16:
10791 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
10792 case X86::ATOMMAX16:
10793 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
10794 case X86::ATOMUMIN16:
10795 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
10796 case X86::ATOMUMAX16:
10797 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
10799 case X86::ATOMAND8:
10800 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
10801 X86::AND8ri, X86::MOV8rm,
10803 X86::NOT8r, X86::AL,
10804 X86::GR8RegisterClass);
10806 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
10807 X86::OR8ri, X86::MOV8rm,
10809 X86::NOT8r, X86::AL,
10810 X86::GR8RegisterClass);
10811 case X86::ATOMXOR8:
10812 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
10813 X86::XOR8ri, X86::MOV8rm,
10815 X86::NOT8r, X86::AL,
10816 X86::GR8RegisterClass);
10817 case X86::ATOMNAND8:
10818 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
10819 X86::AND8ri, X86::MOV8rm,
10821 X86::NOT8r, X86::AL,
10822 X86::GR8RegisterClass, true);
10823 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
10824 // This group is for 64-bit host.
10825 case X86::ATOMAND64:
10826 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
10827 X86::AND64ri32, X86::MOV64rm,
10829 X86::NOT64r, X86::RAX,
10830 X86::GR64RegisterClass);
10831 case X86::ATOMOR64:
10832 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
10833 X86::OR64ri32, X86::MOV64rm,
10835 X86::NOT64r, X86::RAX,
10836 X86::GR64RegisterClass);
10837 case X86::ATOMXOR64:
10838 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
10839 X86::XOR64ri32, X86::MOV64rm,
10841 X86::NOT64r, X86::RAX,
10842 X86::GR64RegisterClass);
10843 case X86::ATOMNAND64:
10844 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
10845 X86::AND64ri32, X86::MOV64rm,
10847 X86::NOT64r, X86::RAX,
10848 X86::GR64RegisterClass, true);
10849 case X86::ATOMMIN64:
10850 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
10851 case X86::ATOMMAX64:
10852 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
10853 case X86::ATOMUMIN64:
10854 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
10855 case X86::ATOMUMAX64:
10856 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
10858 // This group does 64-bit operations on a 32-bit host.
10859 case X86::ATOMAND6432:
10860 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10861 X86::AND32rr, X86::AND32rr,
10862 X86::AND32ri, X86::AND32ri,
10864 case X86::ATOMOR6432:
10865 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10866 X86::OR32rr, X86::OR32rr,
10867 X86::OR32ri, X86::OR32ri,
10869 case X86::ATOMXOR6432:
10870 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10871 X86::XOR32rr, X86::XOR32rr,
10872 X86::XOR32ri, X86::XOR32ri,
10874 case X86::ATOMNAND6432:
10875 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10876 X86::AND32rr, X86::AND32rr,
10877 X86::AND32ri, X86::AND32ri,
10879 case X86::ATOMADD6432:
10880 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10881 X86::ADD32rr, X86::ADC32rr,
10882 X86::ADD32ri, X86::ADC32ri,
10884 case X86::ATOMSUB6432:
10885 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10886 X86::SUB32rr, X86::SBB32rr,
10887 X86::SUB32ri, X86::SBB32ri,
10889 case X86::ATOMSWAP6432:
10890 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10891 X86::MOV32rr, X86::MOV32rr,
10892 X86::MOV32ri, X86::MOV32ri,
10894 case X86::VASTART_SAVE_XMM_REGS:
10895 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
10897 case X86::VAARG_64:
10898 return EmitVAARG64WithCustomInserter(MI, BB);
10902 //===----------------------------------------------------------------------===//
10903 // X86 Optimization Hooks
10904 //===----------------------------------------------------------------------===//
10906 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
10910 const SelectionDAG &DAG,
10911 unsigned Depth) const {
10912 unsigned Opc = Op.getOpcode();
10913 assert((Opc >= ISD::BUILTIN_OP_END ||
10914 Opc == ISD::INTRINSIC_WO_CHAIN ||
10915 Opc == ISD::INTRINSIC_W_CHAIN ||
10916 Opc == ISD::INTRINSIC_VOID) &&
10917 "Should use MaskedValueIsZero if you don't know whether Op"
10918 " is a target node!");
10920 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
10934 // These nodes' second result is a boolean.
10935 if (Op.getResNo() == 0)
10938 case X86ISD::SETCC:
10939 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
10940 Mask.getBitWidth() - 1);
10943 case ISD::INTRINSIC_WO_CHAIN: {
10944 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
10947 case Intrinsic::x86_sse42_crc64_8:
10948 case Intrinsic::x86_sse42_crc64_64:
10949 // crc32 with 64-bit destination zeros high 32-bit.
10950 KnownZero |= APInt::getHighBitsSet(64, 32);
10958 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
10959 unsigned Depth) const {
10960 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
10961 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
10962 return Op.getValueType().getScalarType().getSizeInBits();
10968 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
10969 /// node is a GlobalAddress + offset.
10970 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
10971 const GlobalValue* &GA,
10972 int64_t &Offset) const {
10973 if (N->getOpcode() == X86ISD::Wrapper) {
10974 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
10975 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
10976 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
10980 return TargetLowering::isGAPlusOffset(N, GA, Offset);
10983 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
10984 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
10985 /// if the load addresses are consecutive, non-overlapping, and in the right
10987 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
10988 TargetLowering::DAGCombinerInfo &DCI) {
10989 DebugLoc dl = N->getDebugLoc();
10990 EVT VT = N->getValueType(0);
10992 if (VT.getSizeInBits() != 128)
10995 // Don't create instructions with illegal types after legalize types has run.
10996 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10997 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
11000 SmallVector<SDValue, 16> Elts;
11001 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
11002 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
11004 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
11007 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
11008 /// generation and convert it from being a bunch of shuffles and extracts
11009 /// to a simple store and scalar loads to extract the elements.
11010 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
11011 const TargetLowering &TLI) {
11012 SDValue InputVector = N->getOperand(0);
11014 // Only operate on vectors of 4 elements, where the alternative shuffling
11015 // gets to be more expensive.
11016 if (InputVector.getValueType() != MVT::v4i32)
11019 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
11020 // single use which is a sign-extend or zero-extend, and all elements are
11022 SmallVector<SDNode *, 4> Uses;
11023 unsigned ExtractedElements = 0;
11024 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
11025 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
11026 if (UI.getUse().getResNo() != InputVector.getResNo())
11029 SDNode *Extract = *UI;
11030 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
11033 if (Extract->getValueType(0) != MVT::i32)
11035 if (!Extract->hasOneUse())
11037 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
11038 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
11040 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
11043 // Record which element was extracted.
11044 ExtractedElements |=
11045 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
11047 Uses.push_back(Extract);
11050 // If not all the elements were used, this may not be worthwhile.
11051 if (ExtractedElements != 15)
11054 // Ok, we've now decided to do the transformation.
11055 DebugLoc dl = InputVector.getDebugLoc();
11057 // Store the value to a temporary stack slot.
11058 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
11059 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
11060 MachinePointerInfo(), false, false, 0);
11062 // Replace each use (extract) with a load of the appropriate element.
11063 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
11064 UE = Uses.end(); UI != UE; ++UI) {
11065 SDNode *Extract = *UI;
11067 // cOMpute the element's address.
11068 SDValue Idx = Extract->getOperand(1);
11070 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
11071 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
11072 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
11074 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
11075 StackPtr, OffsetVal);
11077 // Load the scalar.
11078 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
11079 ScalarAddr, MachinePointerInfo(),
11082 // Replace the exact with the load.
11083 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
11086 // The replacement was made in place; don't return anything.
11090 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
11091 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
11092 const X86Subtarget *Subtarget) {
11093 DebugLoc DL = N->getDebugLoc();
11094 SDValue Cond = N->getOperand(0);
11095 // Get the LHS/RHS of the select.
11096 SDValue LHS = N->getOperand(1);
11097 SDValue RHS = N->getOperand(2);
11099 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
11100 // instructions match the semantics of the common C idiom x<y?x:y but not
11101 // x<=y?x:y, because of how they handle negative zero (which can be
11102 // ignored in unsafe-math mode).
11103 if (Subtarget->hasSSE2() &&
11104 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
11105 Cond.getOpcode() == ISD::SETCC) {
11106 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
11108 unsigned Opcode = 0;
11109 // Check for x CC y ? x : y.
11110 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
11111 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
11115 // Converting this to a min would handle NaNs incorrectly, and swapping
11116 // the operands would cause it to handle comparisons between positive
11117 // and negative zero incorrectly.
11118 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
11119 if (!UnsafeFPMath &&
11120 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
11122 std::swap(LHS, RHS);
11124 Opcode = X86ISD::FMIN;
11127 // Converting this to a min would handle comparisons between positive
11128 // and negative zero incorrectly.
11129 if (!UnsafeFPMath &&
11130 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
11132 Opcode = X86ISD::FMIN;
11135 // Converting this to a min would handle both negative zeros and NaNs
11136 // incorrectly, but we can swap the operands to fix both.
11137 std::swap(LHS, RHS);
11141 Opcode = X86ISD::FMIN;
11145 // Converting this to a max would handle comparisons between positive
11146 // and negative zero incorrectly.
11147 if (!UnsafeFPMath &&
11148 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(LHS))
11150 Opcode = X86ISD::FMAX;
11153 // Converting this to a max would handle NaNs incorrectly, and swapping
11154 // the operands would cause it to handle comparisons between positive
11155 // and negative zero incorrectly.
11156 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
11157 if (!UnsafeFPMath &&
11158 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
11160 std::swap(LHS, RHS);
11162 Opcode = X86ISD::FMAX;
11165 // Converting this to a max would handle both negative zeros and NaNs
11166 // incorrectly, but we can swap the operands to fix both.
11167 std::swap(LHS, RHS);
11171 Opcode = X86ISD::FMAX;
11174 // Check for x CC y ? y : x -- a min/max with reversed arms.
11175 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
11176 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
11180 // Converting this to a min would handle comparisons between positive
11181 // and negative zero incorrectly, and swapping the operands would
11182 // cause it to handle NaNs incorrectly.
11183 if (!UnsafeFPMath &&
11184 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
11185 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
11187 std::swap(LHS, RHS);
11189 Opcode = X86ISD::FMIN;
11192 // Converting this to a min would handle NaNs incorrectly.
11193 if (!UnsafeFPMath &&
11194 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
11196 Opcode = X86ISD::FMIN;
11199 // Converting this to a min would handle both negative zeros and NaNs
11200 // incorrectly, but we can swap the operands to fix both.
11201 std::swap(LHS, RHS);
11205 Opcode = X86ISD::FMIN;
11209 // Converting this to a max would handle NaNs incorrectly.
11210 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
11212 Opcode = X86ISD::FMAX;
11215 // Converting this to a max would handle comparisons between positive
11216 // and negative zero incorrectly, and swapping the operands would
11217 // cause it to handle NaNs incorrectly.
11218 if (!UnsafeFPMath &&
11219 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
11220 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
11222 std::swap(LHS, RHS);
11224 Opcode = X86ISD::FMAX;
11227 // Converting this to a max would handle both negative zeros and NaNs
11228 // incorrectly, but we can swap the operands to fix both.
11229 std::swap(LHS, RHS);
11233 Opcode = X86ISD::FMAX;
11239 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
11242 // If this is a select between two integer constants, try to do some
11244 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
11245 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
11246 // Don't do this for crazy integer types.
11247 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
11248 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
11249 // so that TrueC (the true value) is larger than FalseC.
11250 bool NeedsCondInvert = false;
11252 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
11253 // Efficiently invertible.
11254 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
11255 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
11256 isa<ConstantSDNode>(Cond.getOperand(1))))) {
11257 NeedsCondInvert = true;
11258 std::swap(TrueC, FalseC);
11261 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
11262 if (FalseC->getAPIntValue() == 0 &&
11263 TrueC->getAPIntValue().isPowerOf2()) {
11264 if (NeedsCondInvert) // Invert the condition if needed.
11265 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
11266 DAG.getConstant(1, Cond.getValueType()));
11268 // Zero extend the condition if needed.
11269 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
11271 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
11272 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
11273 DAG.getConstant(ShAmt, MVT::i8));
11276 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
11277 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
11278 if (NeedsCondInvert) // Invert the condition if needed.
11279 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
11280 DAG.getConstant(1, Cond.getValueType()));
11282 // Zero extend the condition if needed.
11283 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
11284 FalseC->getValueType(0), Cond);
11285 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
11286 SDValue(FalseC, 0));
11289 // Optimize cases that will turn into an LEA instruction. This requires
11290 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
11291 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
11292 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
11293 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
11295 bool isFastMultiplier = false;
11297 switch ((unsigned char)Diff) {
11299 case 1: // result = add base, cond
11300 case 2: // result = lea base( , cond*2)
11301 case 3: // result = lea base(cond, cond*2)
11302 case 4: // result = lea base( , cond*4)
11303 case 5: // result = lea base(cond, cond*4)
11304 case 8: // result = lea base( , cond*8)
11305 case 9: // result = lea base(cond, cond*8)
11306 isFastMultiplier = true;
11311 if (isFastMultiplier) {
11312 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
11313 if (NeedsCondInvert) // Invert the condition if needed.
11314 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
11315 DAG.getConstant(1, Cond.getValueType()));
11317 // Zero extend the condition if needed.
11318 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
11320 // Scale the condition by the difference.
11322 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
11323 DAG.getConstant(Diff, Cond.getValueType()));
11325 // Add the base if non-zero.
11326 if (FalseC->getAPIntValue() != 0)
11327 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
11328 SDValue(FalseC, 0));
11338 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
11339 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
11340 TargetLowering::DAGCombinerInfo &DCI) {
11341 DebugLoc DL = N->getDebugLoc();
11343 // If the flag operand isn't dead, don't touch this CMOV.
11344 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
11347 // If this is a select between two integer constants, try to do some
11348 // optimizations. Note that the operands are ordered the opposite of SELECT
11350 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
11351 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
11352 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
11353 // larger than FalseC (the false value).
11354 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
11356 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
11357 CC = X86::GetOppositeBranchCondition(CC);
11358 std::swap(TrueC, FalseC);
11361 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
11362 // This is efficient for any integer data type (including i8/i16) and
11364 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
11365 SDValue Cond = N->getOperand(3);
11366 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
11367 DAG.getConstant(CC, MVT::i8), Cond);
11369 // Zero extend the condition if needed.
11370 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
11372 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
11373 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
11374 DAG.getConstant(ShAmt, MVT::i8));
11375 if (N->getNumValues() == 2) // Dead flag value?
11376 return DCI.CombineTo(N, Cond, SDValue());
11380 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
11381 // for any integer data type, including i8/i16.
11382 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
11383 SDValue Cond = N->getOperand(3);
11384 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
11385 DAG.getConstant(CC, MVT::i8), Cond);
11387 // Zero extend the condition if needed.
11388 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
11389 FalseC->getValueType(0), Cond);
11390 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
11391 SDValue(FalseC, 0));
11393 if (N->getNumValues() == 2) // Dead flag value?
11394 return DCI.CombineTo(N, Cond, SDValue());
11398 // Optimize cases that will turn into an LEA instruction. This requires
11399 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
11400 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
11401 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
11402 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
11404 bool isFastMultiplier = false;
11406 switch ((unsigned char)Diff) {
11408 case 1: // result = add base, cond
11409 case 2: // result = lea base( , cond*2)
11410 case 3: // result = lea base(cond, cond*2)
11411 case 4: // result = lea base( , cond*4)
11412 case 5: // result = lea base(cond, cond*4)
11413 case 8: // result = lea base( , cond*8)
11414 case 9: // result = lea base(cond, cond*8)
11415 isFastMultiplier = true;
11420 if (isFastMultiplier) {
11421 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
11422 SDValue Cond = N->getOperand(3);
11423 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
11424 DAG.getConstant(CC, MVT::i8), Cond);
11425 // Zero extend the condition if needed.
11426 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
11428 // Scale the condition by the difference.
11430 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
11431 DAG.getConstant(Diff, Cond.getValueType()));
11433 // Add the base if non-zero.
11434 if (FalseC->getAPIntValue() != 0)
11435 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
11436 SDValue(FalseC, 0));
11437 if (N->getNumValues() == 2) // Dead flag value?
11438 return DCI.CombineTo(N, Cond, SDValue());
11448 /// PerformMulCombine - Optimize a single multiply with constant into two
11449 /// in order to implement it with two cheaper instructions, e.g.
11450 /// LEA + SHL, LEA + LEA.
11451 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
11452 TargetLowering::DAGCombinerInfo &DCI) {
11453 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
11456 EVT VT = N->getValueType(0);
11457 if (VT != MVT::i64)
11460 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
11463 uint64_t MulAmt = C->getZExtValue();
11464 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
11467 uint64_t MulAmt1 = 0;
11468 uint64_t MulAmt2 = 0;
11469 if ((MulAmt % 9) == 0) {
11471 MulAmt2 = MulAmt / 9;
11472 } else if ((MulAmt % 5) == 0) {
11474 MulAmt2 = MulAmt / 5;
11475 } else if ((MulAmt % 3) == 0) {
11477 MulAmt2 = MulAmt / 3;
11480 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
11481 DebugLoc DL = N->getDebugLoc();
11483 if (isPowerOf2_64(MulAmt2) &&
11484 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
11485 // If second multiplifer is pow2, issue it first. We want the multiply by
11486 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
11488 std::swap(MulAmt1, MulAmt2);
11491 if (isPowerOf2_64(MulAmt1))
11492 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
11493 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
11495 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
11496 DAG.getConstant(MulAmt1, VT));
11498 if (isPowerOf2_64(MulAmt2))
11499 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
11500 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
11502 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
11503 DAG.getConstant(MulAmt2, VT));
11505 // Do not add new nodes to DAG combiner worklist.
11506 DCI.CombineTo(N, NewMul, false);
11511 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
11512 SDValue N0 = N->getOperand(0);
11513 SDValue N1 = N->getOperand(1);
11514 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
11515 EVT VT = N0.getValueType();
11517 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
11518 // since the result of setcc_c is all zero's or all ones.
11519 if (N1C && N0.getOpcode() == ISD::AND &&
11520 N0.getOperand(1).getOpcode() == ISD::Constant) {
11521 SDValue N00 = N0.getOperand(0);
11522 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
11523 ((N00.getOpcode() == ISD::ANY_EXTEND ||
11524 N00.getOpcode() == ISD::ZERO_EXTEND) &&
11525 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
11526 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
11527 APInt ShAmt = N1C->getAPIntValue();
11528 Mask = Mask.shl(ShAmt);
11530 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
11531 N00, DAG.getConstant(Mask, VT));
11538 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
11540 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
11541 const X86Subtarget *Subtarget) {
11542 EVT VT = N->getValueType(0);
11543 if (!VT.isVector() && VT.isInteger() &&
11544 N->getOpcode() == ISD::SHL)
11545 return PerformSHLCombine(N, DAG);
11547 // On X86 with SSE2 support, we can transform this to a vector shift if
11548 // all elements are shifted by the same amount. We can't do this in legalize
11549 // because the a constant vector is typically transformed to a constant pool
11550 // so we have no knowledge of the shift amount.
11551 if (!Subtarget->hasSSE2())
11554 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
11557 SDValue ShAmtOp = N->getOperand(1);
11558 EVT EltVT = VT.getVectorElementType();
11559 DebugLoc DL = N->getDebugLoc();
11560 SDValue BaseShAmt = SDValue();
11561 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
11562 unsigned NumElts = VT.getVectorNumElements();
11564 for (; i != NumElts; ++i) {
11565 SDValue Arg = ShAmtOp.getOperand(i);
11566 if (Arg.getOpcode() == ISD::UNDEF) continue;
11570 for (; i != NumElts; ++i) {
11571 SDValue Arg = ShAmtOp.getOperand(i);
11572 if (Arg.getOpcode() == ISD::UNDEF) continue;
11573 if (Arg != BaseShAmt) {
11577 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
11578 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
11579 SDValue InVec = ShAmtOp.getOperand(0);
11580 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
11581 unsigned NumElts = InVec.getValueType().getVectorNumElements();
11583 for (; i != NumElts; ++i) {
11584 SDValue Arg = InVec.getOperand(i);
11585 if (Arg.getOpcode() == ISD::UNDEF) continue;
11589 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
11590 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
11591 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
11592 if (C->getZExtValue() == SplatIdx)
11593 BaseShAmt = InVec.getOperand(1);
11596 if (BaseShAmt.getNode() == 0)
11597 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
11598 DAG.getIntPtrConstant(0));
11602 // The shift amount is an i32.
11603 if (EltVT.bitsGT(MVT::i32))
11604 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
11605 else if (EltVT.bitsLT(MVT::i32))
11606 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
11608 // The shift amount is identical so we can do a vector shift.
11609 SDValue ValOp = N->getOperand(0);
11610 switch (N->getOpcode()) {
11612 llvm_unreachable("Unknown shift opcode!");
11615 if (VT == MVT::v2i64)
11616 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11617 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
11619 if (VT == MVT::v4i32)
11620 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11621 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
11623 if (VT == MVT::v8i16)
11624 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11625 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
11629 if (VT == MVT::v4i32)
11630 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11631 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
11633 if (VT == MVT::v8i16)
11634 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11635 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
11639 if (VT == MVT::v2i64)
11640 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11641 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
11643 if (VT == MVT::v4i32)
11644 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11645 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
11647 if (VT == MVT::v8i16)
11648 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11649 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
11657 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
11658 TargetLowering::DAGCombinerInfo &DCI,
11659 const X86Subtarget *Subtarget) {
11660 if (DCI.isBeforeLegalizeOps())
11663 // Want to form PANDN nodes, in the hopes of then easily combining them with
11664 // OR and AND nodes to form PBLEND/PSIGN.
11665 EVT VT = N->getValueType(0);
11666 if (VT != MVT::v2i64)
11669 SDValue N0 = N->getOperand(0);
11670 SDValue N1 = N->getOperand(1);
11671 DebugLoc DL = N->getDebugLoc();
11673 // Check LHS for vnot
11674 if (N0.getOpcode() == ISD::XOR &&
11675 ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
11676 return DAG.getNode(X86ISD::PANDN, DL, VT, N0.getOperand(0), N1);
11678 // Check RHS for vnot
11679 if (N1.getOpcode() == ISD::XOR &&
11680 ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
11681 return DAG.getNode(X86ISD::PANDN, DL, VT, N1.getOperand(0), N0);
11686 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
11687 TargetLowering::DAGCombinerInfo &DCI,
11688 const X86Subtarget *Subtarget) {
11689 if (DCI.isBeforeLegalizeOps())
11692 EVT VT = N->getValueType(0);
11693 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64 && VT != MVT::v2i64)
11696 SDValue N0 = N->getOperand(0);
11697 SDValue N1 = N->getOperand(1);
11699 // look for psign/blend
11700 if (Subtarget->hasSSSE3()) {
11701 if (VT == MVT::v2i64) {
11702 // Canonicalize pandn to RHS
11703 if (N0.getOpcode() == X86ISD::PANDN)
11705 // or (and (m, x), (pandn m, y))
11706 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::PANDN) {
11707 SDValue Mask = N1.getOperand(0);
11708 SDValue X = N1.getOperand(1);
11710 if (N0.getOperand(0) == Mask)
11711 Y = N0.getOperand(1);
11712 if (N0.getOperand(1) == Mask)
11713 Y = N0.getOperand(0);
11715 // Check to see if the mask appeared in both the AND and PANDN and
11719 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
11720 if (Mask.getOpcode() != ISD::BITCAST ||
11721 X.getOpcode() != ISD::BITCAST ||
11722 Y.getOpcode() != ISD::BITCAST)
11725 // Look through mask bitcast.
11726 Mask = Mask.getOperand(0);
11727 EVT MaskVT = Mask.getValueType();
11729 // Validate that the Mask operand is a vector sra node. The sra node
11730 // will be an intrinsic.
11731 if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN)
11734 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
11735 // there is no psrai.b
11736 switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) {
11737 case Intrinsic::x86_sse2_psrai_w:
11738 case Intrinsic::x86_sse2_psrai_d:
11740 default: return SDValue();
11743 // Check that the SRA is all signbits.
11744 SDValue SraC = Mask.getOperand(2);
11745 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
11746 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
11747 if ((SraAmt + 1) != EltBits)
11750 DebugLoc DL = N->getDebugLoc();
11752 // Now we know we at least have a plendvb with the mask val. See if
11753 // we can form a psignb/w/d.
11754 // psign = x.type == y.type == mask.type && y = sub(0, x);
11755 X = X.getOperand(0);
11756 Y = Y.getOperand(0);
11757 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
11758 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
11759 X.getValueType() == MaskVT && X.getValueType() == Y.getValueType()){
11762 case 8: Opc = X86ISD::PSIGNB; break;
11763 case 16: Opc = X86ISD::PSIGNW; break;
11764 case 32: Opc = X86ISD::PSIGND; break;
11768 SDValue Sign = DAG.getNode(Opc, DL, MaskVT, X, Mask.getOperand(1));
11769 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Sign);
11772 // PBLENDVB only available on SSE 4.1
11773 if (!Subtarget->hasSSE41())
11776 X = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, X);
11777 Y = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Y);
11778 Mask = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Mask);
11779 Mask = DAG.getNode(X86ISD::PBLENDVB, DL, MVT::v16i8, X, Y, Mask);
11780 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Mask);
11785 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
11786 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
11788 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
11790 if (!N0.hasOneUse() || !N1.hasOneUse())
11793 SDValue ShAmt0 = N0.getOperand(1);
11794 if (ShAmt0.getValueType() != MVT::i8)
11796 SDValue ShAmt1 = N1.getOperand(1);
11797 if (ShAmt1.getValueType() != MVT::i8)
11799 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
11800 ShAmt0 = ShAmt0.getOperand(0);
11801 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
11802 ShAmt1 = ShAmt1.getOperand(0);
11804 DebugLoc DL = N->getDebugLoc();
11805 unsigned Opc = X86ISD::SHLD;
11806 SDValue Op0 = N0.getOperand(0);
11807 SDValue Op1 = N1.getOperand(0);
11808 if (ShAmt0.getOpcode() == ISD::SUB) {
11809 Opc = X86ISD::SHRD;
11810 std::swap(Op0, Op1);
11811 std::swap(ShAmt0, ShAmt1);
11814 unsigned Bits = VT.getSizeInBits();
11815 if (ShAmt1.getOpcode() == ISD::SUB) {
11816 SDValue Sum = ShAmt1.getOperand(0);
11817 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
11818 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
11819 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
11820 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
11821 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
11822 return DAG.getNode(Opc, DL, VT,
11824 DAG.getNode(ISD::TRUNCATE, DL,
11827 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
11828 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
11830 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
11831 return DAG.getNode(Opc, DL, VT,
11832 N0.getOperand(0), N1.getOperand(0),
11833 DAG.getNode(ISD::TRUNCATE, DL,
11840 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
11841 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
11842 const X86Subtarget *Subtarget) {
11843 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
11844 // the FP state in cases where an emms may be missing.
11845 // A preferable solution to the general problem is to figure out the right
11846 // places to insert EMMS. This qualifies as a quick hack.
11848 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
11849 StoreSDNode *St = cast<StoreSDNode>(N);
11850 EVT VT = St->getValue().getValueType();
11851 if (VT.getSizeInBits() != 64)
11854 const Function *F = DAG.getMachineFunction().getFunction();
11855 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
11856 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
11857 && Subtarget->hasSSE2();
11858 if ((VT.isVector() ||
11859 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
11860 isa<LoadSDNode>(St->getValue()) &&
11861 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
11862 St->getChain().hasOneUse() && !St->isVolatile()) {
11863 SDNode* LdVal = St->getValue().getNode();
11864 LoadSDNode *Ld = 0;
11865 int TokenFactorIndex = -1;
11866 SmallVector<SDValue, 8> Ops;
11867 SDNode* ChainVal = St->getChain().getNode();
11868 // Must be a store of a load. We currently handle two cases: the load
11869 // is a direct child, and it's under an intervening TokenFactor. It is
11870 // possible to dig deeper under nested TokenFactors.
11871 if (ChainVal == LdVal)
11872 Ld = cast<LoadSDNode>(St->getChain());
11873 else if (St->getValue().hasOneUse() &&
11874 ChainVal->getOpcode() == ISD::TokenFactor) {
11875 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
11876 if (ChainVal->getOperand(i).getNode() == LdVal) {
11877 TokenFactorIndex = i;
11878 Ld = cast<LoadSDNode>(St->getValue());
11880 Ops.push_back(ChainVal->getOperand(i));
11884 if (!Ld || !ISD::isNormalLoad(Ld))
11887 // If this is not the MMX case, i.e. we are just turning i64 load/store
11888 // into f64 load/store, avoid the transformation if there are multiple
11889 // uses of the loaded value.
11890 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
11893 DebugLoc LdDL = Ld->getDebugLoc();
11894 DebugLoc StDL = N->getDebugLoc();
11895 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
11896 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
11898 if (Subtarget->is64Bit() || F64IsLegal) {
11899 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
11900 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
11901 Ld->getPointerInfo(), Ld->isVolatile(),
11902 Ld->isNonTemporal(), Ld->getAlignment());
11903 SDValue NewChain = NewLd.getValue(1);
11904 if (TokenFactorIndex != -1) {
11905 Ops.push_back(NewChain);
11906 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
11909 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
11910 St->getPointerInfo(),
11911 St->isVolatile(), St->isNonTemporal(),
11912 St->getAlignment());
11915 // Otherwise, lower to two pairs of 32-bit loads / stores.
11916 SDValue LoAddr = Ld->getBasePtr();
11917 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
11918 DAG.getConstant(4, MVT::i32));
11920 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
11921 Ld->getPointerInfo(),
11922 Ld->isVolatile(), Ld->isNonTemporal(),
11923 Ld->getAlignment());
11924 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
11925 Ld->getPointerInfo().getWithOffset(4),
11926 Ld->isVolatile(), Ld->isNonTemporal(),
11927 MinAlign(Ld->getAlignment(), 4));
11929 SDValue NewChain = LoLd.getValue(1);
11930 if (TokenFactorIndex != -1) {
11931 Ops.push_back(LoLd);
11932 Ops.push_back(HiLd);
11933 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
11937 LoAddr = St->getBasePtr();
11938 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
11939 DAG.getConstant(4, MVT::i32));
11941 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
11942 St->getPointerInfo(),
11943 St->isVolatile(), St->isNonTemporal(),
11944 St->getAlignment());
11945 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
11946 St->getPointerInfo().getWithOffset(4),
11948 St->isNonTemporal(),
11949 MinAlign(St->getAlignment(), 4));
11950 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
11955 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
11956 /// X86ISD::FXOR nodes.
11957 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
11958 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
11959 // F[X]OR(0.0, x) -> x
11960 // F[X]OR(x, 0.0) -> x
11961 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
11962 if (C->getValueAPF().isPosZero())
11963 return N->getOperand(1);
11964 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
11965 if (C->getValueAPF().isPosZero())
11966 return N->getOperand(0);
11970 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
11971 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
11972 // FAND(0.0, x) -> 0.0
11973 // FAND(x, 0.0) -> 0.0
11974 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
11975 if (C->getValueAPF().isPosZero())
11976 return N->getOperand(0);
11977 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
11978 if (C->getValueAPF().isPosZero())
11979 return N->getOperand(1);
11983 static SDValue PerformBTCombine(SDNode *N,
11985 TargetLowering::DAGCombinerInfo &DCI) {
11986 // BT ignores high bits in the bit index operand.
11987 SDValue Op1 = N->getOperand(1);
11988 if (Op1.hasOneUse()) {
11989 unsigned BitWidth = Op1.getValueSizeInBits();
11990 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
11991 APInt KnownZero, KnownOne;
11992 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
11993 !DCI.isBeforeLegalizeOps());
11994 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11995 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
11996 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
11997 DCI.CommitTargetLoweringOpt(TLO);
12002 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
12003 SDValue Op = N->getOperand(0);
12004 if (Op.getOpcode() == ISD::BITCAST)
12005 Op = Op.getOperand(0);
12006 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
12007 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
12008 VT.getVectorElementType().getSizeInBits() ==
12009 OpVT.getVectorElementType().getSizeInBits()) {
12010 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
12015 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
12016 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
12017 // (and (i32 x86isd::setcc_carry), 1)
12018 // This eliminates the zext. This transformation is necessary because
12019 // ISD::SETCC is always legalized to i8.
12020 DebugLoc dl = N->getDebugLoc();
12021 SDValue N0 = N->getOperand(0);
12022 EVT VT = N->getValueType(0);
12023 if (N0.getOpcode() == ISD::AND &&
12025 N0.getOperand(0).hasOneUse()) {
12026 SDValue N00 = N0.getOperand(0);
12027 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
12029 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
12030 if (!C || C->getZExtValue() != 1)
12032 return DAG.getNode(ISD::AND, dl, VT,
12033 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
12034 N00.getOperand(0), N00.getOperand(1)),
12035 DAG.getConstant(1, VT));
12041 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
12042 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
12043 unsigned X86CC = N->getConstantOperandVal(0);
12044 SDValue EFLAG = N->getOperand(1);
12045 DebugLoc DL = N->getDebugLoc();
12047 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
12048 // a zext and produces an all-ones bit which is more useful than 0/1 in some
12050 if (X86CC == X86::COND_B)
12051 return DAG.getNode(ISD::AND, DL, MVT::i8,
12052 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
12053 DAG.getConstant(X86CC, MVT::i8), EFLAG),
12054 DAG.getConstant(1, MVT::i8));
12059 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
12060 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
12061 X86TargetLowering::DAGCombinerInfo &DCI) {
12062 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
12063 // the result is either zero or one (depending on the input carry bit).
12064 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
12065 if (X86::isZeroNode(N->getOperand(0)) &&
12066 X86::isZeroNode(N->getOperand(1)) &&
12067 // We don't have a good way to replace an EFLAGS use, so only do this when
12069 SDValue(N, 1).use_empty()) {
12070 DebugLoc DL = N->getDebugLoc();
12071 EVT VT = N->getValueType(0);
12072 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
12073 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
12074 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
12075 DAG.getConstant(X86::COND_B,MVT::i8),
12077 DAG.getConstant(1, VT));
12078 return DCI.CombineTo(N, Res1, CarryOut);
12084 // fold (add Y, (sete X, 0)) -> adc 0, Y
12085 // (add Y, (setne X, 0)) -> sbb -1, Y
12086 // (sub (sete X, 0), Y) -> sbb 0, Y
12087 // (sub (setne X, 0), Y) -> adc -1, Y
12088 static SDValue OptimizeConditonalInDecrement(SDNode *N, SelectionDAG &DAG) {
12089 DebugLoc DL = N->getDebugLoc();
12091 // Look through ZExts.
12092 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
12093 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
12096 SDValue SetCC = Ext.getOperand(0);
12097 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
12100 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
12101 if (CC != X86::COND_E && CC != X86::COND_NE)
12104 SDValue Cmp = SetCC.getOperand(1);
12105 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
12106 !X86::isZeroNode(Cmp.getOperand(1)) ||
12107 !Cmp.getOperand(0).getValueType().isInteger())
12110 SDValue CmpOp0 = Cmp.getOperand(0);
12111 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
12112 DAG.getConstant(1, CmpOp0.getValueType()));
12114 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
12115 if (CC == X86::COND_NE)
12116 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
12117 DL, OtherVal.getValueType(), OtherVal,
12118 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
12119 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
12120 DL, OtherVal.getValueType(), OtherVal,
12121 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
12124 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
12125 DAGCombinerInfo &DCI) const {
12126 SelectionDAG &DAG = DCI.DAG;
12127 switch (N->getOpcode()) {
12129 case ISD::EXTRACT_VECTOR_ELT:
12130 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
12131 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
12132 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
12134 case ISD::SUB: return OptimizeConditonalInDecrement(N, DAG);
12135 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
12136 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
12139 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
12140 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
12141 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
12142 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
12144 case X86ISD::FOR: return PerformFORCombine(N, DAG);
12145 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
12146 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
12147 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
12148 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
12149 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
12150 case X86ISD::SHUFPS: // Handle all target specific shuffles
12151 case X86ISD::SHUFPD:
12152 case X86ISD::PALIGN:
12153 case X86ISD::PUNPCKHBW:
12154 case X86ISD::PUNPCKHWD:
12155 case X86ISD::PUNPCKHDQ:
12156 case X86ISD::PUNPCKHQDQ:
12157 case X86ISD::UNPCKHPS:
12158 case X86ISD::UNPCKHPD:
12159 case X86ISD::PUNPCKLBW:
12160 case X86ISD::PUNPCKLWD:
12161 case X86ISD::PUNPCKLDQ:
12162 case X86ISD::PUNPCKLQDQ:
12163 case X86ISD::UNPCKLPS:
12164 case X86ISD::UNPCKLPD:
12165 case X86ISD::VUNPCKLPS:
12166 case X86ISD::VUNPCKLPD:
12167 case X86ISD::VUNPCKLPSY:
12168 case X86ISD::VUNPCKLPDY:
12169 case X86ISD::MOVHLPS:
12170 case X86ISD::MOVLHPS:
12171 case X86ISD::PSHUFD:
12172 case X86ISD::PSHUFHW:
12173 case X86ISD::PSHUFLW:
12174 case X86ISD::MOVSS:
12175 case X86ISD::MOVSD:
12176 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI);
12182 /// isTypeDesirableForOp - Return true if the target has native support for
12183 /// the specified value type and it is 'desirable' to use the type for the
12184 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
12185 /// instruction encodings are longer and some i16 instructions are slow.
12186 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
12187 if (!isTypeLegal(VT))
12189 if (VT != MVT::i16)
12196 case ISD::SIGN_EXTEND:
12197 case ISD::ZERO_EXTEND:
12198 case ISD::ANY_EXTEND:
12211 /// IsDesirableToPromoteOp - This method query the target whether it is
12212 /// beneficial for dag combiner to promote the specified node. If true, it
12213 /// should return the desired promotion type by reference.
12214 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
12215 EVT VT = Op.getValueType();
12216 if (VT != MVT::i16)
12219 bool Promote = false;
12220 bool Commute = false;
12221 switch (Op.getOpcode()) {
12224 LoadSDNode *LD = cast<LoadSDNode>(Op);
12225 // If the non-extending load has a single use and it's not live out, then it
12226 // might be folded.
12227 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
12228 Op.hasOneUse()*/) {
12229 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12230 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
12231 // The only case where we'd want to promote LOAD (rather then it being
12232 // promoted as an operand is when it's only use is liveout.
12233 if (UI->getOpcode() != ISD::CopyToReg)
12240 case ISD::SIGN_EXTEND:
12241 case ISD::ZERO_EXTEND:
12242 case ISD::ANY_EXTEND:
12247 SDValue N0 = Op.getOperand(0);
12248 // Look out for (store (shl (load), x)).
12249 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
12262 SDValue N0 = Op.getOperand(0);
12263 SDValue N1 = Op.getOperand(1);
12264 if (!Commute && MayFoldLoad(N1))
12266 // Avoid disabling potential load folding opportunities.
12267 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
12269 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
12279 //===----------------------------------------------------------------------===//
12280 // X86 Inline Assembly Support
12281 //===----------------------------------------------------------------------===//
12283 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
12284 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
12286 std::string AsmStr = IA->getAsmString();
12288 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
12289 SmallVector<StringRef, 4> AsmPieces;
12290 SplitString(AsmStr, AsmPieces, ";\n");
12292 switch (AsmPieces.size()) {
12293 default: return false;
12295 AsmStr = AsmPieces[0];
12297 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
12299 // FIXME: this should verify that we are targeting a 486 or better. If not,
12300 // we will turn this bswap into something that will be lowered to logical ops
12301 // instead of emitting the bswap asm. For now, we don't support 486 or lower
12302 // so don't worry about this.
12304 if (AsmPieces.size() == 2 &&
12305 (AsmPieces[0] == "bswap" ||
12306 AsmPieces[0] == "bswapq" ||
12307 AsmPieces[0] == "bswapl") &&
12308 (AsmPieces[1] == "$0" ||
12309 AsmPieces[1] == "${0:q}")) {
12310 // No need to check constraints, nothing other than the equivalent of
12311 // "=r,0" would be valid here.
12312 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
12313 if (!Ty || Ty->getBitWidth() % 16 != 0)
12315 return IntrinsicLowering::LowerToByteSwap(CI);
12317 // rorw $$8, ${0:w} --> llvm.bswap.i16
12318 if (CI->getType()->isIntegerTy(16) &&
12319 AsmPieces.size() == 3 &&
12320 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") &&
12321 AsmPieces[1] == "$$8," &&
12322 AsmPieces[2] == "${0:w}" &&
12323 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
12325 const std::string &ConstraintsStr = IA->getConstraintString();
12326 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
12327 std::sort(AsmPieces.begin(), AsmPieces.end());
12328 if (AsmPieces.size() == 4 &&
12329 AsmPieces[0] == "~{cc}" &&
12330 AsmPieces[1] == "~{dirflag}" &&
12331 AsmPieces[2] == "~{flags}" &&
12332 AsmPieces[3] == "~{fpsr}") {
12333 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
12334 if (!Ty || Ty->getBitWidth() % 16 != 0)
12336 return IntrinsicLowering::LowerToByteSwap(CI);
12341 if (CI->getType()->isIntegerTy(32) &&
12342 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
12343 SmallVector<StringRef, 4> Words;
12344 SplitString(AsmPieces[0], Words, " \t,");
12345 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
12346 Words[2] == "${0:w}") {
12348 SplitString(AsmPieces[1], Words, " \t,");
12349 if (Words.size() == 3 && Words[0] == "rorl" && Words[1] == "$$16" &&
12350 Words[2] == "$0") {
12352 SplitString(AsmPieces[2], Words, " \t,");
12353 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
12354 Words[2] == "${0:w}") {
12356 const std::string &ConstraintsStr = IA->getConstraintString();
12357 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
12358 std::sort(AsmPieces.begin(), AsmPieces.end());
12359 if (AsmPieces.size() == 4 &&
12360 AsmPieces[0] == "~{cc}" &&
12361 AsmPieces[1] == "~{dirflag}" &&
12362 AsmPieces[2] == "~{flags}" &&
12363 AsmPieces[3] == "~{fpsr}") {
12364 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
12365 if (!Ty || Ty->getBitWidth() % 16 != 0)
12367 return IntrinsicLowering::LowerToByteSwap(CI);
12374 if (CI->getType()->isIntegerTy(64)) {
12375 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
12376 if (Constraints.size() >= 2 &&
12377 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
12378 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
12379 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
12380 SmallVector<StringRef, 4> Words;
12381 SplitString(AsmPieces[0], Words, " \t");
12382 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
12384 SplitString(AsmPieces[1], Words, " \t");
12385 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
12387 SplitString(AsmPieces[2], Words, " \t,");
12388 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
12389 Words[2] == "%edx") {
12390 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
12391 if (!Ty || Ty->getBitWidth() % 16 != 0)
12393 return IntrinsicLowering::LowerToByteSwap(CI);
12406 /// getConstraintType - Given a constraint letter, return the type of
12407 /// constraint it is for this target.
12408 X86TargetLowering::ConstraintType
12409 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
12410 if (Constraint.size() == 1) {
12411 switch (Constraint[0]) {
12421 return C_RegisterClass;
12445 return TargetLowering::getConstraintType(Constraint);
12448 /// Examine constraint type and operand type and determine a weight value.
12449 /// This object must already have been set up with the operand type
12450 /// and the current alternative constraint selected.
12451 TargetLowering::ConstraintWeight
12452 X86TargetLowering::getSingleConstraintMatchWeight(
12453 AsmOperandInfo &info, const char *constraint) const {
12454 ConstraintWeight weight = CW_Invalid;
12455 Value *CallOperandVal = info.CallOperandVal;
12456 // If we don't have a value, we can't do a match,
12457 // but allow it at the lowest weight.
12458 if (CallOperandVal == NULL)
12460 const Type *type = CallOperandVal->getType();
12461 // Look at the constraint type.
12462 switch (*constraint) {
12464 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
12475 if (CallOperandVal->getType()->isIntegerTy())
12476 weight = CW_SpecificReg;
12481 if (type->isFloatingPointTy())
12482 weight = CW_SpecificReg;
12485 if (type->isX86_MMXTy() && Subtarget->hasMMX())
12486 weight = CW_SpecificReg;
12490 if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM())
12491 weight = CW_Register;
12494 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
12495 if (C->getZExtValue() <= 31)
12496 weight = CW_Constant;
12500 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
12501 if (C->getZExtValue() <= 63)
12502 weight = CW_Constant;
12506 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
12507 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
12508 weight = CW_Constant;
12512 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
12513 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
12514 weight = CW_Constant;
12518 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
12519 if (C->getZExtValue() <= 3)
12520 weight = CW_Constant;
12524 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
12525 if (C->getZExtValue() <= 0xff)
12526 weight = CW_Constant;
12531 if (dyn_cast<ConstantFP>(CallOperandVal)) {
12532 weight = CW_Constant;
12536 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
12537 if ((C->getSExtValue() >= -0x80000000LL) &&
12538 (C->getSExtValue() <= 0x7fffffffLL))
12539 weight = CW_Constant;
12543 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
12544 if (C->getZExtValue() <= 0xffffffff)
12545 weight = CW_Constant;
12552 /// LowerXConstraint - try to replace an X constraint, which matches anything,
12553 /// with another that has more specific requirements based on the type of the
12554 /// corresponding operand.
12555 const char *X86TargetLowering::
12556 LowerXConstraint(EVT ConstraintVT) const {
12557 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
12558 // 'f' like normal targets.
12559 if (ConstraintVT.isFloatingPoint()) {
12560 if (Subtarget->hasXMMInt())
12562 if (Subtarget->hasXMM())
12566 return TargetLowering::LowerXConstraint(ConstraintVT);
12569 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
12570 /// vector. If it is invalid, don't add anything to Ops.
12571 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
12573 std::vector<SDValue>&Ops,
12574 SelectionDAG &DAG) const {
12575 SDValue Result(0, 0);
12577 switch (Constraint) {
12580 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
12581 if (C->getZExtValue() <= 31) {
12582 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
12588 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
12589 if (C->getZExtValue() <= 63) {
12590 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
12596 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
12597 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
12598 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
12604 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
12605 if (C->getZExtValue() <= 255) {
12606 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
12612 // 32-bit signed value
12613 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
12614 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
12615 C->getSExtValue())) {
12616 // Widen to 64 bits here to get it sign extended.
12617 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
12620 // FIXME gcc accepts some relocatable values here too, but only in certain
12621 // memory models; it's complicated.
12626 // 32-bit unsigned value
12627 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
12628 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
12629 C->getZExtValue())) {
12630 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
12634 // FIXME gcc accepts some relocatable values here too, but only in certain
12635 // memory models; it's complicated.
12639 // Literal immediates are always ok.
12640 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
12641 // Widen to 64 bits here to get it sign extended.
12642 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
12646 // In any sort of PIC mode addresses need to be computed at runtime by
12647 // adding in a register or some sort of table lookup. These can't
12648 // be used as immediates.
12649 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
12652 // If we are in non-pic codegen mode, we allow the address of a global (with
12653 // an optional displacement) to be used with 'i'.
12654 GlobalAddressSDNode *GA = 0;
12655 int64_t Offset = 0;
12657 // Match either (GA), (GA+C), (GA+C1+C2), etc.
12659 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
12660 Offset += GA->getOffset();
12662 } else if (Op.getOpcode() == ISD::ADD) {
12663 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
12664 Offset += C->getZExtValue();
12665 Op = Op.getOperand(0);
12668 } else if (Op.getOpcode() == ISD::SUB) {
12669 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
12670 Offset += -C->getZExtValue();
12671 Op = Op.getOperand(0);
12676 // Otherwise, this isn't something we can handle, reject it.
12680 const GlobalValue *GV = GA->getGlobal();
12681 // If we require an extra load to get this address, as in PIC mode, we
12682 // can't accept it.
12683 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
12684 getTargetMachine())))
12687 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
12688 GA->getValueType(0), Offset);
12693 if (Result.getNode()) {
12694 Ops.push_back(Result);
12697 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
12700 std::vector<unsigned> X86TargetLowering::
12701 getRegClassForInlineAsmConstraint(const std::string &Constraint,
12703 if (Constraint.size() == 1) {
12704 // FIXME: not handling fp-stack yet!
12705 switch (Constraint[0]) { // GCC X86 Constraint Letters
12706 default: break; // Unknown constraint letter
12707 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
12708 if (Subtarget->is64Bit()) {
12709 if (VT == MVT::i32)
12710 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
12711 X86::ESI, X86::EDI, X86::R8D, X86::R9D,
12712 X86::R10D,X86::R11D,X86::R12D,
12713 X86::R13D,X86::R14D,X86::R15D,
12714 X86::EBP, X86::ESP, 0);
12715 else if (VT == MVT::i16)
12716 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
12717 X86::SI, X86::DI, X86::R8W,X86::R9W,
12718 X86::R10W,X86::R11W,X86::R12W,
12719 X86::R13W,X86::R14W,X86::R15W,
12720 X86::BP, X86::SP, 0);
12721 else if (VT == MVT::i8)
12722 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
12723 X86::SIL, X86::DIL, X86::R8B,X86::R9B,
12724 X86::R10B,X86::R11B,X86::R12B,
12725 X86::R13B,X86::R14B,X86::R15B,
12726 X86::BPL, X86::SPL, 0);
12728 else if (VT == MVT::i64)
12729 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
12730 X86::RSI, X86::RDI, X86::R8, X86::R9,
12731 X86::R10, X86::R11, X86::R12,
12732 X86::R13, X86::R14, X86::R15,
12733 X86::RBP, X86::RSP, 0);
12737 // 32-bit fallthrough
12738 case 'Q': // Q_REGS
12739 if (VT == MVT::i32)
12740 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
12741 else if (VT == MVT::i16)
12742 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
12743 else if (VT == MVT::i8)
12744 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
12745 else if (VT == MVT::i64)
12746 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
12751 return std::vector<unsigned>();
12754 std::pair<unsigned, const TargetRegisterClass*>
12755 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
12757 // First, see if this is a constraint that directly corresponds to an LLVM
12759 if (Constraint.size() == 1) {
12760 // GCC Constraint Letters
12761 switch (Constraint[0]) {
12763 case 'r': // GENERAL_REGS
12764 case 'l': // INDEX_REGS
12766 return std::make_pair(0U, X86::GR8RegisterClass);
12767 if (VT == MVT::i16)
12768 return std::make_pair(0U, X86::GR16RegisterClass);
12769 if (VT == MVT::i32 || !Subtarget->is64Bit())
12770 return std::make_pair(0U, X86::GR32RegisterClass);
12771 return std::make_pair(0U, X86::GR64RegisterClass);
12772 case 'R': // LEGACY_REGS
12774 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
12775 if (VT == MVT::i16)
12776 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
12777 if (VT == MVT::i32 || !Subtarget->is64Bit())
12778 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
12779 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
12780 case 'f': // FP Stack registers.
12781 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
12782 // value to the correct fpstack register class.
12783 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
12784 return std::make_pair(0U, X86::RFP32RegisterClass);
12785 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
12786 return std::make_pair(0U, X86::RFP64RegisterClass);
12787 return std::make_pair(0U, X86::RFP80RegisterClass);
12788 case 'y': // MMX_REGS if MMX allowed.
12789 if (!Subtarget->hasMMX()) break;
12790 return std::make_pair(0U, X86::VR64RegisterClass);
12791 case 'Y': // SSE_REGS if SSE2 allowed
12792 if (!Subtarget->hasXMMInt()) break;
12794 case 'x': // SSE_REGS if SSE1 allowed
12795 if (!Subtarget->hasXMM()) break;
12797 switch (VT.getSimpleVT().SimpleTy) {
12799 // Scalar SSE types.
12802 return std::make_pair(0U, X86::FR32RegisterClass);
12805 return std::make_pair(0U, X86::FR64RegisterClass);
12813 return std::make_pair(0U, X86::VR128RegisterClass);
12819 // Use the default implementation in TargetLowering to convert the register
12820 // constraint into a member of a register class.
12821 std::pair<unsigned, const TargetRegisterClass*> Res;
12822 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
12824 // Not found as a standard register?
12825 if (Res.second == 0) {
12826 // Map st(0) -> st(7) -> ST0
12827 if (Constraint.size() == 7 && Constraint[0] == '{' &&
12828 tolower(Constraint[1]) == 's' &&
12829 tolower(Constraint[2]) == 't' &&
12830 Constraint[3] == '(' &&
12831 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
12832 Constraint[5] == ')' &&
12833 Constraint[6] == '}') {
12835 Res.first = X86::ST0+Constraint[4]-'0';
12836 Res.second = X86::RFP80RegisterClass;
12840 // GCC allows "st(0)" to be called just plain "st".
12841 if (StringRef("{st}").equals_lower(Constraint)) {
12842 Res.first = X86::ST0;
12843 Res.second = X86::RFP80RegisterClass;
12848 if (StringRef("{flags}").equals_lower(Constraint)) {
12849 Res.first = X86::EFLAGS;
12850 Res.second = X86::CCRRegisterClass;
12854 // 'A' means EAX + EDX.
12855 if (Constraint == "A") {
12856 Res.first = X86::EAX;
12857 Res.second = X86::GR32_ADRegisterClass;
12863 // Otherwise, check to see if this is a register class of the wrong value
12864 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
12865 // turn into {ax},{dx}.
12866 if (Res.second->hasType(VT))
12867 return Res; // Correct type already, nothing to do.
12869 // All of the single-register GCC register classes map their values onto
12870 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
12871 // really want an 8-bit or 32-bit register, map to the appropriate register
12872 // class and return the appropriate register.
12873 if (Res.second == X86::GR16RegisterClass) {
12874 if (VT == MVT::i8) {
12875 unsigned DestReg = 0;
12876 switch (Res.first) {
12878 case X86::AX: DestReg = X86::AL; break;
12879 case X86::DX: DestReg = X86::DL; break;
12880 case X86::CX: DestReg = X86::CL; break;
12881 case X86::BX: DestReg = X86::BL; break;
12884 Res.first = DestReg;
12885 Res.second = X86::GR8RegisterClass;
12887 } else if (VT == MVT::i32) {
12888 unsigned DestReg = 0;
12889 switch (Res.first) {
12891 case X86::AX: DestReg = X86::EAX; break;
12892 case X86::DX: DestReg = X86::EDX; break;
12893 case X86::CX: DestReg = X86::ECX; break;
12894 case X86::BX: DestReg = X86::EBX; break;
12895 case X86::SI: DestReg = X86::ESI; break;
12896 case X86::DI: DestReg = X86::EDI; break;
12897 case X86::BP: DestReg = X86::EBP; break;
12898 case X86::SP: DestReg = X86::ESP; break;
12901 Res.first = DestReg;
12902 Res.second = X86::GR32RegisterClass;
12904 } else if (VT == MVT::i64) {
12905 unsigned DestReg = 0;
12906 switch (Res.first) {
12908 case X86::AX: DestReg = X86::RAX; break;
12909 case X86::DX: DestReg = X86::RDX; break;
12910 case X86::CX: DestReg = X86::RCX; break;
12911 case X86::BX: DestReg = X86::RBX; break;
12912 case X86::SI: DestReg = X86::RSI; break;
12913 case X86::DI: DestReg = X86::RDI; break;
12914 case X86::BP: DestReg = X86::RBP; break;
12915 case X86::SP: DestReg = X86::RSP; break;
12918 Res.first = DestReg;
12919 Res.second = X86::GR64RegisterClass;
12922 } else if (Res.second == X86::FR32RegisterClass ||
12923 Res.second == X86::FR64RegisterClass ||
12924 Res.second == X86::VR128RegisterClass) {
12925 // Handle references to XMM physical registers that got mapped into the
12926 // wrong class. This can happen with constraints like {xmm0} where the
12927 // target independent register mapper will just pick the first match it can
12928 // find, ignoring the required type.
12929 if (VT == MVT::f32)
12930 Res.second = X86::FR32RegisterClass;
12931 else if (VT == MVT::f64)
12932 Res.second = X86::FR64RegisterClass;
12933 else if (X86::VR128RegisterClass->hasType(VT))
12934 Res.second = X86::VR128RegisterClass;